diff --git a/autogen_stubs.sh b/autogen_stubs.sh index 3a1c809a92..8c68d5bb3b 100755 --- a/autogen_stubs.sh +++ b/autogen_stubs.sh @@ -247,6 +247,83 @@ generate_qcom() { python3 -c "import tinygrad.runtime.autogen.qcom_dsp" } +generate_pciaccess() { + clang2py -k cdefstum \ + /usr/include/pciaccess.h \ + /usr/include/linux/pci_regs.h \ + -l /usr/lib/x86_64-linux-gnu/libpciaccess.so \ + -o $BASE/libpciaccess.py + sed -i "s\import ctypes\import ctypes, os\g" $BASE/libpciaccess.py + fixup $BASE/libpciaccess.py + sed -i "s/ctypes\.CDLL('\([^']*\)')/ctypes.CDLL('\1') if os.path.exists('\1') else None/g" $BASE/libpciaccess.py +} + +generate_vfio() { + clang2py -k cdefstum \ + /usr/include/linux/vfio.h \ + -o $BASE/vfio.py + fixup $BASE/vfio.py +} + +generate_am() { + clang2py -k cdefstum \ + extra/amdpci/headers/v11_structs.h \ + extra/amdpci/headers/amdgpu_vm.h \ + extra/amdpci/headers/discovery.h \ + extra/amdpci/headers/amdgpu_ucode.h \ + extra/amdpci/headers/soc21_enum.h \ + extra/amdpci/headers/psp_gfx_if.h \ + extra/amdpci/headers/amdgpu_psp.h \ + extra/amdpci/headers/amdgpu_irq.h \ + extra/amdpci/headers/amdgpu_doorbell.h \ + extra/amdpci/headers/soc15_ih_clientid.h \ + -o $BASE/am/am.py + fixup $BASE/am/am.py + + clang2py -k cdefstum \ + extra/amdpci/headers/mp_13_0_0_offset.h \ + extra/amdpci/headers/mp_13_0_0_sh_mask.h \ + -o $BASE/am/mp_13_0_0.py + fixup $BASE/am/mp_13_0_0.py + + clang2py -k cdefstum \ + extra/amdpci/headers/mp_11_0_offset.h \ + extra/amdpci/headers/mp_11_0_sh_mask.h \ + -o $BASE/am/mp_11_0.py + fixup $BASE/am/mp_11_0.py + + clang2py -k cdefstum \ + extra/amdpci/headers/gc_11_0_0_offset.h \ + extra/amdpci/headers/gc_11_0_0_sh_mask.h \ + -o $BASE/am/gc_11_0_0.py + fixup $BASE/am/gc_11_0_0.py + + clang2py -k cdefstum \ + extra/amdpci/headers/mmhub_3_0_0_offset.h \ + extra/amdpci/headers/mmhub_3_0_0_sh_mask.h \ + -o $BASE/am/mmhub_3_0_0.py + fixup $BASE/am/mmhub_3_0_0.py + + clang2py -k cdefstum \ + extra/amdpci/headers/nbio_4_3_0_offset.h \ + extra/amdpci/headers/nbio_4_3_0_sh_mask.h \ + -o $BASE/am/nbio_4_3_0.py + fixup $BASE/am/nbio_4_3_0.py + + clang2py -k cdefstum \ + extra/amdpci/headers/osssys_6_0_0_offset.h \ + extra/amdpci/headers/osssys_6_0_0_sh_mask.h \ + -o $BASE/am/osssys_6_0_0.py + fixup $BASE/am/osssys_6_0_0.py + + clang2py -k cdefstum \ + extra/amdpci/headers/smu_v13_0_0_ppsmc.h \ + extra/amdpci/headers/smu13_driver_if_v13_0_0.h \ + extra/amdpci/headers/amdgpu_smu.h \ + -o $BASE/am/smu_v13_0_0.py + fixup $BASE/am/smu_v13_0_0.py +} + if [ "$1" == "opencl" ]; then generate_opencl elif [ "$1" == "hip" ]; then generate_hip elif [ "$1" == "comgr" ]; then generate_comgr @@ -256,11 +333,14 @@ elif [ "$1" == "hsa" ]; then generate_hsa elif [ "$1" == "kfd" ]; then generate_kfd elif [ "$1" == "nv" ]; then generate_nv elif [ "$1" == "amd" ]; then generate_amd +elif [ "$1" == "am" ]; then generate_am elif [ "$1" == "qcom" ]; then generate_qcom elif [ "$1" == "io_uring" ]; then generate_io_uring elif [ "$1" == "libc" ]; then generate_libc elif [ "$1" == "kgsl" ]; then generate_kgsl elif [ "$1" == "adreno" ]; then generate_adreno -elif [ "$1" == "all" ]; then generate_opencl; generate_hip; generate_comgr; generate_cuda; generate_nvrtc; generate_hsa; generate_kfd; generate_nv; generate_amd; generate_io_uring; generate_libc +elif [ "$1" == "pci" ]; then generate_pciaccess +elif [ "$1" == "vfio" ]; then generate_vfio +elif [ "$1" == "all" ]; then generate_opencl; generate_hip; generate_comgr; generate_cuda; generate_nvrtc; generate_hsa; generate_kfd; generate_nv; generate_amd; generate_io_uring; generate_libc; generate_am else echo "usage: $0 " fi diff --git a/extra/amdpci/headers/amdgpu_doorbell.h b/extra/amdpci/headers/amdgpu_doorbell.h new file mode 100644 index 0000000000..47e27d20fb --- /dev/null +++ b/extra/amdpci/headers/amdgpu_doorbell.h @@ -0,0 +1,279 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef AMDGPU_DOORBELL_H +#define AMDGPU_DOORBELL_H + +enum AMDGPU_DOORBELL_ASSIGNMENT { + AMDGPU_DOORBELL_KIQ = 0x000, + AMDGPU_DOORBELL_HIQ = 0x001, + AMDGPU_DOORBELL_DIQ = 0x002, + AMDGPU_DOORBELL_MEC_RING0 = 0x010, + AMDGPU_DOORBELL_MEC_RING1 = 0x011, + AMDGPU_DOORBELL_MEC_RING2 = 0x012, + AMDGPU_DOORBELL_MEC_RING3 = 0x013, + AMDGPU_DOORBELL_MEC_RING4 = 0x014, + AMDGPU_DOORBELL_MEC_RING5 = 0x015, + AMDGPU_DOORBELL_MEC_RING6 = 0x016, + AMDGPU_DOORBELL_MEC_RING7 = 0x017, + AMDGPU_DOORBELL_GFX_RING0 = 0x020, + AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, + AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, + AMDGPU_DOORBELL_IH = 0x1E8, + AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, + AMDGPU_DOORBELL_INVALID = 0xFFFF +}; + +enum AMDGPU_VEGA20_DOORBELL_ASSIGNMENT { + + /* Compute + GFX: 0~255 */ + AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, + AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, + AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, + AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, + AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, + AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, + AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, + AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, + AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, + AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, + AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, + AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, + AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, + AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, + /* SDMA:256~335*/ + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, + /* IH: 376~391 */ + AMDGPU_VEGA20_DOORBELL_IH = 0x178, + /* MMSCH: 392~407 + * overlap the doorbell assignment with VCN as they are mutually exclusive + * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD + */ + AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ + AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, + AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, + AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, + + AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ + AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, + AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, + AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, + + AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, + AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, + AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, + AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, + + AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, + AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, + AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, + AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, + + AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, + AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, + + /* kiq/kcq from second XCD. Max 8 XCDs */ + AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 0x190, + /* 8 compute rings per GC. Max to 0x1CE */ + AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 0x197, + + /* AID1 SDMA: 0x1D0 ~ 0x1F7 */ + AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 0x1D0, + + AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1F7, + AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF +}; + +enum AMDGPU_NAVI10_DOORBELL_ASSIGNMENT { + + /* Compute + GFX: 0~255 */ + AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, + AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, + AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, + AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, + AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, + AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, + AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, + AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, + AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, + AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, + AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, + AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B, + AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C, + AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D, + AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, + AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, + AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, + AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D, + AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF, + + /* SDMA:256~335*/ + AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, + AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, + AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114, + AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E, + /* IH: 376~391 */ + AMDGPU_NAVI10_DOORBELL_IH = 0x178, + /* MMSCH: 392~407 + * overlap the doorbell assignment with VCN as they are mutually exclusive + * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD + */ + AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ + AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, + AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, + AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, + + AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C, + AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D, + AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E, + AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F, + + AMDGPU_NAVI10_DOORBELL64_VPE = 0x190, + + AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, + AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VPE, + + AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = AMDGPU_NAVI10_DOORBELL64_VPE, + AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF +}; + +/* + * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space + */ +enum AMDGPU_DOORBELL64_ASSIGNMENT { + /* + * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in + * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. + * Compute related doorbells are allocated from 0x00 to 0x8a + */ + + + /* kernel scheduling */ + AMDGPU_DOORBELL64_KIQ = 0x00, + + /* HSA interface queue and debug queue */ + AMDGPU_DOORBELL64_HIQ = 0x01, + AMDGPU_DOORBELL64_DIQ = 0x02, + + /* Compute engines */ + AMDGPU_DOORBELL64_MEC_RING0 = 0x03, + AMDGPU_DOORBELL64_MEC_RING1 = 0x04, + AMDGPU_DOORBELL64_MEC_RING2 = 0x05, + AMDGPU_DOORBELL64_MEC_RING3 = 0x06, + AMDGPU_DOORBELL64_MEC_RING4 = 0x07, + AMDGPU_DOORBELL64_MEC_RING5 = 0x08, + AMDGPU_DOORBELL64_MEC_RING6 = 0x09, + AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, + + /* User queue doorbell range (128 doorbells) */ + AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, + AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, + + /* Graphics engine */ + AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, + + /* + * Other graphics doorbells can be allocated here: from 0x8c to 0xdf + * Graphics voltage island aperture 1 + * default non-graphics QWORD index is 0xe0 - 0xFF inclusive + */ + + /* For vega10 sriov, the sdma doorbell must be fixed as follow + * to keep the same setting with host driver, or it will + * happen conflicts + */ + AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, + AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, + AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, + AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, + + /* Interrupt handler */ + AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ + AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ + AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ + + /* VCN engine use 32 bits doorbell */ + AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ + AMDGPU_DOORBELL64_VCN2_3 = 0xF9, + AMDGPU_DOORBELL64_VCN4_5 = 0xFA, + AMDGPU_DOORBELL64_VCN6_7 = 0xFB, + + /* overlap the doorbell assignment with VCN as they are mutually exclusive + * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD + */ + AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, + AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, + AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, + AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, + + AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, + AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, + AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, + AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, + + AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, + AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, + + AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, + AMDGPU_DOORBELL64_INVALID = 0xFFFF +}; + +enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 { + + /* XCC0: 0x00 ~20, XCC1: 20 ~ 2F ... */ + + /* KIQ/HIQ/DIQ */ + AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0x000, + AMDGPU_DOORBELL_LAYOUT1_HIQ = 0x001, + AMDGPU_DOORBELL_LAYOUT1_DIQ = 0x002, + /* Compute: 0x08 ~ 0x20 */ + AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 0x008, + AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 0x00F, + AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 0x010, + AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 0x01F, + AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 0x020, + + /* SDMA: 0x100 ~ 0x19F */ + AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 0x100, + AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F, + /* IH: 0x1A0 ~ 0x1AF */ + AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0, + /* VCN: 0x1B0 ~ 0x1E8 */ + AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0, + AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1E8, + + AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START, + AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_VCN_END, + + AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1E8, + AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF +}; + +#endif diff --git a/extra/amdpci/headers/amdgpu_irq.h b/extra/amdpci/headers/amdgpu_irq.h new file mode 100644 index 0000000000..f0c961e23a --- /dev/null +++ b/extra/amdpci/headers/amdgpu_irq.h @@ -0,0 +1,87 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_IRQ_H__ +#define __AMDGPU_IRQ_H__ + +// #include +// #include "soc15_ih_clientid.h" +// #include "amdgpu_ih.h" + +#define int32_t int +#define uint32_t unsigned int +#define int8_t signed char +#define uint8_t unsigned char +#define uint16_t unsigned short +#define int16_t short +#define uint64_t unsigned long long +#define bool _Bool +#define u32 unsigned int + +#define AMDGPU_MAX_IRQ_SRC_ID 0x100 +#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100 + +#define AMDGPU_IRQ_CLIENTID_LEGACY 0 +#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX + +#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4 + +struct amdgpu_device; + +enum amdgpu_interrupt_state { + AMDGPU_IRQ_STATE_DISABLE, + AMDGPU_IRQ_STATE_ENABLE, +}; + +struct amdgpu_iv_entry { + // struct amdgpu_ih_ring *ih; + unsigned client_id; + unsigned src_id; + unsigned ring_id; + unsigned vmid; + unsigned vmid_src; + uint64_t timestamp; + unsigned timestamp_src; + unsigned pasid; + unsigned node_id; + unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW]; + const uint32_t *iv_entry; +}; + +enum interrupt_node_id_per_aid { + AID0_NODEID = 0, + XCD0_NODEID = 1, + XCD1_NODEID = 2, + AID1_NODEID = 4, + XCD2_NODEID = 5, + XCD3_NODEID = 6, + AID2_NODEID = 8, + XCD4_NODEID = 9, + XCD5_NODEID = 10, + AID3_NODEID = 12, + XCD6_NODEID = 13, + XCD7_NODEID = 14, + NODEID_MAX, +}; + +#endif diff --git a/extra/amdpci/headers/amdgpu_psp.h b/extra/amdpci/headers/amdgpu_psp.h new file mode 100644 index 0000000000..ae3d762c67 --- /dev/null +++ b/extra/amdpci/headers/amdgpu_psp.h @@ -0,0 +1,559 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Huang Rui + * + */ +#ifndef __AMDGPU_PSP_H__ +#define __AMDGPU_PSP_H__ + +// #include "amdgpu.h" +// #include "psp_gfx_if.h" +// #include "ta_xgmi_if.h" +// #include "ta_ras_if.h" +// #include "ta_rap_if.h" +// #include "ta_secureDisplay_if.h" + +#define PSP_FENCE_BUFFER_SIZE 0x1000 +#define PSP_CMD_BUFFER_SIZE 0x1000 +#define PSP_1_MEG 0x100000 +#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) +#define PSP_TMR_ALIGNMENT 0x100000 +#define PSP_FW_NAME_LEN 0x24 + +// extern const struct attribute_group amdgpu_flash_attr_group; + +enum psp_shared_mem_size { + PSP_ASD_SHARED_MEM_SIZE = 0x0, + PSP_XGMI_SHARED_MEM_SIZE = 0x4000, + PSP_RAS_SHARED_MEM_SIZE = 0x4000, + PSP_HDCP_SHARED_MEM_SIZE = 0x4000, + PSP_DTM_SHARED_MEM_SIZE = 0x4000, + PSP_RAP_SHARED_MEM_SIZE = 0x4000, + PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, +}; + +enum ta_type_id { + TA_TYPE_XGMI = 1, + TA_TYPE_RAS, + TA_TYPE_HDCP, + TA_TYPE_DTM, + TA_TYPE_RAP, + TA_TYPE_SECUREDISPLAY, + + TA_TYPE_MAX_INDEX, +}; + +struct psp_context; +struct psp_xgmi_node_info; +struct psp_xgmi_topology_info; +struct psp_bin_desc; + +enum psp_bootloader_cmd { + PSP_BL__LOAD_SYSDRV = 0x10000, + PSP_BL__LOAD_SOSDRV = 0x20000, + PSP_BL__LOAD_KEY_DATABASE = 0x80000, + PSP_BL__LOAD_SOCDRV = 0xB0000, + PSP_BL__LOAD_DBGDRV = 0xC0000, + PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, + PSP_BL__LOAD_INTFDRV = 0xD0000, + PSP_BL__LOAD_RASDRV = 0xE0000, + PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, + PSP_BL__DRAM_LONG_TRAIN = 0x100000, + PSP_BL__DRAM_SHORT_TRAIN = 0x200000, + PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, +}; + +enum psp_ring_type { + PSP_RING_TYPE__INVALID = 0, + /* + * These values map to the way the PSP kernel identifies the + * rings. + */ + PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ + PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ +}; + +// struct psp_ring { +// enum psp_ring_type ring_type; +// struct psp_gfx_rb_frame *ring_mem; +// uint64_t ring_mem_mc_addr; +// void *ring_mem_handle; +// uint32_t ring_size; +// uint32_t ring_wptr; +// }; + +/* More registers may will be supported */ +enum psp_reg_prog_id { + PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ + PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ + PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ + PSP_REG_LAST +}; + +// struct psp_funcs { +// int (*init_microcode)(struct psp_context *psp); +// int (*wait_for_bootloader)(struct psp_context *psp); +// int (*bootloader_load_kdb)(struct psp_context *psp); +// int (*bootloader_load_spl)(struct psp_context *psp); +// int (*bootloader_load_sysdrv)(struct psp_context *psp); +// int (*bootloader_load_soc_drv)(struct psp_context *psp); +// int (*bootloader_load_intf_drv)(struct psp_context *psp); +// int (*bootloader_load_dbg_drv)(struct psp_context *psp); +// int (*bootloader_load_ras_drv)(struct psp_context *psp); +// int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); +// int (*bootloader_load_sos)(struct psp_context *psp); +// int (*ring_create)(struct psp_context *psp, +// enum psp_ring_type ring_type); +// int (*ring_stop)(struct psp_context *psp, +// enum psp_ring_type ring_type); +// int (*ring_destroy)(struct psp_context *psp, +// enum psp_ring_type ring_type); +// bool (*smu_reload_quirk)(struct psp_context *psp); +// int (*mode1_reset)(struct psp_context *psp); +// int (*mem_training)(struct psp_context *psp, uint32_t ops); +// uint32_t (*ring_get_wptr)(struct psp_context *psp); +// void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); +// int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); +// int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); +// int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); +// int (*vbflash_stat)(struct psp_context *psp); +// int (*fatal_error_recovery_quirk)(struct psp_context *psp); +// bool (*get_ras_capability)(struct psp_context *psp); +// bool (*is_aux_sos_load_required)(struct psp_context *psp); +// }; + +// struct ta_funcs { +// int (*fn_ta_initialize)(struct psp_context *psp); +// int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); +// int (*fn_ta_terminate)(struct psp_context *psp); +// }; + +#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 +// struct psp_xgmi_node_info { +// uint64_t node_id; +// uint8_t num_hops; +// uint8_t is_sharing_enabled; +// enum ta_xgmi_assigned_sdma_engine sdma_engine; +// uint8_t num_links; +// struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; +// }; + +// struct psp_xgmi_topology_info { +// uint32_t num_nodes; +// struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; +// }; + +// struct psp_bin_desc { +// uint32_t fw_version; +// uint32_t feature_version; +// uint32_t size_bytes; +// uint8_t *start_addr; +// }; + +// struct ta_mem_context { +// struct amdgpu_bo *shared_bo; +// uint64_t shared_mc_addr; +// void *shared_buf; +// enum psp_shared_mem_size shared_mem_size; +// }; + +// struct ta_context { +// bool initialized; +// uint32_t session_id; +// uint32_t resp_status; +// struct ta_mem_context mem_context; +// struct psp_bin_desc bin_desc; +// enum psp_gfx_cmd_id ta_load_type; +// enum ta_type_id ta_type; +// }; + +// struct ta_cp_context { +// struct ta_context context; +// struct mutex mutex; +// }; + +// struct psp_xgmi_context { +// struct ta_context context; +// struct psp_xgmi_topology_info top_info; +// bool supports_extended_data; +// uint8_t xgmi_ta_caps; +// }; + +// struct psp_ras_context { +// struct ta_context context; +// struct amdgpu_ras *ras; +// }; + +#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 +#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 +#define GDDR6_MEM_TRAINING_OFFSET 0x8000 +/*Define the VRAM size that will be encroached by BIST training.*/ +#define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 + +enum psp_memory_training_init_flag { + PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, + PSP_MEM_TRAIN_SUPPORT = 0x1, + PSP_MEM_TRAIN_INIT_FAILED = 0x2, + PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, + PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, +}; + +enum psp_memory_training_ops { + PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, + PSP_MEM_TRAIN_SAVE = 0x2, + PSP_MEM_TRAIN_RESTORE = 0x4, + PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, + PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, + PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, +}; + +// struct psp_memory_training_context { +// /*training data size*/ +// u64 train_data_size; +// /* +// * sys_cache +// * cpu virtual address +// * system memory buffer that used to store the training data. +// */ +// void *sys_cache; + +// /*vram offset of the p2c training data*/ +// u64 p2c_train_data_offset; + +// /*vram offset of the c2p training data*/ +// u64 c2p_train_data_offset; +// struct amdgpu_bo *c2p_bo; + +// enum psp_memory_training_init_flag init; +// u32 training_cnt; +// bool enable_mem_training; +// }; + +/** PSP runtime DB **/ +#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 +#define PSP_RUNTIME_DB_OFFSET 0x100000 +#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 +#define PSP_RUNTIME_DB_VER_1 0x0100 +#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 + +enum psp_runtime_entry_type { + PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, + PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, + PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ + PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ + PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ + PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ + PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ +}; + +/* PSP runtime DB header */ +// struct psp_runtime_data_header { +// /* determine the existence of runtime db */ +// uint16_t cookie; +// /* version of runtime db */ +// uint16_t version; +// }; + +// /* PSP runtime DB entry */ +// struct psp_runtime_entry { +// /* type of runtime db entry */ +// uint32_t entry_type; +// /* offset of entry in bytes */ +// uint16_t offset; +// /* size of entry in bytes */ +// uint16_t size; +// }; + +// /* PSP runtime DB directory */ +// struct psp_runtime_data_directory { +// /* number of valid entries */ +// uint16_t entry_count; +// /* db entries*/ +// struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; +// }; + +/* PSP runtime DB boot config feature bitmask */ +enum psp_runtime_boot_cfg_feature { + BOOT_CFG_FEATURE_GECC = 0x1, + BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, +}; + +/* PSP run time DB SCPM authentication defines */ +enum psp_runtime_scpm_authentication { + SCPM_DISABLE = 0x0, + SCPM_ENABLE = 0x1, + SCPM_ENABLE_WITH_SCPM_ERR = 0x2, +}; + +/* PSP runtime DB boot config entry */ +// struct psp_runtime_boot_cfg_entry { +// uint32_t boot_cfg_bitmask; +// uint32_t reserved; +// }; + +// /* PSP runtime DB SCPM entry */ +// struct psp_runtime_scpm_entry { +// enum psp_runtime_scpm_authentication scpm_status; +// }; + +// struct psp_context { +// struct amdgpu_device *adev; +// struct psp_ring km_ring; +// struct psp_gfx_cmd_resp *cmd; + +// const struct psp_funcs *funcs; +// const struct ta_funcs *ta_funcs; + +// /* firmware buffer */ +// struct amdgpu_bo *fw_pri_bo; +// uint64_t fw_pri_mc_addr; +// void *fw_pri_buf; + +// /* sos firmware */ +// const struct firmware *sos_fw; +// struct psp_bin_desc sys; +// struct psp_bin_desc sos; +// struct psp_bin_desc toc; +// struct psp_bin_desc kdb; +// struct psp_bin_desc spl; +// struct psp_bin_desc rl; +// struct psp_bin_desc soc_drv; +// struct psp_bin_desc intf_drv; +// struct psp_bin_desc dbg_drv; +// struct psp_bin_desc ras_drv; +// struct psp_bin_desc ipkeymgr_drv; + +// /* tmr buffer */ +// struct amdgpu_bo *tmr_bo; +// uint64_t tmr_mc_addr; + +// /* asd firmware */ +// const struct firmware *asd_fw; + +// /* toc firmware */ +// const struct firmware *toc_fw; + +// /* cap firmware */ +// const struct firmware *cap_fw; + +// /* fence buffer */ +// struct amdgpu_bo *fence_buf_bo; +// uint64_t fence_buf_mc_addr; +// void *fence_buf; + +// /* cmd buffer */ +// struct amdgpu_bo *cmd_buf_bo; +// uint64_t cmd_buf_mc_addr; +// struct psp_gfx_cmd_resp *cmd_buf_mem; + +// /* fence value associated with cmd buffer */ +// atomic_t fence_value; +// /* flag to mark whether gfx fw autoload is supported or not */ +// bool autoload_supported; +// /* flag to mark whether psp use runtime TMR or boottime TMR */ +// bool boot_time_tmr; +// /* flag to mark whether df cstate management centralized to PMFW */ +// bool pmfw_centralized_cstate_management; + +// /* xgmi ta firmware and buffer */ +// const struct firmware *ta_fw; +// uint32_t ta_fw_version; + +// uint32_t cap_fw_version; +// uint32_t cap_feature_version; +// uint32_t cap_ucode_size; + +// struct ta_context asd_context; +// struct psp_xgmi_context xgmi_context; +// struct psp_ras_context ras_context; +// struct ta_cp_context hdcp_context; +// struct ta_cp_context dtm_context; +// struct ta_cp_context rap_context; +// struct ta_cp_context securedisplay_context; +// struct mutex mutex; +// struct psp_memory_training_context mem_train_ctx; + +// uint32_t boot_cfg_bitmask; + +// /* firmware upgrades supported */ +// bool sup_pd_fw_up; +// bool sup_ifwi_up; + +// char *vbflash_tmp_buf; +// size_t vbflash_image_size; +// bool vbflash_done; +// }; + +// struct amdgpu_psp_funcs { +// bool (*check_fw_loading_status)(struct amdgpu_device *adev, +// enum AMDGPU_UCODE_ID); +// }; + + +// #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) +// #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) +// #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) +// #define psp_init_microcode(psp) \ +// ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) +// #define psp_bootloader_load_kdb(psp) \ +// ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) +// #define psp_bootloader_load_spl(psp) \ +// ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) +// #define psp_bootloader_load_sysdrv(psp) \ +// ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) +// #define psp_bootloader_load_soc_drv(psp) \ +// ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) +// #define psp_bootloader_load_intf_drv(psp) \ +// ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) +// #define psp_bootloader_load_dbg_drv(psp) \ +// ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) +// #define psp_bootloader_load_ras_drv(psp) \ +// ((psp)->funcs->bootloader_load_ras_drv ? \ +// (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) +// #define psp_bootloader_load_ipkeymgr_drv(psp) \ +// ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ +// (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) +// #define psp_bootloader_load_sos(psp) \ +// ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) +// #define psp_smu_reload_quirk(psp) \ +// ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) +// #define psp_mode1_reset(psp) \ +// ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) +// #define psp_mem_training(psp, ops) \ +// ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) + +// #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) +// #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) + +// #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ +// ((psp)->funcs->load_usbc_pd_fw ? \ +// (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) + +// #define psp_read_usbc_pd_fw(psp, fw_ver) \ +// ((psp)->funcs->read_usbc_pd_fw ? \ +// (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) + +// #define psp_update_spirom(psp, fw_pri_mc_addr) \ +// ((psp)->funcs->update_spirom ? \ +// (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) + +// #define psp_vbflash_status(psp) \ +// ((psp)->funcs->vbflash_stat ? \ +// (psp)->funcs->vbflash_stat((psp)) : -EINVAL) + +// #define psp_fatal_error_recovery_quirk(psp) \ +// ((psp)->funcs->fatal_error_recovery_quirk ? \ +// (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) + +// #define psp_is_aux_sos_load_required(psp) \ +// ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) + +// extern const struct amd_ip_funcs psp_ip_funcs; + +// extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; +// extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; +// extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; +// extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; +// extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; +// extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; +// extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; +// extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; + +// extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, +// uint32_t field_val, uint32_t mask, bool check_changed); +// extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, +// uint32_t field_val, uint32_t mask, uint32_t msec_timeout); + +// int psp_execute_ip_fw_load(struct psp_context *psp, +// struct amdgpu_firmware_info *ucode); + +// int psp_gpu_reset(struct amdgpu_device *adev); + +// int psp_ta_init_shared_buf(struct psp_context *psp, +// struct ta_mem_context *mem_ctx); +// void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); +// int psp_ta_unload(struct psp_context *psp, struct ta_context *context); +// int psp_ta_load(struct psp_context *psp, struct ta_context *context); +// int psp_ta_invoke(struct psp_context *psp, +// uint32_t ta_cmd_id, +// struct ta_context *context); + +// int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); +// int psp_xgmi_terminate(struct psp_context *psp); +// int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); +// int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); +// int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); +// int psp_xgmi_get_topology_info(struct psp_context *psp, +// int number_devices, +// struct psp_xgmi_topology_info *topology, +// bool get_extended_data); +// int psp_xgmi_set_topology_info(struct psp_context *psp, +// int number_devices, +// struct psp_xgmi_topology_info *topology); +// int psp_ras_initialize(struct psp_context *psp); +// int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); +// int psp_ras_enable_features(struct psp_context *psp, +// union ta_ras_cmd_input *info, bool enable); +// int psp_ras_trigger_error(struct psp_context *psp, +// struct ta_ras_trigger_error_input *info, uint32_t instance_mask); +// int psp_ras_terminate(struct psp_context *psp); +// int psp_ras_query_address(struct psp_context *psp, +// struct ta_ras_query_address_input *addr_in, +// struct ta_ras_query_address_output *addr_out); + +// int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); +// int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); +// int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); +// int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); + +// int psp_rlc_autoload_start(struct psp_context *psp); + +// int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, +// uint32_t value); +// int psp_ring_cmd_submit(struct psp_context *psp, +// uint64_t cmd_buf_mc_addr, +// uint64_t fence_mc_addr, +// int index); +// int psp_init_asd_microcode(struct psp_context *psp, +// const char *chip_name); +// int psp_init_toc_microcode(struct psp_context *psp, +// const char *chip_name); +// int psp_init_sos_microcode(struct psp_context *psp, +// const char *chip_name); +// int psp_init_ta_microcode(struct psp_context *psp, +// const char *chip_name); +// int psp_init_cap_microcode(struct psp_context *psp, +// const char *chip_name); +// int psp_get_fw_attestation_records_addr(struct psp_context *psp, +// uint64_t *output_ptr); + +// int psp_load_fw_list(struct psp_context *psp, +// struct amdgpu_firmware_info **ucode_list, int ucode_count); +// void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); + +// int psp_spatial_partition(struct psp_context *psp, int mode); + +// int is_psp_fw_valid(struct psp_bin_desc bin); + +// int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); +// bool amdgpu_psp_get_ras_capability(struct psp_context *psp); +#endif diff --git a/extra/amdpci/headers/amdgpu_smu.h b/extra/amdpci/headers/amdgpu_smu.h new file mode 100644 index 0000000000..51b822781a --- /dev/null +++ b/extra/amdpci/headers/amdgpu_smu.h @@ -0,0 +1,347 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_SMU_H__ +#define __AMDGPU_SMU_H__ + +#define int32_t int +#define uint32_t unsigned int +#define int8_t signed char +#define uint8_t unsigned char +#define uint16_t unsigned short +#define int16_t short +#define uint64_t unsigned long long +#define bool _Bool +#define u32 unsigned int + +#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 +#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 +#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 +#define SMU_FW_NAME_LEN 0x24 + +#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) +#define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) +#define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) + +// Power Throttlers +#define SMU_THROTTLER_PPT0_BIT 0 +#define SMU_THROTTLER_PPT1_BIT 1 +#define SMU_THROTTLER_PPT2_BIT 2 +#define SMU_THROTTLER_PPT3_BIT 3 +#define SMU_THROTTLER_SPL_BIT 4 +#define SMU_THROTTLER_FPPT_BIT 5 +#define SMU_THROTTLER_SPPT_BIT 6 +#define SMU_THROTTLER_SPPT_APU_BIT 7 + +// Current Throttlers +#define SMU_THROTTLER_TDC_GFX_BIT 16 +#define SMU_THROTTLER_TDC_SOC_BIT 17 +#define SMU_THROTTLER_TDC_MEM_BIT 18 +#define SMU_THROTTLER_TDC_VDD_BIT 19 +#define SMU_THROTTLER_TDC_CVIP_BIT 20 +#define SMU_THROTTLER_EDC_CPU_BIT 21 +#define SMU_THROTTLER_EDC_GFX_BIT 22 +#define SMU_THROTTLER_APCC_BIT 23 + +// Temperature +#define SMU_THROTTLER_TEMP_GPU_BIT 32 +#define SMU_THROTTLER_TEMP_CORE_BIT 33 +#define SMU_THROTTLER_TEMP_MEM_BIT 34 +#define SMU_THROTTLER_TEMP_EDGE_BIT 35 +#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 +#define SMU_THROTTLER_TEMP_SOC_BIT 37 +#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 +#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 +#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 +#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 +#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 +#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 +#define SMU_THROTTLER_VRHOT0_BIT 44 +#define SMU_THROTTLER_VRHOT1_BIT 45 +#define SMU_THROTTLER_PROCHOT_CPU_BIT 46 +#define SMU_THROTTLER_PROCHOT_GFX_BIT 47 + +// Other +#define SMU_THROTTLER_PPM_BIT 56 +#define SMU_THROTTLER_FIT_BIT 57 + +struct smu_hw_power_state { + unsigned int magic; +}; + +struct smu_power_state; + +enum smu_state_ui_label { + SMU_STATE_UI_LABEL_NONE, + SMU_STATE_UI_LABEL_BATTERY, + SMU_STATE_UI_TABEL_MIDDLE_LOW, + SMU_STATE_UI_LABEL_BALLANCED, + SMU_STATE_UI_LABEL_MIDDLE_HIGHT, + SMU_STATE_UI_LABEL_PERFORMANCE, + SMU_STATE_UI_LABEL_BACO, +}; + +enum smu_state_classification_flag { + SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, + SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, + SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, + SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, + SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, + SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, + SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, + SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, + SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, + SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, + SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, + SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, + SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, + SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, + SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, + SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, + SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, + SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, + SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, + SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, + SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, +}; + +struct smu_state_classification_block { + enum smu_state_ui_label ui_label; + enum smu_state_classification_flag flags; + int bios_index; + bool temporary_state; + bool to_be_deleted; +}; + +struct smu_state_pcie_block { + unsigned int lanes; +}; + +enum smu_refreshrate_source { + SMU_REFRESHRATE_SOURCE_EDID, + SMU_REFRESHRATE_SOURCE_EXPLICIT +}; + +struct smu_state_display_block { + bool disable_frame_modulation; + bool limit_refreshrate; + enum smu_refreshrate_source refreshrate_source; + int explicit_refreshrate; + int edid_refreshrate_index; + bool enable_vari_bright; +}; + +struct smu_state_memory_block { + bool dll_off; + uint8_t m3arb; + uint8_t unused[3]; +}; + +struct smu_state_software_algorithm_block { + bool disable_load_balancing; + bool enable_sleep_for_timestamps; +}; + +struct smu_temperature_range { + int min; + int max; + int edge_emergency_max; + int hotspot_min; + int hotspot_crit_max; + int hotspot_emergency_max; + int mem_min; + int mem_crit_max; + int mem_emergency_max; + int software_shutdown_temp; + int software_shutdown_temp_offset; +}; + +struct smu_state_validation_block { + bool single_display_only; + bool disallow_on_dc; + uint8_t supported_power_levels; +}; + +struct smu_uvd_clocks { + uint32_t vclk; + uint32_t dclk; +}; + +/** +* Structure to hold a SMU Power State. +*/ + +enum smu_power_src_type { + SMU_POWER_SOURCE_AC, + SMU_POWER_SOURCE_DC, + SMU_POWER_SOURCE_COUNT, +}; + +enum smu_ppt_limit_type { + SMU_DEFAULT_PPT_LIMIT = 0, + SMU_FAST_PPT_LIMIT, +}; + +enum smu_ppt_limit_level { + SMU_PPT_LIMIT_MIN = -1, + SMU_PPT_LIMIT_CURRENT, + SMU_PPT_LIMIT_DEFAULT, + SMU_PPT_LIMIT_MAX, +}; + +enum smu_memory_pool_size { + SMU_MEMORY_POOL_SIZE_ZERO = 0, + SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, + SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, + SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, + SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, +}; + +enum smu_clk_type { + SMU_GFXCLK, + SMU_VCLK, + SMU_DCLK, + SMU_VCLK1, + SMU_DCLK1, + SMU_ECLK, + SMU_SOCCLK, + SMU_UCLK, + SMU_DCEFCLK, + SMU_DISPCLK, + SMU_PIXCLK, + SMU_PHYCLK, + SMU_FCLK, + SMU_SCLK, + SMU_MCLK, + SMU_PCIE, + SMU_LCLK, + SMU_OD_CCLK, + SMU_OD_SCLK, + SMU_OD_MCLK, + SMU_OD_VDDC_CURVE, + SMU_OD_RANGE, + SMU_OD_VDDGFX_OFFSET, + SMU_OD_FAN_CURVE, + SMU_OD_ACOUSTIC_LIMIT, + SMU_OD_ACOUSTIC_TARGET, + SMU_OD_FAN_TARGET_TEMPERATURE, + SMU_OD_FAN_MINIMUM_PWM, + SMU_CLK_COUNT, +}; + +struct smu_user_dpm_profile { + uint32_t fan_mode; + uint32_t power_limit; + uint32_t fan_speed_pwm; + uint32_t fan_speed_rpm; + uint32_t flags; + uint32_t user_od; + + /* user clock state information */ + uint32_t clk_mask[SMU_CLK_COUNT]; + uint32_t clk_dependency; +}; + +#define SMU_TABLE_INIT(tables, table_id, s, a, d) \ + do { \ + tables[table_id].size = s; \ + tables[table_id].align = a; \ + tables[table_id].domain = d; \ + } while (0) + +struct smu_table { + uint64_t size; + uint32_t align; + uint8_t domain; + uint64_t mc_address; + void *cpu_addr; + struct amdgpu_bo *bo; + uint32_t version; +}; + +enum smu_perf_level_designation { + PERF_LEVEL_ACTIVITY, + PERF_LEVEL_POWER_CONTAINMENT, +}; + +struct smu_performance_level { + uint32_t core_clock; + uint32_t memory_clock; + uint32_t vddc; + uint32_t vddci; + uint32_t non_local_mem_freq; + uint32_t non_local_mem_width; +}; + +struct smu_clock_info { + uint32_t min_mem_clk; + uint32_t max_mem_clk; + uint32_t min_eng_clk; + uint32_t max_eng_clk; + uint32_t min_bus_bandwidth; + uint32_t max_bus_bandwidth; +}; + +struct smu_bios_boot_up_values { + uint32_t revision; + uint32_t gfxclk; + uint32_t uclk; + uint32_t socclk; + uint32_t dcefclk; + uint32_t eclk; + uint32_t vclk; + uint32_t dclk; + uint16_t vddc; + uint16_t vddci; + uint16_t mvddc; + uint16_t vdd_gfx; + uint8_t cooling_id; + uint32_t pp_table_id; + uint32_t format_revision; + uint32_t content_revision; + uint32_t fclk; + uint32_t lclk; + uint32_t firmware_caps; +}; + +enum smu_table_id { + SMU_TABLE_PPTABLE = 0, + SMU_TABLE_WATERMARKS, + SMU_TABLE_CUSTOM_DPM, + SMU_TABLE_DPMCLOCKS, + SMU_TABLE_AVFS, + SMU_TABLE_AVFS_PSM_DEBUG, + SMU_TABLE_AVFS_FUSE_OVERRIDE, + SMU_TABLE_PMSTATUSLOG, + SMU_TABLE_SMU_METRICS, + SMU_TABLE_DRIVER_SMU_CONFIG, + SMU_TABLE_ACTIVITY_MONITOR_COEFF, + SMU_TABLE_OVERDRIVE, + SMU_TABLE_I2C_COMMANDS, + SMU_TABLE_PACE, + SMU_TABLE_ECCINFO, + SMU_TABLE_COMBO_PPTABLE, + SMU_TABLE_WIFIBAND, + SMU_TABLE_COUNT, +}; + + +#endif diff --git a/extra/amdpci/headers/amdgpu_ucode.h b/extra/amdpci/headers/amdgpu_ucode.h new file mode 100644 index 0000000000..8f8d02490e --- /dev/null +++ b/extra/amdpci/headers/amdgpu_ucode.h @@ -0,0 +1,634 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __AMDGPU_UCODE_H__ +#define __AMDGPU_UCODE_H__ + +// #include "amdgpu_socbb.h" +#define int32_t int +#define uint32_t unsigned int +#define int8_t signed char +#define uint8_t unsigned char +#define uint16_t unsigned short +#define int16_t short +#define uint64_t unsigned long long +#define bool _Bool +#define u32 unsigned int + +struct common_firmware_header { + uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ + uint32_t header_size_bytes; /* size of just the header in bytes */ + uint16_t header_version_major; /* header version */ + uint16_t header_version_minor; /* header version */ + uint16_t ip_version_major; /* IP version */ + uint16_t ip_version_minor; /* IP version */ + uint32_t ucode_version; + uint32_t ucode_size_bytes; /* size of ucode in bytes */ + uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t crc32; /* crc32 checksum of the payload */ +}; + +/* version_major=1, version_minor=0 */ +struct mc_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t io_debug_size_bytes; /* size of debug array in dwords */ + uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ +}; + +/* version_major=1, version_minor=0 */ +struct smc_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_start_addr; +}; + +/* version_major=2, version_minor=0 */ +struct smc_firmware_header_v2_0 { + struct smc_firmware_header_v1_0 v1_0; + uint32_t ppt_offset_bytes; /* soft pptable offset */ + uint32_t ppt_size_bytes; /* soft pptable size */ +}; + +struct smc_soft_pptable_entry { + uint32_t id; + uint32_t ppt_offset_bytes; + uint32_t ppt_size_bytes; +}; + +/* version_major=2, version_minor=1 */ +struct smc_firmware_header_v2_1 { + struct smc_firmware_header_v1_0 v1_0; + uint32_t pptable_count; + uint32_t pptable_entry_offset; +}; + +struct psp_fw_legacy_bin_desc { + uint32_t fw_version; + uint32_t offset_bytes; + uint32_t size_bytes; +}; + +/* version_major=1, version_minor=0 */ +struct psp_firmware_header_v1_0 { + struct common_firmware_header header; + struct psp_fw_legacy_bin_desc sos; +}; + +/* version_major=1, version_minor=1 */ +struct psp_firmware_header_v1_1 { + struct psp_firmware_header_v1_0 v1_0; + struct psp_fw_legacy_bin_desc toc; + struct psp_fw_legacy_bin_desc kdb; +}; + +/* version_major=1, version_minor=2 */ +struct psp_firmware_header_v1_2 { + struct psp_firmware_header_v1_0 v1_0; + struct psp_fw_legacy_bin_desc res; + struct psp_fw_legacy_bin_desc kdb; +}; + +/* version_major=1, version_minor=3 */ +struct psp_firmware_header_v1_3 { + struct psp_firmware_header_v1_1 v1_1; + struct psp_fw_legacy_bin_desc spl; + struct psp_fw_legacy_bin_desc rl; + struct psp_fw_legacy_bin_desc sys_drv_aux; + struct psp_fw_legacy_bin_desc sos_aux; +}; + +struct psp_fw_bin_desc { + uint32_t fw_type; + uint32_t fw_version; + uint32_t offset_bytes; + uint32_t size_bytes; +}; + +enum psp_fw_type { + PSP_FW_TYPE_UNKOWN, + PSP_FW_TYPE_PSP_SOS, + PSP_FW_TYPE_PSP_SYS_DRV, + PSP_FW_TYPE_PSP_KDB, + PSP_FW_TYPE_PSP_TOC, + PSP_FW_TYPE_PSP_SPL, + PSP_FW_TYPE_PSP_RL, + PSP_FW_TYPE_PSP_SOC_DRV, + PSP_FW_TYPE_PSP_INTF_DRV, + PSP_FW_TYPE_PSP_DBG_DRV, + PSP_FW_TYPE_PSP_RAS_DRV, + PSP_FW_TYPE_PSP_IPKEYMGR_DRV, + PSP_FW_TYPE_MAX_INDEX, +}; + +/* version_major=2, version_minor=0 */ +struct psp_firmware_header_v2_0 { + struct common_firmware_header header; + uint32_t psp_fw_bin_count; + struct psp_fw_bin_desc psp_fw_bin[1]; +}; + +/* version_major=2, version_minor=1 */ +struct psp_firmware_header_v2_1 { + struct common_firmware_header header; + uint32_t psp_fw_bin_count; + uint32_t psp_aux_fw_bin_index; + struct psp_fw_bin_desc psp_fw_bin[1]; +}; + +/* version_major=1, version_minor=0 */ +struct ta_firmware_header_v1_0 { + struct common_firmware_header header; + struct psp_fw_legacy_bin_desc xgmi; + struct psp_fw_legacy_bin_desc ras; + struct psp_fw_legacy_bin_desc hdcp; + struct psp_fw_legacy_bin_desc dtm; + struct psp_fw_legacy_bin_desc securedisplay; +}; + +enum ta_fw_type { + TA_FW_TYPE_UNKOWN, + TA_FW_TYPE_PSP_ASD, + TA_FW_TYPE_PSP_XGMI, + TA_FW_TYPE_PSP_RAS, + TA_FW_TYPE_PSP_HDCP, + TA_FW_TYPE_PSP_DTM, + TA_FW_TYPE_PSP_RAP, + TA_FW_TYPE_PSP_SECUREDISPLAY, + TA_FW_TYPE_MAX_INDEX, +}; + +/* version_major=2, version_minor=0 */ +struct ta_firmware_header_v2_0 { + struct common_firmware_header header; + uint32_t ta_fw_bin_count; + struct psp_fw_bin_desc ta_fw_bin[1]; +}; + +/* version_major=1, version_minor=0 */ +struct gfx_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t jt_offset; /* jt location */ + uint32_t jt_size; /* size of jt */ +}; + +/* version_major=2, version_minor=0 */ +struct gfx_firmware_header_v2_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t ucode_size_bytes; + uint32_t ucode_offset_bytes; + uint32_t data_size_bytes; + uint32_t data_offset_bytes; + uint32_t ucode_start_addr_lo; + uint32_t ucode_start_addr_hi; +}; + +/* version_major=1, version_minor=0 */ +struct mes_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t mes_ucode_version; + uint32_t mes_ucode_size_bytes; + uint32_t mes_ucode_offset_bytes; + uint32_t mes_ucode_data_version; + uint32_t mes_ucode_data_size_bytes; + uint32_t mes_ucode_data_offset_bytes; + uint32_t mes_uc_start_addr_lo; + uint32_t mes_uc_start_addr_hi; + uint32_t mes_data_start_addr_lo; + uint32_t mes_data_start_addr_hi; +}; + +/* version_major=1, version_minor=0 */ +struct rlc_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t save_and_restore_offset; + uint32_t clear_state_descriptor_offset; + uint32_t avail_scratch_ram_locations; + uint32_t master_pkt_description_offset; +}; + +/* version_major=2, version_minor=0 */ +struct rlc_firmware_header_v2_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t jt_offset; /* jt location */ + uint32_t jt_size; /* size of jt */ + uint32_t save_and_restore_offset; + uint32_t clear_state_descriptor_offset; + uint32_t avail_scratch_ram_locations; + uint32_t reg_restore_list_size; + uint32_t reg_list_format_start; + uint32_t reg_list_format_separate_start; + uint32_t starting_offsets_start; + uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ + uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ + uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ + uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ + uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ +}; + +/* version_major=2, version_minor=1 */ +struct rlc_firmware_header_v2_1 { + struct rlc_firmware_header_v2_0 v2_0; + uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ + uint32_t save_restore_list_cntl_ucode_ver; + uint32_t save_restore_list_cntl_feature_ver; + uint32_t save_restore_list_cntl_size_bytes; + uint32_t save_restore_list_cntl_offset_bytes; + uint32_t save_restore_list_gpm_ucode_ver; + uint32_t save_restore_list_gpm_feature_ver; + uint32_t save_restore_list_gpm_size_bytes; + uint32_t save_restore_list_gpm_offset_bytes; + uint32_t save_restore_list_srm_ucode_ver; + uint32_t save_restore_list_srm_feature_ver; + uint32_t save_restore_list_srm_size_bytes; + uint32_t save_restore_list_srm_offset_bytes; +}; + +/* version_major=2, version_minor=2 */ +struct rlc_firmware_header_v2_2 { + struct rlc_firmware_header_v2_1 v2_1; + uint32_t rlc_iram_ucode_size_bytes; + uint32_t rlc_iram_ucode_offset_bytes; + uint32_t rlc_dram_ucode_size_bytes; + uint32_t rlc_dram_ucode_offset_bytes; +}; + +/* version_major=2, version_minor=3 */ +struct rlc_firmware_header_v2_3 { + struct rlc_firmware_header_v2_2 v2_2; + uint32_t rlcp_ucode_version; + uint32_t rlcp_ucode_feature_version; + uint32_t rlcp_ucode_size_bytes; + uint32_t rlcp_ucode_offset_bytes; + uint32_t rlcv_ucode_version; + uint32_t rlcv_ucode_feature_version; + uint32_t rlcv_ucode_size_bytes; + uint32_t rlcv_ucode_offset_bytes; +}; + +/* version_major=2, version_minor=4 */ +struct rlc_firmware_header_v2_4 { + struct rlc_firmware_header_v2_3 v2_3; + uint32_t global_tap_delays_ucode_size_bytes; + uint32_t global_tap_delays_ucode_offset_bytes; + uint32_t se0_tap_delays_ucode_size_bytes; + uint32_t se0_tap_delays_ucode_offset_bytes; + uint32_t se1_tap_delays_ucode_size_bytes; + uint32_t se1_tap_delays_ucode_offset_bytes; + uint32_t se2_tap_delays_ucode_size_bytes; + uint32_t se2_tap_delays_ucode_offset_bytes; + uint32_t se3_tap_delays_ucode_size_bytes; + uint32_t se3_tap_delays_ucode_offset_bytes; +}; + +/* version_major=1, version_minor=0 */ +struct sdma_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t ucode_change_version; + uint32_t jt_offset; /* jt location */ + uint32_t jt_size; /* size of jt */ +}; + +/* version_major=1, version_minor=1 */ +struct sdma_firmware_header_v1_1 { + struct sdma_firmware_header_v1_0 v1_0; + uint32_t digest_size; +}; + +/* version_major=2, version_minor=0 */ +struct sdma_firmware_header_v2_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ + uint32_t ctx_jt_offset; /* context thread jt location */ + uint32_t ctx_jt_size; /* context thread size of jt */ + uint32_t ctl_ucode_offset; + uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ + uint32_t ctl_jt_offset; /* control thread jt location */ + uint32_t ctl_jt_size; /* control thread size of jt */ +}; + +/* version_major=1, version_minor=0 */ +struct vpe_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ + uint32_t ctx_jt_offset; /* context thread jt location */ + uint32_t ctx_jt_size; /* context thread size of jt */ + uint32_t ctl_ucode_offset; + uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ + uint32_t ctl_jt_offset; /* control thread jt location */ + uint32_t ctl_jt_size; /* control thread size of jt */ +}; + +/* version_major=1, version_minor=0 */ +struct umsch_mm_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t umsch_mm_ucode_version; + uint32_t umsch_mm_ucode_size_bytes; + uint32_t umsch_mm_ucode_offset_bytes; + uint32_t umsch_mm_ucode_data_version; + uint32_t umsch_mm_ucode_data_size_bytes; + uint32_t umsch_mm_ucode_data_offset_bytes; + uint32_t umsch_mm_irq_start_addr_lo; + uint32_t umsch_mm_irq_start_addr_hi; + uint32_t umsch_mm_uc_start_addr_lo; + uint32_t umsch_mm_uc_start_addr_hi; + uint32_t umsch_mm_data_start_addr_lo; + uint32_t umsch_mm_data_start_addr_hi; +}; + +/* version_major=3, version_minor=0 */ +struct sdma_firmware_header_v3_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t ucode_offset_bytes; + uint32_t ucode_size_bytes; +}; + +/* gpu info payload */ +struct gpu_info_firmware_v1_0 { + uint32_t gc_num_se; + uint32_t gc_num_cu_per_sh; + uint32_t gc_num_sh_per_se; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_tccs; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; +}; + +struct gpu_info_firmware_v1_1 { + struct gpu_info_firmware_v1_0 v1_0; + uint32_t num_sc_per_sh; + uint32_t num_packer_per_sc; +}; + +/* gpu info payload + * version_major=1, version_minor=1 */ +// struct gpu_info_firmware_v1_2 { +// struct gpu_info_firmware_v1_1 v1_1; +// struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; +// }; + +/* version_major=1, version_minor=0 */ +struct gpu_info_firmware_header_v1_0 { + struct common_firmware_header header; + uint16_t version_major; /* version */ + uint16_t version_minor; /* version */ +}; + +/* version_major=1, version_minor=0 */ +struct dmcu_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ + uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ +}; + +/* version_major=1, version_minor=0 */ +struct dmcub_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t inst_const_bytes; /* size of instruction region, in bytes */ + uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ +}; + +/* version_major=1, version_minor=0 */ +struct imu_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t imu_iram_ucode_size_bytes; + uint32_t imu_iram_ucode_offset_bytes; + uint32_t imu_dram_ucode_size_bytes; + uint32_t imu_dram_ucode_offset_bytes; +}; + +/* header is fixed size */ +union amdgpu_firmware_header { + struct common_firmware_header common; + struct mc_firmware_header_v1_0 mc; + struct smc_firmware_header_v1_0 smc; + struct smc_firmware_header_v2_0 smc_v2_0; + struct psp_firmware_header_v1_0 psp; + struct psp_firmware_header_v1_1 psp_v1_1; + struct psp_firmware_header_v1_3 psp_v1_3; + struct psp_firmware_header_v2_0 psp_v2_0; + struct psp_firmware_header_v2_0 psp_v2_1; + struct ta_firmware_header_v1_0 ta; + struct ta_firmware_header_v2_0 ta_v2_0; + struct gfx_firmware_header_v1_0 gfx; + struct gfx_firmware_header_v2_0 gfx_v2_0; + struct rlc_firmware_header_v1_0 rlc; + struct rlc_firmware_header_v2_0 rlc_v2_0; + struct rlc_firmware_header_v2_1 rlc_v2_1; + struct rlc_firmware_header_v2_2 rlc_v2_2; + struct rlc_firmware_header_v2_3 rlc_v2_3; + struct rlc_firmware_header_v2_4 rlc_v2_4; + struct sdma_firmware_header_v1_0 sdma; + struct sdma_firmware_header_v1_1 sdma_v1_1; + struct sdma_firmware_header_v2_0 sdma_v2_0; + struct sdma_firmware_header_v3_0 sdma_v3_0; + struct gpu_info_firmware_header_v1_0 gpu_info; + struct dmcu_firmware_header_v1_0 dmcu; + struct dmcub_firmware_header_v1_0 dmcub; + struct imu_firmware_header_v1_0 imu; + uint8_t raw[0x100]; +}; + +#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2) + +/* + * fw loading support + */ +enum AMDGPU_UCODE_ID { + AMDGPU_UCODE_ID_CAP = 0, + AMDGPU_UCODE_ID_SDMA0, + AMDGPU_UCODE_ID_SDMA1, + AMDGPU_UCODE_ID_SDMA2, + AMDGPU_UCODE_ID_SDMA3, + AMDGPU_UCODE_ID_SDMA4, + AMDGPU_UCODE_ID_SDMA5, + AMDGPU_UCODE_ID_SDMA6, + AMDGPU_UCODE_ID_SDMA7, + AMDGPU_UCODE_ID_SDMA_UCODE_TH0, + AMDGPU_UCODE_ID_SDMA_UCODE_TH1, + AMDGPU_UCODE_ID_SDMA_RS64, + AMDGPU_UCODE_ID_CP_CE, + AMDGPU_UCODE_ID_CP_PFP, + AMDGPU_UCODE_ID_CP_ME, + AMDGPU_UCODE_ID_CP_RS64_PFP, + AMDGPU_UCODE_ID_CP_RS64_ME, + AMDGPU_UCODE_ID_CP_RS64_MEC, + AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, + AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, + AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, + AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, + AMDGPU_UCODE_ID_CP_MEC1, + AMDGPU_UCODE_ID_CP_MEC1_JT, + AMDGPU_UCODE_ID_CP_MEC2, + AMDGPU_UCODE_ID_CP_MEC2_JT, + AMDGPU_UCODE_ID_CP_MES, + AMDGPU_UCODE_ID_CP_MES_DATA, + AMDGPU_UCODE_ID_CP_MES1, + AMDGPU_UCODE_ID_CP_MES1_DATA, + AMDGPU_UCODE_ID_IMU_I, + AMDGPU_UCODE_ID_IMU_D, + AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, + AMDGPU_UCODE_ID_SE0_TAP_DELAYS, + AMDGPU_UCODE_ID_SE1_TAP_DELAYS, + AMDGPU_UCODE_ID_SE2_TAP_DELAYS, + AMDGPU_UCODE_ID_SE3_TAP_DELAYS, + AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, + AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, + AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, + AMDGPU_UCODE_ID_RLC_IRAM, + AMDGPU_UCODE_ID_RLC_DRAM, + AMDGPU_UCODE_ID_RLC_P, + AMDGPU_UCODE_ID_RLC_V, + AMDGPU_UCODE_ID_RLC_G, + AMDGPU_UCODE_ID_STORAGE, + AMDGPU_UCODE_ID_SMC, + AMDGPU_UCODE_ID_PPTABLE, + AMDGPU_UCODE_ID_UVD, + AMDGPU_UCODE_ID_UVD1, + AMDGPU_UCODE_ID_VCE, + AMDGPU_UCODE_ID_VCN, + AMDGPU_UCODE_ID_VCN1, + AMDGPU_UCODE_ID_DMCU_ERAM, + AMDGPU_UCODE_ID_DMCU_INTV, + AMDGPU_UCODE_ID_VCN0_RAM, + AMDGPU_UCODE_ID_VCN1_RAM, + AMDGPU_UCODE_ID_DMCUB, + AMDGPU_UCODE_ID_VPE_CTX, + AMDGPU_UCODE_ID_VPE_CTL, + AMDGPU_UCODE_ID_VPE, + AMDGPU_UCODE_ID_UMSCH_MM_UCODE, + AMDGPU_UCODE_ID_UMSCH_MM_DATA, + AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER, + AMDGPU_UCODE_ID_P2S_TABLE, + AMDGPU_UCODE_ID_JPEG_RAM, + AMDGPU_UCODE_ID_ISP, + AMDGPU_UCODE_ID_MAXIMUM, +}; + +/* engine firmware status */ +enum AMDGPU_UCODE_STATUS { + AMDGPU_UCODE_STATUS_INVALID, + AMDGPU_UCODE_STATUS_NOT_LOADED, + AMDGPU_UCODE_STATUS_LOADED, +}; + +enum amdgpu_firmware_load_type { + AMDGPU_FW_LOAD_DIRECT = 0, + AMDGPU_FW_LOAD_PSP, + AMDGPU_FW_LOAD_SMU, + AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, +}; + +/* conform to smu_ucode_xfer_cz.h */ +#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 +#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 +#define AMDGPU_CPCE_UCODE_LOADED 0x00000004 +#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 +#define AMDGPU_CPME_UCODE_LOADED 0x00000010 +#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 +#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 +#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 + +/* amdgpu firmware info */ +struct amdgpu_firmware_info { + /* ucode ID */ + enum AMDGPU_UCODE_ID ucode_id; + /* request_firmware */ + const struct firmware *fw; + /* starting mc address */ + uint64_t mc_addr; + /* kernel linear address */ + void *kaddr; + /* ucode_size_bytes */ + uint32_t ucode_size; + /* starting tmr mc address */ + uint32_t tmr_mc_addr_lo; + uint32_t tmr_mc_addr_hi; +}; + +// struct amdgpu_firmware { +// struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; +// enum amdgpu_firmware_load_type load_type; +// struct amdgpu_bo *fw_buf; +// unsigned int fw_size; +// unsigned int max_ucodes; +// /* firmwares are loaded by psp instead of smu from vega10 */ +// const struct amdgpu_psp_funcs *funcs; +// struct amdgpu_bo *rbuf; +// struct mutex mutex; + +// /* gpu info firmware data pointer */ +// const struct firmware *gpu_info_fw; + +// void *fw_buf_ptr; +// uint64_t fw_buf_mc; +// }; + +// void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); +// void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); +// void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); +// void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); +// void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); +// void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); +// void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); +// void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); +// int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, +// const char *fw_name); +// void amdgpu_ucode_release(const struct firmware **fw); +// bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, +// uint16_t hdr_major, uint16_t hdr_minor); + +// int amdgpu_ucode_init_bo(struct amdgpu_device *adev); +// int amdgpu_ucode_create_bo(struct amdgpu_device *adev); +// int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); +// void amdgpu_ucode_free_bo(struct amdgpu_device *adev); +// void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); + +// enum amdgpu_firmware_load_type +// amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); + +// const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); + +// void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); + +#endif diff --git a/extra/amdpci/headers/amdgpu_vm.h b/extra/amdpci/headers/amdgpu_vm.h new file mode 100644 index 0000000000..53a6e32378 --- /dev/null +++ b/extra/amdpci/headers/amdgpu_vm.h @@ -0,0 +1,665 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ +#ifndef __AMDGPU_VM_H__ +#define __AMDGPU_VM_H__ + +// #include +// #include +// #include +// #include +// #include +// #include +// #include + +// #include "amdgpu_sync.h" +// #include "amdgpu_ring.h" +// #include "amdgpu_ids.h" + +// struct drm_exec; + +// struct amdgpu_bo_va; +// struct amdgpu_job; +// struct amdgpu_bo_list_entry; +// struct amdgpu_bo_vm; +// struct amdgpu_mem_stats; + +/* + * GPUVM handling + */ + +/* Maximum number of PTEs the hardware can write with one command */ +#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF + +/* number of entries in page table */ +#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) + +#define AMDGPU_PTE_VALID (1ULL << 0) +#define AMDGPU_PTE_SYSTEM (1ULL << 1) +#define AMDGPU_PTE_SNOOPED (1ULL << 2) + +/* RV+ */ +#define AMDGPU_PTE_TMZ (1ULL << 3) + +/* VI only */ +#define AMDGPU_PTE_EXECUTABLE (1ULL << 4) + +#define AMDGPU_PTE_READABLE (1ULL << 5) +#define AMDGPU_PTE_WRITEABLE (1ULL << 6) + +#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) + +/* TILED for VEGA10, reserved for older ASICs */ +#define AMDGPU_PTE_PRT (1ULL << 51) + +/* PDE is handled as PTE for VEGA10 */ +#define AMDGPU_PDE_PTE (1ULL << 54) + +#define AMDGPU_PTE_LOG (1ULL << 55) + +/* PTE is handled as PDE for VEGA10 (Translate Further) */ +#define AMDGPU_PTE_TF (1ULL << 56) + +/* MALL noalloc for sienna_cichlid, reserved for older ASICs */ +#define AMDGPU_PTE_NOALLOC (1ULL << 58) + +/* PDE Block Fragment Size for VEGA10 */ +#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) + +/* Flag combination to set no-retry with TF disabled */ +#define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ + AMDGPU_PTE_TF) + +/* Flag combination to set no-retry with TF enabled */ +#define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ + AMDGPU_PTE_PRT) +/* For GFX9 */ +#define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57) +#define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL) +#define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \ + (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ + AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) + +#define AMDGPU_MTYPE_NC 0 +#define AMDGPU_MTYPE_CC 2 + +#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ + | AMDGPU_PTE_SNOOPED \ + | AMDGPU_PTE_EXECUTABLE \ + | AMDGPU_PTE_READABLE \ + | AMDGPU_PTE_WRITEABLE \ + | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) + +/* gfx10 */ +#define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) +#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) +#define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ + (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ + AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) + +/* gfx12 */ +#define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) +#define AMDGPU_PTE_PRT_FLAG(adev) \ + ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) + +#define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) +#define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) +#define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ + (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ + AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) + +#define AMDGPU_PTE_IS_PTE (1ULL << 63) + +/* PDE Block Fragment Size for gfx v12 */ +#define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) +#define AMDGPU_PDE_BFS_FLAG(adev, a) \ + ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) +/* PDE is handled as PTE for gfx v12 */ +#define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) +#define AMDGPU_PDE_PTE_FLAG(adev) \ + ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) + +/* How to program VM fault handling */ +#define AMDGPU_VM_FAULT_STOP_NEVER 0 +#define AMDGPU_VM_FAULT_STOP_FIRST 1 +#define AMDGPU_VM_FAULT_STOP_ALWAYS 2 + +/* How much VRAM be reserved for page tables */ +#define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) + +/* + * max number of VMHUB + * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 + */ +#define AMDGPU_MAX_VMHUBS 13 +#define AMDGPU_GFXHUB_START 0 +#define AMDGPU_MMHUB0_START 8 +#define AMDGPU_MMHUB1_START 12 +#define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) +#define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) +#define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) + +#define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) +#define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) +#define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) + +/* Reserve space at top/bottom of address space for kernel use */ +#define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) +#define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ + << AMDGPU_GPU_PAGE_SHIFT) \ + - AMDGPU_VA_RESERVED_CSA_SIZE) +#define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) +#define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ + - AMDGPU_VA_RESERVED_SEQ64_SIZE) +#define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) +#define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ + - AMDGPU_VA_RESERVED_TRAP_SIZE) +#define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) +#define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ + AMDGPU_VA_RESERVED_SEQ64_SIZE + \ + AMDGPU_VA_RESERVED_CSA_SIZE) + +/* See vm_update_mode */ +#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) +#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) + +/* VMPT level enumerate, and the hiberachy is: + * PDB2->PDB1->PDB0->PTB + */ +enum amdgpu_vm_level { + AMDGPU_VM_PDB2, + AMDGPU_VM_PDB1, + AMDGPU_VM_PDB0, + AMDGPU_VM_PTB +}; + +// /* base structure for tracking BO usage in a VM */ +// struct amdgpu_vm_bo_base { +// /* constant after initialization */ +// struct amdgpu_vm *vm; +// struct amdgpu_bo *bo; + +// /* protected by bo being reserved */ +// struct amdgpu_vm_bo_base *next; + +// /* protected by spinlock */ +// struct list_head vm_status; + +// /* protected by the BO being reserved */ +// bool moved; +// }; + +// /* provided by hw blocks that can write ptes, e.g., sdma */ +// struct amdgpu_vm_pte_funcs { +// /* number of dw to reserve per operation */ +// unsigned copy_pte_num_dw; + +// /* copy pte entries from GART */ +// void (*copy_pte)(struct amdgpu_ib *ib, +// uint64_t pe, uint64_t src, +// unsigned count); + +// /* write pte one entry at a time with addr mapping */ +// void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, +// uint64_t value, unsigned count, +// uint32_t incr); +// /* for linear pte/pde updates without addr mapping */ +// void (*set_pte_pde)(struct amdgpu_ib *ib, +// uint64_t pe, +// uint64_t addr, unsigned count, +// uint32_t incr, uint64_t flags); +// }; + +// struct amdgpu_task_info { +// char process_name[TASK_COMM_LEN]; +// char task_name[TASK_COMM_LEN]; +// pid_t pid; +// pid_t tgid; +// struct kref refcount; +// }; + +// /** +// * struct amdgpu_vm_update_params +// * +// * Encapsulate some VM table update parameters to reduce +// * the number of function parameters +// * +// */ +// struct amdgpu_vm_update_params { + +// /** +// * @adev: amdgpu device we do this update for +// */ +// struct amdgpu_device *adev; + +// /** +// * @vm: optional amdgpu_vm we do this update for +// */ +// struct amdgpu_vm *vm; + +// /** +// * @immediate: if changes should be made immediately +// */ +// bool immediate; + +// /** +// * @unlocked: true if the root BO is not locked +// */ +// bool unlocked; + +// /** +// * @pages_addr: +// * +// * DMA addresses to use for mapping +// */ +// dma_addr_t *pages_addr; + +// /** +// * @job: job to used for hw submission +// */ +// struct amdgpu_job *job; + +// /** +// * @num_dw_left: number of dw left for the IB +// */ +// unsigned int num_dw_left; + +// /** +// * @needs_flush: true whenever we need to invalidate the TLB +// */ +// bool needs_flush; + +// /** +// * @allow_override: true for memory that is not uncached: allows MTYPE +// * to be overridden for NUMA local memory. +// */ +// bool allow_override; + +// /** +// * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush +// */ +// struct list_head tlb_flush_waitlist; +// }; + +// struct amdgpu_vm_update_funcs { +// int (*map_table)(struct amdgpu_bo_vm *bo); +// int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, +// enum amdgpu_sync_mode sync_mode); +// int (*update)(struct amdgpu_vm_update_params *p, +// struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, +// unsigned count, uint32_t incr, uint64_t flags); +// int (*commit)(struct amdgpu_vm_update_params *p, +// struct dma_fence **fence); +// }; + +// struct amdgpu_vm_fault_info { +// /* fault address */ +// uint64_t addr; +// /* fault status register */ +// uint32_t status; +// /* which vmhub? gfxhub, mmhub, etc. */ +// unsigned int vmhub; +// }; + +// struct amdgpu_vm { +// /* tree of virtual addresses mapped */ +// #ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED +// struct rb_root va; +// #else +// struct rb_root_cached va; +// #endif + +// /* Lock to prevent eviction while we are updating page tables +// * use vm_eviction_lock/unlock(vm) +// */ +// struct mutex eviction_lock; +// bool evicting; +// unsigned int saved_flags; + +// /* Lock to protect vm_bo add/del/move on all lists of vm */ +// spinlock_t status_lock; + +// /* Per-VM and PT BOs who needs a validation */ +// struct list_head evicted; + +// /* BOs for user mode queues that need a validation */ +// struct list_head evicted_user; + +// /* PT BOs which relocated and their parent need an update */ +// struct list_head relocated; + +// /* per VM BOs moved, but not yet updated in the PT */ +// struct list_head moved; + +// /* All BOs of this VM not currently in the state machine */ +// struct list_head idle; + +// /* regular invalidated BOs, but not yet updated in the PT */ +// struct list_head invalidated; + +// /* BO mappings freed, but not yet updated in the PT */ +// struct list_head freed; + +// /* BOs which are invalidated, has been updated in the PTs */ +// struct list_head done; + +// /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ +// struct list_head pt_freed; +// struct work_struct pt_free_work; + +// /* contains the page directory */ +// struct amdgpu_vm_bo_base root; +// struct dma_fence *last_update; + +// /* Scheduler entities for page table updates */ +// struct drm_sched_entity immediate; +// struct drm_sched_entity delayed; + +// /* Last finished delayed update */ +// atomic64_t tlb_seq; +// struct dma_fence *last_tlb_flush; +// atomic64_t kfd_last_flushed_seq; +// uint64_t tlb_fence_context; + +// /* How many times we had to re-generate the page tables */ +// uint64_t generation; + +// /* Last unlocked submission to the scheduler entities */ +// struct dma_fence *last_unlocked; + +// unsigned int pasid; +// bool reserved_vmid[AMDGPU_MAX_VMHUBS]; + +// /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ +// bool use_cpu_for_update; + +// /* Functions to use for VM table updates */ +// const struct amdgpu_vm_update_funcs *update_funcs; + +// /* Up to 128 pending retry page faults */ +// DECLARE_KFIFO(faults, u64, 128); + +// /* Points to the KFD process VM info */ +// struct amdkfd_process_info *process_info; + +// /* List node in amdkfd_process_info.vm_list_head */ +// struct list_head vm_list_node; + +// /* Valid while the PD is reserved or fenced */ +// uint64_t pd_phys_addr; + +// /* Some basic info about the task */ +// struct amdgpu_task_info *task_info; + +// /* Store positions of group of BOs */ +// struct ttm_lru_bulk_move lru_bulk_move; +// /* Flag to indicate if VM is used for compute */ +// bool is_compute_context; + +// /* Memory partition number, -1 means any partition */ +// int8_t mem_id; + +// /* cached fault info */ +// struct amdgpu_vm_fault_info fault_info; +// }; + +// struct amdgpu_vm_manager { +// /* Handling of VMIDs */ +// struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; +// unsigned int first_kfd_vmid; +// bool concurrent_flush; + +// /* Handling of VM fences */ +// u64 fence_context; +// unsigned seqno[AMDGPU_MAX_RINGS]; + +// uint64_t max_pfn; +// uint32_t num_level; +// uint32_t block_size; +// uint32_t fragment_size; +// enum amdgpu_vm_level root_level; +// /* vram base address for page table entry */ +// u64 vram_base_offset; +// /* vm pte handling */ +// const struct amdgpu_vm_pte_funcs *vm_pte_funcs; +// struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; +// unsigned vm_pte_num_scheds; +// struct amdgpu_ring *page_fault; + +// /* partial resident texture handling */ +// spinlock_t prt_lock; +// atomic_t num_prt_users; + +// /* controls how VM page tables are updated for Graphics and Compute. +// * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU +// * BIT1[= 0] Compute updated by SDMA [= 1] by CPU +// */ +// int vm_update_mode; + +// /* PASID to VM mapping, will be used in interrupt context to +// * look up VM of a page fault +// */ +// #ifdef HAVE_STRUCT_XARRAY +// struct xarray pasids; +// #else +// struct idr pasid_idr; +// spinlock_t pasid_lock; +// #endif +// /* Global registration of recent page fault information */ +// struct amdgpu_vm_fault_info fault_info; +// }; + +// struct amdgpu_bo_va_mapping; + +// #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) +// #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) +// #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) + +// extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; +// extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; + +// void amdgpu_vm_manager_init(struct amdgpu_device *adev); +// void amdgpu_vm_manager_fini(struct amdgpu_device *adev); + +// int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, +// u32 pasid); + +// long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); +// int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); +// int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); +// void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); +// void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); +// int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, +// unsigned int num_fences); +// bool amdgpu_vm_ready(struct amdgpu_vm *vm); +// uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); +// int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, +// struct ww_acquire_ctx *ticket, +// int (*callback)(void *p, struct amdgpu_bo *bo), +// void *param); +// int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); +// int amdgpu_vm_update_pdes(struct amdgpu_device *adev, +// struct amdgpu_vm *vm, bool immediate); +// int amdgpu_vm_clear_freed(struct amdgpu_device *adev, +// struct amdgpu_vm *vm, +// struct dma_fence **fence); +// int amdgpu_vm_handle_moved(struct amdgpu_device *adev, +// struct amdgpu_vm *vm, +// struct ww_acquire_ctx *ticket); +// int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, +// struct amdgpu_vm *vm, +// uint32_t flush_type, +// uint32_t xcc_mask); +// void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, +// struct amdgpu_vm *vm, struct amdgpu_bo *bo); +// int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, +// bool immediate, bool unlocked, bool flush_tlb, bool allow_override, +// struct dma_resv *resv, uint64_t start, uint64_t last, +// uint64_t flags, uint64_t offset, uint64_t vram_base, +// struct ttm_resource *res, dma_addr_t *pages_addr, +// struct dma_fence **fence); +// int amdgpu_vm_bo_update(struct amdgpu_device *adev, +// struct amdgpu_bo_va *bo_va, +// bool clear); +// bool amdgpu_vm_evictable(struct amdgpu_bo *bo); +// void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, +// struct amdgpu_bo *bo, bool evicted); +// uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); +// struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, +// struct amdgpu_bo *bo); +// struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, +// struct amdgpu_vm *vm, +// struct amdgpu_bo *bo); +// int amdgpu_vm_bo_map(struct amdgpu_device *adev, +// struct amdgpu_bo_va *bo_va, +// uint64_t addr, uint64_t offset, +// uint64_t size, uint64_t flags); +// int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, +// struct amdgpu_bo_va *bo_va, +// uint64_t addr, uint64_t offset, +// uint64_t size, uint64_t flags); +// int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, +// struct amdgpu_bo_va *bo_va, +// uint64_t addr); +// int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, +// struct amdgpu_vm *vm, +// uint64_t saddr, uint64_t size); +// struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, +// uint64_t addr); +// void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); +// void amdgpu_vm_bo_del(struct amdgpu_device *adev, +// struct amdgpu_bo_va *bo_va); +// void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, +// uint32_t fragment_size_default, unsigned max_level, +// unsigned max_bits); +// int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +// bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, +// struct amdgpu_job *job); +// void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); + +// struct amdgpu_task_info * +// amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); + +// struct amdgpu_task_info * +// amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); + +// void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); + +// bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, +// u32 vmid, u32 node_id, uint64_t addr, +// bool write_fault); + +// void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); + +// void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, +// struct amdgpu_vm *vm); +// void amdgpu_vm_get_memory(struct amdgpu_vm *vm, +// struct amdgpu_mem_stats *stats); + +// int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, +// struct amdgpu_bo_vm *vmbo, bool immediate); +// int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, +// int level, bool immediate, struct amdgpu_bo_vm **vmbo, +// int32_t xcp_id); +// void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); + +// int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, +// struct amdgpu_vm_bo_base *entry); +// int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, +// uint64_t start, uint64_t end, +// uint64_t dst, uint64_t flags); +// void amdgpu_vm_pt_free_work(struct work_struct *work); +// void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, +// struct amdgpu_vm_update_params *params); + +// #if defined(CONFIG_DEBUG_FS) +// void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); +// #endif + +// int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); + +// bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); + +// /** +// * amdgpu_vm_tlb_seq - return tlb flush sequence number +// * @vm: the amdgpu_vm structure to query +// * +// * Returns the tlb flush sequence number which indicates that the VM TLBs needs +// * to be invalidated whenever the sequence number change. +// */ +// static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) +// { +// unsigned long flags; +// spinlock_t *lock; + +// /* +// * Workaround to stop racing between the fence signaling and handling +// * the cb. The lock is static after initially setting it up, just make +// * sure that the dma_fence structure isn't freed up. +// */ +// rcu_read_lock(); +// lock = vm->last_tlb_flush->lock; +// rcu_read_unlock(); + +// spin_lock_irqsave(lock, flags); +// spin_unlock_irqrestore(lock, flags); + +// return atomic64_read(&vm->tlb_seq); +// } + +// /* +// * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS +// * happens while holding this lock anywhere to prevent deadlocks when +// * an MMU notifier runs in reclaim-FS context. +// */ +// static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) +// { +// mutex_lock(&vm->eviction_lock); +// vm->saved_flags = memalloc_noreclaim_save(); +// } + +// static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) +// { +// if (mutex_trylock(&vm->eviction_lock)) { +// vm->saved_flags = memalloc_noreclaim_save(); +// return true; +// } +// return false; +// } + +// static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) +// { +// memalloc_noreclaim_restore(vm->saved_flags); +// mutex_unlock(&vm->eviction_lock); +// } + +// void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, +// unsigned int pasid, +// uint64_t addr, +// uint32_t status, +// unsigned int vmhub); +// void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, +// struct amdgpu_vm *vm, +// struct dma_fence **fence); + +#endif diff --git a/extra/amdpci/headers/discovery.h b/extra/amdpci/headers/discovery.h new file mode 100644 index 0000000000..ad38203928 --- /dev/null +++ b/extra/amdpci/headers/discovery.h @@ -0,0 +1,567 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _DISCOVERY_H_ +#define _DISCOVERY_H_ + +#define uint32_t unsigned int +#define uint8_t unsigned char +#define uint16_t unsigned short +#define uint64_t unsigned long long +#define u32 unsigned int +#define u8 unsigned char +#define u16 unsigned short +#define u64 unsigned long long +#define bool unsigned char + +#define PSP_HEADER_SIZE 256 +#define BINARY_SIGNATURE 0x28211407 +#define DISCOVERY_TABLE_SIGNATURE 0x53445049 +#define GC_TABLE_ID 0x4347 +#define HARVEST_TABLE_SIGNATURE 0x56524148 +#define VCN_INFO_TABLE_ID 0x004E4356 +#define MALL_INFO_TABLE_ID 0x4C4C414D +#define NPS_INFO_TABLE_ID 0x0053504E + +typedef enum { + IP_DISCOVERY = 0, + GC, + HARVEST_INFO, + VCN_INFO, + MALL_INFO, + NPS_INFO, + TOTAL_TABLES = 6 +} table; + +#pragma pack(1) + +typedef struct table_info +{ + uint16_t offset; /* Byte offset */ + uint16_t checksum; /* Byte sum of the table */ + uint16_t size; /* Table size */ + uint16_t padding; +} table_info; + +typedef struct binary_header +{ + /* psp structure should go at the top of this structure */ + uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ + uint16_t version_major; + uint16_t version_minor; + uint16_t binary_checksum; /* Byte sum of the binary after this field */ + uint16_t binary_size; /* Binary Size*/ + table_info table_list[TOTAL_TABLES]; +} binary_header; + +typedef struct die_info +{ + uint16_t die_id; + uint16_t die_offset; /* Points to the corresponding die_header structure */ +} die_info; + + +typedef struct ip_discovery_header +{ + uint32_t signature; /* Table Signature */ + uint16_t version; /* Table Version */ + uint16_t size; /* Table Size */ + uint32_t id; /* Table ID */ + uint16_t num_dies; /* Number of Dies */ + die_info die_info[16]; /* list die information for up to 16 dies */ + union { + uint16_t padding[1]; /* version <= 3 */ + struct { /* version == 4 */ + uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */ + uint8_t reserved : 7; + uint8_t reserved2; + }; + }; +} ip_discovery_header; + +typedef struct ip +{ + uint16_t hw_id; /* Hardware ID */ + uint8_t number_instance; /* instance of the IP */ + uint8_t num_base_address; /* Number of Base Addresses */ + uint8_t major; /* HCID Major */ + uint8_t minor; /* HCID Minor */ + uint8_t revision; /* HCID Revision */ +#if defined(__BIG_ENDIAN) + uint8_t reserved : 4; /* Placeholder field */ + uint8_t harvest : 4; /* Harvest */ +#else + uint8_t harvest : 4; /* Harvest */ + uint8_t reserved : 4; /* Placeholder field */ +#endif + uint32_t base_address[1]; /* variable number of Addresses */ +} ip; + +typedef struct ip_v3 +{ + uint16_t hw_id; /* Hardware ID */ + uint8_t instance_number; /* Instance number for the IP */ + uint8_t num_base_address; /* Number of base addresses*/ + uint8_t major; /* Hardware ID.major version */ + uint8_t minor; /* Hardware ID.minor version */ + uint8_t revision; /* Hardware ID.revision version */ +#if defined(__BIG_ENDIAN) + uint8_t variant : 4; /* HW variant */ + uint8_t sub_revision : 4; /* HCID Sub-Revision */ +#else + uint8_t sub_revision : 4; /* HCID Sub-Revision */ + uint8_t variant : 4; /* HW variant */ +#endif + uint32_t base_address[1]; /* Base Address list. Corresponds to the num_base_address field*/ +} ip_v3; + +typedef struct ip_v4 { + uint16_t hw_id; /* Hardware ID */ + uint8_t instance_number; /* Instance number for the IP */ + uint8_t num_base_address; /* Number of base addresses*/ + uint8_t major; /* Hardware ID.major version */ + uint8_t minor; /* Hardware ID.minor version */ + uint8_t revision; /* Hardware ID.revision version */ +#if defined(LITTLEENDIAN_CPU) + uint8_t sub_revision : 4; /* HCID Sub-Revision */ + uint8_t variant : 4; /* HW variant */ +#elif defined(BIGENDIAN_CPU) + uint8_t variant : 4; /* HW variant */ + uint8_t sub_revision : 4; /* HCID Sub-Revision */ +#endif + uint64_t base_address_64[1]; +} ip_v4; + +typedef struct die_header +{ + uint16_t die_id; + uint16_t num_ips; +} die_header; + +typedef struct ip_structure +{ + ip_discovery_header* header; + struct die + { + die_header *die_header; + union + { + ip *ip_list; + ip_v3 *ip_v3_list; + ip_v4 *ip_v4_list; + }; /* IP list. Variable size*/ + } die; +} ip_structure; + +struct gpu_info_header { + uint32_t table_id; /* table ID */ + uint16_t version_major; /* table version */ + uint16_t version_minor; /* table version */ + uint32_t size; /* size of the entire header+data in bytes */ +}; + +struct gc_info_v1_0 { + struct gpu_info_header header; + + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; +}; + +struct gc_info_v1_1 { + struct gpu_info_header header; + + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; +}; + +struct gc_info_v1_2 { + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; +}; + +struct gc_info_v2_0 { + struct gpu_info_header header; + + uint32_t gc_num_se; + uint32_t gc_num_cu_per_sh; + uint32_t gc_num_sh_per_se; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_tccs; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_packer_per_sc; +}; + +struct gc_info_v2_1 { + struct gpu_info_header header; + + uint32_t gc_num_se; + uint32_t gc_num_cu_per_sh; + uint32_t gc_num_sh_per_se; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_tccs; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_packer_per_sc; + /* new for v2_1 */ + uint32_t gc_num_tcp_per_sh; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_cu_per_sqc; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_tcc_size; +}; + +typedef struct harvest_info_header { + uint32_t signature; /* Table Signature */ + uint32_t version; /* Table Version */ +} harvest_info_header; + +typedef struct harvest_info { + uint16_t hw_id; /* Hardware ID */ + uint8_t number_instance; /* Instance of the IP */ + uint8_t reserved; /* Reserved for alignment */ +} harvest_info; + +typedef struct harvest_table { + harvest_info_header header; + harvest_info list[32]; +} harvest_table; + +struct mall_info_header { + uint32_t table_id; /* table ID */ + uint16_t version_major; /* table version */ + uint16_t version_minor; /* table version */ + uint32_t size_bytes; /* size of the entire header+data in bytes */ +}; + +struct mall_info_v1_0 { + struct mall_info_header header; + uint32_t mall_size_per_m; + uint32_t m_s_present; + uint32_t m_half_use; + uint32_t m_mall_config; + uint32_t reserved[5]; +}; + +struct mall_info_v2_0 { + struct mall_info_header header; + uint32_t mall_size_per_umc; + uint32_t reserved[8]; +}; + +#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4 + +struct vcn_info_header { + uint32_t table_id; /* table ID */ + uint16_t version_major; /* table version */ + uint16_t version_minor; /* table version */ + uint32_t size_bytes; /* size of the entire header+data in bytes */ +}; + +struct vcn_instance_info_v1_0 +{ + uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/ + union _fuse_data { + struct { + uint32_t av1_disabled : 1; + uint32_t vp9_disabled : 1; + uint32_t hevc_disabled : 1; + uint32_t h264_disabled : 1; + uint32_t reserved : 28; + } bits; + uint32_t all_bits; + } fuse_data; + uint32_t reserved[2]; +}; + +struct vcn_info_v1_0 { + struct vcn_info_header header; + uint32_t num_of_instances; /* number of entries used in instance_info below*/ + struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES]; + uint32_t reserved[4]; +}; + +#define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12 + +struct nps_info_header { + uint32_t table_id; /* table ID */ + uint16_t version_major; /* table version */ + uint16_t version_minor; /* table version */ + uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */ +}; + +struct nps_instance_info_v1_0 { + uint64_t base_address; + uint64_t limit_address; +}; + +struct nps_info_v1_0 { + struct nps_info_header header; + uint32_t nps_type; + uint32_t count; + struct nps_instance_info_v1_0 + instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES]; +}; + +enum amd_hw_ip_block_type { + GC_HWIP = 1, + HDP_HWIP, + SDMA0_HWIP, + SDMA1_HWIP, + SDMA2_HWIP, + SDMA3_HWIP, + SDMA4_HWIP, + SDMA5_HWIP, + SDMA6_HWIP, + SDMA7_HWIP, + LSDMA_HWIP, + MMHUB_HWIP, + ATHUB_HWIP, + NBIO_HWIP, + MP0_HWIP, + MP1_HWIP, + UVD_HWIP, + VCN_HWIP = UVD_HWIP, + JPEG_HWIP = VCN_HWIP, + VCN1_HWIP, + VCE_HWIP, + VPE_HWIP, + DF_HWIP, + DCE_HWIP, + OSSSYS_HWIP, + SMUIO_HWIP, + PWR_HWIP, + NBIF_HWIP, + THM_HWIP, + CLK_HWIP, + UMC_HWIP, + RSMU_HWIP, + XGMI_HWIP, + DCI_HWIP, + PCIE_HWIP, + ISP_HWIP, + MAX_HWIP +}; + +#define HWIP_MAX_INSTANCE 44 + +#define HW_ID_MAX 300 + +// HW ID +#define MP1_HWID 1 +#define MP2_HWID 2 +#define THM_HWID 3 +#define SMUIO_HWID 4 +#define FUSE_HWID 5 +#define CLKA_HWID 6 +#define PWR_HWID 10 +#define GC_HWID 11 +#define UVD_HWID 12 +#define VCN_HWID UVD_HWID +#define AUDIO_AZ_HWID 13 +#define ACP_HWID 14 +#define DCI_HWID 15 +#define DMU_HWID 271 +#define DCO_HWID 16 +#define DIO_HWID 272 +#define XDMA_HWID 17 +#define DCEAZ_HWID 18 +#define DAZ_HWID 274 +#define SDPMUX_HWID 19 +#define NTB_HWID 20 +#define VPE_HWID 21 +#define IOHC_HWID 24 +#define L2IMU_HWID 28 +#define VCE_HWID 32 +#define MMHUB_HWID 34 +#define ATHUB_HWID 35 +#define DBGU_NBIO_HWID 36 +#define DFX_HWID 37 +#define DBGU0_HWID 38 +#define DBGU1_HWID 39 +#define OSSSYS_HWID 40 +#define HDP_HWID 41 +#define SDMA0_HWID 42 +#define SDMA1_HWID 43 +#define ISP_HWID 44 +#define DBGU_IO_HWID 45 +#define DF_HWID 46 +#define CLKB_HWID 47 +#define FCH_HWID 48 +#define DFX_DAP_HWID 49 +#define L1IMU_PCIE_HWID 50 +#define L1IMU_NBIF_HWID 51 +#define L1IMU_IOAGR_HWID 52 +#define L1IMU3_HWID 53 +#define L1IMU4_HWID 54 +#define L1IMU5_HWID 55 +#define L1IMU6_HWID 56 +#define L1IMU7_HWID 57 +#define L1IMU8_HWID 58 +#define L1IMU9_HWID 59 +#define L1IMU10_HWID 60 +#define L1IMU11_HWID 61 +#define L1IMU12_HWID 62 +#define L1IMU13_HWID 63 +#define L1IMU14_HWID 64 +#define L1IMU15_HWID 65 +#define WAFLC_HWID 66 +#define FCH_USB_PD_HWID 67 +#define SDMA2_HWID 68 +#define SDMA3_HWID 69 +#define PCIE_HWID 70 +#define PCS_HWID 80 +#define DDCL_HWID 89 +#define SST_HWID 90 +#define LSDMA_HWID 91 +#define IOAGR_HWID 100 +#define NBIF_HWID 108 +#define IOAPIC_HWID 124 +#define SYSTEMHUB_HWID 128 +#define NTBCCP_HWID 144 +#define UMC_HWID 150 +#define SATA_HWID 168 +#define USB_HWID 170 +#define CCXSEC_HWID 176 +#define XGMI_HWID 200 +#define XGBE_HWID 216 +#define MP0_HWID 255 + +static int hw_id_map[MAX_HWIP] = { + [GC_HWIP] = GC_HWID, + [HDP_HWIP] = HDP_HWID, + [SDMA0_HWIP] = SDMA0_HWID, + [SDMA1_HWIP] = SDMA1_HWID, + [SDMA2_HWIP] = SDMA2_HWID, + [SDMA3_HWIP] = SDMA3_HWID, + [LSDMA_HWIP] = LSDMA_HWID, + [MMHUB_HWIP] = MMHUB_HWID, + [ATHUB_HWIP] = ATHUB_HWID, + [NBIO_HWIP] = NBIF_HWID, + [MP0_HWIP] = MP0_HWID, + [MP1_HWIP] = MP1_HWID, + [UVD_HWIP] = UVD_HWID, + [VCE_HWIP] = VCE_HWID, + [DF_HWIP] = DF_HWID, + [DCE_HWIP] = DMU_HWID, + [OSSSYS_HWIP] = OSSSYS_HWID, + [SMUIO_HWIP] = SMUIO_HWID, + [PWR_HWIP] = PWR_HWID, + [NBIF_HWIP] = NBIF_HWID, + [THM_HWIP] = THM_HWID, + [CLK_HWIP] = CLKA_HWID, + [UMC_HWIP] = UMC_HWID, + [XGMI_HWIP] = XGMI_HWID, + [DCI_HWIP] = DCI_HWID, + [PCIE_HWIP] = PCIE_HWID, + [VPE_HWIP] = VPE_HWID, + [ISP_HWIP] = ISP_HWID, +}; + +#endif diff --git a/extra/amdpci/headers/gc_11_0_0_offset.h b/extra/amdpci/headers/gc_11_0_0_offset.h new file mode 100644 index 0000000000..a3bcdf6320 --- /dev/null +++ b/extra/amdpci/headers/gc_11_0_0_offset.h @@ -0,0 +1,11685 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_11_0_0_OFFSET_HEADER +#define _gc_11_0_0_OFFSET_HEADER + + + +// addressBlock: gc_sdma0_sdma0dec +// base address: 0x4980 +#define regSDMA0_DEC_START 0x0000 +#define regSDMA0_DEC_START_BASE_IDX 0 +#define regSDMA0_F32_MISC_CNTL 0x000b +#define regSDMA0_F32_MISC_CNTL_BASE_IDX 0 +#define regSDMA0_GLOBAL_TIMESTAMP_LO 0x000f +#define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA0_GLOBAL_TIMESTAMP_HI 0x0010 +#define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA0_POWER_CNTL 0x001a +#define regSDMA0_POWER_CNTL_BASE_IDX 0 +#define regSDMA0_CNTL 0x001c +#define regSDMA0_CNTL_BASE_IDX 0 +#define regSDMA0_CHICKEN_BITS 0x001d +#define regSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA0_GB_ADDR_CONFIG 0x001e +#define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA0_RB_RPTR_FETCH 0x0020 +#define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA0_RB_RPTR_FETCH_HI 0x0021 +#define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0022 +#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA0_IB_OFFSET_FETCH 0x0023 +#define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA0_PROGRAM 0x0024 +#define regSDMA0_PROGRAM_BASE_IDX 0 +#define regSDMA0_STATUS_REG 0x0025 +#define regSDMA0_STATUS_REG_BASE_IDX 0 +#define regSDMA0_STATUS1_REG 0x0026 +#define regSDMA0_STATUS1_REG_BASE_IDX 0 +#define regSDMA0_CNTL1 0x0027 +#define regSDMA0_CNTL1_BASE_IDX 0 +#define regSDMA0_HBM_PAGE_CONFIG 0x0028 +#define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA0_UCODE_CHECKSUM 0x0029 +#define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA0_FREEZE 0x002b +#define regSDMA0_FREEZE_BASE_IDX 0 +#define regSDMA0_PROCESS_QUANTUM0 0x002c +#define regSDMA0_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA0_PROCESS_QUANTUM1 0x002d +#define regSDMA0_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA0_WATCHDOG_CNTL 0x002e +#define regSDMA0_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE_STATUS0 0x002f +#define regSDMA0_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA0_EDC_CONFIG 0x0032 +#define regSDMA0_EDC_CONFIG_BASE_IDX 0 +#define regSDMA0_BA_THRESHOLD 0x0033 +#define regSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA0_ID 0x0034 +#define regSDMA0_ID_BASE_IDX 0 +#define regSDMA0_VERSION 0x0035 +#define regSDMA0_VERSION_BASE_IDX 0 +#define regSDMA0_EDC_COUNTER 0x0036 +#define regSDMA0_EDC_COUNTER_BASE_IDX 0 +#define regSDMA0_EDC_COUNTER_CLEAR 0x0037 +#define regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define regSDMA0_STATUS2_REG 0x0038 +#define regSDMA0_STATUS2_REG_BASE_IDX 0 +#define regSDMA0_ATOMIC_CNTL 0x0039 +#define regSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA0_ATOMIC_PREOP_LO 0x003a +#define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA0_ATOMIC_PREOP_HI 0x003b +#define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA0_UTCL1_CNTL 0x003c +#define regSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA0_UTCL1_WATERMK 0x003d +#define regSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA0_UTCL1_TIMEOUT 0x003e +#define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA0_UTCL1_PAGE 0x003f +#define regSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_STATUS 0x0040 +#define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_STATUS 0x0041 +#define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA0_UTCL1_INV0 0x0042 +#define regSDMA0_UTCL1_INV0_BASE_IDX 0 +#define regSDMA0_UTCL1_INV1 0x0043 +#define regSDMA0_UTCL1_INV1_BASE_IDX 0 +#define regSDMA0_UTCL1_INV2 0x0044 +#define regSDMA0_UTCL1_INV2_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_XNACK0 0x0045 +#define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_XNACK1 0x0046 +#define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_XNACK0 0x0047 +#define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_XNACK1 0x0048 +#define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA0_RELAX_ORDERING_LUT 0x004a +#define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA0_CHICKEN_BITS_2 0x004b +#define regSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA0_STATUS3_REG 0x004c +#define regSDMA0_STATUS3_REG_BASE_IDX 0 +#define regSDMA0_PHYSICAL_ADDR_LO 0x004d +#define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_PHYSICAL_ADDR_HI 0x004e +#define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_GLOBAL_QUANTUM 0x004f +#define regSDMA0_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA0_ERROR_LOG 0x0050 +#define regSDMA0_ERROR_LOG_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG0 0x0051 +#define regSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG1 0x0052 +#define regSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG2 0x0053 +#define regSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG3 0x0054 +#define regSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA0_F32_COUNTER 0x0055 +#define regSDMA0_F32_COUNTER_BASE_IDX 0 +#define regSDMA0_CRD_CNTL 0x005b +#define regSDMA0_CRD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC_CGCG_CTRL 0x005c +#define regSDMA0_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA0_AQL_STATUS 0x005f +#define regSDMA0_AQL_STATUS_BASE_IDX 0 +#define regSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA0_TLBI_GCR_CNTL 0x0062 +#define regSDMA0_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA0_TILING_CONFIG 0x0063 +#define regSDMA0_TILING_CONFIG_BASE_IDX 0 +#define regSDMA0_INT_STATUS 0x0070 +#define regSDMA0_INT_STATUS_BASE_IDX 0 +#define regSDMA0_HOLE_ADDR_LO 0x0072 +#define regSDMA0_HOLE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_HOLE_ADDR_HI 0x0073 +#define regSDMA0_HOLE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_CLOCK_GATING_STATUS 0x0075 +#define regSDMA0_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA0_STATUS4_REG 0x0076 +#define regSDMA0_STATUS4_REG_BASE_IDX 0 +#define regSDMA0_SCRATCH_RAM_DATA 0x0077 +#define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA0_SCRATCH_RAM_ADDR 0x0078 +#define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA0_TIMESTAMP_CNTL 0x0079 +#define regSDMA0_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA0_STATUS5_REG 0x007a +#define regSDMA0_STATUS5_REG_BASE_IDX 0 +#define regSDMA0_QUEUE_RESET_REQ 0x007b +#define regSDMA0_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA0_STATUS6_REG 0x007c +#define regSDMA0_STATUS6_REG_BASE_IDX 0 +#define regSDMA0_UCODE1_CHECKSUM 0x007d +#define regSDMA0_UCODE1_CHECKSUM_BASE_IDX 0 +#define regSDMA0_CE_CTRL 0x007e +#define regSDMA0_CE_CTRL_BASE_IDX 0 +#define regSDMA0_FED_STATUS 0x007f +#define regSDMA0_FED_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_CNTL 0x0080 +#define regSDMA0_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_BASE 0x0081 +#define regSDMA0_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_BASE_HI 0x0082 +#define regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR 0x0083 +#define regSDMA0_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR_HI 0x0084 +#define regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR 0x0085 +#define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR_HI 0x0086 +#define regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI 0x0088 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO 0x0089 +#define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_CNTL 0x008a +#define regSDMA0_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_RPTR 0x008b +#define regSDMA0_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_OFFSET 0x008c +#define regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_BASE_LO 0x008d +#define regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_BASE_HI 0x008e +#define regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_SIZE 0x008f +#define regSDMA0_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE0_SKIP_CNTL 0x0090 +#define regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_CONTEXT_STATUS 0x0091 +#define regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE0_DOORBELL 0x0092 +#define regSDMA0_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE0_DOORBELL_LOG 0x00a9 +#define regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE0_DOORBELL_OFFSET 0x00ab +#define regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE0_CSA_ADDR_LO 0x00ac +#define regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_CSA_ADDR_HI 0x00ad +#define regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_SCHEDULE_CNTL 0x00ae +#define regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_IB_SUB_REMAIN 0x00af +#define regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE0_PREEMPT 0x00b0 +#define regSDMA0_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE0_DUMMY_REG 0x00b1 +#define regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_AQL_CNTL 0x00b4 +#define regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE0_MINOR_PTR_UPDATE 0x00b5 +#define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE0_RB_PREEMPT 0x00b6 +#define regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00c0 +#define regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA1 0x00c1 +#define regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA2 0x00c2 +#define regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA3 0x00c3 +#define regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA4 0x00c4 +#define regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA5 0x00c5 +#define regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA6 0x00c6 +#define regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA7 0x00c7 +#define regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA8 0x00c8 +#define regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA9 0x00c9 +#define regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_DATA10 0x00ca +#define regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE0_MIDCMD_CNTL 0x00cb +#define regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_CNTL 0x00d8 +#define regSDMA0_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_BASE 0x00d9 +#define regSDMA0_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_BASE_HI 0x00da +#define regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR 0x00db +#define regSDMA0_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR_HI 0x00dc +#define regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR 0x00dd +#define regSDMA0_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR_HI 0x00de +#define regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI 0x00e0 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO 0x00e1 +#define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_CNTL 0x00e2 +#define regSDMA0_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_RPTR 0x00e3 +#define regSDMA0_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_OFFSET 0x00e4 +#define regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_BASE_LO 0x00e5 +#define regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_BASE_HI 0x00e6 +#define regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_SIZE 0x00e7 +#define regSDMA0_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE1_SKIP_CNTL 0x00e8 +#define regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_CONTEXT_STATUS 0x00e9 +#define regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE1_DOORBELL 0x00ea +#define regSDMA0_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE1_DOORBELL_LOG 0x0101 +#define regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE1_DOORBELL_OFFSET 0x0103 +#define regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE1_CSA_ADDR_LO 0x0104 +#define regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_CSA_ADDR_HI 0x0105 +#define regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_SCHEDULE_CNTL 0x0106 +#define regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_IB_SUB_REMAIN 0x0107 +#define regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE1_PREEMPT 0x0108 +#define regSDMA0_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE1_DUMMY_REG 0x0109 +#define regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x010a +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x010b +#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_AQL_CNTL 0x010c +#define regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE1_MINOR_PTR_UPDATE 0x010d +#define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE1_RB_PREEMPT 0x010e +#define regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA0 0x0118 +#define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA1 0x0119 +#define regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA2 0x011a +#define regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA3 0x011b +#define regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA4 0x011c +#define regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA5 0x011d +#define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA6 0x011e +#define regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA7 0x011f +#define regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA8 0x0120 +#define regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA9 0x0121 +#define regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_DATA10 0x0122 +#define regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE1_MIDCMD_CNTL 0x0123 +#define regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_CNTL 0x0130 +#define regSDMA0_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_BASE 0x0131 +#define regSDMA0_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_BASE_HI 0x0132 +#define regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR 0x0133 +#define regSDMA0_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR_HI 0x0134 +#define regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR 0x0135 +#define regSDMA0_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR_HI 0x0136 +#define regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI 0x0138 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO 0x0139 +#define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_CNTL 0x013a +#define regSDMA0_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_RPTR 0x013b +#define regSDMA0_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_OFFSET 0x013c +#define regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_BASE_LO 0x013d +#define regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_BASE_HI 0x013e +#define regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_SIZE 0x013f +#define regSDMA0_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE2_SKIP_CNTL 0x0140 +#define regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_CONTEXT_STATUS 0x0141 +#define regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE2_DOORBELL 0x0142 +#define regSDMA0_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE2_DOORBELL_LOG 0x0159 +#define regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE2_DOORBELL_OFFSET 0x015b +#define regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE2_CSA_ADDR_LO 0x015c +#define regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_CSA_ADDR_HI 0x015d +#define regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_SCHEDULE_CNTL 0x015e +#define regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_IB_SUB_REMAIN 0x015f +#define regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE2_PREEMPT 0x0160 +#define regSDMA0_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE2_DUMMY_REG 0x0161 +#define regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0162 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0163 +#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_AQL_CNTL 0x0164 +#define regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE2_MINOR_PTR_UPDATE 0x0165 +#define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE2_RB_PREEMPT 0x0166 +#define regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA0 0x0170 +#define regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA1 0x0171 +#define regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA2 0x0172 +#define regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA3 0x0173 +#define regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA4 0x0174 +#define regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA5 0x0175 +#define regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA6 0x0176 +#define regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA7 0x0177 +#define regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA8 0x0178 +#define regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA9 0x0179 +#define regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_DATA10 0x017a +#define regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE2_MIDCMD_CNTL 0x017b +#define regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_CNTL 0x0188 +#define regSDMA0_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_BASE 0x0189 +#define regSDMA0_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_BASE_HI 0x018a +#define regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR 0x018b +#define regSDMA0_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR_HI 0x018c +#define regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR 0x018d +#define regSDMA0_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR_HI 0x018e +#define regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI 0x0190 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO 0x0191 +#define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_CNTL 0x0192 +#define regSDMA0_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_RPTR 0x0193 +#define regSDMA0_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_OFFSET 0x0194 +#define regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_BASE_LO 0x0195 +#define regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_BASE_HI 0x0196 +#define regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_SIZE 0x0197 +#define regSDMA0_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE3_SKIP_CNTL 0x0198 +#define regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_CONTEXT_STATUS 0x0199 +#define regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE3_DOORBELL 0x019a +#define regSDMA0_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE3_DOORBELL_LOG 0x01b1 +#define regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE3_DOORBELL_OFFSET 0x01b3 +#define regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE3_CSA_ADDR_LO 0x01b4 +#define regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_CSA_ADDR_HI 0x01b5 +#define regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_SCHEDULE_CNTL 0x01b6 +#define regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_IB_SUB_REMAIN 0x01b7 +#define regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE3_PREEMPT 0x01b8 +#define regSDMA0_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE3_DUMMY_REG 0x01b9 +#define regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x01ba +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x01bb +#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_AQL_CNTL 0x01bc +#define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE3_MINOR_PTR_UPDATE 0x01bd +#define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE3_RB_PREEMPT 0x01be +#define regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA0 0x01c8 +#define regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA1 0x01c9 +#define regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA2 0x01ca +#define regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA3 0x01cb +#define regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA4 0x01cc +#define regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA5 0x01cd +#define regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA6 0x01ce +#define regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA7 0x01cf +#define regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA8 0x01d0 +#define regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA9 0x01d1 +#define regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_DATA10 0x01d2 +#define regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE3_MIDCMD_CNTL 0x01d3 +#define regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_CNTL 0x01e0 +#define regSDMA0_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_BASE 0x01e1 +#define regSDMA0_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_BASE_HI 0x01e2 +#define regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR 0x01e3 +#define regSDMA0_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR_HI 0x01e4 +#define regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR 0x01e5 +#define regSDMA0_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR_HI 0x01e6 +#define regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI 0x01e8 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO 0x01e9 +#define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_CNTL 0x01ea +#define regSDMA0_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_RPTR 0x01eb +#define regSDMA0_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_OFFSET 0x01ec +#define regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_BASE_LO 0x01ed +#define regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_BASE_HI 0x01ee +#define regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_SIZE 0x01ef +#define regSDMA0_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE4_SKIP_CNTL 0x01f0 +#define regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_CONTEXT_STATUS 0x01f1 +#define regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE4_DOORBELL 0x01f2 +#define regSDMA0_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE4_DOORBELL_LOG 0x0209 +#define regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE4_DOORBELL_OFFSET 0x020b +#define regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE4_CSA_ADDR_LO 0x020c +#define regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_CSA_ADDR_HI 0x020d +#define regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_SCHEDULE_CNTL 0x020e +#define regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_IB_SUB_REMAIN 0x020f +#define regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE4_PREEMPT 0x0210 +#define regSDMA0_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE4_DUMMY_REG 0x0211 +#define regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0212 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0213 +#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_AQL_CNTL 0x0214 +#define regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE4_MINOR_PTR_UPDATE 0x0215 +#define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE4_RB_PREEMPT 0x0216 +#define regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA0 0x0220 +#define regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA1 0x0221 +#define regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA2 0x0222 +#define regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA3 0x0223 +#define regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA4 0x0224 +#define regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA5 0x0225 +#define regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA6 0x0226 +#define regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA7 0x0227 +#define regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA8 0x0228 +#define regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA9 0x0229 +#define regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_DATA10 0x022a +#define regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE4_MIDCMD_CNTL 0x022b +#define regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_CNTL 0x0238 +#define regSDMA0_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_BASE 0x0239 +#define regSDMA0_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_BASE_HI 0x023a +#define regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR 0x023b +#define regSDMA0_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR_HI 0x023c +#define regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR 0x023d +#define regSDMA0_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR_HI 0x023e +#define regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI 0x0240 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO 0x0241 +#define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_CNTL 0x0242 +#define regSDMA0_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_RPTR 0x0243 +#define regSDMA0_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_OFFSET 0x0244 +#define regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_BASE_LO 0x0245 +#define regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_BASE_HI 0x0246 +#define regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_SIZE 0x0247 +#define regSDMA0_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE5_SKIP_CNTL 0x0248 +#define regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_CONTEXT_STATUS 0x0249 +#define regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE5_DOORBELL 0x024a +#define regSDMA0_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE5_DOORBELL_LOG 0x0261 +#define regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE5_DOORBELL_OFFSET 0x0263 +#define regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE5_CSA_ADDR_LO 0x0264 +#define regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_CSA_ADDR_HI 0x0265 +#define regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_SCHEDULE_CNTL 0x0266 +#define regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_IB_SUB_REMAIN 0x0267 +#define regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE5_PREEMPT 0x0268 +#define regSDMA0_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE5_DUMMY_REG 0x0269 +#define regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x026a +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x026b +#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_AQL_CNTL 0x026c +#define regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE5_MINOR_PTR_UPDATE 0x026d +#define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE5_RB_PREEMPT 0x026e +#define regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA0 0x0278 +#define regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA1 0x0279 +#define regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA2 0x027a +#define regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA3 0x027b +#define regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA4 0x027c +#define regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA5 0x027d +#define regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA6 0x027e +#define regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA7 0x027f +#define regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA8 0x0280 +#define regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA9 0x0281 +#define regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_DATA10 0x0282 +#define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE5_MIDCMD_CNTL 0x0283 +#define regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_CNTL 0x0290 +#define regSDMA0_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_BASE 0x0291 +#define regSDMA0_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_BASE_HI 0x0292 +#define regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR 0x0293 +#define regSDMA0_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR_HI 0x0294 +#define regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR 0x0295 +#define regSDMA0_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR_HI 0x0296 +#define regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI 0x0298 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO 0x0299 +#define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_CNTL 0x029a +#define regSDMA0_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_RPTR 0x029b +#define regSDMA0_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_OFFSET 0x029c +#define regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_BASE_LO 0x029d +#define regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_BASE_HI 0x029e +#define regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_SIZE 0x029f +#define regSDMA0_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE6_SKIP_CNTL 0x02a0 +#define regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_CONTEXT_STATUS 0x02a1 +#define regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE6_DOORBELL 0x02a2 +#define regSDMA0_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE6_DOORBELL_LOG 0x02b9 +#define regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE6_DOORBELL_OFFSET 0x02bb +#define regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE6_CSA_ADDR_LO 0x02bc +#define regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_CSA_ADDR_HI 0x02bd +#define regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_SCHEDULE_CNTL 0x02be +#define regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_IB_SUB_REMAIN 0x02bf +#define regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE6_PREEMPT 0x02c0 +#define regSDMA0_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE6_DUMMY_REG 0x02c1 +#define regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_AQL_CNTL 0x02c4 +#define regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE6_MINOR_PTR_UPDATE 0x02c5 +#define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE6_RB_PREEMPT 0x02c6 +#define regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA0 0x02d0 +#define regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA1 0x02d1 +#define regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA2 0x02d2 +#define regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA3 0x02d3 +#define regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA4 0x02d4 +#define regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA5 0x02d5 +#define regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA6 0x02d6 +#define regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA7 0x02d7 +#define regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA8 0x02d8 +#define regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA9 0x02d9 +#define regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_DATA10 0x02da +#define regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE6_MIDCMD_CNTL 0x02db +#define regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_CNTL 0x02e8 +#define regSDMA0_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_BASE 0x02e9 +#define regSDMA0_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_BASE_HI 0x02ea +#define regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR 0x02eb +#define regSDMA0_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR_HI 0x02ec +#define regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR 0x02ed +#define regSDMA0_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR_HI 0x02ee +#define regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI 0x02f0 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO 0x02f1 +#define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_CNTL 0x02f2 +#define regSDMA0_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_RPTR 0x02f3 +#define regSDMA0_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_OFFSET 0x02f4 +#define regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_BASE_LO 0x02f5 +#define regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_BASE_HI 0x02f6 +#define regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_SIZE 0x02f7 +#define regSDMA0_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA0_QUEUE7_SKIP_CNTL 0x02f8 +#define regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_CONTEXT_STATUS 0x02f9 +#define regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_QUEUE7_DOORBELL 0x02fa +#define regSDMA0_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA0_QUEUE7_DOORBELL_LOG 0x0311 +#define regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_QUEUE7_DOORBELL_OFFSET 0x0313 +#define regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_QUEUE7_CSA_ADDR_LO 0x0314 +#define regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_CSA_ADDR_HI 0x0315 +#define regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_SCHEDULE_CNTL 0x0316 +#define regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_IB_SUB_REMAIN 0x0317 +#define regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_QUEUE7_PREEMPT 0x0318 +#define regSDMA0_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE7_DUMMY_REG 0x0319 +#define regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x031a +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x031b +#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_AQL_CNTL 0x031c +#define regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_QUEUE7_MINOR_PTR_UPDATE 0x031d +#define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_QUEUE7_RB_PREEMPT 0x031e +#define regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA0 0x0328 +#define regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA1 0x0329 +#define regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA2 0x032a +#define regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA3 0x032b +#define regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA4 0x032c +#define regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA5 0x032d +#define regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA6 0x032e +#define regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA7 0x032f +#define regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA8 0x0330 +#define regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA9 0x0331 +#define regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_DATA10 0x0332 +#define regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_QUEUE7_MIDCMD_CNTL 0x0333 +#define regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: gc_sdma0_sdma1dec +// base address: 0x6180 +#define regSDMA1_DEC_START 0x0600 +#define regSDMA1_DEC_START_BASE_IDX 0 +#define regSDMA1_F32_MISC_CNTL 0x060b +#define regSDMA1_F32_MISC_CNTL_BASE_IDX 0 +#define regSDMA1_GLOBAL_TIMESTAMP_LO 0x060f +#define regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA1_GLOBAL_TIMESTAMP_HI 0x0610 +#define regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA1_POWER_CNTL 0x061a +#define regSDMA1_POWER_CNTL_BASE_IDX 0 +#define regSDMA1_CNTL 0x061c +#define regSDMA1_CNTL_BASE_IDX 0 +#define regSDMA1_CHICKEN_BITS 0x061d +#define regSDMA1_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA1_GB_ADDR_CONFIG 0x061e +#define regSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA1_GB_ADDR_CONFIG_READ 0x061f +#define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA1_RB_RPTR_FETCH 0x0620 +#define regSDMA1_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA1_RB_RPTR_FETCH_HI 0x0621 +#define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0622 +#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA1_IB_OFFSET_FETCH 0x0623 +#define regSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA1_PROGRAM 0x0624 +#define regSDMA1_PROGRAM_BASE_IDX 0 +#define regSDMA1_STATUS_REG 0x0625 +#define regSDMA1_STATUS_REG_BASE_IDX 0 +#define regSDMA1_STATUS1_REG 0x0626 +#define regSDMA1_STATUS1_REG_BASE_IDX 0 +#define regSDMA1_CNTL1 0x0627 +#define regSDMA1_CNTL1_BASE_IDX 0 +#define regSDMA1_HBM_PAGE_CONFIG 0x0628 +#define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA1_UCODE_CHECKSUM 0x0629 +#define regSDMA1_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA1_FREEZE 0x062b +#define regSDMA1_FREEZE_BASE_IDX 0 +#define regSDMA1_PROCESS_QUANTUM0 0x062c +#define regSDMA1_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA1_PROCESS_QUANTUM1 0x062d +#define regSDMA1_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA1_WATCHDOG_CNTL 0x062e +#define regSDMA1_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE_STATUS0 0x062f +#define regSDMA1_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA1_EDC_CONFIG 0x0632 +#define regSDMA1_EDC_CONFIG_BASE_IDX 0 +#define regSDMA1_BA_THRESHOLD 0x0633 +#define regSDMA1_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA1_ID 0x0634 +#define regSDMA1_ID_BASE_IDX 0 +#define regSDMA1_VERSION 0x0635 +#define regSDMA1_VERSION_BASE_IDX 0 +#define regSDMA1_EDC_COUNTER 0x0636 +#define regSDMA1_EDC_COUNTER_BASE_IDX 0 +#define regSDMA1_EDC_COUNTER_CLEAR 0x0637 +#define regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define regSDMA1_STATUS2_REG 0x0638 +#define regSDMA1_STATUS2_REG_BASE_IDX 0 +#define regSDMA1_ATOMIC_CNTL 0x0639 +#define regSDMA1_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA1_ATOMIC_PREOP_LO 0x063a +#define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA1_ATOMIC_PREOP_HI 0x063b +#define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA1_UTCL1_CNTL 0x063c +#define regSDMA1_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA1_UTCL1_WATERMK 0x063d +#define regSDMA1_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA1_UTCL1_TIMEOUT 0x063e +#define regSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA1_UTCL1_PAGE 0x063f +#define regSDMA1_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_STATUS 0x0640 +#define regSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_STATUS 0x0641 +#define regSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA1_UTCL1_INV0 0x0642 +#define regSDMA1_UTCL1_INV0_BASE_IDX 0 +#define regSDMA1_UTCL1_INV1 0x0643 +#define regSDMA1_UTCL1_INV1_BASE_IDX 0 +#define regSDMA1_UTCL1_INV2 0x0644 +#define regSDMA1_UTCL1_INV2_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_XNACK0 0x0645 +#define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_XNACK1 0x0646 +#define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_XNACK0 0x0647 +#define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_XNACK1 0x0648 +#define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA1_RELAX_ORDERING_LUT 0x064a +#define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA1_CHICKEN_BITS_2 0x064b +#define regSDMA1_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA1_STATUS3_REG 0x064c +#define regSDMA1_STATUS3_REG_BASE_IDX 0 +#define regSDMA1_PHYSICAL_ADDR_LO 0x064d +#define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_PHYSICAL_ADDR_HI 0x064e +#define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_GLOBAL_QUANTUM 0x064f +#define regSDMA1_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA1_ERROR_LOG 0x0650 +#define regSDMA1_ERROR_LOG_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG0 0x0651 +#define regSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG1 0x0652 +#define regSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG2 0x0653 +#define regSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG3 0x0654 +#define regSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA1_F32_COUNTER 0x0655 +#define regSDMA1_F32_COUNTER_BASE_IDX 0 +#define regSDMA1_CRD_CNTL 0x065b +#define regSDMA1_CRD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC_CGCG_CTRL 0x065c +#define regSDMA1_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA1_AQL_STATUS 0x065f +#define regSDMA1_AQL_STATUS_BASE_IDX 0 +#define regSDMA1_EA_DBIT_ADDR_DATA 0x0660 +#define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA1_EA_DBIT_ADDR_INDEX 0x0661 +#define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA1_TLBI_GCR_CNTL 0x0662 +#define regSDMA1_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA1_TILING_CONFIG 0x0663 +#define regSDMA1_TILING_CONFIG_BASE_IDX 0 +#define regSDMA1_INT_STATUS 0x0670 +#define regSDMA1_INT_STATUS_BASE_IDX 0 +#define regSDMA1_HOLE_ADDR_LO 0x0672 +#define regSDMA1_HOLE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_HOLE_ADDR_HI 0x0673 +#define regSDMA1_HOLE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_CLOCK_GATING_STATUS 0x0675 +#define regSDMA1_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA1_STATUS4_REG 0x0676 +#define regSDMA1_STATUS4_REG_BASE_IDX 0 +#define regSDMA1_SCRATCH_RAM_DATA 0x0677 +#define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA1_SCRATCH_RAM_ADDR 0x0678 +#define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA1_TIMESTAMP_CNTL 0x0679 +#define regSDMA1_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA1_STATUS5_REG 0x067a +#define regSDMA1_STATUS5_REG_BASE_IDX 0 +#define regSDMA1_QUEUE_RESET_REQ 0x067b +#define regSDMA1_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA1_STATUS6_REG 0x067c +#define regSDMA1_STATUS6_REG_BASE_IDX 0 +#define regSDMA1_UCODE1_CHECKSUM 0x067d +#define regSDMA1_UCODE1_CHECKSUM_BASE_IDX 0 +#define regSDMA1_CE_CTRL 0x067e +#define regSDMA1_CE_CTRL_BASE_IDX 0 +#define regSDMA1_FED_STATUS 0x067f +#define regSDMA1_FED_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_CNTL 0x0680 +#define regSDMA1_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_BASE 0x0681 +#define regSDMA1_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_BASE_HI 0x0682 +#define regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR 0x0683 +#define regSDMA1_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR_HI 0x0684 +#define regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR 0x0685 +#define regSDMA1_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR_HI 0x0686 +#define regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI 0x0688 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO 0x0689 +#define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_CNTL 0x068a +#define regSDMA1_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_RPTR 0x068b +#define regSDMA1_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_OFFSET 0x068c +#define regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_BASE_LO 0x068d +#define regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_BASE_HI 0x068e +#define regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_SIZE 0x068f +#define regSDMA1_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE0_SKIP_CNTL 0x0690 +#define regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_CONTEXT_STATUS 0x0691 +#define regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE0_DOORBELL 0x0692 +#define regSDMA1_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE0_DOORBELL_LOG 0x06a9 +#define regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE0_DOORBELL_OFFSET 0x06ab +#define regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE0_CSA_ADDR_LO 0x06ac +#define regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_CSA_ADDR_HI 0x06ad +#define regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_SCHEDULE_CNTL 0x06ae +#define regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_IB_SUB_REMAIN 0x06af +#define regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE0_PREEMPT 0x06b0 +#define regSDMA1_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE0_DUMMY_REG 0x06b1 +#define regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x06b2 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x06b3 +#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_AQL_CNTL 0x06b4 +#define regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE0_MINOR_PTR_UPDATE 0x06b5 +#define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE0_RB_PREEMPT 0x06b6 +#define regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA0 0x06c0 +#define regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA1 0x06c1 +#define regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA2 0x06c2 +#define regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA3 0x06c3 +#define regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA4 0x06c4 +#define regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA5 0x06c5 +#define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA6 0x06c6 +#define regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA7 0x06c7 +#define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA8 0x06c8 +#define regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA9 0x06c9 +#define regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_DATA10 0x06ca +#define regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE0_MIDCMD_CNTL 0x06cb +#define regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_CNTL 0x06d8 +#define regSDMA1_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_BASE 0x06d9 +#define regSDMA1_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_BASE_HI 0x06da +#define regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR 0x06db +#define regSDMA1_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR_HI 0x06dc +#define regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR 0x06dd +#define regSDMA1_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR_HI 0x06de +#define regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI 0x06e0 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO 0x06e1 +#define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_CNTL 0x06e2 +#define regSDMA1_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_RPTR 0x06e3 +#define regSDMA1_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_OFFSET 0x06e4 +#define regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_BASE_LO 0x06e5 +#define regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_BASE_HI 0x06e6 +#define regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_SIZE 0x06e7 +#define regSDMA1_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE1_SKIP_CNTL 0x06e8 +#define regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_CONTEXT_STATUS 0x06e9 +#define regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE1_DOORBELL 0x06ea +#define regSDMA1_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE1_DOORBELL_LOG 0x0701 +#define regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE1_DOORBELL_OFFSET 0x0703 +#define regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE1_CSA_ADDR_LO 0x0704 +#define regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_CSA_ADDR_HI 0x0705 +#define regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_SCHEDULE_CNTL 0x0706 +#define regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_IB_SUB_REMAIN 0x0707 +#define regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE1_PREEMPT 0x0708 +#define regSDMA1_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE1_DUMMY_REG 0x0709 +#define regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x070a +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x070b +#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_AQL_CNTL 0x070c +#define regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE1_MINOR_PTR_UPDATE 0x070d +#define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE1_RB_PREEMPT 0x070e +#define regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA0 0x0718 +#define regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA1 0x0719 +#define regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA2 0x071a +#define regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA3 0x071b +#define regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA4 0x071c +#define regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA5 0x071d +#define regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA6 0x071e +#define regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA7 0x071f +#define regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA8 0x0720 +#define regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA9 0x0721 +#define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_DATA10 0x0722 +#define regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE1_MIDCMD_CNTL 0x0723 +#define regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_CNTL 0x0730 +#define regSDMA1_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_BASE 0x0731 +#define regSDMA1_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_BASE_HI 0x0732 +#define regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR 0x0733 +#define regSDMA1_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR_HI 0x0734 +#define regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR 0x0735 +#define regSDMA1_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR_HI 0x0736 +#define regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI 0x0738 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO 0x0739 +#define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_CNTL 0x073a +#define regSDMA1_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_RPTR 0x073b +#define regSDMA1_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_OFFSET 0x073c +#define regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_BASE_LO 0x073d +#define regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_BASE_HI 0x073e +#define regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_SIZE 0x073f +#define regSDMA1_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE2_SKIP_CNTL 0x0740 +#define regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_CONTEXT_STATUS 0x0741 +#define regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE2_DOORBELL 0x0742 +#define regSDMA1_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE2_DOORBELL_LOG 0x0759 +#define regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE2_DOORBELL_OFFSET 0x075b +#define regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE2_CSA_ADDR_LO 0x075c +#define regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_CSA_ADDR_HI 0x075d +#define regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_SCHEDULE_CNTL 0x075e +#define regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_IB_SUB_REMAIN 0x075f +#define regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE2_PREEMPT 0x0760 +#define regSDMA1_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE2_DUMMY_REG 0x0761 +#define regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0762 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0763 +#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_AQL_CNTL 0x0764 +#define regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE2_MINOR_PTR_UPDATE 0x0765 +#define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE2_RB_PREEMPT 0x0766 +#define regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA0 0x0770 +#define regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA1 0x0771 +#define regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA2 0x0772 +#define regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA3 0x0773 +#define regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA4 0x0774 +#define regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA5 0x0775 +#define regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA6 0x0776 +#define regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA7 0x0777 +#define regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA8 0x0778 +#define regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA9 0x0779 +#define regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_DATA10 0x077a +#define regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE2_MIDCMD_CNTL 0x077b +#define regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_CNTL 0x0788 +#define regSDMA1_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_BASE 0x0789 +#define regSDMA1_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_BASE_HI 0x078a +#define regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR 0x078b +#define regSDMA1_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR_HI 0x078c +#define regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR 0x078d +#define regSDMA1_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR_HI 0x078e +#define regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI 0x0790 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO 0x0791 +#define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_CNTL 0x0792 +#define regSDMA1_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_RPTR 0x0793 +#define regSDMA1_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_OFFSET 0x0794 +#define regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_BASE_LO 0x0795 +#define regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_BASE_HI 0x0796 +#define regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_SIZE 0x0797 +#define regSDMA1_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE3_SKIP_CNTL 0x0798 +#define regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_CONTEXT_STATUS 0x0799 +#define regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE3_DOORBELL 0x079a +#define regSDMA1_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE3_DOORBELL_LOG 0x07b1 +#define regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE3_DOORBELL_OFFSET 0x07b3 +#define regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE3_CSA_ADDR_LO 0x07b4 +#define regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_CSA_ADDR_HI 0x07b5 +#define regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_SCHEDULE_CNTL 0x07b6 +#define regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_IB_SUB_REMAIN 0x07b7 +#define regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE3_PREEMPT 0x07b8 +#define regSDMA1_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE3_DUMMY_REG 0x07b9 +#define regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x07ba +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x07bb +#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_AQL_CNTL 0x07bc +#define regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE3_MINOR_PTR_UPDATE 0x07bd +#define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE3_RB_PREEMPT 0x07be +#define regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA0 0x07c8 +#define regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA1 0x07c9 +#define regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA2 0x07ca +#define regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA3 0x07cb +#define regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA4 0x07cc +#define regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA5 0x07cd +#define regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA6 0x07ce +#define regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA7 0x07cf +#define regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA8 0x07d0 +#define regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA9 0x07d1 +#define regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_DATA10 0x07d2 +#define regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE3_MIDCMD_CNTL 0x07d3 +#define regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_CNTL 0x07e0 +#define regSDMA1_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_BASE 0x07e1 +#define regSDMA1_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_BASE_HI 0x07e2 +#define regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR 0x07e3 +#define regSDMA1_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR_HI 0x07e4 +#define regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR 0x07e5 +#define regSDMA1_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR_HI 0x07e6 +#define regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI 0x07e8 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO 0x07e9 +#define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_CNTL 0x07ea +#define regSDMA1_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_RPTR 0x07eb +#define regSDMA1_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_OFFSET 0x07ec +#define regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_BASE_LO 0x07ed +#define regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_BASE_HI 0x07ee +#define regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_SIZE 0x07ef +#define regSDMA1_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE4_SKIP_CNTL 0x07f0 +#define regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_CONTEXT_STATUS 0x07f1 +#define regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE4_DOORBELL 0x07f2 +#define regSDMA1_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE4_DOORBELL_LOG 0x0809 +#define regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE4_DOORBELL_OFFSET 0x080b +#define regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE4_CSA_ADDR_LO 0x080c +#define regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_CSA_ADDR_HI 0x080d +#define regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_SCHEDULE_CNTL 0x080e +#define regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_IB_SUB_REMAIN 0x080f +#define regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE4_PREEMPT 0x0810 +#define regSDMA1_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE4_DUMMY_REG 0x0811 +#define regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0812 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0813 +#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_AQL_CNTL 0x0814 +#define regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE4_MINOR_PTR_UPDATE 0x0815 +#define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE4_RB_PREEMPT 0x0816 +#define regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA0 0x0820 +#define regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA1 0x0821 +#define regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA2 0x0822 +#define regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA3 0x0823 +#define regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA4 0x0824 +#define regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA5 0x0825 +#define regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA6 0x0826 +#define regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA7 0x0827 +#define regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA8 0x0828 +#define regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA9 0x0829 +#define regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_DATA10 0x082a +#define regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE4_MIDCMD_CNTL 0x082b +#define regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_CNTL 0x0838 +#define regSDMA1_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_BASE 0x0839 +#define regSDMA1_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_BASE_HI 0x083a +#define regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR 0x083b +#define regSDMA1_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR_HI 0x083c +#define regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR 0x083d +#define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR_HI 0x083e +#define regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI 0x0840 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO 0x0841 +#define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_CNTL 0x0842 +#define regSDMA1_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_RPTR 0x0843 +#define regSDMA1_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_OFFSET 0x0844 +#define regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_BASE_LO 0x0845 +#define regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_BASE_HI 0x0846 +#define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_SIZE 0x0847 +#define regSDMA1_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE5_SKIP_CNTL 0x0848 +#define regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_CONTEXT_STATUS 0x0849 +#define regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE5_DOORBELL 0x084a +#define regSDMA1_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE5_DOORBELL_LOG 0x0861 +#define regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE5_DOORBELL_OFFSET 0x0863 +#define regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE5_CSA_ADDR_LO 0x0864 +#define regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_CSA_ADDR_HI 0x0865 +#define regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_SCHEDULE_CNTL 0x0866 +#define regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_IB_SUB_REMAIN 0x0867 +#define regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE5_PREEMPT 0x0868 +#define regSDMA1_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE5_DUMMY_REG 0x0869 +#define regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x086a +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x086b +#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_AQL_CNTL 0x086c +#define regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE5_MINOR_PTR_UPDATE 0x086d +#define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE5_RB_PREEMPT 0x086e +#define regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA0 0x0878 +#define regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA1 0x0879 +#define regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA2 0x087a +#define regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA3 0x087b +#define regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA4 0x087c +#define regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA5 0x087d +#define regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA6 0x087e +#define regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA7 0x087f +#define regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA8 0x0880 +#define regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA9 0x0881 +#define regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_DATA10 0x0882 +#define regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE5_MIDCMD_CNTL 0x0883 +#define regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_CNTL 0x0890 +#define regSDMA1_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_BASE 0x0891 +#define regSDMA1_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_BASE_HI 0x0892 +#define regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR 0x0893 +#define regSDMA1_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR_HI 0x0894 +#define regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR 0x0895 +#define regSDMA1_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR_HI 0x0896 +#define regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI 0x0898 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO 0x0899 +#define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_CNTL 0x089a +#define regSDMA1_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_RPTR 0x089b +#define regSDMA1_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_OFFSET 0x089c +#define regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_BASE_LO 0x089d +#define regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_BASE_HI 0x089e +#define regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_SIZE 0x089f +#define regSDMA1_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE6_SKIP_CNTL 0x08a0 +#define regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_CONTEXT_STATUS 0x08a1 +#define regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE6_DOORBELL 0x08a2 +#define regSDMA1_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE6_DOORBELL_LOG 0x08b9 +#define regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE6_DOORBELL_OFFSET 0x08bb +#define regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE6_CSA_ADDR_LO 0x08bc +#define regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_CSA_ADDR_HI 0x08bd +#define regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_SCHEDULE_CNTL 0x08be +#define regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_IB_SUB_REMAIN 0x08bf +#define regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE6_PREEMPT 0x08c0 +#define regSDMA1_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE6_DUMMY_REG 0x08c1 +#define regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x08c2 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x08c3 +#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_AQL_CNTL 0x08c4 +#define regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE6_MINOR_PTR_UPDATE 0x08c5 +#define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE6_RB_PREEMPT 0x08c6 +#define regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA0 0x08d0 +#define regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA1 0x08d1 +#define regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA2 0x08d2 +#define regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA3 0x08d3 +#define regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA4 0x08d4 +#define regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA5 0x08d5 +#define regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA6 0x08d6 +#define regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA7 0x08d7 +#define regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA8 0x08d8 +#define regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA9 0x08d9 +#define regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_DATA10 0x08da +#define regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE6_MIDCMD_CNTL 0x08db +#define regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_CNTL 0x08e8 +#define regSDMA1_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_BASE 0x08e9 +#define regSDMA1_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_BASE_HI 0x08ea +#define regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR 0x08eb +#define regSDMA1_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR_HI 0x08ec +#define regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR 0x08ed +#define regSDMA1_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR_HI 0x08ee +#define regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI 0x08f0 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO 0x08f1 +#define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_CNTL 0x08f2 +#define regSDMA1_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_RPTR 0x08f3 +#define regSDMA1_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_OFFSET 0x08f4 +#define regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_BASE_LO 0x08f5 +#define regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_BASE_HI 0x08f6 +#define regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_SIZE 0x08f7 +#define regSDMA1_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA1_QUEUE7_SKIP_CNTL 0x08f8 +#define regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_CONTEXT_STATUS 0x08f9 +#define regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_QUEUE7_DOORBELL 0x08fa +#define regSDMA1_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA1_QUEUE7_DOORBELL_LOG 0x0911 +#define regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_QUEUE7_DOORBELL_OFFSET 0x0913 +#define regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_QUEUE7_CSA_ADDR_LO 0x0914 +#define regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_CSA_ADDR_HI 0x0915 +#define regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_SCHEDULE_CNTL 0x0916 +#define regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_IB_SUB_REMAIN 0x0917 +#define regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_QUEUE7_PREEMPT 0x0918 +#define regSDMA1_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE7_DUMMY_REG 0x0919 +#define regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x091a +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x091b +#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_AQL_CNTL 0x091c +#define regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_QUEUE7_MINOR_PTR_UPDATE 0x091d +#define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_QUEUE7_RB_PREEMPT 0x091e +#define regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA0 0x0928 +#define regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA1 0x0929 +#define regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA2 0x092a +#define regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA3 0x092b +#define regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA4 0x092c +#define regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA5 0x092d +#define regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA6 0x092e +#define regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA7 0x092f +#define regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA8 0x0930 +#define regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA9 0x0931 +#define regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_DATA10 0x0932 +#define regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_QUEUE7_MIDCMD_CNTL 0x0933 +#define regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: gc_sdma0_sdma0hypdec +// base address: 0x3e200 +#define regSDMA0_UCODE_ADDR 0x5880 +#define regSDMA0_UCODE_ADDR_BASE_IDX 1 +#define regSDMA0_UCODE_DATA 0x5881 +#define regSDMA0_UCODE_DATA_BASE_IDX 1 +#define regSDMA0_UCODE_SELFLOAD_CONTROL 0x5882 +#define regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 +#define regSDMA0_BROADCAST_UCODE_ADDR 0x5886 +#define regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX 1 +#define regSDMA0_BROADCAST_UCODE_DATA 0x5887 +#define regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX 1 +#define regSDMA0_F32_CNTL 0x589a +#define regSDMA0_F32_CNTL_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma1hypdec +// base address: 0x3e280 +#define regSDMA1_UCODE_ADDR 0x58a0 +#define regSDMA1_UCODE_ADDR_BASE_IDX 1 +#define regSDMA1_UCODE_DATA 0x58a1 +#define regSDMA1_UCODE_DATA_BASE_IDX 1 +#define regSDMA1_UCODE_SELFLOAD_CONTROL 0x58a2 +#define regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 +#define regSDMA1_BROADCAST_UCODE_ADDR 0x58a6 +#define regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX 1 +#define regSDMA1_BROADCAST_UCODE_DATA 0x58a7 +#define regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX 1 +#define regSDMA1_F32_CNTL 0x58ba +#define regSDMA1_F32_CNTL_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma0perfsdec +// base address: 0x37880 +#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x3e20 +#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x3e21 +#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e22 +#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA0_PERFCNT_MISC_CNTL 0x3e23 +#define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_SELECT 0x3e24 +#define regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_SELECT1 0x3e25 +#define regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_SELECT 0x3e26 +#define regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_SELECT1 0x3e27 +#define regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma1perfsdec +// base address: 0x378b0 +#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x3e2c +#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x3e2d +#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e2e +#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA1_PERFCNT_MISC_CNTL 0x3e2f +#define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_SELECT 0x3e30 +#define regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_SELECT1 0x3e31 +#define regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_SELECT 0x3e32 +#define regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_SELECT1 0x3e33 +#define regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma0perfddec +// base address: 0x35980 +#define regSDMA0_PERFCNT_PERFCOUNTER_LO 0x3660 +#define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA0_PERFCNT_PERFCOUNTER_HI 0x3661 +#define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_LO 0x3662 +#define regSDMA0_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER0_HI 0x3663 +#define regSDMA0_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_LO 0x3664 +#define regSDMA0_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA0_PERFCOUNTER1_HI 0x3665 +#define regSDMA0_PERFCOUNTER1_HI_BASE_IDX 1 + + +// addressBlock: gc_sdma0_sdma1perfddec +// base address: 0x359b0 +#define regSDMA1_PERFCNT_PERFCOUNTER_LO 0x366c +#define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA1_PERFCNT_PERFCOUNTER_HI 0x366d +#define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_LO 0x366e +#define regSDMA1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER0_HI 0x366f +#define regSDMA1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_LO 0x3670 +#define regSDMA1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA1_PERFCOUNTER1_HI 0x3671 +#define regSDMA1_PERFCOUNTER1_HI_BASE_IDX 1 + + +// addressBlock: gc_grbmdec +// base address: 0x8000 +#define regGRBM_CNTL 0x0da0 +#define regGRBM_CNTL_BASE_IDX 0 +#define regGRBM_SKEW_CNTL 0x0da1 +#define regGRBM_SKEW_CNTL_BASE_IDX 0 +#define regGRBM_STATUS2 0x0da2 +#define regGRBM_STATUS2_BASE_IDX 0 +#define regGRBM_PWR_CNTL 0x0da3 +#define regGRBM_PWR_CNTL_BASE_IDX 0 +#define regGRBM_STATUS 0x0da4 +#define regGRBM_STATUS_BASE_IDX 0 +#define regGRBM_STATUS_SE0 0x0da5 +#define regGRBM_STATUS_SE0_BASE_IDX 0 +#define regGRBM_STATUS_SE1 0x0da6 +#define regGRBM_STATUS_SE1_BASE_IDX 0 +#define regGRBM_STATUS3 0x0da7 +#define regGRBM_STATUS3_BASE_IDX 0 +#define regGRBM_SOFT_RESET 0x0da8 +#define regGRBM_SOFT_RESET_BASE_IDX 0 +#define regGRBM_GFX_CLKEN_CNTL 0x0dac +#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBM_WAIT_IDLE_CLOCKS 0x0dad +#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 +#define regGRBM_STATUS_SE2 0x0dae +#define regGRBM_STATUS_SE2_BASE_IDX 0 +#define regGRBM_STATUS_SE3 0x0daf +#define regGRBM_STATUS_SE3_BASE_IDX 0 +#define regGRBM_STATUS_SE4 0x0db0 +#define regGRBM_STATUS_SE4_BASE_IDX 0 +#define regGRBM_STATUS_SE5 0x0db1 +#define regGRBM_STATUS_SE5_BASE_IDX 0 +#define regGRBM_READ_ERROR 0x0db6 +#define regGRBM_READ_ERROR_BASE_IDX 0 +#define regGRBM_READ_ERROR2 0x0db7 +#define regGRBM_READ_ERROR2_BASE_IDX 0 +#define regGRBM_INT_CNTL 0x0db8 +#define regGRBM_INT_CNTL_BASE_IDX 0 +#define regGRBM_TRAP_OP 0x0db9 +#define regGRBM_TRAP_OP_BASE_IDX 0 +#define regGRBM_TRAP_ADDR 0x0dba +#define regGRBM_TRAP_ADDR_BASE_IDX 0 +#define regGRBM_TRAP_ADDR_MSK 0x0dbb +#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 +#define regGRBM_TRAP_WD 0x0dbc +#define regGRBM_TRAP_WD_BASE_IDX 0 +#define regGRBM_TRAP_WD_MSK 0x0dbd +#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 +#define regGRBM_DSM_BYPASS 0x0dbe +#define regGRBM_DSM_BYPASS_BASE_IDX 0 +#define regGRBM_WRITE_ERROR 0x0dbf +#define regGRBM_WRITE_ERROR_BASE_IDX 0 +#define regGRBM_CHIP_REVISION 0x0dc1 +#define regGRBM_CHIP_REVISION_BASE_IDX 0 +#define regGRBM_IH_CREDIT 0x0dc4 +#define regGRBM_IH_CREDIT_BASE_IDX 0 +#define regGRBM_PWR_CNTL2 0x0dc5 +#define regGRBM_PWR_CNTL2_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_START 0x0dc6 +#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_END 0x0dc7 +#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 +#define regGRBM_INVALID_PIPE 0x0dc9 +#define regGRBM_INVALID_PIPE_BASE_IDX 0 +#define regGRBM_FENCE_RANGE0 0x0dca +#define regGRBM_FENCE_RANGE0_BASE_IDX 0 +#define regGRBM_FENCE_RANGE1 0x0dcb +#define regGRBM_FENCE_RANGE1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG0 0x0de0 +#define regGRBM_SCRATCH_REG0_BASE_IDX 0 +#define regGRBM_SCRATCH_REG1 0x0de1 +#define regGRBM_SCRATCH_REG1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG2 0x0de2 +#define regGRBM_SCRATCH_REG2_BASE_IDX 0 +#define regGRBM_SCRATCH_REG3 0x0de3 +#define regGRBM_SCRATCH_REG3_BASE_IDX 0 +#define regGRBM_SCRATCH_REG4 0x0de4 +#define regGRBM_SCRATCH_REG4_BASE_IDX 0 +#define regGRBM_SCRATCH_REG5 0x0de5 +#define regGRBM_SCRATCH_REG5_BASE_IDX 0 +#define regGRBM_SCRATCH_REG6 0x0de6 +#define regGRBM_SCRATCH_REG6_BASE_IDX 0 +#define regGRBM_SCRATCH_REG7 0x0de7 +#define regGRBM_SCRATCH_REG7_BASE_IDX 0 +#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0df1 +#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 + + +// addressBlock: gc_cpdec +// base address: 0x8200 +#define regCP_CPC_DEBUG_CNTL 0x0e20 +#define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPC_DEBUG_DATA 0x0e21 +#define regCP_CPC_DEBUG_DATA_BASE_IDX 0 +#define regCP_CPC_STATUS 0x0e24 +#define regCP_CPC_STATUS_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT 0x0e25 +#define regCP_CPC_BUSY_STAT_BASE_IDX 0 +#define regCP_CPC_STALLED_STAT1 0x0e26 +#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPF_STATUS 0x0e27 +#define regCP_CPF_STATUS_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT 0x0e28 +#define regCP_CPF_BUSY_STAT_BASE_IDX 0 +#define regCP_CPF_STALLED_STAT1 0x0e29 +#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT2 0x0e2a +#define regCP_CPC_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_GRBM_FREE_COUNT 0x0e2b +#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR 0x0e2c +#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_MEC_ME1_HEADER_DUMP 0x0e2e +#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 +#define regCP_MEC_ME2_HEADER_DUMP 0x0e2f +#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 +#define regCP_CPC_SCRATCH_INDEX 0x0e30 +#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 +#define regCP_CPC_SCRATCH_DATA 0x0e31 +#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 +#define regCP_CPF_GRBM_FREE_COUNT 0x0e32 +#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT2 0x0e33 +#define regCP_CPF_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_HALT_HYST_COUNT 0x0e47 +#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 +#define regCP_STALLED_STAT3 0x0f3c +#define regCP_STALLED_STAT3_BASE_IDX 0 +#define regCP_STALLED_STAT1 0x0f3d +#define regCP_STALLED_STAT1_BASE_IDX 0 +#define regCP_STALLED_STAT2 0x0f3e +#define regCP_STALLED_STAT2_BASE_IDX 0 +#define regCP_BUSY_STAT 0x0f3f +#define regCP_BUSY_STAT_BASE_IDX 0 +#define regCP_STAT 0x0f40 +#define regCP_STAT_BASE_IDX 0 +#define regCP_ME_HEADER_DUMP 0x0f41 +#define regCP_ME_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_HEADER_DUMP 0x0f42 +#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 +#define regCP_GRBM_FREE_COUNT 0x0f43 +#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_PFP_INSTR_PNTR 0x0f45 +#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 +#define regCP_ME_INSTR_PNTR 0x0f46 +#define regCP_ME_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC1_INSTR_PNTR 0x0f48 +#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC2_INSTR_PNTR 0x0f49 +#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 +#define regCP_CSF_STAT 0x0f54 +#define regCP_CSF_STAT_BASE_IDX 0 +#define regCP_CNTX_STAT 0x0f58 +#define regCP_CNTX_STAT_BASE_IDX 0 +#define regCP_ME_PREEMPTION 0x0f59 +#define regCP_ME_PREEMPTION_BASE_IDX 0 +#define regCP_RB1_RPTR 0x0f5f +#define regCP_RB1_RPTR_BASE_IDX 0 +#define regCP_RB0_RPTR 0x0f60 +#define regCP_RB0_RPTR_BASE_IDX 0 +#define regCP_RB_RPTR 0x0f60 +#define regCP_RB_RPTR_BASE_IDX 0 +#define regCP_RB_WPTR_DELAY 0x0f61 +#define regCP_RB_WPTR_DELAY_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_CNTL 0x0f62 +#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_ROQ1_THRESHOLDS 0x0f75 +#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ2_THRESHOLDS 0x0f76 +#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 +#define regCP_STQ_THRESHOLDS 0x0f77 +#define regCP_STQ_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_THRESHOLDS 0x0f79 +#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_AVAIL 0x0f7a +#define regCP_ROQ_AVAIL_BASE_IDX 0 +#define regCP_STQ_AVAIL 0x0f7b +#define regCP_STQ_AVAIL_BASE_IDX 0 +#define regCP_ROQ2_AVAIL 0x0f7c +#define regCP_ROQ2_AVAIL_BASE_IDX 0 +#define regCP_MEQ_AVAIL 0x0f7d +#define regCP_MEQ_AVAIL_BASE_IDX 0 +#define regCP_CMD_INDEX 0x0f7e +#define regCP_CMD_INDEX_BASE_IDX 0 +#define regCP_CMD_DATA 0x0f7f +#define regCP_CMD_DATA_BASE_IDX 0 +#define regCP_ROQ_RB_STAT 0x0f80 +#define regCP_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_ROQ_IB1_STAT 0x0f81 +#define regCP_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_ROQ_IB2_STAT 0x0f82 +#define regCP_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_STQ_STAT 0x0f83 +#define regCP_STQ_STAT_BASE_IDX 0 +#define regCP_STQ_WR_STAT 0x0f84 +#define regCP_STQ_WR_STAT_BASE_IDX 0 +#define regCP_MEQ_STAT 0x0f85 +#define regCP_MEQ_STAT_BASE_IDX 0 +#define regCP_ROQ3_THRESHOLDS 0x0f8c +#define regCP_ROQ3_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_DB_STAT 0x0f8d +#define regCP_ROQ_DB_STAT_BASE_IDX 0 +#define regCP_DEBUG_CNTL 0x0f98 +#define regCP_DEBUG_CNTL_BASE_IDX 0 +#define regCP_DEBUG_DATA 0x0f99 +#define regCP_DEBUG_DATA_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR 0x0f9a +#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 + + +// addressBlock: gc_padec +// base address: 0x8800 +#define regVGT_DMA_DATA_FIFO_DEPTH 0x0fcd +#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DMA_REQ_FIFO_DEPTH 0x0fce +#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf +#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_MC_LAT_CNTL 0x0fd6 +#define regVGT_MC_LAT_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS_2 0x0fd7 +#define regIA_UTCL1_STATUS_2_BASE_IDX 0 +#define regWD_CNTL_STATUS 0x0fdf +#define regWD_CNTL_STATUS_BASE_IDX 0 +#define regCC_GC_PRIM_CONFIG 0x0fe0 +#define regCC_GC_PRIM_CONFIG_BASE_IDX 0 +#define regWD_QOS 0x0fe2 +#define regWD_QOS_BASE_IDX 0 +#define regWD_UTCL1_CNTL 0x0fe3 +#define regWD_UTCL1_CNTL_BASE_IDX 0 +#define regWD_UTCL1_STATUS 0x0fe4 +#define regWD_UTCL1_STATUS_BASE_IDX 0 +#define regIA_UTCL1_CNTL 0x0fe6 +#define regIA_UTCL1_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS 0x0fe7 +#define regIA_UTCL1_STATUS_BASE_IDX 0 +#define regCC_GC_SA_UNIT_DISABLE 0x0fe9 +#define regCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 +#define regGE_RATE_CNTL_1 0x0ff4 +#define regGE_RATE_CNTL_1_BASE_IDX 0 +#define regGE_RATE_CNTL_2 0x0ff5 +#define regGE_RATE_CNTL_2_BASE_IDX 0 +#define regVGT_SYS_CONFIG 0x1003 +#define regVGT_SYS_CONFIG_BASE_IDX 0 +#define regGE_PRIV_CONTROL 0x1004 +#define regGE_PRIV_CONTROL_BASE_IDX 0 +#define regGE_STATUS 0x1005 +#define regGE_STATUS_BASE_IDX 0 +#define regVGT_GS_MAX_WAVE_ID 0x1009 +#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 +#define regGFX_PIPE_CONTROL 0x100d +#define regGFX_PIPE_CONTROL_BASE_IDX 0 +#define regCC_GC_SHADER_ARRAY_CONFIG 0x100f +#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regGE2_SE_CNTL_STATUS 0x1011 +#define regGE2_SE_CNTL_STATUS_BASE_IDX 0 +#define regGE_SPI_IF_SAFE_REG 0x1018 +#define regGE_SPI_IF_SAFE_REG_BASE_IDX 0 +#define regGE_PA_IF_SAFE_REG 0x1019 +#define regGE_PA_IF_SAFE_REG_BASE_IDX 0 +#define regPA_CL_CNTL_STATUS 0x1024 +#define regPA_CL_CNTL_STATUS_BASE_IDX 0 +#define regPA_CL_ENHANCE 0x1025 +#define regPA_CL_ENHANCE_BASE_IDX 0 +#define regPA_SU_CNTL_STATUS 0x1034 +#define regPA_SU_CNTL_STATUS_BASE_IDX 0 +#define regPA_SC_FIFO_DEPTH_CNTL 0x1035 +#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 + + +// addressBlock: gc_sqdec +// base address: 0x8c00 +#define regSQ_CONFIG 0x10a0 +#define regSQ_CONFIG_BASE_IDX 0 +#define regSQC_CONFIG 0x10a1 +#define regSQC_CONFIG_BASE_IDX 0 +#define regLDS_CONFIG 0x10a2 +#define regLDS_CONFIG_BASE_IDX 0 +#define regSQ_RANDOM_WAVE_PRI 0x10a3 +#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 +#define regSQG_STATUS 0x10a4 +#define regSQG_STATUS_BASE_IDX 0 +#define regSQ_FIFO_SIZES 0x10a5 +#define regSQ_FIFO_SIZES_BASE_IDX 0 +#define regSQ_DSM_CNTL 0x10a6 +#define regSQ_DSM_CNTL_BASE_IDX 0 +#define regSQ_DSM_CNTL2 0x10a7 +#define regSQ_DSM_CNTL2_BASE_IDX 0 +#define regSP_CONFIG 0x10ab +#define regSP_CONFIG_BASE_IDX 0 +#define regSQ_ARB_CONFIG 0x10ac +#define regSQ_ARB_CONFIG_BASE_IDX 0 +#define regSQ_DEBUG_HOST_TRAP_STATUS 0x10b6 +#define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX 0 +#define regSQG_GL1H_STATUS 0x10b9 +#define regSQG_GL1H_STATUS_BASE_IDX 0 +#define regSQG_CONFIG 0x10ba +#define regSQG_CONFIG_BASE_IDX 0 +#define regSQ_PERF_SNAPSHOT_CTRL 0x10bb +#define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 +#define regCC_GC_SHADER_RATE_CONFIG 0x10bc +#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 +#define regSQ_INTERRUPT_AUTO_MASK 0x10be +#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 +#define regSQ_INTERRUPT_MSG_CTRL 0x10bf +#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_H 0x10d0 +#define regSQ_WATCH0_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_L 0x10d1 +#define regSQ_WATCH0_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH0_CNTL 0x10d2 +#define regSQ_WATCH0_CNTL_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_H 0x10d3 +#define regSQ_WATCH1_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_L 0x10d4 +#define regSQ_WATCH1_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH1_CNTL 0x10d5 +#define regSQ_WATCH1_CNTL_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_H 0x10d6 +#define regSQ_WATCH2_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_L 0x10d7 +#define regSQ_WATCH2_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH2_CNTL 0x10d8 +#define regSQ_WATCH2_CNTL_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_H 0x10d9 +#define regSQ_WATCH3_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_L 0x10da +#define regSQ_WATCH3_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH3_CNTL 0x10db +#define regSQ_WATCH3_CNTL_BASE_IDX 0 +#define regSQ_IND_INDEX 0x1118 +#define regSQ_IND_INDEX_BASE_IDX 0 +#define regSQ_IND_DATA 0x1119 +#define regSQ_IND_DATA_BASE_IDX 0 +#define regSQ_CMD 0x111b +#define regSQ_CMD_BASE_IDX 0 + + +// addressBlock: gc_shsdec +// base address: 0x9000 +#define regSX_DEBUG_1 0x11b8 +#define regSX_DEBUG_1_BASE_IDX 0 +#define regSPI_PS_MAX_WAVE_ID 0x11da +#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 +#define regSPI_GFX_CNTL 0x11dc +#define regSPI_GFX_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL 0x11e3 +#define regSPI_DSM_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL2 0x11e4 +#define regSPI_DSM_CNTL2_BASE_IDX 0 +#define regSPI_EDC_CNT 0x11e5 +#define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPI_CONFIG_PS_CU_EN 0x11f2 +#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 +#define regSPI_WF_LIFETIME_CNTL 0x124a +#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_0 0x124b +#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_1 0x124c +#define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_2 0x124d +#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_3 0x124e +#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_4 0x124f +#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_5 0x1250 +#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_0 0x1255 +#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_2 0x1257 +#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_4 0x1259 +#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_6 0x125b +#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_7 0x125c +#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_9 0x125e +#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_11 0x1260 +#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_13 0x1262 +#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_14 0x1263 +#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_15 0x1264 +#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_16 0x1265 +#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_17 0x1266 +#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_18 0x1267 +#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_19 0x1268 +#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_20 0x1269 +#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_21 0x126b +#define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX 0 +#define regSPI_LB_CTR_CTRL 0x1274 +#define regSPI_LB_CTR_CTRL_BASE_IDX 0 +#define regSPI_LB_WGP_MASK 0x1275 +#define regSPI_LB_WGP_MASK_BASE_IDX 0 +#define regSPI_LB_DATA_REG 0x1276 +#define regSPI_LB_DATA_REG_BASE_IDX 0 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0 +#define regSPI_GDS_CREDITS 0x1278 +#define regSPI_GDS_CREDITS_BASE_IDX 0 +#define regSPI_SX_EXPORT_BUFFER_SIZES 0x1279 +#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_STATUS 0x127b +#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c +#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d +#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e +#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f +#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 +#define regSPI_LB_DATA_WAVES 0x1284 +#define regSPI_LB_DATA_WAVES_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c +#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d +#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e +#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f +#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 + + +// addressBlock: gc_tpdec +// base address: 0x9400 +#define regTD_STATUS 0x12c6 +#define regTD_STATUS_BASE_IDX 0 +#define regTD_DSM_CNTL 0x12cf +#define regTD_DSM_CNTL_BASE_IDX 0 +#define regTD_DSM_CNTL2 0x12d0 +#define regTD_DSM_CNTL2_BASE_IDX 0 +#define regTD_SCRATCH 0x12d3 +#define regTD_SCRATCH_BASE_IDX 0 +#define regTA_CNTL 0x12e1 +#define regTA_CNTL_BASE_IDX 0 +#define regTA_CNTL_AUX 0x12e2 +#define regTA_CNTL_AUX_BASE_IDX 0 +#define regTA_CNTL2 0x12e5 +#define regTA_CNTL2_BASE_IDX 0 +#define regTA_STATUS 0x12e8 +#define regTA_STATUS_BASE_IDX 0 +#define regTA_SCRATCH 0x1304 +#define regTA_SCRATCH_BASE_IDX 0 + + +// addressBlock: gc_gdsdec +// base address: 0x9700 +#define regGDS_CONFIG 0x1360 +#define regGDS_CONFIG_BASE_IDX 0 +#define regGDS_CNTL_STATUS 0x1361 +#define regGDS_CNTL_STATUS_BASE_IDX 0 +#define regGDS_ENHANCE 0x1362 +#define regGDS_ENHANCE_BASE_IDX 0 +#define regGDS_PROTECTION_FAULT 0x1363 +#define regGDS_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_VM_PROTECTION_FAULT 0x1364 +#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_EDC_CNT 0x1365 +#define regGDS_EDC_CNT_BASE_IDX 0 +#define regGDS_EDC_GRBM_CNT 0x1366 +#define regGDS_EDC_GRBM_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_DED 0x1367 +#define regGDS_EDC_OA_DED_BASE_IDX 0 +#define regGDS_DSM_CNTL 0x136a +#define regGDS_DSM_CNTL_BASE_IDX 0 +#define regGDS_EDC_OA_PHY_CNT 0x136b +#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_PIPE_CNT 0x136c +#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 +#define regGDS_DSM_CNTL2 0x136d +#define regGDS_DSM_CNTL2_BASE_IDX 0 + + +// addressBlock: gc_rbdec +// base address: 0x9800 +#define regDB_DEBUG 0x13ac +#define regDB_DEBUG_BASE_IDX 0 +#define regDB_DEBUG2 0x13ad +#define regDB_DEBUG2_BASE_IDX 0 +#define regDB_DEBUG3 0x13ae +#define regDB_DEBUG3_BASE_IDX 0 +#define regDB_DEBUG4 0x13af +#define regDB_DEBUG4_BASE_IDX 0 +#define regDB_ETILE_STUTTER_CONTROL 0x13b0 +#define regDB_ETILE_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_LTILE_STUTTER_CONTROL 0x13b1 +#define regDB_LTILE_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_EQUAD_STUTTER_CONTROL 0x13b2 +#define regDB_EQUAD_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_LQUAD_STUTTER_CONTROL 0x13b3 +#define regDB_LQUAD_STUTTER_CONTROL_BASE_IDX 0 +#define regDB_CREDIT_LIMIT 0x13b4 +#define regDB_CREDIT_LIMIT_BASE_IDX 0 +#define regDB_WATERMARKS 0x13b5 +#define regDB_WATERMARKS_BASE_IDX 0 +#define regDB_SUBTILE_CONTROL 0x13b6 +#define regDB_SUBTILE_CONTROL_BASE_IDX 0 +#define regDB_FREE_CACHELINES 0x13b7 +#define regDB_FREE_CACHELINES_BASE_IDX 0 +#define regDB_FIFO_DEPTH1 0x13b8 +#define regDB_FIFO_DEPTH1_BASE_IDX 0 +#define regDB_FIFO_DEPTH2 0x13b9 +#define regDB_FIFO_DEPTH2_BASE_IDX 0 +#define regDB_LAST_OF_BURST_CONFIG 0x13ba +#define regDB_LAST_OF_BURST_CONFIG_BASE_IDX 0 +#define regDB_RING_CONTROL 0x13bb +#define regDB_RING_CONTROL_BASE_IDX 0 +#define regDB_MEM_ARB_WATERMARKS 0x13bc +#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 +#define regDB_FIFO_DEPTH3 0x13bd +#define regDB_FIFO_DEPTH3_BASE_IDX 0 +#define regDB_DEBUG6 0x13be +#define regDB_DEBUG6_BASE_IDX 0 +#define regDB_EXCEPTION_CONTROL 0x13bf +#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 +#define regDB_DEBUG7 0x13d0 +#define regDB_DEBUG7_BASE_IDX 0 +#define regDB_DEBUG5 0x13d1 +#define regDB_DEBUG5_BASE_IDX 0 +#define regDB_FGCG_SRAMS_CLK_CTRL 0x13d7 +#define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0 +#define regDB_FGCG_INTERFACES_CLK_CTRL 0x13d8 +#define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0 +#define regDB_FIFO_DEPTH4 0x13d9 +#define regDB_FIFO_DEPTH4_BASE_IDX 0 +#define regCC_RB_REDUNDANCY 0x13dc +#define regCC_RB_REDUNDANCY_BASE_IDX 0 +#define regCC_RB_BACKEND_DISABLE 0x13dd +#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 +#define regGB_ADDR_CONFIG 0x13de +#define regGB_ADDR_CONFIG_BASE_IDX 0 +#define regGB_BACKEND_MAP 0x13df +#define regGB_BACKEND_MAP_BASE_IDX 0 +#define regGB_GPU_ID 0x13e0 +#define regGB_GPU_ID_BASE_IDX 0 +#define regCC_RB_DAISY_CHAIN 0x13e1 +#define regCC_RB_DAISY_CHAIN_BASE_IDX 0 +#define regGB_ADDR_CONFIG_READ 0x13e2 +#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regCB_HW_CONTROL_4 0x1422 +#define regCB_HW_CONTROL_4_BASE_IDX 0 +#define regCB_HW_CONTROL_3 0x1423 +#define regCB_HW_CONTROL_3_BASE_IDX 0 +#define regCB_HW_CONTROL 0x1424 +#define regCB_HW_CONTROL_BASE_IDX 0 +#define regCB_HW_CONTROL_1 0x1425 +#define regCB_HW_CONTROL_1_BASE_IDX 0 +#define regCB_HW_CONTROL_2 0x1426 +#define regCB_HW_CONTROL_2_BASE_IDX 0 +#define regCB_DCC_CONFIG 0x1427 +#define regCB_DCC_CONFIG_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_RD 0x1428 +#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_WR 0x1429 +#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 +#define regCB_FGCG_SRAM_OVERRIDE 0x142a +#define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX 0 +#define regCB_DCC_CONFIG2 0x142b +#define regCB_DCC_CONFIG2_BASE_IDX 0 +#define regCHICKEN_BITS 0x142d +#define regCHICKEN_BITS_BASE_IDX 0 +#define regCB_CACHE_EVICT_POINTS 0x142e +#define regCB_CACHE_EVICT_POINTS_BASE_IDX 0 + + +// addressBlock: gc_gceadec +// base address: 0xa800 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x17a0 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x17a1 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x17a2 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x17a3 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_RD_GRP2VC_MAP 0x17a4 +#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_WR_GRP2VC_MAP 0x17a5 +#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_RD_LAZY 0x17a6 +#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_WR_LAZY 0x17a7 +#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_RD_CAM_CNTL 0x17a8 +#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_WR_CAM_CNTL 0x17a9 +#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_PAGE_BURST 0x17aa +#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_AGE 0x17ab +#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_AGE 0x17ac +#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUEUING 0x17ad +#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUEUING 0x17ae +#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_FIXED 0x17af +#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_FIXED 0x17b0 +#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_URGENCY 0x17b1 +#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_URGENCY 0x17b2 +#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x17b3 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x17b4 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x17b5 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x17b6 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x17b7 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x17b8 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP0 0x187d +#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP1 0x187e +#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP0 0x187f +#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP1 0x1880 +#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_RD_COMBINE_FLUSH 0x1881 +#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_WR_COMBINE_FLUSH 0x1882 +#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_GROUP_BURST 0x1883 +#define regGCEA_IO_GROUP_BURST_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_AGE 0x1884 +#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_AGE 0x1885 +#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUEUING 0x1886 +#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUEUING 0x1887 +#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_FIXED 0x1888 +#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_FIXED 0x1889 +#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY 0x188a +#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY 0x188b +#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x188c +#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x188d +#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI1 0x188e +#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI2 0x188f +#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI3 0x1890 +#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI1 0x1891 +#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI2 0x1892 +#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI3 0x1893 +#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_SDP_ARB_FINAL 0x1896 +#define regGCEA_SDP_ARB_FINAL_BASE_IDX 0 +#define regGCEA_SDP_IO_PRIORITY 0x1899 +#define regGCEA_SDP_IO_PRIORITY_BASE_IDX 0 +#define regGCEA_SDP_CREDITS 0x189a +#define regGCEA_SDP_CREDITS_BASE_IDX 0 +#define regGCEA_SDP_TAG_RESERVE0 0x189b +#define regGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regGCEA_SDP_TAG_RESERVE1 0x189c +#define regGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regGCEA_SDP_VCC_RESERVE0 0x189d +#define regGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regGCEA_SDP_VCC_RESERVE1 0x189e +#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 + + +// addressBlock: gc_gceadec2 +// base address: 0x9c00 +#define regGCEA_MISC 0x14a2 +#define regGCEA_MISC_BASE_IDX 0 +#define regGCEA_LATENCY_SAMPLING 0x14a3 +#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 +#define regGCEA_MAM_CTRL2 0x14a9 +#define regGCEA_MAM_CTRL2_BASE_IDX 0 +#define regGCEA_MAM_CTRL 0x14ab +#define regGCEA_MAM_CTRL_BASE_IDX 0 +#define regGCEA_EDC_CNT 0x14b2 +#define regGCEA_EDC_CNT_BASE_IDX 0 +#define regGCEA_EDC_CNT2 0x14b3 +#define regGCEA_EDC_CNT2_BASE_IDX 0 +#define regGCEA_DSM_CNTL 0x14b4 +#define regGCEA_DSM_CNTL_BASE_IDX 0 +#define regGCEA_DSM_CNTLA 0x14b5 +#define regGCEA_DSM_CNTLA_BASE_IDX 0 +#define regGCEA_DSM_CNTLB 0x14b6 +#define regGCEA_DSM_CNTLB_BASE_IDX 0 +#define regGCEA_DSM_CNTL2 0x14b7 +#define regGCEA_DSM_CNTL2_BASE_IDX 0 +#define regGCEA_DSM_CNTL2A 0x14b8 +#define regGCEA_DSM_CNTL2A_BASE_IDX 0 +#define regGCEA_DSM_CNTL2B 0x14b9 +#define regGCEA_DSM_CNTL2B_BASE_IDX 0 +#define regGCEA_GL2C_XBR_CREDITS 0x14ba +#define regGCEA_GL2C_XBR_CREDITS_BASE_IDX 0 +#define regGCEA_GL2C_XBR_MAXBURST 0x14bb +#define regGCEA_GL2C_XBR_MAXBURST_BASE_IDX 0 +#define regGCEA_PROBE_CNTL 0x14bc +#define regGCEA_PROBE_CNTL_BASE_IDX 0 +#define regGCEA_PROBE_MAP 0x14bd +#define regGCEA_PROBE_MAP_BASE_IDX 0 +#define regGCEA_ERR_STATUS 0x14be +#define regGCEA_ERR_STATUS_BASE_IDX 0 +#define regGCEA_MISC2 0x14bf +#define regGCEA_MISC2_BASE_IDX 0 + + +// addressBlock: gc_gceadec3 +// base address: 0x9dc0 +#define regGCEA_RRET_MEM_RESERVE 0x1518 +#define regGCEA_RRET_MEM_RESERVE_BASE_IDX 0 +#define regGCEA_EDC_CNT3 0x151a +#define regGCEA_EDC_CNT3_BASE_IDX 0 +#define regGCEA_SDP_ENABLE 0x151e +#define regGCEA_SDP_ENABLE_BASE_IDX 0 + + +// addressBlock: gc_spipdec2 +// base address: 0x9c80 +#define regSPI_PQEV_CTRL 0x14c0 +#define regSPI_PQEV_CTRL_BASE_IDX 0 +#define regSPI_EXP_THROTTLE_CTRL 0x14c3 +#define regSPI_EXP_THROTTLE_CTRL_BASE_IDX 0 + + +// addressBlock: gc_rmi_rmidec +// base address: 0x2e200 +#define regRMI_GENERAL_CNTL 0x1880 +#define regRMI_GENERAL_CNTL_BASE_IDX 1 +#define regRMI_GENERAL_CNTL1 0x1881 +#define regRMI_GENERAL_CNTL1_BASE_IDX 1 +#define regRMI_GENERAL_STATUS 0x1882 +#define regRMI_GENERAL_STATUS_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS0 0x1883 +#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS1 0x1884 +#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS2 0x1885 +#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS3 0x1886 +#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 1 +#define regRMI_XBAR_CONFIG 0x1887 +#define regRMI_XBAR_CONFIG_BASE_IDX 1 +#define regRMI_PROBE_POP_LOGIC_CNTL 0x1888 +#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 1 +#define regRMI_UTC_XNACK_N_MISC_CNTL 0x1889 +#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 1 +#define regRMI_DEMUX_CNTL 0x188a +#define regRMI_DEMUX_CNTL_BASE_IDX 1 +#define regRMI_UTCL1_CNTL1 0x188b +#define regRMI_UTCL1_CNTL1_BASE_IDX 1 +#define regRMI_UTCL1_CNTL2 0x188c +#define regRMI_UTCL1_CNTL2_BASE_IDX 1 +#define regRMI_UTC_UNIT_CONFIG 0x188d +#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER0_CNTL 0x188e +#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER1_CNTL 0x188f +#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_CNTL 0x1890 +#define regRMI_SCOREBOARD_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS0 0x1891 +#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS1 0x1892 +#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS2 0x1893 +#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG 0x1894 +#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG_1 0x1895 +#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 1 +#define regRMI_CLOCK_CNTRL 0x1896 +#define regRMI_CLOCK_CNTRL_BASE_IDX 1 +#define regRMI_UTCL1_STATUS 0x1897 +#define regRMI_UTCL1_STATUS_BASE_IDX 1 +#define regRMI_RB_GLX_CID_MAP 0x1898 +#define regRMI_RB_GLX_CID_MAP_BASE_IDX 1 +#define regRMI_SPARE 0x189f +#define regRMI_SPARE_BASE_IDX 1 +#define regRMI_SPARE_1 0x18a0 +#define regRMI_SPARE_1_BASE_IDX 1 +#define regRMI_SPARE_2 0x18a1 +#define regRMI_SPARE_2_BASE_IDX 1 +#define regCC_RMI_REDUNDANCY 0x18a2 +#define regCC_RMI_REDUNDANCY_BASE_IDX 1 + + +// addressBlock: gc_pmmdec +// base address: 0x9f80 +#define regGCR_PIO_CNTL 0x1580 +#define regGCR_PIO_CNTL_BASE_IDX 0 +#define regGCR_PIO_DATA 0x1581 +#define regGCR_PIO_DATA_BASE_IDX 0 +#define regPMM_CNTL 0x1582 +#define regPMM_CNTL_BASE_IDX 0 +#define regPMM_STATUS 0x1583 +#define regPMM_STATUS_BASE_IDX 0 + + +// addressBlock: gc_utcl1dec +// base address: 0x9fb0 +#define regUTCL1_CTRL_1 0x158c +#define regUTCL1_CTRL_1_BASE_IDX 0 +#define regUTCL1_ALOG 0x158f +#define regUTCL1_ALOG_BASE_IDX 0 +#define regUTCL1_STATUS 0x1594 +#define regUTCL1_STATUS_BASE_IDX 0 + + +// addressBlock: gc_gcvmsharedpfdec +// base address: 0xa000 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x15a4 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x15a5 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x15a6 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 +#define regGCMC_VM_FB_OFFSET 0x15a7 +#define regGCMC_VM_FB_OFFSET_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x15a8 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x15a9 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regGCMC_VM_STEERING 0x15aa +#define regGCMC_VM_STEERING_BASE_IDX 0 +#define regGCMC_MEM_POWER_LS 0x15ac +#define regGCMC_MEM_POWER_LS_BASE_IDX 0 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x15ad +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x15ae +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x15af +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x15b0 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 +#define regGCMC_VM_APT_CNTL 0x15b1 +#define regGCMC_VM_APT_CNTL_BASE_IDX 0 +#define regGCMC_VM_LOCAL_FB_ADDRESS_START 0x15b2 +#define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 +#define regGCMC_VM_LOCAL_FB_ADDRESS_END 0x15b3 +#define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x15b4 +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 +#define regGCUTCL2_ICG_CTRL 0x15b5 +#define regGCUTCL2_ICG_CTRL_BASE_IDX 0 +#define regGCUTCL2_CGTT_BUSY_CTRL 0x15b7 +#define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCMC_VM_FB_NOALLOC_CNTL 0x15b8 +#define regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS 0x15b9 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 +#define regGCUTCL2_GROUP_RET_FAULT_STATUS 0x15bb +#define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 + + +// addressBlock: gc_gcvml2pfdec +// base address: 0xa070 +#define regGCVM_L2_CNTL 0x15bc +#define regGCVM_L2_CNTL_BASE_IDX 0 +#define regGCVM_L2_CNTL2 0x15bd +#define regGCVM_L2_CNTL2_BASE_IDX 0 +#define regGCVM_L2_CNTL3 0x15be +#define regGCVM_L2_CNTL3_BASE_IDX 0 +#define regGCVM_L2_STATUS 0x15bf +#define regGCVM_L2_STATUS_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL 0x15c0 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15c1 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15c2 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_CNTL 0x15c3 +#define regGCVM_INVALIDATE_CNTL_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL 0x15c4 +#define regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL2 0x15c5 +#define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15c6 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15c7 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_STATUS 0x15c8 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15c9 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15ca +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15cb +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15d0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15d1 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15d2 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15d3 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regGCVM_L2_CNTL4 0x15d4 +#define regGCVM_L2_CNTL4_BASE_IDX 0 +#define regGCVM_L2_MM_GROUP_RT_CLASSES 0x15d5 +#define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID 0x15d6 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15d7 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regGCVM_L2_CACHE_PARITY_CNTL 0x15d8 +#define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regGCVM_L2_ICG_CTRL 0x15d9 +#define regGCVM_L2_ICG_CTRL_BASE_IDX 0 +#define regGCVM_L2_CNTL5 0x15da +#define regGCVM_L2_CNTL5_BASE_IDX 0 +#define regGCVM_L2_GCR_CNTL 0x15db +#define regGCVM_L2_GCR_CNTL_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME 0x15dc +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x15dd +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME 0x15de +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x15df +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVM_L2_CGTT_BUSY_CTRL 0x15e0 +#define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL 0x15e1 +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_READ 0x15e2 +#define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x15e5 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x15e6 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x15e7 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x15e8 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_MASKS 0x15e9 +#define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x15ea +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x15eb +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x15ec +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x15ed +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x15ee +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 + + +// addressBlock: gc_gcvmsharedvcdec +// base address: 0xa360 +#define regGCMC_VM_FB_LOCATION_BASE 0x1678 +#define regGCMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_TOP 0x1679 +#define regGCMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define regGCMC_VM_AGP_TOP 0x167a +#define regGCMC_VM_AGP_TOP_BASE_IDX 0 +#define regGCMC_VM_AGP_BOT 0x167b +#define regGCMC_VM_AGP_BOT_BASE_IDX 0 +#define regGCMC_VM_AGP_BASE 0x167c +#define regGCMC_VM_AGP_BASE_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x167d +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x167e +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define regGCMC_VM_MX_L1_TLB_CNTL 0x167f +#define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: gc_gcvml2vcdec +// base address: 0xa3a0 +#define regGCVM_CONTEXT0_CNTL 0x1688 +#define regGCVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT1_CNTL 0x1689 +#define regGCVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT2_CNTL 0x168a +#define regGCVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT3_CNTL 0x168b +#define regGCVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT4_CNTL 0x168c +#define regGCVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT5_CNTL 0x168d +#define regGCVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT6_CNTL 0x168e +#define regGCVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT7_CNTL 0x168f +#define regGCVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT8_CNTL 0x1690 +#define regGCVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT9_CNTL 0x1691 +#define regGCVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT10_CNTL 0x1692 +#define regGCVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT11_CNTL 0x1693 +#define regGCVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT12_CNTL 0x1694 +#define regGCVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT13_CNTL 0x1695 +#define regGCVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT14_CNTL 0x1696 +#define regGCVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT15_CNTL 0x1697 +#define regGCVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXTS_DISABLE 0x1698 +#define regGCVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_SEM 0x1699 +#define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_SEM 0x169a +#define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_SEM 0x169b +#define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_SEM 0x169c +#define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_SEM 0x169d +#define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_SEM 0x169e +#define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_SEM 0x169f +#define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_SEM 0x16a0 +#define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_SEM 0x16a1 +#define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_SEM 0x16a2 +#define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_SEM 0x16a3 +#define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_SEM 0x16a4 +#define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_SEM 0x16a5 +#define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_SEM 0x16a6 +#define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_SEM 0x16a7 +#define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_SEM 0x16a8 +#define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_SEM 0x16a9 +#define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_SEM 0x16aa +#define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_REQ 0x16ab +#define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_REQ 0x16ac +#define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_REQ 0x16ad +#define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_REQ 0x16ae +#define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_REQ 0x16af +#define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_REQ 0x16b0 +#define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_REQ 0x16b1 +#define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_REQ 0x16b2 +#define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_REQ 0x16b3 +#define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_REQ 0x16b4 +#define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_REQ 0x16b5 +#define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_REQ 0x16b6 +#define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_REQ 0x16b7 +#define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_REQ 0x16b8 +#define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_REQ 0x16b9 +#define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_REQ 0x16ba +#define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_REQ 0x16bb +#define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_REQ 0x16bc +#define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ACK 0x16bd +#define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ACK 0x16be +#define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ACK 0x16bf +#define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ACK 0x16c0 +#define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ACK 0x16c1 +#define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ACK 0x16c2 +#define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ACK 0x16c3 +#define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ACK 0x16c4 +#define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ACK 0x16c5 +#define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ACK 0x16c6 +#define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ACK 0x16c7 +#define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ACK 0x16c8 +#define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ACK 0x16c9 +#define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ACK 0x16ca +#define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ACK 0x16cb +#define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ACK 0x16cc +#define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ACK 0x16cd +#define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ACK 0x16ce +#define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x16cf +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x16d0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x16d1 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x16d2 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x16d3 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x16d4 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x16d5 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x16d6 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x16d7 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x16d8 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x16d9 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x16da +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x16db +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x16dc +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x16dd +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x16de +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x16df +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x16e0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x16e1 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x16e2 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x16e3 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x16e4 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x16e5 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x16e6 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x16e7 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x16e8 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x16e9 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x16ea +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x16eb +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x16ec +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x16ed +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x16ee +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x16ef +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x16f0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x16f1 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x16f2 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x16f3 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x16f4 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x16f5 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x16f6 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x16f7 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x16f8 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x16f9 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x16fa +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x16fb +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x16fc +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x16fd +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x16fe +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x16ff +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x1700 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x1701 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x1702 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x1703 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x1704 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x1705 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x1706 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x1707 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x1708 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x1709 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x170a +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x170b +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x170c +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x170d +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x170e +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x170f +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x1710 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x1711 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x1712 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x1713 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x1714 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x1715 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x1716 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x1717 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x1718 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x1719 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x171a +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x171b +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x171c +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x171d +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x171e +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x171f +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x1720 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x1721 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x1722 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x1723 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x1724 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x1725 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x1726 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x1727 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x1728 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x1729 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x172a +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x172b +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x172c +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x172d +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x172e +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x172f +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x1730 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x1731 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x1732 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x1733 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x1734 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x1735 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x1736 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x1737 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x1738 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x1739 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x173a +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x173b +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x173c +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x173d +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x173e +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x173f +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x1740 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x1741 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x1742 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x1743 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x1744 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x1745 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x1746 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x1747 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x1748 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x1749 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x174a +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x174b +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x174c +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x174d +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x174e +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x174f +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x1750 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x1751 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x1752 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1753 +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1754 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1755 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1756 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1757 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1758 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1759 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175a +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175b +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175c +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175d +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175e +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175f +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1760 +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1761 +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1762 +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1763 +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 + + +// addressBlock: gc_gcvml2perfddec +// base address: 0x35380 +#define regGCVML2_PERFCOUNTER2_0_LO 0x34e0 +#define regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_LO 0x34e1 +#define regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_0_HI 0x34e2 +#define regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_HI 0x34e3 +#define regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX 1 + + +// addressBlock: gc_gcvml2prdec +// base address: 0x35390 +#define regGCMC_VM_L2_PERFCOUNTER_LO 0x34e4 +#define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_HI 0x34e5 +#define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_LO 0x34e6 +#define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_HI 0x34e7 +#define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_gcvml2perfsdec +// base address: 0x37480 +#define regGCVML2_PERFCOUNTER2_0_SELECT 0x3d20 +#define regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_SELECT 0x3d21 +#define regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_0_SELECT1 0x3d22 +#define regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_SELECT1 0x3d23 +#define regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_0_MODE 0x3d24 +#define regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX 1 +#define regGCVML2_PERFCOUNTER2_1_MODE 0x3d25 +#define regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX 1 + + +// addressBlock: gc_gcvml2pldec +// base address: 0x374c0 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG 0x3d30 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG 0x3d31 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG 0x3d32 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG 0x3d33 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG 0x3d34 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG 0x3d35 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG 0x3d36 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG 0x3d37 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d38 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER0_CFG 0x3d39 +#define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER1_CFG 0x3d3a +#define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER2_CFG 0x3d3b +#define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER3_CFG 0x3d3c +#define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL 0x3d3d +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_gcvmsharedhvdec +// base address: 0x3ea00 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 +#define regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 +#define regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 +#define regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 +#define regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a +#define regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b +#define regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c +#define regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d +#define regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e +#define regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f +#define regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 + + +// addressBlock: gc_gcvml2pspdec +// base address: 0x3f900 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0x5e41 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x5e44 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_0 0x5e48 +#define regGCMC_VM_MARC_BASE_LO_0_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_1 0x5e49 +#define regGCMC_VM_MARC_BASE_LO_1_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_2 0x5e4a +#define regGCMC_VM_MARC_BASE_LO_2_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_3 0x5e4b +#define regGCMC_VM_MARC_BASE_LO_3_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_4 0x5e4c +#define regGCMC_VM_MARC_BASE_LO_4_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_5 0x5e4d +#define regGCMC_VM_MARC_BASE_LO_5_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_6 0x5e4e +#define regGCMC_VM_MARC_BASE_LO_6_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_7 0x5e4f +#define regGCMC_VM_MARC_BASE_LO_7_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_8 0x5e50 +#define regGCMC_VM_MARC_BASE_LO_8_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_9 0x5e51 +#define regGCMC_VM_MARC_BASE_LO_9_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_10 0x5e52 +#define regGCMC_VM_MARC_BASE_LO_10_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_11 0x5e53 +#define regGCMC_VM_MARC_BASE_LO_11_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_12 0x5e54 +#define regGCMC_VM_MARC_BASE_LO_12_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_13 0x5e55 +#define regGCMC_VM_MARC_BASE_LO_13_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_14 0x5e56 +#define regGCMC_VM_MARC_BASE_LO_14_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_LO_15 0x5e57 +#define regGCMC_VM_MARC_BASE_LO_15_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_0 0x5e58 +#define regGCMC_VM_MARC_BASE_HI_0_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_1 0x5e59 +#define regGCMC_VM_MARC_BASE_HI_1_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_2 0x5e5a +#define regGCMC_VM_MARC_BASE_HI_2_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_3 0x5e5b +#define regGCMC_VM_MARC_BASE_HI_3_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_4 0x5e5c +#define regGCMC_VM_MARC_BASE_HI_4_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_5 0x5e5d +#define regGCMC_VM_MARC_BASE_HI_5_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_6 0x5e5e +#define regGCMC_VM_MARC_BASE_HI_6_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_7 0x5e5f +#define regGCMC_VM_MARC_BASE_HI_7_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_8 0x5e60 +#define regGCMC_VM_MARC_BASE_HI_8_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_9 0x5e61 +#define regGCMC_VM_MARC_BASE_HI_9_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_10 0x5e62 +#define regGCMC_VM_MARC_BASE_HI_10_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_11 0x5e63 +#define regGCMC_VM_MARC_BASE_HI_11_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_12 0x5e64 +#define regGCMC_VM_MARC_BASE_HI_12_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_13 0x5e65 +#define regGCMC_VM_MARC_BASE_HI_13_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_14 0x5e66 +#define regGCMC_VM_MARC_BASE_HI_14_BASE_IDX 1 +#define regGCMC_VM_MARC_BASE_HI_15 0x5e67 +#define regGCMC_VM_MARC_BASE_HI_15_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_0 0x5e68 +#define regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_1 0x5e69 +#define regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_2 0x5e6a +#define regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_3 0x5e6b +#define regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_4 0x5e6c +#define regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_5 0x5e6d +#define regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_6 0x5e6e +#define regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_7 0x5e6f +#define regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_8 0x5e70 +#define regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_9 0x5e71 +#define regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_10 0x5e72 +#define regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_11 0x5e73 +#define regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_12 0x5e74 +#define regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_13 0x5e75 +#define regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_14 0x5e76 +#define regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_LO_15 0x5e77 +#define regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_0 0x5e78 +#define regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_1 0x5e79 +#define regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_2 0x5e7a +#define regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_3 0x5e7b +#define regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_4 0x5e7c +#define regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_5 0x5e7d +#define regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_6 0x5e7e +#define regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_7 0x5e7f +#define regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_8 0x5e80 +#define regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_9 0x5e81 +#define regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_10 0x5e82 +#define regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_11 0x5e83 +#define regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_12 0x5e84 +#define regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_13 0x5e85 +#define regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_14 0x5e86 +#define regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX 1 +#define regGCMC_VM_MARC_RELOC_HI_15 0x5e87 +#define regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_0 0x5e88 +#define regGCMC_VM_MARC_LEN_LO_0_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_1 0x5e89 +#define regGCMC_VM_MARC_LEN_LO_1_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_2 0x5e8a +#define regGCMC_VM_MARC_LEN_LO_2_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_3 0x5e8b +#define regGCMC_VM_MARC_LEN_LO_3_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_4 0x5e8c +#define regGCMC_VM_MARC_LEN_LO_4_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_5 0x5e8d +#define regGCMC_VM_MARC_LEN_LO_5_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_6 0x5e8e +#define regGCMC_VM_MARC_LEN_LO_6_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_7 0x5e8f +#define regGCMC_VM_MARC_LEN_LO_7_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_8 0x5e90 +#define regGCMC_VM_MARC_LEN_LO_8_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_9 0x5e91 +#define regGCMC_VM_MARC_LEN_LO_9_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_10 0x5e92 +#define regGCMC_VM_MARC_LEN_LO_10_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_11 0x5e93 +#define regGCMC_VM_MARC_LEN_LO_11_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_12 0x5e94 +#define regGCMC_VM_MARC_LEN_LO_12_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_13 0x5e95 +#define regGCMC_VM_MARC_LEN_LO_13_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_14 0x5e96 +#define regGCMC_VM_MARC_LEN_LO_14_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_LO_15 0x5e97 +#define regGCMC_VM_MARC_LEN_LO_15_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_0 0x5e98 +#define regGCMC_VM_MARC_LEN_HI_0_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_1 0x5e99 +#define regGCMC_VM_MARC_LEN_HI_1_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_2 0x5e9a +#define regGCMC_VM_MARC_LEN_HI_2_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_3 0x5e9b +#define regGCMC_VM_MARC_LEN_HI_3_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_4 0x5e9c +#define regGCMC_VM_MARC_LEN_HI_4_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_5 0x5e9d +#define regGCMC_VM_MARC_LEN_HI_5_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_6 0x5e9e +#define regGCMC_VM_MARC_LEN_HI_6_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_7 0x5e9f +#define regGCMC_VM_MARC_LEN_HI_7_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_8 0x5ea0 +#define regGCMC_VM_MARC_LEN_HI_8_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_9 0x5ea1 +#define regGCMC_VM_MARC_LEN_HI_9_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_10 0x5ea2 +#define regGCMC_VM_MARC_LEN_HI_10_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_11 0x5ea3 +#define regGCMC_VM_MARC_LEN_HI_11_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_12 0x5ea4 +#define regGCMC_VM_MARC_LEN_HI_12_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_13 0x5ea5 +#define regGCMC_VM_MARC_LEN_HI_13_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_14 0x5ea6 +#define regGCMC_VM_MARC_LEN_HI_14_BASE_IDX 1 +#define regGCMC_VM_MARC_LEN_HI_15 0x5ea7 +#define regGCMC_VM_MARC_LEN_HI_15_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_0 0x5ea8 +#define regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_1 0x5ea9 +#define regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_2 0x5eaa +#define regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_3 0x5eab +#define regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_4 0x5eac +#define regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_5 0x5ead +#define regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_6 0x5eae +#define regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_7 0x5eaf +#define regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_8 0x5eb0 +#define regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_9 0x5eb1 +#define regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_10 0x5eb2 +#define regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_11 0x5eb3 +#define regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_12 0x5eb4 +#define regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_13 0x5eb5 +#define regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_14 0x5eb6 +#define regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX 1 +#define regGCMC_VM_MARC_PFVF_MAPPING_15 0x5eb7 +#define regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL0 0x5eb8 +#define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL1 0x5eb9 +#define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 + + +// addressBlock: gc_shdec +// base address: 0xb000 +#define regSPI_SHADER_PGM_RSRC4_PS 0x19a1 +#define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_PS 0x19a6 +#define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_PS 0x19a7 +#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_PS 0x19a8 +#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_PS 0x19a9 +#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_PS 0x19aa +#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_PS 0x19ab +#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_0 0x19ac +#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_1 0x19ad +#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_2 0x19ae +#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_3 0x19af +#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_4 0x19b0 +#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_5 0x19b1 +#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_6 0x19b2 +#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_7 0x19b3 +#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_8 0x19b4 +#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_9 0x19b5 +#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_10 0x19b6 +#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_11 0x19b7 +#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_12 0x19b8 +#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_13 0x19b9 +#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_14 0x19ba +#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_15 0x19bb +#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_16 0x19bc +#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_17 0x19bd +#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_18 0x19be +#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_19 0x19bf +#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_20 0x19c0 +#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_21 0x19c1 +#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_22 0x19c2 +#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_23 0x19c3 +#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_24 0x19c4 +#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_25 0x19c5 +#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_26 0x19c6 +#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_27 0x19c7 +#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_28 0x19c8 +#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_29 0x19c9 +#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_30 0x19ca +#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_31 0x19cb +#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_PS 0x19d0 +#define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_0 0x19d2 +#define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_1 0x19d3 +#define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_2 0x19d4 +#define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_3 0x19d5 +#define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_GS 0x1a20 +#define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_GS 0x1a21 +#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES_GS 0x1a24 +#define regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES_GS 0x1a25 +#define regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_GS 0x1a27 +#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_GS 0x1a28 +#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_GS 0x1a29 +#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_GS 0x1a2a +#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS 0x1a2b +#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_0 0x1a2c +#define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_1 0x1a2d +#define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_2 0x1a2e +#define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_3 0x1a2f +#define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_4 0x1a30 +#define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_5 0x1a31 +#define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_6 0x1a32 +#define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_7 0x1a33 +#define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_8 0x1a34 +#define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_9 0x1a35 +#define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_10 0x1a36 +#define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_11 0x1a37 +#define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_12 0x1a38 +#define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_13 0x1a39 +#define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_14 0x1a3a +#define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_15 0x1a3b +#define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_16 0x1a3c +#define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_17 0x1a3d +#define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_18 0x1a3e +#define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_19 0x1a3f +#define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_20 0x1a40 +#define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_21 0x1a41 +#define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_22 0x1a42 +#define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_23 0x1a43 +#define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_24 0x1a44 +#define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_25 0x1a45 +#define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_26 0x1a46 +#define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_27 0x1a47 +#define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_28 0x1a48 +#define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_29 0x1a49 +#define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_30 0x1a4a +#define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_31 0x1a4b +#define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_DIM 0x1a4c +#define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC 0x1a4d +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_ESGS 0x1a50 +#define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52 +#define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53 +#define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54 +#define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55 +#define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES 0x1a68 +#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES 0x1a69 +#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_HS 0x1aa0 +#define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_HS 0x1aa1 +#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS_HS 0x1aa4 +#define regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS_HS 0x1aa5 +#define regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_HS 0x1aa7 +#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_HS 0x1aa8 +#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_HS 0x1aa9 +#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_HS 0x1aaa +#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_HS 0x1aab +#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_0 0x1aac +#define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_1 0x1aad +#define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_2 0x1aae +#define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_3 0x1aaf +#define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_4 0x1ab0 +#define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_5 0x1ab1 +#define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_6 0x1ab2 +#define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_7 0x1ab3 +#define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_8 0x1ab4 +#define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_9 0x1ab5 +#define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_10 0x1ab6 +#define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_11 0x1ab7 +#define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_12 0x1ab8 +#define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_13 0x1ab9 +#define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_14 0x1aba +#define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_15 0x1abb +#define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_16 0x1abc +#define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_17 0x1abd +#define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_18 0x1abe +#define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_19 0x1abf +#define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_20 0x1ac0 +#define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_21 0x1ac1 +#define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_22 0x1ac2 +#define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_23 0x1ac3 +#define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_24 0x1ac4 +#define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_25 0x1ac5 +#define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_26 0x1ac6 +#define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_27 0x1ac7 +#define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_28 0x1ac8 +#define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_29 0x1ac9 +#define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_30 0x1aca +#define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_31 0x1acb +#define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_LSHS 0x1ad0 +#define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2 +#define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3 +#define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4 +#define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5 +#define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS 0x1ae8 +#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS 0x1ae9 +#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INITIATOR 0x1ba0 +#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 +#define regCOMPUTE_DIM_X 0x1ba1 +#define regCOMPUTE_DIM_X_BASE_IDX 0 +#define regCOMPUTE_DIM_Y 0x1ba2 +#define regCOMPUTE_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_DIM_Z 0x1ba3 +#define regCOMPUTE_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_START_X 0x1ba4 +#define regCOMPUTE_START_X_BASE_IDX 0 +#define regCOMPUTE_START_Y 0x1ba5 +#define regCOMPUTE_START_Y_BASE_IDX 0 +#define regCOMPUTE_START_Z 0x1ba6 +#define regCOMPUTE_START_Z_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_X 0x1ba7 +#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Y 0x1ba8 +#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Z 0x1ba9 +#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 +#define regCOMPUTE_PIPELINESTAT_ENABLE 0x1baa +#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PERFCOUNT_ENABLE 0x1bab +#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PGM_LO 0x1bac +#define regCOMPUTE_PGM_LO_BASE_IDX 0 +#define regCOMPUTE_PGM_HI 0x1bad +#define regCOMPUTE_PGM_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC1 0x1bb2 +#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC2 0x1bb3 +#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 +#define regCOMPUTE_VMID 0x1bb4 +#define regCOMPUTE_VMID_BASE_IDX 0 +#define regCOMPUTE_RESOURCE_LIMITS 0x1bb5 +#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE0 0x1bb6 +#define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bb6 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE1 0x1bb7 +#define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bb7 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 +#define regCOMPUTE_TMPRING_SIZE 0x1bb8 +#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE2 0x1bb9 +#define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bb9 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE3 0x1bba +#define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bba +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 +#define regCOMPUTE_RESTART_X 0x1bbb +#define regCOMPUTE_RESTART_X_BASE_IDX 0 +#define regCOMPUTE_RESTART_Y 0x1bbc +#define regCOMPUTE_RESTART_Y_BASE_IDX 0 +#define regCOMPUTE_RESTART_Z 0x1bbd +#define regCOMPUTE_RESTART_Z_BASE_IDX 0 +#define regCOMPUTE_THREAD_TRACE_ENABLE 0x1bbe +#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 +#define regCOMPUTE_MISC_RESERVED 0x1bbf +#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_ID 0x1bc0 +#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 +#define regCOMPUTE_THREADGROUP_ID 0x1bc1 +#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 +#define regCOMPUTE_REQ_CTRL 0x1bc2 +#define regCOMPUTE_REQ_CTRL_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_0 0x1bc4 +#define regCOMPUTE_USER_ACCUM_0_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_1 0x1bc5 +#define regCOMPUTE_USER_ACCUM_1_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_2 0x1bc6 +#define regCOMPUTE_USER_ACCUM_2_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_3 0x1bc7 +#define regCOMPUTE_USER_ACCUM_3_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC3 0x1bc8 +#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 +#define regCOMPUTE_DDID_INDEX 0x1bc9 +#define regCOMPUTE_DDID_INDEX_BASE_IDX 0 +#define regCOMPUTE_SHADER_CHKSUM 0x1bca +#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x1bcb +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x1bcc +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x1bcd +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x1bce +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INTERLEAVE 0x1bcf +#define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH 0x1bd0 +#define regCOMPUTE_RELAUNCH_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1bd1 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1bd2 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH2 0x1bd3 +#define regCOMPUTE_RELAUNCH2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_0 0x1be0 +#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_1 0x1be1 +#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_2 0x1be2 +#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_3 0x1be3 +#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_4 0x1be4 +#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_5 0x1be5 +#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_6 0x1be6 +#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_7 0x1be7 +#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_8 0x1be8 +#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_9 0x1be9 +#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_10 0x1bea +#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_11 0x1beb +#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_12 0x1bec +#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_13 0x1bed +#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_14 0x1bee +#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_15 0x1bef +#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_TUNNEL 0x1c1d +#define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_END 0x1c1e +#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 +#define regCOMPUTE_NOWHERE 0x1c1f +#define regCOMPUTE_NOWHERE_BASE_IDX 0 +#define regSH_RESERVED_REG0 0x1c20 +#define regSH_RESERVED_REG0_BASE_IDX 0 +#define regSH_RESERVED_REG1 0x1c21 +#define regSH_RESERVED_REG1_BASE_IDX 0 + + +// addressBlock: gc_cppdec +// base address: 0xc080 +#define regCP_CU_MASK_ADDR_LO 0x1dd2 +#define regCP_CU_MASK_ADDR_LO_BASE_IDX 0 +#define regCP_CU_MASK_ADDR_HI 0x1dd3 +#define regCP_CU_MASK_ADDR_HI_BASE_IDX 0 +#define regCP_CU_MASK_CNTL 0x1dd4 +#define regCP_CU_MASK_CNTL_BASE_IDX 0 +#define regCP_EOPQ_WAIT_TIME 0x1dd5 +#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 +#define regCP_CPC_MGCG_SYNC_CNTL 0x1dd6 +#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 +#define regCPC_INT_INFO 0x1dd7 +#define regCPC_INT_INFO_BASE_IDX 0 +#define regCP_VIRT_STATUS 0x1dd8 +#define regCP_VIRT_STATUS_BASE_IDX 0 +#define regCPC_INT_ADDR 0x1dd9 +#define regCPC_INT_ADDR_BASE_IDX 0 +#define regCPC_INT_PASID 0x1dda +#define regCPC_INT_PASID_BASE_IDX 0 +#define regCP_GFX_ERROR 0x1ddb +#define regCP_GFX_ERROR_BASE_IDX 0 +#define regCPG_UTCL1_CNTL 0x1ddc +#define regCPG_UTCL1_CNTL_BASE_IDX 0 +#define regCPC_UTCL1_CNTL 0x1ddd +#define regCPC_UTCL1_CNTL_BASE_IDX 0 +#define regCPF_UTCL1_CNTL 0x1dde +#define regCPF_UTCL1_CNTL_BASE_IDX 0 +#define regCP_AQL_SMM_STATUS 0x1ddf +#define regCP_AQL_SMM_STATUS_BASE_IDX 0 +#define regCP_RB0_BASE 0x1de0 +#define regCP_RB0_BASE_BASE_IDX 0 +#define regCP_RB_BASE 0x1de0 +#define regCP_RB_BASE_BASE_IDX 0 +#define regCP_RB0_CNTL 0x1de1 +#define regCP_RB0_CNTL_BASE_IDX 0 +#define regCP_RB_CNTL 0x1de1 +#define regCP_RB_CNTL_BASE_IDX 0 +#define regCP_RB_RPTR_WR 0x1de2 +#define regCP_RB_RPTR_WR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR 0x1de3 +#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR 0x1de3 +#define regCP_RB_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR_HI 0x1de4 +#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR_HI 0x1de4 +#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_BUFSZ_MASK 0x1de5 +#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_BUFSZ_MASK 0x1de5 +#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 +#define regCP_INT_CNTL 0x1de9 +#define regCP_INT_CNTL_BASE_IDX 0 +#define regCP_INT_STATUS 0x1dea +#define regCP_INT_STATUS_BASE_IDX 0 +#define regCP_DEVICE_ID 0x1deb +#define regCP_DEVICE_ID_BASE_IDX 0 +#define regCP_ME0_PIPE_PRIORITY_CNTS 0x1dec +#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_RING_PRIORITY_CNTS 0x1dec +#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME0_PIPE0_PRIORITY 0x1ded +#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_RING0_PRIORITY 0x1ded +#define regCP_RING0_PRIORITY_BASE_IDX 0 +#define regCP_ME0_PIPE1_PRIORITY 0x1dee +#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_RING1_PRIORITY 0x1dee +#define regCP_RING1_PRIORITY_BASE_IDX 0 +#define regCP_FATAL_ERROR 0x1df0 +#define regCP_FATAL_ERROR_BASE_IDX 0 +#define regCP_RB_VMID 0x1df1 +#define regCP_RB_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE0_VMID 0x1df2 +#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE1_VMID 0x1df3 +#define regCP_ME0_PIPE1_VMID_BASE_IDX 0 +#define regCP_RB0_WPTR 0x1df4 +#define regCP_RB0_WPTR_BASE_IDX 0 +#define regCP_RB_WPTR 0x1df4 +#define regCP_RB_WPTR_BASE_IDX 0 +#define regCP_RB0_WPTR_HI 0x1df5 +#define regCP_RB0_WPTR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_HI 0x1df5 +#define regCP_RB_WPTR_HI_BASE_IDX 0 +#define regCP_RB1_WPTR 0x1df6 +#define regCP_RB1_WPTR_BASE_IDX 0 +#define regCP_RB1_WPTR_HI 0x1df7 +#define regCP_RB1_WPTR_HI_BASE_IDX 0 +#define regCP_PROCESS_QUANTUM 0x1df9 +#define regCP_PROCESS_QUANTUM_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_LOWER 0x1dfa +#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_UPPER 0x1dfb +#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc +#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd +#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCPG_UTCL1_ERROR 0x1dfe +#define regCPG_UTCL1_ERROR_BASE_IDX 0 +#define regCPC_UTCL1_ERROR 0x1dff +#define regCPC_UTCL1_ERROR_BASE_IDX 0 +#define regCP_RB1_BASE 0x1e00 +#define regCP_RB1_BASE_BASE_IDX 0 +#define regCP_RB1_CNTL 0x1e01 +#define regCP_RB1_CNTL_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR 0x1e02 +#define regCP_RB1_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR_HI 0x1e03 +#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB1_BUFSZ_MASK 0x1e04 +#define regCP_RB1_BUFSZ_MASK_BASE_IDX 0 +#define regCP_INT_CNTL_RING0 0x1e0a +#define regCP_INT_CNTL_RING0_BASE_IDX 0 +#define regCP_INT_CNTL_RING1 0x1e0b +#define regCP_INT_CNTL_RING1_BASE_IDX 0 +#define regCP_INT_STATUS_RING0 0x1e0d +#define regCP_INT_STATUS_RING0_BASE_IDX 0 +#define regCP_INT_STATUS_RING1 0x1e0e +#define regCP_INT_STATUS_RING1_BASE_IDX 0 +#define regCP_ME_F32_INTERRUPT 0x1e13 +#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PFP_F32_INTERRUPT 0x1e14 +#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC1_F32_INTERRUPT 0x1e16 +#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC2_F32_INTERRUPT 0x1e17 +#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PWR_CNTL 0x1e18 +#define regCP_PWR_CNTL_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE 0x1e1a +#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b +#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING1 0x1e1c +#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 +#define regGB_EDC_MODE 0x1e1e +#define regGB_EDC_MODE_BASE_IDX 0 +#define regCP_DEBUG 0x1e1f +#define regCP_DEBUG_BASE_IDX 0 +#define regCP_CPC_DEBUG 0x1e21 +#define regCP_CPC_DEBUG_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL 0x1e23 +#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL1 0x1e24 +#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_CNTL 0x1e25 +#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_CNTL 0x1e26 +#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_CNTL 0x1e27 +#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_CNTL 0x1e28 +#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_CNTL 0x1e29 +#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_CNTL 0x1e2a +#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_CNTL 0x1e2b +#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_CNTL 0x1e2c +#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_STATUS 0x1e2d +#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_STATUS 0x1e2e +#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_STATUS 0x1e2f +#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_STATUS 0x1e30 +#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_STATUS 0x1e31 +#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_STATUS 0x1e32 +#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_STATUS 0x1e33 +#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_STATUS 0x1e34 +#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_GFX_QUEUE_INDEX 0x1e37 +#define regCP_GFX_QUEUE_INDEX_BASE_IDX 0 +#define regCC_GC_EDC_CONFIG 0x1e38 +#define regCC_GC_EDC_CONFIG_BASE_IDX 0 +#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1e39 +#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME1_PIPE0_PRIORITY 0x1e3a +#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE1_PRIORITY 0x1e3b +#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE2_PRIORITY 0x1e3c +#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE3_PRIORITY 0x1e3d +#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE_PRIORITY_CNTS 0x1e3e +#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME2_PIPE0_PRIORITY 0x1e3f +#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE1_PRIORITY 0x1e40 +#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE2_PRIORITY 0x1e41 +#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE3_PRIORITY 0x1e42 +#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START 0x1e44 +#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START 0x1e45 +#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC1_PRGRM_CNTR_START 0x1e46 +#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC2_PRGRM_CNTR_START 0x1e47 +#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START 0x1e49 +#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START 0x1e4a +#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC1_INTR_ROUTINE_START 0x1e4b +#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC2_INTR_ROUTINE_START 0x1e4c +#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_CONTEXT_CNTL 0x1e4d +#define regCP_CONTEXT_CNTL_BASE_IDX 0 +#define regCP_MAX_CONTEXT 0x1e4e +#define regCP_MAX_CONTEXT_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME1 0x1e4f +#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME2 0x1e50 +#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 +#define regCP_RB0_BASE_HI 0x1e51 +#define regCP_RB0_BASE_HI_BASE_IDX 0 +#define regCP_RB1_BASE_HI 0x1e52 +#define regCP_RB1_BASE_HI_BASE_IDX 0 +#define regCP_VMID_RESET 0x1e53 +#define regCP_VMID_RESET_BASE_IDX 0 +#define regCPC_INT_CNTL 0x1e54 +#define regCPC_INT_CNTL_BASE_IDX 0 +#define regCPC_INT_STATUS 0x1e55 +#define regCPC_INT_STATUS_BASE_IDX 0 +#define regCP_VMID_PREEMPT 0x1e56 +#define regCP_VMID_PREEMPT_BASE_IDX 0 +#define regCPC_INT_CNTX_ID 0x1e57 +#define regCPC_INT_CNTX_ID_BASE_IDX 0 +#define regCP_PQ_STATUS 0x1e58 +#define regCP_PQ_STATUS_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START_HI 0x1e59 +#define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_MAX_DRAW_COUNT 0x1e5c +#define regCP_MAX_DRAW_COUNT_BASE_IDX 0 +#define regCP_MEC1_F32_INT_DIS 0x1e5d +#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 +#define regCP_MEC2_F32_INT_DIS 0x1e5e +#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 +#define regCP_VMID_STATUS 0x1e5f +#define regCP_VMID_STATUS_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64 +#define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCPC_SUSPEND_WG_STATE_OFFSET 0x1e65 +#define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66 +#define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCPC_OS_PIPES 0x1e67 +#define regCPC_OS_PIPES_BASE_IDX 0 +#define regCP_SUSPEND_RESUME_REQ 0x1e68 +#define regCP_SUSPEND_RESUME_REQ_BASE_IDX 0 +#define regCP_SUSPEND_CNTL 0x1e69 +#define regCP_SUSPEND_CNTL_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME3 0x1e6a +#define regCP_IQ_WAIT_TIME3_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_LO 0x1e6b +#define regCPC_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_LO 0x1e6b +#define regCP_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_HI 0x1e6c +#define regCPC_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_HI 0x1e6c +#define regCP_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_DDID_CNTL 0x1e6d +#define regCPC_DDID_CNTL_BASE_IDX 0 +#define regCP_DDID_CNTL 0x1e6d +#define regCP_DDID_CNTL_BASE_IDX 0 +#define regCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e +#define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_GFX_DDID_WPTR 0x1e6f +#define regCP_GFX_DDID_WPTR_BASE_IDX 0 +#define regCP_GFX_DDID_RPTR 0x1e70 +#define regCP_GFX_DDID_RPTR_BASE_IDX 0 +#define regCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71 +#define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_GFX_HPD_STATUS0 0x1e72 +#define regCP_GFX_HPD_STATUS0_BASE_IDX 0 +#define regCP_GFX_HPD_CONTROL0 0x1e73 +#define regCP_GFX_HPD_CONTROL0_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0 +#define regCP_GFX_INDEX_MUTEX 0x1e78 +#define regCP_GFX_INDEX_MUTEX_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START_HI 0x1e79 +#define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START_HI 0x1e7a +#define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START_HI 0x1e7b +#define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR 0x1e7e +#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR_HI 0x1e7f +#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_ACTIVE 0x1e80 +#define regCP_GFX_HQD_ACTIVE_BASE_IDX 0 +#define regCP_GFX_HQD_VMID 0x1e81 +#define regCP_GFX_HQD_VMID_BASE_IDX 0 +#define regCP_GFX_HQD_QUEUE_PRIORITY 0x1e84 +#define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_GFX_HQD_QUANTUM 0x1e85 +#define regCP_GFX_HQD_QUANTUM_BASE_IDX 0 +#define regCP_GFX_HQD_BASE 0x1e86 +#define regCP_GFX_HQD_BASE_BASE_IDX 0 +#define regCP_GFX_HQD_BASE_HI 0x1e87 +#define regCP_GFX_HQD_BASE_HI_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR 0x1e88 +#define regCP_GFX_HQD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR 0x1e89 +#define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a +#define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_LO 0x1e8b +#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_HI 0x1e8c +#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL 0x1e8d +#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_OFFSET 0x1e8e +#define regCP_GFX_HQD_OFFSET_BASE_IDX 0 +#define regCP_GFX_HQD_CNTL 0x1e8f +#define regCP_GFX_HQD_CNTL_BASE_IDX 0 +#define regCP_GFX_HQD_CSMD_RPTR 0x1e90 +#define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR 0x1e91 +#define regCP_GFX_HQD_WPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR_HI 0x1e92 +#define regCP_GFX_HQD_WPTR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93 +#define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_GFX_HQD_MAPPED 0x1e94 +#define regCP_GFX_HQD_MAPPED_BASE_IDX 0 +#define regCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95 +#define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_IQ_TIMER 0x1e96 +#define regCP_GFX_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_STATUS0 0x1e98 +#define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_CONTROL0 0x1e99 +#define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_GFX_MQD_CONTROL 0x1e9a +#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_CONTROL 0x1e9f +#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_STATUS 0x1ea0 +#define regCP_HQD_GFX_STATUS_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_LO 0x1ec0 +#define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_HI 0x1ec1 +#define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH0_MASK 0x1ec2 +#define regCP_DMA_WATCH0_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH0_CNTL 0x1ec3 +#define regCP_DMA_WATCH0_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_LO 0x1ec4 +#define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_HI 0x1ec5 +#define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH1_MASK 0x1ec6 +#define regCP_DMA_WATCH1_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH1_CNTL 0x1ec7 +#define regCP_DMA_WATCH1_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_LO 0x1ec8 +#define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_HI 0x1ec9 +#define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH2_MASK 0x1eca +#define regCP_DMA_WATCH2_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH2_CNTL 0x1ecb +#define regCP_DMA_WATCH2_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_LO 0x1ecc +#define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_HI 0x1ecd +#define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH3_MASK 0x1ece +#define regCP_DMA_WATCH3_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH3_CNTL 0x1ecf +#define regCP_DMA_WATCH3_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0 +#define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1 +#define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT 0x1ed2 +#define regCP_DMA_WATCH_STAT_BASE_IDX 0 +#define regCP_PFP_JT_STAT 0x1ed3 +#define regCP_PFP_JT_STAT_BASE_IDX 0 +#define regCP_MEC_JT_STAT 0x1ed5 +#define regCP_MEC_JT_STAT_BASE_IDX 0 +#define regCP_CPC_BUSY_HYSTERESIS 0x1edb +#define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS1 0x1edc +#define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS2 0x1edd +#define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS1 0x1ede +#define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS2 0x1edf +#define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCP_RB_DOORBELL_CLEAR 0x1f28 +#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 +#define regCP_RB0_ACTIVE 0x1f40 +#define regCP_RB0_ACTIVE_BASE_IDX 0 +#define regCP_RB_ACTIVE 0x1f40 +#define regCP_RB_ACTIVE_BASE_IDX 0 +#define regCP_RB1_ACTIVE 0x1f41 +#define regCP_RB1_ACTIVE_BASE_IDX 0 +#define regCP_RB_STATUS 0x1f43 +#define regCP_RB_STATUS_BASE_IDX 0 +#define regCPG_RCIU_CAM_INDEX 0x1f44 +#define regCPG_RCIU_CAM_INDEX_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA 0x1f45 +#define regCPG_RCIU_CAM_DATA_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE0 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE1 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE2 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_LO 0x1f4c +#define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_HI 0x1f4d +#define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX 0 +#define regCP_SDMA_DMA_DONE 0x1f4e +#define regCP_SDMA_DMA_DONE_BASE_IDX 0 +#define regCP_PFP_SDMA_CS 0x1f4f +#define regCP_PFP_SDMA_CS_BASE_IDX 0 +#define regCP_ME_SDMA_CS 0x1f50 +#define regCP_ME_SDMA_CS_BASE_IDX 0 +#define regCPF_GCR_CNTL 0x1f53 +#define regCPF_GCR_CNTL_BASE_IDX 0 +#define regCPG_UTCL1_STATUS 0x1f54 +#define regCPG_UTCL1_STATUS_BASE_IDX 0 +#define regCPC_UTCL1_STATUS 0x1f55 +#define regCPC_UTCL1_STATUS_BASE_IDX 0 +#define regCPF_UTCL1_STATUS 0x1f56 +#define regCPF_UTCL1_STATUS_BASE_IDX 0 +#define regCP_SD_CNTL 0x1f57 +#define regCP_SD_CNTL_BASE_IDX 0 +#define regCP_SOFT_RESET_CNTL 0x1f59 +#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 +#define regCP_CPC_GFX_CNTL 0x1f5a +#define regCP_CPC_GFX_CNTL_BASE_IDX 0 + + +// addressBlock: gc_spipdec +// base address: 0xc700 +#define regSPI_ARB_PRIORITY 0x1f60 +#define regSPI_ARB_PRIORITY_BASE_IDX 0 +#define regSPI_ARB_CYCLES_0 0x1f61 +#define regSPI_ARB_CYCLES_0_BASE_IDX 0 +#define regSPI_ARB_CYCLES_1 0x1f62 +#define regSPI_ARB_CYCLES_1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_GFX 0x1f67 +#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_HP3D 0x1f68 +#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS0 0x1f69 +#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS1 0x1f6a +#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS2 0x1f6b +#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS3 0x1f6c +#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS4 0x1f6d +#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS5 0x1f6e +#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS6 0x1f6f +#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS7 0x1f70 +#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define regSPI_USER_ACCUM_VMID_CNTL 0x1f71 +#define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0 +#define regSPI_GDBG_PER_VMID_CNTL 0x1f72 +#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 +#define regSPI_COMPUTE_QUEUE_RESET 0x1f73 +#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 +#define regSPI_COMPUTE_WF_CTX_SAVE 0x1f74 +#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 + + +// addressBlock: gc_cpphqddec +// base address: 0xc800 +#define regCP_HPD_UTCL1_CNTL 0x1fa3 +#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR 0x1fa7 +#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR_ADDR 0x1fa8 +#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR 0x1fa9 +#define regCP_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR_HI 0x1faa +#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_ACTIVE 0x1fab +#define regCP_HQD_ACTIVE_BASE_IDX 0 +#define regCP_HQD_VMID 0x1fac +#define regCP_HQD_VMID_BASE_IDX 0 +#define regCP_HQD_PERSISTENT_STATE 0x1fad +#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 +#define regCP_HQD_PIPE_PRIORITY 0x1fae +#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUEUE_PRIORITY 0x1faf +#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUANTUM 0x1fb0 +#define regCP_HQD_QUANTUM_BASE_IDX 0 +#define regCP_HQD_PQ_BASE 0x1fb1 +#define regCP_HQD_PQ_BASE_BASE_IDX 0 +#define regCP_HQD_PQ_BASE_HI 0x1fb2 +#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR 0x1fb3 +#define regCP_HQD_PQ_RPTR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 +#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_CONTROL 0x1fba +#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR 0x1fbb +#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR_HI 0x1fbc +#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_IB_RPTR 0x1fbd +#define regCP_HQD_IB_RPTR_BASE_IDX 0 +#define regCP_HQD_IB_CONTROL 0x1fbe +#define regCP_HQD_IB_CONTROL_BASE_IDX 0 +#define regCP_HQD_IQ_TIMER 0x1fbf +#define regCP_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_HQD_IQ_RPTR 0x1fc0 +#define regCP_HQD_IQ_RPTR_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 +#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_HQD_DMA_OFFLOAD 0x1fc2 +#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_OFFLOAD 0x1fc2 +#define regCP_HQD_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_SEMA_CMD 0x1fc3 +#define regCP_HQD_SEMA_CMD_BASE_IDX 0 +#define regCP_HQD_MSG_TYPE 0x1fc4 +#define regCP_HQD_MSG_TYPE_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_LO 0x1fc5 +#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_HI 0x1fc6 +#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_LO 0x1fc7 +#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_HI 0x1fc8 +#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER0 0x1fc9 +#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS0 0x1fc9 +#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL0 0x1fca +#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER1 0x1fca +#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 +#define regCP_MQD_CONTROL 0x1fcb +#define regCP_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS1 0x1fcc +#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL1 0x1fcd +#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR 0x1fce +#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR_HI 0x1fcf +#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_EOP_CONTROL 0x1fd0 +#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 +#define regCP_HQD_EOP_RPTR 0x1fd1 +#define regCP_HQD_EOP_RPTR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR 0x1fd2 +#define regCP_HQD_EOP_WPTR_BASE_IDX 0 +#define regCP_HQD_EOP_EVENTS 0x1fd3 +#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_CONTROL 0x1fd6 +#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_OFFSET 0x1fd7 +#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_SIZE 0x1fd8 +#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCP_HQD_WG_STATE_OFFSET 0x1fd9 +#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_SIZE 0x1fda +#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCP_HQD_GDS_RESOURCE_STATE 0x1fdb +#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 +#define regCP_HQD_ERROR 0x1fdc +#define regCP_HQD_ERROR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR_MEM 0x1fdd +#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL 0x1fde +#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_LO 0x1fdf +#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_HI 0x1fe0 +#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_DDID_RPTR 0x1fe4 +#define regCP_HQD_DDID_RPTR_BASE_IDX 0 +#define regCP_HQD_DDID_WPTR 0x1fe5 +#define regCP_HQD_DDID_WPTR_BASE_IDX 0 +#define regCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6 +#define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7 +#define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_STATUS 0x1fe8 +#define regCP_HQD_DEQUEUE_STATUS_BASE_IDX 0 + + +// addressBlock: gc_tcpdec +// base address: 0xca80 +#define regTCP_WATCH0_ADDR_H 0x2048 +#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH0_ADDR_L 0x2049 +#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH0_CNTL 0x204a +#define regTCP_WATCH0_CNTL_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_H 0x204b +#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_L 0x204c +#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH1_CNTL 0x204d +#define regTCP_WATCH1_CNTL_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_H 0x204e +#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_L 0x204f +#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH2_CNTL 0x2050 +#define regTCP_WATCH2_CNTL_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_H 0x2051 +#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_L 0x2052 +#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH3_CNTL 0x2053 +#define regTCP_WATCH3_CNTL_BASE_IDX 0 + + +// addressBlock: gc_gdspdec +// base address: 0xcc00 +#define regGDS_VMID0_BASE 0x20a0 +#define regGDS_VMID0_BASE_BASE_IDX 0 +#define regGDS_VMID0_SIZE 0x20a1 +#define regGDS_VMID0_SIZE_BASE_IDX 0 +#define regGDS_VMID1_BASE 0x20a2 +#define regGDS_VMID1_BASE_BASE_IDX 0 +#define regGDS_VMID1_SIZE 0x20a3 +#define regGDS_VMID1_SIZE_BASE_IDX 0 +#define regGDS_VMID2_BASE 0x20a4 +#define regGDS_VMID2_BASE_BASE_IDX 0 +#define regGDS_VMID2_SIZE 0x20a5 +#define regGDS_VMID2_SIZE_BASE_IDX 0 +#define regGDS_VMID3_BASE 0x20a6 +#define regGDS_VMID3_BASE_BASE_IDX 0 +#define regGDS_VMID3_SIZE 0x20a7 +#define regGDS_VMID3_SIZE_BASE_IDX 0 +#define regGDS_VMID4_BASE 0x20a8 +#define regGDS_VMID4_BASE_BASE_IDX 0 +#define regGDS_VMID4_SIZE 0x20a9 +#define regGDS_VMID4_SIZE_BASE_IDX 0 +#define regGDS_VMID5_BASE 0x20aa +#define regGDS_VMID5_BASE_BASE_IDX 0 +#define regGDS_VMID5_SIZE 0x20ab +#define regGDS_VMID5_SIZE_BASE_IDX 0 +#define regGDS_VMID6_BASE 0x20ac +#define regGDS_VMID6_BASE_BASE_IDX 0 +#define regGDS_VMID6_SIZE 0x20ad +#define regGDS_VMID6_SIZE_BASE_IDX 0 +#define regGDS_VMID7_BASE 0x20ae +#define regGDS_VMID7_BASE_BASE_IDX 0 +#define regGDS_VMID7_SIZE 0x20af +#define regGDS_VMID7_SIZE_BASE_IDX 0 +#define regGDS_VMID8_BASE 0x20b0 +#define regGDS_VMID8_BASE_BASE_IDX 0 +#define regGDS_VMID8_SIZE 0x20b1 +#define regGDS_VMID8_SIZE_BASE_IDX 0 +#define regGDS_VMID9_BASE 0x20b2 +#define regGDS_VMID9_BASE_BASE_IDX 0 +#define regGDS_VMID9_SIZE 0x20b3 +#define regGDS_VMID9_SIZE_BASE_IDX 0 +#define regGDS_VMID10_BASE 0x20b4 +#define regGDS_VMID10_BASE_BASE_IDX 0 +#define regGDS_VMID10_SIZE 0x20b5 +#define regGDS_VMID10_SIZE_BASE_IDX 0 +#define regGDS_VMID11_BASE 0x20b6 +#define regGDS_VMID11_BASE_BASE_IDX 0 +#define regGDS_VMID11_SIZE 0x20b7 +#define regGDS_VMID11_SIZE_BASE_IDX 0 +#define regGDS_VMID12_BASE 0x20b8 +#define regGDS_VMID12_BASE_BASE_IDX 0 +#define regGDS_VMID12_SIZE 0x20b9 +#define regGDS_VMID12_SIZE_BASE_IDX 0 +#define regGDS_VMID13_BASE 0x20ba +#define regGDS_VMID13_BASE_BASE_IDX 0 +#define regGDS_VMID13_SIZE 0x20bb +#define regGDS_VMID13_SIZE_BASE_IDX 0 +#define regGDS_VMID14_BASE 0x20bc +#define regGDS_VMID14_BASE_BASE_IDX 0 +#define regGDS_VMID14_SIZE 0x20bd +#define regGDS_VMID14_SIZE_BASE_IDX 0 +#define regGDS_VMID15_BASE 0x20be +#define regGDS_VMID15_BASE_BASE_IDX 0 +#define regGDS_VMID15_SIZE 0x20bf +#define regGDS_VMID15_SIZE_BASE_IDX 0 +#define regGDS_GWS_VMID0 0x20c0 +#define regGDS_GWS_VMID0_BASE_IDX 0 +#define regGDS_GWS_VMID1 0x20c1 +#define regGDS_GWS_VMID1_BASE_IDX 0 +#define regGDS_GWS_VMID2 0x20c2 +#define regGDS_GWS_VMID2_BASE_IDX 0 +#define regGDS_GWS_VMID3 0x20c3 +#define regGDS_GWS_VMID3_BASE_IDX 0 +#define regGDS_GWS_VMID4 0x20c4 +#define regGDS_GWS_VMID4_BASE_IDX 0 +#define regGDS_GWS_VMID5 0x20c5 +#define regGDS_GWS_VMID5_BASE_IDX 0 +#define regGDS_GWS_VMID6 0x20c6 +#define regGDS_GWS_VMID6_BASE_IDX 0 +#define regGDS_GWS_VMID7 0x20c7 +#define regGDS_GWS_VMID7_BASE_IDX 0 +#define regGDS_GWS_VMID8 0x20c8 +#define regGDS_GWS_VMID8_BASE_IDX 0 +#define regGDS_GWS_VMID9 0x20c9 +#define regGDS_GWS_VMID9_BASE_IDX 0 +#define regGDS_GWS_VMID10 0x20ca +#define regGDS_GWS_VMID10_BASE_IDX 0 +#define regGDS_GWS_VMID11 0x20cb +#define regGDS_GWS_VMID11_BASE_IDX 0 +#define regGDS_GWS_VMID12 0x20cc +#define regGDS_GWS_VMID12_BASE_IDX 0 +#define regGDS_GWS_VMID13 0x20cd +#define regGDS_GWS_VMID13_BASE_IDX 0 +#define regGDS_GWS_VMID14 0x20ce +#define regGDS_GWS_VMID14_BASE_IDX 0 +#define regGDS_GWS_VMID15 0x20cf +#define regGDS_GWS_VMID15_BASE_IDX 0 +#define regGDS_OA_VMID0 0x20d0 +#define regGDS_OA_VMID0_BASE_IDX 0 +#define regGDS_OA_VMID1 0x20d1 +#define regGDS_OA_VMID1_BASE_IDX 0 +#define regGDS_OA_VMID2 0x20d2 +#define regGDS_OA_VMID2_BASE_IDX 0 +#define regGDS_OA_VMID3 0x20d3 +#define regGDS_OA_VMID3_BASE_IDX 0 +#define regGDS_OA_VMID4 0x20d4 +#define regGDS_OA_VMID4_BASE_IDX 0 +#define regGDS_OA_VMID5 0x20d5 +#define regGDS_OA_VMID5_BASE_IDX 0 +#define regGDS_OA_VMID6 0x20d6 +#define regGDS_OA_VMID6_BASE_IDX 0 +#define regGDS_OA_VMID7 0x20d7 +#define regGDS_OA_VMID7_BASE_IDX 0 +#define regGDS_OA_VMID8 0x20d8 +#define regGDS_OA_VMID8_BASE_IDX 0 +#define regGDS_OA_VMID9 0x20d9 +#define regGDS_OA_VMID9_BASE_IDX 0 +#define regGDS_OA_VMID10 0x20da +#define regGDS_OA_VMID10_BASE_IDX 0 +#define regGDS_OA_VMID11 0x20db +#define regGDS_OA_VMID11_BASE_IDX 0 +#define regGDS_OA_VMID12 0x20dc +#define regGDS_OA_VMID12_BASE_IDX 0 +#define regGDS_OA_VMID13 0x20dd +#define regGDS_OA_VMID13_BASE_IDX 0 +#define regGDS_OA_VMID14 0x20de +#define regGDS_OA_VMID14_BASE_IDX 0 +#define regGDS_OA_VMID15 0x20df +#define regGDS_OA_VMID15_BASE_IDX 0 +#define regGDS_GWS_RESET0 0x20e4 +#define regGDS_GWS_RESET0_BASE_IDX 0 +#define regGDS_GWS_RESET1 0x20e5 +#define regGDS_GWS_RESET1_BASE_IDX 0 +#define regGDS_GWS_RESOURCE_RESET 0x20e6 +#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 +#define regGDS_COMPUTE_MAX_WAVE_ID 0x20e8 +#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 +#define regGDS_OA_RESET_MASK 0x20e9 +#define regGDS_OA_RESET_MASK_BASE_IDX 0 +#define regGDS_OA_RESET 0x20ea +#define regGDS_OA_RESET_BASE_IDX 0 +#define regGDS_CS_CTXSW_STATUS 0x20ed +#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT0 0x20ee +#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT1 0x20ef +#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT2 0x20f0 +#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT3 0x20f1 +#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_GFX_CTXSW_STATUS 0x20f2 +#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT0 0x20f7 +#define regGDS_PS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT1 0x20f8 +#define regGDS_PS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT2 0x20f9 +#define regGDS_PS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS_CTXSW_CNT3 0x20fa +#define regGDS_PS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS_CTXSW_IDX 0x20fb +#define regGDS_PS_CTXSW_IDX_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT0 0x2117 +#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT1 0x2118 +#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT2 0x2119 +#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT3 0x211a +#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_MEMORY_CLEAN 0x211f +#define regGDS_MEMORY_CLEAN_BASE_IDX 0 + + +// addressBlock: gc_gusdec +// base address: 0x33000 +#define regGUS_IO_RD_COMBINE_FLUSH 0x2c00 +#define regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define regGUS_IO_WR_COMBINE_FLUSH 0x2c01 +#define regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define regGUS_IO_RD_PRI_AGE_RATE 0x2c02 +#define regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX 1 +#define regGUS_IO_WR_PRI_AGE_RATE 0x2c03 +#define regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX 1 +#define regGUS_IO_RD_PRI_AGE_COEFF 0x2c04 +#define regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX 1 +#define regGUS_IO_WR_PRI_AGE_COEFF 0x2c05 +#define regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUEUING 0x2c06 +#define regGUS_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUEUING 0x2c07 +#define regGUS_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define regGUS_IO_RD_PRI_FIXED 0x2c08 +#define regGUS_IO_RD_PRI_FIXED_BASE_IDX 1 +#define regGUS_IO_WR_PRI_FIXED 0x2c09 +#define regGUS_IO_WR_PRI_FIXED_BASE_IDX 1 +#define regGUS_IO_RD_PRI_URGENCY_COEFF 0x2c0a +#define regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX 1 +#define regGUS_IO_WR_PRI_URGENCY_COEFF 0x2c0b +#define regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX 1 +#define regGUS_IO_RD_PRI_URGENCY_MODE 0x2c0c +#define regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX 1 +#define regGUS_IO_WR_PRI_URGENCY_MODE 0x2c0d +#define regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI1 0x2c0e +#define regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI2 0x2c0f +#define regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI3 0x2c10 +#define regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT_PRI4 0x2c11 +#define regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI1 0x2c12 +#define regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI2 0x2c13 +#define regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI3 0x2c14 +#define regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT_PRI4 0x2c15 +#define regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI1 0x2c16 +#define regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI2 0x2c17 +#define regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI3 0x2c18 +#define regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX 1 +#define regGUS_IO_RD_PRI_QUANT1_PRI4 0x2c19 +#define regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI1 0x2c1a +#define regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI2 0x2c1b +#define regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI3 0x2c1c +#define regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX 1 +#define regGUS_IO_WR_PRI_QUANT1_PRI4 0x2c1d +#define regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX 1 +#define regGUS_DRAM_COMBINE_FLUSH 0x2c1e +#define regGUS_DRAM_COMBINE_FLUSH_BASE_IDX 1 +#define regGUS_DRAM_COMBINE_RD_WR_EN 0x2c1f +#define regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX 1 +#define regGUS_DRAM_PRI_AGE_RATE 0x2c20 +#define regGUS_DRAM_PRI_AGE_RATE_BASE_IDX 1 +#define regGUS_DRAM_PRI_AGE_COEFF 0x2c21 +#define regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUEUING 0x2c22 +#define regGUS_DRAM_PRI_QUEUING_BASE_IDX 1 +#define regGUS_DRAM_PRI_FIXED 0x2c23 +#define regGUS_DRAM_PRI_FIXED_BASE_IDX 1 +#define regGUS_DRAM_PRI_URGENCY_COEFF 0x2c24 +#define regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX 1 +#define regGUS_DRAM_PRI_URGENCY_MODE 0x2c25 +#define regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI1 0x2c26 +#define regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI2 0x2c27 +#define regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI3 0x2c28 +#define regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI4 0x2c29 +#define regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT_PRI5 0x2c2a +#define regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI1 0x2c2b +#define regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI2 0x2c2c +#define regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI3 0x2c2d +#define regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI4 0x2c2e +#define regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX 1 +#define regGUS_DRAM_PRI_QUANT1_PRI5 0x2c2f +#define regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX 1 +#define regGUS_IO_GROUP_BURST 0x2c30 +#define regGUS_IO_GROUP_BURST_BASE_IDX 1 +#define regGUS_DRAM_GROUP_BURST 0x2c31 +#define regGUS_DRAM_GROUP_BURST_BASE_IDX 1 +#define regGUS_SDP_ARB_FINAL 0x2c32 +#define regGUS_SDP_ARB_FINAL_BASE_IDX 1 +#define regGUS_SDP_QOS_VC_PRIORITY 0x2c33 +#define regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX 1 +#define regGUS_SDP_CREDITS 0x2c34 +#define regGUS_SDP_CREDITS_BASE_IDX 1 +#define regGUS_SDP_TAG_RESERVE0 0x2c35 +#define regGUS_SDP_TAG_RESERVE0_BASE_IDX 1 +#define regGUS_SDP_TAG_RESERVE1 0x2c36 +#define regGUS_SDP_TAG_RESERVE1_BASE_IDX 1 +#define regGUS_SDP_VCC_RESERVE0 0x2c37 +#define regGUS_SDP_VCC_RESERVE0_BASE_IDX 1 +#define regGUS_SDP_VCC_RESERVE1 0x2c38 +#define regGUS_SDP_VCC_RESERVE1_BASE_IDX 1 +#define regGUS_SDP_VCD_RESERVE0 0x2c39 +#define regGUS_SDP_VCD_RESERVE0_BASE_IDX 1 +#define regGUS_SDP_VCD_RESERVE1 0x2c3a +#define regGUS_SDP_VCD_RESERVE1_BASE_IDX 1 +#define regGUS_SDP_REQ_CNTL 0x2c3b +#define regGUS_SDP_REQ_CNTL_BASE_IDX 1 +#define regGUS_MISC 0x2c3c +#define regGUS_MISC_BASE_IDX 1 +#define regGUS_LATENCY_SAMPLING 0x2c3d +#define regGUS_LATENCY_SAMPLING_BASE_IDX 1 +#define regGUS_ERR_STATUS 0x2c3e +#define regGUS_ERR_STATUS_BASE_IDX 1 +#define regGUS_MISC2 0x2c3f +#define regGUS_MISC2_BASE_IDX 1 +#define regGUS_SDP_ENABLE 0x2c45 +#define regGUS_SDP_ENABLE_BASE_IDX 1 +#define regGUS_L1_CH0_CMD_IN 0x2c46 +#define regGUS_L1_CH0_CMD_IN_BASE_IDX 1 +#define regGUS_L1_CH0_CMD_OUT 0x2c47 +#define regGUS_L1_CH0_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_IN 0x2c48 +#define regGUS_L1_CH0_DATA_IN_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_OUT 0x2c49 +#define regGUS_L1_CH0_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_U_IN 0x2c4a +#define regGUS_L1_CH0_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_CH0_DATA_U_OUT 0x2c4b +#define regGUS_L1_CH0_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_CH1_CMD_IN 0x2c4c +#define regGUS_L1_CH1_CMD_IN_BASE_IDX 1 +#define regGUS_L1_CH1_CMD_OUT 0x2c4d +#define regGUS_L1_CH1_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_IN 0x2c4e +#define regGUS_L1_CH1_DATA_IN_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_OUT 0x2c4f +#define regGUS_L1_CH1_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_U_IN 0x2c50 +#define regGUS_L1_CH1_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_CH1_DATA_U_OUT 0x2c51 +#define regGUS_L1_CH1_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA0_CMD_IN 0x2c52 +#define regGUS_L1_SA0_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA0_CMD_OUT 0x2c53 +#define regGUS_L1_SA0_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_IN 0x2c54 +#define regGUS_L1_SA0_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_OUT 0x2c55 +#define regGUS_L1_SA0_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_U_IN 0x2c56 +#define regGUS_L1_SA0_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA0_DATA_U_OUT 0x2c57 +#define regGUS_L1_SA0_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA1_CMD_IN 0x2c58 +#define regGUS_L1_SA1_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA1_CMD_OUT 0x2c59 +#define regGUS_L1_SA1_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_IN 0x2c5a +#define regGUS_L1_SA1_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_OUT 0x2c5b +#define regGUS_L1_SA1_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_U_IN 0x2c5c +#define regGUS_L1_SA1_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA1_DATA_U_OUT 0x2c5d +#define regGUS_L1_SA1_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA2_CMD_IN 0x2c5e +#define regGUS_L1_SA2_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA2_CMD_OUT 0x2c5f +#define regGUS_L1_SA2_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_IN 0x2c60 +#define regGUS_L1_SA2_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_OUT 0x2c61 +#define regGUS_L1_SA2_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_U_IN 0x2c62 +#define regGUS_L1_SA2_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA2_DATA_U_OUT 0x2c63 +#define regGUS_L1_SA2_DATA_U_OUT_BASE_IDX 1 +#define regGUS_L1_SA3_CMD_IN 0x2c64 +#define regGUS_L1_SA3_CMD_IN_BASE_IDX 1 +#define regGUS_L1_SA3_CMD_OUT 0x2c65 +#define regGUS_L1_SA3_CMD_OUT_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_IN 0x2c66 +#define regGUS_L1_SA3_DATA_IN_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_OUT 0x2c67 +#define regGUS_L1_SA3_DATA_OUT_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_U_IN 0x2c68 +#define regGUS_L1_SA3_DATA_U_IN_BASE_IDX 1 +#define regGUS_L1_SA3_DATA_U_OUT 0x2c69 +#define regGUS_L1_SA3_DATA_U_OUT_BASE_IDX 1 +#define regGUS_MISC3 0x2c6a +#define regGUS_MISC3_BASE_IDX 1 +#define regGUS_WRRSP_FIFO_CNTL 0x2c6b +#define regGUS_WRRSP_FIFO_CNTL_BASE_IDX 1 + + +// addressBlock: gc_gfxdec0 +// base address: 0x28000 +#define regDB_RENDER_CONTROL 0x0000 +#define regDB_RENDER_CONTROL_BASE_IDX 1 +#define regDB_COUNT_CONTROL 0x0001 +#define regDB_COUNT_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_VIEW 0x0002 +#define regDB_DEPTH_VIEW_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE 0x0003 +#define regDB_RENDER_OVERRIDE_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE2 0x0004 +#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE 0x0005 +#define regDB_HTILE_DATA_BASE_BASE_IDX 1 +#define regDB_DEPTH_SIZE_XY 0x0007 +#define regDB_DEPTH_SIZE_XY_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MIN 0x0008 +#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MAX 0x0009 +#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 +#define regDB_STENCIL_CLEAR 0x000a +#define regDB_STENCIL_CLEAR_BASE_IDX 1 +#define regDB_DEPTH_CLEAR 0x000b +#define regDB_DEPTH_CLEAR_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_TL 0x000c +#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_BR 0x000d +#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 +#define regDB_RESERVED_REG_2 0x000f +#define regDB_RESERVED_REG_2_BASE_IDX 1 +#define regDB_Z_INFO 0x0010 +#define regDB_Z_INFO_BASE_IDX 1 +#define regDB_STENCIL_INFO 0x0011 +#define regDB_STENCIL_INFO_BASE_IDX 1 +#define regDB_Z_READ_BASE 0x0012 +#define regDB_Z_READ_BASE_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE 0x0013 +#define regDB_STENCIL_READ_BASE_BASE_IDX 1 +#define regDB_Z_WRITE_BASE 0x0014 +#define regDB_Z_WRITE_BASE_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE 0x0015 +#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 +#define regDB_RESERVED_REG_1 0x0016 +#define regDB_RESERVED_REG_1_BASE_IDX 1 +#define regDB_RESERVED_REG_3 0x0017 +#define regDB_RESERVED_REG_3_BASE_IDX 1 +#define regDB_Z_READ_BASE_HI 0x001a +#define regDB_Z_READ_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE_HI 0x001b +#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 +#define regDB_Z_WRITE_BASE_HI 0x001c +#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE_HI 0x001d +#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE_HI 0x001e +#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 +#define regDB_RMI_L2_CACHE_CONTROL 0x001f +#define regDB_RMI_L2_CACHE_CONTROL_BASE_IDX 1 +#define regTA_BC_BASE_ADDR 0x0020 +#define regTA_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_BC_BASE_ADDR_HI 0x0021 +#define regTA_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_0 0x007a +#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_1 0x007b +#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_2 0x007c +#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_3 0x007d +#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_2 0x007e +#define regCOHER_DEST_BASE_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_3 0x007f +#define regCOHER_DEST_BASE_3_BASE_IDX 1 +#define regPA_SC_WINDOW_OFFSET 0x0080 +#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 +#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 +#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_RULE 0x0083 +#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_TL 0x0084 +#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_BR 0x0085 +#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_TL 0x0086 +#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_BR 0x0087 +#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_TL 0x0088 +#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_BR 0x0089 +#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_TL 0x008a +#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_BR 0x008b +#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 +#define regPA_SC_EDGERULE 0x008c +#define regPA_SC_EDGERULE_BASE_IDX 1 +#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d +#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 +#define regCB_TARGET_MASK 0x008e +#define regCB_TARGET_MASK_BASE_IDX 1 +#define regCB_SHADER_MASK 0x008f +#define regCB_SHADER_MASK_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 +#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 +#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 +#define regCOHER_DEST_BASE_0 0x0092 +#define regCOHER_DEST_BASE_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_1 0x0093 +#define regCOHER_DEST_BASE_1_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 +#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 +#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 +#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 +#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 +#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 +#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a +#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b +#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c +#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d +#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e +#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f +#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 +#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 +#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 +#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 +#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 +#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 +#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 +#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 +#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 +#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 +#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa +#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab +#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac +#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad +#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae +#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af +#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 +#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 +#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 +#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 +#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_0 0x00b4 +#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_0 0x00b5 +#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_1 0x00b6 +#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_1 0x00b7 +#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_2 0x00b8 +#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_2 0x00b9 +#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_3 0x00ba +#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_3 0x00bb +#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_4 0x00bc +#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_4 0x00bd +#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_5 0x00be +#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_5 0x00bf +#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_6 0x00c0 +#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_6 0x00c1 +#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_7 0x00c2 +#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_7 0x00c3 +#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_8 0x00c4 +#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_8 0x00c5 +#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_9 0x00c6 +#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_9 0x00c7 +#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_10 0x00c8 +#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_10 0x00c9 +#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_11 0x00ca +#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_11 0x00cb +#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_12 0x00cc +#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_12 0x00cd +#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_13 0x00ce +#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_13 0x00cf +#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_14 0x00d0 +#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_14 0x00d1 +#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_15 0x00d2 +#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_15 0x00d3 +#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG 0x00d4 +#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG_1 0x00d5 +#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 +#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 +#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 +#define regCP_PERFMON_CNTX_CNTL 0x00d8 +#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 +#define regCP_PIPEID 0x00d9 +#define regCP_PIPEID_BASE_IDX 1 +#define regCP_RINGID 0x00d9 +#define regCP_RINGID_BASE_IDX 1 +#define regCP_VMID 0x00da +#define regCP_VMID_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG0 0x00db +#define regCONTEXT_RESERVED_REG0_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG1 0x00dc +#define regCONTEXT_RESERVED_REG1_BASE_IDX 1 +#define regPA_SC_VRS_OVERRIDE_CNTL 0x00f4 +#define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE 0x00f5 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT 0x00f6 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY 0x00f7 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX 1 +#define regPA_SC_VRS_RATE_CACHE_CNTL 0x00f9 +#define regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE 0x00fc +#define regPA_SC_VRS_RATE_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE_EXT 0x00fd +#define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_SIZE_XY 0x00fe +#define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 +#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 +#define regCB_RMI_GL2_CACHE_CONTROL 0x0104 +#define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1 +#define regCB_BLEND_RED 0x0105 +#define regCB_BLEND_RED_BASE_IDX 1 +#define regCB_BLEND_GREEN 0x0106 +#define regCB_BLEND_GREEN_BASE_IDX 1 +#define regCB_BLEND_BLUE 0x0107 +#define regCB_BLEND_BLUE_BASE_IDX 1 +#define regCB_BLEND_ALPHA 0x0108 +#define regCB_BLEND_ALPHA_BASE_IDX 1 +#define regCB_FDCC_CONTROL 0x0109 +#define regCB_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COVERAGE_OUT_CONTROL 0x010a +#define regCB_COVERAGE_OUT_CONTROL_BASE_IDX 1 +#define regDB_STENCIL_CONTROL 0x010b +#define regDB_STENCIL_CONTROL_BASE_IDX 1 +#define regDB_STENCILREFMASK 0x010c +#define regDB_STENCILREFMASK_BASE_IDX 1 +#define regDB_STENCILREFMASK_BF 0x010d +#define regDB_STENCILREFMASK_BF_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE 0x010f +#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET 0x0110 +#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE 0x0111 +#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET 0x0112 +#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE 0x0113 +#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET 0x0114 +#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_1 0x0115 +#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_1 0x0116 +#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_1 0x0117 +#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_1 0x0118 +#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_1 0x0119 +#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_1 0x011a +#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_2 0x011b +#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_2 0x011c +#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_2 0x011d +#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_2 0x011e +#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_2 0x011f +#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_2 0x0120 +#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_3 0x0121 +#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_3 0x0122 +#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_3 0x0123 +#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_3 0x0124 +#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_3 0x0125 +#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_3 0x0126 +#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_4 0x0127 +#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_4 0x0128 +#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_4 0x0129 +#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_4 0x012a +#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_4 0x012b +#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_4 0x012c +#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_5 0x012d +#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_5 0x012e +#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_5 0x012f +#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_5 0x0130 +#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_5 0x0131 +#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_5 0x0132 +#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_6 0x0133 +#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_6 0x0134 +#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_6 0x0135 +#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_6 0x0136 +#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_6 0x0137 +#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_6 0x0138 +#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_7 0x0139 +#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_7 0x013a +#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_7 0x013b +#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_7 0x013c +#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_7 0x013d +#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_7 0x013e +#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_8 0x013f +#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_8 0x0140 +#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_8 0x0141 +#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_8 0x0142 +#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_8 0x0143 +#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_8 0x0144 +#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_9 0x0145 +#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_9 0x0146 +#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_9 0x0147 +#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_9 0x0148 +#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_9 0x0149 +#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_9 0x014a +#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_10 0x014b +#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_10 0x014c +#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_10 0x014d +#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_10 0x014e +#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_10 0x014f +#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_10 0x0150 +#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_11 0x0151 +#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_11 0x0152 +#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_11 0x0153 +#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_11 0x0154 +#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_11 0x0155 +#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_11 0x0156 +#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_12 0x0157 +#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_12 0x0158 +#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_12 0x0159 +#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_12 0x015a +#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_12 0x015b +#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_12 0x015c +#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_13 0x015d +#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_13 0x015e +#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_13 0x015f +#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_13 0x0160 +#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_13 0x0161 +#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_13 0x0162 +#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_14 0x0163 +#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_14 0x0164 +#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_14 0x0165 +#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_14 0x0166 +#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_14 0x0167 +#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_14 0x0168 +#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_15 0x0169 +#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_15 0x016a +#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_15 0x016b +#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_15 0x016c +#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_15 0x016d +#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_15 0x016e +#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 +#define regPA_CL_UCP_0_X 0x016f +#define regPA_CL_UCP_0_X_BASE_IDX 1 +#define regPA_CL_UCP_0_Y 0x0170 +#define regPA_CL_UCP_0_Y_BASE_IDX 1 +#define regPA_CL_UCP_0_Z 0x0171 +#define regPA_CL_UCP_0_Z_BASE_IDX 1 +#define regPA_CL_UCP_0_W 0x0172 +#define regPA_CL_UCP_0_W_BASE_IDX 1 +#define regPA_CL_UCP_1_X 0x0173 +#define regPA_CL_UCP_1_X_BASE_IDX 1 +#define regPA_CL_UCP_1_Y 0x0174 +#define regPA_CL_UCP_1_Y_BASE_IDX 1 +#define regPA_CL_UCP_1_Z 0x0175 +#define regPA_CL_UCP_1_Z_BASE_IDX 1 +#define regPA_CL_UCP_1_W 0x0176 +#define regPA_CL_UCP_1_W_BASE_IDX 1 +#define regPA_CL_UCP_2_X 0x0177 +#define regPA_CL_UCP_2_X_BASE_IDX 1 +#define regPA_CL_UCP_2_Y 0x0178 +#define regPA_CL_UCP_2_Y_BASE_IDX 1 +#define regPA_CL_UCP_2_Z 0x0179 +#define regPA_CL_UCP_2_Z_BASE_IDX 1 +#define regPA_CL_UCP_2_W 0x017a +#define regPA_CL_UCP_2_W_BASE_IDX 1 +#define regPA_CL_UCP_3_X 0x017b +#define regPA_CL_UCP_3_X_BASE_IDX 1 +#define regPA_CL_UCP_3_Y 0x017c +#define regPA_CL_UCP_3_Y_BASE_IDX 1 +#define regPA_CL_UCP_3_Z 0x017d +#define regPA_CL_UCP_3_Z_BASE_IDX 1 +#define regPA_CL_UCP_3_W 0x017e +#define regPA_CL_UCP_3_W_BASE_IDX 1 +#define regPA_CL_UCP_4_X 0x017f +#define regPA_CL_UCP_4_X_BASE_IDX 1 +#define regPA_CL_UCP_4_Y 0x0180 +#define regPA_CL_UCP_4_Y_BASE_IDX 1 +#define regPA_CL_UCP_4_Z 0x0181 +#define regPA_CL_UCP_4_Z_BASE_IDX 1 +#define regPA_CL_UCP_4_W 0x0182 +#define regPA_CL_UCP_4_W_BASE_IDX 1 +#define regPA_CL_UCP_5_X 0x0183 +#define regPA_CL_UCP_5_X_BASE_IDX 1 +#define regPA_CL_UCP_5_Y 0x0184 +#define regPA_CL_UCP_5_Y_BASE_IDX 1 +#define regPA_CL_UCP_5_Z 0x0185 +#define regPA_CL_UCP_5_Z_BASE_IDX 1 +#define regPA_CL_UCP_5_W 0x0186 +#define regPA_CL_UCP_5_W_BASE_IDX 1 +#define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 +#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 +#define regPA_RATE_CNTL 0x0188 +#define regPA_RATE_CNTL_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_0 0x0191 +#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_1 0x0192 +#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_2 0x0193 +#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_3 0x0194 +#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_4 0x0195 +#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_5 0x0196 +#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_6 0x0197 +#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_7 0x0198 +#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_8 0x0199 +#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_9 0x019a +#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_10 0x019b +#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_11 0x019c +#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_12 0x019d +#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_13 0x019e +#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_14 0x019f +#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_15 0x01a0 +#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_16 0x01a1 +#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_17 0x01a2 +#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_18 0x01a3 +#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_19 0x01a4 +#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_20 0x01a5 +#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_21 0x01a6 +#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_22 0x01a7 +#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_23 0x01a8 +#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_24 0x01a9 +#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_25 0x01aa +#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_26 0x01ab +#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_27 0x01ac +#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_28 0x01ad +#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_29 0x01ae +#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_30 0x01af +#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_31 0x01b0 +#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 +#define regSPI_VS_OUT_CONFIG 0x01b1 +#define regSPI_VS_OUT_CONFIG_BASE_IDX 1 +#define regSPI_PS_INPUT_ENA 0x01b3 +#define regSPI_PS_INPUT_ENA_BASE_IDX 1 +#define regSPI_PS_INPUT_ADDR 0x01b4 +#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 +#define regSPI_INTERP_CONTROL_0 0x01b5 +#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 +#define regSPI_PS_IN_CONTROL 0x01b6 +#define regSPI_PS_IN_CONTROL_BASE_IDX 1 +#define regSPI_BARYC_CNTL 0x01b8 +#define regSPI_BARYC_CNTL_BASE_IDX 1 +#define regSPI_TMPRING_SIZE 0x01ba +#define regSPI_TMPRING_SIZE_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_LO 0x01bb +#define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_HI 0x01bc +#define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX 1 +#define regSPI_SHADER_IDX_FORMAT 0x01c2 +#define regSPI_SHADER_IDX_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_POS_FORMAT 0x01c3 +#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_Z_FORMAT 0x01c4 +#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_COL_FORMAT 0x01c5 +#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT_CONTROL 0x01d4 +#define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT 0x01d5 +#define regSX_PS_DOWNCONVERT_BASE_IDX 1 +#define regSX_BLEND_OPT_EPSILON 0x01d6 +#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 +#define regSX_BLEND_OPT_CONTROL 0x01d7 +#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 +#define regSX_MRT0_BLEND_OPT 0x01d8 +#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT1_BLEND_OPT 0x01d9 +#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT2_BLEND_OPT 0x01da +#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT3_BLEND_OPT 0x01db +#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT4_BLEND_OPT 0x01dc +#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT5_BLEND_OPT 0x01dd +#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT6_BLEND_OPT 0x01de +#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT7_BLEND_OPT 0x01df +#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 +#define regCB_BLEND0_CONTROL 0x01e0 +#define regCB_BLEND0_CONTROL_BASE_IDX 1 +#define regCB_BLEND1_CONTROL 0x01e1 +#define regCB_BLEND1_CONTROL_BASE_IDX 1 +#define regCB_BLEND2_CONTROL 0x01e2 +#define regCB_BLEND2_CONTROL_BASE_IDX 1 +#define regCB_BLEND3_CONTROL 0x01e3 +#define regCB_BLEND3_CONTROL_BASE_IDX 1 +#define regCB_BLEND4_CONTROL 0x01e4 +#define regCB_BLEND4_CONTROL_BASE_IDX 1 +#define regCB_BLEND5_CONTROL 0x01e5 +#define regCB_BLEND5_CONTROL_BASE_IDX 1 +#define regCB_BLEND6_CONTROL 0x01e6 +#define regCB_BLEND6_CONTROL_BASE_IDX 1 +#define regCB_BLEND7_CONTROL 0x01e7 +#define regCB_BLEND7_CONTROL_BASE_IDX 1 +#define regGFX_COPY_STATE 0x01f4 +#define regGFX_COPY_STATE_BASE_IDX 1 +#define regPA_CL_POINT_X_RAD 0x01f5 +#define regPA_CL_POINT_X_RAD_BASE_IDX 1 +#define regPA_CL_POINT_Y_RAD 0x01f6 +#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 +#define regPA_CL_POINT_SIZE 0x01f7 +#define regPA_CL_POINT_SIZE_BASE_IDX 1 +#define regPA_CL_POINT_CULL_RAD 0x01f8 +#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 +#define regVGT_DMA_BASE_HI 0x01f9 +#define regVGT_DMA_BASE_HI_BASE_IDX 1 +#define regVGT_DMA_BASE 0x01fa +#define regVGT_DMA_BASE_BASE_IDX 1 +#define regVGT_DRAW_INITIATOR 0x01fc +#define regVGT_DRAW_INITIATOR_BASE_IDX 1 +#define regVGT_EVENT_ADDRESS_REG 0x01fe +#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 +#define regGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff +#define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1 +#define regDB_DEPTH_CONTROL 0x0200 +#define regDB_DEPTH_CONTROL_BASE_IDX 1 +#define regDB_EQAA 0x0201 +#define regDB_EQAA_BASE_IDX 1 +#define regCB_COLOR_CONTROL 0x0202 +#define regCB_COLOR_CONTROL_BASE_IDX 1 +#define regDB_SHADER_CONTROL 0x0203 +#define regDB_SHADER_CONTROL_BASE_IDX 1 +#define regPA_CL_CLIP_CNTL 0x0204 +#define regPA_CL_CLIP_CNTL_BASE_IDX 1 +#define regPA_SU_SC_MODE_CNTL 0x0205 +#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 +#define regPA_CL_VTE_CNTL 0x0206 +#define regPA_CL_VTE_CNTL_BASE_IDX 1 +#define regPA_CL_VS_OUT_CNTL 0x0207 +#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 +#define regPA_CL_NANINF_CNTL 0x0208 +#define regPA_CL_NANINF_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 +#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_SCALE 0x020a +#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 +#define regPA_SU_PRIM_FILTER_CNTL 0x020b +#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c +#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_CL_NGG_CNTL 0x020e +#define regPA_CL_NGG_CNTL_BASE_IDX 1 +#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f +#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_STEREO_CNTL 0x0210 +#define regPA_STEREO_CNTL_BASE_IDX 1 +#define regPA_STATE_STEREO_X 0x0211 +#define regPA_STATE_STEREO_X_BASE_IDX 1 +#define regPA_CL_VRS_CNTL 0x0212 +#define regPA_CL_VRS_CNTL_BASE_IDX 1 +#define regPA_SU_POINT_SIZE 0x0280 +#define regPA_SU_POINT_SIZE_BASE_IDX 1 +#define regPA_SU_POINT_MINMAX 0x0281 +#define regPA_SU_POINT_MINMAX_BASE_IDX 1 +#define regPA_SU_LINE_CNTL 0x0282 +#define regPA_SU_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE 0x0283 +#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 +#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 +#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 +#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_0 0x0292 +#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_1 0x0293 +#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 +#define regVGT_ENHANCE 0x0294 +#define regVGT_ENHANCE_BASE_IDX 1 +#define regIA_ENHANCE 0x029c +#define regIA_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_SIZE 0x029d +#define regVGT_DMA_SIZE_BASE_IDX 1 +#define regVGT_DMA_MAX_SIZE 0x029e +#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 +#define regVGT_DMA_INDEX_TYPE 0x029f +#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 +#define regWD_ENHANCE 0x02a0 +#define regWD_ENHANCE_BASE_IDX 1 +#define regVGT_PRIMITIVEID_EN 0x02a1 +#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 +#define regVGT_DMA_NUM_INSTANCES 0x02a2 +#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_PRIMITIVEID_RESET 0x02a3 +#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 +#define regVGT_EVENT_INITIATOR 0x02a4 +#define regVGT_EVENT_INITIATOR_BASE_IDX 1 +#define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 +#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 +#define regVGT_ESGS_RING_ITEMSIZE 0x02ab +#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 +#define regVGT_REUSE_OFF 0x02ad +#define regVGT_REUSE_OFF_BASE_IDX 1 +#define regDB_HTILE_SURFACE 0x02af +#define regDB_HTILE_SURFACE_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 +#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 +#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 +#define regDB_PRELOAD_CONTROL 0x02b2 +#define regDB_PRELOAD_CONTROL_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 +#define regVGT_GS_MAX_VERT_OUT 0x02ce +#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 +#define regGE_NGG_SUBGRP_CNTL 0x02d3 +#define regGE_NGG_SUBGRP_CNTL_BASE_IDX 1 +#define regVGT_TESS_DISTRIBUTION 0x02d4 +#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 +#define regVGT_SHADER_STAGES_EN 0x02d5 +#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 +#define regVGT_LS_HS_CONFIG 0x02d6 +#define regVGT_LS_HS_CONFIG_BASE_IDX 1 +#define regVGT_TF_PARAM 0x02db +#define regVGT_TF_PARAM_BASE_IDX 1 +#define regDB_ALPHA_TO_MASK 0x02dc +#define regDB_ALPHA_TO_MASK_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_CLAMP 0x02df +#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 +#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 +#define regVGT_GS_INSTANCE_CNT 0x02e4 +#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_0 0x02f5 +#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_1 0x02f6 +#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 +#define regPA_SC_LINE_CNTL 0x02f7 +#define regPA_SC_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_AA_CONFIG 0x02f8 +#define regPA_SC_AA_CONFIG_BASE_IDX 1 +#define regPA_SU_VTX_CNTL 0x02f9 +#define regPA_SU_VTX_CNTL_BASE_IDX 1 +#define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa +#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_VERT_DISC_ADJ 0x02fb +#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc +#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd +#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e +#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f +#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 +#define regPA_SC_SHADER_CONTROL 0x0310 +#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_0 0x0311 +#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_1 0x0312 +#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_SC_NGG_MODE_CNTL 0x0314 +#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_2 0x0315 +#define regPA_SC_BINNER_CNTL_2_BASE_IDX 1 +#define regCB_COLOR0_BASE 0x0318 +#define regCB_COLOR0_BASE_BASE_IDX 1 +#define regCB_COLOR0_VIEW 0x031b +#define regCB_COLOR0_VIEW_BASE_IDX 1 +#define regCB_COLOR0_INFO 0x031c +#define regCB_COLOR0_INFO_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB 0x031d +#define regCB_COLOR0_ATTRIB_BASE_IDX 1 +#define regCB_COLOR0_FDCC_CONTROL 0x031e +#define regCB_COLOR0_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE 0x0325 +#define regCB_COLOR0_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR1_BASE 0x0327 +#define regCB_COLOR1_BASE_BASE_IDX 1 +#define regCB_COLOR1_VIEW 0x032a +#define regCB_COLOR1_VIEW_BASE_IDX 1 +#define regCB_COLOR1_INFO 0x032b +#define regCB_COLOR1_INFO_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB 0x032c +#define regCB_COLOR1_ATTRIB_BASE_IDX 1 +#define regCB_COLOR1_FDCC_CONTROL 0x032d +#define regCB_COLOR1_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE 0x0334 +#define regCB_COLOR1_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR2_BASE 0x0336 +#define regCB_COLOR2_BASE_BASE_IDX 1 +#define regCB_COLOR2_VIEW 0x0339 +#define regCB_COLOR2_VIEW_BASE_IDX 1 +#define regCB_COLOR2_INFO 0x033a +#define regCB_COLOR2_INFO_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB 0x033b +#define regCB_COLOR2_ATTRIB_BASE_IDX 1 +#define regCB_COLOR2_FDCC_CONTROL 0x033c +#define regCB_COLOR2_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE 0x0343 +#define regCB_COLOR2_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR3_BASE 0x0345 +#define regCB_COLOR3_BASE_BASE_IDX 1 +#define regCB_COLOR3_VIEW 0x0348 +#define regCB_COLOR3_VIEW_BASE_IDX 1 +#define regCB_COLOR3_INFO 0x0349 +#define regCB_COLOR3_INFO_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB 0x034a +#define regCB_COLOR3_ATTRIB_BASE_IDX 1 +#define regCB_COLOR3_FDCC_CONTROL 0x034b +#define regCB_COLOR3_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE 0x0352 +#define regCB_COLOR3_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR4_BASE 0x0354 +#define regCB_COLOR4_BASE_BASE_IDX 1 +#define regCB_COLOR4_VIEW 0x0357 +#define regCB_COLOR4_VIEW_BASE_IDX 1 +#define regCB_COLOR4_INFO 0x0358 +#define regCB_COLOR4_INFO_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB 0x0359 +#define regCB_COLOR4_ATTRIB_BASE_IDX 1 +#define regCB_COLOR4_FDCC_CONTROL 0x035a +#define regCB_COLOR4_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE 0x0361 +#define regCB_COLOR4_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR5_BASE 0x0363 +#define regCB_COLOR5_BASE_BASE_IDX 1 +#define regCB_COLOR5_VIEW 0x0366 +#define regCB_COLOR5_VIEW_BASE_IDX 1 +#define regCB_COLOR5_INFO 0x0367 +#define regCB_COLOR5_INFO_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB 0x0368 +#define regCB_COLOR5_ATTRIB_BASE_IDX 1 +#define regCB_COLOR5_FDCC_CONTROL 0x0369 +#define regCB_COLOR5_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE 0x0370 +#define regCB_COLOR5_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR6_BASE 0x0372 +#define regCB_COLOR6_BASE_BASE_IDX 1 +#define regCB_COLOR6_VIEW 0x0375 +#define regCB_COLOR6_VIEW_BASE_IDX 1 +#define regCB_COLOR6_INFO 0x0376 +#define regCB_COLOR6_INFO_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB 0x0377 +#define regCB_COLOR6_ATTRIB_BASE_IDX 1 +#define regCB_COLOR6_FDCC_CONTROL 0x0378 +#define regCB_COLOR6_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE 0x037f +#define regCB_COLOR6_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR7_BASE 0x0381 +#define regCB_COLOR7_BASE_BASE_IDX 1 +#define regCB_COLOR7_VIEW 0x0384 +#define regCB_COLOR7_VIEW_BASE_IDX 1 +#define regCB_COLOR7_INFO 0x0385 +#define regCB_COLOR7_INFO_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB 0x0386 +#define regCB_COLOR7_ATTRIB_BASE_IDX 1 +#define regCB_COLOR7_FDCC_CONTROL 0x0387 +#define regCB_COLOR7_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE 0x038e +#define regCB_COLOR7_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR0_BASE_EXT 0x0390 +#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_BASE_EXT 0x0391 +#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_BASE_EXT 0x0392 +#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_BASE_EXT 0x0393 +#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_BASE_EXT 0x0394 +#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_BASE_EXT 0x0395 +#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_BASE_EXT 0x0396 +#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_BASE_EXT 0x0397 +#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE_EXT 0x03a8 +#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE_EXT 0x03a9 +#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE_EXT 0x03aa +#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE_EXT 0x03ab +#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE_EXT 0x03ac +#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE_EXT 0x03ad +#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE_EXT 0x03ae +#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE_EXT 0x03af +#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB2 0x03b0 +#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB2 0x03b1 +#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB2 0x03b2 +#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB2 0x03b3 +#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB2 0x03b4 +#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB2 0x03b5 +#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB2 0x03b6 +#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB2 0x03b7 +#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB3 0x03b8 +#define regCB_COLOR0_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB3 0x03b9 +#define regCB_COLOR1_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB3 0x03ba +#define regCB_COLOR2_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB3 0x03bb +#define regCB_COLOR3_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB3 0x03bc +#define regCB_COLOR4_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB3 0x03bd +#define regCB_COLOR5_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB3 0x03be +#define regCB_COLOR6_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB3 0x03bf +#define regCB_COLOR7_ATTRIB3_BASE_IDX 1 + + +// addressBlock: gc_pfvf_cpdec +// base address: 0x2a000 +#define regCONFIG_RESERVED_REG0 0x0800 +#define regCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regCONFIG_RESERVED_REG1 0x0801 +#define regCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_MEC_CNTL 0x0802 +#define regCP_MEC_CNTL_BASE_IDX 1 +#define regCP_ME_CNTL 0x0803 +#define regCP_ME_CNTL_BASE_IDX 1 + + +// addressBlock: gc_pfvf_grbmdec +// base address: 0x2a400 +#define regGRBM_GFX_CNTL 0x0900 +#define regGRBM_GFX_CNTL_BASE_IDX 1 +#define regGRBM_NOWHERE 0x0901 +#define regGRBM_NOWHERE_BASE_IDX 1 + + +// addressBlock: gc_pfvf_padec +// base address: 0x2a500 +#define regPA_SC_VRS_SURFACE_CNTL 0x0940 +#define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_ENHANCE 0x0941 +#define regPA_SC_ENHANCE_BASE_IDX 1 +#define regPA_SC_ENHANCE_1 0x0942 +#define regPA_SC_ENHANCE_1_BASE_IDX 1 +#define regPA_SC_ENHANCE_2 0x0943 +#define regPA_SC_ENHANCE_2_BASE_IDX 1 +#define regPA_SC_ENHANCE_3 0x0944 +#define regPA_SC_ENHANCE_3_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_OVERRIDE 0x0946 +#define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 1 +#define regPA_SC_PBB_OVERRIDE_FLAG 0x0947 +#define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 1 +#define regPA_SC_DSM_CNTL 0x0948 +#define regPA_SC_DSM_CNTL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x0949 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 1 +#define regPA_SC_FIFO_SIZE 0x094a +#define regPA_SC_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_IF_FIFO_SIZE 0x094b +#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_PACKER_WAVE_ID_CNTL 0x094c +#define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX 1 +#define regPA_SC_ATM_CNTL 0x094d +#define regPA_SC_ATM_CNTL_BASE_IDX 1 +#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x094e +#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 1 +#define regPA_SC_FORCE_EOV_MAX_CNTS 0x094f +#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_0 0x0950 +#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_1 0x0951 +#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_2 0x0952 +#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_3 0x0953 +#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 1 +#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x0954 +#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_0 0x0955 +#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_1 0x0956 +#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_2 0x0957 +#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_3 0x0958 +#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x095b +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x095c +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x095d +#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_PH_INTERFACE_FIFO_SIZE 0x095e +#define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 1 +#define regPA_PH_ENHANCE 0x095f +#define regPA_PH_ENHANCE_BASE_IDX 1 +#define regPA_SC_VRS_SURFACE_CNTL_1 0x0960 +#define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX 1 + + +// addressBlock: gc_pfvf_sqdec +// base address: 0x2a780 +#define regSQ_RUNTIME_CONFIG 0x09e0 +#define regSQ_RUNTIME_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL 0x09e1 +#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL2 0x09e2 +#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 1 +#define regSH_MEM_BASES 0x09e3 +#define regSH_MEM_BASES_BASE_IDX 1 +#define regSH_MEM_CONFIG 0x09e4 +#define regSH_MEM_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG 0x09e5 +#define regSQ_DEBUG_BASE_IDX 1 +#define regSQ_SHADER_TBA_LO 0x09e6 +#define regSQ_SHADER_TBA_LO_BASE_IDX 1 +#define regSQ_SHADER_TBA_HI 0x09e7 +#define regSQ_SHADER_TBA_HI_BASE_IDX 1 +#define regSQ_SHADER_TMA_LO 0x09e8 +#define regSQ_SHADER_TMA_LO_BASE_IDX 1 +#define regSQ_SHADER_TMA_HI 0x09e9 +#define regSQ_SHADER_TMA_HI_BASE_IDX 1 + + +// addressBlock: gc_pfonly_cpdec +// base address: 0x2e000 +#define regCP_DEBUG_2 0x1800 +#define regCP_DEBUG_2_BASE_IDX 1 +#define regCP_FETCHER_SOURCE 0x1801 +#define regCP_FETCHER_SOURCE_BASE_IDX 1 + + +// addressBlock: gc_pfonly_cpphqddec +// base address: 0x2e080 +#define regCP_HPD_MES_ROQ_OFFSETS 0x1821 +#define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_ROQ_OFFSETS 0x1821 +#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_STATUS0 0x1822 +#define regCP_HPD_STATUS0_BASE_IDX 1 + + +// addressBlock: gc_pfonly_didtdec +// base address: 0x2e400 +#define regDIDT_INDEX_AUTO_INCR_EN 0x1900 +#define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 1 +#define regDIDT_EDC_CTRL 0x1901 +#define regDIDT_EDC_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THROTTLE_CTRL 0x1902 +#define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THRESHOLD 0x1903 +#define regDIDT_EDC_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_1_2 0x1904 +#define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_3_4 0x1905 +#define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_5_6 0x1906 +#define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_7 0x1907 +#define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_EDC_STATUS 0x1908 +#define regDIDT_EDC_STATUS_BASE_IDX 1 +#define regDIDT_EDC_DYNAMIC_THRESHOLD_RO 0x1909 +#define regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX 1 +#define regDIDT_EDC_OVERFLOW 0x190a +#define regDIDT_EDC_OVERFLOW_BASE_IDX 1 +#define regDIDT_EDC_ROLLING_POWER_DELTA 0x190b +#define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 +#define regDIDT_IND_INDEX 0x190c +#define regDIDT_IND_INDEX_BASE_IDX 1 +#define regDIDT_IND_DATA 0x190d +#define regDIDT_IND_DATA_BASE_IDX 1 + + +// addressBlock: gc_pfonly_spidec +// base address: 0x2e500 +#define regSPI_GDBG_WAVE_CNTL 0x1943 +#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 1 +#define regSPI_GDBG_TRAP_CONFIG 0x1944 +#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 1 +#define regSPI_GDBG_WAVE_CNTL3 0x1945 +#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 +#define regSPI_ARB_CNTL_0 0x1949 +#define regSPI_ARB_CNTL_0_BASE_IDX 1 +#define regSPI_FEATURE_CTRL 0x194a +#define regSPI_FEATURE_CTRL_BASE_IDX 1 +#define regSPI_SHADER_RSRC_LIMIT_CTRL 0x194b +#define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 1 +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS 0x194e +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX 1 + + +// addressBlock: gc_pfonly_tcpdec +// base address: 0x2e680 +#define regTCP_INVALIDATE 0x19a0 +#define regTCP_INVALIDATE_BASE_IDX 1 +#define regTCP_STATUS 0x19a1 +#define regTCP_STATUS_BASE_IDX 1 +#define regTCP_CNTL 0x19a2 +#define regTCP_CNTL_BASE_IDX 1 +#define regTCP_CNTL2 0x19a3 +#define regTCP_CNTL2_BASE_IDX 1 +#define regTCP_DEBUG_INDEX 0x19a5 +#define regTCP_DEBUG_INDEX_BASE_IDX 1 +#define regTCP_DEBUG_DATA 0x19a6 +#define regTCP_DEBUG_DATA_BASE_IDX 1 + + +// addressBlock: gc_pfonly_gdsdec +// base address: 0x2e6c0 +#define regGDS_ENHANCE2 0x19b0 +#define regGDS_ENHANCE2_BASE_IDX 1 +#define regGDS_OA_CGPG_RESTORE 0x19b1 +#define regGDS_OA_CGPG_RESTORE_BASE_IDX 1 + + +// addressBlock: gc_pfonly_utcl1dec +// base address: 0x2e600 +#define regUTCL1_CTRL_0 0x1980 +#define regUTCL1_CTRL_0_BASE_IDX 1 +#define regUTCL1_UTCL0_INVREQ_DISABLE 0x1984 +#define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 1 +#define regUTCL1_CTRL_2 0x1985 +#define regUTCL1_CTRL_2_BASE_IDX 1 +#define regUTCL1_FIFO_SIZING 0x1986 +#define regUTCL1_FIFO_SIZING_BASE_IDX 1 +#define regGCRD_SA0_TARGETS_DISABLE 0x1987 +#define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_SA1_TARGETS_DISABLE 0x1989 +#define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_CREDIT_SAFE 0x198a +#define regGCRD_CREDIT_SAFE_BASE_IDX 1 + + +// addressBlock: gc_pfonly_pmmdec +// base address: 0x2e640 +#define regGCR_GENERAL_CNTL 0x1990 +#define regGCR_GENERAL_CNTL_BASE_IDX 1 +#define regGCR_CMD_STATUS 0x1992 +#define regGCR_CMD_STATUS_BASE_IDX 1 +#define regGCR_SPARE 0x1993 +#define regGCR_SPARE_BASE_IDX 1 +#define regPMM_CNTL2 0x1999 +#define regPMM_CNTL2_BASE_IDX 1 + + +// addressBlock: gc_sedcdec +// base address: 0x2eb00 +#define regSEDC_GL1_GL2_OVERRIDES 0x1ac0 +#define regSEDC_GL1_GL2_OVERRIDES_BASE_IDX 1 + + +// addressBlock: gc_pfonly_gccacdec +// base address: 0x2eb40 +#define regGC_CAC_CTRL_1 0x1ad0 +#define regGC_CAC_CTRL_1_BASE_IDX 1 +#define regGC_CAC_CTRL_2 0x1ad1 +#define regGC_CAC_CTRL_2_BASE_IDX 1 +#define regGC_CAC_AGGR_LOWER 0x1ad2 +#define regGC_CAC_AGGR_LOWER_BASE_IDX 1 +#define regGC_CAC_AGGR_UPPER 0x1ad3 +#define regGC_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE0_CAC_AGGR_LOWER 0x1ad4 +#define regSE0_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE0_CAC_AGGR_UPPER 0x1ad5 +#define regSE0_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE1_CAC_AGGR_LOWER 0x1ad6 +#define regSE1_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE1_CAC_AGGR_UPPER 0x1ad7 +#define regSE1_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE2_CAC_AGGR_LOWER 0x1ad8 +#define regSE2_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE2_CAC_AGGR_UPPER 0x1ad9 +#define regSE2_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE3_CAC_AGGR_LOWER 0x1ada +#define regSE3_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE3_CAC_AGGR_UPPER 0x1adb +#define regSE3_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE4_CAC_AGGR_LOWER 0x1adc +#define regSE4_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE4_CAC_AGGR_UPPER 0x1add +#define regSE4_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE5_CAC_AGGR_LOWER 0x1ade +#define regSE5_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE5_CAC_AGGR_UPPER 0x1adf +#define regSE5_CAC_AGGR_UPPER_BASE_IDX 1 +#define regGC_CAC_AGGR_GFXCLK_CYCLE 0x1ae4 +#define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE 0x1ae5 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE 0x1ae6 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE2_CAC_AGGR_GFXCLK_CYCLE 0x1ae7 +#define regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE3_CAC_AGGR_GFXCLK_CYCLE 0x1ae8 +#define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE4_CAC_AGGR_GFXCLK_CYCLE 0x1ae9 +#define regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE5_CAC_AGGR_GFXCLK_CYCLE 0x1aea +#define regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regGC_EDC_CTRL 0x1aed +#define regGC_EDC_CTRL_BASE_IDX 1 +#define regGC_EDC_THRESHOLD 0x1aee +#define regGC_EDC_THRESHOLD_BASE_IDX 1 +#define regGC_EDC_STRETCH_CTRL 0x1aef +#define regGC_EDC_STRETCH_CTRL_BASE_IDX 1 +#define regGC_EDC_STRETCH_THRESHOLD 0x1af0 +#define regGC_EDC_STRETCH_THRESHOLD_BASE_IDX 1 +#define regEDC_HYSTERESIS_CNTL 0x1af1 +#define regEDC_HYSTERESIS_CNTL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL 0x1af2 +#define regGC_THROTTLE_CTRL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL1 0x1af3 +#define regGC_THROTTLE_CTRL1_BASE_IDX 1 +#define regPCC_STALL_PATTERN_CTRL 0x1af4 +#define regPCC_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_CTRL 0x1af5 +#define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPCC_STALL_PATTERN_1_2 0x1af6 +#define regPCC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPCC_STALL_PATTERN_3_4 0x1af7 +#define regPCC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPCC_STALL_PATTERN_5_6 0x1af8 +#define regPCC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPCC_STALL_PATTERN_7 0x1af9 +#define regPCC_STALL_PATTERN_7_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_1_2 0x1afa +#define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_3_4 0x1afb +#define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_5_6 0x1afc +#define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_7 0x1afd +#define regPWRBRK_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_CTRL 0x1afe +#define regDIDT_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_1_2 0x1aff +#define regDIDT_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_3_4 0x1b00 +#define regDIDT_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_5_6 0x1b01 +#define regDIDT_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_7 0x1b02 +#define regDIDT_STALL_PATTERN_7_BASE_IDX 1 +#define regPCC_PWRBRK_HYSTERESIS_CTRL 0x1b03 +#define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX 1 +#define regEDC_STRETCH_PERF_COUNTER 0x1b04 +#define regEDC_STRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_UNSTRETCH_PERF_COUNTER 0x1b05 +#define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_STRETCH_NUM_PERF_COUNTER 0x1b06 +#define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX 1 +#define regGC_EDC_STATUS 0x1b07 +#define regGC_EDC_STATUS_BASE_IDX 1 +#define regGC_EDC_OVERFLOW 0x1b08 +#define regGC_EDC_OVERFLOW_BASE_IDX 1 +#define regGC_EDC_ROLLING_POWER_DELTA 0x1b09 +#define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 +#define regGC_THROTTLE_STATUS 0x1b0a +#define regGC_THROTTLE_STATUS_BASE_IDX 1 +#define regEDC_PERF_COUNTER 0x1b0b +#define regEDC_PERF_COUNTER_BASE_IDX 1 +#define regPCC_PERF_COUNTER 0x1b0c +#define regPCC_PERF_COUNTER_BASE_IDX 1 +#define regPWRBRK_PERF_COUNTER 0x1b0d +#define regPWRBRK_PERF_COUNTER_BASE_IDX 1 +#define regEDC_HYSTERESIS_STAT 0x1b0e +#define regEDC_HYSTERESIS_STAT_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_0 0x1b10 +#define regGC_CAC_WEIGHT_CP_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_1 0x1b11 +#define regGC_CAC_WEIGHT_CP_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_EA_0 0x1b12 +#define regGC_CAC_WEIGHT_EA_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_EA_1 0x1b13 +#define regGC_CAC_WEIGHT_EA_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_EA_2 0x1b14 +#define regGC_CAC_WEIGHT_EA_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x1b15 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x1b16 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x1b17 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x1b18 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x1b19 +#define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_VML2_0 0x1b1a +#define regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_VML2_1 0x1b1b +#define regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_VML2_2 0x1b1c +#define regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_0 0x1b1d +#define regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_1 0x1b1e +#define regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_UTCL2_WALKER_2 0x1b1f +#define regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GDS_0 0x1b20 +#define regGC_CAC_WEIGHT_GDS_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GDS_1 0x1b21 +#define regGC_CAC_WEIGHT_GDS_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GDS_2 0x1b22 +#define regGC_CAC_WEIGHT_GDS_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_0 0x1b23 +#define regGC_CAC_WEIGHT_GE_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_1 0x1b24 +#define regGC_CAC_WEIGHT_GE_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_2 0x1b25 +#define regGC_CAC_WEIGHT_GE_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_3 0x1b26 +#define regGC_CAC_WEIGHT_GE_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_4 0x1b27 +#define regGC_CAC_WEIGHT_GE_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_5 0x1b28 +#define regGC_CAC_WEIGHT_GE_5_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GE_6 0x1b29 +#define regGC_CAC_WEIGHT_GE_6_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PMM_0 0x1b2e +#define regGC_CAC_WEIGHT_PMM_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GL2C_0 0x1b2f +#define regGC_CAC_WEIGHT_GL2C_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GL2C_1 0x1b30 +#define regGC_CAC_WEIGHT_GL2C_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GL2C_2 0x1b31 +#define regGC_CAC_WEIGHT_GL2C_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_0 0x1b32 +#define regGC_CAC_WEIGHT_PH_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_1 0x1b33 +#define regGC_CAC_WEIGHT_PH_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_2 0x1b34 +#define regGC_CAC_WEIGHT_PH_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PH_3 0x1b35 +#define regGC_CAC_WEIGHT_PH_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_0 0x1b36 +#define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_1 0x1b37 +#define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_2 0x1b38 +#define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_3 0x1b39 +#define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_4 0x1b3a +#define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_5 0x1b3b +#define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_0 0x1b3c +#define regGC_CAC_WEIGHT_CHC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_1 0x1b3d +#define regGC_CAC_WEIGHT_CHC_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GUS_0 0x1b3e +#define regGC_CAC_WEIGHT_GUS_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GUS_1 0x1b3f +#define regGC_CAC_WEIGHT_GUS_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_RLC_0 0x1b40 +#define regGC_CAC_WEIGHT_RLC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GRBM_0 0x1b44 +#define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX 1 +#define regGC_EDC_CLK_MONITOR_CTRL 0x1b56 +#define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX 1 +#define regGC_CAC_IND_INDEX 0x1b58 +#define regGC_CAC_IND_INDEX_BASE_IDX 1 +#define regGC_CAC_IND_DATA 0x1b59 +#define regGC_CAC_IND_DATA_BASE_IDX 1 +#define regSE_CAC_CTRL_1 0x1b70 +#define regSE_CAC_CTRL_1_BASE_IDX 1 +#define regSE_CAC_CTRL_2 0x1b71 +#define regSE_CAC_CTRL_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TA_0 0x1b72 +#define regSE_CAC_WEIGHT_TA_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_0 0x1b73 +#define regSE_CAC_WEIGHT_TD_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_1 0x1b74 +#define regSE_CAC_WEIGHT_TD_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_2 0x1b75 +#define regSE_CAC_WEIGHT_TD_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_3 0x1b76 +#define regSE_CAC_WEIGHT_TD_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_4 0x1b77 +#define regSE_CAC_WEIGHT_TD_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TD_5 0x1b78 +#define regSE_CAC_WEIGHT_TD_5_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_0 0x1b79 +#define regSE_CAC_WEIGHT_TCP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_1 0x1b7a +#define regSE_CAC_WEIGHT_TCP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_2 0x1b7b +#define regSE_CAC_WEIGHT_TCP_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_3 0x1b7c +#define regSE_CAC_WEIGHT_TCP_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_0 0x1b7d +#define regSE_CAC_WEIGHT_SQ_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_1 0x1b7e +#define regSE_CAC_WEIGHT_SQ_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_2 0x1b7f +#define regSE_CAC_WEIGHT_SQ_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_0 0x1b80 +#define regSE_CAC_WEIGHT_SP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_1 0x1b81 +#define regSE_CAC_WEIGHT_SP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_0 0x1b82 +#define regSE_CAC_WEIGHT_LDS_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_1 0x1b83 +#define regSE_CAC_WEIGHT_LDS_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_2 0x1b84 +#define regSE_CAC_WEIGHT_LDS_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS_3 0x1b85 +#define regSE_CAC_WEIGHT_LDS_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_0 0x1b87 +#define regSE_CAC_WEIGHT_SQC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_1 0x1b88 +#define regSE_CAC_WEIGHT_SQC_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CU_0 0x1b89 +#define regSE_CAC_WEIGHT_CU_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_BCI_0 0x1b8a +#define regSE_CAC_WEIGHT_BCI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_0 0x1b8b +#define regSE_CAC_WEIGHT_CB_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_1 0x1b8c +#define regSE_CAC_WEIGHT_CB_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_2 0x1b8d +#define regSE_CAC_WEIGHT_CB_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_3 0x1b8e +#define regSE_CAC_WEIGHT_CB_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_4 0x1b8f +#define regSE_CAC_WEIGHT_CB_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_5 0x1b90 +#define regSE_CAC_WEIGHT_CB_5_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_6 0x1b91 +#define regSE_CAC_WEIGHT_CB_6_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_7 0x1b92 +#define regSE_CAC_WEIGHT_CB_7_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_8 0x1b93 +#define regSE_CAC_WEIGHT_CB_8_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_9 0x1b94 +#define regSE_CAC_WEIGHT_CB_9_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_10 0x1b95 +#define regSE_CAC_WEIGHT_CB_10_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CB_11 0x1b96 +#define regSE_CAC_WEIGHT_CB_11_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_0 0x1b97 +#define regSE_CAC_WEIGHT_DB_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_1 0x1b98 +#define regSE_CAC_WEIGHT_DB_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_2 0x1b99 +#define regSE_CAC_WEIGHT_DB_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_3 0x1b9a +#define regSE_CAC_WEIGHT_DB_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_DB_4 0x1b9b +#define regSE_CAC_WEIGHT_DB_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_RMI_0 0x1b9c +#define regSE_CAC_WEIGHT_RMI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_RMI_1 0x1b9d +#define regSE_CAC_WEIGHT_RMI_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SX_0 0x1b9e +#define regSE_CAC_WEIGHT_SX_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SXRB_0 0x1b9f +#define regSE_CAC_WEIGHT_SXRB_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_UTCL1_0 0x1ba0 +#define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_0 0x1ba1 +#define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_1 0x1ba2 +#define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_2 0x1ba3 +#define regSE_CAC_WEIGHT_GL1C_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_0 0x1ba4 +#define regSE_CAC_WEIGHT_SPI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_1 0x1ba5 +#define regSE_CAC_WEIGHT_SPI_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_2 0x1ba6 +#define regSE_CAC_WEIGHT_SPI_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PC_0 0x1ba7 +#define regSE_CAC_WEIGHT_PC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_0 0x1ba8 +#define regSE_CAC_WEIGHT_PA_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_1 0x1ba9 +#define regSE_CAC_WEIGHT_PA_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_2 0x1baa +#define regSE_CAC_WEIGHT_PA_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_PA_3 0x1bab +#define regSE_CAC_WEIGHT_PA_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_0 0x1bac +#define regSE_CAC_WEIGHT_SC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_1 0x1bad +#define regSE_CAC_WEIGHT_SC_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_2 0x1bae +#define regSE_CAC_WEIGHT_SC_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SC_3 0x1baf +#define regSE_CAC_WEIGHT_SC_3_BASE_IDX 1 +#define regSE_CAC_WINDOW_AGGR_VALUE 0x1bb0 +#define regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX 1 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE 0x1bb1 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE_CAC_IND_INDEX 0x1bce +#define regSE_CAC_IND_INDEX_BASE_IDX 1 +#define regSE_CAC_IND_DATA 0x1bcf +#define regSE_CAC_IND_DATA_BASE_IDX 1 + + +// addressBlock: gc_pfonly2_spidec +// base address: 0x2f000 +#define regSPI_RESOURCE_RESERVE_CU_0 0x1c00 +#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_1 0x1c01 +#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_2 0x1c02 +#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_3 0x1c03 +#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_4 0x1c04 +#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_5 0x1c05 +#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_6 0x1c06 +#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_7 0x1c07 +#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_8 0x1c08 +#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_9 0x1c09 +#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_10 0x1c0a +#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_11 0x1c0b +#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_12 0x1c0c +#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_13 0x1c0d +#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_14 0x1c0e +#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_15 0x1c0f +#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x1c10 +#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x1c11 +#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x1c12 +#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x1c13 +#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x1c14 +#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x1c15 +#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x1c16 +#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x1c17 +#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x1c18 +#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x1c19 +#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x1c1a +#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x1c1b +#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x1c1c +#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x1c1d +#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x1c1e +#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x1c1f +#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 1 + + +// addressBlock: gc_gfxudec +// base address: 0x30000 +#define regCP_EOP_DONE_ADDR_LO 0x2000 +#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 +#define regCP_EOP_DONE_ADDR_HI 0x2001 +#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_LO 0x2002 +#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_HI 0x2003 +#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_LO 0x2004 +#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_HI 0x2005 +#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_LO 0x2018 +#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_HI 0x2019 +#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_LO 0x201a +#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_HI 0x201b +#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_LO 0x201c +#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_HI 0x201d +#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_LO 0x201e +#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_HI 0x201f +#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 +#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 +#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 +#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 +#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 +#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 +#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 +#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 +#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_LO 0x2028 +#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_HI 0x2029 +#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_LO 0x202a +#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_HI 0x202b +#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_LO 0x202c +#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_HI 0x202d +#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_LO 0x202e +#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_HI 0x202f +#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 +#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 +#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_LO 0x2032 +#define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_HI 0x2033 +#define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_CONTROL 0x203d +#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 +#define regSCRATCH_REG0 0x2040 +#define regSCRATCH_REG0_BASE_IDX 1 +#define regSCRATCH_REG1 0x2041 +#define regSCRATCH_REG1_BASE_IDX 1 +#define regSCRATCH_REG2 0x2042 +#define regSCRATCH_REG2_BASE_IDX 1 +#define regSCRATCH_REG3 0x2043 +#define regSCRATCH_REG3_BASE_IDX 1 +#define regSCRATCH_REG4 0x2044 +#define regSCRATCH_REG4_BASE_IDX 1 +#define regSCRATCH_REG5 0x2045 +#define regSCRATCH_REG5_BASE_IDX 1 +#define regSCRATCH_REG6 0x2046 +#define regSCRATCH_REG6_BASE_IDX 1 +#define regSCRATCH_REG7 0x2047 +#define regSCRATCH_REG7_BASE_IDX 1 +#define regSCRATCH_REG_ATOMIC 0x2048 +#define regSCRATCH_REG_ATOMIC_BASE_IDX 1 +#define regSCRATCH_REG_CMPSWAP_ATOMIC 0x2048 +#define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX 1 +#define regCP_APPEND_DDID_CNT 0x204b +#define regCP_APPEND_DDID_CNT_BASE_IDX 1 +#define regCP_APPEND_DATA_HI 0x204c +#define regCP_APPEND_DATA_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d +#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e +#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 +#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 +#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_APPEND_ADDR_LO 0x2058 +#define regCP_APPEND_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_ADDR_HI 0x2059 +#define regCP_APPEND_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_DATA 0x205a +#define regCP_APPEND_DATA_BASE_IDX 1 +#define regCP_APPEND_DATA_LO 0x205a +#define regCP_APPEND_DATA_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE 0x205b +#define regCP_APPEND_LAST_CS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b +#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE 0x205c +#define regCP_APPEND_LAST_PS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c +#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_LO 0x205d +#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_LO 0x205d +#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_HI 0x205e +#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_HI 0x205e +#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_MC_WADDR_LO 0x2069 +#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_WADDR_HI 0x206a +#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 +#define regCP_ME_MC_WDATA_LO 0x206b +#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 +#define regCP_ME_MC_WDATA_HI 0x206c +#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 +#define regCP_ME_MC_RADDR_LO 0x206d +#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_RADDR_HI 0x206e +#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 +#define regCP_SEM_WAIT_TIMER 0x206f +#define regCP_SEM_WAIT_TIMER_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_LO 0x2070 +#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_HI 0x2071 +#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 +#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_LO 0x2075 +#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_HI 0x2076 +#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CONTROL 0x2077 +#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_CONTROL 0x2078 +#define regCP_DMA_ME_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR 0x2080 +#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 +#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR 0x2082 +#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR_HI 0x2083 +#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_COMMAND 0x2084 +#define regCP_DMA_ME_COMMAND_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR 0x2085 +#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 +#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR 0x2087 +#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 +#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_COMMAND 0x2089 +#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 +#define regCP_DMA_CNTL 0x208a +#define regCP_DMA_CNTL_BASE_IDX 1 +#define regCP_DMA_READ_TAGS 0x208b +#define regCP_DMA_READ_TAGS_BASE_IDX 1 +#define regCP_PFP_IB_CONTROL 0x208d +#define regCP_PFP_IB_CONTROL_BASE_IDX 1 +#define regCP_PFP_LOAD_CONTROL 0x208e +#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 +#define regCP_SCRATCH_INDEX 0x208f +#define regCP_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_SCRATCH_DATA 0x2090 +#define regCP_SCRATCH_DATA_BASE_IDX 1 +#define regCP_RB_OFFSET 0x2091 +#define regCP_RB_OFFSET_BASE_IDX 1 +#define regCP_IB2_OFFSET 0x2093 +#define regCP_IB2_OFFSET_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_BEGIN 0x2096 +#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_END 0x2097 +#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_LO 0x209c +#define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_HI 0x209d +#define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_LO 0x209e +#define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_HI 0x209f +#define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_CMD_ADDR_LO 0x20a0 +#define regCP_APPEND_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_CMD_ADDR_HI 0x20a1 +#define regCP_APPEND_CMD_ADDR_HI_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG0 0x20a2 +#define regUCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG1 0x20a3 +#define regUCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_LO 0x20a4 +#define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_HI 0x20a5 +#define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_LO 0x20a6 +#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_HI 0x20a7 +#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_IB1_CMD_BUFSZ 0x20c0 +#define regCP_IB1_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB2_CMD_BUFSZ 0x20c1 +#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_ST_CMD_BUFSZ 0x20c2 +#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB1_BASE_LO 0x20cc +#define regCP_IB1_BASE_LO_BASE_IDX 1 +#define regCP_IB1_BASE_HI 0x20cd +#define regCP_IB1_BASE_HI_BASE_IDX 1 +#define regCP_IB1_BUFSZ 0x20ce +#define regCP_IB1_BUFSZ_BASE_IDX 1 +#define regCP_IB2_BASE_LO 0x20cf +#define regCP_IB2_BASE_LO_BASE_IDX 1 +#define regCP_IB2_BASE_HI 0x20d0 +#define regCP_IB2_BASE_HI_BASE_IDX 1 +#define regCP_IB2_BUFSZ 0x20d1 +#define regCP_IB2_BUFSZ_BASE_IDX 1 +#define regCP_ST_BASE_LO 0x20d2 +#define regCP_ST_BASE_LO_BASE_IDX 1 +#define regCP_ST_BASE_HI 0x20d3 +#define regCP_ST_BASE_HI_BASE_IDX 1 +#define regCP_ST_BUFSZ 0x20d4 +#define regCP_ST_BUFSZ_BASE_IDX 1 +#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 +#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_CNTL 0x20d6 +#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_CNTX_ID 0x20d7 +#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 +#define regCP_DB_BASE_LO 0x20d8 +#define regCP_DB_BASE_LO_BASE_IDX 1 +#define regCP_DB_BASE_HI 0x20d9 +#define regCP_DB_BASE_HI_BASE_IDX 1 +#define regCP_DB_BUFSZ 0x20da +#define regCP_DB_BUFSZ_BASE_IDX 1 +#define regCP_DB_CMD_BUFSZ 0x20db +#define regCP_DB_CMD_BUFSZ_BASE_IDX 1 +#define regCP_PFP_COMPLETION_STATUS 0x20ec +#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_PRED_NOT_VISIBLE 0x20ee +#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 +#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 +#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 +#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 +#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR 0x20f6 +#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 +#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR 0x20f8 +#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR_HI 0x20f9 +#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_TYPE 0x20fa +#define regCP_INDEX_TYPE_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR 0x20fb +#define regCP_GDS_BKUP_ADDR_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR_HI 0x20fc +#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 +#define regCP_SAMPLE_STATUS 0x20fd +#define regCP_SAMPLE_STATUS_BASE_IDX 1 +#define regCP_ME_COHER_CNTL 0x20fe +#define regCP_ME_COHER_CNTL_BASE_IDX 1 +#define regCP_ME_COHER_SIZE 0x20ff +#define regCP_ME_COHER_SIZE_BASE_IDX 1 +#define regCP_ME_COHER_SIZE_HI 0x2100 +#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_ME_COHER_BASE 0x2101 +#define regCP_ME_COHER_BASE_BASE_IDX 1 +#define regCP_ME_COHER_BASE_HI 0x2102 +#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 +#define regCP_ME_COHER_STATUS 0x2103 +#define regCP_ME_COHER_STATUS_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_0 0x2140 +#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_1 0x2141 +#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 +#define regGRBM_GFX_INDEX 0x2200 +#define regGRBM_GFX_INDEX_BASE_IDX 1 +#define regVGT_PRIMITIVE_TYPE 0x2242 +#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 +#define regVGT_INDEX_TYPE 0x2243 +#define regVGT_INDEX_TYPE_BASE_IDX 1 +#define regGE_MIN_VTX_INDX 0x2249 +#define regGE_MIN_VTX_INDX_BASE_IDX 1 +#define regGE_INDX_OFFSET 0x224a +#define regGE_INDX_OFFSET_BASE_IDX 1 +#define regGE_MULTI_PRIM_IB_RESET_EN 0x224b +#define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 +#define regVGT_NUM_INDICES 0x224c +#define regVGT_NUM_INDICES_BASE_IDX 1 +#define regVGT_NUM_INSTANCES 0x224d +#define regVGT_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_TF_RING_SIZE 0x224e +#define regVGT_TF_RING_SIZE_BASE_IDX 1 +#define regVGT_HS_OFFCHIP_PARAM 0x224f +#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE 0x2250 +#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 +#define regGE_MAX_VTX_INDX 0x2259 +#define regGE_MAX_VTX_INDX_BASE_IDX 1 +#define regVGT_INSTANCE_BASE_ID 0x225a +#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 +#define regGE_CNTL 0x225b +#define regGE_CNTL_BASE_IDX 1 +#define regGE_USER_VGPR1 0x225c +#define regGE_USER_VGPR1_BASE_IDX 1 +#define regGE_USER_VGPR2 0x225d +#define regGE_USER_VGPR2_BASE_IDX 1 +#define regGE_USER_VGPR3 0x225e +#define regGE_USER_VGPR3_BASE_IDX 1 +#define regGE_STEREO_CNTL 0x225f +#define regGE_STEREO_CNTL_BASE_IDX 1 +#define regGE_PC_ALLOC 0x2260 +#define regGE_PC_ALLOC_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE_HI 0x2261 +#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 +#define regGE_USER_VGPR_EN 0x2262 +#define regGE_USER_VGPR_EN_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM 0x2264 +#define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1 0x2265 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX 1 +#define regVGT_GS_OUT_PRIM_TYPE 0x2266 +#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 +#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_STATE 0x2281 +#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 +#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 +#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 +#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b +#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 +#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 +#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 +#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa +#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 +#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_H 0x22b1 +#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_V 0x22b2 +#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 +#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 +#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 +#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 +#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 +#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_4 0x2344 +#define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_5 0x2345 +#define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_6 0x2346 +#define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_7 0x2347 +#define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1 +#define regSQC_CACHES 0x2348 +#define regSQC_CACHES_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR 0x2380 +#define regTA_CS_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR_HI 0x2381 +#define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 +#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_HI 0x23c1 +#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 +#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_HI 0x23c3 +#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 +#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_HI 0x23c5 +#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 +#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_HI 0x23c7 +#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 +#define regGDS_RD_ADDR 0x2400 +#define regGDS_RD_ADDR_BASE_IDX 1 +#define regGDS_RD_DATA 0x2401 +#define regGDS_RD_DATA_BASE_IDX 1 +#define regGDS_RD_BURST_ADDR 0x2402 +#define regGDS_RD_BURST_ADDR_BASE_IDX 1 +#define regGDS_RD_BURST_COUNT 0x2403 +#define regGDS_RD_BURST_COUNT_BASE_IDX 1 +#define regGDS_RD_BURST_DATA 0x2404 +#define regGDS_RD_BURST_DATA_BASE_IDX 1 +#define regGDS_WR_ADDR 0x2405 +#define regGDS_WR_ADDR_BASE_IDX 1 +#define regGDS_WR_DATA 0x2406 +#define regGDS_WR_DATA_BASE_IDX 1 +#define regGDS_WR_BURST_ADDR 0x2407 +#define regGDS_WR_BURST_ADDR_BASE_IDX 1 +#define regGDS_WR_BURST_DATA 0x2408 +#define regGDS_WR_BURST_DATA_BASE_IDX 1 +#define regGDS_WRITE_COMPLETE 0x2409 +#define regGDS_WRITE_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_CNTL 0x240a +#define regGDS_ATOM_CNTL_BASE_IDX 1 +#define regGDS_ATOM_COMPLETE 0x240b +#define regGDS_ATOM_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_BASE 0x240c +#define regGDS_ATOM_BASE_BASE_IDX 1 +#define regGDS_ATOM_SIZE 0x240d +#define regGDS_ATOM_SIZE_BASE_IDX 1 +#define regGDS_ATOM_OFFSET0 0x240e +#define regGDS_ATOM_OFFSET0_BASE_IDX 1 +#define regGDS_ATOM_OFFSET1 0x240f +#define regGDS_ATOM_OFFSET1_BASE_IDX 1 +#define regGDS_ATOM_DST 0x2410 +#define regGDS_ATOM_DST_BASE_IDX 1 +#define regGDS_ATOM_OP 0x2411 +#define regGDS_ATOM_OP_BASE_IDX 1 +#define regGDS_ATOM_SRC0 0x2412 +#define regGDS_ATOM_SRC0_BASE_IDX 1 +#define regGDS_ATOM_SRC0_U 0x2413 +#define regGDS_ATOM_SRC0_U_BASE_IDX 1 +#define regGDS_ATOM_SRC1 0x2414 +#define regGDS_ATOM_SRC1_BASE_IDX 1 +#define regGDS_ATOM_SRC1_U 0x2415 +#define regGDS_ATOM_SRC1_U_BASE_IDX 1 +#define regGDS_ATOM_READ0 0x2416 +#define regGDS_ATOM_READ0_BASE_IDX 1 +#define regGDS_ATOM_READ0_U 0x2417 +#define regGDS_ATOM_READ0_U_BASE_IDX 1 +#define regGDS_ATOM_READ1 0x2418 +#define regGDS_ATOM_READ1_BASE_IDX 1 +#define regGDS_ATOM_READ1_U 0x2419 +#define regGDS_ATOM_READ1_U_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNTL 0x241a +#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 +#define regGDS_GWS_RESOURCE 0x241b +#define regGDS_GWS_RESOURCE_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNT 0x241c +#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 +#define regGDS_OA_CNTL 0x241d +#define regGDS_OA_CNTL_BASE_IDX 1 +#define regGDS_OA_COUNTER 0x241e +#define regGDS_OA_COUNTER_BASE_IDX 1 +#define regGDS_OA_ADDRESS 0x241f +#define regGDS_OA_ADDRESS_BASE_IDX 1 +#define regGDS_OA_INCDEC 0x2420 +#define regGDS_OA_INCDEC_BASE_IDX 1 +#define regGDS_OA_RING_SIZE 0x2421 +#define regGDS_OA_RING_SIZE_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_0 0x2422 +#define regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_1 0x2423 +#define regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_2 0x2424 +#define regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX 1 +#define regGDS_STRMOUT_DWORDS_WRITTEN_3 0x2425 +#define regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX 1 +#define regGDS_GS_0 0x2426 +#define regGDS_GS_0_BASE_IDX 1 +#define regGDS_GS_1 0x2427 +#define regGDS_GS_1_BASE_IDX 1 +#define regGDS_GS_2 0x2428 +#define regGDS_GS_2_BASE_IDX 1 +#define regGDS_GS_3 0x2429 +#define regGDS_GS_3_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_0_LO 0x242a +#define regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_0_HI 0x242b +#define regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO 0x242c +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI 0x242d +#define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_1_LO 0x242e +#define regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_1_HI 0x242f +#define regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO 0x2430 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI 0x2431 +#define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_LO 0x2432 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_HI 0x2433 +#define regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO 0x2434 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI 0x2435 +#define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_LO 0x2436 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_HI 0x2437 +#define regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO 0x2438 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX 1 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI 0x2439 +#define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX 1 +#define regSPI_CONFIG_CNTL 0x2440 +#define regSPI_CONFIG_CNTL_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_1 0x2441 +#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_2 0x2442 +#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 +#define regSPI_WAVE_LIMIT_CNTL 0x2443 +#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL1 0x2444 +#define regSPI_GS_THROTTLE_CNTL1_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL2 0x2445 +#define regSPI_GS_THROTTLE_CNTL2_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_BASE 0x2446 +#define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_SIZE 0x2447 +#define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX 1 + + +// addressBlock: gc_cprs64dec +// base address: 0x32000 +#define regCP_MES_PRGRM_CNTR_START 0x2800 +#define regCP_MES_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START 0x2801 +#define regCP_MES_INTR_ROUTINE_START_BASE_IDX 1 +#define regCP_MES_MTVEC_LO 0x2801 +#define regCP_MES_MTVEC_LO_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START_HI 0x2802 +#define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 +#define regCP_MES_MTVEC_HI 0x2802 +#define regCP_MES_MTVEC_HI_BASE_IDX 1 +#define regCP_MES_CNTL 0x2807 +#define regCP_MES_CNTL_BASE_IDX 1 +#define regCP_MES_PIPE_PRIORITY_CNTS 0x2808 +#define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 +#define regCP_MES_PIPE0_PRIORITY 0x2809 +#define regCP_MES_PIPE0_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE1_PRIORITY 0x280a +#define regCP_MES_PIPE1_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE2_PRIORITY 0x280b +#define regCP_MES_PIPE2_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE3_PRIORITY 0x280c +#define regCP_MES_PIPE3_PRIORITY_BASE_IDX 1 +#define regCP_MES_HEADER_DUMP 0x280d +#define regCP_MES_HEADER_DUMP_BASE_IDX 1 +#define regCP_MES_MIE_LO 0x280e +#define regCP_MES_MIE_LO_BASE_IDX 1 +#define regCP_MES_MIE_HI 0x280f +#define regCP_MES_MIE_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT 0x2810 +#define regCP_MES_INTERRUPT_BASE_IDX 1 +#define regCP_MES_SCRATCH_INDEX 0x2811 +#define regCP_MES_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_MES_SCRATCH_DATA 0x2812 +#define regCP_MES_SCRATCH_DATA_BASE_IDX 1 +#define regCP_MES_INSTR_PNTR 0x2813 +#define regCP_MES_INSTR_PNTR_BASE_IDX 1 +#define regCP_MES_MSCRATCH_HI 0x2814 +#define regCP_MES_MSCRATCH_HI_BASE_IDX 1 +#define regCP_MES_MSCRATCH_LO 0x2815 +#define regCP_MES_MSCRATCH_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_LO 0x2816 +#define regCP_MES_MSTATUS_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_HI 0x2817 +#define regCP_MES_MSTATUS_HI_BASE_IDX 1 +#define regCP_MES_MEPC_LO 0x2818 +#define regCP_MES_MEPC_LO_BASE_IDX 1 +#define regCP_MES_MEPC_HI 0x2819 +#define regCP_MES_MEPC_HI_BASE_IDX 1 +#define regCP_MES_MCAUSE_LO 0x281a +#define regCP_MES_MCAUSE_LO_BASE_IDX 1 +#define regCP_MES_MCAUSE_HI 0x281b +#define regCP_MES_MCAUSE_HI_BASE_IDX 1 +#define regCP_MES_MBADADDR_LO 0x281c +#define regCP_MES_MBADADDR_LO_BASE_IDX 1 +#define regCP_MES_MBADADDR_HI 0x281d +#define regCP_MES_MBADADDR_HI_BASE_IDX 1 +#define regCP_MES_MIP_LO 0x281e +#define regCP_MES_MIP_LO_BASE_IDX 1 +#define regCP_MES_MIP_HI 0x281f +#define regCP_MES_MIP_HI_BASE_IDX 1 +#define regCP_MES_IC_OP_CNTL 0x2820 +#define regCP_MES_IC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MCYCLE_LO 0x2826 +#define regCP_MES_MCYCLE_LO_BASE_IDX 1 +#define regCP_MES_MCYCLE_HI 0x2827 +#define regCP_MES_MCYCLE_HI_BASE_IDX 1 +#define regCP_MES_MTIME_LO 0x2828 +#define regCP_MES_MTIME_LO_BASE_IDX 1 +#define regCP_MES_MTIME_HI 0x2829 +#define regCP_MES_MTIME_HI_BASE_IDX 1 +#define regCP_MES_MINSTRET_LO 0x282a +#define regCP_MES_MINSTRET_LO_BASE_IDX 1 +#define regCP_MES_MINSTRET_HI 0x282b +#define regCP_MES_MINSTRET_HI_BASE_IDX 1 +#define regCP_MES_MISA_LO 0x282c +#define regCP_MES_MISA_LO_BASE_IDX 1 +#define regCP_MES_MISA_HI 0x282d +#define regCP_MES_MISA_HI_BASE_IDX 1 +#define regCP_MES_MVENDORID_LO 0x282e +#define regCP_MES_MVENDORID_LO_BASE_IDX 1 +#define regCP_MES_MVENDORID_HI 0x282f +#define regCP_MES_MVENDORID_HI_BASE_IDX 1 +#define regCP_MES_MARCHID_LO 0x2830 +#define regCP_MES_MARCHID_LO_BASE_IDX 1 +#define regCP_MES_MARCHID_HI 0x2831 +#define regCP_MES_MARCHID_HI_BASE_IDX 1 +#define regCP_MES_MIMPID_LO 0x2832 +#define regCP_MES_MIMPID_LO_BASE_IDX 1 +#define regCP_MES_MIMPID_HI 0x2833 +#define regCP_MES_MIMPID_HI_BASE_IDX 1 +#define regCP_MES_MHARTID_LO 0x2834 +#define regCP_MES_MHARTID_LO_BASE_IDX 1 +#define regCP_MES_MHARTID_HI 0x2835 +#define regCP_MES_MHARTID_HI_BASE_IDX 1 +#define regCP_MES_DC_BASE_CNTL 0x2836 +#define regCP_MES_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_OP_CNTL 0x2837 +#define regCP_MES_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MTIMECMP_LO 0x2838 +#define regCP_MES_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MES_MTIMECMP_HI 0x2839 +#define regCP_MES_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE0 0x283a +#define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE1 0x283b +#define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL1 0x283c +#define regCP_MES_DOORBELL_CONTROL1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL2 0x283d +#define regCP_MES_DOORBELL_CONTROL2_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL3 0x283e +#define regCP_MES_DOORBELL_CONTROL3_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL4 0x283f +#define regCP_MES_DOORBELL_CONTROL4_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL5 0x2840 +#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL6 0x2841 +#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 +#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842 +#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1 +#define regCP_MES_GP0_LO 0x2843 +#define regCP_MES_GP0_LO_BASE_IDX 1 +#define regCP_MES_GP0_HI 0x2844 +#define regCP_MES_GP0_HI_BASE_IDX 1 +#define regCP_MES_GP1_LO 0x2845 +#define regCP_MES_GP1_LO_BASE_IDX 1 +#define regCP_MES_GP1_HI 0x2846 +#define regCP_MES_GP1_HI_BASE_IDX 1 +#define regCP_MES_GP2_LO 0x2847 +#define regCP_MES_GP2_LO_BASE_IDX 1 +#define regCP_MES_GP2_HI 0x2848 +#define regCP_MES_GP2_HI_BASE_IDX 1 +#define regCP_MES_GP3_LO 0x2849 +#define regCP_MES_GP3_LO_BASE_IDX 1 +#define regCP_MES_GP3_HI 0x284a +#define regCP_MES_GP3_HI_BASE_IDX 1 +#define regCP_MES_GP4_LO 0x284b +#define regCP_MES_GP4_LO_BASE_IDX 1 +#define regCP_MES_GP4_HI 0x284c +#define regCP_MES_GP4_HI_BASE_IDX 1 +#define regCP_MES_GP5_LO 0x284d +#define regCP_MES_GP5_LO_BASE_IDX 1 +#define regCP_MES_GP5_HI 0x284e +#define regCP_MES_GP5_HI_BASE_IDX 1 +#define regCP_MES_GP6_LO 0x284f +#define regCP_MES_GP6_LO_BASE_IDX 1 +#define regCP_MES_GP6_HI 0x2850 +#define regCP_MES_GP6_HI_BASE_IDX 1 +#define regCP_MES_GP7_LO 0x2851 +#define regCP_MES_GP7_LO_BASE_IDX 1 +#define regCP_MES_GP7_HI 0x2852 +#define regCP_MES_GP7_HI_BASE_IDX 1 +#define regCP_MES_GP8_LO 0x2853 +#define regCP_MES_GP8_LO_BASE_IDX 1 +#define regCP_MES_GP8_HI 0x2854 +#define regCP_MES_GP8_HI_BASE_IDX 1 +#define regCP_MES_GP9_LO 0x2855 +#define regCP_MES_GP9_LO_BASE_IDX 1 +#define regCP_MES_GP9_HI 0x2856 +#define regCP_MES_GP9_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_LO 0x2883 +#define regCP_MES_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_HI 0x2884 +#define regCP_MES_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_LO 0x2885 +#define regCP_MES_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_HI 0x2886 +#define regCP_MES_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_APERTURE 0x2887 +#define regCP_MES_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_LO 0x2888 +#define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_HI 0x2889 +#define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_LO 0x288a +#define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_HI 0x288b +#define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_APERTURE 0x288c +#define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_APERTURE 0x288d +#define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_LO 0x288e +#define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_HI 0x288f +#define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MES_PERFCOUNT_CNTL 0x2899 +#define regCP_MES_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MES_PENDING_INTERRUPT 0x289a +#define regCP_MES_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MES_PRGRM_CNTR_START_HI 0x289d +#define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_16 0x289f +#define regCP_MES_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_17 0x28a0 +#define regCP_MES_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_18 0x28a1 +#define regCP_MES_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_19 0x28a2 +#define regCP_MES_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_20 0x28a3 +#define regCP_MES_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_21 0x28a4 +#define regCP_MES_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_22 0x28a5 +#define regCP_MES_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_23 0x28a6 +#define regCP_MES_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_24 0x28a7 +#define regCP_MES_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_25 0x28a8 +#define regCP_MES_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_26 0x28a9 +#define regCP_MES_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_27 0x28aa +#define regCP_MES_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_28 0x28ab +#define regCP_MES_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_29 0x28ac +#define regCP_MES_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_30 0x28ad +#define regCP_MES_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_31 0x28ae +#define regCP_MES_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_MES_DC_APERTURE0_BASE 0x28af +#define regCP_MES_DC_APERTURE0_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE0_MASK 0x28b0 +#define regCP_MES_DC_APERTURE0_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE0_CNTL 0x28b1 +#define regCP_MES_DC_APERTURE0_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE1_BASE 0x28b2 +#define regCP_MES_DC_APERTURE1_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE1_MASK 0x28b3 +#define regCP_MES_DC_APERTURE1_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE1_CNTL 0x28b4 +#define regCP_MES_DC_APERTURE1_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE2_BASE 0x28b5 +#define regCP_MES_DC_APERTURE2_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE2_MASK 0x28b6 +#define regCP_MES_DC_APERTURE2_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE2_CNTL 0x28b7 +#define regCP_MES_DC_APERTURE2_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE3_BASE 0x28b8 +#define regCP_MES_DC_APERTURE3_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE3_MASK 0x28b9 +#define regCP_MES_DC_APERTURE3_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE3_CNTL 0x28ba +#define regCP_MES_DC_APERTURE3_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE4_BASE 0x28bb +#define regCP_MES_DC_APERTURE4_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE4_MASK 0x28bc +#define regCP_MES_DC_APERTURE4_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE4_CNTL 0x28bd +#define regCP_MES_DC_APERTURE4_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE5_BASE 0x28be +#define regCP_MES_DC_APERTURE5_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE5_MASK 0x28bf +#define regCP_MES_DC_APERTURE5_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE5_CNTL 0x28c0 +#define regCP_MES_DC_APERTURE5_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE6_BASE 0x28c1 +#define regCP_MES_DC_APERTURE6_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE6_MASK 0x28c2 +#define regCP_MES_DC_APERTURE6_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE6_CNTL 0x28c3 +#define regCP_MES_DC_APERTURE6_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE7_BASE 0x28c4 +#define regCP_MES_DC_APERTURE7_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE7_MASK 0x28c5 +#define regCP_MES_DC_APERTURE7_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE7_CNTL 0x28c6 +#define regCP_MES_DC_APERTURE7_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE8_BASE 0x28c7 +#define regCP_MES_DC_APERTURE8_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE8_MASK 0x28c8 +#define regCP_MES_DC_APERTURE8_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE8_CNTL 0x28c9 +#define regCP_MES_DC_APERTURE8_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE9_BASE 0x28ca +#define regCP_MES_DC_APERTURE9_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE9_MASK 0x28cb +#define regCP_MES_DC_APERTURE9_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE9_CNTL 0x28cc +#define regCP_MES_DC_APERTURE9_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE10_BASE 0x28cd +#define regCP_MES_DC_APERTURE10_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE10_MASK 0x28ce +#define regCP_MES_DC_APERTURE10_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE10_CNTL 0x28cf +#define regCP_MES_DC_APERTURE10_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE11_BASE 0x28d0 +#define regCP_MES_DC_APERTURE11_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE11_MASK 0x28d1 +#define regCP_MES_DC_APERTURE11_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE11_CNTL 0x28d2 +#define regCP_MES_DC_APERTURE11_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE12_BASE 0x28d3 +#define regCP_MES_DC_APERTURE12_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE12_MASK 0x28d4 +#define regCP_MES_DC_APERTURE12_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE12_CNTL 0x28d5 +#define regCP_MES_DC_APERTURE12_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE13_BASE 0x28d6 +#define regCP_MES_DC_APERTURE13_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE13_MASK 0x28d7 +#define regCP_MES_DC_APERTURE13_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE13_CNTL 0x28d8 +#define regCP_MES_DC_APERTURE13_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE14_BASE 0x28d9 +#define regCP_MES_DC_APERTURE14_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE14_MASK 0x28da +#define regCP_MES_DC_APERTURE14_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE14_CNTL 0x28db +#define regCP_MES_DC_APERTURE14_CNTL_BASE_IDX 1 +#define regCP_MES_DC_APERTURE15_BASE 0x28dc +#define regCP_MES_DC_APERTURE15_BASE_BASE_IDX 1 +#define regCP_MES_DC_APERTURE15_MASK 0x28dd +#define regCP_MES_DC_APERTURE15_MASK_BASE_IDX 1 +#define regCP_MES_DC_APERTURE15_CNTL 0x28de +#define regCP_MES_DC_APERTURE15_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START 0x2900 +#define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MEC_MTVEC_LO 0x2901 +#define regCP_MEC_MTVEC_LO_BASE_IDX 1 +#define regCP_MEC_MTVEC_HI 0x2902 +#define regCP_MEC_MTVEC_HI_BASE_IDX 1 +#define regCP_MEC_ISA_CNTL 0x2903 +#define regCP_MEC_ISA_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_CNTL 0x2904 +#define regCP_MEC_RS64_CNTL_BASE_IDX 1 +#define regCP_MEC_MIE_LO 0x2905 +#define regCP_MEC_MIE_LO_BASE_IDX 1 +#define regCP_MEC_MIE_HI 0x2906 +#define regCP_MEC_MIE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT 0x2907 +#define regCP_MEC_RS64_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_INSTR_PNTR 0x2908 +#define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX 1 +#define regCP_MEC_MIP_LO 0x2909 +#define regCP_MEC_MIP_LO_BASE_IDX 1 +#define regCP_MEC_MIP_HI 0x290a +#define regCP_MEC_MIP_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_CNTL 0x290b +#define regCP_MEC_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_OP_CNTL 0x290c +#define regCP_MEC_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_LO 0x290d +#define regCP_MEC_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_HI 0x290e +#define regCP_MEC_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MEC_GP0_LO 0x2910 +#define regCP_MEC_GP0_LO_BASE_IDX 1 +#define regCP_MEC_GP0_HI 0x2911 +#define regCP_MEC_GP0_HI_BASE_IDX 1 +#define regCP_MEC_GP1_LO 0x2912 +#define regCP_MEC_GP1_LO_BASE_IDX 1 +#define regCP_MEC_GP1_HI 0x2913 +#define regCP_MEC_GP1_HI_BASE_IDX 1 +#define regCP_MEC_GP2_LO 0x2914 +#define regCP_MEC_GP2_LO_BASE_IDX 1 +#define regCP_MEC_GP2_HI 0x2915 +#define regCP_MEC_GP2_HI_BASE_IDX 1 +#define regCP_MEC_GP3_LO 0x2916 +#define regCP_MEC_GP3_LO_BASE_IDX 1 +#define regCP_MEC_GP3_HI 0x2917 +#define regCP_MEC_GP3_HI_BASE_IDX 1 +#define regCP_MEC_GP4_LO 0x2918 +#define regCP_MEC_GP4_LO_BASE_IDX 1 +#define regCP_MEC_GP4_HI 0x2919 +#define regCP_MEC_GP4_HI_BASE_IDX 1 +#define regCP_MEC_GP5_LO 0x291a +#define regCP_MEC_GP5_LO_BASE_IDX 1 +#define regCP_MEC_GP5_HI 0x291b +#define regCP_MEC_GP5_HI_BASE_IDX 1 +#define regCP_MEC_GP6_LO 0x291c +#define regCP_MEC_GP6_LO_BASE_IDX 1 +#define regCP_MEC_GP6_HI 0x291d +#define regCP_MEC_GP6_HI_BASE_IDX 1 +#define regCP_MEC_GP7_LO 0x291e +#define regCP_MEC_GP7_LO_BASE_IDX 1 +#define regCP_MEC_GP7_HI 0x291f +#define regCP_MEC_GP7_HI_BASE_IDX 1 +#define regCP_MEC_GP8_LO 0x2920 +#define regCP_MEC_GP8_LO_BASE_IDX 1 +#define regCP_MEC_GP8_HI 0x2921 +#define regCP_MEC_GP8_HI_BASE_IDX 1 +#define regCP_MEC_GP9_LO 0x2922 +#define regCP_MEC_GP9_LO_BASE_IDX 1 +#define regCP_MEC_GP9_HI 0x2923 +#define regCP_MEC_GP9_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_LO 0x2927 +#define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_HI 0x2928 +#define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_LO 0x2929 +#define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_HI 0x292a +#define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_APERTURE 0x292b +#define regCP_MEC_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_LO 0x292c +#define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_HI 0x292d +#define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_LO 0x292e +#define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_HI 0x292f +#define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_APERTURE 0x2930 +#define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE 0x2931 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO 0x2932 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI 0x2933 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_PERFCOUNT_CNTL 0x2934 +#define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PENDING_INTERRUPT 0x2935 +#define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI 0x2938 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_16 0x293a +#define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_17 0x293b +#define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_18 0x293c +#define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_19 0x293d +#define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_20 0x293e +#define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_21 0x293f +#define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_22 0x2940 +#define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_23 0x2941 +#define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_24 0x2942 +#define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_25 0x2943 +#define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_26 0x2944 +#define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_27 0x2945 +#define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_28 0x2946 +#define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_29 0x2947 +#define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_30 0x2948 +#define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_31 0x2949 +#define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE0_BASE 0x294a +#define regCP_MEC_DC_APERTURE0_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE0_MASK 0x294b +#define regCP_MEC_DC_APERTURE0_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE0_CNTL 0x294c +#define regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE1_BASE 0x294d +#define regCP_MEC_DC_APERTURE1_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE1_MASK 0x294e +#define regCP_MEC_DC_APERTURE1_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE1_CNTL 0x294f +#define regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE2_BASE 0x2950 +#define regCP_MEC_DC_APERTURE2_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE2_MASK 0x2951 +#define regCP_MEC_DC_APERTURE2_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE2_CNTL 0x2952 +#define regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE3_BASE 0x2953 +#define regCP_MEC_DC_APERTURE3_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE3_MASK 0x2954 +#define regCP_MEC_DC_APERTURE3_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE3_CNTL 0x2955 +#define regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE4_BASE 0x2956 +#define regCP_MEC_DC_APERTURE4_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE4_MASK 0x2957 +#define regCP_MEC_DC_APERTURE4_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE4_CNTL 0x2958 +#define regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE5_BASE 0x2959 +#define regCP_MEC_DC_APERTURE5_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE5_MASK 0x295a +#define regCP_MEC_DC_APERTURE5_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE5_CNTL 0x295b +#define regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE6_BASE 0x295c +#define regCP_MEC_DC_APERTURE6_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE6_MASK 0x295d +#define regCP_MEC_DC_APERTURE6_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE6_CNTL 0x295e +#define regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE7_BASE 0x295f +#define regCP_MEC_DC_APERTURE7_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE7_MASK 0x2960 +#define regCP_MEC_DC_APERTURE7_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE7_CNTL 0x2961 +#define regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE8_BASE 0x2962 +#define regCP_MEC_DC_APERTURE8_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE8_MASK 0x2963 +#define regCP_MEC_DC_APERTURE8_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE8_CNTL 0x2964 +#define regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE9_BASE 0x2965 +#define regCP_MEC_DC_APERTURE9_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE9_MASK 0x2966 +#define regCP_MEC_DC_APERTURE9_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE9_CNTL 0x2967 +#define regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE10_BASE 0x2968 +#define regCP_MEC_DC_APERTURE10_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE10_MASK 0x2969 +#define regCP_MEC_DC_APERTURE10_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE10_CNTL 0x296a +#define regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE11_BASE 0x296b +#define regCP_MEC_DC_APERTURE11_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE11_MASK 0x296c +#define regCP_MEC_DC_APERTURE11_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE11_CNTL 0x296d +#define regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE12_BASE 0x296e +#define regCP_MEC_DC_APERTURE12_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE12_MASK 0x296f +#define regCP_MEC_DC_APERTURE12_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE12_CNTL 0x2970 +#define regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE13_BASE 0x2971 +#define regCP_MEC_DC_APERTURE13_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE13_MASK 0x2972 +#define regCP_MEC_DC_APERTURE13_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE13_CNTL 0x2973 +#define regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE14_BASE 0x2974 +#define regCP_MEC_DC_APERTURE14_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE14_MASK 0x2975 +#define regCP_MEC_DC_APERTURE14_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE14_CNTL 0x2976 +#define regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE15_BASE 0x2977 +#define regCP_MEC_DC_APERTURE15_BASE_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE15_MASK 0x2978 +#define regCP_MEC_DC_APERTURE15_MASK_BASE_IDX 1 +#define regCP_MEC_DC_APERTURE15_CNTL 0x2979 +#define regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX 1 +#define regCP_CPC_IC_OP_CNTL 0x297a +#define regCP_CPC_IC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_CNTL 0x2a00 +#define regCP_GFX_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT0 0x2a01 +#define regCP_GFX_RS64_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN0 0x2a02 +#define regCP_GFX_RS64_INTR_EN0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN1 0x2a03 +#define regCP_GFX_RS64_INTR_EN1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE_CNTL 0x2a08 +#define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_DC_OP_CNTL 0x2a09 +#define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_LO 0x2a0a +#define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_HI 0x2a0b +#define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_LO 0x2a0c +#define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_HI 0x2a0d +#define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_APERTURE 0x2a0e +#define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO 0x2a0f +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI 0x2a10 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO 0x2a11 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI 0x2a12 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE 0x2a13 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE 0x2a14 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO 0x2a15 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI 0x2a16 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL0 0x2a1a +#define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL1 0x2a1b +#define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO0 0x2a1c +#define regCP_GFX_RS64_MIP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO1 0x2a1d +#define regCP_GFX_RS64_MIP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI0 0x2a1e +#define regCP_GFX_RS64_MIP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI1 0x2a1f +#define regCP_GFX_RS64_MIP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO0 0x2a20 +#define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO1 0x2a21 +#define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI0 0x2a22 +#define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI1 0x2a23 +#define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO0 0x2a24 +#define regCP_GFX_RS64_GP0_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO1 0x2a25 +#define regCP_GFX_RS64_GP0_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI0 0x2a26 +#define regCP_GFX_RS64_GP0_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI1 0x2a27 +#define regCP_GFX_RS64_GP0_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO0 0x2a28 +#define regCP_GFX_RS64_GP1_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO1 0x2a29 +#define regCP_GFX_RS64_GP1_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI0 0x2a2a +#define regCP_GFX_RS64_GP1_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI1 0x2a2b +#define regCP_GFX_RS64_GP1_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO0 0x2a2c +#define regCP_GFX_RS64_GP2_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO1 0x2a2d +#define regCP_GFX_RS64_GP2_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI0 0x2a2e +#define regCP_GFX_RS64_GP2_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI1 0x2a2f +#define regCP_GFX_RS64_GP2_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO0 0x2a30 +#define regCP_GFX_RS64_GP3_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO1 0x2a31 +#define regCP_GFX_RS64_GP3_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI0 0x2a32 +#define regCP_GFX_RS64_GP3_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI1 0x2a33 +#define regCP_GFX_RS64_GP3_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO0 0x2a34 +#define regCP_GFX_RS64_GP4_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO1 0x2a35 +#define regCP_GFX_RS64_GP4_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI0 0x2a36 +#define regCP_GFX_RS64_GP4_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI1 0x2a37 +#define regCP_GFX_RS64_GP4_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO0 0x2a38 +#define regCP_GFX_RS64_GP5_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO1 0x2a39 +#define regCP_GFX_RS64_GP5_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI0 0x2a3a +#define regCP_GFX_RS64_GP5_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI1 0x2a3b +#define regCP_GFX_RS64_GP5_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_LO 0x2a3c +#define regCP_GFX_RS64_GP6_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_HI 0x2a3d +#define regCP_GFX_RS64_GP6_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_LO 0x2a3e +#define regCP_GFX_RS64_GP7_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_HI 0x2a3f +#define regCP_GFX_RS64_GP7_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_LO 0x2a40 +#define regCP_GFX_RS64_GP8_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_HI 0x2a41 +#define regCP_GFX_RS64_GP8_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_LO 0x2a42 +#define regCP_GFX_RS64_GP9_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_HI 0x2a43 +#define regCP_GFX_RS64_GP9_HI_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR0 0x2a44 +#define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR1 0x2a45 +#define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT0 0x2a46 +#define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT1 0x2a47 +#define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0 0x2a49 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK0 0x2a4a +#define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0 0x2a4b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE0 0x2a4c +#define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK0 0x2a4d +#define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0 0x2a4e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE0 0x2a4f +#define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0 0x2a50 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0 0x2a51 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0 0x2a52 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0 0x2a53 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0 0x2a54 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0 0x2a55 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0 0x2a56 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0 0x2a57 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0 0x2a58 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0 0x2a59 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0 0x2a5a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE0 0x2a5b +#define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK0 0x2a5c +#define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0 0x2a5d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE0 0x2a5e +#define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK0 0x2a5f +#define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0 0x2a60 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0 0x2a61 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0 0x2a62 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0 0x2a63 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0 0x2a64 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0 0x2a65 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0 0x2a66 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0 0x2a67 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0 0x2a68 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0 0x2a69 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE0 0x2a6a +#define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK0 0x2a6b +#define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0 0x2a6c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE0 0x2a6d +#define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK0 0x2a6e +#define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0 0x2a6f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0 0x2a70 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0 0x2a71 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0 0x2a72 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0 0x2a73 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0 0x2a74 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0 0x2a75 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0 0x2a76 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0 0x2a77 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0 0x2a78 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1 0x2a79 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK1 0x2a7a +#define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1 0x2a7b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE1 0x2a7c +#define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK1 0x2a7d +#define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1 0x2a7e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE1 0x2a7f +#define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1 0x2a80 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1 0x2a81 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1 0x2a82 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1 0x2a83 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1 0x2a84 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1 0x2a85 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1 0x2a86 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1 0x2a87 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1 0x2a88 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1 0x2a89 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1 0x2a8a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE1 0x2a8b +#define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK1 0x2a8c +#define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1 0x2a8d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE1 0x2a8e +#define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK1 0x2a8f +#define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1 0x2a90 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1 0x2a91 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1 0x2a92 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1 0x2a93 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1 0x2a94 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1 0x2a95 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1 0x2a96 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1 0x2a97 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1 0x2a98 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1 0x2a99 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE1 0x2a9a +#define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK1 0x2a9b +#define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1 0x2a9c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE1 0x2a9d +#define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK1 0x2a9e +#define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1 0x2a9f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1 0x2aa0 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1 0x2aa1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1 0x2aa2 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1 0x2aa3 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1 0x2aa4 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1 0x2aa5 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1 0x2aa6 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1 0x2aa7 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1 0x2aa8 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT1 0x2aac +#define regCP_GFX_RS64_INTERRUPT1_BASE_IDX 1 + + +// addressBlock: gc_gl1dec +// base address: 0x33400 +#define regGL1_DRAM_BURST_MASK 0x2d02 +#define regGL1_DRAM_BURST_MASK_BASE_IDX 1 +#define regGL1_ARB_STATUS 0x2d03 +#define regGL1_ARB_STATUS_BASE_IDX 1 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE 0x2d05 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGL1C_STATUS 0x2d41 +#define regGL1C_STATUS_BASE_IDX 1 +#define regGL1C_UTCL0_CNTL1 0x2d42 +#define regGL1C_UTCL0_CNTL1_BASE_IDX 1 +#define regGL1C_UTCL0_CNTL2 0x2d43 +#define regGL1C_UTCL0_CNTL2_BASE_IDX 1 +#define regGL1C_UTCL0_STATUS 0x2d44 +#define regGL1C_UTCL0_STATUS_BASE_IDX 1 +#define regGL1C_UTCL0_RETRY 0x2d45 +#define regGL1C_UTCL0_RETRY_BASE_IDX 1 + + +// addressBlock: gc_chdec +// base address: 0x33600 +#define regCH_ARB_CTRL 0x2d80 +#define regCH_ARB_CTRL_BASE_IDX 1 +#define regCH_DRAM_BURST_MASK 0x2d82 +#define regCH_DRAM_BURST_MASK_BASE_IDX 1 +#define regCH_ARB_STATUS 0x2d83 +#define regCH_ARB_STATUS_BASE_IDX 1 +#define regCH_DRAM_BURST_CTRL 0x2d84 +#define regCH_DRAM_BURST_CTRL_BASE_IDX 1 +#define regCHA_CHC_CREDITS 0x2d88 +#define regCHA_CHC_CREDITS_BASE_IDX 1 +#define regCHA_CLIENT_FREE_DELAY 0x2d89 +#define regCHA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regCHI_CHR_REP_FGCG_OVERRIDE 0x2d8c +#define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regCH_VC5_ENABLE 0x2d94 +#define regCH_VC5_ENABLE_BASE_IDX 1 +#define regCHC_CTRL 0x2dc0 +#define regCHC_CTRL_BASE_IDX 1 +#define regCHC_STATUS 0x2dc1 +#define regCHC_STATUS_BASE_IDX 1 +#define regCHCG_CTRL 0x2dc2 +#define regCHCG_CTRL_BASE_IDX 1 +#define regCHCG_STATUS 0x2dc3 +#define regCHCG_STATUS_BASE_IDX 1 + + +// addressBlock: gc_gl2dec +// base address: 0x33800 +#define regGL2C_CTRL 0x2e00 +#define regGL2C_CTRL_BASE_IDX 1 +#define regGL2C_CTRL2 0x2e01 +#define regGL2C_CTRL2_BASE_IDX 1 +#define regGL2C_ADDR_MATCH_MASK 0x2e03 +#define regGL2C_ADDR_MATCH_MASK_BASE_IDX 1 +#define regGL2C_ADDR_MATCH_SIZE 0x2e04 +#define regGL2C_ADDR_MATCH_SIZE_BASE_IDX 1 +#define regGL2C_WBINVL2 0x2e05 +#define regGL2C_WBINVL2_BASE_IDX 1 +#define regGL2C_SOFT_RESET 0x2e06 +#define regGL2C_SOFT_RESET_BASE_IDX 1 +#define regGL2C_CM_CTRL0 0x2e07 +#define regGL2C_CM_CTRL0_BASE_IDX 1 +#define regGL2C_CM_CTRL1 0x2e08 +#define regGL2C_CM_CTRL1_BASE_IDX 1 +#define regGL2C_CM_STALL 0x2e09 +#define regGL2C_CM_STALL_BASE_IDX 1 +#define regGL2C_CTRL3 0x2e0c +#define regGL2C_CTRL3_BASE_IDX 1 +#define regGL2C_LB_CTR_CTRL 0x2e0d +#define regGL2C_LB_CTR_CTRL_BASE_IDX 1 +#define regGL2C_LB_DATA0 0x2e0e +#define regGL2C_LB_DATA0_BASE_IDX 1 +#define regGL2C_LB_DATA1 0x2e0f +#define regGL2C_LB_DATA1_BASE_IDX 1 +#define regGL2C_LB_DATA2 0x2e10 +#define regGL2C_LB_DATA2_BASE_IDX 1 +#define regGL2C_LB_DATA3 0x2e11 +#define regGL2C_LB_DATA3_BASE_IDX 1 +#define regGL2C_LB_CTR_SEL0 0x2e12 +#define regGL2C_LB_CTR_SEL0_BASE_IDX 1 +#define regGL2C_LB_CTR_SEL1 0x2e13 +#define regGL2C_LB_CTR_SEL1_BASE_IDX 1 +#define regGL2C_CTRL4 0x2e17 +#define regGL2C_CTRL4_BASE_IDX 1 +#define regGL2C_DISCARD_STALL_CTRL 0x2e18 +#define regGL2C_DISCARD_STALL_CTRL_BASE_IDX 1 +#define regGL2A_ADDR_MATCH_CTRL 0x2e20 +#define regGL2A_ADDR_MATCH_CTRL_BASE_IDX 1 +#define regGL2A_ADDR_MATCH_MASK 0x2e21 +#define regGL2A_ADDR_MATCH_MASK_BASE_IDX 1 +#define regGL2A_ADDR_MATCH_SIZE 0x2e22 +#define regGL2A_ADDR_MATCH_SIZE_BASE_IDX 1 +#define regGL2A_PRIORITY_CTRL 0x2e23 +#define regGL2A_PRIORITY_CTRL_BASE_IDX 1 +#define regGL2A_RESP_THROTTLE_CTRL 0x2e2a +#define regGL2A_RESP_THROTTLE_CTRL_BASE_IDX 1 + + +// addressBlock: gc_gl1hdec +// base address: 0x33900 +#define regGL1H_ARB_CTRL 0x2e40 +#define regGL1H_ARB_CTRL_BASE_IDX 1 +#define regGL1H_GL1_CREDITS 0x2e41 +#define regGL1H_GL1_CREDITS_BASE_IDX 1 +#define regGL1H_BURST_MASK 0x2e42 +#define regGL1H_BURST_MASK_BASE_IDX 1 +#define regGL1H_BURST_CTRL 0x2e43 +#define regGL1H_BURST_CTRL_BASE_IDX 1 +#define regGL1H_ARB_STATUS 0x2e44 +#define regGL1H_ARB_STATUS_BASE_IDX 1 + + +// addressBlock: gc_perfddec +// base address: 0x34000 +#define regCPG_PERFCOUNTER1_LO 0x3000 +#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER1_HI 0x3001 +#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_LO 0x3002 +#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_HI 0x3003 +#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_LO 0x3004 +#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_HI 0x3005 +#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_LO 0x3006 +#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_HI 0x3007 +#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_LO 0x3008 +#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_HI 0x3009 +#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_LO 0x300a +#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_HI 0x300b +#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_LATENCY_STATS_DATA 0x300c +#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPG_LATENCY_STATS_DATA 0x300d +#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPC_LATENCY_STATS_DATA 0x300e +#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_LO 0x3040 +#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_HI 0x3041 +#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_LO 0x3043 +#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_HI 0x3044 +#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_LO 0x3045 +#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_HI 0x3046 +#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_LO 0x3047 +#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_HI 0x3048 +#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_LO 0x3049 +#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_HI 0x304a +#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_LO 0x304b +#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_HI 0x304c +#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE4_PERFCOUNTER_LO 0x304d +#define regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE4_PERFCOUNTER_HI 0x304e +#define regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE5_PERFCOUNTER_LO 0x304f +#define regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE5_PERFCOUNTER_HI 0x3050 +#define regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE6_PERFCOUNTER_LO 0x3051 +#define regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE6_PERFCOUNTER_HI 0x3052 +#define regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_LO 0x30a4 +#define regGE1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_HI 0x30a5 +#define regGE1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_LO 0x30a6 +#define regGE1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_HI 0x30a7 +#define regGE1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_LO 0x30a8 +#define regGE1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_HI 0x30a9 +#define regGE1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_LO 0x30aa +#define regGE1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_HI 0x30ab +#define regGE1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_LO 0x30ac +#define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_HI 0x30ad +#define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_LO 0x30ae +#define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_HI 0x30af +#define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_LO 0x30b0 +#define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_HI 0x30b1 +#define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_LO 0x30b2 +#define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_HI 0x30b3 +#define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_LO 0x30b4 +#define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_HI 0x30b5 +#define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_LO 0x30b6 +#define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_HI 0x30b7 +#define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_LO 0x30b8 +#define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_HI 0x30b9 +#define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_LO 0x30ba +#define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_HI 0x30bb +#define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_LO 0x3100 +#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_HI 0x3101 +#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_LO 0x3102 +#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_HI 0x3103 +#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_LO 0x3104 +#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_HI 0x3105 +#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_LO 0x3106 +#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_HI 0x3107 +#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_LO 0x3140 +#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_HI 0x3141 +#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_LO 0x3142 +#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_HI 0x3143 +#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_LO 0x3144 +#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_HI 0x3145 +#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_LO 0x3146 +#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_HI 0x3147 +#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_LO 0x3148 +#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_HI 0x3149 +#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_LO 0x314a +#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_HI 0x314b +#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_LO 0x314c +#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_HI 0x314d +#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_LO 0x314e +#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_HI 0x314f +#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_HI 0x3180 +#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_LO 0x3181 +#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_HI 0x3182 +#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_LO 0x3183 +#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_HI 0x3184 +#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_LO 0x3185 +#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_HI 0x3186 +#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_LO 0x3187 +#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_HI 0x3188 +#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_LO 0x3189 +#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_HI 0x318a +#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_LO 0x318b +#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER0_HI 0x318c +#define regPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER0_LO 0x318d +#define regPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER1_HI 0x318e +#define regPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER1_LO 0x318f +#define regPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER2_HI 0x3190 +#define regPC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER2_LO 0x3191 +#define regPC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER3_HI 0x3192 +#define regPC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER3_LO 0x3193 +#define regPC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_LO 0x31c0 +#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_LO 0x31c2 +#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_LO 0x31c4 +#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_LO 0x31c6 +#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_LO 0x31c8 +#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_LO 0x31ca +#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_LO 0x31cc +#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_LO 0x31ce +#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_LO 0x31e4 +#define regSQG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_HI 0x31e5 +#define regSQG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_LO 0x31e6 +#define regSQG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_HI 0x31e7 +#define regSQG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_LO 0x31e8 +#define regSQG_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_HI 0x31e9 +#define regSQG_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_LO 0x31ea +#define regSQG_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_HI 0x31eb +#define regSQG_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_LO 0x31ec +#define regSQG_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_HI 0x31ed +#define regSQG_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_LO 0x31ee +#define regSQG_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_HI 0x31ef +#define regSQG_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_LO 0x31f0 +#define regSQG_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_HI 0x31f1 +#define regSQG_PERFCOUNTER6_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_LO 0x31f2 +#define regSQG_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_HI 0x31f3 +#define regSQG_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER0_LO 0x3240 +#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER0_HI 0x3241 +#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER1_LO 0x3242 +#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER1_HI 0x3243 +#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER2_LO 0x3244 +#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER2_HI 0x3245 +#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER3_LO 0x3246 +#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER3_HI 0x3247 +#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_LO 0x3260 +#define regGCEA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_HI 0x3261 +#define regGCEA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGCEA_PERFCOUNTER_LO 0x3262 +#define regGCEA_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCEA_PERFCOUNTER_HI 0x3263 +#define regGCEA_PERFCOUNTER_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_LO 0x3280 +#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_HI 0x3281 +#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_LO 0x3282 +#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_HI 0x3283 +#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_LO 0x3284 +#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_HI 0x3285 +#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_LO 0x3286 +#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_HI 0x3287 +#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER0_LO 0x32c0 +#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER0_HI 0x32c1 +#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER1_LO 0x32c2 +#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER1_HI 0x32c3 +#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER0_LO 0x3300 +#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER0_HI 0x3301 +#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER1_LO 0x3302 +#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER1_HI 0x3303 +#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_LO 0x3340 +#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_HI 0x3341 +#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_LO 0x3342 +#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_HI 0x3343 +#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_LO 0x3344 +#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_HI 0x3345 +#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_LO 0x3346 +#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_HI 0x3347 +#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER 0x3348 +#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER2 0x3349 +#define regTCP_PERFCOUNTER_FILTER2_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER_EN 0x334a +#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_LO 0x3380 +#define regGL2C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_HI 0x3381 +#define regGL2C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_LO 0x3382 +#define regGL2C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_HI 0x3383 +#define regGL2C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_LO 0x3384 +#define regGL2C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_HI 0x3385 +#define regGL2C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_LO 0x3386 +#define regGL2C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_HI 0x3387 +#define regGL2C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_LO 0x3390 +#define regGL2A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_HI 0x3391 +#define regGL2A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_LO 0x3392 +#define regGL2A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_HI 0x3393 +#define regGL2A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_LO 0x3394 +#define regGL2A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_HI 0x3395 +#define regGL2A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_LO 0x3396 +#define regGL2A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_HI 0x3397 +#define regGL2A_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_LO 0x33a0 +#define regGL1C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_HI 0x33a1 +#define regGL1C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_LO 0x33a2 +#define regGL1C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_HI 0x33a3 +#define regGL1C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_LO 0x33a4 +#define regGL1C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_HI 0x33a5 +#define regGL1C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_LO 0x33a6 +#define regGL1C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_HI 0x33a7 +#define regGL1C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_LO 0x33c0 +#define regCHC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_HI 0x33c1 +#define regCHC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_LO 0x33c2 +#define regCHC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_HI 0x33c3 +#define regCHC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_LO 0x33c4 +#define regCHC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_HI 0x33c5 +#define regCHC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_LO 0x33c6 +#define regCHC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_HI 0x33c7 +#define regCHC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_LO 0x33c8 +#define regCHCG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_HI 0x33c9 +#define regCHCG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER1_LO 0x33ca +#define regCHCG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER1_HI 0x33cb +#define regCHCG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER2_LO 0x33cc +#define regCHCG_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER2_HI 0x33cd +#define regCHCG_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHCG_PERFCOUNTER3_LO 0x33ce +#define regCHCG_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHCG_PERFCOUNTER3_HI 0x33cf +#define regCHCG_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER0_LO 0x3406 +#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER0_HI 0x3407 +#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER1_LO 0x3408 +#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER1_HI 0x3409 +#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER2_LO 0x340a +#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER2_HI 0x340b +#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER3_LO 0x340c +#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER3_HI 0x340d +#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER0_LO 0x3440 +#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER0_HI 0x3441 +#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER1_LO 0x3442 +#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER1_HI 0x3443 +#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER2_LO 0x3444 +#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER2_HI 0x3445 +#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER3_LO 0x3446 +#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER3_HI 0x3447 +#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_LO 0x3480 +#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_HI 0x3481 +#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_LO 0x3482 +#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_HI 0x3483 +#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_LO 0x34c0 +#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_HI 0x34c1 +#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_LO 0x34c2 +#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_HI 0x34c3 +#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_LO 0x34c4 +#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_HI 0x34c5 +#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_LO 0x34c6 +#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_HI 0x34c7 +#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_LO 0x3520 +#define regGCR_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_HI 0x3521 +#define regGCR_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_LO 0x3522 +#define regGCR_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_HI 0x3523 +#define regGCR_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_LO 0x3580 +#define regPA_PH_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_HI 0x3581 +#define regPA_PH_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_LO 0x3582 +#define regPA_PH_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_HI 0x3583 +#define regPA_PH_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_LO 0x3584 +#define regPA_PH_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_HI 0x3585 +#define regPA_PH_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_LO 0x3586 +#define regPA_PH_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_HI 0x3587 +#define regPA_PH_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_LO 0x3588 +#define regPA_PH_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_HI 0x3589 +#define regPA_PH_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_LO 0x358a +#define regPA_PH_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_HI 0x358b +#define regPA_PH_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_LO 0x358c +#define regPA_PH_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_HI 0x358d +#define regPA_PH_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_LO 0x358e +#define regPA_PH_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_HI 0x358f +#define regPA_PH_PERFCOUNTER7_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_LO 0x35a0 +#define regUTCL1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_HI 0x35a1 +#define regUTCL1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_LO 0x35a2 +#define regUTCL1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_HI 0x35a3 +#define regUTCL1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_LO 0x35a4 +#define regUTCL1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_HI 0x35a5 +#define regUTCL1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_LO 0x35a6 +#define regUTCL1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_HI 0x35a7 +#define regUTCL1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_LO 0x35c0 +#define regGL1A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_HI 0x35c1 +#define regGL1A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_LO 0x35c2 +#define regGL1A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_HI 0x35c3 +#define regGL1A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_LO 0x35c4 +#define regGL1A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_HI 0x35c5 +#define regGL1A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_LO 0x35c6 +#define regGL1A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_HI 0x35c7 +#define regGL1A_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_LO 0x35d0 +#define regGL1H_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_HI 0x35d1 +#define regGL1H_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER1_LO 0x35d2 +#define regGL1H_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER1_HI 0x35d3 +#define regGL1H_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER2_LO 0x35d4 +#define regGL1H_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER2_HI 0x35d5 +#define regGL1H_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1H_PERFCOUNTER3_LO 0x35d6 +#define regGL1H_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1H_PERFCOUNTER3_HI 0x35d7 +#define regGL1H_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_LO 0x3600 +#define regCHA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_HI 0x3601 +#define regCHA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_LO 0x3602 +#define regCHA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_HI 0x3603 +#define regCHA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_LO 0x3604 +#define regCHA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_HI 0x3605 +#define regCHA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_LO 0x3606 +#define regCHA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_HI 0x3607 +#define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_LO 0x3640 +#define regGUS_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_HI 0x3641 +#define regGUS_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGUS_PERFCOUNTER_LO 0x3642 +#define regGUS_PERFCOUNTER_LO_BASE_IDX 1 +#define regGUS_PERFCOUNTER_HI 0x3643 +#define regGUS_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_perfsdec +// base address: 0x36000 +#define regCPG_PERFCOUNTER1_SELECT 0x3800 +#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT1 0x3801 +#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT 0x3802 +#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_SELECT 0x3803 +#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT1 0x3804 +#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_SELECT 0x3805 +#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT1 0x3806 +#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT 0x3807 +#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCP_PERFMON_CNTL 0x3808 +#define regCP_PERFMON_CNTL_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT 0x3809 +#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPF_LATENCY_STATS_SELECT 0x380c +#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPG_LATENCY_STATS_SELECT 0x380d +#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_LATENCY_STATS_SELECT 0x380e +#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT 0x380f +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT 0x3810 +#define regCP_DRAW_OBJECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT_COUNTER 0x3811 +#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 +#define regCP_DRAW_WINDOW_MASK_HI 0x3812 +#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_HI 0x3813 +#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_LO 0x3814 +#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 +#define regCP_DRAW_WINDOW_CNTL 0x3815 +#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT 0x3840 +#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT 0x3841 +#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 +#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 +#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 +#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 +#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE4_PERFCOUNTER_SELECT 0x3846 +#define regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE5_PERFCOUNTER_SELECT 0x3847 +#define regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE6_PERFCOUNTER_SELECT 0x3848 +#define regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT_HI 0x384d +#define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT_HI 0x384e +#define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT 0x38a4 +#define regGE1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT1 0x38a5 +#define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT 0x38a6 +#define regGE1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT1 0x38a7 +#define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT 0x38a8 +#define regGE1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT1 0x38a9 +#define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT 0x38aa +#define regGE1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT1 0x38ab +#define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT 0x38ac +#define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT1 0x38ad +#define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT 0x38ae +#define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT1 0x38af +#define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT 0x38b0 +#define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1 0x38b1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT 0x38b2 +#define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT1 0x38b3 +#define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_SELECT 0x38b4 +#define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_SELECT1 0x38b5 +#define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT 0x38b6 +#define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT1 0x38b7 +#define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT 0x38b8 +#define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT1 0x38b9 +#define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT 0x38ba +#define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT1 0x38bb +#define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 +#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 +#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 +#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 +#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 +#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT1 0x3905 +#define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT 0x3906 +#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT1 0x3907 +#define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 +#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 +#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 +#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 +#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 +#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 +#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 +#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 +#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 +#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT 0x3980 +#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT 0x3981 +#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT 0x3982 +#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT 0x3983 +#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT1 0x3984 +#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT1 0x3985 +#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT1 0x3986 +#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT1 0x3987 +#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT 0x3988 +#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT 0x3989 +#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER_BINS 0x398a +#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT 0x398c +#define regPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT 0x398d +#define regPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT 0x398e +#define regPC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT 0x398f +#define regPC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT1 0x3990 +#define regPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT1 0x3991 +#define regPC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT1 0x3992 +#define regPC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT1 0x3993 +#define regPC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_SELECT 0x39c0 +#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_SELECT 0x39c1 +#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_SELECT 0x39c2 +#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_SELECT 0x39c3 +#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_SELECT 0x39c4 +#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_SELECT 0x39c5 +#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_SELECT 0x39c6 +#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_SELECT 0x39c7 +#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_SELECT 0x39c8 +#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_SELECT 0x39c9 +#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_SELECT 0x39ca +#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_SELECT 0x39cb +#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_SELECT 0x39cc +#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_SELECT 0x39cd +#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_SELECT 0x39ce +#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_SELECT 0x39cf +#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_SELECT 0x39d0 +#define regSQG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_SELECT 0x39d1 +#define regSQG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_SELECT 0x39d2 +#define regSQG_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_SELECT 0x39d3 +#define regSQG_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_SELECT 0x39d4 +#define regSQG_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_SELECT 0x39d5 +#define regSQG_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_SELECT 0x39d6 +#define regSQG_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_SELECT 0x39d7 +#define regSQG_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL 0x39d8 +#define regSQG_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL2 0x39da +#define regSQG_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQG_PERF_SAMPLE_FINISH 0x39db +#define regSQG_PERF_SAMPLE_FINISH_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL 0x39e0 +#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL2 0x39e2 +#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_BASE 0x39e8 +#define regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_SIZE 0x39e9 +#define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_BASE 0x39ea +#define regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_SIZE 0x39eb +#define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CTRL 0x39ec +#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MASK 0x39ed +#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK 0x39ee +#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_WPTR 0x39ef +#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS 0x39f4 +#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS2 0x39f5 +#define regSQ_THREAD_TRACE_STATUS2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x39f6 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x39f7 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x39f8 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x39f9 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_DROPPED_CNTR 0x39fa +#define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_SELECT 0x3a00 +#define regGCEA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_SELECT1 0x3a01 +#define regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGCEA_PERFCOUNTER2_MODE 0x3a02 +#define regGCEA_PERFCOUNTER2_MODE_BASE_IDX 1 +#define regGCEA_PERFCOUNTER0_CFG 0x3a03 +#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCEA_PERFCOUNTER1_CFG 0x3a04 +#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCEA_PERFCOUNTER_RSLT_CNTL 0x3a05 +#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT 0x3a40 +#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT 0x3a41 +#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT 0x3a42 +#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT 0x3a43 +#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT1 0x3a44 +#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT1 0x3a45 +#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT 0x3a80 +#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_SELECT 0x3a81 +#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_SELECT 0x3a82 +#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_SELECT 0x3a83 +#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT1 0x3a84 +#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_SELECT1 0x3a85 +#define regGDS_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_SELECT1 0x3a86 +#define regGDS_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_SELECT1 0x3a87 +#define regGDS_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT 0x3ac0 +#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 +#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER1_SELECT 0x3ac2 +#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT 0x3b00 +#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT1 0x3b01 +#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTD_PERFCOUNTER1_SELECT 0x3b02 +#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT 0x3b40 +#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 +#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT 0x3b42 +#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 +#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT 0x3b44 +#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT 0x3b45 +#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_SELECT 0x3b80 +#define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_SELECT1 0x3b81 +#define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT 0x3b82 +#define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT1 0x3b83 +#define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_SELECT 0x3b84 +#define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_SELECT 0x3b85 +#define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT 0x3b90 +#define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT1 0x3b91 +#define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT 0x3b92 +#define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT1 0x3b93 +#define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_SELECT 0x3b94 +#define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_SELECT 0x3b95 +#define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT 0x3ba0 +#define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT1 0x3ba1 +#define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_SELECT 0x3ba2 +#define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_SELECT 0x3ba3 +#define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_SELECT 0x3ba4 +#define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT 0x3bc0 +#define regCHC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT1 0x3bc1 +#define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_SELECT 0x3bc2 +#define regCHC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_SELECT 0x3bc3 +#define regCHC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_SELECT 0x3bc4 +#define regCHC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_SELECT 0x3bc6 +#define regCHCG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER0_SELECT1 0x3bc7 +#define regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHCG_PERFCOUNTER1_SELECT 0x3bc8 +#define regCHCG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER2_SELECT 0x3bc9 +#define regCHCG_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHCG_PERFCOUNTER3_SELECT 0x3bca +#define regCHCG_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER_FILTER 0x3c00 +#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT 0x3c01 +#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT1 0x3c02 +#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER1_SELECT 0x3c03 +#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER2_SELECT 0x3c04 +#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER3_SELECT 0x3c05 +#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT 0x3c40 +#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT1 0x3c41 +#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT 0x3c42 +#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT1 0x3c43 +#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT 0x3c44 +#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT 0x3c46 +#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRLC_SPM_PERFMON_CNTL 0x3c80 +#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 +#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 +#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 +#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 +#define regRLC_SPM_RING_WRPTR 0x3c84 +#define regRLC_SPM_RING_WRPTR_BASE_IDX 1 +#define regRLC_SPM_RING_RDPTR 0x3c85 +#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 +#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c86 +#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c87 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c88 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c89 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c8a +#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_DATA 0x3c8b +#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_ADDR 0x3c92 +#define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_DATA 0x3c93 +#define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0x3c94 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA 0x3c95 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c96 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c97 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0x3c98 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX 1 +#define regRLC_SPM_ACCUM_STATUS 0x3c99 +#define regRLC_SPM_ACCUM_STATUS_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRL 0x3c9a +#define regRLC_SPM_ACCUM_CTRL_BASE_IDX 1 +#define regRLC_SPM_ACCUM_MODE 0x3c9b +#define regRLC_SPM_ACCUM_MODE_BASE_IDX 1 +#define regRLC_SPM_ACCUM_THRESHOLD 0x3c9c +#define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0x3c9f +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX 1 +#define regRLC_SPM_PAUSE 0x3ca2 +#define regRLC_SPM_PAUSE_BASE_IDX 1 +#define regRLC_SPM_STATUS 0x3ca3 +#define regRLC_SPM_STATUS_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT 0x3ca4 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT 0x3ca5 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX 1 +#define regRLC_SPM_MODE 0x3cad +#define regRLC_SPM_MODE_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_DATA_LO 0x3cae +#define regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_DATA_HI 0x3caf +#define regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_OP 0x3cb0 +#define regRLC_SPM_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_DATA 0x3cb1 +#define regRLC_SPM_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_OP 0x3cb2 +#define regRLC_SPM_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_DATA_LO 0x3cb3 +#define regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_DATA_HI 0x3cb4 +#define regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_OP 0x3cb5 +#define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_DATA 0x3cb6 +#define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_OP 0x3cb7 +#define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD 0x3cb8 +#define regRLC_SPM_RSPM_CMD_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD_ACK 0x3cb9 +#define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX 1 +#define regRLC_SPM_SPARE 0x3cbf +#define regRLC_SPM_SPARE_BASE_IDX 1 +#define regRLC_PERFMON_CNTL 0x3cc0 +#define regRLC_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 +#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 +#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 +#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT 0x3d00 +#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 +#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_SELECT 0x3d02 +#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT 0x3d03 +#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 +#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_SELECT 0x3d05 +#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRMI_PERF_COUNTER_CNTL 0x3d06 +#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT 0x3d60 +#define regGCR_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT1 0x3d61 +#define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_SELECT 0x3d62 +#define regGCR_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT 0x3d80 +#define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT1 0x3d81 +#define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT 0x3d82 +#define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT 0x3d83 +#define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT 0x3d84 +#define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_SELECT 0x3d85 +#define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_SELECT 0x3d86 +#define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_SELECT 0x3d87 +#define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_SELECT 0x3d88 +#define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT1 0x3d90 +#define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT1 0x3d91 +#define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT1 0x3d92 +#define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_SELECT 0x3da0 +#define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_SELECT 0x3da1 +#define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_SELECT 0x3da2 +#define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_SELECT 0x3da3 +#define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT 0x3dc0 +#define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT1 0x3dc1 +#define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_SELECT 0x3dc2 +#define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_SELECT 0x3dc3 +#define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_SELECT 0x3dc4 +#define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_SELECT 0x3dd0 +#define regGL1H_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER0_SELECT1 0x3dd1 +#define regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1H_PERFCOUNTER1_SELECT 0x3dd2 +#define regGL1H_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER2_SELECT 0x3dd3 +#define regGL1H_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1H_PERFCOUNTER3_SELECT 0x3dd4 +#define regGL1H_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT 0x3de0 +#define regCHA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT1 0x3de1 +#define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_SELECT 0x3de2 +#define regCHA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_SELECT 0x3de3 +#define regCHA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_SELECT 0x3de4 +#define regCHA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_SELECT 0x3e00 +#define regGUS_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_SELECT1 0x3e01 +#define regGUS_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGUS_PERFCOUNTER2_MODE 0x3e02 +#define regGUS_PERFCOUNTER2_MODE_BASE_IDX 1 +#define regGUS_PERFCOUNTER0_CFG 0x3e03 +#define regGUS_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGUS_PERFCOUNTER1_CFG 0x3e04 +#define regGUS_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGUS_PERFCOUNTER_RSLT_CNTL 0x3e05 +#define regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_grtavfs_grtavfs_dec +// base address: 0x3ac00 +#define regGRTAVFS_RTAVFS_REG_ADDR 0x4b00 +#define regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_WR_DATA 0x4b01 +#define regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 +#define regGRTAVFS_GENERAL_0 0x4b02 +#define regGRTAVFS_GENERAL_0_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_RD_DATA 0x4b03 +#define regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_REG_CTRL 0x4b04 +#define regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX 1 +#define regGRTAVFS_RTAVFS_REG_STATUS 0x4b05 +#define regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX 1 +#define regGRTAVFS_TARG_FREQ 0x4b06 +#define regGRTAVFS_TARG_FREQ_BASE_IDX 1 +#define regGRTAVFS_TARG_VOLT 0x4b07 +#define regGRTAVFS_TARG_VOLT_BASE_IDX 1 +#define regGRTAVFS_SOFT_RESET 0x4b0c +#define regGRTAVFS_SOFT_RESET_BASE_IDX 1 +#define regGRTAVFS_PSM_CNTL 0x4b0d +#define regGRTAVFS_PSM_CNTL_BASE_IDX 1 +#define regGRTAVFS_CLK_CNTL 0x4b0e +#define regGRTAVFS_CLK_CNTL_BASE_IDX 1 + + +// addressBlock: gc_grtavfs_se_grtavfs_dec +// base address: 0x3ad00 +#define regGRTAVFS_SE_RTAVFS_REG_ADDR 0x4b40 +#define regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_WR_DATA 0x4b41 +#define regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX 1 +#define regGRTAVFS_SE_GENERAL_0 0x4b42 +#define regGRTAVFS_SE_GENERAL_0_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_RD_DATA 0x4b43 +#define regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_REG_CTRL 0x4b44 +#define regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX 1 +#define regGRTAVFS_SE_RTAVFS_REG_STATUS 0x4b45 +#define regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX 1 +#define regGRTAVFS_SE_TARG_FREQ 0x4b46 +#define regGRTAVFS_SE_TARG_FREQ_BASE_IDX 1 +#define regGRTAVFS_SE_TARG_VOLT 0x4b47 +#define regGRTAVFS_SE_TARG_VOLT_BASE_IDX 1 +#define regGRTAVFS_SE_SOFT_RESET 0x4b4c +#define regGRTAVFS_SE_SOFT_RESET_BASE_IDX 1 +#define regGRTAVFS_SE_PSM_CNTL 0x4b4d +#define regGRTAVFS_SE_PSM_CNTL_BASE_IDX 1 +#define regGRTAVFS_SE_CLK_CNTL 0x4b4e +#define regGRTAVFS_SE_CLK_CNTL_BASE_IDX 1 + + +// addressBlock: gc_grtavfsdec +// base address: 0x3ac00 +#define regRTAVFS_RTAVFS_REG_ADDR 0x4b00 +#define regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 +#define regRTAVFS_RTAVFS_WR_DATA 0x4b01 +#define regRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 + + +// addressBlock: gc_cphypdec +// base address: 0x3e000 +#define regCP_HYP_PFP_UCODE_ADDR 0x5814 +#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_PFP_UCODE_ADDR 0x5814 +#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_DATA 0x5815 +#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_UCODE_DATA 0x5815 +#define regCP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_ADDR 0x5816 +#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 +#define regCP_ME_RAM_RADDR 0x5816 +#define regCP_ME_RAM_RADDR_BASE_IDX 1 +#define regCP_ME_RAM_WADDR 0x5816 +#define regCP_ME_RAM_WADDR_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_DATA 0x5817 +#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 +#define regCP_ME_RAM_DATA 0x5817 +#define regCP_ME_RAM_DATA_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_ADDR 0x581a +#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_ADDR 0x581a +#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_DATA 0x581b +#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_DATA 0x581b +#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_ADDR 0x581c +#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_ADDR 0x581c +#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_DATA 0x581d +#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_DATA 0x581d +#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_IC_BASE_LO 0x5840 +#define regCP_PFP_IC_BASE_LO_BASE_IDX 1 +#define regCP_PFP_IC_BASE_HI 0x5841 +#define regCP_PFP_IC_BASE_HI_BASE_IDX 1 +#define regCP_PFP_IC_BASE_CNTL 0x5842 +#define regCP_PFP_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_PFP_IC_OP_CNTL 0x5843 +#define regCP_PFP_IC_OP_CNTL_BASE_IDX 1 +#define regCP_ME_IC_BASE_LO 0x5844 +#define regCP_ME_IC_BASE_LO_BASE_IDX 1 +#define regCP_ME_IC_BASE_HI 0x5845 +#define regCP_ME_IC_BASE_HI_BASE_IDX 1 +#define regCP_ME_IC_BASE_CNTL 0x5846 +#define regCP_ME_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_ME_IC_OP_CNTL 0x5847 +#define regCP_ME_IC_OP_CNTL_BASE_IDX 1 +#define regCP_CPC_IC_BASE_LO 0x584c +#define regCP_CPC_IC_BASE_LO_BASE_IDX 1 +#define regCP_CPC_IC_BASE_HI 0x584d +#define regCP_CPC_IC_BASE_HI_BASE_IDX 1 +#define regCP_CPC_IC_BASE_CNTL 0x584e +#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_IC_BASE_LO 0x5850 +#define regCP_MES_IC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MIBASE_LO 0x5850 +#define regCP_MES_MIBASE_LO_BASE_IDX 1 +#define regCP_MES_IC_BASE_HI 0x5851 +#define regCP_MES_IC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MIBASE_HI 0x5851 +#define regCP_MES_MIBASE_HI_BASE_IDX 1 +#define regCP_MES_IC_BASE_CNTL 0x5852 +#define regCP_MES_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_BASE_LO 0x5854 +#define regCP_MES_DC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MDBASE_LO 0x5854 +#define regCP_MES_MDBASE_LO_BASE_IDX 1 +#define regCP_MES_DC_BASE_HI 0x5855 +#define regCP_MES_DC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MDBASE_HI 0x5855 +#define regCP_MES_MDBASE_HI_BASE_IDX 1 +#define regCP_MES_MIBOUND_LO 0x585b +#define regCP_MES_MIBOUND_LO_BASE_IDX 1 +#define regCP_MES_MIBOUND_HI 0x585c +#define regCP_MES_MIBOUND_HI_BASE_IDX 1 +#define regCP_MES_MDBOUND_LO 0x585d +#define regCP_MES_MDBOUND_LO_BASE_IDX 1 +#define regCP_MES_MDBOUND_HI 0x585e +#define regCP_MES_MDBOUND_HI_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_LO 0x5863 +#define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_LO 0x5864 +#define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_HI 0x5865 +#define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_HI 0x5866 +#define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_LO 0x586c +#define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_HI 0x586d +#define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_LO 0x5870 +#define regCP_MEC_DC_BASE_LO_BASE_IDX 1 +#define regCP_MEC_MDBASE_LO 0x5870 +#define regCP_MEC_MDBASE_LO_BASE_IDX 1 +#define regCP_MEC_DC_BASE_HI 0x5871 +#define regCP_MEC_DC_BASE_HI_BASE_IDX 1 +#define regCP_MEC_MDBASE_HI 0x5871 +#define regCP_MEC_MDBASE_HI_BASE_IDX 1 +#define regCP_MEC_MIBOUND_LO 0x5872 +#define regCP_MEC_MIBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MIBOUND_HI 0x5873 +#define regCP_MEC_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_MDBOUND_LO 0x5874 +#define regCP_MEC_MDBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MDBOUND_HI 0x5875 +#define regCP_MEC_MDBOUND_HI_BASE_IDX 1 + + +// addressBlock: gc_rlcdec +// base address: 0x3b000 +#define regRLC_CNTL 0x4c00 +#define regRLC_CNTL_BASE_IDX 1 +#define regRLC_F32_UCODE_VERSION 0x4c03 +#define regRLC_F32_UCODE_VERSION_BASE_IDX 1 +#define regRLC_STAT 0x4c04 +#define regRLC_STAT_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c +#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d +#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_0 0x4c0e +#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_1 0x4c0f +#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_2 0x4c10 +#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_3 0x4c11 +#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_4 0x4c12 +#define regRLC_GPM_TIMER_INT_4_BASE_IDX 1 +#define regRLC_GPM_TIMER_CTRL 0x4c13 +#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 +#define regRLC_GPM_TIMER_STAT 0x4c14 +#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_STAT 0x4c16 +#define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_CLEAR 0x4c17 +#define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX 1 +#define regRLC_INT_STAT 0x4c18 +#define regRLC_INT_STAT_BASE_IDX 1 +#define regRLC_MGCG_CTRL 0x4c1a +#define regRLC_MGCG_CTRL_BASE_IDX 1 +#define regRLC_JUMP_TABLE_RESTORE 0x4c1e +#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 +#define regRLC_PG_DELAY_2 0x4c1f +#define regRLC_PG_DELAY_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 +#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 +#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 +#define regRLC_UCODE_CNTL 0x4c27 +#define regRLC_UCODE_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_RESET 0x4c28 +#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 +#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a +#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 +#define regRLC_GPM_THREAD_INVALIDATE_CACHE 0x4c2b +#define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 +#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 +#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 +#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 +#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_CTRL 0x4c34 +#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 +#define regRLC_CLK_COUNT_STAT 0x4c35 +#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_CNTL 0x4c36 +#define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_STAT 0x4c37 +#define regRLC_RLCG_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_LO 0x4c38 +#define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_HI 0x4c39 +#define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_LO 0x4c3a +#define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_HI 0x4c3b +#define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_LO 0x4c3c +#define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_HI 0x4c3d +#define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_LO 0x4c3e +#define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_HI 0x4c3f +#define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 +#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32 0x4c42 +#define regRLC_GPU_CLOCK_32_BASE_IDX 1 +#define regRLC_PG_CNTL 0x4c43 +#define regRLC_PG_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_PRIORITY 0x4c44 +#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 +#define regRLC_GPM_THREAD_ENABLE 0x4c45 +#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_RANGE 0x4c47 +#define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 +#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL 0x4c49 +#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL 0x4c4a +#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 +#define regRLC_DYN_PG_STATUS 0x4c4b +#define regRLC_DYN_PG_STATUS_BASE_IDX 1 +#define regRLC_DYN_PG_REQUEST 0x4c4c +#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 +#define regRLC_PG_DELAY 0x4c4d +#define regRLC_PG_DELAY_BASE_IDX 1 +#define regRLC_WGP_STATUS 0x4c4e +#define regRLC_WGP_STATUS_BASE_IDX 1 +#define regRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53 +#define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1 +#define regRLC_MAX_PG_WGP 0x4c54 +#define regRLC_MAX_PG_WGP_BASE_IDX 1 +#define regRLC_AUTO_PG_CTRL 0x4c55 +#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 +#define regRLC_SERDES_RD_INDEX 0x4c59 +#define regRLC_SERDES_RD_INDEX_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_0 0x4c5a +#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_1 0x4c5b +#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_2 0x4c5c +#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_3 0x4c5d +#define regRLC_SERDES_RD_DATA_3_BASE_IDX 1 +#define regRLC_SERDES_MASK 0x4c5e +#define regRLC_SERDES_MASK_BASE_IDX 1 +#define regRLC_SERDES_CTRL 0x4c5f +#define regRLC_SERDES_CTRL_BASE_IDX 1 +#define regRLC_SERDES_DATA 0x4c60 +#define regRLC_SERDES_DATA_BASE_IDX 1 +#define regRLC_SERDES_BUSY 0x4c61 +#define regRLC_SERDES_BUSY_BASE_IDX 1 +#define regRLC_GPM_GENERAL_0 0x4c63 +#define regRLC_GPM_GENERAL_0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_1 0x4c64 +#define regRLC_GPM_GENERAL_1_BASE_IDX 1 +#define regRLC_GPM_GENERAL_2 0x4c65 +#define regRLC_GPM_GENERAL_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_3 0x4c66 +#define regRLC_GPM_GENERAL_3_BASE_IDX 1 +#define regRLC_GPM_GENERAL_4 0x4c67 +#define regRLC_GPM_GENERAL_4_BASE_IDX 1 +#define regRLC_GPM_GENERAL_5 0x4c68 +#define regRLC_GPM_GENERAL_5_BASE_IDX 1 +#define regRLC_GPM_GENERAL_6 0x4c69 +#define regRLC_GPM_GENERAL_6_BASE_IDX 1 +#define regRLC_GPM_GENERAL_7 0x4c6a +#define regRLC_GPM_GENERAL_7_BASE_IDX 1 +#define regRLC_STATIC_PG_STATUS 0x4c6e +#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 +#define regRLC_GPM_GENERAL_16 0x4c76 +#define regRLC_GPM_GENERAL_16_BASE_IDX 1 +#define regRLC_PG_DELAY_3 0x4c78 +#define regRLC_PG_DELAY_3_BASE_IDX 1 +#define regRLC_GPR_REG1 0x4c79 +#define regRLC_GPR_REG1_BASE_IDX 1 +#define regRLC_GPR_REG2 0x4c7a +#define regRLC_GPR_REG2_BASE_IDX 1 +#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c +#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_DISABLE 0x4c7d +#define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH0 0x4c7e +#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 +#define regRLC_SRM_CNTL 0x4c80 +#define regRLC_SRM_CNTL_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 +#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b +#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c +#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d +#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e +#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f +#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 +#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 +#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 +#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 +#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 +#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 +#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 +#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 +#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 +#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 +#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a +#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 +#define regRLC_SRM_STAT 0x4c9b +#define regRLC_SRM_STAT_BASE_IDX 1 +#define regRLC_GPM_GENERAL_8 0x4cad +#define regRLC_GPM_GENERAL_8_BASE_IDX 1 +#define regRLC_GPM_GENERAL_9 0x4cae +#define regRLC_GPM_GENERAL_9_BASE_IDX 1 +#define regRLC_GPM_GENERAL_10 0x4caf +#define regRLC_GPM_GENERAL_10_BASE_IDX 1 +#define regRLC_GPM_GENERAL_11 0x4cb0 +#define regRLC_GPM_GENERAL_11_BASE_IDX 1 +#define regRLC_GPM_GENERAL_12 0x4cb1 +#define regRLC_GPM_GENERAL_12_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 +#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 +#define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 +#define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_CNTL 0x4cb5 +#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_UTCL1_STATUS_2 0x4cb6 +#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc +#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd +#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe +#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 +#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 +#define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 +#define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 +#define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL_3D 0x4cc5 +#define regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL_3D 0x4cc6 +#define regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 +#define regRLC_SEMAPHORE_0 0x4cc7 +#define regRLC_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_SEMAPHORE_1 0x4cc8 +#define regRLC_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_SEMAPHORE_2 0x4cc9 +#define regRLC_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_3 0x4cca +#define regRLC_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_PACE_INT_STAT 0x4ccc +#define regRLC_PACE_INT_STAT_BASE_IDX 1 +#define regRLC_UTCL1_STATUS 0x4cd4 +#define regRLC_UTCL1_STATUS_BASE_IDX 1 +#define regRLC_R2I_CNTL_0 0x4cd5 +#define regRLC_R2I_CNTL_0_BASE_IDX 1 +#define regRLC_R2I_CNTL_1 0x4cd6 +#define regRLC_R2I_CNTL_1_BASE_IDX 1 +#define regRLC_R2I_CNTL_2 0x4cd7 +#define regRLC_R2I_CNTL_2_BASE_IDX 1 +#define regRLC_R2I_CNTL_3 0x4cd8 +#define regRLC_R2I_CNTL_3_BASE_IDX 1 +#define regRLC_GPM_INT_STAT_TH0 0x4cdc +#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_13 0x4cdd +#define regRLC_GPM_GENERAL_13_BASE_IDX 1 +#define regRLC_GPM_GENERAL_14 0x4cde +#define regRLC_GPM_GENERAL_14_BASE_IDX 1 +#define regRLC_GPM_GENERAL_15 0x4cdf +#define regRLC_GPM_GENERAL_15_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb +#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec +#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 +#define regRLC_PACE_INT_DISABLE 0x4ced +#define regRLC_PACE_INT_DISABLE_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_RANGE 0x4cf0 +#define regRLC_RLCV_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_CNTL 0x4cf1 +#define regRLC_RLCV_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_STAT 0x4cf2 +#define regRLC_RLCV_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_LO 0x4cf3 +#define regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_HI 0x4cf4 +#define regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_LO 0x4cf5 +#define regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_HI 0x4cf6 +#define regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_LO 0x4cf7 +#define regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_HI 0x4cf8 +#define regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_LO 0x4cf9 +#define regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_HI 0x4cfa +#define regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4cfb +#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4cfc +#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT 0x4d00 +#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 +#define regRLC_PACE_TIMER_INT_0 0x4d04 +#define regRLC_PACE_TIMER_INT_0_BASE_IDX 1 +#define regRLC_PACE_TIMER_INT_1 0x4d05 +#define regRLC_PACE_TIMER_INT_1_BASE_IDX 1 +#define regRLC_PACE_TIMER_CTRL 0x4d06 +#define regRLC_PACE_TIMER_CTRL_BASE_IDX 1 +#define regRLC_SMU_CLK_REQ 0x4d08 +#define regRLC_SMU_CLK_REQ_BASE_IDX 1 +#define regRLC_CP_STAT_INVAL_STAT 0x4d09 +#define regRLC_CP_STAT_INVAL_STAT_BASE_IDX 1 +#define regRLC_CP_STAT_INVAL_CTRL 0x4d0a +#define regRLC_CP_STAT_INVAL_CTRL_BASE_IDX 1 +#define regRLC_SPARE 0x4d0b +#define regRLC_SPARE_BASE_IDX 1 +#define regRLC_SPP_CTRL 0x4d0c +#define regRLC_SPP_CTRL_BASE_IDX 1 +#define regRLC_SPP_SHADER_PROFILE_EN 0x4d0d +#define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_CAPTURE_EN 0x4d0e +#define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_0 0x4d0f +#define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_1 0x4d10 +#define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_2 0x4d11 +#define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_ADDR 0x4d12 +#define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_DATA 0x4d13 +#define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_1 0x4d18 +#define regRLC_SPP_PROF_INFO_1_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_2 0x4d19 +#define regRLC_SPP_PROF_INFO_2_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID 0x4d1a +#define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b +#define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1 +#define regRLC_SPP_STATUS 0x4d1c +#define regRLC_SPP_STATUS_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_0 0x4d1d +#define regRLC_SPP_PVT_STAT_0_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_1 0x4d1e +#define regRLC_SPP_PVT_STAT_1_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_2 0x4d1f +#define regRLC_SPP_PVT_STAT_2_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_3 0x4d20 +#define regRLC_SPP_PVT_STAT_3_BASE_IDX 1 +#define regRLC_SPP_PVT_LEVEL_MAX 0x4d21 +#define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1 +#define regRLC_SPP_STALL_STATE_UPDATE 0x4d22 +#define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1 +#define regRLC_SPP_PBB_INFO 0x4d23 +#define regRLC_SPP_PBB_INFO_BASE_IDX 1 +#define regRLC_SPP_RESET 0x4d24 +#define regRLC_SPP_RESET_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_RANGE 0x4d26 +#define regRLC_RLCP_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_CNTL 0x4d27 +#define regRLC_RLCP_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_STAT 0x4d28 +#define regRLC_RLCP_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_0_DATA_LO 0x4d29 +#define regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_0_DATA_HI 0x4d2a +#define regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_1_DATA_LO 0x4d2b +#define regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_1_DATA_HI 0x4d2c +#define regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_2_DATA_LO 0x4d2d +#define regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_2_DATA_HI 0x4d2e +#define regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_3_DATA_LO 0x4d2f +#define regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCP_DOORBELL_3_DATA_HI 0x4d30 +#define regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_CAC_MASK_CNTL 0x4d45 +#define regRLC_CAC_MASK_CNTL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL 0x4d48 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL 0x4d49 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_CNTR_CTRL 0x4d4a +#define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_CNTR_CTRL 0x4d4b +#define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_CNTR_CTRL 0x4d4c +#define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL 0x4d4d +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR 0x4d50 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR 0x4d51 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_EVENT_CNTR 0x4d52 +#define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR 0x4d53 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR 0x4d54 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR 0x4d55 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_REF_CNTR 0x4d58 +#define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_REF_CNTR 0x4d59 +#define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_REF_CNTR 0x4d5a +#define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_REF_CNTR 0x4d5b +#define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_REF_CNTR 0x4d5c +#define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_REF_CNTR 0x4d5d +#define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_CTRL 0x4d5e +#define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX 1 +#define regRLC_GFX_IH_ARBITER_STAT 0x4d5f +#define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L 0x4d60 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H 0x4d61 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT 0x4d62 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT 0x4d63 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR 0x4d64 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA 0x4d65 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_ADDR 0x4d66 +#define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_DATA 0x4d67 +#define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_LX6_CNTL 0x4d80 +#define regRLC_LX6_CNTL_BASE_IDX 1 +#define regRLC_XT_CORE_STATUS 0x4dd4 +#define regRLC_XT_CORE_STATUS_BASE_IDX 1 +#define regRLC_XT_CORE_INTERRUPT 0x4dd5 +#define regRLC_XT_CORE_INTERRUPT_BASE_IDX 1 +#define regRLC_XT_CORE_FAULT_INFO 0x4dd6 +#define regRLC_XT_CORE_FAULT_INFO_BASE_IDX 1 +#define regRLC_XT_CORE_ALT_RESET_VEC 0x4dd7 +#define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX 1 +#define regRLC_XT_CORE_RESERVED 0x4dd8 +#define regRLC_XT_CORE_RESERVED_BASE_IDX 1 +#define regRLC_XT_INT_VEC_FORCE 0x4dd9 +#define regRLC_XT_INT_VEC_FORCE_BASE_IDX 1 +#define regRLC_XT_INT_VEC_CLEAR 0x4dda +#define regRLC_XT_INT_VEC_CLEAR_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_SEL 0x4ddb +#define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_INT_SEL 0x4ddc +#define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1 +#define regRLC_SPM_THREAD_TRACE_CTRL 0x4de6 +#define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regRLC_SPP_CAM_ADDR 0x4de8 +#define regRLC_SPP_CAM_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_DATA 0x4de9 +#define regRLC_SPP_CAM_DATA_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_ADDR 0x4dea +#define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_DATA 0x4deb +#define regRLC_SPP_CAM_EXT_DATA_BASE_IDX 1 +#define regRLC_XT_DOORBELL_RANGE 0x4df5 +#define regRLC_XT_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_XT_DOORBELL_CNTL 0x4df6 +#define regRLC_XT_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_XT_DOORBELL_STAT 0x4df7 +#define regRLC_XT_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_LO 0x4df8 +#define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_HI 0x4df9 +#define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_LO 0x4dfa +#define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_HI 0x4dfb +#define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_LO 0x4dfc +#define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_HI 0x4dfd +#define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_LO 0x4dfe +#define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_HI 0x4dff +#define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_MEM_SLP_CNTL 0x4e00 +#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 +#define regSMU_RLC_RESPONSE 0x4e01 +#define regSMU_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_RLCV_SAFE_MODE 0x4e02 +#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 +#define regRLC_SMU_SAFE_MODE 0x4e03 +#define regRLC_SMU_SAFE_MODE_BASE_IDX 1 +#define regRLC_RLCV_COMMAND 0x4e04 +#define regRLC_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_SMU_MESSAGE 0x4e05 +#define regRLC_SMU_MESSAGE_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_1 0x4e06 +#define regRLC_SMU_MESSAGE_1_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_2 0x4e07 +#define regRLC_SMU_MESSAGE_2_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND 0x4e08 +#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 +#define regRLC_SRM_GPM_ABORT 0x4e09 +#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 +#define regRLC_SMU_COMMAND 0x4e0a +#define regRLC_SMU_COMMAND_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_1 0x4e0b +#define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_2 0x4e0c +#define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_3 0x4e0d +#define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_4 0x4e0e +#define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_5 0x4e0f +#define regRLC_SMU_ARGUMENT_5_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_HI 0x4e10 +#define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_LO 0x4e11 +#define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_SIZE 0x4e12 +#define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX 1 +#define regRLC_IMU_MISC 0x4e16 +#define regRLC_IMU_MISC_BASE_IDX 1 +#define regRLC_IMU_RESET_VECTOR 0x4e17 +#define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 + + +// addressBlock: gc_rlcsdec +// base address: 0x3b980 +#define regRLC_RLCS_DEC_START 0x4e60 +#define regRLC_RLCS_DEC_START_BASE_IDX 1 +#define regRLC_RLCS_DEC_DUMP_ADDR 0x4e61 +#define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_1 0x4e62 +#define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_2 0x4e63 +#define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_3 0x4e64 +#define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_4 0x4e65 +#define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1 +#define regRLC_RLCS_CGCG_REQUEST 0x4e66 +#define regRLC_RLCS_CGCG_REQUEST_BASE_IDX 1 +#define regRLC_RLCS_CGCG_STATUS 0x4e67 +#define regRLC_RLCS_CGCG_STATUS_BASE_IDX 1 +#define regRLC_RLCS_SOC_DS_CNTL 0x4e68 +#define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_CNTL 0x4e69 +#define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL 0x4e6a +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX 1 +#define regRLC_GPM_STAT 0x4e6b +#define regRLC_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT 0x4e6b +#define regRLC_RLCS_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6c +#define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1 +#define regRLC_RLCS_DIDT_FORCE_STALL 0x4e6d +#define regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX 1 +#define regRLC_RLCS_IOV_CMD_STATUS 0x4e6e +#define regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e6f +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1 +#define regRLC_RLCS_IOV_SCH_BLOCK 0x4e70 +#define regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e71 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT_2 0x4e72 +#define regRLC_RLCS_GPM_STAT_2_BASE_IDX 1 +#define regRLC_RLCS_GRBM_SOFT_RESET 0x4e73 +#define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_STATUS 0x4e74 +#define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_READ 0x4e75 +#define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1 +#define regRLC_RLCS_IH_SEMAPHORE 0x4e76 +#define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e77 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_WGP_STATUS 0x4e78 +#define regRLC_RLCS_WGP_STATUS_BASE_IDX 1 +#define regRLC_RLCS_WGP_READ 0x4e79 +#define regRLC_RLCS_WGP_READ_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_1 0x4e7a +#define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_2 0x4e7b +#define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_1 0x4e7c +#define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_2 0x4e7d +#define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_CTRL 0x4e7e +#define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_1 0x4e7f +#define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_2 0x4e80 +#define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_DSM_TRIG 0x4e81 +#define regRLC_RLCS_DSM_TRIG_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_STATUS 0x4e82 +#define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_POWER_BRAKE_CNTL 0x4e83 +#define regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_POWER_BRAKE_CNTL_TH1 0x4e84 +#define regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4e85 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4e86 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1 +#define regRLC_RLCS_CMP_IDLE_CNTL 0x4e87 +#define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_0 0x4e88 +#define regRLC_RLCS_GENERAL_0_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_1 0x4e89 +#define regRLC_RLCS_GENERAL_1_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_2 0x4e8a +#define regRLC_RLCS_GENERAL_2_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_3 0x4e8b +#define regRLC_RLCS_GENERAL_3_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_4 0x4e8c +#define regRLC_RLCS_GENERAL_4_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_5 0x4e8d +#define regRLC_RLCS_GENERAL_5_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_6 0x4e8e +#define regRLC_RLCS_GENERAL_6_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_7 0x4e8f +#define regRLC_RLCS_GENERAL_7_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_8 0x4e90 +#define regRLC_RLCS_GENERAL_8_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_9 0x4e91 +#define regRLC_RLCS_GENERAL_9_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_10 0x4e92 +#define regRLC_RLCS_GENERAL_10_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_11 0x4e93 +#define regRLC_RLCS_GENERAL_11_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_12 0x4e94 +#define regRLC_RLCS_GENERAL_12_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_13 0x4e95 +#define regRLC_RLCS_GENERAL_13_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_14 0x4e96 +#define regRLC_RLCS_GENERAL_14_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_15 0x4e97 +#define regRLC_RLCS_GENERAL_15_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_16 0x4e98 +#define regRLC_RLCS_GENERAL_16_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_1 0x4ec5 +#define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_2 0x4ec6 +#define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_3 0x4ec7 +#define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_4 0x4ec8 +#define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1 +#define regRLC_RLCS_SPM_SQTT_MODE 0x4ec9 +#define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1 +#define regRLC_RLCS_CP_DMA_SRCID_OVER 0x4eca +#define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4ecb +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4ecc +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1 +#define regRLC_RLCS_IMU_VIDCHG_CNTL 0x4ecd +#define regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_EDC_INT_CNTL 0x4ece +#define regRLC_RLCS_EDC_INT_CNTL_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL1 0x4ecf +#define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL2 0x4ed0 +#define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_STAT 0x4ed1 +#define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE 0x4ed2 +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_RLCS_SRM_SRCID_CNTL 0x4ed3 +#define regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_0 0x4ed4 +#define regRLC_RLCS_GCR_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_1 0x4ed5 +#define regRLC_RLCS_GCR_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_2 0x4ed6 +#define regRLC_RLCS_GCR_DATA_2_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_3 0x4ed7 +#define regRLC_RLCS_GCR_DATA_3_BASE_IDX 1 +#define regRLC_RLCS_GCR_STATUS 0x4ed8 +#define regRLC_RLCS_GCR_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0x4ed9 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_CNTL 0x4eda +#define regRLC_RLCS_UTCL2_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA0 0x4edb +#define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA1 0x4edc +#define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA2 0x4edd +#define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA3 0x4ede +#define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA4 0x4edf +#define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL 0x4ee0 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL 0x4ee1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0 0x4ee2 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL 0x4ee3 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL 0x4ee4 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 0x4ee5 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 0x4ee6 +#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL 0x4ee7 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_STATUS 0x4ee8 +#define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_STATUS 0x4ee9 +#define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_1 0x4eea +#define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB 0x4eeb +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB 0x4eec +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_0 0x4eed +#define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB 0x4eee +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB 0x4eef +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_CNTL 0x4ef0 +#define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE 0x4ef1 +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_1 0x4ef3 +#define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_2 0x4ef4 +#define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_STAT 0x4ef5 +#define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_INFO 0x4ef6 +#define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX 1 +#define regRLC_RLCS_PMM_CGCG_CNTL 0x4ef7 +#define regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO 0x4ef8 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX 1 +#define regRLC_RLCS_GFX_RM_CNTL 0x4efa +#define regRLC_RLCS_GFX_RM_CNTL_BASE_IDX 1 +#define regRLC_RLCS_DEC_END 0x4fff +#define regRLC_RLCS_DEC_END_BASE_IDX 1 + + +// addressBlock: gc_pfvfdec_rlc +// base address: 0x2a600 +#define regRLC_SAFE_MODE 0x0980 +#define regRLC_SAFE_MODE_BASE_IDX 1 +#define regRLC_SPM_SAMPLE_CNT 0x0981 +#define regRLC_SPM_SAMPLE_CNT_BASE_IDX 1 +#define regRLC_SPM_MC_CNTL 0x0982 +#define regRLC_SPM_MC_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_CNTL 0x0983 +#define regRLC_SPM_INT_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_STATUS 0x0984 +#define regRLC_SPM_INT_STATUS_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_1 0x0985 +#define regRLC_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_2 0x0986 +#define regRLC_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_CSIB_ADDR_LO 0x0987 +#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 +#define regRLC_CSIB_ADDR_HI 0x0988 +#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 +#define regRLC_CSIB_LENGTH 0x0989 +#define regRLC_CSIB_LENGTH_BASE_IDX 1 +#define regRLC_CP_SCHEDULERS 0x098a +#define regRLC_CP_SCHEDULERS_BASE_IDX 1 +#define regRLC_CP_EOF_INT 0x098b +#define regRLC_CP_EOF_INT_BASE_IDX 1 +#define regRLC_CP_EOF_INT_CNT 0x098c +#define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 +#define regRLC_SPARE_INT_0 0x098d +#define regRLC_SPARE_INT_0_BASE_IDX 1 +#define regRLC_SPARE_INT_1 0x098e +#define regRLC_SPARE_INT_1_BASE_IDX 1 +#define regRLC_SPARE_INT_2 0x098f +#define regRLC_SPARE_INT_2_BASE_IDX 1 +#define regRLC_PACE_SPARE_INT 0x0990 +#define regRLC_PACE_SPARE_INT_BASE_IDX 1 +#define regRLC_PACE_SPARE_INT_1 0x0991 +#define regRLC_PACE_SPARE_INT_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT_1 0x0992 +#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 + + +// addressBlock: gc_pwrdec +// base address: 0x3c000 +#define regCGTS_TCC_DISABLE 0x5006 +#define regCGTS_TCC_DISABLE_BASE_IDX 1 +#define regCGTT_GS_NGG_CLK_CTRL 0x5087 +#define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PA_CLK_CTRL 0x5088 +#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL0 0x5089 +#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL1 0x508a +#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL2 0x508b +#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_SQG_CLK_CTRL 0x508d +#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 +#define regSQ_ALU_CLK_CTRL 0x508e +#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 +#define regSQ_TEX_CLK_CTRL 0x508f +#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 +#define regSQ_LDS_CLK_CTRL 0x5090 +#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 +#define regICG_SP_CLK_CTRL 0x5093 +#define regICG_SP_CLK_CTRL_BASE_IDX 1 +#define regTA_CGTT_CTRL 0x509d +#define regTA_CGTT_CTRL_BASE_IDX 1 +#define regDB_CGTT_CLK_CTRL_0 0x50a4 +#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 +#define regCB_CGTT_SCLK_CTRL 0x50a8 +#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regCGTT_CP_CLK_CTRL 0x50b0 +#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPF_CLK_CTRL 0x50b1 +#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPC_CLK_CTRL 0x50b2 +#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_RLC_CLK_CTRL 0x50b5 +#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL3 0x50bc +#define regCGTT_SC_CLK_CTRL3_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL4 0x50bd +#define regCGTT_SC_CLK_CTRL4_BASE_IDX 1 +#define regGCEA_ICG_CTRL 0x50c4 +#define regGCEA_ICG_CTRL_BASE_IDX 1 +#define regGL1I_GL1R_MGCG_OVERRIDE 0x50e4 +#define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX 1 +#define regGL1H_ICG_CTRL 0x50e8 +#define regGL1H_ICG_CTRL_BASE_IDX 1 +#define regCHI_CHR_MGCG_OVERRIDE 0x50e9 +#define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_GL1C_CLK_CTRL 0x50ec +#define regICG_GL1C_CLK_CTRL_BASE_IDX 1 +#define regICG_GL1A_CTRL 0x50f0 +#define regICG_GL1A_CTRL_BASE_IDX 1 +#define regICG_CHA_CTRL 0x50f1 +#define regICG_CHA_CTRL_BASE_IDX 1 +#define regGUS_ICG_CTRL 0x50f4 +#define regGUS_ICG_CTRL_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL0 0x50f8 +#define regCGTT_PH_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL1 0x50f9 +#define regCGTT_PH_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL2 0x50fa +#define regCGTT_PH_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL3 0x50fb +#define regCGTT_PH_CLK_CTRL3_BASE_IDX 1 +#define regGFX_ICG_GL2C_CTRL 0x50fc +#define regGFX_ICG_GL2C_CTRL_BASE_IDX 1 +#define regGFX_ICG_GL2C_CTRL1 0x50fd +#define regGFX_ICG_GL2C_CTRL1_BASE_IDX 1 +#define regICG_LDS_CLK_CTRL 0x5114 +#define regICG_LDS_CLK_CTRL_BASE_IDX 1 +#define regICG_CHC_CLK_CTRL 0x5140 +#define regICG_CHC_CLK_CTRL_BASE_IDX 1 +#define regICG_CHCG_CLK_CTRL 0x5144 +#define regICG_CHCG_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: gc_hypdec +// base address: 0x3e000 +#define regGFX_PIPE_PRIORITY 0x587f +#define regGFX_PIPE_PRIORITY_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 +#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_DATA 0x5a01 +#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 +#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_DATA 0x5a03 +#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 +#define regGC_IH_COOKIE_0_PTR 0x5a07 +#define regGC_IH_COOKIE_0_PTR_BASE_IDX 1 +#define regGRBM_SE_REMAP_CNTL 0x5a08 +#define regGRBM_SE_REMAP_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 +#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG6 0x5b06 +#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 +#define regRLC_SDMA0_STATUS 0x5b18 +#define regRLC_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_STATUS 0x5b19 +#define regRLC_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_STATUS 0x5b1a +#define regRLC_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_STATUS 0x5b1b +#define regRLC_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_SDMA0_BUSY_STATUS 0x5b1c +#define regRLC_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_BUSY_STATUS 0x5b1d +#define regRLC_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_BUSY_STATUS 0x5b1e +#define regRLC_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_BUSY_STATUS 0x5b1f +#define regRLC_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG8 0x5b20 +#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_0 0x5b25 +#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_1 0x5b26 +#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 +#define regRLC_RLCV_TIMER_CTRL 0x5b27 +#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 +#define regRLC_RLCV_TIMER_STAT 0x5b28 +#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_MASK 0x5b2d +#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_0 0x5b2e +#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_1 0x5b2f +#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_BUSY_CLK_CNTL 0x5b30 +#define regRLC_BUSY_CLK_CNTL_BASE_IDX 1 +#define regRLC_CLK_CNTL 0x5b31 +#define regRLC_CLK_CNTL_BASE_IDX 1 +#define regRLC_PACE_TIMER_STAT 0x5b33 +#define regRLC_PACE_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 +#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG1 0x5b35 +#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG2 0x5b36 +#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 +#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 +#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_0 0x5b38 +#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_3 0x5b3a +#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_1 0x5b3b +#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_2 0x5b3c +#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 +#define regRLC_PACE_INT_FORCE 0x5b3d +#define regRLC_PACE_INT_FORCE_BASE_IDX 1 +#define regRLC_PACE_INT_CLEAR 0x5b3e +#define regRLC_PACE_INT_CLEAR_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_STAT 0x5b3f +#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 +#define regRLC_IH_COOKIE 0x5b41 +#define regRLC_IH_COOKIE_BASE_IDX 1 +#define regRLC_IH_COOKIE_CNTL 0x5b42 +#define regRLC_IH_COOKIE_CNTL_BASE_IDX 1 +#define regRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43 +#define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_HYP_RLCP_UCODE_CHKSUM 0x5b44 +#define regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_HYP_RLCV_UCODE_CHKSUM 0x5b45 +#define regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_CNTL 0x5b46 +#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_RESET 0x5b47 +#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_ADDR 0x5b48 +#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_DATA 0x5b49 +#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a +#define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_INVALIDATE_CACHE 0x5b4b +#define regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX 1 +#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d +#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_DISABLE 0x5b4e +#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_FORCE 0x5b4f +#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b50 +#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_DATA 0x5b51 +#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_2 0x5b52 +#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_3 0x5b53 +#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_GPM_UCODE_ADDR 0x5b60 +#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPM_UCODE_DATA 0x5b61 +#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPM_IRAM_ADDR 0x5b62 +#define regRLC_GPM_IRAM_ADDR_BASE_IDX 1 +#define regRLC_GPM_IRAM_DATA 0x5b63 +#define regRLC_GPM_IRAM_DATA_BASE_IDX 1 +#define regRLC_RLCP_IRAM_ADDR 0x5b64 +#define regRLC_RLCP_IRAM_ADDR_BASE_IDX 1 +#define regRLC_RLCP_IRAM_DATA 0x5b65 +#define regRLC_RLCP_IRAM_DATA_BASE_IDX 1 +#define regRLC_RLCV_IRAM_ADDR 0x5b66 +#define regRLC_RLCV_IRAM_ADDR_BASE_IDX 1 +#define regRLC_RLCV_IRAM_DATA 0x5b67 +#define regRLC_RLCV_IRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_DRAM_ADDR 0x5b68 +#define regRLC_LX6_DRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_DRAM_DATA 0x5b69 +#define regRLC_LX6_DRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_IRAM_ADDR 0x5b6a +#define regRLC_LX6_IRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_IRAM_DATA 0x5b6b +#define regRLC_LX6_IRAM_DATA_BASE_IDX 1 +#define regRLC_PACE_UCODE_ADDR 0x5b6c +#define regRLC_PACE_UCODE_ADDR_BASE_IDX 1 +#define regRLC_PACE_UCODE_DATA 0x5b6d +#define regRLC_PACE_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_ADDR 0x5b6e +#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_DATA 0x5b6f +#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_SRM_DRAM_ADDR 0x5b71 +#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_DRAM_DATA 0x5b72 +#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 +#define regRLC_SRM_ARAM_ADDR 0x5b73 +#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_ARAM_DATA 0x5b74 +#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 +#define regRLC_PACE_SCRATCH_ADDR 0x5b77 +#define regRLC_PACE_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_PACE_SCRATCH_DATA 0x5b78 +#define regRLC_PACE_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_GTS_OFFSET_LSB 0x5b79 +#define regRLC_GTS_OFFSET_LSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_MSB 0x5b7a +#define regRLC_GTS_OFFSET_MSB_BASE_IDX 1 +#define regGL2_PIPE_STEER_0 0x5b80 +#define regGL2_PIPE_STEER_0_BASE_IDX 1 +#define regGL2_PIPE_STEER_1 0x5b81 +#define regGL2_PIPE_STEER_1_BASE_IDX 1 +#define regGL2_PIPE_STEER_2 0x5b82 +#define regGL2_PIPE_STEER_2_BASE_IDX 1 +#define regGL2_PIPE_STEER_3 0x5b83 +#define regGL2_PIPE_STEER_3_BASE_IDX 1 +#define regGL1_PIPE_STEER 0x5b84 +#define regGL1_PIPE_STEER_BASE_IDX 1 +#define regCH_PIPE_STEER 0x5b88 +#define regCH_PIPE_STEER_BASE_IDX 1 +#define regGC_USER_SHADER_ARRAY_CONFIG 0x5b90 +#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 1 +#define regGC_USER_PRIM_CONFIG 0x5b91 +#define regGC_USER_PRIM_CONFIG_BASE_IDX 1 +#define regGC_USER_SA_UNIT_DISABLE 0x5b92 +#define regGC_USER_SA_UNIT_DISABLE_BASE_IDX 1 +#define regGC_USER_RB_REDUNDANCY 0x5b93 +#define regGC_USER_RB_REDUNDANCY_BASE_IDX 1 +#define regGC_USER_RB_BACKEND_DISABLE 0x5b94 +#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 1 +#define regGC_USER_RMI_REDUNDANCY 0x5b95 +#define regGC_USER_RMI_REDUNDANCY_BASE_IDX 1 +#define regCGTS_USER_TCC_DISABLE 0x5b96 +#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 +#define regGC_USER_SHADER_RATE_CONFIG 0x5b97 +#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_STATUS 0x5bc0 +#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_STATUS 0x5bc1 +#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_STATUS 0x5bc2 +#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_STATUS 0x5bc3 +#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_STATUS 0x5bc4 +#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_STATUS 0x5bc5 +#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_STATUS 0x5bc6 +#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_STATUS 0x5bc7 +#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5bc8 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5bc9 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5bca +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5bcb +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5bcc +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5bcd +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5bce +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5bcf +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 + + +// addressBlock: gc_pspdec +// base address: 0x3f000 +#define regCP_MES_DM_INDEX_ADDR 0x5c00 +#define regCP_MES_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MES_DM_INDEX_DATA 0x5c01 +#define regCP_MES_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_ADDR 0x5c02 +#define regCP_MEC_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_DATA 0x5c03 +#define regCP_MEC_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_ADDR 0x5c04 +#define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_DATA 0x5c05 +#define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX 1 +#define regCPG_PSP_DEBUG 0x5c10 +#define regCPG_PSP_DEBUG_BASE_IDX 1 +#define regCPC_PSP_DEBUG 0x5c11 +#define regCPC_PSP_DEBUG_BASE_IDX 1 +#define regGRBM_SEC_CNTL 0x5e0d +#define regGRBM_SEC_CNTL_BASE_IDX 1 +#define regGRBM_CAM_INDEX 0x5e10 +#define regGRBM_CAM_INDEX_BASE_IDX 1 +#define regGRBM_HYP_CAM_INDEX 0x5e10 +#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 +#define regGRBM_CAM_DATA 0x5e11 +#define regGRBM_CAM_DATA_BASE_IDX 1 +#define regGRBM_HYP_CAM_DATA 0x5e11 +#define regGRBM_HYP_CAM_DATA_BASE_IDX 1 +#define regGRBM_CAM_DATA_UPPER 0x5e12 +#define regGRBM_CAM_DATA_UPPER_BASE_IDX 1 +#define regGRBM_HYP_CAM_DATA_UPPER 0x5e12 +#define regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX 1 +#define regRLC_FWL_FIRST_VIOL_ADDR 0x5f26 +#define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 + + +// addressBlock: gc_gfx_imu_gfx_imudec +// base address: 0x38000 +#define regGFX_IMU_C2PMSG_0 0x4000 +#define regGFX_IMU_C2PMSG_0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_1 0x4001 +#define regGFX_IMU_C2PMSG_1_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_2 0x4002 +#define regGFX_IMU_C2PMSG_2_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_3 0x4003 +#define regGFX_IMU_C2PMSG_3_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_4 0x4004 +#define regGFX_IMU_C2PMSG_4_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_5 0x4005 +#define regGFX_IMU_C2PMSG_5_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_6 0x4006 +#define regGFX_IMU_C2PMSG_6_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_7 0x4007 +#define regGFX_IMU_C2PMSG_7_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_8 0x4008 +#define regGFX_IMU_C2PMSG_8_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_9 0x4009 +#define regGFX_IMU_C2PMSG_9_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_10 0x400a +#define regGFX_IMU_C2PMSG_10_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_11 0x400b +#define regGFX_IMU_C2PMSG_11_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_12 0x400c +#define regGFX_IMU_C2PMSG_12_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_13 0x400d +#define regGFX_IMU_C2PMSG_13_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_14 0x400e +#define regGFX_IMU_C2PMSG_14_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_15 0x400f +#define regGFX_IMU_C2PMSG_15_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_16 0x4010 +#define regGFX_IMU_C2PMSG_16_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_17 0x4011 +#define regGFX_IMU_C2PMSG_17_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_18 0x4012 +#define regGFX_IMU_C2PMSG_18_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_19 0x4013 +#define regGFX_IMU_C2PMSG_19_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_20 0x4014 +#define regGFX_IMU_C2PMSG_20_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_21 0x4015 +#define regGFX_IMU_C2PMSG_21_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_22 0x4016 +#define regGFX_IMU_C2PMSG_22_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_23 0x4017 +#define regGFX_IMU_C2PMSG_23_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_24 0x4018 +#define regGFX_IMU_C2PMSG_24_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_25 0x4019 +#define regGFX_IMU_C2PMSG_25_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_26 0x401a +#define regGFX_IMU_C2PMSG_26_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_27 0x401b +#define regGFX_IMU_C2PMSG_27_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_28 0x401c +#define regGFX_IMU_C2PMSG_28_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_29 0x401d +#define regGFX_IMU_C2PMSG_29_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_30 0x401e +#define regGFX_IMU_C2PMSG_30_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_31 0x401f +#define regGFX_IMU_C2PMSG_31_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_32 0x4020 +#define regGFX_IMU_C2PMSG_32_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_33 0x4021 +#define regGFX_IMU_C2PMSG_33_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_34 0x4022 +#define regGFX_IMU_C2PMSG_34_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_35 0x4023 +#define regGFX_IMU_C2PMSG_35_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_36 0x4024 +#define regGFX_IMU_C2PMSG_36_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_37 0x4025 +#define regGFX_IMU_C2PMSG_37_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_38 0x4026 +#define regGFX_IMU_C2PMSG_38_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_39 0x4027 +#define regGFX_IMU_C2PMSG_39_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_40 0x4028 +#define regGFX_IMU_C2PMSG_40_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_41 0x4029 +#define regGFX_IMU_C2PMSG_41_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_42 0x402a +#define regGFX_IMU_C2PMSG_42_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_43 0x402b +#define regGFX_IMU_C2PMSG_43_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_44 0x402c +#define regGFX_IMU_C2PMSG_44_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_45 0x402d +#define regGFX_IMU_C2PMSG_45_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_46 0x402e +#define regGFX_IMU_C2PMSG_46_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_47 0x402f +#define regGFX_IMU_C2PMSG_47_BASE_IDX 1 +#define regGFX_IMU_MSG_FLAGS 0x403f +#define regGFX_IMU_MSG_FLAGS_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0 0x4040 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1 0x4041 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX 1 +#define regGFX_IMU_PWRMGT_IRQ_CTRL 0x4042 +#define regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX 1 +#define regGFX_IMU_MP1_MUTEX 0x4043 +#define regGFX_IMU_MP1_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_4 0x4046 +#define regGFX_IMU_RLC_DATA_4_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_3 0x4047 +#define regGFX_IMU_RLC_DATA_3_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_2 0x4048 +#define regGFX_IMU_RLC_DATA_2_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_1 0x4049 +#define regGFX_IMU_RLC_DATA_1_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_0 0x404a +#define regGFX_IMU_RLC_DATA_0_BASE_IDX 1 +#define regGFX_IMU_RLC_CMD 0x404b +#define regGFX_IMU_RLC_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_MUTEX 0x404c +#define regGFX_IMU_RLC_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_MSG_STATUS 0x404f +#define regGFX_IMU_RLC_MSG_STATUS_BASE_IDX 1 +#define regRLC_GFX_IMU_DATA_0 0x4052 +#define regRLC_GFX_IMU_DATA_0_BASE_IDX 1 +#define regRLC_GFX_IMU_CMD 0x4053 +#define regRLC_GFX_IMU_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_STATUS 0x4054 +#define regGFX_IMU_RLC_STATUS_BASE_IDX 1 +#define regGFX_IMU_STATUS 0x4055 +#define regGFX_IMU_STATUS_BASE_IDX 1 +#define regGFX_IMU_SOC_DATA 0x4059 +#define regGFX_IMU_SOC_DATA_BASE_IDX 1 +#define regGFX_IMU_SOC_ADDR 0x405a +#define regGFX_IMU_SOC_ADDR_BASE_IDX 1 +#define regGFX_IMU_SOC_REQ 0x405b +#define regGFX_IMU_SOC_REQ_BASE_IDX 1 +#define regGFX_IMU_VF_CTRL 0x405c +#define regGFX_IMU_VF_CTRL_BASE_IDX 1 +#define regGFX_IMU_TELEMETRY 0x4060 +#define regGFX_IMU_TELEMETRY_BASE_IDX 1 +#define regGFX_IMU_TELEMETRY_DATA 0x4061 +#define regGFX_IMU_TELEMETRY_DATA_BASE_IDX 1 +#define regGFX_IMU_TELEMETRY_TEMPERATURE 0x4062 +#define regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_0 0x4068 +#define regGFX_IMU_SCRATCH_0_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_1 0x4069 +#define regGFX_IMU_SCRATCH_1_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_2 0x406a +#define regGFX_IMU_SCRATCH_2_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_3 0x406b +#define regGFX_IMU_SCRATCH_3_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_4 0x406c +#define regGFX_IMU_SCRATCH_4_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_5 0x406d +#define regGFX_IMU_SCRATCH_5_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_6 0x406e +#define regGFX_IMU_SCRATCH_6_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_7 0x406f +#define regGFX_IMU_SCRATCH_7_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_8 0x4070 +#define regGFX_IMU_SCRATCH_8_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_9 0x4071 +#define regGFX_IMU_SCRATCH_9_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_10 0x4072 +#define regGFX_IMU_SCRATCH_10_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_11 0x4073 +#define regGFX_IMU_SCRATCH_11_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_12 0x4074 +#define regGFX_IMU_SCRATCH_12_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_13 0x4075 +#define regGFX_IMU_SCRATCH_13_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_14 0x4076 +#define regGFX_IMU_SCRATCH_14_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_15 0x4077 +#define regGFX_IMU_SCRATCH_15_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_LO 0x4078 +#define regGFX_IMU_FW_GTS_LO_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_HI 0x4079 +#define regGFX_IMU_FW_GTS_HI_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_LO 0x407a +#define regGFX_IMU_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_HI 0x407b +#define regGFX_IMU_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_LO 0x407c +#define regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_HI 0x407d +#define regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_CORE_INT_STATUS 0x407f +#define regGFX_IMU_CORE_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_MASK 0x4080 +#define regGFX_IMU_PIC_INT_MASK_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_LVL 0x4081 +#define regGFX_IMU_PIC_INT_LVL_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_EDGE 0x4082 +#define regGFX_IMU_PIC_INT_EDGE_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_0 0x4083 +#define regGFX_IMU_PIC_INT_PRI_0_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_1 0x4084 +#define regGFX_IMU_PIC_INT_PRI_1_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_2 0x4085 +#define regGFX_IMU_PIC_INT_PRI_2_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_3 0x4086 +#define regGFX_IMU_PIC_INT_PRI_3_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_4 0x4087 +#define regGFX_IMU_PIC_INT_PRI_4_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_5 0x4088 +#define regGFX_IMU_PIC_INT_PRI_5_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_6 0x4089 +#define regGFX_IMU_PIC_INT_PRI_6_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_7 0x408a +#define regGFX_IMU_PIC_INT_PRI_7_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_STATUS 0x408b +#define regGFX_IMU_PIC_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR 0x408c +#define regGFX_IMU_PIC_INTR_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR_ID 0x408d +#define regGFX_IMU_PIC_INTR_ID_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_1 0x4090 +#define regGFX_IMU_IH_CTRL_1_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_2 0x4091 +#define regGFX_IMU_IH_CTRL_2_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_3 0x4092 +#define regGFX_IMU_IH_CTRL_3_BASE_IDX 1 +#define regGFX_IMU_IH_STATUS 0x4093 +#define regGFX_IMU_IH_STATUS_BASE_IDX 1 +#define regGFX_IMU_FUSESTRAP 0x4094 +#define regGFX_IMU_SMUIO_VIDCHG_CTRL 0x4098 +#define regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX 1 +#define regGFX_IMU_GFXCLK_BYPASS_CTRL 0x409c +#define regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX 1 +#define regGFX_IMU_CLK_CTRL 0x409d +#define regGFX_IMU_CLK_CTRL_BASE_IDX 1 +#define regGFX_IMU_DOORBELL_CONTROL 0x409e +#define regGFX_IMU_DOORBELL_CONTROL_BASE_IDX 1 +#define regGFX_IMU_RLC_CG_CTRL 0x40a0 +#define regGFX_IMU_RLC_CG_CTRL_BASE_IDX 1 +#define regGFX_IMU_RLC_THROTTLE_GFX 0x40a1 +#define regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX 1 +#define regGFX_IMU_RLC_RESET_VECTOR 0x40a2 +#define regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX 1 +#define regGFX_IMU_RLC_OVERRIDE 0x40a3 +#define regGFX_IMU_RLC_OVERRIDE_BASE_IDX 1 +#define regGFX_IMU_DPM_CONTROL 0x40a8 +#define regGFX_IMU_DPM_CONTROL_BASE_IDX 1 +#define regGFX_IMU_DPM_ACC 0x40a9 +#define regGFX_IMU_DPM_ACC_BASE_IDX 1 +#define regGFX_IMU_DPM_REF_COUNTER 0x40aa +#define regGFX_IMU_DPM_REF_COUNTER_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_INDEX 0x40ac +#define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_HIGH 0x40ad +#define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_LOW 0x40ae +#define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_DATA 0x40af +#define regGFX_IMU_RLC_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_FENCE_CTRL 0x40b0 +#define regGFX_IMU_FENCE_CTRL_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_INIT 0x40b1 +#define regGFX_IMU_FENCE_LOG_INIT_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_ADDR 0x40b2 +#define regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX 1 +#define regGFX_IMU_PROGRAM_CTR 0x40b5 +#define regGFX_IMU_PROGRAM_CTR_BASE_IDX 1 +#define regGFX_IMU_CORE_CTRL 0x40b6 +#define regGFX_IMU_CORE_CTRL_BASE_IDX 1 +#define regGFX_IMU_CORE_STATUS 0x40b7 +#define regGFX_IMU_CORE_STATUS_BASE_IDX 1 +#define regGFX_IMU_PWROKRAW 0x40b8 +#define regGFX_IMU_PWROKRAW_BASE_IDX 1 +#define regGFX_IMU_PWROK 0x40b9 +#define regGFX_IMU_PWROK_BASE_IDX 1 +#define regGFX_IMU_GAP_PWROK 0x40ba +#define regGFX_IMU_GAP_PWROK_BASE_IDX 1 +#define regGFX_IMU_RESETn 0x40bb +#define regGFX_IMU_RESETn_BASE_IDX 1 +#define regGFX_IMU_GFX_RESET_CTRL 0x40bc +#define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_AEB_OVERRIDE 0x40bd +#define regGFX_IMU_AEB_OVERRIDE_BASE_IDX 1 +#define regGFX_IMU_VDCI_RESET_CTRL 0x40be +#define regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_GFX_ISO_CTRL 0x40bf +#define regGFX_IMU_GFX_ISO_CTRL_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL0 0x40c0 +#define regGFX_IMU_TIMER0_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL1 0x40c1 +#define regGFX_IMU_TIMER0_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_AUTOINC 0x40c2 +#define regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_INTEN 0x40c3 +#define regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP0 0x40c4 +#define regGFX_IMU_TIMER0_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP1 0x40c5 +#define regGFX_IMU_TIMER0_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP3 0x40c7 +#define regGFX_IMU_TIMER0_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER0_VALUE 0x40c8 +#define regGFX_IMU_TIMER0_VALUE_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL0 0x40c9 +#define regGFX_IMU_TIMER1_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL1 0x40ca +#define regGFX_IMU_TIMER1_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_AUTOINC 0x40cb +#define regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_INTEN 0x40cc +#define regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP0 0x40cd +#define regGFX_IMU_TIMER1_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP1 0x40ce +#define regGFX_IMU_TIMER1_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP3 0x40d0 +#define regGFX_IMU_TIMER1_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER1_VALUE 0x40d1 +#define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CTRL0 0x40d2 +#define regGFX_IMU_TIMER2_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CTRL1 0x40d3 +#define regGFX_IMU_TIMER2_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP_AUTOINC 0x40d4 +#define regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP_INTEN 0x40d5 +#define regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP0 0x40d6 +#define regGFX_IMU_TIMER2_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP1 0x40d7 +#define regGFX_IMU_TIMER2_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER2_CMP3 0x40d9 +#define regGFX_IMU_TIMER2_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER2_VALUE 0x40da +#define regGFX_IMU_TIMER2_VALUE_BASE_IDX 1 +#define regGFX_IMU_FUSE_CTRL 0x40e0 +#define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 +#define regGFX_IMU_D_RAM_ADDR 0x40fc +#define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_D_RAM_DATA 0x40fd +#define regGFX_IMU_D_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_GFX_IH_GASKET_CTRL 0x40ff +#define regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX 1 + + +// addressBlock: gc_gfx_imu_gfx_imu_pspdec +// base address: 0x3fe00 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI 0x5f81 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO 0x5f82 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE 0x5f83 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX 1 +#define regGFX_IMU_I_RAM_ADDR 0x5f90 +#define regGFX_IMU_I_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_I_RAM_DATA 0x5f91 +#define regGFX_IMU_I_RAM_DATA_BASE_IDX 1 + + +// addressBlock: gccacind +// base address: 0x0 +#define ixGC_CAC_ID 0x0000 +#define ixGC_CAC_CNTL 0x0001 +#define ixGC_CAC_ACC_CP0 0x0010 +#define ixGC_CAC_ACC_CP1 0x0011 +#define ixGC_CAC_ACC_CP2 0x0012 +#define ixGC_CAC_ACC_EA0 0x0013 +#define ixGC_CAC_ACC_EA1 0x0014 +#define ixGC_CAC_ACC_EA2 0x0015 +#define ixGC_CAC_ACC_EA3 0x0016 +#define ixGC_CAC_ACC_EA4 0x0017 +#define ixGC_CAC_ACC_EA5 0x0018 +#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x0019 +#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x001a +#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x001b +#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x001c +#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x001d +#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x001e +#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x001f +#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0020 +#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0021 +#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0022 +#define ixGC_CAC_ACC_UTCL2_VML20 0x0023 +#define ixGC_CAC_ACC_UTCL2_VML21 0x0024 +#define ixGC_CAC_ACC_UTCL2_VML22 0x0025 +#define ixGC_CAC_ACC_UTCL2_VML23 0x0026 +#define ixGC_CAC_ACC_UTCL2_VML24 0x0027 +#define ixGC_CAC_ACC_UTCL2_WALKER0 0x0028 +#define ixGC_CAC_ACC_UTCL2_WALKER1 0x0029 +#define ixGC_CAC_ACC_UTCL2_WALKER2 0x002a +#define ixGC_CAC_ACC_UTCL2_WALKER3 0x002b +#define ixGC_CAC_ACC_UTCL2_WALKER4 0x002c +#define ixGC_CAC_ACC_GDS0 0x002d +#define ixGC_CAC_ACC_GDS1 0x002e +#define ixGC_CAC_ACC_GDS2 0x002f +#define ixGC_CAC_ACC_GDS3 0x0030 +#define ixGC_CAC_ACC_GDS4 0x0031 +#define ixGC_CAC_ACC_GE0 0x0032 +#define ixGC_CAC_ACC_GE1 0x0033 +#define ixGC_CAC_ACC_GE2 0x0034 +#define ixGC_CAC_ACC_GE3 0x0035 +#define ixGC_CAC_ACC_GE4 0x0036 +#define ixGC_CAC_ACC_GE5 0x0037 +#define ixGC_CAC_ACC_GE6 0x0038 +#define ixGC_CAC_ACC_GE7 0x0039 +#define ixGC_CAC_ACC_GE8 0x003a +#define ixGC_CAC_ACC_GE9 0x003b +#define ixGC_CAC_ACC_GE10 0x003c +#define ixGC_CAC_ACC_GE11 0x003d +#define ixGC_CAC_ACC_GE12 0x003e +#define ixGC_CAC_ACC_GE13 0x003f +#define ixGC_CAC_ACC_GE14 0x0040 +#define ixGC_CAC_ACC_GE15 0x0041 +#define ixGC_CAC_ACC_GE16 0x0042 +#define ixGC_CAC_ACC_GE17 0x0043 +#define ixGC_CAC_ACC_GE18 0x0044 +#define ixGC_CAC_ACC_GE19 0x0045 +#define ixGC_CAC_ACC_GE20 0x0046 +#define ixGC_CAC_ACC_PMM0 0x0047 +#define ixGC_CAC_ACC_GL2C0 0x0048 +#define ixGC_CAC_ACC_GL2C1 0x0049 +#define ixGC_CAC_ACC_GL2C2 0x004a +#define ixGC_CAC_ACC_GL2C3 0x004b +#define ixGC_CAC_ACC_GL2C4 0x004c +#define ixGC_CAC_ACC_PH0 0x004d +#define ixGC_CAC_ACC_PH1 0x004e +#define ixGC_CAC_ACC_PH2 0x004f +#define ixGC_CAC_ACC_PH3 0x0050 +#define ixGC_CAC_ACC_PH4 0x0051 +#define ixGC_CAC_ACC_PH5 0x0052 +#define ixGC_CAC_ACC_PH6 0x0053 +#define ixGC_CAC_ACC_PH7 0x0054 +#define ixGC_CAC_ACC_SDMA0 0x0055 +#define ixGC_CAC_ACC_SDMA1 0x0056 +#define ixGC_CAC_ACC_SDMA2 0x0057 +#define ixGC_CAC_ACC_SDMA3 0x0058 +#define ixGC_CAC_ACC_SDMA4 0x0059 +#define ixGC_CAC_ACC_SDMA5 0x005a +#define ixGC_CAC_ACC_SDMA6 0x005b +#define ixGC_CAC_ACC_SDMA7 0x005c +#define ixGC_CAC_ACC_SDMA8 0x005d +#define ixGC_CAC_ACC_SDMA9 0x005e +#define ixGC_CAC_ACC_SDMA10 0x005f +#define ixGC_CAC_ACC_SDMA11 0x0060 +#define ixGC_CAC_ACC_CHC0 0x0061 +#define ixGC_CAC_ACC_CHC1 0x0062 +#define ixGC_CAC_ACC_CHC2 0x0063 +#define ixGC_CAC_ACC_GUS0 0x0064 +#define ixGC_CAC_ACC_GUS1 0x0065 +#define ixGC_CAC_ACC_GUS2 0x0066 +#define ixGC_CAC_ACC_RLC0 0x0067 +#define ixRELEASE_TO_STALL_LUT_1_8 0x0100 +#define ixRELEASE_TO_STALL_LUT_9_16 0x0101 +#define ixRELEASE_TO_STALL_LUT_17_20 0x0102 +#define ixSTALL_TO_RELEASE_LUT_1_4 0x0103 +#define ixSTALL_TO_RELEASE_LUT_5_7 0x0104 +#define ixSTALL_TO_PWRBRK_LUT_1_4 0x0105 +#define ixSTALL_TO_PWRBRK_LUT_5_7 0x0106 +#define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 0x0107 +#define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 0x0108 +#define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 0x0109 +#define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 0x010a +#define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 0x010b +#define ixFIXED_PATTERN_PERF_COUNTER_1 0x010c +#define ixFIXED_PATTERN_PERF_COUNTER_2 0x010d +#define ixFIXED_PATTERN_PERF_COUNTER_3 0x010e +#define ixFIXED_PATTERN_PERF_COUNTER_4 0x010f +#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0110 +#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0111 +#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0112 +#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0113 +#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0114 +#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0115 +#define ixHW_LUT_UPDATE_STATUS 0x0116 + + +// addressBlock: secacind +// base address: 0x0 +#define ixSE_CAC_ID 0x0000 +#define ixSE_CAC_CNTL 0x0001 + + +// addressBlock: grtavfsind +// base address: 0x0 +#define ixRTAVFS_REG0 0x0000 +#define ixRTAVFS_REG1 0x0001 +#define ixRTAVFS_REG2 0x0002 +#define ixRTAVFS_REG3 0x0003 +#define ixRTAVFS_REG4 0x0004 +#define ixRTAVFS_REG5 0x0005 +#define ixRTAVFS_REG6 0x0006 +#define ixRTAVFS_REG7 0x0007 +#define ixRTAVFS_REG8 0x0008 +#define ixRTAVFS_REG9 0x0009 +#define ixRTAVFS_REG10 0x000a +#define ixRTAVFS_REG11 0x000b +#define ixRTAVFS_REG12 0x000c +#define ixRTAVFS_REG13 0x000d +#define ixRTAVFS_REG14 0x000e +#define ixRTAVFS_REG15 0x000f +#define ixRTAVFS_REG16 0x0010 +#define ixRTAVFS_REG17 0x0011 +#define ixRTAVFS_REG18 0x0012 +#define ixRTAVFS_REG19 0x0013 +#define ixRTAVFS_REG20 0x0014 +#define ixRTAVFS_REG21 0x0015 +#define ixRTAVFS_REG22 0x0016 +#define ixRTAVFS_REG23 0x0017 +#define ixRTAVFS_REG24 0x0018 +#define ixRTAVFS_REG25 0x0019 +#define ixRTAVFS_REG26 0x001a +#define ixRTAVFS_REG27 0x001b +#define ixRTAVFS_REG28 0x001c +#define ixRTAVFS_REG29 0x001d +#define ixRTAVFS_REG30 0x001e +#define ixRTAVFS_REG31 0x001f +#define ixRTAVFS_REG32 0x0020 +#define ixRTAVFS_REG33 0x0021 +#define ixRTAVFS_REG34 0x0022 +#define ixRTAVFS_REG35 0x0023 +#define ixRTAVFS_REG36 0x0024 +#define ixRTAVFS_REG37 0x0025 +#define ixRTAVFS_REG38 0x0026 +#define ixRTAVFS_REG39 0x0027 +#define ixRTAVFS_REG40 0x0028 +#define ixRTAVFS_REG41 0x0029 +#define ixRTAVFS_REG42 0x002a +#define ixRTAVFS_REG43 0x002b +#define ixRTAVFS_REG44 0x002c +#define ixRTAVFS_REG45 0x002d +#define ixRTAVFS_REG46 0x002e +#define ixRTAVFS_REG47 0x002f +#define ixRTAVFS_REG48 0x0030 +#define ixRTAVFS_REG49 0x0031 +#define ixRTAVFS_REG50 0x0032 +#define ixRTAVFS_REG51 0x0033 +#define ixRTAVFS_REG52 0x0034 +#define ixRTAVFS_REG53 0x0035 +#define ixRTAVFS_REG54 0x0036 +#define ixRTAVFS_REG55 0x0037 +#define ixRTAVFS_REG56 0x0038 +#define ixRTAVFS_REG57 0x0039 +#define ixRTAVFS_REG58 0x003a +#define ixRTAVFS_REG59 0x003b +#define ixRTAVFS_REG60 0x003c +#define ixRTAVFS_REG61 0x003d +#define ixRTAVFS_REG62 0x003e +#define ixRTAVFS_REG63 0x003f +#define ixRTAVFS_REG64 0x0040 +#define ixRTAVFS_REG65 0x0041 +#define ixRTAVFS_REG66 0x0042 +#define ixRTAVFS_REG67 0x0043 +#define ixRTAVFS_REG68 0x0044 +#define ixRTAVFS_REG69 0x0045 +#define ixRTAVFS_REG70 0x0046 +#define ixRTAVFS_REG71 0x0047 +#define ixRTAVFS_REG72 0x0048 +#define ixRTAVFS_REG73 0x0049 +#define ixRTAVFS_REG74 0x004a +#define ixRTAVFS_REG75 0x004b +#define ixRTAVFS_REG76 0x004c +#define ixRTAVFS_REG77 0x004d +#define ixRTAVFS_REG78 0x004e +#define ixRTAVFS_REG79 0x004f +#define ixRTAVFS_REG80 0x0050 +#define ixRTAVFS_REG81 0x0051 +#define ixRTAVFS_REG82 0x0052 +#define ixRTAVFS_REG83 0x0053 +#define ixRTAVFS_REG84 0x0054 +#define ixRTAVFS_REG85 0x0055 +#define ixRTAVFS_REG86 0x0056 +#define ixRTAVFS_REG87 0x0057 +#define ixRTAVFS_REG88 0x0058 +#define ixRTAVFS_REG89 0x0059 +#define ixRTAVFS_REG90 0x005a +#define ixRTAVFS_REG91 0x005b +#define ixRTAVFS_REG92 0x005c +#define ixRTAVFS_REG93 0x005d +#define ixRTAVFS_REG94 0x005e +#define ixRTAVFS_REG95 0x005f +#define ixRTAVFS_REG96 0x0060 +#define ixRTAVFS_REG97 0x0061 +#define ixRTAVFS_REG98 0x0062 +#define ixRTAVFS_REG99 0x0063 +#define ixRTAVFS_REG100 0x0064 +#define ixRTAVFS_REG101 0x0065 +#define ixRTAVFS_REG102 0x0066 +#define ixRTAVFS_REG103 0x0067 +#define ixRTAVFS_REG104 0x0068 +#define ixRTAVFS_REG105 0x0069 +#define ixRTAVFS_REG106 0x006a +#define ixRTAVFS_REG107 0x006b +#define ixRTAVFS_REG108 0x006c +#define ixRTAVFS_REG109 0x006d +#define ixRTAVFS_REG110 0x006e +#define ixRTAVFS_REG111 0x006f +#define ixRTAVFS_REG112 0x0070 +#define ixRTAVFS_REG113 0x0071 +#define ixRTAVFS_REG114 0x0072 +#define ixRTAVFS_REG115 0x0073 +#define ixRTAVFS_REG116 0x0074 +#define ixRTAVFS_REG117 0x0075 +#define ixRTAVFS_REG118 0x0076 +#define ixRTAVFS_REG119 0x0077 +#define ixRTAVFS_REG120 0x0078 +#define ixRTAVFS_REG121 0x0079 +#define ixRTAVFS_REG122 0x007a +#define ixRTAVFS_REG123 0x007b +#define ixRTAVFS_REG124 0x007c +#define ixRTAVFS_REG125 0x007d +#define ixRTAVFS_REG126 0x007e +#define ixRTAVFS_REG127 0x007f +#define ixRTAVFS_REG128 0x0080 +#define ixRTAVFS_REG129 0x0081 +#define ixRTAVFS_REG130 0x0082 +#define ixRTAVFS_REG131 0x0083 +#define ixRTAVFS_REG132 0x0084 +#define ixRTAVFS_REG133 0x0085 +#define ixRTAVFS_REG134 0x0086 +#define ixRTAVFS_REG135 0x0087 +#define ixRTAVFS_REG136 0x0088 +#define ixRTAVFS_REG137 0x0089 +#define ixRTAVFS_REG138 0x008a +#define ixRTAVFS_REG139 0x008b +#define ixRTAVFS_REG140 0x008c +#define ixRTAVFS_REG141 0x008d +#define ixRTAVFS_REG142 0x008e +#define ixRTAVFS_REG143 0x008f +#define ixRTAVFS_REG144 0x0090 +#define ixRTAVFS_REG145 0x0091 +#define ixRTAVFS_REG146 0x0092 +#define ixRTAVFS_REG147 0x0093 +#define ixRTAVFS_REG148 0x0094 +#define ixRTAVFS_REG149 0x0095 +#define ixRTAVFS_REG150 0x0096 +#define ixRTAVFS_REG151 0x0097 +#define ixRTAVFS_REG152 0x0098 +#define ixRTAVFS_REG153 0x0099 +#define ixRTAVFS_REG154 0x009a +#define ixRTAVFS_REG155 0x009b +#define ixRTAVFS_REG156 0x009c +#define ixRTAVFS_REG157 0x009d +#define ixRTAVFS_REG158 0x009e +#define ixRTAVFS_REG159 0x009f +#define ixRTAVFS_REG160 0x00a0 +#define ixRTAVFS_REG161 0x00a1 +#define ixRTAVFS_REG162 0x00a2 +#define ixRTAVFS_REG163 0x00a3 +#define ixRTAVFS_REG164 0x00a4 +#define ixRTAVFS_REG165 0x00a5 +#define ixRTAVFS_REG166 0x00a6 +#define ixRTAVFS_REG167 0x00a7 +#define ixRTAVFS_REG168 0x00a8 +#define ixRTAVFS_REG169 0x00a9 +#define ixRTAVFS_REG170 0x00aa +#define ixRTAVFS_REG171 0x00ab +#define ixRTAVFS_REG172 0x00ac +#define ixRTAVFS_REG173 0x00ad +#define ixRTAVFS_REG174 0x00ae +#define ixRTAVFS_REG175 0x00af +#define ixRTAVFS_REG176 0x00b0 +#define ixRTAVFS_REG177 0x00b1 +#define ixRTAVFS_REG178 0x00b2 +#define ixRTAVFS_REG179 0x00b3 +#define ixRTAVFS_REG180 0x00b4 +#define ixRTAVFS_REG181 0x00b5 +#define ixRTAVFS_REG182 0x00b6 +#define ixRTAVFS_REG183 0x00b7 +#define ixRTAVFS_REG184 0x00b8 +#define ixRTAVFS_REG185 0x00b9 +#define ixRTAVFS_REG186 0x00ba +#define ixRTAVFS_REG187 0x00bb +#define ixRTAVFS_REG188 0x00bc +#define ixRTAVFS_REG189 0x00bd +#define ixRTAVFS_REG190 0x00be +#define ixRTAVFS_REG191 0x00bf +#define ixRTAVFS_REG192 0x00c0 +#define ixRTAVFS_REG193 0x00c1 +#define ixRTAVFS_REG194 0x00c2 + + +// addressBlock: sqind +// base address: 0x0 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_WAVE_ACTIVE 0x000a +#define ixSQ_WAVE_VALID_AND_IDLE 0x000b +#define ixSQ_WAVE_MODE 0x0101 +#define ixSQ_WAVE_STATUS 0x0102 +#define ixSQ_WAVE_TRAPSTS 0x0103 +#define ixSQ_WAVE_GPR_ALLOC 0x0105 +#define ixSQ_WAVE_LDS_ALLOC 0x0106 +#define ixSQ_WAVE_IB_STS 0x0107 +#define ixSQ_WAVE_PC_LO 0x0108 +#define ixSQ_WAVE_PC_HI 0x0109 +#define ixSQ_WAVE_IB_DBG1 0x010d +#define ixSQ_WAVE_FLUSH_IB 0x010e +#define ixSQ_WAVE_FLAT_SCRATCH_LO 0x0114 +#define ixSQ_WAVE_FLAT_SCRATCH_HI 0x0115 +#define ixSQ_WAVE_HW_ID1 0x0117 +#define ixSQ_WAVE_HW_ID2 0x0118 +#define ixSQ_WAVE_POPS_PACKER 0x0119 +#define ixSQ_WAVE_SCHED_MODE 0x011a +#define ixSQ_WAVE_IB_STS2 0x011c +#define ixSQ_WAVE_SHADER_CYCLES 0x011d +#define ixSQ_WAVE_TTMP0 0x026c +#define ixSQ_WAVE_TTMP1 0x026d +#define ixSQ_WAVE_TTMP3 0x026f +#define ixSQ_WAVE_TTMP4 0x0270 +#define ixSQ_WAVE_TTMP5 0x0271 +#define ixSQ_WAVE_TTMP6 0x0272 +#define ixSQ_WAVE_TTMP7 0x0273 +#define ixSQ_WAVE_TTMP8 0x0274 +#define ixSQ_WAVE_TTMP9 0x0275 +#define ixSQ_WAVE_TTMP10 0x0276 +#define ixSQ_WAVE_TTMP11 0x0277 +#define ixSQ_WAVE_TTMP12 0x0278 +#define ixSQ_WAVE_TTMP13 0x0279 +#define ixSQ_WAVE_TTMP14 0x027a +#define ixSQ_WAVE_TTMP15 0x027b +#define ixSQ_WAVE_M0 0x027d +#define ixSQ_WAVE_EXEC_LO 0x027e +#define ixSQ_WAVE_EXEC_HI 0x027f + + +#endif diff --git a/extra/amdpci/headers/gc_11_0_0_sh_mask.h b/extra/amdpci/headers/gc_11_0_0_sh_mask.h new file mode 100644 index 0000000000..3088a4a13c --- /dev/null +++ b/extra/amdpci/headers/gc_11_0_0_sh_mask.h @@ -0,0 +1,41664 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_11_0_0_SH_MASK_HEADER +#define _gc_11_0_0_SH_MASK_HEADER + + +// addressBlock: gc_sdma0_sdma0dec +//SDMA0_DEC_START +#define SDMA0_DEC_START__START__SHIFT 0x0 +#define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL +//SDMA0_F32_MISC_CNTL +#define SDMA0_F32_MISC_CNTL__F32_WAKEUP__SHIFT 0x0 +#define SDMA0_F32_MISC_CNTL__F32_WAKEUP_MASK 0x00000001L +//SDMA0_GLOBAL_TIMESTAMP_LO +#define SDMA0_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define SDMA0_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_GLOBAL_TIMESTAMP_HI +#define SDMA0_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define SDMA0_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_POWER_CNTL +#define SDMA0_POWER_CNTL__LS_ENABLE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__LS_ENABLE_MASK 0x00000100L +//SDMA0_CNTL +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 +#define SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 +#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa +#define SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb +#define SDMA0_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc +#define SDMA0_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd +#define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L +#define SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L +#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define SDMA0_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L +#define SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L +#define SDMA0_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L +#define SDMA0_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L +#define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define SDMA0_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//SDMA0_CHICKEN_BITS +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 +#define SDMA0_CHICKEN_BITS__RD_BURST__SHIFT 0x6 +#define SDMA0_CHICKEN_BITS__WR_BURST__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe +#define SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 +#define SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS__RESERVED__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L +#define SDMA0_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L +#define SDMA0_CHICKEN_BITS__WR_BURST_MASK 0x00000300L +#define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L +#define SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L +#define SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L +#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L +#define SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L +#define SDMA0_CHICKEN_BITS__RESERVED_MASK 0xFC000000L +//SDMA0_GB_ADDR_CONFIG +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define SDMA0_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define SDMA0_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +//SDMA0_GB_ADDR_CONFIG_READ +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//SDMA0_RB_RPTR_FETCH +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_RB_RPTR_FETCH_HI +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA0_IB_OFFSET_FETCH +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_PROGRAM +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_STATUS_REG +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__CGCG_FENCE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA0_STATUS_REG__CGCG_FENCE_MASK 0x00000800L +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_STATUS1_REG +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc +#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0xf +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 +#define SDMA0_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 +#define SDMA0_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 +#define SDMA0_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L +#define SDMA0_STATUS1_REG__EX_START_MASK 0x00002000L +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L +#define SDMA0_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L +#define SDMA0_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L +#define SDMA0_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L +//SDMA0_CNTL1 +#define SDMA0_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 +#define SDMA0_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL +//SDMA0_HBM_PAGE_CONFIG +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_UCODE_CHECKSUM +#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_FREEZE +#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA0_PROCESS_QUANTUM0 +#define SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//SDMA0_PROCESS_QUANTUM1 +#define SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//SDMA0_WATCHDOG_CNTL +#define SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//SDMA0_QUEUE_STATUS0 +#define SDMA0_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define SDMA0_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define SDMA0_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define SDMA0_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define SDMA0_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define SDMA0_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define SDMA0_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define SDMA0_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define SDMA0_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define SDMA0_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define SDMA0_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define SDMA0_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define SDMA0_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define SDMA0_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define SDMA0_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define SDMA0_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//SDMA0_EDC_CONFIG +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA0_BA_THRESHOLD +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA0_ID +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_VERSION +#define SDMA0_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_VERSION__REV__SHIFT 0x10 +#define SDMA0_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_VERSION__REV_MASK 0x003F0000L +//SDMA0_EDC_COUNTER +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L +//SDMA0_EDC_COUNTER_CLEAR +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA0_STATUS2_REG +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA0_STATUS2_REG__TH0F32_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_ATOMIC_CNTL +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_ATOMIC_PREOP_LO +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_ATOMIC_PREOP_HI +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_CNTL +#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 +#define SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 +#define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 +#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe +#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf +#define SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0x10 +#define SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0x11 +#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x12 +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL +#define SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L +#define SDMA0_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L +#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L +#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L +#define SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00010000L +#define SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00020000L +#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x003C0000L +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x3F000000L +//SDMA0_UTCL1_WATERMK +#define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 +#define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 +#define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 +#define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa +#define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc +#define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 +#define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 +#define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 +#define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL +#define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L +#define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L +#define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L +#define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L +#define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L +#define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L +#define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L +//SDMA0_UTCL1_TIMEOUT +#define SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0x0000FFFFL +//SDMA0_UTCL1_PAGE +#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa +#define SDMA0_UTCL1_PAGE__USE_IO__SHIFT 0xb +#define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc +#define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe +#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 +#define SDMA0_UTCL1_PAGE__USE_BC__SHIFT 0x16 +#define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 +#define SDMA0_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 +#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L +#define SDMA0_UTCL1_PAGE__USE_IO_MASK 0x00000800L +#define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L +#define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L +#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L +#define SDMA0_UTCL1_PAGE__USE_BC_MASK 0x00400000L +#define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L +#define SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L +//SDMA0_UTCL1_RD_STATUS +#define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_RD_STATUS__RESERVED0__SHIFT 0x5 +#define SDMA0_UTCL1_RD_STATUS__RESERVED1__SHIFT 0x6 +#define SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0x8 +#define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT 0xb +#define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_RD_STATUS__RESERVED2__SHIFT 0xd +#define SDMA0_UTCL1_RD_STATUS__RESERVED3__SHIFT 0xe +#define SDMA0_UTCL1_RD_STATUS__META_Q_FULL__SHIFT 0xf +#define SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT 0x10 +#define SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 +#define SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT 0x13 +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT 0x15 +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT 0x16 +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT 0x17 +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT 0x18 +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT 0x19 +#define SDMA0_UTCL1_RD_STATUS__RESERVED4__SHIFT 0x1a +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT 0x1b +#define SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT 0x1c +#define SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_RD_STATUS__INV_BUSY__SHIFT 0x1e +#define SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT 0x1f +#define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_RD_STATUS__RESERVED0_MASK 0x00000020L +#define SDMA0_UTCL1_RD_STATUS__RESERVED1_MASK 0x00000040L +#define SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000100L +#define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_RD_STATUS__RESERVED2_MASK 0x00002000L +#define SDMA0_UTCL1_RD_STATUS__RESERVED3_MASK 0x00004000L +#define SDMA0_UTCL1_RD_STATUS__META_Q_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK 0x00010000L +#define SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L +#define SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK 0x00180000L +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK 0x00200000L +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK 0x00400000L +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK 0x00800000L +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK 0x01000000L +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK 0x02000000L +#define SDMA0_UTCL1_RD_STATUS__RESERVED4_MASK 0x04000000L +#define SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK 0x08000000L +#define SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK 0x10000000L +#define SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_RD_STATUS__INV_BUSY_MASK 0x40000000L +#define SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK 0x80000000L +//SDMA0_UTCL1_WR_STATUS +#define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_WR_STATUS__RESERVED0__SHIFT 0x7 +#define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0x8 +#define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT 0xb +#define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT 0xd +#define SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT 0xe +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0xf +#define SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT 0x10 +#define SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 +#define SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT 0x13 +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT 0x15 +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT 0x16 +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT 0x17 +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT 0x18 +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT 0x19 +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT 0x1a +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT 0x1b +#define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT 0x1c +#define SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT 0x1e +#define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT 0x1f +#define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_WR_STATUS__RESERVED0_MASK 0x00000080L +#define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000100L +#define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00008000L +#define SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK 0x00010000L +#define SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L +#define SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK 0x00180000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK 0x00200000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK 0x00400000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK 0x00800000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK 0x01000000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK 0x02000000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK 0x04000000L +#define SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK 0x08000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK 0x10000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK 0x40000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK 0x80000000L +//SDMA0_UTCL1_INV0 +#define SDMA0_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 +#define SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 +#define SDMA0_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 +#define SDMA0_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb +#define SDMA0_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd +#define SDMA0_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe +#define SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 +#define SDMA0_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 +#define SDMA0_UTCL1_INV0__INV_TYPE__SHIFT 0x1a +#define SDMA0_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L +#define SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL +#define SDMA0_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L +#define SDMA0_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L +#define SDMA0_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L +#define SDMA0_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L +#define SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L +#define SDMA0_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L +#define SDMA0_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L +//SDMA0_UTCL1_INV1 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_INV2 +#define SDMA0_UTCL1_INV2__CPF_VMID__SHIFT 0x0 +#define SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 +#define SDMA0_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 +#define SDMA0_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL +#define SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L +#define SDMA0_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L +//SDMA0_UTCL1_RD_XNACK0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK1 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa +#define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe +#define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf +#define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L +//SDMA0_UTCL1_WR_XNACK0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_WR_XNACK1 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa +#define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe +#define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf +#define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L +//SDMA0_RELAX_ORDERING_LUT +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA0_CHICKEN_BITS_2 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT 0x6 +#define SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 +#define SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc +#define SDMA0_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf +#define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define SDMA0_CHICKEN_BITS_2__RESERVED_22_20__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +#define SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK 0x00000040L +#define SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L +#define SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L +#define SDMA0_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L +#define SDMA0_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L +#define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define SDMA0_CHICKEN_BITS_2__RESERVED_22_20_MASK 0x00700000L +#define SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L +#define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L +#define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK 0x40000000L +#define SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L +//SDMA0_STATUS3_REG +#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 +#define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 +#define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT 0x17 +#define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 +#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a +#define SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e +#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L +#define SDMA0_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L +#define SDMA0_STATUS3_REG__GCR_IDLE_MASK 0x00800000L +#define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L +#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L +#define SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L +//SDMA0_PHYSICAL_ADDR_LO +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA0_PHYSICAL_ADDR_HI +#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA0_GLOBAL_QUANTUM +#define SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//SDMA0_ERROR_LOG +#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_PUB_DUMMY_REG0 +#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG1 +#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG2 +#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG3 +#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_COUNTER +#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_CRD_CNTL +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 +#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L +#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L +//SDMA0_RLC_CGCG_CTRL +#define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 +#define SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 +#define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L +#define SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L +//SDMA0_AQL_STATUS +#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 +#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 +#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L +#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L +//SDMA0_EA_DBIT_ADDR_DATA +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_EA_DBIT_ADDR_INDEX +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA0_TLBI_GCR_CNTL +#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 +#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 +#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 +#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 +#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 +#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL +#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L +#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L +#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L +#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L +//SDMA0_TILING_CONFIG +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//SDMA0_INT_STATUS +#define SDMA0_INT_STATUS__DATA__SHIFT 0x0 +#define SDMA0_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//SDMA0_HOLE_ADDR_LO +#define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT 0x0 +#define SDMA0_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//SDMA0_HOLE_ADDR_HI +#define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT 0x0 +#define SDMA0_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//SDMA0_CLOCK_GATING_STATUS +#define SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 +#define SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT 0x2 +#define SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 +#define SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 +#define SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x5 +#define SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x6 +#define SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L +#define SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK 0x00000004L +#define SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L +#define SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L +#define SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000020L +#define SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000040L +//SDMA0_STATUS4_REG +#define SDMA0_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 +#define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA0_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 +#define SDMA0_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 +#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 +#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 +#define SDMA0_STATUS4_REG__REG_POLLING__SHIFT 0xa +#define SDMA0_STATUS4_REG__MEM_POLLING__SHIFT 0xb +#define SDMA0_STATUS4_REG__RESERVED_13_12__SHIFT 0xc +#define SDMA0_STATUS4_REG__RESERVED_15_14__SHIFT 0xe +#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 +#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b +#define SDMA0_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L +#define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA0_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L +#define SDMA0_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L +#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L +#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L +#define SDMA0_STATUS4_REG__REG_POLLING_MASK 0x00000400L +#define SDMA0_STATUS4_REG__MEM_POLLING_MASK 0x00000800L +#define SDMA0_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L +#define SDMA0_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L +#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L +#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L +//SDMA0_SCRATCH_RAM_DATA +#define SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA0_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA0_SCRATCH_RAM_ADDR +#define SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA0_TIMESTAMP_CNTL +#define SDMA0_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define SDMA0_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//SDMA0_STATUS5_REG +#define SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 +#define SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 +#define SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 +#define SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 +#define SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 +#define SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 +#define SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1a +#define SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1b +#define SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L +#define SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L +#define SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L +#define SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L +#define SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L +#define SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L +#define SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x04000000L +#define SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x08000000L +//SDMA0_QUEUE_RESET_REQ +#define SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define SDMA0_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 +#define SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define SDMA0_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L +//SDMA0_STATUS6_REG +#define SDMA0_STATUS6_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 +#define SDMA0_STATUS6_REG__ID_MASK 0x00000003L +#define SDMA0_STATUS6_REG__TH1F32_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA0_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L +//SDMA0_UCODE1_CHECKSUM +#define SDMA0_UCODE1_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_CE_CTRL +#define SDMA0_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA0_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT 0x8 +#define SDMA0_CE_CTRL__RESERVED__SHIFT 0x9 +#define SDMA0_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA0_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK 0x00000100L +#define SDMA0_CE_CTRL__RESERVED_MASK 0xFFFFFE00L +//SDMA0_FED_STATUS +#define SDMA0_FED_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA0_FED_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA0_FED_STATUS__F32_DATA_ECC__SHIFT 0x2 +#define SDMA0_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT 0x3 +#define SDMA0_FED_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA0_FED_STATUS__COPY_METADATA_ECC__SHIFT 0x5 +#define SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT 0x6 +#define SDMA0_FED_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA0_FED_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA0_FED_STATUS__F32_DATA_ECC_MASK 0x00000004L +#define SDMA0_FED_STATUS__WPTR_ATOMIC_ECC_MASK 0x00000008L +#define SDMA0_FED_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA0_FED_STATUS__COPY_METADATA_ECC_MASK 0x00000020L +#define SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC_MASK 0x00000040L +//SDMA0_QUEUE0_RB_CNTL +#define SDMA0_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE0_RB_BASE +#define SDMA0_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_BASE_HI +#define SDMA0_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE0_RB_RPTR +#define SDMA0_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_RPTR_HI +#define SDMA0_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_WPTR +#define SDMA0_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_WPTR_HI +#define SDMA0_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE0_IB_CNTL +#define SDMA0_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE0_IB_RPTR +#define SDMA0_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE0_IB_OFFSET +#define SDMA0_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE0_IB_BASE_LO +#define SDMA0_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE0_IB_BASE_HI +#define SDMA0_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_IB_SIZE +#define SDMA0_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE0_SKIP_CNTL +#define SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE0_CONTEXT_STATUS +#define SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE0_DOORBELL +#define SDMA0_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE0_DOORBELL_LOG +#define SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE0_DOORBELL_OFFSET +#define SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE0_CSA_ADDR_LO +#define SDMA0_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE0_CSA_ADDR_HI +#define SDMA0_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_SCHEDULE_CNTL +#define SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE0_IB_SUB_REMAIN +#define SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE0_PREEMPT +#define SDMA0_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE0_DUMMY_REG +#define SDMA0_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE0_RB_AQL_CNTL +#define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE0_MINOR_PTR_UPDATE +#define SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE0_RB_PREEMPT +#define SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE0_MIDCMD_DATA0 +#define SDMA0_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA1 +#define SDMA0_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA2 +#define SDMA0_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA3 +#define SDMA0_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA4 +#define SDMA0_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA5 +#define SDMA0_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA6 +#define SDMA0_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA7 +#define SDMA0_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA8 +#define SDMA0_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA9 +#define SDMA0_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_DATA10 +#define SDMA0_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE0_MIDCMD_CNTL +#define SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_QUEUE1_RB_CNTL +#define SDMA0_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE1_RB_BASE +#define SDMA0_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_BASE_HI +#define SDMA0_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE1_RB_RPTR +#define SDMA0_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_RPTR_HI +#define SDMA0_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_WPTR +#define SDMA0_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_WPTR_HI +#define SDMA0_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE1_IB_CNTL +#define SDMA0_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE1_IB_RPTR +#define SDMA0_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE1_IB_OFFSET +#define SDMA0_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE1_IB_BASE_LO +#define SDMA0_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE1_IB_BASE_HI +#define SDMA0_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_IB_SIZE +#define SDMA0_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE1_SKIP_CNTL +#define SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE1_CONTEXT_STATUS +#define SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE1_DOORBELL +#define SDMA0_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE1_DOORBELL_LOG +#define SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE1_DOORBELL_OFFSET +#define SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE1_CSA_ADDR_LO +#define SDMA0_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE1_CSA_ADDR_HI +#define SDMA0_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_SCHEDULE_CNTL +#define SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE1_IB_SUB_REMAIN +#define SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE1_PREEMPT +#define SDMA0_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE1_DUMMY_REG +#define SDMA0_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE1_RB_AQL_CNTL +#define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE1_MINOR_PTR_UPDATE +#define SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE1_RB_PREEMPT +#define SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE1_MIDCMD_DATA0 +#define SDMA0_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA1 +#define SDMA0_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA2 +#define SDMA0_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA3 +#define SDMA0_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA4 +#define SDMA0_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA5 +#define SDMA0_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA6 +#define SDMA0_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA7 +#define SDMA0_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA8 +#define SDMA0_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA9 +#define SDMA0_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_DATA10 +#define SDMA0_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE1_MIDCMD_CNTL +#define SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_QUEUE2_RB_CNTL +#define SDMA0_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE2_RB_BASE +#define SDMA0_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_BASE_HI +#define SDMA0_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE2_RB_RPTR +#define SDMA0_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_RPTR_HI +#define SDMA0_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_WPTR +#define SDMA0_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_WPTR_HI +#define SDMA0_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE2_IB_CNTL +#define SDMA0_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE2_IB_RPTR +#define SDMA0_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE2_IB_OFFSET +#define SDMA0_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE2_IB_BASE_LO +#define SDMA0_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE2_IB_BASE_HI +#define SDMA0_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_IB_SIZE +#define SDMA0_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE2_SKIP_CNTL +#define SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE2_CONTEXT_STATUS +#define SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE2_DOORBELL +#define SDMA0_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE2_DOORBELL_LOG +#define SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE2_DOORBELL_OFFSET +#define SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE2_CSA_ADDR_LO +#define SDMA0_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE2_CSA_ADDR_HI +#define SDMA0_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_SCHEDULE_CNTL +#define SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE2_IB_SUB_REMAIN +#define SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE2_PREEMPT +#define SDMA0_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE2_DUMMY_REG +#define SDMA0_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE2_RB_AQL_CNTL +#define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE2_MINOR_PTR_UPDATE +#define SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE2_RB_PREEMPT +#define SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE2_MIDCMD_DATA0 +#define SDMA0_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA1 +#define SDMA0_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA2 +#define SDMA0_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA3 +#define SDMA0_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA4 +#define SDMA0_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA5 +#define SDMA0_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA6 +#define SDMA0_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA7 +#define SDMA0_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA8 +#define SDMA0_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA9 +#define SDMA0_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_DATA10 +#define SDMA0_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE2_MIDCMD_CNTL +#define SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_QUEUE3_RB_CNTL +#define SDMA0_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE3_RB_BASE +#define SDMA0_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_BASE_HI +#define SDMA0_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE3_RB_RPTR +#define SDMA0_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_RPTR_HI +#define SDMA0_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_WPTR +#define SDMA0_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_WPTR_HI +#define SDMA0_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE3_IB_CNTL +#define SDMA0_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE3_IB_RPTR +#define SDMA0_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE3_IB_OFFSET +#define SDMA0_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE3_IB_BASE_LO +#define SDMA0_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE3_IB_BASE_HI +#define SDMA0_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_IB_SIZE +#define SDMA0_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE3_SKIP_CNTL +#define SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE3_CONTEXT_STATUS +#define SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE3_DOORBELL +#define SDMA0_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE3_DOORBELL_LOG +#define SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE3_DOORBELL_OFFSET +#define SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE3_CSA_ADDR_LO +#define SDMA0_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE3_CSA_ADDR_HI +#define SDMA0_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_SCHEDULE_CNTL +#define SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE3_IB_SUB_REMAIN +#define SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE3_PREEMPT +#define SDMA0_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE3_DUMMY_REG +#define SDMA0_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE3_RB_AQL_CNTL +#define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE3_MINOR_PTR_UPDATE +#define SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE3_RB_PREEMPT +#define SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE3_MIDCMD_DATA0 +#define SDMA0_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA1 +#define SDMA0_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA2 +#define SDMA0_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA3 +#define SDMA0_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA4 +#define SDMA0_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA5 +#define SDMA0_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA6 +#define SDMA0_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA7 +#define SDMA0_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA8 +#define SDMA0_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA9 +#define SDMA0_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_DATA10 +#define SDMA0_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE3_MIDCMD_CNTL +#define SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_QUEUE4_RB_CNTL +#define SDMA0_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE4_RB_BASE +#define SDMA0_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_BASE_HI +#define SDMA0_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE4_RB_RPTR +#define SDMA0_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_RPTR_HI +#define SDMA0_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_WPTR +#define SDMA0_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_WPTR_HI +#define SDMA0_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE4_IB_CNTL +#define SDMA0_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE4_IB_RPTR +#define SDMA0_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE4_IB_OFFSET +#define SDMA0_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE4_IB_BASE_LO +#define SDMA0_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE4_IB_BASE_HI +#define SDMA0_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_IB_SIZE +#define SDMA0_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE4_SKIP_CNTL +#define SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE4_CONTEXT_STATUS +#define SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE4_DOORBELL +#define SDMA0_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE4_DOORBELL_LOG +#define SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE4_DOORBELL_OFFSET +#define SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE4_CSA_ADDR_LO +#define SDMA0_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE4_CSA_ADDR_HI +#define SDMA0_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_SCHEDULE_CNTL +#define SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE4_IB_SUB_REMAIN +#define SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE4_PREEMPT +#define SDMA0_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE4_DUMMY_REG +#define SDMA0_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE4_RB_AQL_CNTL +#define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE4_MINOR_PTR_UPDATE +#define SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE4_RB_PREEMPT +#define SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE4_MIDCMD_DATA0 +#define SDMA0_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA1 +#define SDMA0_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA2 +#define SDMA0_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA3 +#define SDMA0_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA4 +#define SDMA0_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA5 +#define SDMA0_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA6 +#define SDMA0_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA7 +#define SDMA0_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA8 +#define SDMA0_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA9 +#define SDMA0_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_DATA10 +#define SDMA0_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE4_MIDCMD_CNTL +#define SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_QUEUE5_RB_CNTL +#define SDMA0_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE5_RB_BASE +#define SDMA0_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_BASE_HI +#define SDMA0_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE5_RB_RPTR +#define SDMA0_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_RPTR_HI +#define SDMA0_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_WPTR +#define SDMA0_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_WPTR_HI +#define SDMA0_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE5_IB_CNTL +#define SDMA0_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE5_IB_RPTR +#define SDMA0_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE5_IB_OFFSET +#define SDMA0_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE5_IB_BASE_LO +#define SDMA0_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE5_IB_BASE_HI +#define SDMA0_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_IB_SIZE +#define SDMA0_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE5_SKIP_CNTL +#define SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE5_CONTEXT_STATUS +#define SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE5_DOORBELL +#define SDMA0_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE5_DOORBELL_LOG +#define SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE5_DOORBELL_OFFSET +#define SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE5_CSA_ADDR_LO +#define SDMA0_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE5_CSA_ADDR_HI +#define SDMA0_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_SCHEDULE_CNTL +#define SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE5_IB_SUB_REMAIN +#define SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE5_PREEMPT +#define SDMA0_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE5_DUMMY_REG +#define SDMA0_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE5_RB_AQL_CNTL +#define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE5_MINOR_PTR_UPDATE +#define SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE5_RB_PREEMPT +#define SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE5_MIDCMD_DATA0 +#define SDMA0_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA1 +#define SDMA0_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA2 +#define SDMA0_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA3 +#define SDMA0_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA4 +#define SDMA0_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA5 +#define SDMA0_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA6 +#define SDMA0_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA7 +#define SDMA0_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA8 +#define SDMA0_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA9 +#define SDMA0_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_DATA10 +#define SDMA0_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE5_MIDCMD_CNTL +#define SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_QUEUE6_RB_CNTL +#define SDMA0_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE6_RB_BASE +#define SDMA0_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_BASE_HI +#define SDMA0_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE6_RB_RPTR +#define SDMA0_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_RPTR_HI +#define SDMA0_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_WPTR +#define SDMA0_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_WPTR_HI +#define SDMA0_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE6_IB_CNTL +#define SDMA0_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE6_IB_RPTR +#define SDMA0_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE6_IB_OFFSET +#define SDMA0_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE6_IB_BASE_LO +#define SDMA0_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE6_IB_BASE_HI +#define SDMA0_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_IB_SIZE +#define SDMA0_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE6_SKIP_CNTL +#define SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE6_CONTEXT_STATUS +#define SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE6_DOORBELL +#define SDMA0_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE6_DOORBELL_LOG +#define SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE6_DOORBELL_OFFSET +#define SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE6_CSA_ADDR_LO +#define SDMA0_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE6_CSA_ADDR_HI +#define SDMA0_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_SCHEDULE_CNTL +#define SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE6_IB_SUB_REMAIN +#define SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE6_PREEMPT +#define SDMA0_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE6_DUMMY_REG +#define SDMA0_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE6_RB_AQL_CNTL +#define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE6_MINOR_PTR_UPDATE +#define SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE6_RB_PREEMPT +#define SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE6_MIDCMD_DATA0 +#define SDMA0_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA1 +#define SDMA0_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA2 +#define SDMA0_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA3 +#define SDMA0_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA4 +#define SDMA0_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA5 +#define SDMA0_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA6 +#define SDMA0_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA7 +#define SDMA0_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA8 +#define SDMA0_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA9 +#define SDMA0_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_DATA10 +#define SDMA0_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE6_MIDCMD_CNTL +#define SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_QUEUE7_RB_CNTL +#define SDMA0_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_QUEUE7_RB_BASE +#define SDMA0_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_BASE_HI +#define SDMA0_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_QUEUE7_RB_RPTR +#define SDMA0_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_RPTR_HI +#define SDMA0_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_WPTR +#define SDMA0_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_WPTR_HI +#define SDMA0_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_RPTR_ADDR_HI +#define SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_RPTR_ADDR_LO +#define SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE7_IB_CNTL +#define SDMA0_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_QUEUE7_IB_RPTR +#define SDMA0_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE7_IB_OFFSET +#define SDMA0_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_QUEUE7_IB_BASE_LO +#define SDMA0_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_QUEUE7_IB_BASE_HI +#define SDMA0_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_IB_SIZE +#define SDMA0_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_QUEUE7_SKIP_CNTL +#define SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_QUEUE7_CONTEXT_STATUS +#define SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_QUEUE7_DOORBELL +#define SDMA0_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_QUEUE7_DOORBELL_LOG +#define SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_QUEUE7_DOORBELL_OFFSET +#define SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_QUEUE7_CSA_ADDR_LO +#define SDMA0_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE7_CSA_ADDR_HI +#define SDMA0_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_SCHEDULE_CNTL +#define SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_QUEUE7_IB_SUB_REMAIN +#define SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_QUEUE7_PREEMPT +#define SDMA0_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_QUEUE7_DUMMY_REG +#define SDMA0_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI +#define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO +#define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_QUEUE7_RB_AQL_CNTL +#define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_QUEUE7_MINOR_PTR_UPDATE +#define SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_QUEUE7_RB_PREEMPT +#define SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA0_QUEUE7_MIDCMD_DATA0 +#define SDMA0_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA1 +#define SDMA0_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA2 +#define SDMA0_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA3 +#define SDMA0_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA4 +#define SDMA0_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA5 +#define SDMA0_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA6 +#define SDMA0_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA7 +#define SDMA0_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA8 +#define SDMA0_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA9 +#define SDMA0_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_DATA10 +#define SDMA0_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_QUEUE7_MIDCMD_CNTL +#define SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + + +// addressBlock: gc_sdma0_sdma1dec +//SDMA1_DEC_START +#define SDMA1_DEC_START__START__SHIFT 0x0 +#define SDMA1_DEC_START__START_MASK 0xFFFFFFFFL +//SDMA1_F32_MISC_CNTL +#define SDMA1_F32_MISC_CNTL__F32_WAKEUP__SHIFT 0x0 +#define SDMA1_F32_MISC_CNTL__F32_WAKEUP_MASK 0x00000001L +//SDMA1_GLOBAL_TIMESTAMP_LO +#define SDMA1_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define SDMA1_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_GLOBAL_TIMESTAMP_HI +#define SDMA1_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define SDMA1_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_POWER_CNTL +#define SDMA1_POWER_CNTL__LS_ENABLE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__LS_ENABLE_MASK 0x00000100L +//SDMA1_CNTL +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 +#define SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 +#define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define SDMA1_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa +#define SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb +#define SDMA1_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc +#define SDMA1_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd +#define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L +#define SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L +#define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define SDMA1_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L +#define SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L +#define SDMA1_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L +#define SDMA1_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L +#define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define SDMA1_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//SDMA1_CHICKEN_BITS +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 +#define SDMA1_CHICKEN_BITS__RD_BURST__SHIFT 0x6 +#define SDMA1_CHICKEN_BITS__WR_BURST__SHIFT 0x8 +#define SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe +#define SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 +#define SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 +#define SDMA1_CHICKEN_BITS__RESERVED__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L +#define SDMA1_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L +#define SDMA1_CHICKEN_BITS__WR_BURST_MASK 0x00000300L +#define SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L +#define SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L +#define SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L +#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L +#define SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L +#define SDMA1_CHICKEN_BITS__RESERVED_MASK 0xFC000000L +//SDMA1_GB_ADDR_CONFIG +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define SDMA1_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define SDMA1_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +//SDMA1_GB_ADDR_CONFIG_READ +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//SDMA1_RB_RPTR_FETCH +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_RB_RPTR_FETCH_HI +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA1_IB_OFFSET_FETCH +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_PROGRAM +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_STATUS_REG +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__CGCG_FENCE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA1_STATUS_REG__CGCG_FENCE_MASK 0x00000800L +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_STATUS1_REG +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc +#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0xf +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 +#define SDMA1_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 +#define SDMA1_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 +#define SDMA1_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L +#define SDMA1_STATUS1_REG__EX_START_MASK 0x00002000L +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L +#define SDMA1_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L +#define SDMA1_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L +#define SDMA1_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L +//SDMA1_CNTL1 +#define SDMA1_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 +#define SDMA1_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL +//SDMA1_HBM_PAGE_CONFIG +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA1_UCODE_CHECKSUM +#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA1_FREEZE +#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA1_PROCESS_QUANTUM0 +#define SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//SDMA1_PROCESS_QUANTUM1 +#define SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//SDMA1_WATCHDOG_CNTL +#define SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//SDMA1_QUEUE_STATUS0 +#define SDMA1_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define SDMA1_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define SDMA1_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define SDMA1_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define SDMA1_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define SDMA1_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define SDMA1_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define SDMA1_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define SDMA1_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define SDMA1_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define SDMA1_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define SDMA1_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define SDMA1_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define SDMA1_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define SDMA1_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define SDMA1_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//SDMA1_EDC_CONFIG +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA1_BA_THRESHOLD +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA1_ID +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_VERSION +#define SDMA1_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_VERSION__REV__SHIFT 0x10 +#define SDMA1_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_VERSION__REV_MASK 0x003F0000L +//SDMA1_EDC_COUNTER +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L +//SDMA1_EDC_COUNTER_CLEAR +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA1_STATUS2_REG +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT 0x2 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA1_STATUS2_REG__TH0F32_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_ATOMIC_CNTL +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_ATOMIC_PREOP_LO +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_ATOMIC_PREOP_HI +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_CNTL +#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 +#define SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 +#define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 +#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe +#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf +#define SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0x10 +#define SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0x11 +#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x12 +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL +#define SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L +#define SDMA1_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L +#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L +#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L +#define SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00010000L +#define SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00020000L +#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x003C0000L +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x3F000000L +//SDMA1_UTCL1_WATERMK +#define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 +#define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 +#define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 +#define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa +#define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc +#define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 +#define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 +#define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 +#define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL +#define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L +#define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L +#define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L +#define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L +#define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L +#define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L +#define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L +//SDMA1_UTCL1_TIMEOUT +#define SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0x0000FFFFL +//SDMA1_UTCL1_PAGE +#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa +#define SDMA1_UTCL1_PAGE__USE_IO__SHIFT 0xb +#define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc +#define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe +#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 +#define SDMA1_UTCL1_PAGE__USE_BC__SHIFT 0x16 +#define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 +#define SDMA1_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 +#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L +#define SDMA1_UTCL1_PAGE__USE_IO_MASK 0x00000800L +#define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L +#define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L +#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L +#define SDMA1_UTCL1_PAGE__USE_BC_MASK 0x00400000L +#define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L +#define SDMA1_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L +//SDMA1_UTCL1_RD_STATUS +#define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_RD_STATUS__RESERVED0__SHIFT 0x5 +#define SDMA1_UTCL1_RD_STATUS__RESERVED1__SHIFT 0x6 +#define SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0x8 +#define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT 0xb +#define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_RD_STATUS__RESERVED2__SHIFT 0xd +#define SDMA1_UTCL1_RD_STATUS__RESERVED3__SHIFT 0xe +#define SDMA1_UTCL1_RD_STATUS__META_Q_FULL__SHIFT 0xf +#define SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT 0x10 +#define SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 +#define SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT 0x13 +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT 0x15 +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT 0x16 +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT 0x17 +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT 0x18 +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT 0x19 +#define SDMA1_UTCL1_RD_STATUS__RESERVED4__SHIFT 0x1a +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT 0x1b +#define SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT 0x1c +#define SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT 0x1d +#define SDMA1_UTCL1_RD_STATUS__INV_BUSY__SHIFT 0x1e +#define SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT 0x1f +#define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_RD_STATUS__RESERVED0_MASK 0x00000020L +#define SDMA1_UTCL1_RD_STATUS__RESERVED1_MASK 0x00000040L +#define SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000100L +#define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_RD_STATUS__RESERVED2_MASK 0x00002000L +#define SDMA1_UTCL1_RD_STATUS__RESERVED3_MASK 0x00004000L +#define SDMA1_UTCL1_RD_STATUS__META_Q_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK 0x00010000L +#define SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L +#define SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK 0x00180000L +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK 0x00200000L +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK 0x00400000L +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK 0x00800000L +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK 0x01000000L +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK 0x02000000L +#define SDMA1_UTCL1_RD_STATUS__RESERVED4_MASK 0x04000000L +#define SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK 0x08000000L +#define SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK 0x10000000L +#define SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK 0x20000000L +#define SDMA1_UTCL1_RD_STATUS__INV_BUSY_MASK 0x40000000L +#define SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK 0x80000000L +//SDMA1_UTCL1_WR_STATUS +#define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_WR_STATUS__RESERVED0__SHIFT 0x7 +#define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0x8 +#define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT 0xb +#define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT 0xd +#define SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT 0xe +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0xf +#define SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT 0x10 +#define SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 +#define SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT 0x13 +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT 0x15 +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT 0x16 +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT 0x17 +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT 0x18 +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT 0x19 +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT 0x1a +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT 0x1b +#define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT 0x1c +#define SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT 0x1d +#define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT 0x1e +#define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT 0x1f +#define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_WR_STATUS__RESERVED0_MASK 0x00000080L +#define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000100L +#define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00008000L +#define SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK 0x00010000L +#define SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L +#define SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK 0x00180000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK 0x00200000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK 0x00400000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK 0x00800000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK 0x01000000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK 0x02000000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK 0x04000000L +#define SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK 0x08000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK 0x10000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK 0x20000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK 0x40000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK 0x80000000L +//SDMA1_UTCL1_INV0 +#define SDMA1_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 +#define SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 +#define SDMA1_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 +#define SDMA1_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb +#define SDMA1_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd +#define SDMA1_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe +#define SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 +#define SDMA1_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 +#define SDMA1_UTCL1_INV0__INV_TYPE__SHIFT 0x1a +#define SDMA1_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L +#define SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL +#define SDMA1_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L +#define SDMA1_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L +#define SDMA1_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L +#define SDMA1_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L +#define SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L +#define SDMA1_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L +#define SDMA1_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L +//SDMA1_UTCL1_INV1 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_INV2 +#define SDMA1_UTCL1_INV2__CPF_VMID__SHIFT 0x0 +#define SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 +#define SDMA1_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 +#define SDMA1_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL +#define SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L +#define SDMA1_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L +//SDMA1_UTCL1_RD_XNACK0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK1 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa +#define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe +#define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf +#define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L +//SDMA1_UTCL1_WR_XNACK0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_WR_XNACK1 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa +#define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe +#define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf +#define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L +//SDMA1_RELAX_ORDERING_LUT +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA1_CHICKEN_BITS_2 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT 0x6 +#define SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 +#define SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 +#define SDMA1_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc +#define SDMA1_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf +#define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define SDMA1_CHICKEN_BITS_2__RESERVED_22_20__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 +#define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +#define SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK 0x00000040L +#define SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L +#define SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L +#define SDMA1_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L +#define SDMA1_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L +#define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define SDMA1_CHICKEN_BITS_2__RESERVED_22_20_MASK 0x00700000L +#define SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L +#define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L +#define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK 0x40000000L +#define SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L +//SDMA1_STATUS3_REG +#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 +#define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 +#define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT 0x17 +#define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 +#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a +#define SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e +#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L +#define SDMA1_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L +#define SDMA1_STATUS3_REG__GCR_IDLE_MASK 0x00800000L +#define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L +#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L +#define SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L +//SDMA1_PHYSICAL_ADDR_LO +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA1_PHYSICAL_ADDR_HI +#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA1_GLOBAL_QUANTUM +#define SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//SDMA1_ERROR_LOG +#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_PUB_DUMMY_REG0 +#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG1 +#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG2 +#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG3 +#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_F32_COUNTER +#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_CRD_CNTL +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 +#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L +#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L +//SDMA1_RLC_CGCG_CTRL +#define SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 +#define SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 +#define SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L +#define SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L +//SDMA1_AQL_STATUS +#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 +#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 +#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L +#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L +//SDMA1_EA_DBIT_ADDR_DATA +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_EA_DBIT_ADDR_INDEX +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA1_TLBI_GCR_CNTL +#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 +#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 +#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 +#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 +#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 +#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL +#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L +#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L +#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L +#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L +//SDMA1_TILING_CONFIG +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//SDMA1_INT_STATUS +#define SDMA1_INT_STATUS__DATA__SHIFT 0x0 +#define SDMA1_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//SDMA1_HOLE_ADDR_LO +#define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT 0x0 +#define SDMA1_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//SDMA1_HOLE_ADDR_HI +#define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT 0x0 +#define SDMA1_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//SDMA1_CLOCK_GATING_STATUS +#define SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 +#define SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT 0x2 +#define SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 +#define SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 +#define SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x5 +#define SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x6 +#define SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L +#define SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK 0x00000004L +#define SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L +#define SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L +#define SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000020L +#define SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000040L +//SDMA1_STATUS4_REG +#define SDMA1_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 +#define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA1_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 +#define SDMA1_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 +#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 +#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 +#define SDMA1_STATUS4_REG__REG_POLLING__SHIFT 0xa +#define SDMA1_STATUS4_REG__MEM_POLLING__SHIFT 0xb +#define SDMA1_STATUS4_REG__RESERVED_13_12__SHIFT 0xc +#define SDMA1_STATUS4_REG__RESERVED_15_14__SHIFT 0xe +#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 +#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b +#define SDMA1_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L +#define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA1_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L +#define SDMA1_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L +#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L +#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L +#define SDMA1_STATUS4_REG__REG_POLLING_MASK 0x00000400L +#define SDMA1_STATUS4_REG__MEM_POLLING_MASK 0x00000800L +#define SDMA1_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L +#define SDMA1_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L +#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L +#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L +//SDMA1_SCRATCH_RAM_DATA +#define SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA1_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA1_SCRATCH_RAM_ADDR +#define SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA1_TIMESTAMP_CNTL +#define SDMA1_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define SDMA1_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//SDMA1_STATUS5_REG +#define SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 +#define SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 +#define SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 +#define SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 +#define SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 +#define SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 +#define SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1a +#define SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1b +#define SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L +#define SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L +#define SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L +#define SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L +#define SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L +#define SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L +#define SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x04000000L +#define SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x08000000L +//SDMA1_QUEUE_RESET_REQ +#define SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define SDMA1_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 +#define SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define SDMA1_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L +//SDMA1_STATUS6_REG +#define SDMA1_STATUS6_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT 0x2 +#define SDMA1_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 +#define SDMA1_STATUS6_REG__ID_MASK 0x00000003L +#define SDMA1_STATUS6_REG__TH1F32_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA1_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L +//SDMA1_UCODE1_CHECKSUM +#define SDMA1_UCODE1_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA1_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA1_CE_CTRL +#define SDMA1_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA1_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT 0x8 +#define SDMA1_CE_CTRL__RESERVED__SHIFT 0x9 +#define SDMA1_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA1_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK 0x00000100L +#define SDMA1_CE_CTRL__RESERVED_MASK 0xFFFFFE00L +//SDMA1_FED_STATUS +#define SDMA1_FED_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA1_FED_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA1_FED_STATUS__F32_DATA_ECC__SHIFT 0x2 +#define SDMA1_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT 0x3 +#define SDMA1_FED_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA1_FED_STATUS__COPY_METADATA_ECC__SHIFT 0x5 +#define SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT 0x6 +#define SDMA1_FED_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA1_FED_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA1_FED_STATUS__F32_DATA_ECC_MASK 0x00000004L +#define SDMA1_FED_STATUS__WPTR_ATOMIC_ECC_MASK 0x00000008L +#define SDMA1_FED_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA1_FED_STATUS__COPY_METADATA_ECC_MASK 0x00000020L +#define SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC_MASK 0x00000040L +//SDMA1_QUEUE0_RB_CNTL +#define SDMA1_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE0_RB_BASE +#define SDMA1_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_BASE_HI +#define SDMA1_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE0_RB_RPTR +#define SDMA1_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_RPTR_HI +#define SDMA1_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_WPTR +#define SDMA1_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_WPTR_HI +#define SDMA1_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE0_IB_CNTL +#define SDMA1_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE0_IB_RPTR +#define SDMA1_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE0_IB_OFFSET +#define SDMA1_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE0_IB_BASE_LO +#define SDMA1_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE0_IB_BASE_HI +#define SDMA1_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_IB_SIZE +#define SDMA1_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE0_SKIP_CNTL +#define SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE0_CONTEXT_STATUS +#define SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE0_DOORBELL +#define SDMA1_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE0_DOORBELL_LOG +#define SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE0_DOORBELL_OFFSET +#define SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE0_CSA_ADDR_LO +#define SDMA1_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE0_CSA_ADDR_HI +#define SDMA1_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_SCHEDULE_CNTL +#define SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE0_IB_SUB_REMAIN +#define SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE0_PREEMPT +#define SDMA1_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE0_DUMMY_REG +#define SDMA1_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE0_RB_AQL_CNTL +#define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE0_MINOR_PTR_UPDATE +#define SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE0_RB_PREEMPT +#define SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE0_MIDCMD_DATA0 +#define SDMA1_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA1 +#define SDMA1_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA2 +#define SDMA1_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA3 +#define SDMA1_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA4 +#define SDMA1_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA5 +#define SDMA1_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA6 +#define SDMA1_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA7 +#define SDMA1_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA8 +#define SDMA1_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA9 +#define SDMA1_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_DATA10 +#define SDMA1_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE0_MIDCMD_CNTL +#define SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_QUEUE1_RB_CNTL +#define SDMA1_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE1_RB_BASE +#define SDMA1_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_BASE_HI +#define SDMA1_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE1_RB_RPTR +#define SDMA1_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_RPTR_HI +#define SDMA1_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_WPTR +#define SDMA1_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_WPTR_HI +#define SDMA1_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE1_IB_CNTL +#define SDMA1_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE1_IB_RPTR +#define SDMA1_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE1_IB_OFFSET +#define SDMA1_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE1_IB_BASE_LO +#define SDMA1_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE1_IB_BASE_HI +#define SDMA1_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_IB_SIZE +#define SDMA1_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE1_SKIP_CNTL +#define SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE1_CONTEXT_STATUS +#define SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE1_DOORBELL +#define SDMA1_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE1_DOORBELL_LOG +#define SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE1_DOORBELL_OFFSET +#define SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE1_CSA_ADDR_LO +#define SDMA1_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE1_CSA_ADDR_HI +#define SDMA1_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_SCHEDULE_CNTL +#define SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE1_IB_SUB_REMAIN +#define SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE1_PREEMPT +#define SDMA1_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE1_DUMMY_REG +#define SDMA1_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE1_RB_AQL_CNTL +#define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE1_MINOR_PTR_UPDATE +#define SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE1_RB_PREEMPT +#define SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE1_MIDCMD_DATA0 +#define SDMA1_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA1 +#define SDMA1_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA2 +#define SDMA1_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA3 +#define SDMA1_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA4 +#define SDMA1_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA5 +#define SDMA1_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA6 +#define SDMA1_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA7 +#define SDMA1_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA8 +#define SDMA1_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA9 +#define SDMA1_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_DATA10 +#define SDMA1_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE1_MIDCMD_CNTL +#define SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_QUEUE2_RB_CNTL +#define SDMA1_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE2_RB_BASE +#define SDMA1_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_BASE_HI +#define SDMA1_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE2_RB_RPTR +#define SDMA1_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_RPTR_HI +#define SDMA1_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_WPTR +#define SDMA1_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_WPTR_HI +#define SDMA1_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE2_IB_CNTL +#define SDMA1_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE2_IB_RPTR +#define SDMA1_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE2_IB_OFFSET +#define SDMA1_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE2_IB_BASE_LO +#define SDMA1_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE2_IB_BASE_HI +#define SDMA1_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_IB_SIZE +#define SDMA1_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE2_SKIP_CNTL +#define SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE2_CONTEXT_STATUS +#define SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE2_DOORBELL +#define SDMA1_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE2_DOORBELL_LOG +#define SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE2_DOORBELL_OFFSET +#define SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE2_CSA_ADDR_LO +#define SDMA1_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE2_CSA_ADDR_HI +#define SDMA1_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_SCHEDULE_CNTL +#define SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE2_IB_SUB_REMAIN +#define SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE2_PREEMPT +#define SDMA1_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE2_DUMMY_REG +#define SDMA1_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE2_RB_AQL_CNTL +#define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE2_MINOR_PTR_UPDATE +#define SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE2_RB_PREEMPT +#define SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE2_MIDCMD_DATA0 +#define SDMA1_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA1 +#define SDMA1_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA2 +#define SDMA1_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA3 +#define SDMA1_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA4 +#define SDMA1_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA5 +#define SDMA1_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA6 +#define SDMA1_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA7 +#define SDMA1_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA8 +#define SDMA1_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA9 +#define SDMA1_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_DATA10 +#define SDMA1_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE2_MIDCMD_CNTL +#define SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_QUEUE3_RB_CNTL +#define SDMA1_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE3_RB_BASE +#define SDMA1_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_BASE_HI +#define SDMA1_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE3_RB_RPTR +#define SDMA1_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_RPTR_HI +#define SDMA1_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_WPTR +#define SDMA1_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_WPTR_HI +#define SDMA1_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE3_IB_CNTL +#define SDMA1_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE3_IB_RPTR +#define SDMA1_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE3_IB_OFFSET +#define SDMA1_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE3_IB_BASE_LO +#define SDMA1_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE3_IB_BASE_HI +#define SDMA1_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_IB_SIZE +#define SDMA1_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE3_SKIP_CNTL +#define SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE3_CONTEXT_STATUS +#define SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE3_DOORBELL +#define SDMA1_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE3_DOORBELL_LOG +#define SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE3_DOORBELL_OFFSET +#define SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE3_CSA_ADDR_LO +#define SDMA1_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE3_CSA_ADDR_HI +#define SDMA1_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_SCHEDULE_CNTL +#define SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE3_IB_SUB_REMAIN +#define SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE3_PREEMPT +#define SDMA1_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE3_DUMMY_REG +#define SDMA1_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE3_RB_AQL_CNTL +#define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE3_MINOR_PTR_UPDATE +#define SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE3_RB_PREEMPT +#define SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE3_MIDCMD_DATA0 +#define SDMA1_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA1 +#define SDMA1_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA2 +#define SDMA1_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA3 +#define SDMA1_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA4 +#define SDMA1_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA5 +#define SDMA1_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA6 +#define SDMA1_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA7 +#define SDMA1_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA8 +#define SDMA1_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA9 +#define SDMA1_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_DATA10 +#define SDMA1_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE3_MIDCMD_CNTL +#define SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_QUEUE4_RB_CNTL +#define SDMA1_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE4_RB_BASE +#define SDMA1_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_BASE_HI +#define SDMA1_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE4_RB_RPTR +#define SDMA1_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_RPTR_HI +#define SDMA1_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_WPTR +#define SDMA1_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_WPTR_HI +#define SDMA1_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE4_IB_CNTL +#define SDMA1_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE4_IB_RPTR +#define SDMA1_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE4_IB_OFFSET +#define SDMA1_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE4_IB_BASE_LO +#define SDMA1_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE4_IB_BASE_HI +#define SDMA1_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_IB_SIZE +#define SDMA1_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE4_SKIP_CNTL +#define SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE4_CONTEXT_STATUS +#define SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE4_DOORBELL +#define SDMA1_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE4_DOORBELL_LOG +#define SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE4_DOORBELL_OFFSET +#define SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE4_CSA_ADDR_LO +#define SDMA1_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE4_CSA_ADDR_HI +#define SDMA1_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_SCHEDULE_CNTL +#define SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE4_IB_SUB_REMAIN +#define SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE4_PREEMPT +#define SDMA1_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE4_DUMMY_REG +#define SDMA1_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE4_RB_AQL_CNTL +#define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE4_MINOR_PTR_UPDATE +#define SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE4_RB_PREEMPT +#define SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE4_MIDCMD_DATA0 +#define SDMA1_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA1 +#define SDMA1_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA2 +#define SDMA1_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA3 +#define SDMA1_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA4 +#define SDMA1_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA5 +#define SDMA1_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA6 +#define SDMA1_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA7 +#define SDMA1_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA8 +#define SDMA1_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA9 +#define SDMA1_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_DATA10 +#define SDMA1_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE4_MIDCMD_CNTL +#define SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_QUEUE5_RB_CNTL +#define SDMA1_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE5_RB_BASE +#define SDMA1_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_BASE_HI +#define SDMA1_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE5_RB_RPTR +#define SDMA1_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_RPTR_HI +#define SDMA1_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_WPTR +#define SDMA1_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_WPTR_HI +#define SDMA1_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE5_IB_CNTL +#define SDMA1_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE5_IB_RPTR +#define SDMA1_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE5_IB_OFFSET +#define SDMA1_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE5_IB_BASE_LO +#define SDMA1_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE5_IB_BASE_HI +#define SDMA1_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_IB_SIZE +#define SDMA1_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE5_SKIP_CNTL +#define SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE5_CONTEXT_STATUS +#define SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE5_DOORBELL +#define SDMA1_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE5_DOORBELL_LOG +#define SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE5_DOORBELL_OFFSET +#define SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE5_CSA_ADDR_LO +#define SDMA1_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE5_CSA_ADDR_HI +#define SDMA1_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_SCHEDULE_CNTL +#define SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE5_IB_SUB_REMAIN +#define SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE5_PREEMPT +#define SDMA1_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE5_DUMMY_REG +#define SDMA1_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE5_RB_AQL_CNTL +#define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE5_MINOR_PTR_UPDATE +#define SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE5_RB_PREEMPT +#define SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE5_MIDCMD_DATA0 +#define SDMA1_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA1 +#define SDMA1_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA2 +#define SDMA1_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA3 +#define SDMA1_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA4 +#define SDMA1_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA5 +#define SDMA1_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA6 +#define SDMA1_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA7 +#define SDMA1_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA8 +#define SDMA1_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA9 +#define SDMA1_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_DATA10 +#define SDMA1_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE5_MIDCMD_CNTL +#define SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_QUEUE6_RB_CNTL +#define SDMA1_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE6_RB_BASE +#define SDMA1_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_BASE_HI +#define SDMA1_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE6_RB_RPTR +#define SDMA1_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_RPTR_HI +#define SDMA1_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_WPTR +#define SDMA1_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_WPTR_HI +#define SDMA1_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE6_IB_CNTL +#define SDMA1_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE6_IB_RPTR +#define SDMA1_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE6_IB_OFFSET +#define SDMA1_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE6_IB_BASE_LO +#define SDMA1_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE6_IB_BASE_HI +#define SDMA1_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_IB_SIZE +#define SDMA1_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE6_SKIP_CNTL +#define SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE6_CONTEXT_STATUS +#define SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE6_DOORBELL +#define SDMA1_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE6_DOORBELL_LOG +#define SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE6_DOORBELL_OFFSET +#define SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE6_CSA_ADDR_LO +#define SDMA1_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE6_CSA_ADDR_HI +#define SDMA1_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_SCHEDULE_CNTL +#define SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE6_IB_SUB_REMAIN +#define SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE6_PREEMPT +#define SDMA1_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE6_DUMMY_REG +#define SDMA1_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE6_RB_AQL_CNTL +#define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE6_MINOR_PTR_UPDATE +#define SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE6_RB_PREEMPT +#define SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE6_MIDCMD_DATA0 +#define SDMA1_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA1 +#define SDMA1_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA2 +#define SDMA1_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA3 +#define SDMA1_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA4 +#define SDMA1_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA5 +#define SDMA1_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA6 +#define SDMA1_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA7 +#define SDMA1_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA8 +#define SDMA1_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA9 +#define SDMA1_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_DATA10 +#define SDMA1_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE6_MIDCMD_CNTL +#define SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_QUEUE7_RB_CNTL +#define SDMA1_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_QUEUE7_RB_BASE +#define SDMA1_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_BASE_HI +#define SDMA1_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_QUEUE7_RB_RPTR +#define SDMA1_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_RPTR_HI +#define SDMA1_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_WPTR +#define SDMA1_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_WPTR_HI +#define SDMA1_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_RPTR_ADDR_HI +#define SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_RPTR_ADDR_LO +#define SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE7_IB_CNTL +#define SDMA1_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_QUEUE7_IB_RPTR +#define SDMA1_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE7_IB_OFFSET +#define SDMA1_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_QUEUE7_IB_BASE_LO +#define SDMA1_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_QUEUE7_IB_BASE_HI +#define SDMA1_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_IB_SIZE +#define SDMA1_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_QUEUE7_SKIP_CNTL +#define SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_QUEUE7_CONTEXT_STATUS +#define SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_QUEUE7_DOORBELL +#define SDMA1_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_QUEUE7_DOORBELL_LOG +#define SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_QUEUE7_DOORBELL_OFFSET +#define SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_QUEUE7_CSA_ADDR_LO +#define SDMA1_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE7_CSA_ADDR_HI +#define SDMA1_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_SCHEDULE_CNTL +#define SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_QUEUE7_IB_SUB_REMAIN +#define SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_QUEUE7_PREEMPT +#define SDMA1_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_QUEUE7_DUMMY_REG +#define SDMA1_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI +#define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO +#define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_QUEUE7_RB_AQL_CNTL +#define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_QUEUE7_MINOR_PTR_UPDATE +#define SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_QUEUE7_RB_PREEMPT +#define SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//SDMA1_QUEUE7_MIDCMD_DATA0 +#define SDMA1_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA1 +#define SDMA1_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA2 +#define SDMA1_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA3 +#define SDMA1_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA4 +#define SDMA1_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA5 +#define SDMA1_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA6 +#define SDMA1_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA7 +#define SDMA1_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA8 +#define SDMA1_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA9 +#define SDMA1_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_DATA10 +#define SDMA1_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_QUEUE7_MIDCMD_CNTL +#define SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + + +// addressBlock: gc_sdma0_sdma0hypdec +//SDMA0_UCODE_ADDR +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__THID__SHIFT 0xf +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL +#define SDMA0_UCODE_ADDR__THID_MASK 0x00008000L +//SDMA0_UCODE_DATA +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_BROADCAST_UCODE_ADDR +#define SDMA0_BROADCAST_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_BROADCAST_UCODE_ADDR__THID__SHIFT 0xf +#define SDMA0_BROADCAST_UCODE_ADDR__VALUE_MASK 0x00001FFFL +#define SDMA0_BROADCAST_UCODE_ADDR__THID_MASK 0x00008000L +//SDMA0_BROADCAST_UCODE_DATA +#define SDMA0_BROADCAST_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_BROADCAST_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_CNTL +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 +#define SDMA0_F32_CNTL__TH0_RESET__SHIFT 0x9 +#define SDMA0_F32_CNTL__TH0_ENABLE__SHIFT 0xa +#define SDMA0_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc +#define SDMA0_F32_CNTL__TH1_RESET__SHIFT 0xd +#define SDMA0_F32_CNTL__TH1_ENABLE__SHIFT 0xe +#define SDMA0_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 +#define SDMA0_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 +#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA0_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L +#define SDMA0_F32_CNTL__TH0_RESET_MASK 0x00000200L +#define SDMA0_F32_CNTL__TH0_ENABLE_MASK 0x00000400L +#define SDMA0_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L +#define SDMA0_F32_CNTL__TH1_RESET_MASK 0x00002000L +#define SDMA0_F32_CNTL__TH1_ENABLE_MASK 0x00004000L +#define SDMA0_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L +#define SDMA0_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L + + +// addressBlock: gc_sdma0_sdma1hypdec +//SDMA1_UCODE_ADDR +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_ADDR__THID__SHIFT 0xf +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL +#define SDMA1_UCODE_ADDR__THID_MASK 0x00008000L +//SDMA1_UCODE_DATA +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_BROADCAST_UCODE_ADDR +#define SDMA1_BROADCAST_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_BROADCAST_UCODE_ADDR__THID__SHIFT 0xf +#define SDMA1_BROADCAST_UCODE_ADDR__VALUE_MASK 0x00001FFFL +#define SDMA1_BROADCAST_UCODE_ADDR__THID_MASK 0x00008000L +//SDMA1_BROADCAST_UCODE_DATA +#define SDMA1_BROADCAST_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_BROADCAST_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_F32_CNTL +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 +#define SDMA1_F32_CNTL__TH0_RESET__SHIFT 0x9 +#define SDMA1_F32_CNTL__TH0_ENABLE__SHIFT 0xa +#define SDMA1_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc +#define SDMA1_F32_CNTL__TH1_RESET__SHIFT 0xd +#define SDMA1_F32_CNTL__TH1_ENABLE__SHIFT 0xe +#define SDMA1_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 +#define SDMA1_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 +#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA1_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L +#define SDMA1_F32_CNTL__TH0_RESET_MASK 0x00000200L +#define SDMA1_F32_CNTL__TH0_ENABLE_MASK 0x00000400L +#define SDMA1_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L +#define SDMA1_F32_CNTL__TH1_RESET_MASK 0x00002000L +#define SDMA1_F32_CNTL__TH1_ENABLE_MASK 0x00004000L +#define SDMA1_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L +#define SDMA1_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L + + +// addressBlock: gc_sdma0_sdma0perfsdec +//SDMA0_PERFCNT_PERFCOUNTER0_CFG +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA0_PERFCNT_PERFCOUNTER1_CFG +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA0_PERFCNT_MISC_CNTL +#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA0_PERFCOUNTER0_SELECT +#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SDMA0_PERFCOUNTER0_SELECT1 +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SDMA0_PERFCOUNTER1_SELECT +#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SDMA0_PERFCOUNTER1_SELECT1 +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: gc_sdma0_sdma1perfsdec +//SDMA1_PERFCNT_PERFCOUNTER0_CFG +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA1_PERFCNT_PERFCOUNTER1_CFG +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA1_PERFCNT_MISC_CNTL +#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA1_PERFCOUNTER0_SELECT +#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SDMA1_PERFCOUNTER0_SELECT1 +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SDMA1_PERFCOUNTER1_SELECT +#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SDMA1_PERFCOUNTER1_SELECT1 +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: gc_sdma0_sdma0perfddec +//SDMA0_PERFCNT_PERFCOUNTER_LO +#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_PERFCNT_PERFCOUNTER_HI +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA0_PERFCOUNTER0_LO +#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER0_HI +#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER1_LO +#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER1_HI +#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: gc_sdma0_sdma1perfddec +//SDMA1_PERFCNT_PERFCOUNTER_LO +#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_PERFCNT_PERFCOUNTER_HI +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA1_PERFCOUNTER0_LO +#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER0_HI +#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER1_LO +#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER1_HI +#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: gc_sdma0_sdma0pwrdec + + +// addressBlock: gc_sdma0_sdma1pwrdec + + +// addressBlock: gc_grbmdec +//GRBM_CNTL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBM_SKEW_CNTL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L +//GRBM_STATUS2 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf +#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 +#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 +#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 +#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT 0x13 +#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 +#define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15 +#define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16 +#define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x1a +#define GRBM_STATUS2__TCP_BUSY__SHIFT 0x1b +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L +#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L +#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L +#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L +#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L +#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK 0x00080000L +#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L +#define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L +#define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L +#define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L +#define GRBM_STATUS2__RLC_BUSY_MASK 0x04000000L +#define GRBM_STATUS2__TCP_BUSY_MASK 0x08000000L +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +//GRBM_PWR_CNTL +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L +//GRBM_STATUS +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__SDMA_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf +#define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__GE_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__ANY_ACTIVE__SHIFT 0x1b +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS__SDMA_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L +#define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__GE_BUSY_MASK 0x00200000L +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__ANY_ACTIVE_MASK 0x08000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +//GRBM_STATUS_SE0 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE0__GL1H_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE0__PC_BUSY__SHIFT 0x7 +#define GRBM_STATUS_SE0__SEDC_BUSY__SHIFT 0x8 +#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE0__GL1H_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE0__PC_BUSY_MASK 0x00000080L +#define GRBM_STATUS_SE0__SEDC_BUSY_MASK 0x00000100L +#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE1 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE1__GL1H_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE1__PC_BUSY__SHIFT 0x7 +#define GRBM_STATUS_SE1__SEDC_BUSY__SHIFT 0x8 +#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE1__GL1H_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE1__PC_BUSY_MASK 0x00000080L +#define GRBM_STATUS_SE1__SEDC_BUSY_MASK 0x00000100L +#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS3 +#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5 +#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7 +#define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS3__PH_BUSY__SHIFT 0xd +#define GRBM_STATUS3__CH_BUSY__SHIFT 0xe +#define GRBM_STATUS3__GL2CC_BUSY__SHIFT 0xf +#define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10 +#define GRBM_STATUS3__SEDC_BUSY__SHIFT 0x19 +#define GRBM_STATUS3__PC_BUSY__SHIFT 0x1a +#define GRBM_STATUS3__GL1H_BUSY__SHIFT 0x1b +#define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT 0x1c +#define GRBM_STATUS3__GUS_BUSY__SHIFT 0x1d +#define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e +#define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f +#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L +#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L +#define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS3__PH_BUSY_MASK 0x00002000L +#define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L +#define GRBM_STATUS3__GL2CC_BUSY_MASK 0x00008000L +#define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L +#define GRBM_STATUS3__SEDC_BUSY_MASK 0x02000000L +#define GRBM_STATUS3__PC_BUSY_MASK 0x04000000L +#define GRBM_STATUS3__GL1H_BUSY_MASK 0x08000000L +#define GRBM_STATUS3__GUS_LINK_BUSY_MASK 0x10000000L +#define GRBM_STATUS3__GUS_BUSY_MASK 0x20000000L +#define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L +#define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L +//GRBM_SOFT_RESET +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT 0xf +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17 +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK 0x00008000L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L +#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L +//GRBM_GFX_CLKEN_CNTL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBM_WAIT_IDLE_CLOCKS +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL +//GRBM_STATUS_SE2 +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE2__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE2__GL1H_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE2__PC_BUSY__SHIFT 0x7 +#define GRBM_STATUS_SE2__SEDC_BUSY__SHIFT 0x8 +#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE2__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE2__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE2__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE2__GL1H_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE2__PC_BUSY_MASK 0x00000080L +#define GRBM_STATUS_SE2__SEDC_BUSY_MASK 0x00000100L +#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE3 +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE3__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE3__GL1H_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE3__PC_BUSY__SHIFT 0x7 +#define GRBM_STATUS_SE3__SEDC_BUSY__SHIFT 0x8 +#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE3__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE3__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE3__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE3__GL1H_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE3__PC_BUSY_MASK 0x00000080L +#define GRBM_STATUS_SE3__SEDC_BUSY_MASK 0x00000100L +#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE4 +#define GRBM_STATUS_SE4__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE4__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE4__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE4__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE4__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE4__GL1H_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE4__PC_BUSY__SHIFT 0x7 +#define GRBM_STATUS_SE4__SEDC_BUSY__SHIFT 0x8 +#define GRBM_STATUS_SE4__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE4__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE4__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE4__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE4__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE4__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE4__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE4__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE4__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE4__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE4__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE4__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE4__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE4__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE4__GL1H_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE4__PC_BUSY_MASK 0x00000080L +#define GRBM_STATUS_SE4__SEDC_BUSY_MASK 0x00000100L +#define GRBM_STATUS_SE4__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE4__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE4__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE4__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE4__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE4__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE4__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE4__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE4__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE5 +#define GRBM_STATUS_SE5__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE5__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE5__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE5__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE5__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE5__GL1H_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE5__PC_BUSY__SHIFT 0x7 +#define GRBM_STATUS_SE5__SEDC_BUSY__SHIFT 0x8 +#define GRBM_STATUS_SE5__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE5__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE5__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE5__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE5__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE5__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE5__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE5__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE5__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE5__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE5__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE5__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE5__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE5__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE5__GL1H_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE5__PC_BUSY_MASK 0x00000080L +#define GRBM_STATUS_SE5__SEDC_BUSY_MASK 0x00000100L +#define GRBM_STATUS_SE5__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE5__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE5__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE5__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE5__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE5__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE5__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE5__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE5__CB_BUSY_MASK 0x80000000L +//GRBM_READ_ERROR +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x000FFFFCL +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBM_READ_ERROR2 +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT 0x9 +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT 0xa +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT 0xb +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT 0xc +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT 0xd +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT 0xe +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK 0x00000200L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK 0x00000400L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK 0x00000800L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK 0x00001000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK 0x00002000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK 0x00004000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +//GRBM_INT_CNTL +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +//GRBM_TRAP_OP +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_OP__RW_MASK 0x00000001L +//GRBM_TRAP_ADDR +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_ADDR_MSK +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_WD +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL +//GRBM_TRAP_WD_MSK +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL +//GRBM_DSM_BYPASS +#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 +#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L +#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L +//GRBM_WRITE_ERROR +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x8 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11 +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000003CL +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x00000F00L +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L +#define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L +//GRBM_CHIP_REVISION +#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL +//GRBM_IH_CREDIT +#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//GRBM_PWR_CNTL2 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L +//GRBM_UTCL2_INVAL_RANGE_START +#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL +//GRBM_UTCL2_INVAL_RANGE_END +#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL +//GRBM_INVALID_PIPE +#define GRBM_INVALID_PIPE__ADDR__SHIFT 0x2 +#define GRBM_INVALID_PIPE__PIPEID__SHIFT 0x14 +#define GRBM_INVALID_PIPE__MEID__SHIFT 0x16 +#define GRBM_INVALID_PIPE__QUEUEID__SHIFT 0x18 +#define GRBM_INVALID_PIPE__SSRCID__SHIFT 0x1b +#define GRBM_INVALID_PIPE__INVALID_PIPE__SHIFT 0x1f +#define GRBM_INVALID_PIPE__ADDR_MASK 0x000FFFFCL +#define GRBM_INVALID_PIPE__PIPEID_MASK 0x00300000L +#define GRBM_INVALID_PIPE__MEID_MASK 0x00C00000L +#define GRBM_INVALID_PIPE__QUEUEID_MASK 0x07000000L +#define GRBM_INVALID_PIPE__SSRCID_MASK 0x78000000L +#define GRBM_INVALID_PIPE__INVALID_PIPE_MASK 0x80000000L +//GRBM_FENCE_RANGE0 +#define GRBM_FENCE_RANGE0__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE0__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L +//GRBM_FENCE_RANGE1 +#define GRBM_FENCE_RANGE1__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE1__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L +//GRBM_SCRATCH_REG0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG1 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG2 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG3 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG4 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG5 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG6 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG7 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//VIOLATION_DATA_ASYNC_VF_PROG +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L + + +// addressBlock: gc_cpdec +//CP_CPC_DEBUG_CNTL +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_CPC_DEBUG_DATA +#define CP_CPC_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_CPC_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_CPC_STATUS +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf +#define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10 +#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 +#define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12 +#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 +#define CP_CPC_STATUS__MES_DATA_CACHE_BUSY__SHIFT 0x14 +#define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY__SHIFT 0x15 +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L +#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L +#define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L +#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L +#define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L +#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L +#define CP_CPC_STATUS__MES_DATA_CACHE_BUSY_MASK 0x00100000L +#define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY_MASK 0x00200000L +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L +//CP_CPC_BUSY_STAT +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY__SHIFT 0x1 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY_MASK 0x00000002L +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY_MASK 0x00020000L +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//CP_CPC_STALLED_STAT1 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x7 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000080L +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L +//CP_CPF_STATUS +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12 +#define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13 +#define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14 +#define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15 +#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16 +#define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17 +#define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L +#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L +#define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L +#define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L +#define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L +#define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L +#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L +#define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L +#define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L +//CP_CPF_BUSY_STAT +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L +#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L +#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L +//CP_CPF_STALLED_STAT1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb +#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc +#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L +#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L +#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L +//CP_CPC_BUSY_STAT2 +#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L +//CP_CPC_GRBM_FREE_COUNT +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +//CP_CPC_PRIV_VIOLATION_ADDR +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0003FFFFL +//CP_MEC_ME1_HEADER_DUMP +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_MEC_ME2_HEADER_DUMP +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_CPC_SCRATCH_INDEX +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_CPC_SCRATCH_DATA +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_CPF_GRBM_FREE_COUNT +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L +//CP_CPF_BUSY_STAT2 +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L +//CP_CPC_HALT_HYST_COUNT +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//CP_STALLED_STAT3 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L +#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L +//CP_STALLED_STAT1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0__SHIFT 0x2 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1__SHIFT 0x3 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT 0x4 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT 0x5 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0_MASK 0x00000004L +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1_MASK 0x00000008L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK 0x00000010L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK 0x00000020L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L +//CP_STALLED_STAT2 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT 0x15 +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK 0x00200000L +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +//CP_BUSY_STAT +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +//CP_STAT +#define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5 +#define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6 +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__GCRIU_BUSY__SHIFT 0x19 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L +#define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__GCRIU_BUSY_MASK 0x02000000L +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +//CP_ME_HEADER_DUMP +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_HEADER_DUMP +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_GRBM_FREE_COUNT +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L +//CP_PFP_INSTR_PNTR +#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_ME_INSTR_PNTR +#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC1_INSTR_PNTR +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC2_INSTR_PNTR +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CSF_STAT +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L +//CP_CNTX_STAT +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +//CP_ME_PREEMPTION +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L +//CP_RB1_RPTR +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB0_RPTR +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L +//CP_RB_WPTR_POLL_CNTL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000UL +//CP_ROQ1_THRESHOLDS +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L +//CP_ROQ2_THRESHOLDS +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L +//CP_STQ_THRESHOLDS +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L +//CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L +//CP_ROQ_AVAIL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L +//CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL +//CP_ROQ2_AVAIL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL +#define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L +//CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL +//CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L +//CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL +//CP_ROQ_RB_STAT +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L +//CP_ROQ_IB1_STAT +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L +//CP_ROQ_IB2_STAT +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L +//CP_STQ_STAT +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL +//CP_STQ_WR_STAT +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL +//CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L +//CP_ROQ3_THRESHOLDS +#define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0 +#define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa +#define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL +#define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L +//CP_ROQ_DB_STAT +#define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0 +#define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10 +#define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL +#define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +//CP_DEBUG_CNTL +#define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_DEBUG_DATA +#define CP_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_PRIV_VIOLATION_ADDR +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0003FFFFL + + +// addressBlock: gc_padec +//VGT_DMA_DATA_FIFO_DEPTH +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL +//VGT_DMA_REQ_FIFO_DEPTH +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL +//VGT_DRAW_INIT_FIFO_DEPTH +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL +//VGT_MC_LAT_CNTL +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL +//IA_UTCL1_STATUS_2 +#define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT 0x0 +#define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT 0x1 +#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT 0x2 +#define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT 0x3 +#define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT 0x4 +#define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x5 +#define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x6 +#define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x7 +#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS_2__IA_BUSY_MASK 0x00000001L +#define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK 0x00000002L +#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK 0x00000004L +#define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK 0x00000008L +#define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK 0x00000010L +#define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000020L +#define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000040L +#define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000080L +#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L +//WD_CNTL_STATUS +#define WD_CNTL_STATUS__DIST_BUSY__SHIFT 0x0 +#define WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT 0x1 +#define WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT 0x2 +#define WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT 0x3 +#define WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT 0x4 +#define WD_CNTL_STATUS__WLC_BUSY__SHIFT 0x5 +#define WD_CNTL_STATUS__DIST_BUSY_MASK 0x00000001L +#define WD_CNTL_STATUS__DIST_BE_BUSY_MASK 0x00000002L +#define WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK 0x00000004L +#define WD_CNTL_STATUS__WD_TE11_BUSY_MASK 0x00000008L +#define WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK 0x00000010L +#define WD_CNTL_STATUS__WLC_BUSY_MASK 0x00000020L +//CC_GC_PRIM_CONFIG +#define CC_GC_PRIM_CONFIG__INACTIVE_PA__SHIFT 0x4 +#define CC_GC_PRIM_CONFIG__INACTIVE_PA_MASK 0x000FFFF0L +//WD_QOS +#define WD_QOS__DRAW_STALL__SHIFT 0x0 +#define WD_QOS__DRAW_STALL_MASK 0x00000001L +//WD_UTCL1_CNTL +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d +#define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT 0x1e +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L +#define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK 0x40000000L +//WD_UTCL1_STATUS +#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//IA_UTCL1_CNTL +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d +#define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT 0x1e +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L +#define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK 0x40000000L +//IA_UTCL1_STATUS +#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CC_GC_SA_UNIT_DISABLE +#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L +//GE_RATE_CNTL_1 +#define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT__SHIFT 0x0 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT__SHIFT 0x4 +#define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT__SHIFT 0x8 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT__SHIFT 0xc +#define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT__SHIFT 0x10 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT__SHIFT 0x14 +#define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM__SHIFT 0x18 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM__SHIFT 0x1c +#define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT_MASK 0x0000000FL +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT_MASK 0x000000F0L +#define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT_MASK 0x00000F00L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT_MASK 0x0000F000L +#define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT_MASK 0x000F0000L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT_MASK 0x00F00000L +#define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM_MASK 0x0F000000L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM_MASK 0xF0000000L +//GE_RATE_CNTL_2 +#define GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT__SHIFT 0x0 +#define GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT__SHIFT 0x4 +#define GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM__SHIFT 0x8 +#define GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM__SHIFT 0xc +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS__SHIFT 0x10 +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES__SHIFT 0x14 +#define GE_RATE_CNTL_2__MERGED_HS_GS_MODE__SHIFT 0x18 +#define GE_RATE_CNTL_2__MERGED_LS_ES_MODE__SHIFT 0x19 +#define GE_RATE_CNTL_2__ENABLE_RATE_CNTL__SHIFT 0x1a +#define GE_RATE_CNTL_2__SWAP_PRIORITY__SHIFT 0x1b +#define GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT_MASK 0x0000000FL +#define GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT_MASK 0x000000F0L +#define GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM_MASK 0x00000F00L +#define GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM_MASK 0x0000F000L +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS_MASK 0x000F0000L +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES_MASK 0x00F00000L +#define GE_RATE_CNTL_2__MERGED_HS_GS_MODE_MASK 0x01000000L +#define GE_RATE_CNTL_2__MERGED_LS_ES_MODE_MASK 0x02000000L +#define GE_RATE_CNTL_2__ENABLE_RATE_CNTL_MASK 0x04000000L +#define GE_RATE_CNTL_2__SWAP_PRIORITY_MASK 0x08000000L +//VGT_SYS_CONFIG +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 +#define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT__SHIFT 0x8 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L +#define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT_MASK 0x0007FF00L +//GE_PRIV_CONTROL +#define GE_PRIV_CONTROL__RESERVED__SHIFT 0x0 +#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1 +#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa +#define GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT 0xf +#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT 0x10 +#define GE_PRIV_CONTROL__DISABLE_ACCUM_AGM__SHIFT 0x11 +#define GE_PRIV_CONTROL__RESERVED_MASK 0x00000001L +#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL +#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK 0x00000400L +#define GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK 0x00008000L +#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK 0x00010000L +#define GE_PRIV_CONTROL__DISABLE_ACCUM_AGM_MASK 0x00020000L +//GE_STATUS +#define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0 +#define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1 +#define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L +#define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L +//VGT_GS_MAX_WAVE_ID +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GFX_PIPE_CONTROL +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT 0x11 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL +#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK 0x00020000L +//CC_GC_SHADER_ARRAY_CONFIG +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L +//GE2_SE_CNTL_STATUS +#define GE2_SE_CNTL_STATUS__TE_BUSY__SHIFT 0x0 +#define GE2_SE_CNTL_STATUS__NGG_BUSY__SHIFT 0x1 +#define GE2_SE_CNTL_STATUS__HS_BUSY__SHIFT 0x2 +#define GE2_SE_CNTL_STATUS__TE_BUSY_MASK 0x00000001L +#define GE2_SE_CNTL_STATUS__NGG_BUSY_MASK 0x00000002L +#define GE2_SE_CNTL_STATUS__HS_BUSY_MASK 0x00000004L +//GE_SPI_IF_SAFE_REG +#define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA__SHIFT 0x0 +#define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA__SHIFT 0x6 +#define GE_SPI_IF_SAFE_REG__GE_SPI_GRP__SHIFT 0xc +#define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA_MASK 0x0000003FL +#define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA_MASK 0x00000FC0L +#define GE_SPI_IF_SAFE_REG__GE_SPI_GRP_MASK 0x0003F000L +//GE_PA_IF_SAFE_REG +#define GE_PA_IF_SAFE_REG__GE_PA_CSB__SHIFT 0x0 +#define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD__SHIFT 0xa +#define GE_PA_IF_SAFE_REG__GE_PA_CSB_MASK 0x000003FFL +#define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD_MASK 0x000FFC00L +//PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +//PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x12 +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x13 +#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x14 +#define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE__SHIFT 0x15 +#define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL__SHIFT 0x16 +#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT 0x17 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00040000L +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00080000L +#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00100000L +#define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE_MASK 0x00200000L +#define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL_MASK 0x00400000L +#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK 0x00800000L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +//PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +//PA_SC_FIFO_DEPTH_CNTL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL + + +// addressBlock: gc_sqdec +//SQ_CONFIG +#define SQ_CONFIG__ECO_SPARE__SHIFT 0x0 +#define SQ_CONFIG__NEW_TRANS_ARB_SCHEME__SHIFT 0x8 +#define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP__SHIFT 0x9 +#define SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT 0xa +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS__SHIFT 0x13 +#define SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT 0x15 +#define SQ_CONFIG__DISABLE_END_CLAUSE_TX__SHIFT 0x1b +#define SQ_CONFIG__ECO_SPARE_MASK 0x000000FFL +#define SQ_CONFIG__NEW_TRANS_ARB_SCHEME_MASK 0x00000100L +#define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP_MASK 0x00000200L +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS_MASK 0x00040000L +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS_MASK 0x00180000L +#define SQ_CONFIG__DISABLE_END_CLAUSE_TX_MASK 0x08000000L +//SQC_CONFIG +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x9 +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xa +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xc +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xd +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0xe +#define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE__SHIFT 0x16 +#define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG__SHIFT 0x17 +#define SQC_CONFIG__SPARE__SHIFT 0x1a +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000200L +#define SQC_CONFIG__EVICT_LRU_MASK 0x00000C00L +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00001000L +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00002000L +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x003FC000L +#define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE_MASK 0x00400000L +#define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG_MASK 0x03800000L +#define SQC_CONFIG__SPARE_MASK 0xFC000000L +//LDS_CONFIG +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 +#define LDS_CONFIG__CONF_BIT_1__SHIFT 0x1 +#define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE__SHIFT 0x2 +#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT 0x3 +#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT 0x4 +#define LDS_CONFIG__CONF_BIT_5__SHIFT 0x5 +#define LDS_CONFIG__CONF_BIT_6__SHIFT 0x6 +#define LDS_CONFIG__CONF_BIT_7__SHIFT 0x7 +#define LDS_CONFIG__CONF_BIT_8__SHIFT 0x8 +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L +#define LDS_CONFIG__CONF_BIT_1_MASK 0x00000002L +#define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE_MASK 0x00000004L +#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK 0x00000008L +#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK 0x00000010L +#define LDS_CONFIG__CONF_BIT_5_MASK 0x00000020L +#define LDS_CONFIG__CONF_BIT_6_MASK 0x00000040L +#define LDS_CONFIG__CONF_BIT_7_MASK 0x00000080L +#define LDS_CONFIG__CONF_BIT_8_MASK 0x00000100L +//SQ_RANDOM_WAVE_PRI +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT 0x1f +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L +#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK 0x80000000L +//SQG_STATUS +#define SQG_STATUS__REG_BUSY__SHIFT 0x0 +#define SQG_STATUS__REG_BUSY_MASK 0x00000001L +//SQ_FIFO_SIZES +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED__SHIFT 0xc +#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe +#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT__SHIFT 0x14 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L +#define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED_MASK 0x00003000L +#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L +#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L +#define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT_MASK 0x00300000L +//SQ_DSM_CNTL +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQ_DSM_CNTL2 +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe +#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L +#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L +//SP_CONFIG +#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT 0x0 +#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT 0x2 +#define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3 +#define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x4 +#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT 0x5 +#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK 0x00000003L +#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK 0x00000004L +#define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L +#define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000010L +#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK 0x00000020L +//SQ_ARB_CONFIG +#define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0 +#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4 +#define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L +#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L +//SQ_DEBUG_HOST_TRAP_STATUS +#define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT__SHIFT 0x0 +#define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT_MASK 0x0000007FL +//SQG_GL1H_STATUS +#define SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED__SHIFT 0x0 +#define SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED__SHIFT 0x1 +#define SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED__SHIFT 0x2 +#define SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED__SHIFT 0x3 +#define SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED_MASK 0x00000001L +#define SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED_MASK 0x00000002L +#define SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED_MASK 0x00000004L +#define SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED_MASK 0x00000008L +//SQG_CONFIG +#define SQG_CONFIG__GL1H_PREFETCH_PAGE__SHIFT 0x0 +#define SQG_CONFIG__SQG_ICPFT_EN__SHIFT 0xd +#define SQG_CONFIG__SQG_ICPFT_CLR__SHIFT 0xe +#define SQG_CONFIG__XNACK_INTR_MASK__SHIFT 0x10 +#define SQG_CONFIG__GL1H_PREFETCH_PAGE_MASK 0x0000000FL +#define SQG_CONFIG__SQG_ICPFT_EN_MASK 0x00002000L +#define SQG_CONFIG__SQG_ICPFT_CLR_MASK 0x00004000L +#define SQG_CONFIG__XNACK_INTR_MASK_MASK 0xFFFF0000L +//SQ_PERF_SNAPSHOT_CTRL +#define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT 0x1 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT 0x11 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL__SHIFT 0x12 +#define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF_MASK 0x00000001L +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK 0x0001FFFEL +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK 0x00020000L +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL_MASK 0x003C0000L +//CC_GC_SHADER_RATE_CONFIG +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +//SQ_INTERRUPT_AUTO_MASK +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL +//SQ_INTERRUPT_MSG_CTRL +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L +//SQ_WATCH0_ADDR_H +#define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL +//SQ_WATCH0_ADDR_L +#define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH0_CNTL +#define SQ_WATCH0_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH0_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH1_ADDR_H +#define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL +//SQ_WATCH1_ADDR_L +#define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH1_CNTL +#define SQ_WATCH1_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH1_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH2_ADDR_H +#define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL +//SQ_WATCH2_ADDR_L +#define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH2_CNTL +#define SQ_WATCH2_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH2_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH3_ADDR_H +#define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL +//SQ_WATCH3_ADDR_L +#define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH3_CNTL +#define SQ_WATCH3_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH3_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L +//SQ_IND_INDEX +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL +#define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L +#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L +//SQ_IND_DATA +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL +//SQ_CMD +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_CMD__CMD_MASK 0x0000000FL +#define SQ_CMD__MODE_MASK 0x00000070L +#define SQ_CMD__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD__DATA_MASK 0x00000F00L +#define SQ_CMD__WAVE_ID_MASK 0x001F0000L +#define SQ_CMD__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD__VM_ID_MASK 0xF0000000L + + +// addressBlock: gc_shsdec +//SX_DEBUG_1 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x7 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc +#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd +#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT 0xe +#define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf +#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT 0x10 +#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11 +#define SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT 0x12 +#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT 0x13 +#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT 0x14 +#define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT__SHIFT 0x15 +#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT 0x16 +#define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT__SHIFT 0x17 +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x18 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL +#define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00000080L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L +#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L +#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK 0x00004000L +#define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L +#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK 0x00010000L +#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L +#define SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK 0x00040000L +#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK 0x00080000L +#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK 0x00100000L +#define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT_MASK 0x00200000L +#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK 0x00400000L +#define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT_MASK 0x00800000L +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFF000000L +//SPI_PS_MAX_WAVE_ID +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L +//SPI_GFX_CNTL +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L +//SPI_DSM_CNTL +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +//SPI_DSM_CNTL2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L +//SPI_EDC_CNT +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L +//SPI_CONFIG_PS_CU_EN +#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT 0x0 +#define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET__SHIFT 0x4 +#define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET__SHIFT 0x8 +#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK 0x0000000FL +#define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET_MASK 0x000000F0L +#define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET_MASK 0x00000F00L +//SPI_WF_LIFETIME_CNTL +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L +//SPI_WF_LIFETIME_LIMIT_0 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_1 +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_2 +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_3 +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_4 +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_5 +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_0 +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_2 +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_4 +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_6 +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_7 +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_9 +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_11 +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_13 +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_14 +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_15 +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_16 +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_17 +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_18 +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_19 +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_20 +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_21 +#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK 0x80000000L +//SPI_LB_CTR_CTRL +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 +#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L +#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L +//SPI_LB_WGP_MASK +#define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0 +#define SPI_LB_WGP_MASK__WGP_MASK_MASK 0xFFFFL +//SPI_LB_DATA_REG +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL +//SPI_PG_ENABLE_STATIC_WGP_MASK +#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0xFFFFL +//SPI_GDS_CREDITS +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L +//SPI_SX_EXPORT_BUFFER_SIZES +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L +//SPI_SX_SCOREBOARD_BUFFER_SIZES +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L +//SPI_CSQ_WF_ACTIVE_STATUS +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL +//SPI_CSQ_WF_ACTIVE_COUNT_0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_1 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_2 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_3 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L +//SPI_LB_DATA_WAVES +#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 +#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 +#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL +#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L +//SPI_P0_TRAP_SCREEN_PSBA_LO +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_HI +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_PSMA_LO +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSMA_HI +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_GPR_MIN +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L +//SPI_P1_TRAP_SCREEN_PSBA_LO +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSBA_HI +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_PSMA_LO +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSMA_HI +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_GPR_MIN +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L + + +// addressBlock: gc_tpdec +//TD_STATUS +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_STATUS__BUSY_MASK 0x80000000L +//TD_DSM_CNTL +//TD_DSM_CNTL2 +//TD_SCRATCH +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_CNTL +#define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT 0x0 +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK 0x00000001L +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L +//TA_CNTL_AUX +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS__SHIFT 0x1 +#define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM__SHIFT 0x2 +#define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS__SHIFT 0x3 +#define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT 0x4 +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 +#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 +#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT 0x8 +#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9 +#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc +#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd +#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe +#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 +#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c +#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d +#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L +#define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS_MASK 0x00000002L +#define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM_MASK 0x00000004L +#define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS_MASK 0x00000008L +#define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK 0x00000010L +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L +#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L +#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK 0x00000100L +#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L +#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L +#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L +#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L +#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L +#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L +#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L +#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L +#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L +//TA_CNTL2 +#define TA_CNTL2__POINT_SAMPLE_ACCEL_DIS__SHIFT 0x10 +#define TA_CNTL2__TRUNCATE_COORD_MODE__SHIFT 0x12 +#define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS__SHIFT 0x13 +#define TA_CNTL2__POINT_SAMPLE_ACCEL_DIS_MASK 0x00010000L +#define TA_CNTL2__TRUNCATE_COORD_MODE_MASK 0x00040000L +#define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS_MASK 0x00080000L +//TA_STATUS +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__LA_BUSY_MASK 0x04000000L +#define TA_STATUS__FL_BUSY_MASK 0x08000000L +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__BUSY_MASK 0x80000000L +//TA_SCRATCH +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL + + +// addressBlock: gc_gdsdec +//GDS_CONFIG +#define GDS_CONFIG__UNUSED__SHIFT 0x1 +#define GDS_CONFIG__UNUSED_MASK 0xFFFFFFFEL +//GDS_CNTL_STATUS +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x3 +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x4 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x5 +#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x6 +#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x7 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0x8 +#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0x9 +#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xa +#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xb +#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xc +#define GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT 0xd +#define GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT 0xe +#define GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT 0xf +#define GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT 0x10 +#define GDS_CNTL_STATUS__UNUSED__SHIFT 0x11 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000008L +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000010L +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000020L +#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000040L +#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000080L +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000100L +#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000200L +#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00000400L +#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00000800L +#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00001000L +#define GDS_CNTL_STATUS__CREDIT_BUSY4_MASK 0x00002000L +#define GDS_CNTL_STATUS__CREDIT_BUSY5_MASK 0x00004000L +#define GDS_CNTL_STATUS__CREDIT_BUSY6_MASK 0x00008000L +#define GDS_CNTL_STATUS__CREDIT_BUSY7_MASK 0x00010000L +#define GDS_CNTL_STATUS__UNUSED_MASK 0xFFFE0000L +//GDS_ENHANCE +#define GDS_ENHANCE__MISC__SHIFT 0x0 +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 +#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 +#define GDS_ENHANCE__UNUSED__SHIFT 0x12 +#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L +#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L +#define GDS_ENHANCE__UNUSED_MASK 0xFFFC0000L +//GDS_PROTECTION_FAULT +#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 +#define GDS_PROTECTION_FAULT__SE_ID__SHIFT 0x3 +#define GDS_PROTECTION_FAULT__SA_ID__SHIFT 0x6 +#define GDS_PROTECTION_FAULT__WGP_ID__SHIFT 0x7 +#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xb +#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xd +#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x12 +#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L +#define GDS_PROTECTION_FAULT__SE_ID_MASK 0x00000038L +#define GDS_PROTECTION_FAULT__SA_ID_MASK 0x00000040L +#define GDS_PROTECTION_FAULT__WGP_ID_MASK 0x00000780L +#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00001800L +#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0003E000L +#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFC0000L +//GDS_VM_PROTECTION_FAULT +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 +#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 +#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 +#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 +#define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT 0x6 +#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 +#define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT 0xc +#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L +#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L +#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L +#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L +#define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK 0x000000C0L +#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L +#define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK 0x0000F000L +#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L +//GDS_EDC_CNT +#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 +#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 +#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 +#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L +#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL +#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L +//GDS_EDC_GRBM_CNT +#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 +#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 +#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 +#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L +#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL +#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L +//GDS_EDC_OA_DED +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 +#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa +#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb +#define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED__SHIFT 0xc +#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xd +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L +#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L +#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L +#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L +#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L +#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L +#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L +#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L +#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L +#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L +#define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED_MASK 0x00001000L +#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFE000L +//GDS_DSM_CNTL +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L +//GDS_EDC_OA_PHY_CNT +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 +#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L +#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L +//GDS_EDC_OA_PIPE_CNT +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe +#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L +#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_DSM_CNTL2 +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L + + +// addressBlock: gc_rbdec +//DB_DEBUG +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L +//DB_DEBUG2 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT 0xe +#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0xf +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x14 +#define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES__SHIFT 0x15 +#define DB_DEBUG2__FORCE_ITERATE_256__SHIFT 0x18 +#define DB_DEBUG2__RESERVED1__SHIFT 0x1a +#define DB_DEBUG2__DEBUG_BUS_FLOP_EN__SHIFT 0x1b +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L +#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK 0x00004000L +#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x00008000L +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00100000L +#define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES_MASK 0x00200000L +#define DB_DEBUG2__FORCE_ITERATE_256_MASK 0x03000000L +#define DB_DEBUG2__RESERVED1_MASK 0x04000000L +#define DB_DEBUG2__DEBUG_BUS_FLOP_EN_MASK 0x08000000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +//DB_DEBUG3 +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 +#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c +#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT 0x1d +#define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT 0x1e +#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L +#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L +#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L +#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK 0x20000000L +#define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK 0x40000000L +#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L +//DB_DEBUG4 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4 +#define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK__SHIFT 0x5 +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x6 +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x7 +#define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK__SHIFT 0x8 +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf +#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10 +#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT 0x12 +#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT 0x13 +#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT 0x15 +#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT 0x16 +#define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT 0x18 +#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT 0x1b +#define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT 0x1c +#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e +#define DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD__SHIFT 0x1f +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L +#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L +#define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK_MASK 0x00000020L +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000040L +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000080L +#define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK_MASK 0x00000100L +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L +#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L +#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK 0x00040000L +#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK 0x00080000L +#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK 0x00200000L +#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK 0x00400000L +#define DB_DEBUG4__WR_MEM_BURST_CTL_MASK 0x07000000L +#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK 0x08000000L +#define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK 0x10000000L +#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L +#define DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD_MASK 0x80000000L +//DB_ETILE_STUTTER_CONTROL +#define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 +#define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 +#define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL +#define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L +//DB_LTILE_STUTTER_CONTROL +#define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 +#define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 +#define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL +#define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L +//DB_EQUAD_STUTTER_CONTROL +#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 +#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 +#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL +#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L +//DB_LQUAD_STUTTER_CONTROL +#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 +#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 +#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL +#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L +//DB_CREDIT_LIMIT +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS__SHIFT 0xd +#define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS__SHIFT 0x12 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L +#define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS_MASK 0x0003E000L +#define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS_MASK 0x007C0000L +//DB_WATERMARKS +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8 +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10 +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L +//DB_SUBTILE_CONTROL +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L +//DB_FREE_CACHELINES +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10 +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x18 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0xFF000000L +//DB_FIFO_DEPTH1 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x00FF0000L +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L +//DB_FIFO_DEPTH2 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L +//DB_LAST_OF_BURST_CONFIG +#define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT 0x0 +#define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT 0x8 +#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT 0xb +#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT 0x11 +#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT 0x12 +#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT 0x13 +#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT 0x14 +#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT 0x15 +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT 0x16 +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT 0x17 +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT 0x19 +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT 0x1a +#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT 0x1c +#define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE__SHIFT 0x1d +#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT 0x1e +#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT 0x1f +#define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK 0x000000FFL +#define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK 0x00000700L +#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK 0x0000F800L +#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK 0x00020000L +#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK 0x00040000L +#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK 0x00080000L +#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK 0x00100000L +#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK 0x00200000L +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK 0x00400000L +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK 0x00800000L +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK 0x02000000L +#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK 0x04000000L +#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK 0x10000000L +#define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE_MASK 0x20000000L +#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK 0x40000000L +#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK 0x80000000L +//DB_RING_CONTROL +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L +//DB_MEM_ARB_WATERMARKS +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L +//DB_FIFO_DEPTH3 +#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18 +#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH_MASK 0x00FF0000L +#define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L +//DB_DEBUG6 +#define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT__SHIFT 0x0 +#define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT__SHIFT 0x1 +#define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT__SHIFT 0x2 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL__SHIFT 0x3 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ID__SHIFT 0x4 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_EN__SHIFT 0xa +#define DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL__SHIFT 0xb +#define DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL__SHIFT 0xc +#define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID__SHIFT 0xd +#define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL__SHIFT 0x10 +#define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT__SHIFT 0x18 +#define DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK__SHIFT 0x19 +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX__SHIFT 0x1a +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC__SHIFT 0x1b +#define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT_MASK 0x00000001L +#define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT_MASK 0x00000002L +#define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT_MASK 0x00000004L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL_MASK 0x00000008L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ID_MASK 0x000003F0L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_EN_MASK 0x00000400L +#define DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL_MASK 0x00000800L +#define DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL_MASK 0x00001000L +#define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID_MASK 0x00006000L +#define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL_MASK 0x00FF0000L +#define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT_MASK 0x01000000L +#define DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK_MASK 0x02000000L +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX_MASK 0x04000000L +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC_MASK 0x08000000L +//DB_EXCEPTION_CONTROL +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT 0x3 +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4 +#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8 +#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT 0x18 +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK 0x00000008L +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L +#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L +#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK 0x7F000000L +//DB_DEBUG7 +#define DB_DEBUG7__SPARE_BITS__SHIFT 0x0 +#define DB_DEBUG7__SPARE_BITS_MASK 0xFFFFFFFFL +//DB_DEBUG5 +#define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD__SHIFT 0x0 +#define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION__SHIFT 0x1 +#define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT__SHIFT 0x2 +#define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT__SHIFT 0x3 +#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT 0x4 +#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT 0x5 +#define DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX__SHIFT 0x6 +#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT 0x7 +#define DB_DEBUG5__DISABLE_VRS_1X2_2XAA__SHIFT 0x8 +#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT 0x9 +#define DB_DEBUG5__DISABLE_HTILE_HARVESTING__SHIFT 0xa +#define DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK__SHIFT 0xb +#define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH__SHIFT 0xc +#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT 0xd +#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT 0xe +#define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK__SHIFT 0xf +#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT 0x10 +#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT 0x11 +#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT 0x12 +#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT 0x13 +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT 0x14 +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT 0x15 +#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT 0x16 +#define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE__SHIFT 0x17 +#define DB_DEBUG5__SPARE_BITS__SHIFT 0x18 +#define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD_MASK 0x00000001L +#define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION_MASK 0x00000002L +#define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT_MASK 0x00000004L +#define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT_MASK 0x00000008L +#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK 0x00000010L +#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK 0x00000020L +#define DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX_MASK 0x00000040L +#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK 0x00000080L +#define DB_DEBUG5__DISABLE_VRS_1X2_2XAA_MASK 0x00000100L +#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK 0x00000200L +#define DB_DEBUG5__DISABLE_HTILE_HARVESTING_MASK 0x00000400L +#define DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK_MASK 0x00000800L +#define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH_MASK 0x00001000L +#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK 0x00002000L +#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK 0x00004000L +#define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK_MASK 0x00008000L +#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK 0x00010000L +#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK 0x00020000L +#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK 0x00040000L +#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK 0x00080000L +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK 0x00100000L +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK 0x00200000L +#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK 0x00400000L +#define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE_MASK 0x00800000L +#define DB_DEBUG5__SPARE_BITS_MASK 0xFF000000L +//DB_FGCG_SRAMS_CLK_CTRL +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT 0x15 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT 0x19 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27__SHIFT 0x1b +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28__SHIFT 0x1c +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29__SHIFT 0x1d +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30__SHIFT 0x1e +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31__SHIFT 0x1f +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK 0x00200000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK 0x02000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27_MASK 0x08000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28_MASK 0x10000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29_MASK 0x20000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30_MASK 0x40000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31_MASK 0x80000000L +//DB_FGCG_INTERFACES_CLK_CTRL +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE__SHIFT 0x2 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT 0x3 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT 0x4 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT 0x5 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE__SHIFT 0x7 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE__SHIFT 0x8 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE_MASK 0x00000004L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK 0x00000008L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK 0x00000010L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK 0x00000020L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE_MASK 0x00000080L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE_MASK 0x00000100L +//DB_FIFO_DEPTH4 +#define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH__SHIFT 0x18 +#define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH_MASK 0x00FF0000L +#define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH_MASK 0xFF000000L +//CC_RB_REDUNDANCY +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//CC_RB_BACKEND_DISABLE +#define CC_RB_BACKEND_DISABLE__RESERVED__SHIFT 0x2 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 +#define CC_RB_BACKEND_DISABLE__RESERVED_MASK 0x0000000CL +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xFFFFFFF0L +//GB_ADDR_CONFIG +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +//GB_BACKEND_MAP +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL +//GB_GPU_ID +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL +//CC_RB_DAISY_CHAIN +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L +//GB_ADDR_CONFIG_READ +#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//CB_HW_CONTROL_4 +#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2__SHIFT 0x0 +#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM__SHIFT 0x3 +#define CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE__SHIFT 0x5 +#define CB_HW_CONTROL_4__SPARE_10__SHIFT 0x6 +#define CB_HW_CONTROL_4__SPARE_11__SHIFT 0x7 +#define CB_HW_CONTROL_4__SPARE_12__SHIFT 0x8 +#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT 0x9 +#define CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD__SHIFT 0xa +#define CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD__SHIFT 0xd +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD__SHIFT 0x10 +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD__SHIFT 0x11 +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD__SHIFT 0x12 +#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2_MASK 0x00000007L +#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM_MASK 0x00000018L +#define CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE_MASK 0x00000020L +#define CB_HW_CONTROL_4__SPARE_10_MASK 0x00000040L +#define CB_HW_CONTROL_4__SPARE_11_MASK 0x00000080L +#define CB_HW_CONTROL_4__SPARE_12_MASK 0x00000100L +#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK 0x00000200L +#define CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD_MASK 0x00001C00L +#define CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD_MASK 0x0000E000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD_MASK 0x00010000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD_MASK 0x00020000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD_MASK 0x00040000L +//CB_HW_CONTROL_3 +#define CB_HW_CONTROL_3__SPARE_5__SHIFT 0x0 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 +#define CB_HW_CONTROL_3__SPARE_6__SHIFT 0x2 +#define CB_HW_CONTROL_3__SPARE_7__SHIFT 0x3 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x4 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x5 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x6 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0x7 +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xb +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0xc +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0xd +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0xe +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0xf +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x10 +#define CB_HW_CONTROL_3__SPARE_8__SHIFT 0x11 +#define CB_HW_CONTROL_3__SPARE_9__SHIFT 0x12 +#define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT__SHIFT 0x14 +#define CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x15 +#define CB_HW_CONTROL_3__SPARE_5_MASK 0x00000001L +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L +#define CB_HW_CONTROL_3__SPARE_6_MASK 0x00000004L +#define CB_HW_CONTROL_3__SPARE_7_MASK 0x00000008L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000010L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000020L +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000040L +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000080L +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00000800L +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00001000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00002000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00004000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00008000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00010000L +#define CB_HW_CONTROL_3__SPARE_8_MASK 0x00020000L +#define CB_HW_CONTROL_3__SPARE_9_MASK 0x00040000L +#define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT_MASK 0x00100000L +#define CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00200000L +//CB_HW_CONTROL +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x0 +#define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT 0x1 +#define CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX__SHIFT 0x2 +#define CB_HW_CONTROL__RMI_CREDITS__SHIFT 0x6 +#define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES__SHIFT 0xc +#define CB_HW_CONTROL__FORCE_FEA_HIGH__SHIFT 0xf +#define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID__SHIFT 0x10 +#define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING__SHIFT 0x11 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__SPARE_2__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__SPARE_3__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00000001L +#define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK 0x00000002L +#define CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX_MASK 0x00000004L +#define CB_HW_CONTROL__RMI_CREDITS_MASK 0x00000FC0L +#define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES_MASK 0x00007000L +#define CB_HW_CONTROL__FORCE_FEA_HIGH_MASK 0x00008000L +#define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID_MASK 0x00010000L +#define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING_MASK 0x00020000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__SPARE_2_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__SPARE_3_MASK 0x20000000L +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L +//CB_HW_CONTROL_1 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0000003FL +//CB_HW_CONTROL_2 +#define CB_HW_CONTROL_2__SPARE_4__SHIFT 0x0 +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x8 +#define CB_HW_CONTROL_2__SPARE__SHIFT 0xe +#define CB_HW_CONTROL_2__SPARE_4_MASK 0x000000FFL +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x00003F00L +#define CB_HW_CONTROL_2__SPARE_MASK 0xFFFFC000L +//CB_DCC_CONFIG +#define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH__SHIFT 0x0 +#define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x5 +#define CB_DCC_CONFIG__SPARE_13__SHIFT 0x6 +#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 +#define CB_DCC_CONFIG__SPARE_14__SHIFT 0x8 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x19 +#define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH_MASK 0x0000001FL +#define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000020L +#define CB_DCC_CONFIG__SPARE_13_MASK 0x00000040L +#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L +#define CB_DCC_CONFIG__SPARE_14_MASK 0x0000FF00L +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x01FF0000L +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xFE000000L +//CB_HW_MEM_ARBITER_RD +#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0xe +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x13 +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x19 +#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00040000L +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x00380000L +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x01C00000L +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x02000000L +//CB_HW_MEM_ARBITER_WR +#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0xe +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x13 +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x19 +#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00040000L +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x00380000L +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x01C00000L +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x02000000L +//CB_FGCG_SRAM_OVERRIDE +#define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG__SHIFT 0x0 +#define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG_MASK 0x000FFFFFL +//CB_DCC_CONFIG2 +//CHICKEN_BITS +#define CHICKEN_BITS__SPARE__SHIFT 0x0 +#define CHICKEN_BITS__SPARE_MASK 0xFFFFFFFFL +//CB_CACHE_EVICT_POINTS +#define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT__SHIFT 0x0 +#define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT__SHIFT 0x8 +#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT 0x10 +#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT_MASK 0x000000FFL +#define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT_MASK 0x0000FF00L +#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK 0x00FF0000L +#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L + + +// addressBlock: gc_gceadec +//GCEA_DRAM_RD_CLI2GRP_MAP0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_CLI2GRP_MAP1 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP1 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_GRP2VC_MAP +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_WR_GRP2VC_MAP +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_RD_LAZY +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//GCEA_DRAM_WR_LAZY +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//GCEA_DRAM_RD_CAM_CNTL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//GCEA_DRAM_WR_CAM_CNTL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//GCEA_DRAM_PAGE_BURST +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_AGE +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_WR_PRI_AGE +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_RD_PRI_QUEUING +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_QUEUING +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_FIXED +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_FIXED +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_URGENCY +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_WR_PRI_URGENCY +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_RD_PRI_QUANT_PRI1 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI2 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI3 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI1 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI2 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI3 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_CLI2GRP_MAP0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_CLI2GRP_MAP1 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP1 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_COMBINE_FLUSH +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//GCEA_IO_WR_COMBINE_FLUSH +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//GCEA_IO_GROUP_BURST +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_IO_RD_PRI_AGE +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_WR_PRI_AGE +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_RD_PRI_QUEUING +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_QUEUING +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_FIXED +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_FIXED +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_URGENCY +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_WR_PRI_URGENCY +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_RD_PRI_URGENCY_MASKING +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//GCEA_IO_WR_PRI_URGENCY_MASKING +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//GCEA_IO_RD_PRI_QUANT_PRI1 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI2 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI3 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI1 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI2 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI3 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_SDP_ARB_FINAL +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c +#define GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d +#define GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e +#define GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +#define GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L +#define GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L +#define GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L +#define GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L +//GCEA_SDP_IO_PRIORITY +#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//GCEA_SDP_CREDITS +#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 +#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L +//GCEA_SDP_TAG_RESERVE0 +#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//GCEA_SDP_TAG_RESERVE1 +#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//GCEA_SDP_VCC_RESERVE0 +#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GCEA_SDP_VCC_RESERVE1 +#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L + + +// addressBlock: gc_gceadec2 +//GCEA_MISC +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//GCEA_LATENCY_SAMPLING +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//GCEA_MAM_CTRL2 +#define GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE__SHIFT 0x0 +#define GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY__SHIFT 0x1 +#define GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY__SHIFT 0x2 +#define GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT__SHIFT 0x3 +#define GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT__SHIFT 0x6 +#define GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE__SHIFT 0x9 +#define GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE__SHIFT 0xf +#define GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP__SHIFT 0x12 +#define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE__SHIFT 0x13 +#define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE__SHIFT 0x14 +#define GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER__SHIFT 0x15 +#define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE__SHIFT 0x16 +#define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE__SHIFT 0x17 +#define GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT 0x18 +#define GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE_MASK 0x00000001L +#define GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY_MASK 0x00000002L +#define GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY_MASK 0x00000004L +#define GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT_MASK 0x00000038L +#define GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT_MASK 0x000001C0L +#define GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE_MASK 0x00007E00L +#define GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE_MASK 0x00038000L +#define GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP_MASK 0x00040000L +#define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE_MASK 0x00080000L +#define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE_MASK 0x00100000L +#define GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER_MASK 0x00200000L +#define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE_MASK 0x00400000L +#define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE_MASK 0x00800000L +#define GCEA_MAM_CTRL2__RESERVED_FIELD_MASK 0xFF000000L +//GCEA_MAM_CTRL +#define GCEA_MAM_CTRL__MAM_DISABLE__SHIFT 0x0 +#define GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE__SHIFT 0x1 +#define GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE__SHIFT 0x2 +#define GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN__SHIFT 0x3 +#define GCEA_MAM_CTRL__SDMA_UPDT_ARAM__SHIFT 0x4 +#define GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC__SHIFT 0x5 +#define GCEA_MAM_CTRL__FLUSH_TRACKER__SHIFT 0x6 +#define GCEA_MAM_CTRL__CLEAR_TRACKER__SHIFT 0x7 +#define GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT 0x8 +#define GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER__SHIFT 0xc +#define GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT__SHIFT 0xd +#define GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER__SHIFT 0xe +#define GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT__SHIFT 0xf +#define GCEA_MAM_CTRL__RESERVED_FIELD__SHIFT 0x10 +#define GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES__SHIFT 0x17 +#define GCEA_MAM_CTRL__ARAM_RB_ADDR_HI__SHIFT 0x1c +#define GCEA_MAM_CTRL__MAM_DISABLE_MASK 0x00000001L +#define GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE_MASK 0x00000002L +#define GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE_MASK 0x00000004L +#define GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN_MASK 0x00000008L +#define GCEA_MAM_CTRL__SDMA_UPDT_ARAM_MASK 0x00000010L +#define GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC_MASK 0x00000020L +#define GCEA_MAM_CTRL__FLUSH_TRACKER_MASK 0x00000040L +#define GCEA_MAM_CTRL__CLEAR_TRACKER_MASK 0x00000080L +#define GCEA_MAM_CTRL__SDP_PRIORITY_MASK 0x00000F00L +#define GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER_MASK 0x00001000L +#define GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT_MASK 0x00002000L +#define GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER_MASK 0x00004000L +#define GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT_MASK 0x00008000L +#define GCEA_MAM_CTRL__RESERVED_FIELD_MASK 0x007F0000L +#define GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES_MASK 0x0F800000L +#define GCEA_MAM_CTRL__ARAM_RB_ADDR_HI_MASK 0xF0000000L +//GCEA_EDC_CNT +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//GCEA_EDC_CNT2 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//GCEA_DSM_CNTL +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//GCEA_DSM_CNTLA +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//GCEA_DSM_CNTLB +//GCEA_DSM_CNTL2 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//GCEA_DSM_CNTL2A +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//GCEA_DSM_CNTL2B +//GCEA_GL2C_XBR_CREDITS +#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 +#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 +#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 +#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe +#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 +#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 +#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 +#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e +#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL +#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L +#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L +#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L +#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L +#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L +#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L +#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L +//GCEA_GL2C_XBR_MAXBURST +#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 +#define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT 0x4 +#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 +#define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT 0xc +#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT 0x10 +#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT 0x13 +#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT 0x14 +#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT 0x17 +#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL +#define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK 0x000000F0L +#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L +#define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK 0x0000F000L +#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK 0x00070000L +#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK 0x00080000L +#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK 0x00700000L +#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK 0x00800000L +//GCEA_PROBE_CNTL +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L +//GCEA_PROBE_MAP +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT 0x0 +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT 0x1 +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT 0x2 +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT 0x3 +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT 0x4 +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT 0x5 +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT 0x6 +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT 0x7 +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT 0x8 +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT 0x9 +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT 0xb +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT 0xc +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT 0xd +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT 0xe +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT 0xf +#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK 0x00000001L +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK 0x00000002L +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK 0x00000004L +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK 0x00000008L +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK 0x00000010L +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK 0x00000020L +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK 0x00000040L +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK 0x00000080L +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK 0x00000100L +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK 0x00000200L +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK 0x00000400L +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK 0x00000800L +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK 0x00001000L +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK 0x00002000L +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK 0x00004000L +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK 0x00008000L +#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L +//GCEA_ERR_STATUS +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +//GCEA_MISC2 +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define GCEA_MISC2__BLOCK_REQUESTS__SHIFT 0xd +#define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT 0xe +#define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT 0xf +#define GCEA_MISC2__LINKMGR_CRBUSY_MASK__SHIFT 0x10 +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define GCEA_MISC2__BLOCK_REQUESTS_MASK 0x00002000L +#define GCEA_MISC2__REQUESTS_BLOCKED_MASK 0x00004000L +#define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK 0x00008000L +#define GCEA_MISC2__LINKMGR_CRBUSY_MASK_MASK 0x00010000L + + +// addressBlock: gc_gceadec3 +//GCEA_RRET_MEM_RESERVE +#define GCEA_RRET_MEM_RESERVE__VC0__SHIFT 0x0 +#define GCEA_RRET_MEM_RESERVE__VC1__SHIFT 0x4 +#define GCEA_RRET_MEM_RESERVE__VC2__SHIFT 0x8 +#define GCEA_RRET_MEM_RESERVE__VC3__SHIFT 0xc +#define GCEA_RRET_MEM_RESERVE__VC4__SHIFT 0x10 +#define GCEA_RRET_MEM_RESERVE__VC5__SHIFT 0x14 +#define GCEA_RRET_MEM_RESERVE__VC6__SHIFT 0x18 +#define GCEA_RRET_MEM_RESERVE__VC7__SHIFT 0x1c +#define GCEA_RRET_MEM_RESERVE__VC0_MASK 0x0000000FL +#define GCEA_RRET_MEM_RESERVE__VC1_MASK 0x000000F0L +#define GCEA_RRET_MEM_RESERVE__VC2_MASK 0x00000F00L +#define GCEA_RRET_MEM_RESERVE__VC3_MASK 0x0000F000L +#define GCEA_RRET_MEM_RESERVE__VC4_MASK 0x000F0000L +#define GCEA_RRET_MEM_RESERVE__VC5_MASK 0x00F00000L +#define GCEA_RRET_MEM_RESERVE__VC6_MASK 0x0F000000L +#define GCEA_RRET_MEM_RESERVE__VC7_MASK 0xF0000000L +//GCEA_EDC_CNT3 +#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT 0x1e +#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT_MASK 0x30000000L +#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK 0xC0000000L +//GCEA_SDP_ENABLE +#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST__SHIFT 0x1 +#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L +#define GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST_MASK 0x00000002L + + +// addressBlock: gc_spipdec2 +//SPI_PQEV_CTRL +#define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0 +#define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa +#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10 +#define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL +#define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L +#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L +//SPI_EXP_THROTTLE_CTRL +#define SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT 0x0 +#define SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT 0x1 +#define SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT 0x5 +#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT 0x9 +#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT 0xd +#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT 0x10 +#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT 0x13 +#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT 0x1a +#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT 0x1d +#define SPI_EXP_THROTTLE_CTRL__ENABLE_MASK 0x00000001L +#define SPI_EXP_THROTTLE_CTRL__PERIOD_MASK 0x0000001EL +#define SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK 0x000001E0L +#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK 0x00001E00L +#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK 0x0000E000L +#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK 0x00070000L +#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK 0x03F80000L +#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK 0x1C000000L +#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK 0x20000000L + + +// addressBlock: gc_rmi_rmidec +//RMI_GENERAL_CNTL +#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 +#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L +//RMI_GENERAL_CNTL1 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb +#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe +#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf +#define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS__SHIFT 0x10 +#define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS__SHIFT 0x16 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L +#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L +#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L +#define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS_MASK 0x003F0000L +#define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS_MASK 0x0FC00000L +//RMI_GENERAL_STATUS +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 +#define RMI_GENERAL_STATUS__RESERVED_BIT_6__SHIFT 0x6 +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf +#define RMI_GENERAL_STATUS__RESERVED_BIT_18__SHIFT 0x12 +#define RMI_GENERAL_STATUS__RESERVED_BIT_19__SHIFT 0x13 +#define RMI_GENERAL_STATUS__RESERVED_BIT_20__SHIFT 0x14 +#define RMI_GENERAL_STATUS__RESERVED_BITS_28_21__SHIFT 0x15 +#define RMI_GENERAL_STATUS__RESERVED_BIT_29__SHIFT 0x1d +#define RMI_GENERAL_STATUS__RESERVED_BIT_30__SHIFT 0x1e +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L +#define RMI_GENERAL_STATUS__RESERVED_BIT_6_MASK 0x00000040L +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_18_MASK 0x00040000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_19_MASK 0x00080000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_20_MASK 0x00100000L +#define RMI_GENERAL_STATUS__RESERVED_BITS_28_21_MASK 0x1FE00000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_29_MASK 0x20000000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_30_MASK 0x40000000L +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L +//RMI_SUBBLOCK_STATUS0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L +//RMI_SUBBLOCK_STATUS1 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L +//RMI_SUBBLOCK_STATUS2 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L +//RMI_SUBBLOCK_STATUS3 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L +//RMI_XBAR_CONFIG +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L +#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L +//RMI_PROBE_POP_LOGIC_CNTL +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L +//RMI_UTC_XNACK_N_MISC_CNTL +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L +//RMI_DEMUX_CNTL +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L +//RMI_UTCL1_CNTL1 +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//RMI_UTCL1_CNTL2 +#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b +#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c +#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d +#define RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define RMI_UTCL1_CNTL2__RESERVED__SHIFT 0x1f +#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L +#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L +#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L +#define RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define RMI_UTCL1_CNTL2__RESERVED_MASK 0x80000000L +//RMI_UTC_UNIT_CONFIG +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0 +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL +//RMI_TCIW_FORMATTER0_CNTL +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L +//RMI_TCIW_FORMATTER1_CNTL +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L +//RMI_SCOREBOARD_CNTL +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L +//RMI_SCOREBOARD_STATUS0 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 +#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L +#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L +//RMI_SCOREBOARD_STATUS1 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L +//RMI_SCOREBOARD_STATUS2 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L +//RMI_XBAR_ARBITER_CONFIG +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L +//RMI_XBAR_ARBITER_CONFIG_1 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L +//RMI_CLOCK_CNTRL +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L +//RMI_UTCL1_STATUS +#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//RMI_RB_GLX_CID_MAP +#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0 +#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4 +#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8 +#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc +#define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10 +#define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14 +#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18 +#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c +#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL +#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L +#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L +#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L +#define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L +#define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L +#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L +#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L +//RMI_SPARE +#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1 +#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2 +#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3 +#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4 +#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5 +#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT 0x6 +#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8 +#define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9 +#define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa +#define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb +#define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc +#define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd +#define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe +#define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf +#define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10 +#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L +#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L +#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L +#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L +#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L +#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK 0x00000040L +#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L +#define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L +#define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L +#define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L +#define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L +#define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L +#define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L +#define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L +#define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L +//RMI_SPARE_1 +#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT 0x0 +#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 +#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 +#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 +#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 +#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 +#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 +#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 +#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8 +#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 +#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK 0x00000001L +#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L +#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L +#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L +#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L +#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L +#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L +#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L +#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L +#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L +//RMI_SPARE_2 +#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT 0x0 +#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 +#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 +#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK 0x0000FFFFL +#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L +#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L +//CC_RMI_REDUNDANCY +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 +#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 +#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L +#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L +#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L + + +// addressBlock: gc_pmmdec +//GCR_PIO_CNTL +#define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0 +#define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x2 +#define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x3 +#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10 +#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e +#define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f +#define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000003L +#define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000004L +#define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000008L +#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L +#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L +#define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L +//GCR_PIO_DATA +#define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0 +#define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL +//PMM_CNTL +#define PMM_CNTL__PMM_DISABLE__SHIFT 0x0 +#define PMM_CNTL__ABIT_FORCE_FLUSH__SHIFT 0x1 +#define PMM_CNTL__ABIT_TIMER_THRESHOLD__SHIFT 0x2 +#define PMM_CNTL__ABIT_TIMER_DISABLE__SHIFT 0x6 +#define PMM_CNTL__ABIT_TIMER_RESET__SHIFT 0x7 +#define PMM_CNTL__INTERRUPT_PRIORITY__SHIFT 0x8 +#define PMM_CNTL__PMM_INTERRUPTS_DISABLE__SHIFT 0xa +#define PMM_CNTL__RESERVED__SHIFT 0xb +#define PMM_CNTL__PMM_DISABLE_MASK 0x00000001L +#define PMM_CNTL__ABIT_FORCE_FLUSH_MASK 0x00000002L +#define PMM_CNTL__ABIT_TIMER_THRESHOLD_MASK 0x0000003CL +#define PMM_CNTL__ABIT_TIMER_DISABLE_MASK 0x00000040L +#define PMM_CNTL__ABIT_TIMER_RESET_MASK 0x00000080L +#define PMM_CNTL__INTERRUPT_PRIORITY_MASK 0x00000300L +#define PMM_CNTL__PMM_INTERRUPTS_DISABLE_MASK 0x00000400L +#define PMM_CNTL__RESERVED_MASK 0xFFFFF800L +//PMM_STATUS +#define PMM_STATUS__PMM_IDLE__SHIFT 0x0 +#define PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS__SHIFT 0x1 +#define PMM_STATUS__ABIT_FORCE_FLUSH_DONE__SHIFT 0x2 +#define PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS__SHIFT 0x3 +#define PMM_STATUS__ABIT_TIMER_FLUSH_DONE__SHIFT 0x4 +#define PMM_STATUS__ABIT_TIMER_RUNNING__SHIFT 0x5 +#define PMM_STATUS__PMM_INTERRUPTS_PENDING__SHIFT 0x6 +#define PMM_STATUS__ABIT_FLUSH_ERROR__SHIFT 0x7 +#define PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS__SHIFT 0x8 +#define PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS__SHIFT 0x9 +#define PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS__SHIFT 0xa +#define PMM_STATUS__RESERVED__SHIFT 0xb +#define PMM_STATUS__PMM_IDLE_MASK 0x00000001L +#define PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS_MASK 0x00000002L +#define PMM_STATUS__ABIT_FORCE_FLUSH_DONE_MASK 0x00000004L +#define PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS_MASK 0x00000008L +#define PMM_STATUS__ABIT_TIMER_FLUSH_DONE_MASK 0x00000010L +#define PMM_STATUS__ABIT_TIMER_RUNNING_MASK 0x00000020L +#define PMM_STATUS__PMM_INTERRUPTS_PENDING_MASK 0x00000040L +#define PMM_STATUS__ABIT_FLUSH_ERROR_MASK 0x00000080L +#define PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS_MASK 0x00000100L +#define PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS_MASK 0x00000200L +#define PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS_MASK 0x00000400L +#define PMM_STATUS__RESERVED_MASK 0xFFFFF800L + + +// addressBlock: gc_utcl1dec +//UTCL1_CTRL_1 +#define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x0 +#define UTCL1_CTRL_1__UTCL1_TCP_BYPASS__SHIFT 0x1 +#define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS__SHIFT 0x2 +#define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS__SHIFT 0x3 +#define UTCL1_CTRL_1__UTCL1_RMI_BYPASS__SHIFT 0x4 +#define UTCL1_CTRL_1__UTCL1_SQG_BYPASS__SHIFT 0x5 +#define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x6 +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL__SHIFT 0x7 +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0x8 +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1__SHIFT 0x9 +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2__SHIFT 0xb +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3__SHIFT 0xd +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4__SHIFT 0xf +#define UTCL1_CTRL_1__RESERVED__SHIFT 0x11 +#define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000001L +#define UTCL1_CTRL_1__UTCL1_TCP_BYPASS_MASK 0x00000002L +#define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS_MASK 0x00000004L +#define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS_MASK 0x00000008L +#define UTCL1_CTRL_1__UTCL1_RMI_BYPASS_MASK 0x00000010L +#define UTCL1_CTRL_1__UTCL1_SQG_BYPASS_MASK 0x00000020L +#define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000040L +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_MASK 0x00000080L +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000100L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1_MASK 0x00000600L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2_MASK 0x00001800L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3_MASK 0x00006000L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4_MASK 0x00018000L +#define UTCL1_CTRL_1__RESERVED_MASK 0xFFFE0000L +//UTCL1_ALOG +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3 +#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4 +#define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5 +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6 +#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9 +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa +#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc +#define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf +#define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10 +#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L +#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L +#define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L +#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L +#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L +#define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L +#define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L +#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L +//UTCL1_STATUS +#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT 0x0 +#define UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT 0x1 +#define UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT 0x2 +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT 0x3 +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT 0x4 +#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT 0x5 +#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT 0x7 +#define UTCL1_STATUS__RESERVED__SHIFT 0x8 +#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK 0x00000001L +#define UTCL1_STATUS__UTCL1_MH_BUSY_MASK 0x00000002L +#define UTCL1_STATUS__UTCL1_INV_BUSY_MASK 0x00000004L +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK 0x00000008L +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK 0x00000010L +#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK 0x00000060L +#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK 0x00000080L +#define UTCL1_STATUS__RESERVED_MASK 0x00000100L + + +// addressBlock: gc_gcvmsharedpfdec +//GCMC_VM_NB_TOP_OF_DRAM_SLOT1 +#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//GCMC_VM_NB_LOWER_TOP_OF_DRAM2 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//GCMC_VM_NB_UPPER_TOP_OF_DRAM2 +#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL +//GCMC_VM_FB_OFFSET +#define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//GCMC_VM_STEERING +#define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//GCMC_MEM_POWER_LS +#define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define GCMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define GCMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//GCMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//GCMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//GCMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//GCMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//GCMC_VM_APT_CNTL +#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +//GCMC_VM_LOCAL_FB_ADDRESS_START +#define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_END +#define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL +#define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//GCUTCL2_ICG_CTRL +#define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GCUTCL2_CGTT_BUSY_CTRL +#define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//GCMC_VM_FB_NOALLOC_CNTL +#define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 +#define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 +#define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH__SHIFT 0x2 +#define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT 0x3 +#define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT 0x4 +#define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT 0x5 +#define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L +#define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L +#define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH_MASK 0x00000004L +#define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK 0x00000008L +#define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK 0x00000010L +#define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK 0x00000020L +//GCUTCL2_HARVEST_BYPASS_GROUPS +#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL +//GCUTCL2_GROUP_RET_FAULT_STATUS +#define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: gc_gcvml2pfdec +//GCVM_L2_CNTL +#define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//GCVM_L2_CNTL2 +#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//GCVM_L2_CNTL3 +#define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//GCVM_L2_STATUS +#define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//GCVM_DUMMY_PAGE_FAULT_CNTL +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//GCVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//GCVM_INVALIDATE_CNTL +#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//GCVM_L2_PROTECTION_FAULT_CNTL +#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//GCVM_L2_PROTECTION_FAULT_CNTL2 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//GCVM_L2_PROTECTION_FAULT_MM_CNTL3 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_MM_CNTL4 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_STATUS +#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define GCVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d +#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +#define GCVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L +//GCVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//GCVM_L2_CNTL4 +#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//GCVM_L2_MM_GROUP_RT_CLASSES +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//GCVM_L2_BANK_SELECT_RESERVED_CID +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//GCVM_L2_BANK_SELECT_RESERVED_CID2 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//GCVM_L2_CACHE_PARITY_CNTL +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//GCVM_L2_ICG_CTRL +#define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GCVM_L2_CNTL5 +#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf +#define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x10 +#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L +#define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00010000L +//GCVM_L2_GCR_CNTL +#define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//GCVML2_WALKER_MACRO_THROTTLE_TIME +#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 +#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL +//GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT +#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 +#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL +//GCVML2_WALKER_MICRO_THROTTLE_TIME +#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 +#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL +//GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT +#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 +#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL +//GCVM_L2_CGTT_BUSY_CTRL +#define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//GCVM_L2_PTE_CACHE_DUMP_CNTL +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//GCVM_L2_PTE_CACHE_DUMP_READ +#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L +//GCVM_L2_BANK_SELECT_MASKS +#define GCVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define GCVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define GCVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define GCVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define GCVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define GCVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define GCVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L + + +// addressBlock: gc_gcvmsharedvcdec +//GCMC_VM_FB_LOCATION_BASE +#define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//GCMC_VM_FB_LOCATION_TOP +#define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//GCMC_VM_AGP_TOP +#define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define GCMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//GCMC_VM_AGP_BOT +#define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define GCMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//GCMC_VM_AGP_BASE +#define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define GCMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//GCMC_VM_MX_L1_TLB_CNTL +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L + + +// addressBlock: gc_gcvml2vcdec +//GCVM_CONTEXT0_CNTL +#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT1_CNTL +#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT2_CNTL +#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT3_CNTL +#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT4_CNTL +#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT5_CNTL +#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT6_CNTL +#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT7_CNTL +#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT8_CNTL +#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT9_CNTL +#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT10_CNTL +#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT11_CNTL +#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT12_CNTL +#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT13_CNTL +#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT14_CNTL +#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXT15_CNTL +#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//GCVM_CONTEXTS_DISABLE +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//GCVM_INVALIDATE_ENG0_SEM +#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG1_SEM +#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG2_SEM +#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG3_SEM +#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG4_SEM +#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG5_SEM +#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG6_SEM +#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG7_SEM +#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG8_SEM +#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG9_SEM +#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG10_SEM +#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG11_SEM +#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG12_SEM +#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG13_SEM +#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG14_SEM +#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG15_SEM +#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG16_SEM +#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG17_SEM +#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG0_REQ +#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG1_REQ +#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG2_REQ +#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG3_REQ +#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG4_REQ +#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG5_REQ +#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG6_REQ +#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG7_REQ +#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG8_REQ +#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG9_REQ +#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG10_REQ +#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG11_REQ +#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG12_REQ +#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG13_REQ +#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG14_REQ +#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG15_REQ +#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG16_REQ +#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG17_REQ +#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//GCVM_INVALIDATE_ENG0_ACK +#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG1_ACK +#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG2_ACK +#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG3_ACK +#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG4_ACK +#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG5_ACK +#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG6_ACK +#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG7_ACK +#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG8_ACK +#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG9_ACK +#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG10_ACK +#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG11_ACK +#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG12_ACK +#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG13_ACK +#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG14_ACK +#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG15_ACK +#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG16_ACK +#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG17_ACK +#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: gc_gcvml2perfddec +//GCVML2_PERFCOUNTER2_0_LO +#define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCVML2_PERFCOUNTER2_1_LO +#define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCVML2_PERFCOUNTER2_0_HI +#define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCVML2_PERFCOUNTER2_1_HI +#define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: gc_gcvml2prdec +//GCMC_VM_L2_PERFCOUNTER_LO +#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCMC_VM_L2_PERFCOUNTER_HI +#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//GCUTCL2_PERFCOUNTER_LO +#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCUTCL2_PERFCOUNTER_HI +#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: gc_gcvml2perfsdec +//GCVML2_PERFCOUNTER2_0_SELECT +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT 0xa +#define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT 0x1c +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK 0xF0000000L +//GCVML2_PERFCOUNTER2_1_SELECT +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT 0xa +#define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT 0x1c +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK 0xF0000000L +//GCVML2_PERFCOUNTER2_0_SELECT1 +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GCVML2_PERFCOUNTER2_1_SELECT1 +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GCVML2_PERFCOUNTER2_0_MODE +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT 0x2 +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT 0x4 +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT 0x6 +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT 0x8 +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT 0xc +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT 0x10 +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT 0x14 +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK 0x00000003L +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK 0x0000000CL +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK 0x00000030L +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK 0x000000C0L +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK 0x00000F00L +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK 0x0000F000L +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK 0x000F0000L +#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK 0x00F00000L +//GCVML2_PERFCOUNTER2_1_MODE +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT 0x0 +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT 0x2 +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT 0x4 +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT 0x6 +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT 0x8 +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT 0xc +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT 0x10 +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT 0x14 +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK 0x00000003L +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK 0x0000000CL +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK 0x00000030L +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK 0x000000C0L +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK 0x00000F00L +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK 0x0000F000L +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK 0x000F0000L +#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK 0x00F00000L + + +// addressBlock: gc_gcvml2pldec +//GCMC_VM_L2_PERFCOUNTER0_CFG +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER1_CFG +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER2_CFG +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER3_CFG +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER4_CFG +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER5_CFG +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER6_CFG +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER7_CFG +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//GCUTCL2_PERFCOUNTER0_CFG +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER1_CFG +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER2_CFG +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER3_CFG +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER_RSLT_CNTL +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_gcvmsharedhvdec +//GCMC_VM_FB_SIZE_OFFSET_VF0 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF1 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF2 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF3 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF4 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF5 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF6 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF7 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF8 +#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF9 +#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF10 +#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF11 +#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF12 +#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF13 +#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF14 +#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF15 +#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L + + +// addressBlock: gc_gcvml2pspdec +//GCUTCL2_TRANSLATION_BYPASS_BY_VMID +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L +//GCMC_VM_MARC_BASE_LO_0 +#define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_1 +#define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_2 +#define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_3 +#define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_4 +#define GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_5 +#define GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_6 +#define GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_7 +#define GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_8 +#define GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_9 +#define GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_10 +#define GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_11 +#define GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_12 +#define GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_13 +#define GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_14 +#define GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_LO_15 +#define GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15__SHIFT 0xc +#define GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15_MASK 0xFFFFF000L +//GCMC_VM_MARC_BASE_HI_0 +#define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_1 +#define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_2 +#define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_3 +#define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_4 +#define GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_5 +#define GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_6 +#define GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_7 +#define GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_8 +#define GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_9 +#define GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_10 +#define GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_11 +#define GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_12 +#define GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_13 +#define GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_14 +#define GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14_MASK 0x000FFFFFL +//GCMC_VM_MARC_BASE_HI_15 +#define GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15__SHIFT 0x0 +#define GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_LO_0 +#define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_1 +#define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_2 +#define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_3 +#define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_4 +#define GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_5 +#define GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_6 +#define GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_7 +#define GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_8 +#define GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_9 +#define GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_10 +#define GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_11 +#define GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_12 +#define GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_13 +#define GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_14 +#define GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_LO_15 +#define GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15__SHIFT 0x1 +#define GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15__SHIFT 0xc +#define GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15_MASK 0x00000001L +#define GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15_MASK 0x00000002L +#define GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15_MASK 0xFFFFF000L +//GCMC_VM_MARC_RELOC_HI_0 +#define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_1 +#define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_2 +#define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_3 +#define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_4 +#define GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_5 +#define GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_6 +#define GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_7 +#define GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_8 +#define GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_9 +#define GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_10 +#define GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_11 +#define GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_12 +#define GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_13 +#define GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_14 +#define GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14_MASK 0x000FFFFFL +//GCMC_VM_MARC_RELOC_HI_15 +#define GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15__SHIFT 0x0 +#define GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_LO_0 +#define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_1 +#define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_2 +#define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_3 +#define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_4 +#define GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_5 +#define GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_6 +#define GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_7 +#define GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_8 +#define GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_9 +#define GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_10 +#define GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_11 +#define GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_12 +#define GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_13 +#define GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_14 +#define GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_LO_15 +#define GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15__SHIFT 0xc +#define GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15_MASK 0xFFFFF000L +//GCMC_VM_MARC_LEN_HI_0 +#define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_1 +#define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_2 +#define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_3 +#define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_4 +#define GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_5 +#define GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_6 +#define GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_7 +#define GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_8 +#define GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_9 +#define GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_10 +#define GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_11 +#define GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_12 +#define GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_13 +#define GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_14 +#define GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14_MASK 0x000FFFFFL +//GCMC_VM_MARC_LEN_HI_15 +#define GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15__SHIFT 0x0 +#define GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15_MASK 0x000FFFFFL +//GCMC_VM_MARC_PFVF_MAPPING_0 +#define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_1 +#define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_2 +#define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_3 +#define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_4 +#define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_5 +#define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_6 +#define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_7 +#define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_8 +#define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_9 +#define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_10 +#define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_11 +#define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_12 +#define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_13 +#define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_14 +#define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF_MASK 0x00010000L +//GCMC_VM_MARC_PFVF_MAPPING_15 +#define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS__SHIFT 0x0 +#define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF__SHIFT 0x10 +#define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS_MASK 0x0000FFFFL +#define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF_MASK 0x00010000L +//GCUTC_TRANSLATION_FAULT_CNTL0 +#define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 +#define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL +//GCUTC_TRANSLATION_FAULT_CNTL1 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L + + +// addressBlock: gc_shdec +//SPI_SHADER_PGM_RSRC4_PS +#define SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START_MASK 0x20000000L +#define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_PGM_CHKSUM_PS +#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC3_PS +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE_MASK 0x00C00000L +//SPI_SHADER_PGM_LO_PS +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_PS +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_PS +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L +//SPI_SHADER_PGM_RSRC2_PS +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_PS_0 +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_1 +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_2 +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_3 +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_4 +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_5 +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_6 +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_7 +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_8 +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_9 +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_10 +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_11 +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_12 +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_13 +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_14 +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_15 +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_16 +#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_17 +#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_18 +#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_19 +#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_20 +#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_21 +#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_22 +#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_23 +#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_24 +#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_25 +#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_26 +#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_27 +#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_28 +#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_29 +#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_30 +#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_31 +#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_REQ_CTRL_PS +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_USER_ACCUM_PS_0 +#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_1 +#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_2 +#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_3 +#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_PGM_CHKSUM_GS +#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_GS +#define SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_GS__RESERVED__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN__SHIFT 0xe +#define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN__SHIFT 0xf +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC4_GS__RESERVED_MASK 0x00003FFEL +#define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN_MASK 0x00004000L +#define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN_MASK 0x00008000L +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x007F0000L +#define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE_MASK 0x1F800000L +#define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START_MASK 0x20000000L +#define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_USER_DATA_ADDR_LO_GS +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_GS +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_ES_GS +#define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_ES_GS +#define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_GS +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xFC000000L +//SPI_SHADER_PGM_LO_GS +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_GS +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC1_GS +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_GS +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_GS_0 +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_1 +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_2 +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_3 +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_4 +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_5 +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_6 +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_7 +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_8 +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_9 +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_10 +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_11 +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_12 +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_13 +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_14 +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_15 +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_16 +#define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_17 +#define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_18 +#define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_19 +#define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_20 +#define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_21 +#define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_22 +#define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_23 +#define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_24 +#define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_25 +#define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_26 +#define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_27 +#define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_28 +#define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_29 +#define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_30 +#define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_31 +#define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_GS_MESHLET_DIM +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y__SHIFT 0x8 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z__SHIFT 0x10 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE__SHIFT 0x18 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X_MASK 0x000000FFL +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y_MASK 0x0000FF00L +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z_MASK 0x00FF0000L +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE_MASK 0xFF000000L +//SPI_SHADER_GS_MESHLET_EXP_ALLOC +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS__SHIFT 0x9 +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS_MASK 0x000001FFL +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS_MASK 0x0003FE00L +//SPI_SHADER_REQ_CTRL_ESGS +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_USER_ACCUM_ESGS_0 +#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_1 +#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_2 +#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_3 +#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_PGM_LO_ES +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_ES +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_CHKSUM_HS +#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_HS +#define SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START_MASK 0x20000000L +#define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_USER_DATA_ADDR_LO_HS +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_HS +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_LS_HS +#define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_LS_HS +#define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_HS +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0x0000FC00L +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L +//SPI_SHADER_PGM_LO_HS +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_HS +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC1_HS +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L +//SPI_SHADER_PGM_RSRC2_HS +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0003FE00L +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x07FC0000L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_HS_0 +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_1 +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_2 +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_3 +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_4 +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_5 +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_6 +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_7 +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_8 +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_9 +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_10 +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_11 +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_12 +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_13 +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_14 +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_15 +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_16 +#define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_17 +#define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_18 +#define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_19 +#define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_20 +#define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_21 +#define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_22 +#define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_23 +#define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_24 +#define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_25 +#define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_26 +#define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_27 +#define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_28 +#define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_29 +#define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_30 +#define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_31 +#define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_REQ_CTRL_LSHS +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_USER_ACCUM_LSHS_0 +#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_1 +#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_2 +#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_3 +#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_PGM_LO_LS +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_LS +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL +//COMPUTE_DISPATCH_INITIATOR +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf +#define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT 0x10 +#define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT 0x11 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L +#define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK 0x00010000L +#define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK 0x00020000L +//COMPUTE_DIM_X +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Y +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Z +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_START_X +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Y +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Z +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//COMPUTE_NUM_THREAD_X +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Y +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Z +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_PIPELINESTAT_ENABLE +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//COMPUTE_PERFCOUNT_ENABLE +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//COMPUTE_PGM_LO +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PGM_HI +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_PKT_ADDR_LO +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_PKT_ADDR_HI +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//COMPUTE_PGM_RSRC1 +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d +#define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT 0x1e +#define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +#define COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L +#define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK 0x40000000L +#define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L +//COMPUTE_PGM_RSRC2 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +//COMPUTE_VMID +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_VMID__DATA_MASK 0x0000000FL +//COMPUTE_RESOURCE_LIMITS +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +//COMPUTE_DESTINATION_EN_SE0 +#define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE1 +#define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE1 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_TMPRING_SIZE +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x07FFF000L +//COMPUTE_DESTINATION_EN_SE2 +#define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE2 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE3 +#define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE3 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_RESTART_X +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Y +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Z +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_THREAD_TRACE_ENABLE +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//COMPUTE_MISC_RESERVED +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 +#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000007L +#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L +#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +//COMPUTE_DISPATCH_ID +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//COMPUTE_THREADGROUP_ID +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//COMPUTE_REQ_CTRL +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 +#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L +#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L +//COMPUTE_USER_ACCUM_0 +#define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_1 +#define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_2 +#define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_3 +#define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_PGM_RSRC3 +#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 +#define COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT 0x4 +#define COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT 0xa +#define COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT 0xb +#define COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT 0x1f +#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL +#define COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK 0x000003F0L +#define COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK 0x00000400L +#define COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK 0x00000800L +#define COMPUTE_PGM_RSRC3__IMAGE_OP_MASK 0x80000000L +//COMPUTE_DDID_INDEX +#define COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 +#define COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL +//COMPUTE_SHADER_CHKSUM +#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 +#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE4 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE5 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE6 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE7 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DISPATCH_INTERLEAVE +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE__SHIFT 0x0 +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_MASK 0x000003FFL +//COMPUTE_RELAUNCH +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//COMPUTE_WAVE_RESTORE_ADDR_LO +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//COMPUTE_WAVE_RESTORE_ADDR_HI +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL +//COMPUTE_RELAUNCH2 +#define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L +//COMPUTE_USER_DATA_0 +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_1 +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_2 +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_3 +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_4 +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_5 +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_6 +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_7 +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_8 +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_9 +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_10 +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_11 +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_12 +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_13 +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_14 +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_15 +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_TUNNEL +#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 +#define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT 0xa +#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x000003FFL +#define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK 0x00000400L +//COMPUTE_DISPATCH_END +#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL +//COMPUTE_NOWHERE +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL +//SH_RESERVED_REG0 +#define SH_RESERVED_REG0__DATA__SHIFT 0x0 +#define SH_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//SH_RESERVED_REG1 +#define SH_RESERVED_REG1__DATA__SHIFT 0x0 +#define SH_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_cppdec +//CP_CU_MASK_ADDR_LO +#define CP_CU_MASK_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_CU_MASK_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_CU_MASK_ADDR_HI +#define CP_CU_MASK_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CU_MASK_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_CU_MASK_CNTL +#define CP_CU_MASK_CNTL__POLICY__SHIFT 0x0 +#define CP_CU_MASK_CNTL__POLICY_MASK 0x00000001L +//CP_EOPQ_WAIT_TIME +#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa +#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L +//CP_CPC_MGCG_SYNC_CNTL +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//CPC_INT_INFO +#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 +#define CPC_INT_INFO__TYPE__SHIFT 0x10 +#define CPC_INT_INFO__VMID__SHIFT 0x14 +#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c +#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL +#define CPC_INT_INFO__TYPE_MASK 0x00010000L +#define CPC_INT_INFO__VMID_MASK 0x00F00000L +#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L +//CP_VIRT_STATUS +#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 +#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL +//CPC_INT_ADDR +#define CPC_INT_ADDR__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL +//CPC_INT_PASID +#define CPC_INT_PASID__PASID__SHIFT 0x0 +#define CPC_INT_PASID__BYPASS_PASID__SHIFT 0x10 +#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL +#define CPC_INT_PASID__BYPASS_PASID_MASK 0x00010000L +//CP_GFX_ERROR +#define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x0 +#define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x1 +#define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR__SHIFT 0x2 +#define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR__SHIFT 0x3 +#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT 0x6 +#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e +#define CP_GFX_ERROR__RESERVED__SHIFT 0x1f +#define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000001L +#define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000002L +#define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR_MASK 0x00000004L +#define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR_MASK 0x00000008L +#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK 0x00000040L +#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L +#define CP_GFX_ERROR__RESERVED_MASK 0x80000000L +//CPG_UTCL1_CNTL +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPC_UTCL1_CNTL +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPF_UTCL1_CNTL +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L +//CP_AQL_SMM_STATUS +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL +//CP_RB0_BASE +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB0_CNTL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_RB0_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_EXE__SHIFT 0x1c +#define CP_RB0_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB0_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_RB0_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB0_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_EXE_MASK 0x10000000L +#define CP_RB0_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_RB_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_EXE__SHIFT 0x1c +#define CP_RB_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_RB_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_EXE_MASK 0x10000000L +#define CP_RB_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL +//CP_RB0_RPTR_ADDR +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB0_RPTR_ADDR_HI +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_RPTR_ADDR_HI +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_BUFSZ_MASK +#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_BUFSZ_MASK +#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_INT_CNTL +#define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT 0x8 +#define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT 0x9 +#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL__RESUME_INT_ENABLE_MASK 0x00000100L +#define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK 0x00000200L +#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK 0x00000400L +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS +#define CP_INT_STATUS__RESUME_INT_STAT__SHIFT 0x8 +#define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT 0x9 +#define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS__RESUME_INT_STAT_MASK 0x00000100L +#define CP_INT_STATUS__SUSPEND_INT_STAT_MASK 0x00000200L +#define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK 0x00000400L +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_DEVICE_ID +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL +//CP_ME0_PIPE_PRIORITY_CNTS +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_RING_PRIORITY_CNTS +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME0_PIPE0_PRIORITY +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING0_PRIORITY +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME0_PIPE1_PRIORITY +#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING1_PRIORITY +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_FATAL_ERROR +#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 +#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 +#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 +#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L +#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L +#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L +//CP_RB_VMID +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL +#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L +#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L +//CP_ME0_PIPE0_VMID +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL +//CP_ME0_PIPE1_VMID +#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL +//CP_RB0_WPTR +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB0_WPTR_HI +#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR_HI +#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR_HI +#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_PROCESS_QUANTUM +#define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT 0x0 +#define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT 0x1c +#define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT 0x1d +#define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT 0x1f +#define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK 0x10000000L +#define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK 0x60000000L +#define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK 0x80000000L +//CP_RB_DOORBELL_RANGE_LOWER +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL +//CP_RB_DOORBELL_RANGE_UPPER +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL +//CP_MEC_DOORBELL_RANGE_LOWER +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL +//CP_MEC_DOORBELL_RANGE_UPPER +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL +//CPG_UTCL1_ERROR +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPC_UTCL1_ERROR +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CP_RB1_BASE +#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB1_CNTL +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB1_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_RB1_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB1_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB1_CNTL__RB_EXE__SHIFT 0x1c +#define CP_RB1_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB1_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_RB1_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB1_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB1_CNTL__RB_EXE_MASK 0x10000000L +#define CP_RB1_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB1_RPTR_ADDR +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB1_RPTR_ADDR_HI +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB1_BUFSZ_MASK +#define CP_RB1_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB1_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_INT_CNTL_RING0 +#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT 0x8 +#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT 0x9 +#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK 0x00000100L +#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK 0x00000200L +#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK 0x00000400L +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_CNTL_RING1 +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS_RING0 +#define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT 0x8 +#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT 0x9 +#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK 0x00000100L +#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK 0x00000200L +#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK 0x00000400L +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_INT_STATUS_RING1 +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_ME_F32_INTERRUPT +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L +//CP_PFP_F32_INTERRUPT +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L +//CP_MEC1_F32_INTERRUPT +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_MEC2_F32_INTERRUPT +#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_PWR_CNTL +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT 0x14 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT 0x15 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT 0x16 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT 0x17 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK 0x00100000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK 0x00200000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK 0x00400000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK 0x00800000L +//CP_ECC_FIRSTOCCURRENCE +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE_RING0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL +//CP_ECC_FIRSTOCCURRENCE_RING1 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL +//GB_EDC_MODE +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +#define CP_DEBUG__PERFMON_RING_SEL__SHIFT 0x0 +#define CP_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT 0x2 +#define CP_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0x8 +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define CP_DEBUG__PACKET_FILTER_DISABLE__SHIFT 0xa +#define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE__SHIFT 0xb +#define CP_DEBUG__CPG_CHIU_RO_DISABLE__SHIFT 0xc +#define CP_DEBUG__CPG_GCR_CNTL_BYPASS__SHIFT 0xd +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT 0xe +#define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE__SHIFT 0xf +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT 0x10 +#define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 +#define CP_DEBUG__CPG_CHIU_GUS_DISABLE__SHIFT 0x15 +#define CP_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x17 +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE__SHIFT 0x1b +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT 0x1e +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT 0x1f +#define CP_DEBUG__PERFMON_RING_SEL_MASK 0x00000003L +#define CP_DEBUG__DEBUG_BUS_SELECT_BITS_MASK 0x000000FCL +#define CP_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00000100L +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +#define CP_DEBUG__PACKET_FILTER_DISABLE_MASK 0x00000400L +#define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE_MASK 0x00000800L +#define CP_DEBUG__CPG_CHIU_RO_DISABLE_MASK 0x00001000L +#define CP_DEBUG__CPG_GCR_CNTL_BYPASS_MASK 0x00002000L +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK 0x00004000L +#define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE_MASK 0x00008000L +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK 0x00070000L +#define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L +#define CP_DEBUG__CPG_CHIU_GUS_DISABLE_MASK 0x00200000L +#define CP_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE_MASK 0x08000000L +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK 0x40000000L +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK 0x80000000L +//CP_CPC_DEBUG +#define CP_CPC_DEBUG__PIPE_SELECT__SHIFT 0x0 +#define CP_CPC_DEBUG__ME_SELECT__SHIFT 0x2 +#define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE__SHIFT 0x4 +#define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0xe +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT 0xf +#define CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE__SHIFT 0x10 +#define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS__SHIFT 0x11 +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT 0x12 +#define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT 0x15 +#define CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 +#define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE__SHIFT 0x17 +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE__SHIFT 0x1b +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE__SHIFT 0x1e +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT 0x1f +#define CP_CPC_DEBUG__PIPE_SELECT_MASK 0x00000003L +#define CP_CPC_DEBUG__ME_SELECT_MASK 0x00000004L +#define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE_MASK 0x00000010L +#define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00004000L +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK 0x00008000L +#define CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE_MASK 0x00010000L +#define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS_MASK 0x00020000L +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK 0x00040000L +#define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK 0x00200000L +#define CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L +#define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE_MASK 0x00800000L +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE_MASK 0x08000000L +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE_MASK 0x40000000L +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL1 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL +//CP_ME1_PIPE0_INT_CNTL +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE1_INT_CNTL +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE2_INT_CNTL +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE3_INT_CNTL +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE0_INT_CNTL +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE1_INT_CNTL +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE2_INT_CNTL +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE3_INT_CNTL +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE0_INT_STATUS +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE1_INT_STATUS +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE2_INT_STATUS +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE3_INT_STATUS +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE0_INT_STATUS +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE1_INT_STATUS +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE2_INT_STATUS +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE3_INT_STATUS +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +//CP_GFX_QUEUE_INDEX +#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT 0x0 +#define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT 0x4 +#define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT 0x8 +#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK 0x00000001L +#define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK 0x00000030L +#define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK 0x00000700L +//CC_GC_EDC_CONFIG +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//CP_ME1_PIPE_PRIORITY_CNTS +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME1_PIPE0_PRIORITY +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE1_PRIORITY +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE2_PRIORITY +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE3_PRIORITY +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE_PRIORITY_CNTS +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME2_PIPE0_PRIORITY +#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE1_PRIORITY +#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE2_PRIORITY +#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE3_PRIORITY +#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_PFP_PRGRM_CNTR_START +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_ME_PRGRM_CNTR_START +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MEC1_PRGRM_CNTR_START +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL +//CP_MEC2_PRGRM_CNTR_START +#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL +//CP_PFP_INTR_ROUTINE_START +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_ME_INTR_ROUTINE_START +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_MEC1_INTR_ROUTINE_START +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL +//CP_MEC2_INTR_ROUTINE_START +#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL +//CP_CONTEXT_CNTL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK 0x00000007L +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK 0x00070000L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L +//CP_MAX_CONTEXT +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L +//CP_IQ_WAIT_TIME1 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//CP_IQ_WAIT_TIME2 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//CP_RB0_BASE_HI +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_RB1_BASE_HI +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_VMID_RESET +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__PIPE0_QUEUES__SHIFT 0x10 +#define CP_VMID_RESET__PIPE1_QUEUES__SHIFT 0x18 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_RESET__PIPE0_QUEUES_MASK 0x00FF0000L +#define CP_VMID_RESET__PIPE1_QUEUES_MASK 0xFF000000L +//CPC_INT_CNTL +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CPC_INT_STATUS +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_VMID_PREEMPT +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L +//CPC_INT_CNTX_ID +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PQ_STATUS +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT 0x3 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L +#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK 0x00000008L +//CP_PFP_PRGRM_CNTR_START_HI +#define CP_PFP_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MAX_DRAW_COUNT +#define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT__SHIFT 0x0 +#define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT_MASK 0xFFFFFFFFL +//CP_MEC1_F32_INT_DIS +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_MEC2_F32_INT_DIS +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_VMID_STATUS +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L +//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CPC_SUSPEND_CTX_SAVE_CONTROL +#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CPC_SUSPEND_CNTL_STACK_OFFSET +#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CPC_SUSPEND_CNTL_STACK_SIZE +#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CPC_SUSPEND_WG_STATE_OFFSET +#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CPC_SUSPEND_CTX_SAVE_SIZE +#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//CPC_OS_PIPES +#define CPC_OS_PIPES__OS_PIPES__SHIFT 0x0 +#define CPC_OS_PIPES__OS_PIPES_MASK 0x000000FFL +//CP_SUSPEND_RESUME_REQ +#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 +#define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 +#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L +#define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L +//CP_SUSPEND_CNTL +#define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT 0x0 +#define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT 0x1 +#define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT 0x2 +#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT 0x3 +#define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK 0x00000001L +#define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK 0x00000002L +#define CP_SUSPEND_CNTL__RESUME_LOCK_MASK 0x00000004L +#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK 0x00000008L +//CP_IQ_WAIT_TIME3 +#define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 +#define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL +//CPC_DDID_BASE_ADDR_LO +#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//CP_DDID_BASE_ADDR_LO +#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//CPC_DDID_BASE_ADDR_HI +#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_DDID_BASE_ADDR_HI +#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CPC_DDID_CNTL +#define CPC_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define CPC_DDID_CNTL__SIZE__SHIFT 0x10 +#define CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define CPC_DDID_CNTL__POLICY__SHIFT 0x1c +#define CPC_DDID_CNTL__MODE__SHIFT 0x1e +#define CPC_DDID_CNTL__ENABLE__SHIFT 0x1f +#define CPC_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define CPC_DDID_CNTL__SIZE_MASK 0x00010000L +#define CPC_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define CPC_DDID_CNTL__POLICY_MASK 0x30000000L +#define CPC_DDID_CNTL__MODE_MASK 0x40000000L +#define CPC_DDID_CNTL__ENABLE_MASK 0x80000000L +//CP_DDID_CNTL +#define CP_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define CP_DDID_CNTL__SIZE__SHIFT 0x10 +#define CP_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define CP_DDID_CNTL__VMID__SHIFT 0x14 +#define CP_DDID_CNTL__VMID_SEL__SHIFT 0x18 +#define CP_DDID_CNTL__POLICY__SHIFT 0x1c +#define CP_DDID_CNTL__MODE__SHIFT 0x1e +#define CP_DDID_CNTL__ENABLE__SHIFT 0x1f +#define CP_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define CP_DDID_CNTL__SIZE_MASK 0x00010000L +#define CP_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define CP_DDID_CNTL__VMID_MASK 0x00F00000L +#define CP_DDID_CNTL__VMID_SEL_MASK 0x01000000L +#define CP_DDID_CNTL__POLICY_MASK 0x30000000L +#define CP_DDID_CNTL__MODE_MASK 0x40000000L +#define CP_DDID_CNTL__ENABLE_MASK 0x80000000L +//CP_GFX_DDID_INFLIGHT_COUNT +#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_WPTR +#define CP_GFX_DDID_WPTR__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_WPTR__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_RPTR +#define CP_GFX_DDID_RPTR__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_RPTR__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_DELTA_RPT_COUNT +#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL +//CP_GFX_HPD_STATUS0 +#define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT 0x10 +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT 0x1c +#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT 0x1d +#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT 0x1e +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK 0x00070000L +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK 0x10000000L +#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK 0x20000000L +#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK 0x40000000L +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L +//CP_GFX_HPD_CONTROL0 +#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT 0x0 +#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT 0x4 +#define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL__SHIFT 0x8 +#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK 0x00000001L +#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK 0x00000010L +#define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL_MASK 0x00000100L +//CP_GFX_HPD_OSPRE_FENCE_ADDR_LO +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_GFX_HPD_OSPRE_FENCE_ADDR_HI +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_GFX_HPD_OSPRE_FENCE_DATA_LO +#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_GFX_HPD_OSPRE_FENCE_DATA_HI +#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_GFX_INDEX_MUTEX +#define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT 0x0 +#define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT 0x1 +#define CP_GFX_INDEX_MUTEX__REQUEST_MASK 0x00000001L +#define CP_GFX_INDEX_MUTEX__CLIENTID_MASK 0x0000000EL +//CP_ME_PRGRM_CNTR_START_HI +#define CP_ME_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_PFP_INTR_ROUTINE_START_HI +#define CP_PFP_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL +//CP_ME_INTR_ROUTINE_START_HI +#define CP_ME_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL +//CP_GFX_MQD_BASE_ADDR +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_MQD_BASE_ADDR_HI +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT 0x1c +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK 0xF0000000L +//CP_GFX_HQD_ACTIVE +#define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_GFX_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_GFX_HQD_VMID +#define CP_GFX_HQD_VMID__VMID__SHIFT 0x0 +#define CP_GFX_HQD_VMID__VMID_MASK 0x0000000FL +//CP_GFX_HQD_QUEUE_PRIORITY +#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_GFX_HQD_QUANTUM +#define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x3 +#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000018L +#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x0000FF00L +#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_GFX_HQD_BASE +#define CP_GFX_HQD_BASE__RB_BASE__SHIFT 0x0 +#define CP_GFX_HQD_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_GFX_HQD_BASE_HI +#define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_GFX_HQD_RPTR +#define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_GFX_HQD_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_GFX_HQD_RPTR_ADDR +#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_HQD_RPTR_ADDR_HI +#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_WPTR_POLL_ADDR_LO +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL +//CP_RB_WPTR_POLL_ADDR_HI +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_DOORBELL_CONTROL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_GFX_HQD_OFFSET +#define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f +#define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L +//CP_GFX_HQD_CNTL +#define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_GFX_HQD_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_GFX_HQD_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT 0x10 +#define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_GFX_HQD_CNTL__RB_EXE__SHIFT 0x1c +#define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_GFX_HQD_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_GFX_HQD_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_GFX_HQD_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_GFX_HQD_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_GFX_HQD_CNTL__RB_EXE_MASK 0x10000000L +#define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_GFX_HQD_CSMD_RPTR +#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_GFX_HQD_WPTR +#define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_GFX_HQD_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_GFX_HQD_WPTR_HI +#define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_GFX_HQD_DEQUEUE_REQUEST +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000001L +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_GFX_HQD_MAPPED +#define CP_GFX_HQD_MAPPED__MAPPED__SHIFT 0x0 +#define CP_GFX_HQD_MAPPED__MAPPED_MASK 0x00000001L +//CP_GFX_HQD_QUE_MGR_CONTROL +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT__SHIFT 0x0 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE__SHIFT 0x4 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT__SHIFT 0x5 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN__SHIFT 0x6 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN__SHIFT 0x7 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE__SHIFT 0x8 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE__SHIFT 0xb +#define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE__SHIFT 0xd +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR__SHIFT 0xf +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE__SHIFT 0x10 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE__SHIFT 0x11 +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT__SHIFT 0x12 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG__SHIFT 0x17 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT_MASK 0x00000001L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE_MASK 0x00000010L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT_MASK 0x00000020L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN_MASK 0x00000040L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN_MASK 0x00000080L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_MASK 0x00000700L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE_MASK 0x00000800L +#define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE_MASK 0x00002000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR_MASK 0x00008000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE_MASK 0x00010000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE_MASK 0x00020000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT_MASK 0x00040000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG_MASK 0x00800000L +//CP_GFX_HQD_IQ_TIMER +#define CP_GFX_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define CP_GFX_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_GFX_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_GFX_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define CP_GFX_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_GFX_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_GFX_HQD_HQ_STATUS0 +#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT 0x4 +#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT 0x6 +#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000001L +#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK 0x00000030L +#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK 0x00000040L +#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +//CP_GFX_HQD_HQ_CONTROL0 +#define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT 0x0 +#define CP_GFX_HQD_HQ_CONTROL0__SPARES__SHIFT 0x4 +#define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK 0x0000000FL +#define CP_GFX_HQD_HQ_CONTROL0__SPARES_MASK 0x000000F0L +//CP_GFX_MQD_CONTROL +#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L +//CP_HQD_GFX_CONTROL +#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 +#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf +#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL +#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L +//CP_HQD_GFX_STATUS +#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 +#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL +//CP_DMA_WATCH0_ADDR_LO +#define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT 0x7 +#define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L +//CP_DMA_WATCH0_ADDR_HI +#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_DMA_WATCH0_MASK +#define CP_DMA_WATCH0_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH0_MASK__MASK__SHIFT 0x7 +#define CP_DMA_WATCH0_MASK__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH0_MASK__MASK_MASK 0xFFFFFF80L +//CP_DMA_WATCH0_CNTL +#define CP_DMA_WATCH0_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH0_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH0_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH0_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH1_ADDR_LO +#define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT 0x7 +#define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L +//CP_DMA_WATCH1_ADDR_HI +#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_DMA_WATCH1_MASK +#define CP_DMA_WATCH1_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH1_MASK__MASK__SHIFT 0x7 +#define CP_DMA_WATCH1_MASK__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH1_MASK__MASK_MASK 0xFFFFFF80L +//CP_DMA_WATCH1_CNTL +#define CP_DMA_WATCH1_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH1_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH1_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH1_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH2_ADDR_LO +#define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT 0x7 +#define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L +//CP_DMA_WATCH2_ADDR_HI +#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_DMA_WATCH2_MASK +#define CP_DMA_WATCH2_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH2_MASK__MASK__SHIFT 0x7 +#define CP_DMA_WATCH2_MASK__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH2_MASK__MASK_MASK 0xFFFFFF80L +//CP_DMA_WATCH2_CNTL +#define CP_DMA_WATCH2_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH2_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH2_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH2_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH3_ADDR_LO +#define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT 0x7 +#define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L +//CP_DMA_WATCH3_ADDR_HI +#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_DMA_WATCH3_MASK +#define CP_DMA_WATCH3_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH3_MASK__MASK__SHIFT 0x7 +#define CP_DMA_WATCH3_MASK__RSVD_MASK 0x0000007FL +#define CP_DMA_WATCH3_MASK__MASK_MASK 0xFFFFFF80L +//CP_DMA_WATCH3_CNTL +#define CP_DMA_WATCH3_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH3_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH3_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH3_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH_STAT_ADDR_LO +#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_WATCH_STAT_ADDR_HI +#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_WATCH_STAT +#define CP_DMA_WATCH_STAT__VMID__SHIFT 0x0 +#define CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT 0x4 +#define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT 0x8 +#define CP_DMA_WATCH_STAT__PIPE__SHIFT 0xc +#define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT 0x10 +#define CP_DMA_WATCH_STAT__RD_WR__SHIFT 0x14 +#define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT 0x1f +#define CP_DMA_WATCH_STAT__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH_STAT__QUEUE_ID_MASK 0x00000070L +#define CP_DMA_WATCH_STAT__CLIENT_ID_MASK 0x00000700L +#define CP_DMA_WATCH_STAT__PIPE_MASK 0x00003000L +#define CP_DMA_WATCH_STAT__WATCH_ID_MASK 0x00030000L +#define CP_DMA_WATCH_STAT__RD_WR_MASK 0x00100000L +#define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK 0x80000000L +//CP_PFP_JT_STAT +#define CP_PFP_JT_STAT__JT_LOADED__SHIFT 0x0 +#define CP_PFP_JT_STAT__WR_MASK__SHIFT 0x10 +#define CP_PFP_JT_STAT__JT_LOADED_MASK 0x00000003L +#define CP_PFP_JT_STAT__WR_MASK_MASK 0x00030000L +//CP_MEC_JT_STAT +#define CP_MEC_JT_STAT__JT_LOADED__SHIFT 0x0 +#define CP_MEC_JT_STAT__WR_MASK__SHIFT 0x10 +#define CP_MEC_JT_STAT__JT_LOADED_MASK 0x000000FFL +#define CP_MEC_JT_STAT__WR_MASK_MASK 0x00FF0000L +//CP_CPC_BUSY_HYSTERESIS +#define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY_MASK 0x0000FF00L +//CP_CPF_BUSY_HYSTERESIS1 +#define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY_MASK 0x0000FF00L +#define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY_MASK 0x00FF0000L +#define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L +//CP_CPF_BUSY_HYSTERESIS2 +#define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL +//CP_CPG_BUSY_HYSTERESIS1 +#define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY__SHIFT 0x8 +#define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY__SHIFT 0x10 +#define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 +#define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY_MASK 0x0000FF00L +#define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY_MASK 0x00FF0000L +#define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L +//CP_CPG_BUSY_HYSTERESIS2 +#define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0__SHIFT 0x8 +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1__SHIFT 0x10 +#define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0_MASK 0x0000FF00L +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1_MASK 0x00FF0000L +//CP_RB_DOORBELL_CLEAR +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L +//CP_RB0_ACTIVE +#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_ACTIVE +#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB1_ACTIVE +#define CP_RB1_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB1_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_STATUS +#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CPG_RCIU_CAM_INDEX +#define CPG_RCIU_CAM_INDEX__INDEX__SHIFT 0x0 +#define CPG_RCIU_CAM_INDEX__INDEX_MASK 0x0000001FL +//CPG_RCIU_CAM_DATA +#define CPG_RCIU_CAM_DATA__DATA__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE0 +#define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT 0x18 +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT 0x19 +#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT 0x1f +#define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK 0x0003FFFFL +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK 0x01000000L +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK 0x02000000L +#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK 0x80000000L +//CPG_RCIU_CAM_DATA_PHASE1 +#define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE2 +#define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK 0xFFFFFFFFL +//CP_GPU_TIMESTAMP_OFFSET_LO +#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT 0x0 +#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK 0xFFFFFFFFL +//CP_GPU_TIMESTAMP_OFFSET_HI +#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT 0x0 +#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK 0xFFFFFFFFL +//CP_SDMA_DMA_DONE +#define CP_SDMA_DMA_DONE__SDMA_ID__SHIFT 0x0 +#define CP_SDMA_DMA_DONE__SDMA_ID_MASK 0x0000000FL +//CP_PFP_SDMA_CS +#define CP_PFP_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 +#define CP_PFP_SDMA_CS__SDMA_ID__SHIFT 0x4 +#define CP_PFP_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 +#define CP_PFP_SDMA_CS__SDMA_COUNT__SHIFT 0xc +#define CP_PFP_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L +#define CP_PFP_SDMA_CS__SDMA_ID_MASK 0x000000F0L +#define CP_PFP_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L +#define CP_PFP_SDMA_CS__SDMA_COUNT_MASK 0x00003000L +//CP_ME_SDMA_CS +#define CP_ME_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 +#define CP_ME_SDMA_CS__SDMA_ID__SHIFT 0x4 +#define CP_ME_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 +#define CP_ME_SDMA_CS__SDMA_COUNT__SHIFT 0xc +#define CP_ME_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L +#define CP_ME_SDMA_CS__SDMA_ID_MASK 0x000000F0L +#define CP_ME_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L +#define CP_ME_SDMA_CS__SDMA_COUNT_MASK 0x00003000L +//CPF_GCR_CNTL +#define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT 0x0 +#define CPF_GCR_CNTL__GCR_GL_CMD_MASK 0x0007FFFFL +//CPG_UTCL1_STATUS +#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPC_UTCL1_STATUS +#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPF_UTCL1_STATUS +#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CP_SD_CNTL +#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 +#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 +#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 +#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 +#define CP_SD_CNTL__GE_EN__SHIFT 0x5 +#define CP_SD_CNTL__UTCL1_EN__SHIFT 0x6 +#define CP_SD_CNTL__EA_EN__SHIFT 0x9 +#define CP_SD_CNTL__SDMA_EN__SHIFT 0xa +#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT 0x1f +#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L +#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L +#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L +#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L +#define CP_SD_CNTL__GE_EN_MASK 0x00000020L +#define CP_SD_CNTL__UTCL1_EN_MASK 0x00000040L +#define CP_SD_CNTL__EA_EN_MASK 0x00000200L +#define CP_SD_CNTL__SDMA_EN_MASK 0x00000400L +#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK 0x80000000L +//CP_SOFT_RESET_CNTL +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 +#define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET__SHIFT 0x7 +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L +#define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET_MASK 0x00000080L +//CP_CPC_GFX_CNTL +#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 +#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 +#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 +#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 +#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L +#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L +#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L +#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L + + +// addressBlock: gc_spipdec +//SPI_ARB_PRIORITY +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L +//SPI_ARB_CYCLES_0 +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L +//SPI_ARB_CYCLES_1 +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L +//SPI_WCL_PIPE_PERCENT_GFX +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_HP3D +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_CS0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS1 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS2 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS3 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS4 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS5 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS6 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS7 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL +//SPI_USER_ACCUM_VMID_CNTL +#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0 +#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL +//SPI_GDBG_PER_VMID_CNTL +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0 +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1 +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT 0xe +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT 0xf +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x00000001L +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x00000006L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x00000008L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x00001FF0L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x00002000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK 0x00004000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK 0x00008000L +//SPI_COMPUTE_QUEUE_RESET +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L +//SPI_COMPUTE_WF_CTX_SAVE +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L + + +// addressBlock: gc_cpphqddec +//CP_HPD_UTCL1_CNTL +#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 +#define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT__SHIFT 0xa +#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL +#define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT_MASK 0x00000400L +//CP_HPD_UTCL1_ERROR +#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 +#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 +#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 +#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL +#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L +#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L +//CP_HPD_UTCL1_ERROR_ADDR +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L +//CP_MQD_BASE_ADDR +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_MQD_BASE_ADDR_HI +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_ACTIVE +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L +//CP_HQD_VMID +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_VMID__VMID_MASK 0x0000000FL +#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L +#define CP_HQD_VMID__VQID_MASK 0x03FF0000L +//CP_HQD_PERSISTENT_STATE +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE__SHIFT 0x1 +#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT 0x7 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT__SHIFT 0x12 +#define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS__SHIFT 0x13 +#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT 0x14 +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L +#define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE_MASK 0x00000002L +#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK 0x00000080L +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L +#define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT_MASK 0x00040000L +#define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS_MASK 0x00080000L +#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK 0x00100000L +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L +//CP_HQD_PIPE_PRIORITY +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L +//CP_HQD_QUEUE_PRIORITY +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_HQD_QUANTUM +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_HQD_PQ_BASE +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_PQ_BASE_HI +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL +//CP_HQD_PQ_RPTR +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_RPTR_REPORT_ADDR +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_PQ_RPTR_REPORT_ADDR_HI +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_WPTR_POLL_ADDR +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L +//CP_HQD_PQ_WPTR_POLL_ADDR_HI +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_DOORBELL_CONTROL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_HQD_PQ_CONTROL +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 +#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe +#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16 +#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL +#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L +#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L +#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x000C0000L +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L +#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x04000000L +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L +#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK 0x20000000L +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L +//CP_HQD_IB_BASE_ADDR +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_IB_BASE_ADDR_HI +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_IB_RPTR +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL +//CP_HQD_IB_CONTROL +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x04000000L +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L +//CP_HQD_IQ_TIMER +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a +#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x04000000L +#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_HQD_IQ_RPTR +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL +//CP_HQD_DEQUEUE_REQUEST +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x0000000FL +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_HQD_DMA_OFFLOAD +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_OFFLOAD +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_SEMA_CMD +#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 +#define CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT 0x8 +#define CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT 0x9 +#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L +#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L +#define CP_HQD_SEMA_CMD__POLLING_DIS_MASK 0x00000100L +#define CP_HQD_SEMA_CMD__MESSAGE_EN_MASK 0x00000200L +//CP_HQD_MSG_TYPE +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L +//CP_HQD_ATOMIC0_PREOP_LO +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC0_PREOP_HI +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_LO +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_HI +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER0 +#define CP_HQD_HQ_SCHEDULER0__CWSR__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS__SHIFT 0x1 +#define CP_HQD_HQ_SCHEDULER0__RSRV__SHIFT 0x2 +#define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE__SHIFT 0x3 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6 +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID__SHIFT 0x9 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS__SHIFT 0xd +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED__SHIFT 0xf +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED__SHIFT 0x14 +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE__SHIFT 0x15 +#define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_SCHEDULER0__CWSR_MASK 0x00000001L +#define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS_MASK 0x00000002L +#define CP_HQD_HQ_SCHEDULER0__RSRV_MASK 0x00000004L +#define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE_MASK 0x00000038L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x00000040L +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID_MASK 0x00000200L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS_MASK 0x00002000L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED_MASK 0x00100000L +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE_MASK 0x00600000L +#define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_STATUS0 +#define CP_HQD_HQ_STATUS0__CWSR__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__SAVE_STATUS__SHIFT 0x1 +#define CP_HQD_HQ_STATUS0__RSRV__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__STATIC_QUEUE__SHIFT 0x3 +#define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE__SHIFT 0x6 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__C_INHERIT_VMID__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa +#define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS__SHIFT 0xd +#define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED__SHIFT 0xf +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED__SHIFT 0x14 +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE__SHIFT 0x15 +#define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_STATUS0__CWSR_MASK 0x00000001L +#define CP_HQD_HQ_STATUS0__SAVE_STATUS_MASK 0x00000002L +#define CP_HQD_HQ_STATUS0__RSRV_MASK 0x00000004L +#define CP_HQD_HQ_STATUS0__STATIC_QUEUE_MASK 0x00000038L +#define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE_MASK 0x00000040L +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_STATUS0__C_INHERIT_VMID_MASK 0x00000200L +#define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L +#define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS_MASK 0x00002000L +#define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED_MASK 0x00100000L +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE_MASK 0x00600000L +#define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_CONTROL0 +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER1 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL +//CP_MQD_CONTROL +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a +#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x04000000L +//CP_HQD_HQ_STATUS1 +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL +//CP_HQD_HQ_CONTROL1 +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR_HI +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL +//CP_HQD_EOP_CONTROL +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 +#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L +#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK 0x04000000L +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L +//CP_HQD_EOP_RPTR +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L +//CP_HQD_EOP_WPTR +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L +//CP_HQD_EOP_EVENTS +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L +//CP_HQD_CTX_SAVE_BASE_ADDR_LO +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CP_HQD_CTX_SAVE_BASE_ADDR_HI +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_CTX_SAVE_CONTROL +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CP_HQD_CNTL_STACK_OFFSET +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_CNTL_STACK_SIZE +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CP_HQD_WG_STATE_OFFSET +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CP_HQD_CTX_SAVE_SIZE +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//CP_HQD_GDS_RESOURCE_STATE +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L +//CP_HQD_ERROR +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 +#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 +#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 +#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa +#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc +#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd +#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 +#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 +#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 +#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L +#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L +#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L +#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L +#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L +#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L +#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L +#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L +#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L +#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L +//CP_HQD_EOP_WPTR_MEM +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL +//CP_HQD_AQL_CONTROL +#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf +#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 +#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f +#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL +#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L +#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L +#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L +//CP_HQD_PQ_WPTR_LO +#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_WPTR_HI +#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL +//CP_HQD_SUSPEND_CNTL_STACK_OFFSET +#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_SUSPEND_CNTL_STACK_DW_CNT +#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT 0x0 +#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK 0x00003FFFL +//CP_HQD_SUSPEND_WG_STATE_OFFSET +#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CP_HQD_DDID_RPTR +#define CP_HQD_DDID_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_DDID_RPTR__RPTR_MASK 0x000007FFL +//CP_HQD_DDID_WPTR +#define CP_HQD_DDID_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_DDID_WPTR__WPTR_MASK 0x000007FFL +//CP_HQD_DDID_INFLIGHT_COUNT +#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 +#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL +//CP_HQD_DDID_DELTA_RPT_COUNT +#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 +#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL +//CP_HQD_DEQUEUE_STATUS +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT 0x0 +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK 0x0000000FL +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK 0x00000400L + + +// addressBlock: gc_tcpdec +//TCP_WATCH0_ADDR_H +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH0_ADDR_L +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH0_CNTL +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH0_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH1_ADDR_H +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH1_ADDR_L +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH1_CNTL +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH2_ADDR_H +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH2_ADDR_L +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH2_CNTL +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH3_ADDR_H +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH3_ADDR_L +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH3_CNTL +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L + + +// addressBlock: gc_gdspdec +//GDS_VMID0_BASE +#define GDS_VMID0_BASE__BASE__SHIFT 0x0 +#define GDS_VMID0_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID0_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID0_SIZE +#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID0_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID0_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID1_BASE +#define GDS_VMID1_BASE__BASE__SHIFT 0x0 +#define GDS_VMID1_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID1_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID1_SIZE +#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID1_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID1_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID2_BASE +#define GDS_VMID2_BASE__BASE__SHIFT 0x0 +#define GDS_VMID2_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID2_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID2_SIZE +#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID2_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID2_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID3_BASE +#define GDS_VMID3_BASE__BASE__SHIFT 0x0 +#define GDS_VMID3_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID3_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID3_SIZE +#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID3_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID3_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID4_BASE +#define GDS_VMID4_BASE__BASE__SHIFT 0x0 +#define GDS_VMID4_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID4_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID4_SIZE +#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID4_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID4_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID5_BASE +#define GDS_VMID5_BASE__BASE__SHIFT 0x0 +#define GDS_VMID5_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID5_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID5_SIZE +#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID5_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID5_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID6_BASE +#define GDS_VMID6_BASE__BASE__SHIFT 0x0 +#define GDS_VMID6_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID6_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID6_SIZE +#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID6_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID6_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID7_BASE +#define GDS_VMID7_BASE__BASE__SHIFT 0x0 +#define GDS_VMID7_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID7_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID7_SIZE +#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID7_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID7_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID8_BASE +#define GDS_VMID8_BASE__BASE__SHIFT 0x0 +#define GDS_VMID8_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID8_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID8_SIZE +#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID8_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID8_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID9_BASE +#define GDS_VMID9_BASE__BASE__SHIFT 0x0 +#define GDS_VMID9_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID9_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID9_SIZE +#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID9_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID9_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID10_BASE +#define GDS_VMID10_BASE__BASE__SHIFT 0x0 +#define GDS_VMID10_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID10_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID10_SIZE +#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID10_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID10_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID11_BASE +#define GDS_VMID11_BASE__BASE__SHIFT 0x0 +#define GDS_VMID11_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID11_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID11_SIZE +#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID11_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID11_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID12_BASE +#define GDS_VMID12_BASE__BASE__SHIFT 0x0 +#define GDS_VMID12_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID12_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID12_SIZE +#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID12_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID12_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID13_BASE +#define GDS_VMID13_BASE__BASE__SHIFT 0x0 +#define GDS_VMID13_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID13_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID13_SIZE +#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID13_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID13_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID14_BASE +#define GDS_VMID14_BASE__BASE__SHIFT 0x0 +#define GDS_VMID14_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID14_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID14_SIZE +#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID14_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID14_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_VMID15_BASE +#define GDS_VMID15_BASE__BASE__SHIFT 0x0 +#define GDS_VMID15_BASE__UNUSED__SHIFT 0x10 +#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL +#define GDS_VMID15_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_VMID15_SIZE +#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID15_SIZE__UNUSED__SHIFT 0x11 +#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL +#define GDS_VMID15_SIZE__UNUSED_MASK 0xFFFE0000L +//GDS_GWS_VMID0 +#define GDS_GWS_VMID0__BASE__SHIFT 0x0 +#define GDS_GWS_VMID0__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID0__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID0__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID0__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID1 +#define GDS_GWS_VMID1__BASE__SHIFT 0x0 +#define GDS_GWS_VMID1__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID1__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID1__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID1__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID2 +#define GDS_GWS_VMID2__BASE__SHIFT 0x0 +#define GDS_GWS_VMID2__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID2__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID2__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID2__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID3 +#define GDS_GWS_VMID3__BASE__SHIFT 0x0 +#define GDS_GWS_VMID3__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID3__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID3__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID3__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID4 +#define GDS_GWS_VMID4__BASE__SHIFT 0x0 +#define GDS_GWS_VMID4__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID4__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID4__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID4__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID5 +#define GDS_GWS_VMID5__BASE__SHIFT 0x0 +#define GDS_GWS_VMID5__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID5__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID5__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID5__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID6 +#define GDS_GWS_VMID6__BASE__SHIFT 0x0 +#define GDS_GWS_VMID6__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID6__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID6__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID6__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID7 +#define GDS_GWS_VMID7__BASE__SHIFT 0x0 +#define GDS_GWS_VMID7__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID7__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID7__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID7__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID8 +#define GDS_GWS_VMID8__BASE__SHIFT 0x0 +#define GDS_GWS_VMID8__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID8__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID8__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID8__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID9 +#define GDS_GWS_VMID9__BASE__SHIFT 0x0 +#define GDS_GWS_VMID9__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID9__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID9__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID9__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID10 +#define GDS_GWS_VMID10__BASE__SHIFT 0x0 +#define GDS_GWS_VMID10__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID10__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID10__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID10__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID11 +#define GDS_GWS_VMID11__BASE__SHIFT 0x0 +#define GDS_GWS_VMID11__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID11__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID11__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID11__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID12 +#define GDS_GWS_VMID12__BASE__SHIFT 0x0 +#define GDS_GWS_VMID12__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID12__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID12__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID12__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID13 +#define GDS_GWS_VMID13__BASE__SHIFT 0x0 +#define GDS_GWS_VMID13__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID13__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID13__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID13__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID14 +#define GDS_GWS_VMID14__BASE__SHIFT 0x0 +#define GDS_GWS_VMID14__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID14__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID14__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID14__UNUSED2_MASK 0xFF800000L +//GDS_GWS_VMID15 +#define GDS_GWS_VMID15__BASE__SHIFT 0x0 +#define GDS_GWS_VMID15__UNUSED1__SHIFT 0x6 +#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID15__UNUSED2__SHIFT 0x17 +#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID15__UNUSED1_MASK 0x0000FFC0L +#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L +#define GDS_GWS_VMID15__UNUSED2_MASK 0xFF800000L +//GDS_OA_VMID0 +#define GDS_OA_VMID0__MASK__SHIFT 0x0 +#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID1 +#define GDS_OA_VMID1__MASK__SHIFT 0x0 +#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID2 +#define GDS_OA_VMID2__MASK__SHIFT 0x0 +#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID3 +#define GDS_OA_VMID3__MASK__SHIFT 0x0 +#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID4 +#define GDS_OA_VMID4__MASK__SHIFT 0x0 +#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID5 +#define GDS_OA_VMID5__MASK__SHIFT 0x0 +#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID6 +#define GDS_OA_VMID6__MASK__SHIFT 0x0 +#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID7 +#define GDS_OA_VMID7__MASK__SHIFT 0x0 +#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID8 +#define GDS_OA_VMID8__MASK__SHIFT 0x0 +#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID9 +#define GDS_OA_VMID9__MASK__SHIFT 0x0 +#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID10 +#define GDS_OA_VMID10__MASK__SHIFT 0x0 +#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID11 +#define GDS_OA_VMID11__MASK__SHIFT 0x0 +#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID12 +#define GDS_OA_VMID12__MASK__SHIFT 0x0 +#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID13 +#define GDS_OA_VMID13__MASK__SHIFT 0x0 +#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID14 +#define GDS_OA_VMID14__MASK__SHIFT 0x0 +#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID15 +#define GDS_OA_VMID15__MASK__SHIFT 0x0 +#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L +//GDS_GWS_RESET0 +#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 +#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 +#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 +#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 +#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 +#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 +#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 +#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 +#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 +#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 +#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa +#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb +#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc +#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd +#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe +#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf +#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 +#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 +#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 +#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 +#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 +#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 +#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 +#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 +#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 +#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a +#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b +#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c +#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d +#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e +#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f +#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L +#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L +#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L +#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L +#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L +#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L +#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L +#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L +#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L +#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L +#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L +#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L +#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L +#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L +#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L +#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L +#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L +#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L +#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L +#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L +#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L +#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L +#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L +#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L +#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L +#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L +#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L +#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L +#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L +#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L +#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L +#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L +//GDS_GWS_RESET1 +#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 +#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 +#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 +#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 +#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 +#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 +#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 +#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 +#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 +#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 +#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa +#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb +#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc +#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd +#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe +#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf +#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 +#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 +#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 +#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 +#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 +#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 +#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 +#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 +#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 +#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 +#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a +#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b +#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c +#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d +#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e +#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f +#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L +#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L +#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L +#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L +#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L +#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L +#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L +#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L +#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L +#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L +#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L +#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L +#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L +#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L +#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L +#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L +#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L +#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L +#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L +#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L +#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L +#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L +#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L +#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L +#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L +#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L +#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L +#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L +#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L +#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L +#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L +#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L +//GDS_GWS_RESOURCE_RESET +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 +#define GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L +#define GDS_GWS_RESOURCE_RESET__UNUSED_MASK 0xFFFF0000L +//GDS_COMPUTE_MAX_WAVE_ID +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT 0xc +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +#define GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK 0xFFFFF000L +//GDS_OA_RESET_MASK +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 +#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb +#define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET__SHIFT 0xc +#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xd +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L +#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L +#define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET_MASK 0x00001000L +#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFE000L +//GDS_OA_RESET +#define GDS_OA_RESET__RESET__SHIFT 0x0 +#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 +#define GDS_OA_RESET__UNUSED__SHIFT 0x10 +#define GDS_OA_RESET__RESET_MASK 0x00000001L +#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L +#define GDS_OA_RESET__UNUSED_MASK 0xFFFF0000L +//GDS_CS_CTXSW_STATUS +#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_CS_CTXSW_CNT0 +#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT1 +#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT2 +#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT3 +#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_GFX_CTXSW_STATUS +#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_PS_CTXSW_CNT0 +#define GDS_PS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS_CTXSW_CNT1 +#define GDS_PS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS_CTXSW_CNT2 +#define GDS_PS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS_CTXSW_CNT3 +#define GDS_PS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS_CTXSW_IDX +#define GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT 0x0 +#define GDS_PS_CTXSW_IDX__UNUSED__SHIFT 0x6 +#define GDS_PS_CTXSW_IDX__PACKER_ID_MASK 0x0000003FL +#define GDS_PS_CTXSW_IDX__UNUSED_MASK 0xFFFFFFC0L +//GDS_GS_CTXSW_CNT0 +#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT1 +#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT2 +#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT3 +#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_MEMORY_CLEAN +#define GDS_MEMORY_CLEAN__START__SHIFT 0x0 +#define GDS_MEMORY_CLEAN__FINISH__SHIFT 0x1 +#define GDS_MEMORY_CLEAN__UNUSED__SHIFT 0x2 +#define GDS_MEMORY_CLEAN__START_MASK 0x00000001L +#define GDS_MEMORY_CLEAN__FINISH_MASK 0x00000002L +#define GDS_MEMORY_CLEAN__UNUSED_MASK 0xFFFFFFFCL + + +// addressBlock: gc_gusdec +//GUS_IO_RD_COMBINE_FLUSH +#define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 +#define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 +#define GUS_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x18 +#define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L +#define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L +#define GUS_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x03000000L +//GUS_IO_WR_COMBINE_FLUSH +#define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 +#define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 +#define GUS_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x18 +#define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L +#define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L +#define GUS_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x03000000L +//GUS_IO_RD_PRI_AGE_RATE +#define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc +#define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf +#define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L +#define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L +//GUS_IO_WR_PRI_AGE_RATE +#define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc +#define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf +#define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L +#define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L +//GUS_IO_RD_PRI_AGE_COEFF +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L +//GUS_IO_WR_PRI_AGE_COEFF +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L +//GUS_IO_RD_PRI_QUEUING +#define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc +#define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf +#define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L +//GUS_IO_WR_PRI_QUEUING +#define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc +#define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf +#define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L +//GUS_IO_RD_PRI_FIXED +#define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc +#define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf +#define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L +//GUS_IO_WR_PRI_FIXED +#define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc +#define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf +#define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L +//GUS_IO_RD_PRI_URGENCY_COEFF +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L +//GUS_IO_WR_PRI_URGENCY_COEFF +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L +#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L +//GUS_IO_RD_PRI_URGENCY_MODE +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L +#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L +//GUS_IO_WR_PRI_URGENCY_MODE +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L +#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L +//GUS_IO_RD_PRI_QUANT_PRI1 +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_RD_PRI_QUANT_PRI2 +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_RD_PRI_QUANT_PRI3 +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_RD_PRI_QUANT_PRI4 +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_WR_PRI_QUANT_PRI1 +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_WR_PRI_QUANT_PRI2 +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_WR_PRI_QUANT_PRI3 +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_WR_PRI_QUANT_PRI4 +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_IO_RD_PRI_QUANT1_PRI1 +#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_RD_PRI_QUANT1_PRI2 +#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_RD_PRI_QUANT1_PRI3 +#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_RD_PRI_QUANT1_PRI4 +#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_WR_PRI_QUANT1_PRI1 +#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_WR_PRI_QUANT1_PRI2 +#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_WR_PRI_QUANT1_PRI3 +#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_WR_PRI_QUANT1_PRI4 +#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_DRAM_COMBINE_FLUSH +#define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 +#define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 +#define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L +#define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L +//GUS_DRAM_COMBINE_RD_WR_EN +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT 0x0 +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT 0x2 +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT 0x4 +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT 0x6 +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT 0x8 +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT 0xa +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK 0x00000003L +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK 0x0000000CL +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK 0x00000030L +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK 0x000000C0L +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK 0x00000300L +#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK 0x00000C00L +//GUS_DRAM_PRI_AGE_RATE +#define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc +#define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf +#define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L +#define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L +//GUS_DRAM_PRI_AGE_COEFF +#define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 +#define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 +#define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 +#define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 +#define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc +#define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf +#define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L +#define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L +#define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L +#define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L +#define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L +#define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L +//GUS_DRAM_PRI_QUEUING +#define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc +#define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf +#define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +#define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L +#define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L +//GUS_DRAM_PRI_FIXED +#define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc +#define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf +#define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +#define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L +#define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L +//GUS_DRAM_PRI_URGENCY_COEFF +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L +#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L +//GUS_DRAM_PRI_URGENCY_MODE +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L +#define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L +//GUS_DRAM_PRI_QUANT_PRI1 +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_DRAM_PRI_QUANT_PRI2 +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_DRAM_PRI_QUANT_PRI3 +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_DRAM_PRI_QUANT_PRI4 +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_DRAM_PRI_QUANT_PRI5 +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT 0x10 +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT 0x18 +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK 0xFF000000L +//GUS_DRAM_PRI_QUANT1_PRI1 +#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_DRAM_PRI_QUANT1_PRI2 +#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_DRAM_PRI_QUANT1_PRI3 +#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_DRAM_PRI_QUANT1_PRI4 +#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_DRAM_PRI_QUANT1_PRI5 +#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT 0x0 +#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT 0x8 +#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK 0x000000FFL +#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK 0x0000FF00L +//GUS_IO_GROUP_BURST +#define GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GUS_DRAM_GROUP_BURST +#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT 0x0 +#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT 0x8 +#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK 0x000000FFL +#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK 0x0000FF00L +//GUS_SDP_ARB_FINAL +#define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT 0x0 +#define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x5 +#define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x11 +#define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x12 +#define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK 0x0000001FL +#define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x000003E0L +#define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x00020000L +#define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x00040000L +//GUS_SDP_QOS_VC_PRIORITY +#define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT 0x0 +#define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT 0x4 +#define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT 0x8 +#define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT 0xc +#define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK 0x0000000FL +#define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK 0x000000F0L +#define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK 0x00000F00L +#define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK 0x0000F000L +//GUS_SDP_CREDITS +#define GUS_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define GUS_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//GUS_SDP_TAG_RESERVE0 +#define GUS_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define GUS_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define GUS_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define GUS_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define GUS_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define GUS_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define GUS_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define GUS_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//GUS_SDP_TAG_RESERVE1 +#define GUS_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define GUS_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define GUS_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define GUS_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define GUS_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define GUS_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define GUS_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define GUS_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//GUS_SDP_VCC_RESERVE0 +#define GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GUS_SDP_VCC_RESERVE1 +#define GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GUS_SDP_VCD_RESERVE0 +#define GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GUS_SDP_VCD_RESERVE1 +#define GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GUS_SDP_REQ_CNTL +#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 +#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L +//GUS_MISC +#define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT 0x0 +#define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x1 +#define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x2 +#define GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x3 +#define GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x4 +#define GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x6 +#define GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x8 +#define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xa +#define GUS_MISC__SEND0_IOWR_ONLY__SHIFT 0xf +#define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK 0x00000001L +#define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000002L +#define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000004L +#define GUS_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000008L +#define GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000030L +#define GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x000000C0L +#define GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00000300L +#define GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x00007C00L +#define GUS_MISC__SEND0_IOWR_ONLY_MASK 0x00008000L +//GUS_LATENCY_SAMPLING +#define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x2 +#define GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x3 +#define GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x4 +#define GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x5 +#define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x6 +#define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x7 +#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0x8 +#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0x9 +#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xa +#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xb +#define GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xc +#define GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x14 +#define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000004L +#define GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000008L +#define GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000010L +#define GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000020L +#define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000040L +#define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000080L +#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000100L +#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000200L +#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00000400L +#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00000800L +#define GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x000FF000L +#define GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x0FF00000L +//GUS_ERR_STATUS +#define GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define GUS_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define GUS_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define GUS_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//GUS_MISC2 +#define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0x0 +#define GUS_MISC2__CH_L1_RO_MASK__SHIFT 0x1 +#define GUS_MISC2__SA0_L1_RO_MASK__SHIFT 0x2 +#define GUS_MISC2__SA1_L1_RO_MASK__SHIFT 0x3 +#define GUS_MISC2__SA2_L1_RO_MASK__SHIFT 0x4 +#define GUS_MISC2__SA3_L1_RO_MASK__SHIFT 0x5 +#define GUS_MISC2__CH_L1_PERF_MASK__SHIFT 0x6 +#define GUS_MISC2__SA0_L1_PERF_MASK__SHIFT 0x7 +#define GUS_MISC2__SA1_L1_PERF_MASK__SHIFT 0x8 +#define GUS_MISC2__SA2_L1_PERF_MASK__SHIFT 0x9 +#define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT 0xa +#define GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT 0xb +#define GUS_MISC2__L1_RET_CLKEN__SHIFT 0xc +#define GUS_MISC2__FGCLKEN_HIGH__SHIFT 0xd +#define GUS_MISC2__BLOCK_REQUESTS__SHIFT 0xe +#define GUS_MISC2__REQUESTS_BLOCKED__SHIFT 0xf +#define GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT 0x10 +#define GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT 0x11 +#define GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK__SHIFT 0x12 +#define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00000001L +#define GUS_MISC2__CH_L1_RO_MASK_MASK 0x00000002L +#define GUS_MISC2__SA0_L1_RO_MASK_MASK 0x00000004L +#define GUS_MISC2__SA1_L1_RO_MASK_MASK 0x00000008L +#define GUS_MISC2__SA2_L1_RO_MASK_MASK 0x00000010L +#define GUS_MISC2__SA3_L1_RO_MASK_MASK 0x00000020L +#define GUS_MISC2__CH_L1_PERF_MASK_MASK 0x00000040L +#define GUS_MISC2__SA0_L1_PERF_MASK_MASK 0x00000080L +#define GUS_MISC2__SA1_L1_PERF_MASK_MASK 0x00000100L +#define GUS_MISC2__SA2_L1_PERF_MASK_MASK 0x00000200L +#define GUS_MISC2__SA3_L1_PERF_MASK_MASK 0x00000400L +#define GUS_MISC2__FP_ATOMICS_ENABLE_MASK 0x00000800L +#define GUS_MISC2__L1_RET_CLKEN_MASK 0x00001000L +#define GUS_MISC2__FGCLKEN_HIGH_MASK 0x00002000L +#define GUS_MISC2__BLOCK_REQUESTS_MASK 0x00004000L +#define GUS_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L +#define GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK_MASK 0x00010000L +#define GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK_MASK 0x00020000L +#define GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK_MASK 0x00040000L +//GUS_SDP_ENABLE +#define GUS_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define GUS_SDP_ENABLE__ENABLE_MASK 0x00000001L +//GUS_L1_CH0_CMD_IN +#define GUS_L1_CH0_CMD_IN__COUNT__SHIFT 0x0 +#define GUS_L1_CH0_CMD_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH0_CMD_OUT +#define GUS_L1_CH0_CMD_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_CH0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH0_DATA_IN +#define GUS_L1_CH0_DATA_IN__COUNT__SHIFT 0x0 +#define GUS_L1_CH0_DATA_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH0_DATA_OUT +#define GUS_L1_CH0_DATA_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_CH0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH0_DATA_U_IN +#define GUS_L1_CH0_DATA_U_IN__COUNT__SHIFT 0x0 +#define GUS_L1_CH0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH0_DATA_U_OUT +#define GUS_L1_CH0_DATA_U_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_CH0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH1_CMD_IN +#define GUS_L1_CH1_CMD_IN__COUNT__SHIFT 0x0 +#define GUS_L1_CH1_CMD_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH1_CMD_OUT +#define GUS_L1_CH1_CMD_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_CH1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH1_DATA_IN +#define GUS_L1_CH1_DATA_IN__COUNT__SHIFT 0x0 +#define GUS_L1_CH1_DATA_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH1_DATA_OUT +#define GUS_L1_CH1_DATA_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_CH1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH1_DATA_U_IN +#define GUS_L1_CH1_DATA_U_IN__COUNT__SHIFT 0x0 +#define GUS_L1_CH1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_CH1_DATA_U_OUT +#define GUS_L1_CH1_DATA_U_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_CH1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA0_CMD_IN +#define GUS_L1_SA0_CMD_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA0_CMD_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA0_CMD_OUT +#define GUS_L1_SA0_CMD_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA0_DATA_IN +#define GUS_L1_SA0_DATA_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA0_DATA_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA0_DATA_OUT +#define GUS_L1_SA0_DATA_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA0_DATA_U_IN +#define GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA0_DATA_U_OUT +#define GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA1_CMD_IN +#define GUS_L1_SA1_CMD_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA1_CMD_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA1_CMD_OUT +#define GUS_L1_SA1_CMD_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA1_DATA_IN +#define GUS_L1_SA1_DATA_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA1_DATA_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA1_DATA_OUT +#define GUS_L1_SA1_DATA_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA1_DATA_U_IN +#define GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA1_DATA_U_OUT +#define GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA2_CMD_IN +#define GUS_L1_SA2_CMD_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA2_CMD_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA2_CMD_OUT +#define GUS_L1_SA2_CMD_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA2_CMD_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA2_DATA_IN +#define GUS_L1_SA2_DATA_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA2_DATA_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA2_DATA_OUT +#define GUS_L1_SA2_DATA_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA2_DATA_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA2_DATA_U_IN +#define GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA2_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA2_DATA_U_OUT +#define GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA2_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA3_CMD_IN +#define GUS_L1_SA3_CMD_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA3_CMD_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA3_CMD_OUT +#define GUS_L1_SA3_CMD_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA3_CMD_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA3_DATA_IN +#define GUS_L1_SA3_DATA_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA3_DATA_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA3_DATA_OUT +#define GUS_L1_SA3_DATA_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA3_DATA_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA3_DATA_U_IN +#define GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT 0x0 +#define GUS_L1_SA3_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL +//GUS_L1_SA3_DATA_U_OUT +#define GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT 0x0 +#define GUS_L1_SA3_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL +//GUS_MISC3 +#define GUS_MISC3__FP_ATOMICS_LOG__SHIFT 0x0 +#define GUS_MISC3__CLEAR_LOG__SHIFT 0x1 +#define GUS_MISC3__FP_ATOMICS_LOG_MASK 0x00000001L +#define GUS_MISC3__CLEAR_LOG_MASK 0x00000002L +//GUS_WRRSP_FIFO_CNTL +#define GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT 0x0 +#define GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK 0x0000003FL + + +// addressBlock: gc_gfxdec0 +//DB_RENDER_CONTROL +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT 0xe +#define DB_RENDER_CONTROL__OREO_MODE__SHIFT 0x10 +#define DB_RENDER_CONTROL__FORCE_OREO_MODE__SHIFT 0x12 +#define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER__SHIFT 0x13 +#define DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE__SHIFT 0x14 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L +#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK 0x00004000L +#define DB_RENDER_CONTROL__OREO_MODE_MASK 0x00030000L +#define DB_RENDER_CONTROL__FORCE_OREO_MODE_MASK 0x00040000L +#define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER_MASK 0x00080000L +#define DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE_MASK 0x00F00000L +//DB_COUNT_CONTROL +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x2 +#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x3 +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000004L +#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000008L +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L +//DB_DEPTH_VIEW +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_START_HI__SHIFT 0xb +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a +#define DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT 0x1e +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL +#define DB_DEPTH_VIEW__SLICE_START_HI_MASK 0x00001800L +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L +#define DB_DEPTH_VIEW__SLICE_MAX_HI_MASK 0xC0000000L +//DB_RENDER_OVERRIDE +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +//DB_RENDER_OVERRIDE2 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 +#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT 0x1b +#define DB_RENDER_OVERRIDE2__DISABLE_NOZ__SHIFT 0x1d +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L +#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK 0x18000000L +#define DB_RENDER_OVERRIDE2__DISABLE_NOZ_MASK 0x20000000L +//DB_HTILE_DATA_BASE +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_DEPTH_SIZE_XY +#define DB_DEPTH_SIZE_XY__X_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT 0x10 +#define DB_DEPTH_SIZE_XY__X_MAX_MASK 0x00003FFFL +#define DB_DEPTH_SIZE_XY__Y_MAX_MASK 0x3FFF0000L +//DB_DEPTH_BOUNDS_MIN +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL +//DB_DEPTH_BOUNDS_MAX +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL +//DB_STENCIL_CLEAR +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL +//DB_DEPTH_CLEAR +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL +//PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//DB_RESERVED_REG_2 +#define DB_RESERVED_REG_2__FIELD_1__SHIFT 0x0 +#define DB_RESERVED_REG_2__FIELD_2__SHIFT 0x4 +#define DB_RESERVED_REG_2__FIELD_3__SHIFT 0x8 +#define DB_RESERVED_REG_2__FIELD_4__SHIFT 0xd +#define DB_RESERVED_REG_2__FIELD_5__SHIFT 0xf +#define DB_RESERVED_REG_2__FIELD_6__SHIFT 0x11 +#define DB_RESERVED_REG_2__FIELD_7__SHIFT 0x13 +#define DB_RESERVED_REG_2__FIELD_8__SHIFT 0x1c +#define DB_RESERVED_REG_2__FIELD_1_MASK 0x0000000FL +#define DB_RESERVED_REG_2__FIELD_2_MASK 0x000000F0L +#define DB_RESERVED_REG_2__FIELD_3_MASK 0x00001F00L +#define DB_RESERVED_REG_2__FIELD_4_MASK 0x00006000L +#define DB_RESERVED_REG_2__FIELD_5_MASK 0x00018000L +#define DB_RESERVED_REG_2__FIELD_6_MASK 0x00060000L +#define DB_RESERVED_REG_2__FIELD_7_MASK 0x00180000L +#define DB_RESERVED_REG_2__FIELD_8_MASK 0xF0000000L +//DB_Z_INFO +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__SW_MODE__SHIFT 0x4 +#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0x9 +#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xb +#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_Z_INFO__RESERVED_FIELD_1__SHIFT 0xd +#define DB_Z_INFO__MAXMIP__SHIFT 0x10 +#define DB_Z_INFO__ITERATE_256__SHIFT 0x14 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL +#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L +#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00000600L +#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00000800L +#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_Z_INFO__RESERVED_FIELD_1_MASK 0x0000E000L +#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L +#define DB_Z_INFO__ITERATE_256_MASK 0x00100000L +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L +//DB_STENCIL_INFO +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 +#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0x9 +#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xb +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT 0xd +#define DB_STENCIL_INFO__ITERATE_256__SHIFT 0x14 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L +#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00000600L +#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00000800L +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK 0x0000E000L +#define DB_STENCIL_INFO__ITERATE_256_MASK 0x00100000L +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +//DB_Z_READ_BASE +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_READ_BASE +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_WRITE_BASE +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_WRITE_BASE +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_RESERVED_REG_1 +#define DB_RESERVED_REG_1__FIELD_1__SHIFT 0x0 +#define DB_RESERVED_REG_1__FIELD_2__SHIFT 0xb +#define DB_RESERVED_REG_1__FIELD_1_MASK 0x000007FFL +#define DB_RESERVED_REG_1__FIELD_2_MASK 0x003FF800L +//DB_RESERVED_REG_3 +#define DB_RESERVED_REG_3__FIELD_1__SHIFT 0x0 +#define DB_RESERVED_REG_3__FIELD_1_MASK 0x003FFFFFL +//DB_Z_READ_BASE_HI +#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_READ_BASE_HI +#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_Z_WRITE_BASE_HI +#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_WRITE_BASE_HI +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_HTILE_DATA_BASE_HI +#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_RMI_L2_CACHE_CONTROL +#define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0 +#define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2 +#define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4 +#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6 +#define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10 +#define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12 +#define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14 +#define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT 0x18 +#define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT 0x19 +#define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC__SHIFT 0x1a +#define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC__SHIFT 0x1b +#define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC__SHIFT 0x1c +#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC__SHIFT 0x1d +#define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L +#define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL +#define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L +#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L +#define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L +#define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L +#define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L +#define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK 0x01000000L +#define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK 0x02000000L +#define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC_MASK 0x04000000L +#define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC_MASK 0x08000000L +#define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC_MASK 0x10000000L +#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC_MASK 0x20000000L +//TA_BC_BASE_ADDR +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_BC_BASE_ADDR_HI +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//COHER_DEST_BASE_HI_0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_1 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_2 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_3 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_RULE +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL +//PA_SC_CLIPRECT_0_TL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_0_BR +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_TL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_BR +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_TL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_BR +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_TL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_BR +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_EDGERULE +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L +//PA_SU_HARDWARE_SCREEN_OFFSET +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L +//CB_TARGET_MASK +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L +//CB_SHADER_MASK +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L +//PA_SC_GENERIC_SCISSOR_TL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_GENERIC_SCISSOR_BR +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VPORT_SCISSOR_0_TL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_0_BR +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_1_TL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_1_BR +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_2_TL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_2_BR +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_3_TL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_3_BR +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_4_TL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_4_BR +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_5_TL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_5_BR +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_6_TL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_6_BR +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_7_TL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_7_BR +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_8_TL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_8_BR +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_9_TL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_9_BR +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_10_TL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_10_BR +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_11_TL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_11_BR +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_12_TL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_12_BR +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_13_TL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_13_BR +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_14_TL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_14_BR +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_15_TL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_15_BR +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_ZMIN_0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_1 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_1 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_2 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_2 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_3 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_3 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_4 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_4 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_5 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_5 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_6 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_6 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_7 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_7 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_8 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_8 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_9 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_9 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_10 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_10 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_11 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_11 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_12 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_12 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_13 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_13 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_14 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_14 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_15 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_15 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_RASTER_CONFIG +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0C000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L +//PA_SC_RASTER_CONFIG_1 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L +//PA_SC_SCREEN_EXTENT_CONTROL +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL +//PA_SC_TILE_STEERING_OVERRIDE +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT 0xc +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT 0x10 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT 0x14 +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK 0x00003000L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK 0x00030000L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK 0x00300000L +//CP_PERFMON_CNTX_CNTL +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +//CP_PIPEID +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x00000003L +//CP_RINGID +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_RINGID__RINGID_MASK 0x00000003L +//CP_VMID +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0x0000000FL +//CONTEXT_RESERVED_REG0 +#define CONTEXT_RESERVED_REG0__DATA__SHIFT 0x0 +#define CONTEXT_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//CONTEXT_RESERVED_REG1 +#define CONTEXT_RESERVED_REG1__DATA__SHIFT 0x0 +#define CONTEXT_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//PA_SC_VRS_OVERRIDE_CNTL +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT 0x0 +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE__SHIFT 0x4 +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE__SHIFT 0xc +#define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE__SHIFT 0xd +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0xe +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK 0x00000007L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE_MASK 0x000000F0L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE_MASK 0x00001000L +#define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE_MASK 0x00002000L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00004000L +//PA_SC_VRS_RATE_FEEDBACK_BASE +#define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VRS_RATE_FEEDBACK_BASE_EXT +#define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//PA_SC_VRS_RATE_FEEDBACK_SIZE_XY +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX_MASK 0x000007FFL +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX_MASK 0x07FF0000L +//PA_SC_VRS_RATE_CACHE_CNTL +#define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD__SHIFT 0x0 +#define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR__SHIFT 0x1 +#define PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY__SHIFT 0x2 +#define PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY__SHIFT 0x4 +#define PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY__SHIFT 0x6 +#define PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC__SHIFT 0x8 +#define PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC__SHIFT 0x9 +#define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD__SHIFT 0xa +#define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR__SHIFT 0xb +#define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD__SHIFT 0xc +#define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR__SHIFT 0xd +#define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD_MASK 0x00000001L +#define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR_MASK 0x00000002L +#define PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY_MASK 0x0000000CL +#define PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY_MASK 0x00000030L +#define PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY_MASK 0x000000C0L +#define PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC_MASK 0x00000100L +#define PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC_MASK 0x00000200L +#define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD_MASK 0x00000400L +#define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR_MASK 0x00000800L +#define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD_MASK 0x00001000L +#define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR_MASK 0x00002000L +//PA_SC_VRS_RATE_BASE +#define PA_SC_VRS_RATE_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VRS_RATE_BASE_EXT +#define PA_SC_VRS_RATE_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID__SHIFT 0x1c +#define PA_SC_VRS_RATE_BASE_EXT__BASE_256B_MASK 0x000000FFL +#define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID_MASK 0xF0000000L +//PA_SC_VRS_RATE_SIZE_XY +#define PA_SC_VRS_RATE_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_VRS_RATE_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_VRS_RATE_SIZE_XY__X_MAX_MASK 0x000007FFL +#define PA_SC_VRS_RATE_SIZE_XY__Y_MAX_MASK 0x07FF0000L +//VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL +//CB_RMI_GL2_CACHE_CONTROL +#define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x0 +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x2 +#define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14 +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 +#define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS__SHIFT 0x1a +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS__SHIFT 0x1b +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT 0x1f +#define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000003L +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x0000000CL +#define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L +#define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS_MASK 0x04000000L +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS_MASK 0x08000000L +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK 0x80000000L +//CB_BLEND_RED +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL +//CB_BLEND_GREEN +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL +//CB_BLEND_BLUE +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL +//CB_BLEND_ALPHA +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL +//CB_FDCC_CONTROL +#define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK__SHIFT 0x2 +#define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 +#define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 +#define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa +#define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc +#define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd +#define CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe +#define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK_MASK 0x0000007CL +#define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L +#define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L +#define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L +#define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L +#define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L +#define CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L +//CB_COVERAGE_OUT_CONTROL +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT 0x0 +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT 0x1 +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT 0x4 +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT 0x8 +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK 0x00000001L +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK 0x0000000EL +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK 0x00000030L +#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK 0x00000F00L +//DB_STENCIL_CONTROL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L +//DB_STENCILREFMASK +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL +#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L +//DB_STENCILREFMASK_BF +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L +//PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_1 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_1 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_1 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_1 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_1 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_1 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_2 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_2 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_2 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_2 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_2 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_2 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_3 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_3 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_3 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_3 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_3 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_3 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_4 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_4 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_4 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_4 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_4 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_4 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_5 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_5 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_5 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_5 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_5 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_5 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_6 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_6 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_6 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_6 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_6 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_6 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_7 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_7 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_7 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_7 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_7 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_7 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_8 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_8 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_8 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_8 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_8 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_8 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_9 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_9 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_9 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_9 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_9 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_9 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_10 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_10 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_10 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_10 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_10 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_10 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_11 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_11 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_11 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_11 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_11 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_11 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_12 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_12 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_12 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_12 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_12 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_12 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_13 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_13 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_13 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_13 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_13 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_13 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_14 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_14 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_14 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_14 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_14 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_14 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_15 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_15 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_15 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_15 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_15 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_15 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_X +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Y +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Z +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_W +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_X +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Y +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Z +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_W +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_X +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Y +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Z +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_W +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_X +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Y +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Z +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_W +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_X +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Y +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Z +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_W +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_X +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Y +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Z +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_W +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_PROG_NEAR_CLIP_Z +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_RATE_CNTL +#define PA_RATE_CNTL__VERTEX_RATE__SHIFT 0x0 +#define PA_RATE_CNTL__PRIM_RATE__SHIFT 0x4 +#define PA_RATE_CNTL__VERTEX_RATE_MASK 0x0000000FL +#define PA_RATE_CNTL__PRIM_RATE_MASK 0x000000F0L +//SPI_PS_INPUT_CNTL_0 +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_0__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_0__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_1 +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_1__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_1__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_2 +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_2__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_2__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_3 +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_3__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_3__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_4 +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_4__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_4__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_5 +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_5__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_5__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_6 +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_6__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_6__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_7 +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_7__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_7__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_8 +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_8__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_8__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_9 +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_9__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_9__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_10 +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_10__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_10__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_11 +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_11__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_11__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_12 +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_12__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_12__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_13 +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_13__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_13__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_14 +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_14__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_14__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_15 +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_15__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_15__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_16 +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_16__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_16__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_17 +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_17__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_17__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_18 +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_18__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_18__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_19 +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_19__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_19__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_20 +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_20__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_20__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_21 +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_21__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_21__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_22 +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_22__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_22__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_23 +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_23__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_23__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_24 +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_24__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_24__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_25 +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_25__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_25__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_26 +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_26__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_26__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_27 +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_27__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_27__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_28 +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_28__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_28__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_29 +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_29__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_29__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_30 +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_30__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_30__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_31 +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_31__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_31__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L +//SPI_VS_OUT_CONFIG +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 +#define SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT 0x7 +#define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT__SHIFT 0x8 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL +#define SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK 0x00000080L +#define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT_MASK 0x00001F00L +//SPI_PS_INPUT_ENA +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_PS_INPUT_ADDR +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_INTERP_CONTROL_0 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +//SPI_PS_IN_CONTROL +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 +#define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP__SHIFT 0x9 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT 0xf +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L +#define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP_MASK 0x00003E00L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +#define SPI_PS_IN_CONTROL__PS_W32_EN_MASK 0x00008000L +//SPI_BARYC_CNTL +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +//SPI_TMPRING_SIZE +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x07FFF000L +//SPI_GFX_SCRATCH_BASE_LO +#define SPI_GFX_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define SPI_GFX_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//SPI_GFX_SCRATCH_BASE_HI +#define SPI_GFX_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define SPI_GFX_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//SPI_SHADER_IDX_FORMAT +#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_POS_FORMAT +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK 0x000F0000L +//SPI_SHADER_Z_FORMAT +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_COL_FORMAT +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L +//SX_PS_DOWNCONVERT_CONTROL +#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT 0x0 +#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT 0x1 +#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT 0x2 +#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT 0x3 +#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT 0x4 +#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT 0x5 +#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT 0x6 +#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT 0x7 +#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK 0x00000001L +#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK 0x00000002L +#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK 0x00000004L +#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK 0x00000008L +#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK 0x00000010L +#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK 0x00000020L +#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK 0x00000040L +#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK 0x00000080L +//SX_PS_DOWNCONVERT +#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 +#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 +#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 +#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc +#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 +#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 +#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 +#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c +#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL +#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L +#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L +#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L +#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L +#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L +#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L +#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L +//SX_BLEND_OPT_EPSILON +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L +//SX_BLEND_OPT_CONTROL +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L +//SX_MRT0_BLEND_OPT +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT1_BLEND_OPT +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT2_BLEND_OPT +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT3_BLEND_OPT +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT4_BLEND_OPT +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT5_BLEND_OPT +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT6_BLEND_OPT +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT7_BLEND_OPT +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//CB_BLEND0_CONTROL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND1_CONTROL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND2_CONTROL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND3_CONTROL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND4_CONTROL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND5_CONTROL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND6_CONTROL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND7_CONTROL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//PA_CL_POINT_X_RAD +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_Y_RAD +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_SIZE +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_CULL_RAD +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//VGT_DMA_BASE_HI +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL +//VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL +//VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L +//VGT_EVENT_ADDRESS_REG +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL +//GE_MAX_OUTPUT_PER_SUBGROUP +#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT 0x0 +#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK 0x000003FFL +//DB_DEPTH_CONTROL +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L +//DB_EQAA +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +//CB_COLOR_CONTROL +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 +#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT 0x1 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L +#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK 0x00000002L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L +//DB_SHADER_CONTROL +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 +#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT 0x17 +#define DB_SHADER_CONTROL__OREO_BLEND_ENABLE__SHIFT 0x18 +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE__SHIFT 0x19 +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE__SHIFT 0x1a +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L +#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK 0x00800000L +#define DB_SHADER_CONTROL__OREO_BLEND_ENABLE_MASK 0x01000000L +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE_MASK 0x02000000L +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_MASK 0x1C000000L +//PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L +//PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 +#define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT 0x18 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK 0x01000000L +//PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +//PA_CL_VS_OUT_CNTL +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b +#define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT 0x1c +#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT 0x1d +#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT 0x1e +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK 0x10000000L +#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK 0x20000000L +#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK 0x40000000L +//PA_CL_NANINF_CNTL +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +//PA_SU_LINE_STIPPLE_CNTL +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +//PA_SU_LINE_STIPPLE_SCALE +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL +//PA_SU_PRIM_FILTER_CNTL +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +//PA_SU_SMALL_PRIM_FILTER_CNTL +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L +//PA_CL_NGG_CNTL +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT 0x2 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L +#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK 0x000003FCL +//PA_SU_OVER_RASTERIZATION_CNTL +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L +//PA_STEREO_CNTL +#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 +#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 +#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 +#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0x10 +#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0x13 +#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL +#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L +#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000F00L +#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00070000L +#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x00780000L +//PA_STATE_STEREO_X +#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 +#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL +//PA_CL_VRS_CNTL +#define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT 0x0 +#define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT 0x3 +#define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT 0x6 +#define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT 0x9 +#define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT 0xd +#define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT 0xe +#define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK 0x00000007L +#define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK 0x00000038L +#define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK 0x000001C0L +#define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK 0x00000E00L +#define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK 0x00002000L +#define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK 0x00004000L +//PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L +//PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L +//PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL +//PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L +//VGT_HOS_MAX_TESS_LEVEL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_MIN_TESS_LEVEL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL +//PA_SC_MODE_CNTL_0 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L +//PA_SC_MODE_CNTL_1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +//VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x0 +#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL +//IA_ENHANCE +#define IA_ENHANCE__MISC__SHIFT 0x0 +#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_DMA_MAX_SIZE +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL +//VGT_DMA_INDEX_TYPE +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa +#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb +#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000C0L +#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L +#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x00003800L +#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L +//WD_ENHANCE +#define WD_ENHANCE__MISC__SHIFT 0x0 +#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_EN +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L +//VGT_DMA_NUM_INSTANCES +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_RESET +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL +//VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//VGT_DRAW_PAYLOAD_CNTL +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 +#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT 0x3 +#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT 0x4 +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L +#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK 0x00000008L +#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK 0x00000010L +//VGT_ESGS_RING_ITEMSIZE +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_REUSE_OFF +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +//DB_HTILE_SURFACE +#define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT 0x0 +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 +#define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT 0x2 +#define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT 0x3 +#define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT 0x4 +#define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11 +#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 +#define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L +#define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L +#define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK 0x00000008L +#define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK 0x000003F0L +#define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK 0x0000FC00L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L +#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L +//DB_SRESULTS_COMPARE_STATE0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L +//DB_SRESULTS_COMPARE_STATE1 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L +//DB_PRELOAD_CONTROL +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 +#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL +#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L +//VGT_STRMOUT_DRAW_OPAQUE_OFFSET +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL +//VGT_GS_MAX_VERT_OUT +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL +//GE_NGG_SUBGRP_CNTL +#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT 0x0 +#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT 0x9 +#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK 0x000001FFL +#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK 0x0003FE00L +//VGT_TESS_DISTRIBUTION +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L +//VGT_SHADER_STAGES_EN +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 +#define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT 0x15 +#define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT 0x16 +#define VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT 0x17 +#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT 0x18 +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT 0x19 +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG__SHIFT 0x1a +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L +#define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK 0x00200000L +#define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK 0x00400000L +#define VGT_SHADER_STAGES_EN__VS_W32_EN_MASK 0x00800000L +#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK 0x01000000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK 0x02000000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG_MASK 0x04000000L +//VGT_LS_HS_CONFIG +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L +//VGT_TF_PARAM +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__NOT_USED__SHIFT 0x9 +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__DETECT_ONE__SHIFT 0x13 +#define VGT_TF_PARAM__DETECT_ZERO__SHIFT 0x14 +#define VGT_TF_PARAM__MTYPE__SHIFT 0x17 +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L +#define VGT_TF_PARAM__NOT_USED_MASK 0x00000200L +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003C00L +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L +#define VGT_TF_PARAM__DETECT_ONE_MASK 0x00080000L +#define VGT_TF_PARAM__DETECT_ZERO_MASK 0x00100000L +#define VGT_TF_PARAM__MTYPE_MASK 0x03800000L +//DB_ALPHA_TO_MASK +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +//PA_SU_POLY_OFFSET_DB_FMT_CNTL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +//PA_SU_POLY_OFFSET_CLAMP +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_GS_INSTANCE_CNT +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT 0x1f +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL +#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK 0x80000000L +//PA_SC_CENTROID_PRIORITY_0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L +//PA_SC_CENTROID_PRIORITY_1 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L +//PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L +//PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a +#define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING__SHIFT 0x1c +#define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER__SHIFT 0x1d +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L +#define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING_MASK 0x10000000L +#define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER_MASK 0x20000000L +//PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +//PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_MASK_X0Y0_X1Y0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L +//PA_SC_AA_MASK_X0Y1_X1Y1 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L +//PA_SC_SHADER_CONTROL +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 +#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT 0x5 +#define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x7 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L +#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK 0x00000060L +#define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x00000080L +//PA_SC_BINNER_CNTL_0 +#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT 0x1d +#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L +#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK 0x60000000L +//PA_SC_BINNER_CNTL_1 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L +//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT 0x19 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT 0x1b +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK 0x06000000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK 0x18000000L +//PA_SC_NGG_MODE_CNTL +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 +#define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT__SHIFT 0xc +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC__SHIFT 0xd +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0xe +#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT 0x10 +#define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x18 +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL +#define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT_MASK 0x00001000L +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC_MASK 0x00002000L +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00004000L +#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L +#define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0xFF000000L +//PA_SC_BINNER_CNTL_2 +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X__SHIFT 0x1 +#define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_2__ZPP_ENABLED__SHIFT 0xb +#define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED__SHIFT 0xc +#define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD__SHIFT 0xd +#define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION__SHIFT 0x15 +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X_MASK 0x00000001L +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X_MASK 0x00000002L +#define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN_MASK 0x00000780L +#define PA_SC_BINNER_CNTL_2__ZPP_ENABLED_MASK 0x00000800L +#define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED_MASK 0x00001000L +#define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD_MASK 0x001FE000L +#define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION_MASK 0x00200000L +//CB_COLOR0_BASE +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_VIEW +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR0_INFO +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR0_ATTRIB +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR0_FDCC_CONTROL +#define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR0_DCC_BASE +#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_BASE +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_VIEW +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR1_INFO +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR1_ATTRIB +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR1_FDCC_CONTROL +#define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR1_DCC_BASE +#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_BASE +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_VIEW +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR2_INFO +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR2_ATTRIB +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR2_FDCC_CONTROL +#define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR2_DCC_BASE +#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_BASE +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_VIEW +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR3_INFO +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR3_ATTRIB +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR3_FDCC_CONTROL +#define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR3_DCC_BASE +#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_BASE +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_VIEW +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR4_INFO +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR4_ATTRIB +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR4_FDCC_CONTROL +#define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR4_DCC_BASE +#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_BASE +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_VIEW +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR5_INFO +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR5_ATTRIB +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR5_FDCC_CONTROL +#define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR5_DCC_BASE +#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_BASE +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_VIEW +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR6_INFO +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR6_ATTRIB +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR6_FDCC_CONTROL +#define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR6_DCC_BASE +#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_BASE +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_VIEW +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x1a +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x00001FFFL +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x03FFE000L +#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x3C000000L +//CB_COLOR7_INFO +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +//CB_COLOR7_ATTRIB +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 +#define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 +#define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L +#define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L +#define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L +//CB_COLOR7_FDCC_CONTROL +#define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 +#define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 +#define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa +#define CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 +#define CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 +#define CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 +#define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L +#define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L +#define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L +#define CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +#define CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L +#define CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L +#define CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L +#define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +//CB_COLOR7_DCC_BASE +#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_BASE_EXT +#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_BASE_EXT +#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_BASE_EXT +#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_BASE_EXT +#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_BASE_EXT +#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_BASE_EXT +#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_BASE_EXT +#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_BASE_EXT +#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_DCC_BASE_EXT +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_DCC_BASE_EXT +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_DCC_BASE_EXT +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_DCC_BASE_EXT +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_DCC_BASE_EXT +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_DCC_BASE_EXT +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_DCC_BASE_EXT +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_DCC_BASE_EXT +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_ATTRIB2 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR1_ATTRIB2 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR2_ATTRIB2 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR3_ATTRIB2 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR4_ATTRIB2 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR5_ATTRIB2 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR6_ATTRIB2 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR7_ATTRIB2 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR0_ATTRIB3 +#define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR0_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L +//CB_COLOR1_ATTRIB3 +#define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR1_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L +//CB_COLOR2_ATTRIB3 +#define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR2_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L +//CB_COLOR3_ATTRIB3 +#define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR3_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L +//CB_COLOR4_ATTRIB3 +#define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR4_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L +//CB_COLOR5_ATTRIB3 +#define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR5_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L +//CB_COLOR6_ATTRIB3 +#define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR6_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L +//CB_COLOR7_ATTRIB3 +#define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT 0xd +#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe +#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e +#define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL +#define CB_COLOR7_ATTRIB3__META_LINEAR_MASK 0x00002000L +#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L +#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L + + +// addressBlock: gc_pfvf_cpdec +//CONFIG_RESERVED_REG0 +#define CONFIG_RESERVED_REG0__DATA__SHIFT 0x0 +#define CONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//CONFIG_RESERVED_REG1 +#define CONFIG_RESERVED_REG1__DATA__SHIFT 0x0 +#define CONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//CP_MEC_CNTL +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 +#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT 0x16 +#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT 0x17 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b +#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c +#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L +#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK 0x00400000L +#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK 0x00800000L +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L +#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L +#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L +//CP_ME_CNTL +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__PFP_PIPE0_DISABLE__SHIFT 0xc +#define CP_ME_CNTL__PFP_PIPE1_DISABLE__SHIFT 0xd +#define CP_ME_CNTL__ME_PIPE0_DISABLE__SHIFT 0xe +#define CP_ME_CNTL__ME_PIPE1_DISABLE__SHIFT 0xf +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__PFP_PIPE0_DISABLE_MASK 0x00001000L +#define CP_ME_CNTL__PFP_PIPE1_DISABLE_MASK 0x00002000L +#define CP_ME_CNTL__ME_PIPE0_DISABLE_MASK 0x00004000L +#define CP_ME_CNTL__ME_PIPE1_DISABLE_MASK 0x00008000L +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L +#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L +#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L +#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L + + +// addressBlock: gc_pfvf_grbmdec +//GRBM_GFX_CNTL +#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL__CTXID__SHIFT 0xb +#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L +#define GRBM_GFX_CNTL__CTXID_MASK 0x00003800L +//GRBM_NOWHERE +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_pfvf_padec +//PA_SC_VRS_SURFACE_CNTL +#define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 +#define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0x7 +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 +#define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE__SHIFT 0xd +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE__SHIFT 0xe +#define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf +#define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 +#define PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH__SHIFT 0x11 +#define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE__SHIFT 0x12 +#define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS__SHIFT 0x13 +#define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT__SHIFT 0x1a +#define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L +#define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00000080L +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L +#define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE_MASK 0x00002000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH_MASK 0x00020000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE_MASK 0x00040000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS_MASK 0x03F80000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT_MASK 0xFC000000L +//PA_SC_ENHANCE +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L +//PA_SC_ENHANCE_1 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 +#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 +#define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE__SHIFT 0x5 +#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 +#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 +#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L +#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L +#define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE_MASK 0x00000020L +#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L +#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L +#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L +//PA_SC_ENHANCE_2 +#define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE__SHIFT 0x0 +#define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x1 +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x2 +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT 0x3 +#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4 +#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5 +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7 +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8 +#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9 +#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa +#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb +#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc +#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe +#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf +#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT 0x10 +#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11 +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12 +#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT 0x15 +#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17 +#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a +#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b +#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT 0x1e +#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1f +#define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE_MASK 0x00000001L +#define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000002L +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000004L +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK 0x00000008L +#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L +#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L +#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L +#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L +#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L +#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L +#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L +#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L +#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK 0x00010000L +#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L +#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK 0x00200000L +#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L +#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L +#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L +#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK 0x40000000L +#define PA_SC_ENHANCE_2__RSVD_MASK 0x80000000L +//PA_SC_ENHANCE_3 +#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT 0x0 +#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST__SHIFT 0x2 +#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 +#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT 0x4 +#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT 0x5 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER__SHIFT 0x6 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER__SHIFT 0x7 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS__SHIFT 0x8 +#define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY__SHIFT 0x9 +#define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES__SHIFT 0xa +#define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION__SHIFT 0xb +#define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED__SHIFT 0xc +#define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0xd +#define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION__SHIFT 0xe +#define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN__SHIFT 0xf +#define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS__SHIFT 0x10 +#define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM__SHIFT 0x11 +#define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE__SHIFT 0x12 +#define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE__SHIFT 0x13 +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x14 +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x15 +#define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE__SHIFT 0x16 +#define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION__SHIFT 0x17 +#define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY__SHIFT 0x18 +#define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL__SHIFT 0x19 +#define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL__SHIFT 0x1a +#define PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL__SHIFT 0x1b +#define PA_SC_ENHANCE_3__ECO_SPARE0__SHIFT 0x1c +#define PA_SC_ENHANCE_3__ECO_SPARE1__SHIFT 0x1d +#define PA_SC_ENHANCE_3__ECO_SPARE2__SHIFT 0x1e +#define PA_SC_ENHANCE_3__ECO_SPARE3__SHIFT 0x1f +#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK 0x00000001L +#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST_MASK 0x00000004L +#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L +#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK 0x00000010L +#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK 0x00000020L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER_MASK 0x00000040L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_MASK 0x00000080L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS_MASK 0x00000100L +#define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY_MASK 0x00000200L +#define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES_MASK 0x00000400L +#define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION_MASK 0x00000800L +#define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED_MASK 0x00001000L +#define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00002000L +#define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION_MASK 0x00004000L +#define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN_MASK 0x00008000L +#define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS_MASK 0x00010000L +#define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM_MASK 0x00020000L +#define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE_MASK 0x00040000L +#define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE_MASK 0x00080000L +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00100000L +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00200000L +#define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE_MASK 0x00400000L +#define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION_MASK 0x00800000L +#define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY_MASK 0x01000000L +#define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL_MASK 0x02000000L +#define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL_MASK 0x04000000L +#define PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL_MASK 0x08000000L +#define PA_SC_ENHANCE_3__ECO_SPARE0_MASK 0x10000000L +#define PA_SC_ENHANCE_3__ECO_SPARE1_MASK 0x20000000L +#define PA_SC_ENHANCE_3__ECO_SPARE2_MASK 0x40000000L +#define PA_SC_ENHANCE_3__ECO_SPARE3_MASK 0x80000000L +//PA_SC_BINNER_CNTL_OVERRIDE +#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L +//PA_SC_PBB_OVERRIDE_FLAG +#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0 +#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1 +#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L +#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L +//PA_SC_DSM_CNTL +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L +//PA_SC_TILE_STEERING_CREST_OVERRIDE +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L +//PA_SC_FIFO_SIZE +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L +//PA_SC_IF_FIFO_SIZE +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L +//PA_SC_PACKER_WAVE_ID_CNTL +#define PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE__SHIFT 0x0 +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE__SHIFT 0xa +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN__SHIFT 0x10 +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE__SHIFT 0x11 +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN__SHIFT 0x17 +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x1f +#define PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE_MASK 0x000003FFL +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE_MASK 0x0000FC00L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN_MASK 0x00010000L +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE_MASK 0x007E0000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN_MASK 0x00800000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x80000000L +//PA_SC_ATM_CNTL +#define PA_SC_ATM_CNTL__SC_PC_IF_SIZE__SHIFT 0x0 +#define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN__SHIFT 0x7 +#define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x8 +#define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0x10 +#define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES__SHIFT 0x11 +#define PA_SC_ATM_CNTL__SC_PC_IF_SIZE_MASK 0x0000003FL +#define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN_MASK 0x00000080L +#define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0x0000FF00L +#define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00010000L +#define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES_MASK 0x00020000L +//PA_SC_PKR_WAVE_TABLE_CNTL +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL +//PA_SC_FORCE_EOV_MAX_CNTS +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L +//PA_SC_BINNER_EVENT_CNTL_0 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_1 +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_2 +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_3 +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L +//PA_SC_BINNER_TIMEOUT_COUNTER +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_PERF_CNTL_0 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L +//PA_SC_BINNER_PERF_CNTL_1 +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L +//PA_SC_BINNER_PERF_CNTL_2 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L +//PA_SC_BINNER_PERF_CNTL_3 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_P3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_TRAP_SCREEN_HV_LOCK +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_PH_INTERFACE_FIFO_SIZE +#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10 +#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL +#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L +//PA_PH_ENHANCE +#define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0 +#define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1 +#define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2 +#define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3 +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4 +#define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5 +#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6 +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7 +#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9 +#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa +#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT 0xd +#define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS__SHIFT 0xe +#define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON__SHIFT 0xf +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE__SHIFT 0x10 +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE__SHIFT 0x11 +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE__SHIFT 0x12 +#define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L +#define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L +#define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L +#define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L +#define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L +#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L +#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L +#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L +#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK 0x00002000L +#define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS_MASK 0x00004000L +#define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON_MASK 0x00008000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_MASK 0x00010000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE_MASK 0x00020000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE_MASK 0x00040000L +//PA_SC_VRS_SURFACE_CNTL_1 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE__SHIFT 0x0 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE__SHIFT 0x1 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE__SHIFT 0x2 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA__SHIFT 0x3 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL__SHIFT 0x4 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED__SHIFT 0x5 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT__SHIFT 0x6 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS__SHIFT 0x7 +#define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG__SHIFT 0x8 +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION__SHIFT 0xc +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE__SHIFT 0xf +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE__SHIFT 0x13 +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING__SHIFT 0x14 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0__SHIFT 0x15 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1__SHIFT 0x16 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2__SHIFT 0x17 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3__SHIFT 0x18 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4__SHIFT 0x19 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5__SHIFT 0x1a +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6__SHIFT 0x1b +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7__SHIFT 0x1c +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8__SHIFT 0x1d +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9__SHIFT 0x1e +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10__SHIFT 0x1f +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK 0x00000001L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE_MASK 0x00000002L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE_MASK 0x00000004L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA_MASK 0x00000008L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL_MASK 0x00000010L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED_MASK 0x00000020L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT_MASK 0x00000040L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS_MASK 0x00000080L +#define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG_MASK 0x00000100L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION_MASK 0x00001000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE_MASK 0x00008000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE_MASK 0x00080000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING_MASK 0x00100000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0_MASK 0x00200000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1_MASK 0x00400000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2_MASK 0x00800000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3_MASK 0x01000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4_MASK 0x02000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5_MASK 0x04000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6_MASK 0x08000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7_MASK 0x10000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8_MASK 0x20000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9_MASK 0x40000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10_MASK 0x80000000L + + +// addressBlock: gc_pfvf_sqdec +//SQ_RUNTIME_CONFIG +#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0 +#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L +//SQ_DEBUG_STS_GLOBAL +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY_MASK 0x00000002L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000FFF0L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0FFF0000L +//SQ_DEBUG_STS_GLOBAL2 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0_MASK 0x000000FFL +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1_MASK 0x0000FF00L +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE_MASK 0x00FF0000L +//SH_MEM_BASES +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL +#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L +//SH_MEM_CONFIG +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 +#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe +#define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12 +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x0000000CL +#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L +#define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L +//SQ_DEBUG +#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0 +#define SQ_DEBUG__SINGLE_ALU_OP__SHIFT 0x1 +#define SQ_DEBUG__WAIT_DEP_CTR_ZERO__SHIFT 0x2 +#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L +#define SQ_DEBUG__SINGLE_ALU_OP_MASK 0x00000002L +#define SQ_DEBUG__WAIT_DEP_CTR_ZERO_MASK 0x00000004L +//SQ_SHADER_TBA_LO +#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TBA_HI +#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f +#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL +#define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L +//SQ_SHADER_TMA_LO +#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TMA_HI +#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL + + +// addressBlock: gc_pfonly_cpdec +//CP_DEBUG_2 +#define CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE__SHIFT 0xc +#define CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE__SHIFT 0xd +#define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE__SHIFT 0xe +#define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE__SHIFT 0xf +#define CP_DEBUG_2__NOP_DISCARD_DISABLE__SHIFT 0x10 +#define CP_DEBUG_2__DC_INTERLEAVE_DISABLE__SHIFT 0x11 +#define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE__SHIFT 0x1b +#define CP_DEBUG_2__DC_FORCE_CLK_EN__SHIFT 0x1c +#define CP_DEBUG_2__DC_DISABLE_BROADCAST__SHIFT 0x1d +#define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE__SHIFT 0x1e +#define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE__SHIFT 0x1f +#define CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE_MASK 0x00001000L +#define CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE_MASK 0x00002000L +#define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE_MASK 0x00004000L +#define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE_MASK 0x00008000L +#define CP_DEBUG_2__NOP_DISCARD_DISABLE_MASK 0x00010000L +#define CP_DEBUG_2__DC_INTERLEAVE_DISABLE_MASK 0x00020000L +#define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE_MASK 0x08000000L +#define CP_DEBUG_2__DC_FORCE_CLK_EN_MASK 0x10000000L +#define CP_DEBUG_2__DC_DISABLE_BROADCAST_MASK 0x20000000L +#define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE_MASK 0x40000000L +#define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE_MASK 0x80000000L +//CP_FETCHER_SOURCE +#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 +#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x00000001L + + +// addressBlock: gc_pfonly_cpphqddec +//CP_HPD_MES_ROQ_OFFSETS +#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L +//CP_HPD_ROQ_OFFSETS +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L +//CP_HPD_STATUS0 +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT 0x1b +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1c +#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT 0x1e +#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK 0x08000000L +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x30000000L +#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK 0x40000000L +#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L + + +// addressBlock: gc_pfonly_didtdec +//DIDT_INDEX_AUTO_INCR_EN +#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0 +#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L +//DIDT_EDC_CTRL +#define DIDT_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0xa +#define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xe +#define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0xf +#define DIDT_EDC_CTRL__EDC_AVGDIV__SHIFT 0x10 +#define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL__SHIFT 0x14 +#define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS__SHIFT 0x15 +#define DIDT_EDC_CTRL__RLC_FORCE_STALL_EN__SHIFT 0x18 +#define DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL__SHIFT 0x19 +#define DIDT_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L +#define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x00003C00L +#define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00004000L +#define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00008000L +#define DIDT_EDC_CTRL__EDC_AVGDIV_MASK 0x000F0000L +#define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL_MASK 0x00100000L +#define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS_MASK 0x00E00000L +#define DIDT_EDC_CTRL__RLC_FORCE_STALL_EN_MASK 0x01000000L +#define DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL_MASK 0x02000000L +//DIDT_EDC_THROTTLE_CTRL +#define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN__SHIFT 0x0 +#define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN__SHIFT 0x1 +#define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN__SHIFT 0x2 +#define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN__SHIFT 0x3 +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN__SHIFT 0x4 +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE__SHIFT 0x5 +#define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN_MASK 0x00000001L +#define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN_MASK 0x00000002L +#define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN_MASK 0x00000004L +#define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN_MASK 0x00000008L +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN_MASK 0x00000010L +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE_MASK 0x000000E0L +//DIDT_EDC_THRESHOLD +#define DIDT_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_EDC_STALL_PATTERN_1_2 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_3_4 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_5_6 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_7 +#define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_EDC_STATUS +#define DIDT_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_EDC_DYNAMIC_THRESHOLD_RO +#define DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO__SHIFT 0x0 +#define DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO_MASK 0x00000001L +//DIDT_EDC_OVERFLOW +#define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_EDC_ROLLING_POWER_DELTA +#define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_IND_INDEX +#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 +#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL +//DIDT_IND_DATA +#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 +#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_pfonly_spidec +//SPI_GDBG_WAVE_CNTL +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH_MASK 0x00000002L +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18 +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L +//SPI_GDBG_WAVE_CNTL3 +#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c +#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L +#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L +//SPI_ARB_CNTL_0 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L +//SPI_FEATURE_CTRL +#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT 0x0 +#define SPI_FEATURE_CTRL__RA_PROBE_IGNORE__SHIFT 0x4 +#define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT__SHIFT 0x5 +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL__SHIFT 0xb +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL__SHIFT 0xd +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE__SHIFT 0xe +#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK 0x0000000FL +#define SPI_FEATURE_CTRL__RA_PROBE_IGNORE_MASK 0x00000010L +#define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT_MASK 0x000007E0L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL_MASK 0x00001800L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL_MASK 0x00002000L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE_MASK 0x00004000L +//SPI_SHADER_RSRC_LIMIT_CTRL +#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT 0x0 +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT 0x5 +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT 0xc +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT 0xd +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT 0x13 +#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT 0x14 +#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT 0x1c +#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT 0x1f +#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK 0x0000001FL +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK 0x00000FE0L +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK 0x00001000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK 0x0007E000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK 0x00080000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK 0x0FF00000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK 0x10000000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK 0x80000000L +//SPI_COMPUTE_WF_CTX_SAVE_STATUS +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY__SHIFT 0x3 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY__SHIFT 0x4 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY__SHIFT 0x5 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY__SHIFT 0x6 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY__SHIFT 0x7 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY__SHIFT 0x8 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY__SHIFT 0x9 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY__SHIFT 0xa +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY__SHIFT 0xb +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY__SHIFT 0xc +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY__SHIFT 0xd +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY__SHIFT 0xe +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY__SHIFT 0xf +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY__SHIFT 0x10 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY__SHIFT 0x11 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY__SHIFT 0x12 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY__SHIFT 0x13 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY__SHIFT 0x14 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY__SHIFT 0x15 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY__SHIFT 0x16 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY__SHIFT 0x17 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY__SHIFT 0x18 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY__SHIFT 0x19 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY__SHIFT 0x1a +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY__SHIFT 0x1b +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY__SHIFT 0x1c +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY__SHIFT 0x1d +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY_MASK 0x00000002L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY_MASK 0x00000008L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY_MASK 0x00000010L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY_MASK 0x00000020L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY_MASK 0x00000040L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY_MASK 0x00000080L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY_MASK 0x00000100L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY_MASK 0x00000200L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY_MASK 0x00000400L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY_MASK 0x00000800L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY_MASK 0x00001000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY_MASK 0x00002000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY_MASK 0x00004000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY_MASK 0x00008000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY_MASK 0x00010000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY_MASK 0x00020000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY_MASK 0x00040000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY_MASK 0x00080000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY_MASK 0x00100000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY_MASK 0x00200000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY_MASK 0x00400000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY_MASK 0x00800000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY_MASK 0x01000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY_MASK 0x02000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY_MASK 0x04000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY_MASK 0x08000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY_MASK 0x10000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY_MASK 0x20000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY_MASK 0x40000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY_MASK 0x80000000L + + +// addressBlock: gc_pfonly_tcpdec +//TCP_INVALIDATE +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_INVALIDATE__START_MASK 0x00000001L +//TCP_STATUS +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 +#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 +#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 +#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 +#define TCP_STATUS__READ_BUSY__SHIFT 0x6 +#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 +#define TCP_STATUS__VM_BUSY__SHIFT 0x8 +#define TCP_STATUS__MEMIF_BUSY__SHIFT 0x9 +#define TCP_STATUS__GCR_BUSY__SHIFT 0xa +#define TCP_STATUS__OFIFO_BUSY__SHIFT 0xb +#define TCP_STATUS__OFIFO_QUEUE_BUSY__SHIFT 0xc +#define TCP_STATUS__XNACK_PRT__SHIFT 0xf +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L +#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L +#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L +#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L +#define TCP_STATUS__READ_BUSY_MASK 0x00000040L +#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L +#define TCP_STATUS__VM_BUSY_MASK 0x00000100L +#define TCP_STATUS__MEMIF_BUSY_MASK 0x00000200L +#define TCP_STATUS__GCR_BUSY_MASK 0x00000400L +#define TCP_STATUS__OFIFO_BUSY_MASK 0x00000800L +#define TCP_STATUS__OFIFO_QUEUE_BUSY_MASK 0x00003000L +#define TCP_STATUS__XNACK_PRT_MASK 0x00008000L +//TCP_CNTL2 +#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 +#define TCP_CNTL2__TCP_FMT_MGCG_DISABLE__SHIFT 0x8 +#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9 +#define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa +#define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE__SHIFT 0xb +#define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT 0xc +#define TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT 0xd +#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT 0xe +#define TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT 0xf +#define TCP_CNTL2__POWER_OPT_DISABLE__SHIFT 0x10 +#define TCP_CNTL2__GCR_RSP_FGCG_DISABLE__SHIFT 0x11 +#define TCP_CNTL2__PERF_EN_OVERRIDE__SHIFT 0x12 +#define TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE__SHIFT 0x14 +#define TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE__SHIFT 0x15 +#define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE__SHIFT 0x16 +#define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE__SHIFT 0x17 +#define TCP_CNTL2__SPARE_BIT__SHIFT 0x1a +#define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE__SHIFT 0x1b +#define TCP_CNTL2__TCP_REQ_MGCG_DISABLE__SHIFT 0x1d +#define TCP_CNTL2__TCP_MISS_MGCG_DISABLE__SHIFT 0x1e +#define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING__SHIFT 0x1f +#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL +#define TCP_CNTL2__TCP_FMT_MGCG_DISABLE_MASK 0x00000100L +#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L +#define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE_MASK 0x00000400L +#define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE_MASK 0x00000800L +#define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE_MASK 0x00001000L +#define TCP_CNTL2__V64_COMBINE_ENABLE_MASK 0x00002000L +#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK 0x00004000L +#define TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK 0x00008000L +#define TCP_CNTL2__POWER_OPT_DISABLE_MASK 0x00010000L +#define TCP_CNTL2__GCR_RSP_FGCG_DISABLE_MASK 0x00020000L +#define TCP_CNTL2__PERF_EN_OVERRIDE_MASK 0x000C0000L +#define TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE_MASK 0x00100000L +#define TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE_MASK 0x00200000L +#define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE_MASK 0x00400000L +#define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE_MASK 0x00800000L +#define TCP_CNTL2__SPARE_BIT_MASK 0x04000000L +#define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE_MASK 0x18000000L +#define TCP_CNTL2__TCP_REQ_MGCG_DISABLE_MASK 0x20000000L +#define TCP_CNTL2__TCP_MISS_MGCG_DISABLE_MASK 0x40000000L +#define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING_MASK 0x80000000L +//TCP_DEBUG_INDEX +#define TCP_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define TCP_DEBUG_INDEX__INDEX_MASK 0x0000001FL +//TCP_DEBUG_DATA +#define TCP_DEBUG_DATA__DATA__SHIFT 0x0 +#define TCP_DEBUG_DATA__DATA_MASK 0x0003FFFFL + + +// addressBlock: gc_pfonly_gdsdec +//GDS_ENHANCE2 +#define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT__SHIFT 0x0 +#define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE__SHIFT 0x1 +#define GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT__SHIFT 0x2 +#define GDS_ENHANCE2__UNUSED__SHIFT 0x3 +#define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT_MASK 0x00000001L +#define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE_MASK 0x00000002L +#define GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT_MASK 0x00000004L +#define GDS_ENHANCE2__UNUSED_MASK 0xFFFFFFF8L +//GDS_OA_CGPG_RESTORE +#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 +#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 +#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc +#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 +#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 +#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL +#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L +#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L +#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L +#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L + + +// addressBlock: gc_pfonly_utcl1dec +//UTCL1_CTRL_0 +#define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE__SHIFT 0x0 +#define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE__SHIFT 0x1 +#define UTCL1_CTRL_0__RESERVED_0__SHIFT 0x2 +#define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS__SHIFT 0x3 +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS__SHIFT 0x9 +#define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE__SHIFT 0xd +#define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE__SHIFT 0xe +#define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xf +#define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID__SHIFT 0x10 +#define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0x11 +#define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT 0x12 +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT 0x13 +#define UTCL1_CTRL_0__GCRD_FGCG_DISABLE__SHIFT 0x14 +#define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE__SHIFT 0x15 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x16 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT 0x17 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x18 +#define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL__SHIFT 0x19 +#define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1b +#define UTCL1_CTRL_0__RESERVED_1__SHIFT 0x1d +#define UTCL1_CTRL_0__MH_SPARE0__SHIFT 0x1e +#define UTCL1_CTRL_0__RESERVED_2__SHIFT 0x1f +#define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE_MASK 0x00000001L +#define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE_MASK 0x00000002L +#define UTCL1_CTRL_0__RESERVED_0_MASK 0x00000004L +#define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_MASK 0x000001F8L +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS_MASK 0x00001E00L +#define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE_MASK 0x00002000L +#define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE_MASK 0x00004000L +#define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00008000L +#define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID_MASK 0x00010000L +#define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00020000L +#define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK 0x00040000L +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK 0x00080000L +#define UTCL1_CTRL_0__GCRD_FGCG_DISABLE_MASK 0x00100000L +#define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE_MASK 0x00200000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00400000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK 0x00800000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x01000000L +#define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL_MASK 0x06000000L +#define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE_MASK 0x18000000L +#define UTCL1_CTRL_0__RESERVED_1_MASK 0x20000000L +#define UTCL1_CTRL_0__MH_SPARE0_MASK 0x40000000L +#define UTCL1_CTRL_0__RESERVED_2_MASK 0x80000000L +//UTCL1_UTCL0_INVREQ_DISABLE +#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0 +#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0xFFFFFFFFL +//UTCL1_CTRL_2 +#define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD__SHIFT 0x0 +#define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE__SHIFT 0x4 +#define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM__SHIFT 0xa +#define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE__SHIFT 0xb +#define UTCL1_CTRL_2__UTCL1_SPARE0__SHIFT 0xc +#define UTCL1_CTRL_2__UTCL1_SPARE1__SHIFT 0xd +#define UTCL1_CTRL_2__RESERVED__SHIFT 0xe +#define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD_MASK 0x0000000FL +#define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE_MASK 0x000003F0L +#define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM_MASK 0x00000400L +#define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE_MASK 0x00000800L +#define UTCL1_CTRL_2__UTCL1_SPARE0_MASK 0x00001000L +#define UTCL1_CTRL_2__UTCL1_SPARE1_MASK 0x00002000L +#define UTCL1_CTRL_2__RESERVED_MASK 0xFFFFC000L +//UTCL1_FIFO_SIZING +#define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH__SHIFT 0x0 +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW__SHIFT 0x3 +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH__SHIFT 0x10 +#define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH_MASK 0x00000007L +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW_MASK 0x0000FFF8L +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH_MASK 0xFFFF0000L +//GCRD_SA0_TARGETS_DISABLE +#define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE__SHIFT 0x0 +#define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE_MASK 0x0007FFFFL +//GCRD_SA1_TARGETS_DISABLE +#define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE__SHIFT 0x0 +#define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE_MASK 0x0007FFFFL +//GCRD_CREDIT_SAFE +#define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG__SHIFT 0x0 +#define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG__SHIFT 0x4 +#define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG_MASK 0x00000007L +#define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG_MASK 0x00000070L + + +// addressBlock: gc_pfonly_pmmdec +//GCR_GENERAL_CNTL +#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0 +#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1 +#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2 +#define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3 +#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4 +#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6 +#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7 +#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8 +#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9 +#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa +#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd +#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe +#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf +#define GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT 0x10 +#define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14 +#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L +#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L +#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L +#define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L +#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L +#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L +#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L +#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L +#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L +#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L +#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L +#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L +#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L +#define GCR_GENERAL_CNTL__DISABLE_FGCG_MASK 0x00010000L +#define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L +//GCR_CMD_STATUS +#define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0 +#define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x13 +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17 +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18 +#define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c +#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e +#define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f +#define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL +#define GCR_CMD_STATUS__GCR_SRC_MASK 0x00380000L +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L +#define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L +#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L +#define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L +//GCR_SPARE +#define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1 +#define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2 +#define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3 +#define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4 +#define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5 +#define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6 +#define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define GCR_SPARE__UTCL2_REQ_CREDIT__SHIFT 0x8 +#define GCR_SPARE__GCRD_GL2A_REQ_CREDIT__SHIFT 0x10 +#define GCR_SPARE__GCRD_SE_REQ_CREDIT__SHIFT 0x14 +#define GCR_SPARE__SPARE_BIT_31_24__SHIFT 0x18 +#define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L +#define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L +#define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L +#define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L +#define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L +#define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L +#define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define GCR_SPARE__UTCL2_REQ_CREDIT_MASK 0x0000FF00L +#define GCR_SPARE__GCRD_GL2A_REQ_CREDIT_MASK 0x000F0000L +#define GCR_SPARE__GCRD_SE_REQ_CREDIT_MASK 0x00F00000L +#define GCR_SPARE__SPARE_BIT_31_24_MASK 0xFF000000L +//PMM_CNTL2 +#define PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE__SHIFT 0x18 +#define PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE__SHIFT 0x19 +#define PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE__SHIFT 0x1a +#define PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE__SHIFT 0x1e +#define PMM_CNTL2__RESERVED__SHIFT 0x1f +#define PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE_MASK 0x01000000L +#define PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE_MASK 0x02000000L +#define PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE_MASK 0x3C000000L +#define PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE_MASK 0x40000000L +#define PMM_CNTL2__RESERVED_MASK 0x80000000L + + +// addressBlock: gc_sedcdec +//SEDC_GL1_GL2_OVERRIDES +#define SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_REQ_CREDITS__SHIFT 0x0 +#define SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_DATA_CREDITS__SHIFT 0x8 +#define SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_OUT_CLK_OVERRIDE__SHIFT 0x10 +#define SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_REQ_CREDITS_MASK 0x0000003FL +#define SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_DATA_CREDITS_MASK 0x00003F00L +#define SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_OUT_CLK_OVERRIDE_MASK 0x00010000L + + +// addressBlock: gc_pfonly_gccacdec +//GC_CAC_CTRL_1 +#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 +#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL +#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L +//GC_CAC_CTRL_2 +#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x1 +#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x2 +#define GC_CAC_CTRL_2__TOGGLE_EN__SHIFT 0x3 +#define GC_CAC_CTRL_2__INTR_EN__SHIFT 0x4 +#define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL__SHIFT 0x5 +#define GC_CAC_CTRL_2__SE_AGGR_ACC_EN__SHIFT 0x6 +#define GC_CAC_CTRL_2__GC_AGGR_ACC_EN__SHIFT 0xe +#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000002L +#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000004L +#define GC_CAC_CTRL_2__TOGGLE_EN_MASK 0x00000008L +#define GC_CAC_CTRL_2__INTR_EN_MASK 0x00000010L +#define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL_MASK 0x00000020L +#define GC_CAC_CTRL_2__SE_AGGR_ACC_EN_MASK 0x00003FC0L +#define GC_CAC_CTRL_2__GC_AGGR_ACC_EN_MASK 0x00004000L +//GC_CAC_AGGR_LOWER +#define GC_CAC_AGGR_LOWER__GC_AGGR_31_0__SHIFT 0x0 +#define GC_CAC_AGGR_LOWER__GC_AGGR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_UPPER +#define GC_CAC_AGGR_UPPER__GC_AGGR_63_32__SHIFT 0x0 +#define GC_CAC_AGGR_UPPER__GC_AGGR_63_32_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_LOWER +#define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0__SHIFT 0x0 +#define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_UPPER +#define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32__SHIFT 0x0 +#define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_LOWER +#define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0__SHIFT 0x0 +#define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_UPPER +#define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32__SHIFT 0x0 +#define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32_MASK 0xFFFFFFFFL +//SE2_CAC_AGGR_LOWER +#define SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0__SHIFT 0x0 +#define SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0_MASK 0xFFFFFFFFL +//SE2_CAC_AGGR_UPPER +#define SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32__SHIFT 0x0 +#define SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32_MASK 0xFFFFFFFFL +//SE3_CAC_AGGR_LOWER +#define SE3_CAC_AGGR_LOWER__SE3_AGGR_31_0__SHIFT 0x0 +#define SE3_CAC_AGGR_LOWER__SE3_AGGR_31_0_MASK 0xFFFFFFFFL +//SE3_CAC_AGGR_UPPER +#define SE3_CAC_AGGR_UPPER__SE3_AGGR_63_32__SHIFT 0x0 +#define SE3_CAC_AGGR_UPPER__SE3_AGGR_63_32_MASK 0xFFFFFFFFL +//SE4_CAC_AGGR_LOWER +#define SE4_CAC_AGGR_LOWER__SE4_AGGR_31_0__SHIFT 0x0 +#define SE4_CAC_AGGR_LOWER__SE4_AGGR_31_0_MASK 0xFFFFFFFFL +//SE4_CAC_AGGR_UPPER +#define SE4_CAC_AGGR_UPPER__SE4_AGGR_63_32__SHIFT 0x0 +#define SE4_CAC_AGGR_UPPER__SE4_AGGR_63_32_MASK 0xFFFFFFFFL +//SE5_CAC_AGGR_LOWER +#define SE5_CAC_AGGR_LOWER__SE5_AGGR_31_0__SHIFT 0x0 +#define SE5_CAC_AGGR_LOWER__SE5_AGGR_31_0_MASK 0xFFFFFFFFL +//SE5_CAC_AGGR_UPPER +#define SE5_CAC_AGGR_UPPER__SE5_AGGR_63_32__SHIFT 0x0 +#define SE5_CAC_AGGR_UPPER__SE5_AGGR_63_32_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_GFXCLK_CYCLE +#define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_GFXCLK_CYCLE +#define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_GFXCLK_CYCLE +#define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE2_CAC_AGGR_GFXCLK_CYCLE +#define SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE3_CAC_AGGR_GFXCLK_CYCLE +#define SE3_CAC_AGGR_GFXCLK_CYCLE__SE3_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE3_CAC_AGGR_GFXCLK_CYCLE__SE3_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE4_CAC_AGGR_GFXCLK_CYCLE +#define SE4_CAC_AGGR_GFXCLK_CYCLE__SE4_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE4_CAC_AGGR_GFXCLK_CYCLE__SE4_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE5_CAC_AGGR_GFXCLK_CYCLE +#define SE5_CAC_AGGR_GFXCLK_CYCLE__SE5_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE5_CAC_AGGR_GFXCLK_CYCLE__SE5_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//GC_EDC_CTRL +#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xa +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xb +#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf +#define GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0x10 +#define GC_EDC_CTRL__EDC_AVGDIV__SHIFT 0x11 +#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT 0x15 +#define GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT 0x18 +#define GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT 0x19 +#define GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT 0x1a +#define GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT 0x1b +#define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS__SHIFT 0x1c +#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00007800L +#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L +#define GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00010000L +#define GC_EDC_CTRL__EDC_AVGDIV_MASK 0x001E0000L +#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK 0x00E00000L +#define GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK 0x01000000L +#define GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK 0x02000000L +#define GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK 0x04000000L +#define GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK 0x08000000L +#define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS_MASK 0xF0000000L +//GC_EDC_THRESHOLD +#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//GC_EDC_STRETCH_CTRL +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT 0x0 +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT 0x1 +#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT 0xa +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK 0x00000001L +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK 0x000003FEL +#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK 0x0007FC00L +//GC_EDC_STRETCH_THRESHOLD +#define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT 0x0 +#define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK 0xFFFFFFFFL +//EDC_HYSTERESIS_CNTL +#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER__SHIFT 0x8 +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN__SHIFT 0x10 +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE__SHIFT 0x11 +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE__SHIFT 0x14 +#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER_MASK 0x0000FF00L +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN_MASK 0x00010000L +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE_MASK 0x000E0000L +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE_MASK 0x00100000L +//GC_THROTTLE_CTRL +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 +#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 +#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT 0x3 +#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x4 +#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x5 +#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x6 +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x7 +#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x8 +#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT 0x9 +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0xb +#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT 0xc +#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0xd +#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x17 +#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x18 +#define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT 0x1d +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT 0x1e +#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT 0x1f +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L +#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L +#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK 0x00000008L +#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000010L +#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000020L +#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000040L +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000080L +#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000100L +#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK 0x00000200L +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000400L +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000800L +#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK 0x00001000L +#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK 0x007FE000L +#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00800000L +#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x1F000000L +#define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK 0x20000000L +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK 0x40000000L +#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK 0x80000000L +//GC_THROTTLE_CTRL1 +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa +#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0xd +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0xe +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x12 +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x17 +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x1a +#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT 0x1e +#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT 0x1f +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L +#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00002000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0003C000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK 0x007C0000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x03800000L +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x0C000000L +#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK 0x40000000L +#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK 0x80000000L +//PCC_STALL_PATTERN_CTRL +#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT 0x0 +#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa +#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT 0xf +#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT 0x18 +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT 0x19 +#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT 0x1a +#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK 0x000003FFL +#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK 0x00007C00L +#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK 0x000F8000L +#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK 0x01000000L +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK 0x02000000L +#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK 0x04000000L +//PWRBRK_STALL_PATTERN_CTRL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L +//PCC_STALL_PATTERN_1_2 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_3_4 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_5_6 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_7 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL +//PWRBRK_STALL_PATTERN_1_2 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_3_4 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_5_6 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_7 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_STALL_PATTERN_CTRL +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN__SHIFT 0x0 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST__SHIFT 0x1 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x3 +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN__SHIFT 0x7 +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE__SHIFT 0x8 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN_MASK 0x00000001L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST_MASK 0x00000002L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x00000078L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN_MASK 0x00000080L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE_MASK 0x00000700L +//DIDT_STALL_PATTERN_1_2 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_3_4 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_5_6 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_7 +#define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +//PCC_PWRBRK_HYSTERESIS_CTRL +#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT 0x0 +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x8 +#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK 0x000000FFL +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x0000FF00L +//EDC_STRETCH_PERF_COUNTER +#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT 0x0 +#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_UNSTRETCH_PERF_COUNTER +#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT 0x0 +#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_STRETCH_NUM_PERF_COUNTER +#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT 0x0 +#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK 0xFFFFFFFFL +//GC_EDC_STATUS +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 +#define GC_EDC_STATUS__GPIO_IN_0__SHIFT 0x3 +#define GC_EDC_STATUS__GPIO_IN_1__SHIFT 0x4 +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L +#define GC_EDC_STATUS__GPIO_IN_0_MASK 0x00000008L +#define GC_EDC_STATUS__GPIO_IN_1_MASK 0x00000010L +//GC_EDC_OVERFLOW +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//GC_EDC_ROLLING_POWER_DELTA +#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//GC_THROTTLE_STATUS +#define GC_THROTTLE_STATUS__FSM_STATE__SHIFT 0x0 +#define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT 0x4 +#define GC_THROTTLE_STATUS__FSM_STATE_MASK 0x0000000FL +#define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK 0x000001F0L +//EDC_PERF_COUNTER +#define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 +#define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL +//PCC_PERF_COUNTER +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL +//PWRBRK_PERF_COUNTER +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_HYSTERESIS_STAT +#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 +#define EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT 0x8 +#define EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW__SHIFT 0x9 +#define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL__SHIFT 0xa +#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL +#define EDC_HYSTERESIS_STAT__EDC_STATUS_MASK 0x00000100L +#define EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW_MASK 0x00000200L +#define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL_MASK 0x00000400L +//GC_CAC_WEIGHT_CP_0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CP_1 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_EA_0 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_EA_1 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_EA_2 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_1 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_2 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_3 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_4 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_0 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_1 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_2 +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_UTCL2_WALKER_0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_WALKER_1 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_WALKER_2 +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_GDS_0 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GDS_1 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GDS_2 +#define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_GE_0 +#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GE_1 +#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GE_2 +#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GE_3 +#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GE_4 +#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GE_5 +#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10__SHIFT 0x0 +#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11__SHIFT 0x10 +#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GE_6 +#define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12__SHIFT 0x0 +#define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_PMM_0 +#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_GL2C_0 +#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GL2C_1 +#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GL2C_2 +#define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_PH_0 +#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_PH_1 +#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_PH_2 +#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_PH_3 +#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_0 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_1 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_2 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_3 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_4 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_5 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CHC_0 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CHC_1 +#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_GUS_0 +#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GUS_1 +#define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_RLC_0 +#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_GRBM_0 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1_MASK 0xFFFF0000L +//GC_EDC_CLK_MONITOR_CTRL +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN__SHIFT 0x0 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT 0x1 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT 0x5 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN_MASK 0x00000001L +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK 0x0000001EL +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK 0x0001FFE0L +//GC_CAC_IND_INDEX +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//GC_CAC_IND_DATA +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL +//SE_CAC_CTRL_1 +#define SE_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define SE_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 +#define SE_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL +#define SE_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L +//SE_CAC_CTRL_2 +#define SE_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define SE_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x1 +#define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE__SHIFT 0x2 +#define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x3 +#define SE_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define SE_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000002L +#define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE_MASK 0x00000004L +#define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000008L +//SE_CAC_WEIGHT_TA_0 +#define SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_TD_0 +#define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TD_1 +#define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TD_2 +#define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TD_3 +#define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TD_4 +#define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT 0x0 +#define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT 0x10 +#define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TD_5 +#define SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10__SHIFT 0x0 +#define SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_TCP_0 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_1 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_2 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_3 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_0 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_1 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_2 +#define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_SP_0 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SP_1 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_LDS_0 +#define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS_1 +#define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS_2 +#define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS_3 +#define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQC_0 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQC_1 +#define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_CU_0 +#define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_BCI_0 +#define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_0 +#define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_1 +#define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_2 +#define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_3 +#define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_4 +#define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_5 +#define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_6 +#define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_7 +#define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_8 +#define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_9 +#define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_10 +#define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_CB_11 +#define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22__SHIFT 0x0 +#define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23__SHIFT 0x10 +#define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_DB_0 +#define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_DB_1 +#define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_DB_2 +#define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_DB_3 +#define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_DB_4 +#define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8__SHIFT 0x0 +#define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9__SHIFT 0x10 +#define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_RMI_0 +#define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_RMI_1 +#define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SX_0 +#define SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_SXRB_0 +#define SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_UTCL1_0 +#define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_GL1C_0 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_GL1C_1 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_GL1C_2 +#define SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_SPI_0 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_1 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_2 +#define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_PC_0 +#define SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_PA_0 +#define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_PA_1 +#define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_PA_2 +#define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_PA_3 +#define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SC_0 +#define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SC_1 +#define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SC_2 +#define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SC_3 +#define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7_MASK 0xFFFF0000L +//SE_CAC_WINDOW_AGGR_VALUE +#define SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE__SHIFT 0x0 +#define SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE_MASK 0xFFFFFFFFL +//SE_CAC_WINDOW_GFXCLK_CYCLE +#define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE__SHIFT 0x0 +#define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE_MASK 0x000003FFL +//SE_CAC_IND_INDEX +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//SE_CAC_IND_DATA +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_pfonly2_spidec +//SPI_RESOURCE_RESERVE_CU_0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_1 +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_2 +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_3 +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_4 +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_5 +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_6 +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_7 +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_8 +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_9 +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_10 +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_11 +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_12 +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_13 +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_14 +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_15 +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_2 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_3 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_4 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_5 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_6 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_7 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_8 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_9 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_11 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_12 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_13 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_14 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_15 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L + + +// addressBlock: gc_gfxudec +//CP_EOP_DONE_ADDR_LO +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_EOP_DONE_ADDR_HI +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_EOP_DONE_DATA_LO +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_EOP_DONE_DATA_HI +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_LO +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_HI +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_ADDR_LO +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL +//CP_PIPE_STATS_ADDR_HI +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL +//CP_VGT_IAVERT_COUNT_LO +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAVERT_COUNT_HI +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_LO +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_HI +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_LO +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_HI +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_LO +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_HI +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_LO +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_HI +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_LO +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_HI +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_LO +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_HI +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_LO +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_HI +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_LO +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_HI +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_LO +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_HI +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_LO +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_HI +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_LO +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_HI +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_ASINVOC_COUNT_LO +#define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_ASINVOC_COUNT_HI +#define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_CONTROL +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x06000000L +//SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//SCRATCH_REG_ATOMIC +#define SCRATCH_REG_ATOMIC__IMMED__SHIFT 0x0 +#define SCRATCH_REG_ATOMIC__ID__SHIFT 0x18 +#define SCRATCH_REG_ATOMIC__reserved27__SHIFT 0x1b +#define SCRATCH_REG_ATOMIC__OP__SHIFT 0x1c +#define SCRATCH_REG_ATOMIC__reserved31__SHIFT 0x1f +#define SCRATCH_REG_ATOMIC__IMMED_MASK 0x00FFFFFFL +#define SCRATCH_REG_ATOMIC__ID_MASK 0x07000000L +#define SCRATCH_REG_ATOMIC__reserved27_MASK 0x08000000L +#define SCRATCH_REG_ATOMIC__OP_MASK 0x70000000L +#define SCRATCH_REG_ATOMIC__reserved31_MASK 0x80000000L +//SCRATCH_REG_CMPSWAP_ATOMIC +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT 0x0 +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT 0xc +#define SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT 0x18 +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT 0x1b +#define SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT 0x1c +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT 0x1f +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK 0x00000FFFL +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK 0x00FFF000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK 0x07000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK 0x08000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK 0x70000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK 0x80000000L +//CP_APPEND_DDID_CNT +#define CP_APPEND_DDID_CNT__DATA__SHIFT 0x0 +#define CP_APPEND_DDID_CNT__DATA_MASK 0x000000FFL +//CP_APPEND_DATA_HI +#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_HI +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_HI +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_LO +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_HI +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_LO +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_HI +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_LO +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_HI +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_APPEND_ADDR_LO +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL +//CP_APPEND_ADDR_HI +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__FENCE_SIZE__SHIFT 0x12 +#define CP_APPEND_ADDR_HI__PWS_ENABLE__SHIFT 0x13 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L +#define CP_APPEND_ADDR_HI__FENCE_SIZE_MASK 0x00040000L +#define CP_APPEND_ADDR_HI__PWS_ENABLE_MASK 0x00080000L +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x06000000L +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L +//CP_APPEND_DATA +#define CP_APPEND_DATA__DATA__SHIFT 0x0 +#define CP_APPEND_DATA__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_DATA_LO +#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_LO +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_LO +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_LO +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_LO +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_HI +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_HI +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_LO +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_LO +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_HI +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_HI +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_LO +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_LO +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_HI +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_HI +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_WADDR_LO +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_WADDR_HI +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__WRITE_CONFIRM__SHIFT 0x11 +#define CP_ME_MC_WADDR_HI__WRITE64__SHIFT 0x12 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WADDR_HI__VMID__SHIFT 0x18 +#define CP_ME_MC_WADDR_HI__RINGID__SHIFT 0x1c +#define CP_ME_MC_WADDR_HI__PRIVILEGE__SHIFT 0x1f +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_WADDR_HI__WRITE_CONFIRM_MASK 0x00020000L +#define CP_ME_MC_WADDR_HI__WRITE64_MASK 0x00040000L +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00C00000L +#define CP_ME_MC_WADDR_HI__VMID_MASK 0x0F000000L +#define CP_ME_MC_WADDR_HI__RINGID_MASK 0x30000000L +#define CP_ME_MC_WADDR_HI__PRIVILEGE_MASK 0x80000000L +//CP_ME_MC_WDATA_LO +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL +//CP_ME_MC_WDATA_HI +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_RADDR_LO +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_RADDR_HI +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__SIZE__SHIFT 0x10 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_RADDR_HI__VMID__SHIFT 0x18 +#define CP_ME_MC_RADDR_HI__PRIVILEGE__SHIFT 0x1f +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_RADDR_HI__SIZE_MASK 0x000F0000L +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00C00000L +#define CP_ME_MC_RADDR_HI__VMID_MASK 0x0F000000L +#define CP_ME_MC_RADDR_HI__PRIVILEGE_MASK 0x80000000L +//CP_SEM_WAIT_TIMER +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL +//CP_SIG_SEM_ADDR_LO +#define CP_SIG_SEM_ADDR_LO__SEM_PRIV__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_SIG_SEM_ADDR_LO__SEM_PRIV_MASK 0x00000001L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_SIG_SEM_ADDR_HI +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_WAIT_REG_MEM_TIMEOUT +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL +//CP_WAIT_SEM_ADDR_LO +#define CP_WAIT_SEM_ADDR_LO__SEM_PRIV__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_WAIT_SEM_ADDR_LO__SEM_PRIV_MASK 0x00000001L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_WAIT_SEM_ADDR_HI +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_DMA_PFP_CONTROL +#define CP_DMA_PFP_CONTROL__VMID__SHIFT 0x0 +#define CP_DMA_PFP_CONTROL__TMZ__SHIFT 0x4 +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT 0xf +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT 0x1b +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_CONTROL__VMID_MASK 0x0000000FL +#define CP_DMA_PFP_CONTROL__TMZ_MASK 0x00000010L +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L +#define CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK 0x00008000L +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L +#define CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK 0x08000000L +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_CONTROL +#define CP_DMA_ME_CONTROL__VMID__SHIFT 0x0 +#define CP_DMA_ME_CONTROL__TMZ__SHIFT 0x4 +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT 0xf +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT 0x1b +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_CONTROL__VMID_MASK 0x0000000FL +#define CP_DMA_ME_CONTROL__TMZ_MASK 0x00000010L +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L +#define CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK 0x00008000L +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L +#define CP_DMA_ME_CONTROL__DST_VOLATLE_MASK 0x08000000L +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_SRC_ADDR +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_SRC_ADDR_HI +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_DST_ADDR +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_DST_ADDR_HI +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_COMMAND +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_PFP_SRC_ADDR +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_SRC_ADDR_HI +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_DST_ADDR +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_DST_ADDR_HI +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_COMMAND +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_CNTL +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 +#define CP_DMA_CNTL__WATCH_CONTROL__SHIFT 0x1 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L +#define CP_DMA_CNTL__WATCH_CONTROL_MASK 0x00000002L +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x01FF0000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L +//CP_DMA_READ_TAGS +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +//CP_PFP_IB_CONTROL +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL +//CP_PFP_LOAD_CONTROL +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL__SHIFT 0x1f +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +#define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL_MASK 0x80000000L +//CP_SCRATCH_INDEX +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_SCRATCH_DATA +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_RB_OFFSET +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_IB2_OFFSET +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_BEGIN +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_END +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL +//CP_DMA_ME_CMD_ADDR_LO +#define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK 0x00000003L +#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_ME_CMD_ADDR_HI +#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_DMA_PFP_CMD_ADDR_LO +#define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK 0x00000003L +#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_PFP_CMD_ADDR_HI +#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_APPEND_CMD_ADDR_LO +#define CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_APPEND_CMD_ADDR_LO__RSVD_MASK 0x00000003L +#define CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_APPEND_CMD_ADDR_HI +#define CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_APPEND_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L +//UCONFIG_RESERVED_REG0 +#define UCONFIG_RESERVED_REG0__DATA__SHIFT 0x0 +#define UCONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//UCONFIG_RESERVED_REG1 +#define UCONFIG_RESERVED_REG1__DATA__SHIFT 0x0 +#define UCONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//CP_PA_MSPRIM_COUNT_LO +#define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_MSPRIM_COUNT_HI +#define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_GE_MSINVOC_COUNT_LO +#define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_GE_MSINVOC_COUNT_HI +#define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_IB2_CMD_BUFSZ +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_ST_CMD_BUFSZ +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB2_BASE_LO +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB2_BASE_HI +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_ST_BASE_LO +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL +//CP_ST_BASE_HI +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL +//CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL +//CP_EOP_DONE_EVENT_CNTL +#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c +#define CP_EOP_DONE_EVENT_CNTL__GLK_INV__SHIFT 0x1e +#define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE__SHIFT 0x1f +#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK 0x01FFF000L +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x06000000L +#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x08000000L +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L +#define CP_EOP_DONE_EVENT_CNTL__GLK_INV_MASK 0x40000000L +#define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE_MASK 0x80000000L +//CP_EOP_DONE_DATA_CNTL +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE__SHIFT 0x13 +#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT 0x14 +#define CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT 0x16 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE_MASK 0x00080000L +#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK 0x00300000L +#define CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK 0x00C00000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L +//CP_EOP_DONE_CNTX_ID +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_DB_BASE_LO +#define CP_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 +#define CP_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL +//CP_DB_BASE_HI +#define CP_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 +#define CP_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL +//CP_DB_BUFSZ +#define CP_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 +#define CP_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL +//CP_DB_CMD_BUFSZ +#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 +#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL +//CP_PFP_COMPLETION_STATUS +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_PRED_NOT_VISIBLE +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L +//CP_PFP_METADATA_BASE_ADDR +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_PFP_METADATA_BASE_ADDR_HI +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DRAW_INDX_INDR_ADDR +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DRAW_INDX_INDR_ADDR_HI +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DISPATCH_INDR_ADDR +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DISPATCH_INDR_ADDR_HI +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_BASE_ADDR +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_INDEX_BASE_ADDR_HI +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_TYPE +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +//CP_GDS_BKUP_ADDR +#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_GDS_BKUP_ADDR_HI +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_SAMPLE_STATUS +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L +//CP_ME_COHER_CNTL +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +//CP_ME_COHER_SIZE +#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_SIZE_HI +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_BASE +#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_BASE_HI +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_STATUS +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL +#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L +//RLC_GPM_PERF_COUNT_0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L +//RLC_GPM_PERF_COUNT_1 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L +//GRBM_GFX_INDEX +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SA_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX__SA_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +//VGT_PRIMITIVE_TYPE +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +//VGT_INDEX_TYPE +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L +//GE_MIN_VTX_INDX +#define GE_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define GE_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL +//GE_INDX_OFFSET +#define GE_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define GE_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL +//GE_MULTI_PRIM_IB_RESET_EN +#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 +#define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX__SHIFT 0x2 +#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L +#define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX_MASK 0x00000004L +//VGT_NUM_INDICES +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_NUM_INSTANCES +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_TF_RING_SIZE +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL +//VGT_HS_OFFCHIP_PARAM +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0xa +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000003FFL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000C00L +//VGT_TF_MEMORY_BASE +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL +//GE_MAX_VTX_INDX +#define GE_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define GE_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL +//VGT_INSTANCE_BASE_ID +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL +//GE_CNTL +#define GE_CNTL__PRIMS_PER_SUBGRP__SHIFT 0x0 +#define GE_CNTL__VERTS_PER_SUBGRP__SHIFT 0x9 +#define GE_CNTL__BREAK_SUBGRP_AT_EOI__SHIFT 0x12 +#define GE_CNTL__PACKET_TO_ONE_PA__SHIFT 0x13 +#define GE_CNTL__BREAK_PRIMGRP_AT_EOI__SHIFT 0x14 +#define GE_CNTL__PRIM_GRP_SIZE__SHIFT 0x15 +#define GE_CNTL__GCR_DISABLE__SHIFT 0x1e +#define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP__SHIFT 0x1f +#define GE_CNTL__PRIMS_PER_SUBGRP_MASK 0x000001FFL +#define GE_CNTL__VERTS_PER_SUBGRP_MASK 0x0003FE00L +#define GE_CNTL__BREAK_SUBGRP_AT_EOI_MASK 0x00040000L +#define GE_CNTL__PACKET_TO_ONE_PA_MASK 0x00080000L +#define GE_CNTL__BREAK_PRIMGRP_AT_EOI_MASK 0x00100000L +#define GE_CNTL__PRIM_GRP_SIZE_MASK 0x3FE00000L +#define GE_CNTL__GCR_DISABLE_MASK 0x40000000L +#define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP_MASK 0x80000000L +//GE_USER_VGPR1 +#define GE_USER_VGPR1__DATA__SHIFT 0x0 +#define GE_USER_VGPR1__DATA_MASK 0xFFFFFFFFL +//GE_USER_VGPR2 +#define GE_USER_VGPR2__DATA__SHIFT 0x0 +#define GE_USER_VGPR2__DATA_MASK 0xFFFFFFFFL +//GE_USER_VGPR3 +#define GE_USER_VGPR3__DATA__SHIFT 0x0 +#define GE_USER_VGPR3__DATA_MASK 0xFFFFFFFFL +//GE_STEREO_CNTL +#define GE_STEREO_CNTL__RT_SLICE__SHIFT 0x0 +#define GE_STEREO_CNTL__VIEWPORT__SHIFT 0x3 +#define GE_STEREO_CNTL__EN_STEREO__SHIFT 0x8 +#define GE_STEREO_CNTL__RT_SLICE_MASK 0x00000007L +#define GE_STEREO_CNTL__VIEWPORT_MASK 0x00000078L +#define GE_STEREO_CNTL__EN_STEREO_MASK 0x00000100L +//GE_PC_ALLOC +#define GE_PC_ALLOC__OVERSUB_EN__SHIFT 0x0 +#define GE_PC_ALLOC__NUM_PC_LINES__SHIFT 0x1 +#define GE_PC_ALLOC__OVERSUB_EN_MASK 0x00000001L +#define GE_PC_ALLOC__NUM_PC_LINES_MASK 0x000007FEL +//VGT_TF_MEMORY_BASE_HI +#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL +//GE_USER_VGPR_EN +#define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT 0x0 +#define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT 0x1 +#define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT 0x2 +#define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK 0x00000001L +#define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK 0x00000002L +#define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK 0x00000004L +//GE_GS_FAST_LAUNCH_WG_DIM +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X__SHIFT 0x0 +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y__SHIFT 0x10 +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X_MASK 0x0000FFFFL +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y_MASK 0xFFFF0000L +//GE_GS_FAST_LAUNCH_WG_DIM_1 +#define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z__SHIFT 0x0 +#define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z_MASK 0x0000FFFFL +//VGT_GS_OUT_PRIM_TYPE +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL +//PA_SU_LINE_STIPPLE_VALUE +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL +//PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L +//PA_SC_SCREEN_EXTENT_MIN_0 +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_0 +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MIN_1 +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_1 +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L +//PA_SC_P3D_TRAP_SCREEN_HV_EN +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_P3D_TRAP_SCREEN_H +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_V +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_COUNT +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_HV_EN +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_HP3D_TRAP_SCREEN_H +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_V +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_COUNT +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_HV_EN +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_TRAP_SCREEN_H +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_V +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_OCCURRENCE +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_COUNT +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//SQ_THREAD_TRACE_USERDATA_0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_1 +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_2 +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_3 +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_4 +#define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_5 +#define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_6 +#define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_7 +#define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK 0xFFFFFFFFL +//SQC_CACHES +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x00000001L +#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L +#define SQC_CACHES__INVALIDATE_MASK 0x00000004L +#define SQC_CACHES__COMPLETE_MASK 0x00010000L +//TA_CS_BC_BASE_ADDR +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_CS_BC_BASE_ADDR_HI +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//DB_OCCLUSION_COUNT0_LOW +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT0_HI +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT1_LOW +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT1_HI +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT2_LOW +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT2_HI +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT3_LOW +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT3_HI +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL +//GDS_RD_ADDR +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 +#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_DATA +#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 +#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL +//GDS_RD_BURST_ADDR +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_BURST_COUNT +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL +//GDS_RD_BURST_DATA +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL +//GDS_WR_ADDR +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_DATA +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WR_BURST_ADDR +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_BURST_DATA +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WRITE_COMPLETE +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL +//GDS_ATOM_CNTL +#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa +#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL +#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L +#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L +//GDS_ATOM_COMPLETE +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL +//GDS_ATOM_BASE +#define GDS_ATOM_BASE__BASE__SHIFT 0x0 +#define GDS_ATOM_BASE__UNUSED__SHIFT 0xc +#define GDS_ATOM_BASE__BASE_MASK 0x00000FFFL +#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFFF000L +//GDS_ATOM_SIZE +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0xd +#define GDS_ATOM_SIZE__SIZE_MASK 0x00001FFFL +#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFFE000L +//GDS_ATOM_OFFSET0 +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_OFFSET1 +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_DST +#define GDS_ATOM_DST__DST__SHIFT 0x0 +#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL +//GDS_ATOM_OP +#define GDS_ATOM_OP__OP__SHIFT 0x0 +#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OP__OP_MASK 0x000000FFL +#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_SRC0 +#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC0_U +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1 +#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1_U +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0 +#define GDS_ATOM_READ0__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0_U +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1 +#define GDS_ATOM_READ1__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1_U +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL +//GDS_GWS_RESOURCE_CNTL +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L +//GDS_GWS_RESOURCE +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd +#define GDS_GWS_RESOURCE__DED__SHIFT 0xe +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1d +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1e +#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1f +#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL +#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L +#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x1FFF0000L +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x20000000L +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x40000000L +#define GDS_GWS_RESOURCE__HALTED_MASK 0x80000000L +//GDS_GWS_RESOURCE_CNT +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_OA_CNTL +#define GDS_OA_CNTL__INDEX__SHIFT 0x0 +#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 +#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL +#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L +//GDS_OA_COUNTER +#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 +#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL +//GDS_OA_ADDRESS +#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 +#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10 +#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14 +#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18 +#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e +#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f +#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL +#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x000F0000L +#define GDS_OA_ADDRESS__CRAWLER_MASK 0x00F00000L +#define GDS_OA_ADDRESS__UNUSED_MASK 0x3F000000L +#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L +#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L +//GDS_OA_INCDEC +#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 +#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f +#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL +#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L +//GDS_OA_RING_SIZE +#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 +#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL +//GDS_STRMOUT_DWORDS_WRITTEN_0 +#define GDS_STRMOUT_DWORDS_WRITTEN_0__DATA__SHIFT 0x0 +#define GDS_STRMOUT_DWORDS_WRITTEN_0__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_DWORDS_WRITTEN_1 +#define GDS_STRMOUT_DWORDS_WRITTEN_1__DATA__SHIFT 0x0 +#define GDS_STRMOUT_DWORDS_WRITTEN_1__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_DWORDS_WRITTEN_2 +#define GDS_STRMOUT_DWORDS_WRITTEN_2__DATA__SHIFT 0x0 +#define GDS_STRMOUT_DWORDS_WRITTEN_2__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_DWORDS_WRITTEN_3 +#define GDS_STRMOUT_DWORDS_WRITTEN_3__DATA__SHIFT 0x0 +#define GDS_STRMOUT_DWORDS_WRITTEN_3__DATA_MASK 0xFFFFFFFFL +//GDS_GS_0 +#define GDS_GS_0__DATA__SHIFT 0x0 +#define GDS_GS_0__DATA_MASK 0xFFFFFFFFL +//GDS_GS_1 +#define GDS_GS_1__DATA__SHIFT 0x0 +#define GDS_GS_1__DATA_MASK 0xFFFFFFFFL +//GDS_GS_2 +#define GDS_GS_2__DATA__SHIFT 0x0 +#define GDS_GS_2__DATA_MASK 0xFFFFFFFFL +//GDS_GS_3 +#define GDS_GS_3__DATA__SHIFT 0x0 +#define GDS_GS_3__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_0_LO +#define GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_0_HI +#define GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_0_LO +#define GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_0_HI +#define GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_1_LO +#define GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_1_HI +#define GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_1_LO +#define GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_1_HI +#define GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_2_LO +#define GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_2_HI +#define GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_2_LO +#define GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_2_HI +#define GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_3_LO +#define GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_NEEDED_3_HI +#define GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_3_LO +#define GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA_MASK 0xFFFFFFFFL +//GDS_STRMOUT_PRIMS_WRITTEN_3_HI +#define GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA__SHIFT 0x0 +#define GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA_MASK 0xFFFFFFFFL +//SPI_CONFIG_CNTL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L +//SPI_CONFIG_CNTL_1 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf +#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10 +#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15 +#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT 0x16 +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT__SHIFT 0x17 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L +#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L +#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L +#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK 0x00400000L +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MASK 0xFF800000L +//SPI_CONFIG_CNTL_2 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE__SHIFT 0xa +#define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE__SHIFT 0xb +#define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY__SHIFT 0xc +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L +#define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE_MASK 0x00000400L +#define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE_MASK 0x00000800L +#define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY_MASK 0x0001F000L +//SPI_WAVE_LIMIT_CNTL +#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 +#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 +#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 +#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L +#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L +#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L +//SPI_GS_THROTTLE_CNTL1 +#define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL__SHIFT 0x0 +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE__SHIFT 0x4 +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE__SHIFT 0x8 +#define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD__SHIFT 0xc +#define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD__SHIFT 0x10 +#define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL__SHIFT 0x14 +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE__SHIFT 0x18 +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE__SHIFT 0x1c +#define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL_MASK 0x0000000FL +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE_MASK 0x000000F0L +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE_MASK 0x00000F00L +#define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD_MASK 0x0000F000L +#define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD_MASK 0x000F0000L +#define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL_MASK 0x00F00000L +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE_MASK 0x0F000000L +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE_MASK 0xF0000000L +//SPI_GS_THROTTLE_CNTL2 +#define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE__SHIFT 0x0 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD__SHIFT 0x2 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR__SHIFT 0x6 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1__SHIFT 0x8 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2__SHIFT 0xb +#define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD__SHIFT 0xe +#define SPI_GS_THROTTLE_CNTL2__PH_MODE__SHIFT 0x10 +#define SPI_GS_THROTTLE_CNTL2__RESERVED__SHIFT 0x11 +#define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE_MASK 0x00000003L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_MASK 0x0000003CL +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR_MASK 0x000000C0L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1_MASK 0x00000700L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2_MASK 0x00003800L +#define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD_MASK 0x0000C000L +#define SPI_GS_THROTTLE_CNTL2__PH_MODE_MASK 0x00010000L +#define SPI_GS_THROTTLE_CNTL2__RESERVED_MASK 0xFFFE0000L +//SPI_ATTRIBUTE_RING_BASE +#define SPI_ATTRIBUTE_RING_BASE__BASE__SHIFT 0x0 +#define SPI_ATTRIBUTE_RING_BASE__BASE_MASK 0xFFFFFFFFL +//SPI_ATTRIBUTE_RING_SIZE +#define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE__SHIFT 0x10 +#define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY__SHIFT 0x11 +#define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY__SHIFT 0x13 +#define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC__SHIFT 0x15 +#define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE__SHIFT 0x16 +#define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE_MASK 0x000000FFL +#define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE_MASK 0x00010000L +#define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY_MASK 0x00060000L +#define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY_MASK 0x00180000L +#define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC_MASK 0x00200000L +#define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE_MASK 0x00400000L + + +// addressBlock: gc_cprs64dec +//CP_MES_PRGRM_CNTR_START +#define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MES_INTR_ROUTINE_START +#define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_MES_MTVEC_LO +#define CP_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define CP_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_INTR_ROUTINE_START_HI +#define CP_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL +//CP_MES_MTVEC_HI +#define CP_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define CP_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_CNTL +#define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 +#define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 +#define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 +#define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 +#define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a +#define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b +#define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c +#define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d +#define CP_MES_CNTL__MES_HALT__SHIFT 0x1e +#define CP_MES_CNTL__MES_STEP__SHIFT 0x1f +#define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L +#define CP_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L +#define CP_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L +#define CP_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L +#define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L +#define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L +#define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L +#define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L +#define CP_MES_CNTL__MES_HALT_MASK 0x40000000L +#define CP_MES_CNTL__MES_STEP_MASK 0x80000000L +//CP_MES_PIPE_PRIORITY_CNTS +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_MES_PIPE0_PRIORITY +#define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE1_PRIORITY +#define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE2_PRIORITY +#define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE3_PRIORITY +#define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_HEADER_DUMP +#define CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_MES_MIE_LO +#define CP_MES_MIE_LO__MES_INT__SHIFT 0x0 +#define CP_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_MIE_HI +#define CP_MES_MIE_HI__MES_INT__SHIFT 0x0 +#define CP_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT +#define CP_MES_INTERRUPT__MES_INT__SHIFT 0x0 +#define CP_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_SCRATCH_INDEX +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_MES_SCRATCH_DATA +#define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_MES_INSTR_PNTR +#define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//CP_MES_MSCRATCH_HI +#define CP_MES_MSCRATCH_HI__DATA__SHIFT 0x0 +#define CP_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_MSCRATCH_LO +#define CP_MES_MSCRATCH_LO__DATA__SHIFT 0x0 +#define CP_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_MSTATUS_LO +#define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 +#define CP_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL +//CP_MES_MSTATUS_HI +#define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 +#define CP_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL +//CP_MES_MEPC_LO +#define CP_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 +#define CP_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL +//CP_MES_MEPC_HI +#define CP_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 +#define CP_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL +//CP_MES_MCAUSE_LO +#define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 +#define CP_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL +//CP_MES_MCAUSE_HI +#define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 +#define CP_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL +//CP_MES_MBADADDR_LO +#define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 +#define CP_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_MBADADDR_HI +#define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_MES_MIP_LO +#define CP_MES_MIP_LO__MIP_LO__SHIFT 0x0 +#define CP_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//CP_MES_MIP_HI +#define CP_MES_MIP_HI__MIP_HI__SHIFT 0x0 +#define CP_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//CP_MES_IC_OP_CNTL +#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_MES_MCYCLE_LO +#define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 +#define CP_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL +//CP_MES_MCYCLE_HI +#define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 +#define CP_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL +//CP_MES_MTIME_LO +#define CP_MES_MTIME_LO__TIME_LO__SHIFT 0x0 +#define CP_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MES_MTIME_HI +#define CP_MES_MTIME_HI__TIME_HI__SHIFT 0x0 +#define CP_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MES_MINSTRET_LO +#define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 +#define CP_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL +//CP_MES_MINSTRET_HI +#define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 +#define CP_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL +//CP_MES_MISA_LO +#define CP_MES_MISA_LO__MISA_LO__SHIFT 0x0 +#define CP_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL +//CP_MES_MISA_HI +#define CP_MES_MISA_HI__MISA_HI__SHIFT 0x0 +#define CP_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL +//CP_MES_MVENDORID_LO +#define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 +#define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL +//CP_MES_MVENDORID_HI +#define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 +#define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL +//CP_MES_MARCHID_LO +#define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 +#define CP_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL +//CP_MES_MARCHID_HI +#define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 +#define CP_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL +//CP_MES_MIMPID_LO +#define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 +#define CP_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL +//CP_MES_MIMPID_HI +#define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 +#define CP_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL +//CP_MES_MHARTID_LO +#define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 +#define CP_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL +//CP_MES_MHARTID_HI +#define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 +#define CP_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL +//CP_MES_DC_BASE_CNTL +#define CP_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MES_DC_OP_CNTL +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//CP_MES_MTIMECMP_LO +#define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define CP_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MES_MTIMECMP_HI +#define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define CP_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MES_PROCESS_QUANTUM_PIPE0 +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT 0x0 +#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT 0x1c +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT 0x1d +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT 0x1f +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK 0x10000000L +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK 0x60000000L +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK 0x80000000L +//CP_MES_PROCESS_QUANTUM_PIPE1 +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT 0x0 +#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT 0x1c +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT 0x1d +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT 0x1f +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK 0x10000000L +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK 0x60000000L +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL1 +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL2 +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL3 +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL4 +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL5 +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL6 +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_GP0_LO +#define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MES_GP0_LO__DATA__SHIFT 0x1 +#define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL +//CP_MES_GP0_HI +#define CP_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MES_GP1_LO +#define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MES_GP1_HI +#define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MES_GP2_LO +#define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MES_GP2_HI +#define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MES_GP3_LO +#define CP_MES_GP3_LO__DATA__SHIFT 0x0 +#define CP_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP3_HI +#define CP_MES_GP3_HI__DATA__SHIFT 0x0 +#define CP_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP4_LO +#define CP_MES_GP4_LO__DATA__SHIFT 0x0 +#define CP_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP4_HI +#define CP_MES_GP4_HI__DATA__SHIFT 0x0 +#define CP_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP5_LO +#define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MES_GP5_LO__DATA__SHIFT 0x1 +#define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL +//CP_MES_GP5_HI +#define CP_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MES_GP6_LO +#define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MES_GP6_HI +#define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MES_GP7_LO +#define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MES_GP7_HI +#define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MES_GP8_LO +#define CP_MES_GP8_LO__DATA__SHIFT 0x0 +#define CP_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP8_HI +#define CP_MES_GP8_HI__DATA__SHIFT 0x0 +#define CP_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP9_LO +#define CP_MES_GP9_LO__DATA__SHIFT 0x0 +#define CP_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP9_HI +#define CP_MES_GP9_HI__DATA__SHIFT 0x0 +#define CP_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_LOCAL_BASE0_LO +#define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_BASE0_HI +#define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//CP_MES_LOCAL_MASK0_LO +#define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_MASK0_HI +#define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//CP_MES_LOCAL_APERTURE +#define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +//CP_MES_LOCAL_INSTR_BASE_LO +#define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_INSTR_BASE_HI +#define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_MES_LOCAL_INSTR_MASK_LO +#define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_INSTR_MASK_HI +#define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//CP_MES_LOCAL_INSTR_APERTURE +#define CP_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +//CP_MES_LOCAL_SCRATCH_APERTURE +#define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_MES_LOCAL_SCRATCH_BASE_LO +#define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_SCRATCH_BASE_HI +#define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_MES_PERFCOUNT_CNTL +#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//CP_MES_PENDING_INTERRUPT +#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_MES_PRGRM_CNTR_START_HI +#define CP_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MES_INTERRUPT_DATA_16 +#define CP_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_17 +#define CP_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_18 +#define CP_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_19 +#define CP_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_20 +#define CP_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_21 +#define CP_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_22 +#define CP_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_23 +#define CP_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_24 +#define CP_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_25 +#define CP_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_26 +#define CP_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_27 +#define CP_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_28 +#define CP_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_29 +#define CP_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_30 +#define CP_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_31 +#define CP_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE0_BASE +#define CP_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE0_MASK +#define CP_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE0_CNTL +#define CP_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE1_BASE +#define CP_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE1_MASK +#define CP_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE1_CNTL +#define CP_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE2_BASE +#define CP_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE2_MASK +#define CP_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE2_CNTL +#define CP_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE3_BASE +#define CP_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE3_MASK +#define CP_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE3_CNTL +#define CP_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE4_BASE +#define CP_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE4_MASK +#define CP_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE4_CNTL +#define CP_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE5_BASE +#define CP_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE5_MASK +#define CP_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE5_CNTL +#define CP_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE6_BASE +#define CP_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE6_MASK +#define CP_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE6_CNTL +#define CP_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE7_BASE +#define CP_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE7_MASK +#define CP_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE7_CNTL +#define CP_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE8_BASE +#define CP_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE8_MASK +#define CP_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE8_CNTL +#define CP_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE9_BASE +#define CP_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE9_MASK +#define CP_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE9_CNTL +#define CP_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE10_BASE +#define CP_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE10_MASK +#define CP_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE10_CNTL +#define CP_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE11_BASE +#define CP_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE11_MASK +#define CP_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE11_CNTL +#define CP_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE12_BASE +#define CP_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE12_MASK +#define CP_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE12_CNTL +#define CP_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE13_BASE +#define CP_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE13_MASK +#define CP_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE13_CNTL +#define CP_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE14_BASE +#define CP_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE14_MASK +#define CP_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE14_CNTL +#define CP_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MES_DC_APERTURE15_BASE +#define CP_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0 +#define CP_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE15_MASK +#define CP_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0 +#define CP_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MES_DC_APERTURE15_CNTL +#define CP_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_RS64_PRGRM_CNTR_START +#define CP_MEC_RS64_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC_RS64_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MEC_MTVEC_LO +#define CP_MEC_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define CP_MEC_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MEC_MTVEC_HI +#define CP_MEC_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define CP_MEC_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MEC_ISA_CNTL +#define CP_MEC_ISA_CNTL__ISA_MODE__SHIFT 0x0 +#define CP_MEC_ISA_CNTL__ISA_MODE_MASK 0x00000001L +//CP_MEC_RS64_CNTL +#define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE__SHIFT 0x1a +#define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE__SHIFT 0x1b +#define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE__SHIFT 0x1c +#define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE__SHIFT 0x1d +#define CP_MEC_RS64_CNTL__MEC_HALT__SHIFT 0x1e +#define CP_MEC_RS64_CNTL__MEC_STEP__SHIFT 0x1f +#define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE_MASK 0x04000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE_MASK 0x08000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE_MASK 0x10000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE_MASK 0x20000000L +#define CP_MEC_RS64_CNTL__MEC_HALT_MASK 0x40000000L +#define CP_MEC_RS64_CNTL__MEC_STEP_MASK 0x80000000L +//CP_MEC_MIE_LO +#define CP_MEC_MIE_LO__MEC_INT__SHIFT 0x0 +#define CP_MEC_MIE_LO__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_MIE_HI +#define CP_MEC_MIE_HI__MEC_INT__SHIFT 0x0 +#define CP_MEC_MIE_HI__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT +#define CP_MEC_RS64_INTERRUPT__MEC_INT__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INSTR_PNTR +#define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//CP_MEC_MIP_LO +#define CP_MEC_MIP_LO__MIP_LO__SHIFT 0x0 +#define CP_MEC_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//CP_MEC_MIP_HI +#define CP_MEC_MIP_HI__MIP_HI__SHIFT 0x0 +#define CP_MEC_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//CP_MEC_DC_BASE_CNTL +#define CP_MEC_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MEC_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MEC_DC_OP_CNTL +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_MEC_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_MEC_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//CP_MEC_MTIMECMP_LO +#define CP_MEC_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define CP_MEC_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MEC_MTIMECMP_HI +#define CP_MEC_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define CP_MEC_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP0_LO +#define CP_MEC_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MEC_GP0_LO__DATA__SHIFT 0x1 +#define CP_MEC_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MEC_GP0_LO__DATA_MASK 0xFFFFFFFEL +//CP_MEC_GP0_HI +#define CP_MEC_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MEC_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MEC_GP1_LO +#define CP_MEC_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MEC_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP1_HI +#define CP_MEC_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MEC_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP2_LO +#define CP_MEC_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MEC_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP2_HI +#define CP_MEC_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MEC_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP3_LO +#define CP_MEC_GP3_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP3_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP3_HI +#define CP_MEC_GP3_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP3_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP4_LO +#define CP_MEC_GP4_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP4_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP4_HI +#define CP_MEC_GP4_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP4_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP5_LO +#define CP_MEC_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MEC_GP5_LO__DATA__SHIFT 0x1 +#define CP_MEC_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MEC_GP5_LO__DATA_MASK 0xFFFFFFFEL +//CP_MEC_GP5_HI +#define CP_MEC_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MEC_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MEC_GP6_LO +#define CP_MEC_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MEC_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP6_HI +#define CP_MEC_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MEC_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP7_LO +#define CP_MEC_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MEC_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP7_HI +#define CP_MEC_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MEC_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP8_LO +#define CP_MEC_GP8_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP8_HI +#define CP_MEC_GP8_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP9_LO +#define CP_MEC_GP9_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP9_HI +#define CP_MEC_GP9_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_LOCAL_BASE0_LO +#define CP_MEC_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_BASE0_HI +#define CP_MEC_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//CP_MEC_LOCAL_MASK0_LO +#define CP_MEC_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_MASK0_HI +#define CP_MEC_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//CP_MEC_LOCAL_APERTURE +#define CP_MEC_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +//CP_MEC_LOCAL_INSTR_BASE_LO +#define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_INSTR_BASE_HI +#define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_MEC_LOCAL_INSTR_MASK_LO +#define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_INSTR_MASK_HI +#define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//CP_MEC_LOCAL_INSTR_APERTURE +#define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +//CP_MEC_LOCAL_SCRATCH_APERTURE +#define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_MEC_LOCAL_SCRATCH_BASE_LO +#define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_SCRATCH_BASE_HI +#define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_MEC_RS64_PERFCOUNT_CNTL +#define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//CP_MEC_RS64_PENDING_INTERRUPT +#define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_PRGRM_CNTR_START_HI +#define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_16 +#define CP_MEC_RS64_INTERRUPT_DATA_16__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_17 +#define CP_MEC_RS64_INTERRUPT_DATA_17__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_18 +#define CP_MEC_RS64_INTERRUPT_DATA_18__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_19 +#define CP_MEC_RS64_INTERRUPT_DATA_19__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_20 +#define CP_MEC_RS64_INTERRUPT_DATA_20__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_21 +#define CP_MEC_RS64_INTERRUPT_DATA_21__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_22 +#define CP_MEC_RS64_INTERRUPT_DATA_22__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_23 +#define CP_MEC_RS64_INTERRUPT_DATA_23__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_24 +#define CP_MEC_RS64_INTERRUPT_DATA_24__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_25 +#define CP_MEC_RS64_INTERRUPT_DATA_25__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_26 +#define CP_MEC_RS64_INTERRUPT_DATA_26__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_27 +#define CP_MEC_RS64_INTERRUPT_DATA_27__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_28 +#define CP_MEC_RS64_INTERRUPT_DATA_28__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_29 +#define CP_MEC_RS64_INTERRUPT_DATA_29__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_30 +#define CP_MEC_RS64_INTERRUPT_DATA_30__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_31 +#define CP_MEC_RS64_INTERRUPT_DATA_31__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE0_BASE +#define CP_MEC_DC_APERTURE0_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE0_MASK +#define CP_MEC_DC_APERTURE0_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE0_CNTL +#define CP_MEC_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE1_BASE +#define CP_MEC_DC_APERTURE1_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE1_MASK +#define CP_MEC_DC_APERTURE1_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE1_CNTL +#define CP_MEC_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE2_BASE +#define CP_MEC_DC_APERTURE2_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE2_MASK +#define CP_MEC_DC_APERTURE2_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE2_CNTL +#define CP_MEC_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE3_BASE +#define CP_MEC_DC_APERTURE3_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE3_MASK +#define CP_MEC_DC_APERTURE3_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE3_CNTL +#define CP_MEC_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE4_BASE +#define CP_MEC_DC_APERTURE4_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE4_MASK +#define CP_MEC_DC_APERTURE4_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE4_CNTL +#define CP_MEC_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE5_BASE +#define CP_MEC_DC_APERTURE5_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE5_MASK +#define CP_MEC_DC_APERTURE5_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE5_CNTL +#define CP_MEC_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE6_BASE +#define CP_MEC_DC_APERTURE6_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE6_MASK +#define CP_MEC_DC_APERTURE6_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE6_CNTL +#define CP_MEC_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE7_BASE +#define CP_MEC_DC_APERTURE7_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE7_MASK +#define CP_MEC_DC_APERTURE7_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE7_CNTL +#define CP_MEC_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE8_BASE +#define CP_MEC_DC_APERTURE8_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE8_MASK +#define CP_MEC_DC_APERTURE8_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE8_CNTL +#define CP_MEC_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE9_BASE +#define CP_MEC_DC_APERTURE9_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE9_MASK +#define CP_MEC_DC_APERTURE9_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE9_CNTL +#define CP_MEC_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE10_BASE +#define CP_MEC_DC_APERTURE10_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE10_MASK +#define CP_MEC_DC_APERTURE10_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE10_CNTL +#define CP_MEC_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE11_BASE +#define CP_MEC_DC_APERTURE11_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE11_MASK +#define CP_MEC_DC_APERTURE11_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE11_CNTL +#define CP_MEC_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE12_BASE +#define CP_MEC_DC_APERTURE12_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE12_MASK +#define CP_MEC_DC_APERTURE12_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE12_CNTL +#define CP_MEC_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE13_BASE +#define CP_MEC_DC_APERTURE13_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE13_MASK +#define CP_MEC_DC_APERTURE13_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE13_CNTL +#define CP_MEC_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE14_BASE +#define CP_MEC_DC_APERTURE14_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE14_MASK +#define CP_MEC_DC_APERTURE14_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE14_CNTL +#define CP_MEC_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_MEC_DC_APERTURE15_BASE +#define CP_MEC_DC_APERTURE15_BASE__BASE__SHIFT 0x0 +#define CP_MEC_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE15_MASK +#define CP_MEC_DC_APERTURE15_MASK__MASK__SHIFT 0x0 +#define CP_MEC_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL +//CP_MEC_DC_APERTURE15_CNTL +#define CP_MEC_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 +#define CP_MEC_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L +//CP_CPC_IC_OP_CNTL +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_GFX_CNTL +#define CP_GFX_CNTL__ENGINE_SEL__SHIFT 0x0 +#define CP_GFX_CNTL__CONFIG__SHIFT 0x1 +#define CP_GFX_CNTL__ENGINE_SEL_MASK 0x00000001L +#define CP_GFX_CNTL__CONFIG_MASK 0x00000006L +//CP_GFX_RS64_INTERRUPT0 +#define CP_GFX_RS64_INTERRUPT0__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTERRUPT0__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INTR_EN0 +#define CP_GFX_RS64_INTR_EN0__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTR_EN0__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INTR_EN1 +#define CP_GFX_RS64_INTR_EN1__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTR_EN1__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_BASE_CNTL +#define CP_GFX_RS64_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_RS64_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_GFX_RS64_DC_OP_CNTL +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_GFX_RS64_DC_OP_CNTL__RESERVED__SHIFT 0x3 +#define CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE__SHIFT 0x4 +#define CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED__SHIFT 0x5 +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +#define CP_GFX_RS64_DC_OP_CNTL__RESERVED_MASK 0x00000008L +#define CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE_MASK 0x00000010L +#define CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED_MASK 0x00000020L +//CP_GFX_RS64_LOCAL_BASE0_LO +#define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_BASE0_HI +#define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_MASK0_LO +#define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_MASK0_HI +#define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_APERTURE +#define CP_GFX_RS64_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +//CP_GFX_RS64_LOCAL_INSTR_BASE_LO +#define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_INSTR_BASE_HI +#define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_INSTR_MASK_LO +#define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_INSTR_MASK_HI +#define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_INSTR_APERTURE +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +//CP_GFX_RS64_LOCAL_SCRATCH_APERTURE +#define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_PERFCOUNT_CNTL0 +#define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL__SHIFT 0x0 +#define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL_MASK 0x0000001FL +//CP_GFX_RS64_PERFCOUNT_CNTL1 +#define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL__SHIFT 0x0 +#define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL_MASK 0x0000001FL +//CP_GFX_RS64_MIP_LO0 +#define CP_GFX_RS64_MIP_LO0__MIP_LO__SHIFT 0x0 +#define CP_GFX_RS64_MIP_LO0__MIP_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_LO1 +#define CP_GFX_RS64_MIP_LO1__MIP_LO__SHIFT 0x0 +#define CP_GFX_RS64_MIP_LO1__MIP_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_HI0 +#define CP_GFX_RS64_MIP_HI0__MIP_HI__SHIFT 0x0 +#define CP_GFX_RS64_MIP_HI0__MIP_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_HI1 +#define CP_GFX_RS64_MIP_HI1__MIP_HI__SHIFT 0x0 +#define CP_GFX_RS64_MIP_HI1__MIP_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_LO0 +#define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_LO1 +#define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_HI0 +#define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_HI1 +#define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP0_LO0 +#define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP0_LO0__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP0_LO0__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP0_LO1 +#define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP0_LO1__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP0_LO1__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP0_HI0 +#define CP_GFX_RS64_GP0_HI0__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP0_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP0_HI1 +#define CP_GFX_RS64_GP0_HI1__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP0_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_LO0 +#define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_LO1 +#define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_HI0 +#define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_HI1 +#define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_LO0 +#define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_LO1 +#define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_HI0 +#define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_HI1 +#define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_LO0 +#define CP_GFX_RS64_GP3_LO0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_LO0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_LO1 +#define CP_GFX_RS64_GP3_LO1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_LO1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_HI0 +#define CP_GFX_RS64_GP3_HI0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_HI0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_HI1 +#define CP_GFX_RS64_GP3_HI1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_HI1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_LO0 +#define CP_GFX_RS64_GP4_LO0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_LO0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_LO1 +#define CP_GFX_RS64_GP4_LO1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_LO1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_HI0 +#define CP_GFX_RS64_GP4_HI0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_HI0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_HI1 +#define CP_GFX_RS64_GP4_HI1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_HI1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP5_LO0 +#define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP5_LO0__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP5_LO0__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP5_LO1 +#define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP5_LO1__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP5_LO1__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP5_HI0 +#define CP_GFX_RS64_GP5_HI0__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP5_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP5_HI1 +#define CP_GFX_RS64_GP5_HI1__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP5_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP6_LO +#define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP6_HI +#define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP7_LO +#define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP7_HI +#define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP8_LO +#define CP_GFX_RS64_GP8_LO__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP8_HI +#define CP_GFX_RS64_GP8_HI__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP9_LO +#define CP_GFX_RS64_GP9_LO__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP9_HI +#define CP_GFX_RS64_GP9_HI__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INSTR_PNTR0 +#define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR__SHIFT 0x0 +#define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR_MASK 0x000FFFFFL +//CP_GFX_RS64_INSTR_PNTR1 +#define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR__SHIFT 0x0 +#define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR_MASK 0x000FFFFFL +//CP_GFX_RS64_PENDING_INTERRUPT0 +#define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_PENDING_INTERRUPT1 +#define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_BASE0 +#define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_MASK0 +#define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_CNTL0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE1_BASE0 +#define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_MASK0 +#define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_CNTL0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE2_BASE0 +#define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_MASK0 +#define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_CNTL0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE3_BASE0 +#define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_MASK0 +#define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_CNTL0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE4_BASE0 +#define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_MASK0 +#define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_CNTL0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE5_BASE0 +#define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_MASK0 +#define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_CNTL0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE6_BASE0 +#define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_MASK0 +#define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_CNTL0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE7_BASE0 +#define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_MASK0 +#define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_CNTL0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE8_BASE0 +#define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_MASK0 +#define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_CNTL0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE9_BASE0 +#define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_MASK0 +#define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_CNTL0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE10_BASE0 +#define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_MASK0 +#define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_CNTL0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE11_BASE0 +#define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_MASK0 +#define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_CNTL0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE12_BASE0 +#define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_MASK0 +#define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_CNTL0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE13_BASE0 +#define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_MASK0 +#define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_CNTL0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE14_BASE0 +#define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_MASK0 +#define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_CNTL0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE15_BASE0 +#define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_MASK0 +#define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_CNTL0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE0_BASE1 +#define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_MASK1 +#define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_CNTL1 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE1_BASE1 +#define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_MASK1 +#define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_CNTL1 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE2_BASE1 +#define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_MASK1 +#define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_CNTL1 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE3_BASE1 +#define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_MASK1 +#define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_CNTL1 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE4_BASE1 +#define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_MASK1 +#define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_CNTL1 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE5_BASE1 +#define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_MASK1 +#define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_CNTL1 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE6_BASE1 +#define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_MASK1 +#define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_CNTL1 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE7_BASE1 +#define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_MASK1 +#define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_CNTL1 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE8_BASE1 +#define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_MASK1 +#define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_CNTL1 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE9_BASE1 +#define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_MASK1 +#define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_CNTL1 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE10_BASE1 +#define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_MASK1 +#define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_CNTL1 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE11_BASE1 +#define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_MASK1 +#define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_CNTL1 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE12_BASE1 +#define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_MASK1 +#define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_CNTL1 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE13_BASE1 +#define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_MASK1 +#define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_CNTL1 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE14_BASE1 +#define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_MASK1 +#define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_CNTL1 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_DC_APERTURE15_BASE1 +#define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_MASK1 +#define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_CNTL1 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE_MASK 0x00000010L +//CP_GFX_RS64_INTERRUPT1 +#define CP_GFX_RS64_INTERRUPT1__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTERRUPT1__ME_INT_MASK 0xFFFFFFFFL + + +// addressBlock: gc_gl1dec +//GL1_DRAM_BURST_MASK +#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//GL1_ARB_STATUS +#define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GL1_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//GL1I_GL1R_REP_FGCG_OVERRIDE +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//GL1C_STATUS +#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 +#define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define GL1C_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT 0x14 +#define GL1C_STATUS__TAG_STALL__SHIFT 0x15 +#define GL1C_STATUS__TAG_BUSY__SHIFT 0x16 +#define GL1C_STATUS__TAG_ACK_STALL__SHIFT 0x17 +#define GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT 0x18 +#define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT 0x19 +#define GL1C_STATUS__TAG_EVICT__SHIFT 0x1a +#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT 0x1b +#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT 0x1f +#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L +#define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define GL1C_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK 0x00100000L +#define GL1C_STATUS__TAG_STALL_MASK 0x00200000L +#define GL1C_STATUS__TAG_BUSY_MASK 0x00400000L +#define GL1C_STATUS__TAG_ACK_STALL_MASK 0x00800000L +#define GL1C_STATUS__TAG_GCR_INV_STALL_MASK 0x01000000L +#define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK 0x02000000L +#define GL1C_STATUS__TAG_EVICT_MASK 0x04000000L +#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK 0x78000000L +#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK 0x80000000L +//GL1C_UTCL0_CNTL1 +#define GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define GL1C_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define GL1C_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define GL1C_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define GL1C_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define GL1C_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define GL1C_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define GL1C_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a +#define GL1C_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define GL1C_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define GL1C_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define GL1C_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define GL1C_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define GL1C_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define GL1C_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define GL1C_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L +#define GL1C_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x06000000L +#define GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//GL1C_UTCL0_CNTL2 +#define GL1C_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8 +#define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define GL1C_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define GL1C_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define GL1C_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define GL1C_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT 0x1f +#define GL1C_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK 0x00000100L +#define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define GL1C_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define GL1C_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define GL1C_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define GL1C_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK 0x80000000L +//GL1C_UTCL0_STATUS +#define GL1C_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define GL1C_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define GL1C_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define GL1C_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define GL1C_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define GL1C_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +//GL1C_UTCL0_RETRY +#define GL1C_UTCL0_RETRY__INCR__SHIFT 0x0 +#define GL1C_UTCL0_RETRY__COUNT__SHIFT 0x8 +#define GL1C_UTCL0_RETRY__INCR_MASK 0x000000FFL +#define GL1C_UTCL0_RETRY__COUNT_MASK 0x00000F00L + + +// addressBlock: gc_chdec +//CH_ARB_CTRL +#define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT 0x2 +#define CH_ARB_CTRL__FGCG_DISABLE__SHIFT 0x3 +#define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x4 +#define CH_ARB_CTRL__CHICKEN_BITS__SHIFT 0x5 +#define CH_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000003L +#define CH_ARB_CTRL__UC_IO_WR_PATH_MASK 0x00000004L +#define CH_ARB_CTRL__FGCG_DISABLE_MASK 0x00000008L +#define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000010L +#define CH_ARB_CTRL__CHICKEN_BITS_MASK 0x00001FE0L +//CH_DRAM_BURST_MASK +#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//CH_ARB_STATUS +#define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define CH_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define CH_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//CH_DRAM_BURST_CTRL +#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4 +#define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT 0x5 +#define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT 0x6 +#define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE__SHIFT 0x7 +#define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT 0x8 +#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +#define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L +#define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK 0x00000020L +#define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK 0x00000040L +#define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE_MASK 0x00000080L +#define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK 0x00000100L +//CHA_CHC_CREDITS +#define CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT 0x0 +#define CHA_CHC_CREDITS__CHCG_REQ_CREDITS__SHIFT 0x8 +#define CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK 0x000000FFL +#define CHA_CHC_CREDITS__CHCG_REQ_CREDITS_MASK 0x0000FF00L +//CHA_CLIENT_FREE_DELAY +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L +//CHI_CHR_REP_FGCG_OVERRIDE +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//CH_VC5_ENABLE +#define CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT 0x1 +#define CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK 0x00000002L +//CHC_CTRL +#define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define CHC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define CHC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT__SHIFT 0x1d +#define CHC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define CHC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define CHC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT_MASK 0x20000000L +//CHC_STATUS +#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 +#define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define CHC_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define CHC_STATUS__BUFFER_FULL__SHIFT 0x17 +#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L +#define CHC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define CHC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define CHC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define CHC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define CHC_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define CHC_STATUS__BUFFER_FULL_MASK 0x00800000L +//CHCG_CTRL +#define CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT 0x4 +#define CHCG_CTRL__GL2_REQ_CREDITS__SHIFT 0x8 +#define CHCG_CTRL__GL2_DATA_CREDITS__SHIFT 0xf +#define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x16 +#define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x17 +#define CHCG_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK 0x000000F0L +#define CHCG_CTRL__GL2_REQ_CREDITS_MASK 0x00007F00L +#define CHCG_CTRL__GL2_DATA_CREDITS_MASK 0x003F8000L +#define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00400000L +#define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00800000L +//CHCG_STATUS +#define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 +#define CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define CHCG_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define CHCG_STATUS__BUFFER_FULL__SHIFT 0x17 +#define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT 0x18 +#define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT 0x19 +#define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT 0x1a +#define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT 0x1b +#define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L +#define CHCG_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define CHCG_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define CHCG_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define CHCG_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define CHCG_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define CHCG_STATUS__BUFFER_FULL_MASK 0x00800000L +#define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK 0x01000000L +#define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK 0x02000000L +#define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK 0x04000000L +#define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK 0x08000000L + + +// addressBlock: gc_gl2dec +//GL2C_CTRL +#define GL2C_CTRL__CACHE_SIZE__SHIFT 0x0 +#define GL2C_CTRL__RATE__SHIFT 0x2 +#define GL2C_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 +#define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 +#define GL2C_CTRL__SRC_FIFO_SIZE__SHIFT 0xc +#define GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 +#define GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT 0x14 +#define GL2C_CTRL__LINEAR_SET_HASH__SHIFT 0x15 +#define GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT 0x16 +#define GL2C_CTRL__MDC_SIZE__SHIFT 0x18 +#define GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT 0x1a +#define GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT 0x1b +#define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c +#define GL2C_CTRL__CACHE_SIZE_MASK 0x00000003L +#define GL2C_CTRL__RATE_MASK 0x0000000CL +#define GL2C_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L +#define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L +#define GL2C_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L +#define GL2C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L +#define GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK 0x00100000L +#define GL2C_CTRL__LINEAR_SET_HASH_MASK 0x00200000L +#define GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK 0x00C00000L +#define GL2C_CTRL__MDC_SIZE_MASK 0x03000000L +#define GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK 0x04000000L +#define GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK 0x08000000L +#define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L +//GL2C_CTRL2 +#define GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 +#define GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT 0x4 +#define GL2C_CTRL2__FILL_SIZE_32__SHIFT 0x5 +#define GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT 0x6 +#define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT 0x7 +#define GL2C_CTRL2__RO_DISABLE__SHIFT 0x8 +#define GL2C_CTRL2__FORCE_MDC_INV__SHIFT 0x9 +#define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT 0xa +#define GL2C_CTRL2__GCR_ALL_SET__SHIFT 0xd +#define GL2C_CTRL2__FILL_SIZE_64__SHIFT 0x11 +#define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x12 +#define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT 0x13 +#define GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT 0x14 +#define GL2C_CTRL2__RB_VOLATILE_EN__SHIFT 0x15 +#define GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT 0x16 +#define GL2C_CTRL2__MAX_MIN_CTRL__SHIFT 0x17 +#define GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT 0x1a +#define GL2C_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL +#define GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK 0x00000010L +#define GL2C_CTRL2__FILL_SIZE_32_MASK 0x00000020L +#define GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK 0x00000040L +#define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK 0x00000080L +#define GL2C_CTRL2__RO_DISABLE_MASK 0x00000100L +#define GL2C_CTRL2__FORCE_MDC_INV_MASK 0x00000200L +#define GL2C_CTRL2__GCR_ARB_CTRL_MASK 0x00001C00L +#define GL2C_CTRL2__GCR_ALL_SET_MASK 0x00002000L +#define GL2C_CTRL2__FILL_SIZE_64_MASK 0x00020000L +#define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x00040000L +#define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK 0x00080000L +#define GL2C_CTRL2__METADATA_VOLATILE_EN_MASK 0x00100000L +#define GL2C_CTRL2__RB_VOLATILE_EN_MASK 0x00200000L +#define GL2C_CTRL2__PROBE_UNSHARED_EN_MASK 0x00400000L +#define GL2C_CTRL2__MAX_MIN_CTRL_MASK 0x01800000L +#define GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK 0x04000000L +//GL2C_ADDR_MATCH_MASK +#define GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 +#define GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL +//GL2C_ADDR_MATCH_SIZE +#define GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 +#define GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L +//GL2C_WBINVL2 +#define GL2C_WBINVL2__DONE__SHIFT 0x4 +#define GL2C_WBINVL2__DONE_MASK 0x00000010L +//GL2C_SOFT_RESET +#define GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 +#define GL2C_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L +//GL2C_CM_CTRL0 +//GL2C_CM_CTRL1 +#define GL2C_CM_CTRL1__BURST_TIMER__SHIFT 0x8 +#define GL2C_CM_CTRL1__RVF_SIZE__SHIFT 0x10 +#define GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT 0x17 +#define GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT 0x19 +#define GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT 0x1a +#define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT 0x1b +#define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT 0x1c +#define GL2C_CM_CTRL1__BURST_MODE__SHIFT 0x1d +#define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT 0x1e +#define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT 0x1f +#define GL2C_CM_CTRL1__BURST_TIMER_MASK 0x0000FF00L +#define GL2C_CM_CTRL1__RVF_SIZE_MASK 0x000F0000L +#define GL2C_CM_CTRL1__WRITE_COH_MODE_MASK 0x01800000L +#define GL2C_CM_CTRL1__MDC_ARB_MODE_MASK 0x02000000L +#define GL2C_CM_CTRL1__READ_REQ_ONLY_MASK 0x04000000L +#define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK 0x08000000L +#define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK 0x10000000L +#define GL2C_CM_CTRL1__BURST_MODE_MASK 0x20000000L +#define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK 0x40000000L +#define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK 0x80000000L +//GL2C_CM_STALL +#define GL2C_CM_STALL__QUEUE__SHIFT 0x0 +#define GL2C_CM_STALL__QUEUE_MASK 0xFFFFFFFFL +//GL2C_CTRL3 +#define GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT 0x0 +#define GL2C_CTRL3__METADATA_NOFILL__SHIFT 0x3 +#define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT 0x4 +#define GL2C_CTRL3__BANK_LINEAR_HASH_MODE__SHIFT 0x5 +#define GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT 0x6 +#define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT 0x7 +#define GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT 0x8 +#define GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT 0x9 +#define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT 0xa +#define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT 0xb +#define GL2C_CTRL3__HASH_256B_ENABLE__SHIFT 0xc +#define GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE__SHIFT 0xd +#define GL2C_CTRL3__FORCE_READ_ON_WRITE_OP__SHIFT 0xe +#define GL2C_CTRL3__FGCG_OVERRIDE__SHIFT 0xf +#define GL2C_CTRL3__FORCE_MTYPE_UC__SHIFT 0x10 +#define GL2C_CTRL3__DGPU_SHARED_MODE__SHIFT 0x11 +#define GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN__SHIFT 0x12 +#define GL2C_CTRL3__EA_READ_SIZE_LIMIT__SHIFT 0x13 +#define GL2C_CTRL3__READ_BYPASS_AS_UC__SHIFT 0x14 +#define GL2C_CTRL3__WB_OPT_ENABLE__SHIFT 0x15 +#define GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT__SHIFT 0x16 +#define GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE__SHIFT 0x18 +#define GL2C_CTRL3__EA_GMI_DISABLE__SHIFT 0x19 +#define GL2C_CTRL3__SQC_TO_HI_PRIORITY__SHIFT 0x1a +#define GL2C_CTRL3__INF_NAN_CLAMP__SHIFT 0x1b +#define GL2C_CTRL3__SCRATCH__SHIFT 0x1c +#define GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK 0x00000003L +#define GL2C_CTRL3__METADATA_NOFILL_MASK 0x00000008L +#define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK 0x00000010L +#define GL2C_CTRL3__BANK_LINEAR_HASH_MODE_MASK 0x00000020L +#define GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK 0x00000040L +#define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK 0x00000080L +#define GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK 0x00000100L +#define GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK 0x00000200L +#define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK 0x00000400L +#define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK 0x00000800L +#define GL2C_CTRL3__HASH_256B_ENABLE_MASK 0x00001000L +#define GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE_MASK 0x00002000L +#define GL2C_CTRL3__FORCE_READ_ON_WRITE_OP_MASK 0x00004000L +#define GL2C_CTRL3__FGCG_OVERRIDE_MASK 0x00008000L +#define GL2C_CTRL3__FORCE_MTYPE_UC_MASK 0x00010000L +#define GL2C_CTRL3__DGPU_SHARED_MODE_MASK 0x00020000L +#define GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN_MASK 0x00040000L +#define GL2C_CTRL3__EA_READ_SIZE_LIMIT_MASK 0x00080000L +#define GL2C_CTRL3__READ_BYPASS_AS_UC_MASK 0x00100000L +#define GL2C_CTRL3__WB_OPT_ENABLE_MASK 0x00200000L +#define GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT_MASK 0x00C00000L +#define GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE_MASK 0x01000000L +#define GL2C_CTRL3__EA_GMI_DISABLE_MASK 0x02000000L +#define GL2C_CTRL3__SQC_TO_HI_PRIORITY_MASK 0x04000000L +#define GL2C_CTRL3__INF_NAN_CLAMP_MASK 0x08000000L +#define GL2C_CTRL3__SCRATCH_MASK 0xF0000000L +//GL2C_LB_CTR_CTRL +#define GL2C_LB_CTR_CTRL__START__SHIFT 0x0 +#define GL2C_LB_CTR_CTRL__LOAD__SHIFT 0x1 +#define GL2C_LB_CTR_CTRL__CLEAR__SHIFT 0x2 +#define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x1f +#define GL2C_LB_CTR_CTRL__START_MASK 0x00000001L +#define GL2C_LB_CTR_CTRL__LOAD_MASK 0x00000002L +#define GL2C_LB_CTR_CTRL__CLEAR_MASK 0x00000004L +#define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x80000000L +//GL2C_LB_DATA0 +#define GL2C_LB_DATA0__DATA__SHIFT 0x0 +#define GL2C_LB_DATA0__DATA_MASK 0xFFFFFFFFL +//GL2C_LB_DATA1 +#define GL2C_LB_DATA1__DATA__SHIFT 0x0 +#define GL2C_LB_DATA1__DATA_MASK 0xFFFFFFFFL +//GL2C_LB_DATA2 +#define GL2C_LB_DATA2__DATA__SHIFT 0x0 +#define GL2C_LB_DATA2__DATA_MASK 0xFFFFFFFFL +//GL2C_LB_DATA3 +#define GL2C_LB_DATA3__DATA__SHIFT 0x0 +#define GL2C_LB_DATA3__DATA_MASK 0xFFFFFFFFL +//GL2C_LB_CTR_SEL0 +#define GL2C_LB_CTR_SEL0__SEL0__SHIFT 0x0 +#define GL2C_LB_CTR_SEL0__DIV0__SHIFT 0xf +#define GL2C_LB_CTR_SEL0__SEL1__SHIFT 0x10 +#define GL2C_LB_CTR_SEL0__DIV1__SHIFT 0x1f +#define GL2C_LB_CTR_SEL0__SEL0_MASK 0x000000FFL +#define GL2C_LB_CTR_SEL0__DIV0_MASK 0x00008000L +#define GL2C_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L +#define GL2C_LB_CTR_SEL0__DIV1_MASK 0x80000000L +//GL2C_LB_CTR_SEL1 +#define GL2C_LB_CTR_SEL1__SEL2__SHIFT 0x0 +#define GL2C_LB_CTR_SEL1__DIV2__SHIFT 0xf +#define GL2C_LB_CTR_SEL1__SEL3__SHIFT 0x10 +#define GL2C_LB_CTR_SEL1__DIV3__SHIFT 0x1f +#define GL2C_LB_CTR_SEL1__SEL2_MASK 0x000000FFL +#define GL2C_LB_CTR_SEL1__DIV2_MASK 0x00008000L +#define GL2C_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L +#define GL2C_LB_CTR_SEL1__DIV3_MASK 0x80000000L +//GL2C_CTRL4 +#define GL2C_CTRL4__METADATA_WR_OP_CID__SHIFT 0x0 +#define GL2C_CTRL4__SPA_CHANNEL_ENABLE__SHIFT 0x1 +#define GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY__SHIFT 0x2 +#define GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE__SHIFT 0x3 +#define GL2C_CTRL4__CM_MGCG_MODE__SHIFT 0x4 +#define GL2C_CTRL4__MDC_MGCG_MODE__SHIFT 0x5 +#define GL2C_CTRL4__TAG_MGCG_MODE__SHIFT 0x6 +#define GL2C_CTRL4__CORE_MGCG_MODE__SHIFT 0x7 +#define GL2C_CTRL4__EXECUTE_MGCG_MODE__SHIFT 0x8 +#define GL2C_CTRL4__EA_NACK_DISABLE__SHIFT 0x9 +#define GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE__SHIFT 0x1a +#define GL2C_CTRL4__METADATA_WR_OP_CID_MASK 0x00000001L +#define GL2C_CTRL4__SPA_CHANNEL_ENABLE_MASK 0x00000002L +#define GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY_MASK 0x00000004L +#define GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE_MASK 0x00000008L +#define GL2C_CTRL4__CM_MGCG_MODE_MASK 0x00000010L +#define GL2C_CTRL4__MDC_MGCG_MODE_MASK 0x00000020L +#define GL2C_CTRL4__TAG_MGCG_MODE_MASK 0x00000040L +#define GL2C_CTRL4__CORE_MGCG_MODE_MASK 0x00000080L +#define GL2C_CTRL4__EXECUTE_MGCG_MODE_MASK 0x00000100L +#define GL2C_CTRL4__EA_NACK_DISABLE_MASK 0x00000200L +#define GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE_MASK 0x04000000L +//GL2C_DISCARD_STALL_CTRL +#define GL2C_DISCARD_STALL_CTRL__LIMIT__SHIFT 0x0 +#define GL2C_DISCARD_STALL_CTRL__WINDOW__SHIFT 0xf +#define GL2C_DISCARD_STALL_CTRL__DROP_NEXT__SHIFT 0x1e +#define GL2C_DISCARD_STALL_CTRL__ENABLE__SHIFT 0x1f +#define GL2C_DISCARD_STALL_CTRL__LIMIT_MASK 0x00007FFFL +#define GL2C_DISCARD_STALL_CTRL__WINDOW_MASK 0x3FFF8000L +#define GL2C_DISCARD_STALL_CTRL__DROP_NEXT_MASK 0x40000000L +#define GL2C_DISCARD_STALL_CTRL__ENABLE_MASK 0x80000000L +//GL2A_ADDR_MATCH_CTRL +#define GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT 0x0 +#define GL2A_ADDR_MATCH_CTRL__DISABLE_MASK 0xFFFFFFFFL +//GL2A_ADDR_MATCH_MASK +#define GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 +#define GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL +//GL2A_ADDR_MATCH_SIZE +#define GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 +#define GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L +//GL2A_PRIORITY_CTRL +#define GL2A_PRIORITY_CTRL__DISABLE__SHIFT 0x0 +#define GL2A_PRIORITY_CTRL__DISABLE_MASK 0xFFFFFFFFL +//GL2A_RESP_THROTTLE_CTRL +#define GL2A_RESP_THROTTLE_CTRL__DISABLE__SHIFT 0x0 +#define GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1__SHIFT 0x10 +#define GL2A_RESP_THROTTLE_CTRL__CREDIT_CH__SHIFT 0x18 +#define GL2A_RESP_THROTTLE_CTRL__DISABLE_MASK 0x0000FFFFL +#define GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1_MASK 0x00FF0000L +#define GL2A_RESP_THROTTLE_CTRL__CREDIT_CH_MASK 0xFF000000L + + +// addressBlock: gc_gl1hdec +//GL1H_ARB_CTRL +#define GL1H_ARB_CTRL__REQ_FGCG_DISABLE__SHIFT 0x0 +#define GL1H_ARB_CTRL__SRC_FGCG_DISABLE__SHIFT 0x1 +#define GL1H_ARB_CTRL__RET_FGCG_DISABLE__SHIFT 0x2 +#define GL1H_ARB_CTRL__CHICKEN_BITS__SHIFT 0x3 +#define GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0xb +#define GL1H_ARB_CTRL__REQ_FGCG_DISABLE_MASK 0x00000001L +#define GL1H_ARB_CTRL__SRC_FGCG_DISABLE_MASK 0x00000002L +#define GL1H_ARB_CTRL__RET_FGCG_DISABLE_MASK 0x00000004L +#define GL1H_ARB_CTRL__CHICKEN_BITS_MASK 0x000007F8L +#define GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000800L +//GL1H_GL1_CREDITS +#define GL1H_GL1_CREDITS__GL1_REQ_CREDITS__SHIFT 0x0 +#define GL1H_GL1_CREDITS__GL1_REQ_CREDITS_MASK 0x000000FFL +//GL1H_BURST_MASK +#define GL1H_BURST_MASK__BURST_ADDR_MASK__SHIFT 0x0 +#define GL1H_BURST_MASK__BURST_ADDR_MASK_MASK 0x000000FFL +//GL1H_BURST_CTRL +#define GL1H_BURST_CTRL__MAX_BURST_SIZE__SHIFT 0x0 +#define GL1H_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS__SHIFT 0x4 +#define GL1H_BURST_CTRL__MAX_BURST_SIZE_MASK 0x00000007L +#define GL1H_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +#define GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS_MASK 0x00000030L +//GL1H_ARB_STATUS +#define GL1H_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ__SHIFT 0x1 +#define GL1H_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ_MASK 0x00000002L + + +// addressBlock: gc_perfddec +//CPG_PERFCOUNTER1_LO +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER1_HI +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_LO +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_HI +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_LO +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_HI +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_LO +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_HI +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_LO +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_HI +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_LO +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_HI +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_LATENCY_STATS_DATA +#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_LATENCY_STATS_DATA +#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPC_LATENCY_STATS_DATA +#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_LO +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_HI +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_LO +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_HI +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_LO +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_HI +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_LO +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_HI +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_LO +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_HI +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_LO +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_HI +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE4_PERFCOUNTER_LO +#define GRBM_SE4_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE4_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE4_PERFCOUNTER_HI +#define GRBM_SE4_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE4_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE5_PERFCOUNTER_LO +#define GRBM_SE5_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE5_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE5_PERFCOUNTER_HI +#define GRBM_SE5_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE5_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE6_PERFCOUNTER_LO +#define GRBM_SE6_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE6_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE6_PERFCOUNTER_HI +#define GRBM_SE6_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE6_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER0_LO +#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER0_HI +#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER1_LO +#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER1_HI +#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER2_LO +#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER2_HI +#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER3_LO +#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER3_HI +#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER0_LO +#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER0_HI +#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER1_LO +#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER1_HI +#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER2_LO +#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER2_HI +#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER3_LO +#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER3_HI +#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER0_LO +#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER0_HI +#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER1_LO +#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER1_HI +#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER2_LO +#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER2_HI +#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER3_LO +#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER3_HI +#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_LO +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_LO +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_LO +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_LO +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_LO +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_LO +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_HI +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_LO +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_HI +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_LO +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_HI +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_LO +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_HI +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_LO +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_HI +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_LO +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_HI +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_LO +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_HI +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_HI +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_LO +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_HI +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_LO +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_HI +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_LO +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_HI +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_LO +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_HI +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_LO +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_HI +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_LO +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER0_HI +#define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER0_LO +#define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER1_HI +#define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER1_LO +#define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER2_HI +#define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER2_LO +#define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER3_HI +#define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER3_LO +#define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_LO +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_LO +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_LO +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_LO +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_LO +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_LO +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_LO +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_LO +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER0_LO +#define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER0_HI +#define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER1_LO +#define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER1_HI +#define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER2_LO +#define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER2_HI +#define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER3_LO +#define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER3_HI +#define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER4_LO +#define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER4_HI +#define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER5_LO +#define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER5_HI +#define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER6_LO +#define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER6_HI +#define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER7_LO +#define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER7_HI +#define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_LO +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_LO +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_HI +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_LO +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_HI +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_LO +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_HI +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER2_LO +#define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER2_HI +#define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER_LO +#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER_HI +#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//GDS_PERFCOUNTER0_LO +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER0_HI +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_LO +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_HI +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_LO +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_HI +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_LO +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_HI +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_LO +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_HI +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_LO +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_HI +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_LO +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_HI +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_LO +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_HI +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_LO +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_HI +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_LO +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_HI +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_LO +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_HI +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_LO +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_HI +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER_FILTER +#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xd +#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x11 +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x16 +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x18 +#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1b +#define TCP_PERFCOUNTER_FILTER__DLC__SHIFT 0x1c +#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x1d +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1e +#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x00000FE0L +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x0001E000L +#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x003E0000L +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00C00000L +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x07000000L +#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x08000000L +#define TCP_PERFCOUNTER_FILTER__DLC_MASK 0x10000000L +#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x20000000L +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x40000000L +//TCP_PERFCOUNTER_FILTER2 +#define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK 0x00000007L +//TCP_PERFCOUNTER_FILTER_EN +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 +#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x8 +#define TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT 0x9 +#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0xa +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT 0xc +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L +#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000100L +#define TCP_PERFCOUNTER_FILTER_EN__DLC_MASK 0x00000200L +#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000400L +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000800L +#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK 0x00001000L +//GL2C_PERFCOUNTER0_LO +#define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2C_PERFCOUNTER0_HI +#define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL2C_PERFCOUNTER1_LO +#define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2C_PERFCOUNTER1_HI +#define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL2C_PERFCOUNTER2_LO +#define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2C_PERFCOUNTER2_HI +#define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL2C_PERFCOUNTER3_LO +#define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2C_PERFCOUNTER3_HI +#define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER0_LO +#define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER0_HI +#define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER1_LO +#define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER1_HI +#define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER2_LO +#define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER2_HI +#define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER3_LO +#define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL2A_PERFCOUNTER3_HI +#define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER0_LO +#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER0_HI +#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER1_LO +#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER1_HI +#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER2_LO +#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER2_HI +#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER3_LO +#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER3_HI +#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER0_LO +#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER0_HI +#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER1_LO +#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER1_HI +#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER2_LO +#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER2_HI +#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER3_LO +#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER3_HI +#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER0_LO +#define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER0_HI +#define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER1_LO +#define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER1_HI +#define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER2_LO +#define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER2_HI +#define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER3_LO +#define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHCG_PERFCOUNTER3_HI +#define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_LO +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_HI +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_LO +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_HI +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_LO +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_HI +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_LO +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_HI +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_LO +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_HI +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_LO +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_HI +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_LO +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_HI +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_LO +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_HI +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_LO +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_HI +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_LO +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_HI +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_LO +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_HI +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_LO +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_HI +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_LO +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_HI +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_LO +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_HI +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_LO +#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_HI +#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER1_LO +#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER1_HI +#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER0_LO +#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER0_HI +#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER1_LO +#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER1_HI +#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER2_LO +#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER2_HI +#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER3_LO +#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER3_HI +#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER4_LO +#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER4_HI +#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER5_LO +#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER5_HI +#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER6_LO +#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER6_HI +#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER7_LO +#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER7_HI +#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER0_LO +#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER0_HI +#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER1_LO +#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER1_HI +#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER2_LO +#define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER2_HI +#define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER3_LO +#define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER3_HI +#define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER0_LO +#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER0_HI +#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER1_LO +#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER1_HI +#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER2_LO +#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER2_HI +#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER3_LO +#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER3_HI +#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER0_LO +#define GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER0_HI +#define GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER1_LO +#define GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER1_HI +#define GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER2_LO +#define GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER2_HI +#define GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER3_LO +#define GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1H_PERFCOUNTER3_HI +#define GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER0_LO +#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER0_HI +#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER1_LO +#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER1_HI +#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER2_LO +#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER2_HI +#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER3_LO +#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER3_HI +#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GUS_PERFCOUNTER2_LO +#define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GUS_PERFCOUNTER2_HI +#define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GUS_PERFCOUNTER_LO +#define GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GUS_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GUS_PERFCOUNTER_HI +#define GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GUS_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: gc_perfsdec +//CPG_PERFCOUNTER1_SELECT +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT1 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER1_SELECT +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPC_PERFCOUNTER0_SELECT1 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER1_SELECT +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT1 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//CPC_PERFCOUNTER0_SELECT +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_TC_PERF_COUNTER_WINDOW_SELECT +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPG_TC_PERF_COUNTER_WINDOW_SELECT +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPF_LATENCY_STATS_SELECT +#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL +#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPG_LATENCY_STATS_SELECT +#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_LATENCY_STATS_SELECT +#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL +#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_TC_PERF_COUNTER_WINDOW_SELECT +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CP_DRAW_OBJECT +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL +//CP_DRAW_OBJECT_COUNTER +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL +//CP_DRAW_WINDOW_MASK_HI +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_HI +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_LO +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L +//CP_DRAW_WINDOW_CNTL +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L +//GRBM_PERFCOUNTER0_SELECT +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_PERFCOUNTER1_SELECT +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_SE0_PERFCOUNTER_SELECT +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +//GRBM_SE1_PERFCOUNTER_SELECT +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +//GRBM_SE2_PERFCOUNTER_SELECT +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +//GRBM_SE3_PERFCOUNTER_SELECT +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +//GRBM_SE4_PERFCOUNTER_SELECT +#define GRBM_SE4_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE4_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE4_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE4_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE4_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE4_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE4_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE4_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE4_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE4_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE4_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE4_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE4_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_SE4_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_SE4_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_SE4_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_SE4_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_SE4_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE4_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE4_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE4_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE4_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE4_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE4_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE4_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE4_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE4_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE4_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE4_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE4_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE4_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_SE4_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_SE4_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_SE4_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_SE4_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_SE4_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +//GRBM_SE5_PERFCOUNTER_SELECT +#define GRBM_SE5_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE5_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE5_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE5_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE5_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE5_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE5_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE5_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE5_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE5_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE5_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE5_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE5_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_SE5_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_SE5_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_SE5_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_SE5_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_SE5_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE5_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE5_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE5_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE5_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE5_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE5_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE5_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE5_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE5_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE5_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE5_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE5_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE5_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_SE5_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_SE5_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_SE5_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_SE5_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_SE5_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +//GRBM_SE6_PERFCOUNTER_SELECT +#define GRBM_SE6_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE6_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE6_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE6_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE6_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE6_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE6_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE6_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE6_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE6_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE6_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE6_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE6_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_SE6_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_SE6_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_SE6_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_SE6_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_SE6_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE6_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE6_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE6_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE6_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE6_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE6_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE6_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE6_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE6_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE6_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE6_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE6_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE6_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_SE6_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_SE6_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_SE6_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_SE6_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_SE6_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +//GRBM_PERFCOUNTER0_SELECT_HI +#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 +#define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 +#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 +#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 +#define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 +#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L +#define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L +#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L +#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L +#define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L +#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x00000200L +//GRBM_PERFCOUNTER1_SELECT_HI +#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 +#define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 +#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 +#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 +#define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 +#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L +#define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L +#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L +#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L +#define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L +#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x00000200L +//GE1_PERFCOUNTER0_SELECT +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER0_SELECT1 +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER1_SELECT +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER1_SELECT1 +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER2_SELECT +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER2_SELECT1 +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER3_SELECT +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER3_SELECT1 +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER0_SELECT +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER0_SELECT1 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER1_SELECT +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER1_SELECT1 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER2_SELECT +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER2_SELECT1 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER3_SELECT +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER3_SELECT1 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER0_SELECT +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER0_SELECT1 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER1_SELECT +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER1_SELECT1 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER2_SELECT +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER2_SELECT1 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER3_SELECT +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER3_SELECT1 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER0_SELECT1 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT1 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT1 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT1 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT1 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER1_SELECT +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER2_SELECT +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER3_SELECT +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER4_SELECT +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER5_SELECT +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER6_SELECT +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER7_SELECT +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER0_SELECT +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER0_SELECT1 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT1 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT1 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT1 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER5_SELECT +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER_BINS +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L +//PC_PERFCOUNTER0_SELECT +#define PC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER1_SELECT +#define PC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER2_SELECT +#define PC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER3_SELECT +#define PC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER0_SELECT1 +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER1_SELECT1 +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER2_SELECT1 +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER3_SELECT1 +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER4_SELECT +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER5_SELECT +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER6_SELECT +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER7_SELECT +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER8_SELECT +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER9_SELECT +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER10_SELECT +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER11_SELECT +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER12_SELECT +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER13_SELECT +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER14_SELECT +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER15_SELECT +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER0_SELECT +#define SQG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER1_SELECT +#define SQG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER2_SELECT +#define SQG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER3_SELECT +#define SQG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER4_SELECT +#define SQG_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER5_SELECT +#define SQG_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER6_SELECT +#define SQG_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER7_SELECT +#define SQG_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER_CTRL +#define SQG_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQG_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQG_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQG_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 +#define SQG_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQG_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQG_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQG_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L +//SQG_PERFCOUNTER_CTRL2 +#define SQG_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQG_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 +#define SQG_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQG_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL +//SQG_PERF_SAMPLE_FINISH +#define SQG_PERF_SAMPLE_FINISH__STATUS__SHIFT 0x0 +#define SQG_PERF_SAMPLE_FINISH__STATUS_MASK 0x0000007FL +//SQ_PERFCOUNTER_CTRL +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L +//SQ_PERFCOUNTER_CTRL2 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL +//SQ_THREAD_TRACE_BUF0_BASE +#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BUF0_SIZE +#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x8 +#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK 0x0000000FL +#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x3FFFFF00L +//SQ_THREAD_TRACE_BUF1_BASE +#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BUF1_SIZE +#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x8 +#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK 0x0000000FL +#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x3FFFFF00L +//SQ_THREAD_TRACE_CTRL +#define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0 +#define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT 0x2 +#define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN__SHIFT 0x3 +#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4 +#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5 +#define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6 +#define SQ_THREAD_TRACE_CTRL__REG_AT_HWM__SHIFT 0x9 +#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xb +#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xc +#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xd +#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xe +#define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT 0x10 +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12 +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13 +#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT 0x14 +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT 0x1c +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L +#define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK 0x00000004L +#define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN_MASK 0x00000008L +#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L +#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L +#define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L +#define SQ_THREAD_TRACE_CTRL__REG_AT_HWM_MASK 0x00000600L +#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000800L +#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00001000L +#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00002000L +#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x0000C000L +#define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK 0x00030000L +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L +#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK 0x00700000L +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK 0x10000000L +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L +//SQ_THREAD_TRACE_MASK +#define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4 +#define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9 +#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA__SHIFT 0x11 +#define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L +#define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L +#define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L +#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA_MASK 0x00020000L +//SQ_THREAD_TRACE_TOKEN_MASK +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC__SHIFT 0xb +#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT 0xc +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT 0x1a +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x000007FFL +#define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC_MASK 0x00000800L +#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK 0x00001000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK 0x1C000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L +//SQ_THREAD_TRACE_WPTR +#define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f +#define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL +#define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L +//SQ_THREAD_TRACE_STATUS +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc +#define SQ_THREAD_TRACE_STATUS__WRITE_ERROR__SHIFT 0x18 +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19 +#define SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT 0x1c +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L +#define SQ_THREAD_TRACE_STATUS__WRITE_ERROR_MASK 0x01000000L +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L +#define SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK 0xF0000000L +//SQ_THREAD_TRACE_STATUS2 +#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT 0x1 +#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT 0x4 +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS__SHIFT 0x8 +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE__SHIFT 0xd +#define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL__SHIFT 0xe +#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK 0x00000001L +#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK 0x00000002L +#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK 0x00000010L +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS_MASK 0x00001F00L +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_MASK 0x00002000L +#define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL_MASK 0x00004000L +//SQ_THREAD_TRACE_GFX_DRAW_CNTR +#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_GFX_MARKER_CNTR +#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_HP3D_DRAW_CNTR +#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_HP3D_MARKER_CNTR +#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_DROPPED_CNTR +#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER2_SELECT +#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GCEA_PERFCOUNTER2_SELECT1 +#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GCEA_PERFCOUNTER2_MODE +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L +#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L +#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L +//GCEA_PERFCOUNTER0_CFG +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCEA_PERFCOUNTER1_CFG +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCEA_PERFCOUNTER_RSLT_CNTL +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT +#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER2_SELECT +#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER3_SELECT +#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER0_SELECT1 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT1 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GDS_PERFCOUNTER0_SELECT +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER1_SELECT +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER2_SELECT +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER3_SELECT +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER0_SELECT1 +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GDS_PERFCOUNTER1_SELECT1 +#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GDS_PERFCOUNTER2_SELECT1 +#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GDS_PERFCOUNTER3_SELECT1 +#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT1 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER1_SELECT +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT1 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TD_PERFCOUNTER1_SELECT +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT1 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT1 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER0_SELECT +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER0_SELECT1 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//GL2C_PERFCOUNTER1_SELECT +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER1_SELECT1 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//GL2C_PERFCOUNTER2_SELECT +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER3_SELECT +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER0_SELECT +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER0_SELECT1 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//GL2A_PERFCOUNTER1_SELECT +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER1_SELECT1 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//GL2A_PERFCOUNTER2_SELECT +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER3_SELECT +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER0_SELECT +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER0_SELECT1 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//GL1C_PERFCOUNTER1_SELECT +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER2_SELECT +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER3_SELECT +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER0_SELECT +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER0_SELECT1 +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//CHC_PERFCOUNTER1_SELECT +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER2_SELECT +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER3_SELECT +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CHCG_PERFCOUNTER0_SELECT +#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CHCG_PERFCOUNTER0_SELECT1 +#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//CHCG_PERFCOUNTER1_SELECT +#define CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CHCG_PERFCOUNTER2_SELECT +#define CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CHCG_PERFCOUNTER3_SELECT +#define CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER_FILTER +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L +//CB_PERFCOUNTER0_SELECT +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER0_SELECT1 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER1_SELECT +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER2_SELECT +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER3_SELECT +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT1 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT1 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RLC_SPM_PERFMON_CNTL +#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xf +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L +#define RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT_MASK 0x00004000L +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x00008000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_BASE_LO +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_RING_BASE_HI +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_SIZE +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL +//RLC_SPM_RING_WRPTR +#define RLC_SPM_RING_WRPTR__RESERVED__SHIFT 0x0 +#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT 0x5 +#define RLC_SPM_RING_WRPTR__RESERVED_MASK 0x0000001FL +#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK 0xFFFFFFE0L +//RLC_SPM_RING_RDPTR +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL +//RLC_SPM_SEGMENT_THRESHOLD +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT 0x8 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0x000000FFL +#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PERFMON_SEGMENT_SIZE +#define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT__SHIFT 0x18 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT_MASK 0x0000FFFFL +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT_MASK 0x00FF0000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT_MASK 0xFF000000L +//RLC_SPM_GLOBAL_MUXSEL_ADDR +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_GLOBAL_MUXSEL_DATA +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1__SHIFT 0x10 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L +//RLC_SPM_SE_MUXSEL_ADDR +#define RLC_SPM_SE_MUXSEL_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_SE_MUXSEL_DATA +#define RLC_SPM_SE_MUXSEL_DATA__SEL0__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__SEL1__SHIFT 0x10 +#define RLC_SPM_SE_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL +#define RLC_SPM_SE_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L +//RLC_SPM_ACCUM_DATARAM_ADDR +#define RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT 0x7 +#define RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK 0x0000007FL +#define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L +//RLC_SPM_ACCUM_DATARAM_DATA +#define RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_DATA__data_MASK 0xFFFFFFFFL +//RLC_SPM_ACCUM_SWA_DATARAM_ADDR +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr__SHIFT 0x0 +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED__SHIFT 0x7 +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr_MASK 0x0000007FL +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L +//RLC_SPM_ACCUM_SWA_DATARAM_DATA +#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data__SHIFT 0x0 +#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data_MASK 0xFFFFFFFFL +//RLC_SPM_ACCUM_CTRLRAM_ADDR +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT 0xb +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK 0x000007FFL +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK 0xFFFFF800L +//RLC_SPM_ACCUM_CTRLRAM_DATA +#define RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT 0x8 +#define RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK 0x000000FFL +#define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT 0x8 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT 0x10 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED__SHIFT 0x18 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK 0x000000FFL +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK 0x0000FF00L +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK 0x00FF0000L +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED_MASK 0xFF000000L +//RLC_SPM_ACCUM_STATUS +#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT 0x0 +#define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT 0x8 +#define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT 0x9 +#define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa +#define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT 0xb +#define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT 0xc +#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT 0xd +#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT 0xe +#define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT 0xf +#define RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT 0x10 +#define RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT 0x11 +#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT 0x12 +#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT 0x13 +#define RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT 0x14 +#define RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT 0x15 +#define RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT 0x16 +#define RLC_SPM_ACCUM_STATUS__MultiSampleAborted__SHIFT 0x17 +#define RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT 0x18 +#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK 0x000000FFL +#define RLC_SPM_ACCUM_STATUS__AccumDone_MASK 0x00000100L +#define RLC_SPM_ACCUM_STATUS__SpmDone_MASK 0x00000200L +#define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK 0x00000400L +#define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK 0x00000800L +#define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK 0x00001000L +#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK 0x00002000L +#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK 0x00004000L +#define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK 0x00008000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK 0x00010000L +#define RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK 0x00020000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK 0x00040000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK 0x00080000L +#define RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK 0x00100000L +#define RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK 0x00200000L +#define RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK 0x00400000L +#define RLC_SPM_ACCUM_STATUS__MultiSampleAborted_MASK 0x00800000L +#define RLC_SPM_ACCUM_STATUS__RESERVED_MASK 0xFF000000L +//RLC_SPM_ACCUM_CTRL +#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT 0x1 +#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT 0x2 +#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT 0x3 +#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT 0x4 +#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT 0x8 +#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT 0x9 +#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT 0xa +#define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT 0xb +#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK 0x00000001L +#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK 0x00000002L +#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK 0x00000004L +#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK 0x00000008L +#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK 0x000000F0L +#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK 0x00000100L +#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK 0x00000200L +#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK 0x00000400L +#define RLC_SPM_ACCUM_CTRL__RESERVED_MASK 0xFFFFF800L +//RLC_SPM_ACCUM_MODE +#define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT 0x0 +#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT 0x1 +#define RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT 0x2 +#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT 0x3 +#define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT 0x5 +#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT 0x6 +#define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT 0x7 +#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT 0x8 +#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT 0x9 +#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT 0xa +#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT 0xb +#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT 0xc +#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT 0xd +#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT 0xe +#define RLC_SPM_ACCUM_MODE__SE2_LoadOverride__SHIFT 0xf +#define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride__SHIFT 0x10 +#define RLC_SPM_ACCUM_MODE__SE3_LoadOverride__SHIFT 0x11 +#define RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride__SHIFT 0x12 +#define RLC_SPM_ACCUM_MODE__SE4_LoadOverride__SHIFT 0x13 +#define RLC_SPM_ACCUM_MODE__SE4_SwaLoadOverride__SHIFT 0x14 +#define RLC_SPM_ACCUM_MODE__SE5_LoadOverride__SHIFT 0x15 +#define RLC_SPM_ACCUM_MODE__SE5_SwaLoadOverride__SHIFT 0x16 +#define RLC_SPM_ACCUM_MODE__EnableAccum_MASK 0x00000001L +#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK 0x00000002L +#define RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK 0x00000004L +#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK 0x00000008L +#define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK 0x00000020L +#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK 0x00000040L +#define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK 0x00000080L +#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK 0x00000100L +#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK 0x00000200L +#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK 0x00000400L +#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK 0x00000800L +#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK 0x00001000L +#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK 0x00002000L +#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK 0x00004000L +#define RLC_SPM_ACCUM_MODE__SE2_LoadOverride_MASK 0x00008000L +#define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride_MASK 0x00010000L +#define RLC_SPM_ACCUM_MODE__SE3_LoadOverride_MASK 0x00020000L +#define RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride_MASK 0x00040000L +#define RLC_SPM_ACCUM_MODE__SE4_LoadOverride_MASK 0x00080000L +#define RLC_SPM_ACCUM_MODE__SE4_SwaLoadOverride_MASK 0x00100000L +#define RLC_SPM_ACCUM_MODE__SE5_LoadOverride_MASK 0x00200000L +#define RLC_SPM_ACCUM_MODE__SE5_SwaLoadOverride_MASK 0x00400000L +//RLC_SPM_ACCUM_THRESHOLD +#define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT 0x0 +#define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK 0x0000FFFFL +//RLC_SPM_ACCUM_SAMPLES_REQUESTED +#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT 0x0 +#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK 0x000000FFL +//RLC_SPM_ACCUM_DATARAM_WRCOUNT +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT 0x13 +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK 0x0007FFFFL +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK 0xFFF80000L +//RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT 0x8 +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED__SHIFT 0x10 +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK 0x000000FFL +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK 0x0000FF00L +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED_MASK 0xFFFF0000L +//RLC_SPM_PAUSE +#define RLC_SPM_PAUSE__PAUSE__SHIFT 0x0 +#define RLC_SPM_PAUSE__PAUSED__SHIFT 0x1 +#define RLC_SPM_PAUSE__PAUSE_MASK 0x00000001L +#define RLC_SPM_PAUSE__PAUSED_MASK 0x00000002L +//RLC_SPM_STATUS +#define RLC_SPM_STATUS__CTL_BUSY__SHIFT 0x0 +#define RLC_SPM_STATUS__RSPM_REG_BUSY__SHIFT 0x1 +#define RLC_SPM_STATUS__SPM_RSPM_BUSY__SHIFT 0x2 +#define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY__SHIFT 0x3 +#define RLC_SPM_STATUS__SE_RSPM_IO_BUSY__SHIFT 0x4 +#define RLC_SPM_STATUS__ACCUM_BUSY__SHIFT 0xf +#define RLC_SPM_STATUS__FSM_MASTER_STATE__SHIFT 0x10 +#define RLC_SPM_STATUS__FSM_MEMORY_STATE__SHIFT 0x14 +#define RLC_SPM_STATUS__CTL_REQ_STATE__SHIFT 0x18 +#define RLC_SPM_STATUS__CTL_RET_STATE__SHIFT 0x1a +#define RLC_SPM_STATUS__CTL_BUSY_MASK 0x00000001L +#define RLC_SPM_STATUS__RSPM_REG_BUSY_MASK 0x00000002L +#define RLC_SPM_STATUS__SPM_RSPM_BUSY_MASK 0x00000004L +#define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY_MASK 0x00000008L +#define RLC_SPM_STATUS__SE_RSPM_IO_BUSY_MASK 0x00000FF0L +#define RLC_SPM_STATUS__ACCUM_BUSY_MASK 0x00008000L +#define RLC_SPM_STATUS__FSM_MASTER_STATE_MASK 0x000F0000L +#define RLC_SPM_STATUS__FSM_MEMORY_STATE_MASK 0x00F00000L +#define RLC_SPM_STATUS__CTL_REQ_STATE_MASK 0x03000000L +#define RLC_SPM_STATUS__CTL_RET_STATE_MASK 0x04000000L +//RLC_SPM_GFXCLOCK_LOWCOUNT +#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT 0x0 +#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK 0xFFFFFFFFL +//RLC_SPM_GFXCLOCK_HIGHCOUNT +#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT 0x0 +#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK 0xFFFFFFFFL +//RLC_SPM_MODE +#define RLC_SPM_MODE__MODE__SHIFT 0x0 +#define RLC_SPM_MODE__MODE_MASK 0x00000001L +//RLC_SPM_RSPM_REQ_DATA_LO +#define RLC_SPM_RSPM_REQ_DATA_LO__DATA__SHIFT 0x0 +#define RLC_SPM_RSPM_REQ_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_RSPM_REQ_DATA_HI +#define RLC_SPM_RSPM_REQ_DATA_HI__DATA__SHIFT 0x0 +#define RLC_SPM_RSPM_REQ_DATA_HI__DATA_MASK 0x00000FFFL +//RLC_SPM_RSPM_REQ_OP +#define RLC_SPM_RSPM_REQ_OP__OP__SHIFT 0x0 +#define RLC_SPM_RSPM_REQ_OP__OP_MASK 0x0000000FL +//RLC_SPM_RSPM_RET_DATA +#define RLC_SPM_RSPM_RET_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_RSPM_RET_OP +#define RLC_SPM_RSPM_RET_OP__OP__SHIFT 0x0 +#define RLC_SPM_RSPM_RET_OP__VALID__SHIFT 0x8 +#define RLC_SPM_RSPM_RET_OP__OP_MASK 0x0000000FL +#define RLC_SPM_RSPM_RET_OP__VALID_MASK 0x00000100L +//RLC_SPM_SE_RSPM_REQ_DATA_LO +#define RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_SE_RSPM_REQ_DATA_HI +#define RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA_MASK 0x00000FFFL +//RLC_SPM_SE_RSPM_REQ_OP +#define RLC_SPM_SE_RSPM_REQ_OP__OP__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_REQ_OP__OP_MASK 0x0000000FL +//RLC_SPM_SE_RSPM_RET_DATA +#define RLC_SPM_SE_RSPM_RET_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_SE_RSPM_RET_OP +#define RLC_SPM_SE_RSPM_RET_OP__OP__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_RET_OP__VALID__SHIFT 0x8 +#define RLC_SPM_SE_RSPM_RET_OP__OP_MASK 0x0000000FL +#define RLC_SPM_SE_RSPM_RET_OP__VALID_MASK 0x00000100L +//RLC_SPM_RSPM_CMD +#define RLC_SPM_RSPM_CMD__CMD__SHIFT 0x0 +#define RLC_SPM_RSPM_CMD__CMD_MASK 0x0000000FL +//RLC_SPM_RSPM_CMD_ACK +#define RLC_SPM_RSPM_CMD_ACK__SE0_ACK__SHIFT 0x0 +#define RLC_SPM_RSPM_CMD_ACK__SE1_ACK__SHIFT 0x1 +#define RLC_SPM_RSPM_CMD_ACK__SE2_ACK__SHIFT 0x2 +#define RLC_SPM_RSPM_CMD_ACK__SE3_ACK__SHIFT 0x3 +#define RLC_SPM_RSPM_CMD_ACK__SE4_ACK__SHIFT 0x4 +#define RLC_SPM_RSPM_CMD_ACK__SE5_ACK__SHIFT 0x5 +#define RLC_SPM_RSPM_CMD_ACK__SE6_ACK__SHIFT 0x6 +#define RLC_SPM_RSPM_CMD_ACK__SE7_ACK__SHIFT 0x7 +#define RLC_SPM_RSPM_CMD_ACK__SPM_ACK__SHIFT 0x8 +#define RLC_SPM_RSPM_CMD_ACK__SE0_ACK_MASK 0x00000001L +#define RLC_SPM_RSPM_CMD_ACK__SE1_ACK_MASK 0x00000002L +#define RLC_SPM_RSPM_CMD_ACK__SE2_ACK_MASK 0x00000004L +#define RLC_SPM_RSPM_CMD_ACK__SE3_ACK_MASK 0x00000008L +#define RLC_SPM_RSPM_CMD_ACK__SE4_ACK_MASK 0x00000010L +#define RLC_SPM_RSPM_CMD_ACK__SE5_ACK_MASK 0x00000020L +#define RLC_SPM_RSPM_CMD_ACK__SE6_ACK_MASK 0x00000040L +#define RLC_SPM_RSPM_CMD_ACK__SE7_ACK_MASK 0x00000080L +#define RLC_SPM_RSPM_CMD_ACK__SPM_ACK_MASK 0x00000100L +//RLC_SPM_SPARE +#define RLC_SPM_SPARE__SPARE__SHIFT 0x0 +#define RLC_SPM_SPARE__SPARE_MASK 0xFFFFFFFFL +//RLC_PERFMON_CNTL +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//RLC_PERFCOUNTER0_SELECT +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL +//RLC_PERFCOUNTER1_SELECT +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL +//RLC_GPU_IOV_PERF_CNT_CNTL +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_GPU_IOV_PERF_CNT_WR_ADDR +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_WR_DATA +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_PERF_CNT_RD_ADDR +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_RD_DATA +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_SELECT +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT1 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER1_SELECT +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT1 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER3_SELECT +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERF_COUNTER_CNTL +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L +//GCR_PERFCOUNTER0_SELECT +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GCR_PERFCOUNTER0_SELECT1 +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GCR_PERFCOUNTER1_SELECT +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GCR_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCR_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER0_SELECT +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER0_SELECT1 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER1_SELECT +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER2_SELECT +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER3_SELECT +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER4_SELECT +#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER5_SELECT +#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER6_SELECT +#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER7_SELECT +#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER1_SELECT1 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER2_SELECT1 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER3_SELECT1 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//UTCL1_PERFCOUNTER0_SELECT +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER1_SELECT +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER2_SELECT +#define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER3_SELECT +#define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER0_SELECT +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER0_SELECT1 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//GL1A_PERFCOUNTER1_SELECT +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER2_SELECT +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER3_SELECT +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1H_PERFCOUNTER0_SELECT +#define GL1H_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1H_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1H_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1H_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1H_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1H_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1H_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1H_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1H_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1H_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1H_PERFCOUNTER0_SELECT1 +#define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//GL1H_PERFCOUNTER1_SELECT +#define GL1H_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1H_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1H_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1H_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1H_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1H_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1H_PERFCOUNTER2_SELECT +#define GL1H_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1H_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1H_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1H_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1H_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1H_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1H_PERFCOUNTER3_SELECT +#define GL1H_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1H_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1H_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1H_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1H_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1H_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER0_SELECT +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER0_SELECT1 +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//CHA_PERFCOUNTER1_SELECT +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER2_SELECT +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER3_SELECT +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GUS_PERFCOUNTER2_SELECT +#define GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GUS_PERFCOUNTER2_SELECT1 +#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GUS_PERFCOUNTER2_MODE +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L +#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L +#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L +//GUS_PERFCOUNTER0_CFG +#define GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GUS_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GUS_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GUS_PERFCOUNTER1_CFG +#define GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GUS_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GUS_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GUS_PERFCOUNTER_RSLT_CNTL +#define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_grtavfs_grtavfs_dec +//GRTAVFS_RTAVFS_REG_ADDR +#define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 +#define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL +//GRTAVFS_RTAVFS_WR_DATA +#define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 +#define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL +//GRTAVFS_GENERAL_0 +#define GRTAVFS_GENERAL_0__DATA__SHIFT 0x0 +#define GRTAVFS_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//GRTAVFS_RTAVFS_RD_DATA +#define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT 0x0 +#define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL +//GRTAVFS_RTAVFS_REG_CTRL +#define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT 0x0 +#define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT 0x1 +#define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN_MASK 0x00000001L +#define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN_MASK 0x00000002L +//GRTAVFS_RTAVFS_REG_STATUS +#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT 0x0 +#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT 0x1 +#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK 0x00000001L +#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK 0x00000002L +//GRTAVFS_TARG_FREQ +#define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY__SHIFT 0x0 +#define GRTAVFS_TARG_FREQ__REQUEST__SHIFT 0x10 +#define GRTAVFS_TARG_FREQ__RESERVED__SHIFT 0x11 +#define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY_MASK 0x0000FFFFL +#define GRTAVFS_TARG_FREQ__REQUEST_MASK 0x00010000L +#define GRTAVFS_TARG_FREQ__RESERVED_MASK 0xFFFE0000L +//GRTAVFS_TARG_VOLT +#define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE__SHIFT 0x0 +#define GRTAVFS_TARG_VOLT__VALID__SHIFT 0xa +#define GRTAVFS_TARG_VOLT__RESERVED__SHIFT 0xb +#define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE_MASK 0x000003FFL +#define GRTAVFS_TARG_VOLT__VALID_MASK 0x00000400L +#define GRTAVFS_TARG_VOLT__RESERVED_MASK 0xFFFFF800L +//GRTAVFS_SOFT_RESET +#define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE__SHIFT 0x0 +#define GRTAVFS_SOFT_RESET__RESERVED__SHIFT 0x1 +#define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE_MASK 0x00000001L +#define GRTAVFS_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL +//GRTAVFS_PSM_CNTL +#define GRTAVFS_PSM_CNTL__PSM_COUNT__SHIFT 0x0 +#define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN__SHIFT 0xe +#define GRTAVFS_PSM_CNTL__RESERVED__SHIFT 0xf +#define GRTAVFS_PSM_CNTL__PSM_COUNT_MASK 0x00003FFFL +#define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN_MASK 0x00004000L +#define GRTAVFS_PSM_CNTL__RESERVED_MASK 0xFFFF8000L +//GRTAVFS_CLK_CNTL +#define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT 0x0 +#define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT 0x1 +#define GRTAVFS_CLK_CNTL__RESERVED__SHIFT 0x2 +#define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK 0x00000001L +#define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK 0x00000002L +#define GRTAVFS_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL + + +// addressBlock: gc_grtavfs_se_grtavfs_dec +//GRTAVFS_SE_RTAVFS_REG_ADDR +#define GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 +#define GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL +//GRTAVFS_SE_RTAVFS_WR_DATA +#define GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 +#define GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL +//GRTAVFS_SE_GENERAL_0 +#define GRTAVFS_SE_GENERAL_0__DATA__SHIFT 0x0 +#define GRTAVFS_SE_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//GRTAVFS_SE_RTAVFS_RD_DATA +#define GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT 0x0 +#define GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL +//GRTAVFS_SE_RTAVFS_REG_CTRL +#define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT 0x0 +#define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT 0x1 +#define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN_MASK 0x00000001L +#define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN_MASK 0x00000002L +//GRTAVFS_SE_RTAVFS_REG_STATUS +#define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT 0x0 +#define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT 0x1 +#define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK 0x00000001L +#define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK 0x00000002L +//GRTAVFS_SE_TARG_FREQ +#define GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY__SHIFT 0x0 +#define GRTAVFS_SE_TARG_FREQ__REQUEST__SHIFT 0x10 +#define GRTAVFS_SE_TARG_FREQ__RESERVED__SHIFT 0x11 +#define GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY_MASK 0x0000FFFFL +#define GRTAVFS_SE_TARG_FREQ__REQUEST_MASK 0x00010000L +#define GRTAVFS_SE_TARG_FREQ__RESERVED_MASK 0xFFFE0000L +//GRTAVFS_SE_TARG_VOLT +#define GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE__SHIFT 0x0 +#define GRTAVFS_SE_TARG_VOLT__VALID__SHIFT 0xa +#define GRTAVFS_SE_TARG_VOLT__RESERVED__SHIFT 0xb +#define GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE_MASK 0x000003FFL +#define GRTAVFS_SE_TARG_VOLT__VALID_MASK 0x00000400L +#define GRTAVFS_SE_TARG_VOLT__RESERVED_MASK 0xFFFFF800L +//GRTAVFS_SE_SOFT_RESET +#define GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE__SHIFT 0x0 +#define GRTAVFS_SE_SOFT_RESET__RESERVED__SHIFT 0x1 +#define GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE_MASK 0x00000001L +#define GRTAVFS_SE_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL +//GRTAVFS_SE_PSM_CNTL +#define GRTAVFS_SE_PSM_CNTL__PSM_COUNT__SHIFT 0x0 +#define GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN__SHIFT 0xe +#define GRTAVFS_SE_PSM_CNTL__RESERVED__SHIFT 0xf +#define GRTAVFS_SE_PSM_CNTL__PSM_COUNT_MASK 0x00003FFFL +#define GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN_MASK 0x00004000L +#define GRTAVFS_SE_PSM_CNTL__RESERVED_MASK 0xFFFF8000L +//GRTAVFS_SE_CLK_CNTL +#define GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT 0x0 +#define GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT 0x1 +#define GRTAVFS_SE_CLK_CNTL__RESERVED__SHIFT 0x2 +#define GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK 0x00000001L +#define GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK 0x00000002L +#define GRTAVFS_SE_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL + + +// addressBlock: gc_grtavfsdec +//RTAVFS_RTAVFS_REG_ADDR +#define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 +#define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL +//RTAVFS_RTAVFS_WR_DATA +#define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 +#define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_cphypdec +//CP_HYP_PFP_UCODE_ADDR +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL +//CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL +//CP_HYP_PFP_UCODE_DATA +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_ADDR +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL +//CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000FFFFFL +//CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x001FFFFFL +//CP_HYP_ME_UCODE_DATA +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC1_UCODE_ADDR +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL +//CP_MEC_ME1_UCODE_ADDR +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL +//CP_HYP_MEC1_UCODE_DATA +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME1_UCODE_DATA +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC2_UCODE_ADDR +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL +//CP_MEC_ME2_UCODE_ADDR +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL +//CP_HYP_MEC2_UCODE_DATA +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME2_UCODE_DATA +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_PFP_IC_BASE_LO +#define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_PFP_IC_BASE_HI +#define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_PFP_IC_BASE_CNTL +#define CP_PFP_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 +#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_PFP_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L +#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_PFP_IC_OP_CNTL +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_ME_IC_BASE_LO +#define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_ME_IC_BASE_HI +#define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_ME_IC_BASE_CNTL +#define CP_ME_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 +#define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_ME_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L +#define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_ME_IC_OP_CNTL +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_CPC_IC_BASE_LO +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_CPC_IC_BASE_HI +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_CPC_IC_BASE_CNTL +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 +#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L +#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MES_IC_BASE_LO +#define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_MES_MIBASE_LO +#define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_MES_IC_BASE_HI +#define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_MES_MIBASE_HI +#define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_MES_IC_BASE_CNTL +#define CP_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MES_DC_BASE_LO +#define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_MES_MDBASE_LO +#define CP_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_DC_BASE_HI +#define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_MES_MDBASE_HI +#define CP_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_MES_MIBOUND_LO +#define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MES_MIBOUND_HI +#define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_MES_MDBOUND_LO +#define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MES_MDBOUND_HI +#define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_BASE0_LO +#define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_DC_BASE1_LO +#define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_DC_BASE0_HI +#define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_DC_BASE1_HI +#define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_MIBOUND_LO +#define CP_GFX_RS64_MIBOUND_LO__BOUND__SHIFT 0x0 +#define CP_GFX_RS64_MIBOUND_LO__BOUND_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIBOUND_HI +#define CP_GFX_RS64_MIBOUND_HI__BOUND__SHIFT 0x0 +#define CP_GFX_RS64_MIBOUND_HI__BOUND_MASK 0xFFFFFFFFL +//CP_MEC_DC_BASE_LO +#define CP_MEC_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_MEC_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_MEC_MDBASE_LO +#define CP_MEC_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_DC_BASE_HI +#define CP_MEC_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_MEC_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_MEC_MDBASE_HI +#define CP_MEC_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_MEC_MIBOUND_LO +#define CP_MEC_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MEC_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MEC_MIBOUND_HI +#define CP_MEC_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MEC_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_MEC_MDBOUND_LO +#define CP_MEC_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MEC_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MEC_MDBOUND_HI +#define CP_MEC_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MEC_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL + + +// addressBlock: gc_rlcdec +//RLC_CNTL +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__RESERVED__SHIFT 0x4 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L +//RLC_F32_UCODE_VERSION +#define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT 0x0 +#define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa +#define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT 0x14 +#define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK 0x000003FFL +#define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK 0x000FFC00L +#define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK 0x3FF00000L +//RLC_STAT +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 +#define RLC_STAT__MC_BUSY__SHIFT 0x4 +#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 +#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 +#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 +#define RLC_STAT__RESERVED__SHIFT 0x8 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L +#define RLC_STAT__MC_BUSY_MASK 0x00000010L +#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L +#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L +#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L +#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L +//RLC_REFCLOCK_TIMESTAMP_LSB +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL +//RLC_REFCLOCK_TIMESTAMP_MSB +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_0 +#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_1 +#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_2 +#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_3 +#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_4 +#define RLC_GPM_TIMER_INT_4__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_4__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_CTRL +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 +#define RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT 0x4 +#define RLC_GPM_TIMER_CTRL__RESERVED_1__SHIFT 0x5 +#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x8 +#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x9 +#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0xa +#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT 0xb +#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT 0xc +#define RLC_GPM_TIMER_CTRL__RESERVED_2__SHIFT 0xd +#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x10 +#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x11 +#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0x12 +#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT 0x13 +#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT 0x14 +#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x15 +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L +#define RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK 0x00000010L +#define RLC_GPM_TIMER_CTRL__RESERVED_1_MASK 0x000000E0L +#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000100L +#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000200L +#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK 0x00000400L +#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK 0x00000800L +#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK 0x00001000L +#define RLC_GPM_TIMER_CTRL__RESERVED_2_MASK 0x0000E000L +#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00010000L +#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00020000L +#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK 0x00040000L +#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK 0x00080000L +#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK 0x00100000L +#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFE00000L +//RLC_GPM_TIMER_STAT +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 +#define RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT 0x4 +#define RLC_GPM_TIMER_STAT__RESERVED_1__SHIFT 0x5 +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb +#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT 0xc +#define RLC_GPM_TIMER_STAT__RESERVED_2__SHIFT 0xd +#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0x10 +#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0x11 +#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT 0x12 +#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT 0x13 +#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT 0x14 +#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x15 +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L +#define RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK 0x00000010L +#define RLC_GPM_TIMER_STAT__RESERVED_1_MASK 0x000000E0L +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L +#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK 0x00001000L +#define RLC_GPM_TIMER_STAT__RESERVED_2_MASK 0x0000E000L +#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00010000L +#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00020000L +#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK 0x00040000L +#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK 0x00080000L +#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK 0x00100000L +#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFE00000L +//RLC_GPM_LEGACY_INT_STAT +#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +//RLC_GPM_LEGACY_INT_CLEAR +#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +//RLC_INT_STAT +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 +#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 +#define RLC_INT_STAT__RESERVED__SHIFT 0x9 +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL +#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L +#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_MGCG_CTRL +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L +#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L +//RLC_JUMP_TABLE_RESTORE +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_2 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK 0xFFFF0000L +//RLC_GPU_CLOCK_COUNT_LSB +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL +//RLC_UCODE_CNTL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL +//RLC_GPM_THREAD_RESET +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPM_CP_DMA_COMPLETE_T0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_CP_DMA_COMPLETE_T1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_THREAD_INVALIDATE_CACHE +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE__SHIFT 0x0 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE__SHIFT 0x1 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE__SHIFT 0x2 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE__SHIFT 0x3 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE_MASK 0x00000001L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE_MASK 0x00000002L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE_MASK 0x00000004L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE_MASK 0x00000008L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED_MASK 0xFFFFFFF0L +//RLC_CLK_COUNT_GFXCLK_LSB +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_GFXCLK_MSB +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_LSB +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_MSB +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_CTRL +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L +//RLC_CLK_COUNT_STAT +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 +#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 +#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L +#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L +#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCG_DOORBELL_CNTL +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_RLCG_DOORBELL_CNTL__RESERVED__SHIFT 0x16 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +#define RLC_RLCG_DOORBELL_CNTL__RESERVED_MASK 0xFFC00000L +//RLC_RLCG_DOORBELL_STAT +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_RLCG_DOORBELL_0_DATA_LO +#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_0_DATA_HI +#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_1_DATA_LO +#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_1_DATA_HI +#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_2_DATA_LO +#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_2_DATA_HI +#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_3_DATA_LO +#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_3_DATA_HI +#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_32_RES_SEL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_CLOCK_32 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL +//RLC_PG_CNTL +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__MEM_DS_DISABLE__SHIFT 0xd +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 +#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT 0x17 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L +#define RLC_PG_CNTL__RESERVED_MASK 0x00001FE0L +#define RLC_PG_CNTL__MEM_DS_DISABLE_MASK 0x00002000L +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L +#define RLC_PG_CNTL__RESERVED1_MASK 0x00180000L +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L +#define RLC_PG_CNTL__RESERVED2_MASK 0x00400000L +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK 0x00800000L +//RLC_GPM_THREAD_PRIORITY +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L +//RLC_GPM_THREAD_ENABLE +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCG_DOORBELL_RANGE +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +//RLC_CGTT_MGCG_OVERRIDE +#define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE__SHIFT 0x0 +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE__SHIFT 0xa +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11__SHIFT 0xb +#define RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL__SHIFT 0x11 +#define RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x12 +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19__SHIFT 0x13 +#define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK 0x00000001L +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +#define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK 0x00000400L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11_MASK 0x0001F800L +#define RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL_MASK 0x00020000L +#define RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL_MASK 0x00040000L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19_MASK 0xFFF80000L +//RLC_CGCG_CGLS_CTRL +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_DYN_PG_STATUS +#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 +#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_DYN_PG_REQUEST +#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_PG_DELAY +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L +//RLC_WGP_STATUS +#define RLC_WGP_STATUS__WORK_PENDING__SHIFT 0x0 +#define RLC_WGP_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL +//RLC_PG_ALWAYS_ON_WGP_MASK +#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT 0x0 +#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_MAX_PG_WGP +#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT 0x0 +#define RLC_MAX_PG_WGP__SPARE__SHIFT 0x8 +#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK 0x000000FFL +#define RLC_MAX_PG_WGP__SPARE_MASK 0xFFFFFF00L +//RLC_AUTO_PG_CTRL +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L +//RLC_SERDES_RD_INDEX +#define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT 0x0 +#define RLC_SERDES_RD_INDEX__SPARE__SHIFT 0x2 +#define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK 0x00000003L +#define RLC_SERDES_RD_INDEX__SPARE_MASK 0xFFFFFFFCL +//RLC_SERDES_RD_DATA_0 +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_1 +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_2 +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_3 +#define RLC_SERDES_RD_DATA_3__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_MASK +#define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT 0x0 +#define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT 0x1 +#define RLC_SERDES_MASK__RESERVED__SHIFT 0x2 +#define RLC_SERDES_MASK__GC_SE_0__SHIFT 0x10 +#define RLC_SERDES_MASK__GC_SE_1__SHIFT 0x11 +#define RLC_SERDES_MASK__GC_SE_2__SHIFT 0x12 +#define RLC_SERDES_MASK__GC_SE_3__SHIFT 0x13 +#define RLC_SERDES_MASK__GC_SE_4__SHIFT 0x14 +#define RLC_SERDES_MASK__GC_SE_5__SHIFT 0x15 +#define RLC_SERDES_MASK__GC_SE_6__SHIFT 0x16 +#define RLC_SERDES_MASK__GC_SE_7__SHIFT 0x17 +#define RLC_SERDES_MASK__RESERVED_31_24__SHIFT 0x18 +#define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK 0x00000001L +#define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK 0x00000002L +#define RLC_SERDES_MASK__RESERVED_MASK 0x0000FFFCL +#define RLC_SERDES_MASK__GC_SE_0_MASK 0x00010000L +#define RLC_SERDES_MASK__GC_SE_1_MASK 0x00020000L +#define RLC_SERDES_MASK__GC_SE_2_MASK 0x00040000L +#define RLC_SERDES_MASK__GC_SE_3_MASK 0x00080000L +#define RLC_SERDES_MASK__GC_SE_4_MASK 0x00100000L +#define RLC_SERDES_MASK__GC_SE_5_MASK 0x00200000L +#define RLC_SERDES_MASK__GC_SE_6_MASK 0x00400000L +#define RLC_SERDES_MASK__GC_SE_7_MASK 0x00800000L +#define RLC_SERDES_MASK__RESERVED_31_24_MASK 0xFF000000L +//RLC_SERDES_CTRL +#define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT 0x0 +#define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT 0x1 +#define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT 0x2 +#define RLC_SERDES_CTRL__BPM_ADDR__SHIFT 0x3 +#define RLC_SERDES_CTRL__REG_ADDR__SHIFT 0x10 +#define RLC_SERDES_CTRL__BPM_BROADCAST_MASK 0x000001L +#define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK 0x000002L +#define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK 0x000004L +#define RLC_SERDES_CTRL__BPM_ADDR_MASK 0x00FFF8L +#define RLC_SERDES_CTRL__REG_ADDR_MASK 0xFF0000L +//RLC_SERDES_DATA +#define RLC_SERDES_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_BUSY +#define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT 0x0 +#define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT 0x1 +#define RLC_SERDES_BUSY__RESERVED__SHIFT 0x2 +#define RLC_SERDES_BUSY__GC_SE_0__SHIFT 0x10 +#define RLC_SERDES_BUSY__GC_SE_1__SHIFT 0x11 +#define RLC_SERDES_BUSY__GC_SE_2__SHIFT 0x12 +#define RLC_SERDES_BUSY__GC_SE_3__SHIFT 0x13 +#define RLC_SERDES_BUSY__GC_SE_4__SHIFT 0x14 +#define RLC_SERDES_BUSY__GC_SE_5__SHIFT 0x15 +#define RLC_SERDES_BUSY__GC_SE_6__SHIFT 0x16 +#define RLC_SERDES_BUSY__GC_SE_7__SHIFT 0x17 +#define RLC_SERDES_BUSY__RESERVED_29_24__SHIFT 0x18 +#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT 0x1e +#define RLC_SERDES_BUSY__RD_PENDING__SHIFT 0x1f +#define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK 0x00000001L +#define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK 0x00000002L +#define RLC_SERDES_BUSY__RESERVED_MASK 0x0000FFFCL +#define RLC_SERDES_BUSY__GC_SE_0_MASK 0x00010000L +#define RLC_SERDES_BUSY__GC_SE_1_MASK 0x00020000L +#define RLC_SERDES_BUSY__GC_SE_2_MASK 0x00040000L +#define RLC_SERDES_BUSY__GC_SE_3_MASK 0x00080000L +#define RLC_SERDES_BUSY__GC_SE_4_MASK 0x00100000L +#define RLC_SERDES_BUSY__GC_SE_5_MASK 0x00200000L +#define RLC_SERDES_BUSY__GC_SE_6_MASK 0x00400000L +#define RLC_SERDES_BUSY__GC_SE_7_MASK 0x00800000L +#define RLC_SERDES_BUSY__RESERVED_29_24_MASK 0x3F000000L +#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK 0x40000000L +#define RLC_SERDES_BUSY__RD_PENDING_MASK 0x80000000L +//RLC_GPM_GENERAL_0 +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_1 +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_2 +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_3 +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_4 +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_5 +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_6 +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_7 +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_STATIC_PG_STATUS +#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_16 +#define RLC_GPM_GENERAL_16__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_16__DATA_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_3 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL +#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L +//RLC_GPR_REG1 +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL +//RLC_GPR_REG2 +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_INT_DISABLE_TH0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK 0xFFFFFFFFL +//RLC_GPM_LEGACY_INT_DISABLE +#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +//RLC_GPM_INT_FORCE_TH0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK 0xFFFFFFFFL +//RLC_SRM_CNTL +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L +#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_GPM_COMMAND_STATUS +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_INDEX_CNTL_ADDR_0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_1 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_2 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_3 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_4 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_5 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_6 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_7 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_DATA_0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_1 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_2 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_3 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_4 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_5 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_6 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_7 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_STAT +#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 +#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 +#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 +#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L +#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L +#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL +//RLC_GPM_GENERAL_8 +#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_9 +#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_10 +#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_11 +#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_12 +#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_CNTL_0 +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L +//RLC_GPM_UTCL1_CNTL_1 +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L +//RLC_GPM_UTCL1_CNTL_2 +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L +//RLC_SPM_UTCL1_CNTL +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L +//RLC_UTCL1_STATUS_2 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 +#define RLC_UTCL1_STATUS_2__RESERVED_1__SHIFT 0x4 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 +#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0x9 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L +#define RLC_UTCL1_STATUS_2__RESERVED_1_MASK 0x00000010L +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L +#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFE00L +//RLC_SPM_UTCL1_ERROR_1 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_SPM_UTCL1_ERROR_2 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_1 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH0_ERROR_2 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH1_ERROR_1 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH1_ERROR_2 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH2_ERROR_1 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH2_ERROR_2 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_CGCG_CGLS_CTRL_3D +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL_3D +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_SEMAPHORE_0 +#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_1 +#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_2 +#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_3 +#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L +//RLC_PACE_INT_STAT +#define RLC_PACE_INT_STAT__STATUS__SHIFT 0x0 +#define RLC_PACE_INT_STAT__STATUS_MASK 0xFFFFFFFFL +//RLC_UTCL1_STATUS +#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 +#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e +#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L +#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L +//RLC_R2I_CNTL_0 +#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_1 +#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_2 +#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_3 +#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL +//RLC_GPM_INT_STAT_TH0 +#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 +#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_13 +#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_14 +#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_15 +#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_CLOCK_COUNT_LSB_2 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_2 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_PACE_INT_DISABLE +#define RLC_PACE_INT_DISABLE__DISABLE_INT__SHIFT 0x0 +#define RLC_PACE_INT_DISABLE__DISABLE_INT_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_2 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCV_DOORBELL_RANGE +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +//RLC_RLCV_DOORBELL_CNTL +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +//RLC_RLCV_DOORBELL_STAT +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_RLCV_DOORBELL_0_DATA_LO +#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_0_DATA_HI +#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_1_DATA_LO +#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_1_DATA_HI +#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_2_DATA_LO +#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_2_DATA_HI +#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_3_DATA_LO +#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_3_DATA_HI +#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_LSB_1 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_1 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_RLCV_SPARE_INT +#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_PACE_TIMER_INT_0 +#define RLC_PACE_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_PACE_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_PACE_TIMER_INT_1 +#define RLC_PACE_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_PACE_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_PACE_TIMER_CTRL +#define RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 +#define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 +#define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 +#define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 +#define RLC_PACE_TIMER_CTRL__RESERVED__SHIFT 0x6 +#define RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L +#define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L +#define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L +#define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L +#define RLC_PACE_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L +//RLC_SMU_CLK_REQ +#define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 +#define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L +//RLC_CP_STAT_INVAL_STAT +#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT 0x0 +#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT 0x1 +#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT 0x2 +#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT 0x3 +#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT 0x4 +#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT 0x5 +#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK 0x00000001L +#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK 0x00000002L +#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK 0x00000004L +#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK 0x00000008L +#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK 0x00000010L +#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK 0x00000020L +//RLC_CP_STAT_INVAL_CTRL +#define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT 0x0 +#define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT 0x1 +#define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT 0x2 +#define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK 0x00000001L +#define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK 0x00000002L +#define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK 0x00000004L +//RLC_SPARE +#define RLC_SPARE__SPARE__SHIFT 0x0 +#define RLC_SPARE__SPARE_MASK 0xFFFFFFFFL +//RLC_SPP_CTRL +#define RLC_SPP_CTRL__ENABLE__SHIFT 0x0 +#define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT 0x1 +#define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT 0x2 +#define RLC_SPP_CTRL__PAUSE__SHIFT 0x3 +#define RLC_SPP_CTRL__ENABLE_MASK 0x00000001L +#define RLC_SPP_CTRL__ENABLE_PPROF_MASK 0x00000002L +#define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK 0x00000004L +#define RLC_SPP_CTRL__PAUSE_MASK 0x00000008L +//RLC_SPP_SHADER_PROFILE_EN +#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT 0x0 +#define RLC_SPP_SHADER_PROFILE_EN__RESERVED_1__SHIFT 0x1 +#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT 0x2 +#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT 0x3 +#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT 0x4 +#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT 0x5 +#define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT 0x6 +#define RLC_SPP_SHADER_PROFILE_EN__RESERVED_7__SHIFT 0x7 +#define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT 0x8 +#define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT 0x9 +#define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT 0xa +#define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT 0xb +#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT 0xc +#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT 0xd +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT 0xe +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT 0xf +#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT 0x10 +#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK 0x00000001L +#define RLC_SPP_SHADER_PROFILE_EN__RESERVED_1_MASK 0x00000002L +#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK 0x00000004L +#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK 0x00000008L +#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK 0x00000010L +#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK 0x00000020L +#define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK 0x00000040L +#define RLC_SPP_SHADER_PROFILE_EN__RESERVED_7_MASK 0x00000080L +#define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK 0x00000100L +#define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK 0x00000200L +#define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK 0x00000400L +#define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK 0x00000800L +#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK 0x00001000L +#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK 0x00002000L +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK 0x00004000L +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK 0x00008000L +#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK 0x00010000L +//RLC_SPP_SSF_CAPTURE_EN +#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT 0x0 +#define RLC_SPP_SSF_CAPTURE_EN__RESERVED_1__SHIFT 0x1 +#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT 0x2 +#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT 0x3 +#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT 0x4 +#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT 0x5 +#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK 0x00000001L +#define RLC_SPP_SSF_CAPTURE_EN__RESERVED_1_MASK 0x00000002L +#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK 0x00000004L +#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK 0x00000008L +#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK 0x00000010L +#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK 0x00000020L +//RLC_SPP_SSF_THRESHOLD_0 +#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_0__RESERVED__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_0__RESERVED_MASK 0xFFFF0000L +//RLC_SPP_SSF_THRESHOLD_1 +#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK 0xFFFF0000L +//RLC_SPP_SSF_THRESHOLD_2 +#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK 0xFFFF0000L +//RLC_SPP_INFLIGHT_RD_ADDR +#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK 0x0000001FL +//RLC_SPP_INFLIGHT_RD_DATA +#define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPP_PROF_INFO_1 +#define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT 0x0 +#define RLC_SPP_PROF_INFO_1__SH_ID_MASK 0xFFFFFFFFL +//RLC_SPP_PROF_INFO_2 +#define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT 0x0 +#define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT 0x4 +#define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT 0x5 +#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT 0x6 +#define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK 0x0000000FL +#define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK 0x00000010L +#define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK 0x00000020L +#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK 0x00000040L +//RLC_SPP_GLOBAL_SH_ID +#define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT 0x0 +#define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK 0xFFFFFFFFL +//RLC_SPP_GLOBAL_SH_ID_VALID +#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT 0x0 +#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK 0x00000001L +//RLC_SPP_STATUS +#define RLC_SPP_STATUS__RESERVED_0__SHIFT 0x0 +#define RLC_SPP_STATUS__SSF_BUSY__SHIFT 0x1 +#define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT 0x2 +#define RLC_SPP_STATUS__SPP_BUSY__SHIFT 0x1f +#define RLC_SPP_STATUS__RESERVED_0_MASK 0x00000001L +#define RLC_SPP_STATUS__SSF_BUSY_MASK 0x00000002L +#define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK 0x00000004L +#define RLC_SPP_STATUS__SPP_BUSY_MASK 0x80000000L +//RLC_SPP_PVT_STAT_0 +#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT 0x6 +#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT 0xc +#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT 0x12 +#define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK 0x0000003FL +#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK 0x00000FC0L +#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK 0x0003F000L +#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK 0x00FC0000L +#define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_1 +#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT 0x6 +#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT 0xc +#define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT 0x12 +#define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK 0x0000003FL +#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK 0x00000FC0L +#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK 0x0003F000L +#define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK 0x00FC0000L +#define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_2 +#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT 0x6 +#define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT 0xc +#define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT 0x12 +#define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK 0x0000003FL +#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK 0x00000FC0L +#define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK 0x0003F000L +#define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK 0x00FC0000L +#define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_3 +#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK 0x0000003FL +//RLC_SPP_PVT_LEVEL_MAX +#define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT 0x0 +#define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK 0x0000000FL +//RLC_SPP_STALL_STATE_UPDATE +#define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT 0x0 +#define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT 0x1 +#define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK 0x00000001L +#define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK 0x00000002L +//RLC_SPP_PBB_INFO +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT 0x0 +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT 0x1 +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT 0x2 +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT 0x3 +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK 0x00000001L +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK 0x00000002L +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK 0x00000004L +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK 0x00000008L +//RLC_SPP_RESET +#define RLC_SPP_RESET__SSF_RESET__SHIFT 0x0 +#define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT 0x1 +#define RLC_SPP_RESET__CAM_RESET__SHIFT 0x2 +#define RLC_SPP_RESET__PVT_RESET__SHIFT 0x3 +#define RLC_SPP_RESET__SSF_RESET_MASK 0x00000001L +#define RLC_SPP_RESET__EVENT_ARB_RESET_MASK 0x00000002L +#define RLC_SPP_RESET__CAM_RESET_MASK 0x00000004L +#define RLC_SPP_RESET__PVT_RESET_MASK 0x00000008L +//RLC_RLCP_DOORBELL_RANGE +#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +//RLC_RLCP_DOORBELL_CNTL +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +//RLC_RLCP_DOORBELL_STAT +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_RLCP_DOORBELL_0_DATA_LO +#define RLC_RLCP_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_DOORBELL_0_DATA_HI +#define RLC_RLCP_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_DOORBELL_1_DATA_LO +#define RLC_RLCP_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_DOORBELL_1_DATA_HI +#define RLC_RLCP_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_DOORBELL_2_DATA_LO +#define RLC_RLCP_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_DOORBELL_2_DATA_HI +#define RLC_RLCP_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_DOORBELL_3_DATA_LO +#define RLC_RLCP_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_DOORBELL_3_DATA_HI +#define RLC_RLCP_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCP_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_CAC_MASK_CNTL +#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT 0x0 +#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK 0xFFFFFFFFL +//RLC_POWER_RESIDENCY_CNTR_CTRL +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_CLK_RESIDENCY_CNTR_CTRL +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_DS_RESIDENCY_CNTR_CTRL +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_ULV_RESIDENCY_CNTR_CTRL +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_PCC_RESIDENCY_CNTR_CTRL +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL__SHIFT 0x5 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x9 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL_MASK 0x000001E0L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFE00L +//RLC_GENERAL_RESIDENCY_CNTR_CTRL +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_POWER_RESIDENCY_EVENT_CNTR +#define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_CLK_RESIDENCY_EVENT_CNTR +#define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_DS_RESIDENCY_EVENT_CNTR +#define RLC_DS_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_DS_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_ULV_RESIDENCY_EVENT_CNTR +#define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_PCC_RESIDENCY_EVENT_CNTR +#define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GENERAL_RESIDENCY_EVENT_CNTR +#define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_POWER_RESIDENCY_REF_CNTR +#define RLC_POWER_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_CLK_RESIDENCY_REF_CNTR +#define RLC_CLK_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_DS_RESIDENCY_REF_CNTR +#define RLC_DS_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_DS_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_ULV_RESIDENCY_REF_CNTR +#define RLC_ULV_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_PCC_RESIDENCY_REF_CNTR +#define RLC_PCC_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GENERAL_RESIDENCY_REF_CNTR +#define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IH_CLIENT_CTRL +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_14__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_31_30__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK_MASK 0x000000FFL +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_14_MASK 0x0000C000L +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR_MASK 0x00FF0000L +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_31_30_MASK 0xC0000000L +//RLC_GFX_IH_ARBITER_STAT +#define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED__SHIFT 0x0 +#define RLC_GFX_IH_ARBITER_STAT__RESERVED__SHIFT 0x10 +#define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED__SHIFT 0x1c +#define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED_MASK 0x0000FFFFL +#define RLC_GFX_IH_ARBITER_STAT__RESERVED_MASK 0x0FFF0000L +#define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED_MASK 0xF0000000L +//RLC_GFX_IH_CLIENT_SE_STAT_L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_SE_STAT_H +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_SDMA_STAT +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_OTHER_STAT +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_16__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_16_MASK 0xFFFF0000L +//RLC_SPM_GLOBAL_DELAY_IND_ADDR +#define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_GLOBAL_DELAY_IND_DATA +#define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA_MASK 0x0000003FL +//RLC_SPM_SE_DELAY_IND_ADDR +#define RLC_SPM_SE_DELAY_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_SE_DELAY_IND_DATA +#define RLC_SPM_SE_DELAY_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_DELAY_IND_DATA__DATA_MASK 0x0000003FL +//RLC_LX6_CNTL +#define RLC_LX6_CNTL__BRESET__SHIFT 0x0 +#define RLC_LX6_CNTL__RUNSTALL__SHIFT 0x1 +#define RLC_LX6_CNTL__PDEBUG_ENABLE__SHIFT 0x2 +#define RLC_LX6_CNTL__STAT_VECTOR_SEL__SHIFT 0x3 +#define RLC_LX6_CNTL__BRESET_MASK 0x00000001L +#define RLC_LX6_CNTL__RUNSTALL_MASK 0x00000002L +#define RLC_LX6_CNTL__PDEBUG_ENABLE_MASK 0x00000004L +#define RLC_LX6_CNTL__STAT_VECTOR_SEL_MASK 0x00000008L +//RLC_XT_CORE_STATUS +#define RLC_XT_CORE_STATUS__P_WAIT_MODE__SHIFT 0x0 +#define RLC_XT_CORE_STATUS__P_FATAL_ERROR__SHIFT 0x1 +#define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR__SHIFT 0x2 +#define RLC_XT_CORE_STATUS__P_WAIT_MODE_MASK 0x00000001L +#define RLC_XT_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000002L +#define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR_MASK 0x00000004L +//RLC_XT_CORE_INTERRUPT +#define RLC_XT_CORE_INTERRUPT__EXTINT1__SHIFT 0x0 +#define RLC_XT_CORE_INTERRUPT__EXTINT2__SHIFT 0x1a +#define RLC_XT_CORE_INTERRUPT__NMI__SHIFT 0x1b +#define RLC_XT_CORE_INTERRUPT__EXTINT1_MASK 0x03FFFFFFL +#define RLC_XT_CORE_INTERRUPT__EXTINT2_MASK 0x04000000L +#define RLC_XT_CORE_INTERRUPT__NMI_MASK 0x08000000L +//RLC_XT_CORE_FAULT_INFO +#define RLC_XT_CORE_FAULT_INFO__FAULT_INFO__SHIFT 0x0 +#define RLC_XT_CORE_FAULT_INFO__FAULT_INFO_MASK 0xFFFFFFFFL +//RLC_XT_CORE_ALT_RESET_VEC +#define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC__SHIFT 0x0 +#define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC_MASK 0xFFFFFFFFL +//RLC_XT_CORE_RESERVED +#define RLC_XT_CORE_RESERVED__RESERVED__SHIFT 0x0 +#define RLC_XT_CORE_RESERVED__RESERVED_MASK 0xFFFFFFFFL +//RLC_XT_INT_VEC_FORCE +#define RLC_XT_INT_VEC_FORCE__NUM_0__SHIFT 0x0 +#define RLC_XT_INT_VEC_FORCE__NUM_1__SHIFT 0x1 +#define RLC_XT_INT_VEC_FORCE__NUM_2__SHIFT 0x2 +#define RLC_XT_INT_VEC_FORCE__NUM_3__SHIFT 0x3 +#define RLC_XT_INT_VEC_FORCE__NUM_4__SHIFT 0x4 +#define RLC_XT_INT_VEC_FORCE__NUM_5__SHIFT 0x5 +#define RLC_XT_INT_VEC_FORCE__NUM_6__SHIFT 0x6 +#define RLC_XT_INT_VEC_FORCE__NUM_7__SHIFT 0x7 +#define RLC_XT_INT_VEC_FORCE__NUM_8__SHIFT 0x8 +#define RLC_XT_INT_VEC_FORCE__NUM_9__SHIFT 0x9 +#define RLC_XT_INT_VEC_FORCE__NUM_10__SHIFT 0xa +#define RLC_XT_INT_VEC_FORCE__NUM_11__SHIFT 0xb +#define RLC_XT_INT_VEC_FORCE__NUM_12__SHIFT 0xc +#define RLC_XT_INT_VEC_FORCE__NUM_13__SHIFT 0xd +#define RLC_XT_INT_VEC_FORCE__NUM_14__SHIFT 0xe +#define RLC_XT_INT_VEC_FORCE__NUM_15__SHIFT 0xf +#define RLC_XT_INT_VEC_FORCE__NUM_16__SHIFT 0x10 +#define RLC_XT_INT_VEC_FORCE__NUM_17__SHIFT 0x11 +#define RLC_XT_INT_VEC_FORCE__NUM_18__SHIFT 0x12 +#define RLC_XT_INT_VEC_FORCE__NUM_19__SHIFT 0x13 +#define RLC_XT_INT_VEC_FORCE__NUM_20__SHIFT 0x14 +#define RLC_XT_INT_VEC_FORCE__NUM_21__SHIFT 0x15 +#define RLC_XT_INT_VEC_FORCE__NUM_22__SHIFT 0x16 +#define RLC_XT_INT_VEC_FORCE__NUM_23__SHIFT 0x17 +#define RLC_XT_INT_VEC_FORCE__NUM_24__SHIFT 0x18 +#define RLC_XT_INT_VEC_FORCE__NUM_25__SHIFT 0x19 +#define RLC_XT_INT_VEC_FORCE__NUM_0_MASK 0x00000001L +#define RLC_XT_INT_VEC_FORCE__NUM_1_MASK 0x00000002L +#define RLC_XT_INT_VEC_FORCE__NUM_2_MASK 0x00000004L +#define RLC_XT_INT_VEC_FORCE__NUM_3_MASK 0x00000008L +#define RLC_XT_INT_VEC_FORCE__NUM_4_MASK 0x00000010L +#define RLC_XT_INT_VEC_FORCE__NUM_5_MASK 0x00000020L +#define RLC_XT_INT_VEC_FORCE__NUM_6_MASK 0x00000040L +#define RLC_XT_INT_VEC_FORCE__NUM_7_MASK 0x00000080L +#define RLC_XT_INT_VEC_FORCE__NUM_8_MASK 0x00000100L +#define RLC_XT_INT_VEC_FORCE__NUM_9_MASK 0x00000200L +#define RLC_XT_INT_VEC_FORCE__NUM_10_MASK 0x00000400L +#define RLC_XT_INT_VEC_FORCE__NUM_11_MASK 0x00000800L +#define RLC_XT_INT_VEC_FORCE__NUM_12_MASK 0x00001000L +#define RLC_XT_INT_VEC_FORCE__NUM_13_MASK 0x00002000L +#define RLC_XT_INT_VEC_FORCE__NUM_14_MASK 0x00004000L +#define RLC_XT_INT_VEC_FORCE__NUM_15_MASK 0x00008000L +#define RLC_XT_INT_VEC_FORCE__NUM_16_MASK 0x00010000L +#define RLC_XT_INT_VEC_FORCE__NUM_17_MASK 0x00020000L +#define RLC_XT_INT_VEC_FORCE__NUM_18_MASK 0x00040000L +#define RLC_XT_INT_VEC_FORCE__NUM_19_MASK 0x00080000L +#define RLC_XT_INT_VEC_FORCE__NUM_20_MASK 0x00100000L +#define RLC_XT_INT_VEC_FORCE__NUM_21_MASK 0x00200000L +#define RLC_XT_INT_VEC_FORCE__NUM_22_MASK 0x00400000L +#define RLC_XT_INT_VEC_FORCE__NUM_23_MASK 0x00800000L +#define RLC_XT_INT_VEC_FORCE__NUM_24_MASK 0x01000000L +#define RLC_XT_INT_VEC_FORCE__NUM_25_MASK 0x02000000L +//RLC_XT_INT_VEC_CLEAR +#define RLC_XT_INT_VEC_CLEAR__NUM_0__SHIFT 0x0 +#define RLC_XT_INT_VEC_CLEAR__NUM_1__SHIFT 0x1 +#define RLC_XT_INT_VEC_CLEAR__NUM_2__SHIFT 0x2 +#define RLC_XT_INT_VEC_CLEAR__NUM_3__SHIFT 0x3 +#define RLC_XT_INT_VEC_CLEAR__NUM_4__SHIFT 0x4 +#define RLC_XT_INT_VEC_CLEAR__NUM_5__SHIFT 0x5 +#define RLC_XT_INT_VEC_CLEAR__NUM_6__SHIFT 0x6 +#define RLC_XT_INT_VEC_CLEAR__NUM_7__SHIFT 0x7 +#define RLC_XT_INT_VEC_CLEAR__NUM_8__SHIFT 0x8 +#define RLC_XT_INT_VEC_CLEAR__NUM_9__SHIFT 0x9 +#define RLC_XT_INT_VEC_CLEAR__NUM_10__SHIFT 0xa +#define RLC_XT_INT_VEC_CLEAR__NUM_11__SHIFT 0xb +#define RLC_XT_INT_VEC_CLEAR__NUM_12__SHIFT 0xc +#define RLC_XT_INT_VEC_CLEAR__NUM_13__SHIFT 0xd +#define RLC_XT_INT_VEC_CLEAR__NUM_14__SHIFT 0xe +#define RLC_XT_INT_VEC_CLEAR__NUM_15__SHIFT 0xf +#define RLC_XT_INT_VEC_CLEAR__NUM_16__SHIFT 0x10 +#define RLC_XT_INT_VEC_CLEAR__NUM_17__SHIFT 0x11 +#define RLC_XT_INT_VEC_CLEAR__NUM_18__SHIFT 0x12 +#define RLC_XT_INT_VEC_CLEAR__NUM_19__SHIFT 0x13 +#define RLC_XT_INT_VEC_CLEAR__NUM_20__SHIFT 0x14 +#define RLC_XT_INT_VEC_CLEAR__NUM_21__SHIFT 0x15 +#define RLC_XT_INT_VEC_CLEAR__NUM_22__SHIFT 0x16 +#define RLC_XT_INT_VEC_CLEAR__NUM_23__SHIFT 0x17 +#define RLC_XT_INT_VEC_CLEAR__NUM_24__SHIFT 0x18 +#define RLC_XT_INT_VEC_CLEAR__NUM_25__SHIFT 0x19 +#define RLC_XT_INT_VEC_CLEAR__NUM_0_MASK 0x00000001L +#define RLC_XT_INT_VEC_CLEAR__NUM_1_MASK 0x00000002L +#define RLC_XT_INT_VEC_CLEAR__NUM_2_MASK 0x00000004L +#define RLC_XT_INT_VEC_CLEAR__NUM_3_MASK 0x00000008L +#define RLC_XT_INT_VEC_CLEAR__NUM_4_MASK 0x00000010L +#define RLC_XT_INT_VEC_CLEAR__NUM_5_MASK 0x00000020L +#define RLC_XT_INT_VEC_CLEAR__NUM_6_MASK 0x00000040L +#define RLC_XT_INT_VEC_CLEAR__NUM_7_MASK 0x00000080L +#define RLC_XT_INT_VEC_CLEAR__NUM_8_MASK 0x00000100L +#define RLC_XT_INT_VEC_CLEAR__NUM_9_MASK 0x00000200L +#define RLC_XT_INT_VEC_CLEAR__NUM_10_MASK 0x00000400L +#define RLC_XT_INT_VEC_CLEAR__NUM_11_MASK 0x00000800L +#define RLC_XT_INT_VEC_CLEAR__NUM_12_MASK 0x00001000L +#define RLC_XT_INT_VEC_CLEAR__NUM_13_MASK 0x00002000L +#define RLC_XT_INT_VEC_CLEAR__NUM_14_MASK 0x00004000L +#define RLC_XT_INT_VEC_CLEAR__NUM_15_MASK 0x00008000L +#define RLC_XT_INT_VEC_CLEAR__NUM_16_MASK 0x00010000L +#define RLC_XT_INT_VEC_CLEAR__NUM_17_MASK 0x00020000L +#define RLC_XT_INT_VEC_CLEAR__NUM_18_MASK 0x00040000L +#define RLC_XT_INT_VEC_CLEAR__NUM_19_MASK 0x00080000L +#define RLC_XT_INT_VEC_CLEAR__NUM_20_MASK 0x00100000L +#define RLC_XT_INT_VEC_CLEAR__NUM_21_MASK 0x00200000L +#define RLC_XT_INT_VEC_CLEAR__NUM_22_MASK 0x00400000L +#define RLC_XT_INT_VEC_CLEAR__NUM_23_MASK 0x00800000L +#define RLC_XT_INT_VEC_CLEAR__NUM_24_MASK 0x01000000L +#define RLC_XT_INT_VEC_CLEAR__NUM_25_MASK 0x02000000L +//RLC_XT_INT_VEC_MUX_SEL +#define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL__SHIFT 0x0 +#define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL_MASK 0x0000001FL +//RLC_XT_INT_VEC_MUX_INT_SEL +#define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL__SHIFT 0x0 +#define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL_MASK 0x0000003FL +//RLC_GPU_CLOCK_COUNT_SPM_LSB +#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_SPM_MSB +#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_SPM_THREAD_TRACE_CTRL +#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT 0x0 +#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK 0x00000001L +//RLC_SPP_CAM_ADDR +#define RLC_SPP_CAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_CAM_ADDR__ADDR_MASK 0x000000FFL +//RLC_SPP_CAM_DATA +#define RLC_SPP_CAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPP_CAM_DATA__TAG__SHIFT 0x8 +#define RLC_SPP_CAM_DATA__DATA_MASK 0x000000FFL +#define RLC_SPP_CAM_DATA__TAG_MASK 0xFFFFFF00L +//RLC_SPP_CAM_EXT_ADDR +#define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK 0x000000FFL +//RLC_SPP_CAM_EXT_DATA +#define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT 0x0 +#define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT 0x1 +#define RLC_SPP_CAM_EXT_DATA__VALID_MASK 0x00000001L +#define RLC_SPP_CAM_EXT_DATA__LOCK_MASK 0x00000002L +//RLC_XT_DOORBELL_RANGE +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +//RLC_XT_DOORBELL_CNTL +#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +//RLC_XT_DOORBELL_STAT +#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_XT_DOORBELL_0_DATA_LO +#define RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_0_DATA_HI +#define RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_1_DATA_LO +#define RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_1_DATA_HI +#define RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_2_DATA_LO +#define RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_2_DATA_HI +#define RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_3_DATA_LO +#define RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_3_DATA_HI +#define RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_MEM_SLP_CNTL +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE__SHIFT 0x3 +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE__SHIFT 0x4 +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE__SHIFT 0x5 +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x6 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE__SHIFT 0x18 +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE__SHIFT 0x19 +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x1a +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE_MASK 0x00000004L +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE_MASK 0x00000008L +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE_MASK 0x00000010L +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE_MASK 0x00000020L +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x00000040L +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE_MASK 0x01000000L +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE_MASK 0x02000000L +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFC000000L +//SMU_RLC_RESPONSE +#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 +#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_RLCV_SAFE_MODE +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SMU_SAFE_MODE +#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_RLCV_COMMAND +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L +//RLC_SMU_MESSAGE +#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_MESSAGE_1 +#define RLC_SMU_MESSAGE_1__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE_1__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_MESSAGE_2 +#define RLC_SMU_MESSAGE_2__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE_2__CMD_MASK 0xFFFFFFFFL +//RLC_SRM_GPM_COMMAND +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x12 +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0003FFE0L +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x7FFC0000L +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L +//RLC_SRM_GPM_ABORT +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_COMMAND +#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 +#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_1 +#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_2 +#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_3 +#define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_4 +#define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_5 +#define RLC_SMU_ARGUMENT_5__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_5__ARG_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_ADDR_HI +#define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_ADDR_LO +#define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_SIZE +#define RLC_IMU_BOOTLOAD_SIZE__SIZE__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_SIZE__RESERVED__SHIFT 0x1a +#define RLC_IMU_BOOTLOAD_SIZE__SIZE_MASK 0x03FFFFFFL +#define RLC_IMU_BOOTLOAD_SIZE__RESERVED_MASK 0xFC000000L +//RLC_IMU_MISC +#define RLC_IMU_MISC__THROTTLE_GFX__SHIFT 0x0 +#define RLC_IMU_MISC__EARLY_MGCG__SHIFT 0x1 +#define RLC_IMU_MISC__RESERVED__SHIFT 0x2 +#define RLC_IMU_MISC__THROTTLE_GFX_MASK 0x00000001L +#define RLC_IMU_MISC__EARLY_MGCG_MASK 0x00000002L +#define RLC_IMU_MISC__RESERVED_MASK 0xFFFFFFFCL +//RLC_IMU_RESET_VECTOR +#define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT 0x0 +#define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT__SHIFT 0x1 +#define RLC_IMU_RESET_VECTOR__VECTOR__SHIFT 0x2 +#define RLC_IMU_RESET_VECTOR__RESERVED__SHIFT 0x8 +#define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT_MASK 0x00000001L +#define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT_MASK 0x00000002L +#define RLC_IMU_RESET_VECTOR__VECTOR_MASK 0x000000FCL +#define RLC_IMU_RESET_VECTOR__RESERVED_MASK 0xFFFFFF00L + + +// addressBlock: gc_rlcsdec +//RLC_RLCS_DEC_START +//RLC_RLCS_DEC_DUMP_ADDR +//RLC_RLCS_EXCEPTION_REG_1 +#define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_2 +#define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_3 +#define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_4 +#define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_CGCG_REQUEST +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT 0x0 +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT 0x1 +#define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT 0x2 +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK 0x00000001L +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK 0x00000002L +#define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_CGCG_STATUS +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT 0x0 +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT 0x2 +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT 0x3 +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT 0x5 +#define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT 0x6 +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK 0x00000003L +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK 0x00000004L +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK 0x00000018L +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK 0x00000020L +#define RLC_RLCS_CGCG_STATUS__RESERVED_MASK 0xFFFFFFC0L +//RLC_RLCS_SOC_DS_CNTL +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT 0x0 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK 0x00000001L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L +//RLC_RLCS_GFX_DS_CNTL +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT 0x0 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK__SHIFT 0x8 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK 0x00000001L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK_MASK 0x00000100L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L +//RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL +//RLC_GPM_STAT +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 +#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L +#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L +#define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L +#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L +#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_RLCS_GPM_STAT +#define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 +#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT 0x12 +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 +#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L +#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK 0x00040000L +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L +#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_RLCS_ABORTED_PD_SEQUENCE +#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT 0x0 +#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT 0x10 +#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK 0x0000FFFFL +#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_DIDT_FORCE_STALL +#define RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT 0x0 +#define RLC_RLCS_DIDT_FORCE_STALL__VALID__SHIFT 0x3 +#define RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT 0x4 +#define RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK 0x00000007L +#define RLC_RLCS_DIDT_FORCE_STALL__VALID_MASK 0x00000008L +#define RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_IOV_CMD_STATUS +#define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IOV_CNTX_LOC_SIZE +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT 0x8 +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK 0x000000FFL +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK 0xFFFFFF00L +//RLC_RLCS_IOV_SCH_BLOCK +#define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IOV_VM_BUSY_STATUS +#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GPM_STAT_2 +#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT 0x0 +#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT 0x1 +#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT 0x2 +#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT 0x3 +#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT 0x4 +#define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT 0x5 +#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK 0x00000001L +#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK 0x00000002L +#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK 0x00000004L +#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK 0x00000008L +#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK 0x00000010L +#define RLC_RLCS_GPM_STAT_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_GRBM_SOFT_RESET +#define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT 0x0 +#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT 0x1 +#define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK 0x00000001L +#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_PG_CHANGE_STATUS +#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT 0x0 +#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT 0x1 +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT 0x3 +#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT 0x4 +#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK 0x00000001L +#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK 0x00000002L +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK 0x00000008L +#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_PG_CHANGE_READ +#define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT 0x0 +#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT 0x1 +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT 0x3 +#define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK 0x00000001L +#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK 0x00000002L +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK 0x00000008L +//RLC_RLCS_IH_SEMAPHORE +#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT 0x0 +#define RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT 0x5 +#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL +#define RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_IH_COOKIE_SEMAPHORE +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT 0x0 +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT 0x5 +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_WGP_STATUS +#define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT 0x0 +#define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 +#define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT 0x3 +#define RLC_RLCS_WGP_STATUS__RESERVED__SHIFT 0x4 +#define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK 0x00000001L +#define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L +#define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK 0x00000008L +#define RLC_RLCS_WGP_STATUS__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_WGP_READ +#define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT 0x0 +#define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 +#define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_WGP_READ__RESERVED__SHIFT 0x3 +#define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK 0x00000001L +#define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L +#define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_WGP_READ__RESERVED_MASK 0xFFFFFFF8L +//RLC_RLCS_CP_INT_CTRL_1 +#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT 0x1 +#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_CP_INT_CTRL_2 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT 0x0 +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT 0x1 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE__SHIFT 0x2 +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE__SHIFT 0x3 +#define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING__SHIFT 0x4 +#define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT 0x5 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK 0x00000001L +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK 0x00000002L +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE_MASK 0x00000004L +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE_MASK 0x00000008L +#define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING_MASK 0x00000010L +#define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_CP_INT_INFO_1 +#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_RLCS_CP_INT_INFO_2 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT 0x19 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L +#define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK 0xFE000000L +//RLC_RLCS_SPM_INT_CTRL +#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT 0x1 +#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_SPM_INT_INFO_1 +#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_RLCS_SPM_INT_INFO_2 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT 0x19 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L +#define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK 0xFE000000L +//RLC_RLCS_DSM_TRIG +#define RLC_RLCS_DSM_TRIG__START__SHIFT 0x0 +#define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT 0x1 +#define RLC_RLCS_DSM_TRIG__START_MASK 0x00000001L +#define RLC_RLCS_DSM_TRIG__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_BOOTLOAD_STATUS +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED__SHIFT 0x3 +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED_MASK 0x00000008L +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK 0x7FFFFFE0L +#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK 0x80000000L +//RLC_RLCS_POWER_BRAKE_CNTL +#define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT 0x0 +#define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT 0x1 +#define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT 0x2 +#define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT 0xa +#define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT 0x12 +#define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK 0x00000001L +#define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK 0x00000002L +#define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK 0x000003FCL +#define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK 0x0003FC00L +#define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_POWER_BRAKE_CNTL_TH1 +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT 0x0 +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT 0x1 +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT 0x2 +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT 0xa +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT 0x12 +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK 0x00000001L +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK 0x00000002L +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK 0x000003FCL +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK 0x0003FC00L +#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_GRBM_IDLE_BUSY_STAT +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT 0x0 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT 0x10 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT 0x11 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT 0x12 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT 0x13 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT 0x14 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT 0x15 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT 0x16 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT 0x17 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT 0x18 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT 0x19 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT 0x1a +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT 0x1b +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT 0x1c +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT 0x1d +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT 0x1e +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT 0x1f +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK 0x00000003L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK 0x00010000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK 0x00020000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK 0x00040000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK 0x00080000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK 0x00100000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK 0x00200000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK 0x00400000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK 0x00800000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK 0x01000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK 0x02000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK 0x04000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK 0x08000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK 0x10000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK 0x20000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK 0x40000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK 0x80000000L +//RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT 0x0 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT 0x1 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT 0x2 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT 0x3 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT 0x4 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT 0x5 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT 0x6 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT 0x7 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK 0x00000001L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK 0x00000002L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK 0x00000004L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK 0x00000008L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK 0x00000010L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK 0x00000020L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK 0x00000040L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK 0x00000080L +//RLC_RLCS_CMP_IDLE_CNTL +#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT 0x0 +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT 0x1 +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT 0x2 +#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT 0x3 +#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT 0xb +#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT 0x13 +#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK 0x00000001L +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK 0x00000002L +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK 0x00000004L +#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK 0x000007F8L +#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK 0x0007F800L +#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK 0xFFF80000L +//RLC_RLCS_GENERAL_0 +#define RLC_RLCS_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_1 +#define RLC_RLCS_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_2 +#define RLC_RLCS_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_3 +#define RLC_RLCS_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_4 +#define RLC_RLCS_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_5 +#define RLC_RLCS_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_6 +#define RLC_RLCS_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_7 +#define RLC_RLCS_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_8 +#define RLC_RLCS_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_9 +#define RLC_RLCS_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_10 +#define RLC_RLCS_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_11 +#define RLC_RLCS_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_12 +#define RLC_RLCS_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_13 +#define RLC_RLCS_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_14 +#define RLC_RLCS_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_15 +#define RLC_RLCS_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_16 +#define RLC_RLCS_GENERAL_16__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_16__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_AUXILIARY_REG_1 +#define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_2 +#define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_3 +#define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_4 +#define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_SPM_SQTT_MODE +#define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT 0x0 +#define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK 0x00000001L +//RLC_RLCS_CP_DMA_SRCID_OVER +#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT 0x0 +#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK 0x00000001L +//RLC_RLCS_BOOTLOAD_ID_STATUS1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT 0x2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT 0x3 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT 0x7 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT 0x8 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT 0x9 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT 0xb +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT 0xc +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT 0xd +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT 0xe +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT 0xf +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT 0x10 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT 0x11 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT 0x12 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT 0x13 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT 0x14 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT 0x15 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT 0x16 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT 0x17 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT 0x18 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT 0x19 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT 0x1a +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT 0x1b +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT 0x1c +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT 0x1d +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT 0x1e +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK 0x00000004L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK 0x00000008L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK 0x00000040L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK 0x00000080L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK 0x00000100L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK 0x00000200L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK 0x00000400L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK 0x00000800L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK 0x00001000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK 0x00002000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK 0x00004000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK 0x00008000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK 0x00010000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK 0x00020000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK 0x00040000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK 0x00080000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK 0x00100000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK 0x00200000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK 0x00400000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK 0x00800000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK 0x01000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK 0x02000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK 0x04000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK 0x08000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK 0x10000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK 0x20000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK 0x40000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK 0x80000000L +//RLC_RLCS_BOOTLOAD_ID_STATUS2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT 0x2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT 0x3 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT 0x7 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT 0x8 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT 0x9 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT 0xb +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT 0xc +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT 0xd +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT 0xe +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT 0xf +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT 0x10 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT 0x11 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT 0x12 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT 0x13 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT 0x14 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT 0x15 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT 0x16 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT 0x17 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT 0x18 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT 0x19 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT 0x1a +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT 0x1b +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT 0x1c +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT 0x1d +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT 0x1e +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK 0x00000004L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK 0x00000008L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK 0x00000040L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK 0x00000080L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK 0x00000100L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK 0x00000200L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK 0x00000400L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK 0x00000800L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK 0x00001000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK 0x00002000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK 0x00004000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK 0x00008000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK 0x00010000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK 0x00020000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK 0x00040000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK 0x00080000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK 0x00100000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK 0x00200000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK 0x00400000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK 0x00800000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK 0x01000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK 0x02000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK 0x04000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK 0x08000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK 0x10000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK 0x20000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK 0x40000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK 0x80000000L +//RLC_RLCS_IMU_VIDCHG_CNTL +#define RLC_RLCS_IMU_VIDCHG_CNTL__REQ__SHIFT 0x0 +#define RLC_RLCS_IMU_VIDCHG_CNTL__DATA__SHIFT 0x1 +#define RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN__SHIFT 0xa +#define RLC_RLCS_IMU_VIDCHG_CNTL__ACK__SHIFT 0xb +#define RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED__SHIFT 0xc +#define RLC_RLCS_IMU_VIDCHG_CNTL__REQ_MASK 0x00000001L +#define RLC_RLCS_IMU_VIDCHG_CNTL__DATA_MASK 0x000003FEL +#define RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN_MASK 0x00000400L +#define RLC_RLCS_IMU_VIDCHG_CNTL__ACK_MASK 0x00000800L +#define RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED_MASK 0xFFFFF000L +//RLC_RLCS_EDC_INT_CNTL +#define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT 0x0 +#define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK 0x00000001L +//RLC_RLCS_KMD_LOG_CNTL1 +#define RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT 0x0 +#define RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_KMD_LOG_CNTL2 +#define RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT 0x0 +#define RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GPM_LEGACY_INT_STAT +#define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED__SHIFT 0x0 +#define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED__SHIFT 0x1 +#define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED_MASK 0x00000001L +#define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED_MASK 0x00000002L +//RLC_RLCS_GPM_LEGACY_INT_DISABLE +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED__SHIFT 0x0 +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED__SHIFT 0x1 +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED_MASK 0x00000001L +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED_MASK 0x00000002L +//RLC_RLCS_SRM_SRCID_CNTL +#define RLC_RLCS_SRM_SRCID_CNTL__SRCID__SHIFT 0x0 +#define RLC_RLCS_SRM_SRCID_CNTL__SRCID_MASK 0x00000007L +//RLC_RLCS_GCR_DATA_0 +#define RLC_RLCS_GCR_DATA_0__PHASE_0__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_0__PHASE_1__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_0__PHASE_0_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_0__PHASE_1_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_1 +#define RLC_RLCS_GCR_DATA_1__PHASE_2__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_1__PHASE_3__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_1__PHASE_2_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_1__PHASE_3_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_2 +#define RLC_RLCS_GCR_DATA_2__PHASE_4__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_2__PHASE_5__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_2__PHASE_4_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_2__PHASE_5_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_3 +#define RLC_RLCS_GCR_DATA_3__PHASE_6__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_3__PHASE_7__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_3__PHASE_6_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_3__PHASE_7_MASK 0xFFFF0000L +//RLC_RLCS_GCR_STATUS +#define RLC_RLCS_GCR_STATUS__GCR_BUSY__SHIFT 0x0 +#define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT__SHIFT 0x1 +#define RLC_RLCS_GCR_STATUS__RESERVED_2__SHIFT 0x5 +#define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG__SHIFT 0x8 +#define RLC_RLCS_GCR_STATUS__RESERVED__SHIFT 0x10 +#define RLC_RLCS_GCR_STATUS__GCR_BUSY_MASK 0x00000001L +#define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT_MASK 0x0000001EL +#define RLC_RLCS_GCR_STATUS__RESERVED_2_MASK 0x000000E0L +#define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG_MASK 0x0000FF00L +#define RLC_RLCS_GCR_STATUS__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_PERFMON_CLK_CNTL_UCODE +#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L +//RLC_RLCS_UTCL2_CNTL +#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT 0x1 +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT 0x2 +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT 0x3 +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT 0x5 +#define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x6 +#define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT 0x7 +#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK 0x00000002L +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK 0x00000004L +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK 0x00000018L +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK 0x00000020L +#define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK 0x00000040L +#define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK 0xFFFFFF80L +//RLC_RLCS_IMU_RLC_MSG_DATA0 +#define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA1 +#define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA2 +#define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA3 +#define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA4 +#define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_CONTROL +#define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_CNTL +#define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_RLC_IMU_MSG_DATA0 +#define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_RLC_IMU_MSG_CONTROL +#define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_RLC_IMU_MSG_CNTL +#define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG__SHIFT 0x1 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG_MASK 0x00000001L +#define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG_MASK 0x00000002L +#define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE__SHIFT 0x10 +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RLC_MUTEX_CNTL +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_RLC_STATUS +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2_MASK 0x00007FFCL +#define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_RLC_IMU_STATUS +#define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE__SHIFT 0x1 +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2__SHIFT 0x2 +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED__SHIFT 0x4 +#define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE_MASK 0x00000001L +#define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE_MASK 0x00000002L +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2_MASK 0x0000000CL +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_IMU_RAM_DATA_1 +#define RLC_RLCS_IMU_RAM_DATA_1__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_1_LSB +#define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_1_MSB +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RAM_DATA_0 +#define RLC_RLCS_IMU_RAM_DATA_0__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_0_LSB +#define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_0_MSB +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RAM_CNTL +#define RLC_RLCS_IMU_RAM_CNTL__REQTOG__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_CNTL__ACKTOG__SHIFT 0x1 +#define RLC_RLCS_IMU_RAM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RAM_CNTL__REQTOG_MASK 0x00000001L +#define RLC_RLCS_IMU_RAM_CNTL__ACKTOG_MASK 0x00000002L +#define RLC_RLCS_IMU_RAM_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_GFX_DOORBELL_FENCE +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE__SHIFT 0x0 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK__SHIFT 0x1 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE_MASK 0x00000001L +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK_MASK 0x00000002L +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_CNTL_1 +#define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID__SHIFT 0x1 +#define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED__SHIFT 0x2 +#define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID_MASK 0x00000002L +#define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_CNTL_2 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE__SHIFT 0x1 +#define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED__SHIFT 0x2 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN_MASK 0x00000001L +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE_MASK 0x00000002L +#define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_STAT +#define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST__SHIFT 0x8 +#define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID__SHIFT 0x10 +#define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING__SHIFT 0x11 +#define RLC_RLCS_SDMA_INT_STAT__RESERVED__SHIFT 0x12 +#define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST_MASK 0x000000FFL +#define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST_MASK 0x0000FF00L +#define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID_MASK 0x00010000L +#define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING_MASK 0x00020000L +#define RLC_RLCS_SDMA_INT_STAT__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_SDMA_INT_INFO +#define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW__SHIFT 0x8 +#define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_SDMA_INT_INFO__RESERVED__SHIFT 0x11 +#define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW_MASK 0x000000FFL +#define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW_MASK 0x0000FF00L +#define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID_MASK 0x00010000L +#define RLC_RLCS_SDMA_INT_INFO__RESERVED_MASK 0xFFFE0000L +//RLC_RLCS_PMM_CGCG_CNTL +#define RLC_RLCS_PMM_CGCG_CNTL__VALID__SHIFT 0x0 +#define RLC_RLCS_PMM_CGCG_CNTL__CLEAN__SHIFT 0x1 +#define RLC_RLCS_PMM_CGCG_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_PMM_CGCG_CNTL__VALID_MASK 0x00000001L +#define RLC_RLCS_PMM_CGCG_CNTL__CLEAN_MASK 0x00000002L +#define RLC_RLCS_PMM_CGCG_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_GFX_MEM_POWER_CTRL_LO +#define RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA__SHIFT 0x0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GFX_RM_CNTL +#define RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 +#define RLC_RLCS_GFX_RM_CNTL__RESERVED__SHIFT 0x1 +#define RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L +#define RLC_RLCS_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_DEC_END + + +// addressBlock: gc_pfvfdec_rlc +//RLC_SAFE_MODE +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SPM_SAMPLE_CNT +#define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT 0x0 +#define RLC_SPM_SAMPLE_CNT__COUNT_MASK 0xFFFFFFFFL +//RLC_SPM_MC_CNTL +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x6 +#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x7 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x8 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x9 +#define RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT 0xc +#define RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT 0xd +#define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT 0xe +#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT 0xf +#define RLC_SPM_MC_CNTL__RESERVED_3__SHIFT 0x10 +#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC__SHIFT 0x12 +#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER__SHIFT 0x13 +#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x14 +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000030L +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000040L +#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000080L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000100L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000E00L +#define RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK 0x00001000L +#define RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK 0x00002000L +#define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK 0x00004000L +#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK 0x00008000L +#define RLC_SPM_MC_CNTL__RESERVED_3_MASK 0x00030000L +#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_MASK 0x00040000L +#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER_MASK 0x00080000L +#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFF00000L +//RLC_SPM_INT_CNTL +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_STATUS +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_INFO_1 +#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_SPM_INT_INFO_2 +#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_SPM_INT_INFO_2__RESERVED__SHIFT 0x18 +#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x00FF0000L +#define RLC_SPM_INT_INFO_2__RESERVED_MASK 0xFF000000L +//RLC_CSIB_ADDR_LO +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL +//RLC_CSIB_ADDR_HI +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL +//RLC_CSIB_LENGTH +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL +//RLC_CP_SCHEDULERS +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L +//RLC_CP_EOF_INT +#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 +#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 +#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L +#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CP_EOF_INT_CNT +#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 +#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL +//RLC_SPARE_INT_0 +#define RLC_SPARE_INT_0__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_0__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_0__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_0__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_0__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_0__COMPLETE_MASK 0x80000000L +//RLC_SPARE_INT_1 +#define RLC_SPARE_INT_1__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_1__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_1__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_1__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_1__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_1__COMPLETE_MASK 0x80000000L +//RLC_SPARE_INT_2 +#define RLC_SPARE_INT_2__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_2__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_2__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_2__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_2__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_2__COMPLETE_MASK 0x80000000L +//RLC_PACE_SPARE_INT +#define RLC_PACE_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_PACE_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_PACE_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_PACE_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_PACE_SPARE_INT_1 +#define RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_PACE_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_PACE_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_PACE_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCV_SPARE_INT_1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: gc_pwrdec +//CGTS_TCC_DISABLE +#define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//CGTT_GS_NGG_CLK_CTRL +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1c +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x10000000L +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PA_CLK_CTRL +#define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT 0xc +#define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE__SHIFT 0xd +#define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE__SHIFT 0xe +#define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE__SHIFT 0xf +#define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE__SHIFT 0x10 +#define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE__SHIFT 0x11 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE__SHIFT 0x14 +#define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE__SHIFT 0x15 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK 0x00001000L +#define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE_MASK 0x00002000L +#define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE_MASK 0x00004000L +#define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE_MASK 0x00008000L +#define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE_MASK 0x00010000L +#define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE_MASK 0x00020000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE_MASK 0x00100000L +#define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE_MASK 0x00200000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL0 +#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL1 +#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT 0x10 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK 0x00010000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL2 +#define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE__SHIFT 0x10 +#define CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE_MASK 0x00010000L +#define CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SQG_CLK_CTRL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN__SHIFT 0x17 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG__SHIFT 0x18 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG__SHIFT 0x19 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG__SHIFT 0x1a +#define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG__SHIFT 0x1b +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN_MASK 0x00800000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG_MASK 0x01000000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG_MASK 0x02000000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG_MASK 0x04000000L +#define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG_MASK 0x08000000L +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//SQ_ALU_CLK_CTRL +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_TEX_CLK_CTRL +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_LDS_CLK_CTRL +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//ICG_SP_CLK_CTRL +#define ICG_SP_CLK_CTRL__CLK_OVERRIDE__SHIFT 0x0 +#define ICG_SP_CLK_CTRL__CLK_OVERRIDE_MASK 0xFFFFFFFFL +//TA_CGTT_CTRL +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//DB_CGTT_CLK_CTRL_0 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x2 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x3 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x5 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x6 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x7 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8__SHIFT 0x8 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x9 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x00000001L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x00000002L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x00000004L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x00000008L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x00000010L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x00000020L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x00000040L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x00000080L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8_MASK 0x00000100L +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xFFFFFE00L +//CB_CGTT_SCLK_CTRL +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_CP_CLK_CTRL +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPF_CLK_CTRL +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1a +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT 0x1b +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT 0x1c +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT 0x1d +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x04000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK 0x08000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK 0x10000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK 0x20000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPC_CLK_CTRL +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_RLC_CLK_CTRL +#define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__RESERVED_MASK 0xFFFFFFFFL +//CGTT_SC_CLK_CTRL3 +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE__SHIFT 0x1 +#define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE__SHIFT 0x2 +#define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE__SHIFT 0x5 +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE__SHIFT 0x6 +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE__SHIFT 0x7 +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE__SHIFT 0x8 +#define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE__SHIFT 0x9 +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE__SHIFT 0xa +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE__SHIFT 0xb +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE__SHIFT 0xd +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE_MASK 0x00000001L +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE_MASK 0x00000002L +#define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE_MASK 0x00000004L +#define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE_MASK 0x00000010L +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE_MASK 0x00000020L +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE_MASK 0x00000040L +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE_MASK 0x00000080L +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE_MASK 0x00000100L +#define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE_MASK 0x00000200L +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE_MASK 0x00000400L +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE_MASK 0x00000800L +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE_MASK 0x00002000L +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL4 +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x1 +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE__SHIFT 0x2 +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE__SHIFT 0x3 +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x5 +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x6 +#define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE__SHIFT 0x7 +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE__SHIFT 0x8 +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE__SHIFT 0x9 +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE__SHIFT 0xa +#define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE__SHIFT 0xb +#define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000001L +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000002L +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE_MASK 0x00000004L +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE_MASK 0x00000008L +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE_MASK 0x00000010L +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000020L +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000040L +#define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE_MASK 0x00000080L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE_MASK 0x00000100L +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE_MASK 0x00000200L +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE_MASK 0x00000400L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE_MASK 0x00000800L +#define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE_MASK 0x80000000L +//GCEA_ICG_CTRL +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x0 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x2 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x4 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x00000001L +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK 0x00000002L +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x00000004L +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x00000010L +//GL1I_GL1R_MGCG_OVERRIDE +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE__SHIFT 0x0 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE__SHIFT 0x2 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x3 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x4 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE__SHIFT 0x5 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE__SHIFT 0x6 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE_MASK 0x00000001L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE_MASK 0x00000004L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000008L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000010L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE_MASK 0x00000020L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE_MASK 0x00000040L +//GL1H_ICG_CTRL +#define GL1H_ICG_CTRL__REG_DCLK_OVERRIDE__SHIFT 0x0 +#define GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE__SHIFT 0x1 +#define GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE__SHIFT 0x2 +#define GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE__SHIFT 0x3 +#define GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE__SHIFT 0x4 +#define GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE__SHIFT 0x5 +#define GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE__SHIFT 0x6 +#define GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE__SHIFT 0x7 +#define GL1H_ICG_CTRL__RET_DCLK_OVERRIDE__SHIFT 0x8 +#define GL1H_ICG_CTRL__REG_DCLK_OVERRIDE_MASK 0x00000001L +#define GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE_MASK 0x00000002L +#define GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE_MASK 0x00000004L +#define GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE_MASK 0x00000008L +#define GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE_MASK 0x00000010L +#define GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE_MASK 0x00000020L +#define GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE_MASK 0x00000040L +#define GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE_MASK 0x00000080L +#define GL1H_ICG_CTRL__RET_DCLK_OVERRIDE_MASK 0x00000100L +//CHI_CHR_MGCG_OVERRIDE +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE__SHIFT 0x0 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE__SHIFT 0x2 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x3 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x4 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE__SHIFT 0x5 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE__SHIFT 0x6 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE_MASK 0x00000001L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE_MASK 0x00000004L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000008L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000010L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE_MASK 0x00000020L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE_MASK 0x00000040L +//ICG_GL1C_CLK_CTRL +#define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE__SHIFT 0xa +#define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000200L +#define ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE_MASK 0x00000400L +//ICG_GL1A_CTRL +#define ICG_GL1A_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1A_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1A_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1A_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +//ICG_CHA_CTRL +#define ICG_CHA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_CHA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_CHA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_CHA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +//GUS_ICG_CTRL +#define GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM__SHIFT 0x0 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x2 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX__SHIFT 0x3 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE__SHIFT 0x4 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ__SHIFT 0x5 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x6 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x7 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC__SHIFT 0x8 +#define GUS_ICG_CTRL__SPARE1__SHIFT 0x9 +#define GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM_MASK 0x00000001L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x00000002L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_READ_MASK 0x00000004L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX_MASK 0x00000008L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE_MASK 0x00000010L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ_MASK 0x00000020L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000040L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x00000080L +#define GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC_MASK 0x00000100L +#define GUS_ICG_CTRL__SPARE1_MASK 0x0003FE00L +//CGTT_PH_CLK_CTRL0 +#define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_PH_CLK_CTRL1 +#define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L +//CGTT_PH_CLK_CTRL2 +#define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +//CGTT_PH_CLK_CTRL3 +#define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +//GFX_ICG_GL2C_CTRL +#define GFX_ICG_GL2C_CTRL__REG_OVERRIDE__SHIFT 0x0 +#define GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE__SHIFT 0x1 +#define GFX_ICG_GL2C_CTRL__IB_OVERRIDE__SHIFT 0x2 +#define GFX_ICG_GL2C_CTRL__TAG_OVERRIDE__SHIFT 0x3 +#define GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE__SHIFT 0x4 +#define GFX_ICG_GL2C_CTRL__CORE_OVERRIDE__SHIFT 0x5 +#define GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE__SHIFT 0x6 +#define GFX_ICG_GL2C_CTRL__GCR_OVERRIDE__SHIFT 0x7 +#define GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE__SHIFT 0x8 +#define GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE__SHIFT 0x9 +#define GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE__SHIFT 0xa +#define GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE__SHIFT 0xb +#define GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE__SHIFT 0xc +#define GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE__SHIFT 0xd +#define GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE__SHIFT 0xe +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE__SHIFT 0xf +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE__SHIFT 0x10 +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE__SHIFT 0x11 +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE__SHIFT 0x12 +#define GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE__SHIFT 0x14 +#define GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE__SHIFT 0x15 +#define GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE__SHIFT 0x16 +#define GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE__SHIFT 0x17 +#define GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE__SHIFT 0x18 +#define GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE__SHIFT 0x19 +#define GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE__SHIFT 0x1a +#define GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE__SHIFT 0x1b +#define GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE__SHIFT 0x1d +#define GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_GL2C_CTRL__REG_OVERRIDE_MASK 0x00000001L +#define GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE_MASK 0x00000002L +#define GFX_ICG_GL2C_CTRL__IB_OVERRIDE_MASK 0x00000004L +#define GFX_ICG_GL2C_CTRL__TAG_OVERRIDE_MASK 0x00000008L +#define GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE_MASK 0x00000010L +#define GFX_ICG_GL2C_CTRL__CORE_OVERRIDE_MASK 0x00000020L +#define GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE_MASK 0x00000040L +#define GFX_ICG_GL2C_CTRL__GCR_OVERRIDE_MASK 0x00000080L +#define GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE_MASK 0x00000100L +#define GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE_MASK 0x00000200L +#define GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE_MASK 0x00000400L +#define GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE_MASK 0x00000800L +#define GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE_MASK 0x00001000L +#define GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE_MASK 0x00002000L +#define GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE_MASK 0x00004000L +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE_MASK 0x00008000L +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE_MASK 0x00010000L +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE_MASK 0x00020000L +#define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE_MASK 0x00040000L +#define GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE_MASK 0x00100000L +#define GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE_MASK 0x00200000L +#define GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE_MASK 0x00400000L +#define GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE_MASK 0x00800000L +#define GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE_MASK 0x01000000L +#define GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE_MASK 0x02000000L +#define GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE_MASK 0x04000000L +#define GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE_MASK 0x08000000L +#define GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE_MASK 0x10000000L +#define GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE_MASK 0x20000000L +#define GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE_MASK 0x80000000L +//GFX_ICG_GL2C_CTRL1 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE__SHIFT 0x0 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE__SHIFT 0x1 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE__SHIFT 0x2 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE__SHIFT 0x3 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE__SHIFT 0x4 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE__SHIFT 0x5 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE__SHIFT 0x6 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE__SHIFT 0x7 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE__SHIFT 0x8 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE__SHIFT 0x9 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE__SHIFT 0xa +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE__SHIFT 0xb +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE__SHIFT 0xc +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE__SHIFT 0xd +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE__SHIFT 0xe +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE__SHIFT 0xf +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE__SHIFT 0x10 +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE__SHIFT 0x11 +#define GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE__SHIFT 0x18 +#define GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE__SHIFT 0x19 +#define GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE__SHIFT 0x1a +#define GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE__SHIFT 0x1b +#define GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE_MASK 0x00000001L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE_MASK 0x00000002L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE_MASK 0x00000004L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE_MASK 0x00000008L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE_MASK 0x00000010L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE_MASK 0x00000020L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE_MASK 0x00000040L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE_MASK 0x00000080L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE_MASK 0x00000100L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE_MASK 0x00000200L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE_MASK 0x00000400L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE_MASK 0x00000800L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE_MASK 0x00001000L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE_MASK 0x00002000L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE_MASK 0x00004000L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE_MASK 0x00008000L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE_MASK 0x00010000L +#define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE_MASK 0x00020000L +#define GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE_MASK 0x01000000L +#define GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE_MASK 0x02000000L +#define GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE_MASK 0x04000000L +#define GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE_MASK 0x08000000L +#define GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE_MASK 0x10000000L +//ICG_LDS_CLK_CTRL +#define ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE__SHIFT 0x0 +#define ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE__SHIFT 0x1 +#define ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE__SHIFT 0x2 +#define ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE__SHIFT 0x3 +#define ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE__SHIFT 0x4 +#define ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE__SHIFT 0x5 +#define ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE__SHIFT 0x6 +#define ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE__SHIFT 0x7 +#define ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE__SHIFT 0x8 +#define ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE__SHIFT 0x9 +#define ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE__SHIFT 0xa +#define ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0xb +#define ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0xc +#define ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE__SHIFT 0xd +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE__SHIFT 0xe +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE__SHIFT 0xf +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE__SHIFT 0x10 +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE__SHIFT 0x11 +#define ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE__SHIFT 0x12 +#define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE__SHIFT 0x13 +#define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE__SHIFT 0x14 +#define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE__SHIFT 0x15 +#define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE__SHIFT 0x16 +#define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE__SHIFT 0x17 +#define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE__SHIFT 0x18 +#define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE__SHIFT 0x19 +#define ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED__SHIFT 0x1a +#define ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE_MASK 0x00000001L +#define ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE_MASK 0x00000002L +#define ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE_MASK 0x00000004L +#define ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE_MASK 0x00000008L +#define ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE_MASK 0x00000010L +#define ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE_MASK 0x00000020L +#define ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE_MASK 0x00000040L +#define ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE_MASK 0x00000080L +#define ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE_MASK 0x00000100L +#define ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE_MASK 0x00000200L +#define ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE_MASK 0x00000400L +#define ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE_MASK 0x00000800L +#define ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE_MASK 0x00001000L +#define ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE_MASK 0x00002000L +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE_MASK 0x00004000L +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE_MASK 0x00008000L +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE_MASK 0x00010000L +#define ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE_MASK 0x00020000L +#define ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE_MASK 0x00040000L +#define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE_MASK 0x00080000L +#define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE_MASK 0x00100000L +#define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE_MASK 0x00200000L +#define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE_MASK 0x00400000L +#define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE_MASK 0x00800000L +#define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE_MASK 0x01000000L +#define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE_MASK 0x02000000L +#define ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED_MASK 0xFC000000L +//ICG_CHC_CLK_CTRL +#define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L +//ICG_CHCG_CLK_CTRL +#define ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L + + +// addressBlock: gc_hypdec +//GFX_PIPE_PRIORITY +#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 +#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x00000001L +//GRBM_GFX_INDEX_SR_SELECT +#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_INDEX_SR_DATA +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_SELECT +#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_DATA +#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L +//GC_IH_COOKIE_0_PTR +#define GC_IH_COOKIE_0_PTR__ADDR__SHIFT 0x0 +#define GC_IH_COOKIE_0_PTR__ADDR_MASK 0x000FFFFFL +//GRBM_SE_REMAP_CNTL +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT 0x0 +#define GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT 0x1 +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT 0x4 +#define GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT 0x5 +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT 0x8 +#define GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT 0x9 +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT 0xc +#define GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT 0xd +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT 0x10 +#define GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT 0x11 +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT 0x14 +#define GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT 0x15 +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT 0x18 +#define GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT 0x19 +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT 0x1c +#define GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT 0x1d +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK 0x00000001L +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK 0x0000000EL +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK 0x00000010L +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK 0x000000E0L +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK 0x00000100L +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK 0x00000E00L +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK 0x00001000L +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK 0x0000E000L +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK 0x00010000L +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK 0x000E0000L +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK 0x00100000L +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK 0x00E00000L +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK 0x01000000L +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK 0x0E000000L +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK 0x10000000L +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK 0xE0000000L +//RLC_GPU_IOV_VF_ENABLE +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L +//RLC_GPU_IOV_CFG_REG6 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 +#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L +#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L +//RLC_SDMA0_STATUS +#define RLC_SDMA0_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA1_STATUS +#define RLC_SDMA1_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA2_STATUS +#define RLC_SDMA2_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA3_STATUS +#define RLC_SDMA3_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA0_BUSY_STATUS +#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA1_BUSY_STATUS +#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA2_BUSY_STATUS +#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA3_BUSY_STATUS +#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_CFG_REG8 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_INT_0 +#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_INT_1 +#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_CTRL +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 +#define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 +#define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 +#define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 +#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x6 +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L +#define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L +#define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L +#define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L +#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L +//RLC_RLCV_TIMER_STAT +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 +#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa +#define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL +#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +#define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L +#define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L +//RLC_GPU_IOV_VF_DOORBELL_STATUS +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L +//RLC_GPU_IOV_VF_MASK +#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 +#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x7FFFFFFFL +//RLC_HYP_SEMAPHORE_0 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L +//RLC_HYP_SEMAPHORE_1 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L +//RLC_BUSY_CLK_CNTL +#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT 0x0 +#define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY__SHIFT 0x8 +#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK 0x0000003FL +#define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY_MASK 0x00003F00L +//RLC_CLK_CNTL +#define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE__SHIFT 0x0 +#define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE__SHIFT 0x1 +#define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE__SHIFT 0x2 +#define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE__SHIFT 0x3 +#define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE__SHIFT 0x4 +#define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE__SHIFT 0x5 +#define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE__SHIFT 0x6 +#define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE__SHIFT 0x7 +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 +#define RLC_CLK_CNTL__RESERVED_9__SHIFT 0x9 +#define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE__SHIFT 0xa +#define RLC_CLK_CNTL__RESERVED_11__SHIFT 0xb +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc +#define RLC_CLK_CNTL__RESERVED_15__SHIFT 0xf +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 +#define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE__SHIFT 0x13 +#define RLC_CLK_CNTL__RESERVED__SHIFT 0x14 +#define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE_MASK 0x00000001L +#define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE_MASK 0x00000002L +#define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE_MASK 0x00000004L +#define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE_MASK 0x00000008L +#define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE_MASK 0x00000010L +#define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE_MASK 0x00000020L +#define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE_MASK 0x00000040L +#define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE_MASK 0x00000080L +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L +#define RLC_CLK_CNTL__RESERVED_9_MASK 0x00000200L +#define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE_MASK 0x00000400L +#define RLC_CLK_CNTL__RESERVED_11_MASK 0x00000800L +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L +#define RLC_CLK_CNTL__RESERVED_15_MASK 0x00008000L +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L +#define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE_MASK 0x00080000L +#define RLC_CLK_CNTL__RESERVED_MASK 0xFFF00000L +//RLC_PACE_TIMER_STAT +#define RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_PACE_TIMER_STAT__RESERVED__SHIFT 0x2 +#define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa +#define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb +#define RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_PACE_TIMER_STAT__RESERVED_MASK 0x000000FCL +#define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +#define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L +#define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L +//RLC_GPU_IOV_SCH_BLOCK +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x0000FF00L +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0xFFFF0000L +//RLC_GPU_IOV_CFG_REG1 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L +#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L +#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L +//RLC_GPU_IOV_CFG_REG2 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPU_IOV_VM_BUSY_STATUS +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_3 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_1 +#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_2 +#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL +//RLC_PACE_INT_FORCE +#define RLC_PACE_INT_FORCE__FORCE_INT__SHIFT 0x0 +#define RLC_PACE_INT_FORCE__FORCE_INT_MASK 0xFFFFFFFFL +//RLC_PACE_INT_CLEAR +#define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR__SHIFT 0x0 +#define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR__SHIFT 0x1 +#define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR_MASK 0x00000001L +#define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR_MASK 0x00000002L +//RLC_GPU_IOV_INT_STAT +#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL +//RLC_IH_COOKIE +#define RLC_IH_COOKIE__DATA__SHIFT 0x0 +#define RLC_IH_COOKIE__DATA_MASK 0xFFFFFFFFL +//RLC_IH_COOKIE_CNTL +#define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT 0x0 +#define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT 0x2 +#define RLC_IH_COOKIE_CNTL__CREDIT_MASK 0x00000003L +#define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK 0x00000004L +//RLC_HYP_RLCG_UCODE_CHKSUM +#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//RLC_HYP_RLCP_UCODE_CHKSUM +#define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//RLC_HYP_RLCV_UCODE_CHKSUM +#define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_F32_CNTL +#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L +//RLC_GPU_IOV_F32_RESET +#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 +#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L +//RLC_GPU_IOV_UCODE_ADDR +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_GPU_IOV_UCODE_DATA +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SMU_RESPONSE +#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_F32_INVALIDATE_CACHE +#define RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE__SHIFT 0x0 +#define RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE_MASK 0x00000001L +//RLC_GPU_IOV_RLC_RESPONSE +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_DISABLE +#define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT__SHIFT 0x0 +#define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_FORCE +#define RLC_GPU_IOV_INT_FORCE__FORCE_INT__SHIFT 0x0 +#define RLC_GPU_IOV_INT_FORCE__FORCE_INT_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCRATCH_ADDR +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL +//RLC_GPU_IOV_SCRATCH_DATA +#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_HYP_SEMAPHORE_2 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_HYP_SEMAPHORE_3 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L +//RLC_GPM_UCODE_ADDR +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L +//RLC_GPM_UCODE_DATA +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPM_IRAM_ADDR +#define RLC_GPM_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL +//RLC_GPM_IRAM_DATA +#define RLC_GPM_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_RLCP_IRAM_ADDR +#define RLC_RLCP_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_RLCP_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL +//RLC_RLCP_IRAM_DATA +#define RLC_RLCP_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_RLCP_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_IRAM_ADDR +#define RLC_RLCV_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_RLCV_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL +//RLC_RLCV_IRAM_DATA +#define RLC_RLCV_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_RLCV_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_DRAM_ADDR +#define RLC_LX6_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_LX6_DRAM_ADDR__ADDR_MASK 0x000007FFL +//RLC_LX6_DRAM_DATA +#define RLC_LX6_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_LX6_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_IRAM_ADDR +#define RLC_LX6_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_LX6_IRAM_ADDR__ADDR_MASK 0x00000FFFL +//RLC_LX6_IRAM_DATA +#define RLC_LX6_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_LX6_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_PACE_UCODE_ADDR +#define RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_PACE_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +#define RLC_PACE_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_PACE_UCODE_DATA +#define RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_PACE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPM_SCRATCH_ADDR +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL +//RLC_GPM_SCRATCH_DATA +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_DRAM_ADDR +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xd +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00001FFFL +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFE000L +//RLC_SRM_DRAM_DATA +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_ARAM_ADDR +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xd +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00001FFFL +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFE000L +//RLC_SRM_ARAM_DATA +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_PACE_SCRATCH_ADDR +#define RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_PACE_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL +//RLC_PACE_SCRATCH_DATA +#define RLC_PACE_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_PACE_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_LSB +#define RLC_GTS_OFFSET_LSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_MSB +#define RLC_GTS_OFFSET_MSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_MSB__DATA_MASK 0xFFFFFFFFL +//GL2_PIPE_STEER_0 +#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT 0x0 +#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT 0x4 +#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT 0x8 +#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT 0xc +#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT 0x10 +#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT 0x14 +#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT 0x18 +#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT 0x1c +#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK 0x00000007L +#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK 0x00000070L +#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK 0x00000700L +#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK 0x00007000L +#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK 0x00070000L +#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK 0x00700000L +#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK 0x07000000L +#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK 0x70000000L +//GL2_PIPE_STEER_1 +#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT 0x0 +#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT 0x4 +#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT 0x8 +#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT 0xc +#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT 0x10 +#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT 0x14 +#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT 0x18 +#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT 0x1c +#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK 0x00000007L +#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK 0x00000070L +#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK 0x00000700L +#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK 0x00007000L +#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK 0x00070000L +#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK 0x00700000L +#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK 0x07000000L +#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK 0x70000000L +//GL2_PIPE_STEER_2 +#define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0__SHIFT 0x0 +#define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0__SHIFT 0x4 +#define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0__SHIFT 0x8 +#define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0__SHIFT 0xc +#define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1__SHIFT 0x10 +#define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1__SHIFT 0x14 +#define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1__SHIFT 0x18 +#define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1__SHIFT 0x1c +#define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0_MASK 0x00000007L +#define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0_MASK 0x00000070L +#define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0_MASK 0x00000700L +#define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0_MASK 0x00007000L +#define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1_MASK 0x00070000L +#define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1_MASK 0x00700000L +#define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1_MASK 0x07000000L +#define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1_MASK 0x70000000L +//GL2_PIPE_STEER_3 +#define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2__SHIFT 0x0 +#define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2__SHIFT 0x4 +#define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2__SHIFT 0x8 +#define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2__SHIFT 0xc +#define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3__SHIFT 0x10 +#define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3__SHIFT 0x14 +#define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3__SHIFT 0x18 +#define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3__SHIFT 0x1c +#define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2_MASK 0x00000007L +#define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2_MASK 0x00000070L +#define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2_MASK 0x00000700L +#define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2_MASK 0x00007000L +#define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3_MASK 0x00070000L +#define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3_MASK 0x00700000L +#define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3_MASK 0x07000000L +#define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3_MASK 0x70000000L +//GL1_PIPE_STEER +#define GL1_PIPE_STEER__PIPE0__SHIFT 0x0 +#define GL1_PIPE_STEER__PIPE1__SHIFT 0x2 +#define GL1_PIPE_STEER__PIPE2__SHIFT 0x4 +#define GL1_PIPE_STEER__PIPE3__SHIFT 0x6 +#define GL1_PIPE_STEER__PIPE0_MASK 0x00000003L +#define GL1_PIPE_STEER__PIPE1_MASK 0x0000000CL +#define GL1_PIPE_STEER__PIPE2_MASK 0x00000030L +#define GL1_PIPE_STEER__PIPE3_MASK 0x000000C0L +//CH_PIPE_STEER +#define CH_PIPE_STEER__PIPE0__SHIFT 0x0 +#define CH_PIPE_STEER__PIPE1__SHIFT 0x2 +#define CH_PIPE_STEER__PIPE2__SHIFT 0x4 +#define CH_PIPE_STEER__PIPE3__SHIFT 0x6 +#define CH_PIPE_STEER__PIPE0_MASK 0x00000003L +#define CH_PIPE_STEER__PIPE1_MASK 0x0000000CL +#define CH_PIPE_STEER__PIPE2_MASK 0x00000030L +#define CH_PIPE_STEER__PIPE3_MASK 0x000000C0L +//GC_USER_SHADER_ARRAY_CONFIG +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L +//GC_USER_PRIM_CONFIG +#define GC_USER_PRIM_CONFIG__INACTIVE_PA__SHIFT 0x4 +#define GC_USER_PRIM_CONFIG__INACTIVE_PA_MASK 0x000FFFF0L +//GC_USER_SA_UNIT_DISABLE +#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L +//GC_USER_RB_REDUNDANCY +#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//GC_USER_RB_BACKEND_DISABLE +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xFFFFFFF0L +//GC_USER_RMI_REDUNDANCY +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 +#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 +#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L +#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L +#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L +//CGTS_USER_TCC_DISABLE +#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//GC_USER_SHADER_RATE_CONFIG +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +//RLC_GPU_IOV_SDMA0_STATUS +#define RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_STATUS +#define RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA2_STATUS +#define RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_STATUS +#define RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_STATUS +#define RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_STATUS +#define RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_STATUS +#define RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_STATUS +#define RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA0_BUSY_STATUS +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_BUSY_STATUS +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA2_BUSY_STATUS +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_BUSY_STATUS +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_BUSY_STATUS +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_BUSY_STATUS +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_BUSY_STATUS +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_BUSY_STATUS +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL + + +// addressBlock: gc_pspdec +//CP_MES_DM_INDEX_ADDR +#define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_MES_DM_INDEX_DATA +#define CP_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CP_MEC_DM_INDEX_ADDR +#define CP_MEC_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_MEC_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_MEC_DM_INDEX_DATA +#define CP_MEC_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_MEC_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DM_INDEX_ADDR +#define CP_GFX_RS64_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_GFX_RS64_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DM_INDEX_DATA +#define CP_GFX_RS64_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_GFX_RS64_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_PSP_DEBUG +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x2 +#define CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 +#define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 +#define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L +#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L +#define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L +#define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L +//CPC_PSP_DEBUG +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 +#define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 +#define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L +#define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L +#define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L +//GRBM_SEC_CNTL +//GRBM_CAM_INDEX +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL +//GRBM_HYP_CAM_INDEX +#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL +//GRBM_CAM_DATA +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//GRBM_HYP_CAM_DATA +#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//GRBM_CAM_DATA_UPPER +#define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L +#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L +//GRBM_HYP_CAM_DATA_UPPER +#define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L +#define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L +//RLC_FWL_FIRST_VIOL_ADDR +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x0 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT 0x12 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x1e +#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT 0x1f +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x0003FFFFL +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK 0x3FFC0000L +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x40000000L +#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK 0x80000000L + + +// addressBlock: gc_gfx_imu_gfx_imudec +//GFX_IMU_C2PMSG_0 +#define GFX_IMU_C2PMSG_0__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_1 +#define GFX_IMU_C2PMSG_1__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_2 +#define GFX_IMU_C2PMSG_2__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_3 +#define GFX_IMU_C2PMSG_3__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_4 +#define GFX_IMU_C2PMSG_4__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_5 +#define GFX_IMU_C2PMSG_5__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_5__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_6 +#define GFX_IMU_C2PMSG_6__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_6__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_7 +#define GFX_IMU_C2PMSG_7__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_7__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_8 +#define GFX_IMU_C2PMSG_8__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_8__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_9 +#define GFX_IMU_C2PMSG_9__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_9__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_10 +#define GFX_IMU_C2PMSG_10__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_10__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_11 +#define GFX_IMU_C2PMSG_11__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_11__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_12 +#define GFX_IMU_C2PMSG_12__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_12__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_13 +#define GFX_IMU_C2PMSG_13__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_13__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_14 +#define GFX_IMU_C2PMSG_14__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_14__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_15 +#define GFX_IMU_C2PMSG_15__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_15__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_16 +#define GFX_IMU_C2PMSG_16__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_16__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_17 +#define GFX_IMU_C2PMSG_17__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_17__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_18 +#define GFX_IMU_C2PMSG_18__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_18__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_19 +#define GFX_IMU_C2PMSG_19__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_19__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_20 +#define GFX_IMU_C2PMSG_20__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_20__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_21 +#define GFX_IMU_C2PMSG_21__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_21__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_22 +#define GFX_IMU_C2PMSG_22__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_22__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_23 +#define GFX_IMU_C2PMSG_23__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_23__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_24 +#define GFX_IMU_C2PMSG_24__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_24__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_25 +#define GFX_IMU_C2PMSG_25__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_25__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_26 +#define GFX_IMU_C2PMSG_26__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_26__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_27 +#define GFX_IMU_C2PMSG_27__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_27__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_28 +#define GFX_IMU_C2PMSG_28__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_28__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_29 +#define GFX_IMU_C2PMSG_29__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_29__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_30 +#define GFX_IMU_C2PMSG_30__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_30__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_31 +#define GFX_IMU_C2PMSG_31__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_31__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_32 +#define GFX_IMU_C2PMSG_32__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_32__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_33 +#define GFX_IMU_C2PMSG_33__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_33__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_34 +#define GFX_IMU_C2PMSG_34__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_34__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_35 +#define GFX_IMU_C2PMSG_35__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_35__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_36 +#define GFX_IMU_C2PMSG_36__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_36__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_37 +#define GFX_IMU_C2PMSG_37__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_37__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_38 +#define GFX_IMU_C2PMSG_38__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_38__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_39 +#define GFX_IMU_C2PMSG_39__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_39__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_40 +#define GFX_IMU_C2PMSG_40__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_40__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_41 +#define GFX_IMU_C2PMSG_41__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_41__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_42 +#define GFX_IMU_C2PMSG_42__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_42__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_43 +#define GFX_IMU_C2PMSG_43__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_43__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_44 +#define GFX_IMU_C2PMSG_44__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_44__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_45 +#define GFX_IMU_C2PMSG_45__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_45__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_46 +#define GFX_IMU_C2PMSG_46__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_46__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_47 +#define GFX_IMU_C2PMSG_47__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_47__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_MSG_FLAGS +#define GFX_IMU_MSG_FLAGS__STATUS__SHIFT 0x0 +#define GFX_IMU_MSG_FLAGS__STATUS_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_ACCESS_CTRL0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0__SHIFT 0x0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1__SHIFT 0x3 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2__SHIFT 0x6 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3__SHIFT 0x9 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4__SHIFT 0xc +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5__SHIFT 0xf +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6__SHIFT 0x12 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7__SHIFT 0x15 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0_MASK 0x00000007L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1_MASK 0x00000038L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2_MASK 0x000001C0L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3_MASK 0x00000E00L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4_MASK 0x00007000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5_MASK 0x00038000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6_MASK 0x001C0000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7_MASK 0x00E00000L +//GFX_IMU_C2PMSG_ACCESS_CTRL1 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15__SHIFT 0x0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23__SHIFT 0x3 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31__SHIFT 0x6 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39__SHIFT 0x9 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47__SHIFT 0xc +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15_MASK 0x00000007L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23_MASK 0x00000038L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31_MASK 0x000001C0L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39_MASK 0x00000E00L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47_MASK 0x00007000L +//GFX_IMU_PWRMGT_IRQ_CTRL +#define GFX_IMU_PWRMGT_IRQ_CTRL__REQ__SHIFT 0x0 +#define GFX_IMU_PWRMGT_IRQ_CTRL__REQ_MASK 0x00000001L +//GFX_IMU_MP1_MUTEX +#define GFX_IMU_MP1_MUTEX__MUTEX__SHIFT 0x0 +#define GFX_IMU_MP1_MUTEX__MUTEX_MASK 0x00000003L +//GFX_IMU_RLC_DATA_4 +#define GFX_IMU_RLC_DATA_4__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_3 +#define GFX_IMU_RLC_DATA_3__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_2 +#define GFX_IMU_RLC_DATA_2__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_1 +#define GFX_IMU_RLC_DATA_1__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_0 +#define GFX_IMU_RLC_DATA_0__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_CMD +#define GFX_IMU_RLC_CMD__CMD__SHIFT 0x0 +#define GFX_IMU_RLC_CMD__CMD_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_MUTEX +#define GFX_IMU_RLC_MUTEX__MUTEX__SHIFT 0x0 +#define GFX_IMU_RLC_MUTEX__MUTEX_MASK 0x00000003L +//GFX_IMU_RLC_MSG_STATUS +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY__SHIFT 0x0 +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR__SHIFT 0x1 +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE__SHIFT 0x10 +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG__SHIFT 0x1e +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG__SHIFT 0x1f +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY_MASK 0x00000001L +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR_MASK 0x00000002L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE_MASK 0x00010000L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG_MASK 0x40000000L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG_MASK 0x80000000L +//RLC_GFX_IMU_DATA_0 +#define RLC_GFX_IMU_DATA_0__DATA__SHIFT 0x0 +#define RLC_GFX_IMU_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IMU_CMD +#define RLC_GFX_IMU_CMD__CMD__SHIFT 0x0 +#define RLC_GFX_IMU_CMD__CMD_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_STATUS +#define GFX_IMU_RLC_STATUS__PD_ACTIVE__SHIFT 0x0 +#define GFX_IMU_RLC_STATUS__RLC_ALIVE__SHIFT 0x1 +#define GFX_IMU_RLC_STATUS__TBD2__SHIFT 0x2 +#define GFX_IMU_RLC_STATUS__TBD3__SHIFT 0x3 +#define GFX_IMU_RLC_STATUS__PD_ACTIVE_MASK 0x00000001L +#define GFX_IMU_RLC_STATUS__RLC_ALIVE_MASK 0x00000002L +#define GFX_IMU_RLC_STATUS__TBD2_MASK 0x00000004L +#define GFX_IMU_RLC_STATUS__TBD3_MASK 0x00000008L +//GFX_IMU_STATUS +#define GFX_IMU_STATUS__ALLOW_GFXOFF__SHIFT 0x0 +#define GFX_IMU_STATUS__ALLOW_FA_DCS__SHIFT 0x1 +#define GFX_IMU_STATUS__TBD2__SHIFT 0x2 +#define GFX_IMU_STATUS__TBD3__SHIFT 0x3 +#define GFX_IMU_STATUS__TBD4__SHIFT 0x4 +#define GFX_IMU_STATUS__TBD5__SHIFT 0x5 +#define GFX_IMU_STATUS__TBD6__SHIFT 0x6 +#define GFX_IMU_STATUS__TBD7__SHIFT 0x7 +#define GFX_IMU_STATUS__TBD8__SHIFT 0x8 +#define GFX_IMU_STATUS__TBD9__SHIFT 0x9 +#define GFX_IMU_STATUS__TBD10__SHIFT 0xa +#define GFX_IMU_STATUS__TBD11__SHIFT 0xb +#define GFX_IMU_STATUS__TBD12__SHIFT 0xc +#define GFX_IMU_STATUS__TBD13__SHIFT 0xd +#define GFX_IMU_STATUS__TBD14__SHIFT 0xe +#define GFX_IMU_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf +#define GFX_IMU_STATUS__ALLOW_GFXOFF_MASK 0x00000001L +#define GFX_IMU_STATUS__ALLOW_FA_DCS_MASK 0x00000002L +#define GFX_IMU_STATUS__TBD2_MASK 0x00000004L +#define GFX_IMU_STATUS__TBD3_MASK 0x00000008L +#define GFX_IMU_STATUS__TBD4_MASK 0x00000010L +#define GFX_IMU_STATUS__TBD5_MASK 0x00000020L +#define GFX_IMU_STATUS__TBD6_MASK 0x00000040L +#define GFX_IMU_STATUS__TBD7_MASK 0x00000080L +#define GFX_IMU_STATUS__TBD8_MASK 0x00000100L +#define GFX_IMU_STATUS__TBD9_MASK 0x00000200L +#define GFX_IMU_STATUS__TBD10_MASK 0x00000400L +#define GFX_IMU_STATUS__TBD11_MASK 0x00000800L +#define GFX_IMU_STATUS__TBD12_MASK 0x00001000L +#define GFX_IMU_STATUS__TBD13_MASK 0x00002000L +#define GFX_IMU_STATUS__TBD14_MASK 0x00004000L +#define GFX_IMU_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L +//GFX_IMU_SOC_DATA +#define GFX_IMU_SOC_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_SOC_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SOC_ADDR +#define GFX_IMU_SOC_ADDR__ADDR__SHIFT 0x0 +#define GFX_IMU_SOC_ADDR__ADDR_MASK 0xFFFFFFFFL +//GFX_IMU_SOC_REQ +#define GFX_IMU_SOC_REQ__REQ_BUSY__SHIFT 0x0 +#define GFX_IMU_SOC_REQ__R_W__SHIFT 0x1 +#define GFX_IMU_SOC_REQ__ERR__SHIFT 0x1f +#define GFX_IMU_SOC_REQ__REQ_BUSY_MASK 0x00000001L +#define GFX_IMU_SOC_REQ__R_W_MASK 0x00000002L +#define GFX_IMU_SOC_REQ__ERR_MASK 0x80000000L +//GFX_IMU_VF_CTRL +#define GFX_IMU_VF_CTRL__VF__SHIFT 0x0 +#define GFX_IMU_VF_CTRL__VFID__SHIFT 0x1 +#define GFX_IMU_VF_CTRL__QOS__SHIFT 0x7 +#define GFX_IMU_VF_CTRL__VF_MASK 0x00000001L +#define GFX_IMU_VF_CTRL__VFID_MASK 0x0000007EL +#define GFX_IMU_VF_CTRL__QOS_MASK 0x00000780L +//GFX_IMU_TELEMETRY +#define GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES__SHIFT 0x0 +#define GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE__SHIFT 0x5 +#define GFX_IMU_TELEMETRY__FIFO_OVERFLOW__SHIFT 0x6 +#define GFX_IMU_TELEMETRY__FIFO_UNDERFLOW__SHIFT 0x7 +#define GFX_IMU_TELEMETRY__FSM_STATE__SHIFT 0x8 +#define GFX_IMU_TELEMETRY__SVI_TYPE__SHIFT 0xc +#define GFX_IMU_TELEMETRY__ENABLE_FIFO__SHIFT 0x1e +#define GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY__SHIFT 0x1f +#define GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES_MASK 0x0000001FL +#define GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE_MASK 0x00000020L +#define GFX_IMU_TELEMETRY__FIFO_OVERFLOW_MASK 0x00000040L +#define GFX_IMU_TELEMETRY__FIFO_UNDERFLOW_MASK 0x00000080L +#define GFX_IMU_TELEMETRY__FSM_STATE_MASK 0x00000700L +#define GFX_IMU_TELEMETRY__SVI_TYPE_MASK 0x00003000L +#define GFX_IMU_TELEMETRY__ENABLE_FIFO_MASK 0x40000000L +#define GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY_MASK 0x80000000L +//GFX_IMU_TELEMETRY_DATA +#define GFX_IMU_TELEMETRY_DATA__CURRENT__SHIFT 0x0 +#define GFX_IMU_TELEMETRY_DATA__VOLTAGE__SHIFT 0x10 +#define GFX_IMU_TELEMETRY_DATA__CURRENT_MASK 0x0000FFFFL +#define GFX_IMU_TELEMETRY_DATA__VOLTAGE_MASK 0xFFFF0000L +//GFX_IMU_TELEMETRY_TEMPERATURE +#define GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE__SHIFT 0x0 +#define GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE_MASK 0x0000FFFFL +//GFX_IMU_SCRATCH_0 +#define GFX_IMU_SCRATCH_0__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_1 +#define GFX_IMU_SCRATCH_1__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_2 +#define GFX_IMU_SCRATCH_2__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_3 +#define GFX_IMU_SCRATCH_3__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_4 +#define GFX_IMU_SCRATCH_4__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_5 +#define GFX_IMU_SCRATCH_5__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_5__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_6 +#define GFX_IMU_SCRATCH_6__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_6__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_7 +#define GFX_IMU_SCRATCH_7__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_7__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_8 +#define GFX_IMU_SCRATCH_8__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_8__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_9 +#define GFX_IMU_SCRATCH_9__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_9__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_10 +#define GFX_IMU_SCRATCH_10__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_10__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_11 +#define GFX_IMU_SCRATCH_11__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_11__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_12 +#define GFX_IMU_SCRATCH_12__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_12__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_13 +#define GFX_IMU_SCRATCH_13__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_13__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_14 +#define GFX_IMU_SCRATCH_14__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_14__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_15 +#define GFX_IMU_SCRATCH_15__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_15__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_FW_GTS_LO +#define GFX_IMU_FW_GTS_LO__TSTAMP_LO__SHIFT 0x0 +#define GFX_IMU_FW_GTS_LO__TSTAMP_LO_MASK 0xFFFFFFFFL +//GFX_IMU_FW_GTS_HI +#define GFX_IMU_FW_GTS_HI__TSTAMP_HI__SHIFT 0x0 +#define GFX_IMU_FW_GTS_HI__TSTAMP_HI_MASK 0x00FFFFFFL +//GFX_IMU_GTS_OFFSET_LO +#define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 +#define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL +//GFX_IMU_GTS_OFFSET_HI +#define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 +#define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL +//GFX_IMU_RLC_GTS_OFFSET_LO +#define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 +#define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_GTS_OFFSET_HI +#define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 +#define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL +//GFX_IMU_CORE_INT_STATUS +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24__SHIFT 0x18 +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25__SHIFT 0x19 +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29__SHIFT 0x1d +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24_MASK 0x01000000L +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25_MASK 0x02000000L +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29_MASK 0x20000000L +//GFX_IMU_PIC_INT_MASK +#define GFX_IMU_PIC_INT_MASK__MASK_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_MASK__MASK_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_MASK__MASK_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_MASK__MASK_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_MASK__MASK_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_MASK__MASK_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_MASK__MASK_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_MASK__MASK_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_MASK__MASK_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_MASK__MASK_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_MASK__MASK_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_MASK__MASK_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_MASK__MASK_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_MASK__MASK_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_MASK__MASK_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_MASK__MASK_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_MASK__MASK_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_MASK__MASK_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_MASK__MASK_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_MASK__MASK_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_MASK__MASK_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_MASK__MASK_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_MASK__MASK_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_MASK__MASK_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_MASK__MASK_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_MASK__MASK_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_MASK__MASK_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_MASK__MASK_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_MASK__MASK_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_MASK__MASK_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_MASK__MASK_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_MASK__MASK_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_MASK__MASK_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_MASK__MASK_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_MASK__MASK_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_MASK__MASK_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_MASK__MASK_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_MASK__MASK_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_MASK__MASK_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_MASK__MASK_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_MASK__MASK_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_MASK__MASK_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_MASK__MASK_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_MASK__MASK_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_MASK__MASK_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_MASK__MASK_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_MASK__MASK_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_MASK__MASK_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_MASK__MASK_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_MASK__MASK_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_MASK__MASK_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_MASK__MASK_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_MASK__MASK_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_MASK__MASK_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_MASK__MASK_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_MASK__MASK_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_MASK__MASK_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_MASK__MASK_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_MASK__MASK_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_MASK__MASK_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_MASK__MASK_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_MASK__MASK_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_MASK__MASK_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_MASK__MASK_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_LVL +#define GFX_IMU_PIC_INT_LVL__LVL_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_LVL__LVL_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_LVL__LVL_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_LVL__LVL_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_LVL__LVL_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_LVL__LVL_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_LVL__LVL_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_LVL__LVL_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_LVL__LVL_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_LVL__LVL_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_LVL__LVL_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_LVL__LVL_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_LVL__LVL_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_LVL__LVL_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_LVL__LVL_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_LVL__LVL_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_LVL__LVL_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_LVL__LVL_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_LVL__LVL_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_LVL__LVL_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_LVL__LVL_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_LVL__LVL_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_LVL__LVL_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_LVL__LVL_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_LVL__LVL_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_LVL__LVL_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_LVL__LVL_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_LVL__LVL_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_LVL__LVL_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_LVL__LVL_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_LVL__LVL_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_LVL__LVL_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_LVL__LVL_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_LVL__LVL_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_LVL__LVL_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_LVL__LVL_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_LVL__LVL_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_LVL__LVL_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_LVL__LVL_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_LVL__LVL_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_LVL__LVL_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_LVL__LVL_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_LVL__LVL_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_LVL__LVL_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_LVL__LVL_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_LVL__LVL_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_LVL__LVL_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_LVL__LVL_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_LVL__LVL_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_LVL__LVL_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_LVL__LVL_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_LVL__LVL_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_LVL__LVL_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_LVL__LVL_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_LVL__LVL_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_LVL__LVL_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_LVL__LVL_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_LVL__LVL_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_LVL__LVL_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_LVL__LVL_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_LVL__LVL_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_LVL__LVL_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_LVL__LVL_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_LVL__LVL_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_EDGE +#define GFX_IMU_PIC_INT_EDGE__EDGE_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_EDGE__EDGE_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_EDGE__EDGE_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_EDGE__EDGE_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_EDGE__EDGE_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_EDGE__EDGE_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_EDGE__EDGE_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_EDGE__EDGE_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_EDGE__EDGE_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_EDGE__EDGE_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_EDGE__EDGE_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_EDGE__EDGE_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_EDGE__EDGE_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_EDGE__EDGE_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_EDGE__EDGE_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_EDGE__EDGE_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_EDGE__EDGE_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_EDGE__EDGE_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_EDGE__EDGE_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_EDGE__EDGE_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_EDGE__EDGE_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_EDGE__EDGE_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_EDGE__EDGE_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_EDGE__EDGE_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_EDGE__EDGE_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_EDGE__EDGE_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_EDGE__EDGE_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_EDGE__EDGE_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_EDGE__EDGE_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_EDGE__EDGE_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_EDGE__EDGE_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_EDGE__EDGE_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_EDGE__EDGE_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_EDGE__EDGE_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_EDGE__EDGE_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_EDGE__EDGE_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_EDGE__EDGE_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_EDGE__EDGE_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_EDGE__EDGE_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_EDGE__EDGE_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_EDGE__EDGE_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_EDGE__EDGE_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_EDGE__EDGE_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_EDGE__EDGE_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_EDGE__EDGE_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_PRI_0 +#define GFX_IMU_PIC_INT_PRI_0__PRI_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_0__PRI_1__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_0__PRI_2__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_0__PRI_3__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_0__PRI_0_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_0__PRI_1_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_0__PRI_2_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_0__PRI_3_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_1 +#define GFX_IMU_PIC_INT_PRI_1__PRI_4__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_1__PRI_5__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_1__PRI_6__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_1__PRI_7__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_1__PRI_4_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_1__PRI_5_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_1__PRI_6_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_1__PRI_7_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_2 +#define GFX_IMU_PIC_INT_PRI_2__PRI_8__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_2__PRI_9__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_2__PRI_10__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_2__PRI_11__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_2__PRI_8_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_2__PRI_9_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_2__PRI_10_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_2__PRI_11_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_3 +#define GFX_IMU_PIC_INT_PRI_3__PRI_12__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_3__PRI_13__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_3__PRI_14__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_3__PRI_15__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_3__PRI_12_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_3__PRI_13_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_3__PRI_14_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_3__PRI_15_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_4 +#define GFX_IMU_PIC_INT_PRI_4__PRI_16__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_4__PRI_17__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_4__PRI_18__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_4__PRI_19__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_4__PRI_16_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_4__PRI_17_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_4__PRI_18_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_4__PRI_19_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_5 +#define GFX_IMU_PIC_INT_PRI_5__PRI_20__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_5__PRI_21__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_5__PRI_22__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_5__PRI_23__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_5__PRI_20_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_5__PRI_21_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_5__PRI_22_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_5__PRI_23_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_6 +#define GFX_IMU_PIC_INT_PRI_6__PRI_24__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_6__PRI_25__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_6__PRI_26__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_6__PRI_27__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_6__PRI_24_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_6__PRI_25_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_6__PRI_26_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_6__PRI_27_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_7 +#define GFX_IMU_PIC_INT_PRI_7__PRI_28__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_7__PRI_29__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_7__PRI_30__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_7__PRI_31__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_7__PRI_28_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_7__PRI_29_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_7__PRI_30_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_7__PRI_31_MASK 0xFF000000L +//GFX_IMU_PIC_INT_STATUS +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS10__SHIFT 0xa +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS11__SHIFT 0xb +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS12__SHIFT 0xc +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS13__SHIFT 0xd +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS14__SHIFT 0xe +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS15__SHIFT 0xf +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS31_MASK 0x80000000L +//GFX_IMU_PIC_INTR +#define GFX_IMU_PIC_INTR__INTR_n__SHIFT 0x0 +#define GFX_IMU_PIC_INTR__INTR_n_MASK 0x00000001L +//GFX_IMU_PIC_INTR_ID +#define GFX_IMU_PIC_INTR_ID__INTR_n__SHIFT 0x0 +#define GFX_IMU_PIC_INTR_ID__INTR_n_MASK 0x000000FFL +//GFX_IMU_IH_CTRL_1 +#define GFX_IMU_IH_CTRL_1__CONTEXT_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_1__CONTEXT_ID_MASK 0xFFFFFFFFL +//GFX_IMU_IH_CTRL_2 +#define GFX_IMU_IH_CTRL_2__CONTEXT_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_2__RING_ID__SHIFT 0x8 +#define GFX_IMU_IH_CTRL_2__VM_ID__SHIFT 0x10 +#define GFX_IMU_IH_CTRL_2__SRSTB__SHIFT 0x1f +#define GFX_IMU_IH_CTRL_2__CONTEXT_ID_MASK 0x000000FFL +#define GFX_IMU_IH_CTRL_2__RING_ID_MASK 0x0000FF00L +#define GFX_IMU_IH_CTRL_2__VM_ID_MASK 0x000F0000L +#define GFX_IMU_IH_CTRL_2__SRSTB_MASK 0x80000000L +//GFX_IMU_IH_CTRL_3 +#define GFX_IMU_IH_CTRL_3__SOURCE_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_3__VF_ID__SHIFT 0x8 +#define GFX_IMU_IH_CTRL_3__VF__SHIFT 0xd +#define GFX_IMU_IH_CTRL_3__SOURCE_ID_MASK 0x000000FFL +#define GFX_IMU_IH_CTRL_3__VF_ID_MASK 0x00001F00L +#define GFX_IMU_IH_CTRL_3__VF_MASK 0x00002000L +//GFX_IMU_IH_STATUS +#define GFX_IMU_IH_STATUS__IH_BUSY__SHIFT 0x0 +#define GFX_IMU_IH_STATUS__IH_BUSY_MASK 0x00000001L +//GFX_IMU_FUSESTRAP +//GFX_IMU_SMUIO_VIDCHG_CTRL +#define GFX_IMU_SMUIO_VIDCHG_CTRL__REQ__SHIFT 0x0 +#define GFX_IMU_SMUIO_VIDCHG_CTRL__DATA__SHIFT 0x1 +#define GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN__SHIFT 0xa +#define GFX_IMU_SMUIO_VIDCHG_CTRL__ACK__SHIFT 0xb +#define GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL__SHIFT 0x1f +#define GFX_IMU_SMUIO_VIDCHG_CTRL__REQ_MASK 0x00000001L +#define GFX_IMU_SMUIO_VIDCHG_CTRL__DATA_MASK 0x000003FEL +#define GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN_MASK 0x00000400L +#define GFX_IMU_SMUIO_VIDCHG_CTRL__ACK_MASK 0x00000800L +#define GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL_MASK 0x80000000L +//GFX_IMU_GFXCLK_BYPASS_CTRL +#define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL__SHIFT 0x0 +#define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL_MASK 0x00000001L +//GFX_IMU_CLK_CTRL +#define GFX_IMU_CLK_CTRL__CG_OVR__SHIFT 0x0 +#define GFX_IMU_CLK_CTRL__CG_OVR_CORE__SHIFT 0x1 +#define GFX_IMU_CLK_CTRL__CLKDIV__SHIFT 0x4 +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG__SHIFT 0x8 +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG__SHIFT 0x9 +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV__SHIFT 0x10 +#define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD__SHIFT 0x1c +#define GFX_IMU_CLK_CTRL__CG_OVR_MASK 0x00000001L +#define GFX_IMU_CLK_CTRL__CG_OVR_CORE_MASK 0x00000002L +#define GFX_IMU_CLK_CTRL__CLKDIV_MASK 0x00000010L +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG_MASK 0x00000100L +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG_MASK 0x00000200L +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV_MASK 0x007F0000L +#define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD_MASK 0xF0000000L +//GFX_IMU_DOORBELL_CONTROL +#define GFX_IMU_DOORBELL_CONTROL__OVR_EN__SHIFT 0x0 +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR__SHIFT 0x1 +#define GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT__SHIFT 0x18 +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS__SHIFT 0x1f +#define GFX_IMU_DOORBELL_CONTROL__OVR_EN_MASK 0x00000001L +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR_MASK 0x00000002L +#define GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT_MASK 0x7F000000L +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS_MASK 0x80000000L +//GFX_IMU_RLC_CG_CTRL +#define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG__SHIFT 0x0 +#define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN__SHIFT 0x1 +#define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG_MASK 0x00000001L +#define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN_MASK 0x00000002L +//GFX_IMU_RLC_THROTTLE_GFX +#define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN__SHIFT 0x0 +#define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN_MASK 0x00000001L +//GFX_IMU_RLC_RESET_VECTOR +#define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF__SHIFT 0x0 +#define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT__SHIFT 0x2 +#define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT__SHIFT 0x3 +#define GFX_IMU_RLC_RESET_VECTOR__VECTOR__SHIFT 0x4 +#define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF_MASK 0x00000001L +#define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT_MASK 0x00000004L +#define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT_MASK 0x00000008L +#define GFX_IMU_RLC_RESET_VECTOR__VECTOR_MASK 0x000000F0L +//GFX_IMU_RLC_OVERRIDE +#define GFX_IMU_RLC_OVERRIDE__DS_ALLOW__SHIFT 0x0 +#define GFX_IMU_RLC_OVERRIDE__DS_ALLOW_MASK 0x00000001L +//GFX_IMU_DPM_CONTROL +#define GFX_IMU_DPM_CONTROL__ACC_RESET__SHIFT 0x0 +#define GFX_IMU_DPM_CONTROL__ACC_START__SHIFT 0x1 +#define GFX_IMU_DPM_CONTROL__BUSY_MASK__SHIFT 0x2 +#define GFX_IMU_DPM_CONTROL__ACC_RESET_MASK 0x00000001L +#define GFX_IMU_DPM_CONTROL__ACC_START_MASK 0x00000002L +#define GFX_IMU_DPM_CONTROL__BUSY_MASK_MASK 0x0003FFFCL +//GFX_IMU_DPM_ACC +#define GFX_IMU_DPM_ACC__COUNT__SHIFT 0x0 +#define GFX_IMU_DPM_ACC__COUNT_MASK 0x00FFFFFFL +//GFX_IMU_DPM_REF_COUNTER +#define GFX_IMU_DPM_REF_COUNTER__COUNT__SHIFT 0x0 +#define GFX_IMU_DPM_REF_COUNTER__COUNT_MASK 0x00FFFFFFL +//GFX_IMU_RLC_RAM_INDEX +#define GFX_IMU_RLC_RAM_INDEX__INDEX__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX__SHIFT 0x10 +#define GFX_IMU_RLC_RAM_INDEX__RAM_VALID__SHIFT 0x1f +#define GFX_IMU_RLC_RAM_INDEX__INDEX_MASK 0x000000FFL +#define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX_MASK 0x00FF0000L +#define GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK 0x80000000L +//GFX_IMU_RLC_RAM_ADDR_HIGH +#define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB_MASK 0x0000FFFFL +//GFX_IMU_RLC_RAM_ADDR_LOW +#define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_RAM_DATA +#define GFX_IMU_RLC_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_FENCE_CTRL +#define GFX_IMU_FENCE_CTRL__ENABLED__SHIFT 0x0 +#define GFX_IMU_FENCE_CTRL__ARM_LOG__SHIFT 0x1 +#define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS__SHIFT 0x3 +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN__SHIFT 0x8 +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR__SHIFT 0x9 +#define GFX_IMU_FENCE_CTRL__ENABLED_MASK 0x00000001L +#define GFX_IMU_FENCE_CTRL__ARM_LOG_MASK 0x00000002L +#define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS_MASK 0x00000008L +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN_MASK 0x00000100L +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_MASK 0x00000200L +//GFX_IMU_FENCE_LOG_INIT +#define GFX_IMU_FENCE_LOG_INIT__UNIT_ID__SHIFT 0x0 +#define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID__SHIFT 0x7 +#define GFX_IMU_FENCE_LOG_INIT__UNIT_ID_MASK 0x0000007FL +#define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID_MASK 0x0001FF80L +//GFX_IMU_FENCE_LOG_ADDR +#define GFX_IMU_FENCE_LOG_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_FENCE_LOG_ADDR__ADDR_MASK 0x000FFFFCL +//GFX_IMU_PROGRAM_CTR +#define GFX_IMU_PROGRAM_CTR__PC__SHIFT 0x0 +#define GFX_IMU_PROGRAM_CTR__PC_MASK 0xFFFFFFFFL +//GFX_IMU_CORE_CTRL +#define GFX_IMU_CORE_CTRL__CRESET__SHIFT 0x0 +#define GFX_IMU_CORE_CTRL__CSTALL__SHIFT 0x1 +#define GFX_IMU_CORE_CTRL__DRESET__SHIFT 0x3 +#define GFX_IMU_CORE_CTRL__HALT_ON_RESET__SHIFT 0x4 +#define GFX_IMU_CORE_CTRL__BREAK_IN__SHIFT 0x8 +#define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK__SHIFT 0x9 +#define GFX_IMU_CORE_CTRL__CRESET_MASK 0x00000001L +#define GFX_IMU_CORE_CTRL__CSTALL_MASK 0x00000002L +#define GFX_IMU_CORE_CTRL__DRESET_MASK 0x00000008L +#define GFX_IMU_CORE_CTRL__HALT_ON_RESET_MASK 0x00000010L +#define GFX_IMU_CORE_CTRL__BREAK_IN_MASK 0x00000100L +#define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK_MASK 0x00000200L +//GFX_IMU_CORE_STATUS +#define GFX_IMU_CORE_STATUS__CBUSY__SHIFT 0x0 +#define GFX_IMU_CORE_STATUS__PWAIT_MODE__SHIFT 0x1 +#define GFX_IMU_CORE_STATUS__CINTLEVEL__SHIFT 0x4 +#define GFX_IMU_CORE_STATUS__BREAK_IN_ACK__SHIFT 0x8 +#define GFX_IMU_CORE_STATUS__BREAK_OUT__SHIFT 0x9 +#define GFX_IMU_CORE_STATUS__P_FATAL_ERROR__SHIFT 0xb +#define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL__SHIFT 0x18 +#define GFX_IMU_CORE_STATUS__FAULT_TYPE__SHIFT 0x1c +#define GFX_IMU_CORE_STATUS__CBUSY_MASK 0x00000001L +#define GFX_IMU_CORE_STATUS__PWAIT_MODE_MASK 0x00000002L +#define GFX_IMU_CORE_STATUS__CINTLEVEL_MASK 0x000000F0L +#define GFX_IMU_CORE_STATUS__BREAK_IN_ACK_MASK 0x00000100L +#define GFX_IMU_CORE_STATUS__BREAK_OUT_MASK 0x00000200L +#define GFX_IMU_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000800L +#define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL_MASK 0x0F000000L +#define GFX_IMU_CORE_STATUS__FAULT_TYPE_MASK 0xF0000000L +//GFX_IMU_PWROKRAW +#define GFX_IMU_PWROKRAW__PWROKRAW__SHIFT 0x0 +#define GFX_IMU_PWROKRAW__PWROKRAW_MASK 0x00000001L +//GFX_IMU_PWROK +#define GFX_IMU_PWROK__PWROK__SHIFT 0x0 +#define GFX_IMU_PWROK__PWROK_MASK 0x00000001L +//GFX_IMU_GAP_PWROK +#define GFX_IMU_GAP_PWROK__GAP_PWROK__SHIFT 0x0 +#define GFX_IMU_GAP_PWROK__GAP_PWROK_MASK 0x00000001L +//GFX_IMU_RESETn +#define GFX_IMU_RESETn__Cpl_RESETn__SHIFT 0x0 +#define GFX_IMU_RESETn__Cpl_RESETn_MASK 0x00000001L +//GFX_IMU_GFX_RESET_CTRL +#define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB__SHIFT 0x0 +#define GFX_IMU_GFX_RESET_CTRL__EA_RESETB__SHIFT 0x1 +#define GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB__SHIFT 0x2 +#define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB__SHIFT 0x3 +#define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB__SHIFT 0x4 +#define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB_MASK 0x00000001L +#define GFX_IMU_GFX_RESET_CTRL__EA_RESETB_MASK 0x00000002L +#define GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB_MASK 0x00000004L +#define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB_MASK 0x00000008L +#define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB_MASK 0x00000010L +//GFX_IMU_AEB_OVERRIDE +#define GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL__SHIFT 0x0 +#define GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE__SHIFT 0x1 +#define GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE__SHIFT 0x2 +#define GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL_MASK 0x00000001L +#define GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE_MASK 0x00000002L +#define GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE_MASK 0x00000004L +//GFX_IMU_VDCI_RESET_CTRL +#define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn__SHIFT 0x0 +#define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET__SHIFT 0x1 +#define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET__SHIFT 0x2 +#define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn__SHIFT 0x4 +#define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn_MASK 0x00000001L +#define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET_MASK 0x00000002L +#define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET_MASK 0x00000004L +#define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn_MASK 0x00000010L +//GFX_IMU_GFX_ISO_CTRL +#define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn__SHIFT 0x0 +#define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN__SHIFT 0x1 +#define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN__SHIFT 0x2 +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn__SHIFT 0x3 +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn__SHIFT 0x4 +#define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn_MASK 0x00000001L +#define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN_MASK 0x00000002L +#define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN_MASK 0x00000004L +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn_MASK 0x00000008L +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn_MASK 0x00000010L +//GFX_IMU_TIMER0_CTRL0 +#define GFX_IMU_TIMER0_CTRL0__START_STOP__SHIFT 0x0 +#define GFX_IMU_TIMER0_CTRL0__CLEAR__SHIFT 0x8 +#define GFX_IMU_TIMER0_CTRL0__UP_DOWN__SHIFT 0x10 +#define GFX_IMU_TIMER0_CTRL0__PULSE_EN__SHIFT 0x18 +#define GFX_IMU_TIMER0_CTRL0__START_STOP_MASK 0x00000001L +#define GFX_IMU_TIMER0_CTRL0__CLEAR_MASK 0x00000100L +#define GFX_IMU_TIMER0_CTRL0__UP_DOWN_MASK 0x00010000L +#define GFX_IMU_TIMER0_CTRL0__PULSE_EN_MASK 0x01000000L +//GFX_IMU_TIMER0_CTRL1 +#define GFX_IMU_TIMER0_CTRL1__PWM_EN__SHIFT 0x0 +#define GFX_IMU_TIMER0_CTRL1__TS_MODE__SHIFT 0x8 +#define GFX_IMU_TIMER0_CTRL1__SAT_EN__SHIFT 0x10 +#define GFX_IMU_TIMER0_CTRL1__PWM_EN_MASK 0x00000001L +#define GFX_IMU_TIMER0_CTRL1__TS_MODE_MASK 0x00000100L +#define GFX_IMU_TIMER0_CTRL1__SAT_EN_MASK 0x00010000L +//GFX_IMU_TIMER0_CMP_AUTOINC +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L +//GFX_IMU_TIMER0_CMP_INTEN +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3_MASK 0x00000008L +//GFX_IMU_TIMER0_CMP0 +#define GFX_IMU_TIMER0_CMP0__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP0__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_CMP1 +#define GFX_IMU_TIMER0_CMP1__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP1__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_CMP3 +#define GFX_IMU_TIMER0_CMP3__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP3__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_VALUE +#define GFX_IMU_TIMER0_VALUE__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_VALUE__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CTRL0 +#define GFX_IMU_TIMER1_CTRL0__START_STOP__SHIFT 0x0 +#define GFX_IMU_TIMER1_CTRL0__CLEAR__SHIFT 0x8 +#define GFX_IMU_TIMER1_CTRL0__UP_DOWN__SHIFT 0x10 +#define GFX_IMU_TIMER1_CTRL0__PULSE_EN__SHIFT 0x18 +#define GFX_IMU_TIMER1_CTRL0__START_STOP_MASK 0x00000001L +#define GFX_IMU_TIMER1_CTRL0__CLEAR_MASK 0x00000100L +#define GFX_IMU_TIMER1_CTRL0__UP_DOWN_MASK 0x00010000L +#define GFX_IMU_TIMER1_CTRL0__PULSE_EN_MASK 0x01000000L +//GFX_IMU_TIMER1_CTRL1 +#define GFX_IMU_TIMER1_CTRL1__PWM_EN__SHIFT 0x0 +#define GFX_IMU_TIMER1_CTRL1__TS_MODE__SHIFT 0x8 +#define GFX_IMU_TIMER1_CTRL1__SAT_EN__SHIFT 0x10 +#define GFX_IMU_TIMER1_CTRL1__PWM_EN_MASK 0x00000001L +#define GFX_IMU_TIMER1_CTRL1__TS_MODE_MASK 0x00000100L +#define GFX_IMU_TIMER1_CTRL1__SAT_EN_MASK 0x00010000L +//GFX_IMU_TIMER1_CMP_AUTOINC +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L +//GFX_IMU_TIMER1_CMP_INTEN +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3_MASK 0x00000008L +//GFX_IMU_TIMER1_CMP0 +#define GFX_IMU_TIMER1_CMP0__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP0__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CMP1 +#define GFX_IMU_TIMER1_CMP1__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP1__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CMP3 +#define GFX_IMU_TIMER1_CMP3__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP3__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_VALUE +#define GFX_IMU_TIMER1_VALUE__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_VALUE__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER2_CTRL0 +#define GFX_IMU_TIMER2_CTRL0__START_STOP__SHIFT 0x0 +#define GFX_IMU_TIMER2_CTRL0__CLEAR__SHIFT 0x8 +#define GFX_IMU_TIMER2_CTRL0__UP_DOWN__SHIFT 0x10 +#define GFX_IMU_TIMER2_CTRL0__PULSE_EN__SHIFT 0x18 +#define GFX_IMU_TIMER2_CTRL0__START_STOP_MASK 0x00000001L +#define GFX_IMU_TIMER2_CTRL0__CLEAR_MASK 0x00000100L +#define GFX_IMU_TIMER2_CTRL0__UP_DOWN_MASK 0x00010000L +#define GFX_IMU_TIMER2_CTRL0__PULSE_EN_MASK 0x01000000L +//GFX_IMU_TIMER2_CTRL1 +#define GFX_IMU_TIMER2_CTRL1__PWM_EN__SHIFT 0x0 +#define GFX_IMU_TIMER2_CTRL1__TS_MODE__SHIFT 0x8 +#define GFX_IMU_TIMER2_CTRL1__SAT_EN__SHIFT 0x10 +#define GFX_IMU_TIMER2_CTRL1__PWM_EN_MASK 0x00000001L +#define GFX_IMU_TIMER2_CTRL1__TS_MODE_MASK 0x00000100L +#define GFX_IMU_TIMER2_CTRL1__SAT_EN_MASK 0x00010000L +//GFX_IMU_TIMER2_CMP_AUTOINC +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L +//GFX_IMU_TIMER2_CMP_INTEN +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER2_CMP_INTEN__INT_EN3_MASK 0x00000008L +//GFX_IMU_TIMER2_CMP0 +#define GFX_IMU_TIMER2_CMP0__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER2_CMP0__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER2_CMP1 +#define GFX_IMU_TIMER2_CMP1__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER2_CMP1__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER2_CMP3 +#define GFX_IMU_TIMER2_CMP3__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER2_CMP3__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER2_VALUE +#define GFX_IMU_TIMER2_VALUE__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER2_VALUE__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_FUSE_CTRL +#define GFX_IMU_FUSE_CTRL__DIV_OVR__SHIFT 0x0 +#define GFX_IMU_FUSE_CTRL__DIV_OVR_EN__SHIFT 0x5 +#define GFX_IMU_FUSE_CTRL__FORCE_DONE__SHIFT 0x6 +#define GFX_IMU_FUSE_CTRL__DIV_OVR_MASK 0x0000001FL +#define GFX_IMU_FUSE_CTRL__DIV_OVR_EN_MASK 0x00000020L +#define GFX_IMU_FUSE_CTRL__FORCE_DONE_MASK 0x00000040L +//GFX_IMU_D_RAM_ADDR +#define GFX_IMU_D_RAM_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_D_RAM_ADDR__ADDR_MASK 0x0000FFFCL +//GFX_IMU_D_RAM_DATA +#define GFX_IMU_D_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_D_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_GFX_IH_GASKET_CTRL +#define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB__SHIFT 0x0 +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL__SHIFT 0x10 +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW__SHIFT 0x14 +#define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB_MASK 0x00000001L +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL_MASK 0x000F0000L +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW_MASK 0x00100000L + + +// addressBlock: gc_gfx_imu_gfx_imu_pspdec +//GFX_IMU_I_RAM_ADDR +#define GFX_IMU_I_RAM_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_I_RAM_ADDR__ADDR_MASK 0x0000FFFCL +//GFX_IMU_I_RAM_DATA +#define GFX_IMU_I_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_I_RAM_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gccacind +//GC_CAC_ID +#define GC_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 +#define GC_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 +#define GC_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL +#define GC_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L +//GC_CAC_CNTL +#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x0 +#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0000FFFFL +//GC_CAC_ACC_CP0 +#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP1 +#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP2 +#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA0 +#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA1 +#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA2 +#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA3 +#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA4 +#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA5 +#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER0 +#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER1 +#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER2 +#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER3 +#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER4 +#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER5 +#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER6 +#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER7 +#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER8 +#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER9 +#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML20 +#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML21 +#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML22 +#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML23 +#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML24 +#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER0 +#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER1 +#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER2 +#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER3 +#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER4 +#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS0 +#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS1 +#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS2 +#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS3 +#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS4 +#define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE0 +#define GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE1 +#define GC_CAC_ACC_GE1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE2 +#define GC_CAC_ACC_GE2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE3 +#define GC_CAC_ACC_GE3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE4 +#define GC_CAC_ACC_GE4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE5 +#define GC_CAC_ACC_GE5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE6 +#define GC_CAC_ACC_GE6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE7 +#define GC_CAC_ACC_GE7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE8 +#define GC_CAC_ACC_GE8__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE9 +#define GC_CAC_ACC_GE9__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE10 +#define GC_CAC_ACC_GE10__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE11 +#define GC_CAC_ACC_GE11__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE12 +#define GC_CAC_ACC_GE12__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE13 +#define GC_CAC_ACC_GE13__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE14 +#define GC_CAC_ACC_GE14__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE14__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE15 +#define GC_CAC_ACC_GE15__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE15__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE16 +#define GC_CAC_ACC_GE16__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE16__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE17 +#define GC_CAC_ACC_GE17__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE17__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE18 +#define GC_CAC_ACC_GE18__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE18__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE19 +#define GC_CAC_ACC_GE19__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE19__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GE20 +#define GC_CAC_ACC_GE20__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GE20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PMM0 +#define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GL2C0 +#define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GL2C1 +#define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GL2C2 +#define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GL2C3 +#define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GL2C4 +#define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH0 +#define GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH1 +#define GC_CAC_ACC_PH1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH2 +#define GC_CAC_ACC_PH2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH3 +#define GC_CAC_ACC_PH3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH4 +#define GC_CAC_ACC_PH4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH5 +#define GC_CAC_ACC_PH5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH6 +#define GC_CAC_ACC_PH6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PH7 +#define GC_CAC_ACC_PH7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PH7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA0 +#define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA1 +#define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA2 +#define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA3 +#define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA4 +#define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA5 +#define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA6 +#define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA7 +#define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA8 +#define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA9 +#define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA10 +#define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SDMA11 +#define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CHC0 +#define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CHC1 +#define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CHC2 +#define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GUS0 +#define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GUS1 +#define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GUS2 +#define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_RLC0 +#define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//RELEASE_TO_STALL_LUT_1_8 +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L +#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L +//RELEASE_TO_STALL_LUT_9_16 +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L +#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L +//RELEASE_TO_STALL_LUT_17_20 +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L +#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L +//STALL_TO_RELEASE_LUT_1_4 +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L +#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L +//STALL_TO_RELEASE_LUT_5_7 +#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 +#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 +#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 +#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL +#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L +#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L +//STALL_TO_PWRBRK_LUT_1_4 +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK 0x00000007L +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK 0x00000700L +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK 0x00070000L +#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK 0x07000000L +//STALL_TO_PWRBRK_LUT_5_7 +#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 +#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 +#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 +#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK 0x00000007L +#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK 0x00000700L +#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK 0x00070000L +//PWRBRK_STALL_TO_RELEASE_LUT_1_4 +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L +#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L +//PWRBRK_STALL_TO_RELEASE_LUT_5_7 +#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 +#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 +#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 +#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL +#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L +#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L +//PWRBRK_RELEASE_TO_STALL_LUT_1_8 +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L +#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L +//PWRBRK_RELEASE_TO_STALL_LUT_9_16 +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L +#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L +//PWRBRK_RELEASE_TO_STALL_LUT_17_20 +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L +#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L +//FIXED_PATTERN_PERF_COUNTER_1 +#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_2 +#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_3 +#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_4 +#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_5 +#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_6 +#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_7 +#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_8 +#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_9 +#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_10 +#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL +//HW_LUT_UPDATE_STATUS +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT 0x0 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT 0x1 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT 0x2 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT 0x5 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT 0x6 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT 0x7 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT 0xa +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT 0xb +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT 0xc +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT 0x11 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT 0x12 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT 0x13 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT 0x16 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT 0x17 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT 0x18 +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK 0x00000001L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK 0x00000002L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK 0x0000001CL +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK 0x00000020L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK 0x00000040L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK 0x00000380L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK 0x00000400L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK 0x00000800L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK 0x0001F000L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK 0x00020000L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK 0x00040000L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK 0x00380000L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK 0x00400000L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK 0x00800000L +#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK 0x1F000000L + + +// addressBlock: secacind +//SE_CAC_ID +#define SE_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 +#define SE_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 +#define SE_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL +#define SE_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L +//SE_CAC_CNTL +#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x0 +#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0000FFFFL + + +// addressBlock: grtavfsind +//RTAVFS_REG0 +#define RTAVFS_REG0__RTAVFSZONE0STARTCNT__SHIFT 0x0 +#define RTAVFS_REG0__RTAVFSZONE0STOPCNT__SHIFT 0x10 +#define RTAVFS_REG0__RTAVFSZONE0STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG0__RTAVFSZONE0STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG1 +#define RTAVFS_REG1__RTAVFSZONE1STARTCNT__SHIFT 0x0 +#define RTAVFS_REG1__RTAVFSZONE1STOPCNT__SHIFT 0x10 +#define RTAVFS_REG1__RTAVFSZONE1STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG1__RTAVFSZONE1STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG2 +#define RTAVFS_REG2__RTAVFSZONE2STARTCNT__SHIFT 0x0 +#define RTAVFS_REG2__RTAVFSZONE2STOPCNT__SHIFT 0x10 +#define RTAVFS_REG2__RTAVFSZONE2STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG2__RTAVFSZONE2STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG3 +#define RTAVFS_REG3__RTAVFSZONE3STARTCNT__SHIFT 0x0 +#define RTAVFS_REG3__RTAVFSZONE3STOPCNT__SHIFT 0x10 +#define RTAVFS_REG3__RTAVFSZONE3STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG3__RTAVFSZONE3STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG4 +#define RTAVFS_REG4__RTAVFSZONE4STARTCNT__SHIFT 0x0 +#define RTAVFS_REG4__RTAVFSZONE4STOPCNT__SHIFT 0x10 +#define RTAVFS_REG4__RTAVFSZONE4STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG4__RTAVFSZONE4STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG5 +#define RTAVFS_REG5__RTAVFSZONE0EN0__SHIFT 0x0 +#define RTAVFS_REG5__RTAVFSZONE0EN0_MASK 0xFFFFFFFFL +//RTAVFS_REG6 +#define RTAVFS_REG6__RTAVFSZONE0EN1__SHIFT 0x0 +#define RTAVFS_REG6__RTAVFSZONE0EN1_MASK 0xFFFFFFFFL +//RTAVFS_REG7 +#define RTAVFS_REG7__RTAVFSZONE1EN0__SHIFT 0x0 +#define RTAVFS_REG7__RTAVFSZONE1EN0_MASK 0xFFFFFFFFL +//RTAVFS_REG8 +#define RTAVFS_REG8__RTAVFSZONE1EN1__SHIFT 0x0 +#define RTAVFS_REG8__RTAVFSZONE1EN1_MASK 0xFFFFFFFFL +//RTAVFS_REG9 +#define RTAVFS_REG9__RTAVFSZONE2EN0__SHIFT 0x0 +#define RTAVFS_REG9__RTAVFSZONE2EN0_MASK 0xFFFFFFFFL +//RTAVFS_REG10 +#define RTAVFS_REG10__RTAVFSZONE2EN1__SHIFT 0x0 +#define RTAVFS_REG10__RTAVFSZONE2EN1_MASK 0xFFFFFFFFL +//RTAVFS_REG11 +#define RTAVFS_REG11__RTAVFSZONE3EN0__SHIFT 0x0 +#define RTAVFS_REG11__RTAVFSZONE3EN0_MASK 0xFFFFFFFFL +//RTAVFS_REG12 +#define RTAVFS_REG12__RTAVFSZONE3EN1__SHIFT 0x0 +#define RTAVFS_REG12__RTAVFSZONE3EN1_MASK 0xFFFFFFFFL +//RTAVFS_REG13 +#define RTAVFS_REG13__RTAVFSZONE4EN0__SHIFT 0x0 +#define RTAVFS_REG13__RTAVFSZONE4EN0_MASK 0xFFFFFFFFL +//RTAVFS_REG14 +#define RTAVFS_REG14__RTAVFSZONE4EN1__SHIFT 0x0 +#define RTAVFS_REG14__RTAVFSZONE4EN1_MASK 0xFFFFFFFFL +//RTAVFS_REG15 +#define RTAVFS_REG15__RTAVFSVF0FREQCOUNT__SHIFT 0x0 +#define RTAVFS_REG15__RTAVFSVF0VOLTCODE__SHIFT 0x10 +#define RTAVFS_REG15__RTAVFSVF0FREQCOUNT_MASK 0x0000FFFFL +#define RTAVFS_REG15__RTAVFSVF0VOLTCODE_MASK 0xFFFF0000L +//RTAVFS_REG16 +#define RTAVFS_REG16__RTAVFSVF1FREQCOUNT__SHIFT 0x0 +#define RTAVFS_REG16__RTAVFSVF1VOLTCODE__SHIFT 0x10 +#define RTAVFS_REG16__RTAVFSVF1FREQCOUNT_MASK 0x0000FFFFL +#define RTAVFS_REG16__RTAVFSVF1VOLTCODE_MASK 0xFFFF0000L +//RTAVFS_REG17 +#define RTAVFS_REG17__RTAVFSVF2FREQCOUNT__SHIFT 0x0 +#define RTAVFS_REG17__RTAVFSVF2VOLTCODE__SHIFT 0x10 +#define RTAVFS_REG17__RTAVFSVF2FREQCOUNT_MASK 0x0000FFFFL +#define RTAVFS_REG17__RTAVFSVF2VOLTCODE_MASK 0xFFFF0000L +//RTAVFS_REG18 +#define RTAVFS_REG18__RTAVFSVF3FREQCOUNT__SHIFT 0x0 +#define RTAVFS_REG18__RTAVFSVF3VOLTCODE__SHIFT 0x10 +#define RTAVFS_REG18__RTAVFSVF3FREQCOUNT_MASK 0x0000FFFFL +#define RTAVFS_REG18__RTAVFSVF3VOLTCODE_MASK 0xFFFF0000L +//RTAVFS_REG19 +#define RTAVFS_REG19__RTAVFSGB_ZONE0__SHIFT 0x0 +#define RTAVFS_REG19__RTAVFSGB_ZONE1__SHIFT 0x6 +#define RTAVFS_REG19__RTAVFSGB_ZONE2__SHIFT 0xc +#define RTAVFS_REG19__RTAVFSGB_ZONE3__SHIFT 0x12 +#define RTAVFS_REG19__RTAVFSGB_ZONE4__SHIFT 0x19 +#define RTAVFS_REG19__RTAVFSGB_ZONE0_MASK 0x0000003FL +#define RTAVFS_REG19__RTAVFSGB_ZONE1_MASK 0x00000FC0L +#define RTAVFS_REG19__RTAVFSGB_ZONE2_MASK 0x0003F000L +#define RTAVFS_REG19__RTAVFSGB_ZONE3_MASK 0x01FC0000L +#define RTAVFS_REG19__RTAVFSGB_ZONE4_MASK 0xFE000000L +//RTAVFS_REG20 +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0__SHIFT 0x0 +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1__SHIFT 0x2 +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2__SHIFT 0x4 +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3__SHIFT 0x6 +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4__SHIFT 0x8 +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5__SHIFT 0xa +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6__SHIFT 0xc +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7__SHIFT 0xe +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL__SHIFT 0x10 +#define RTAVFS_REG20__RTAVFSZONE0RESERVED__SHIFT 0x12 +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0_MASK 0x00000003L +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1_MASK 0x0000000CL +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2_MASK 0x00000030L +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3_MASK 0x000000C0L +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4_MASK 0x00000300L +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK 0x00000C00L +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6_MASK 0x00003000L +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7_MASK 0x0000C000L +#define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL_MASK 0x00030000L +#define RTAVFS_REG20__RTAVFSZONE0RESERVED_MASK 0xFFFC0000L +//RTAVFS_REG21 +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0__SHIFT 0x0 +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1__SHIFT 0x2 +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2__SHIFT 0x4 +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3__SHIFT 0x6 +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4__SHIFT 0x8 +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5__SHIFT 0xa +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6__SHIFT 0xc +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7__SHIFT 0xe +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL__SHIFT 0x10 +#define RTAVFS_REG21__RTAVFSZONE1RESERVED__SHIFT 0x12 +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0_MASK 0x00000003L +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1_MASK 0x0000000CL +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2_MASK 0x00000030L +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3_MASK 0x000000C0L +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4_MASK 0x00000300L +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5_MASK 0x00000C00L +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6_MASK 0x00003000L +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7_MASK 0x0000C000L +#define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL_MASK 0x00030000L +#define RTAVFS_REG21__RTAVFSZONE1RESERVED_MASK 0xFFFC0000L +//RTAVFS_REG22 +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0__SHIFT 0x0 +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1__SHIFT 0x2 +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2__SHIFT 0x4 +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3__SHIFT 0x6 +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4__SHIFT 0x8 +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5__SHIFT 0xa +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6__SHIFT 0xc +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7__SHIFT 0xe +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL__SHIFT 0x10 +#define RTAVFS_REG22__RTAVFSZONE2RESERVED__SHIFT 0x12 +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0_MASK 0x00000003L +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1_MASK 0x0000000CL +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2_MASK 0x00000030L +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3_MASK 0x000000C0L +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4_MASK 0x00000300L +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5_MASK 0x00000C00L +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6_MASK 0x00003000L +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7_MASK 0x0000C000L +#define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL_MASK 0x00030000L +#define RTAVFS_REG22__RTAVFSZONE2RESERVED_MASK 0xFFFC0000L +//RTAVFS_REG23 +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0__SHIFT 0x0 +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1__SHIFT 0x2 +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2__SHIFT 0x4 +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3__SHIFT 0x6 +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4__SHIFT 0x8 +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5__SHIFT 0xa +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6__SHIFT 0xc +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7__SHIFT 0xe +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL__SHIFT 0x10 +#define RTAVFS_REG23__RTAVFSZONE3RESERVED__SHIFT 0x12 +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0_MASK 0x00000003L +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1_MASK 0x0000000CL +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2_MASK 0x00000030L +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3_MASK 0x000000C0L +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4_MASK 0x00000300L +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5_MASK 0x00000C00L +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6_MASK 0x00003000L +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7_MASK 0x0000C000L +#define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL_MASK 0x00030000L +#define RTAVFS_REG23__RTAVFSZONE3RESERVED_MASK 0xFFFC0000L +//RTAVFS_REG24 +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0__SHIFT 0x0 +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1__SHIFT 0x2 +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2__SHIFT 0x4 +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3__SHIFT 0x6 +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4__SHIFT 0x8 +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT 0xa +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6__SHIFT 0xc +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7__SHIFT 0xe +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL__SHIFT 0x10 +#define RTAVFS_REG24__RTAVFSZONE4RESERVED__SHIFT 0x12 +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0_MASK 0x00000003L +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1_MASK 0x0000000CL +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2_MASK 0x00000030L +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3_MASK 0x000000C0L +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4_MASK 0x00000300L +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5_MASK 0x00000C00L +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6_MASK 0x00003000L +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7_MASK 0x0000C000L +#define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL_MASK 0x00030000L +#define RTAVFS_REG24__RTAVFSZONE4RESERVED_MASK 0xFFFC0000L +//RTAVFS_REG25 +#define RTAVFS_REG25__RTAVFSRESERVED0__SHIFT 0x0 +#define RTAVFS_REG25__RTAVFSRESERVED0_MASK 0xFFFFFFFFL +//RTAVFS_REG26 +#define RTAVFS_REG26__RTAVFSRESERVED1__SHIFT 0x0 +#define RTAVFS_REG26__RTAVFSRESERVED1_MASK 0xFFFFFFFFL +//RTAVFS_REG27 +#define RTAVFS_REG27__RTAVFSRESERVED2__SHIFT 0x0 +#define RTAVFS_REG27__RTAVFSRESERVED2_MASK 0xFFFFFFFFL +//RTAVFS_REG28 +#define RTAVFS_REG28__RTAVFSZONE0INTERCEPT__SHIFT 0x0 +#define RTAVFS_REG28__RTAVFSZONE1INTERCEPT__SHIFT 0x10 +#define RTAVFS_REG28__RTAVFSZONE0INTERCEPT_MASK 0x0000FFFFL +#define RTAVFS_REG28__RTAVFSZONE1INTERCEPT_MASK 0xFFFF0000L +//RTAVFS_REG29 +#define RTAVFS_REG29__RTAVFSZONE2INTERCEPT__SHIFT 0x0 +#define RTAVFS_REG29__RTAVFSZONE3INTERCEPT__SHIFT 0x10 +#define RTAVFS_REG29__RTAVFSZONE2INTERCEPT_MASK 0x0000FFFFL +#define RTAVFS_REG29__RTAVFSZONE3INTERCEPT_MASK 0xFFFF0000L +//RTAVFS_REG30 +#define RTAVFS_REG30__RTAVFSZONE4INTERCEPT__SHIFT 0x0 +#define RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT__SHIFT 0x10 +#define RTAVFS_REG30__RTAVFSZONE4INTERCEPT_MASK 0x0000FFFFL +#define RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT_MASK 0xFFFF0000L +//RTAVFS_REG31 +#define RTAVFS_REG31__RTAVFSCPOCLKDIV0__SHIFT 0x0 +#define RTAVFS_REG31__RTAVFSCPOCLKDIV1__SHIFT 0x2 +#define RTAVFS_REG31__RTAVFSCPOCLKDIV2__SHIFT 0x4 +#define RTAVFS_REG31__RTAVFSCPOCLKDIV3__SHIFT 0x6 +#define RTAVFS_REG31__RTAVFSCPOCLKDIV4__SHIFT 0x8 +#define RTAVFS_REG31__RTAVFSCPOCLKDIV5__SHIFT 0xa +#define RTAVFS_REG31__RTAVFSCPOCLKDIV6__SHIFT 0xc +#define RTAVFS_REG31__RTAVFSCPOCLKDIV7__SHIFT 0xe +#define RTAVFS_REG31__RESERVED__SHIFT 0x10 +#define RTAVFS_REG31__RTAVFSCPOCLKDIV0_MASK 0x00000003L +#define RTAVFS_REG31__RTAVFSCPOCLKDIV1_MASK 0x0000000CL +#define RTAVFS_REG31__RTAVFSCPOCLKDIV2_MASK 0x00000030L +#define RTAVFS_REG31__RTAVFSCPOCLKDIV3_MASK 0x000000C0L +#define RTAVFS_REG31__RTAVFSCPOCLKDIV4_MASK 0x00000300L +#define RTAVFS_REG31__RTAVFSCPOCLKDIV5_MASK 0x00000C00L +#define RTAVFS_REG31__RTAVFSCPOCLKDIV6_MASK 0x00003000L +#define RTAVFS_REG31__RTAVFSCPOCLKDIV7_MASK 0x0000C000L +#define RTAVFS_REG31__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG32 +#define RTAVFS_REG32__RTAVFSFSMSTARTUPCNT__SHIFT 0x0 +#define RTAVFS_REG32__RESERVED__SHIFT 0x10 +#define RTAVFS_REG32__RTAVFSFSMSTARTUPCNT_MASK 0x0000FFFFL +#define RTAVFS_REG32__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG33 +#define RTAVFS_REG33__RTAVFSFSMIDLECNT__SHIFT 0x0 +#define RTAVFS_REG33__RESERVED__SHIFT 0x10 +#define RTAVFS_REG33__RTAVFSFSMIDLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG33__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG34 +#define RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT__SHIFT 0x0 +#define RTAVFS_REG34__RESERVED__SHIFT 0x10 +#define RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT_MASK 0x0000FFFFL +#define RTAVFS_REG34__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG35 +#define RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT__SHIFT 0x0 +#define RTAVFS_REG35__RESERVED__SHIFT 0x10 +#define RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT_MASK 0x0000FFFFL +#define RTAVFS_REG35__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG36 +#define RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT__SHIFT 0x0 +#define RTAVFS_REG36__RESERVED__SHIFT 0x10 +#define RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT_MASK 0x0000FFFFL +#define RTAVFS_REG36__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG37 +#define RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT__SHIFT 0x0 +#define RTAVFS_REG37__RESERVED__SHIFT 0x10 +#define RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT_MASK 0x0000FFFFL +#define RTAVFS_REG37__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG38 +#define RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT__SHIFT 0x0 +#define RTAVFS_REG38__RESERVED__SHIFT 0x10 +#define RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT_MASK 0x0000FFFFL +#define RTAVFS_REG38__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG39 +#define RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT__SHIFT 0x0 +#define RTAVFS_REG39__RESERVED__SHIFT 0x10 +#define RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT_MASK 0x0000FFFFL +#define RTAVFS_REG39__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG40 +#define RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT__SHIFT 0x0 +#define RTAVFS_REG40__RESERVED__SHIFT 0x10 +#define RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT_MASK 0x0000FFFFL +#define RTAVFS_REG40__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG41 +#define RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT__SHIFT 0x0 +#define RTAVFS_REG41__RESERVED__SHIFT 0x10 +#define RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT_MASK 0x0000FFFFL +#define RTAVFS_REG41__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG42 +#define RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT__SHIFT 0x0 +#define RTAVFS_REG42__RESERVED__SHIFT 0x10 +#define RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT_MASK 0x0000FFFFL +#define RTAVFS_REG42__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG43 +#define RTAVFS_REG43__RTAVFSKP0__SHIFT 0x0 +#define RTAVFS_REG43__RTAVFSKP1__SHIFT 0x4 +#define RTAVFS_REG43__RTAVFSKP2__SHIFT 0x8 +#define RTAVFS_REG43__RTAVFSKP3__SHIFT 0xc +#define RTAVFS_REG43__RTAVFSKI0__SHIFT 0x10 +#define RTAVFS_REG43__RTAVFSKI1__SHIFT 0x14 +#define RTAVFS_REG43__RTAVFSKI2__SHIFT 0x18 +#define RTAVFS_REG43__RTAVFSKI3__SHIFT 0x1c +#define RTAVFS_REG43__RTAVFSKP0_MASK 0x0000000FL +#define RTAVFS_REG43__RTAVFSKP1_MASK 0x000000F0L +#define RTAVFS_REG43__RTAVFSKP2_MASK 0x00000F00L +#define RTAVFS_REG43__RTAVFSKP3_MASK 0x0000F000L +#define RTAVFS_REG43__RTAVFSKI0_MASK 0x000F0000L +#define RTAVFS_REG43__RTAVFSKI1_MASK 0x00F00000L +#define RTAVFS_REG43__RTAVFSKI2_MASK 0x0F000000L +#define RTAVFS_REG43__RTAVFSKI3_MASK 0xF0000000L +//RTAVFS_REG44 +#define RTAVFS_REG44__RTAVFSV1__SHIFT 0x0 +#define RTAVFS_REG44__RTAVFSV2__SHIFT 0xa +#define RTAVFS_REG44__RTAVFSV3__SHIFT 0x14 +#define RTAVFS_REG44__RTAVFSUSEBINARYSEARCH__SHIFT 0x1e +#define RTAVFS_REG44__RTAVFSVOLTCODEHWCAL__SHIFT 0x1f +#define RTAVFS_REG44__RTAVFSV1_MASK 0x000003FFL +#define RTAVFS_REG44__RTAVFSV2_MASK 0x000FFC00L +#define RTAVFS_REG44__RTAVFSV3_MASK 0x3FF00000L +#define RTAVFS_REG44__RTAVFSUSEBINARYSEARCH_MASK 0x40000000L +#define RTAVFS_REG44__RTAVFSVOLTCODEHWCAL_MASK 0x80000000L +//RTAVFS_REG45 +#define RTAVFS_REG45__RTAVFSVRBLEEDCNTRL__SHIFT 0x0 +#define RTAVFS_REG45__RTAVFSVRENABLE__SHIFT 0x1 +#define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE__SHIFT 0x2 +#define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL__SHIFT 0xc +#define RTAVFS_REG45__RTAVFSLOWPWREN__SHIFT 0xd +#define RTAVFS_REG45__RTAVFSUREGENABLE__SHIFT 0xe +#define RTAVFS_REG45__RTAVFSBGENABLE__SHIFT 0xf +#define RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING__SHIFT 0x10 +#define RTAVFS_REG45__RESERVED__SHIFT 0x11 +#define RTAVFS_REG45__RTAVFSVRBLEEDCNTRL_MASK 0x00000001L +#define RTAVFS_REG45__RTAVFSVRENABLE_MASK 0x00000002L +#define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE_MASK 0x00000FFCL +#define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL_MASK 0x00001000L +#define RTAVFS_REG45__RTAVFSLOWPWREN_MASK 0x00002000L +#define RTAVFS_REG45__RTAVFSUREGENABLE_MASK 0x00004000L +#define RTAVFS_REG45__RTAVFSBGENABLE_MASK 0x00008000L +#define RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING_MASK 0x00010000L +#define RTAVFS_REG45__RESERVED_MASK 0xFFFE0000L +//RTAVFS_REG46 +#define RTAVFS_REG46__RTAVFSKP__SHIFT 0x0 +#define RTAVFS_REG46__RTAVFSKI__SHIFT 0x4 +#define RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP__SHIFT 0x8 +#define RTAVFS_REG46__RTAVFSPISHIFT__SHIFT 0x9 +#define RTAVFS_REG46__RTAVFSPIERREN__SHIFT 0xd +#define RTAVFS_REG46__RTAVFSPISHIFTOUT__SHIFT 0xe +#define RTAVFS_REG46__RTAVFSUSELUTKPKI__SHIFT 0x12 +#define RTAVFS_REG46__RESERVED__SHIFT 0x13 +#define RTAVFS_REG46__RTAVFSKP_MASK 0x0000000FL +#define RTAVFS_REG46__RTAVFSKI_MASK 0x000000F0L +#define RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP_MASK 0x00000100L +#define RTAVFS_REG46__RTAVFSPISHIFT_MASK 0x00001E00L +#define RTAVFS_REG46__RTAVFSPIERREN_MASK 0x00002000L +#define RTAVFS_REG46__RTAVFSPISHIFTOUT_MASK 0x0003C000L +#define RTAVFS_REG46__RTAVFSUSELUTKPKI_MASK 0x00040000L +#define RTAVFS_REG46__RESERVED_MASK 0xFFF80000L +//RTAVFS_REG47 +#define RTAVFS_REG47__RTAVFSVOLTCODEPIMIN__SHIFT 0x0 +#define RTAVFS_REG47__RTAVFSVOLTCODEPIMAX__SHIFT 0xa +#define RTAVFS_REG47__RTAVFSPIERRMASK__SHIFT 0x14 +#define RTAVFS_REG47__RTAVFSFORCEDISABLEPI__SHIFT 0x1b +#define RTAVFS_REG47__RESERVED__SHIFT 0x1c +#define RTAVFS_REG47__RTAVFSVOLTCODEPIMIN_MASK 0x000003FFL +#define RTAVFS_REG47__RTAVFSVOLTCODEPIMAX_MASK 0x000FFC00L +#define RTAVFS_REG47__RTAVFSPIERRMASK_MASK 0x07F00000L +#define RTAVFS_REG47__RTAVFSFORCEDISABLEPI_MASK 0x08000000L +#define RTAVFS_REG47__RESERVED_MASK 0xF0000000L +//RTAVFS_REG48 +#define RTAVFS_REG48__RTAVFSPILOOPNITERATIONS__SHIFT 0x0 +#define RTAVFS_REG48__RTAVFSPIERRTHRESHOLD__SHIFT 0x10 +#define RTAVFS_REG48__RTAVFSPILOOPNITERATIONS_MASK 0x0000FFFFL +#define RTAVFS_REG48__RTAVFSPIERRTHRESHOLD_MASK 0xFFFF0000L +//RTAVFS_REG49 +#define RTAVFS_REG49__RTAVFSPSMRSTAVGVDD__SHIFT 0x0 +#define RTAVFS_REG49__RTAVFSPSMMEASMAXVDD__SHIFT 0x1 +#define RTAVFS_REG49__RTAVFSPSMCLKDIVVDD__SHIFT 0x2 +#define RTAVFS_REG49__RTAVFSPSMAVGDIVVDD__SHIFT 0x4 +#define RTAVFS_REG49__RTAVFSPSMOSCENVDD__SHIFT 0xa +#define RTAVFS_REG49__RTAVFSPSMAVGENVDD__SHIFT 0xb +#define RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD__SHIFT 0xc +#define RTAVFS_REG49__RESERVED__SHIFT 0xd +#define RTAVFS_REG49__RTAVFSPSMRSTAVGVDD_MASK 0x00000001L +#define RTAVFS_REG49__RTAVFSPSMMEASMAXVDD_MASK 0x00000002L +#define RTAVFS_REG49__RTAVFSPSMCLKDIVVDD_MASK 0x0000000CL +#define RTAVFS_REG49__RTAVFSPSMAVGDIVVDD_MASK 0x000003F0L +#define RTAVFS_REG49__RTAVFSPSMOSCENVDD_MASK 0x00000400L +#define RTAVFS_REG49__RTAVFSPSMAVGENVDD_MASK 0x00000800L +#define RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD_MASK 0x00001000L +#define RTAVFS_REG49__RESERVED_MASK 0xFFFFE000L +//RTAVFS_REG50 +#define RTAVFS_REG50__RTAVFSPSMRSTAVGVREG__SHIFT 0x0 +#define RTAVFS_REG50__RTAVFSPSMMEASMAXVREG__SHIFT 0x1 +#define RTAVFS_REG50__RTAVFSPSMCLKDIVVREG__SHIFT 0x2 +#define RTAVFS_REG50__RTAVFSPSMAVGDIVVREG__SHIFT 0x4 +#define RTAVFS_REG50__RTAVFSPSMOSCENVREG__SHIFT 0xa +#define RTAVFS_REG50__RTAVFSPSMAVGENVREG__SHIFT 0xb +#define RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG__SHIFT 0xc +#define RTAVFS_REG50__RESERVED__SHIFT 0xd +#define RTAVFS_REG50__RTAVFSPSMRSTAVGVREG_MASK 0x00000001L +#define RTAVFS_REG50__RTAVFSPSMMEASMAXVREG_MASK 0x00000002L +#define RTAVFS_REG50__RTAVFSPSMCLKDIVVREG_MASK 0x0000000CL +#define RTAVFS_REG50__RTAVFSPSMAVGDIVVREG_MASK 0x000003F0L +#define RTAVFS_REG50__RTAVFSPSMOSCENVREG_MASK 0x00000400L +#define RTAVFS_REG50__RTAVFSPSMAVGENVREG_MASK 0x00000800L +#define RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG_MASK 0x00001000L +#define RTAVFS_REG50__RESERVED_MASK 0xFFFFE000L +//RTAVFS_REG51 +#define RTAVFS_REG51__RTAVFSAVFSENABLE__SHIFT 0x0 +#define RTAVFS_REG51__RTAVFSCPOTURNONDELAY__SHIFT 0x1 +#define RTAVFS_REG51__RTAVFSSELECTMINMAX__SHIFT 0x5 +#define RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING__SHIFT 0x6 +#define RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND__SHIFT 0x7 +#define RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT__SHIFT 0x8 +#define RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES__SHIFT 0x9 +#define RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT__SHIFT 0xa +#define RTAVFS_REG51__RESERVED__SHIFT 0xb +#define RTAVFS_REG51__RTAVFSAVFSENABLE_MASK 0x00000001L +#define RTAVFS_REG51__RTAVFSCPOTURNONDELAY_MASK 0x0000001EL +#define RTAVFS_REG51__RTAVFSSELECTMINMAX_MASK 0x00000020L +#define RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING_MASK 0x00000040L +#define RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND_MASK 0x00000080L +#define RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT_MASK 0x00000100L +#define RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES_MASK 0x00000200L +#define RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT_MASK 0x00000400L +#define RTAVFS_REG51__RESERVED_MASK 0xFFFFF800L +//RTAVFS_REG52 +#define RTAVFS_REG52__RTAVFSMINMAXPSMVDD__SHIFT 0x0 +#define RTAVFS_REG52__RTAVFSAVGPSMVDD__SHIFT 0xe +#define RTAVFS_REG52__RESERVED__SHIFT 0x1c +#define RTAVFS_REG52__RTAVFSMINMAXPSMVDD_MASK 0x00003FFFL +#define RTAVFS_REG52__RTAVFSAVGPSMVDD_MASK 0x0FFFC000L +#define RTAVFS_REG52__RESERVED_MASK 0xF0000000L +//RTAVFS_REG53 +#define RTAVFS_REG53__RTAVFSMINMAXPSMVREG__SHIFT 0x0 +#define RTAVFS_REG53__RTAVFSAVGPSMVREG__SHIFT 0xe +#define RTAVFS_REG53__RESERVED__SHIFT 0x1c +#define RTAVFS_REG53__RTAVFSMINMAXPSMVREG_MASK 0x00003FFFL +#define RTAVFS_REG53__RTAVFSAVGPSMVREG_MASK 0x0FFFC000L +#define RTAVFS_REG53__RESERVED_MASK 0xF0000000L +//RTAVFS_REG54 +#define RTAVFS_REG54__RTAVFSCPO0_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG54__RTAVFSCPO0_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG54__RTAVFSCPO0_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG54__RTAVFSCPO0_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG55 +#define RTAVFS_REG55__RTAVFSCPO1_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG55__RTAVFSCPO1_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG55__RTAVFSCPO1_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG55__RTAVFSCPO1_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG56 +#define RTAVFS_REG56__RTAVFSCPO2_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG56__RTAVFSCPO2_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG56__RTAVFSCPO2_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG56__RTAVFSCPO2_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG57 +#define RTAVFS_REG57__RTAVFSCPO3_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG57__RTAVFSCPO3_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG57__RTAVFSCPO3_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG57__RTAVFSCPO3_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG58 +#define RTAVFS_REG58__RTAVFSCPO4_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG58__RTAVFSCPO4_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG58__RTAVFSCPO4_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG58__RTAVFSCPO4_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG59 +#define RTAVFS_REG59__RTAVFSCPO5_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG59__RTAVFSCPO5_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG59__RTAVFSCPO5_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG59__RTAVFSCPO5_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG60 +#define RTAVFS_REG60__RTAVFSCPO6_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG60__RTAVFSCPO6_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG60__RTAVFSCPO6_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG60__RTAVFSCPO6_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG61 +#define RTAVFS_REG61__RTAVFSCPO7_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG61__RTAVFSCPO7_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG61__RTAVFSCPO7_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG61__RTAVFSCPO7_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG62 +#define RTAVFS_REG62__RTAVFSCPO8_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG62__RTAVFSCPO8_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG62__RTAVFSCPO8_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG62__RTAVFSCPO8_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG63 +#define RTAVFS_REG63__RTAVFSCPO9_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG63__RTAVFSCPO9_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG63__RTAVFSCPO9_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG63__RTAVFSCPO9_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG64 +#define RTAVFS_REG64__RTAVFSCPO10_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG64__RTAVFSCPO10_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG64__RTAVFSCPO10_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG64__RTAVFSCPO10_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG65 +#define RTAVFS_REG65__RTAVFSCPO11_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG65__RTAVFSCPO11_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG65__RTAVFSCPO11_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG65__RTAVFSCPO11_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG66 +#define RTAVFS_REG66__RTAVFSCPO12_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG66__RTAVFSCPO12_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG66__RTAVFSCPO12_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG66__RTAVFSCPO12_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG67 +#define RTAVFS_REG67__RTAVFSCPO13_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG67__RTAVFSCPO13_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG67__RTAVFSCPO13_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG67__RTAVFSCPO13_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG68 +#define RTAVFS_REG68__RTAVFSCPO14_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG68__RTAVFSCPO14_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG68__RTAVFSCPO14_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG68__RTAVFSCPO14_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG69 +#define RTAVFS_REG69__RTAVFSCPO15_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG69__RTAVFSCPO15_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG69__RTAVFSCPO15_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG69__RTAVFSCPO15_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG70 +#define RTAVFS_REG70__RTAVFSCPO16_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG70__RTAVFSCPO16_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG70__RTAVFSCPO16_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG70__RTAVFSCPO16_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG71 +#define RTAVFS_REG71__RTAVFSCPO17_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG71__RTAVFSCPO17_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG71__RTAVFSCPO17_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG71__RTAVFSCPO17_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG72 +#define RTAVFS_REG72__RTAVFSCPO18_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG72__RTAVFSCPO18_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG72__RTAVFSCPO18_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG72__RTAVFSCPO18_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG73 +#define RTAVFS_REG73__RTAVFSCPO19_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG73__RTAVFSCPO19_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG73__RTAVFSCPO19_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG73__RTAVFSCPO19_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG74 +#define RTAVFS_REG74__RTAVFSCPO20_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG74__RTAVFSCPO20_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG74__RTAVFSCPO20_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG74__RTAVFSCPO20_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG75 +#define RTAVFS_REG75__RTAVFSCPO21_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG75__RTAVFSCPO21_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG75__RTAVFSCPO21_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG75__RTAVFSCPO21_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG76 +#define RTAVFS_REG76__RTAVFSCPO22_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG76__RTAVFSCPO22_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG76__RTAVFSCPO22_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG76__RTAVFSCPO22_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG77 +#define RTAVFS_REG77__RTAVFSCPO23_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG77__RTAVFSCPO23_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG77__RTAVFSCPO23_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG77__RTAVFSCPO23_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG78 +#define RTAVFS_REG78__RTAVFSCPO24_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG78__RTAVFSCPO24_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG78__RTAVFSCPO24_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG78__RTAVFSCPO24_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG79 +#define RTAVFS_REG79__RTAVFSCPO25_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG79__RTAVFSCPO25_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG79__RTAVFSCPO25_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG79__RTAVFSCPO25_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG80 +#define RTAVFS_REG80__RTAVFSCPO26_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG80__RTAVFSCPO26_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG80__RTAVFSCPO26_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG80__RTAVFSCPO26_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG81 +#define RTAVFS_REG81__RTAVFSCPO27_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG81__RTAVFSCPO27_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG81__RTAVFSCPO27_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG81__RTAVFSCPO27_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG82 +#define RTAVFS_REG82__RTAVFSCPO28_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG82__RTAVFSCPO28_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG82__RTAVFSCPO28_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG82__RTAVFSCPO28_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG83 +#define RTAVFS_REG83__RTAVFSCPO29_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG83__RTAVFSCPO29_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG83__RTAVFSCPO29_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG83__RTAVFSCPO29_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG84 +#define RTAVFS_REG84__RTAVFSCPO30_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG84__RTAVFSCPO30_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG84__RTAVFSCPO30_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG84__RTAVFSCPO30_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG85 +#define RTAVFS_REG85__RTAVFSCPO31_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG85__RTAVFSCPO31_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG85__RTAVFSCPO31_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG85__RTAVFSCPO31_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG86 +#define RTAVFS_REG86__RTAVFSCPO32_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG86__RTAVFSCPO32_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG86__RTAVFSCPO32_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG86__RTAVFSCPO32_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG87 +#define RTAVFS_REG87__RTAVFSCPO33_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG87__RTAVFSCPO33_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG87__RTAVFSCPO33_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG87__RTAVFSCPO33_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG88 +#define RTAVFS_REG88__RTAVFSCPO34_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG88__RTAVFSCPO34_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG88__RTAVFSCPO34_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG88__RTAVFSCPO34_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG89 +#define RTAVFS_REG89__RTAVFSCPO35_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG89__RTAVFSCPO35_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG89__RTAVFSCPO35_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG89__RTAVFSCPO35_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG90 +#define RTAVFS_REG90__RTAVFSCPO36_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG90__RTAVFSCPO36_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG90__RTAVFSCPO36_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG90__RTAVFSCPO36_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG91 +#define RTAVFS_REG91__RTAVFSCPO37_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG91__RTAVFSCPO37_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG91__RTAVFSCPO37_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG91__RTAVFSCPO37_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG92 +#define RTAVFS_REG92__RTAVFSCPO38_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG92__RTAVFSCPO38_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG92__RTAVFSCPO38_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG92__RTAVFSCPO38_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG93 +#define RTAVFS_REG93__RTAVFSCPO39_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG93__RTAVFSCPO39_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG93__RTAVFSCPO39_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG93__RTAVFSCPO39_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG94 +#define RTAVFS_REG94__RTAVFSCPO40_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG94__RTAVFSCPO40_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG94__RTAVFSCPO40_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG94__RTAVFSCPO40_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG95 +#define RTAVFS_REG95__RTAVFSCPO41_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG95__RTAVFSCPO41_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG95__RTAVFSCPO41_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG95__RTAVFSCPO41_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG96 +#define RTAVFS_REG96__RTAVFSCPO42_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG96__RTAVFSCPO42_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG96__RTAVFSCPO42_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG96__RTAVFSCPO42_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG97 +#define RTAVFS_REG97__RTAVFSCPO43_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG97__RTAVFSCPO43_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG97__RTAVFSCPO43_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG97__RTAVFSCPO43_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG98 +#define RTAVFS_REG98__RTAVFSCPO44_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG98__RTAVFSCPO44_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG98__RTAVFSCPO44_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG98__RTAVFSCPO44_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG99 +#define RTAVFS_REG99__RTAVFSCPO45_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG99__RTAVFSCPO45_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG99__RTAVFSCPO45_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG99__RTAVFSCPO45_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG100 +#define RTAVFS_REG100__RTAVFSCPO46_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG100__RTAVFSCPO46_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG100__RTAVFSCPO46_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG100__RTAVFSCPO46_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG101 +#define RTAVFS_REG101__RTAVFSCPO47_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG101__RTAVFSCPO47_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG101__RTAVFSCPO47_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG101__RTAVFSCPO47_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG102 +#define RTAVFS_REG102__RTAVFSCPO48_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG102__RTAVFSCPO48_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG102__RTAVFSCPO48_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG102__RTAVFSCPO48_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG103 +#define RTAVFS_REG103__RTAVFSCPO49_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG103__RTAVFSCPO49_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG103__RTAVFSCPO49_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG103__RTAVFSCPO49_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG104 +#define RTAVFS_REG104__RTAVFSCPO50_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG104__RTAVFSCPO50_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG104__RTAVFSCPO50_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG104__RTAVFSCPO50_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG105 +#define RTAVFS_REG105__RTAVFSCPO51_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG105__RTAVFSCPO51_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG105__RTAVFSCPO51_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG105__RTAVFSCPO51_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG106 +#define RTAVFS_REG106__RTAVFSCPO52_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG106__RTAVFSCPO52_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG106__RTAVFSCPO52_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG106__RTAVFSCPO52_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG107 +#define RTAVFS_REG107__RTAVFSCPO53_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG107__RTAVFSCPO53_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG107__RTAVFSCPO53_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG107__RTAVFSCPO53_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG108 +#define RTAVFS_REG108__RTAVFSCPO54_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG108__RTAVFSCPO54_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG108__RTAVFSCPO54_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG108__RTAVFSCPO54_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG109 +#define RTAVFS_REG109__RTAVFSCPO55_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG109__RTAVFSCPO55_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG109__RTAVFSCPO55_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG109__RTAVFSCPO55_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG110 +#define RTAVFS_REG110__RTAVFSCPO56_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG110__RTAVFSCPO56_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG110__RTAVFSCPO56_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG110__RTAVFSCPO56_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG111 +#define RTAVFS_REG111__RTAVFSCPO57_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG111__RTAVFSCPO57_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG111__RTAVFSCPO57_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG111__RTAVFSCPO57_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG112 +#define RTAVFS_REG112__RTAVFSCPO58_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG112__RTAVFSCPO58_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG112__RTAVFSCPO58_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG112__RTAVFSCPO58_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG113 +#define RTAVFS_REG113__RTAVFSCPO59_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG113__RTAVFSCPO59_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG113__RTAVFSCPO59_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG113__RTAVFSCPO59_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG114 +#define RTAVFS_REG114__RTAVFSCPO60_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG114__RTAVFSCPO60_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG114__RTAVFSCPO60_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG114__RTAVFSCPO60_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG115 +#define RTAVFS_REG115__RTAVFSCPO61_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG115__RTAVFSCPO61_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG115__RTAVFSCPO61_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG115__RTAVFSCPO61_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG116 +#define RTAVFS_REG116__RTAVFSCPO62_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG116__RTAVFSCPO62_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG116__RTAVFSCPO62_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG116__RTAVFSCPO62_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG117 +#define RTAVFS_REG117__RTAVFSCPO63_STARTCNT__SHIFT 0x0 +#define RTAVFS_REG117__RTAVFSCPO63_STOPCNT__SHIFT 0x10 +#define RTAVFS_REG117__RTAVFSCPO63_STARTCNT_MASK 0x0000FFFFL +#define RTAVFS_REG117__RTAVFSCPO63_STOPCNT_MASK 0xFFFF0000L +//RTAVFS_REG118 +#define RTAVFS_REG118__RTAVFSCPOEN0__SHIFT 0x0 +#define RTAVFS_REG118__RTAVFSCPOEN0_MASK 0xFFFFFFFFL +//RTAVFS_REG119 +#define RTAVFS_REG119__RTAVFSCPOEN1__SHIFT 0x0 +#define RTAVFS_REG119__RTAVFSCPOEN1_MASK 0xFFFFFFFFL +//RTAVFS_REG120 +#define RTAVFS_REG120__RTAVFSCPOAVGDIV0__SHIFT 0x0 +#define RTAVFS_REG120__RTAVFSCPOAVGDIV1__SHIFT 0x2 +#define RTAVFS_REG120__RTAVFSCPOAVGDIV2__SHIFT 0x4 +#define RTAVFS_REG120__RTAVFSCPOAVGDIV3__SHIFT 0x6 +#define RTAVFS_REG120__RTAVFSCPOAVGDIV4__SHIFT 0x8 +#define RTAVFS_REG120__RTAVFSCPOAVGDIV5__SHIFT 0xa +#define RTAVFS_REG120__RTAVFSCPOAVGDIV6__SHIFT 0xc +#define RTAVFS_REG120__RTAVFSCPOAVGDIV7__SHIFT 0xe +#define RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL__SHIFT 0x10 +#define RTAVFS_REG120__RESERVED__SHIFT 0x12 +#define RTAVFS_REG120__RTAVFSCPOAVGDIV0_MASK 0x00000003L +#define RTAVFS_REG120__RTAVFSCPOAVGDIV1_MASK 0x0000000CL +#define RTAVFS_REG120__RTAVFSCPOAVGDIV2_MASK 0x00000030L +#define RTAVFS_REG120__RTAVFSCPOAVGDIV3_MASK 0x000000C0L +#define RTAVFS_REG120__RTAVFSCPOAVGDIV4_MASK 0x00000300L +#define RTAVFS_REG120__RTAVFSCPOAVGDIV5_MASK 0x00000C00L +#define RTAVFS_REG120__RTAVFSCPOAVGDIV6_MASK 0x00003000L +#define RTAVFS_REG120__RTAVFSCPOAVGDIV7_MASK 0x0000C000L +#define RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL_MASK 0x00030000L +#define RTAVFS_REG120__RESERVED_MASK 0xFFFC0000L +//RTAVFS_REG121 +#define RTAVFS_REG121__RTAVFSZONE0INUSE__SHIFT 0x0 +#define RTAVFS_REG121__RTAVFSZONE1INUSE__SHIFT 0x1 +#define RTAVFS_REG121__RTAVFSZONE2INUSE__SHIFT 0x2 +#define RTAVFS_REG121__RTAVFSZONE3INUSE__SHIFT 0x3 +#define RTAVFS_REG121__RTAVFSZONE4INUSE__SHIFT 0x4 +#define RTAVFS_REG121__RTAVFSRESERVED__SHIFT 0x5 +#define RTAVFS_REG121__RTAVFSERRORCODE__SHIFT 0x1c +#define RTAVFS_REG121__RTAVFSZONE0INUSE_MASK 0x00000001L +#define RTAVFS_REG121__RTAVFSZONE1INUSE_MASK 0x00000002L +#define RTAVFS_REG121__RTAVFSZONE2INUSE_MASK 0x00000004L +#define RTAVFS_REG121__RTAVFSZONE3INUSE_MASK 0x00000008L +#define RTAVFS_REG121__RTAVFSZONE4INUSE_MASK 0x00000010L +#define RTAVFS_REG121__RTAVFSRESERVED_MASK 0x0FFFFFE0L +#define RTAVFS_REG121__RTAVFSERRORCODE_MASK 0xF0000000L +//RTAVFS_REG122 +#define RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG122__RESERVED__SHIFT 0x10 +#define RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG122__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG123 +#define RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG123__RESERVED__SHIFT 0x10 +#define RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG123__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG124 +#define RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG124__RESERVED__SHIFT 0x10 +#define RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG124__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG125 +#define RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG125__RESERVED__SHIFT 0x10 +#define RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG125__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG126 +#define RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG126__RESERVED__SHIFT 0x10 +#define RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG126__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG127 +#define RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG127__RESERVED__SHIFT 0x10 +#define RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG127__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG128 +#define RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG128__RESERVED__SHIFT 0x10 +#define RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG128__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG129 +#define RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG129__RESERVED__SHIFT 0x10 +#define RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG129__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG130 +#define RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG130__RESERVED__SHIFT 0x10 +#define RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG130__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG131 +#define RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG131__RESERVED__SHIFT 0x10 +#define RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG131__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG132 +#define RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG132__RESERVED__SHIFT 0x10 +#define RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG132__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG133 +#define RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG133__RESERVED__SHIFT 0x10 +#define RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG133__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG134 +#define RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG134__RESERVED__SHIFT 0x10 +#define RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG134__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG135 +#define RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG135__RESERVED__SHIFT 0x10 +#define RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG135__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG136 +#define RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG136__RESERVED__SHIFT 0x10 +#define RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG136__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG137 +#define RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG137__RESERVED__SHIFT 0x10 +#define RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG137__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG138 +#define RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG138__RESERVED__SHIFT 0x10 +#define RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG138__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG139 +#define RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG139__RESERVED__SHIFT 0x10 +#define RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG139__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG140 +#define RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG140__RESERVED__SHIFT 0x10 +#define RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG140__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG141 +#define RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG141__RESERVED__SHIFT 0x10 +#define RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG141__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG142 +#define RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG142__RESERVED__SHIFT 0x10 +#define RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG142__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG143 +#define RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG143__RESERVED__SHIFT 0x10 +#define RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG143__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG144 +#define RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG144__RESERVED__SHIFT 0x10 +#define RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG144__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG145 +#define RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG145__RESERVED__SHIFT 0x10 +#define RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG145__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG146 +#define RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG146__RESERVED__SHIFT 0x10 +#define RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG146__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG147 +#define RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG147__RESERVED__SHIFT 0x10 +#define RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG147__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG148 +#define RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG148__RESERVED__SHIFT 0x10 +#define RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG148__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG149 +#define RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG149__RESERVED__SHIFT 0x10 +#define RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG149__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG150 +#define RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG150__RESERVED__SHIFT 0x10 +#define RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG150__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG151 +#define RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG151__RESERVED__SHIFT 0x10 +#define RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG151__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG152 +#define RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG152__RESERVED__SHIFT 0x10 +#define RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG152__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG153 +#define RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG153__RESERVED__SHIFT 0x10 +#define RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG153__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG154 +#define RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG154__RESERVED__SHIFT 0x10 +#define RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG154__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG155 +#define RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG155__RESERVED__SHIFT 0x10 +#define RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG155__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG156 +#define RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG156__RESERVED__SHIFT 0x10 +#define RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG156__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG157 +#define RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG157__RESERVED__SHIFT 0x10 +#define RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG157__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG158 +#define RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG158__RESERVED__SHIFT 0x10 +#define RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG158__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG159 +#define RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG159__RESERVED__SHIFT 0x10 +#define RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG159__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG160 +#define RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG160__RESERVED__SHIFT 0x10 +#define RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG160__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG161 +#define RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG161__RESERVED__SHIFT 0x10 +#define RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG161__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG162 +#define RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG162__RESERVED__SHIFT 0x10 +#define RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG162__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG163 +#define RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG163__RESERVED__SHIFT 0x10 +#define RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG163__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG164 +#define RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG164__RESERVED__SHIFT 0x10 +#define RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG164__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG165 +#define RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG165__RESERVED__SHIFT 0x10 +#define RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG165__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG166 +#define RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG166__RESERVED__SHIFT 0x10 +#define RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG166__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG167 +#define RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG167__RESERVED__SHIFT 0x10 +#define RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG167__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG168 +#define RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG168__RESERVED__SHIFT 0x10 +#define RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG168__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG169 +#define RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG169__RESERVED__SHIFT 0x10 +#define RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG169__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG170 +#define RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG170__RESERVED__SHIFT 0x10 +#define RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG170__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG171 +#define RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG171__RESERVED__SHIFT 0x10 +#define RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG171__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG172 +#define RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG172__RESERVED__SHIFT 0x10 +#define RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG172__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG173 +#define RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG173__RESERVED__SHIFT 0x10 +#define RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG173__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG174 +#define RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG174__RESERVED__SHIFT 0x10 +#define RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG174__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG175 +#define RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG175__RESERVED__SHIFT 0x10 +#define RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG175__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG176 +#define RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG176__RESERVED__SHIFT 0x10 +#define RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG176__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG177 +#define RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG177__RESERVED__SHIFT 0x10 +#define RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG177__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG178 +#define RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG178__RESERVED__SHIFT 0x10 +#define RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG178__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG179 +#define RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG179__RESERVED__SHIFT 0x10 +#define RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG179__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG180 +#define RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG180__RESERVED__SHIFT 0x10 +#define RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG180__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG181 +#define RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG181__RESERVED__SHIFT 0x10 +#define RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG181__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG182 +#define RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG182__RESERVED__SHIFT 0x10 +#define RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG182__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG183 +#define RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG183__RESERVED__SHIFT 0x10 +#define RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG183__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG184 +#define RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG184__RESERVED__SHIFT 0x10 +#define RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG184__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG185 +#define RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT__SHIFT 0x0 +#define RTAVFS_REG185__RESERVED__SHIFT 0x10 +#define RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT_MASK 0x0000FFFFL +#define RTAVFS_REG185__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG186 +#define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE__SHIFT 0x0 +#define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL__SHIFT 0x10 +#define RTAVFS_REG186__RESERVED__SHIFT 0x11 +#define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE_MASK 0x0000FFFFL +#define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL_MASK 0x00010000L +#define RTAVFS_REG186__RESERVED_MASK 0xFFFE0000L +//RTAVFS_REG187 +#define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE__SHIFT 0x0 +#define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL__SHIFT 0x10 +#define RTAVFS_REG187__RESERVED__SHIFT 0x11 +#define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE_MASK 0x0000FFFFL +#define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL_MASK 0x00010000L +#define RTAVFS_REG187__RESERVED_MASK 0xFFFE0000L +//RTAVFS_REG188 +#define RTAVFS_REG188__RESERVED__SHIFT 0x16 +#define RTAVFS_REG188__RESERVED_MASK 0xFFC00000L +//RTAVFS_REG189 +#define RTAVFS_REG189__RTAVFSVOLTCODEFROMPI__SHIFT 0x0 +#define RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH__SHIFT 0xa +#define RTAVFS_REG189__RTAVFSVDDREGON__SHIFT 0x14 +#define RTAVFS_REG189__RTAVFSVDDABOVEVDDRET__SHIFT 0x15 +#define RTAVFS_REG189__RESERVED__SHIFT 0x16 +#define RTAVFS_REG189__RTAVFSVOLTCODEFROMPI_MASK 0x000003FFL +#define RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH_MASK 0x000FFC00L +#define RTAVFS_REG189__RTAVFSVDDREGON_MASK 0x00100000L +#define RTAVFS_REG189__RTAVFSVDDABOVEVDDRET_MASK 0x00200000L +#define RTAVFS_REG189__RESERVED_MASK 0xFFC00000L +//RTAVFS_REG190 +#define RTAVFS_REG190__RTAVFSIGNORERLCREQ__SHIFT 0x0 +#define RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL__SHIFT 0x1 +#define RTAVFS_REG190__RTAVFSRUNLOOP__SHIFT 0x6 +#define RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS__SHIFT 0x7 +#define RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS__SHIFT 0x8 +#define RTAVFS_REG190__RTAVFSRESETRETENTIONREGS__SHIFT 0x9 +#define RTAVFS_REG190__RESERVED__SHIFT 0xa +#define RTAVFS_REG190__RTAVFSIGNORERLCREQ_MASK 0x00000001L +#define RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL_MASK 0x0000003EL +#define RTAVFS_REG190__RTAVFSRUNLOOP_MASK 0x00000040L +#define RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS_MASK 0x00000080L +#define RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS_MASK 0x00000100L +#define RTAVFS_REG190__RTAVFSRESETRETENTIONREGS_MASK 0x00000200L +#define RTAVFS_REG190__RESERVED_MASK 0xFFFFFC00L +//RTAVFS_REG191 +#define RTAVFS_REG191__RTAVFSSTOPATSTARTUP__SHIFT 0x0 +#define RTAVFS_REG191__RTAVFSSTOPATIDLE__SHIFT 0x1 +#define RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS__SHIFT 0x2 +#define RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS__SHIFT 0x3 +#define RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS__SHIFT 0x4 +#define RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE__SHIFT 0x5 +#define RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY__SHIFT 0x6 +#define RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY__SHIFT 0x7 +#define RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY__SHIFT 0x8 +#define RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS__SHIFT 0x9 +#define RTAVFS_REG191__RTAVFSSTOPATWAITFORACK__SHIFT 0xa +#define RTAVFS_REG191__RESERVED__SHIFT 0xb +#define RTAVFS_REG191__RTAVFSSTOPATSTARTUP_MASK 0x00000001L +#define RTAVFS_REG191__RTAVFSSTOPATIDLE_MASK 0x00000002L +#define RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS_MASK 0x00000004L +#define RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS_MASK 0x00000008L +#define RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS_MASK 0x00000010L +#define RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE_MASK 0x00000020L +#define RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY_MASK 0x00000040L +#define RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY_MASK 0x00000080L +#define RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY_MASK 0x00000100L +#define RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS_MASK 0x00000200L +#define RTAVFS_REG191__RTAVFSSTOPATWAITFORACK_MASK 0x00000400L +#define RTAVFS_REG191__RESERVED_MASK 0xFFFFF800L +//RTAVFS_REG192 +#define RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT__SHIFT 0x0 +#define RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT__SHIFT 0x10 +#define RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT_MASK 0x0000FFFFL +#define RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT_MASK 0xFFFF0000L +//RTAVFS_REG193 +#define RTAVFS_REG193__RTAVFSFSMSTATE__SHIFT 0x0 +#define RTAVFS_REG193__RESERVED__SHIFT 0x10 +#define RTAVFS_REG193__RTAVFSFSMSTATE_MASK 0x0000FFFFL +#define RTAVFS_REG193__RESERVED_MASK 0xFFFF0000L +//RTAVFS_REG194 +#define RTAVFS_REG194__RTAVFSRIPPLECNTREAD__SHIFT 0x0 +#define RTAVFS_REG194__RTAVFSRIPPLECNTREAD_MASK 0xFFFFFFFFL + + +// addressBlock: sqind +//SQ_DEBUG_STS_LOCAL +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0xc +#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0xd +#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0xe +#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0xf +#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x10 +#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x11 +#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x12 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L +#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L +#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L +#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L +#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L +#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L +#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L +#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L +//SQ_DEBUG_CTRL_LOCAL +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL +//SQ_WAVE_ACTIVE +#define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK 0x000FFFFFL +//SQ_WAVE_VALID_AND_IDLE +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0x000FFFFFL +//SQ_WAVE_MODE +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 +#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa +#define SQ_WAVE_MODE__TRAP_AFTER_INST_EN__SHIFT 0xb +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc +#define SQ_WAVE_MODE__WAVE_END__SHIFT 0x15 +#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 +#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1b +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L +#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L +#define SQ_WAVE_MODE__TRAP_AFTER_INST_EN_MASK 0x00000800L +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L +#define SQ_WAVE_MODE__WAVE_END_MASK 0x00200000L +#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L +#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x08000000L +//SQ_WAVE_STATUS +#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 +#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc +#define SQ_WAVE_STATUS__HALT__SHIFT 0xd +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATUS__OREO_CONFLICT__SHIFT 0x16 +#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 +#define SQ_WAVE_STATUS__NO_VGPRS__SHIFT 0x18 +#define SQ_WAVE_STATUS__LDS_PARAM_READY__SHIFT 0x19 +#define SQ_WAVE_STATUS__MUST_GS_ALLOC__SHIFT 0x1a +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b +#define SQ_WAVE_STATUS__IDLE__SHIFT 0x1c +#define SQ_WAVE_STATUS__SCRATCH_EN__SHIFT 0x1d +#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L +#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L +#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK 0x00008000L +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATUS__OREO_CONFLICT_MASK 0x00400000L +#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L +#define SQ_WAVE_STATUS__NO_VGPRS_MASK 0x01000000L +#define SQ_WAVE_STATUS__LDS_PARAM_READY_MASK 0x02000000L +#define SQ_WAVE_STATUS__MUST_GS_ALLOC_MASK 0x04000000L +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L +#define SQ_WAVE_STATUS__IDLE_MASK 0x10000000L +#define SQ_WAVE_STATUS__SCRATCH_EN_MASK 0x20000000L +//SQ_WAVE_TRAPSTS +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 +#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb +#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc +#define SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT 0xf +#define SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT 0x10 +#define SQ_WAVE_TRAPSTS__WAVESTART__SHIFT 0x11 +#define SQ_WAVE_TRAPSTS__WAVE_END__SHIFT 0x12 +#define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT 0x13 +#define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT 0x14 +#define SQ_WAVE_TRAPSTS__UTC_ERROR__SHIFT 0x1c +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL +#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L +#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L +#define SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK 0x00008000L +#define SQ_WAVE_TRAPSTS__HOST_TRAP_MASK 0x00010000L +#define SQ_WAVE_TRAPSTS__WAVESTART_MASK 0x00020000L +#define SQ_WAVE_TRAPSTS__WAVE_END_MASK 0x00040000L +#define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK 0x00080000L +#define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK 0x00100000L +#define SQ_WAVE_TRAPSTS__UTC_ERROR_MASK 0x10000000L +//SQ_WAVE_GPR_ALLOC +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0xc +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x000001FFL +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x000FF000L +//SQ_WAVE_LDS_ALLOC +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT 0x18 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000001FFL +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L +#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK 0x0F000000L +//SQ_WAVE_IB_STS +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x4 +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0xa +#define SQ_WAVE_IB_STS__VS_CNT__SHIFT 0x1a +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000007L +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x000003F0L +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000FC00L +#define SQ_WAVE_IB_STS__VS_CNT_MASK 0xFC000000L +//SQ_WAVE_PC_LO +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_HI +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL +//SQ_WAVE_IB_DBG1 +#define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT 0x18 +#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 +#define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK 0x01000000L +#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L +//SQ_WAVE_FLUSH_IB +#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 +#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL +//SQ_WAVE_FLAT_SCRATCH_LO +#define SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT 0x0 +#define SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_FLAT_SCRATCH_HI +#define SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT 0x0 +#define SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_HW_ID1 +#define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa +#define SQ_WAVE_HW_ID1__SA_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID1__SE_ID__SHIFT 0x12 +#define SQ_WAVE_HW_ID1__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_HW_ID1__WAVE_ID_MASK 0x0000001FL +#define SQ_WAVE_HW_ID1__SIMD_ID_MASK 0x00000300L +#define SQ_WAVE_HW_ID1__WGP_ID_MASK 0x00003C00L +#define SQ_WAVE_HW_ID1__SA_ID_MASK 0x00010000L +#define SQ_WAVE_HW_ID1__SE_ID_MASK 0x001C0000L +#define SQ_WAVE_HW_ID1__DP_RATE_MASK 0xE0000000L +//SQ_WAVE_HW_ID2 +#define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID2__ME_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID2__STATE_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID2__WG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID2__VM_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID2__QUEUE_ID_MASK 0x0000000FL +#define SQ_WAVE_HW_ID2__PIPE_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID2__ME_ID_MASK 0x00000300L +#define SQ_WAVE_HW_ID2__STATE_ID_MASK 0x00007000L +#define SQ_WAVE_HW_ID2__WG_ID_MASK 0x001F0000L +#define SQ_WAVE_HW_ID2__VM_ID_MASK 0x0F000000L +//SQ_WAVE_POPS_PACKER +#define SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT 0x0 +#define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT 0x1 +#define SQ_WAVE_POPS_PACKER__POPS_EN_MASK 0x00000001L +#define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK 0x00000006L +//SQ_WAVE_SCHED_MODE +#define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT 0x0 +#define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK 0x00000003L +//SQ_WAVE_IB_STS2 +#define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT 0x0 +#define SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT 0x8 +#define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0xa +#define SQ_WAVE_IB_STS2__WAVE64__SHIFT 0xb +#define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK 0x00000003L +#define SQ_WAVE_IB_STS2__MEM_ORDER_MASK 0x00000300L +#define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK 0x00000400L +#define SQ_WAVE_IB_STS2__WAVE64_MASK 0x00000800L +//SQ_WAVE_SHADER_CYCLES +#define SQ_WAVE_SHADER_CYCLES__CYCLES__SHIFT 0x0 +#define SQ_WAVE_SHADER_CYCLES__CYCLES_MASK 0x000FFFFFL +//SQ_WAVE_TTMP0 +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP1 +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP3 +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP4 +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP5 +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP6 +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP7 +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP8 +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP9 +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP10 +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP11 +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP12 +#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP13 +#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP14 +#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP15 +#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_M0 +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_LO +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_HI +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL + + + + + + + + + + + + + + + + + + + +#endif diff --git a/extra/amdpci/headers/mmhub_3_0_0_offset.h b/extra/amdpci/headers/mmhub_3_0_0_offset.h new file mode 100644 index 0000000000..88be857ad3 --- /dev/null +++ b/extra/amdpci/headers/mmhub_3_0_0_offset.h @@ -0,0 +1,1529 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_3_0_0_OFFSET_HEADER +#define _mmhub_3_0_0_OFFSET_HEADER + + + +// addressBlock: mmhub_dagbdec +// base address: 0x68000 +#define regDAGB0_RDCLI0 0x0000 +#define regDAGB0_RDCLI0_BASE_IDX 0 +#define regDAGB0_RDCLI1 0x0001 +#define regDAGB0_RDCLI1_BASE_IDX 0 +#define regDAGB0_RDCLI2 0x0002 +#define regDAGB0_RDCLI2_BASE_IDX 0 +#define regDAGB0_RDCLI3 0x0003 +#define regDAGB0_RDCLI3_BASE_IDX 0 +#define regDAGB0_RDCLI4 0x0004 +#define regDAGB0_RDCLI4_BASE_IDX 0 +#define regDAGB0_RDCLI5 0x0005 +#define regDAGB0_RDCLI5_BASE_IDX 0 +#define regDAGB0_RDCLI6 0x0006 +#define regDAGB0_RDCLI6_BASE_IDX 0 +#define regDAGB0_RDCLI7 0x0007 +#define regDAGB0_RDCLI7_BASE_IDX 0 +#define regDAGB0_RDCLI8 0x0008 +#define regDAGB0_RDCLI8_BASE_IDX 0 +#define regDAGB0_RDCLI9 0x0009 +#define regDAGB0_RDCLI9_BASE_IDX 0 +#define regDAGB0_RDCLI10 0x000a +#define regDAGB0_RDCLI10_BASE_IDX 0 +#define regDAGB0_RDCLI11 0x000b +#define regDAGB0_RDCLI11_BASE_IDX 0 +#define regDAGB0_RDCLI12 0x000c +#define regDAGB0_RDCLI12_BASE_IDX 0 +#define regDAGB0_RDCLI13 0x000d +#define regDAGB0_RDCLI13_BASE_IDX 0 +#define regDAGB0_RDCLI14 0x000e +#define regDAGB0_RDCLI14_BASE_IDX 0 +#define regDAGB0_RDCLI15 0x000f +#define regDAGB0_RDCLI15_BASE_IDX 0 +#define regDAGB0_RDCLI16 0x0010 +#define regDAGB0_RDCLI16_BASE_IDX 0 +#define regDAGB0_RDCLI17 0x0011 +#define regDAGB0_RDCLI17_BASE_IDX 0 +#define regDAGB0_RDCLI18 0x0012 +#define regDAGB0_RDCLI18_BASE_IDX 0 +#define regDAGB0_RDCLI19 0x0013 +#define regDAGB0_RDCLI19_BASE_IDX 0 +#define regDAGB0_RDCLI20 0x0014 +#define regDAGB0_RDCLI20_BASE_IDX 0 +#define regDAGB0_RDCLI21 0x0015 +#define regDAGB0_RDCLI21_BASE_IDX 0 +#define regDAGB0_RDCLI22 0x0016 +#define regDAGB0_RDCLI22_BASE_IDX 0 +#define regDAGB0_RDCLI23 0x0017 +#define regDAGB0_RDCLI23_BASE_IDX 0 +#define regDAGB0_RD_CNTL 0x0018 +#define regDAGB0_RD_CNTL_BASE_IDX 0 +#define regDAGB0_RD_IO_CNTL 0x0019 +#define regDAGB0_RD_IO_CNTL_BASE_IDX 0 +#define regDAGB0_RD_GMI_CNTL 0x001a +#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB 0x001b +#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB0_RD_CGTT_CLK_CTRL 0x001c +#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x001d +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001e +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001f +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0020 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0021 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0022 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0023 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB0_RD_VC0_CNTL 0x0024 +#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC1_CNTL 0x0025 +#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC2_CNTL 0x0026 +#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC3_CNTL 0x0027 +#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC4_CNTL 0x0028 +#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC5_CNTL 0x0029 +#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB0_RD_IO_VC_CNTL 0x002a +#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 0 +#define regDAGB0_RD_GMI_VC_CNTL 0x002b +#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 0 +#define regDAGB0_RD_CNTL_MISC 0x002c +#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_RD_TLB_CREDIT 0x002d +#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x002e +#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x002f +#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK_PENDING 0x0030 +#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_GO_PENDING 0x0031 +#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0032 +#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_TLB_PENDING 0x0033 +#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_OARB_PENDING 0x0034 +#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK2ARB_PENDING 0x0035 +#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK2DF_PENDING 0x0036 +#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_OSD_PENDING 0x0037 +#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x0038 +#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE 0x0039 +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 0x003a +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB0_WRCLI0 0x003b +#define regDAGB0_WRCLI0_BASE_IDX 0 +#define regDAGB0_WRCLI1 0x003c +#define regDAGB0_WRCLI1_BASE_IDX 0 +#define regDAGB0_WRCLI2 0x003d +#define regDAGB0_WRCLI2_BASE_IDX 0 +#define regDAGB0_WRCLI3 0x003e +#define regDAGB0_WRCLI3_BASE_IDX 0 +#define regDAGB0_WRCLI4 0x003f +#define regDAGB0_WRCLI4_BASE_IDX 0 +#define regDAGB0_WRCLI5 0x0040 +#define regDAGB0_WRCLI5_BASE_IDX 0 +#define regDAGB0_WRCLI6 0x0041 +#define regDAGB0_WRCLI6_BASE_IDX 0 +#define regDAGB0_WRCLI7 0x0042 +#define regDAGB0_WRCLI7_BASE_IDX 0 +#define regDAGB0_WRCLI8 0x0043 +#define regDAGB0_WRCLI8_BASE_IDX 0 +#define regDAGB0_WRCLI9 0x0044 +#define regDAGB0_WRCLI9_BASE_IDX 0 +#define regDAGB0_WRCLI10 0x0045 +#define regDAGB0_WRCLI10_BASE_IDX 0 +#define regDAGB0_WRCLI11 0x0046 +#define regDAGB0_WRCLI11_BASE_IDX 0 +#define regDAGB0_WRCLI12 0x0047 +#define regDAGB0_WRCLI12_BASE_IDX 0 +#define regDAGB0_WRCLI13 0x0048 +#define regDAGB0_WRCLI13_BASE_IDX 0 +#define regDAGB0_WRCLI14 0x0049 +#define regDAGB0_WRCLI14_BASE_IDX 0 +#define regDAGB0_WRCLI15 0x004a +#define regDAGB0_WRCLI15_BASE_IDX 0 +#define regDAGB0_WRCLI16 0x004b +#define regDAGB0_WRCLI16_BASE_IDX 0 +#define regDAGB0_WRCLI17 0x004c +#define regDAGB0_WRCLI17_BASE_IDX 0 +#define regDAGB0_WRCLI18 0x004d +#define regDAGB0_WRCLI18_BASE_IDX 0 +#define regDAGB0_WRCLI19 0x004e +#define regDAGB0_WRCLI19_BASE_IDX 0 +#define regDAGB0_WRCLI20 0x004f +#define regDAGB0_WRCLI20_BASE_IDX 0 +#define regDAGB0_WRCLI21 0x0050 +#define regDAGB0_WRCLI21_BASE_IDX 0 +#define regDAGB0_WRCLI22 0x0051 +#define regDAGB0_WRCLI22_BASE_IDX 0 +#define regDAGB0_WRCLI23 0x0052 +#define regDAGB0_WRCLI23_BASE_IDX 0 +#define regDAGB0_WR_CNTL 0x0053 +#define regDAGB0_WR_CNTL_BASE_IDX 0 +#define regDAGB0_WR_IO_CNTL 0x0054 +#define regDAGB0_WR_IO_CNTL_BASE_IDX 0 +#define regDAGB0_WR_GMI_CNTL 0x0055 +#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB 0x0056 +#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB0_WR_CGTT_CLK_CTRL 0x0057 +#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0058 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0059 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x005a +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x005b +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x005c +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x005d +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x005e +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB 0x005f +#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0060 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0061 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0062 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0063 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0064 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0065 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB0_WR_VC0_CNTL 0x0066 +#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC1_CNTL 0x0067 +#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC2_CNTL 0x0068 +#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC3_CNTL 0x0069 +#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC4_CNTL 0x006a +#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC5_CNTL 0x006b +#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB0_WR_IO_VC_CNTL 0x006c +#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 0 +#define regDAGB0_WR_GMI_VC_CNTL 0x006d +#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 0 +#define regDAGB0_WR_CNTL_MISC 0x006e +#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_WR_TLB_CREDIT 0x006f +#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_DATA_CREDIT 0x0070 +#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_MISC_CREDIT 0x0071 +#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0072 +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0073 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK_PENDING 0x0074 +#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GO_PENDING 0x0075 +#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0076 +#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_TLB_PENDING 0x0077 +#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_OARB_PENDING 0x0078 +#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0079 +#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK2DF_PENDING 0x007a +#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_OSD_PENDING 0x007b +#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x007c +#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x007d +#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x007e +#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x007f +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0080 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE 0x0081 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX 0 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 0x0082 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB0_DAGB_DLY 0x0083 +#define regDAGB0_DAGB_DLY_BASE_IDX 0 +#define regDAGB0_CNTL_MISC 0x0084 +#define regDAGB0_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_CNTL_MISC2 0x0085 +#define regDAGB0_CNTL_MISC2_BASE_IDX 0 +#define regDAGB0_FIFO_EMPTY 0x0086 +#define regDAGB0_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB0_FIFO_FULL 0x0087 +#define regDAGB0_FIFO_FULL_BASE_IDX 0 +#define regDAGB0_RD_CREDITS_FULL 0x0088 +#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB0_WR_CREDITS_FULL 0x0089 +#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_LO 0x008a +#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_HI 0x008b +#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER0_CFG 0x008c +#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER1_CFG 0x008d +#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER2_CFG 0x008e +#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x008f +#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB0_L1TLB_REG_RW 0x0090 +#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB0_RESERVE1 0x0091 +#define regDAGB0_RESERVE1_BASE_IDX 0 +#define regDAGB0_RESERVE2 0x0092 +#define regDAGB0_RESERVE2_BASE_IDX 0 +#define regDAGB0_RESERVE3 0x0093 +#define regDAGB0_RESERVE3_BASE_IDX 0 +#define regDAGB0_RESERVE4 0x0094 +#define regDAGB0_RESERVE4_BASE_IDX 0 +#define regDAGB0_SDP_RD_BW_CNTL 0x0095 +#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 0 +#define regDAGB0_SDP_PRIORITY_OVERRIDE 0x0096 +#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 +#define regDAGB0_SDP_RD_PRIORITY 0x0097 +#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 0 +#define regDAGB0_SDP_WR_PRIORITY 0x0098 +#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 0 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x0099 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x009a +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 0 +#define regDAGB0_SDP_ENABLE 0x009b +#define regDAGB0_SDP_ENABLE_BASE_IDX 0 +#define regDAGB0_SDP_CREDITS 0x009c +#define regDAGB0_SDP_CREDITS_BASE_IDX 0 +#define regDAGB0_SDP_TAG_RESERVE0 0x009d +#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regDAGB0_SDP_TAG_RESERVE1 0x009e +#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regDAGB0_SDP_VCC_RESERVE0 0x009f +#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regDAGB0_SDP_VCC_RESERVE1 0x00a0 +#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regDAGB0_SDP_ERR_STATUS 0x00a1 +#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 0 +#define regDAGB0_SDP_REQ_CNTL 0x00a2 +#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 0 +#define regDAGB0_SDP_MISC 0x00a4 +#define regDAGB0_SDP_MISC_BASE_IDX 0 +#define regDAGB0_SDP_MISC2 0x00a5 +#define regDAGB0_SDP_MISC2_BASE_IDX 0 +#define regDAGB0_SDP_VCD_RESERVE0 0x00a7 +#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regDAGB0_SDP_VCD_RESERVE1 0x00a8 +#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regDAGB0_SDP_ARB_CNTL0 0x00a9 +#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 0 +#define regDAGB0_SDP_ARB_CNTL1 0x00aa +#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_CNTL 0x00ab +#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_CLEAR 0x00ac +#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS0 0x00ad +#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS1 0x00ae +#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS2 0x00af +#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS3 0x00b0 +#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS4 0x00b1 +#define regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX 0 +#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00b6 +#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_SDP_LATENCY_SAMPLING 0x00b7 +#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 0 +#define regDAGB1_RDCLI0 0x00b8 +#define regDAGB1_RDCLI0_BASE_IDX 0 +#define regDAGB1_RDCLI1 0x00b9 +#define regDAGB1_RDCLI1_BASE_IDX 0 +#define regDAGB1_RDCLI2 0x00ba +#define regDAGB1_RDCLI2_BASE_IDX 0 +#define regDAGB1_RDCLI3 0x00bb +#define regDAGB1_RDCLI3_BASE_IDX 0 +#define regDAGB1_RDCLI4 0x00bc +#define regDAGB1_RDCLI4_BASE_IDX 0 +#define regDAGB1_RDCLI5 0x00bd +#define regDAGB1_RDCLI5_BASE_IDX 0 +#define regDAGB1_RDCLI6 0x00be +#define regDAGB1_RDCLI6_BASE_IDX 0 +#define regDAGB1_RDCLI7 0x00bf +#define regDAGB1_RDCLI7_BASE_IDX 0 +#define regDAGB1_RDCLI8 0x00c0 +#define regDAGB1_RDCLI8_BASE_IDX 0 +#define regDAGB1_RDCLI9 0x00c1 +#define regDAGB1_RDCLI9_BASE_IDX 0 +#define regDAGB1_RDCLI10 0x00c2 +#define regDAGB1_RDCLI10_BASE_IDX 0 +#define regDAGB1_RDCLI11 0x00c3 +#define regDAGB1_RDCLI11_BASE_IDX 0 +#define regDAGB1_RDCLI12 0x00c4 +#define regDAGB1_RDCLI12_BASE_IDX 0 +#define regDAGB1_RDCLI13 0x00c5 +#define regDAGB1_RDCLI13_BASE_IDX 0 +#define regDAGB1_RDCLI14 0x00c6 +#define regDAGB1_RDCLI14_BASE_IDX 0 +#define regDAGB1_RDCLI15 0x00c7 +#define regDAGB1_RDCLI15_BASE_IDX 0 +#define regDAGB1_RDCLI16 0x00c8 +#define regDAGB1_RDCLI16_BASE_IDX 0 +#define regDAGB1_RDCLI17 0x00c9 +#define regDAGB1_RDCLI17_BASE_IDX 0 +#define regDAGB1_RDCLI18 0x00ca +#define regDAGB1_RDCLI18_BASE_IDX 0 +#define regDAGB1_RDCLI19 0x00cb +#define regDAGB1_RDCLI19_BASE_IDX 0 +#define regDAGB1_RDCLI20 0x00cc +#define regDAGB1_RDCLI20_BASE_IDX 0 +#define regDAGB1_RDCLI21 0x00cd +#define regDAGB1_RDCLI21_BASE_IDX 0 +#define regDAGB1_RDCLI22 0x00ce +#define regDAGB1_RDCLI22_BASE_IDX 0 +#define regDAGB1_RDCLI23 0x00cf +#define regDAGB1_RDCLI23_BASE_IDX 0 +#define regDAGB1_RD_CNTL 0x00d0 +#define regDAGB1_RD_CNTL_BASE_IDX 0 +#define regDAGB1_RD_IO_CNTL 0x00d1 +#define regDAGB1_RD_IO_CNTL_BASE_IDX 0 +#define regDAGB1_RD_GMI_CNTL 0x00d2 +#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB 0x00d3 +#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB1_RD_CGTT_CLK_CTRL 0x00d4 +#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x00d5 +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x00d6 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x00d7 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x00d8 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x00d9 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2 0x00da +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 0x00db +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB1_RD_VC0_CNTL 0x00dc +#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC1_CNTL 0x00dd +#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC2_CNTL 0x00de +#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC3_CNTL 0x00df +#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC4_CNTL 0x00e0 +#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC5_CNTL 0x00e1 +#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB1_RD_IO_VC_CNTL 0x00e2 +#define regDAGB1_RD_IO_VC_CNTL_BASE_IDX 0 +#define regDAGB1_RD_GMI_VC_CNTL 0x00e3 +#define regDAGB1_RD_GMI_VC_CNTL_BASE_IDX 0 +#define regDAGB1_RD_CNTL_MISC 0x00e4 +#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB1_RD_TLB_CREDIT 0x00e5 +#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00e6 +#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00e7 +#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK_PENDING 0x00e8 +#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_GO_PENDING 0x00e9 +#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00ea +#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_TLB_PENDING 0x00eb +#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_OARB_PENDING 0x00ec +#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK2ARB_PENDING 0x00ed +#define regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK2DF_PENDING 0x00ee +#define regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_OSD_PENDING 0x00ef +#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK_OSD_PENDING 0x00f0 +#define regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE 0x00f1 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE 0x00f2 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB1_DAGB_DLY 0x00f3 +#define regDAGB1_DAGB_DLY_BASE_IDX 0 +#define regDAGB1_CNTL_MISC 0x00f4 +#define regDAGB1_CNTL_MISC_BASE_IDX 0 +#define regDAGB1_CNTL_MISC2 0x00f5 +#define regDAGB1_CNTL_MISC2_BASE_IDX 0 +#define regDAGB1_FIFO_EMPTY 0x00f6 +#define regDAGB1_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB1_FIFO_FULL 0x00f7 +#define regDAGB1_FIFO_FULL_BASE_IDX 0 +#define regDAGB1_RD_CREDITS_FULL 0x00f8 +#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_LO 0x00f9 +#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_HI 0x00fa +#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER0_CFG 0x00fb +#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER1_CFG 0x00fc +#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER2_CFG 0x00fd +#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fe +#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB1_L1TLB_REG_RW 0x00ff +#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB1_RESERVE1 0x0100 +#define regDAGB1_RESERVE1_BASE_IDX 0 +#define regDAGB1_RESERVE2 0x0101 +#define regDAGB1_RESERVE2_BASE_IDX 0 +#define regDAGB1_RESERVE3 0x0102 +#define regDAGB1_RESERVE3_BASE_IDX 0 +#define regDAGB1_RESERVE4 0x0103 +#define regDAGB1_RESERVE4_BASE_IDX 0 +#define regDAGB1_SDP_RD_BW_CNTL 0x0104 +#define regDAGB1_SDP_RD_BW_CNTL_BASE_IDX 0 +#define regDAGB1_SDP_PRIORITY_OVERRIDE 0x0105 +#define regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 +#define regDAGB1_SDP_RD_PRIORITY 0x0106 +#define regDAGB1_SDP_RD_PRIORITY_BASE_IDX 0 +#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP 0x0107 +#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 +#define regDAGB1_SDP_ENABLE 0x0108 +#define regDAGB1_SDP_ENABLE_BASE_IDX 0 +#define regDAGB1_SDP_CREDITS 0x0109 +#define regDAGB1_SDP_CREDITS_BASE_IDX 0 +#define regDAGB1_SDP_TAG_RESERVE0 0x010a +#define regDAGB1_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regDAGB1_SDP_TAG_RESERVE1 0x010b +#define regDAGB1_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regDAGB1_SDP_VCC_RESERVE0 0x010c +#define regDAGB1_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regDAGB1_SDP_VCC_RESERVE1 0x010d +#define regDAGB1_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regDAGB1_SDP_ERR_STATUS 0x010e +#define regDAGB1_SDP_ERR_STATUS_BASE_IDX 0 +#define regDAGB1_SDP_REQ_CNTL 0x010f +#define regDAGB1_SDP_REQ_CNTL_BASE_IDX 0 +#define regDAGB1_SDP_MISC 0x0111 +#define regDAGB1_SDP_MISC_BASE_IDX 0 +#define regDAGB1_SDP_MISC2 0x0112 +#define regDAGB1_SDP_MISC2_BASE_IDX 0 +#define regDAGB1_SDP_ARB_CNTL0 0x0114 +#define regDAGB1_SDP_ARB_CNTL0_BASE_IDX 0 +#define regDAGB1_SDP_ARB_CNTL1 0x0115 +#define regDAGB1_SDP_ARB_CNTL1_BASE_IDX 0 +#define regDAGB1_SDP_CGTT_CLK_CTRL 0x0116 +#define regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_SDP_LATENCY_SAMPLING 0x0117 +#define regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX 0 + + +// addressBlock: mmhub_pctldec +// base address: 0x68e00 +#define regPCTL_CTRL 0x0380 +#define regPCTL_CTRL_BASE_IDX 0 +#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381 +#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 0 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0 +#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384 +#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388 +#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c +#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL_UTCL2_MISC 0x038e +#define regPCTL_UTCL2_MISC_BASE_IDX 0 +#define regPCTL_SLICE0_MISC 0x038f +#define regPCTL_SLICE0_MISC_BASE_IDX 0 +#define regPCTL_SLICE1_MISC 0x0390 +#define regPCTL_SLICE1_MISC_BASE_IDX 0 +#define regPCTL_RENG_CTRL 0x0391 +#define regPCTL_RENG_CTRL_BASE_IDX 0 +#define regPCTL_UTCL2_RENG_EXECUTE 0x0392 +#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 0 +#define regPCTL_SLICE0_RENG_EXECUTE 0x0393 +#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 0 +#define regPCTL_SLICE1_RENG_EXECUTE 0x0394 +#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 0 +#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395 +#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 0 +#define regPCTL_UTCL2_RENG_RAM_DATA 0x0396 +#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 0 +#define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397 +#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 0 +#define regPCTL_SLICE0_RENG_RAM_DATA 0x0398 +#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 0 +#define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399 +#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 0 +#define regPCTL_SLICE1_RENG_RAM_DATA 0x039a +#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define regPCTL_STATUS 0x03b0 +#define regPCTL_STATUS_BASE_IDX 0 +#define regPCTL_PERFCOUNTER_LO 0x03b1 +#define regPCTL_PERFCOUNTER_LO_BASE_IDX 0 +#define regPCTL_PERFCOUNTER_HI 0x03b2 +#define regPCTL_PERFCOUNTER_HI_BASE_IDX 0 +#define regPCTL_PERFCOUNTER0_CFG 0x03b3 +#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regPCTL_PERFCOUNTER1_CFG 0x03b4 +#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 +#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regPCTL_RESERVED_0 0x03b6 +#define regPCTL_RESERVED_0_BASE_IDX 0 +#define regPCTL_RESERVED_1 0x03b7 +#define regPCTL_RESERVED_1_BASE_IDX 0 +#define regPCTL_RESERVED_2 0x03b8 +#define regPCTL_RESERVED_2_BASE_IDX 0 +#define regPCTL_RESERVED_3 0x03b9 +#define regPCTL_RESERVED_3_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_mmutcl1pfdec +// base address: 0x69600 +#define regMMMC_VM_MX_L1_TLB0_STATUS 0x0586 +#define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB1_STATUS 0x0587 +#define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB2_STATUS 0x0588 +#define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB3_STATUS 0x0589 +#define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB4_STATUS 0x058a +#define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB5_STATUS 0x058b +#define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_mmutcl1pldec +// base address: 0x69670 +#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c +#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d +#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e +#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f +#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 +#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_mmutcl1prdec +// base address: 0x69690 +#define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 +#define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 +#define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmatcl2dec +// base address: 0x69b00 +#define regMM_ATC_L2_CNTL 0x06c0 +#define regMM_ATC_L2_CNTL_BASE_IDX 0 +#define regMM_ATC_L2_CNTL2 0x06c1 +#define regMM_ATC_L2_CNTL2_BASE_IDX 0 +#define regMM_ATC_L2_CACHE_DATA0 0x06c4 +#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 0 +#define regMM_ATC_L2_CACHE_DATA1 0x06c5 +#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 0 +#define regMM_ATC_L2_CACHE_DATA2 0x06c6 +#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 0 +#define regMM_ATC_L2_CNTL3 0x06c7 +#define regMM_ATC_L2_CNTL3_BASE_IDX 0 +#define regMM_ATC_L2_CNTL4 0x06c8 +#define regMM_ATC_L2_CNTL4_BASE_IDX 0 +#define regMM_ATC_L2_CNTL5 0x06c9 +#define regMM_ATC_L2_CNTL5_BASE_IDX 0 +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regMM_ATC_L2_STATUS 0x06cb +#define regMM_ATC_L2_STATUS_BASE_IDX 0 +#define regMM_ATC_L2_STATUS2 0x06cc +#define regMM_ATC_L2_STATUS2_BASE_IDX 0 +#define regMM_ATC_L2_MISC_CG 0x06cd +#define regMM_ATC_L2_MISC_CG_BASE_IDX 0 +#define regMM_ATC_L2_MEM_POWER_LS 0x06ce +#define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX 0 +#define regMM_ATC_L2_CGTT_CLK_CTRL 0x06cf +#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMM_ATC_L2_SDPPORT_CTRL 0x06d2 +#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 0 +#define regMMUTCL2_FFBM_CONFIG 0x06d4 +#define regMMUTCL2_FFBM_CONFIG_BASE_IDX 0 +#define regMMUTCL2_FFBM_ACCESS_CNTL 0x06d5 +#define regMMUTCL2_FFBM_ACCESS_CNTL_BASE_IDX 0 +#define regMMUTCL2_FFBM_ADDRESS 0x06d6 +#define regMMUTCL2_FFBM_ADDRESS_BASE_IDX 0 +#define regMMUTCL2_FFBM_DATA 0x06d7 +#define regMMUTCL2_FFBM_DATA_BASE_IDX 0 +#define regMMUTCL2_FFBM_INVALIDATE_REQUEST 0x06d8 +#define regMMUTCL2_FFBM_INVALIDATE_REQUEST_BASE_IDX 0 +#define regMMUTCL2_FFBM_INVALIDATE_RESPONSE 0x06d9 +#define regMMUTCL2_FFBM_INVALIDATE_RESPONSE_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +// base address: 0x69c00 +#define regMMVM_L2_CNTL 0x0700 +#define regMMVM_L2_CNTL_BASE_IDX 0 +#define regMMVM_L2_CNTL2 0x0701 +#define regMMVM_L2_CNTL2_BASE_IDX 0 +#define regMMVM_L2_CNTL3 0x0702 +#define regMMVM_L2_CNTL3_BASE_IDX 0 +#define regMMVM_L2_STATUS 0x0703 +#define regMMVM_L2_STATUS_BASE_IDX 0 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_CNTL 0x0707 +#define regMMVM_INVALIDATE_CNTL_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0708 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_STATUS 0x070c +#define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regMMVM_L2_CNTL4 0x0718 +#define regMMVM_L2_CNTL4_BASE_IDX 0 +#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0719 +#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a +#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regMMVM_L2_CACHE_PARITY_CNTL 0x071c +#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regMMVM_L2_CGTT_CLK_CTRL 0x071d +#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMVM_L2_CNTL5 0x071e +#define regMMVM_L2_CNTL5_BASE_IDX 0 +#define regMMVM_L2_GCR_CNTL 0x071f +#define regMMVM_L2_GCR_CNTL_BASE_IDX 0 +#define regMMVM_L2_CGTT_BUSY_CTRL 0x0720 +#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0721 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 +#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0722 +#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 +#define regMMVM_L2_BANK_SELECT_MASKS 0x0725 +#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0726 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0727 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0728 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0729 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x072a +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +// base address: 0x69d00 +#define regMMVM_CONTEXT0_CNTL 0x0740 +#define regMMVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT1_CNTL 0x0741 +#define regMMVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT2_CNTL 0x0742 +#define regMMVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT3_CNTL 0x0743 +#define regMMVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT4_CNTL 0x0744 +#define regMMVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT5_CNTL 0x0745 +#define regMMVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT6_CNTL 0x0746 +#define regMMVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT7_CNTL 0x0747 +#define regMMVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT8_CNTL 0x0748 +#define regMMVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT9_CNTL 0x0749 +#define regMMVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT10_CNTL 0x074a +#define regMMVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT11_CNTL 0x074b +#define regMMVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT12_CNTL 0x074c +#define regMMVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT13_CNTL 0x074d +#define regMMVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT14_CNTL 0x074e +#define regMMVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT15_CNTL 0x074f +#define regMMVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXTS_DISABLE 0x0750 +#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_SEM 0x0751 +#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_SEM 0x0752 +#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_SEM 0x0753 +#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_SEM 0x0754 +#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_SEM 0x0755 +#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_SEM 0x0756 +#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_SEM 0x0757 +#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_SEM 0x0758 +#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_SEM 0x0759 +#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_SEM 0x075a +#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_SEM 0x075b +#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_SEM 0x075c +#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_SEM 0x075d +#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_SEM 0x075e +#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_SEM 0x075f +#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_SEM 0x0760 +#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_SEM 0x0761 +#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_SEM 0x0762 +#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_REQ 0x0763 +#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_REQ 0x0764 +#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_REQ 0x0765 +#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_REQ 0x0766 +#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_REQ 0x0767 +#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_REQ 0x0768 +#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_REQ 0x0769 +#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_REQ 0x076a +#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_REQ 0x076b +#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_REQ 0x076c +#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_REQ 0x076d +#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_REQ 0x076e +#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_REQ 0x076f +#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_REQ 0x0770 +#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_REQ 0x0771 +#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_REQ 0x0772 +#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_REQ 0x0773 +#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_REQ 0x0774 +#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_ACK 0x0775 +#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_ACK 0x0776 +#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_ACK 0x0777 +#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_ACK 0x0778 +#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_ACK 0x0779 +#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_ACK 0x077a +#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_ACK 0x077b +#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_ACK 0x077c +#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_ACK 0x077d +#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_ACK 0x077e +#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_ACK 0x077f +#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_ACK 0x0780 +#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_ACK 0x0781 +#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_ACK 0x0782 +#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_ACK 0x0783 +#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_ACK 0x0784 +#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_ACK 0x0785 +#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_ACK 0x0786 +#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0787 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0788 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0789 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x078a +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x078b +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x078c +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x078d +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x078e +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x078f +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0790 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0791 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0792 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0793 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0794 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0795 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0796 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0797 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0798 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0799 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x079a +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x079b +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x079c +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x079d +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x079e +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x079f +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x07a0 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x07a1 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x07a2 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x07a3 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x07a4 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x07a5 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x07a6 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x07a7 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x07a8 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x07a9 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x07aa +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x07ab +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x07ac +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x07ad +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x07ae +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x07af +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x07b0 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x07b1 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x07b2 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x07b3 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x07b4 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x07b5 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x07b6 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x07b7 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x07b8 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x07b9 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x07ba +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x07bb +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x07bc +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x07bd +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x07be +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x07bf +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x07c0 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x07c1 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x07c2 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x07c3 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x07c4 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x07c5 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x07c6 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x07c7 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x07c8 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x07c9 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x07ca +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x07cb +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x07cc +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x07cd +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x07ce +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x07cf +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x07d0 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x07d1 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x07d2 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x07d3 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x07d4 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x07d5 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x07d6 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x07d7 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x07d8 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x07d9 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x07da +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x07db +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x07dc +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x07dd +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x07de +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x07df +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x07e0 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x07e1 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x07e2 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x07e3 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x07e4 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x07e5 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x07e6 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x07e7 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x07e8 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x07e9 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x07ea +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x07eb +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x07ec +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x07ed +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x07ee +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x07ef +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x07f0 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x07f1 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x07f2 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x07f3 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x07f4 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x07f5 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x07f6 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x07f7 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x07f8 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x07f9 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x07fa +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x07fb +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x07fc +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x07fd +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x07fe +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x07ff +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0800 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0801 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0802 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0803 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0804 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0805 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0806 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0807 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0808 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0809 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x080a +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080b +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080c +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080d +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080e +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080f +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0810 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0811 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0812 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0813 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0814 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0815 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0816 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0817 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0818 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0819 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081a +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081b +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +// base address: 0x6a090 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a +#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b +#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER0_CFG 0x082d +#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER1_CFG 0x082e +#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER2_CFG 0x082f +#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER3_CFG 0x0830 +#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +// base address: 0x6a0e0 +#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0838 +#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0839 +#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER_LO 0x083a +#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER_HI 0x083b +#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +// base address: 0x6a130 +#define regMMMC_VM_FB_SIZE_OFFSET_VF0 0x084c +#define regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF1 0x084d +#define regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF2 0x084e +#define regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF3 0x084f +#define regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF4 0x0850 +#define regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF5 0x0851 +#define regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF6 0x0852 +#define regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF7 0x0853 +#define regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF8 0x0854 +#define regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF9 0x0855 +#define regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF10 0x0856 +#define regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF11 0x0857 +#define regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF12 0x0858 +#define regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF13 0x0859 +#define regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF14 0x085a +#define regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF15 0x085b +#define regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +// base address: 0x6a340 +#define regMMMC_VM_FB_OFFSET 0x08d7 +#define regMMMC_VM_FB_OFFSET_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regMMMC_VM_STEERING 0x08da +#define regMMMC_VM_STEERING_BASE_IDX 0 +#define regMMMC_MEM_POWER_LS 0x08dc +#define regMMMC_MEM_POWER_LS_BASE_IDX 0 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x08df +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x08e0 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 +#define regMMMC_VM_APT_CNTL 0x08e1 +#define regMMMC_VM_APT_CNTL_BASE_IDX 0 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x08e2 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x08e3 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x08e4 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 +#define regMMUTCL2_CGTT_CLK_CTRL 0x08e5 +#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMUTCL2_CGTT_BUSY_CTRL 0x08e7 +#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regMMMC_VM_FB_NOALLOC_CNTL 0x08e8 +#define regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e9 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 +#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x08eb +#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +// base address: 0x6a3b0 +#define regMMMC_VM_FB_LOCATION_BASE 0x08ec +#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regMMMC_VM_FB_LOCATION_TOP 0x08ed +#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define regMMMC_VM_AGP_TOP 0x08ee +#define regMMMC_VM_AGP_TOP_BASE_IDX 0 +#define regMMMC_VM_AGP_BOT 0x08ef +#define regMMMC_VM_AGP_BOT_BASE_IDX 0 +#define regMMMC_VM_AGP_BASE 0x08f0 +#define regMMMC_VM_AGP_BASE_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB_CNTL 0x08f3 +#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec +// base address: 0x6a400 +#define regMM_ATC_L2_PERFCOUNTER_LO 0x0900 +#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 0 +#define regMM_ATC_L2_PERFCOUNTER_HI 0x0901 +#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec +// base address: 0x6a420 +#define regMM_ATC_L2_PERFCOUNTER0_CFG 0x0908 +#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMM_ATC_L2_PERFCOUNTER1_CFG 0x0909 +#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +// base address: 0x6aa50 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0a94 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 0 +#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0a99 +#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 0 +#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0a9a +#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 0 +#define regMMUTCL2_FFBM_ENABLE_CNTL 0x0a9b +#define regMMUTCL2_FFBM_ENABLE_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mml2tlbpspdec +// base address: 0x6aa80 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0aa0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pspdec +// base address: 0x6aa90 +#define regMM_ATC_L2_IOV_MODE_CNTL 0x0aa4 +#define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mml2tlbpfdec +// base address: 0x6aac0 +#define regMML2TLB_TLB0_STATUS 0x0ab1 +#define regMML2TLB_TLB0_STATUS_BASE_IDX 0 +#define regMML2TLB_TMZ_CNTL 0x0ab2 +#define regMML2TLB_TMZ_CNTL_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0ab3 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0ab4 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0ab5 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0ab6 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 +#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x0ab7 +#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mml2tlbpldec +// base address: 0x6ab00 +#define regMML2TLB_PERFCOUNTER0_CFG 0x0ac0 +#define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMML2TLB_PERFCOUNTER1_CFG 0x0ac1 +#define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMML2TLB_PERFCOUNTER2_CFG 0x0ac2 +#define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMML2TLB_PERFCOUNTER3_CFG 0x0ac3 +#define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4 +#define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mml2tlbprdec +// base address: 0x6ab20 +#define regMML2TLB_PERFCOUNTER_LO 0x0ac8 +#define regMML2TLB_PERFCOUNTER_LO_BASE_IDX 0 +#define regMML2TLB_PERFCOUNTER_HI 0x0ac9 +#define regMML2TLB_PERFCOUNTER_HI_BASE_IDX 0 + +#endif diff --git a/extra/amdpci/headers/mmhub_3_0_0_sh_mask.h b/extra/amdpci/headers/mmhub_3_0_0_sh_mask.h new file mode 100644 index 0000000000..b354346ec6 --- /dev/null +++ b/extra/amdpci/headers/mmhub_3_0_0_sh_mask.h @@ -0,0 +1,7478 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_3_0_0_SH_MASK_HEADER +#define _mmhub_3_0_0_SH_MASK_HEADER + + +// addressBlock: mmhub_dagbdec +//DAGB0_RDCLI0 +#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI1 +#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI2 +#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI3 +#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI4 +#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI5 +#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI6 +#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI7 +#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI8 +#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI9 +#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI10 +#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI11 +#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI12 +#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI13 +#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI14 +#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI15 +#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI16 +#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI17 +#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI18 +#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI19 +#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI20 +#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI21 +#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI22 +#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI23 +#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_RD_CNTL +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc +#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L +#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L +//DAGB0_RD_IO_CNTL +#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_RD_GMI_CNTL +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_RD_ADDR_DAGB +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_RD_CGTT_CLK_CTRL +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_VC0_CNTL +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC1_CNTL +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC2_CNTL +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC3_CNTL +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC4_CNTL +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC5_CNTL +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_IO_VC_CNTL +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_GMI_VC_CNTL +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_CNTL_MISC +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 +#define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L +#define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L +//DAGB0_RD_TLB_CREDIT +#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_RD_RDRET_CREDIT_CNTL +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB0_RD_RDRET_CREDIT_CNTL2 +#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL +//DAGB0_RDCLI_ASK_PENDING +#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GO_PENDING +#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GBLSEND_PENDING +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_TLB_PENDING +#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OARB_PENDING +#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK2ARB_PENDING +#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK2DF_PENDING +#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OSD_PENDING +#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK_OSD_PENDING +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_NOALLOC_OVERRIDE +#define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE +#define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 +#define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI0 +#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI1 +#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI2 +#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI3 +#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI4 +#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI5 +#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI6 +#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI7 +#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI8 +#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI9 +#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI10 +#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI11 +#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI12 +#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI13 +#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI14 +#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI15 +#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI16 +#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI17 +#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI18 +#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI19 +#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI20 +#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI21 +#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI22 +#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI23 +#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_WR_CNTL +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc +#define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd +#define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L +#define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L +#define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L +//DAGB0_WR_IO_CNTL +#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_WR_GMI_CNTL +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_WR_ADDR_DAGB +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_WR_CGTT_CLK_CTRL +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST2 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_DATA_DAGB_MAX_BURST0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST1 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST2 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_VC0_CNTL +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC1_CNTL +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC2_CNTL +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC3_CNTL +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC4_CNTL +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC5_CNTL +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_IO_VC_CNTL +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_GMI_VC_CNTL +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_CNTL_MISC +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L +//DAGB0_WR_TLB_CREDIT +#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_WR_DATA_CREDIT +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB0_WR_MISC_CREDIT +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L +//DAGB0_WRCLI_ASK_PENDING +#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GO_PENDING +#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GBLSEND_PENDING +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_TLB_PENDING +#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OARB_PENDING +#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK2ARB_PENDING +#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK2DF_PENDING +#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OSD_PENDING +#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK_OSD_PENDING +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_ASK_PENDING +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_GO_PENDING +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_NOALLOC_OVERRIDE +#define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE +#define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 +#define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL +//DAGB0_DAGB_DLY +#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB0_CNTL_MISC +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 +#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 +#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb +#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L +#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L +#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L +#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L +#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L +//DAGB0_FIFO_EMPTY +#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL +//DAGB0_FIFO_FULL +#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL +//DAGB0_RD_CREDITS_FULL +#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL +//DAGB0_WR_CREDITS_FULL +#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL +//DAGB0_PERFCOUNTER_LO +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB0_PERFCOUNTER_HI +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB0_PERFCOUNTER0_CFG +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER1_CFG +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER2_CFG +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER_RSLT_CNTL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB0_L1TLB_REG_RW +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2 +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL +//DAGB0_RESERVE1 +#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE2 +#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE3 +#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE4 +#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_SDP_RD_BW_CNTL +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L +//DAGB0_SDP_PRIORITY_OVERRIDE +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L +//DAGB0_SDP_RD_PRIORITY +#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 +#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 +#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc +#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 +#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L +//DAGB0_SDP_WR_PRIORITY +#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 +#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 +#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc +#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 +#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L +//DAGB0_SDP_RD_CLI2SDP_VC_MAP +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB0_SDP_WR_CLI2SDP_VC_MAP +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB0_SDP_ENABLE +#define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L +//DAGB0_SDP_CREDITS +#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L +//DAGB0_SDP_TAG_RESERVE0 +#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//DAGB0_SDP_TAG_RESERVE1 +#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//DAGB0_SDP_VCC_RESERVE0 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB0_SDP_VCC_RESERVE1 +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB0_SDP_ERR_STATUS +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//DAGB0_SDP_REQ_CNTL +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//DAGB0_SDP_MISC +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L +//DAGB0_SDP_MISC2 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 +#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L +#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L +//DAGB0_SDP_VCD_RESERVE0 +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB0_SDP_VCD_RESERVE1 +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12 +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L +//DAGB0_SDP_ARB_CNTL0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 +#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 +#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 +#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 +#define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L +#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L +#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L +#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L +#define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L +//DAGB0_SDP_ARB_CNTL1 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L +//DAGB0_FATAL_ERROR_CNTL +#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB0_FATAL_ERROR_CLEAR +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB0_FATAL_ERROR_STATUS0 +#define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB0_FATAL_ERROR_STATUS1 +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB0_FATAL_ERROR_STATUS2 +#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT 0x10 +#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x18 +#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x1c +#define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x1d +#define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x1e +#define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x1f +#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK 0x0000FFFFL +#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK 0x00FF0000L +#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x0F000000L +#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x10000000L +#define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x20000000L +#define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x40000000L +#define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x80000000L +//DAGB0_FATAL_ERROR_STATUS3 +#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT 0x18 +#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT 0x19 +#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK 0x01000000L +#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK 0x02000000L +//DAGB0_FATAL_ERROR_STATUS4 +#define DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT 0x4 +#define DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT 0x5 +#define DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT 0x7 +#define DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT 0x8 +#define DAGB0_FATAL_ERROR_STATUS4__PRI_MASK 0x0000000FL +#define DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK 0x00000010L +#define DAGB0_FATAL_ERROR_STATUS4__FULL_MASK 0x00000020L +#define DAGB0_FATAL_ERROR_STATUS4__DROP_MASK 0x00000040L +#define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK 0x00000080L +#define DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK 0x00000100L +//DAGB0_SDP_CGTT_CLK_CTRL +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_SDP_LATENCY_SAMPLING +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//DAGB1_RDCLI0 +#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI1 +#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI2 +#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI3 +#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI4 +#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI5 +#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI6 +#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI7 +#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI8 +#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI9 +#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI10 +#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI11 +#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI12 +#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI13 +#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI14 +#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI15 +#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI16 +#define DAGB1_RDCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI16__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI17 +#define DAGB1_RDCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI17__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI18 +#define DAGB1_RDCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI18__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI19 +#define DAGB1_RDCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI19__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI20 +#define DAGB1_RDCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI20__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI21 +#define DAGB1_RDCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI21__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI22 +#define DAGB1_RDCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI22__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI23 +#define DAGB1_RDCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI23__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB1_RD_CNTL +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc +#define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L +#define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L +//DAGB1_RD_IO_CNTL +#define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB1_RD_GMI_CNTL +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB1_RD_ADDR_DAGB +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB1_RD_CGTT_CLK_CTRL +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB1_RD_VC0_CNTL +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC1_CNTL +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC2_CNTL +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC3_CNTL +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC4_CNTL +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC5_CNTL +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_IO_VC_CNTL +#define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_GMI_VC_CNTL +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_CNTL_MISC +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 +#define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L +#define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L +//DAGB1_RD_TLB_CREDIT +#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB1_RD_RDRET_CREDIT_CNTL +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB1_RD_RDRET_CREDIT_CNTL2 +#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 +#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL +//DAGB1_RDCLI_ASK_PENDING +#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GO_PENDING +#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GBLSEND_PENDING +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_TLB_PENDING +#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OARB_PENDING +#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_ASK2ARB_PENDING +#define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_ASK2DF_PENDING +#define DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OSD_PENDING +#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_ASK_OSD_PENDING +#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_NOALLOC_OVERRIDE +#define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE +#define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 +#define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL +//DAGB1_DAGB_DLY +#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB1_CNTL_MISC +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL +//DAGB1_CNTL_MISC2 +#define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 +#define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 +#define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 +#define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 +#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 +#define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 +#define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 +#define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb +#define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L +#define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L +#define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L +#define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L +#define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L +#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L +#define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L +#define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L +#define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L +//DAGB1_FIFO_EMPTY +#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x0000007FL +//DAGB1_FIFO_FULL +#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB1_FIFO_FULL__FULL_MASK 0x0000007FL +//DAGB1_RD_CREDITS_FULL +#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0000007FL +//DAGB1_PERFCOUNTER_LO +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB1_PERFCOUNTER_HI +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB1_PERFCOUNTER0_CFG +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER1_CFG +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER2_CFG +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER_RSLT_CNTL +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB1_L1TLB_REG_RW +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x2 +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL +//DAGB1_RESERVE1 +#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE2 +#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE3 +#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE4 +#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_SDP_RD_BW_CNTL +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L +//DAGB1_SDP_PRIORITY_OVERRIDE +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L +//DAGB1_SDP_RD_PRIORITY +#define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 +#define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 +#define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 +#define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc +#define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 +#define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 +#define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L +//DAGB1_SDP_RD_CLI2SDP_VC_MAP +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB1_SDP_ENABLE +#define DAGB1_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define DAGB1_SDP_ENABLE__ENABLE_MASK 0x00000001L +//DAGB1_SDP_CREDITS +#define DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define DAGB1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L +//DAGB1_SDP_TAG_RESERVE0 +#define DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define DAGB1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define DAGB1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define DAGB1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define DAGB1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//DAGB1_SDP_TAG_RESERVE1 +#define DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define DAGB1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define DAGB1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define DAGB1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define DAGB1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//DAGB1_SDP_VCC_RESERVE0 +#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB1_SDP_VCC_RESERVE1 +#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB1_SDP_ERR_STATUS +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//DAGB1_SDP_REQ_CNTL +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//DAGB1_SDP_MISC +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 +#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 +#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 +#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb +#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd +#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf +#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 +#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L +#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L +#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L +#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L +#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L +#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L +#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L +#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L +//DAGB1_SDP_MISC2 +#define DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 +#define DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 +#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 +#define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 +#define DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L +#define DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L +#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L +#define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L +//DAGB1_SDP_ARB_CNTL0 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 +#define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 +#define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 +#define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 +#define DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L +#define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L +#define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L +#define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L +#define DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L +//DAGB1_SDP_ARB_CNTL1 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L +//DAGB1_SDP_CGTT_CLK_CTRL +#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_SDP_LATENCY_SAMPLING +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L + + +// addressBlock: mmhub_pctldec +//PCTL_CTRL +#define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 +#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 +#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 +#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b +#define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c +#define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d +#define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e +#define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f +#define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L +#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L +#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L +#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L +#define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L +#define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L +#define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L +#define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_IB +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L +//PCTL_PG_IGNORE_DEEPSLEEP +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L +//PCTL_PG_IGNORE_DEEPSLEEP_IB +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L +//PCTL_SLICE0_CFG_DAGB_WRBUSY +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DAGB_RDBUSY +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DS_ALLOW +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE0_CFG_DS_ALLOW_IB +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_SLICE1_CFG_DAGB_WRBUSY +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DAGB_RDBUSY +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DS_ALLOW +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE1_CFG_DS_ALLOW_IB +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_UTCL2_MISC +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +//PCTL_SLICE0_MISC +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L +//PCTL_SLICE1_MISC +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L +//PCTL_RENG_CTRL +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +//PCTL_UTCL2_RENG_EXECUTE +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L +//PCTL_SLICE0_RENG_EXECUTE +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_SLICE1_RENG_EXECUTE +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_UTCL2_RENG_RAM_INDEX +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL +//PCTL_UTCL2_RENG_RAM_DATA +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE0_RENG_RAM_INDEX +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE0_RENG_RAM_DATA +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE1_RENG_RAM_INDEX +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE1_RENG_RAM_DATA +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_STATUS +#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0 +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 +#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 +#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 +#define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 +#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 +#define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 +#define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 +#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L +#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L +#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L +#define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L +#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L +#define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L +#define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L +//PCTL_PERFCOUNTER_LO +#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//PCTL_PERFCOUNTER_HI +#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//PCTL_PERFCOUNTER0_CFG +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER1_CFG +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER_RSLT_CNTL +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//PCTL_RESERVED_0 +#define PCTL_RESERVED_0__WORD__SHIFT 0x0 +#define PCTL_RESERVED_0__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_0__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_0__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_0__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_0__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_0__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_0__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_0__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_0__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_0__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_0__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_0__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_0__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_0__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_0__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_0__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_0__BIT0_MASK 0x80000000L +//PCTL_RESERVED_1 +#define PCTL_RESERVED_1__WORD__SHIFT 0x0 +#define PCTL_RESERVED_1__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_1__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_1__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_1__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_1__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_1__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_1__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_1__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_1__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_1__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_1__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_1__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_1__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_1__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_1__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_1__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_1__BIT0_MASK 0x80000000L +//PCTL_RESERVED_2 +#define PCTL_RESERVED_2__WORD__SHIFT 0x0 +#define PCTL_RESERVED_2__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_2__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_2__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_2__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_2__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_2__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_2__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_2__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_2__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_2__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_2__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_2__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_2__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_2__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_2__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_2__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_2__BIT0_MASK 0x80000000L +//PCTL_RESERVED_3 +#define PCTL_RESERVED_3__WORD__SHIFT 0x0 +#define PCTL_RESERVED_3__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_3__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_3__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_3__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_3__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_3__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_3__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_3__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_3__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_3__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_3__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_3__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_3__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_3__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_3__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_3__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_3__BIT0_MASK 0x80000000L + + +// addressBlock: mmhub_l1tlb_mmutcl1pfdec +//MMMC_VM_MX_L1_TLB0_STATUS +#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB1_STATUS +#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB2_STATUS +#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB3_STATUS +#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB4_STATUS +#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MMMC_VM_MX_L1_TLB5_STATUS +#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L + + +// addressBlock: mmhub_l1tlb_mmutcl1pldec +//MMMC_VM_MX_L1_PERFCOUNTER0_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER1_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER2_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER3_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_l1tlb_mmutcl1prdec +//MMMC_VM_MX_L1_PERFCOUNTER_LO +#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_PERFCOUNTER_HI +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmatcl2dec +//MM_ATC_L2_CNTL +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 +#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L +#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L +//MM_ATC_L2_CNTL2 +#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//MM_ATC_L2_CACHE_DATA0 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL +#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L +//MM_ATC_L2_CACHE_DATA1 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//MM_ATC_L2_CACHE_DATA2 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//MM_ATC_L2_CNTL3 +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L +//MM_ATC_L2_CNTL4 +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L +//MM_ATC_L2_CNTL5 +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//MM_ATC_L2_MM_GROUP_RT_CLASSES +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL +//MM_ATC_L2_STATUS +#define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 +#define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L +//MM_ATC_L2_STATUS2 +#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 +#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 +#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL +#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L +//MM_ATC_L2_MISC_CG +#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//MM_ATC_L2_MEM_POWER_LS +#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MM_ATC_L2_CGTT_CLK_CTRL +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MM_ATC_L2_SDPPORT_CTRL +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L +//MMUTCL2_FFBM_CONFIG +#define MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE__SHIFT 0x0 +#define MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE_MASK 0x0000001FL +//MMUTCL2_FFBM_ACCESS_CNTL +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST__SHIFT 0x0 +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT__SHIFT 0x1 +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST_MASK 0x00000001L +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT_MASK 0x00000002L +//MMUTCL2_FFBM_ADDRESS +#define MMUTCL2_FFBM_ADDRESS__VFID__SHIFT 0x0 +#define MMUTCL2_FFBM_ADDRESS__ADDRESS__SHIFT 0x4 +#define MMUTCL2_FFBM_ADDRESS__VFID_MASK 0x0000000FL +#define MMUTCL2_FFBM_ADDRESS__ADDRESS_MASK 0x07FFFFF0L +//MMUTCL2_FFBM_DATA +#define MMUTCL2_FFBM_DATA__VALID__SHIFT 0x0 +#define MMUTCL2_FFBM_DATA__READ_PERMISSION__SHIFT 0x1 +#define MMUTCL2_FFBM_DATA__WRITE_PERMISSION__SHIFT 0x2 +#define MMUTCL2_FFBM_DATA__FRAGMENT__SHIFT 0x3 +#define MMUTCL2_FFBM_DATA__FB_SPA__SHIFT 0x8 +#define MMUTCL2_FFBM_DATA__VALID_MASK 0x00000001L +#define MMUTCL2_FFBM_DATA__READ_PERMISSION_MASK 0x00000002L +#define MMUTCL2_FFBM_DATA__WRITE_PERMISSION_MASK 0x00000004L +#define MMUTCL2_FFBM_DATA__FRAGMENT_MASK 0x000000F8L +#define MMUTCL2_FFBM_DATA__FB_SPA_MASK 0x7FFFFF00L +//MMUTCL2_FFBM_INVALIDATE_REQUEST +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ__SHIFT 0x0 +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID__SHIFT 0x1 +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE__SHIFT 0x6 +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE__SHIFT 0x7 +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS__SHIFT 0x8 +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ_MASK 0x00000001L +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID_MASK 0x0000001EL +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE_MASK 0x00000040L +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE_MASK 0x00000080L +#define MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS_MASK 0x7FFFFF00L +//MMUTCL2_FFBM_INVALIDATE_RESPONSE +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK__SHIFT 0x0 +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK__SHIFT 0x1 +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK_MASK 0x00000001L +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK_MASK 0x00000002L + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +//MMVM_L2_CNTL +#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//MMVM_L2_CNTL2 +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//MMVM_L2_CNTL3 +#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//MMVM_L2_STATUS +#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//MMVM_DUMMY_PAGE_FAULT_CNTL +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_INVALIDATE_CNTL +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//MMVM_L2_PROTECTION_FAULT_CNTL +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//MMVM_L2_PROTECTION_FAULT_CNTL2 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//MMVM_L2_PROTECTION_FAULT_MM_CNTL3 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_MM_CNTL4 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_STATUS +#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d +#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L +//MMVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//MMVM_L2_CNTL4 +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//MMVM_L2_MM_GROUP_RT_CLASSES +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID2 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_CACHE_PARITY_CNTL +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//MMVM_L2_CGTT_CLK_CTRL +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMVM_L2_CNTL5 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L +//MMVM_L2_GCR_CNTL +#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//MMVM_L2_CGTT_BUSY_CTRL +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMVM_L2_PTE_CACHE_DUMP_CNTL +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//MMVM_L2_PTE_CACHE_DUMP_READ +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//MMVM_L2_BANK_SELECT_MASKS +#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +//MMVM_CONTEXT0_CNTL +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT1_CNTL +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT2_CNTL +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT3_CNTL +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT4_CNTL +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT5_CNTL +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT6_CNTL +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT7_CNTL +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT8_CNTL +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT9_CNTL +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT10_CNTL +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT11_CNTL +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT12_CNTL +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT13_CNTL +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT14_CNTL +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXT15_CNTL +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//MMVM_CONTEXTS_DISABLE +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//MMVM_INVALIDATE_ENG0_SEM +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG1_SEM +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG2_SEM +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG3_SEM +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG4_SEM +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG5_SEM +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG6_SEM +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG7_SEM +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG8_SEM +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG9_SEM +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG10_SEM +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG11_SEM +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG12_SEM +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG13_SEM +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG14_SEM +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG15_SEM +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG16_SEM +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG17_SEM +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG0_REQ +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG1_REQ +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG2_REQ +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG3_REQ +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG4_REQ +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG5_REQ +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG6_REQ +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG7_REQ +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG8_REQ +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG9_REQ +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG10_REQ +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG11_REQ +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG12_REQ +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG13_REQ +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG14_REQ +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG15_REQ +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG16_REQ +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG17_REQ +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG0_ACK +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG1_ACK +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG2_ACK +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG3_ACK +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG4_ACK +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG5_ACK +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG6_ACK +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG7_ACK +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG8_ACK +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG9_ACK +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG10_ACK +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG11_ACK +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG12_ACK +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG13_ACK +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG14_ACK +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG15_ACK +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG16_ACK +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG17_ACK +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +//MMMC_VM_L2_PERFCOUNTER0_CFG +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER1_CFG +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER2_CFG +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER3_CFG +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER4_CFG +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER5_CFG +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER6_CFG +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER7_CFG +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMUTCL2_PERFCOUNTER0_CFG +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER1_CFG +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER2_CFG +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER3_CFG +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER_RSLT_CNTL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +//MMMC_VM_L2_PERFCOUNTER_LO +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_L2_PERFCOUNTER_HI +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMUTCL2_PERFCOUNTER_LO +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMUTCL2_PERFCOUNTER_HI +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +//MMMC_VM_FB_SIZE_OFFSET_VF0 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF1 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF2 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF3 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF4 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF5 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF6 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF7 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF8 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF9 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF10 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF11 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF12 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF13 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF14 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF15 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +//MMMC_VM_FB_OFFSET +#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MMMC_VM_STEERING +#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MMMC_MEM_POWER_LS +#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_APT_CNTL +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +//MMMC_VM_LOCAL_FB_ADDRESS_START +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_END +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//MMUTCL2_CGTT_CLK_CTRL +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMUTCL2_CGTT_BUSY_CTRL +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMMC_VM_FB_NOALLOC_CNTL +#define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 +#define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT 0x2 +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT 0x3 +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT 0x4 +#define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L +#define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK 0x00000004L +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK 0x00000008L +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK 0x00000010L +//MMUTCL2_HARVEST_BYPASS_GROUPS +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL +//MMUTCL2_GROUP_RET_FAULT_STATUS +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +//MMMC_VM_FB_LOCATION_BASE +#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MMMC_VM_FB_LOCATION_TOP +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_TOP +#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BOT +#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BASE +#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_MX_L1_TLB_CNTL +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec +//MM_ATC_L2_PERFCOUNTER_LO +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MM_ATC_L2_PERFCOUNTER_HI +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec +//MM_ATC_L2_PERFCOUNTER0_CFG +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER1_CFG +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +//MMUTCL2_TRANSLATION_BYPASS_BY_VMID +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L +//MMUTC_TRANSLATION_FAULT_CNTL0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL +//MMUTC_TRANSLATION_FAULT_CNTL1 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L +//MMUTCL2_FFBM_ENABLE_CNTL +#define MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM__SHIFT 0x0 +#define MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mml2tlbpspdec +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pspdec +//MM_ATC_L2_IOV_MODE_CNTL +#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT 0x0 +#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mml2tlbpfdec +//MML2TLB_TLB0_STATUS +#define MML2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 +#define MML2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L +//MML2TLB_TMZ_CNTL +#define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0 +#define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L +//MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L + + +// addressBlock: mmhub_mmutcl2_mml2tlbpldec +//MML2TLB_PERFCOUNTER0_CFG +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER1_CFG +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER2_CFG +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER3_CFG +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MML2TLB_PERFCOUNTER_RSLT_CNTL +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mml2tlbprdec +//MML2TLB_PERFCOUNTER_LO +#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MML2TLB_PERFCOUNTER_HI +#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + +#endif diff --git a/extra/amdpci/headers/mp_11_0_offset.h b/extra/amdpci/headers/mp_11_0_offset.h new file mode 100644 index 0000000000..da6d380c94 --- /dev/null +++ b/extra/amdpci/headers/mp_11_0_offset.h @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _mp_11_0_2_OFFSET_HEADER +#define _mp_11_0_2_OFFSET_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define mmMP0_SMN_C2PMSG_32 0x0060 +#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_33 0x0061 +#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_34 0x0062 +#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_35 0x0063 +#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_36 0x0064 +#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_37 0x0065 +#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_38 0x0066 +#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_39 0x0067 +#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_40 0x0068 +#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_41 0x0069 +#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_42 0x006a +#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_43 0x006b +#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_44 0x006c +#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_45 0x006d +#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_46 0x006e +#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_47 0x006f +#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_48 0x0070 +#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_49 0x0071 +#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_50 0x0072 +#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_51 0x0073 +#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_52 0x0074 +#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_53 0x0075 +#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_54 0x0076 +#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_55 0x0077 +#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_56 0x0078 +#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_57 0x0079 +#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_58 0x007a +#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_59 0x007b +#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_60 0x007c +#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_61 0x007d +#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_62 0x007e +#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_63 0x007f +#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_64 0x0080 +#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_65 0x0081 +#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_66 0x0082 +#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_67 0x0083 +#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_68 0x0084 +#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_69 0x0085 +#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_70 0x0086 +#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_71 0x0087 +#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_72 0x0088 +#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_73 0x0089 +#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_74 0x008a +#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_75 0x008b +#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_76 0x008c +#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_77 0x008d +#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_78 0x008e +#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_79 0x008f +#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_80 0x0090 +#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_81 0x0091 +#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_82 0x0092 +#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_83 0x0093 +#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_84 0x0094 +#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_85 0x0095 +#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_86 0x0096 +#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_87 0x0097 +#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_88 0x0098 +#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_89 0x0099 +#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_90 0x009a +#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_91 0x009b +#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_92 0x009c +#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_93 0x009d +#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_94 0x009e +#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_95 0x009f +#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_96 0x00a0 +#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_97 0x00a1 +#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_98 0x00a2 +#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_99 0x00a3 +#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_100 0x00a4 +#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_101 0x00a5 +#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_102 0x00a6 +#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_103 0x00a7 +#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0 +#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmMP0_SMN_IH_CREDIT 0x00c1 +#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT 0x00c2 +#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define mmMP1_SMN_C2PMSG_32 0x0260 +#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_33 0x0261 +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_34 0x0262 +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_35 0x0263 +#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_36 0x0264 +#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_37 0x0265 +#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_38 0x0266 +#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_39 0x0267 +#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_40 0x0268 +#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_41 0x0269 +#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_42 0x026a +#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_43 0x026b +#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_44 0x026c +#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_45 0x026d +#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_46 0x026e +#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_47 0x026f +#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_48 0x0270 +#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_49 0x0271 +#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_50 0x0272 +#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_51 0x0273 +#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_52 0x0274 +#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_53 0x0275 +#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_54 0x0276 +#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_55 0x0277 +#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_56 0x0278 +#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_57 0x0279 +#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_58 0x027a +#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_59 0x027b +#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_60 0x027c +#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_61 0x027d +#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_62 0x027e +#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_63 0x027f +#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_64 0x0280 +#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_65 0x0281 +#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_67 0x0283 +#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_68 0x0284 +#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_69 0x0285 +#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_70 0x0286 +#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_71 0x0287 +#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_72 0x0288 +#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_73 0x0289 +#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_74 0x028a +#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_75 0x028b +#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_76 0x028c +#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_77 0x028d +#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_78 0x028e +#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_79 0x028f +#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_80 0x0290 +#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_81 0x0291 +#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_83 0x0293 +#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_84 0x0294 +#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_85 0x0295 +#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_86 0x0296 +#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_87 0x0297 +#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_88 0x0298 +#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_89 0x0299 +#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_91 0x029b +#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_92 0x029c +#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_93 0x029d +#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_94 0x029e +#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_95 0x029f +#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_96 0x02a0 +#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_97 0x02a1 +#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_98 0x02a2 +#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_99 0x02a3 +#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_100 0x02a4 +#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_101 0x02a5 +#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_102 0x02a6 +#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_103 0x02a7 +#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0 +#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmMP1_SMN_IH_CREDIT 0x02c1 +#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT 0x02c2 +#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define mmMP1_SMN_FPS_CNT 0x02c4 +#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 +#define mmMP1_SMN_PUB_CTRL 0x02c5 +#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH0 0x03c0 +#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH1 0x03c1 +#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH2 0x03c2 +#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH3 0x03c3 +#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH4 0x03c4 +#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH5 0x03c5 +#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH6 0x03c6 +#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH7 0x03c7 +#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 + +/* + * addressBlock: mp_SmuMp1Pub_MmuDec + * base address: 0x0 + */ +#define smnMP1_PMI_3_START 0x3030204 +#define smnMP1_PMI_3_FIFO 0x3030208 +#define smnMP1_PMI_3 0x3030600 + +#endif diff --git a/extra/amdpci/headers/mp_11_0_sh_mask.h b/extra/amdpci/headers/mp_11_0_sh_mask.h new file mode 100644 index 0000000000..a5ae2a8012 --- /dev/null +++ b/extra/amdpci/headers/mp_11_0_sh_mask.h @@ -0,0 +1,975 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _mp_11_0_2_SH_MASK_HEADER +#define _mp_11_0_2_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_ACTIVE_FCN_ID +#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_SMN_IH_SW_INT_CTRL +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +//MP1_PUB_SCRATCH0 +#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH1 +#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH2 +#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH3 +#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_C2PMSG_0 +#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_1 +#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_2 +#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_3 +#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_4 +#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_5 +#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_6 +#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_7 +#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_8 +#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_9 +#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_10 +#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_11 +#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_12 +#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_13 +#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_14 +#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_15 +#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_16 +#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_17 +#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_18 +#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_19 +#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_20 +#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_21 +#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_22 +#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_23 +#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_24 +#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_25 +#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_26 +#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_27 +#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_28 +#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_29 +#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_30 +#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_31 +#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_0 +#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_1 +#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_2 +#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_3 +#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_INTEN +#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 +#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +//MP1_P2CMSG_INTSTS +#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_P2SMSG_0 +#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_1 +#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_2 +#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_3 +#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_INTSTS +#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_S2PMSG_0 +#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_32 +#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_33 +#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_34 +#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_35 +#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_36 +#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_37 +#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_38 +#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_39 +#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_40 +#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_41 +#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_42 +#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_43 +#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_44 +#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_45 +#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_46 +#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_47 +#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_48 +#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_49 +#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_50 +#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_51 +#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_52 +#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_53 +#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_54 +#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_55 +#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_56 +#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_57 +#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_58 +#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_59 +#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_60 +#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_61 +#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_62 +#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_63 +#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_64 +#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_65 +#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_66 +#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_67 +#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_68 +#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_69 +#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_70 +#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_71 +#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_72 +#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_73 +#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_74 +#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_75 +#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_76 +#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_77 +#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_78 +#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_79 +#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_80 +#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_81 +#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_82 +#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_83 +#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_84 +#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_85 +#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_86 +#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_87 +#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_88 +#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_89 +#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_90 +#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_91 +#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_92 +#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_93 +#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_94 +#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_95 +#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_96 +#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_97 +#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_98 +#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_99 +#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_100 +#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_101 +#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_102 +#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_103 +#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_ACTIVE_FCN_ID +#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP1_IH_CREDIT +#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_IH_SW_INT +#define MP1_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_IH_SW_INT_CTRL +#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_FPS_CNT +#define MP1_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_PUB_CTRL +#define MP1_PUB_CTRL__RESET__SHIFT 0x0 +#define MP1_PUB_CTRL__RESET_MASK 0x00000001L +//MP1_EXT_SCRATCH0 +#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH1 +#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH2 +#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH3 +#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH4 +#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH5 +#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH6 +#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH7 +#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_ACTIVE_FCN_ID +#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_PUB_CTRL +#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 +#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL + +// MP1_PMI_3_START +#define MP1_PMI_3_START__ENABLE_MASK 0x80000000L +// MP1_PMI_3_FIFO +#define MP1_PMI_3_FIFO__DEPTH_MASK 0x00000fffL + +// MP1_PMI_3_START +#define MP1_PMI_3_START__ENABLE__SHIFT 0x0000001f +// MP1_PMI_3_FIFO +#define MP1_PMI_3_FIFO__DEPTH__SHIFT 0x00000000 + + + + +#endif diff --git a/extra/amdpci/headers/mp_13_0_0_offset.h b/extra/amdpci/headers/mp_13_0_0_offset.h new file mode 100644 index 0000000000..130fa1393b --- /dev/null +++ b/extra/amdpci/headers/mp_13_0_0_offset.h @@ -0,0 +1,461 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mp_13_0_0_OFFSET_HEADER +#define _mp_13_0_0_OFFSET_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define regMP0_SMN_C2PMSG_32 0x0060 +#define regMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_33 0x0061 +#define regMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_34 0x0062 +#define regMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_35 0x0063 +#define regMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_36 0x0064 +#define regMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_37 0x0065 +#define regMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_38 0x0066 +#define regMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_39 0x0067 +#define regMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_40 0x0068 +#define regMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_41 0x0069 +#define regMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_42 0x006a +#define regMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_43 0x006b +#define regMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_44 0x006c +#define regMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_45 0x006d +#define regMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_46 0x006e +#define regMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_47 0x006f +#define regMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_48 0x0070 +#define regMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_49 0x0071 +#define regMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_50 0x0072 +#define regMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_51 0x0073 +#define regMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_52 0x0074 +#define regMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_53 0x0075 +#define regMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_54 0x0076 +#define regMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_55 0x0077 +#define regMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_56 0x0078 +#define regMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_57 0x0079 +#define regMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_58 0x007a +#define regMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_59 0x007b +#define regMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_60 0x007c +#define regMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_61 0x007d +#define regMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_62 0x007e +#define regMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_63 0x007f +#define regMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_64 0x0080 +#define regMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_65 0x0081 +#define regMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_66 0x0082 +#define regMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_67 0x0083 +#define regMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_68 0x0084 +#define regMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_69 0x0085 +#define regMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_70 0x0086 +#define regMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_71 0x0087 +#define regMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_72 0x0088 +#define regMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_73 0x0089 +#define regMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_74 0x008a +#define regMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_75 0x008b +#define regMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_76 0x008c +#define regMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_77 0x008d +#define regMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_78 0x008e +#define regMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_79 0x008f +#define regMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_80 0x0090 +#define regMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_81 0x0091 +#define regMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_82 0x0092 +#define regMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_83 0x0093 +#define regMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_84 0x0094 +#define regMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_85 0x0095 +#define regMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_86 0x0096 +#define regMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_87 0x0097 +#define regMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_88 0x0098 +#define regMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_89 0x0099 +#define regMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_90 0x009a +#define regMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_91 0x009b +#define regMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_92 0x009c +#define regMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_93 0x009d +#define regMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_94 0x009e +#define regMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_95 0x009f +#define regMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_96 0x00a0 +#define regMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_97 0x00a1 +#define regMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_98 0x00a2 +#define regMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_99 0x00a3 +#define regMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_100 0x00a4 +#define regMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_101 0x00a5 +#define regMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_102 0x00a6 +#define regMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_103 0x00a7 +#define regMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define regMP0_SMN_IH_CREDIT 0x00c1 +#define regMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define regMP0_SMN_IH_SW_INT 0x00c2 +#define regMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define regMP1_SMN_C2PMSG_32 0x0260 +#define regMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_33 0x0261 +#define regMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_34 0x0262 +#define regMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_35 0x0263 +#define regMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_36 0x0264 +#define regMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_37 0x0265 +#define regMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_38 0x0266 +#define regMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_39 0x0267 +#define regMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_40 0x0268 +#define regMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_41 0x0269 +#define regMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_42 0x026a +#define regMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_43 0x026b +#define regMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_44 0x026c +#define regMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_45 0x026d +#define regMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_46 0x026e +#define regMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_47 0x026f +#define regMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_48 0x0270 +#define regMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_49 0x0271 +#define regMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_50 0x0272 +#define regMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_51 0x0273 +#define regMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_52 0x0274 +#define regMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_53 0x0275 +#define regMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_54 0x0276 +#define regMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_55 0x0277 +#define regMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_56 0x0278 +#define regMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_57 0x0279 +#define regMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_58 0x027a +#define regMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_59 0x027b +#define regMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_60 0x027c +#define regMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_61 0x027d +#define regMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_62 0x027e +#define regMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_63 0x027f +#define regMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_64 0x0280 +#define regMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_65 0x0281 +#define regMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_66 0x0282 +#define regMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_67 0x0283 +#define regMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_68 0x0284 +#define regMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_69 0x0285 +#define regMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_70 0x0286 +#define regMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_71 0x0287 +#define regMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_72 0x0288 +#define regMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_73 0x0289 +#define regMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_74 0x028a +#define regMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_75 0x028b +#define regMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_76 0x028c +#define regMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_77 0x028d +#define regMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_78 0x028e +#define regMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_79 0x028f +#define regMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_80 0x0290 +#define regMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_81 0x0291 +#define regMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_82 0x0292 +#define regMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_83 0x0293 +#define regMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_84 0x0294 +#define regMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_85 0x0295 +#define regMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_86 0x0296 +#define regMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_87 0x0297 +#define regMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_88 0x0298 +#define regMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_89 0x0299 +#define regMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_90 0x029a +#define regMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_91 0x029b +#define regMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_92 0x029c +#define regMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_93 0x029d +#define regMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_94 0x029e +#define regMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_95 0x029f +#define regMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_96 0x02a0 +#define regMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_97 0x02a1 +#define regMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_98 0x02a2 +#define regMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_99 0x02a3 +#define regMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_100 0x02a4 +#define regMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_101 0x02a5 +#define regMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_102 0x02a6 +#define regMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_103 0x02a7 +#define regMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_104 0x02a8 +#define regMP1_SMN_C2PMSG_104_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_105 0x02a9 +#define regMP1_SMN_C2PMSG_105_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_106 0x02aa +#define regMP1_SMN_C2PMSG_106_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_107 0x02ab +#define regMP1_SMN_C2PMSG_107_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_108 0x02ac +#define regMP1_SMN_C2PMSG_108_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_109 0x02ad +#define regMP1_SMN_C2PMSG_109_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_110 0x02ae +#define regMP1_SMN_C2PMSG_110_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_111 0x02af +#define regMP1_SMN_C2PMSG_111_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_112 0x02b0 +#define regMP1_SMN_C2PMSG_112_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_113 0x02b1 +#define regMP1_SMN_C2PMSG_113_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_114 0x02b2 +#define regMP1_SMN_C2PMSG_114_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_115 0x02b3 +#define regMP1_SMN_C2PMSG_115_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_116 0x02b4 +#define regMP1_SMN_C2PMSG_116_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_117 0x02b5 +#define regMP1_SMN_C2PMSG_117_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_118 0x02b6 +#define regMP1_SMN_C2PMSG_118_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_119 0x02b7 +#define regMP1_SMN_C2PMSG_119_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_120 0x02b8 +#define regMP1_SMN_C2PMSG_120_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_121 0x02b9 +#define regMP1_SMN_C2PMSG_121_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_122 0x02ba +#define regMP1_SMN_C2PMSG_122_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_123 0x02bb +#define regMP1_SMN_C2PMSG_123_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_124 0x02bc +#define regMP1_SMN_C2PMSG_124_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_125 0x02bd +#define regMP1_SMN_C2PMSG_125_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_126 0x02be +#define regMP1_SMN_C2PMSG_126_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_127 0x02bf +#define regMP1_SMN_C2PMSG_127_BASE_IDX 0 +#define regMP1_SMN_IH_CREDIT 0x02c1 +#define regMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT 0x02c2 +#define regMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define regMP1_SMN_FPS_CNT 0x02c4 +#define regMP1_SMN_FPS_CNT_BASE_IDX 0 +#define regMP1_SMN_PUB_CTRL 0x02c5 +#define regMP1_SMN_PUB_CTRL_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH0 0x0340 +#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH1 0x0341 +#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH2 0x0342 +#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH3 0x0343 +#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH4 0x0344 +#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH5 0x0345 +#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH6 0x0346 +#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH7 0x0347 +#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH8 0x0348 +#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH10 0x034a +#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH11 0x034b +#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH12 0x034c +#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH13 0x034d +#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH14 0x034e +#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH15 0x034f +#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH16 0x0350 +#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH17 0x0351 +#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH18 0x0352 +#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH19 0x0353 +#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH20 0x0354 +#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH21 0x0355 +#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH22 0x0356 +#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH23 0x0357 +#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH24 0x0358 +#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH25 0x0359 +#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH26 0x035a +#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH27 0x035b +#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH28 0x035c +#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH29 0x035d +#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH30 0x035e +#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH31 0x035f +#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1Pub_CruDec +// base address: 0x0 +#define regMP1_FIRMWARE_FLAGS 0xbee009 +#define regMP1_FIRMWARE_FLAGS_BASE_IDX 0 + + +// addressBlock: mp_SmuMpIOPub_CruDec +// base address: 0x0 +#define regMPIO_FIRMWARE_FLAGS 0xbee009 +#define regMPIO_FIRMWARE_FLAGS_BASE_IDX 0 + + +#endif diff --git a/extra/amdpci/headers/mp_13_0_0_sh_mask.h b/extra/amdpci/headers/mp_13_0_0_sh_mask.h new file mode 100644 index 0000000000..38ad6e7a1c --- /dev/null +++ b/extra/amdpci/headers/mp_13_0_0_sh_mask.h @@ -0,0 +1,682 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mp_13_0_0_SH_MASK_HEADER +#define _mp_13_0_0_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_SMN_IH_SW_INT_CTRL +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_104 +#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_105 +#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_106 +#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_107 +#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_108 +#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_109 +#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_110 +#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_111 +#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_112 +#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_113 +#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_114 +#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_115 +#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_116 +#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_117 +#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_118 +#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_119 +#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_120 +#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_121 +#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_122 +#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_123 +#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_124 +#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_125 +#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_126 +#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_127 +#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_PUB_CTRL +#define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT 0x0 +#define MP1_SMN_PUB_CTRL__LX3_RESET_MASK 0x00000001L +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH8 +#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH10 +#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH11 +#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH12 +#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH13 +#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH14 +#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH15 +#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH16 +#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH17 +#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH18 +#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH19 +#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH20 +#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH21 +#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH22 +#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH23 +#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH24 +#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH25 +#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH26 +#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH27 +#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH28 +#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH29 +#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH30 +#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH31 +#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: mp_SmuMpIOPub_CruDec +//MPIO_FIRMWARE_FLAGS +#define MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MPIO_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +#endif diff --git a/extra/amdpci/headers/nbio_4_3_0_offset.h b/extra/amdpci/headers/nbio_4_3_0_offset.h new file mode 100644 index 0000000000..4b489d64de --- /dev/null +++ b/extra/amdpci/headers/nbio_4_3_0_offset.h @@ -0,0 +1,17381 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_4_3_0_OFFSET_HEADER +#define _nbio_4_3_0_OFFSET_HEADER + + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +// base address: 0x0 +#define regBIF_BX0_PCIE_INDEX 0x000c +#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA 0x000d +#define regBIF_BX0_PCIE_DATA_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2 0x000e +#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA2 0x000f +#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX_HI 0x0010 +#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2_HI 0x0011 +#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 +#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 +#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 +#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 +#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 +#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_0 0x0038 +#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_1 0x0039 +#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_2 0x003a +#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_4 0x003c +#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_5 0x003d +#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_7 0x003f +#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_8 0x0040 +#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_9 0x0041 +#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_10 0x0042 +#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_11 0x0043 +#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_12 0x0044 +#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_13 0x0045 +#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_14 0x0046 +#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_15 0x0047 +#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c +#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d +#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e +#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 +#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 +#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 +#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 +#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 +#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 +#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 +#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 +#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 +#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 +#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a +#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b +#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c +#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d +#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e +#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f +#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_0 0x0090 +#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_1 0x0091 +#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_2 0x0092 +#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_3 0x0093 +#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_4 0x0094 +#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_5 0x0095 +#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_6 0x0096 +#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_7 0x0097 +#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_8 0x0098 +#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_9 0x0099 +#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_10 0x009a +#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_11 0x009b +#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_12 0x009c +#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_13 0x009d +#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_14 0x009e +#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_15 0x009f +#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 +#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 +#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 +#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 +#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 +#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 +#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 +#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 +#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 +#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 +#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa +#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab +#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0040 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0042 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0043 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0044 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0045 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0046 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0047 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0049 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004c +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004d +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x004f +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0050 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0052 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0053 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0055 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0056 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0057 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0058 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0059 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_PF0_MM_INDEX 0x0000 +#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_PF0_MM_DATA 0x0001 +#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_PF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 +#define regBIF_BX_PF0_RSMU_INDEX 0x0000 +#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_DATA 0x0001 +#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 +#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x0 +#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 +#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BUS_CNTL 0x00e7 +#define regBIF_BX0_BUS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH0 0x00e8 +#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH1 0x00e9 +#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_EN 0x00ed +#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 +#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee +#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_CNTL 0x00f0 +#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL 0x00f1 +#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 +#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 +#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 +#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd +#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FB_EN 0x0100 +#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_BIF_INTR_CNTL 0x0101 +#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_MEM_TYPE_CNTL 0x0111 +#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_CNTL 0x012f +#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_BASE 0x0130 +#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_RPTR 0x0131 +#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR 0x0132 +#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 +#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_RESET_EN 0x0088 +#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c +#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 +#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 +#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca +#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 +#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 +#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 +#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 +#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 +#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 +#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 +#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x000d +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0010 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0011 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0012 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0013 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0014 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0015 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0016 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0017 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0018 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0019 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x001a +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001b +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001c +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001d +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001e +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 0x001f +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0020 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0021 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0022 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0023 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0024 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0025 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0031 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0032 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0033 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 0x0034 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0035 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0036 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 0x0037 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0038 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x0039 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003b +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003c +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +// base address: 0x3480 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +// base address: 0x0 +#define regGDC0_SHUB_REGS_IF_CTL 0x01c3 +#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2 +#define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x01cf +#define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2 +#define regGDC0_ATDMA_MISC_CNTL 0x01dd +#define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 2 +#define regGDC0_S2A_MISC_CNTL 0x01df +#define regGDC0_S2A_MISC_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +// base address: 0xfffe00000000 +#define cfgPSWUSCFG0_0_VENDOR_ID 0xfffe00000000 +#define cfgPSWUSCFG0_0_DEVICE_ID 0xfffe00000002 +#define cfgPSWUSCFG0_0_COMMAND 0xfffe00000004 +#define cfgPSWUSCFG0_0_STATUS 0xfffe00000006 +#define cfgPSWUSCFG0_0_REVISION_ID 0xfffe00000008 +#define cfgPSWUSCFG0_0_PROG_INTERFACE 0xfffe00000009 +#define cfgPSWUSCFG0_0_SUB_CLASS 0xfffe0000000a +#define cfgPSWUSCFG0_0_BASE_CLASS 0xfffe0000000b +#define cfgPSWUSCFG0_0_CACHE_LINE 0xfffe0000000c +#define cfgPSWUSCFG0_0_LATENCY 0xfffe0000000d +#define cfgPSWUSCFG0_0_HEADER 0xfffe0000000e +#define cfgPSWUSCFG0_0_BIST 0xfffe0000000f +#define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY 0xfffe00000018 +#define cfgPSWUSCFG0_0_IO_BASE_LIMIT 0xfffe0000001c +#define cfgPSWUSCFG0_0_SECONDARY_STATUS 0xfffe0000001e +#define cfgPSWUSCFG0_0_MEM_BASE_LIMIT 0xfffe00000020 +#define cfgPSWUSCFG0_0_PREF_BASE_LIMIT 0xfffe00000024 +#define cfgPSWUSCFG0_0_PREF_BASE_UPPER 0xfffe00000028 +#define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER 0xfffe0000002c +#define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI 0xfffe00000030 +#define cfgPSWUSCFG0_0_CAP_PTR 0xfffe00000034 +#define cfgPSWUSCFG0_0_ROM_BASE_ADDR 0xfffe00000038 +#define cfgPSWUSCFG0_0_INTERRUPT_LINE 0xfffe0000003c +#define cfgPSWUSCFG0_0_INTERRUPT_PIN 0xfffe0000003d +#define cfgPSWUSCFG0_0_VENDOR_CAP_LIST 0xfffe00000048 +#define cfgPSWUSCFG0_0_ADAPTER_ID_W 0xfffe0000004c +#define cfgPSWUSCFG0_0_PMI_CAP_LIST 0xfffe00000050 +#define cfgPSWUSCFG0_0_PMI_CAP 0xfffe00000052 +#define cfgPSWUSCFG0_0_PMI_STATUS_CNTL 0xfffe00000054 +#define cfgPSWUSCFG0_0_PCIE_CAP_LIST 0xfffe00000058 +#define cfgPSWUSCFG0_0_PCIE_CAP 0xfffe0000005a +#define cfgPSWUSCFG0_0_DEVICE_CAP 0xfffe0000005c +#define cfgPSWUSCFG0_0_DEVICE_CNTL 0xfffe00000060 +#define cfgPSWUSCFG0_0_DEVICE_STATUS 0xfffe00000062 +#define cfgPSWUSCFG0_0_LINK_CAP 0xfffe00000064 +#define cfgPSWUSCFG0_0_LINK_CNTL 0xfffe00000068 +#define cfgPSWUSCFG0_0_LINK_STATUS 0xfffe0000006a +#define cfgPSWUSCFG0_0_DEVICE_CAP2 0xfffe0000007c +#define cfgPSWUSCFG0_0_DEVICE_CNTL2 0xfffe00000080 +#define cfgPSWUSCFG0_0_DEVICE_STATUS2 0xfffe00000082 +#define cfgPSWUSCFG0_0_LINK_CAP2 0xfffe00000084 +#define cfgPSWUSCFG0_0_LINK_CNTL2 0xfffe00000088 +#define cfgPSWUSCFG0_0_LINK_STATUS2 0xfffe0000008a +#define cfgPSWUSCFG0_0_MSI_CAP_LIST 0xfffe000000a0 +#define cfgPSWUSCFG0_0_MSI_MSG_CNTL 0xfffe000000a2 +#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO 0xfffe000000a4 +#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI 0xfffe000000a8 +#define cfgPSWUSCFG0_0_MSI_MSG_DATA 0xfffe000000a8 +#define cfgPSWUSCFG0_0_MSI_MSG_DATA_64 0xfffe000000ac +#define cfgPSWUSCFG0_0_SSID_CAP_LIST 0xfffe000000c0 +#define cfgPSWUSCFG0_0_SSID_CAP 0xfffe000000c4 +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe00000100 +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe00000104 +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 0xfffe00000108 +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 0xfffe0000010c +#define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST 0xfffe00000110 +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 0xfffe00000114 +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 0xfffe00000118 +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL 0xfffe0000011c +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS 0xfffe0000011e +#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP 0xfffe00000120 +#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL 0xfffe00000124 +#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS 0xfffe0000012a +#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP 0xfffe0000012c +#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL 0xfffe00000130 +#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS 0xfffe00000136 +#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe00000140 +#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe00000144 +#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe00000148 +#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe00000150 +#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS 0xfffe00000154 +#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK 0xfffe00000158 +#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe0000015c +#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS 0xfffe00000160 +#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK 0xfffe00000164 +#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe00000168 +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG0 0xfffe0000016c +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG1 0xfffe00000170 +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG2 0xfffe00000174 +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG3 0xfffe00000178 +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 0xfffe00000188 +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 0xfffe0000018c +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 0xfffe00000190 +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 0xfffe00000194 +#define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe00000270 +#define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3 0xfffe00000274 +#define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS 0xfffe00000278 +#define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe0000027c +#define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe0000027e +#define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe00000280 +#define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe00000282 +#define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe00000284 +#define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe00000286 +#define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe00000288 +#define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe0000028a +#define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe0000028c +#define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe0000028e +#define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe00000290 +#define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe00000292 +#define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe00000294 +#define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe00000296 +#define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe00000298 +#define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe0000029a +#define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST 0xfffe000002a0 +#define cfgPSWUSCFG0_0_PCIE_ACS_CAP 0xfffe000002a4 +#define cfgPSWUSCFG0_0_PCIE_ACS_CNTL 0xfffe000002a6 +#define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST 0xfffe000002f0 +#define cfgPSWUSCFG0_0_PCIE_MC_CAP 0xfffe000002f4 +#define cfgPSWUSCFG0_0_PCIE_MC_CNTL 0xfffe000002f6 +#define cfgPSWUSCFG0_0_PCIE_MC_ADDR0 0xfffe000002f8 +#define cfgPSWUSCFG0_0_PCIE_MC_ADDR1 0xfffe000002fc +#define cfgPSWUSCFG0_0_PCIE_MC_RCV0 0xfffe00000300 +#define cfgPSWUSCFG0_0_PCIE_MC_RCV1 0xfffe00000304 +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 0xfffe00000308 +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 0xfffe0000030c +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe00000310 +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe00000314 +#define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST 0xfffe00000320 +#define cfgPSWUSCFG0_0_PCIE_LTR_CAP 0xfffe00000324 +#define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe00000328 +#define cfgPSWUSCFG0_0_PCIE_ARI_CAP 0xfffe0000032c +#define cfgPSWUSCFG0_0_PCIE_ARI_CNTL 0xfffe0000032e +#define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST 0xfffe00000400 +#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP 0xfffe00000404 +#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS 0xfffe00000408 +#define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe00000410 +#define cfgPSWUSCFG0_0_LINK_CAP_16GT 0xfffe00000414 +#define cfgPSWUSCFG0_0_LINK_CNTL_16GT 0xfffe00000418 +#define cfgPSWUSCFG0_0_LINK_STATUS_16GT 0xfffe0000041c +#define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe00000420 +#define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe00000424 +#define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe00000428 +#define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe00000430 +#define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe00000431 +#define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe00000432 +#define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe00000433 +#define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe00000434 +#define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe00000435 +#define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe00000436 +#define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe00000437 +#define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe00000438 +#define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe00000439 +#define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe0000043a +#define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe0000043b +#define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe0000043c +#define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe0000043d +#define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe0000043e +#define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe0000043f +#define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe00000440 +#define cfgPSWUSCFG0_0_MARGINING_PORT_CAP 0xfffe00000444 +#define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS 0xfffe00000446 +#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL 0xfffe00000448 +#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS 0xfffe0000044a +#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL 0xfffe0000044c +#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS 0xfffe0000044e +#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL 0xfffe00000450 +#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS 0xfffe00000452 +#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL 0xfffe00000454 +#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS 0xfffe00000456 +#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL 0xfffe00000458 +#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS 0xfffe0000045a +#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL 0xfffe0000045c +#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS 0xfffe0000045e +#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL 0xfffe00000460 +#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS 0xfffe00000462 +#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL 0xfffe00000464 +#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS 0xfffe00000466 +#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL 0xfffe00000468 +#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS 0xfffe0000046a +#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL 0xfffe0000046c +#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS 0xfffe0000046e +#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL 0xfffe00000470 +#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS 0xfffe00000472 +#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL 0xfffe00000474 +#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS 0xfffe00000476 +#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL 0xfffe00000478 +#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS 0xfffe0000047a +#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL 0xfffe0000047c +#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS 0xfffe0000047e +#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL 0xfffe00000480 +#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS 0xfffe00000482 +#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL 0xfffe00000484 +#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS 0xfffe00000486 +#define cfgPSWUSCFG0_0_LINK_CAP_32GT 0xfffe00000504 +#define cfgPSWUSCFG0_0_LINK_CNTL_32GT 0xfffe00000508 +#define cfgPSWUSCFG0_0_LINK_STATUS_32GT 0xfffe0000050c + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0xfffe10100000 +#define cfgBIF_CFG_DEV0_RC0_VENDOR_ID 0xfffe10100000 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_ID 0xfffe10100002 +#define cfgBIF_CFG_DEV0_RC0_COMMAND 0xfffe10100004 +#define cfgBIF_CFG_DEV0_RC0_STATUS 0xfffe10100006 +#define cfgBIF_CFG_DEV0_RC0_REVISION_ID 0xfffe10100008 +#define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE 0xfffe10100009 +#define cfgBIF_CFG_DEV0_RC0_SUB_CLASS 0xfffe1010000a +#define cfgBIF_CFG_DEV0_RC0_BASE_CLASS 0xfffe1010000b +#define cfgBIF_CFG_DEV0_RC0_CACHE_LINE 0xfffe1010000c +#define cfgBIF_CFG_DEV0_RC0_LATENCY 0xfffe1010000d +#define cfgBIF_CFG_DEV0_RC0_HEADER 0xfffe1010000e +#define cfgBIF_CFG_DEV0_RC0_BIST 0xfffe1010000f +#define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1 0xfffe10100010 +#define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_2 0xfffe10100014 +#define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0xfffe10100018 +#define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0xfffe1010001c +#define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0xfffe1010001e +#define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0xfffe10100020 +#define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0xfffe10100024 +#define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0xfffe10100028 +#define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0xfffe1010002c +#define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0xfffe10100030 +#define cfgBIF_CFG_DEV0_RC0_CAP_PTR 0xfffe10100034 +#define cfgBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0xfffe10100038 +#define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0xfffe1010003c +#define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0xfffe1010003d +#define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0xfffe10100050 +#define cfgBIF_CFG_DEV0_RC0_PMI_CAP 0xfffe10100052 +#define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0xfffe10100054 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0xfffe10100058 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CAP 0xfffe1010005a +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP 0xfffe1010005c +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL 0xfffe10100060 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS 0xfffe10100062 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP 0xfffe10100064 +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL 0xfffe10100068 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS 0xfffe1010006a +#define cfgBIF_CFG_DEV0_RC0_SLOT_CAP 0xfffe1010006c +#define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL 0xfffe10100070 +#define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS 0xfffe10100072 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2 0xfffe1010007c +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0xfffe10100080 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0xfffe10100082 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP2 0xfffe10100084 +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2 0xfffe10100088 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2 0xfffe1010008a +#define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2 0xfffe1010008c +#define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2 0xfffe10100090 +#define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2 0xfffe10100092 +#define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0xfffe101000a0 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0xfffe101000a2 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0xfffe101000a4 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0xfffe101000a8 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0xfffe101000a8 +#define cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0xfffe101000aa +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0xfffe101000ac +#define cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0xfffe101000ae +#define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0xfffe101000c0 +#define cfgBIF_CFG_DEV0_RC0_SSID_CAP 0xfffe101000c4 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10100100 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10100104 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0xfffe10100108 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0xfffe1010010c +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0xfffe10100110 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0xfffe10100114 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0xfffe10100118 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0xfffe1010011c +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0xfffe1010011e +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0xfffe10100120 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0xfffe10100124 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0xfffe1010012a +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0xfffe1010012c +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0xfffe10100130 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0xfffe10100136 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10100140 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10100144 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10100148 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10100150 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0xfffe10100154 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0xfffe10100158 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1010015c +#define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0xfffe10100160 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0xfffe10100164 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10100168 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0xfffe1010016c +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0xfffe10100170 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0xfffe10100174 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0xfffe10100178 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0xfffe10100188 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0xfffe1010018c +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0xfffe10100190 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0xfffe10100194 +#define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10100270 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0xfffe10100274 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0xfffe10100278 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1010027c +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1010027e +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10100280 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10100282 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10100284 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10100286 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10100288 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1010028a +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1010028c +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1010028e +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10100290 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10100292 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10100294 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10100296 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10100298 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1010029a +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0xfffe101002a0 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0xfffe101002a4 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0xfffe101002a6 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0xfffe10100400 +#define cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0xfffe10100404 +#define cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0xfffe10100408 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10100410 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0xfffe10100414 +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0xfffe10100418 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0xfffe1010041c +#define cfgBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10100420 +#define cfgBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10100424 +#define cfgBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10100428 +#define cfgBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10100430 +#define cfgBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10100431 +#define cfgBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10100432 +#define cfgBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10100433 +#define cfgBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10100434 +#define cfgBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10100435 +#define cfgBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10100436 +#define cfgBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10100437 +#define cfgBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10100438 +#define cfgBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10100439 +#define cfgBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1010043a +#define cfgBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1010043b +#define cfgBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1010043c +#define cfgBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1010043d +#define cfgBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1010043e +#define cfgBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1010043f +#define cfgBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10100450 +#define cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0xfffe10100454 +#define cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0xfffe10100456 +#define cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0xfffe10100458 +#define cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0xfffe1010045a +#define cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0xfffe1010045c +#define cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0xfffe1010045e +#define cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0xfffe10100460 +#define cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0xfffe10100462 +#define cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0xfffe10100464 +#define cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0xfffe10100466 +#define cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0xfffe10100468 +#define cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0xfffe1010046a +#define cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0xfffe1010046c +#define cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0xfffe1010046e +#define cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0xfffe10100470 +#define cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0xfffe10100472 +#define cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0xfffe10100474 +#define cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0xfffe10100476 +#define cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0xfffe10100478 +#define cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0xfffe1010047a +#define cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0xfffe1010047c +#define cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0xfffe1010047e +#define cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0xfffe10100480 +#define cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0xfffe10100482 +#define cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0xfffe10100484 +#define cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0xfffe10100486 +#define cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0xfffe10100488 +#define cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0xfffe1010048a +#define cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0xfffe1010048c +#define cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0xfffe1010048e +#define cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0xfffe10100490 +#define cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0xfffe10100492 +#define cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0xfffe10100494 +#define cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0xfffe10100496 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0xfffe10100504 +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0xfffe10100508 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0xfffe1010050c + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0xfffe10200000 +#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0xfffe10200000 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0xfffe10200002 +#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0xfffe10200004 +#define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0xfffe10200006 +#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0xfffe10200008 +#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0xfffe10200009 +#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0xfffe1020000a +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0xfffe1020000b +#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0xfffe1020000c +#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0xfffe1020000d +#define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0xfffe1020000e +#define cfgBIF_CFG_DEV0_EPF0_0_BIST 0xfffe1020000f +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0xfffe10200010 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0xfffe10200014 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0xfffe10200018 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0xfffe1020001c +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0xfffe10200020 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0xfffe10200024 +#define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0xfffe10200028 +#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0xfffe1020002c +#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0xfffe10200030 +#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0xfffe10200034 +#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0xfffe1020003c +#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0xfffe1020003d +#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0xfffe1020003e +#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0xfffe1020003f +#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0xfffe10200048 +#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0xfffe1020004c +#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0xfffe10200050 +#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0xfffe10200052 +#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0xfffe10200054 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0xfffe10200064 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0xfffe10200066 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0xfffe10200068 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0xfffe1020006c +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0xfffe1020006e +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0xfffe10200070 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0xfffe10200074 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0xfffe10200076 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0xfffe10200088 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0xfffe1020008c +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0xfffe1020008e +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0xfffe10200090 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0xfffe10200094 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0xfffe10200096 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0xfffe102000a0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0xfffe102000a2 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0xfffe102000a4 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0xfffe102000a8 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0xfffe102000a8 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0xfffe102000aa +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0xfffe102000ac +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0xfffe102000ac +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0xfffe102000ae +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0xfffe102000b0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0xfffe102000b0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0xfffe102000b4 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0xfffe102000c0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0xfffe102000c2 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0xfffe102000c4 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0xfffe102000c8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10200100 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10200104 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0xfffe10200108 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020010c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0xfffe10200110 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0xfffe10200114 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0xfffe10200118 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0xfffe1020011c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0xfffe1020011e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0xfffe10200120 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0xfffe10200124 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0xfffe1020012a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0xfffe1020012c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0xfffe10200130 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0xfffe10200136 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10200140 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10200144 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10200148 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10200150 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0xfffe10200154 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0xfffe10200158 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020015c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0xfffe10200160 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0xfffe10200164 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10200168 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0xfffe1020016c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0xfffe10200170 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0xfffe10200174 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0xfffe10200178 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0xfffe10200188 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020018c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0xfffe10200190 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0xfffe10200194 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10200200 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0xfffe10200204 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0xfffe10200208 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0xfffe1020020c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0xfffe10200210 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0xfffe10200214 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0xfffe10200218 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0xfffe1020021c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0xfffe10200220 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0xfffe10200224 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0xfffe10200228 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0xfffe1020022c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0xfffe10200230 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10200240 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10200244 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0xfffe10200248 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0xfffe1020024c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10200250 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0xfffe10200254 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10200258 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0xfffe1020025c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0xfffe1020025e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10200260 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10200261 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10200262 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10200263 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10200264 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10200265 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10200266 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10200267 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10200270 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0xfffe10200274 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0xfffe10200278 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020027c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020027e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10200280 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10200282 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10200284 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10200286 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10200288 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020028a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020028c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020028e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10200290 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10200292 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10200294 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10200296 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10200298 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020029a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102002a0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0xfffe102002a4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0xfffe102002a6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102002d0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0xfffe102002d4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0xfffe102002d6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0xfffe102002f0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0xfffe102002f4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0xfffe102002f6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0xfffe102002f8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0xfffe102002fc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0xfffe10200300 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0xfffe10200304 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0xfffe10200308 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0xfffe1020030c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10200310 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10200314 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0xfffe10200320 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0xfffe10200324 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10200328 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0xfffe1020032c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0xfffe1020032e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10200330 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0xfffe10200334 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0xfffe10200338 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0xfffe1020033a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0xfffe1020033c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0xfffe1020033e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0xfffe10200340 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10200342 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10200344 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0xfffe10200346 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020034a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020034c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10200350 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10200354 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10200358 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020035c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10200360 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10200364 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10200368 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020036c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0xfffe10200400 +#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0xfffe10200404 +#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0xfffe10200408 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10200410 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0xfffe10200414 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0xfffe10200418 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0xfffe1020041c +#define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10200420 +#define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10200424 +#define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10200428 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10200430 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10200431 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10200432 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10200433 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10200434 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10200435 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10200436 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10200437 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10200438 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10200439 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020043a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020043b +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020043c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020043d +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020043e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020043f +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10200450 +#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0xfffe10200454 +#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0xfffe10200456 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0xfffe10200458 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0xfffe1020045a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0xfffe1020045c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0xfffe1020045e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0xfffe10200460 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0xfffe10200462 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0xfffe10200464 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0xfffe10200466 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0xfffe10200468 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0xfffe1020046a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0xfffe1020046c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0xfffe1020046e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0xfffe10200470 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0xfffe10200472 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0xfffe10200474 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0xfffe10200476 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0xfffe10200478 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0xfffe1020047a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0xfffe1020047c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0xfffe1020047e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0xfffe10200480 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0xfffe10200482 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0xfffe10200484 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0xfffe10200486 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0xfffe10200488 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0xfffe1020048a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0xfffe1020048c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0xfffe1020048e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0xfffe10200490 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0xfffe10200492 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0xfffe10200494 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0xfffe10200496 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102004c0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102004c4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102004c8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102004cc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102004d0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102004d4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102004d8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102004dc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102004e0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102004e4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102004e8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102004ec +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102004f0 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0xfffe10200504 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0xfffe10200508 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0xfffe1020050c + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0xfffe10201000 +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0xfffe10201000 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0xfffe10201002 +#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0xfffe10201004 +#define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0xfffe10201006 +#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0xfffe10201008 +#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0xfffe10201009 +#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0xfffe1020100a +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0xfffe1020100b +#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0xfffe1020100c +#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0xfffe1020100d +#define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0xfffe1020100e +#define cfgBIF_CFG_DEV0_EPF1_0_BIST 0xfffe1020100f +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0xfffe10201010 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0xfffe10201014 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0xfffe10201018 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0xfffe1020101c +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0xfffe10201020 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0xfffe10201024 +#define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0xfffe10201028 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0xfffe1020102c +#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0xfffe10201030 +#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0xfffe10201034 +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0xfffe1020103c +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0xfffe1020103d +#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0xfffe1020103e +#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0xfffe1020103f +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0xfffe10201048 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0xfffe1020104c +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0xfffe10201050 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0xfffe10201052 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0xfffe10201054 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0xfffe10201064 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0xfffe10201066 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0xfffe10201068 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0xfffe1020106c +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0xfffe1020106e +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0xfffe10201070 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0xfffe10201074 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0xfffe10201076 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0xfffe10201088 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0xfffe1020108c +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0xfffe1020108e +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0xfffe10201090 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0xfffe10201094 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0xfffe10201096 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0xfffe102010a0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0xfffe102010a2 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0xfffe102010a4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0xfffe102010a8 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0xfffe102010a8 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0xfffe102010aa +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0xfffe102010ac +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0xfffe102010ac +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0xfffe102010ae +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0xfffe102010b0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0xfffe102010b0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0xfffe102010b4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0xfffe102010c0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0xfffe102010c2 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0xfffe102010c4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0xfffe102010c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10201100 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10201104 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0xfffe10201108 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020110c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10201140 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10201144 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10201148 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10201150 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0xfffe10201154 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0xfffe10201158 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020115c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0xfffe10201160 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0xfffe10201164 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10201168 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0xfffe1020116c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0xfffe10201170 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0xfffe10201174 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0xfffe10201178 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0xfffe10201188 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020118c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0xfffe10201190 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0xfffe10201194 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10201200 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0xfffe10201204 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0xfffe10201208 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0xfffe1020120c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0xfffe10201210 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0xfffe10201214 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0xfffe10201218 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0xfffe1020121c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0xfffe10201220 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0xfffe10201224 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0xfffe10201228 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0xfffe1020122c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0xfffe10201230 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10201240 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10201244 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0xfffe10201248 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0xfffe1020124c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10201250 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0xfffe10201254 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10201258 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0xfffe1020125c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0xfffe1020125e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10201260 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10201261 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10201262 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10201263 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10201264 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10201265 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10201266 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10201267 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10201270 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0xfffe10201274 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0xfffe10201278 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020127c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020127e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10201280 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10201282 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10201284 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10201286 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10201288 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020128a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020128c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020128e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10201290 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10201292 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10201294 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10201296 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10201298 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020129a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102012a0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0xfffe102012a4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0xfffe102012a6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102012d0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0xfffe102012d4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0xfffe102012d6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0xfffe102012f0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0xfffe102012f4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0xfffe102012f6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0xfffe102012f8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0xfffe102012fc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0xfffe10201300 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0xfffe10201304 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0xfffe10201308 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0xfffe1020130c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10201310 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10201314 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0xfffe10201320 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0xfffe10201324 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10201328 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0xfffe1020132c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0xfffe1020132e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10201330 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0xfffe10201334 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0xfffe10201338 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0xfffe1020133a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0xfffe1020133c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0xfffe1020133e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0xfffe10201340 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10201342 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10201344 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0xfffe10201346 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020134a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020134c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10201350 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10201354 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10201358 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020135c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10201360 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10201364 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10201368 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020136c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102014c0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102014c4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102014c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102014cc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102014d0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102014d4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102014d8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102014dc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102014e0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102014e4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102014e8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102014ec +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102014f0 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +// base address: 0xfffe10202000 +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0xfffe10202000 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0xfffe10202002 +#define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0xfffe10202004 +#define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0xfffe10202006 +#define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0xfffe10202008 +#define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0xfffe10202009 +#define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0xfffe1020200a +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0xfffe1020200b +#define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0xfffe1020200c +#define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0xfffe1020200d +#define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0xfffe1020200e +#define cfgBIF_CFG_DEV0_EPF2_0_BIST 0xfffe1020200f +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0xfffe10202010 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0xfffe10202014 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0xfffe10202018 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0xfffe1020201c +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0xfffe10202020 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0xfffe10202024 +#define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0xfffe10202028 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0xfffe1020202c +#define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0xfffe10202030 +#define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0xfffe10202034 +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0xfffe1020203c +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0xfffe1020203d +#define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0xfffe1020203e +#define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0xfffe1020203f +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0xfffe10202048 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0xfffe1020204c +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0xfffe10202050 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0xfffe10202052 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0xfffe10202054 +#define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0xfffe10202060 +#define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0xfffe10202061 +#define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0xfffe10202062 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0xfffe10202064 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0xfffe10202066 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0xfffe10202068 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0xfffe1020206c +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0xfffe1020206e +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0xfffe10202070 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0xfffe10202074 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0xfffe10202076 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0xfffe10202088 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0xfffe1020208c +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0xfffe1020208e +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0xfffe10202090 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0xfffe10202094 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0xfffe10202096 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0xfffe102020a0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0xfffe102020a2 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0xfffe102020a4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0xfffe102020a8 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0xfffe102020a8 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA 0xfffe102020aa +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0xfffe102020ac +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0xfffe102020ac +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 0xfffe102020ae +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0xfffe102020b0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0xfffe102020b0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0xfffe102020b4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0xfffe102020c0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0xfffe102020c2 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0xfffe102020c4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0xfffe102020c8 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10202100 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10202104 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0xfffe10202108 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020210c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10202150 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0xfffe10202154 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0xfffe10202158 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020215c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0xfffe10202160 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0xfffe10202164 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10202168 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0xfffe1020216c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0xfffe10202170 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0xfffe10202174 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0xfffe10202178 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0xfffe10202188 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020218c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0xfffe10202190 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0xfffe10202194 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10202200 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0xfffe10202204 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0xfffe10202208 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0xfffe1020220c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0xfffe10202210 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0xfffe10202214 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0xfffe10202218 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0xfffe1020221c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0xfffe10202220 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0xfffe10202224 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0xfffe10202228 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0xfffe1020222c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0xfffe10202230 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10202240 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10202244 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0xfffe10202248 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0xfffe1020224c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10202250 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0xfffe10202254 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10202258 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0xfffe1020225c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0xfffe1020225e +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10202260 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10202261 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10202262 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10202263 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10202264 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10202265 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10202266 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10202267 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102022a0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0xfffe102022a4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0xfffe102022a6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102022d0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0xfffe102022d4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0xfffe102022d6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10202328 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0xfffe1020232c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0xfffe1020232e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +// base address: 0xfffe10203000 +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0xfffe10203000 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0xfffe10203002 +#define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0xfffe10203004 +#define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0xfffe10203006 +#define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0xfffe10203008 +#define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0xfffe10203009 +#define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0xfffe1020300a +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0xfffe1020300b +#define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0xfffe1020300c +#define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0xfffe1020300d +#define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0xfffe1020300e +#define cfgBIF_CFG_DEV0_EPF3_0_BIST 0xfffe1020300f +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0xfffe10203010 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0xfffe10203014 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0xfffe10203018 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0xfffe1020301c +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0xfffe10203020 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0xfffe10203024 +#define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0xfffe10203028 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0xfffe1020302c +#define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0xfffe10203030 +#define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0xfffe10203034 +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0xfffe1020303c +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0xfffe1020303d +#define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0xfffe1020303e +#define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0xfffe1020303f +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0xfffe10203048 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0xfffe1020304c +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0xfffe10203050 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0xfffe10203052 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0xfffe10203054 +#define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0xfffe10203060 +#define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0xfffe10203061 +#define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0xfffe10203062 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0xfffe10203064 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0xfffe10203066 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0xfffe10203068 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0xfffe1020306c +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0xfffe1020306e +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0xfffe10203070 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0xfffe10203074 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0xfffe10203076 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0xfffe10203088 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0xfffe1020308c +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0xfffe1020308e +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0xfffe10203090 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0xfffe10203094 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0xfffe10203096 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0xfffe102030a0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0xfffe102030a2 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0xfffe102030a4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0xfffe102030a8 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0xfffe102030a8 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA 0xfffe102030aa +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0xfffe102030ac +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0xfffe102030ac +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 0xfffe102030ae +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0xfffe102030b0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0xfffe102030b0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0xfffe102030b4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0xfffe102030c0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0xfffe102030c2 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0xfffe102030c4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0xfffe102030c8 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10203100 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10203104 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0xfffe10203108 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020310c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10203150 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0xfffe10203154 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0xfffe10203158 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020315c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0xfffe10203160 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0xfffe10203164 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10203168 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0xfffe1020316c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0xfffe10203170 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0xfffe10203174 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0xfffe10203178 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0xfffe10203188 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020318c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0xfffe10203190 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0xfffe10203194 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10203200 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0xfffe10203204 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0xfffe10203208 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0xfffe1020320c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0xfffe10203210 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0xfffe10203214 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0xfffe10203218 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0xfffe1020321c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0xfffe10203220 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0xfffe10203224 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0xfffe10203228 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0xfffe1020322c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0xfffe10203230 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10203240 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10203244 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0xfffe10203248 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0xfffe1020324c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10203250 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0xfffe10203254 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10203258 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0xfffe1020325c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0xfffe1020325e +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10203260 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10203261 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10203262 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10203263 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10203264 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10203265 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10203266 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10203267 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102032a0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0xfffe102032a4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0xfffe102032a6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102032d0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0xfffe102032d4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0xfffe102032d6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10203328 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0xfffe1020332c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0xfffe1020332e + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +// base address: 0x30200000 +#define cfgPCIE_INDEX 0x30200030 +#define cfgPCIE_DATA 0x30200034 +#define cfgPCIE_INDEX2 0x30200038 +#define cfgPCIE_DATA2 0x3020003c +#define cfgPCIE_INDEX_HI 0x30200040 +#define cfgPCIE_INDEX2_HI 0x30200044 +#define cfgSBIOS_SCRATCH_0 0x30200120 +#define cfgSBIOS_SCRATCH_1 0x30200124 +#define cfgSBIOS_SCRATCH_2 0x30200128 +#define cfgSBIOS_SCRATCH_3 0x3020012c +#define cfgBIOS_SCRATCH_0 0x30200130 +#define cfgBIOS_SCRATCH_1 0x30200134 +#define cfgBIOS_SCRATCH_2 0x30200138 +#define cfgBIOS_SCRATCH_3 0x3020013c +#define cfgBIOS_SCRATCH_4 0x30200140 +#define cfgBIOS_SCRATCH_5 0x30200144 +#define cfgBIOS_SCRATCH_6 0x30200148 +#define cfgBIOS_SCRATCH_7 0x3020014c +#define cfgBIOS_SCRATCH_8 0x30200150 +#define cfgBIOS_SCRATCH_9 0x30200154 +#define cfgBIOS_SCRATCH_10 0x30200158 +#define cfgBIOS_SCRATCH_11 0x3020015c +#define cfgBIOS_SCRATCH_12 0x30200160 +#define cfgBIOS_SCRATCH_13 0x30200164 +#define cfgBIOS_SCRATCH_14 0x30200168 +#define cfgBIOS_SCRATCH_15 0x3020016c +#define cfgBIF_RLC_INTR_CNTL 0x30200180 +#define cfgBIF_VCE_INTR_CNTL 0x30200184 +#define cfgBIF_UVD_INTR_CNTL 0x30200188 +#define cfgGFX_MMIOREG_CAM_ADDR0 0x30200200 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR0 0x30200204 +#define cfgGFX_MMIOREG_CAM_ADDR1 0x30200208 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR1 0x3020020c +#define cfgGFX_MMIOREG_CAM_ADDR2 0x30200210 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR2 0x30200214 +#define cfgGFX_MMIOREG_CAM_ADDR3 0x30200218 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR3 0x3020021c +#define cfgGFX_MMIOREG_CAM_ADDR4 0x30200220 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR4 0x30200224 +#define cfgGFX_MMIOREG_CAM_ADDR5 0x30200228 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR5 0x3020022c +#define cfgGFX_MMIOREG_CAM_ADDR6 0x30200230 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR6 0x30200234 +#define cfgGFX_MMIOREG_CAM_ADDR7 0x30200238 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR7 0x3020023c +#define cfgGFX_MMIOREG_CAM_CNTL 0x30200240 +#define cfgGFX_MMIOREG_CAM_ZERO_CPL 0x30200244 +#define cfgGFX_MMIOREG_CAM_ONE_CPL 0x30200248 +#define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x3020024c +#define cfgDRIVER_SCRATCH_0 0x30200250 +#define cfgDRIVER_SCRATCH_1 0x30200254 +#define cfgDRIVER_SCRATCH_2 0x30200258 +#define cfgDRIVER_SCRATCH_3 0x3020025c +#define cfgDRIVER_SCRATCH_4 0x30200260 +#define cfgDRIVER_SCRATCH_5 0x30200264 +#define cfgDRIVER_SCRATCH_6 0x30200268 +#define cfgDRIVER_SCRATCH_7 0x3020026c +#define cfgDRIVER_SCRATCH_8 0x30200270 +#define cfgDRIVER_SCRATCH_9 0x30200274 +#define cfgDRIVER_SCRATCH_10 0x30200278 +#define cfgDRIVER_SCRATCH_11 0x3020027c +#define cfgDRIVER_SCRATCH_12 0x30200280 +#define cfgDRIVER_SCRATCH_13 0x30200284 +#define cfgDRIVER_SCRATCH_14 0x30200288 +#define cfgDRIVER_SCRATCH_15 0x3020028c +#define cfgFW_SCRATCH_0 0x30200290 +#define cfgFW_SCRATCH_1 0x30200294 +#define cfgFW_SCRATCH_2 0x30200298 +#define cfgFW_SCRATCH_3 0x3020029c +#define cfgFW_SCRATCH_4 0x302002a0 +#define cfgFW_SCRATCH_5 0x302002a4 +#define cfgFW_SCRATCH_6 0x302002a8 +#define cfgFW_SCRATCH_7 0x302002ac +#define cfgFW_SCRATCH_8 0x302002b0 +#define cfgFW_SCRATCH_9 0x302002b4 +#define cfgFW_SCRATCH_10 0x302002b8 +#define cfgFW_SCRATCH_11 0x302002bc +#define cfgFW_SCRATCH_12 0x302002c0 +#define cfgFW_SCRATCH_13 0x302002c4 +#define cfgFW_SCRATCH_14 0x302002c8 +#define cfgFW_SCRATCH_15 0x302002cc +#define cfgSBIOS_SCRATCH_4 0x302002d0 +#define cfgSBIOS_SCRATCH_5 0x302002d4 +#define cfgSBIOS_SCRATCH_6 0x302002d8 +#define cfgSBIOS_SCRATCH_7 0x302002dc +#define cfgSBIOS_SCRATCH_8 0x302002e0 +#define cfgSBIOS_SCRATCH_9 0x302002e4 +#define cfgSBIOS_SCRATCH_10 0x302002e8 +#define cfgSBIOS_SCRATCH_11 0x302002ec +#define cfgSBIOS_SCRATCH_12 0x302002f0 +#define cfgSBIOS_SCRATCH_13 0x302002f4 +#define cfgSBIOS_SCRATCH_14 0x302002f8 +#define cfgSBIOS_SCRATCH_15 0x302002fc + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x30200000 +#define cfgDN_PCIE_RESERVED 0x30203600 +#define cfgDN_PCIE_SCRATCH 0x30203604 +#define cfgDN_PCIE_CNTL 0x3020360c +#define cfgDN_PCIE_CONFIG_CNTL 0x30203610 +#define cfgDN_PCIE_RX_CNTL2 0x30203614 +#define cfgDN_PCIE_BUS_CNTL 0x30203618 +#define cfgDN_PCIE_CFG_CNTL 0x3020361c +#define cfgDN_PCIE_STRAP_F0 0x30203620 +#define cfgDN_PCIE_STRAP_MISC 0x30203624 +#define cfgDN_PCIE_STRAP_MISC2 0x30203628 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x30200000 +#define cfgPCIE_ERR_CNTL 0x30203630 +#define cfgPCIE_RX_CNTL 0x30203634 +#define cfgPCIE_LC_SPEED_CNTL 0x30203638 +#define cfgPCIE_LC_CNTL2 0x3020363c +#define cfgPCIEP_STRAP_MISC 0x30203640 +#define cfgLTR_MSG_INFO_FROM_EP 0x30203644 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x30200000 +#define cfgEP_PCIE_SCRATCH 0x30203580 +#define cfgEP_PCIE_CNTL 0x30203588 +#define cfgEP_PCIE_INT_CNTL 0x3020358c +#define cfgEP_PCIE_INT_STATUS 0x30203590 +#define cfgEP_PCIE_RX_CNTL2 0x30203594 +#define cfgEP_PCIE_BUS_CNTL 0x30203598 +#define cfgEP_PCIE_CFG_CNTL 0x3020359c +#define cfgEP_PCIE_TX_LTR_CNTL 0x302035a4 +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x302035a8 +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x302035a9 +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x302035aa +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x302035ab +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x302035ac +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x302035ad +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x302035ae +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x302035af +#define cfgEP_PCIE_STRAP_MISC 0x302035b0 +#define cfgEP_PCIE_STRAP_MISC2 0x302035b4 +#define cfgEP_PCIE_F0_DPA_CAP 0x302035bc +#define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x302035c0 +#define cfgEP_PCIE_F0_DPA_CNTL 0x302035c1 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x302035c3 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x302035c4 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x302035c5 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x302035c6 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x302035c7 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x302035c8 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x302035c9 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x302035ca +#define cfgEP_PCIE_PME_CONTROL 0x302035cb +#define cfgEP_PCIEP_RESERVED 0x302035cc +#define cfgEP_PCIE_TX_CNTL 0x302035d4 +#define cfgEP_PCIE_TX_REQUESTER_ID 0x302035d8 +#define cfgEP_PCIE_ERR_CNTL 0x302035dc +#define cfgEP_PCIE_RX_CNTL 0x302035e0 +#define cfgEP_PCIE_LC_SPEED_CNTL 0x302035e4 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x30200000 +#define cfgBIF_BX_PF0_MM_INDEX 0x30200000 +#define cfgBIF_BX_PF0_MM_DATA 0x30200004 +#define cfgBIF_BX_PF0_MM_INDEX_HI 0x30200018 + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x30200000 +#define cfgCC_BIF_BX_STRAP0 0x30203808 +#define cfgCC_BIF_BX_PINSTRAP0 0x30203810 +#define cfgBIF_MM_INDACCESS_CNTL 0x30203818 +#define cfgBUS_CNTL 0x3020381c +#define cfgBIF_SCRATCH0 0x30203820 +#define cfgBIF_SCRATCH1 0x30203824 +#define cfgBX_RESET_EN 0x30203834 +#define cfgMM_CFGREGS_CNTL 0x30203838 +#define cfgBX_RESET_CNTL 0x30203840 +#define cfgINTERRUPT_CNTL 0x30203844 +#define cfgINTERRUPT_CNTL2 0x30203848 +#define cfgCLKREQB_PAD_CNTL 0x30203860 +#define cfgBIF_FEATURES_CONTROL_MISC 0x3020386c +#define cfgHDP_ATOMIC_CONTROL_MISC 0x30203870 +#define cfgBIF_DOORBELL_CNTL 0x30203874 +#define cfgBIF_DOORBELL_INT_CNTL 0x30203878 +#define cfgBIF_FB_EN 0x30203880 +#define cfgBIF_INTR_CNTL 0x30203884 +#define cfgBIF_MST_TRANS_PENDING_VF 0x302038a4 +#define cfgBIF_SLV_TRANS_PENDING_VF 0x302038a8 +#define cfgBACO_CNTL 0x302038ac +#define cfgBIF_BACO_EXIT_TIME0 0x302038b0 +#define cfgBIF_BACO_EXIT_TIMER1 0x302038b4 +#define cfgBIF_BACO_EXIT_TIMER2 0x302038b8 +#define cfgBIF_BACO_EXIT_TIMER3 0x302038bc +#define cfgBIF_BACO_EXIT_TIMER4 0x302038c0 +#define cfgMEM_TYPE_CNTL 0x302038c4 +#define cfgNBIF_GFX_ADDR_LUT_CNTL 0x302038cc +#define cfgNBIF_GFX_ADDR_LUT_0 0x302038d0 +#define cfgNBIF_GFX_ADDR_LUT_1 0x302038d4 +#define cfgNBIF_GFX_ADDR_LUT_2 0x302038d8 +#define cfgNBIF_GFX_ADDR_LUT_3 0x302038dc +#define cfgNBIF_GFX_ADDR_LUT_4 0x302038e0 +#define cfgNBIF_GFX_ADDR_LUT_5 0x302038e4 +#define cfgNBIF_GFX_ADDR_LUT_6 0x302038e8 +#define cfgNBIF_GFX_ADDR_LUT_7 0x302038ec +#define cfgNBIF_GFX_ADDR_LUT_8 0x302038f0 +#define cfgNBIF_GFX_ADDR_LUT_9 0x302038f4 +#define cfgNBIF_GFX_ADDR_LUT_10 0x302038f8 +#define cfgNBIF_GFX_ADDR_LUT_11 0x302038fc +#define cfgNBIF_GFX_ADDR_LUT_12 0x30203900 +#define cfgNBIF_GFX_ADDR_LUT_13 0x30203904 +#define cfgNBIF_GFX_ADDR_LUT_14 0x30203908 +#define cfgNBIF_GFX_ADDR_LUT_15 0x3020390c +#define cfgREMAP_HDP_MEM_FLUSH_CNTL 0x30203934 +#define cfgREMAP_HDP_REG_FLUSH_CNTL 0x30203938 +#define cfgBIF_RB_CNTL 0x3020393c +#define cfgBIF_RB_BASE 0x30203940 +#define cfgBIF_RB_RPTR 0x30203944 +#define cfgBIF_RB_WPTR 0x30203948 +#define cfgBIF_RB_WPTR_ADDR_HI 0x3020394c +#define cfgBIF_RB_WPTR_ADDR_LO 0x30203950 +#define cfgMAILBOX_INDEX 0x30203954 +#define cfgBIF_MP1_INTR_CTRL 0x30203988 +#define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x30203994 +#define cfgBIF_PERSTB_PAD_CNTL 0x302039a0 +#define cfgBIF_PX_EN_PAD_CNTL 0x302039a4 +#define cfgBIF_REFPADKIN_PAD_CNTL 0x302039a8 +#define cfgBIF_CLKREQB_PAD_CNTL 0x302039ac +#define cfgBIF_PWRBRK_PAD_CNTL 0x302039b0 +#define cfgBIF_WAKEB_PAD_CNTL 0x302039b4 +#define cfgBIF_VAUX_PRESENT_PAD_CNTL 0x302039b8 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x30200000 +#define cfgRCC_ERR_INT_CNTL 0x30203698 +#define cfgRCC_BACO_CNTL_MISC 0x3020369c +#define cfgRCC_RESET_EN 0x302036a0 +#define cfgRCC_VDM_SUPPORT 0x302036a4 +#define cfgRCC_MARGIN_PARAM_CNTL0 0x302036a8 +#define cfgRCC_MARGIN_PARAM_CNTL1 0x302036ac +#define cfgRCC_GPUIOV_REGION 0x302036b0 +#define cfgRCC_PEER_REG_RANGE0 0x30203778 +#define cfgRCC_PEER_REG_RANGE1 0x3020377c +#define cfgRCC_BUS_CNTL 0x30203784 +#define cfgRCC_CONFIG_CNTL 0x30203788 +#define cfgRCC_CONFIG_F0_BASE 0x30203798 +#define cfgRCC_CONFIG_APER_SIZE 0x3020379c +#define cfgRCC_CONFIG_REG_APER_SIZE 0x302037a0 +#define cfgRCC_XDMA_LO 0x302037a4 +#define cfgRCC_XDMA_HI 0x302037a8 +#define cfgRCC_FEATURES_CONTROL_MISC 0x302037ac +#define cfgRCC_BUSNUM_CNTL1 0x302037b0 +#define cfgRCC_BUSNUM_LIST0 0x302037b4 +#define cfgRCC_BUSNUM_LIST1 0x302037b8 +#define cfgRCC_BUSNUM_CNTL2 0x302037bc +#define cfgRCC_CAPTURE_HOST_BUSNUM 0x302037c0 +#define cfgRCC_HOST_BUSNUM 0x302037c4 +#define cfgRCC_PEER0_FB_OFFSET_HI 0x302037c8 +#define cfgRCC_PEER0_FB_OFFSET_LO 0x302037cc +#define cfgRCC_PEER1_FB_OFFSET_HI 0x302037d0 +#define cfgRCC_PEER1_FB_OFFSET_LO 0x302037d4 +#define cfgRCC_PEER2_FB_OFFSET_HI 0x302037d8 +#define cfgRCC_PEER2_FB_OFFSET_LO 0x302037dc +#define cfgRCC_PEER3_FB_OFFSET_HI 0x302037e0 +#define cfgRCC_PEER3_FB_OFFSET_LO 0x302037e4 +#define cfgRCC_DEVFUNCNUM_LIST0 0x302037e8 +#define cfgRCC_DEVFUNCNUM_LIST1 0x302037ec +#define cfgRCC_DEV0_LINK_CNTL 0x302037f4 +#define cfgRCC_CMN_LINK_CNTL 0x302037f8 +#define cfgRCC_EP_REQUESTERID_RESTORE 0x302037fc +#define cfgRCC_LTR_LSWITCH_CNTL 0x30203800 +#define cfgRCC_MH_ARB_CNTL 0x30203804 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x30200000 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x30242000 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x30242004 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x30242008 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x3024200c +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x30242010 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x30242014 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x30242018 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x3024201c +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x30242020 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x30242024 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x30242028 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x3024202c +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x30242030 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x30242034 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x30242038 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x3024203c +#define cfgRCC_DEV0_EPF0_GFXMSIX_PBA 0x30243000 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x30200000 +#define cfgRCC_BIF_STRAP0 0x30203480 +#define cfgRCC_BIF_STRAP1 0x30203484 +#define cfgRCC_BIF_STRAP2 0x30203488 +#define cfgRCC_BIF_STRAP3 0x3020348c +#define cfgRCC_BIF_STRAP4 0x30203490 +#define cfgRCC_BIF_STRAP5 0x30203494 +#define cfgRCC_BIF_STRAP6 0x30203498 +#define cfgRCC_DEV0_PORT_STRAP0 0x3020349c +#define cfgRCC_DEV0_PORT_STRAP1 0x302034a0 +#define cfgRCC_DEV0_PORT_STRAP10 0x302034a4 +#define cfgRCC_DEV0_PORT_STRAP11 0x302034a8 +#define cfgRCC_DEV0_PORT_STRAP12 0x302034ac +#define cfgRCC_DEV0_PORT_STRAP13 0x302034b0 +#define cfgRCC_DEV0_PORT_STRAP14 0x302034b4 +#define cfgRCC_DEV0_PORT_STRAP2 0x302034b8 +#define cfgRCC_DEV0_PORT_STRAP3 0x302034bc +#define cfgRCC_DEV0_PORT_STRAP4 0x302034c0 +#define cfgRCC_DEV0_PORT_STRAP5 0x302034c4 +#define cfgRCC_DEV0_PORT_STRAP6 0x302034c8 +#define cfgRCC_DEV0_PORT_STRAP7 0x302034cc +#define cfgRCC_DEV0_PORT_STRAP8 0x302034d0 +#define cfgRCC_DEV0_PORT_STRAP9 0x302034d4 +#define cfgRCC_DEV0_EPF0_STRAP0 0x302034d8 +#define cfgRCC_DEV0_EPF0_STRAP1 0x302034dc +#define cfgRCC_DEV0_EPF0_STRAP13 0x302034e0 +#define cfgRCC_DEV0_EPF0_STRAP14 0x302034e4 +#define cfgRCC_DEV0_EPF0_STRAP15 0x302034e8 +#define cfgRCC_DEV0_EPF0_STRAP16 0x302034ec +#define cfgRCC_DEV0_EPF0_STRAP17 0x302034f0 +#define cfgRCC_DEV0_EPF0_STRAP18 0x302034f4 +#define cfgRCC_DEV0_EPF0_STRAP2 0x302034f8 +#define cfgRCC_DEV0_EPF0_STRAP26 0x302034fc +#define cfgRCC_DEV0_EPF0_STRAP3 0x30203500 +#define cfgRCC_DEV0_EPF0_STRAP4 0x30203504 +#define cfgRCC_DEV0_EPF0_STRAP5 0x30203508 +#define cfgRCC_DEV0_EPF0_STRAP8 0x3020350c +#define cfgRCC_DEV0_EPF0_STRAP9 0x30203510 +#define cfgRCC_DEV0_EPF1_STRAP0 0x30203514 +#define cfgRCC_DEV0_EPF1_STRAP2 0x30203544 +#define cfgRCC_DEV0_EPF1_STRAP20 0x30203548 +#define cfgRCC_DEV0_EPF1_STRAP21 0x3020354c +#define cfgRCC_DEV0_EPF1_STRAP22 0x30203550 +#define cfgRCC_DEV0_EPF1_STRAP23 0x30203554 +#define cfgRCC_DEV0_EPF1_STRAP24 0x30203558 +#define cfgRCC_DEV0_EPF1_STRAP25 0x3020355c +#define cfgRCC_DEV0_EPF1_STRAP3 0x30203560 +#define cfgRCC_DEV0_EPF1_STRAP4 0x30203564 +#define cfgRCC_DEV0_EPF1_STRAP5 0x30203568 +#define cfgRCC_DEV0_EPF1_STRAP6 0x3020356c +#define cfgRCC_DEV0_EPF1_STRAP7 0x30203570 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x30200000 +#define cfgBIF_BX_PF_BIF_BME_STATUS 0x3020382c +#define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x30203830 +#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x3020384c +#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x30203850 +#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x30203854 +#define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x30203858 +#define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x3020385c +#define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x30203864 +#define cfgBIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x30203868 +#define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x30203898 +#define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x3020389c +#define cfgBIF_BX_PF_BIF_TRANS_PENDING 0x302038a0 +#define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x302038c8 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x30203958 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x3020395c +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x30203960 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x30203964 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x30203968 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x3020396c +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x30203970 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x30203974 +#define cfgBIF_BX_PF_MAILBOX_CONTROL 0x30203978 +#define cfgBIF_BX_PF_MAILBOX_INT_CNTL 0x3020397c +#define cfgBIF_BX_PF_BIF_VMHV_MAILBOX 0x30203980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +// base address: 0x30203480 +#define cfgRCC_DEV0_EPF0_RCC_ERR_LOG 0x30203694 +#define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x30203780 +#define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x3020378c +#define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x30203790 +#define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x30203794 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +// base address: 0x30200000 +#define cfgSHUB_REGS_IF_CTL 0x30203b8c +#define cfgNGDC_MGCG_CTRL 0x30203ba8 +#define cfgNGDC_RESERVED_0 0x30203bac +#define cfgNGDC_RESERVED_1 0x30203bb0 +#define cfgATDMA_MISC_CNTL 0x30203bf4 +#define cfgS2A_MISC_CNTL 0x30203bfc +#define cfgNGDC_PG_MISC_CTRL 0x30203c60 +#define cfgNGDC_PGMST_CTRL 0x30203c64 +#define cfgNGDC_PGSLV_CTRL 0x30203c68 + + +// addressBlock: nbio_nbif0_bif_swus_SUMDEC +// base address: 0x100000 +#define cfgSUM_INDEX 0x1000e0 +#define cfgSUM_DATA 0x1000e4 +#define cfgSUM_INDEX_HI 0x1000ec + + +// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec +// base address: 0xfffe30000000 +#define cfgSHADOW_COMMAND 0xfffe30000004 +#define cfgSHADOW_BASE_ADDR_1 0xfffe30000010 +#define cfgSHADOW_BASE_ADDR_2 0xfffe30000014 +#define cfgSHADOW_SUB_BUS_NUMBER_LATENCY 0xfffe30000018 +#define cfgSHADOW_IO_BASE_LIMIT 0xfffe3000001c +#define cfgSHADOW_MEM_BASE_LIMIT 0xfffe30000020 +#define cfgSHADOW_PREF_BASE_LIMIT 0xfffe30000024 +#define cfgSHADOW_PREF_BASE_UPPER 0xfffe30000028 +#define cfgSHADOW_PREF_LIMIT_UPPER 0xfffe3000002c +#define cfgSHADOW_IO_BASE_LIMIT_HI 0xfffe30000030 +#define cfgSUC_INDEX 0xfffe300000e0 +#define cfgSUC_DATA 0xfffe300000e4 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 +// base address: 0x0 +#define cfgBIF_BX_PF1_MM_INDEX 0x0000 +#define cfgBIF_BX_PF1_MM_DATA 0x0004 +#define cfgBIF_BX_PF1_MM_INDEX_HI 0x0018 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0xfffe10300000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0xfffe10300000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0xfffe10300002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0xfffe10300004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0xfffe10300006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0xfffe10300008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0xfffe10300009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0xfffe1030000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0xfffe1030000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0xfffe1030000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0xfffe1030000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0xfffe1030000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0xfffe1030000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0xfffe10300010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0xfffe10300014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0xfffe10300018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0xfffe1030001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0xfffe10300020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0xfffe10300024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR 0xfffe10300028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0xfffe1030002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0xfffe10300030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0xfffe10300034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0xfffe1030003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0xfffe1030003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT 0xfffe1030003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY 0xfffe1030003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0xfffe10300064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0xfffe10300066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0xfffe10300068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0xfffe1030006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0xfffe1030006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0xfffe10300070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0xfffe10300074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0xfffe10300076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0xfffe10300088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0xfffe1030008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0xfffe1030008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0xfffe10300090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0xfffe10300094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0xfffe10300096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0xfffe103000a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0xfffe103000a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0xfffe103000a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0xfffe103000a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0xfffe103000a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA 0xfffe103000aa +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0xfffe103000ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0xfffe103000ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64 0xfffe103000ae +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0xfffe103000b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0xfffe103000b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0xfffe103000b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0xfffe103000c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0xfffe103000c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0xfffe103000c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0xfffe103000c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10300100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10300104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0xfffe10300108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10300150 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0xfffe10300154 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0xfffe10300158 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030015c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0xfffe10300160 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0xfffe10300164 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10300168 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0xfffe1030016c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0xfffe10300170 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0xfffe10300174 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0xfffe10300178 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0xfffe10300188 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030018c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0xfffe10300190 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0xfffe10300194 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10300328 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0xfffe1030032c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0xfffe1030032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0xfffe10301000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0xfffe10301000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0xfffe10301002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0xfffe10301004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0xfffe10301006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0xfffe10301008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0xfffe10301009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0xfffe1030100a +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0xfffe1030100b +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0xfffe1030100c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0xfffe1030100d +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0xfffe1030100e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0xfffe1030100f +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0xfffe10301010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0xfffe10301014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0xfffe10301018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0xfffe1030101c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0xfffe10301020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0xfffe10301024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR 0xfffe10301028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0xfffe1030102c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0xfffe10301030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0xfffe10301034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0xfffe1030103c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0xfffe1030103d +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT 0xfffe1030103e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY 0xfffe1030103f +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0xfffe10301064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0xfffe10301066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0xfffe10301068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0xfffe1030106c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0xfffe1030106e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0xfffe10301070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0xfffe10301074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0xfffe10301076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0xfffe10301088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0xfffe1030108c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0xfffe1030108e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0xfffe10301090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0xfffe10301094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0xfffe10301096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0xfffe103010a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0xfffe103010a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0xfffe103010a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0xfffe103010a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0xfffe103010a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA 0xfffe103010aa +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0xfffe103010ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0xfffe103010ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64 0xfffe103010ae +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0xfffe103010b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0xfffe103010b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0xfffe103010b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0xfffe103010c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0xfffe103010c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0xfffe103010c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0xfffe103010c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10301100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10301104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0xfffe10301108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030110c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10301150 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0xfffe10301154 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0xfffe10301158 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030115c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0xfffe10301160 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0xfffe10301164 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10301168 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0xfffe1030116c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0xfffe10301170 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0xfffe10301174 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0xfffe10301178 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0xfffe10301188 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030118c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0xfffe10301190 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0xfffe10301194 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10301328 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0xfffe1030132c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0xfffe1030132e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0xfffe10302000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0xfffe10302000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0xfffe10302002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0xfffe10302004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0xfffe10302006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0xfffe10302008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0xfffe10302009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0xfffe1030200a +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0xfffe1030200b +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0xfffe1030200c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0xfffe1030200d +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0xfffe1030200e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0xfffe1030200f +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0xfffe10302010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0xfffe10302014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0xfffe10302018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0xfffe1030201c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0xfffe10302020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0xfffe10302024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR 0xfffe10302028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0xfffe1030202c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0xfffe10302030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0xfffe10302034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0xfffe1030203c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0xfffe1030203d +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT 0xfffe1030203e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY 0xfffe1030203f +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0xfffe10302064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0xfffe10302066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0xfffe10302068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0xfffe1030206c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0xfffe1030206e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0xfffe10302070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0xfffe10302074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0xfffe10302076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0xfffe10302088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0xfffe1030208c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0xfffe1030208e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0xfffe10302090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0xfffe10302094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0xfffe10302096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0xfffe103020a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0xfffe103020a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0xfffe103020a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0xfffe103020a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0xfffe103020a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA 0xfffe103020aa +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0xfffe103020ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0xfffe103020ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64 0xfffe103020ae +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0xfffe103020b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0xfffe103020b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0xfffe103020b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0xfffe103020c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0xfffe103020c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0xfffe103020c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0xfffe103020c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10302100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10302104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0xfffe10302108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030210c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10302150 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0xfffe10302154 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0xfffe10302158 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030215c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0xfffe10302160 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0xfffe10302164 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10302168 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0xfffe1030216c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0xfffe10302170 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0xfffe10302174 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0xfffe10302178 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0xfffe10302188 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030218c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0xfffe10302190 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0xfffe10302194 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10302328 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0xfffe1030232c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0xfffe1030232e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0xfffe10303000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0xfffe10303000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0xfffe10303002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0xfffe10303004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0xfffe10303006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0xfffe10303008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0xfffe10303009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0xfffe1030300a +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0xfffe1030300b +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0xfffe1030300c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0xfffe1030300d +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0xfffe1030300e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0xfffe1030300f +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0xfffe10303010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0xfffe10303014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0xfffe10303018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0xfffe1030301c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0xfffe10303020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0xfffe10303024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR 0xfffe10303028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0xfffe1030302c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0xfffe10303030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0xfffe10303034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0xfffe1030303c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0xfffe1030303d +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT 0xfffe1030303e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY 0xfffe1030303f +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0xfffe10303064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0xfffe10303066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0xfffe10303068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0xfffe1030306c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0xfffe1030306e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0xfffe10303070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0xfffe10303074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0xfffe10303076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0xfffe10303088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0xfffe1030308c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0xfffe1030308e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0xfffe10303090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0xfffe10303094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0xfffe10303096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0xfffe103030a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0xfffe103030a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0xfffe103030a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0xfffe103030a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0xfffe103030a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA 0xfffe103030aa +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0xfffe103030ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0xfffe103030ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64 0xfffe103030ae +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0xfffe103030b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0xfffe103030b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0xfffe103030b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0xfffe103030c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0xfffe103030c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0xfffe103030c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0xfffe103030c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10303100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10303104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0xfffe10303108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030310c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10303150 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0xfffe10303154 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0xfffe10303158 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030315c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0xfffe10303160 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0xfffe10303164 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10303168 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0xfffe1030316c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0xfffe10303170 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0xfffe10303174 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0xfffe10303178 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0xfffe10303188 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030318c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0xfffe10303190 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0xfffe10303194 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10303328 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0xfffe1030332c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0xfffe1030332e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0xfffe10304000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0xfffe10304000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0xfffe10304002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0xfffe10304004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0xfffe10304006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0xfffe10304008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0xfffe10304009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0xfffe1030400a +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0xfffe1030400b +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0xfffe1030400c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0xfffe1030400d +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0xfffe1030400e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0xfffe1030400f +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0xfffe10304010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0xfffe10304014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0xfffe10304018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0xfffe1030401c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0xfffe10304020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0xfffe10304024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR 0xfffe10304028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0xfffe1030402c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0xfffe10304030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0xfffe10304034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0xfffe1030403c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0xfffe1030403d +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT 0xfffe1030403e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY 0xfffe1030403f +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0xfffe10304064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0xfffe10304066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0xfffe10304068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0xfffe1030406c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0xfffe1030406e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0xfffe10304070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0xfffe10304074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0xfffe10304076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0xfffe10304088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0xfffe1030408c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0xfffe1030408e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0xfffe10304090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0xfffe10304094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0xfffe10304096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0xfffe103040a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0xfffe103040a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0xfffe103040a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0xfffe103040a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0xfffe103040a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA 0xfffe103040aa +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0xfffe103040ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0xfffe103040ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64 0xfffe103040ae +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0xfffe103040b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0xfffe103040b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0xfffe103040b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0xfffe103040c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0xfffe103040c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0xfffe103040c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0xfffe103040c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10304100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10304104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0xfffe10304108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030410c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10304150 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0xfffe10304154 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0xfffe10304158 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030415c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0xfffe10304160 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0xfffe10304164 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10304168 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0xfffe1030416c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0xfffe10304170 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0xfffe10304174 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0xfffe10304178 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0xfffe10304188 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030418c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0xfffe10304190 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0xfffe10304194 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10304328 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0xfffe1030432c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0xfffe1030432e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0xfffe10305000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0xfffe10305000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0xfffe10305002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0xfffe10305004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0xfffe10305006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0xfffe10305008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0xfffe10305009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0xfffe1030500a +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0xfffe1030500b +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0xfffe1030500c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0xfffe1030500d +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0xfffe1030500e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0xfffe1030500f +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0xfffe10305010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0xfffe10305014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0xfffe10305018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0xfffe1030501c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0xfffe10305020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0xfffe10305024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR 0xfffe10305028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0xfffe1030502c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0xfffe10305030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0xfffe10305034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0xfffe1030503c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0xfffe1030503d +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT 0xfffe1030503e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY 0xfffe1030503f +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0xfffe10305064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0xfffe10305066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0xfffe10305068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0xfffe1030506c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0xfffe1030506e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0xfffe10305070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0xfffe10305074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0xfffe10305076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0xfffe10305088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0xfffe1030508c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0xfffe1030508e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0xfffe10305090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0xfffe10305094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0xfffe10305096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0xfffe103050a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0xfffe103050a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0xfffe103050a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0xfffe103050a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0xfffe103050a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA 0xfffe103050aa +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0xfffe103050ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0xfffe103050ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64 0xfffe103050ae +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0xfffe103050b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0xfffe103050b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0xfffe103050b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0xfffe103050c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0xfffe103050c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0xfffe103050c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0xfffe103050c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10305100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10305104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0xfffe10305108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030510c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10305150 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0xfffe10305154 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0xfffe10305158 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030515c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0xfffe10305160 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0xfffe10305164 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10305168 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0xfffe1030516c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0xfffe10305170 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0xfffe10305174 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0xfffe10305178 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0xfffe10305188 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030518c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0xfffe10305190 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0xfffe10305194 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10305328 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0xfffe1030532c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0xfffe1030532e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0xfffe10306000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0xfffe10306000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0xfffe10306002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0xfffe10306004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0xfffe10306006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0xfffe10306008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0xfffe10306009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0xfffe1030600a +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0xfffe1030600b +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0xfffe1030600c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0xfffe1030600d +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0xfffe1030600e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0xfffe1030600f +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0xfffe10306010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0xfffe10306014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0xfffe10306018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0xfffe1030601c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0xfffe10306020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0xfffe10306024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR 0xfffe10306028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0xfffe1030602c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0xfffe10306030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0xfffe10306034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0xfffe1030603c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0xfffe1030603d +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT 0xfffe1030603e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY 0xfffe1030603f +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0xfffe10306064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0xfffe10306066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0xfffe10306068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0xfffe1030606c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0xfffe1030606e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0xfffe10306070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0xfffe10306074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0xfffe10306076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0xfffe10306088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0xfffe1030608c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0xfffe1030608e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0xfffe10306090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0xfffe10306094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0xfffe10306096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0xfffe103060a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0xfffe103060a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0xfffe103060a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0xfffe103060a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0xfffe103060a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA 0xfffe103060aa +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0xfffe103060ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0xfffe103060ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64 0xfffe103060ae +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0xfffe103060b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0xfffe103060b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0xfffe103060b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0xfffe103060c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0xfffe103060c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0xfffe103060c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0xfffe103060c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10306100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10306104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0xfffe10306108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030610c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10306150 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0xfffe10306154 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0xfffe10306158 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030615c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0xfffe10306160 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0xfffe10306164 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10306168 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0xfffe1030616c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0xfffe10306170 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0xfffe10306174 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0xfffe10306178 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0xfffe10306188 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030618c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0xfffe10306190 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0xfffe10306194 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10306328 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0xfffe1030632c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0xfffe1030632e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0xfffe10307000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0xfffe10307000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0xfffe10307002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0xfffe10307004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0xfffe10307006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0xfffe10307008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0xfffe10307009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0xfffe1030700a +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0xfffe1030700b +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0xfffe1030700c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0xfffe1030700d +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0xfffe1030700e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0xfffe1030700f +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0xfffe10307010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0xfffe10307014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0xfffe10307018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0xfffe1030701c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0xfffe10307020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0xfffe10307024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR 0xfffe10307028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0xfffe1030702c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0xfffe10307030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0xfffe10307034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0xfffe1030703c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0xfffe1030703d +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT 0xfffe1030703e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY 0xfffe1030703f +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0xfffe10307064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0xfffe10307066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0xfffe10307068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0xfffe1030706c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0xfffe1030706e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0xfffe10307070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0xfffe10307074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0xfffe10307076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0xfffe10307088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0xfffe1030708c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0xfffe1030708e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0xfffe10307090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0xfffe10307094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0xfffe10307096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0xfffe103070a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0xfffe103070a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0xfffe103070a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0xfffe103070a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0xfffe103070a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA 0xfffe103070aa +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0xfffe103070ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0xfffe103070ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64 0xfffe103070ae +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0xfffe103070b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0xfffe103070b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0xfffe103070b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0xfffe103070c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0xfffe103070c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0xfffe103070c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0xfffe103070c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10307100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10307104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0xfffe10307108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030710c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10307150 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0xfffe10307154 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0xfffe10307158 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030715c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0xfffe10307160 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0xfffe10307164 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10307168 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0xfffe1030716c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0xfffe10307170 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0xfffe10307174 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0xfffe10307178 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0xfffe10307188 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030718c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0xfffe10307190 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0xfffe10307194 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10307328 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0xfffe1030732c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0xfffe1030732e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +// base address: 0xfffe10308000 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0xfffe10308000 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0xfffe10308002 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0xfffe10308004 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0xfffe10308006 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0xfffe10308008 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0xfffe10308009 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0xfffe1030800a +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0xfffe1030800b +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0xfffe1030800c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0xfffe1030800d +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0xfffe1030800e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0xfffe1030800f +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0xfffe10308010 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0xfffe10308014 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0xfffe10308018 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0xfffe1030801c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0xfffe10308020 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0xfffe10308024 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR 0xfffe10308028 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0xfffe1030802c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0xfffe10308030 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0xfffe10308034 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0xfffe1030803c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0xfffe1030803d +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT 0xfffe1030803e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY 0xfffe1030803f +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0xfffe10308064 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0xfffe10308066 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0xfffe10308068 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0xfffe1030806c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0xfffe1030806e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0xfffe10308070 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0xfffe10308074 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0xfffe10308076 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0xfffe10308088 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0xfffe1030808c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0xfffe1030808e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0xfffe10308090 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0xfffe10308094 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0xfffe10308096 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0xfffe103080a0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0xfffe103080a2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0xfffe103080a4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0xfffe103080a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0xfffe103080a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA 0xfffe103080aa +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0xfffe103080ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0xfffe103080ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64 0xfffe103080ae +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0xfffe103080b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0xfffe103080b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0xfffe103080b4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0xfffe103080c0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0xfffe103080c2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0xfffe103080c4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0xfffe103080c8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10308100 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10308104 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0xfffe10308108 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030810c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10308150 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0xfffe10308154 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0xfffe10308158 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030815c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0xfffe10308160 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0xfffe10308164 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10308168 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0xfffe1030816c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0xfffe10308170 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0xfffe10308174 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0xfffe10308178 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0xfffe10308188 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030818c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0xfffe10308190 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0xfffe10308194 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10308328 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0xfffe1030832c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0xfffe1030832e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +// base address: 0xfffe10309000 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0xfffe10309000 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0xfffe10309002 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0xfffe10309004 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0xfffe10309006 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0xfffe10309008 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0xfffe10309009 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0xfffe1030900a +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0xfffe1030900b +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0xfffe1030900c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0xfffe1030900d +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0xfffe1030900e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0xfffe1030900f +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0xfffe10309010 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0xfffe10309014 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0xfffe10309018 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0xfffe1030901c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0xfffe10309020 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0xfffe10309024 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR 0xfffe10309028 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0xfffe1030902c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0xfffe10309030 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0xfffe10309034 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0xfffe1030903c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0xfffe1030903d +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT 0xfffe1030903e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY 0xfffe1030903f +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0xfffe10309064 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0xfffe10309066 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0xfffe10309068 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0xfffe1030906c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0xfffe1030906e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0xfffe10309070 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0xfffe10309074 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0xfffe10309076 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0xfffe10309088 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0xfffe1030908c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0xfffe1030908e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0xfffe10309090 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0xfffe10309094 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0xfffe10309096 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0xfffe103090a0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0xfffe103090a2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0xfffe103090a4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0xfffe103090a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0xfffe103090a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA 0xfffe103090aa +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0xfffe103090ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0xfffe103090ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64 0xfffe103090ae +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0xfffe103090b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0xfffe103090b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0xfffe103090b4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0xfffe103090c0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0xfffe103090c2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0xfffe103090c4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0xfffe103090c8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10309100 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10309104 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0xfffe10309108 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030910c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10309150 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0xfffe10309154 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0xfffe10309158 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030915c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0xfffe10309160 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0xfffe10309164 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10309168 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0xfffe1030916c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0xfffe10309170 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0xfffe10309174 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0xfffe10309178 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0xfffe10309188 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030918c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0xfffe10309190 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0xfffe10309194 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10309328 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0xfffe1030932c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0xfffe1030932e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +// base address: 0xfffe1030a000 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0xfffe1030a000 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0xfffe1030a002 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0xfffe1030a004 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0xfffe1030a006 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0xfffe1030a008 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0xfffe1030a009 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0xfffe1030a00a +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0xfffe1030a00b +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0xfffe1030a00c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0xfffe1030a00d +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0xfffe1030a00e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0xfffe1030a00f +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0xfffe1030a010 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0xfffe1030a014 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0xfffe1030a018 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0xfffe1030a01c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0xfffe1030a020 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0xfffe1030a024 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR 0xfffe1030a028 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0xfffe1030a02c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0xfffe1030a030 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0xfffe1030a034 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0xfffe1030a03c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0xfffe1030a03d +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT 0xfffe1030a03e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY 0xfffe1030a03f +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0xfffe1030a064 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0xfffe1030a066 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0xfffe1030a068 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0xfffe1030a06c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0xfffe1030a06e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0xfffe1030a070 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0xfffe1030a074 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0xfffe1030a076 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0xfffe1030a088 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0xfffe1030a08c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0xfffe1030a08e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0xfffe1030a090 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0xfffe1030a094 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0xfffe1030a096 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0xfffe1030a0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0xfffe1030a0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0xfffe1030a0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0xfffe1030a0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0xfffe1030a0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA 0xfffe1030a0aa +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0xfffe1030a0ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0xfffe1030a0ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64 0xfffe1030a0ae +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0xfffe1030a0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0xfffe1030a0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0xfffe1030a0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0xfffe1030a0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0xfffe1030a0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0xfffe1030a0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0xfffe1030a0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030a100 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030a104 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030a108 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030a10c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030a150 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030a154 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0xfffe1030a158 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030a15c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0xfffe1030a160 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0xfffe1030a164 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030a168 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0xfffe1030a16c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0xfffe1030a170 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0xfffe1030a174 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0xfffe1030a178 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030a188 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030a18c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030a190 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030a194 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030a328 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0xfffe1030a32c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0xfffe1030a32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +// base address: 0xfffe1030b000 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0xfffe1030b000 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0xfffe1030b002 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0xfffe1030b004 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0xfffe1030b006 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0xfffe1030b008 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0xfffe1030b009 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0xfffe1030b00a +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0xfffe1030b00b +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0xfffe1030b00c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0xfffe1030b00d +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0xfffe1030b00e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0xfffe1030b00f +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0xfffe1030b010 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0xfffe1030b014 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0xfffe1030b018 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0xfffe1030b01c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0xfffe1030b020 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0xfffe1030b024 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR 0xfffe1030b028 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0xfffe1030b02c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0xfffe1030b030 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0xfffe1030b034 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0xfffe1030b03c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0xfffe1030b03d +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT 0xfffe1030b03e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY 0xfffe1030b03f +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0xfffe1030b064 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0xfffe1030b066 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0xfffe1030b068 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0xfffe1030b06c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0xfffe1030b06e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0xfffe1030b070 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0xfffe1030b074 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0xfffe1030b076 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0xfffe1030b088 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0xfffe1030b08c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0xfffe1030b08e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0xfffe1030b090 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0xfffe1030b094 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0xfffe1030b096 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0xfffe1030b0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0xfffe1030b0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0xfffe1030b0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0xfffe1030b0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0xfffe1030b0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA 0xfffe1030b0aa +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0xfffe1030b0ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0xfffe1030b0ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64 0xfffe1030b0ae +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0xfffe1030b0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0xfffe1030b0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0xfffe1030b0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0xfffe1030b0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0xfffe1030b0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0xfffe1030b0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0xfffe1030b0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030b100 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030b104 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030b108 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030b10c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030b150 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030b154 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0xfffe1030b158 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030b15c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0xfffe1030b160 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0xfffe1030b164 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030b168 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0xfffe1030b16c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0xfffe1030b170 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0xfffe1030b174 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0xfffe1030b178 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030b188 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030b18c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030b190 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030b194 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030b328 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0xfffe1030b32c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0xfffe1030b32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +// base address: 0xfffe1030c000 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0xfffe1030c000 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0xfffe1030c002 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0xfffe1030c004 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0xfffe1030c006 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0xfffe1030c008 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0xfffe1030c009 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0xfffe1030c00a +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0xfffe1030c00b +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0xfffe1030c00c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0xfffe1030c00d +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0xfffe1030c00e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0xfffe1030c00f +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0xfffe1030c010 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0xfffe1030c014 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0xfffe1030c018 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0xfffe1030c01c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0xfffe1030c020 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0xfffe1030c024 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR 0xfffe1030c028 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0xfffe1030c02c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0xfffe1030c030 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0xfffe1030c034 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0xfffe1030c03c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0xfffe1030c03d +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT 0xfffe1030c03e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY 0xfffe1030c03f +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0xfffe1030c064 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0xfffe1030c066 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0xfffe1030c068 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0xfffe1030c06c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0xfffe1030c06e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0xfffe1030c070 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0xfffe1030c074 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0xfffe1030c076 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0xfffe1030c088 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0xfffe1030c08c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0xfffe1030c08e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0xfffe1030c090 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0xfffe1030c094 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0xfffe1030c096 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0xfffe1030c0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0xfffe1030c0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0xfffe1030c0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0xfffe1030c0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0xfffe1030c0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA 0xfffe1030c0aa +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0xfffe1030c0ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0xfffe1030c0ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64 0xfffe1030c0ae +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0xfffe1030c0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0xfffe1030c0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0xfffe1030c0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0xfffe1030c0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0xfffe1030c0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0xfffe1030c0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0xfffe1030c0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030c100 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030c104 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030c108 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030c10c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030c150 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030c154 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0xfffe1030c158 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030c15c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0xfffe1030c160 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0xfffe1030c164 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030c168 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0xfffe1030c16c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0xfffe1030c170 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0xfffe1030c174 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0xfffe1030c178 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030c188 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030c18c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030c190 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030c194 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030c328 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0xfffe1030c32c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0xfffe1030c32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +// base address: 0xfffe1030d000 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0xfffe1030d000 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0xfffe1030d002 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0xfffe1030d004 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0xfffe1030d006 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0xfffe1030d008 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0xfffe1030d009 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0xfffe1030d00a +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0xfffe1030d00b +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0xfffe1030d00c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0xfffe1030d00d +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0xfffe1030d00e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0xfffe1030d00f +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0xfffe1030d010 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0xfffe1030d014 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0xfffe1030d018 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0xfffe1030d01c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0xfffe1030d020 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0xfffe1030d024 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR 0xfffe1030d028 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0xfffe1030d02c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0xfffe1030d030 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0xfffe1030d034 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0xfffe1030d03c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0xfffe1030d03d +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT 0xfffe1030d03e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY 0xfffe1030d03f +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0xfffe1030d064 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0xfffe1030d066 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0xfffe1030d068 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0xfffe1030d06c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0xfffe1030d06e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0xfffe1030d070 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0xfffe1030d074 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0xfffe1030d076 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0xfffe1030d088 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0xfffe1030d08c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0xfffe1030d08e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0xfffe1030d090 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0xfffe1030d094 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0xfffe1030d096 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0xfffe1030d0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0xfffe1030d0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0xfffe1030d0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0xfffe1030d0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0xfffe1030d0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA 0xfffe1030d0aa +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0xfffe1030d0ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0xfffe1030d0ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64 0xfffe1030d0ae +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0xfffe1030d0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0xfffe1030d0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0xfffe1030d0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0xfffe1030d0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0xfffe1030d0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0xfffe1030d0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0xfffe1030d0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030d100 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030d104 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030d108 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030d10c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030d150 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030d154 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0xfffe1030d158 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030d15c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0xfffe1030d160 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0xfffe1030d164 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030d168 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0xfffe1030d16c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0xfffe1030d170 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0xfffe1030d174 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0xfffe1030d178 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030d188 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030d18c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030d190 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030d194 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030d328 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0xfffe1030d32c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0xfffe1030d32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +// base address: 0xfffe1030e000 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0xfffe1030e000 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0xfffe1030e002 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0xfffe1030e004 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0xfffe1030e006 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0xfffe1030e008 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0xfffe1030e009 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0xfffe1030e00a +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0xfffe1030e00b +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0xfffe1030e00c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0xfffe1030e00d +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0xfffe1030e00e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0xfffe1030e00f +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0xfffe1030e010 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0xfffe1030e014 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0xfffe1030e018 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0xfffe1030e01c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0xfffe1030e020 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0xfffe1030e024 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR 0xfffe1030e028 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0xfffe1030e02c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0xfffe1030e030 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0xfffe1030e034 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0xfffe1030e03c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0xfffe1030e03d +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT 0xfffe1030e03e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY 0xfffe1030e03f +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0xfffe1030e064 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0xfffe1030e066 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0xfffe1030e068 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0xfffe1030e06c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0xfffe1030e06e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0xfffe1030e070 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0xfffe1030e074 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0xfffe1030e076 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0xfffe1030e088 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0xfffe1030e08c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0xfffe1030e08e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0xfffe1030e090 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0xfffe1030e094 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0xfffe1030e096 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0xfffe1030e0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0xfffe1030e0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0xfffe1030e0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0xfffe1030e0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0xfffe1030e0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA 0xfffe1030e0aa +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0xfffe1030e0ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0xfffe1030e0ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64 0xfffe1030e0ae +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0xfffe1030e0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0xfffe1030e0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0xfffe1030e0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0xfffe1030e0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0xfffe1030e0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0xfffe1030e0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0xfffe1030e0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030e100 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030e104 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030e108 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030e10c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030e150 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030e154 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0xfffe1030e158 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030e15c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0xfffe1030e160 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0xfffe1030e164 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030e168 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0xfffe1030e16c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0xfffe1030e170 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0xfffe1030e174 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0xfffe1030e178 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030e188 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030e18c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030e190 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030e194 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030e328 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0xfffe1030e32c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0xfffe1030e32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +// base address: 0xfffe1030f000 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0xfffe1030f000 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0xfffe1030f002 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0xfffe1030f004 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0xfffe1030f006 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0xfffe1030f008 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0xfffe1030f009 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0xfffe1030f00a +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0xfffe1030f00b +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0xfffe1030f00c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0xfffe1030f00d +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0xfffe1030f00e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0xfffe1030f00f +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0xfffe1030f010 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0xfffe1030f014 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0xfffe1030f018 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0xfffe1030f01c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0xfffe1030f020 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0xfffe1030f024 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR 0xfffe1030f028 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0xfffe1030f02c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0xfffe1030f030 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0xfffe1030f034 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0xfffe1030f03c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0xfffe1030f03d +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT 0xfffe1030f03e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY 0xfffe1030f03f +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0xfffe1030f064 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0xfffe1030f066 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0xfffe1030f068 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0xfffe1030f06c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0xfffe1030f06e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0xfffe1030f070 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0xfffe1030f074 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0xfffe1030f076 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0xfffe1030f088 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0xfffe1030f08c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0xfffe1030f08e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0xfffe1030f090 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0xfffe1030f094 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0xfffe1030f096 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0xfffe1030f0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0xfffe1030f0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0xfffe1030f0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0xfffe1030f0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0xfffe1030f0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA 0xfffe1030f0aa +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0xfffe1030f0ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0xfffe1030f0ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64 0xfffe1030f0ae +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0xfffe1030f0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0xfffe1030f0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0xfffe1030f0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0xfffe1030f0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0xfffe1030f0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0xfffe1030f0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0xfffe1030f0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030f100 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030f104 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030f108 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030f10c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030f150 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030f154 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0xfffe1030f158 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030f15c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0xfffe1030f160 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0xfffe1030f164 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030f168 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0xfffe1030f16c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0xfffe1030f170 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0xfffe1030f174 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0xfffe1030f178 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030f188 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030f18c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030f190 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030f194 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030f328 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0xfffe1030f32c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0xfffe1030f32e + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0xd0000000 +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0xd000382c +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0xd0003830 +#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd000384c +#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0003850 +#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0003854 +#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0003858 +#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd000385c +#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0003864 +#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0003868 +#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0xd0003898 +#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0xd000389c +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0xd00038a0 +#define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0xd00038c8 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0xd0003958 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0xd000395c +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0xd0003960 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0xd0003964 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0xd0003968 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0xd000396c +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0xd0003970 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0xd0003974 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0xd0003978 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0xd000397c +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0xd0003980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0xd0000000 +#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0xd0000000 +#define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA 0xd0000004 +#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0xd0000018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0xd0000000 +#define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0xd0003694 +#define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0xd0003780 +#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0xd000378c +#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0xd0003790 +#define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0xd0003794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0xd0000000 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0xd0042000 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0xd0042004 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0xd0042008 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0xd004200c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0xd0042010 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0xd0042014 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0xd0042018 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0xd004201c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0xd0042020 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0xd0042024 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0xd0042028 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0xd004202c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0xd0042030 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0xd0042034 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0xd0042038 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0xd004203c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0xd0043000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0xd0080000 +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0xd008382c +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0xd0083830 +#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd008384c +#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0083850 +#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0083854 +#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0083858 +#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd008385c +#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0083864 +#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0083868 +#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0xd0083898 +#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0xd008389c +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0xd00838a0 +#define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0xd00838c8 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0xd0083958 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0xd008395c +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0xd0083960 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0xd0083964 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0xd0083968 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0xd008396c +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0xd0083970 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0xd0083974 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0xd0083978 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0xd008397c +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0xd0083980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0xd0080000 +#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0xd0080000 +#define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA 0xd0080004 +#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0xd0080018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0xd0080000 +#define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0xd0083694 +#define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0xd0083780 +#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0xd008378c +#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0xd0083790 +#define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0xd0083794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0xd0080000 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0xd00c2000 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0xd00c2004 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0xd00c2008 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0xd00c200c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0xd00c2010 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0xd00c2014 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0xd00c2018 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0xd00c201c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0xd00c2020 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0xd00c2024 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0xd00c2028 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0xd00c202c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0xd00c2030 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0xd00c2034 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0xd00c2038 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0xd00c203c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0xd00c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0xd0100000 +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0xd010382c +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0xd0103830 +#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd010384c +#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0103850 +#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0103854 +#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0103858 +#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd010385c +#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0103864 +#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0103868 +#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0xd0103898 +#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0xd010389c +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0xd01038a0 +#define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0xd01038c8 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0xd0103958 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0xd010395c +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0xd0103960 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0xd0103964 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0xd0103968 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0xd010396c +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0xd0103970 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0xd0103974 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0xd0103978 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0xd010397c +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0xd0103980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0xd0100000 +#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0xd0100000 +#define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA 0xd0100004 +#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0xd0100018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0xd0100000 +#define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0xd0103694 +#define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0xd0103780 +#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0xd010378c +#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0xd0103790 +#define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0xd0103794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0xd0100000 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0xd0142000 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0xd0142004 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0xd0142008 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0xd014200c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0xd0142010 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0xd0142014 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0xd0142018 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0xd014201c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0xd0142020 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0xd0142024 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0xd0142028 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0xd014202c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0xd0142030 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0xd0142034 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0xd0142038 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0xd014203c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0xd0143000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0xd0180000 +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0xd018382c +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0xd0183830 +#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd018384c +#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0183850 +#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0183854 +#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0183858 +#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd018385c +#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0183864 +#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0183868 +#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0xd0183898 +#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0xd018389c +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0xd01838a0 +#define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0xd01838c8 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0xd0183958 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0xd018395c +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0xd0183960 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0xd0183964 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0xd0183968 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0xd018396c +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0xd0183970 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0xd0183974 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0xd0183978 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0xd018397c +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0xd0183980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0xd0180000 +#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0xd0180000 +#define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA 0xd0180004 +#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0xd0180018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0xd0180000 +#define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0xd0183694 +#define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0xd0183780 +#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0xd018378c +#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0xd0183790 +#define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0xd0183794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0xd0180000 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0xd01c2000 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0xd01c2004 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0xd01c2008 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0xd01c200c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0xd01c2010 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0xd01c2014 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0xd01c2018 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0xd01c201c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0xd01c2020 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0xd01c2024 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0xd01c2028 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0xd01c202c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0xd01c2030 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0xd01c2034 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0xd01c2038 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0xd01c203c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0xd01c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0xd0200000 +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0xd020382c +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0xd0203830 +#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd020384c +#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0203850 +#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0203854 +#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0203858 +#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd020385c +#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0203864 +#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0203868 +#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0xd0203898 +#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0xd020389c +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0xd02038a0 +#define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0xd02038c8 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0xd0203958 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0xd020395c +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0xd0203960 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0xd0203964 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0xd0203968 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0xd020396c +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0xd0203970 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0xd0203974 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0xd0203978 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0xd020397c +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0xd0203980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0xd0200000 +#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0xd0200000 +#define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA 0xd0200004 +#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0xd0200018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0xd0200000 +#define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0xd0203694 +#define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0xd0203780 +#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0xd020378c +#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0xd0203790 +#define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0xd0203794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0xd0200000 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0xd0242000 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0xd0242004 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0xd0242008 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0xd024200c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0xd0242010 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0xd0242014 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0xd0242018 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0xd024201c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0xd0242020 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0xd0242024 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0xd0242028 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0xd024202c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0xd0242030 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0xd0242034 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0xd0242038 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0xd024203c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0xd0243000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0xd0280000 +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0xd028382c +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0xd0283830 +#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd028384c +#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0283850 +#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0283854 +#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0283858 +#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd028385c +#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0283864 +#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0283868 +#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0xd0283898 +#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0xd028389c +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0xd02838a0 +#define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0xd02838c8 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0xd0283958 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0xd028395c +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0xd0283960 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0xd0283964 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0xd0283968 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0xd028396c +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0xd0283970 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0xd0283974 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0xd0283978 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0xd028397c +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0xd0283980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0xd0280000 +#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0xd0280000 +#define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA 0xd0280004 +#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0xd0280018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0xd0280000 +#define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0xd0283694 +#define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0xd0283780 +#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0xd028378c +#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0xd0283790 +#define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0xd0283794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0xd0280000 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0xd02c2000 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0xd02c2004 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0xd02c2008 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0xd02c200c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0xd02c2010 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0xd02c2014 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0xd02c2018 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0xd02c201c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0xd02c2020 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0xd02c2024 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0xd02c2028 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0xd02c202c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0xd02c2030 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0xd02c2034 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0xd02c2038 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0xd02c203c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0xd02c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0xd0300000 +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0xd030382c +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0xd0303830 +#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd030384c +#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0303850 +#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0303854 +#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0303858 +#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd030385c +#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0303864 +#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0303868 +#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0xd0303898 +#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0xd030389c +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0xd03038a0 +#define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0xd03038c8 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0xd0303958 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0xd030395c +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0xd0303960 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0xd0303964 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0xd0303968 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0xd030396c +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0xd0303970 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0xd0303974 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0xd0303978 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0xd030397c +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0xd0303980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0xd0300000 +#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0xd0300000 +#define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA 0xd0300004 +#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0xd0300018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0xd0300000 +#define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0xd0303694 +#define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0xd0303780 +#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0xd030378c +#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0xd0303790 +#define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0xd0303794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0xd0300000 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0xd0342000 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0xd0342004 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0xd0342008 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0xd034200c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0xd0342010 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0xd0342014 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0xd0342018 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0xd034201c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0xd0342020 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0xd0342024 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0xd0342028 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0xd034202c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0xd0342030 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0xd0342034 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0xd0342038 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0xd034203c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0xd0343000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0xd0380000 +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0xd038382c +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0xd0383830 +#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd038384c +#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0383850 +#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0383854 +#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0383858 +#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd038385c +#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0383864 +#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0383868 +#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0xd0383898 +#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0xd038389c +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0xd03838a0 +#define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0xd03838c8 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0xd0383958 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0xd038395c +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0xd0383960 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0xd0383964 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0xd0383968 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0xd038396c +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0xd0383970 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0xd0383974 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0xd0383978 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0xd038397c +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0xd0383980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0xd0380000 +#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0xd0380000 +#define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA 0xd0380004 +#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0xd0380018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0xd0380000 +#define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0xd0383694 +#define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0xd0383780 +#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0xd038378c +#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0xd0383790 +#define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0xd0383794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0xd0380000 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0xd03c2000 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0xd03c2004 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0xd03c2008 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0xd03c200c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0xd03c2010 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0xd03c2014 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0xd03c2018 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0xd03c201c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0xd03c2020 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0xd03c2024 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0xd03c2028 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0xd03c202c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0xd03c2030 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0xd03c2034 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0xd03c2038 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0xd03c203c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0xd03c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0xd0400000 +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0xd040382c +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0xd0403830 +#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd040384c +#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0403850 +#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0403854 +#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0403858 +#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd040385c +#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0403864 +#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0403868 +#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0xd0403898 +#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0xd040389c +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0xd04038a0 +#define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0xd04038c8 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0xd0403958 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0xd040395c +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0xd0403960 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0xd0403964 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0xd0403968 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0xd040396c +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0xd0403970 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0xd0403974 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0xd0403978 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0xd040397c +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0xd0403980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC +// base address: 0xd0400000 +#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0xd0400000 +#define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA 0xd0400004 +#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0xd0400018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0xd0400000 +#define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0xd0403694 +#define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0xd0403780 +#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0xd040378c +#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0xd0403790 +#define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0xd0403794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 +// base address: 0xd0400000 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0xd0442000 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0xd0442004 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0xd0442008 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0xd044200c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0xd0442010 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0xd0442014 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0xd0442018 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0xd044201c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0xd0442020 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0xd0442024 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0xd0442028 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0xd044202c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0xd0442030 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0xd0442034 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0xd0442038 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0xd044203c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0xd0443000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0xd0480000 +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0xd048382c +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0xd0483830 +#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd048384c +#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0483850 +#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0483854 +#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0483858 +#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd048385c +#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0483864 +#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0483868 +#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0xd0483898 +#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0xd048389c +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0xd04838a0 +#define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0xd04838c8 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0xd0483958 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0xd048395c +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0xd0483960 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0xd0483964 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0xd0483968 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0xd048396c +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0xd0483970 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0xd0483974 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0xd0483978 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0xd048397c +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0xd0483980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC +// base address: 0xd0480000 +#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0xd0480000 +#define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA 0xd0480004 +#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0xd0480018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0xd0480000 +#define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0xd0483694 +#define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0xd0483780 +#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0xd048378c +#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0xd0483790 +#define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0xd0483794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 +// base address: 0xd0480000 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0xd04c2000 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0xd04c2004 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0xd04c2008 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0xd04c200c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0xd04c2010 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0xd04c2014 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0xd04c2018 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0xd04c201c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0xd04c2020 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0xd04c2024 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0xd04c2028 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0xd04c202c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0xd04c2030 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0xd04c2034 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0xd04c2038 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0xd04c203c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0xd04c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0xd0500000 +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0xd050382c +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0xd0503830 +#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd050384c +#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0503850 +#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0503854 +#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0503858 +#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd050385c +#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0503864 +#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0503868 +#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0xd0503898 +#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0xd050389c +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0xd05038a0 +#define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0xd05038c8 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0xd0503958 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0xd050395c +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0xd0503960 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0xd0503964 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0xd0503968 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0xd050396c +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0xd0503970 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0xd0503974 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0xd0503978 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0xd050397c +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0xd0503980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC +// base address: 0xd0500000 +#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0xd0500000 +#define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA 0xd0500004 +#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0xd0500018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0xd0500000 +#define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0xd0503694 +#define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0xd0503780 +#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0xd050378c +#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0xd0503790 +#define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0xd0503794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 +// base address: 0xd0500000 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0xd0542000 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0xd0542004 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0xd0542008 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0xd054200c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0xd0542010 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0xd0542014 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0xd0542018 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0xd054201c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0xd0542020 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0xd0542024 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0xd0542028 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0xd054202c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0xd0542030 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0xd0542034 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0xd0542038 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0xd054203c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0xd0543000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0xd0580000 +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0xd058382c +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0xd0583830 +#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd058384c +#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0583850 +#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0583854 +#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0583858 +#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd058385c +#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0583864 +#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0583868 +#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0xd0583898 +#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0xd058389c +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0xd05838a0 +#define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0xd05838c8 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0xd0583958 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0xd058395c +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0xd0583960 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0xd0583964 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0xd0583968 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0xd058396c +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0xd0583970 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0xd0583974 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0xd0583978 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0xd058397c +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0xd0583980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC +// base address: 0xd0580000 +#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0xd0580000 +#define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA 0xd0580004 +#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0xd0580018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0xd0580000 +#define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0xd0583694 +#define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0xd0583780 +#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0xd058378c +#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0xd0583790 +#define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0xd0583794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 +// base address: 0xd0580000 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0xd05c2000 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0xd05c2004 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0xd05c2008 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0xd05c200c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0xd05c2010 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0xd05c2014 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0xd05c2018 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0xd05c201c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0xd05c2020 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0xd05c2024 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0xd05c2028 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0xd05c202c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0xd05c2030 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0xd05c2034 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0xd05c2038 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0xd05c203c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0xd05c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0xd0600000 +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0xd060382c +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0xd0603830 +#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd060384c +#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0603850 +#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0603854 +#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0603858 +#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd060385c +#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0603864 +#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0603868 +#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0xd0603898 +#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0xd060389c +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0xd06038a0 +#define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0xd06038c8 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0xd0603958 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0xd060395c +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0xd0603960 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0xd0603964 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0xd0603968 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0xd060396c +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0xd0603970 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0xd0603974 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0xd0603978 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0xd060397c +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0xd0603980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC +// base address: 0xd0600000 +#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0xd0600000 +#define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA 0xd0600004 +#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0xd0600018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0xd0600000 +#define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0xd0603694 +#define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0xd0603780 +#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0xd060378c +#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0xd0603790 +#define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0xd0603794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 +// base address: 0xd0600000 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0xd0642000 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0xd0642004 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0xd0642008 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0xd064200c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0xd0642010 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0xd0642014 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0xd0642018 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0xd064201c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0xd0642020 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0xd0642024 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0xd0642028 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0xd064202c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0xd0642030 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0xd0642034 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0xd0642038 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0xd064203c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0xd0643000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0xd0680000 +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0xd068382c +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0xd0683830 +#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd068384c +#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0683850 +#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0683854 +#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0683858 +#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd068385c +#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0683864 +#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0683868 +#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0xd0683898 +#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0xd068389c +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0xd06838a0 +#define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0xd06838c8 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0xd0683958 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0xd068395c +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0xd0683960 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0xd0683964 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0xd0683968 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0xd068396c +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0xd0683970 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0xd0683974 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0xd0683978 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0xd068397c +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0xd0683980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC +// base address: 0xd0680000 +#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0xd0680000 +#define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA 0xd0680004 +#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0xd0680018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0xd0680000 +#define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0xd0683694 +#define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0xd0683780 +#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0xd068378c +#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0xd0683790 +#define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0xd0683794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 +// base address: 0xd0680000 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0xd06c2000 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0xd06c2004 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0xd06c2008 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0xd06c200c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0xd06c2010 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0xd06c2014 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0xd06c2018 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0xd06c201c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0xd06c2020 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0xd06c2024 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0xd06c2028 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0xd06c202c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0xd06c2030 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0xd06c2034 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0xd06c2038 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0xd06c203c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0xd06c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0xd0700000 +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0xd070382c +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0xd0703830 +#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd070384c +#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0703850 +#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0703854 +#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0703858 +#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd070385c +#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0703864 +#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0703868 +#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0xd0703898 +#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0xd070389c +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0xd07038a0 +#define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0xd07038c8 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0xd0703958 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0xd070395c +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0xd0703960 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0xd0703964 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0xd0703968 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0xd070396c +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0xd0703970 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0xd0703974 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0xd0703978 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0xd070397c +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0xd0703980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC +// base address: 0xd0700000 +#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0xd0700000 +#define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA 0xd0700004 +#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0xd0700018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0xd0700000 +#define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0xd0703694 +#define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0xd0703780 +#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0xd070378c +#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0xd0703790 +#define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0xd0703794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 +// base address: 0xd0700000 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0xd0742000 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0xd0742004 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0xd0742008 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0xd074200c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0xd0742010 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0xd0742014 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0xd0742018 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0xd074201c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0xd0742020 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0xd0742024 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0xd0742028 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0xd074202c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0xd0742030 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0xd0742034 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0xd0742038 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0xd074203c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0xd0743000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0xd0780000 +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0xd078382c +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0xd0783830 +#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd078384c +#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0783850 +#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0783854 +#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0783858 +#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd078385c +#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0783864 +#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0783868 +#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0xd0783898 +#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0xd078389c +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0xd07838a0 +#define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0xd07838c8 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0xd0783958 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0xd078395c +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0xd0783960 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0xd0783964 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0xd0783968 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0xd078396c +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0xd0783970 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0xd0783974 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0xd0783978 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0xd078397c +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0xd0783980 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC +// base address: 0xd0780000 +#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0xd0780000 +#define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA 0xd0780004 +#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0xd0780018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0xd0780000 +#define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0xd0783694 +#define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0xd0783780 +#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0xd078378c +#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0xd0783790 +#define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0xd0783794 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 +// base address: 0xd0780000 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0xd07c2000 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0xd07c2004 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0xd07c2008 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0xd07c200c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0xd07c2010 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0xd07c2014 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0xd07c2018 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0xd07c201c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0xd07c2020 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0xd07c2024 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0xd07c2028 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0xd07c202c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0xd07c2030 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0xd07c2034 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0xd07c2038 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0xd07c203c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0xd07c3000 + + +// addressBlock: nbio_pcie0_pswusp0_pciedir_p +// base address: 0x1a340000 +#define regPCIEP_RESERVED 0x2890000 +#define regPCIEP_RESERVED_BASE_IDX 5 +#define regPCIEP_SCRATCH 0x2890001 +#define regPCIEP_SCRATCH_BASE_IDX 5 +#define regPCIEP_PORT_CNTL 0x2890010 +#define regPCIEP_PORT_CNTL_BASE_IDX 5 +#define regPCIE_TX_REQUESTER_ID 0x2890021 +#define regPCIE_TX_REQUESTER_ID_BASE_IDX 5 +#define regPCIE_P_PORT_LANE_STATUS 0x2890050 +#define regPCIE_P_PORT_LANE_STATUS_BASE_IDX 5 +#define regPSWUSP0_PCIE_ERR_CNTL 0x289006a +#define regPSWUSP0_PCIE_ERR_CNTL_BASE_IDX 5 +#define regPSWUSP0_PCIE_RX_CNTL 0x2890070 +#define regPSWUSP0_PCIE_RX_CNTL_BASE_IDX 5 +#define regPCIE_RX_EXPECTED_SEQNUM 0x2890071 +#define regPCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 +#define regPCIE_RX_VENDOR_SPECIFIC 0x2890072 +#define regPCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 +#define regPCIE_RX_CNTL3 0x2890074 +#define regPCIE_RX_CNTL3_BASE_IDX 5 +#define regPCIE_RX_CREDITS_ALLOCATED_P 0x2890080 +#define regPCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 +#define regPCIE_RX_CREDITS_ALLOCATED_NP 0x2890081 +#define regPCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 +#define regPCIE_RX_CREDITS_ALLOCATED_CPL 0x2890082 +#define regPCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 +#define regPCIEP_ERROR_INJECT_PHYSICAL 0x2890083 +#define regPCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 +#define regPCIEP_ERROR_INJECT_TRANSACTION 0x2890084 +#define regPCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 +#define regPCIEP_NAK_COUNTER 0x2890086 +#define regPCIEP_NAK_COUNTER_BASE_IDX 5 +#define regPCIE_LC_CNTL 0x28900a0 +#define regPCIE_LC_CNTL_BASE_IDX 5 +#define regPCIE_LC_TRAINING_CNTL 0x28900a1 +#define regPCIE_LC_TRAINING_CNTL_BASE_IDX 5 +#define regPCIE_LC_LINK_WIDTH_CNTL 0x28900a2 +#define regPCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 +#define regPCIE_LC_N_FTS_CNTL 0x28900a3 +#define regPCIE_LC_N_FTS_CNTL_BASE_IDX 5 +#define regPSWUSP0_PCIE_LC_SPEED_CNTL 0x28900a4 +#define regPSWUSP0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regPCIE_LC_STATE0 0x28900a5 +#define regPCIE_LC_STATE0_BASE_IDX 5 +#define regPCIE_LC_STATE1 0x28900a6 +#define regPCIE_LC_STATE1_BASE_IDX 5 +#define regPCIE_LC_STATE2 0x28900a7 +#define regPCIE_LC_STATE2_BASE_IDX 5 +#define regPCIE_LC_STATE3 0x28900a8 +#define regPCIE_LC_STATE3_BASE_IDX 5 +#define regPCIE_LC_STATE4 0x28900a9 +#define regPCIE_LC_STATE4_BASE_IDX 5 +#define regPCIE_LC_STATE5 0x28900aa +#define regPCIE_LC_STATE5_BASE_IDX 5 +#define regPSWUSP0_PCIE_LC_CNTL2 0x28900b1 +#define regPSWUSP0_PCIE_LC_CNTL2_BASE_IDX 5 +#define regPCIE_LC_BW_CHANGE_CNTL 0x28900b2 +#define regPCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 +#define regPCIE_LC_CDR_CNTL 0x28900b3 +#define regPCIE_LC_CDR_CNTL_BASE_IDX 5 +#define regPCIE_LC_LANE_CNTL 0x28900b4 +#define regPCIE_LC_LANE_CNTL_BASE_IDX 5 +#define regPCIE_LC_CNTL3 0x28900b5 +#define regPCIE_LC_CNTL3_BASE_IDX 5 +#define regPCIE_LC_CNTL4 0x28900b6 +#define regPCIE_LC_CNTL4_BASE_IDX 5 +#define regPCIE_LC_CNTL5 0x28900b7 +#define regPCIE_LC_CNTL5_BASE_IDX 5 +#define regPCIE_LC_FORCE_COEFF 0x28900b8 +#define regPCIE_LC_FORCE_COEFF_BASE_IDX 5 +#define regPCIE_LC_BEST_EQ_SETTINGS 0x28900b9 +#define regPCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 +#define regPCIE_LC_FORCE_EQ_REQ_COEFF 0x28900ba +#define regPCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 +#define regPCIE_LC_CNTL6 0x28900bb +#define regPCIE_LC_CNTL6_BASE_IDX 5 +#define regPCIE_LC_CNTL7 0x28900bc +#define regPCIE_LC_CNTL7_BASE_IDX 5 +#define regPCIEP_STRAP_LC 0x28900c0 +#define regPCIEP_STRAP_LC_BASE_IDX 5 +#define regPSWUSP0_PCIEP_STRAP_MISC 0x28900c1 +#define regPSWUSP0_PCIEP_STRAP_MISC_BASE_IDX 5 +#define regPCIEP_STRAP_LC2 0x28900c2 +#define regPCIEP_STRAP_LC2_BASE_IDX 5 +#define regPCIE_LC_L1_PM_SUBSTATE 0x28900c6 +#define regPCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 +#define regPCIE_LC_L1_PM_SUBSTATE2 0x28900c7 +#define regPCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 +#define regPCIE_LC_L1_PM_SUBSTATE3 0x28900c8 +#define regPCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 +#define regPCIE_LC_L1_PM_SUBSTATE4 0x28900c9 +#define regPCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 +#define regPCIE_LC_L1_PM_SUBSTATE5 0x28900ca +#define regPCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 +#define regPCIEP_BCH_ECC_CNTL 0x28900d0 +#define regPCIEP_BCH_ECC_CNTL_BASE_IDX 5 +#define regPCIE_LC_CNTL8 0x28900dd +#define regPCIE_LC_CNTL8_BASE_IDX 5 +#define regPCIE_LC_CNTL9 0x28900de +#define regPCIE_LC_CNTL9_BASE_IDX 5 +#define regPCIE_LC_FORCE_COEFF2 0x28900df +#define regPCIE_LC_FORCE_COEFF2_BASE_IDX 5 +#define regPCIE_LC_FORCE_EQ_REQ_COEFF2 0x28900e0 +#define regPCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 +#define regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x28900e2 +#define regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 +#define regPCIE_LC_CNTL10 0x28900e3 +#define regPCIE_LC_CNTL10_BASE_IDX 5 +#define regPCIE_LC_SAVE_RESTORE_1 0x28900e6 +#define regPCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 +#define regPCIE_LC_SAVE_RESTORE_2 0x28900e7 +#define regPCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 +#define regPCIE_LC_CNTL11 0x2890103 +#define regPCIE_LC_CNTL11_BASE_IDX 5 +#define regPCIE_LC_CNTL12 0x2890104 +#define regPCIE_LC_CNTL12_BASE_IDX 5 +#define regPCIE_LC_SPEED_CNTL2 0x2890105 +#define regPCIE_LC_SPEED_CNTL2_BASE_IDX 5 +#define regPCIE_LC_FORCE_COEFF3 0x2890106 +#define regPCIE_LC_FORCE_COEFF3_BASE_IDX 5 +#define regPCIE_LC_FORCE_EQ_REQ_COEFF3 0x2890107 +#define regPCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 +#define regPCIE_TX_SEQ 0x2890188 +#define regPCIE_TX_SEQ_BASE_IDX 5 +#define regPCIE_TX_REPLAY 0x2890189 +#define regPCIE_TX_REPLAY_BASE_IDX 5 +#define regPCIE_TX_ACK_LATENCY_LIMIT 0x289018c +#define regPCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 +#define regPCIE_TX_CREDITS_FCU_THRESHOLD 0x2890190 +#define regPCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 +#define regPCIE_TX_VENDOR_SPECIFIC 0x2890194 +#define regPCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 +#define regPCIE_TX_NOP_DLLP 0x2890195 +#define regPCIE_TX_NOP_DLLP_BASE_IDX 5 +#define regPCIE_TX_REQUEST_NUM_CNTL 0x2890198 +#define regPCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 +#define regPCIE_TX_CREDITS_ADVT_P 0x28901a0 +#define regPCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 +#define regPCIE_TX_CREDITS_ADVT_NP 0x28901a1 +#define regPCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 +#define regPCIE_TX_CREDITS_ADVT_CPL 0x28901a2 +#define regPCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 +#define regPCIE_TX_CREDITS_INIT_P 0x28901a3 +#define regPCIE_TX_CREDITS_INIT_P_BASE_IDX 5 +#define regPCIE_TX_CREDITS_INIT_NP 0x28901a4 +#define regPCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 +#define regPCIE_TX_CREDITS_INIT_CPL 0x28901a5 +#define regPCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 +#define regPCIE_TX_CREDITS_STATUS 0x28901a6 +#define regPCIE_TX_CREDITS_STATUS_BASE_IDX 5 +#define regPCIE_FC_P 0x28901a8 +#define regPCIE_FC_P_BASE_IDX 5 +#define regPCIE_FC_NP 0x28901a9 +#define regPCIE_FC_NP_BASE_IDX 5 +#define regPCIE_FC_CPL 0x28901aa +#define regPCIE_FC_CPL_BASE_IDX 5 +#define regPCIE_FC_P_VC1 0x28901ab +#define regPCIE_FC_P_VC1_BASE_IDX 5 +#define regPCIE_FC_NP_VC1 0x28901ac +#define regPCIE_FC_NP_VC1_BASE_IDX 5 +#define regPCIE_FC_CPL_VC1 0x28901ad +#define regPCIE_FC_CPL_VC1_BASE_IDX 5 + + +// addressBlock: nbio_pcie0_pciedir +// base address: 0x1a380000 +#define regPCIE_RESERVED 0x28a0000 +#define regPCIE_RESERVED_BASE_IDX 5 +#define regPCIE_SCRATCH 0x28a0001 +#define regPCIE_SCRATCH_BASE_IDX 5 +#define regPCIE_RX_NUM_NAK 0x28a000e +#define regPCIE_RX_NUM_NAK_BASE_IDX 5 +#define regPCIE_RX_NUM_NAK_GENERATED 0x28a000f +#define regPCIE_RX_NUM_NAK_GENERATED_BASE_IDX 5 +#define regPCIE_CNTL 0x28a0010 +#define regPCIE_CNTL_BASE_IDX 5 +#define regPCIE_CONFIG_CNTL 0x28a0011 +#define regPCIE_CONFIG_CNTL_BASE_IDX 5 +#define regPCIE_RX_CNTL5 0x28a0018 +#define regPCIE_RX_CNTL5_BASE_IDX 5 +#define regPCIE_RX_CNTL4 0x28a0019 +#define regPCIE_RX_CNTL4_BASE_IDX 5 +#define regPCIE_COMMON_AER_MASK 0x28a001a +#define regPCIE_COMMON_AER_MASK_BASE_IDX 5 +#define regPCIE_CNTL2 0x28a001c +#define regPCIE_CNTL2_BASE_IDX 5 +#define regPCIE_RX_CNTL2 0x28a001d +#define regPCIE_RX_CNTL2_BASE_IDX 5 +#define regPCIE_CI_CNTL 0x28a0020 +#define regPCIE_CI_CNTL_BASE_IDX 5 +#define regPCIE_BUS_CNTL 0x28a0021 +#define regPCIE_BUS_CNTL_BASE_IDX 5 +#define regPCIE_LC_STATE6 0x28a0022 +#define regPCIE_LC_STATE6_BASE_IDX 5 +#define regPCIE_LC_STATE7 0x28a0023 +#define regPCIE_LC_STATE7_BASE_IDX 5 +#define regPCIE_LC_STATE8 0x28a0024 +#define regPCIE_LC_STATE8_BASE_IDX 5 +#define regPCIE_LC_STATE9 0x28a0025 +#define regPCIE_LC_STATE9_BASE_IDX 5 +#define regPCIE_LC_STATE10 0x28a0026 +#define regPCIE_LC_STATE10_BASE_IDX 5 +#define regPCIE_LC_STATE11 0x28a0027 +#define regPCIE_LC_STATE11_BASE_IDX 5 +#define regPCIE_LC_STATUS1 0x28a0028 +#define regPCIE_LC_STATUS1_BASE_IDX 5 +#define regPCIE_LC_STATUS2 0x28a0029 +#define regPCIE_LC_STATUS2_BASE_IDX 5 +#define regPCIE_WPR_CNTL 0x28a0030 +#define regPCIE_WPR_CNTL_BASE_IDX 5 +#define regPCIE_RX_LAST_TLP0 0x28a0031 +#define regPCIE_RX_LAST_TLP0_BASE_IDX 5 +#define regPCIE_RX_LAST_TLP1 0x28a0032 +#define regPCIE_RX_LAST_TLP1_BASE_IDX 5 +#define regPCIE_RX_LAST_TLP2 0x28a0033 +#define regPCIE_RX_LAST_TLP2_BASE_IDX 5 +#define regPCIE_RX_LAST_TLP3 0x28a0034 +#define regPCIE_RX_LAST_TLP3_BASE_IDX 5 +#define regPCIE_I2C_REG_ADDR_EXPAND 0x28a003a +#define regPCIE_I2C_REG_ADDR_EXPAND_BASE_IDX 5 +#define regPCIE_I2C_REG_DATA 0x28a003b +#define regPCIE_I2C_REG_DATA_BASE_IDX 5 +#define regPCIE_CFG_CNTL 0x28a003c +#define regPCIE_CFG_CNTL_BASE_IDX 5 +#define regPCIE_LC_PM_CNTL 0x28a003d +#define regPCIE_LC_PM_CNTL_BASE_IDX 5 +#define regPCIE_LC_PM_CNTL2 0x28a003e +#define regPCIE_LC_PM_CNTL2_BASE_IDX 5 +#define regPCIE_P_CNTL 0x28a0040 +#define regPCIE_P_CNTL_BASE_IDX 5 +#define regPCIE_P_BUF_STATUS 0x28a0041 +#define regPCIE_P_BUF_STATUS_BASE_IDX 5 +#define regPCIE_P_DECODER_STATUS 0x28a0042 +#define regPCIE_P_DECODER_STATUS_BASE_IDX 5 +#define regPCIE_P_MISC_STATUS 0x28a0043 +#define regPCIE_P_MISC_STATUS_BASE_IDX 5 +#define regPCIE_P_RCV_L0S_FTS_DET 0x28a0050 +#define regPCIE_P_RCV_L0S_FTS_DET_BASE_IDX 5 +#define regPCIE_RX_AD 0x28a0062 +#define regPCIE_RX_AD_BASE_IDX 5 +#define regPCIE_SDP_CTRL 0x28a0063 +#define regPCIE_SDP_CTRL_BASE_IDX 5 +#define regPCIE_SDP_SWUS_SLV_ATTR_CTRL 0x28a0065 +#define regPCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX 5 +#define regPCIE_SDP_CTRL2 0x28a0068 +#define regPCIE_SDP_CTRL2_BASE_IDX 5 +#define regPCIE_PERF_COUNT_CNTL 0x28a0080 +#define regPCIE_PERF_COUNT_CNTL_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK1 0x28a0081 +#define regPCIE_PERF_CNTL_TXCLK1_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK1 0x28a0082 +#define regPCIE_PERF_COUNT0_TXCLK1_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK1 0x28a0083 +#define regPCIE_PERF_COUNT1_TXCLK1_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK2 0x28a0084 +#define regPCIE_PERF_CNTL_TXCLK2_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK2 0x28a0085 +#define regPCIE_PERF_COUNT0_TXCLK2_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK2 0x28a0086 +#define regPCIE_PERF_COUNT1_TXCLK2_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK3 0x28a0087 +#define regPCIE_PERF_CNTL_TXCLK3_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK3 0x28a0088 +#define regPCIE_PERF_COUNT0_TXCLK3_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK3 0x28a0089 +#define regPCIE_PERF_COUNT1_TXCLK3_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK4 0x28a008a +#define regPCIE_PERF_CNTL_TXCLK4_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK4 0x28a008b +#define regPCIE_PERF_COUNT0_TXCLK4_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK4 0x28a008c +#define regPCIE_PERF_COUNT1_TXCLK4_BASE_IDX 5 +#define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x28a0093 +#define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX 5 +#define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x28a0094 +#define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK5 0x28a0096 +#define regPCIE_PERF_CNTL_TXCLK5_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK5 0x28a0097 +#define regPCIE_PERF_COUNT0_TXCLK5_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK5 0x28a0098 +#define regPCIE_PERF_COUNT1_TXCLK5_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK6 0x28a0099 +#define regPCIE_PERF_CNTL_TXCLK6_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK6 0x28a009a +#define regPCIE_PERF_COUNT0_TXCLK6_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK6 0x28a009b +#define regPCIE_PERF_COUNT1_TXCLK6_BASE_IDX 5 +#define regPCIE_STRAP_F0 0x28a00b0 +#define regPCIE_STRAP_F0_BASE_IDX 5 +#define regPCIE_STRAP_MISC 0x28a00c0 +#define regPCIE_STRAP_MISC_BASE_IDX 5 +#define regPCIE_STRAP_MISC2 0x28a00c1 +#define regPCIE_STRAP_MISC2_BASE_IDX 5 +#define regPCIE_STRAP_PI 0x28a00c2 +#define regPCIE_STRAP_PI_BASE_IDX 5 +#define regPCIE_STRAP_I2C_BD 0x28a00c4 +#define regPCIE_STRAP_I2C_BD_BASE_IDX 5 +#define regPCIE_PRBS_CLR 0x28a00c8 +#define regPCIE_PRBS_CLR_BASE_IDX 5 +#define regPCIE_PRBS_STATUS1 0x28a00c9 +#define regPCIE_PRBS_STATUS1_BASE_IDX 5 +#define regPCIE_PRBS_STATUS2 0x28a00ca +#define regPCIE_PRBS_STATUS2_BASE_IDX 5 +#define regPCIE_PRBS_FREERUN 0x28a00cb +#define regPCIE_PRBS_FREERUN_BASE_IDX 5 +#define regPCIE_PRBS_MISC 0x28a00cc +#define regPCIE_PRBS_MISC_BASE_IDX 5 +#define regPCIE_PRBS_USER_PATTERN 0x28a00cd +#define regPCIE_PRBS_USER_PATTERN_BASE_IDX 5 +#define regPCIE_PRBS_LO_BITCNT 0x28a00ce +#define regPCIE_PRBS_LO_BITCNT_BASE_IDX 5 +#define regPCIE_PRBS_HI_BITCNT 0x28a00cf +#define regPCIE_PRBS_HI_BITCNT_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_0 0x28a00d0 +#define regPCIE_PRBS_ERRCNT_0_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_1 0x28a00d1 +#define regPCIE_PRBS_ERRCNT_1_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_2 0x28a00d2 +#define regPCIE_PRBS_ERRCNT_2_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_3 0x28a00d3 +#define regPCIE_PRBS_ERRCNT_3_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_4 0x28a00d4 +#define regPCIE_PRBS_ERRCNT_4_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_5 0x28a00d5 +#define regPCIE_PRBS_ERRCNT_5_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_6 0x28a00d6 +#define regPCIE_PRBS_ERRCNT_6_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_7 0x28a00d7 +#define regPCIE_PRBS_ERRCNT_7_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_8 0x28a00d8 +#define regPCIE_PRBS_ERRCNT_8_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_9 0x28a00d9 +#define regPCIE_PRBS_ERRCNT_9_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_10 0x28a00da +#define regPCIE_PRBS_ERRCNT_10_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_11 0x28a00db +#define regPCIE_PRBS_ERRCNT_11_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_12 0x28a00dc +#define regPCIE_PRBS_ERRCNT_12_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_13 0x28a00dd +#define regPCIE_PRBS_ERRCNT_13_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_14 0x28a00de +#define regPCIE_PRBS_ERRCNT_14_BASE_IDX 5 +#define regPCIE_PRBS_ERRCNT_15 0x28a00df +#define regPCIE_PRBS_ERRCNT_15_BASE_IDX 5 +#define regSWRST_COMMAND_STATUS 0x28a0100 +#define regSWRST_COMMAND_STATUS_BASE_IDX 5 +#define regSWRST_GENERAL_CONTROL 0x28a0101 +#define regSWRST_GENERAL_CONTROL_BASE_IDX 5 +#define regSWRST_COMMAND_0 0x28a0102 +#define regSWRST_COMMAND_0_BASE_IDX 5 +#define regSWRST_COMMAND_1 0x28a0103 +#define regSWRST_COMMAND_1_BASE_IDX 5 +#define regSWRST_CONTROL_0 0x28a0104 +#define regSWRST_CONTROL_0_BASE_IDX 5 +#define regSWRST_CONTROL_1 0x28a0105 +#define regSWRST_CONTROL_1_BASE_IDX 5 +#define regSWRST_CONTROL_2 0x28a0106 +#define regSWRST_CONTROL_2_BASE_IDX 5 +#define regSWRST_CONTROL_3 0x28a0107 +#define regSWRST_CONTROL_3_BASE_IDX 5 +#define regSWRST_CONTROL_4 0x28a0108 +#define regSWRST_CONTROL_4_BASE_IDX 5 +#define regSWRST_CONTROL_5 0x28a0109 +#define regSWRST_CONTROL_5_BASE_IDX 5 +#define regSWRST_CONTROL_6 0x28a010a +#define regSWRST_CONTROL_6_BASE_IDX 5 +#define regSWRST_EP_COMMAND_0 0x28a010b +#define regSWRST_EP_COMMAND_0_BASE_IDX 5 +#define regSWRST_EP_CONTROL_0 0x28a010c +#define regSWRST_EP_CONTROL_0_BASE_IDX 5 +#define regCPM_CONTROL 0x28a0118 +#define regCPM_CONTROL_BASE_IDX 5 +#define regCPM_SPLIT_CONTROL 0x28a0119 +#define regCPM_SPLIT_CONTROL_BASE_IDX 5 +#define regCPM_CONTROL_EXT 0x28a011a +#define regCPM_CONTROL_EXT_BASE_IDX 5 +#define regSMN_APERTURE_ID_A 0x28a011d +#define regSMN_APERTURE_ID_A_BASE_IDX 5 +#define regSMN_APERTURE_ID_B 0x28a011e +#define regSMN_APERTURE_ID_B_BASE_IDX 5 +#define regLNCNT_CONTROL 0x28a0125 +#define regLNCNT_CONTROL_BASE_IDX 5 +#define regSMU_INT_PIN_SHARING_PORT_INDICATOR 0x28a012f +#define regSMU_INT_PIN_SHARING_PORT_INDICATOR_BASE_IDX 5 +#define regPCIE_PGMST_CNTL 0x28a0130 +#define regPCIE_PGMST_CNTL_BASE_IDX 5 +#define regPCIE_PGSLV_CNTL 0x28a0131 +#define regPCIE_PGSLV_CNTL_BASE_IDX 5 +#define regLC_CPM_CONTROL_0 0x28a0133 +#define regLC_CPM_CONTROL_0_BASE_IDX 5 +#define regLC_CPM_CONTROL_1 0x28a0134 +#define regLC_CPM_CONTROL_1_BASE_IDX 5 +#define regPCIE_RXMARGIN_CONTROL_CAPABILITIES 0x28a0135 +#define regPCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX 5 +#define regPCIE_RXMARGIN_1_SETTINGS 0x28a0136 +#define regPCIE_RXMARGIN_1_SETTINGS_BASE_IDX 5 +#define regPCIE_RXMARGIN_2_SETTINGS 0x28a0137 +#define regPCIE_RXMARGIN_2_SETTINGS_BASE_IDX 5 +#define regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO 0x28a013a +#define regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO_BASE_IDX 5 +#define regPCIE_TX_LAST_TLP0 0x28a0180 +#define regPCIE_TX_LAST_TLP0_BASE_IDX 5 +#define regPCIE_TX_LAST_TLP1 0x28a0181 +#define regPCIE_TX_LAST_TLP1_BASE_IDX 5 +#define regPCIE_TX_LAST_TLP2 0x28a0182 +#define regPCIE_TX_LAST_TLP2_BASE_IDX 5 +#define regPCIE_TX_LAST_TLP3 0x28a0183 +#define regPCIE_TX_LAST_TLP3_BASE_IDX 5 +#define regPCIE_TX_TRACKING_ADDR_LO 0x28a0184 +#define regPCIE_TX_TRACKING_ADDR_LO_BASE_IDX 5 +#define regPCIE_TX_TRACKING_ADDR_HI 0x28a0185 +#define regPCIE_TX_TRACKING_ADDR_HI_BASE_IDX 5 +#define regPCIE_TX_TRACKING_CTRL_STATUS 0x28a0186 +#define regPCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX 5 +#define regPCIE_TX_CTRL_4 0x28a018b +#define regPCIE_TX_CTRL_4_BASE_IDX 5 +#define regPCIE_TX_STATUS 0x28a0194 +#define regPCIE_TX_STATUS_BASE_IDX 5 +#define regPCIE_TX_F0_ATTR_CNTL 0x28a019c +#define regPCIE_TX_F0_ATTR_CNTL_BASE_IDX 5 +#define regPCIE_TX_SWUS_ATTR_CNTL 0x28a019d +#define regPCIE_TX_SWUS_ATTR_CNTL_BASE_IDX 5 +#define regPCIE_MST_CTRL_1 0x28a01c4 +#define regPCIE_MST_CTRL_1_BASE_IDX 5 +#define regPCIE_HIP_REG0 0x28a01e0 +#define regPCIE_HIP_REG0_BASE_IDX 5 +#define regPCIE_HIP_REG1 0x28a01e1 +#define regPCIE_HIP_REG1_BASE_IDX 5 +#define regPCIE_HIP_REG2 0x28a01e2 +#define regPCIE_HIP_REG2_BASE_IDX 5 +#define regPCIE_HIP_REG3 0x28a01e3 +#define regPCIE_HIP_REG3_BASE_IDX 5 +#define regPCIE_HIP_REG4 0x28a01e4 +#define regPCIE_HIP_REG4_BASE_IDX 5 +#define regPCIE_HIP_REG5 0x28a01e5 +#define regPCIE_HIP_REG5_BASE_IDX 5 +#define regPCIE_HIP_REG6 0x28a01e6 +#define regPCIE_HIP_REG6_BASE_IDX 5 +#define regPCIE_HIP_REG7 0x28a01e7 +#define regPCIE_HIP_REG7_BASE_IDX 5 +#define regPCIE_HIP_REG8 0x28a01e8 +#define regPCIE_HIP_REG8_BASE_IDX 5 +#define regSMU_PCIE_FENCED1_REG 0x28a0200 +#define regSMU_PCIE_FENCED1_REG_BASE_IDX 5 +#define regSMU_PCIE_FENCED2_REG 0x28a0201 +#define regSMU_PCIE_FENCED2_REG_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK7 0x28a0222 +#define regPCIE_PERF_CNTL_TXCLK7_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK7 0x28a0223 +#define regPCIE_PERF_COUNT0_TXCLK7_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK7 0x28a0224 +#define regPCIE_PERF_COUNT1_TXCLK7_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK8 0x28a0225 +#define regPCIE_PERF_CNTL_TXCLK8_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK8 0x28a0226 +#define regPCIE_PERF_COUNT0_TXCLK8_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK8 0x28a0227 +#define regPCIE_PERF_COUNT1_TXCLK8_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK9 0x28a0228 +#define regPCIE_PERF_CNTL_TXCLK9_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK9 0x28a0229 +#define regPCIE_PERF_COUNT0_TXCLK9_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK9 0x28a022a +#define regPCIE_PERF_COUNT1_TXCLK9_BASE_IDX 5 +#define regPCIE_PERF_CNTL_TXCLK10 0x28a022b +#define regPCIE_PERF_CNTL_TXCLK10_BASE_IDX 5 +#define regPCIE_PERF_COUNT0_TXCLK10 0x28a022c +#define regPCIE_PERF_COUNT0_TXCLK10_BASE_IDX 5 +#define regPCIE_PERF_COUNT1_TXCLK10 0x28a022d +#define regPCIE_PERF_COUNT1_TXCLK10_BASE_IDX 5 + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +// base address: 0x1a300000 +#define regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x2880006 +#define regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 +#define regPSWUSCFG0_IO_BASE_LIMIT 0x2880007 +#define regPSWUSCFG0_IO_BASE_LIMIT_BASE_IDX 5 +#define regPSWUSCFG0_SECONDARY_STATUS 0x2880007 +#define regPSWUSCFG0_SECONDARY_STATUS_BASE_IDX 5 +#define regPSWUSCFG0_MEM_BASE_LIMIT 0x2880008 +#define regPSWUSCFG0_MEM_BASE_LIMIT_BASE_IDX 5 +#define regPSWUSCFG0_PREF_BASE_LIMIT 0x2880009 +#define regPSWUSCFG0_PREF_BASE_LIMIT_BASE_IDX 5 +#define regPSWUSCFG0_PREF_BASE_UPPER 0x288000a +#define regPSWUSCFG0_PREF_BASE_UPPER_BASE_IDX 5 +#define regPSWUSCFG0_PREF_LIMIT_UPPER 0x288000b +#define regPSWUSCFG0_PREF_LIMIT_UPPER_BASE_IDX 5 +#define regPSWUSCFG0_IO_BASE_LIMIT_HI 0x288000c +#define regPSWUSCFG0_IO_BASE_LIMIT_HI_BASE_IDX 5 +#define regPSWUSCFG0_SSID_CAP_LIST 0x2880030 +#define regPSWUSCFG0_SSID_CAP_LIST_BASE_IDX 5 +#define regPSWUSCFG0_SSID_CAP 0x2880031 +#define regPSWUSCFG0_SSID_CAP_BASE_IDX 5 + +#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL 0x2890102 +#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX 5 + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x10100000 +#define regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0006 +#define regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x0007 +#define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x0007 +#define regBIF_CFG_DEV0_RC_SECONDARY_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0008 +#define regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0009 +#define regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x000a +#define regBIF_CFG_DEV0_RC_PREF_BASE_UPPER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x000b +#define regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x000c +#define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI_BASE_IDX 5 +#define regSLOT_CAP 0x001b +#define regSLOT_CAP_BASE_IDX 5 +#define regSLOT_CNTL 0x001c +#define regSLOT_CNTL_BASE_IDX 5 +#define regSLOT_STATUS 0x001c +#define regSLOT_STATUS_BASE_IDX 5 +#define regSLOT_CAP2 0x0023 +#define regSLOT_CAP2_BASE_IDX 5 +#define regSLOT_CNTL2 0x0024 +#define regSLOT_CNTL2_BASE_IDX 5 +#define regSLOT_STATUS2 0x0024 +#define regSLOT_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x0030 +#define regBIF_CFG_DEV0_RC_SSID_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC_SSID_CAP 0x0031 +#define regBIF_CFG_DEV0_RC_SSID_CAP_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x10012 +#define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x10013 +#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x10014 +#define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PMI_CAP 0x10014 +#define regBIF_CFG_DEV0_EPF0_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x10015 +#define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x10044 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x10045 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x10046 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x10047 +#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x10048 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x1004a +#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x1004b +#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x1004d +#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 +#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 +#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 +#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 +#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x10055 +#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x10056 +#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x10057 +#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x10058 +#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x10059 +#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x1005a +#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x1005b +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x1005c +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x1005d +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x1005e +#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x10062 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x10063 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x10064 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x10065 +#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x10080 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x10081 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x10082 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x10083 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x10084 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x10085 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x10086 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x10087 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x10088 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x10089 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x1008a +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x1008b +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x1008c +#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x10092 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x10093 +#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x10094 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x10095 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x10096 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x10097 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x10097 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 +#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c +#define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x1009d +#define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x1009e +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x100a8 +#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x100a9 +#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x100a9 +#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x100b4 +#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x100b5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x100b5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x100bc +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x100bd +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x100bd +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x100be +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x100bf +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x100c0 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x100c1 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x100c2 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x100c3 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x100c8 +#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x100c9 +#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x100ca +#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x100cb +#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x100cb +#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x100cd +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x100ce +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x100ce +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x100d0 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x100d1 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db +#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x10101 +#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x10102 +#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 +#define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x10105 +#define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x10106 +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x10107 +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 +#define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 +#define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a +#define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 +#define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x10115 +#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x10115 +#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x10116 +#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x10116 +#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x10117 +#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x10117 +#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x10118 +#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x10118 +#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x10119 +#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x10119 +#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x1011a +#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x1011a +#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x1011b +#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x1011b +#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x1011c +#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x1011c +#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x1011d +#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x1011d +#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x1011e +#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x1011e +#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x1011f +#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x1011f +#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x10120 +#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x10120 +#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x10121 +#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x10121 +#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x10122 +#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x10122 +#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x10123 +#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x10123 +#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x10124 +#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x10124 +#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x10125 +#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x10125 +#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10130 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x10131 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x10132 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x10133 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x10134 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x10135 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x10136 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x10137 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x10138 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x10139 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x1013a +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x1013b +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x1013c +#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x10141 +#define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x10142 +#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x10143 +#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x10160000 +#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x18000 +#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x18000 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x18001 +#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x18001 +#define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x18002 +#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x18002 +#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x18002 +#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x18002 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x18003 +#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x18003 +#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x18003 +#define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x18003 +#define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x18004 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x18005 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x18006 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x18007 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x18008 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x18009 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1800a +#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1800b +#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1800c +#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1800d +#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1800f +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1800f +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1800f +#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1800f +#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x18019 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x18019 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1801a +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1801b +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1801b +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1801c +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1801d +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1801d +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x18022 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x18023 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x18023 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x18024 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x18025 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x18025 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x18028 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x18028 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x18029 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1802a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1802a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1802a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1802b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1802b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1802b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1802c +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1802c +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1802d +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x18030 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x18030 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x18031 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x18032 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18040 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x18041 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x18042 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x18043 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18054 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x18055 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x18056 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x18057 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x18058 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x18059 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x1805a +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x1805b +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x1805c +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1805d +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1805e +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x18062 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x18063 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x18064 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x18065 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x180ca +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x180cb +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x180cb +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x10161000 +#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x18400 +#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x18400 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x18401 +#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x18401 +#define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x18402 +#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x18402 +#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x18402 +#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x18402 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x18403 +#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x18403 +#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x18403 +#define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x18403 +#define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x18404 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x18405 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x18406 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x18407 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x18408 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x18409 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1840a +#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1840b +#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1840c +#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1840d +#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1840f +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1840f +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1840f +#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1840f +#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x18419 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x18419 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1841a +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1841b +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1841b +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1841c +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1841d +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1841d +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x18422 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x18423 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x18423 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x18424 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x18425 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x18425 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x18428 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x18428 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x18429 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1842a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1842a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1842a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1842b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1842b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1842b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1842c +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1842c +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1842d +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x18430 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x18430 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x18431 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x18432 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18440 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x18441 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x18442 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x18443 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18454 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x18455 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x18456 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x18457 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x18458 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x18459 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x1845a +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x1845b +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x1845c +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1845d +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1845e +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x18462 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x18463 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x18464 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x18465 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x184ca +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x184cb +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x184cb +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x10162000 +#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x18800 +#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x18800 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x18801 +#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x18801 +#define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x18802 +#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x18802 +#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x18802 +#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x18802 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x18803 +#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x18803 +#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x18803 +#define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x18803 +#define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x18804 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x18805 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x18806 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x18807 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x18808 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x18809 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1880a +#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1880b +#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1880c +#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1880d +#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1880f +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1880f +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1880f +#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1880f +#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x18819 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x18819 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1881a +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1881b +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1881b +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1881c +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1881d +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1881d +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x18822 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x18823 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x18823 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x18824 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x18825 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x18825 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x18828 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x18828 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x18829 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1882a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1882a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1882a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1882b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1882b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1882b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1882c +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1882c +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1882d +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x18830 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x18830 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x18831 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x18832 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18840 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x18841 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x18842 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x18843 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18854 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x18855 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x18856 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x18857 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x18858 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x18859 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x1885a +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x1885b +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x1885c +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1885d +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1885e +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x18862 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x18863 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x18864 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x18865 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x188ca +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x188cb +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x188cb +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x10163000 +#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x18c00 +#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x18c00 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x18c01 +#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x18c01 +#define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x18c02 +#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x18c02 +#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x18c02 +#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x18c02 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x18c03 +#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x18c03 +#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x18c03 +#define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x18c03 +#define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x18c04 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x18c05 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x18c06 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x18c07 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x18c08 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x18c09 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x18c0a +#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x18c0b +#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x18c0c +#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x18c0d +#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x18c0f +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x18c0f +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x18c0f +#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x18c0f +#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x18c19 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x18c19 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x18c1a +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x18c1b +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x18c1b +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x18c1c +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x18c1d +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x18c1d +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x18c22 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x18c23 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x18c23 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x18c24 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x18c25 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x18c25 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x18c28 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x18c28 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x18c29 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x18c2a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x18c2a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x18c2a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x18c2b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x18c2b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x18c2b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x18c2c +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x18c2c +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x18c2d +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x18c30 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x18c30 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x18c31 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x18c32 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18c40 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x18c41 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x18c42 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x18c43 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18c54 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x18c55 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x18c56 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x18c57 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x18c58 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x18c59 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x18c5a +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x18c5b +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x18c5c +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x18c5d +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x18c5e +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x18c62 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x18c63 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x18c64 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x18c65 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x18cca +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x18ccb +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x18ccb +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x10164000 +#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x19000 +#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x19000 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x19001 +#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x19001 +#define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x19002 +#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x19002 +#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x19002 +#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x19002 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x19003 +#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x19003 +#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x19003 +#define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x19003 +#define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x19004 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x19005 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x19006 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x19007 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x19008 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x19009 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1900a +#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1900b +#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1900c +#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1900d +#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1900f +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1900f +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1900f +#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1900f +#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x19019 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x19019 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1901a +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1901b +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1901b +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1901c +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1901d +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1901d +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x19022 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x19023 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x19023 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x19024 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x19025 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x19025 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x19028 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x19028 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x19029 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1902a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1902a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1902a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1902b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1902b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1902b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1902c +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1902c +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1902d +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x19030 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x19030 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x19031 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x19032 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19040 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x19041 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x19042 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x19043 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19054 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x19055 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x19056 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x19057 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x19058 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x19059 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x1905a +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x1905b +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x1905c +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1905d +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1905e +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x19062 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x19063 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x19064 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x19065 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x190ca +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x190cb +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x190cb +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x10165000 +#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x19400 +#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x19400 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x19401 +#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x19401 +#define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x19402 +#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x19402 +#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x19402 +#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x19402 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x19403 +#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x19403 +#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x19403 +#define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x19403 +#define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x19404 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x19405 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x19406 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x19407 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x19408 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x19409 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1940a +#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1940b +#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1940c +#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1940d +#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1940f +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1940f +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1940f +#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1940f +#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x19419 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x19419 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1941a +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1941b +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1941b +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1941c +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1941d +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1941d +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x19422 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x19423 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x19423 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x19424 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x19425 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x19425 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x19428 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x19428 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x19429 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1942a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1942a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1942a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1942b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1942b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1942b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1942c +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1942c +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1942d +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x19430 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x19430 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x19431 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x19432 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19440 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x19441 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x19442 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x19443 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19454 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x19455 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x19456 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x19457 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x19458 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x19459 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x1945a +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x1945b +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x1945c +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1945d +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1945e +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x19462 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x19463 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x19464 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x19465 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x194ca +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x194cb +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x194cb +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x10166000 +#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x19800 +#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x19800 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x19801 +#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x19801 +#define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x19802 +#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x19802 +#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x19802 +#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x19802 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x19803 +#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x19803 +#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x19803 +#define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x19803 +#define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x19804 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x19805 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x19806 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x19807 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x19808 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x19809 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1980a +#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1980b +#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1980c +#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1980d +#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1980f +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1980f +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1980f +#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1980f +#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x19819 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x19819 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1981a +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1981b +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1981b +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1981c +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1981d +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1981d +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x19822 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x19823 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x19823 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x19824 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x19825 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x19825 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x19828 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x19828 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x19829 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1982a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1982a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1982a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1982b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1982b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1982b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1982c +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1982c +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1982d +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x19830 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x19830 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x19831 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x19832 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19840 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x19841 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x19842 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x19843 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19854 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x19855 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x19856 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x19857 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x19858 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x19859 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x1985a +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x1985b +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x1985c +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1985d +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1985e +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x19862 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x19863 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x19864 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x19865 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x198ca +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x198cb +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x198cb +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x10167000 +#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x19c00 +#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x19c00 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x19c01 +#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x19c01 +#define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x19c02 +#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x19c02 +#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x19c02 +#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x19c02 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x19c03 +#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x19c03 +#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x19c03 +#define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x19c03 +#define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x19c04 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x19c05 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x19c06 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x19c07 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x19c08 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x19c09 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x19c0a +#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x19c0b +#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x19c0c +#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x19c0d +#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x19c0f +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x19c0f +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x19c0f +#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x19c0f +#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x19c19 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x19c19 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x19c1a +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x19c1b +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x19c1b +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x19c1c +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x19c1d +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x19c1d +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x19c22 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x19c23 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x19c23 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x19c24 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x19c25 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x19c25 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x19c28 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x19c28 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x19c29 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x19c2a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x19c2a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x19c2a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x19c2b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x19c2b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x19c2b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x19c2c +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x19c2c +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x19c2d +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x19c30 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x19c30 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x19c31 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x19c32 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19c40 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x19c41 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x19c42 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x19c43 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19c54 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x19c55 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x19c56 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x19c57 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x19c58 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x19c59 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x19c5a +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x19c5b +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x19c5c +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x19c5d +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x19c5e +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x19c62 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x19c63 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x19c64 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x19c65 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x19cca +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x19ccb +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x19ccb +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +// base address: 0x10168000 +#define regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID 0x1a000 +#define regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID 0x1a000 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_COMMAND 0x1a001 +#define regBIF_CFG_DEV0_EPF0_VF8_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_STATUS 0x1a001 +#define regBIF_CFG_DEV0_EPF0_VF8_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID 0x1a002 +#define regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE 0x1a002 +#define regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS 0x1a002 +#define regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS 0x1a002 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE 0x1a003 +#define regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_LATENCY 0x1a003 +#define regBIF_CFG_DEV0_EPF0_VF8_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_HEADER 0x1a003 +#define regBIF_CFG_DEV0_EPF0_VF8_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BIST 0x1a003 +#define regBIF_CFG_DEV0_EPF0_VF8_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1 0x1a004 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2 0x1a005 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3 0x1a006 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4 0x1a007 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5 0x1a008 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6 0x1a009 +#define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR 0x1a00a +#define regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID 0x1a00b +#define regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR 0x1a00c +#define regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR 0x1a00d +#define regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE 0x1a00f +#define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN 0x1a00f +#define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT 0x1a00f +#define regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY 0x1a00f +#define regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST 0x1a019 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP 0x1a019 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP 0x1a01a +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL 0x1a01b +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS 0x1a01b +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP 0x1a01c +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL 0x1a01d +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS 0x1a01d +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2 0x1a022 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2 0x1a023 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2 0x1a023 +#define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2 0x1a024 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2 0x1a025 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2 0x1a025 +#define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST 0x1a028 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL 0x1a028 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO 0x1a029 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI 0x1a02a +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA 0x1a02a +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA 0x1a02a +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK 0x1a02b +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64 0x1a02b +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64 0x1a02b +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64 0x1a02c +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING 0x1a02c +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64 0x1a02d +#define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST 0x1a030 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL 0x1a030 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE 0x1a031 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA 0x1a032 +#define regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a040 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR 0x1a041 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1 0x1a042 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2 0x1a043 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a054 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS 0x1a055 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK 0x1a056 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY 0x1a057 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS 0x1a058 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK 0x1a059 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL 0x1a05a +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0 0x1a05b +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1 0x1a05c +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2 0x1a05d +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3 0x1a05e +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0 0x1a062 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1 0x1a063 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2 0x1a064 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3 0x1a065 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST 0x1a0ca +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP 0x1a0cb +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL 0x1a0cb +#define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +// base address: 0x10169000 +#define regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID 0x1a400 +#define regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID 0x1a400 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_COMMAND 0x1a401 +#define regBIF_CFG_DEV0_EPF0_VF9_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_STATUS 0x1a401 +#define regBIF_CFG_DEV0_EPF0_VF9_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID 0x1a402 +#define regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE 0x1a402 +#define regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS 0x1a402 +#define regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS 0x1a402 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE 0x1a403 +#define regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_LATENCY 0x1a403 +#define regBIF_CFG_DEV0_EPF0_VF9_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_HEADER 0x1a403 +#define regBIF_CFG_DEV0_EPF0_VF9_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BIST 0x1a403 +#define regBIF_CFG_DEV0_EPF0_VF9_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1 0x1a404 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2 0x1a405 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3 0x1a406 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4 0x1a407 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5 0x1a408 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6 0x1a409 +#define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR 0x1a40a +#define regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID 0x1a40b +#define regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR 0x1a40c +#define regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR 0x1a40d +#define regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE 0x1a40f +#define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN 0x1a40f +#define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT 0x1a40f +#define regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY 0x1a40f +#define regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST 0x1a419 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP 0x1a419 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP 0x1a41a +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL 0x1a41b +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS 0x1a41b +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP 0x1a41c +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL 0x1a41d +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS 0x1a41d +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2 0x1a422 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2 0x1a423 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2 0x1a423 +#define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2 0x1a424 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2 0x1a425 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2 0x1a425 +#define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST 0x1a428 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL 0x1a428 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO 0x1a429 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI 0x1a42a +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA 0x1a42a +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA 0x1a42a +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK 0x1a42b +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64 0x1a42b +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64 0x1a42b +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64 0x1a42c +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING 0x1a42c +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64 0x1a42d +#define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST 0x1a430 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL 0x1a430 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE 0x1a431 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA 0x1a432 +#define regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a440 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR 0x1a441 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1 0x1a442 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2 0x1a443 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a454 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS 0x1a455 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK 0x1a456 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY 0x1a457 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS 0x1a458 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK 0x1a459 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL 0x1a45a +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0 0x1a45b +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1 0x1a45c +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2 0x1a45d +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3 0x1a45e +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0 0x1a462 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1 0x1a463 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2 0x1a464 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3 0x1a465 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST 0x1a4ca +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP 0x1a4cb +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL 0x1a4cb +#define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +// base address: 0x1016a000 +#define regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID 0x1a800 +#define regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID 0x1a800 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_COMMAND 0x1a801 +#define regBIF_CFG_DEV0_EPF0_VF10_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_STATUS 0x1a801 +#define regBIF_CFG_DEV0_EPF0_VF10_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID 0x1a802 +#define regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE 0x1a802 +#define regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS 0x1a802 +#define regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS 0x1a802 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE 0x1a803 +#define regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_LATENCY 0x1a803 +#define regBIF_CFG_DEV0_EPF0_VF10_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_HEADER 0x1a803 +#define regBIF_CFG_DEV0_EPF0_VF10_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BIST 0x1a803 +#define regBIF_CFG_DEV0_EPF0_VF10_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1 0x1a804 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2 0x1a805 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3 0x1a806 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4 0x1a807 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5 0x1a808 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6 0x1a809 +#define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR 0x1a80a +#define regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID 0x1a80b +#define regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR 0x1a80c +#define regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR 0x1a80d +#define regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE 0x1a80f +#define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN 0x1a80f +#define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT 0x1a80f +#define regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY 0x1a80f +#define regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST 0x1a819 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP 0x1a819 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP 0x1a81a +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL 0x1a81b +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS 0x1a81b +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP 0x1a81c +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL 0x1a81d +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS 0x1a81d +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2 0x1a822 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2 0x1a823 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2 0x1a823 +#define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2 0x1a824 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2 0x1a825 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2 0x1a825 +#define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST 0x1a828 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL 0x1a828 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO 0x1a829 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI 0x1a82a +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA 0x1a82a +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA 0x1a82a +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK 0x1a82b +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64 0x1a82b +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64 0x1a82b +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64 0x1a82c +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING 0x1a82c +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64 0x1a82d +#define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST 0x1a830 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL 0x1a830 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE 0x1a831 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA 0x1a832 +#define regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a840 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR 0x1a841 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1 0x1a842 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2 0x1a843 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a854 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS 0x1a855 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK 0x1a856 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY 0x1a857 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS 0x1a858 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK 0x1a859 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL 0x1a85a +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0 0x1a85b +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1 0x1a85c +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2 0x1a85d +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3 0x1a85e +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0 0x1a862 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1 0x1a863 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2 0x1a864 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3 0x1a865 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST 0x1a8ca +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP 0x1a8cb +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL 0x1a8cb +#define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +// base address: 0x1016b000 +#define regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID 0x1ac00 +#define regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID 0x1ac00 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_COMMAND 0x1ac01 +#define regBIF_CFG_DEV0_EPF0_VF11_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_STATUS 0x1ac01 +#define regBIF_CFG_DEV0_EPF0_VF11_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID 0x1ac02 +#define regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE 0x1ac02 +#define regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS 0x1ac02 +#define regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS 0x1ac02 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE 0x1ac03 +#define regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_LATENCY 0x1ac03 +#define regBIF_CFG_DEV0_EPF0_VF11_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_HEADER 0x1ac03 +#define regBIF_CFG_DEV0_EPF0_VF11_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BIST 0x1ac03 +#define regBIF_CFG_DEV0_EPF0_VF11_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1 0x1ac04 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2 0x1ac05 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3 0x1ac06 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4 0x1ac07 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5 0x1ac08 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6 0x1ac09 +#define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR 0x1ac0a +#define regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID 0x1ac0b +#define regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR 0x1ac0c +#define regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR 0x1ac0d +#define regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE 0x1ac0f +#define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN 0x1ac0f +#define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT 0x1ac0f +#define regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY 0x1ac0f +#define regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST 0x1ac19 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP 0x1ac19 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP 0x1ac1a +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL 0x1ac1b +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS 0x1ac1b +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP 0x1ac1c +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL 0x1ac1d +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS 0x1ac1d +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2 0x1ac22 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2 0x1ac23 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2 0x1ac23 +#define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2 0x1ac24 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2 0x1ac25 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2 0x1ac25 +#define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST 0x1ac28 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL 0x1ac28 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO 0x1ac29 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI 0x1ac2a +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA 0x1ac2a +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA 0x1ac2a +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK 0x1ac2b +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64 0x1ac2b +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64 0x1ac2b +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64 0x1ac2c +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING 0x1ac2c +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64 0x1ac2d +#define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST 0x1ac30 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL 0x1ac30 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE 0x1ac31 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA 0x1ac32 +#define regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1ac40 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR 0x1ac41 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1 0x1ac42 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2 0x1ac43 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1ac54 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS 0x1ac55 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK 0x1ac56 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY 0x1ac57 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS 0x1ac58 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK 0x1ac59 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL 0x1ac5a +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0 0x1ac5b +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1 0x1ac5c +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2 0x1ac5d +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3 0x1ac5e +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0 0x1ac62 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1 0x1ac63 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2 0x1ac64 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3 0x1ac65 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST 0x1acca +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP 0x1accb +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL 0x1accb +#define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +// base address: 0x1016c000 +#define regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID 0x1b000 +#define regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID 0x1b000 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_COMMAND 0x1b001 +#define regBIF_CFG_DEV0_EPF0_VF12_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_STATUS 0x1b001 +#define regBIF_CFG_DEV0_EPF0_VF12_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID 0x1b002 +#define regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE 0x1b002 +#define regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS 0x1b002 +#define regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS 0x1b002 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE 0x1b003 +#define regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_LATENCY 0x1b003 +#define regBIF_CFG_DEV0_EPF0_VF12_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_HEADER 0x1b003 +#define regBIF_CFG_DEV0_EPF0_VF12_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BIST 0x1b003 +#define regBIF_CFG_DEV0_EPF0_VF12_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1 0x1b004 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2 0x1b005 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3 0x1b006 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4 0x1b007 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5 0x1b008 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6 0x1b009 +#define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR 0x1b00a +#define regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID 0x1b00b +#define regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR 0x1b00c +#define regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR 0x1b00d +#define regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE 0x1b00f +#define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN 0x1b00f +#define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT 0x1b00f +#define regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY 0x1b00f +#define regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST 0x1b019 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP 0x1b019 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP 0x1b01a +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL 0x1b01b +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS 0x1b01b +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP 0x1b01c +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL 0x1b01d +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS 0x1b01d +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2 0x1b022 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2 0x1b023 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2 0x1b023 +#define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2 0x1b024 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2 0x1b025 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2 0x1b025 +#define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST 0x1b028 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL 0x1b028 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO 0x1b029 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI 0x1b02a +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA 0x1b02a +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA 0x1b02a +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK 0x1b02b +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64 0x1b02b +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64 0x1b02b +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64 0x1b02c +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING 0x1b02c +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64 0x1b02d +#define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST 0x1b030 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL 0x1b030 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE 0x1b031 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA 0x1b032 +#define regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b040 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR 0x1b041 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1 0x1b042 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2 0x1b043 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b054 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS 0x1b055 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK 0x1b056 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY 0x1b057 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS 0x1b058 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK 0x1b059 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL 0x1b05a +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0 0x1b05b +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1 0x1b05c +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2 0x1b05d +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3 0x1b05e +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0 0x1b062 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1 0x1b063 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2 0x1b064 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3 0x1b065 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST 0x1b0ca +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP 0x1b0cb +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL 0x1b0cb +#define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +// base address: 0x1016d000 +#define regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID 0x1b400 +#define regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID 0x1b400 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_COMMAND 0x1b401 +#define regBIF_CFG_DEV0_EPF0_VF13_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_STATUS 0x1b401 +#define regBIF_CFG_DEV0_EPF0_VF13_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID 0x1b402 +#define regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE 0x1b402 +#define regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS 0x1b402 +#define regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS 0x1b402 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE 0x1b403 +#define regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_LATENCY 0x1b403 +#define regBIF_CFG_DEV0_EPF0_VF13_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_HEADER 0x1b403 +#define regBIF_CFG_DEV0_EPF0_VF13_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BIST 0x1b403 +#define regBIF_CFG_DEV0_EPF0_VF13_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1 0x1b404 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2 0x1b405 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3 0x1b406 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4 0x1b407 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5 0x1b408 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6 0x1b409 +#define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR 0x1b40a +#define regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID 0x1b40b +#define regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR 0x1b40c +#define regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR 0x1b40d +#define regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE 0x1b40f +#define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN 0x1b40f +#define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT 0x1b40f +#define regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY 0x1b40f +#define regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST 0x1b419 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP 0x1b419 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP 0x1b41a +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL 0x1b41b +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS 0x1b41b +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP 0x1b41c +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL 0x1b41d +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS 0x1b41d +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2 0x1b422 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2 0x1b423 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2 0x1b423 +#define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2 0x1b424 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2 0x1b425 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2 0x1b425 +#define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST 0x1b428 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL 0x1b428 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO 0x1b429 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI 0x1b42a +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA 0x1b42a +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA 0x1b42a +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK 0x1b42b +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64 0x1b42b +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64 0x1b42b +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64 0x1b42c +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING 0x1b42c +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64 0x1b42d +#define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST 0x1b430 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL 0x1b430 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE 0x1b431 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA 0x1b432 +#define regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b440 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR 0x1b441 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1 0x1b442 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2 0x1b443 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b454 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS 0x1b455 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK 0x1b456 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY 0x1b457 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS 0x1b458 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK 0x1b459 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL 0x1b45a +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0 0x1b45b +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1 0x1b45c +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2 0x1b45d +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3 0x1b45e +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0 0x1b462 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1 0x1b463 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2 0x1b464 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3 0x1b465 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST 0x1b4ca +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP 0x1b4cb +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL 0x1b4cb +#define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +// base address: 0x1016e000 +#define regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID 0x1b800 +#define regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID 0x1b800 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_COMMAND 0x1b801 +#define regBIF_CFG_DEV0_EPF0_VF14_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_STATUS 0x1b801 +#define regBIF_CFG_DEV0_EPF0_VF14_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID 0x1b802 +#define regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE 0x1b802 +#define regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS 0x1b802 +#define regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS 0x1b802 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE 0x1b803 +#define regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_LATENCY 0x1b803 +#define regBIF_CFG_DEV0_EPF0_VF14_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_HEADER 0x1b803 +#define regBIF_CFG_DEV0_EPF0_VF14_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BIST 0x1b803 +#define regBIF_CFG_DEV0_EPF0_VF14_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1 0x1b804 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2 0x1b805 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3 0x1b806 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4 0x1b807 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5 0x1b808 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6 0x1b809 +#define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR 0x1b80a +#define regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID 0x1b80b +#define regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR 0x1b80c +#define regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR 0x1b80d +#define regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE 0x1b80f +#define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN 0x1b80f +#define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT 0x1b80f +#define regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY 0x1b80f +#define regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST 0x1b819 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP 0x1b819 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP 0x1b81a +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL 0x1b81b +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS 0x1b81b +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP 0x1b81c +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL 0x1b81d +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS 0x1b81d +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2 0x1b822 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2 0x1b823 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2 0x1b823 +#define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2 0x1b824 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2 0x1b825 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2 0x1b825 +#define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST 0x1b828 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL 0x1b828 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO 0x1b829 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI 0x1b82a +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA 0x1b82a +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA 0x1b82a +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK 0x1b82b +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64 0x1b82b +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64 0x1b82b +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64 0x1b82c +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING 0x1b82c +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64 0x1b82d +#define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST 0x1b830 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL 0x1b830 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE 0x1b831 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA 0x1b832 +#define regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b840 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR 0x1b841 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1 0x1b842 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2 0x1b843 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b854 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS 0x1b855 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK 0x1b856 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY 0x1b857 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS 0x1b858 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK 0x1b859 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL 0x1b85a +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0 0x1b85b +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1 0x1b85c +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2 0x1b85d +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3 0x1b85e +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0 0x1b862 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1 0x1b863 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2 0x1b864 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3 0x1b865 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST 0x1b8ca +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP 0x1b8cb +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL 0x1b8cb +#define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +// base address: 0x1016f000 +#define regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID 0x1bc00 +#define regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID 0x1bc00 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_COMMAND 0x1bc01 +#define regBIF_CFG_DEV0_EPF0_VF15_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_STATUS 0x1bc01 +#define regBIF_CFG_DEV0_EPF0_VF15_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID 0x1bc02 +#define regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE 0x1bc02 +#define regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS 0x1bc02 +#define regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS 0x1bc02 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE 0x1bc03 +#define regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_LATENCY 0x1bc03 +#define regBIF_CFG_DEV0_EPF0_VF15_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_HEADER 0x1bc03 +#define regBIF_CFG_DEV0_EPF0_VF15_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BIST 0x1bc03 +#define regBIF_CFG_DEV0_EPF0_VF15_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1 0x1bc04 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2 0x1bc05 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3 0x1bc06 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4 0x1bc07 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5 0x1bc08 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6 0x1bc09 +#define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR 0x1bc0a +#define regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID 0x1bc0b +#define regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR 0x1bc0c +#define regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR 0x1bc0d +#define regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE 0x1bc0f +#define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN 0x1bc0f +#define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT 0x1bc0f +#define regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY 0x1bc0f +#define regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST 0x1bc19 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP 0x1bc19 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP 0x1bc1a +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL 0x1bc1b +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS 0x1bc1b +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP 0x1bc1c +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL 0x1bc1d +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS 0x1bc1d +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2 0x1bc22 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2 0x1bc23 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2 0x1bc23 +#define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2 0x1bc24 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2 0x1bc25 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2 0x1bc25 +#define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST 0x1bc28 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL 0x1bc28 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO 0x1bc29 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI 0x1bc2a +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA 0x1bc2a +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA 0x1bc2a +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK 0x1bc2b +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64 0x1bc2b +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64 0x1bc2b +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64 0x1bc2c +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING 0x1bc2c +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64 0x1bc2d +#define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST 0x1bc30 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL 0x1bc30 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE 0x1bc31 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA 0x1bc32 +#define regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1bc40 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR 0x1bc41 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1 0x1bc42 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2 0x1bc43 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1bc54 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS 0x1bc55 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK 0x1bc56 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY 0x1bc57 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS 0x1bc58 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK 0x1bc59 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL 0x1bc5a +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0 0x1bc5b +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1 0x1bc5c +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2 0x1bc5d +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3 0x1bc5e +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0 0x1bc62 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1 0x1bc63 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2 0x1bc64 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3 0x1bc65 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST 0x1bcca +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP 0x1bccb +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL 0x1bccb +#define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412 +#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415 +#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10450 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x10451 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x10452 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10455 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10456 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10457 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10458 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10459 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x1045a +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x1045b +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x1045c +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1045d +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1045e +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x10462 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10463 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10464 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10465 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x10480 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x10481 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x10482 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x10483 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x10484 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x10485 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x10486 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x10487 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x10488 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x10489 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x1048a +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x1048b +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x1048c +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x10492 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x10493 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x10494 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x10495 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x10496 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x10497 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x10497 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x1049c +#define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x1049d +#define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x1049e +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x1049f +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x1049f +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x104a0 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x104a0 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x104a1 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x104a1 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x104a2 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x104a2 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x104a3 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x104a3 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x104a4 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x104a4 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x104a5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x104a5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x104a6 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x104a6 +#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x104a8 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x104a9 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x104a9 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x104b4 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x104b5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x104b5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST 0x104bc +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP 0x104bd +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL 0x104bd +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 0x104be +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 0x104bf +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 0x104c0 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 0x104c1 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 0x104c2 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 0x104c3 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x104c4 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x104c5 +#define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x104c8 +#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x104c9 +#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x104ca +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x104cb +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x104cb +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x104cc +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x104cd +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x104ce +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x104ce +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x104cf +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x104cf +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x104d0 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x104d0 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x104d1 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x104d1 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x104d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x104d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x104d4 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x104d5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x104d6 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x104d7 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x104d8 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x104d9 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x104da +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x104db +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10530 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10531 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x10532 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x10533 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x10534 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x10535 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x10536 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x10537 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10538 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10539 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x1053a +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x1053b +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x1053c +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +// base address: 0x10142000 +#define regBIF_CFG_DEV0_EPF2_VENDOR_ID 0x10800 +#define regBIF_CFG_DEV0_EPF2_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DEVICE_ID 0x10800 +#define regBIF_CFG_DEV0_EPF2_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_COMMAND 0x10801 +#define regBIF_CFG_DEV0_EPF2_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_STATUS 0x10801 +#define regBIF_CFG_DEV0_EPF2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_REVISION_ID 0x10802 +#define regBIF_CFG_DEV0_EPF2_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE 0x10802 +#define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_SUB_CLASS 0x10802 +#define regBIF_CFG_DEV0_EPF2_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BASE_CLASS 0x10802 +#define regBIF_CFG_DEV0_EPF2_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_CACHE_LINE 0x10803 +#define regBIF_CFG_DEV0_EPF2_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_LATENCY 0x10803 +#define regBIF_CFG_DEV0_EPF2_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_HEADER 0x10803 +#define regBIF_CFG_DEV0_EPF2_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BIST 0x10803 +#define regBIF_CFG_DEV0_EPF2_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1 0x10804 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2 0x10805 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3 0x10806 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4 0x10807 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5 0x10808 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6 0x10809 +#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR 0x1080a +#define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID 0x1080b +#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR 0x1080c +#define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_CAP_PTR 0x1080d +#define regBIF_CFG_DEV0_EPF2_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE 0x1080f +#define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN 0x1080f +#define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MIN_GRANT 0x1080f +#define regBIF_CFG_DEV0_EPF2_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MAX_LATENCY 0x1080f +#define regBIF_CFG_DEV0_EPF2_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST 0x10812 +#define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W 0x10813 +#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST 0x10814 +#define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PMI_CAP 0x10814 +#define regBIF_CFG_DEV0_EPF2_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL 0x10815 +#define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_SBRN 0x10818 +#define regBIF_CFG_DEV0_EPF2_SBRN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_FLADJ 0x10818 +#define regBIF_CFG_DEV0_EPF2_FLADJ_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD 0x10818 +#define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST 0x10819 +#define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_CAP 0x10819 +#define regBIF_CFG_DEV0_EPF2_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP 0x1081a +#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL 0x1081b +#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS 0x1081b +#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_LINK_CAP 0x1081c +#define regBIF_CFG_DEV0_EPF2_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_LINK_CNTL 0x1081d +#define regBIF_CFG_DEV0_EPF2_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_LINK_STATUS 0x1081d +#define regBIF_CFG_DEV0_EPF2_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2 0x10822 +#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 0x10823 +#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 0x10823 +#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_LINK_CAP2 0x10824 +#define regBIF_CFG_DEV0_EPF2_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_LINK_CNTL2 0x10825 +#define regBIF_CFG_DEV0_EPF2_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_LINK_STATUS2 0x10825 +#define regBIF_CFG_DEV0_EPF2_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST 0x10828 +#define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL 0x10828 +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO 0x10829 +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI 0x1082a +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA 0x1082a +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA 0x1082a +#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_MASK 0x1082b +#define regBIF_CFG_DEV0_EPF2_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 0x1082b +#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 0x1082b +#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_MASK_64 0x1082c +#define regBIF_CFG_DEV0_EPF2_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_PENDING 0x1082c +#define regBIF_CFG_DEV0_EPF2_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64 0x1082d +#define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST 0x10830 +#define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL 0x10830 +#define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSIX_TABLE 0x10831 +#define regBIF_CFG_DEV0_EPF2_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_MSIX_PBA 0x10832 +#define regBIF_CFG_DEV0_EPF2_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10840 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR 0x10841 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 0x10842 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 0x10843 +#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10854 +#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS 0x10855 +#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK 0x10856 +#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY 0x10857 +#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS 0x10858 +#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK 0x10859 +#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL 0x1085a +#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 0x1085b +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 0x1085c +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 0x1085d +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 0x1085e +#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 0x10862 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 0x10863 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 0x10864 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 0x10865 +#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST 0x10880 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP 0x10881 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL 0x10882 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP 0x10883 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL 0x10884 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP 0x10885 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL 0x10886 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP 0x10887 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL 0x10888 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP 0x10889 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL 0x1088a +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP 0x1088b +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL 0x1088c +#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10890 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT 0x10891 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA 0x10892 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP 0x10893 +#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST 0x10894 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP 0x10895 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR 0x10896 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS 0x10897 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL 0x10897 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10898 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10898 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10898 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10898 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10899 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10899 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10899 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10899 +#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST 0x108a8 +#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP 0x108a9 +#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL 0x108a9 +#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST 0x108b4 +#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP 0x108b5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL 0x108b5 +#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST 0x108ca +#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP 0x108cb +#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL 0x108cb +#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +// base address: 0x10143000 +#define regBIF_CFG_DEV0_EPF3_VENDOR_ID 0x10c00 +#define regBIF_CFG_DEV0_EPF3_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DEVICE_ID 0x10c00 +#define regBIF_CFG_DEV0_EPF3_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_COMMAND 0x10c01 +#define regBIF_CFG_DEV0_EPF3_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_STATUS 0x10c01 +#define regBIF_CFG_DEV0_EPF3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_REVISION_ID 0x10c02 +#define regBIF_CFG_DEV0_EPF3_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE 0x10c02 +#define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_SUB_CLASS 0x10c02 +#define regBIF_CFG_DEV0_EPF3_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BASE_CLASS 0x10c02 +#define regBIF_CFG_DEV0_EPF3_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_CACHE_LINE 0x10c03 +#define regBIF_CFG_DEV0_EPF3_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_LATENCY 0x10c03 +#define regBIF_CFG_DEV0_EPF3_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_HEADER 0x10c03 +#define regBIF_CFG_DEV0_EPF3_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BIST 0x10c03 +#define regBIF_CFG_DEV0_EPF3_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1 0x10c04 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2 0x10c05 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3 0x10c06 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4 0x10c07 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5 0x10c08 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6 0x10c09 +#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR 0x10c0a +#define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID 0x10c0b +#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR 0x10c0c +#define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_CAP_PTR 0x10c0d +#define regBIF_CFG_DEV0_EPF3_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE 0x10c0f +#define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN 0x10c0f +#define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MIN_GRANT 0x10c0f +#define regBIF_CFG_DEV0_EPF3_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MAX_LATENCY 0x10c0f +#define regBIF_CFG_DEV0_EPF3_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST 0x10c12 +#define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W 0x10c13 +#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST 0x10c14 +#define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PMI_CAP 0x10c14 +#define regBIF_CFG_DEV0_EPF3_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL 0x10c15 +#define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_SBRN 0x10c18 +#define regBIF_CFG_DEV0_EPF3_SBRN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_FLADJ 0x10c18 +#define regBIF_CFG_DEV0_EPF3_FLADJ_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD 0x10c18 +#define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST 0x10c19 +#define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_CAP 0x10c19 +#define regBIF_CFG_DEV0_EPF3_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP 0x10c1a +#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL 0x10c1b +#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS 0x10c1b +#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_LINK_CAP 0x10c1c +#define regBIF_CFG_DEV0_EPF3_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_LINK_CNTL 0x10c1d +#define regBIF_CFG_DEV0_EPF3_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_LINK_STATUS 0x10c1d +#define regBIF_CFG_DEV0_EPF3_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2 0x10c22 +#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 0x10c23 +#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 0x10c23 +#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_LINK_CAP2 0x10c24 +#define regBIF_CFG_DEV0_EPF3_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_LINK_CNTL2 0x10c25 +#define regBIF_CFG_DEV0_EPF3_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_LINK_STATUS2 0x10c25 +#define regBIF_CFG_DEV0_EPF3_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST 0x10c28 +#define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL 0x10c28 +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO 0x10c29 +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI 0x10c2a +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA 0x10c2a +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA 0x10c2a +#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_MASK 0x10c2b +#define regBIF_CFG_DEV0_EPF3_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 0x10c2b +#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 0x10c2b +#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_MASK_64 0x10c2c +#define regBIF_CFG_DEV0_EPF3_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_PENDING 0x10c2c +#define regBIF_CFG_DEV0_EPF3_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64 0x10c2d +#define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST 0x10c30 +#define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL 0x10c30 +#define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSIX_TABLE 0x10c31 +#define regBIF_CFG_DEV0_EPF3_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_MSIX_PBA 0x10c32 +#define regBIF_CFG_DEV0_EPF3_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10c40 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR 0x10c41 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 0x10c42 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 0x10c43 +#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10c54 +#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS 0x10c55 +#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK 0x10c56 +#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY 0x10c57 +#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS 0x10c58 +#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK 0x10c59 +#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL 0x10c5a +#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 0x10c5b +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 0x10c5c +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 0x10c5d +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 0x10c5e +#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 0x10c62 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 0x10c63 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 0x10c64 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 0x10c65 +#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST 0x10c80 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP 0x10c81 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL 0x10c82 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP 0x10c83 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL 0x10c84 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP 0x10c85 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL 0x10c86 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP 0x10c87 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL 0x10c88 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP 0x10c89 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL 0x10c8a +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP 0x10c8b +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL 0x10c8c +#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10c90 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT 0x10c91 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA 0x10c92 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP 0x10c93 +#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST 0x10c94 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP 0x10c95 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR 0x10c96 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS 0x10c97 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL 0x10c97 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10c98 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10c98 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10c98 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10c98 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10c99 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10c99 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10c99 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10c99 +#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST 0x10ca8 +#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP 0x10ca9 +#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL 0x10ca9 +#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST 0x10cb4 +#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP 0x10cb5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL 0x10cb5 +#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST 0x10cca +#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP 0x10ccb +#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL 0x10ccb +#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 +#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 + + +// base address: 0x10170000 +#define regPCIEMSIX_VECT0_ADDR_LO 0x1c000 +#define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT0_ADDR_HI 0x1c001 +#define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT0_MSG_DATA 0x1c002 +#define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT0_CONTROL 0x1c003 +#define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT1_ADDR_LO 0x1c004 +#define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT1_ADDR_HI 0x1c005 +#define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT1_MSG_DATA 0x1c006 +#define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT1_CONTROL 0x1c007 +#define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT2_ADDR_LO 0x1c008 +#define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT2_ADDR_HI 0x1c009 +#define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT2_MSG_DATA 0x1c00a +#define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT2_CONTROL 0x1c00b +#define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT3_ADDR_LO 0x1c00c +#define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT3_ADDR_HI 0x1c00d +#define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT3_MSG_DATA 0x1c00e +#define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT3_CONTROL 0x1c00f +#define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT4_ADDR_LO 0x1c010 +#define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT4_ADDR_HI 0x1c011 +#define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT4_MSG_DATA 0x1c012 +#define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT4_CONTROL 0x1c013 +#define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT5_ADDR_LO 0x1c014 +#define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT5_ADDR_HI 0x1c015 +#define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT5_MSG_DATA 0x1c016 +#define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT5_CONTROL 0x1c017 +#define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT6_ADDR_LO 0x1c018 +#define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT6_ADDR_HI 0x1c019 +#define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT6_MSG_DATA 0x1c01a +#define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT6_CONTROL 0x1c01b +#define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT7_ADDR_LO 0x1c01c +#define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT7_ADDR_HI 0x1c01d +#define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT7_MSG_DATA 0x1c01e +#define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT7_CONTROL 0x1c01f +#define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT8_ADDR_LO 0x1c020 +#define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT8_ADDR_HI 0x1c021 +#define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT8_MSG_DATA 0x1c022 +#define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT8_CONTROL 0x1c023 +#define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT9_ADDR_LO 0x1c024 +#define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT9_ADDR_HI 0x1c025 +#define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT9_MSG_DATA 0x1c026 +#define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT9_CONTROL 0x1c027 +#define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT10_ADDR_LO 0x1c028 +#define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT10_ADDR_HI 0x1c029 +#define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT10_MSG_DATA 0x1c02a +#define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT10_CONTROL 0x1c02b +#define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT11_ADDR_LO 0x1c02c +#define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT11_ADDR_HI 0x1c02d +#define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT11_MSG_DATA 0x1c02e +#define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT11_CONTROL 0x1c02f +#define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT12_ADDR_LO 0x1c030 +#define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT12_ADDR_HI 0x1c031 +#define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT12_MSG_DATA 0x1c032 +#define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT12_CONTROL 0x1c033 +#define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT13_ADDR_LO 0x1c034 +#define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT13_ADDR_HI 0x1c035 +#define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT13_MSG_DATA 0x1c036 +#define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT13_CONTROL 0x1c037 +#define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT14_ADDR_LO 0x1c038 +#define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT14_ADDR_HI 0x1c039 +#define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT14_MSG_DATA 0x1c03a +#define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT14_CONTROL 0x1c03b +#define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT15_ADDR_LO 0x1c03c +#define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT15_ADDR_HI 0x1c03d +#define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT15_MSG_DATA 0x1c03e +#define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT15_CONTROL 0x1c03f +#define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT16_ADDR_LO 0x1c040 +#define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT16_ADDR_HI 0x1c041 +#define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT16_MSG_DATA 0x1c042 +#define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT16_CONTROL 0x1c043 +#define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT17_ADDR_LO 0x1c044 +#define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT17_ADDR_HI 0x1c045 +#define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT17_MSG_DATA 0x1c046 +#define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT17_CONTROL 0x1c047 +#define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT18_ADDR_LO 0x1c048 +#define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT18_ADDR_HI 0x1c049 +#define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT18_MSG_DATA 0x1c04a +#define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT18_CONTROL 0x1c04b +#define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT19_ADDR_LO 0x1c04c +#define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT19_ADDR_HI 0x1c04d +#define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT19_MSG_DATA 0x1c04e +#define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT19_CONTROL 0x1c04f +#define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT20_ADDR_LO 0x1c050 +#define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT20_ADDR_HI 0x1c051 +#define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT20_MSG_DATA 0x1c052 +#define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT20_CONTROL 0x1c053 +#define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT21_ADDR_LO 0x1c054 +#define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT21_ADDR_HI 0x1c055 +#define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT21_MSG_DATA 0x1c056 +#define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT21_CONTROL 0x1c057 +#define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT22_ADDR_LO 0x1c058 +#define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT22_ADDR_HI 0x1c059 +#define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT22_MSG_DATA 0x1c05a +#define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT22_CONTROL 0x1c05b +#define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT23_ADDR_LO 0x1c05c +#define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT23_ADDR_HI 0x1c05d +#define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT23_MSG_DATA 0x1c05e +#define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT23_CONTROL 0x1c05f +#define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT24_ADDR_LO 0x1c060 +#define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT24_ADDR_HI 0x1c061 +#define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT24_MSG_DATA 0x1c062 +#define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT24_CONTROL 0x1c063 +#define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT25_ADDR_LO 0x1c064 +#define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT25_ADDR_HI 0x1c065 +#define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT25_MSG_DATA 0x1c066 +#define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT25_CONTROL 0x1c067 +#define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT26_ADDR_LO 0x1c068 +#define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT26_ADDR_HI 0x1c069 +#define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT26_MSG_DATA 0x1c06a +#define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT26_CONTROL 0x1c06b +#define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT27_ADDR_LO 0x1c06c +#define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT27_ADDR_HI 0x1c06d +#define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT27_MSG_DATA 0x1c06e +#define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT27_CONTROL 0x1c06f +#define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT28_ADDR_LO 0x1c070 +#define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT28_ADDR_HI 0x1c071 +#define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT28_MSG_DATA 0x1c072 +#define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT28_CONTROL 0x1c073 +#define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT29_ADDR_LO 0x1c074 +#define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT29_ADDR_HI 0x1c075 +#define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT29_MSG_DATA 0x1c076 +#define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT29_CONTROL 0x1c077 +#define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT30_ADDR_LO 0x1c078 +#define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT30_ADDR_HI 0x1c079 +#define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT30_MSG_DATA 0x1c07a +#define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT30_CONTROL 0x1c07b +#define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT31_ADDR_LO 0x1c07c +#define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT31_ADDR_HI 0x1c07d +#define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT31_MSG_DATA 0x1c07e +#define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT31_CONTROL 0x1c07f +#define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT32_ADDR_LO 0x1c080 +#define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT32_ADDR_HI 0x1c081 +#define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT32_MSG_DATA 0x1c082 +#define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT32_CONTROL 0x1c083 +#define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT33_ADDR_LO 0x1c084 +#define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT33_ADDR_HI 0x1c085 +#define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT33_MSG_DATA 0x1c086 +#define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT33_CONTROL 0x1c087 +#define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT34_ADDR_LO 0x1c088 +#define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT34_ADDR_HI 0x1c089 +#define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT34_MSG_DATA 0x1c08a +#define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT34_CONTROL 0x1c08b +#define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT35_ADDR_LO 0x1c08c +#define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT35_ADDR_HI 0x1c08d +#define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT35_MSG_DATA 0x1c08e +#define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT35_CONTROL 0x1c08f +#define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT36_ADDR_LO 0x1c090 +#define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT36_ADDR_HI 0x1c091 +#define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT36_MSG_DATA 0x1c092 +#define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT36_CONTROL 0x1c093 +#define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT37_ADDR_LO 0x1c094 +#define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT37_ADDR_HI 0x1c095 +#define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT37_MSG_DATA 0x1c096 +#define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT37_CONTROL 0x1c097 +#define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT38_ADDR_LO 0x1c098 +#define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT38_ADDR_HI 0x1c099 +#define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT38_MSG_DATA 0x1c09a +#define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT38_CONTROL 0x1c09b +#define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT39_ADDR_LO 0x1c09c +#define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT39_ADDR_HI 0x1c09d +#define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT39_MSG_DATA 0x1c09e +#define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT39_CONTROL 0x1c09f +#define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT40_ADDR_LO 0x1c0a0 +#define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT40_ADDR_HI 0x1c0a1 +#define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT40_MSG_DATA 0x1c0a2 +#define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT40_CONTROL 0x1c0a3 +#define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT41_ADDR_LO 0x1c0a4 +#define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT41_ADDR_HI 0x1c0a5 +#define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT41_MSG_DATA 0x1c0a6 +#define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT41_CONTROL 0x1c0a7 +#define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT42_ADDR_LO 0x1c0a8 +#define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT42_ADDR_HI 0x1c0a9 +#define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT42_MSG_DATA 0x1c0aa +#define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT42_CONTROL 0x1c0ab +#define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT43_ADDR_LO 0x1c0ac +#define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT43_ADDR_HI 0x1c0ad +#define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT43_MSG_DATA 0x1c0ae +#define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT43_CONTROL 0x1c0af +#define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT44_ADDR_LO 0x1c0b0 +#define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT44_ADDR_HI 0x1c0b1 +#define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT44_MSG_DATA 0x1c0b2 +#define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT44_CONTROL 0x1c0b3 +#define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT45_ADDR_LO 0x1c0b4 +#define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT45_ADDR_HI 0x1c0b5 +#define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT45_MSG_DATA 0x1c0b6 +#define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT45_CONTROL 0x1c0b7 +#define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT46_ADDR_LO 0x1c0b8 +#define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT46_ADDR_HI 0x1c0b9 +#define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT46_MSG_DATA 0x1c0ba +#define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT46_CONTROL 0x1c0bb +#define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT47_ADDR_LO 0x1c0bc +#define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT47_ADDR_HI 0x1c0bd +#define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT47_MSG_DATA 0x1c0be +#define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT47_CONTROL 0x1c0bf +#define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT48_ADDR_LO 0x1c0c0 +#define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT48_ADDR_HI 0x1c0c1 +#define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT48_MSG_DATA 0x1c0c2 +#define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT48_CONTROL 0x1c0c3 +#define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT49_ADDR_LO 0x1c0c4 +#define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT49_ADDR_HI 0x1c0c5 +#define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT49_MSG_DATA 0x1c0c6 +#define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT49_CONTROL 0x1c0c7 +#define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT50_ADDR_LO 0x1c0c8 +#define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT50_ADDR_HI 0x1c0c9 +#define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT50_MSG_DATA 0x1c0ca +#define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT50_CONTROL 0x1c0cb +#define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT51_ADDR_LO 0x1c0cc +#define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT51_ADDR_HI 0x1c0cd +#define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT51_MSG_DATA 0x1c0ce +#define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT51_CONTROL 0x1c0cf +#define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT52_ADDR_LO 0x1c0d0 +#define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT52_ADDR_HI 0x1c0d1 +#define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT52_MSG_DATA 0x1c0d2 +#define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT52_CONTROL 0x1c0d3 +#define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT53_ADDR_LO 0x1c0d4 +#define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT53_ADDR_HI 0x1c0d5 +#define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT53_MSG_DATA 0x1c0d6 +#define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT53_CONTROL 0x1c0d7 +#define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT54_ADDR_LO 0x1c0d8 +#define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT54_ADDR_HI 0x1c0d9 +#define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT54_MSG_DATA 0x1c0da +#define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT54_CONTROL 0x1c0db +#define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT55_ADDR_LO 0x1c0dc +#define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT55_ADDR_HI 0x1c0dd +#define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT55_MSG_DATA 0x1c0de +#define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT55_CONTROL 0x1c0df +#define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT56_ADDR_LO 0x1c0e0 +#define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT56_ADDR_HI 0x1c0e1 +#define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT56_MSG_DATA 0x1c0e2 +#define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT56_CONTROL 0x1c0e3 +#define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT57_ADDR_LO 0x1c0e4 +#define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT57_ADDR_HI 0x1c0e5 +#define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT57_MSG_DATA 0x1c0e6 +#define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT57_CONTROL 0x1c0e7 +#define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT58_ADDR_LO 0x1c0e8 +#define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT58_ADDR_HI 0x1c0e9 +#define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT58_MSG_DATA 0x1c0ea +#define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT58_CONTROL 0x1c0eb +#define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT59_ADDR_LO 0x1c0ec +#define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT59_ADDR_HI 0x1c0ed +#define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT59_MSG_DATA 0x1c0ee +#define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT59_CONTROL 0x1c0ef +#define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT60_ADDR_LO 0x1c0f0 +#define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT60_ADDR_HI 0x1c0f1 +#define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT60_MSG_DATA 0x1c0f2 +#define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT60_CONTROL 0x1c0f3 +#define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT61_ADDR_LO 0x1c0f4 +#define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT61_ADDR_HI 0x1c0f5 +#define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT61_MSG_DATA 0x1c0f6 +#define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT61_CONTROL 0x1c0f7 +#define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT62_ADDR_LO 0x1c0f8 +#define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT62_ADDR_HI 0x1c0f9 +#define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT62_MSG_DATA 0x1c0fa +#define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT62_CONTROL 0x1c0fb +#define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT63_ADDR_LO 0x1c0fc +#define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT63_ADDR_HI 0x1c0fd +#define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT63_MSG_DATA 0x1c0fe +#define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT63_CONTROL 0x1c0ff +#define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT64_ADDR_LO 0x1c100 +#define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT64_ADDR_HI 0x1c101 +#define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT64_MSG_DATA 0x1c102 +#define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT64_CONTROL 0x1c103 +#define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT65_ADDR_LO 0x1c104 +#define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT65_ADDR_HI 0x1c105 +#define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT65_MSG_DATA 0x1c106 +#define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT65_CONTROL 0x1c107 +#define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT66_ADDR_LO 0x1c108 +#define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT66_ADDR_HI 0x1c109 +#define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT66_MSG_DATA 0x1c10a +#define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT66_CONTROL 0x1c10b +#define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT67_ADDR_LO 0x1c10c +#define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT67_ADDR_HI 0x1c10d +#define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT67_MSG_DATA 0x1c10e +#define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT67_CONTROL 0x1c10f +#define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT68_ADDR_LO 0x1c110 +#define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT68_ADDR_HI 0x1c111 +#define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT68_MSG_DATA 0x1c112 +#define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT68_CONTROL 0x1c113 +#define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT69_ADDR_LO 0x1c114 +#define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT69_ADDR_HI 0x1c115 +#define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT69_MSG_DATA 0x1c116 +#define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT69_CONTROL 0x1c117 +#define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT70_ADDR_LO 0x1c118 +#define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT70_ADDR_HI 0x1c119 +#define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT70_MSG_DATA 0x1c11a +#define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT70_CONTROL 0x1c11b +#define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT71_ADDR_LO 0x1c11c +#define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT71_ADDR_HI 0x1c11d +#define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT71_MSG_DATA 0x1c11e +#define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT71_CONTROL 0x1c11f +#define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT72_ADDR_LO 0x1c120 +#define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT72_ADDR_HI 0x1c121 +#define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT72_MSG_DATA 0x1c122 +#define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT72_CONTROL 0x1c123 +#define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT73_ADDR_LO 0x1c124 +#define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT73_ADDR_HI 0x1c125 +#define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT73_MSG_DATA 0x1c126 +#define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT73_CONTROL 0x1c127 +#define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT74_ADDR_LO 0x1c128 +#define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT74_ADDR_HI 0x1c129 +#define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT74_MSG_DATA 0x1c12a +#define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT74_CONTROL 0x1c12b +#define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT75_ADDR_LO 0x1c12c +#define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT75_ADDR_HI 0x1c12d +#define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT75_MSG_DATA 0x1c12e +#define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT75_CONTROL 0x1c12f +#define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT76_ADDR_LO 0x1c130 +#define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT76_ADDR_HI 0x1c131 +#define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT76_MSG_DATA 0x1c132 +#define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT76_CONTROL 0x1c133 +#define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT77_ADDR_LO 0x1c134 +#define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT77_ADDR_HI 0x1c135 +#define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT77_MSG_DATA 0x1c136 +#define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT77_CONTROL 0x1c137 +#define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT78_ADDR_LO 0x1c138 +#define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT78_ADDR_HI 0x1c139 +#define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT78_MSG_DATA 0x1c13a +#define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT78_CONTROL 0x1c13b +#define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT79_ADDR_LO 0x1c13c +#define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT79_ADDR_HI 0x1c13d +#define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT79_MSG_DATA 0x1c13e +#define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT79_CONTROL 0x1c13f +#define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT80_ADDR_LO 0x1c140 +#define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT80_ADDR_HI 0x1c141 +#define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT80_MSG_DATA 0x1c142 +#define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT80_CONTROL 0x1c143 +#define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT81_ADDR_LO 0x1c144 +#define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT81_ADDR_HI 0x1c145 +#define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT81_MSG_DATA 0x1c146 +#define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT81_CONTROL 0x1c147 +#define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT82_ADDR_LO 0x1c148 +#define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT82_ADDR_HI 0x1c149 +#define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT82_MSG_DATA 0x1c14a +#define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT82_CONTROL 0x1c14b +#define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT83_ADDR_LO 0x1c14c +#define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT83_ADDR_HI 0x1c14d +#define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT83_MSG_DATA 0x1c14e +#define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT83_CONTROL 0x1c14f +#define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT84_ADDR_LO 0x1c150 +#define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT84_ADDR_HI 0x1c151 +#define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT84_MSG_DATA 0x1c152 +#define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT84_CONTROL 0x1c153 +#define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT85_ADDR_LO 0x1c154 +#define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT85_ADDR_HI 0x1c155 +#define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT85_MSG_DATA 0x1c156 +#define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT85_CONTROL 0x1c157 +#define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT86_ADDR_LO 0x1c158 +#define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT86_ADDR_HI 0x1c159 +#define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT86_MSG_DATA 0x1c15a +#define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT86_CONTROL 0x1c15b +#define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT87_ADDR_LO 0x1c15c +#define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT87_ADDR_HI 0x1c15d +#define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT87_MSG_DATA 0x1c15e +#define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT87_CONTROL 0x1c15f +#define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT88_ADDR_LO 0x1c160 +#define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT88_ADDR_HI 0x1c161 +#define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT88_MSG_DATA 0x1c162 +#define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT88_CONTROL 0x1c163 +#define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT89_ADDR_LO 0x1c164 +#define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT89_ADDR_HI 0x1c165 +#define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT89_MSG_DATA 0x1c166 +#define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT89_CONTROL 0x1c167 +#define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT90_ADDR_LO 0x1c168 +#define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT90_ADDR_HI 0x1c169 +#define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT90_MSG_DATA 0x1c16a +#define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT90_CONTROL 0x1c16b +#define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT91_ADDR_LO 0x1c16c +#define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT91_ADDR_HI 0x1c16d +#define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT91_MSG_DATA 0x1c16e +#define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT91_CONTROL 0x1c16f +#define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT92_ADDR_LO 0x1c170 +#define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT92_ADDR_HI 0x1c171 +#define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT92_MSG_DATA 0x1c172 +#define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT92_CONTROL 0x1c173 +#define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT93_ADDR_LO 0x1c174 +#define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT93_ADDR_HI 0x1c175 +#define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT93_MSG_DATA 0x1c176 +#define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT93_CONTROL 0x1c177 +#define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT94_ADDR_LO 0x1c178 +#define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT94_ADDR_HI 0x1c179 +#define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT94_MSG_DATA 0x1c17a +#define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT94_CONTROL 0x1c17b +#define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT95_ADDR_LO 0x1c17c +#define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT95_ADDR_HI 0x1c17d +#define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT95_MSG_DATA 0x1c17e +#define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT95_CONTROL 0x1c17f +#define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT96_ADDR_LO 0x1c180 +#define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT96_ADDR_HI 0x1c181 +#define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT96_MSG_DATA 0x1c182 +#define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT96_CONTROL 0x1c183 +#define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT97_ADDR_LO 0x1c184 +#define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT97_ADDR_HI 0x1c185 +#define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT97_MSG_DATA 0x1c186 +#define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT97_CONTROL 0x1c187 +#define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT98_ADDR_LO 0x1c188 +#define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT98_ADDR_HI 0x1c189 +#define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT98_MSG_DATA 0x1c18a +#define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT98_CONTROL 0x1c18b +#define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT99_ADDR_LO 0x1c18c +#define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT99_ADDR_HI 0x1c18d +#define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT99_MSG_DATA 0x1c18e +#define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT99_CONTROL 0x1c18f +#define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT100_ADDR_LO 0x1c190 +#define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT100_ADDR_HI 0x1c191 +#define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT100_MSG_DATA 0x1c192 +#define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT100_CONTROL 0x1c193 +#define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT101_ADDR_LO 0x1c194 +#define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT101_ADDR_HI 0x1c195 +#define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT101_MSG_DATA 0x1c196 +#define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT101_CONTROL 0x1c197 +#define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT102_ADDR_LO 0x1c198 +#define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT102_ADDR_HI 0x1c199 +#define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT102_MSG_DATA 0x1c19a +#define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT102_CONTROL 0x1c19b +#define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT103_ADDR_LO 0x1c19c +#define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT103_ADDR_HI 0x1c19d +#define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT103_MSG_DATA 0x1c19e +#define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT103_CONTROL 0x1c19f +#define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT104_ADDR_LO 0x1c1a0 +#define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT104_ADDR_HI 0x1c1a1 +#define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT104_MSG_DATA 0x1c1a2 +#define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT104_CONTROL 0x1c1a3 +#define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT105_ADDR_LO 0x1c1a4 +#define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT105_ADDR_HI 0x1c1a5 +#define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT105_MSG_DATA 0x1c1a6 +#define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT105_CONTROL 0x1c1a7 +#define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT106_ADDR_LO 0x1c1a8 +#define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT106_ADDR_HI 0x1c1a9 +#define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT106_MSG_DATA 0x1c1aa +#define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT106_CONTROL 0x1c1ab +#define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT107_ADDR_LO 0x1c1ac +#define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT107_ADDR_HI 0x1c1ad +#define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT107_MSG_DATA 0x1c1ae +#define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT107_CONTROL 0x1c1af +#define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT108_ADDR_LO 0x1c1b0 +#define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT108_ADDR_HI 0x1c1b1 +#define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT108_MSG_DATA 0x1c1b2 +#define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT108_CONTROL 0x1c1b3 +#define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT109_ADDR_LO 0x1c1b4 +#define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT109_ADDR_HI 0x1c1b5 +#define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT109_MSG_DATA 0x1c1b6 +#define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT109_CONTROL 0x1c1b7 +#define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT110_ADDR_LO 0x1c1b8 +#define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT110_ADDR_HI 0x1c1b9 +#define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT110_MSG_DATA 0x1c1ba +#define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT110_CONTROL 0x1c1bb +#define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT111_ADDR_LO 0x1c1bc +#define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT111_ADDR_HI 0x1c1bd +#define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT111_MSG_DATA 0x1c1be +#define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT111_CONTROL 0x1c1bf +#define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT112_ADDR_LO 0x1c1c0 +#define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT112_ADDR_HI 0x1c1c1 +#define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT112_MSG_DATA 0x1c1c2 +#define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT112_CONTROL 0x1c1c3 +#define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT113_ADDR_LO 0x1c1c4 +#define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT113_ADDR_HI 0x1c1c5 +#define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT113_MSG_DATA 0x1c1c6 +#define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT113_CONTROL 0x1c1c7 +#define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT114_ADDR_LO 0x1c1c8 +#define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT114_ADDR_HI 0x1c1c9 +#define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT114_MSG_DATA 0x1c1ca +#define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT114_CONTROL 0x1c1cb +#define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT115_ADDR_LO 0x1c1cc +#define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT115_ADDR_HI 0x1c1cd +#define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT115_MSG_DATA 0x1c1ce +#define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT115_CONTROL 0x1c1cf +#define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT116_ADDR_LO 0x1c1d0 +#define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT116_ADDR_HI 0x1c1d1 +#define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT116_MSG_DATA 0x1c1d2 +#define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT116_CONTROL 0x1c1d3 +#define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT117_ADDR_LO 0x1c1d4 +#define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT117_ADDR_HI 0x1c1d5 +#define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT117_MSG_DATA 0x1c1d6 +#define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT117_CONTROL 0x1c1d7 +#define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT118_ADDR_LO 0x1c1d8 +#define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT118_ADDR_HI 0x1c1d9 +#define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT118_MSG_DATA 0x1c1da +#define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT118_CONTROL 0x1c1db +#define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT119_ADDR_LO 0x1c1dc +#define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT119_ADDR_HI 0x1c1dd +#define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT119_MSG_DATA 0x1c1de +#define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT119_CONTROL 0x1c1df +#define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT120_ADDR_LO 0x1c1e0 +#define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT120_ADDR_HI 0x1c1e1 +#define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT120_MSG_DATA 0x1c1e2 +#define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT120_CONTROL 0x1c1e3 +#define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT121_ADDR_LO 0x1c1e4 +#define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT121_ADDR_HI 0x1c1e5 +#define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT121_MSG_DATA 0x1c1e6 +#define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT121_CONTROL 0x1c1e7 +#define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT122_ADDR_LO 0x1c1e8 +#define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT122_ADDR_HI 0x1c1e9 +#define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT122_MSG_DATA 0x1c1ea +#define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT122_CONTROL 0x1c1eb +#define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT123_ADDR_LO 0x1c1ec +#define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT123_ADDR_HI 0x1c1ed +#define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT123_MSG_DATA 0x1c1ee +#define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT123_CONTROL 0x1c1ef +#define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT124_ADDR_LO 0x1c1f0 +#define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT124_ADDR_HI 0x1c1f1 +#define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT124_MSG_DATA 0x1c1f2 +#define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT124_CONTROL 0x1c1f3 +#define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT125_ADDR_LO 0x1c1f4 +#define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT125_ADDR_HI 0x1c1f5 +#define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT125_MSG_DATA 0x1c1f6 +#define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT125_CONTROL 0x1c1f7 +#define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT126_ADDR_LO 0x1c1f8 +#define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT126_ADDR_HI 0x1c1f9 +#define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT126_MSG_DATA 0x1c1fa +#define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT126_CONTROL 0x1c1fb +#define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT127_ADDR_LO 0x1c1fc +#define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT127_ADDR_HI 0x1c1fd +#define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT127_MSG_DATA 0x1c1fe +#define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT127_CONTROL 0x1c1ff +#define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT128_ADDR_LO 0x1c200 +#define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT128_ADDR_HI 0x1c201 +#define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT128_MSG_DATA 0x1c202 +#define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT128_CONTROL 0x1c203 +#define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT129_ADDR_LO 0x1c204 +#define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT129_ADDR_HI 0x1c205 +#define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT129_MSG_DATA 0x1c206 +#define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT129_CONTROL 0x1c207 +#define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT130_ADDR_LO 0x1c208 +#define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT130_ADDR_HI 0x1c209 +#define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT130_MSG_DATA 0x1c20a +#define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT130_CONTROL 0x1c20b +#define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT131_ADDR_LO 0x1c20c +#define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT131_ADDR_HI 0x1c20d +#define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT131_MSG_DATA 0x1c20e +#define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT131_CONTROL 0x1c20f +#define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT132_ADDR_LO 0x1c210 +#define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT132_ADDR_HI 0x1c211 +#define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT132_MSG_DATA 0x1c212 +#define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT132_CONTROL 0x1c213 +#define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT133_ADDR_LO 0x1c214 +#define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT133_ADDR_HI 0x1c215 +#define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT133_MSG_DATA 0x1c216 +#define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT133_CONTROL 0x1c217 +#define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT134_ADDR_LO 0x1c218 +#define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT134_ADDR_HI 0x1c219 +#define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT134_MSG_DATA 0x1c21a +#define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT134_CONTROL 0x1c21b +#define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT135_ADDR_LO 0x1c21c +#define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT135_ADDR_HI 0x1c21d +#define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT135_MSG_DATA 0x1c21e +#define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT135_CONTROL 0x1c21f +#define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT136_ADDR_LO 0x1c220 +#define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT136_ADDR_HI 0x1c221 +#define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT136_MSG_DATA 0x1c222 +#define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT136_CONTROL 0x1c223 +#define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT137_ADDR_LO 0x1c224 +#define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT137_ADDR_HI 0x1c225 +#define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT137_MSG_DATA 0x1c226 +#define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT137_CONTROL 0x1c227 +#define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT138_ADDR_LO 0x1c228 +#define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT138_ADDR_HI 0x1c229 +#define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT138_MSG_DATA 0x1c22a +#define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT138_CONTROL 0x1c22b +#define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT139_ADDR_LO 0x1c22c +#define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT139_ADDR_HI 0x1c22d +#define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT139_MSG_DATA 0x1c22e +#define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT139_CONTROL 0x1c22f +#define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT140_ADDR_LO 0x1c230 +#define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT140_ADDR_HI 0x1c231 +#define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT140_MSG_DATA 0x1c232 +#define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT140_CONTROL 0x1c233 +#define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT141_ADDR_LO 0x1c234 +#define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT141_ADDR_HI 0x1c235 +#define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT141_MSG_DATA 0x1c236 +#define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT141_CONTROL 0x1c237 +#define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT142_ADDR_LO 0x1c238 +#define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT142_ADDR_HI 0x1c239 +#define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT142_MSG_DATA 0x1c23a +#define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT142_CONTROL 0x1c23b +#define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT143_ADDR_LO 0x1c23c +#define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT143_ADDR_HI 0x1c23d +#define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT143_MSG_DATA 0x1c23e +#define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT143_CONTROL 0x1c23f +#define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT144_ADDR_LO 0x1c240 +#define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT144_ADDR_HI 0x1c241 +#define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT144_MSG_DATA 0x1c242 +#define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT144_CONTROL 0x1c243 +#define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT145_ADDR_LO 0x1c244 +#define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT145_ADDR_HI 0x1c245 +#define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT145_MSG_DATA 0x1c246 +#define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT145_CONTROL 0x1c247 +#define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT146_ADDR_LO 0x1c248 +#define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT146_ADDR_HI 0x1c249 +#define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT146_MSG_DATA 0x1c24a +#define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT146_CONTROL 0x1c24b +#define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT147_ADDR_LO 0x1c24c +#define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT147_ADDR_HI 0x1c24d +#define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT147_MSG_DATA 0x1c24e +#define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT147_CONTROL 0x1c24f +#define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT148_ADDR_LO 0x1c250 +#define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT148_ADDR_HI 0x1c251 +#define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT148_MSG_DATA 0x1c252 +#define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT148_CONTROL 0x1c253 +#define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT149_ADDR_LO 0x1c254 +#define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT149_ADDR_HI 0x1c255 +#define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT149_MSG_DATA 0x1c256 +#define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT149_CONTROL 0x1c257 +#define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT150_ADDR_LO 0x1c258 +#define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT150_ADDR_HI 0x1c259 +#define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT150_MSG_DATA 0x1c25a +#define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT150_CONTROL 0x1c25b +#define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT151_ADDR_LO 0x1c25c +#define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT151_ADDR_HI 0x1c25d +#define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT151_MSG_DATA 0x1c25e +#define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT151_CONTROL 0x1c25f +#define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT152_ADDR_LO 0x1c260 +#define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT152_ADDR_HI 0x1c261 +#define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT152_MSG_DATA 0x1c262 +#define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT152_CONTROL 0x1c263 +#define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT153_ADDR_LO 0x1c264 +#define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT153_ADDR_HI 0x1c265 +#define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT153_MSG_DATA 0x1c266 +#define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT153_CONTROL 0x1c267 +#define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT154_ADDR_LO 0x1c268 +#define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT154_ADDR_HI 0x1c269 +#define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT154_MSG_DATA 0x1c26a +#define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT154_CONTROL 0x1c26b +#define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT155_ADDR_LO 0x1c26c +#define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT155_ADDR_HI 0x1c26d +#define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT155_MSG_DATA 0x1c26e +#define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT155_CONTROL 0x1c26f +#define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT156_ADDR_LO 0x1c270 +#define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT156_ADDR_HI 0x1c271 +#define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT156_MSG_DATA 0x1c272 +#define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT156_CONTROL 0x1c273 +#define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT157_ADDR_LO 0x1c274 +#define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT157_ADDR_HI 0x1c275 +#define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT157_MSG_DATA 0x1c276 +#define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT157_CONTROL 0x1c277 +#define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT158_ADDR_LO 0x1c278 +#define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT158_ADDR_HI 0x1c279 +#define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT158_MSG_DATA 0x1c27a +#define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT158_CONTROL 0x1c27b +#define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT159_ADDR_LO 0x1c27c +#define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT159_ADDR_HI 0x1c27d +#define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT159_MSG_DATA 0x1c27e +#define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT159_CONTROL 0x1c27f +#define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT160_ADDR_LO 0x1c280 +#define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT160_ADDR_HI 0x1c281 +#define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT160_MSG_DATA 0x1c282 +#define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT160_CONTROL 0x1c283 +#define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT161_ADDR_LO 0x1c284 +#define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT161_ADDR_HI 0x1c285 +#define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT161_MSG_DATA 0x1c286 +#define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT161_CONTROL 0x1c287 +#define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT162_ADDR_LO 0x1c288 +#define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT162_ADDR_HI 0x1c289 +#define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT162_MSG_DATA 0x1c28a +#define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT162_CONTROL 0x1c28b +#define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT163_ADDR_LO 0x1c28c +#define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT163_ADDR_HI 0x1c28d +#define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT163_MSG_DATA 0x1c28e +#define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT163_CONTROL 0x1c28f +#define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT164_ADDR_LO 0x1c290 +#define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT164_ADDR_HI 0x1c291 +#define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT164_MSG_DATA 0x1c292 +#define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT164_CONTROL 0x1c293 +#define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT165_ADDR_LO 0x1c294 +#define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT165_ADDR_HI 0x1c295 +#define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT165_MSG_DATA 0x1c296 +#define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT165_CONTROL 0x1c297 +#define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT166_ADDR_LO 0x1c298 +#define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT166_ADDR_HI 0x1c299 +#define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT166_MSG_DATA 0x1c29a +#define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT166_CONTROL 0x1c29b +#define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT167_ADDR_LO 0x1c29c +#define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT167_ADDR_HI 0x1c29d +#define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT167_MSG_DATA 0x1c29e +#define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT167_CONTROL 0x1c29f +#define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT168_ADDR_LO 0x1c2a0 +#define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT168_ADDR_HI 0x1c2a1 +#define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT168_MSG_DATA 0x1c2a2 +#define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT168_CONTROL 0x1c2a3 +#define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT169_ADDR_LO 0x1c2a4 +#define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT169_ADDR_HI 0x1c2a5 +#define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT169_MSG_DATA 0x1c2a6 +#define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT169_CONTROL 0x1c2a7 +#define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT170_ADDR_LO 0x1c2a8 +#define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT170_ADDR_HI 0x1c2a9 +#define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT170_MSG_DATA 0x1c2aa +#define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT170_CONTROL 0x1c2ab +#define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT171_ADDR_LO 0x1c2ac +#define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT171_ADDR_HI 0x1c2ad +#define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT171_MSG_DATA 0x1c2ae +#define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT171_CONTROL 0x1c2af +#define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT172_ADDR_LO 0x1c2b0 +#define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT172_ADDR_HI 0x1c2b1 +#define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT172_MSG_DATA 0x1c2b2 +#define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT172_CONTROL 0x1c2b3 +#define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT173_ADDR_LO 0x1c2b4 +#define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT173_ADDR_HI 0x1c2b5 +#define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT173_MSG_DATA 0x1c2b6 +#define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT173_CONTROL 0x1c2b7 +#define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT174_ADDR_LO 0x1c2b8 +#define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT174_ADDR_HI 0x1c2b9 +#define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT174_MSG_DATA 0x1c2ba +#define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT174_CONTROL 0x1c2bb +#define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT175_ADDR_LO 0x1c2bc +#define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT175_ADDR_HI 0x1c2bd +#define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT175_MSG_DATA 0x1c2be +#define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT175_CONTROL 0x1c2bf +#define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT176_ADDR_LO 0x1c2c0 +#define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT176_ADDR_HI 0x1c2c1 +#define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT176_MSG_DATA 0x1c2c2 +#define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT176_CONTROL 0x1c2c3 +#define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT177_ADDR_LO 0x1c2c4 +#define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT177_ADDR_HI 0x1c2c5 +#define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT177_MSG_DATA 0x1c2c6 +#define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT177_CONTROL 0x1c2c7 +#define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT178_ADDR_LO 0x1c2c8 +#define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT178_ADDR_HI 0x1c2c9 +#define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT178_MSG_DATA 0x1c2ca +#define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT178_CONTROL 0x1c2cb +#define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT179_ADDR_LO 0x1c2cc +#define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT179_ADDR_HI 0x1c2cd +#define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT179_MSG_DATA 0x1c2ce +#define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT179_CONTROL 0x1c2cf +#define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT180_ADDR_LO 0x1c2d0 +#define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT180_ADDR_HI 0x1c2d1 +#define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT180_MSG_DATA 0x1c2d2 +#define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT180_CONTROL 0x1c2d3 +#define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT181_ADDR_LO 0x1c2d4 +#define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT181_ADDR_HI 0x1c2d5 +#define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT181_MSG_DATA 0x1c2d6 +#define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT181_CONTROL 0x1c2d7 +#define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT182_ADDR_LO 0x1c2d8 +#define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT182_ADDR_HI 0x1c2d9 +#define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT182_MSG_DATA 0x1c2da +#define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT182_CONTROL 0x1c2db +#define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT183_ADDR_LO 0x1c2dc +#define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT183_ADDR_HI 0x1c2dd +#define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT183_MSG_DATA 0x1c2de +#define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT183_CONTROL 0x1c2df +#define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT184_ADDR_LO 0x1c2e0 +#define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT184_ADDR_HI 0x1c2e1 +#define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT184_MSG_DATA 0x1c2e2 +#define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT184_CONTROL 0x1c2e3 +#define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT185_ADDR_LO 0x1c2e4 +#define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT185_ADDR_HI 0x1c2e5 +#define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT185_MSG_DATA 0x1c2e6 +#define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT185_CONTROL 0x1c2e7 +#define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT186_ADDR_LO 0x1c2e8 +#define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT186_ADDR_HI 0x1c2e9 +#define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT186_MSG_DATA 0x1c2ea +#define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT186_CONTROL 0x1c2eb +#define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT187_ADDR_LO 0x1c2ec +#define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT187_ADDR_HI 0x1c2ed +#define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT187_MSG_DATA 0x1c2ee +#define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT187_CONTROL 0x1c2ef +#define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT188_ADDR_LO 0x1c2f0 +#define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT188_ADDR_HI 0x1c2f1 +#define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT188_MSG_DATA 0x1c2f2 +#define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT188_CONTROL 0x1c2f3 +#define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT189_ADDR_LO 0x1c2f4 +#define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT189_ADDR_HI 0x1c2f5 +#define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT189_MSG_DATA 0x1c2f6 +#define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT189_CONTROL 0x1c2f7 +#define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT190_ADDR_LO 0x1c2f8 +#define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT190_ADDR_HI 0x1c2f9 +#define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT190_MSG_DATA 0x1c2fa +#define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT190_CONTROL 0x1c2fb +#define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT191_ADDR_LO 0x1c2fc +#define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT191_ADDR_HI 0x1c2fd +#define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT191_MSG_DATA 0x1c2fe +#define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT191_CONTROL 0x1c2ff +#define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT192_ADDR_LO 0x1c300 +#define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT192_ADDR_HI 0x1c301 +#define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT192_MSG_DATA 0x1c302 +#define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT192_CONTROL 0x1c303 +#define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT193_ADDR_LO 0x1c304 +#define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT193_ADDR_HI 0x1c305 +#define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT193_MSG_DATA 0x1c306 +#define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT193_CONTROL 0x1c307 +#define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT194_ADDR_LO 0x1c308 +#define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT194_ADDR_HI 0x1c309 +#define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT194_MSG_DATA 0x1c30a +#define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT194_CONTROL 0x1c30b +#define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT195_ADDR_LO 0x1c30c +#define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT195_ADDR_HI 0x1c30d +#define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT195_MSG_DATA 0x1c30e +#define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT195_CONTROL 0x1c30f +#define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT196_ADDR_LO 0x1c310 +#define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT196_ADDR_HI 0x1c311 +#define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT196_MSG_DATA 0x1c312 +#define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT196_CONTROL 0x1c313 +#define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT197_ADDR_LO 0x1c314 +#define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT197_ADDR_HI 0x1c315 +#define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT197_MSG_DATA 0x1c316 +#define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT197_CONTROL 0x1c317 +#define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT198_ADDR_LO 0x1c318 +#define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT198_ADDR_HI 0x1c319 +#define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT198_MSG_DATA 0x1c31a +#define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT198_CONTROL 0x1c31b +#define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT199_ADDR_LO 0x1c31c +#define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT199_ADDR_HI 0x1c31d +#define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT199_MSG_DATA 0x1c31e +#define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT199_CONTROL 0x1c31f +#define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT200_ADDR_LO 0x1c320 +#define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT200_ADDR_HI 0x1c321 +#define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT200_MSG_DATA 0x1c322 +#define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT200_CONTROL 0x1c323 +#define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT201_ADDR_LO 0x1c324 +#define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT201_ADDR_HI 0x1c325 +#define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT201_MSG_DATA 0x1c326 +#define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT201_CONTROL 0x1c327 +#define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT202_ADDR_LO 0x1c328 +#define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT202_ADDR_HI 0x1c329 +#define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT202_MSG_DATA 0x1c32a +#define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT202_CONTROL 0x1c32b +#define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT203_ADDR_LO 0x1c32c +#define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT203_ADDR_HI 0x1c32d +#define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT203_MSG_DATA 0x1c32e +#define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT203_CONTROL 0x1c32f +#define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT204_ADDR_LO 0x1c330 +#define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT204_ADDR_HI 0x1c331 +#define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT204_MSG_DATA 0x1c332 +#define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT204_CONTROL 0x1c333 +#define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT205_ADDR_LO 0x1c334 +#define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT205_ADDR_HI 0x1c335 +#define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT205_MSG_DATA 0x1c336 +#define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT205_CONTROL 0x1c337 +#define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT206_ADDR_LO 0x1c338 +#define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT206_ADDR_HI 0x1c339 +#define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT206_MSG_DATA 0x1c33a +#define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT206_CONTROL 0x1c33b +#define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT207_ADDR_LO 0x1c33c +#define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT207_ADDR_HI 0x1c33d +#define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT207_MSG_DATA 0x1c33e +#define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT207_CONTROL 0x1c33f +#define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT208_ADDR_LO 0x1c340 +#define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT208_ADDR_HI 0x1c341 +#define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT208_MSG_DATA 0x1c342 +#define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT208_CONTROL 0x1c343 +#define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT209_ADDR_LO 0x1c344 +#define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT209_ADDR_HI 0x1c345 +#define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT209_MSG_DATA 0x1c346 +#define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT209_CONTROL 0x1c347 +#define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT210_ADDR_LO 0x1c348 +#define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT210_ADDR_HI 0x1c349 +#define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT210_MSG_DATA 0x1c34a +#define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT210_CONTROL 0x1c34b +#define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT211_ADDR_LO 0x1c34c +#define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT211_ADDR_HI 0x1c34d +#define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT211_MSG_DATA 0x1c34e +#define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT211_CONTROL 0x1c34f +#define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT212_ADDR_LO 0x1c350 +#define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT212_ADDR_HI 0x1c351 +#define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT212_MSG_DATA 0x1c352 +#define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT212_CONTROL 0x1c353 +#define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT213_ADDR_LO 0x1c354 +#define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT213_ADDR_HI 0x1c355 +#define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT213_MSG_DATA 0x1c356 +#define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT213_CONTROL 0x1c357 +#define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT214_ADDR_LO 0x1c358 +#define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT214_ADDR_HI 0x1c359 +#define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT214_MSG_DATA 0x1c35a +#define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT214_CONTROL 0x1c35b +#define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT215_ADDR_LO 0x1c35c +#define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT215_ADDR_HI 0x1c35d +#define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT215_MSG_DATA 0x1c35e +#define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT215_CONTROL 0x1c35f +#define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT216_ADDR_LO 0x1c360 +#define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT216_ADDR_HI 0x1c361 +#define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT216_MSG_DATA 0x1c362 +#define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT216_CONTROL 0x1c363 +#define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT217_ADDR_LO 0x1c364 +#define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT217_ADDR_HI 0x1c365 +#define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT217_MSG_DATA 0x1c366 +#define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT217_CONTROL 0x1c367 +#define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT218_ADDR_LO 0x1c368 +#define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT218_ADDR_HI 0x1c369 +#define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT218_MSG_DATA 0x1c36a +#define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT218_CONTROL 0x1c36b +#define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT219_ADDR_LO 0x1c36c +#define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT219_ADDR_HI 0x1c36d +#define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT219_MSG_DATA 0x1c36e +#define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT219_CONTROL 0x1c36f +#define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT220_ADDR_LO 0x1c370 +#define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT220_ADDR_HI 0x1c371 +#define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT220_MSG_DATA 0x1c372 +#define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT220_CONTROL 0x1c373 +#define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT221_ADDR_LO 0x1c374 +#define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT221_ADDR_HI 0x1c375 +#define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT221_MSG_DATA 0x1c376 +#define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT221_CONTROL 0x1c377 +#define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT222_ADDR_LO 0x1c378 +#define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT222_ADDR_HI 0x1c379 +#define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT222_MSG_DATA 0x1c37a +#define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT222_CONTROL 0x1c37b +#define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT223_ADDR_LO 0x1c37c +#define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT223_ADDR_HI 0x1c37d +#define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT223_MSG_DATA 0x1c37e +#define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT223_CONTROL 0x1c37f +#define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT224_ADDR_LO 0x1c380 +#define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT224_ADDR_HI 0x1c381 +#define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT224_MSG_DATA 0x1c382 +#define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT224_CONTROL 0x1c383 +#define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT225_ADDR_LO 0x1c384 +#define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT225_ADDR_HI 0x1c385 +#define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT225_MSG_DATA 0x1c386 +#define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT225_CONTROL 0x1c387 +#define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT226_ADDR_LO 0x1c388 +#define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT226_ADDR_HI 0x1c389 +#define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT226_MSG_DATA 0x1c38a +#define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT226_CONTROL 0x1c38b +#define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT227_ADDR_LO 0x1c38c +#define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT227_ADDR_HI 0x1c38d +#define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT227_MSG_DATA 0x1c38e +#define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT227_CONTROL 0x1c38f +#define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT228_ADDR_LO 0x1c390 +#define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT228_ADDR_HI 0x1c391 +#define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT228_MSG_DATA 0x1c392 +#define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT228_CONTROL 0x1c393 +#define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT229_ADDR_LO 0x1c394 +#define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT229_ADDR_HI 0x1c395 +#define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT229_MSG_DATA 0x1c396 +#define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT229_CONTROL 0x1c397 +#define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT230_ADDR_LO 0x1c398 +#define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT230_ADDR_HI 0x1c399 +#define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT230_MSG_DATA 0x1c39a +#define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT230_CONTROL 0x1c39b +#define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT231_ADDR_LO 0x1c39c +#define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT231_ADDR_HI 0x1c39d +#define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT231_MSG_DATA 0x1c39e +#define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT231_CONTROL 0x1c39f +#define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT232_ADDR_LO 0x1c3a0 +#define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT232_ADDR_HI 0x1c3a1 +#define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT232_MSG_DATA 0x1c3a2 +#define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT232_CONTROL 0x1c3a3 +#define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT233_ADDR_LO 0x1c3a4 +#define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT233_ADDR_HI 0x1c3a5 +#define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT233_MSG_DATA 0x1c3a6 +#define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT233_CONTROL 0x1c3a7 +#define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT234_ADDR_LO 0x1c3a8 +#define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT234_ADDR_HI 0x1c3a9 +#define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT234_MSG_DATA 0x1c3aa +#define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT234_CONTROL 0x1c3ab +#define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT235_ADDR_LO 0x1c3ac +#define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT235_ADDR_HI 0x1c3ad +#define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT235_MSG_DATA 0x1c3ae +#define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT235_CONTROL 0x1c3af +#define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT236_ADDR_LO 0x1c3b0 +#define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT236_ADDR_HI 0x1c3b1 +#define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT236_MSG_DATA 0x1c3b2 +#define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT236_CONTROL 0x1c3b3 +#define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT237_ADDR_LO 0x1c3b4 +#define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT237_ADDR_HI 0x1c3b5 +#define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT237_MSG_DATA 0x1c3b6 +#define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT237_CONTROL 0x1c3b7 +#define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT238_ADDR_LO 0x1c3b8 +#define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT238_ADDR_HI 0x1c3b9 +#define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT238_MSG_DATA 0x1c3ba +#define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT238_CONTROL 0x1c3bb +#define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT239_ADDR_LO 0x1c3bc +#define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT239_ADDR_HI 0x1c3bd +#define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT239_MSG_DATA 0x1c3be +#define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT239_CONTROL 0x1c3bf +#define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT240_ADDR_LO 0x1c3c0 +#define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT240_ADDR_HI 0x1c3c1 +#define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT240_MSG_DATA 0x1c3c2 +#define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT240_CONTROL 0x1c3c3 +#define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT241_ADDR_LO 0x1c3c4 +#define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT241_ADDR_HI 0x1c3c5 +#define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT241_MSG_DATA 0x1c3c6 +#define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT241_CONTROL 0x1c3c7 +#define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT242_ADDR_LO 0x1c3c8 +#define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT242_ADDR_HI 0x1c3c9 +#define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT242_MSG_DATA 0x1c3ca +#define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT242_CONTROL 0x1c3cb +#define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT243_ADDR_LO 0x1c3cc +#define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT243_ADDR_HI 0x1c3cd +#define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT243_MSG_DATA 0x1c3ce +#define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT243_CONTROL 0x1c3cf +#define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT244_ADDR_LO 0x1c3d0 +#define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT244_ADDR_HI 0x1c3d1 +#define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT244_MSG_DATA 0x1c3d2 +#define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT244_CONTROL 0x1c3d3 +#define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT245_ADDR_LO 0x1c3d4 +#define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT245_ADDR_HI 0x1c3d5 +#define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT245_MSG_DATA 0x1c3d6 +#define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT245_CONTROL 0x1c3d7 +#define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT246_ADDR_LO 0x1c3d8 +#define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT246_ADDR_HI 0x1c3d9 +#define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT246_MSG_DATA 0x1c3da +#define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT246_CONTROL 0x1c3db +#define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT247_ADDR_LO 0x1c3dc +#define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT247_ADDR_HI 0x1c3dd +#define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT247_MSG_DATA 0x1c3de +#define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT247_CONTROL 0x1c3df +#define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT248_ADDR_LO 0x1c3e0 +#define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT248_ADDR_HI 0x1c3e1 +#define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT248_MSG_DATA 0x1c3e2 +#define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT248_CONTROL 0x1c3e3 +#define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT249_ADDR_LO 0x1c3e4 +#define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT249_ADDR_HI 0x1c3e5 +#define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT249_MSG_DATA 0x1c3e6 +#define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT249_CONTROL 0x1c3e7 +#define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT250_ADDR_LO 0x1c3e8 +#define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT250_ADDR_HI 0x1c3e9 +#define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT250_MSG_DATA 0x1c3ea +#define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT250_CONTROL 0x1c3eb +#define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT251_ADDR_LO 0x1c3ec +#define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT251_ADDR_HI 0x1c3ed +#define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT251_MSG_DATA 0x1c3ee +#define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT251_CONTROL 0x1c3ef +#define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT252_ADDR_LO 0x1c3f0 +#define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT252_ADDR_HI 0x1c3f1 +#define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT252_MSG_DATA 0x1c3f2 +#define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT252_CONTROL 0x1c3f3 +#define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT253_ADDR_LO 0x1c3f4 +#define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT253_ADDR_HI 0x1c3f5 +#define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT253_MSG_DATA 0x1c3f6 +#define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT253_CONTROL 0x1c3f7 +#define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT254_ADDR_LO 0x1c3f8 +#define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT254_ADDR_HI 0x1c3f9 +#define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT254_MSG_DATA 0x1c3fa +#define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT254_CONTROL 0x1c3fb +#define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 5 +#define regPCIEMSIX_VECT255_ADDR_LO 0x1c3fc +#define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 5 +#define regPCIEMSIX_VECT255_ADDR_HI 0x1c3fd +#define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 5 +#define regPCIEMSIX_VECT255_MSG_DATA 0x1c3fe +#define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 5 +#define regPCIEMSIX_VECT255_CONTROL 0x1c3ff +#define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 5 + + +// base address: 0x10171000 +#define regPCIEMSIX_PBA_0 0x1c400 +#define regPCIEMSIX_PBA_0_BASE_IDX 5 +#define regPCIEMSIX_PBA_1 0x1c401 +#define regPCIEMSIX_PBA_1_BASE_IDX 5 +#define regPCIEMSIX_PBA_2 0x1c402 +#define regPCIEMSIX_PBA_2_BASE_IDX 5 +#define regPCIEMSIX_PBA_3 0x1c403 +#define regPCIEMSIX_PBA_3_BASE_IDX 5 +#define regPCIEMSIX_PBA_4 0x1c404 +#define regPCIEMSIX_PBA_4_BASE_IDX 5 +#define regPCIEMSIX_PBA_5 0x1c405 +#define regPCIEMSIX_PBA_5_BASE_IDX 5 +#define regPCIEMSIX_PBA_6 0x1c406 +#define regPCIEMSIX_PBA_6_BASE_IDX 5 +#define regPCIEMSIX_PBA_7 0x1c407 +#define regPCIEMSIX_PBA_7_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec +// base address: 0x10130000 +#define regSHADOW_COMMAND 0xc001 +#define regSHADOW_COMMAND_BASE_IDX 5 +#define regSHADOW_BASE_ADDR_1 0xc004 +#define regSHADOW_BASE_ADDR_1_BASE_IDX 5 +#define regSHADOW_BASE_ADDR_2 0xc005 +#define regSHADOW_BASE_ADDR_2_BASE_IDX 5 +#define regSHADOW_SUB_BUS_NUMBER_LATENCY 0xc006 +#define regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 +#define regSHADOW_IO_BASE_LIMIT 0xc007 +#define regSHADOW_IO_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_MEM_BASE_LIMIT 0xc008 +#define regSHADOW_MEM_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_PREF_BASE_LIMIT 0xc009 +#define regSHADOW_PREF_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_PREF_BASE_UPPER 0xc00a +#define regSHADOW_PREF_BASE_UPPER_BASE_IDX 5 +#define regSHADOW_PREF_LIMIT_UPPER 0xc00b +#define regSHADOW_PREF_LIMIT_UPPER_BASE_IDX 5 +#define regSHADOW_IO_BASE_LIMIT_HI 0xc00c +#define regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX 5 +#define regSUC_INDEX 0xc038 +#define regSUC_INDEX_BASE_IDX 5 +#define regSUC_DATA 0xc039 +#define regSUC_DATA_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_swus_SUMDEC +// base address: 0x1013b000 +#define regSUM_INDEX 0xec38 +#define regSUM_INDEX_BASE_IDX 5 +#define regSUM_DATA 0xec39 +#define regSUM_DATA_BASE_IDX 5 +#define regSUM_INDEX_HI 0xec3b +#define regSUM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal +// base address: 0x10100000 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP0 0xc480 +#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP1 0xc481 +#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP2 0xc482 +#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP3 0xc483 +#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP4 0xc484 +#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP5 0xc485 +#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP6 0xc486 +#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP7 0xc487 +#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP8 0xc488 +#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP9 0xc489 +#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP10 0xc48a +#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP11 0xc48b +#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP12 0xc48c +#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP13 0xc48d +#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP14 0xc48e +#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP0 0xc500 +#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP1 0xc501 +#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP2 0xc502 +#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP3 0xc503 +#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP4 0xc504 +#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP5 0xc505 +#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP6 0xc506 +#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP7 0xc507 +#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP8 0xc508 +#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP9 0xc509 +#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP10 0xc50a +#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP11 0xc50b +#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP12 0xc50c +#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP13 0xc50d +#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP14 0xc50e +#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 +#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 +#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 +#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 +#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 +#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 +#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 +#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 0xd01a +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 0xd096 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 0xd099 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP0 0xd100 +#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP2 0xd102 +#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP3 0xd103 +#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP4 0xd104 +#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP5 0xd105 +#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP6 0xd106 +#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP7 0xd107 +#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP10 0xd10a +#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP11 0xd10b +#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP12 0xd10c +#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP13 0xd10d +#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP14 0xd10e +#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP20 0xd114 +#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP0 0xd180 +#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP2 0xd182 +#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP3 0xd183 +#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP4 0xd184 +#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP5 0xd185 +#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP6 0xd186 +#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP7 0xd187 +#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP10 0xd18a +#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP11 0xd18b +#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP12 0xd18c +#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP13 0xd18d +#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP14 0xd18e +#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP20 0xd194 +#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP0 0xd200 +#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP2 0xd202 +#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP3 0xd203 +#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP4 0xd204 +#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP5 0xd205 +#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP6 0xd206 +#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP7 0xd207 +#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP13 0xd20d +#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP14 0xd20e +#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP0 0xd280 +#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP2 0xd282 +#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP3 0xd283 +#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP4 0xd284 +#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP5 0xd285 +#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP6 0xd286 +#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP7 0xd287 +#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP13 0xd28d +#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP14 0xd28e +#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP0 0xd300 +#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP2 0xd302 +#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP3 0xd303 +#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP4 0xd304 +#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP5 0xd305 +#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP6 0xd306 +#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP13 0xd30d +#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP14 0xd30e +#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP0 0xd380 +#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP2 0xd382 +#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP3 0xd383 +#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP4 0xd384 +#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP5 0xd385 +#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP6 0xd386 +#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP7 0xd387 +#define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP13 0xd38d +#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP14 0xd38e +#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP0 0xd400 +#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP2 0xd402 +#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP3 0xd403 +#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP4 0xd404 +#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP5 0xd405 +#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP6 0xd406 +#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP7 0xd407 +#define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP13 0xd40d +#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP14 0xd40e +#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP0 0xd480 +#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP2 0xd482 +#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP3 0xd483 +#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP4 0xd484 +#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP5 0xd485 +#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP6 0xd486 +#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP7 0xd487 +#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP13 0xd48d +#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP14 0xd48e +#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP0 0xd500 +#define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP2 0xd502 +#define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP3 0xd503 +#define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP4 0xd504 +#define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP5 0xd505 +#define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP6 0xd506 +#define regRCC_DEV1_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP13 0xd50d +#define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP14 0xd50e +#define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP0 0xd580 +#define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP2 0xd582 +#define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP3 0xd583 +#define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP4 0xd584 +#define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP5 0xd585 +#define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP6 0xd586 +#define regRCC_DEV1_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP13 0xd58d +#define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP14 0xd58e +#define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP0 0xd600 +#define regRCC_DEV1_EPF4_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP2 0xd602 +#define regRCC_DEV1_EPF4_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP3 0xd603 +#define regRCC_DEV1_EPF4_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP4 0xd604 +#define regRCC_DEV1_EPF4_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP5 0xd605 +#define regRCC_DEV1_EPF4_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP6 0xd606 +#define regRCC_DEV1_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP13 0xd60d +#define regRCC_DEV1_EPF4_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP14 0xd60e +#define regRCC_DEV1_EPF4_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP0 0xd680 +#define regRCC_DEV1_EPF5_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP2 0xd682 +#define regRCC_DEV1_EPF5_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP3 0xd683 +#define regRCC_DEV1_EPF5_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP4 0xd684 +#define regRCC_DEV1_EPF5_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP5 0xd685 +#define regRCC_DEV1_EPF5_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP6 0xd686 +#define regRCC_DEV1_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP13 0xd68d +#define regRCC_DEV1_EPF5_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP14 0xd68e +#define regRCC_DEV1_EPF5_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP0 0xd800 +#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP2 0xd802 +#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP3 0xd803 +#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP4 0xd804 +#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP5 0xd805 +#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP6 0xd806 +#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP7 0xd807 +#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP13 0xd80d +#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP14 0xd80e +#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP0 0xd880 +#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP2 0xd882 +#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP3 0xd883 +#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP4 0xd884 +#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP5 0xd885 +#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP6 0xd886 +#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP13 0xd88d +#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP14 0xd88e +#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP0 0xd900 +#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP2 0xd902 +#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP3 0xd903 +#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP4 0xd904 +#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP5 0xd905 +#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP6 0xd906 +#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP13 0xd90d +#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP14 0xd90e +#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk +// base address: 0x10100000 +#define regHARD_RST_CTRL 0xe000 +#define regHARD_RST_CTRL_BASE_IDX 5 +#define regSELF_SOFT_RST 0xe002 +#define regSELF_SOFT_RST_BASE_IDX 5 +#define regBIF_GFX_DRV_VPU_RST 0xe003 +#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL 0xe004 +#define regBIF_RST_MISC_CTRL_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL2 0xe005 +#define regBIF_RST_MISC_CTRL2_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL3 0xe006 +#define regBIF_RST_MISC_CTRL3_BASE_IDX 5 +#define regDEV0_PF0_FLR_RST_CTRL 0xe008 +#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF1_FLR_RST_CTRL 0xe009 +#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF2_FLR_RST_CTRL 0xe00a +#define regDEV0_PF2_FLR_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF3_FLR_RST_CTRL 0xe00b +#define regDEV0_PF3_FLR_RST_CTRL_BASE_IDX 5 +#define regBIF_INST_RESET_INTR_STS 0xe010 +#define regBIF_INST_RESET_INTR_STS_BASE_IDX 5 +#define regBIF_PF_FLR_INTR_STS 0xe011 +#define regBIF_PF_FLR_INTR_STS_BASE_IDX 5 +#define regBIF_D3HOTD0_INTR_STS 0xe012 +#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5 +#define regBIF_POWER_INTR_STS 0xe014 +#define regBIF_POWER_INTR_STS_BASE_IDX 5 +#define regBIF_PF_DSTATE_INTR_STS 0xe015 +#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5 +#define regSELF_SOFT_RST_2 0xe016 +#define regSELF_SOFT_RST_2_BASE_IDX 5 +#define regBIF_INST_RESET_INTR_MASK 0xe020 +#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_FLR_INTR_MASK 0xe021 +#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5 +#define regBIF_D3HOTD0_INTR_MASK 0xe022 +#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5 +#define regBIF_POWER_INTR_MASK 0xe024 +#define regBIF_POWER_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_DSTATE_INTR_MASK 0xe025 +#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_FLR_RST 0xe040 +#define regBIF_PF_FLR_RST_BASE_IDX 5 +#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 +#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5 +#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 +#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5 +#define regBIF_DEV0_PF2_DSTATE_VALUE 0xe052 +#define regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX 5 +#define regBIF_DEV0_PF3_DSTATE_VALUE 0xe053 +#define regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX 5 +#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 +#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 +#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF2_D3HOTD0_RST_CTRL 0xe07a +#define regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF3_D3HOTD0_RST_CTRL 0xe07b +#define regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regBIF_PORT0_DSTATE_VALUE 0xe230 +#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk +// base address: 0x10100000 +#define regREGS_ROM_OFFSET_CTRL 0xcc23 +#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5 +#define regNBIF_STRAP_BIOS_CNTL 0xcc81 +#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5 +#define regMISC_SCRATCH 0xe800 +#define regMISC_SCRATCH_BASE_IDX 5 +#define regINTR_LINE_POLARITY 0xe801 +#define regINTR_LINE_POLARITY_BASE_IDX 5 +#define regINTR_LINE_ENABLE 0xe802 +#define regINTR_LINE_ENABLE_BASE_IDX 5 +#define regOUTSTANDING_VC_ALLOC 0xe803 +#define regOUTSTANDING_VC_ALLOC_BASE_IDX 5 +#define regBIFC_MISC_CTRL0 0xe804 +#define regBIFC_MISC_CTRL0_BASE_IDX 5 +#define regBIFC_MISC_CTRL1 0xe805 +#define regBIFC_MISC_CTRL1_BASE_IDX 5 +#define regBIFC_BME_ERR_LOG_LB 0xe806 +#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5 +#define regBIFC_LC_TIMER_CTRL 0xe807 +#define regBIFC_LC_TIMER_CTRL_BASE_IDX 5 +#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 +#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5 +#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a +#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5 +#define regBME_DUMMY_CNTL_0 0xe825 +#define regBME_DUMMY_CNTL_0_BASE_IDX 5 +#define regBIFC_HSTARB_CNTL 0xe828 +#define regBIFC_HSTARB_CNTL_BASE_IDX 5 +#define regBIFC_GSI_CNTL 0xe829 +#define regBIFC_GSI_CNTL_BASE_IDX 5 +#define regBIFC_PCIEFUNC_CNTL 0xe82a +#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5 +#define regBIFC_PASID_CHECK_DIS 0xe82b +#define regBIFC_PASID_CHECK_DIS_BASE_IDX 5 +#define regBIFC_SDP_CNTL_0 0xe82c +#define regBIFC_SDP_CNTL_0_BASE_IDX 5 +#define regBIFC_SDP_CNTL_1 0xe82d +#define regBIFC_SDP_CNTL_1_BASE_IDX 5 +#define regBIFC_PASID_STS 0xe82e +#define regBIFC_PASID_STS_BASE_IDX 5 +#define regBIFC_ATHUB_ACT_CNTL 0xe82f +#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5 +#define regBIFC_PERF_CNTL_0 0xe830 +#define regBIFC_PERF_CNTL_0_BASE_IDX 5 +#define regBIFC_PERF_CNTL_1 0xe831 +#define regBIFC_PERF_CNTL_1_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5 +#define regNBIF_REGIF_ERRSET_CTRL 0xe836 +#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5 +#define regBIFC_SDP_CNTL_2 0xe837 +#define regBIFC_SDP_CNTL_2_BASE_IDX 5 +#define regNBIF_PGMST_CTRL 0xe838 +#define regNBIF_PGMST_CTRL_BASE_IDX 5 +#define regNBIF_PGSLV_CTRL 0xe839 +#define regNBIF_PGSLV_CTRL_BASE_IDX 5 +#define regNBIF_PG_MISC_CTRL 0xe83a +#define regNBIF_PG_MISC_CTRL_BASE_IDX 5 +#define regSMN_MST_EP_CNTL3 0xe83c +#define regSMN_MST_EP_CNTL3_BASE_IDX 5 +#define regSMN_MST_EP_CNTL4 0xe83d +#define regSMN_MST_EP_CNTL4_BASE_IDX 5 +#define regSMN_MST_CNTL1 0xe83e +#define regSMN_MST_CNTL1_BASE_IDX 5 +#define regSMN_MST_EP_CNTL5 0xe83f +#define regSMN_MST_EP_CNTL5_BASE_IDX 5 +#define regBIF_SELFRING_BUFFER_VID 0xe840 +#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5 +#define regBIF_SELFRING_VECTOR_CNTL 0xe841 +#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5 +#define regNBIF_STRAP_WRITE_CTRL 0xe845 +#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5 +#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 +#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5 +#define regNBIF_PENDING_MISC_CNTL 0xe847 +#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT 0xe848 +#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT2 0xe849 +#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT3 0xe84a +#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5 +#define regNBIF_PWRBRK_REQUEST 0xe84c +#define regNBIF_PWRBRK_REQUEST_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F2 0xe852 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F3 0xe853 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX 5 +#define regBIF_DMA_MP4_ERR_LOG 0xe870 +#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5 +#define regBIF_PASID_ERR_LOG 0xe871 +#define regBIF_PASID_ERR_LOG_BASE_IDX 5 +#define regBIF_PASID_ERR_CLR 0xe872 +#define regBIF_PASID_ERR_CLR_BASE_IDX 5 +#define regNBIF_VWIRE_CTRL 0xe880 +#define regNBIF_VWIRE_CTRL_BASE_IDX 5 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 5 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 5 +#define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 +#define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 5 +#define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 +#define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 5 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 5 +#define regNBIF_MGCG_CTRL_LCLK 0xe887 +#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5 +#define regNBIF_DS_CTRL_LCLK 0xe888 +#define regNBIF_DS_CTRL_LCLK_BASE_IDX 5 +#define regSMN_MST_CNTL0 0xe889 +#define regSMN_MST_CNTL0_BASE_IDX 5 +#define regSMN_MST_EP_CNTL1 0xe88a +#define regSMN_MST_EP_CNTL1_BASE_IDX 5 +#define regSMN_MST_EP_CNTL2 0xe88b +#define regSMN_MST_EP_CNTL2_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f +#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CTRL 0xe898 +#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 +#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a +#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c +#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d +#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5 +#define regBIFC_BME_ERR_LOG_HB 0xe8ab +#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4 +#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5 +#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 +#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5 +#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 +#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_misc_pfvf_bif_misc_pfvf_regblk +// base address: 0x10100000 + + +// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk +// base address: 0x10100000 +#define regBIFL_RAS_CENTRAL_CNTL 0xe400 +#define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5 +#define regBIFL_RAS_CENTRAL_STATUS 0xe410 +#define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF0_CTRL 0xe420 +#define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF1_CTRL 0xe421 +#define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_CTRL 0xe422 +#define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF3_CTRL 0xe423 +#define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF0_STATUS 0xe430 +#define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF1_STATUS 0xe431 +#define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_STATUS 0xe432 +#define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF3_STATUS 0xe433 +#define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5 +#define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe +#define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5 +#define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff +#define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d60 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d62 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d63 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d64 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d65 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d66 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d67 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d69 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6c +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6d +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d6f +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d70 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d72 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d73 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d75 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d76 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d77 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d78 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d79 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 +#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac +#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 +#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 +#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea +#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +// base address: 0x10120000 +#define regBIF_BX1_PCIE_INDEX 0x800c +#define regBIF_BX1_PCIE_INDEX_BASE_IDX 5 +#define regBIF_BX1_PCIE_DATA 0x800d +#define regBIF_BX1_PCIE_DATA_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX2 0x800e +#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5 +#define regBIF_BX1_PCIE_DATA2 0x800f +#define regBIF_BX1_PCIE_DATA2_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX_HI 0x8010 +#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX2_HI 0x8011 +#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 +#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 +#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a +#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b +#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_0 0x804c +#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_1 0x804d +#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_2 0x804e +#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_3 0x804f +#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_4 0x8050 +#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_5 0x8051 +#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_6 0x8052 +#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_7 0x8053 +#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_8 0x8054 +#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_9 0x8055 +#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_10 0x8056 +#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_11 0x8057 +#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_12 0x8058 +#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_13 0x8059 +#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_14 0x805a +#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_15 0x805b +#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 +#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 +#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 +#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 +#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 +#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 +#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 +#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 +#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 +#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a +#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b +#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c +#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d +#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e +#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f +#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 +#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 +#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 +#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 +#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_0 0x80a4 +#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_1 0x80a5 +#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_2 0x80a6 +#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_3 0x80a7 +#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_4 0x80a8 +#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_5 0x80a9 +#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_6 0x80aa +#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_7 0x80ab +#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_8 0x80ac +#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_9 0x80ad +#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_10 0x80ae +#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_11 0x80af +#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_12 0x80b0 +#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_13 0x80b1 +#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_14 0x80b2 +#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_15 0x80b3 +#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 +#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 +#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 +#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 +#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 +#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 +#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba +#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb +#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc +#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd +#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be +#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf +#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_PF1_MM_INDEX 0x8000 +#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_PF1_MM_DATA 0x8001 +#define regBIF_BX_PF1_MM_DATA_BASE_IDX 5 +#define regBIF_BX_PF1_MM_INDEX_HI 0x8006 +#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x10120000 +#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 +#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BUS_CNTL 0x8e07 +#define regBIF_BX1_BUS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_SCRATCH0 0x8e08 +#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5 +#define regBIF_BX1_BIF_SCRATCH1 0x8e09 +#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5 +#define regBIF_BX1_BX_RESET_EN 0x8e0d +#define regBIF_BX1_BX_RESET_EN_BASE_IDX 5 +#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e +#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BX_RESET_CNTL 0x8e10 +#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5 +#define regBIF_BX1_INTERRUPT_CNTL 0x8e11 +#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5 +#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 +#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5 +#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 +#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5 +#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d +#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_FB_EN 0x8e20 +#define regBIF_BX1_BIF_FB_EN_BASE_IDX 5 +#define regBIF_BX1_BIF_INTR_CNTL 0x8e21 +#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 +#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 +#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5 +#define regBIF_BX1_VF_REGWR_EN 0x8e44 +#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5 +#define regBIF_BX1_VF_DOORBELL_EN 0x8e45 +#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5 +#define regBIF_BX1_VF_FB_EN 0x8e46 +#define regBIF_BX1_VF_FB_EN_BASE_IDX 5 +#define regBIF_BX1_VF_REGWR_STATUS 0x8e47 +#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5 +#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 +#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5 +#define regBIF_BX1_VF_FB_STATUS 0x8e49 +#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5 +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_CNTL 0x8e4f +#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_BASE 0x8e50 +#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_RPTR 0x8e51 +#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR 0x8e52 +#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 +#define regBIF_BX1_MAILBOX_INDEX 0x8e55 +#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5 +#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 +#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5 +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e63 +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 5 +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e64 +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 5 +#define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x8e65 +#define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 5 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e68 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e69 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e6a +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e6b +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6c +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_WAKEB_PAD_CNTL 0x8e6d +#define regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL 0x8e6e +#define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL 0x8e70 +#define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0 0x8e71 +#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX 5 +#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1 0x8e72 +#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX 5 +#define regBIF_BX1_BIF_S5_DUMMY_REGS 0x8e73 +#define regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1 +// base address: 0x10120000 +#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 +#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 +#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d22 +#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d23 +#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d24 +#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d25 +#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d26 +#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d27 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d28 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d29 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d2a +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d2b +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d2c +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d2d +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d2e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d2f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d30 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d31 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d32 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d33 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d34 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d35 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d36 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d37 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d38 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d39 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d3a +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d3b +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d3c +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d3d +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d3e +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 0x8d3f +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d40 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d41 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d42 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d43 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d44 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d45 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d51 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d52 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d53 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 0x8d54 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d55 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d56 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 0x8d57 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d58 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d59 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5b +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5c +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 + + +// addressBlock: nbio_nbif0_gdc_dma_sion_SIONDEC +// base address: 0x1400000 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0 0x4f743c +#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1 0x4f743d +#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0 0x4f743e +#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1 0x4f743f +#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0 0x4f7440 +#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1 0x4f7441 +#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0 0x4f7442 +#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1 0x4f7443 +#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0 0x4f7444 +#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1 0x4f7445 +#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0 0x4f7446 +#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1 0x4f7447 +#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0 0x4f7448 +#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1 0x4f7449 +#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0 0x4f744a +#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1 0x4f744b +#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0 0x4f744c +#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1 0x4f744d +#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0 0x4f744e +#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1 0x4f744f +#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CNTL_REG0 0x4f7450 +#define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CNTL_REG1 0x4f7451 +#define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_gdc_hst_sion_SIONDEC +// base address: 0x1400000 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7628 +#define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7629 +#define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0 0x4f762a +#define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1 0x4f762b +#define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0 0x4f762c +#define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1 0x4f762d +#define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0 0x4f762e +#define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1 0x4f762f +#define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_Req_BurstTarget_REG0 0x4f7630 +#define regGDC_HST_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_Req_BurstTarget_REG1 0x4f7631 +#define regGDC_HST_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_Req_TimeSlot_REG0 0x4f7632 +#define regGDC_HST_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_Req_TimeSlot_REG1 0x4f7633 +#define regGDC_HST_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7634 +#define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7635 +#define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7636 +#define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7637 +#define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7638 +#define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7639 +#define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f763a +#define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f763b +#define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CNTL_REG0 0x4f763c +#define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CNTL_REG1 0x4f763d +#define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_0_CTRL 0x4f7640 +#define regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_1_CTRL 0x4f7641 +#define regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_2_CTRL 0x4f7642 +#define regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_3_CTRL 0x4f7643 +#define regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_4_CTRL 0x4f7644 +#define regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_5_CTRL 0x4f7645 +#define regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_6_CTRL 0x4f7646 +#define regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_7_CTRL 0x4f7647 +#define regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_8_CTRL 0x4f7648 +#define regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_9_CTRL 0x4f7649 +#define regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_10_CTRL 0x4f764a +#define regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_11_CTRL 0x4f764b +#define regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_12_CTRL 0x4f764c +#define regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_13_CTRL 0x4f764d +#define regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_14_CTRL 0x4f764e +#define regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_ENTRY_15_CTRL 0x4f764f +#define regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3 +#define regS2A_DOORBELL_COMMON_CTRL_REG 0x4f7650 +#define regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +// base address: 0x1400000 +#define regGDC1_SHUB_REGS_IF_CTL 0x4f0ae3 +#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3 +#define regGDC1_NGDC_MGCG_CTRL 0x4f0aea +#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3 +#define regGDC1_NGDC_RESERVED_0 0x4f0aeb +#define regGDC1_NGDC_RESERVED_0_BASE_IDX 3 +#define regGDC1_NGDC_RESERVED_1 0x4f0aec +#define regGDC1_NGDC_RESERVED_1_BASE_IDX 3 +#define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x4f0aef +#define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 +#define regGDC1_ATDMA_MISC_CNTL 0x4f0afd +#define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 3 +#define regGDC1_S2A_MISC_CNTL 0x4f0aff +#define regGDC1_S2A_MISC_CNTL_BASE_IDX 3 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0b01 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3 +#define regGDC1_NGDC_PG_MISC_CTRL 0x4f0b18 +#define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 3 +#define regGDC1_NGDC_PGMST_CTRL 0x4f0b19 +#define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 3 +#define regGDC1_NGDC_PGSLV_CTRL 0x4f0b1a +#define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk +// base address: 0x1400000 +#define regGDCSOC_ERR_RSP_CNTL 0x4f5c00 +#define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3 +#define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10 +#define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20 +#define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21 +#define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22 +#define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23 +#define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24 +#define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_MISC_CTRL 0x4f5c2e +#define regGDCSOC_RAS_LEAF2_MISC_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_MISC_CTRL2 0x4f5c2f +#define regGDCSOC_RAS_LEAF2_MISC_CTRL2_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30 +#define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31 +#define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32 +#define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33 +#define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34 +#define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC +// base address: 0x1400000 +#define regSHUB_PF_FLR_RST 0x4f7800 +#define regSHUB_PF_FLR_RST_BASE_IDX 3 +#define regSHUB_GFX_DRV_VPU_RST 0x4f7801 +#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3 +#define regSHUB_LINK_RESET 0x4f7802 +#define regSHUB_LINK_RESET_BASE_IDX 3 +#define regSHUB_HARD_RST_CTRL 0x4f7810 +#define regSHUB_HARD_RST_CTRL_BASE_IDX 3 +#define regSHUB_SOFT_RST_CTRL 0x4f7811 +#define regSHUB_SOFT_RST_CTRL_BASE_IDX 3 +#define regSHUB_SDP_PORT_RST 0x4f7812 +#define regSHUB_SDP_PORT_RST_BASE_IDX 3 +#define regSHUB_RST_MISC_TRL 0x4f7813 +#define regSHUB_RST_MISC_TRL_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect +// base address: 0x1400000 +#define regHST_CLK0_SW0_CL0_CNTL 0x4f3d40 +#define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 3 +#define regHST_CLK0_SW1_CL0_CNTL 0x4f3d60 +#define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 3 + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +// base address: 0x0 +#define cfgPSWUSCFG0_1_VENDOR_ID 0x0000 +#define cfgPSWUSCFG0_1_DEVICE_ID 0x0002 +#define cfgPSWUSCFG0_1_COMMAND 0x0004 +#define cfgPSWUSCFG0_1_STATUS 0x0006 +#define cfgPSWUSCFG0_1_REVISION_ID 0x0008 +#define cfgPSWUSCFG0_1_PROG_INTERFACE 0x0009 +#define cfgPSWUSCFG0_1_SUB_CLASS 0x000a +#define cfgPSWUSCFG0_1_BASE_CLASS 0x000b +#define cfgPSWUSCFG0_1_CACHE_LINE 0x000c +#define cfgPSWUSCFG0_1_LATENCY 0x000d +#define cfgPSWUSCFG0_1_HEADER 0x000e +#define cfgPSWUSCFG0_1_BIST 0x000f +#define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgPSWUSCFG0_1_IO_BASE_LIMIT 0x001c +#define cfgPSWUSCFG0_1_SECONDARY_STATUS 0x001e +#define cfgPSWUSCFG0_1_MEM_BASE_LIMIT 0x0020 +#define cfgPSWUSCFG0_1_PREF_BASE_LIMIT 0x0024 +#define cfgPSWUSCFG0_1_PREF_BASE_UPPER 0x0028 +#define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER 0x002c +#define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI 0x0030 +#define cfgPSWUSCFG0_1_CAP_PTR 0x0034 +#define cfgPSWUSCFG0_1_ROM_BASE_ADDR 0x0038 +#define cfgPSWUSCFG0_1_INTERRUPT_LINE 0x003c +#define cfgPSWUSCFG0_1_INTERRUPT_PIN 0x003d +#define cfgPSWUSCFG0_1_VENDOR_CAP_LIST 0x0048 +#define cfgPSWUSCFG0_1_ADAPTER_ID_W 0x004c +#define cfgPSWUSCFG0_1_PMI_CAP_LIST 0x0050 +#define cfgPSWUSCFG0_1_PMI_CAP 0x0052 +#define cfgPSWUSCFG0_1_PMI_STATUS_CNTL 0x0054 +#define cfgPSWUSCFG0_1_PCIE_CAP_LIST 0x0058 +#define cfgPSWUSCFG0_1_PCIE_CAP 0x005a +#define cfgPSWUSCFG0_1_DEVICE_CAP 0x005c +#define cfgPSWUSCFG0_1_DEVICE_CNTL 0x0060 +#define cfgPSWUSCFG0_1_DEVICE_STATUS 0x0062 +#define cfgPSWUSCFG0_1_LINK_CAP 0x0064 +#define cfgPSWUSCFG0_1_LINK_CNTL 0x0068 +#define cfgPSWUSCFG0_1_LINK_STATUS 0x006a +#define cfgPSWUSCFG0_1_DEVICE_CAP2 0x007c +#define cfgPSWUSCFG0_1_DEVICE_CNTL2 0x0080 +#define cfgPSWUSCFG0_1_DEVICE_STATUS2 0x0082 +#define cfgPSWUSCFG0_1_LINK_CAP2 0x0084 +#define cfgPSWUSCFG0_1_LINK_CNTL2 0x0088 +#define cfgPSWUSCFG0_1_LINK_STATUS2 0x008a +#define cfgPSWUSCFG0_1_MSI_CAP_LIST 0x00a0 +#define cfgPSWUSCFG0_1_MSI_MSG_CNTL 0x00a2 +#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgPSWUSCFG0_1_MSI_MSG_DATA 0x00a8 +#define cfgPSWUSCFG0_1_MSI_MSG_DATA_64 0x00ac +#define cfgPSWUSCFG0_1_SSID_CAP_LIST 0x00c0 +#define cfgPSWUSCFG0_1_SSID_CAP 0x00c4 +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL 0x011c +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS 0x011e +#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG0 0x016c +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG1 0x0170 +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG2 0x0174 +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG3 0x0178 +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3 0x0274 +#define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgPSWUSCFG0_1_PCIE_ACS_CAP 0x02a4 +#define cfgPSWUSCFG0_1_PCIE_ACS_CNTL 0x02a6 +#define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgPSWUSCFG0_1_PCIE_MC_CAP 0x02f4 +#define cfgPSWUSCFG0_1_PCIE_MC_CNTL 0x02f6 +#define cfgPSWUSCFG0_1_PCIE_MC_ADDR0 0x02f8 +#define cfgPSWUSCFG0_1_PCIE_MC_ADDR1 0x02fc +#define cfgPSWUSCFG0_1_PCIE_MC_RCV0 0x0300 +#define cfgPSWUSCFG0_1_PCIE_MC_RCV1 0x0304 +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgPSWUSCFG0_1_PCIE_LTR_CAP 0x0324 +#define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgPSWUSCFG0_1_PCIE_ARI_CAP 0x032c +#define cfgPSWUSCFG0_1_PCIE_ARI_CNTL 0x032e +#define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgPSWUSCFG0_1_LINK_CAP_16GT 0x0414 +#define cfgPSWUSCFG0_1_LINK_CNTL_16GT 0x0418 +#define cfgPSWUSCFG0_1_LINK_STATUS_16GT 0x041c +#define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST 0x0440 +#define cfgPSWUSCFG0_1_MARGINING_PORT_CAP 0x0444 +#define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS 0x0446 +#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL 0x0448 +#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS 0x044a +#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL 0x044c +#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS 0x044e +#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL 0x0450 +#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS 0x0452 +#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL 0x0454 +#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS 0x0456 +#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL 0x0458 +#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS 0x045a +#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL 0x045c +#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS 0x045e +#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL 0x0460 +#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS 0x0462 +#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL 0x0464 +#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS 0x0466 +#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL 0x0468 +#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS 0x046a +#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL 0x046c +#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS 0x046e +#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL 0x0470 +#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS 0x0472 +#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL 0x0474 +#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS 0x0476 +#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL 0x0478 +#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS 0x047a +#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL 0x047c +#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS 0x047e +#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL 0x0480 +#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS 0x0482 +#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL 0x0484 +#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS 0x0486 +#define cfgPSWUSCFG0_1_LINK_CAP_32GT 0x0504 +#define cfgPSWUSCFG0_1_LINK_CNTL_32GT 0x0508 +#define cfgPSWUSCFG0_1_LINK_STATUS_32GT 0x050c + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_RC1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_RC1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_RC1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_RC1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_RC1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_RC1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_RC1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_RC1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_RC1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_RC1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_RC1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_RC1_BIST 0x000f +#define cfgBIF_CFG_DEV0_RC1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_RC1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT 0x001c +#define cfgBIF_CFG_DEV0_RC1_SECONDARY_STATUS 0x001e +#define cfgBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT 0x0020 +#define cfgBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT 0x0024 +#define cfgBIF_CFG_DEV0_RC1_PREF_BASE_UPPER 0x0028 +#define cfgBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER 0x002c +#define cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_RC1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_RC1_ROM_BASE_ADDR 0x0038 +#define cfgBIF_CFG_DEV0_RC1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_RC1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_RC1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_RC1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_RC1_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_RC1_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_RC1_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_RC1_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_RC1_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_RC1_LINK_STATUS 0x006a +#define cfgBIF_CFG_DEV0_RC1_SLOT_CAP 0x006c +#define cfgBIF_CFG_DEV0_RC1_SLOT_CNTL 0x0070 +#define cfgBIF_CFG_DEV0_RC1_SLOT_STATUS 0x0072 +#define cfgBIF_CFG_DEV0_RC1_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_RC1_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_RC1_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_RC1_LINK_STATUS2 0x008a +#define cfgBIF_CFG_DEV0_RC1_SLOT_CAP2 0x008c +#define cfgBIF_CFG_DEV0_RC1_SLOT_CNTL2 0x0090 +#define cfgBIF_CFG_DEV0_RC1_SLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_RC1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_RC1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_RC1_SSID_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_RC1_SSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_RC1_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_RC1_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_RC1_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_RC1_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_RC1_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_RC1_LINK_STATUS_32GT 0x050c + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0x032e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0x0334 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0x0338 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0x033a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0x0340 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT 0x050c + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0x032e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0x0334 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0x0338 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0x033a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0x0340 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF2_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF2_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF2_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF2_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF2_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF2_1_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF2_1_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF3_1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF3_1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF3_1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF3_1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF3_1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF3_1_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF3_1_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0x032e + + +#endif diff --git a/extra/amdpci/headers/nbio_4_3_0_sh_mask.h b/extra/amdpci/headers/nbio_4_3_0_sh_mask.h new file mode 100644 index 0000000000..d038fd9153 --- /dev/null +++ b/extra/amdpci/headers/nbio_4_3_0_sh_mask.h @@ -0,0 +1,82050 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_4_3_0_SH_MASK_HEADER +#define _nbio_4_3_0_SH_MASK_HEADER + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +//BIF_BX0_PCIE_INDEX +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA +#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX2 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA2 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX_HI +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL +//BIF_BX0_PCIE_INDEX2_HI +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL +//BIF_BX0_SBIOS_SCRATCH_0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_1 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_2 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_3 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_1 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_2 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_3 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_4 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_5 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_6 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_7 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_8 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_9 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_10 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_11 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_12 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_13 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_14 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_15 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RLC_INTR_CNTL +//BIF_BX0_BIF_VCE_INTR_CNTL +//BIF_BX0_BIF_UVD_INTR_CNTL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_CNTL +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_1 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_2 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_3 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_4 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_5 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_6 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_7 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_8 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_9 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_10 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_11 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_12 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_13 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_14 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_15 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_1 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_2 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_3 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_4 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_5 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_6 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_7 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_8 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_9 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_10 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_11 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_12 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_13 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_14 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_15 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_4 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_5 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_6 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_7 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_8 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_9 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_10 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_11 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_12 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_13 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_14 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_15 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_0_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_0_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_0_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_0_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF0_MM_INDEX +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF0_MM_DATA +#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MM_INDEX_HI +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +//BIF_BX0_CC_BIF_BX_STRAP0 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX0_CC_BIF_BX_PINSTRAP0 +//BIF_BX0_BIF_MM_INDACCESS_CNTL +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX0_BUS_CNTL +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX0_BIF_SCRATCH0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_SCRATCH1 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX0_BX_RESET_EN +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX0_MM_CFGREGS_CNTL +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX0_BX_RESET_CNTL +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX0_INTERRUPT_CNTL +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX0_INTERRUPT_CNTL2 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_CLKREQB_PAD_CNTL +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX0_BIF_FEATURES_CONTROL_MISC +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX0_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX0_BIF_DOORBELL_CNTL +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX0_BIF_DOORBELL_INT_CNTL +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX0_BIF_FB_EN +#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX0_BIF_INTR_CNTL +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX0_BIF_MST_TRANS_PENDING_VF +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_MEM_TYPE_CNTL +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX0_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_BIF_RB_CNTL +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX0_BIF_RB_BASE +#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RB_RPTR +#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR_ADDR_HI +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX0_BIF_RB_WPTR_ADDR_LO +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX0_BIF_MP1_INTR_CTRL +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_0_RCC_ERR_INT_CNTL +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_BACO_CNTL_MISC +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_0_RCC_RESET_EN +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_0_RCC_VDM_SUPPORT +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_0_RCC_GPUIOV_REGION +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_0_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_0_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_BUS_CNTL +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_0_RCC_CONFIG_CNTL +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_0_RCC_CONFIG_F0_BASE +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_0_RCC_XDMA_LO +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_XDMA_HI +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_0_RCC_BUSNUM_LIST0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_LIST1 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_HOST_BUSNUM +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_0_RCC_CMN_LINK_CNTL +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_0_RCC_MH_ARB_CNTL +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_STRAP0_RCC_BIF_STRAP0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP1 +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP2 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP3 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP4 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP5 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP0_RCC_BIF_STRAP6 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP22 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP25 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF0_BIF_BME_STATUS +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_BIF_TRANS_PENDING +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +//RCC_DEV0_EPF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +//GDC0_SHUB_REGS_IF_CTL +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//GDC0_NBIF_GFX_DOORBELL_STATUS +#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +//GDC0_ATDMA_MISC_CNTL +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL +#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC0_S2A_MISC_CNTL +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF2_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_MM_DATA +#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF3_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_MM_DATA +#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF4_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_MM_DATA +#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF5_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_MM_DATA +#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF6_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_MM_DATA +#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF7_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_MM_DATA +#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF8_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF8_MM_DATA +#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF8_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF8_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF9_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF9_MM_DATA +#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF9_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF9_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF10_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF10_MM_DATA +#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF10_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF10_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF11_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF11_MM_DATA +#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF11_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF11_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF12_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF12_MM_DATA +#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF12_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF12_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF13_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF13_MM_DATA +#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF13_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF13_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF14_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF14_MM_DATA +#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF14_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF14_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF15_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF15_MM_DATA +#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF15_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF15_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +//PSWUSCFG0_0_VENDOR_ID +#define PSWUSCFG0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define PSWUSCFG0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//PSWUSCFG0_0_DEVICE_ID +#define PSWUSCFG0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define PSWUSCFG0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//PSWUSCFG0_0_COMMAND +#define PSWUSCFG0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define PSWUSCFG0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define PSWUSCFG0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define PSWUSCFG0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define PSWUSCFG0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define PSWUSCFG0_0_COMMAND__INT_DIS__SHIFT 0xa +#define PSWUSCFG0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define PSWUSCFG0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define PSWUSCFG0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define PSWUSCFG0_0_COMMAND__SERR_EN_MASK 0x0100L +#define PSWUSCFG0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define PSWUSCFG0_0_COMMAND__INT_DIS_MASK 0x0400L +//PSWUSCFG0_0_STATUS +#define PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define PSWUSCFG0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define PSWUSCFG0_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define PSWUSCFG0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define PSWUSCFG0_0_STATUS__INT_STATUS_MASK 0x0008L +#define PSWUSCFG0_0_STATUS__CAP_LIST_MASK 0x0010L +#define PSWUSCFG0_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define PSWUSCFG0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//PSWUSCFG0_0_REVISION_ID +#define PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//PSWUSCFG0_0_PROG_INTERFACE +#define PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//PSWUSCFG0_0_SUB_CLASS +#define PSWUSCFG0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define PSWUSCFG0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//PSWUSCFG0_0_BASE_CLASS +#define PSWUSCFG0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define PSWUSCFG0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//PSWUSCFG0_0_CACHE_LINE +#define PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//PSWUSCFG0_0_LATENCY +#define PSWUSCFG0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define PSWUSCFG0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//PSWUSCFG0_0_HEADER +#define PSWUSCFG0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define PSWUSCFG0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define PSWUSCFG0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define PSWUSCFG0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//PSWUSCFG0_0_BIST +#define PSWUSCFG0_0_BIST__BIST_COMP__SHIFT 0x0 +#define PSWUSCFG0_0_BIST__BIST_STRT__SHIFT 0x6 +#define PSWUSCFG0_0_BIST__BIST_CAP__SHIFT 0x7 +#define PSWUSCFG0_0_BIST__BIST_COMP_MASK 0x0FL +#define PSWUSCFG0_0_BIST__BIST_STRT_MASK 0x40L +#define PSWUSCFG0_0_BIST__BIST_CAP_MASK 0x80L +//PSWUSCFG0_0_BASE_ADDR_1 +#define PSWUSCFG0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define PSWUSCFG0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_BASE_ADDR_2 +#define PSWUSCFG0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define PSWUSCFG0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//PSWUSCFG0_0_IO_BASE_LIMIT +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//PSWUSCFG0_0_SECONDARY_STATUS +#define PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//PSWUSCFG0_0_MEM_BASE_LIMIT +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//PSWUSCFG0_0_PREF_BASE_LIMIT +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//PSWUSCFG0_0_PREF_BASE_UPPER +#define PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PREF_LIMIT_UPPER +#define PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_IO_BASE_LIMIT_HI +#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//PSWUSCFG0_0_CAP_PTR +#define PSWUSCFG0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define PSWUSCFG0_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//PSWUSCFG0_0_ROM_BASE_ADDR +#define PSWUSCFG0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define PSWUSCFG0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//PSWUSCFG0_0_INTERRUPT_LINE +#define PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//PSWUSCFG0_0_INTERRUPT_PIN +#define PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//PSWUSCFG0_0_VENDOR_CAP_LIST +#define PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//PSWUSCFG0_0_ADAPTER_ID_W +#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//PSWUSCFG0_0_PMI_CAP_LIST +#define PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_0_PMI_CAP +#define PSWUSCFG0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define PSWUSCFG0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define PSWUSCFG0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define PSWUSCFG0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define PSWUSCFG0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define PSWUSCFG0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define PSWUSCFG0_0_PMI_CAP__VERSION_MASK 0x0007L +#define PSWUSCFG0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define PSWUSCFG0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define PSWUSCFG0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define PSWUSCFG0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define PSWUSCFG0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//PSWUSCFG0_0_PMI_STATUS_CNTL +#define PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//PSWUSCFG0_0_PCIE_CAP_LIST +#define PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_0_PCIE_CAP +#define PSWUSCFG0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define PSWUSCFG0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//PSWUSCFG0_0_DEVICE_CAP +#define PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define PSWUSCFG0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define PSWUSCFG0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//PSWUSCFG0_0_DEVICE_CNTL +#define PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//PSWUSCFG0_0_DEVICE_STATUS +#define PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define PSWUSCFG0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define PSWUSCFG0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//PSWUSCFG0_0_LINK_CAP +#define PSWUSCFG0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define PSWUSCFG0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define PSWUSCFG0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define PSWUSCFG0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define PSWUSCFG0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define PSWUSCFG0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define PSWUSCFG0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//PSWUSCFG0_0_LINK_CNTL +#define PSWUSCFG0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define PSWUSCFG0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define PSWUSCFG0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define PSWUSCFG0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define PSWUSCFG0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//PSWUSCFG0_0_LINK_STATUS +#define PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//PSWUSCFG0_0_DEVICE_CAP2 +#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//PSWUSCFG0_0_DEVICE_CNTL2 +#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//PSWUSCFG0_0_DEVICE_STATUS2 +#define PSWUSCFG0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define PSWUSCFG0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//PSWUSCFG0_0_LINK_CAP2 +#define PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//PSWUSCFG0_0_LINK_CNTL2 +#define PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//PSWUSCFG0_0_LINK_STATUS2 +#define PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//PSWUSCFG0_0_MSI_CAP_LIST +#define PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_0_MSI_MSG_CNTL +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//PSWUSCFG0_0_MSI_MSG_ADDR_LO +#define PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PSWUSCFG0_0_MSI_MSG_ADDR_HI +#define PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_MSI_MSG_DATA +#define PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define PSWUSCFG0_0_MSI_MSG_DATA__MSI_EXT_DATA__SHIFT 0x10 +#define PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +#define PSWUSCFG0_0_MSI_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFF0000L +//PSWUSCFG0_0_MSI_MSG_DATA_64 +#define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x10 +#define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +#define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFF0000L +//PSWUSCFG0_0_SSID_CAP_LIST +#define PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_0_SSID_CAP +#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PSWUSCFG0_0_PCIE_PORT_VC_CNTL +#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//PSWUSCFG0_0_PCIE_PORT_VC_STATUS +#define PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//PSWUSCFG0_0_PCIE_CORR_ERR_STATUS +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//PSWUSCFG0_0_PCIE_CORR_ERR_MASK +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//PSWUSCFG0_0_PCIE_HDR_LOG0 +#define PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_HDR_LOG1 +#define PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_HDR_LOG2 +#define PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_HDR_LOG3 +#define PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_LINK_CNTL3 +#define PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS +#define PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_ACS_CAP +#define PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define PSWUSCFG0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define PSWUSCFG0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//PSWUSCFG0_0_PCIE_ACS_CNTL +#define PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define PSWUSCFG0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define PSWUSCFG0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_MC_CAP +#define PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//PSWUSCFG0_0_PCIE_MC_CNTL +#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//PSWUSCFG0_0_PCIE_MC_ADDR0 +#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//PSWUSCFG0_0_PCIE_MC_ADDR1 +#define PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_MC_RCV0 +#define PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_MC_RCV1 +#define PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_LTR_CAP +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_PCIE_ARI_CAP +#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//PSWUSCFG0_0_PCIE_ARI_CNTL +#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_DATA_LINK_FEATURE_CAP +#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1 +#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L +#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL +#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS +#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_LINK_CAP_16GT +#define PSWUSCFG0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_LINK_CNTL_16GT +#define PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//PSWUSCFG0_0_LINK_STATUS_16GT +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_MARGINING_PORT_CAP +#define PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//PSWUSCFG0_0_MARGINING_PORT_STATUS +#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST +#define PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_0_LINK_CAP_32GT +#define PSWUSCFG0_0_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED__SHIFT 0x1 +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED__SHIFT 0x8 +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED__SHIFT 0x9 +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED__SHIFT 0xa +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define PSWUSCFG0_0_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define PSWUSCFG0_0_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED_MASK 0x00000002L +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED_MASK 0x00000100L +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED_MASK 0x00000200L +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED_MASK 0x00000400L +#define PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//PSWUSCFG0_0_LINK_CNTL_32GT +#define PSWUSCFG0_0_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE__SHIFT 0x1 +#define PSWUSCFG0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED__SHIFT 0x8 +#define PSWUSCFG0_0_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE_MASK 0x00000001L +#define PSWUSCFG0_0_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE_MASK 0x00000002L +#define PSWUSCFG0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED_MASK 0x00000700L +//PSWUSCFG0_0_LINK_STATUS_32GT +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define PSWUSCFG0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define PSWUSCFG0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define PSWUSCFG0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL__SHIFT 0x6 +#define PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define PSWUSCFG0_0_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED__SHIFT 0xa +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define PSWUSCFG0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define PSWUSCFG0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define PSWUSCFG0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL_MASK 0x000000C0L +#define PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define PSWUSCFG0_0_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED_MASK 0x00000400L +//PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC0_VENDOR_ID +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_DEVICE_ID +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_COMMAND +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC0_STATUS +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_REVISION_ID +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PROG_INTERFACE +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_SUB_CLASS +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_BASE_CLASS +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_CACHE_LINE +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_LATENCY +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC0_HEADER +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC0_BIST +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC0_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC0_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_CAP_PTR +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC0_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC0_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PMI_CAP +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC0_DEVICE_CAP +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC0_LINK_CAP +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC0_LINK_STATUS +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC0_SLOT_CNTL +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC0_SLOT_STATUS +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC0_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_LINK_CAP2 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC0_LINK_STATUS2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC0_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_SSID_CAP +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_AP_CAP +#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_RC0_AP_CNTL +#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_RC0_AP_DATA1 +#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_AP_DATA2 +#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_RTR_DATA1 +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_RC0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_RTR_DATA2 +#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_COMMAND +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_LATENCY +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_HEADER +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BIST +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_AP_CAP +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_0_AP_CNTL +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_0_AP_DATA1 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_AP_DATA2 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_COMMAND +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_0_STATUS +#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_REVISION_ID +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_LATENCY +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_HEADER +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BIST +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_0_CAP_PTR +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_0_LINK_CAP +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +//BIF_CFG_DEV0_EPF2_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_COMMAND +#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_0_STATUS +#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_REVISION_ID +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_LATENCY +#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_HEADER +#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF2_0_BIST +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF2_0_CAP_PTR +#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PMI_CAP +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_SBRN +#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_FLADJ +#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL +#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF2_0_LINK_CAP +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF2_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF2_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MASK +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +//BIF_CFG_DEV0_EPF3_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_COMMAND +#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_0_STATUS +#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_REVISION_ID +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_LATENCY +#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_HEADER +#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF3_0_BIST +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF3_0_CAP_PTR +#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PMI_CAP +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_SBRN +#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_FLADJ +#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL +#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF3_0_LINK_CAP +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF3_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF3_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MASK +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +//PCIE_INDEX +#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//PCIE_DATA +#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//PCIE_INDEX2 +#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//PCIE_DATA2 +#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//PCIE_INDEX_HI +#define PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL +//PCIE_INDEX2_HI +#define PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL +//SBIOS_SCRATCH_0 +#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_1 +#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_2 +#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_3 +#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_0 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_1 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_2 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_3 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_4 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_5 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_6 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_7 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_8 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_9 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_10 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_11 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_12 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_13 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_14 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_15 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_RLC_INTR_CNTL +//BIF_VCE_INTR_CNTL +//BIF_UVD_INTR_CNTL +//BIF_EngineA_INTR_CNTL +#define BIF_EngineA_INTR_CNTL__EngineA_CMD_COMPLETE__SHIFT 0x0 +#define BIF_EngineA_INTR_CNTL__EngineA_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_EngineA_INTR_CNTL__EngineA_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_EngineA_INTR_CNTL__EngineA_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_EngineA_INTR_CNTL__EngineA_INST_SEL__SHIFT 0x1c +#define BIF_EngineA_INTR_CNTL__EngineA_CMD_COMPLETE_MASK 0x00000001L +#define BIF_EngineA_INTR_CNTL__EngineA_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_EngineA_INTR_CNTL__EngineA_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_EngineA_INTR_CNTL__EngineA_VM_BUSY_TRANSITION_MASK 0x00000008L +#define BIF_EngineA_INTR_CNTL__EngineA_INST_SEL_MASK 0xF0000000L +//BIF_EngineB_INTR_CNTL +#define BIF_EngineB_INTR_CNTL__EngineB_CMD_COMPLETE__SHIFT 0x0 +#define BIF_EngineB_INTR_CNTL__EngineB_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_EngineB_INTR_CNTL__EngineB_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_EngineB_INTR_CNTL__EngineB_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_EngineB_INTR_CNTL__EngineB_INST_SEL__SHIFT 0x1c +#define BIF_EngineB_INTR_CNTL__EngineB_CMD_COMPLETE_MASK 0x00000001L +#define BIF_EngineB_INTR_CNTL__EngineB_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_EngineB_INTR_CNTL__EngineB_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_EngineB_INTR_CNTL__EngineB_VM_BUSY_TRANSITION_MASK 0x00000008L +#define BIF_EngineB_INTR_CNTL__EngineB_INST_SEL_MASK 0xF0000000L +//GFX_MMIOREG_CAM_ADDR0 +#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR0 +#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR1 +#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR1 +#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR2 +#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR2 +#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR3 +#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR3 +#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR4 +#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR4 +#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR5 +#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR5 +#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR6 +#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR6 +#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR7 +#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR7 +#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_CNTL +#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//GFX_MMIOREG_CAM_ZERO_CPL +#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//GFX_MMIOREG_CAM_ONE_CPL +#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_0 +#define DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_1 +#define DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_2 +#define DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_3 +#define DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_4 +#define DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_5 +#define DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_6 +#define DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_7 +#define DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_8 +#define DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_9 +#define DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_10 +#define DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_11 +#define DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_12 +#define DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_13 +#define DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_14 +#define DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//DRIVER_SCRATCH_15 +#define DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//FW_SCRATCH_0 +#define FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//FW_SCRATCH_1 +#define FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//FW_SCRATCH_2 +#define FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//FW_SCRATCH_3 +#define FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//FW_SCRATCH_4 +#define FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//FW_SCRATCH_5 +#define FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//FW_SCRATCH_6 +#define FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//FW_SCRATCH_7 +#define FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//FW_SCRATCH_8 +#define FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//FW_SCRATCH_9 +#define FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//FW_SCRATCH_10 +#define FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//FW_SCRATCH_11 +#define FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//FW_SCRATCH_12 +#define FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//FW_SCRATCH_13 +#define FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//FW_SCRATCH_14 +#define FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//FW_SCRATCH_15 +#define FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_4 +#define SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_5 +#define SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_6 +#define SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_7 +#define SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_8 +#define SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_9 +#define SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_10 +#define SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_11 +#define SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_12 +#define SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_13 +#define SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_14 +#define SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_15 +#define SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//DN_PCIE_RESERVED +#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//DN_PCIE_SCRATCH +#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//DN_PCIE_CNTL +#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//DN_PCIE_CONFIG_CNTL +#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//DN_PCIE_RX_CNTL2 +#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//DN_PCIE_BUS_CNTL +#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//DN_PCIE_CFG_CNTL +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//DN_PCIE_STRAP_F0 +#define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//DN_PCIE_STRAP_MISC +#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//DN_PCIE_STRAP_MISC2 +#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//PCIE_ERR_CNTL +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//PCIE_RX_CNTL +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//PCIE_LC_SPEED_CNTL +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//PCIE_LC_CNTL2 +#define PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//PCIEP_STRAP_MISC +#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//LTR_MSG_INFO_FROM_EP +#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//EP_PCIE_SCRATCH +#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//EP_PCIE_CNTL +#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//EP_PCIE_INT_CNTL +#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//EP_PCIE_INT_STATUS +#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//EP_PCIE_RX_CNTL2 +#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//EP_PCIE_BUS_CNTL +#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//EP_PCIE_CFG_CNTL +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//EP_PCIE_TX_LTR_CNTL +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//EP_PCIE_STRAP_MISC +#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//EP_PCIE_STRAP_MISC2 +#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//EP_PCIE_F0_DPA_CAP +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//EP_PCIE_F0_DPA_CNTL +#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//EP_PCIE_PME_CONTROL +#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//EP_PCIEP_RESERVED +#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//EP_PCIE_TX_CNTL +#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//EP_PCIE_TX_REQUESTER_ID +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//EP_PCIE_ERR_CNTL +#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//EP_PCIE_RX_CNTL +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//EP_PCIE_LC_SPEED_CNTL +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//DVSEC_PRIV_CNTL +#define DVSEC_PRIV_CNTL__DVSEC_PRIV_REG__SHIFT 0x0 +#define DVSEC_PRIV_CNTL__DVSEC_PRIV_REG_MASK 0xFFFFFFFFL +//DVSEC_PRIV_CNTL2 +#define DVSEC_PRIV_CNTL2__DVSEC_PRIV_REG2__SHIFT 0x0 +#define DVSEC_PRIV_CNTL2__DVSEC_PRIV_REG2_MASK 0xFFFFFFFFL +//DVSEC_VF_PRIV_CNTL +#define DVSEC_VF_PRIV_CNTL__DVSEC_VF_PRIV_REG__SHIFT 0x0 +#define DVSEC_VF_PRIV_CNTL__DVSEC_VF_PRIV_REG_MASK 0xFFFFFFFFL +//DVSEC_VF_PRIV_CNTL2 +#define DVSEC_VF_PRIV_CNTL2__DVSEC_VF_PRIV_REG2__SHIFT 0x0 +#define DVSEC_VF_PRIV_CNTL2__DVSEC_VF_PRIV_REG2_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +//CC_BIF_BX_STRAP0 +#define CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//CC_BIF_BX_PINSTRAP0 +//BIF_MM_INDACCESS_CNTL +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BUS_CNTL +#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_SCRATCH0 +#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_SCRATCH1 +#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BX_RESET_EN +#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//MM_CFGREGS_CNTL +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BX_RESET_CNTL +#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//INTERRUPT_CNTL +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//INTERRUPT_CNTL2 +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//CLKREQB_PAD_CNTL +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_FEATURES_CONTROL_MISC +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//HDP_ATOMIC_CONTROL_MISC +#define HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_DOORBELL_CNTL +#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_DOORBELL_INT_CNTL +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_FB_EN +#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_INTR_CNTL +#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_MST_TRANS_PENDING_VF +#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_SLV_TRANS_PENDING_VF +#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BACO_CNTL +#define BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BACO_EXIT_TIME0 +#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BACO_EXIT_TIMER1 +#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BACO_EXIT_TIMER2 +#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BACO_EXIT_TIMER3 +#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BACO_EXIT_TIMER4 +#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//MEM_TYPE_CNTL +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//NBIF_GFX_ADDR_LUT_CNTL +#define NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//NBIF_GFX_ADDR_LUT_0 +#define NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_1 +#define NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_2 +#define NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_3 +#define NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_4 +#define NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_5 +#define NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_6 +#define NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_7 +#define NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_8 +#define NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_9 +#define NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_10 +#define NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_11 +#define NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_12 +#define NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_13 +#define NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_14 +#define NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//NBIF_GFX_ADDR_LUT_15 +#define NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//VF_REGWR_EN +#define VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//VF_DOORBELL_EN +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//VF_FB_EN +#define VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//VF_REGWR_STATUS +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//VF_DOORBELL_STATUS +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//VF_FB_STATUS +#define VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//GFX_RST_CNTL +#define GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +//REMAP_HDP_MEM_FLUSH_CNTL +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//REMAP_HDP_REG_FLUSH_CNTL +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_RB_CNTL +#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_RB_BASE +#define BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_RB_RPTR +#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_RB_WPTR +#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_RB_WPTR_ADDR_HI +#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_RB_WPTR_ADDR_LO +#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//MAILBOX_INDEX +#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BACO_AZ_ENHANCE_CTRL +#define BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT 0x2 +#define BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT 0x10 +#define BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT 0x11 +#define BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT 0x1f +#define BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK 0x00003FFCL +#define BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK 0x00010000L +#define BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK 0x00020000L +#define BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK 0x80000000L +//BIF_MP1_INTR_CTRL +#define BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_VCN0_GPUIOV_CFG_SIZE +#define BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_VCN1_GPUIOV_CFG_SIZE +#define BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_GFX_SDMA_GPUIOV_CFG_SIZE +#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_PERSTB_PAD_CNTL +#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_PX_EN_PAD_CNTL +#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_REFPADKIN_PAD_CNTL +#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_CLKREQB_PAD_CNTL +#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_PWRBRK_PAD_CNTL +#define BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_WAKEB_PAD_CNTL +#define BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT 0x0 +#define BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT 0x1 +#define BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT 0x2 +#define BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT 0x3 +#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT 0x4 +#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT 0x5 +#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT 0x6 +#define BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT 0x7 +#define BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK 0x00000001L +#define BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK 0x00000002L +#define BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK 0x00000004L +#define BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK 0x00000008L +#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK 0x00000010L +#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK 0x00000020L +#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK 0x00000040L +#define BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK 0x00000080L +//BIF_VAUX_PRESENT_PAD_CNTL +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT 0x0 +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT 0x1 +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT 0x2 +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT 0x3 +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT 0x4 +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT 0x5 +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK 0x00000001L +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK 0x00000002L +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK 0x00000004L +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK 0x00000008L +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK 0x00000010L +#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK 0x00000020L +//PCIE_PAR_SAVE_RESTORE_CNTL +#define PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT 0x0 +#define PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT 0x1 +#define PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK 0x00000001L +#define PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK 0xFFFFFFFEL +//BIF_S5_MEM_POWER_CTRL0 +#define BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT 0x0 +#define BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK 0xFFFFFFFFL +//BIF_S5_MEM_POWER_CTRL1 +#define BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT 0x0 +#define BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT 0xa +#define BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK 0x000003FFL +#define BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK 0x00000400L +//BIF_S5_DUMMY_REGS +#define BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT 0x0 +#define BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK 0xFFFFFFFFL +//GPIO_CNTL_0_REG +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iTXIMPSEL__SHIFT 0x0 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iCTFEN__SHIFT 0x1 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iPD__SHIFT 0x2 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iPU__SHIFT 0x3 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXEN__SHIFT 0x4 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL0__SHIFT 0x5 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL1__SHIFT 0x6 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_Reserved__SHIFT 0x7 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iA__SHIFT 0x8 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iOE__SHIFT 0x9 +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_Y__SHIFT 0xa +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iTXIMPSEL_MASK 0x00000001L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iCTFEN_MASK 0x00000002L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iPD_MASK 0x00000004L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iPU_MASK 0x00000008L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXEN_MASK 0x00000010L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL0_MASK 0x00000020L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL1_MASK 0x00000040L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_Reserved_MASK 0x00000080L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iA_MASK 0x00000100L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_iOE_MASK 0x00000200L +#define GPIO_CNTL_0_REG__GPIO_CNTL_0_Y_MASK 0x00000400L +//GPIO_CNTL_1_REG +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iTXIMPSEL__SHIFT 0x0 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iCTFEN__SHIFT 0x1 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iPD__SHIFT 0x2 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iPU__SHIFT 0x3 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXEN__SHIFT 0x4 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL0__SHIFT 0x5 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL1__SHIFT 0x6 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_Reserved__SHIFT 0x7 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iA__SHIFT 0x8 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iOE__SHIFT 0x9 +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_Y__SHIFT 0xa +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iTXIMPSEL_MASK 0x00000001L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iCTFEN_MASK 0x00000002L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iPD_MASK 0x00000004L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iPU_MASK 0x00000008L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXEN_MASK 0x00000010L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL0_MASK 0x00000020L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL1_MASK 0x00000040L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_Reserved_MASK 0x00000080L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iA_MASK 0x00000100L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_iOE_MASK 0x00000200L +#define GPIO_CNTL_1_REG__GPIO_CNTL_1_Y_MASK 0x00000400L +//GPIO_CNTL_2_REG +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iTXIMPSEL__SHIFT 0x0 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iCTFEN__SHIFT 0x1 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iPD__SHIFT 0x2 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iPU__SHIFT 0x3 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXEN__SHIFT 0x4 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL0__SHIFT 0x5 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL1__SHIFT 0x6 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_Reserved__SHIFT 0x7 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iA__SHIFT 0x8 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iOE__SHIFT 0x9 +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_Y__SHIFT 0xa +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iTXIMPSEL_MASK 0x00000001L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iCTFEN_MASK 0x00000002L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iPD_MASK 0x00000004L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iPU_MASK 0x00000008L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXEN_MASK 0x00000010L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL0_MASK 0x00000020L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL1_MASK 0x00000040L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_Reserved_MASK 0x00000080L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iA_MASK 0x00000100L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_iOE_MASK 0x00000200L +#define GPIO_CNTL_2_REG__GPIO_CNTL_2_Y_MASK 0x00000400L +//GPIO_CNTL_3_REG +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iTXIMPSEL__SHIFT 0x0 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iCTFEN__SHIFT 0x1 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iPD__SHIFT 0x2 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iPU__SHIFT 0x3 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXEN__SHIFT 0x4 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL0__SHIFT 0x5 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL1__SHIFT 0x6 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_Reserved__SHIFT 0x7 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iA__SHIFT 0x8 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iOE__SHIFT 0x9 +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_Y__SHIFT 0xa +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iTXIMPSEL_MASK 0x00000001L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iCTFEN_MASK 0x00000002L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iPD_MASK 0x00000004L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iPU_MASK 0x00000008L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXEN_MASK 0x00000010L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL0_MASK 0x00000020L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL1_MASK 0x00000040L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_Reserved_MASK 0x00000080L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iA_MASK 0x00000100L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_iOE_MASK 0x00000200L +#define GPIO_CNTL_3_REG__GPIO_CNTL_3_Y_MASK 0x00000400L +//GPIO_CNTL_4_REG +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iTXIMPSEL__SHIFT 0x0 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iCTFEN__SHIFT 0x1 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iPD__SHIFT 0x2 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iPU__SHIFT 0x3 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXEN__SHIFT 0x4 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL0__SHIFT 0x5 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL1__SHIFT 0x6 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_Reserved__SHIFT 0x7 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iA__SHIFT 0x8 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iOE__SHIFT 0x9 +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_Y__SHIFT 0xa +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iTXIMPSEL_MASK 0x00000001L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iCTFEN_MASK 0x00000002L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iPD_MASK 0x00000004L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iPU_MASK 0x00000008L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXEN_MASK 0x00000010L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL0_MASK 0x00000020L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL1_MASK 0x00000040L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_Reserved_MASK 0x00000080L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iA_MASK 0x00000100L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_iOE_MASK 0x00000200L +#define GPIO_CNTL_4_REG__GPIO_CNTL_4_Y_MASK 0x00000400L +//CLDO_075_S5_CTRL +#define CLDO_075_S5_CTRL__SPARE__SHIFT 0x0 +#define CLDO_075_S5_CTRL__LDO_VOLTAGE_OUT__SHIFT 0x3 +#define CLDO_075_S5_CTRL__SELECTS0__SHIFT 0x6 +#define CLDO_075_S5_CTRL__CONFIG_EN__SHIFT 0x7 +#define CLDO_075_S5_CTRL__SPARE_MASK 0x00000007L +#define CLDO_075_S5_CTRL__LDO_VOLTAGE_OUT_MASK 0x00000038L +#define CLDO_075_S5_CTRL__SELECTS0_MASK 0x00000040L +#define CLDO_075_S5_CTRL__CONFIG_EN_MASK 0x00000080L +//CLDO_12_PCIE_CTRL +#define CLDO_12_PCIE_CTRL__SPARE__SHIFT 0x0 +#define CLDO_12_PCIE_CTRL__LDO_VOLTAGE_OUT__SHIFT 0x3 +#define CLDO_12_PCIE_CTRL__SELECTS0__SHIFT 0x6 +#define CLDO_12_PCIE_CTRL__CONFIG_EN__SHIFT 0x7 +#define CLDO_12_PCIE_CTRL__SPARE_MASK 0x00000007L +#define CLDO_12_PCIE_CTRL__LDO_VOLTAGE_OUT_MASK 0x00000038L +#define CLDO_12_PCIE_CTRL__SELECTS0_MASK 0x00000040L +#define CLDO_12_PCIE_CTRL__CONFIG_EN_MASK 0x00000080L +//SMNCLK_SEL +#define SMNCLK_SEL__S5_SMN_CLK_SEL__SHIFT 0x0 +#define SMNCLK_SEL__S5_SMN_CLK_SEL_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_ERR_INT_CNTL +#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_BACO_CNTL_MISC +#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_RESET_EN +#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_VDM_SUPPORT +#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_MARGIN_PARAM_CNTL0 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_MARGIN_PARAM_CNTL1 +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_GPUIOV_REGION +#define RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_GPU_HOSTVM_EN +#define RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_PEER_REG_RANGE0 +#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_PEER_REG_RANGE1 +#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_BUS_CNTL +#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_CONFIG_CNTL +#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_CONFIG_F0_BASE +#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_CONFIG_APER_SIZE +#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_CONFIG_REG_APER_SIZE +#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_XDMA_LO +#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_XDMA_HI +#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_FEATURES_CONTROL_MISC +#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_BUSNUM_CNTL1 +#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_BUSNUM_LIST0 +#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_BUSNUM_LIST1 +#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_BUSNUM_CNTL2 +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_CAPTURE_HOST_BUSNUM +#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_HOST_BUSNUM +#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_PEER0_FB_OFFSET_HI +#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER0_FB_OFFSET_LO +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_PEER1_FB_OFFSET_HI +#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER1_FB_OFFSET_LO +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_PEER2_FB_OFFSET_HI +#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER2_FB_OFFSET_LO +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_PEER3_FB_OFFSET_HI +#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER3_FB_OFFSET_LO +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEVFUNCNUM_LIST0 +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEVFUNCNUM_LIST1 +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_LINK_CNTL +#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_CMN_LINK_CNTL +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_EP_REQUESTERID_RESTORE +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_LTR_LSWITCH_CNTL +#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_MH_ARB_CNTL +#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_BIF_STRAP0 +#define RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_BIF_STRAP1 +#define RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_BIF_STRAP2 +#define RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_BIF_STRAP3 +#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_BIF_STRAP4 +#define RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_BIF_STRAP5 +#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_BIF_STRAP6 +#define RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_DEV0_PORT_STRAP0 +#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_DEV0_PORT_STRAP1 +#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_DEV0_PORT_STRAP10 +#define RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_DEV0_PORT_STRAP11 +#define RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_DEV0_PORT_STRAP12 +#define RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_DEV0_PORT_STRAP13 +#define RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_DEV0_PORT_STRAP14 +#define RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_DEV0_PORT_STRAP2 +#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_DEV0_PORT_STRAP3 +#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_DEV0_PORT_STRAP4 +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_DEV0_PORT_STRAP5 +#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_DEV0_PORT_STRAP6 +#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_DEV0_PORT_STRAP7 +#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_DEV0_PORT_STRAP8 +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_DEV0_PORT_STRAP9 +#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_DEV0_EPF0_STRAP0 +#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_DEV0_EPF0_STRAP1 +#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_DEV0_EPF0_STRAP13 +#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_DEV0_EPF0_STRAP14 +#define RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_DEV0_EPF0_STRAP15 +#define RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_DEV0_EPF0_STRAP16 +#define RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_DEV0_EPF0_STRAP17 +#define RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_DEV0_EPF0_STRAP18 +#define RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_DEV0_EPF0_STRAP2 +#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_DEV0_EPF0_STRAP26 +#define RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_DEV0_EPF0_STRAP3 +#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_DEV0_EPF0_STRAP4 +#define RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_DEV0_EPF0_STRAP5 +#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_DEV0_EPF0_STRAP8 +#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_DEV0_EPF0_STRAP9 +#define RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_DEV0_EPF1_STRAP0 +#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_DEV0_EPF1_STRAP1 +//RCC_DEV0_EPF1_STRAP10 +//RCC_DEV0_EPF1_STRAP11 +//RCC_DEV0_EPF1_STRAP12 +//RCC_DEV0_EPF1_STRAP13 +#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL +#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L +#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L +//RCC_DEV0_EPF1_STRAP14 +#define RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL +//RCC_DEV0_EPF1_STRAP15 +#define RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT 0xc +#define RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT 0x18 +#define RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK 0x00FFF000L +#define RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK 0x01000000L +//RCC_DEV0_EPF1_STRAP16 +#define RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT 0xc +#define RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK 0x00FFF000L +//RCC_DEV0_EPF1_STRAP17 +#define RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT 0xc +#define RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT 0xd +#define RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK 0x00001000L +#define RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK 0x01FFE000L +//RCC_DEV0_EPF1_STRAP18 +#define RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK 0x00000FFFL +//RCC_DEV0_EPF1_STRAP19 +//RCC_DEV0_EPF1_STRAP2 +#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 +#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 +#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_DEV0_EPF1_STRAP20 +//RCC_DEV0_EPF1_STRAP21 +//RCC_DEV0_EPF1_STRAP22 +//RCC_DEV0_EPF1_STRAP23 +//RCC_DEV0_EPF1_STRAP24 +//RCC_DEV0_EPF1_STRAP25 +//RCC_DEV0_EPF1_STRAP3 +#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_DEV0_EPF1_STRAP4 +#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +//RCC_DEV0_EPF1_STRAP5 +#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_DEV0_EPF1_STRAP6 +#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +//RCC_DEV0_EPF1_STRAP7 +//RCC_DEV0_EPF1_STRAP8 +//RCC_DEV0_EPF1_STRAP9 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF_BIF_BME_STATUS +#define BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF_BIF_TRANS_PENDING +#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF_MAILBOX_CONTROL +#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF_MAILBOX_INT_CNTL +#define BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF_BIF_VMHV_MAILBOX +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +//SHUB_REGS_IF_CTL +#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//NGDC_MGCG_CTRL +#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +//NGDC_RESERVED_0 +#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//NGDC_RESERVED_1 +#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//NBIF_GFX_DOORBELL_STATUS +#define NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +//ATDMA_MISC_CNTL +#define ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 +#define ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 +#define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL +#define ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L +#define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//S2A_MISC_CNTL +#define S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//NGDC_EARLY_WAKEUP_CTRL +#define NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//NGDC_MCA_SMN_CTRL0 +#define NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT 0x0 +#define NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK 0x00000001L +//NGDC_PG_MISC_CTRL +#define NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa +#define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd +#define NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe +#define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10 +#define NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L +#define NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L +#define NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//NGDC_PGMST_CTRL +#define NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8 +#define NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L +#define NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//NGDC_PGSLV_CTRL +#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa +#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L + + +// addressBlock: nbio_nbif0_bif_swus_SUMDEC +//SUM_INDEX +#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 +#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL +//SUM_DATA +#define SUM_DATA__SUM_DATA__SHIFT 0x0 +#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL +//SUM_INDEX_HI +#define SUM_INDEX_HI__SUM_INDEX_HI__SHIFT 0x0 +#define SUM_INDEX_HI__SUM_INDEX_HI_MASK 0x000000FFL + + +// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec +//SHADOW_COMMAND +#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 +#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 +#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L +#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L +//SHADOW_BASE_ADDR_1 +#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL +//SHADOW_BASE_ADDR_2 +#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL +//SHADOW_SUB_BUS_NUMBER_LATENCY +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L +//SHADOW_IO_BASE_LIMIT +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L +//SHADOW_MEM_BASE_LIMIT +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_LIMIT +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_UPPER +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_PREF_LIMIT_UPPER +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_IO_BASE_LIMIT_HI +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L +//SUC_INDEX +#define SUC_INDEX__SUC_INDEX__SHIFT 0x0 +#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL +//SUC_DATA +#define SUC_DATA__SUC_DATA__SHIFT 0x0 +#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 +//BIF_BX_PF1_MM_INDEX +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF1_MM_DATA +#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MM_INDEX_HI +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_0_BIST +#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_0_BIST +#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_0_BIST +#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_0_BIST +#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_0_BIST +#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_0_BIST +#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_0_BIST +#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_0_BIST +#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF8_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF8_0_BIST +#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF9_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF9_0_BIST +#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF10_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF10_0_BIST +#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF11_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF11_0_BIST +#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF12_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF12_0_BIST +#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF13_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF13_0_BIST +#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF14_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF14_0_BIST +#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF15_0_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_HEADER +#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF15_0_BIST +#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + + + +// addressBlock: nbio_pcie0_pswusp0_pciedir_p +//PCIEP_RESERVED +#define PCIEP_RESERVED__RESERVED__SHIFT 0x0 +#define PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL +//PCIEP_SCRATCH +#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//PCIEP_PORT_CNTL +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L +//PCIE_TX_REQUESTER_ID +#define PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_FUNCTION__SHIFT 0x10 +#define PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_DEVICE__SHIFT 0x13 +#define PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_BUS__SHIFT 0x18 +#define PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_FUNCTION_MASK 0x00070000L +#define PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_DEVICE_MASK 0x00F80000L +#define PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_BUS_MASK 0xFF000000L +//PCIE_P_PORT_LANE_STATUS +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//PSWUSP0_PCIE_ERR_CNTL +#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_POIS_TLP__SHIFT 0x6 +#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd +#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13 +#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14 +#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_POIS_TLP_MASK 0x00000040L +#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x00001000L +#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x00002000L +#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L +#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L +//PSWUSP0_PCIE_RX_CNTL +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_L23_MODE__SHIFT 0xf +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c +#define PSWUSP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d +#define PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_ON_SURPDN_EN__SHIFT 0x1e +#define PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_3_EN__SHIFT 0x1f +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_L23_MODE_MASK 0x00008000L +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +#define PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L +#define PSWUSP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L +#define PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_ON_SURPDN_EN_MASK 0x40000000L +#define PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_3_EN_MASK 0x80000000L +//PCIE_RX_EXPECTED_SEQNUM +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//PCIE_RX_VENDOR_SPECIFIC +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//PCIE_RX_CNTL3 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define PCIE_RX_CNTL3__RX_ENH_ATOMIC_EN__SHIFT 0x8 +#define PCIE_RX_CNTL3__RX_INGRESS_POISONED_BLOCKING_EN__SHIFT 0x9 +#define PCIE_RX_CNTL3__RX_SWAP_RTRC_TO_BFRC_HDR_ONLY_ENABLE__SHIFT 0xa +#define PCIE_RX_CNTL3__RX_PRIV_POISON_EGRESS_BLOCK_EN__SHIFT 0xb +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +#define PCIE_RX_CNTL3__RX_ENH_ATOMIC_EN_MASK 0x00000100L +#define PCIE_RX_CNTL3__RX_INGRESS_POISONED_BLOCKING_EN_MASK 0x00000200L +#define PCIE_RX_CNTL3__RX_SWAP_RTRC_TO_BFRC_HDR_ONLY_ENABLE_MASK 0x00000400L +#define PCIE_RX_CNTL3__RX_PRIV_POISON_EGRESS_BLOCK_EN_MASK 0x00000800L +//PCIE_RX_CREDITS_ALLOCATED_P +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//PCIE_RX_CREDITS_ALLOCATED_NP +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//PCIE_RX_CREDITS_ALLOCATED_CPL +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//PCIEP_ERROR_INJECT_PHYSICAL +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//PCIEP_ERROR_INJECT_TRANSACTION +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//PCIEP_NAK_COUNTER +#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//PCIE_LC_CNTL +#define PCIE_LC_CNTL__LC_ADVANCE_SPEED_COMPL_ON_EVERY_COMPL_ENTRY__SHIFT 0x0 +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define PCIE_LC_CNTL__LC_ADVANCE_SPEED_COMPL_ON_EVERY_COMPL_ENTRY_MASK 0x00000001L +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//PCIE_LC_TRAINING_CNTL +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1d +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xE0000000L +//PCIE_LC_LINK_WIDTH_CNTL +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//PCIE_LC_N_FTS_CNTL +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xc +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xd +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_32GT_CNTL__SHIFT 0xe +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00001000L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00002000L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_32GT_CNTL_MASK 0x00004000L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//PSWUSP0_PCIE_LC_SPEED_CNTL +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x8 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0xb +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0xc +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x15 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x16 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x17 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x18 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x19 +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x1a +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x1b +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN5__SHIFT 0x1c +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN5__SHIFT 0x1d +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x000000E0L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x00000700L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000800L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00007000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x00200000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00400000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00800000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x01000000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x02000000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x04000000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x08000000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN5_MASK 0x10000000L +#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN5_MASK 0x20000000L +//PCIE_LC_STATE0 +#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//PCIE_LC_STATE1 +#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//PCIE_LC_STATE2 +#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//PCIE_LC_STATE3 +#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//PCIE_LC_STATE4 +#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//PCIE_LC_STATE5 +#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//PSWUSP0_PCIE_LC_CNTL2 +#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13 +#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//PCIE_LC_BW_CHANGE_CNTL +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//PCIE_LC_CDR_CNTL +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//PCIE_LC_LANE_CNTL +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +//PCIE_LC_CNTL3 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc +#define PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd +#define PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe +#define PCIE_LC_CNTL3__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0xf +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L +#define PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L +#define PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L +#define PCIE_LC_CNTL3__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x00008000L +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L +//PCIE_LC_CNTL4 +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define PCIE_LC_CNTL4__LC_L1_POWERDOWN__SHIFT 0x4 +#define PCIE_LC_CNTL4__LC_P2_ENTRY__SHIFT 0x5 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MODE__SHIFT 0x7 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x8 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define PCIE_LC_CNTL4__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0xb +#define PCIE_LC_CNTL4__LC_SEND_EIEOS_IN_RCFG__SHIFT 0xc +#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define PCIE_LC_CNTL4__LC_WAIT_FOR_TWO_EIEOS_SEQUENCE__SHIFT 0xf +#define PCIE_LC_CNTL4__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x10 +#define PCIE_LC_CNTL4__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x11 +#define PCIE_LC_CNTL4__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x12 +#define PCIE_LC_CNTL4__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x13 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x15 +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK 0x00000010L +#define PCIE_LC_CNTL4__LC_P2_ENTRY_MASK 0x00000020L +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000100L +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define PCIE_LC_CNTL4__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00000800L +#define PCIE_LC_CNTL4__LC_SEND_EIEOS_IN_RCFG_MASK 0x00001000L +#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define PCIE_LC_CNTL4__LC_WAIT_FOR_TWO_EIEOS_SEQUENCE_MASK 0x00008000L +#define PCIE_LC_CNTL4__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x00010000L +#define PCIE_LC_CNTL4__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x00020000L +#define PCIE_LC_CNTL4__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x00040000L +#define PCIE_LC_CNTL4__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x00180000L +#define PCIE_LC_CNTL4__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00200000L +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//PCIE_LC_CNTL5 +#define PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0 +#define PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2 +#define PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6 +#define PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa +#define PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10 +#define PCIE_LC_CNTL5__LC_LOCAL_USE_PRESET__SHIFT 0x15 +#define PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16 +#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L +#define PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL +#define PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L +#define PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L +#define PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L +#define PCIE_LC_CNTL5__LC_LOCAL_USE_PRESET_MASK 0x00200000L +#define PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L +#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//PCIE_LC_FORCE_COEFF +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13 +#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L +#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//PCIE_LC_BEST_EQ_SETTINGS +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0xC0000000L +//PCIE_LC_FORCE_EQ_REQ_COEFF +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L +//PCIE_LC_CNTL6 +#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6 +#define PCIE_LC_CNTL6__LC_SPC_MODE_32GT__SHIFT 0x8 +#define PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0xc +#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0xd +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0x14 +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0x15 +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x17 +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x19 +#define PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x1a +#define PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1b +#define PCIE_LC_CNTL6__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x1d +#define PCIE_LC_CNTL6__LC_RETIMER_PRESENCE__SHIFT 0x1e +#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L +#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL +#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L +#define PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L +#define PCIE_LC_CNTL6__LC_SPC_MODE_32GT_MASK 0x00000300L +#define PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00001000L +#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x0003E000L +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00100000L +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x00600000L +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x01800000L +#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x02000000L +#define PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x04000000L +#define PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x18000000L +#define PCIE_LC_CNTL6__LC_IGNORE_RETIMER_PRESENCE_MASK 0x20000000L +#define PCIE_LC_CNTL6__LC_RETIMER_PRESENCE_MASK 0xC0000000L +//PCIE_LC_CNTL7 +#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18 +#define PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19 +#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f +#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L +#define PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L +#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L +//PCIEP_STRAP_LC +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13 +#define PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14 +#define PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15 +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_16GT_DIS__SHIFT 0x16 +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_32GT_DIS__SHIFT 0x17 +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +#define PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L +#define PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L +#define PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_16GT_DIS_MASK 0x00400000L +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_32GT_DIS_MASK 0x00800000L +//PSWUSP0_PCIEP_STRAP_MISC +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6 +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7 +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L +#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L +//PCIEP_STRAP_LC2 +#define PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0 +#define PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1 +#define PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3 +#define PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4 +#define PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7 +#define PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L +#define PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L +#define PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L +#define PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L +#define PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L +//PCIE_LC_L1_PM_SUBSTATE +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5 +#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_EN__SHIFT 0xd +#define PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_TRIGGER__SHIFT 0xe +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_BLOCK_EXIT_PG_COMMIT__SHIFT 0xf +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define PCIE_LC_L1_PM_SUBSTATE__LC_WAKE_FROM_ASPM_L1_ON_PM_CONTROL_CLEAR__SHIFT 0x1a +#define PCIE_LC_L1_PM_SUBSTATE__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x1b +#define PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0x1c +#define PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0x1d +#define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1e +#define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_USE_PCS_SIDEBAND__SHIFT 0x1f +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L +#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_EN_MASK 0x00002000L +#define PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_TRIGGER_MASK 0x00004000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_BLOCK_EXIT_PG_COMMIT_MASK 0x00008000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_WAKE_FROM_ASPM_L1_ON_PM_CONTROL_CLEAR_MASK 0x04000000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x08000000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x10000000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x20000000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x40000000L +#define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_USE_PCS_SIDEBAND_MASK 0x80000000L +//PCIE_LC_L1_PM_SUBSTATE2 +#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_POWERDOWN__SHIFT 0xe +#define PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_P2_EDGE__SHIFT 0xf +#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_POWERDOWN_P2_L1_2_EXIT__SHIFT 0x1b +#define PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_REFCLK_L1_2_T_POWERON__SHIFT 0x1c +#define PCIE_LC_L1_PM_SUBSTATE2__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1d +#define PCIE_LC_L1_PM_SUBSTATE2__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1e +#define PCIE_LC_L1_PM_SUBSTATE2__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x1f +#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_POWERDOWN_MASK 0x00004000L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_P2_EDGE_MASK 0x00008000L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_POWERDOWN_P2_L1_2_EXIT_MASK 0x08000000L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_REFCLK_L1_2_T_POWERON_MASK 0x10000000L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x20000000L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x40000000L +#define PCIE_LC_L1_PM_SUBSTATE2__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x80000000L +//PCIE_LC_L1_PM_SUBSTATE3 +#define PCIE_LC_L1_PM_SUBSTATE3__T_POWER_ON_FCH_TARGET_ADDRESS_LO__SHIFT 0x0 +#define PCIE_LC_L1_PM_SUBSTATE3__T_POWER_ON_FCH_TARGET_ADDRESS_LO_MASK 0xFFFFFFFFL +//PCIE_LC_L1_PM_SUBSTATE4 +#define PCIE_LC_L1_PM_SUBSTATE4__T_POWER_ON_FCH_TARGET_ADDRESS_HI__SHIFT 0x0 +#define PCIE_LC_L1_PM_SUBSTATE4__T_POWER_ON_FCH_TARGET_ADDRESS_HI_MASK 0xFFFFFFFFL +//PCIE_LC_L1_PM_SUBSTATE5 +#define PCIE_LC_L1_PM_SUBSTATE5__T_POWER_ON_FCH_L12_CLKREQ_DELAY__SHIFT 0x0 +#define PCIE_LC_L1_PM_SUBSTATE5__LC_BLOCK_EI_L1_REFCLK_OFF__SHIFT 0x1e +#define PCIE_LC_L1_PM_SUBSTATE5__LC_IGNORE_ALL_RX_ELEC_IDLE_IN_L1SS__SHIFT 0x1f +#define PCIE_LC_L1_PM_SUBSTATE5__T_POWER_ON_FCH_L12_CLKREQ_DELAY_MASK 0x000000FFL +#define PCIE_LC_L1_PM_SUBSTATE5__LC_BLOCK_EI_L1_REFCLK_OFF_MASK 0x40000000L +#define PCIE_LC_L1_PM_SUBSTATE5__LC_IGNORE_ALL_RX_ELEC_IDLE_IN_L1SS_MASK 0x80000000L +//PCIEP_BCH_ECC_CNTL +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//PCIE_LC_CNTL8 +#define PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x0 +#define PCIE_LC_CNTL8__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0x2 +#define PCIE_LC_CNTL8__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0x3 +#define PCIE_LC_CNTL8__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x4 +#define PCIE_LC_CNTL8__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x6 +#define PCIE_LC_CNTL8__LC_ESM_RATE2_TIMER_FACTOR__SHIFT 0x8 +#define PCIE_LC_CNTL8__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xa +#define PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_ON__SHIFT 0x14 +#define PCIE_LC_CNTL8__LC_LOOPBACK_EQ_IN_PROGRESS__SHIFT 0x15 +#define PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN__SHIFT 0x16 +#define PCIE_LC_CNTL8__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN__SHIFT 0x17 +#define PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_LANE_UNDER_TEST__SHIFT 0x18 +#define PCIE_LC_CNTL8__LC_LOOPBACK_EQ_LANE_UNDER_TEST__SHIFT 0x1c +#define PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x00000003L +#define PCIE_LC_CNTL8__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00000004L +#define PCIE_LC_CNTL8__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00000008L +#define PCIE_LC_CNTL8__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x00000030L +#define PCIE_LC_CNTL8__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x000000C0L +#define PCIE_LC_CNTL8__LC_ESM_RATE2_TIMER_FACTOR_MASK 0x00000300L +#define PCIE_LC_CNTL8__LC_USC_ACCEPTABLE_PRESETS_MASK 0x000FFC00L +#define PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_ON_MASK 0x00100000L +#define PCIE_LC_CNTL8__LC_LOOPBACK_EQ_IN_PROGRESS_MASK 0x00200000L +#define PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_MASK 0x00400000L +#define PCIE_LC_CNTL8__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_MASK 0x00800000L +#define PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_LANE_UNDER_TEST_MASK 0x0F000000L +#define PCIE_LC_CNTL8__LC_LOOPBACK_EQ_LANE_UNDER_TEST_MASK 0xF0000000L +//PCIE_LC_CNTL9 +#define PCIE_LC_CNTL9__LC_RESET_RCVR_DETECTED_ALL_ARCS__SHIFT 0x0 +#define PCIE_LC_CNTL9__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0x1 +#define PCIE_LC_CNTL9__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x2 +#define PCIE_LC_CNTL9__LC_LOOPBACK_EQ_ARC_EN__SHIFT 0x3 +#define PCIE_LC_CNTL9__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_EN__SHIFT 0x4 +#define PCIE_LC_CNTL9__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x5 +#define PCIE_LC_CNTL9__LC_EXT_ASPM_L12_COMMONMODE_COUNT_METHOD__SHIFT 0x6 +#define PCIE_LC_CNTL9__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0x7 +#define PCIE_LC_CNTL9__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x8 +#define PCIE_LC_CNTL9__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0x9 +#define PCIE_LC_CNTL9__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0xa +#define PCIE_LC_CNTL9__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0xb +#define PCIE_LC_CNTL9__LC_TRAINING_BITS_REQUIRED__SHIFT 0xc +#define PCIE_LC_CNTL9__LC_REPEAT_RXEQEVAL_AFTER_TIMEOUT__SHIFT 0xe +#define PCIE_LC_CNTL9__LC_CPM_IDLE_REFCLKREQ_CHECK__SHIFT 0xf +#define PCIE_LC_CNTL9__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x10 +#define PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x11 +#define PCIE_LC_CNTL9__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x12 +#define PCIE_LC_CNTL9__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x13 +#define PCIE_LC_CNTL9__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x14 +#define PCIE_LC_CNTL9__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0x15 +#define PCIE_LC_CNTL9__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0x16 +#define PCIE_LC_CNTL9__LC_USE_OLD_PHYSTATUS_FOR_POWERDOWN_INACTIVE__SHIFT 0x17 +#define PCIE_LC_CNTL9__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x18 +#define PCIE_LC_CNTL9__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x19 +#define PCIE_LC_CNTL9__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x1a +#define PCIE_LC_CNTL9__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x1b +#define PCIE_LC_CNTL9__LC_USE_NEW_EQ_SYMBOL_6_EN__SHIFT 0x1c +#define PCIE_LC_CNTL9__LC_DEC_FAILED_SPEED_CHANGE_COUNT_ABORT_BYPASS_TO_HIGH_RATE__SHIFT 0x1d +#define PCIE_LC_CNTL9__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x1e +#define PCIE_LC_CNTL9__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x1f +#define PCIE_LC_CNTL9__LC_RESET_RCVR_DETECTED_ALL_ARCS_MASK 0x00000001L +#define PCIE_LC_CNTL9__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00000002L +#define PCIE_LC_CNTL9__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000004L +#define PCIE_LC_CNTL9__LC_LOOPBACK_EQ_ARC_EN_MASK 0x00000008L +#define PCIE_LC_CNTL9__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_EN_MASK 0x00000010L +#define PCIE_LC_CNTL9__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000020L +#define PCIE_LC_CNTL9__LC_EXT_ASPM_L12_COMMONMODE_COUNT_METHOD_MASK 0x00000040L +#define PCIE_LC_CNTL9__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000080L +#define PCIE_LC_CNTL9__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x00000100L +#define PCIE_LC_CNTL9__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000200L +#define PCIE_LC_CNTL9__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000400L +#define PCIE_LC_CNTL9__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000800L +#define PCIE_LC_CNTL9__LC_TRAINING_BITS_REQUIRED_MASK 0x00003000L +#define PCIE_LC_CNTL9__LC_REPEAT_RXEQEVAL_AFTER_TIMEOUT_MASK 0x00004000L +#define PCIE_LC_CNTL9__LC_CPM_IDLE_REFCLKREQ_CHECK_MASK 0x00008000L +#define PCIE_LC_CNTL9__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x00010000L +#define PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x00020000L +#define PCIE_LC_CNTL9__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x00040000L +#define PCIE_LC_CNTL9__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00080000L +#define PCIE_LC_CNTL9__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00100000L +#define PCIE_LC_CNTL9__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00200000L +#define PCIE_LC_CNTL9__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00400000L +#define PCIE_LC_CNTL9__LC_USE_OLD_PHYSTATUS_FOR_POWERDOWN_INACTIVE_MASK 0x00800000L +#define PCIE_LC_CNTL9__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x01000000L +#define PCIE_LC_CNTL9__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x02000000L +#define PCIE_LC_CNTL9__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x04000000L +#define PCIE_LC_CNTL9__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x08000000L +#define PCIE_LC_CNTL9__LC_USE_NEW_EQ_SYMBOL_6_EN_MASK 0x10000000L +#define PCIE_LC_CNTL9__LC_DEC_FAILED_SPEED_CHANGE_COUNT_ABORT_BYPASS_TO_HIGH_RATE_MASK 0x20000000L +#define PCIE_LC_CNTL9__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x40000000L +#define PCIE_LC_CNTL9__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x80000000L +//PCIE_LC_FORCE_COEFF2 +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0 +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1 +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7 +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd +#define PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13 +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L +#define PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L +#define PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L +//PCIE_LC_FORCE_EQ_REQ_COEFF2 +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0 +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7 +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13 +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19 +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L +//PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0 +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1 +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LC_PKT_GEN_DYN_CLK_GATING__SHIFT 0x2 +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_DYN_CLK_GATING__SHIFT 0x3 +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LTSSM_DYN_CLK_GATING__SHIFT 0x4 +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LC_PKT_GEN_DYN_CLK_GATING_MASK 0x00000004L +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_DYN_CLK_GATING_MASK 0x00000008L +#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LTSSM_DYN_CLK_GATING_MASK 0x00000010L +//PCIE_LC_CNTL10 +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0 +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1 +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2 +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3 +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5 +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9 +#define PCIE_LC_CNTL10__LC_USE_PENDING_FOM_SKIP_SECOND_RXEQEVAL__SHIFT 0xd +#define PCIE_LC_CNTL10__LC_TIEOFF_PORTS_IGNORE_PHYSTATUS__SHIFT 0xf +#define PCIE_LC_CNTL10__LC_CLEAR_CNTL_SKP_SELECT_DATASTREAM_EXIT__SHIFT 0x10 +#define PCIE_LC_CNTL10__LC_DEASSERT_REFCLKREQ_IN_L23__SHIFT 0x11 +#define PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_L23__SHIFT 0x12 +#define PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_NON_SS_L1__SHIFT 0x13 +#define PCIE_LC_CNTL10__LC_LSLD_EN__SHIFT 0x17 +#define PCIE_LC_CNTL10__LC_LSLD_RATE_REQD__SHIFT 0x18 +#define PCIE_LC_CNTL10__LC_LSLD_MODE__SHIFT 0x1a +#define PCIE_LC_CNTL10__LC_LSLD_DONE__SHIFT 0x1b +#define PCIE_LC_CNTL10__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c +#define PCIE_LC_CNTL10__LC_LSLD_CURRENT_RATE__SHIFT 0x1e +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L +#define PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L +#define PCIE_LC_CNTL10__LC_USE_PENDING_FOM_SKIP_SECOND_RXEQEVAL_MASK 0x00002000L +#define PCIE_LC_CNTL10__LC_TIEOFF_PORTS_IGNORE_PHYSTATUS_MASK 0x00008000L +#define PCIE_LC_CNTL10__LC_CLEAR_CNTL_SKP_SELECT_DATASTREAM_EXIT_MASK 0x00010000L +#define PCIE_LC_CNTL10__LC_DEASSERT_REFCLKREQ_IN_L23_MASK 0x00020000L +#define PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_L23_MASK 0x00040000L +#define PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_NON_SS_L1_MASK 0x00080000L +#define PCIE_LC_CNTL10__LC_LSLD_EN_MASK 0x00800000L +#define PCIE_LC_CNTL10__LC_LSLD_RATE_REQD_MASK 0x03000000L +#define PCIE_LC_CNTL10__LC_LSLD_MODE_MASK 0x04000000L +#define PCIE_LC_CNTL10__LC_LSLD_DONE_MASK 0x08000000L +#define PCIE_LC_CNTL10__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L +#define PCIE_LC_CNTL10__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L +//PCIE_LC_SAVE_RESTORE_1 +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0 +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1 +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2 +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EQ_SETTINGS_RESTORED__SHIFT 0xd +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10 +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EQ_SETTINGS_RESTORED_MASK 0x00002000L +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L +#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L +//PCIE_LC_SAVE_RESTORE_2 +#define PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0 +#define PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL +//PCIE_LC_CNTL11 +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_SUPPORT__SHIFT 0x0 +#define PCIE_LC_CNTL11__LC_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT__SHIFT 0x1 +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RESERVED__SHIFT 0x2 +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RCVD__SHIFT 0x3 +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_NEGOTIATED__SHIFT 0x4 +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_FAILURE__SHIFT 0x5 +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_SUPPORT__SHIFT 0x8 +#define PCIE_LC_CNTL11__LC_ADVERTISE_NO_EQ_NEEDED_SUPPORT__SHIFT 0x9 +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RESERVED__SHIFT 0xa +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RCVD__SHIFT 0xb +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_NEGOTIATED__SHIFT 0xc +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_FAILURE__SHIFT 0xd +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_PRESET_SEL__SHIFT 0xe +#define PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_SENT__SHIFT 0xf +#define PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_RCVD__SHIFT 0x11 +#define PCIE_LC_CNTL11__LC_DISABLE_TRAINING_BIT_ARCH_IND__SHIFT 0x13 +#define PCIE_LC_CNTL11__LC_SET_TRANSMITTER_PRECODE_REQUEST__SHIFT 0x18 +#define PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_REQUEST_RCVD__SHIFT 0x19 +#define PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON__SHIFT 0x1a +#define PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_RCVD__SHIFT 0x1b +#define PCIE_LC_CNTL11__LC_LAST_TRANSMITTER_PRECODE_REQUEST__SHIFT 0x1c +#define PCIE_LC_CNTL11__LC_CHECK_TS1_EC_ON_EQ_EXIT__SHIFT 0x1d +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_SUPPORT_MASK 0x00000001L +#define PCIE_LC_CNTL11__LC_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT_MASK 0x00000002L +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RESERVED_MASK 0x00000004L +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RCVD_MASK 0x00000008L +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_NEGOTIATED_MASK 0x00000010L +#define PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_FAILURE_MASK 0x00000020L +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_SUPPORT_MASK 0x00000100L +#define PCIE_LC_CNTL11__LC_ADVERTISE_NO_EQ_NEEDED_SUPPORT_MASK 0x00000200L +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RESERVED_MASK 0x00000400L +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RCVD_MASK 0x00000800L +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_NEGOTIATED_MASK 0x00001000L +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_FAILURE_MASK 0x00002000L +#define PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_PRESET_SEL_MASK 0x00004000L +#define PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_SENT_MASK 0x00018000L +#define PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_RCVD_MASK 0x00060000L +#define PCIE_LC_CNTL11__LC_DISABLE_TRAINING_BIT_ARCH_IND_MASK 0x00F80000L +#define PCIE_LC_CNTL11__LC_SET_TRANSMITTER_PRECODE_REQUEST_MASK 0x01000000L +#define PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_REQUEST_RCVD_MASK 0x02000000L +#define PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_MASK 0x04000000L +#define PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_RCVD_MASK 0x08000000L +#define PCIE_LC_CNTL11__LC_LAST_TRANSMITTER_PRECODE_REQUEST_MASK 0x10000000L +#define PCIE_LC_CNTL11__LC_CHECK_TS1_EC_ON_EQ_EXIT_MASK 0x20000000L +//PCIE_LC_CNTL12 +#define PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0x0 +#define PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x1 +#define PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x2 +#define PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x3 +#define PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x4 +#define PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x5 +#define PCIE_LC_CNTL12__LC_DELAY_PHASE1__SHIFT 0x6 +#define PCIE_LC_CNTL12__LC_BLOCKALIGN_IN_L1_ENTRY__SHIFT 0x8 +#define PCIE_LC_CNTL12__LC_USE_LEGACY_RXSB1_SPDCHG_ELECIDLE__SHIFT 0x9 +#define PCIE_LC_CNTL12__LC_LOCK_REVERSAL_EARLY_CONFIG_COMPLETE__SHIFT 0xa +#define PCIE_LC_CNTL12__LC_LOCK_REVERSAL_IMMEDIATE_CONFIG_COMPLETE__SHIFT 0xb +#define PCIE_LC_CNTL12__LC_USE_LOOPBACK_INACTIVE_LANES__SHIFT 0xc +#define PCIE_LC_CNTL12__LC_LOOPBACK_TEST_MODE_RCVRDET__SHIFT 0xd +#define PCIE_LC_CNTL12__LC_LOOPBACK_EQ_LOCK_REVERSAL__SHIFT 0xe +#define PCIE_LC_CNTL12__LC_LIVE_DESKEW_MASK_EN__SHIFT 0x10 +#define PCIE_LC_CNTL12__LC_LIVE_DESKEW_8B10B_EN__SHIFT 0x11 +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_DATA_UNLOCK__SHIFT 0x12 +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_RECOVER__SHIFT 0x13 +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_ADAPT__SHIFT 0x14 +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_INIT__SHIFT 0x15 +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_EVENT_SEL__SHIFT 0x16 +#define PCIE_LC_CNTL12__LC_DEFER_SKIP_INTERVAL_MODE__SHIFT 0x18 +#define PCIE_LC_CNTL12__LC_RECOVERY_EQ_WAIT_FOR_PIPE_STOPPED__SHIFT 0x19 +#define PCIE_LC_CNTL12__LC_HOLD_TX_STOP_SENDING_PKTS_REPLAY_RETRAIN__SHIFT 0x1a +#define PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_SAFERECOVER__SHIFT 0x1b +#define PCIE_LC_CNTL12__LC_DSC_INITIATE_EQUALIZATION_OS_BOUNDARY__SHIFT 0x1c +#define PCIE_LC_CNTL12__LC_EQ_REQ_PHASE_WAIT_FOR_FINAL_TS1__SHIFT 0x1d +#define PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_RXEQEVAL__SHIFT 0x1e +#define PCIE_LC_CNTL12__LC_TRACK_RX_WAIT_FOR_TS1__SHIFT 0x1f +#define PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000001L +#define PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00000002L +#define PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00000004L +#define PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00000008L +#define PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00000010L +#define PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000020L +#define PCIE_LC_CNTL12__LC_DELAY_PHASE1_MASK 0x000000C0L +#define PCIE_LC_CNTL12__LC_BLOCKALIGN_IN_L1_ENTRY_MASK 0x00000100L +#define PCIE_LC_CNTL12__LC_USE_LEGACY_RXSB1_SPDCHG_ELECIDLE_MASK 0x00000200L +#define PCIE_LC_CNTL12__LC_LOCK_REVERSAL_EARLY_CONFIG_COMPLETE_MASK 0x00000400L +#define PCIE_LC_CNTL12__LC_LOCK_REVERSAL_IMMEDIATE_CONFIG_COMPLETE_MASK 0x00000800L +#define PCIE_LC_CNTL12__LC_USE_LOOPBACK_INACTIVE_LANES_MASK 0x00001000L +#define PCIE_LC_CNTL12__LC_LOOPBACK_TEST_MODE_RCVRDET_MASK 0x00002000L +#define PCIE_LC_CNTL12__LC_LOOPBACK_EQ_LOCK_REVERSAL_MASK 0x00004000L +#define PCIE_LC_CNTL12__LC_LIVE_DESKEW_MASK_EN_MASK 0x00010000L +#define PCIE_LC_CNTL12__LC_LIVE_DESKEW_8B10B_EN_MASK 0x00020000L +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_DATA_UNLOCK_MASK 0x00040000L +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_RECOVER_MASK 0x00080000L +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_ADAPT_MASK 0x00100000L +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_INIT_MASK 0x00200000L +#define PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_EVENT_SEL_MASK 0x00C00000L +#define PCIE_LC_CNTL12__LC_DEFER_SKIP_INTERVAL_MODE_MASK 0x01000000L +#define PCIE_LC_CNTL12__LC_RECOVERY_EQ_WAIT_FOR_PIPE_STOPPED_MASK 0x02000000L +#define PCIE_LC_CNTL12__LC_HOLD_TX_STOP_SENDING_PKTS_REPLAY_RETRAIN_MASK 0x04000000L +#define PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_SAFERECOVER_MASK 0x08000000L +#define PCIE_LC_CNTL12__LC_DSC_INITIATE_EQUALIZATION_OS_BOUNDARY_MASK 0x10000000L +#define PCIE_LC_CNTL12__LC_EQ_REQ_PHASE_WAIT_FOR_FINAL_TS1_MASK 0x20000000L +#define PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_RXEQEVAL_MASK 0x40000000L +#define PCIE_LC_CNTL12__LC_TRACK_RX_WAIT_FOR_TS1_MASK 0x80000000L +//PCIE_LC_SPEED_CNTL2 +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x0 +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x1 +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x2 +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x3 +#define PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x4 +#define PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x5 +#define PCIE_LC_SPEED_CNTL2__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x6 +#define PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_STATUS__SHIFT 0x7 +#define PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x8 +#define PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xa +#define PCIE_LC_SPEED_CNTL2__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0xb +#define PCIE_LC_SPEED_CNTL2__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0xc +#define PCIE_LC_SPEED_CNTL2__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xd +#define PCIE_LC_SPEED_CNTL2__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0xe +#define PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_AFTER_FAILED_EQ__SHIFT 0xf +#define PCIE_LC_SPEED_CNTL2__LC_ENFORCE_CORRECT_SPEED_FOR_EQ__SHIFT 0x10 +#define PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SOFTWARE_PERFORM_EQ__SHIFT 0x11 +#define PCIE_LC_SPEED_CNTL2__LC_SEND_EQ_TS2_IF_OTHER_SIDE_EVER_ADVERTISED_SPEED__SHIFT 0x12 +#define PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SINGLE_EQ_PER_RECOVERY__SHIFT 0x13 +#define PCIE_LC_SPEED_CNTL2__LC_USE_LEGACY_CLEAR_DELAY_DLLPs__SHIFT 0x14 +#define PCIE_LC_SPEED_CNTL2__LC_DEFER_RETRAIN_LINK_UNTIL_EXIT_RECOVERY__SHIFT 0x15 +#define PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_ON_FAIL_SPEED_CHANGE_LIMIT__SHIFT 0x16 +#define PCIE_LC_SPEED_CNTL2__LC_DEFER_PRIVATE_SPEED_CHANGE_UNTIL_EXIT_RECOVERY__SHIFT 0x17 +#define PCIE_LC_SPEED_CNTL2__LC_DONT_UPDATE_GEN_SUPPORT_MID_RECOVERY__SHIFT 0x19 +#define PCIE_LC_SPEED_CNTL2__LC_ALLOW_SET_INITIATE_SPEED_CHANGE_IN_RECOVERY_LOCK__SHIFT 0x1a +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000001L +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000002L +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000004L +#define PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000008L +#define PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x00000010L +#define PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x00000020L +#define PCIE_LC_SPEED_CNTL2__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000040L +#define PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_STATUS_MASK 0x00000080L +#define PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000300L +#define PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000400L +#define PCIE_LC_SPEED_CNTL2__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00000800L +#define PCIE_LC_SPEED_CNTL2__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x00001000L +#define PCIE_LC_SPEED_CNTL2__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00002000L +#define PCIE_LC_SPEED_CNTL2__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00004000L +#define PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_AFTER_FAILED_EQ_MASK 0x00008000L +#define PCIE_LC_SPEED_CNTL2__LC_ENFORCE_CORRECT_SPEED_FOR_EQ_MASK 0x00010000L +#define PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SOFTWARE_PERFORM_EQ_MASK 0x00020000L +#define PCIE_LC_SPEED_CNTL2__LC_SEND_EQ_TS2_IF_OTHER_SIDE_EVER_ADVERTISED_SPEED_MASK 0x00040000L +#define PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SINGLE_EQ_PER_RECOVERY_MASK 0x00080000L +#define PCIE_LC_SPEED_CNTL2__LC_USE_LEGACY_CLEAR_DELAY_DLLPs_MASK 0x00100000L +#define PCIE_LC_SPEED_CNTL2__LC_DEFER_RETRAIN_LINK_UNTIL_EXIT_RECOVERY_MASK 0x00200000L +#define PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_ON_FAIL_SPEED_CHANGE_LIMIT_MASK 0x00400000L +#define PCIE_LC_SPEED_CNTL2__LC_DEFER_PRIVATE_SPEED_CHANGE_UNTIL_EXIT_RECOVERY_MASK 0x01800000L +#define PCIE_LC_SPEED_CNTL2__LC_DONT_UPDATE_GEN_SUPPORT_MID_RECOVERY_MASK 0x02000000L +#define PCIE_LC_SPEED_CNTL2__LC_ALLOW_SET_INITIATE_SPEED_CHANGE_IN_RECOVERY_LOCK_MASK 0x04000000L +//PCIE_LC_FORCE_COEFF3 +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_COEFF_32GT__SHIFT 0x0 +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_PRE_CURSOR_32GT__SHIFT 0x1 +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_CURSOR_32GT__SHIFT 0x7 +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_POST_CURSOR_32GT__SHIFT 0xd +#define PCIE_LC_FORCE_COEFF3__LC_3X3_COEFF_SEARCH_EN_32GT__SHIFT 0x13 +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_COEFF_32GT_MASK 0x00000001L +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_PRE_CURSOR_32GT_MASK 0x0000007EL +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_CURSOR_32GT_MASK 0x00001F80L +#define PCIE_LC_FORCE_COEFF3__LC_FORCE_POST_CURSOR_32GT_MASK 0x0007E000L +#define PCIE_LC_FORCE_COEFF3__LC_3X3_COEFF_SEARCH_EN_32GT_MASK 0x00080000L +//PCIE_LC_FORCE_EQ_REQ_COEFF3 +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_32GT__SHIFT 0x0 +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_PRE_CURSOR_REQ_32GT__SHIFT 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_CURSOR_REQ_32GT__SHIFT 0x7 +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_POST_CURSOR_REQ_32GT__SHIFT 0xd +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FS_OTHER_END_32GT__SHIFT 0x13 +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_LF_OTHER_END_32GT__SHIFT 0x19 +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_32GT_MASK 0x00000001L +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_PRE_CURSOR_REQ_32GT_MASK 0x0000007EL +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_CURSOR_REQ_32GT_MASK 0x00001F80L +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_POST_CURSOR_REQ_32GT_MASK 0x0007E000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FS_OTHER_END_32GT_MASK 0x01F80000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_LF_OTHER_END_32GT_MASK 0x7E000000L +//PCIE_TX_SEQ +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//PCIE_TX_REPLAY +#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define PCIE_TX_REPLAY__TX_REPLAY_ROLLOVER_EN__SHIFT 0x5 +#define PCIE_TX_REPLAY__TX_REPLAY_STALL__SHIFT 0xa +#define PCIE_TX_REPLAY__TX_REPLAY_DISABLE__SHIFT 0xb +#define PCIE_TX_REPLAY__TX_REPLAY_ALL__SHIFT 0xc +#define PCIE_TX_REPLAY__TX_REPLAY_FORCE_WRSCH_ACK__SHIFT 0xd +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x0000001FL +#define PCIE_TX_REPLAY__TX_REPLAY_ROLLOVER_EN_MASK 0x00000020L +#define PCIE_TX_REPLAY__TX_REPLAY_STALL_MASK 0x00000400L +#define PCIE_TX_REPLAY__TX_REPLAY_DISABLE_MASK 0x00000800L +#define PCIE_TX_REPLAY__TX_REPLAY_ALL_MASK 0x00001000L +#define PCIE_TX_REPLAY__TX_REPLAY_FORCE_WRSCH_ACK_MASK 0x00002000L +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//PCIE_TX_ACK_LATENCY_LIMIT +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_FC_ARB_ENABLE__SHIFT 0xd +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_SCALE__SHIFT 0x14 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_ADJUSTMENT__SHIFT 0x18 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_FC_ARB_ENABLE_MASK 0x00002000L +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_SCALE_MASK 0x00F00000L +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_ADJUSTMENT_MASK 0xFF000000L +//PCIE_TX_CREDITS_FCU_THRESHOLD +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//PCIE_TX_VENDOR_SPECIFIC +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18 +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L +//PCIE_TX_NOP_DLLP +#define PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0 +#define PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18 +#define PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL +#define PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L +//PCIE_TX_REQUEST_NUM_CNTL +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//PCIE_TX_CREDITS_ADVT_P +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L +//PCIE_TX_CREDITS_ADVT_NP +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L +//PCIE_TX_CREDITS_ADVT_CPL +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L +//PCIE_TX_CREDITS_INIT_P +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//PCIE_TX_CREDITS_INIT_NP +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//PCIE_TX_CREDITS_INIT_CPL +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//PCIE_TX_CREDITS_STATUS +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//PCIE_FC_P +#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define PCIE_FC_P__PH_CREDITS__SHIFT 0x10 +#define PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL +#define PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L +//PCIE_FC_NP +#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10 +#define PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL +#define PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L +//PCIE_FC_CPL +#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10 +#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL +#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L +//PCIE_FC_P_VC1 +#define PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0 +#define PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10 +#define PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL +#define PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L +//PCIE_FC_NP_VC1 +#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0 +#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10 +#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL +#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L +//PCIE_FC_CPL_VC1 +#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0 +#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10 +#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL +#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L + + +// addressBlock: nbio_pcie0_pciedir +//PCIE_RESERVED +#define PCIE_RESERVED__RESERVED__SHIFT 0x0 +#define PCIE_RESERVED__RESERVED_MASK 0xFFFFFFFFL +//PCIE_SCRATCH +#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//PCIE_RX_NUM_NAK +#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 +#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL +//PCIE_RX_NUM_NAK_GENERATED +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL +//PCIE_CNTL +#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 +#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf +#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 +#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f +#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL +#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L +#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L +#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L +//PCIE_CONFIG_CNTL +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL +//PCIE_RX_CNTL5 +#define PCIE_RX_CNTL5__RX_SB_ARB_MODE__SHIFT 0x0 +#define PCIE_RX_CNTL5__RX_SB_ARB_LOWER_LIMIT__SHIFT 0x8 +#define PCIE_RX_CNTL5__RX_SB_ARB_UPPER_LIMIT__SHIFT 0x10 +#define PCIE_RX_CNTL5__RX_SB_ARB_MODE_MASK 0x00000003L +#define PCIE_RX_CNTL5__RX_SB_ARB_LOWER_LIMIT_MASK 0x00003F00L +#define PCIE_RX_CNTL5__RX_SB_ARB_UPPER_LIMIT_MASK 0x003F0000L +//PCIE_RX_CNTL4 +#define PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_TPH_DIS__SHIFT 0x0 +#define PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE4_DIS__SHIFT 0x1 +#define PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE1_E_F_DIS__SHIFT 0x2 +#define PCIE_RX_CNTL4__CI_ATS_RO_DIS__SHIFT 0x3 +#define PCIE_RX_CNTL4__RX_CTO_CPL_REFCLK_SPEED__SHIFT 0x8 +#define PCIE_RX_CNTL4__RX_OVERFLOW_PRIV_MASK__SHIFT 0xa +#define PCIE_RX_CNTL4__RX_PD_OVERFLOW_FIX_DISABLE__SHIFT 0x10 +#define PCIE_RX_CNTL4__RX_NAK_COUNTER_MODE__SHIFT 0x11 +#define PCIE_RX_CNTL4__RX_SF_FILTERING_END_FROM_DLLP_DIS__SHIFT 0x12 +#define PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_TPH_DIS_MASK 0x00000001L +#define PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE4_DIS_MASK 0x00000002L +#define PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE1_E_F_DIS_MASK 0x00000004L +#define PCIE_RX_CNTL4__CI_ATS_RO_DIS_MASK 0x00000008L +#define PCIE_RX_CNTL4__RX_CTO_CPL_REFCLK_SPEED_MASK 0x00000300L +#define PCIE_RX_CNTL4__RX_OVERFLOW_PRIV_MASK_MASK 0x0000FC00L +#define PCIE_RX_CNTL4__RX_PD_OVERFLOW_FIX_DISABLE_MASK 0x00010000L +#define PCIE_RX_CNTL4__RX_NAK_COUNTER_MODE_MASK 0x00020000L +#define PCIE_RX_CNTL4__RX_SF_FILTERING_END_FROM_DLLP_DIS_MASK 0x00040000L +//PCIE_COMMON_AER_MASK +#define PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC__SHIFT 0x0 +#define PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC_MASK 0x000000FFL +//PCIE_CNTL2 +#define PCIE_CNTL2__RCB_LS_EN__SHIFT 0x0 +#define PCIE_CNTL2__MST_CPL_LS_EN__SHIFT 0x1 +#define PCIE_CNTL2__SLVAER_LS_EN__SHIFT 0x2 +#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 +#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 +#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d +#define PCIE_CNTL2__RCB_LS_EN_MASK 0x00000001L +#define PCIE_CNTL2__MST_CPL_LS_EN_MASK 0x00000002L +#define PCIE_CNTL2__SLVAER_LS_EN_MASK 0x00000004L +#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L +#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L +#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L +//PCIE_RX_CNTL2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 +#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc +#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd +#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 +#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L +#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L +#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L +#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L +#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//PCIE_CI_CNTL +#define PCIE_CI_CNTL__CI_SLV_SDP_CHAIN_DIS__SHIFT 0x0 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT 0x3 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 +#define PCIE_CI_CNTL__CI_SLV_SDP_MEM_WR_FULL_DIS__SHIFT 0x9 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc +#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10 +#define PCIE_CI_CNTL__TX_PGMEM_CTRL_PGATE_DIS__SHIFT 0x15 +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16 +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17 +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18 +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT 0x1d +#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT 0x1e +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT 0x1f +#define PCIE_CI_CNTL__CI_SLV_SDP_CHAIN_DIS_MASK 0x00000001L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK 0x00000038L +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L +#define PCIE_CI_CNTL__CI_SLV_SDP_MEM_WR_FULL_DIS_MASK 0x00000200L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L +#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L +#define PCIE_CI_CNTL__TX_PGMEM_CTRL_PGATE_DIS_MASK 0x00200000L +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK 0x20000000L +#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK 0x40000000L +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK 0x80000000L +//PCIE_BUS_CNTL +#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc +#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L +//PCIE_LC_STATE6 +#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 +#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 +#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 +#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 +#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL +#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L +#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L +#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L +//PCIE_LC_STATE7 +#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 +#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 +#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 +#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 +#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL +#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L +#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L +#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L +//PCIE_LC_STATE8 +#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 +#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 +#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 +#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 +#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL +#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L +#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L +#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L +//PCIE_LC_STATE9 +#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 +#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 +#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 +#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 +#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL +#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L +#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L +#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L +//PCIE_LC_STATE10 +#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 +#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 +#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 +#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 +#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL +#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L +#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L +#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L +//PCIE_LC_STATE11 +#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 +#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 +#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 +#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 +#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL +#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L +#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L +#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L +//PCIE_LC_STATUS1 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L +//PCIE_LC_STATUS2 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L +//PCIE_WPR_CNTL +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L +//PCIE_RX_LAST_TLP0 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL +//PCIE_RX_LAST_TLP1 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL +//PCIE_RX_LAST_TLP2 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL +//PCIE_RX_LAST_TLP3 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL +//PCIE_I2C_REG_ADDR_EXPAND +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL +//PCIE_I2C_REG_DATA +#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 +#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL +//PCIE_CFG_CNTL +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +//PCIE_LC_PM_CNTL +#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0 +#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4 +#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8 +#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc +#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10 +#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14 +#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18 +#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c +#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL +#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L +#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L +#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L +#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L +#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L +#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L +#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L +//PCIE_LC_PM_CNTL2 +#define PCIE_LC_PM_CNTL2__LC_PORT_8_CLKREQB_MAP__SHIFT 0x0 +#define PCIE_LC_PM_CNTL2__LC_PORT_8_CLKREQB_MAP_MASK 0x0000000FL +//PCIE_P_CNTL +#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 +#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11 +#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT 0x12 +#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT 0x13 +#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT 0x17 +#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT 0x18 +#define PCIE_P_CNTL__LC_FILTER_SKP_FROM_L_IDLE__SHIFT 0x19 +#define PCIE_P_CNTL__LC_TIEOFF_LANES_IGNORE_REFCLKACK__SHIFT 0x1a +#define PCIE_P_CNTL__LC_MISSING_COM_RESET_SET_TRACK__SHIFT 0x1b +#define PCIE_P_CNTL__LC_RESET_TRACK_TSX_COUNTER_NO_DATA_VLD__SHIFT 0x1c +#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L +#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L +#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L +#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L +#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK 0x00040000L +#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK 0x00780000L +#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK 0x00800000L +#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK 0x01000000L +#define PCIE_P_CNTL__LC_FILTER_SKP_FROM_L_IDLE_MASK 0x02000000L +#define PCIE_P_CNTL__LC_TIEOFF_LANES_IGNORE_REFCLKACK_MASK 0x04000000L +#define PCIE_P_CNTL__LC_MISSING_COM_RESET_SET_TRACK_MASK 0x08000000L +#define PCIE_P_CNTL__LC_RESET_TRACK_TSX_COUNTER_NO_DATA_VLD_MASK 0x70000000L +//PCIE_P_BUF_STATUS +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L +//PCIE_P_DECODER_STATUS +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL +//PCIE_P_MISC_STATUS +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000001FFL +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L +//PCIE_P_RCV_L0S_FTS_DET +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L +//PCIE_RX_AD +#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0 +#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1 +#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2 +#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3 +#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4 +#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5 +#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8 +#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9 +#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa +#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb +#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc +#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd +#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe +#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf +#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT 0x10 +#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT 0x11 +#define PCIE_RX_AD__RX_RC_LARGE_VDM_BFRC_EN__SHIFT 0x12 +#define PCIE_RX_AD__RC_IGNORE_ACS_ERR_ON_DRS_DIS__SHIFT 0x13 +#define PCIE_RX_AD__RX_SWUS_IGNORE_ROUTING_ON_VDM_EN__SHIFT 0x14 +#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L +#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L +#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L +#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L +#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L +#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L +#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L +#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L +#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L +#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L +#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L +#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L +#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L +#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L +#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK 0x00010000L +#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK 0x00020000L +#define PCIE_RX_AD__RX_RC_LARGE_VDM_BFRC_EN_MASK 0x00040000L +#define PCIE_RX_AD__RC_IGNORE_ACS_ERR_ON_DRS_DIS_MASK 0x00080000L +#define PCIE_RX_AD__RX_SWUS_IGNORE_ROUTING_ON_VDM_EN_MASK 0x00100000L +//PCIE_SDP_CTRL +#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0 +#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4 +#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5 +#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9 +#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa +#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb +#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc +#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf +#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT 0x10 +#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT 0x11 +#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT 0x12 +#define PCIE_SDP_CTRL__CI_SLV_SDP_PARITY_CHECK_EN__SHIFT 0x13 +#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT 0x19 +#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT 0x1a +#define PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN__SHIFT 0x1d +#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_BIT46_EN__SHIFT 0x1e +#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL +#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L +#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L +#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L +#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L +#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L +#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L +#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L +#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK 0x00010000L +#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK 0x00020000L +#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK 0x00040000L +#define PCIE_SDP_CTRL__CI_SLV_SDP_PARITY_CHECK_EN_MASK 0x00080000L +#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK 0x02000000L +#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK 0x1C000000L +#define PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN_MASK 0x20000000L +#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_BIT46_EN_MASK 0x40000000L +//PCIE_SDP_SWUS_SLV_ATTR_CTRL +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L +//PCIE_SDP_CTRL2 +#define PCIE_SDP_CTRL2__CI_VIRTUAL_WIRE_DIS__SHIFT 0x0 +#define PCIE_SDP_CTRL2__CI_VIRTUAL_WIRE_DIS_MASK 0x00000001L +//PCIE_PERF_COUNT_CNTL +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_LCLK_STATUS__SHIFT 0x1f +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_LCLK_STATUS_MASK 0x80000000L +//PCIE_PERF_CNTL_TXCLK1 +#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK1 +#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK1 +#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK2 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK2 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK2 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK3 +#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK3 +#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK3 +#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK4 +#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK4 +#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK4 +#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_EVENT_LC_PORT_SEL +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK 0x0000000FL +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK 0x000000F0L +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x00000F00L +#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0000F000L +//PCIE_PERF_CNTL_EVENT_CI_PORT_SEL +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK1__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK1__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK2__SHIFT 0x1c +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK 0x0000000FL +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK 0x000000F0L +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK 0x00000F00L +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK 0x0000F000L +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK1_MASK 0x000F0000L +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK1_MASK 0x00F00000L +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK2_MASK 0x0F000000L +#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK2_MASK 0xF0000000L +//PCIE_PERF_CNTL_TXCLK5 +#define PCIE_PERF_CNTL_TXCLK5__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK5__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK5__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK5__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK5__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK5__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK5__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK5__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK5 +#define PCIE_PERF_COUNT0_TXCLK5__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK5__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK5 +#define PCIE_PERF_COUNT1_TXCLK5__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK5__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK6 +#define PCIE_PERF_CNTL_TXCLK6__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK6__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK6__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK6__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK6__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK6__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK6__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK6__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK6 +#define PCIE_PERF_COUNT0_TXCLK6__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK6__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK6 +#define PCIE_PERF_COUNT1_TXCLK6__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK6__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_STRAP_F0 +#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 +#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 +#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b +#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c +#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT 0x1d +#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e +#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT 0x1f +#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x00000004L +#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x00000008L +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x00000010L +#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x00000020L +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x00000040L +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x00000080L +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x00000100L +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x00000200L +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x00000400L +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x00000800L +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x00001000L +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x00002000L +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x00004000L +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x00008000L +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x00010000L +#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x00040000L +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x00080000L +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x00100000L +#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x07000000L +#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x08000000L +#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000L +#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK 0x20000000L +#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000L +#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK 0x80000000L +//PCIE_STRAP_MISC +#define PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT 0x0 +#define PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT 0x1 +#define PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT 0x2 +#define PCIE_STRAP_MISC__STRAP_NPEM_EN__SHIFT 0x3 +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 +#define PCIE_STRAP_MISC__STRAP_32GT_EN__SHIFT 0x5 +#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT 0x6 +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f +#define PCIE_STRAP_MISC__STRAP_DLF_EN_MASK 0x00000001L +#define PCIE_STRAP_MISC__STRAP_16GT_EN_MASK 0x00000002L +#define PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK 0x00000004L +#define PCIE_STRAP_MISC__STRAP_NPEM_EN_MASK 0x00000008L +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x00000010L +#define PCIE_STRAP_MISC__STRAP_32GT_EN_MASK 0x00000020L +#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK 0x00000040L +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000L +//PCIE_STRAP_MISC2 +#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0 +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT 0x5 +#define PCIE_STRAP_MISC2__STRAP_GEN5_COMPLIANCE__SHIFT 0x7 +#define PCIE_STRAP_MISC2__STRAP_DRS_SUPPORTED__SHIFT 0x8 +#define PCIE_STRAP_MISC2__STRAP_FRS_SUPPORTED__SHIFT 0x9 +#define PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_EN__SHIFT 0xa +#define PCIE_STRAP_MISC2__STRAP_RTR_EN__SHIFT 0xb +#define PCIE_STRAP_MISC2__STRAP_IMMEDIATE_READINESS_EN__SHIFT 0xc +#define PCIE_STRAP_MISC2__STRAP_RTR_RESET_TIME__SHIFT 0xd +#define PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_MAX_DEPTH__SHIFT 0x10 +#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x00000001L +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x00000008L +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK 0x00000020L +#define PCIE_STRAP_MISC2__STRAP_GEN5_COMPLIANCE_MASK 0x00000080L +#define PCIE_STRAP_MISC2__STRAP_DRS_SUPPORTED_MASK 0x00000100L +#define PCIE_STRAP_MISC2__STRAP_FRS_SUPPORTED_MASK 0x00000200L +#define PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_EN_MASK 0x00000400L +#define PCIE_STRAP_MISC2__STRAP_RTR_EN_MASK 0x00000800L +#define PCIE_STRAP_MISC2__STRAP_IMMEDIATE_READINESS_EN_MASK 0x00001000L +#define PCIE_STRAP_MISC2__STRAP_RTR_RESET_TIME_MASK 0x00006000L +#define PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_MAX_DEPTH_MASK 0x00030000L +//PCIE_STRAP_PI +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L +//PCIE_STRAP_I2C_BD +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007FL +//PCIE_PRBS_CLR +#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 +#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 +#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL +#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L +//PCIE_PRBS_STATUS1 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL +#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L +//PCIE_PRBS_STATUS2 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL +//PCIE_PRBS_FREERUN +#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 +#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL +//PCIE_PRBS_MISC +#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 +#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L +#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L +#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L +//PCIE_PRBS_USER_PATTERN +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL +//PCIE_PRBS_LO_BITCNT +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL +//PCIE_PRBS_HI_BITCNT +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL +//PCIE_PRBS_ERRCNT_0 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_1 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_2 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_3 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_4 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_5 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_6 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_7 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_8 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_9 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_10 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_11 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_12 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_13 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_14 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_15 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL +//SWRST_COMMAND_STATUS +#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 +#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 +#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 +#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 +#define SWRST_COMMAND_STATUS__PERST_ASRT__SHIFT 0x12 +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18 +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19 +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f +#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L +#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L +#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L +#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L +#define SWRST_COMMAND_STATUS__PERST_ASRT_MASK 0x00040000L +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L +//SWRST_GENERAL_CONTROL +#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 +#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 +#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 +#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 +#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 +#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa +#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc +#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT 0x11 +#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18 +#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19 +#define SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS__SHIFT 0x1a +#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L +#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L +#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL +#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L +#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L +#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L +#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L +#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK 0x00020000L +#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L +#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L +#define SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS_MASK 0x04000000L +//SWRST_COMMAND_0 +#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0 +#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8 +#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9 +#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa +#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb +#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc +#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd +#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe +#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf +#define SWRST_COMMAND_0__PORT8_CFG_RESET__SHIFT 0x10 +#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18 +#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19 +#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a +#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b +#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c +#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d +#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e +#define SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET__SHIFT 0x1f +#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L +#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L +#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L +#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L +#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L +#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L +#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L +#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L +#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L +#define SWRST_COMMAND_0__PORT8_CFG_RESET_MASK 0x00010000L +#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L +#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L +#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L +#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L +#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L +#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L +#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L +#define SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET_MASK 0x80000000L +//SWRST_COMMAND_1 +#define SWRST_COMMAND_1__RESETPCS0__SHIFT 0x0 +#define SWRST_COMMAND_1__RESETPCS1__SHIFT 0x1 +#define SWRST_COMMAND_1__RESETPCS2__SHIFT 0x2 +#define SWRST_COMMAND_1__RESETPCS3__SHIFT 0x3 +#define SWRST_COMMAND_1__RESETPCS4__SHIFT 0x4 +#define SWRST_COMMAND_1__RESETPCS5__SHIFT 0x5 +#define SWRST_COMMAND_1__RESETPCS6__SHIFT 0x6 +#define SWRST_COMMAND_1__RESETPCS7__SHIFT 0x7 +#define SWRST_COMMAND_1__RESETPCS8__SHIFT 0x8 +#define SWRST_COMMAND_1__RESETPCS9__SHIFT 0x9 +#define SWRST_COMMAND_1__RESETPCS10__SHIFT 0xa +#define SWRST_COMMAND_1__RESETPCS11__SHIFT 0xb +#define SWRST_COMMAND_1__RESETPCS12__SHIFT 0xc +#define SWRST_COMMAND_1__RESETPCS13__SHIFT 0xd +#define SWRST_COMMAND_1__RESETPCS14__SHIFT 0xe +#define SWRST_COMMAND_1__RESETPCS15__SHIFT 0xf +#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15 +#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19 +#define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a +#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b +#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c +#define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d +#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e +#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f +#define SWRST_COMMAND_1__RESETPCS0_MASK 0x00000001L +#define SWRST_COMMAND_1__RESETPCS1_MASK 0x00000002L +#define SWRST_COMMAND_1__RESETPCS2_MASK 0x00000004L +#define SWRST_COMMAND_1__RESETPCS3_MASK 0x00000008L +#define SWRST_COMMAND_1__RESETPCS4_MASK 0x00000010L +#define SWRST_COMMAND_1__RESETPCS5_MASK 0x00000020L +#define SWRST_COMMAND_1__RESETPCS6_MASK 0x00000040L +#define SWRST_COMMAND_1__RESETPCS7_MASK 0x00000080L +#define SWRST_COMMAND_1__RESETPCS8_MASK 0x00000100L +#define SWRST_COMMAND_1__RESETPCS9_MASK 0x00000200L +#define SWRST_COMMAND_1__RESETPCS10_MASK 0x00000400L +#define SWRST_COMMAND_1__RESETPCS11_MASK 0x00000800L +#define SWRST_COMMAND_1__RESETPCS12_MASK 0x00001000L +#define SWRST_COMMAND_1__RESETPCS13_MASK 0x00002000L +#define SWRST_COMMAND_1__RESETPCS14_MASK 0x00004000L +#define SWRST_COMMAND_1__RESETPCS15_MASK 0x00008000L +#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L +#define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L +#define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L +#define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L +#define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L +#define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L +#define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L +#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L +//SWRST_CONTROL_0 +#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0 +#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8 +#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9 +#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa +#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb +#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc +#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd +#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe +#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf +#define SWRST_CONTROL_0__PORT8_CFG_RCEN__SHIFT 0x10 +#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18 +#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19 +#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a +#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b +#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c +#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d +#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e +#define SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN__SHIFT 0x1f +#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L +#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L +#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L +#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L +#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L +#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L +#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L +#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L +#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L +#define SWRST_CONTROL_0__PORT8_CFG_RCEN_MASK 0x00010000L +#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L +#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L +#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L +#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L +#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L +#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L +#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L +#define SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN_MASK 0x80000000L +//SWRST_CONTROL_1 +#define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT 0x0 +#define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT 0x1 +#define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT 0x2 +#define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT 0x3 +#define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT 0x4 +#define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT 0x5 +#define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT 0x6 +#define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT 0x7 +#define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT 0x8 +#define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT 0x9 +#define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT 0xa +#define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT 0xb +#define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT 0xc +#define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT 0xd +#define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT 0xe +#define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT 0xf +#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15 +#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19 +#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a +#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b +#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c +#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d +#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e +#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f +#define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK 0x00000001L +#define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK 0x00000002L +#define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK 0x00000004L +#define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK 0x00000008L +#define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK 0x00000010L +#define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK 0x00000020L +#define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK 0x00000040L +#define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK 0x00000080L +#define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK 0x00000100L +#define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK 0x00000200L +#define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK 0x00000400L +#define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK 0x00000800L +#define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK 0x00001000L +#define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK 0x00002000L +#define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK 0x00004000L +#define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK 0x00008000L +#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L +#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L +#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L +#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L +#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L +#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L +#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L +#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L +//SWRST_CONTROL_2 +#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0 +#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8 +#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9 +#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa +#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb +#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc +#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd +#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe +#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf +#define SWRST_CONTROL_2__PORT8_CFG_ATEN__SHIFT 0x10 +#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18 +#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19 +#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a +#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b +#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c +#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d +#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e +#define SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN__SHIFT 0x1f +#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L +#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L +#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L +#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L +#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L +#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L +#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L +#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L +#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L +#define SWRST_CONTROL_2__PORT8_CFG_ATEN_MASK 0x00010000L +#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L +#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L +#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L +#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L +#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L +#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L +#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L +#define SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN_MASK 0x80000000L +//SWRST_CONTROL_3 +#define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT 0x0 +#define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT 0x1 +#define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT 0x2 +#define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT 0x3 +#define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT 0x4 +#define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT 0x5 +#define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT 0x6 +#define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT 0x7 +#define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT 0x8 +#define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT 0x9 +#define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT 0xa +#define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT 0xb +#define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT 0xc +#define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT 0xd +#define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT 0xe +#define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT 0xf +#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15 +#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19 +#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a +#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b +#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c +#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d +#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e +#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f +#define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK 0x00000001L +#define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK 0x00000002L +#define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK 0x00000004L +#define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK 0x00000008L +#define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK 0x00000010L +#define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK 0x00000020L +#define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK 0x00000040L +#define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK 0x00000080L +#define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK 0x00000100L +#define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK 0x00000200L +#define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK 0x00000400L +#define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK 0x00000800L +#define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK 0x00001000L +#define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK 0x00002000L +#define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK 0x00004000L +#define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK 0x00008000L +#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L +#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L +#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L +#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L +#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L +#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L +#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L +#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L +//SWRST_CONTROL_4 +#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0 +#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8 +#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9 +#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa +#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb +#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc +#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd +#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe +#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf +#define SWRST_CONTROL_4__PORT8_CFG_WREN__SHIFT 0x10 +#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18 +#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19 +#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a +#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b +#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c +#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d +#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e +#define SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN__SHIFT 0x1f +#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L +#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L +#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L +#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L +#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L +#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L +#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L +#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L +#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L +#define SWRST_CONTROL_4__PORT8_CFG_WREN_MASK 0x00010000L +#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L +#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L +#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L +#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L +#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L +#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L +#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L +#define SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN_MASK 0x80000000L +//SWRST_CONTROL_5 +#define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT 0x0 +#define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT 0x1 +#define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT 0x2 +#define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT 0x3 +#define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT 0x4 +#define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT 0x5 +#define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT 0x6 +#define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT 0x7 +#define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT 0x8 +#define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT 0x9 +#define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT 0xa +#define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT 0xb +#define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT 0xc +#define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT 0xd +#define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT 0xe +#define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT 0xf +#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15 +#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19 +#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a +#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b +#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c +#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d +#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e +#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f +#define SWRST_CONTROL_5__PCSRESET0_WREN_MASK 0x00000001L +#define SWRST_CONTROL_5__PCSRESET1_WREN_MASK 0x00000002L +#define SWRST_CONTROL_5__PCSRESET2_WREN_MASK 0x00000004L +#define SWRST_CONTROL_5__PCSRESET3_WREN_MASK 0x00000008L +#define SWRST_CONTROL_5__PCSRESET4_WREN_MASK 0x00000010L +#define SWRST_CONTROL_5__PCSRESET5_WREN_MASK 0x00000020L +#define SWRST_CONTROL_5__PCSRESET6_WREN_MASK 0x00000040L +#define SWRST_CONTROL_5__PCSRESET7_WREN_MASK 0x00000080L +#define SWRST_CONTROL_5__PCSRESET8_WREN_MASK 0x00000100L +#define SWRST_CONTROL_5__PCSRESET9_WREN_MASK 0x00000200L +#define SWRST_CONTROL_5__PCSRESET10_WREN_MASK 0x00000400L +#define SWRST_CONTROL_5__PCSRESET11_WREN_MASK 0x00000800L +#define SWRST_CONTROL_5__PCSRESET12_WREN_MASK 0x00001000L +#define SWRST_CONTROL_5__PCSRESET13_WREN_MASK 0x00002000L +#define SWRST_CONTROL_5__PCSRESET14_WREN_MASK 0x00004000L +#define SWRST_CONTROL_5__PCSRESET15_WREN_MASK 0x00008000L +#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L +#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L +#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L +#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L +#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L +#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L +#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L +#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L +//SWRST_CONTROL_6 +#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0 +#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1 +#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2 +#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3 +#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4 +#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5 +#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6 +#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7 +#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8 +#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9 +#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa +#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L +#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L +#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L +#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L +#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L +#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L +#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L +#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L +#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L +#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L +#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L +//SWRST_EP_COMMAND_0 +#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0 +#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8 +#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9 +#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa +#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L +#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L +#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L +#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L +//SWRST_EP_CONTROL_0 +#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0 +#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8 +#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9 +#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa +#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L +#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L +#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L +#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L +//CPM_CONTROL +#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 +#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 +#define CPM_CONTROL__L1_PWR_GATE_ENABLE__SHIFT 0x2 +#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE__SHIFT 0x3 +#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE__SHIFT 0x4 +#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 +#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 +#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 +#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 +#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 +#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xb +#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE__SHIFT 0xd +#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xe +#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xf +#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0x10 +#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0x11 +#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x12 +#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG__SHIFT 0x15 +#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 +#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 +#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18 +#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT 0x19 +#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE__SHIFT 0x1a +#define CPM_CONTROL__PCIE_CORE_IDLE__SHIFT 0x1b +#define CPM_CONTROL__PCIE_LINK_IDLE__SHIFT 0x1c +#define CPM_CONTROL__PCIE_BUFFER_EMPTY__SHIFT 0x1d +#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY__SHIFT 0x1e +#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L +#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L +#define CPM_CONTROL__L1_PWR_GATE_ENABLE_MASK 0x00000004L +#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE_MASK 0x00000008L +#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE_MASK 0x00000010L +#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L +#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L +#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L +#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L +#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000600L +#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00001800L +#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE_MASK 0x00002000L +#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00004000L +#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00008000L +#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00010000L +#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00020000L +#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x001C0000L +#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG_MASK 0x00200000L +#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L +#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L +#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L +#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK 0x02000000L +#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE_MASK 0x04000000L +#define CPM_CONTROL__PCIE_CORE_IDLE_MASK 0x08000000L +#define CPM_CONTROL__PCIE_LINK_IDLE_MASK 0x10000000L +#define CPM_CONTROL__PCIE_BUFFER_EMPTY_MASK 0x20000000L +#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY_MASK 0xC0000000L +//CPM_SPLIT_CONTROL +#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE__SHIFT 0x0 +#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE_MASK 0x00000001L +//CPM_CONTROL_EXT +#define CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE__SHIFT 0x0 +#define CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE__SHIFT 0x1 +#define CPM_CONTROL_EXT__LCLK_DS_MODE__SHIFT 0x2 +#define CPM_CONTROL_EXT__LCLK_DS_ENABLE__SHIFT 0x3 +#define CPM_CONTROL_EXT__PG_STATE__SHIFT 0x4 +#define CPM_CONTROL_EXT__HOTPLUG_ALLOW_LCLK_GATING_EN__SHIFT 0x7 +#define CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE_MASK 0x00000001L +#define CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE_MASK 0x00000002L +#define CPM_CONTROL_EXT__LCLK_DS_MODE_MASK 0x00000004L +#define CPM_CONTROL_EXT__LCLK_DS_ENABLE_MASK 0x00000008L +#define CPM_CONTROL_EXT__PG_STATE_MASK 0x00000070L +#define CPM_CONTROL_EXT__HOTPLUG_ALLOW_LCLK_GATING_EN_MASK 0x00000080L +//SMN_APERTURE_ID_A +#define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT 0x0 +#define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT 0xc +#define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK 0x00000FFFL +#define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK 0x00FFF000L +//SMN_APERTURE_ID_B +#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0 +#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc +#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL +#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L +//LNCNT_CONTROL +#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x0 +#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x1 +#define LNCNT_CONTROL__CFG_LNC_BW_QUAN_THRD__SHIFT 0x2 +#define LNCNT_CONTROL__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x5 +#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000001L +#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000002L +#define LNCNT_CONTROL__CFG_LNC_BW_QUAN_THRD_MASK 0x0000001CL +#define LNCNT_CONTROL__CFG_LNC_CMN_QUAN_THRD_MASK 0x000000E0L +//SMU_INT_PIN_SHARING_PORT_INDICATOR +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT 0x0 +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT 0x10 +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK 0x0000FFFFL +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK 0xFFFF0000L +//PCIE_PGMST_CNTL +#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 +#define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 +#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT 0xe +#define PCIE_PGMST_CNTL__PG_EXIT_TIMER__SHIFT 0x10 +#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define PCIE_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L +#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK 0x0000C000L +#define PCIE_PGMST_CNTL__PG_EXIT_TIMER_MASK 0x00FF0000L +//PCIE_PGSLV_CNTL +#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//LC_CPM_CONTROL_0 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE__SHIFT 0x0 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE__SHIFT 0x1 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE__SHIFT 0x2 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE__SHIFT 0x3 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE__SHIFT 0x4 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE__SHIFT 0x5 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE__SHIFT 0x6 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE__SHIFT 0x7 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE__SHIFT 0x8 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE__SHIFT 0x9 +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE__SHIFT 0xa +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE__SHIFT 0xb +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE__SHIFT 0xc +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE__SHIFT 0xd +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE__SHIFT 0xe +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE__SHIFT 0xf +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE__SHIFT 0x10 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE__SHIFT 0x11 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE__SHIFT 0x12 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE__SHIFT 0x13 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE__SHIFT 0x14 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE__SHIFT 0x15 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE__SHIFT 0x16 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE__SHIFT 0x17 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE__SHIFT 0x18 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE__SHIFT 0x19 +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE__SHIFT 0x1a +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE__SHIFT 0x1b +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE__SHIFT 0x1c +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE__SHIFT 0x1d +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE__SHIFT 0x1e +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE__SHIFT 0x1f +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE_MASK 0x00000001L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE_MASK 0x00000002L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE_MASK 0x00000004L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE_MASK 0x00000008L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE_MASK 0x00000010L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE_MASK 0x00000020L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE_MASK 0x00000040L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE_MASK 0x00000080L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE_MASK 0x00000100L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE_MASK 0x00000200L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE_MASK 0x00000400L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE_MASK 0x00000800L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE_MASK 0x00001000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE_MASK 0x00002000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE_MASK 0x00004000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE_MASK 0x00008000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE_MASK 0x00010000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE_MASK 0x00020000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE_MASK 0x00040000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE_MASK 0x00080000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE_MASK 0x00100000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE_MASK 0x00200000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE_MASK 0x00400000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE_MASK 0x00800000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE_MASK 0x01000000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE_MASK 0x02000000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE_MASK 0x04000000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE_MASK 0x08000000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE_MASK 0x10000000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE_MASK 0x20000000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE_MASK 0x40000000L +#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE_MASK 0x80000000L +//LC_CPM_CONTROL_1 +#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY__SHIFT 0x0 +#define LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE__SHIFT 0xf +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE__SHIFT 0x10 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE__SHIFT 0x11 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE__SHIFT 0x12 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE__SHIFT 0x13 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE__SHIFT 0x14 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE__SHIFT 0x15 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE__SHIFT 0x16 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE__SHIFT 0x17 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE__SHIFT 0x18 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE__SHIFT 0x19 +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE__SHIFT 0x1a +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE__SHIFT 0x1b +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE__SHIFT 0x1c +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE__SHIFT 0x1d +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE__SHIFT 0x1e +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE__SHIFT 0x1f +#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY_MASK 0x00000007L +#define LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE_MASK 0x00008000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE_MASK 0x00010000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE_MASK 0x00020000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE_MASK 0x00040000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE_MASK 0x00080000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE_MASK 0x00100000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE_MASK 0x00200000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE_MASK 0x00400000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE_MASK 0x00800000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE_MASK 0x01000000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE_MASK 0x02000000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE_MASK 0x04000000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE_MASK 0x08000000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE_MASK 0x10000000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE_MASK 0x20000000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE_MASK 0x40000000L +#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE_MASK 0x80000000L +//PCIE_RXMARGIN_CONTROL_CAPABILITIES +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT 0x0 +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT 0x1 +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT 0x2 +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT 0x3 +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT 0x4 +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK 0x00000001L +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK 0x00000002L +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK 0x00000004L +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK 0x00000008L +#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK 0x00000010L +//PCIE_RXMARGIN_1_SETTINGS +#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT 0x0 +#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT 0x7 +#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT 0xd +#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT 0x14 +#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK 0x0000007FL +#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK 0x00001F80L +#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK 0x000FE000L +#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK 0x07F00000L +//PCIE_RXMARGIN_2_SETTINGS +#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT 0x0 +#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT 0x6 +#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT 0xc +#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT 0x13 +#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT 0x18 +#define PCIE_RXMARGIN_2_SETTINGS__ENABLE_PRECODING__SHIFT 0x1e +#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK 0x0000003FL +#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK 0x00000FC0L +#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK 0x0007F000L +#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK 0x00F80000L +#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK 0x3F000000L +#define PCIE_RXMARGIN_2_SETTINGS__ENABLE_PRECODING_MASK 0x40000000L +//SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO +#define SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__DPC_INT_STATUS__SHIFT 0x0 +#define SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__PD_INT_STATUS__SHIFT 0x10 +#define SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__DPC_INT_STATUS_MASK 0x0000FFFFL +#define SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__PD_INT_STATUS_MASK 0xFFFF0000L +//PCIE_TX_LAST_TLP0 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL +//PCIE_TX_LAST_TLP1 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL +//PCIE_TX_LAST_TLP2 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL +//PCIE_TX_LAST_TLP3 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL +//PCIE_TX_TRACKING_ADDR_LO +#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2 +#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL +//PCIE_TX_TRACKING_ADDR_HI +#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0 +#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL +//PCIE_TX_TRACKING_CTRL_STATUS +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0 +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1 +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8 +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L +//PCIE_TX_CTRL_4 +#define PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW__SHIFT 0x0 +#define PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW_MASK 0x0000000FL +//PCIE_TX_STATUS +#define PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT 0x0 +#define PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT 0x1 +#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT 0x2 +#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT 0x3 +#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT 0x4 +#define PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT 0x5 +#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT 0x6 +#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT 0x7 +#define PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT 0x8 +#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT 0x9 +#define PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT 0xa +#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT 0xb +#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT 0xc +#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT 0xd +#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT 0xe +#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT 0xf +#define PCIE_TX_STATUS__TX_MST_MEM_READY_MASK 0x00000001L +#define PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK 0x00000002L +#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK 0x00000004L +#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK 0x00000008L +#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK 0x00000010L +#define PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK 0x00000020L +#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK 0x00000040L +#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK 0x00000080L +#define PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK 0x00000100L +#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK 0x00000200L +#define PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK 0x00000400L +#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK 0x00000800L +#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK 0x00001000L +#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK 0x00002000L +#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK 0x00004000L +#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK 0x00008000L +//PCIE_TX_F0_ATTR_CNTL +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L +//PCIE_TX_SWUS_ATTR_CNTL +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L +//PCIE_MST_CTRL_1 +#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT__SHIFT 0x0 +#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN__SHIFT 0x8 +#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS__SHIFT 0x9 +#define PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS__SHIFT 0xa +#define PCIE_MST_CTRL_1__MST_SDP_CREDITS_LIVE_OVERRIDE_DIS__SHIFT 0xe +#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN__SHIFT 0xf +#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT__SHIFT 0x10 +#define PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS__SHIFT 0x18 +#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT_MASK 0x000000FFL +#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN_MASK 0x00000100L +#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS_MASK 0x00000200L +#define PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS_MASK 0x00000400L +#define PCIE_MST_CTRL_1__MST_SDP_CREDITS_LIVE_OVERRIDE_DIS_MASK 0x00004000L +#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN_MASK 0x00008000L +#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT_MASK 0x00FF0000L +#define PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS_MASK 0xFF000000L +//PCIE_HIP_REG0 +#define PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI__SHIFT 0x0 +#define PCIE_HIP_REG0__CI_HIP_APT0_ENABLE__SHIFT 0x18 +#define PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE__SHIFT 0x19 +#define PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE__SHIFT 0x1a +#define PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE__SHIFT 0x1d +#define PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI_MASK 0x000FFFFFL +#define PCIE_HIP_REG0__CI_HIP_APT0_ENABLE_MASK 0x01000000L +#define PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE_MASK 0x02000000L +#define PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE_MASK 0x1C000000L +#define PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE_MASK 0x60000000L +//PCIE_HIP_REG1 +#define PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO__SHIFT 0x0 +#define PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO_MASK 0xFFFFFFFFL +//PCIE_HIP_REG2 +#define PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI__SHIFT 0x0 +#define PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI_MASK 0x000FFFFFL +//PCIE_HIP_REG3 +#define PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO__SHIFT 0x0 +#define PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO_MASK 0xFFFFFFFFL +//PCIE_HIP_REG4 +#define PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI__SHIFT 0x0 +#define PCIE_HIP_REG4__CI_HIP_APT1_ENABLE__SHIFT 0x18 +#define PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE__SHIFT 0x19 +#define PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE__SHIFT 0x1a +#define PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE__SHIFT 0x1d +#define PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI_MASK 0x000FFFFFL +#define PCIE_HIP_REG4__CI_HIP_APT1_ENABLE_MASK 0x01000000L +#define PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE_MASK 0x02000000L +#define PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE_MASK 0x1C000000L +#define PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE_MASK 0x60000000L +//PCIE_HIP_REG5 +#define PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO__SHIFT 0x0 +#define PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO_MASK 0xFFFFFFFFL +//PCIE_HIP_REG6 +#define PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI__SHIFT 0x0 +#define PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI_MASK 0x000FFFFFL +//PCIE_HIP_REG7 +#define PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO__SHIFT 0x0 +#define PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO_MASK 0xFFFFFFFFL +//PCIE_HIP_REG8 +#define PCIE_HIP_REG8__CI_HIP_MASK__SHIFT 0x0 +#define PCIE_HIP_REG8__CI_HIP_MASK_MASK 0x000FFFFFL +//SMU_PCIE_FENCED1_REG +#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x0 +#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x00000001L +//SMU_PCIE_FENCED2_REG +#define SMU_PCIE_FENCED2_REG__MP0_PCIE_OVERCLOCKING_EN__SHIFT 0x0 +#define SMU_PCIE_FENCED2_REG__MP0_PCIE_OVERCLOCKING_EN_MASK 0x00000001L +//PCIE_PERF_CNTL_TXCLK7 +#define PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK7__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK7__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK7__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK7__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK7__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK7__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK7 +#define PCIE_PERF_COUNT0_TXCLK7__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK7__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK7 +#define PCIE_PERF_COUNT1_TXCLK7__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK7__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK8 +#define PCIE_PERF_CNTL_TXCLK8__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK8__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK8__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK8__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK8__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK8__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK8__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK8__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK8 +#define PCIE_PERF_COUNT0_TXCLK8__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK8__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK8 +#define PCIE_PERF_COUNT1_TXCLK8__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK8__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK9 +#define PCIE_PERF_CNTL_TXCLK9__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK9__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK9__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK9__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK9__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK9__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK9__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK9__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK9 +#define PCIE_PERF_COUNT0_TXCLK9__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK9__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK9 +#define PCIE_PERF_COUNT1_TXCLK9__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK9__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK10 +#define PCIE_PERF_CNTL_TXCLK10__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK10__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK10__COUNTER0_FULL__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK10__COUNTER1_FULL__SHIFT 0x11 +#define PCIE_PERF_CNTL_TXCLK10__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK10__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK10__COUNTER0_FULL_MASK 0x00010000L +#define PCIE_PERF_CNTL_TXCLK10__COUNTER1_FULL_MASK 0x00020000L +//PCIE_PERF_COUNT0_TXCLK10 +#define PCIE_PERF_COUNT0_TXCLK10__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK10__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK10 +#define PCIE_PERF_COUNT1_TXCLK10__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK10__COUNTER1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +//PSWUSCFG0_SUB_BUS_NUMBER_LATENCY +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//PSWUSCFG0_IO_BASE_LIMIT +#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//PSWUSCFG0_SECONDARY_STATUS +#define PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//PSWUSCFG0_MEM_BASE_LIMIT +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//PSWUSCFG0_PREF_BASE_LIMIT +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//PSWUSCFG0_PREF_BASE_UPPER +#define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//PSWUSCFG0_PREF_LIMIT_UPPER +#define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//PSWUSCFG0_IO_BASE_LIMIT_HI +#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//PSWUSCFG0_SSID_CAP_LIST +#define PSWUSCFG0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_SSID_CAP +#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//SLOT_CAP +#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//SLOT_CNTL +#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//SLOT_STATUS +#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//SLOT_CAP2 +#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//SLOT_CNTL2 +#define SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//SLOT_STATUS2 +#define SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_SSID_CAP +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_COMMAND +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_STATUS +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_LATENCY +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_HEADER +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BIST +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_HEADER +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BIST +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_HEADER +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BIST +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_COMMAND +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_HEADER +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BIST +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_COMMAND +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_HEADER +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BIST +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_COMMAND +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_HEADER +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BIST +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_COMMAND +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_HEADER +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BIST +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_COMMAND +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_HEADER +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BIST +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_COMMAND +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_HEADER +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BIST +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_COMMAND +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF8_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_LATENCY +#define BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_HEADER +#define BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF8_BIST +#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF8_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF8_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_COMMAND +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF9_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_LATENCY +#define BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_HEADER +#define BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF9_BIST +#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF9_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF9_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_COMMAND +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF10_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_LATENCY +#define BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_HEADER +#define BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF10_BIST +#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF10_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF10_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_COMMAND +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF11_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_LATENCY +#define BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_HEADER +#define BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF11_BIST +#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF11_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF11_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_COMMAND +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF12_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_LATENCY +#define BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_HEADER +#define BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF12_BIST +#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF12_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF12_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_COMMAND +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF13_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_LATENCY +#define BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_HEADER +#define BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF13_BIST +#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF13_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF13_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_COMMAND +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF14_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_LATENCY +#define BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_HEADER +#define BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF14_BIST +#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF14_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF14_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_COMMAND +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF15_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_LATENCY +#define BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_HEADER +#define BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF15_BIST +#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF15_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF15_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_COMMAND +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_STATUS +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_REVISION_ID +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_LATENCY +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_HEADER +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BIST +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_CAP_PTR +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PMI_CAP +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_LINK_CAP +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +//BIF_CFG_DEV0_EPF2_VENDOR_ID +#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_DEVICE_ID +#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_COMMAND +#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_STATUS +#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_REVISION_ID +#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_SUB_CLASS +#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_BASE_CLASS +#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_CACHE_LINE +#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_LATENCY +#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_HEADER +#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF2_BIST +#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF2_CAP_PTR +#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_MIN_GRANT +#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_PMI_CAP +#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_SBRN +#define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_FLADJ +#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK 0x3FL +#define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF2_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_PCIE_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF2_LINK_CAP +#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_LINK_CNTL +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF2_LINK_STATUS +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_MSI_MASK +#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_MSI_PENDING +#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_MSIX_PBA +#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +//BIF_CFG_DEV0_EPF3_VENDOR_ID +#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_DEVICE_ID +#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_COMMAND +#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_STATUS +#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_REVISION_ID +#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_SUB_CLASS +#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_BASE_CLASS +#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_CACHE_LINE +#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_LATENCY +#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_HEADER +#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF3_BIST +#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF3_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_ADAPTER_ID +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF3_CAP_PTR +#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_MIN_GRANT +#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_MAX_LATENCY +#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF3_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_PMI_CAP +#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_SBRN +#define BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_FLADJ +#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK 0x3FL +#define BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF3_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_PCIE_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF3_DEVICE_CAP +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF3_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF3_LINK_CAP +#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_LINK_CNTL +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF3_LINK_STATUS +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_LINK_CAP2 +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF3_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_MSI_MASK +#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_MSI_PENDING +#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_MSIX_TABLE +#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_MSIX_PBA +#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC +//RCC_DEV0_1_RCC_VDM_SUPPORT +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_1_RCC_BUS_CNTL +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_1_RCC_CMN_LINK_CNTL +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_1_RCC_MH_ARB_CNTL +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +//RCC_EP_DEV0_1_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_1_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +//RCC_DWN_DEV0_1_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_1_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + + + + + +//PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT32_ADDR_LO +#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT32_ADDR_HI +#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT32_MSG_DATA +#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT32_CONTROL +#define PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT33_ADDR_LO +#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT33_ADDR_HI +#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT33_MSG_DATA +#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT33_CONTROL +#define PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT34_ADDR_LO +#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT34_ADDR_HI +#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT34_MSG_DATA +#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT34_CONTROL +#define PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT35_ADDR_LO +#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT35_ADDR_HI +#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT35_MSG_DATA +#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT35_CONTROL +#define PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT36_ADDR_LO +#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT36_ADDR_HI +#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT36_MSG_DATA +#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT36_CONTROL +#define PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT37_ADDR_LO +#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT37_ADDR_HI +#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT37_MSG_DATA +#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT37_CONTROL +#define PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT38_ADDR_LO +#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT38_ADDR_HI +#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT38_MSG_DATA +#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT38_CONTROL +#define PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT39_ADDR_LO +#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT39_ADDR_HI +#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT39_MSG_DATA +#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT39_CONTROL +#define PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT40_ADDR_LO +#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT40_ADDR_HI +#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT40_MSG_DATA +#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT40_CONTROL +#define PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT41_ADDR_LO +#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT41_ADDR_HI +#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT41_MSG_DATA +#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT41_CONTROL +#define PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT42_ADDR_LO +#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT42_ADDR_HI +#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT42_MSG_DATA +#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT42_CONTROL +#define PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT43_ADDR_LO +#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT43_ADDR_HI +#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT43_MSG_DATA +#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT43_CONTROL +#define PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT44_ADDR_LO +#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT44_ADDR_HI +#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT44_MSG_DATA +#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT44_CONTROL +#define PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT45_ADDR_LO +#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT45_ADDR_HI +#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT45_MSG_DATA +#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT45_CONTROL +#define PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT46_ADDR_LO +#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT46_ADDR_HI +#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT46_MSG_DATA +#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT46_CONTROL +#define PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT47_ADDR_LO +#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT47_ADDR_HI +#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT47_MSG_DATA +#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT47_CONTROL +#define PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT48_ADDR_LO +#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT48_ADDR_HI +#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT48_MSG_DATA +#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT48_CONTROL +#define PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT49_ADDR_LO +#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT49_ADDR_HI +#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT49_MSG_DATA +#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT49_CONTROL +#define PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT50_ADDR_LO +#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT50_ADDR_HI +#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT50_MSG_DATA +#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT50_CONTROL +#define PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT51_ADDR_LO +#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT51_ADDR_HI +#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT51_MSG_DATA +#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT51_CONTROL +#define PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT52_ADDR_LO +#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT52_ADDR_HI +#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT52_MSG_DATA +#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT52_CONTROL +#define PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT53_ADDR_LO +#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT53_ADDR_HI +#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT53_MSG_DATA +#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT53_CONTROL +#define PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT54_ADDR_LO +#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT54_ADDR_HI +#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT54_MSG_DATA +#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT54_CONTROL +#define PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT55_ADDR_LO +#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT55_ADDR_HI +#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT55_MSG_DATA +#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT55_CONTROL +#define PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT56_ADDR_LO +#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT56_ADDR_HI +#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT56_MSG_DATA +#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT56_CONTROL +#define PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT57_ADDR_LO +#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT57_ADDR_HI +#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT57_MSG_DATA +#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT57_CONTROL +#define PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT58_ADDR_LO +#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT58_ADDR_HI +#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT58_MSG_DATA +#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT58_CONTROL +#define PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT59_ADDR_LO +#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT59_ADDR_HI +#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT59_MSG_DATA +#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT59_CONTROL +#define PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT60_ADDR_LO +#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT60_ADDR_HI +#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT60_MSG_DATA +#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT60_CONTROL +#define PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT61_ADDR_LO +#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT61_ADDR_HI +#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT61_MSG_DATA +#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT61_CONTROL +#define PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT62_ADDR_LO +#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT62_ADDR_HI +#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT62_MSG_DATA +#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT62_CONTROL +#define PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT63_ADDR_LO +#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT63_ADDR_HI +#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT63_MSG_DATA +#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT63_CONTROL +#define PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT64_ADDR_LO +#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT64_ADDR_HI +#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT64_MSG_DATA +#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT64_CONTROL +#define PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT65_ADDR_LO +#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT65_ADDR_HI +#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT65_MSG_DATA +#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT65_CONTROL +#define PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT66_ADDR_LO +#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT66_ADDR_HI +#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT66_MSG_DATA +#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT66_CONTROL +#define PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT67_ADDR_LO +#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT67_ADDR_HI +#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT67_MSG_DATA +#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT67_CONTROL +#define PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT68_ADDR_LO +#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT68_ADDR_HI +#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT68_MSG_DATA +#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT68_CONTROL +#define PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT69_ADDR_LO +#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT69_ADDR_HI +#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT69_MSG_DATA +#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT69_CONTROL +#define PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT70_ADDR_LO +#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT70_ADDR_HI +#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT70_MSG_DATA +#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT70_CONTROL +#define PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT71_ADDR_LO +#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT71_ADDR_HI +#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT71_MSG_DATA +#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT71_CONTROL +#define PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT72_ADDR_LO +#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT72_ADDR_HI +#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT72_MSG_DATA +#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT72_CONTROL +#define PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT73_ADDR_LO +#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT73_ADDR_HI +#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT73_MSG_DATA +#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT73_CONTROL +#define PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT74_ADDR_LO +#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT74_ADDR_HI +#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT74_MSG_DATA +#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT74_CONTROL +#define PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT75_ADDR_LO +#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT75_ADDR_HI +#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT75_MSG_DATA +#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT75_CONTROL +#define PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT76_ADDR_LO +#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT76_ADDR_HI +#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT76_MSG_DATA +#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT76_CONTROL +#define PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT77_ADDR_LO +#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT77_ADDR_HI +#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT77_MSG_DATA +#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT77_CONTROL +#define PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT78_ADDR_LO +#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT78_ADDR_HI +#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT78_MSG_DATA +#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT78_CONTROL +#define PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT79_ADDR_LO +#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT79_ADDR_HI +#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT79_MSG_DATA +#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT79_CONTROL +#define PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT80_ADDR_LO +#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT80_ADDR_HI +#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT80_MSG_DATA +#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT80_CONTROL +#define PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT81_ADDR_LO +#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT81_ADDR_HI +#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT81_MSG_DATA +#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT81_CONTROL +#define PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT82_ADDR_LO +#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT82_ADDR_HI +#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT82_MSG_DATA +#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT82_CONTROL +#define PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT83_ADDR_LO +#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT83_ADDR_HI +#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT83_MSG_DATA +#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT83_CONTROL +#define PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT84_ADDR_LO +#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT84_ADDR_HI +#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT84_MSG_DATA +#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT84_CONTROL +#define PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT85_ADDR_LO +#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT85_ADDR_HI +#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT85_MSG_DATA +#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT85_CONTROL +#define PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT86_ADDR_LO +#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT86_ADDR_HI +#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT86_MSG_DATA +#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT86_CONTROL +#define PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT87_ADDR_LO +#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT87_ADDR_HI +#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT87_MSG_DATA +#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT87_CONTROL +#define PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT88_ADDR_LO +#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT88_ADDR_HI +#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT88_MSG_DATA +#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT88_CONTROL +#define PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT89_ADDR_LO +#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT89_ADDR_HI +#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT89_MSG_DATA +#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT89_CONTROL +#define PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT90_ADDR_LO +#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT90_ADDR_HI +#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT90_MSG_DATA +#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT90_CONTROL +#define PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT91_ADDR_LO +#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT91_ADDR_HI +#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT91_MSG_DATA +#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT91_CONTROL +#define PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT92_ADDR_LO +#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT92_ADDR_HI +#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT92_MSG_DATA +#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT92_CONTROL +#define PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT93_ADDR_LO +#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT93_ADDR_HI +#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT93_MSG_DATA +#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT93_CONTROL +#define PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT94_ADDR_LO +#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT94_ADDR_HI +#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT94_MSG_DATA +#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT94_CONTROL +#define PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT95_ADDR_LO +#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT95_ADDR_HI +#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT95_MSG_DATA +#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT95_CONTROL +#define PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT96_ADDR_LO +#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT96_ADDR_HI +#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT96_MSG_DATA +#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT96_CONTROL +#define PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT97_ADDR_LO +#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT97_ADDR_HI +#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT97_MSG_DATA +#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT97_CONTROL +#define PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT98_ADDR_LO +#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT98_ADDR_HI +#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT98_MSG_DATA +#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT98_CONTROL +#define PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT99_ADDR_LO +#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT99_ADDR_HI +#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT99_MSG_DATA +#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT99_CONTROL +#define PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT100_ADDR_LO +#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT100_ADDR_HI +#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT100_MSG_DATA +#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT100_CONTROL +#define PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT101_ADDR_LO +#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT101_ADDR_HI +#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT101_MSG_DATA +#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT101_CONTROL +#define PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT102_ADDR_LO +#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT102_ADDR_HI +#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT102_MSG_DATA +#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT102_CONTROL +#define PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT103_ADDR_LO +#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT103_ADDR_HI +#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT103_MSG_DATA +#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT103_CONTROL +#define PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT104_ADDR_LO +#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT104_ADDR_HI +#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT104_MSG_DATA +#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT104_CONTROL +#define PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT105_ADDR_LO +#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT105_ADDR_HI +#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT105_MSG_DATA +#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT105_CONTROL +#define PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT106_ADDR_LO +#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT106_ADDR_HI +#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT106_MSG_DATA +#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT106_CONTROL +#define PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT107_ADDR_LO +#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT107_ADDR_HI +#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT107_MSG_DATA +#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT107_CONTROL +#define PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT108_ADDR_LO +#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT108_ADDR_HI +#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT108_MSG_DATA +#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT108_CONTROL +#define PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT109_ADDR_LO +#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT109_ADDR_HI +#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT109_MSG_DATA +#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT109_CONTROL +#define PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT110_ADDR_LO +#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT110_ADDR_HI +#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT110_MSG_DATA +#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT110_CONTROL +#define PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT111_ADDR_LO +#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT111_ADDR_HI +#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT111_MSG_DATA +#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT111_CONTROL +#define PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT112_ADDR_LO +#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT112_ADDR_HI +#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT112_MSG_DATA +#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT112_CONTROL +#define PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT113_ADDR_LO +#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT113_ADDR_HI +#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT113_MSG_DATA +#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT113_CONTROL +#define PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT114_ADDR_LO +#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT114_ADDR_HI +#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT114_MSG_DATA +#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT114_CONTROL +#define PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT115_ADDR_LO +#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT115_ADDR_HI +#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT115_MSG_DATA +#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT115_CONTROL +#define PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT116_ADDR_LO +#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT116_ADDR_HI +#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT116_MSG_DATA +#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT116_CONTROL +#define PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT117_ADDR_LO +#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT117_ADDR_HI +#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT117_MSG_DATA +#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT117_CONTROL +#define PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT118_ADDR_LO +#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT118_ADDR_HI +#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT118_MSG_DATA +#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT118_CONTROL +#define PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT119_ADDR_LO +#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT119_ADDR_HI +#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT119_MSG_DATA +#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT119_CONTROL +#define PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT120_ADDR_LO +#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT120_ADDR_HI +#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT120_MSG_DATA +#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT120_CONTROL +#define PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT121_ADDR_LO +#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT121_ADDR_HI +#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT121_MSG_DATA +#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT121_CONTROL +#define PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT122_ADDR_LO +#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT122_ADDR_HI +#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT122_MSG_DATA +#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT122_CONTROL +#define PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT123_ADDR_LO +#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT123_ADDR_HI +#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT123_MSG_DATA +#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT123_CONTROL +#define PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT124_ADDR_LO +#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT124_ADDR_HI +#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT124_MSG_DATA +#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT124_CONTROL +#define PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT125_ADDR_LO +#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT125_ADDR_HI +#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT125_MSG_DATA +#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT125_CONTROL +#define PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT126_ADDR_LO +#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT126_ADDR_HI +#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT126_MSG_DATA +#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT126_CONTROL +#define PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT127_ADDR_LO +#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT127_ADDR_HI +#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT127_MSG_DATA +#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT127_CONTROL +#define PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT128_ADDR_LO +#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT128_ADDR_HI +#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT128_MSG_DATA +#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT128_CONTROL +#define PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT129_ADDR_LO +#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT129_ADDR_HI +#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT129_MSG_DATA +#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT129_CONTROL +#define PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT130_ADDR_LO +#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT130_ADDR_HI +#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT130_MSG_DATA +#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT130_CONTROL +#define PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT131_ADDR_LO +#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT131_ADDR_HI +#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT131_MSG_DATA +#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT131_CONTROL +#define PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT132_ADDR_LO +#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT132_ADDR_HI +#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT132_MSG_DATA +#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT132_CONTROL +#define PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT133_ADDR_LO +#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT133_ADDR_HI +#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT133_MSG_DATA +#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT133_CONTROL +#define PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT134_ADDR_LO +#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT134_ADDR_HI +#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT134_MSG_DATA +#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT134_CONTROL +#define PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT135_ADDR_LO +#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT135_ADDR_HI +#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT135_MSG_DATA +#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT135_CONTROL +#define PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT136_ADDR_LO +#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT136_ADDR_HI +#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT136_MSG_DATA +#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT136_CONTROL +#define PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT137_ADDR_LO +#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT137_ADDR_HI +#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT137_MSG_DATA +#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT137_CONTROL +#define PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT138_ADDR_LO +#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT138_ADDR_HI +#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT138_MSG_DATA +#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT138_CONTROL +#define PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT139_ADDR_LO +#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT139_ADDR_HI +#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT139_MSG_DATA +#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT139_CONTROL +#define PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT140_ADDR_LO +#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT140_ADDR_HI +#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT140_MSG_DATA +#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT140_CONTROL +#define PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT141_ADDR_LO +#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT141_ADDR_HI +#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT141_MSG_DATA +#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT141_CONTROL +#define PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT142_ADDR_LO +#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT142_ADDR_HI +#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT142_MSG_DATA +#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT142_CONTROL +#define PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT143_ADDR_LO +#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT143_ADDR_HI +#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT143_MSG_DATA +#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT143_CONTROL +#define PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT144_ADDR_LO +#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT144_ADDR_HI +#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT144_MSG_DATA +#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT144_CONTROL +#define PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT145_ADDR_LO +#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT145_ADDR_HI +#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT145_MSG_DATA +#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT145_CONTROL +#define PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT146_ADDR_LO +#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT146_ADDR_HI +#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT146_MSG_DATA +#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT146_CONTROL +#define PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT147_ADDR_LO +#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT147_ADDR_HI +#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT147_MSG_DATA +#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT147_CONTROL +#define PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT148_ADDR_LO +#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT148_ADDR_HI +#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT148_MSG_DATA +#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT148_CONTROL +#define PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT149_ADDR_LO +#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT149_ADDR_HI +#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT149_MSG_DATA +#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT149_CONTROL +#define PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT150_ADDR_LO +#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT150_ADDR_HI +#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT150_MSG_DATA +#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT150_CONTROL +#define PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT151_ADDR_LO +#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT151_ADDR_HI +#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT151_MSG_DATA +#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT151_CONTROL +#define PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT152_ADDR_LO +#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT152_ADDR_HI +#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT152_MSG_DATA +#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT152_CONTROL +#define PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT153_ADDR_LO +#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT153_ADDR_HI +#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT153_MSG_DATA +#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT153_CONTROL +#define PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT154_ADDR_LO +#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT154_ADDR_HI +#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT154_MSG_DATA +#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT154_CONTROL +#define PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT155_ADDR_LO +#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT155_ADDR_HI +#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT155_MSG_DATA +#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT155_CONTROL +#define PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT156_ADDR_LO +#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT156_ADDR_HI +#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT156_MSG_DATA +#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT156_CONTROL +#define PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT157_ADDR_LO +#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT157_ADDR_HI +#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT157_MSG_DATA +#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT157_CONTROL +#define PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT158_ADDR_LO +#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT158_ADDR_HI +#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT158_MSG_DATA +#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT158_CONTROL +#define PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT159_ADDR_LO +#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT159_ADDR_HI +#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT159_MSG_DATA +#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT159_CONTROL +#define PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT160_ADDR_LO +#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT160_ADDR_HI +#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT160_MSG_DATA +#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT160_CONTROL +#define PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT161_ADDR_LO +#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT161_ADDR_HI +#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT161_MSG_DATA +#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT161_CONTROL +#define PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT162_ADDR_LO +#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT162_ADDR_HI +#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT162_MSG_DATA +#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT162_CONTROL +#define PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT163_ADDR_LO +#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT163_ADDR_HI +#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT163_MSG_DATA +#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT163_CONTROL +#define PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT164_ADDR_LO +#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT164_ADDR_HI +#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT164_MSG_DATA +#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT164_CONTROL +#define PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT165_ADDR_LO +#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT165_ADDR_HI +#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT165_MSG_DATA +#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT165_CONTROL +#define PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT166_ADDR_LO +#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT166_ADDR_HI +#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT166_MSG_DATA +#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT166_CONTROL +#define PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT167_ADDR_LO +#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT167_ADDR_HI +#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT167_MSG_DATA +#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT167_CONTROL +#define PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT168_ADDR_LO +#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT168_ADDR_HI +#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT168_MSG_DATA +#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT168_CONTROL +#define PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT169_ADDR_LO +#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT169_ADDR_HI +#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT169_MSG_DATA +#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT169_CONTROL +#define PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT170_ADDR_LO +#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT170_ADDR_HI +#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT170_MSG_DATA +#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT170_CONTROL +#define PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT171_ADDR_LO +#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT171_ADDR_HI +#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT171_MSG_DATA +#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT171_CONTROL +#define PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT172_ADDR_LO +#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT172_ADDR_HI +#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT172_MSG_DATA +#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT172_CONTROL +#define PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT173_ADDR_LO +#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT173_ADDR_HI +#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT173_MSG_DATA +#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT173_CONTROL +#define PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT174_ADDR_LO +#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT174_ADDR_HI +#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT174_MSG_DATA +#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT174_CONTROL +#define PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT175_ADDR_LO +#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT175_ADDR_HI +#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT175_MSG_DATA +#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT175_CONTROL +#define PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT176_ADDR_LO +#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT176_ADDR_HI +#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT176_MSG_DATA +#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT176_CONTROL +#define PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT177_ADDR_LO +#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT177_ADDR_HI +#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT177_MSG_DATA +#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT177_CONTROL +#define PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT178_ADDR_LO +#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT178_ADDR_HI +#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT178_MSG_DATA +#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT178_CONTROL +#define PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT179_ADDR_LO +#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT179_ADDR_HI +#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT179_MSG_DATA +#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT179_CONTROL +#define PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT180_ADDR_LO +#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT180_ADDR_HI +#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT180_MSG_DATA +#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT180_CONTROL +#define PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT181_ADDR_LO +#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT181_ADDR_HI +#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT181_MSG_DATA +#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT181_CONTROL +#define PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT182_ADDR_LO +#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT182_ADDR_HI +#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT182_MSG_DATA +#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT182_CONTROL +#define PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT183_ADDR_LO +#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT183_ADDR_HI +#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT183_MSG_DATA +#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT183_CONTROL +#define PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT184_ADDR_LO +#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT184_ADDR_HI +#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT184_MSG_DATA +#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT184_CONTROL +#define PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT185_ADDR_LO +#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT185_ADDR_HI +#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT185_MSG_DATA +#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT185_CONTROL +#define PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT186_ADDR_LO +#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT186_ADDR_HI +#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT186_MSG_DATA +#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT186_CONTROL +#define PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT187_ADDR_LO +#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT187_ADDR_HI +#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT187_MSG_DATA +#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT187_CONTROL +#define PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT188_ADDR_LO +#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT188_ADDR_HI +#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT188_MSG_DATA +#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT188_CONTROL +#define PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT189_ADDR_LO +#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT189_ADDR_HI +#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT189_MSG_DATA +#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT189_CONTROL +#define PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT190_ADDR_LO +#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT190_ADDR_HI +#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT190_MSG_DATA +#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT190_CONTROL +#define PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT191_ADDR_LO +#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT191_ADDR_HI +#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT191_MSG_DATA +#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT191_CONTROL +#define PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT192_ADDR_LO +#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT192_ADDR_HI +#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT192_MSG_DATA +#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT192_CONTROL +#define PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT193_ADDR_LO +#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT193_ADDR_HI +#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT193_MSG_DATA +#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT193_CONTROL +#define PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT194_ADDR_LO +#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT194_ADDR_HI +#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT194_MSG_DATA +#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT194_CONTROL +#define PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT195_ADDR_LO +#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT195_ADDR_HI +#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT195_MSG_DATA +#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT195_CONTROL +#define PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT196_ADDR_LO +#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT196_ADDR_HI +#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT196_MSG_DATA +#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT196_CONTROL +#define PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT197_ADDR_LO +#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT197_ADDR_HI +#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT197_MSG_DATA +#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT197_CONTROL +#define PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT198_ADDR_LO +#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT198_ADDR_HI +#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT198_MSG_DATA +#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT198_CONTROL +#define PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT199_ADDR_LO +#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT199_ADDR_HI +#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT199_MSG_DATA +#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT199_CONTROL +#define PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT200_ADDR_LO +#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT200_ADDR_HI +#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT200_MSG_DATA +#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT200_CONTROL +#define PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT201_ADDR_LO +#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT201_ADDR_HI +#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT201_MSG_DATA +#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT201_CONTROL +#define PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT202_ADDR_LO +#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT202_ADDR_HI +#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT202_MSG_DATA +#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT202_CONTROL +#define PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT203_ADDR_LO +#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT203_ADDR_HI +#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT203_MSG_DATA +#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT203_CONTROL +#define PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT204_ADDR_LO +#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT204_ADDR_HI +#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT204_MSG_DATA +#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT204_CONTROL +#define PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT205_ADDR_LO +#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT205_ADDR_HI +#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT205_MSG_DATA +#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT205_CONTROL +#define PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT206_ADDR_LO +#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT206_ADDR_HI +#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT206_MSG_DATA +#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT206_CONTROL +#define PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT207_ADDR_LO +#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT207_ADDR_HI +#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT207_MSG_DATA +#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT207_CONTROL +#define PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT208_ADDR_LO +#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT208_ADDR_HI +#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT208_MSG_DATA +#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT208_CONTROL +#define PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT209_ADDR_LO +#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT209_ADDR_HI +#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT209_MSG_DATA +#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT209_CONTROL +#define PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT210_ADDR_LO +#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT210_ADDR_HI +#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT210_MSG_DATA +#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT210_CONTROL +#define PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT211_ADDR_LO +#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT211_ADDR_HI +#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT211_MSG_DATA +#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT211_CONTROL +#define PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT212_ADDR_LO +#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT212_ADDR_HI +#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT212_MSG_DATA +#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT212_CONTROL +#define PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT213_ADDR_LO +#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT213_ADDR_HI +#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT213_MSG_DATA +#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT213_CONTROL +#define PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT214_ADDR_LO +#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT214_ADDR_HI +#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT214_MSG_DATA +#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT214_CONTROL +#define PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT215_ADDR_LO +#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT215_ADDR_HI +#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT215_MSG_DATA +#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT215_CONTROL +#define PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT216_ADDR_LO +#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT216_ADDR_HI +#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT216_MSG_DATA +#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT216_CONTROL +#define PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT217_ADDR_LO +#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT217_ADDR_HI +#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT217_MSG_DATA +#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT217_CONTROL +#define PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT218_ADDR_LO +#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT218_ADDR_HI +#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT218_MSG_DATA +#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT218_CONTROL +#define PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT219_ADDR_LO +#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT219_ADDR_HI +#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT219_MSG_DATA +#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT219_CONTROL +#define PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT220_ADDR_LO +#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT220_ADDR_HI +#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT220_MSG_DATA +#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT220_CONTROL +#define PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT221_ADDR_LO +#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT221_ADDR_HI +#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT221_MSG_DATA +#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT221_CONTROL +#define PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT222_ADDR_LO +#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT222_ADDR_HI +#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT222_MSG_DATA +#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT222_CONTROL +#define PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT223_ADDR_LO +#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT223_ADDR_HI +#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT223_MSG_DATA +#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT223_CONTROL +#define PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT224_ADDR_LO +#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT224_ADDR_HI +#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT224_MSG_DATA +#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT224_CONTROL +#define PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT225_ADDR_LO +#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT225_ADDR_HI +#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT225_MSG_DATA +#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT225_CONTROL +#define PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT226_ADDR_LO +#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT226_ADDR_HI +#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT226_MSG_DATA +#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT226_CONTROL +#define PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT227_ADDR_LO +#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT227_ADDR_HI +#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT227_MSG_DATA +#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT227_CONTROL +#define PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT228_ADDR_LO +#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT228_ADDR_HI +#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT228_MSG_DATA +#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT228_CONTROL +#define PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT229_ADDR_LO +#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT229_ADDR_HI +#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT229_MSG_DATA +#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT229_CONTROL +#define PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT230_ADDR_LO +#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT230_ADDR_HI +#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT230_MSG_DATA +#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT230_CONTROL +#define PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT231_ADDR_LO +#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT231_ADDR_HI +#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT231_MSG_DATA +#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT231_CONTROL +#define PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT232_ADDR_LO +#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT232_ADDR_HI +#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT232_MSG_DATA +#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT232_CONTROL +#define PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT233_ADDR_LO +#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT233_ADDR_HI +#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT233_MSG_DATA +#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT233_CONTROL +#define PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT234_ADDR_LO +#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT234_ADDR_HI +#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT234_MSG_DATA +#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT234_CONTROL +#define PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT235_ADDR_LO +#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT235_ADDR_HI +#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT235_MSG_DATA +#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT235_CONTROL +#define PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT236_ADDR_LO +#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT236_ADDR_HI +#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT236_MSG_DATA +#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT236_CONTROL +#define PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT237_ADDR_LO +#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT237_ADDR_HI +#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT237_MSG_DATA +#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT237_CONTROL +#define PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT238_ADDR_LO +#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT238_ADDR_HI +#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT238_MSG_DATA +#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT238_CONTROL +#define PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT239_ADDR_LO +#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT239_ADDR_HI +#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT239_MSG_DATA +#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT239_CONTROL +#define PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT240_ADDR_LO +#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT240_ADDR_HI +#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT240_MSG_DATA +#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT240_CONTROL +#define PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT241_ADDR_LO +#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT241_ADDR_HI +#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT241_MSG_DATA +#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT241_CONTROL +#define PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT242_ADDR_LO +#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT242_ADDR_HI +#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT242_MSG_DATA +#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT242_CONTROL +#define PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT243_ADDR_LO +#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT243_ADDR_HI +#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT243_MSG_DATA +#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT243_CONTROL +#define PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT244_ADDR_LO +#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT244_ADDR_HI +#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT244_MSG_DATA +#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT244_CONTROL +#define PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT245_ADDR_LO +#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT245_ADDR_HI +#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT245_MSG_DATA +#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT245_CONTROL +#define PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT246_ADDR_LO +#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT246_ADDR_HI +#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT246_MSG_DATA +#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT246_CONTROL +#define PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT247_ADDR_LO +#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT247_ADDR_HI +#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT247_MSG_DATA +#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT247_CONTROL +#define PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT248_ADDR_LO +#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT248_ADDR_HI +#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT248_MSG_DATA +#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT248_CONTROL +#define PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT249_ADDR_LO +#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT249_ADDR_HI +#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT249_MSG_DATA +#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT249_CONTROL +#define PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT250_ADDR_LO +#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT250_ADDR_HI +#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT250_MSG_DATA +#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT250_CONTROL +#define PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT251_ADDR_LO +#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT251_ADDR_HI +#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT251_MSG_DATA +#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT251_CONTROL +#define PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT252_ADDR_LO +#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT252_ADDR_HI +#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT252_MSG_DATA +#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT252_CONTROL +#define PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT253_ADDR_LO +#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT253_ADDR_HI +#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT253_MSG_DATA +#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT253_CONTROL +#define PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT254_ADDR_LO +#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT254_ADDR_HI +#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT254_MSG_DATA +#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT254_CONTROL +#define PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT255_ADDR_LO +#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT255_ADDR_HI +#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT255_MSG_DATA +#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT255_CONTROL +#define PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK 0x00000001L + + + + + + +//PCIEMSIX_PBA_0 +#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_1 +#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_2 +#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_3 +#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_4 +#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_5 +#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_6 +#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_7 +#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal +//RCC_STRAP1_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP1_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_DEV1_PORT_STRAP0 +//RCC_DEV1_PORT_STRAP1 +//RCC_DEV1_PORT_STRAP2 +//RCC_DEV1_PORT_STRAP3 +//RCC_DEV1_PORT_STRAP4 +//RCC_DEV1_PORT_STRAP5 +//RCC_DEV1_PORT_STRAP6 +//RCC_DEV1_PORT_STRAP7 +//RCC_DEV1_PORT_STRAP8 +//RCC_DEV1_PORT_STRAP9 +//RCC_DEV1_PORT_STRAP10 +//RCC_DEV1_PORT_STRAP11 +//RCC_DEV1_PORT_STRAP12 +//RCC_DEV1_PORT_STRAP13 +//RCC_DEV1_PORT_STRAP14 +//RCC_DEV2_PORT_STRAP0 +//RCC_DEV2_PORT_STRAP1 +//RCC_DEV2_PORT_STRAP2 +//RCC_DEV2_PORT_STRAP3 +//RCC_DEV2_PORT_STRAP4 +//RCC_DEV2_PORT_STRAP5 +//RCC_DEV2_PORT_STRAP6 +//RCC_DEV2_PORT_STRAP7 +//RCC_DEV2_PORT_STRAP8 +//RCC_DEV2_PORT_STRAP9 +//RCC_DEV2_PORT_STRAP10 +//RCC_DEV2_PORT_STRAP11 +//RCC_DEV2_PORT_STRAP12 +//RCC_DEV2_PORT_STRAP13 +//RCC_DEV2_PORT_STRAP14 +//RCC_STRAP1_RCC_BIF_STRAP0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP1 +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP2 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP3 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP4 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP5 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP1_RCC_BIF_STRAP6 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP22 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP25 +//RCC_DEV0_EPF2_STRAP0 +#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0 +#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10 +#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14 +#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c +#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d +#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e +#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f +#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK 0x0000FFFFL +#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK 0x000F0000L +#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK 0x00F00000L +#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK 0x10000000L +#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK 0x20000000L +#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK 0x40000000L +#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK 0x80000000L +//RCC_DEV0_EPF2_STRAP2 +#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7 +#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8 +#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT 0x9 +#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe +#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10 +#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11 +#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14 +#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15 +#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17 +#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18 +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT 0x1c +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT 0x1d +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT 0x1e +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT 0x1f +#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK 0x00000080L +#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK 0x00000100L +#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK 0x00003E00L +#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK 0x00004000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK 0x00010000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK 0x00020000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK 0x00100000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK 0x00200000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK 0x00800000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK 0x07000000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK 0x10000000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK 0x20000000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK 0x40000000L +#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK 0x80000000L +//RCC_DEV0_EPF2_STRAP3 +#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x0 +#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x10 +#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x11 +#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12 +#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13 +#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14 +#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18 +#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a +#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b +#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2__SHIFT 0x1d +#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2__SHIFT 0x1e +#define RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2__SHIFT 0x1f +#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK 0x0000FFFFL +#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK 0x00010000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK 0x00020000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK 0x00040000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK 0x00080000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK 0x00100000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK 0x01000000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK 0x04000000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK 0x08000000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2_MASK 0x20000000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2_MASK 0x40000000L +#define RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2_MASK 0x80000000L +//RCC_DEV0_EPF2_STRAP4 +#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14 +#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15 +#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16 +#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17 +#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c +#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f +#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK 0x00100000L +#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK 0x00200000L +#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK 0x00400000L +#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK 0x0F800000L +#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK 0x70000000L +#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK 0x80000000L +//RCC_DEV0_EPF2_STRAP5 +#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0 +#define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2__SHIFT 0x1b +#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2__SHIFT 0x1e +#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK 0x0000FFFFL +#define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2_MASK 0x38000000L +#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2_MASK 0x40000000L +//RCC_DEV0_EPF2_STRAP6 +#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0 +#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK 0x00000001L +//RCC_DEV0_EPF2_STRAP7 +//RCC_DEV0_EPF2_STRAP10 +//RCC_DEV0_EPF2_STRAP11 +//RCC_DEV0_EPF2_STRAP12 +//RCC_DEV0_EPF2_STRAP13 +#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0 +#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8 +#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10 +#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK 0x000000FFL +#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK 0x0000FF00L +#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK 0x00FF0000L +//RCC_DEV0_EPF2_STRAP14 +#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2__SHIFT 0x0 +#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2_MASK 0x0000FFFFL +//RCC_DEV0_EPF2_STRAP20 +//RCC_DEV0_EPF3_STRAP0 +#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0 +#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10 +#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14 +#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c +#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d +#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e +#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f +#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK 0x0000FFFFL +#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK 0x000F0000L +#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK 0x00F00000L +#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK 0x10000000L +#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK 0x20000000L +#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK 0x40000000L +#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK 0x80000000L +//RCC_DEV0_EPF3_STRAP2 +#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7 +#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8 +#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT 0x9 +#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe +#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10 +#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11 +#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14 +#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15 +#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17 +#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18 +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT 0x1c +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT 0x1d +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT 0x1e +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT 0x1f +#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK 0x00000080L +#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK 0x00000100L +#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK 0x00003E00L +#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK 0x00004000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK 0x00010000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK 0x00020000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK 0x00100000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK 0x00200000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK 0x00800000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK 0x07000000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK 0x10000000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK 0x20000000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK 0x40000000L +#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK 0x80000000L +//RCC_DEV0_EPF3_STRAP3 +#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x0 +#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x10 +#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x11 +#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12 +#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13 +#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14 +#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18 +#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a +#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b +#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3__SHIFT 0x1d +#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3__SHIFT 0x1e +#define RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3__SHIFT 0x1f +#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK 0x0000FFFFL +#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK 0x00010000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK 0x00020000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK 0x00040000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK 0x00080000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK 0x00100000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK 0x01000000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK 0x04000000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK 0x08000000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3_MASK 0x20000000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3_MASK 0x40000000L +#define RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3_MASK 0x80000000L +//RCC_DEV0_EPF3_STRAP4 +#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14 +#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15 +#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16 +#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17 +#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c +#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK 0x00100000L +#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK 0x00200000L +#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK 0x00400000L +#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK 0x0F800000L +#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK 0x70000000L +//RCC_DEV0_EPF3_STRAP5 +#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0 +#define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3__SHIFT 0x1b +#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3__SHIFT 0x1e +#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK 0x0000FFFFL +#define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3_MASK 0x38000000L +#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3_MASK 0x40000000L +//RCC_DEV0_EPF3_STRAP6 +#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0 +#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK 0x00000001L +//RCC_DEV0_EPF3_STRAP7 +//RCC_DEV0_EPF3_STRAP10 +//RCC_DEV0_EPF3_STRAP11 +//RCC_DEV0_EPF3_STRAP12 +//RCC_DEV0_EPF3_STRAP13 +#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0 +#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8 +#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10 +#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK 0x000000FFL +#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK 0x0000FF00L +#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK 0x00FF0000L +//RCC_DEV0_EPF3_STRAP14 +#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3__SHIFT 0x0 +#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3_MASK 0x0000FFFFL +//RCC_DEV0_EPF3_STRAP20 +//RCC_DEV0_EPF4_STRAP0 +//RCC_DEV0_EPF4_STRAP2 +//RCC_DEV0_EPF4_STRAP3 +//RCC_DEV0_EPF4_STRAP4 +//RCC_DEV0_EPF4_STRAP5 +//RCC_DEV0_EPF4_STRAP6 +//RCC_DEV0_EPF4_STRAP7 +//RCC_DEV0_EPF4_STRAP13 +//RCC_DEV0_EPF4_STRAP14 +//RCC_DEV0_EPF5_STRAP0 +//RCC_DEV0_EPF5_STRAP2 +//RCC_DEV0_EPF5_STRAP3 +//RCC_DEV0_EPF5_STRAP4 +//RCC_DEV0_EPF5_STRAP5 +//RCC_DEV0_EPF5_STRAP6 +//RCC_DEV0_EPF5_STRAP7 +//RCC_DEV0_EPF5_STRAP13 +//RCC_DEV0_EPF5_STRAP14 +//RCC_DEV0_EPF6_STRAP0 +//RCC_DEV0_EPF6_STRAP2 +//RCC_DEV0_EPF6_STRAP3 +//RCC_DEV0_EPF6_STRAP4 +//RCC_DEV0_EPF6_STRAP5 +//RCC_DEV0_EPF6_STRAP6 +//RCC_DEV0_EPF6_STRAP13 +//RCC_DEV0_EPF6_STRAP14 +//RCC_DEV0_EPF7_STRAP0 +//RCC_DEV0_EPF7_STRAP2 +//RCC_DEV0_EPF7_STRAP3 +//RCC_DEV0_EPF7_STRAP4 +//RCC_DEV0_EPF7_STRAP5 +//RCC_DEV0_EPF7_STRAP6 +//RCC_DEV0_EPF7_STRAP7 +//RCC_DEV0_EPF7_STRAP13 +//RCC_DEV0_EPF7_STRAP14 +//RCC_DEV1_EPF0_STRAP0 +//RCC_DEV1_EPF0_STRAP2 +//RCC_DEV1_EPF0_STRAP3 +//RCC_DEV1_EPF0_STRAP4 +//RCC_DEV1_EPF0_STRAP5 +//RCC_DEV1_EPF0_STRAP6 +//RCC_DEV1_EPF0_STRAP7 +//RCC_DEV1_EPF0_STRAP13 +//RCC_DEV1_EPF0_STRAP14 +//RCC_DEV1_EPF1_STRAP0 +//RCC_DEV1_EPF1_STRAP2 +//RCC_DEV1_EPF1_STRAP3 +//RCC_DEV1_EPF1_STRAP4 +//RCC_DEV1_EPF1_STRAP5 +//RCC_DEV1_EPF1_STRAP6 +//RCC_DEV1_EPF1_STRAP7 +//RCC_DEV1_EPF1_STRAP13 +//RCC_DEV1_EPF1_STRAP14 +//RCC_DEV1_EPF2_STRAP0 +//RCC_DEV1_EPF2_STRAP2 +//RCC_DEV1_EPF2_STRAP3 +//RCC_DEV1_EPF2_STRAP4 +//RCC_DEV1_EPF2_STRAP5 +//RCC_DEV1_EPF2_STRAP6 +//RCC_DEV1_EPF2_STRAP13 +//RCC_DEV1_EPF2_STRAP14 +//RCC_DEV1_EPF3_STRAP0 +//RCC_DEV1_EPF3_STRAP2 +//RCC_DEV1_EPF3_STRAP3 +//RCC_DEV1_EPF3_STRAP4 +//RCC_DEV1_EPF3_STRAP5 +//RCC_DEV1_EPF3_STRAP6 +//RCC_DEV1_EPF3_STRAP13 +//RCC_DEV1_EPF3_STRAP14 +//RCC_DEV1_EPF4_STRAP0 +//RCC_DEV1_EPF4_STRAP2 +//RCC_DEV1_EPF4_STRAP3 +//RCC_DEV1_EPF4_STRAP4 +//RCC_DEV1_EPF4_STRAP5 +//RCC_DEV1_EPF4_STRAP6 +//RCC_DEV1_EPF4_STRAP13 +//RCC_DEV1_EPF4_STRAP14 +//RCC_DEV1_EPF5_STRAP0 +//RCC_DEV1_EPF5_STRAP2 +//RCC_DEV1_EPF5_STRAP3 +//RCC_DEV1_EPF5_STRAP4 +//RCC_DEV1_EPF5_STRAP5 +//RCC_DEV1_EPF5_STRAP6 +//RCC_DEV1_EPF5_STRAP13 +//RCC_DEV1_EPF5_STRAP14 +//RCC_DEV2_EPF0_STRAP0 +//RCC_DEV2_EPF0_STRAP2 +//RCC_DEV2_EPF0_STRAP3 +//RCC_DEV2_EPF0_STRAP4 +//RCC_DEV2_EPF0_STRAP5 +//RCC_DEV2_EPF0_STRAP6 +//RCC_DEV2_EPF0_STRAP7 +//RCC_DEV2_EPF0_STRAP13 +//RCC_DEV2_EPF0_STRAP14 +//RCC_DEV2_EPF1_STRAP0 +//RCC_DEV2_EPF1_STRAP2 +//RCC_DEV2_EPF1_STRAP3 +//RCC_DEV2_EPF1_STRAP4 +//RCC_DEV2_EPF1_STRAP5 +//RCC_DEV2_EPF1_STRAP6 +//RCC_DEV2_EPF1_STRAP13 +//RCC_DEV2_EPF1_STRAP14 +//RCC_DEV2_EPF2_STRAP0 +//RCC_DEV2_EPF2_STRAP2 +//RCC_DEV2_EPF2_STRAP3 +//RCC_DEV2_EPF2_STRAP4 +//RCC_DEV2_EPF2_STRAP5 +//RCC_DEV2_EPF2_STRAP6 +//RCC_DEV2_EPF2_STRAP13 +//RCC_DEV2_EPF2_STRAP14 + + +// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk +//HARD_RST_CTRL +#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9 +#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa +#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT 0x17 +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c +#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L +#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L +#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L +#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L +#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L +#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L +#define HARD_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L +#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L +#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L +#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L +//SELF_SOFT_RST +#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19 +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a +#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b +#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c +#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d +#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e +#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f +#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L +#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L +#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L +#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L +#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L +#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L +//BIF_GFX_DRV_VPU_RST +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L +//BIF_RST_MISC_CTRL +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 +#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L +#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L +//BIF_RST_MISC_CTRL2 +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L +//BIF_RST_MISC_CTRL3 +#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd +#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L +//DEV0_PF0_FLR_RST_CTRL +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L +//DEV0_PF1_FLR_RST_CTRL +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF2_FLR_RST_CTRL +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF3_FLR_RST_CTRL +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//BIF_INST_RESET_INTR_STS +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L +//BIF_PF_FLR_INTR_STS +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 +#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L +#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L +#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L +//BIF_D3HOTD0_INTR_STS +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L +//BIF_POWER_INTR_STS +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_STS +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L +//SELF_SOFT_RST_2 +#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST_2__STRAP_RST__SHIFT 0x19 +#define SELF_SOFT_RST_2__NBIF_S5_RST__SHIFT 0x1e +#define SELF_SOFT_RST_2__NBIF_S5_CDC_RST__SHIFT 0x1f +#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST_2__STRAP_RST_MASK 0x02000000L +#define SELF_SOFT_RST_2__NBIF_S5_RST_MASK 0x40000000L +#define SELF_SOFT_RST_2__NBIF_S5_CDC_RST_MASK 0x80000000L +//BIF_INST_RESET_INTR_MASK +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L +//BIF_PF_FLR_INTR_MASK +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L +//BIF_D3HOTD0_INTR_MASK +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L +//BIF_POWER_INTR_MASK +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_MASK +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L +//BIF_PF_FLR_RST +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 +#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L +#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L +//BIF_DEV0_PF0_DSTATE_VALUE +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF1_DSTATE_VALUE +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF2_DSTATE_VALUE +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF3_DSTATE_VALUE +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L +//DEV0_PF0_D3HOTD0_RST_CTRL +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF1_D3HOTD0_RST_CTRL +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF2_D3HOTD0_RST_CTRL +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF3_D3HOTD0_RST_CTRL +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//BIF_PORT0_DSTATE_VALUE +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L + + +// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk +//REGS_ROM_OFFSET_CTRL +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT 0x0 +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK 0x7FL +//NBIF_STRAP_BIOS_CNTL +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT 0x0 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT 0x1 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK 0x00000001L +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK 0x00000002L +//MISC_SCRATCH +#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 +#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL +//INTR_LINE_POLARITY +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL +//INTR_LINE_ENABLE +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL +//OUTSTANDING_VC_ALLOC +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L +//BIFC_MISC_CTRL0 +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4 +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT 0x9 +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT 0xe +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT 0xf +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT 0x15 +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT 0x16 +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT 0x17 +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT 0x19 +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT 0x1e +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK 0x00000200L +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK 0x00004000L +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK 0x00008000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK 0x00200000L +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK 0x00400000L +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK 0x00800000L +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK 0x02000000L +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK 0x40000000L +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L +//BIFC_MISC_CTRL1 +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT 0x15 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT 0x16 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17 +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK 0x00200000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK 0x00400000L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L +//BIFC_BME_ERR_LOG_LB +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L +//BIFC_LC_TIMER_CTRL +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0 +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10 +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L +//BIFC_RCCBIH_BME_ERR_LOG0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L +//BIFC_DMA_ATTR_CNTL2_DEV0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L +//BME_DUMMY_CNTL_0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L +//BIFC_HSTARB_CNTL +#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8 +#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L +//BIFC_GSI_CNTL +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc +#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xe +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0xf +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x10 +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x11 +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L +#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00004000L +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00008000L +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00010000L +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00020000L +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L +//BIFC_PCIEFUNC_CNTL +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L +//BIFC_PASID_CHECK_DIS +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT 0x2 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT 0x3 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK 0x00000004L +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK 0x00000008L +//BIFC_SDP_CNTL_0 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L +//BIFC_SDP_CNTL_1 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8 +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x9 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000200L +//BIFC_PASID_STS +#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0 +#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL +//BIFC_ATHUB_ACT_CNTL +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT 0x3 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8 +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0x9 +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0xa +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK 0x00000038L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000200L +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000400L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L +//BIFC_PERF_CNTL_0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L +//BIFC_PERF_CNTL_1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x4 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x5 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x8 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000010L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000020L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x0000FF00L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x01FF0000L +//BIFC_PERF_CNT_MMIO_RD_L32BIT +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_MMIO_WR_L32BIT +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_RD_L32BIT +#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_WR_L32BIT +#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//NBIF_REGIF_ERRSET_CTRL +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//BIFC_SDP_CNTL_2 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L +//NBIF_PGMST_CTRL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//NBIF_PGSLV_CTRL +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//NBIF_PG_MISC_CTRL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//SMN_MST_EP_CNTL3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_CNTL1 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L +//SMN_MST_EP_CNTL5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L +//BIF_SELFRING_BUFFER_VID +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8 +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10 +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L +//BIF_SELFRING_VECTOR_CNTL +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L +//NBIF_STRAP_WRITE_CTRL +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L +//NBIF_INTX_DSTATE_MISC_CNTL +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L +//NBIF_PENDING_MISC_CNTL +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0 +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1 +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L +//BIF_GMI_WRR_WEIGHT +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L +//BIF_GMI_WRR_WEIGHT2 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L +//BIF_GMI_WRR_WEIGHT3 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L +//NBIF_PWRBRK_REQUEST +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0 +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L +//BIF_ATOMIC_ERR_LOG_DEV0_F0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L +//BIF_ATOMIC_ERR_LOG_DEV0_F1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L +//BIF_ATOMIC_ERR_LOG_DEV0_F2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK 0x00080000L +//BIF_ATOMIC_ERR_LOG_DEV0_F3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK 0x00080000L +//BIF_DMA_MP4_ERR_LOG +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L +//BIF_PASID_ERR_LOG +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT 0x2 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT 0x3 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK 0x00000004L +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK 0x00000008L +//BIF_PASID_ERR_CLR +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT 0x2 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT 0x3 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK 0x00000004L +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK 0x00000008L +//NBIF_VWIRE_CTRL +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0 +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10 +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L +//NBIF_SMN_VWR_VCHG_DIS_CTRL +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L +//NBIF_SMN_VWR_VCHG_RST_CTRL0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L +//NBIF_SMN_VWR_VCHG_TRIG +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L +//NBIF_SMN_VWR_WTRIG_CNTL +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L +//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L +//NBIF_MGCG_CTRL_LCLK +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L +//NBIF_DS_CTRL_LCLK +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L +//SMN_MST_CNTL0 +#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c +#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L +//SMN_MST_EP_CNTL1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L +//NBIF_SDP_VWR_VCHG_DIS_CTRL +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_TRIG +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L +//NBIF_SHUB_TODET_CTRL +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT 0x1 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK 0x00000002L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L +//NBIF_SHUB_TODET_CLIENT_CTRL +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_CTRL2 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS2 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK 0xFFFFFFFFL +//BIFC_BME_ERR_LOG_HB +//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//DISCON_HYSTERESIS_HEAD_CTRL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L +//BIFC_EARLY_WAKEUP_CNTL +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//BIFC_PERF_CNT_MMIO_RD_H16BIT +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_MMIO_WR_H16BIT +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_DMA_RD_H16BIT +#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_DMA_WR_H16BIT +#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK 0x0000FFFFL + + +// addressBlock: nbio_nbif0_bif_misc_pfvf_bif_misc_pfvf_regblk + + +// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk +//BIFL_RAS_CENTRAL_CNTL +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS__SHIFT 0x1b +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS__SHIFT 0x1c +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e +#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS_MASK 0x08000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS_MASK 0x10000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L +//BIFL_RAS_CENTRAL_STATUS +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e +#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L +//BIFL_RAS_LEAF0_CTRL +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//BIFL_RAS_LEAF1_CTRL +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//BIFL_RAS_LEAF2_CTRL +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//BIFL_RAS_LEAF3_CTRL +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//BIFL_RAS_LEAF0_STATUS +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF1_STATUS +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF2_STATUS +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF3_STATUS +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_IOHUB_RAS_IH_CNTL +#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0 +#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L +//BIFL_RAS_VWR_FROM_IOHUB +#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0 +#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_2_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_2_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_2_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_2_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_1_RCC_ERR_INT_CNTL +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_BACO_CNTL_MISC +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_1_RCC_RESET_EN +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_2_RCC_VDM_SUPPORT +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_1_RCC_GPUIOV_REGION +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_1_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_1_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_BUS_CNTL +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_CONFIG_CNTL +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_1_RCC_CONFIG_F0_BASE +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_1_RCC_XDMA_LO +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_XDMA_HI +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_1_RCC_BUSNUM_LIST0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_LIST1 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_HOST_BUSNUM +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_2_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_2_RCC_CMN_LINK_CNTL +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_2_RCC_MH_ARB_CNTL +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +//BIF_BX1_PCIE_INDEX +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA +#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX2 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA2 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX_HI +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL +//BIF_BX1_PCIE_INDEX2_HI +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL +//BIF_BX1_SBIOS_SCRATCH_0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_1 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_2 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_3 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_1 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_2 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_3 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_4 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_5 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_6 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_7 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_8 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_9 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_10 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_11 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_12 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_13 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_14 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_15 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RLC_INTR_CNTL +//BIF_BX1_BIF_VCE_INTR_CNTL +//BIF_BX1_BIF_UVD_INTR_CNTL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_CNTL +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_1 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_2 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_3 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_4 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_5 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_6 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_7 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_8 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_9 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_10 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_11 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_12 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_13 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_14 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_15 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_1 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_2 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_3 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_4 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_5 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_6 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_7 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_8 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_9 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_10 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_11 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_12 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_13 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_14 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_15 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_4 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_5 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_6 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_7 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_8 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_9 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_10 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_11 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_12 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_13 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_14 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_15 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +//BIF_BX1_CC_BIF_BX_STRAP0 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX1_CC_BIF_BX_PINSTRAP0 +//BIF_BX1_BIF_MM_INDACCESS_CNTL +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX1_BUS_CNTL +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX1_BIF_SCRATCH0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_SCRATCH1 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX1_BX_RESET_EN +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX1_MM_CFGREGS_CNTL +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX1_BX_RESET_CNTL +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX1_INTERRUPT_CNTL +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX1_INTERRUPT_CNTL2 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_CLKREQB_PAD_CNTL +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX1_BIF_FEATURES_CONTROL_MISC +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX1_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX1_BIF_DOORBELL_CNTL +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX1_BIF_DOORBELL_INT_CNTL +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX1_BIF_FB_EN +#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX1_BIF_INTR_CNTL +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX1_BIF_MST_TRANS_PENDING_VF +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_MEM_TYPE_CNTL +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX1_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_VF_REGWR_EN +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_EN +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//BIF_BX1_VF_FB_EN +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_REGWR_STATUS +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_STATUS +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_FB_STATUS +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_BIF_RB_CNTL +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX1_BIF_RB_BASE +#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RB_RPTR +#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR_ADDR_HI +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX1_BIF_RB_WPTR_ADDR_LO +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX1_MAILBOX_INDEX +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX1_BIF_MP1_INTR_CTRL +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE +#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE +#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE +#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX1_BIF_PERSTB_PAD_CNTL +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX1_BIF_PX_EN_PAD_CNTL +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX1_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_CLKREQB_PAD_CNTL +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_PWRBRK_PAD_CNTL +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_WAKEB_PAD_CNTL +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT 0x0 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT 0x1 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT 0x2 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT 0x3 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT 0x4 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT 0x5 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT 0x6 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT 0x7 +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK 0x00000001L +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK 0x00000002L +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK 0x00000004L +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK 0x00000008L +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK 0x00000010L +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK 0x00000020L +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK 0x00000040L +#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK 0x00000080L +//BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT 0x0 +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT 0x1 +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT 0x2 +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT 0x3 +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT 0x4 +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT 0x5 +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK 0x00000001L +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK 0x00000002L +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK 0x00000004L +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK 0x00000008L +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK 0x00000010L +#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK 0x00000020L +//BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL +#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT 0x0 +#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT 0x1 +#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK 0x00000001L +#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK 0xFFFFFFFEL +//BIF_BX1_BIF_S5_MEM_POWER_CTRL0 +#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT 0x0 +#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_S5_MEM_POWER_CTRL1 +#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT 0x0 +#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT 0xa +#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK 0x000003FFL +#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK 0x00000400L +//BIF_BX1_BIF_S5_DUMMY_REGS +#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT 0x0 +#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF1_BIF_BME_STATUS +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_BIF_TRANS_PENDING +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_CONTROL +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF1_MAILBOX_INT_CNTL +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF1_BIF_VMHV_MAILBOX +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1 +//RCC_STRAP2_RCC_BIF_STRAP0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP1 +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP2 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP3 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP4 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP5 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP2_RCC_BIF_STRAP6 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP22 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP25 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7 + + +// addressBlock: nbio_nbif0_mca_nbif_mca_map + + +// addressBlock: nbio_nbif0_gdc_dma_sion_SIONDEC +//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CNTL_REG0 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L +//GDC_DMA_SION_CNTL_REG1 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS__SHIFT 0x8 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L + + +// addressBlock: nbio_nbif0_gdc_hst_sion_SIONDEC +//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_BurstTarget_REG0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_BurstTarget_REG1 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_TimeSlot_REG0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_TimeSlot_REG1 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_BurstTarget_REG0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_BurstTarget_REG1 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_TimeSlot_REG0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_TimeSlot_REG1 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_RdRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_RdRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_RdRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_RdRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_WrRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_WrRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_WrRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_WrRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_Req_BurstTarget_REG0 +#define GDC_HST_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_Req_BurstTarget_REG1 +#define GDC_HST_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_Req_TimeSlot_REG0 +#define GDC_HST_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_Req_TimeSlot_REG1 +#define GDC_HST_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CNTL_REG0 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L +//GDC_HST_SION_CNTL_REG1 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS__SHIFT 0x8 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L +//S2A_DOORBELL_ENTRY_0_CTRL +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_1_CTRL +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_2_CTRL +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_3_CTRL +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_4_CTRL +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_5_CTRL +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_6_CTRL +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_7_CTRL +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_8_CTRL +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_9_CTRL +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_10_CTRL +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_11_CTRL +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_12_CTRL +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_13_CTRL +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_14_CTRL +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_15_CTRL +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_COMMON_CTRL_REG +#define S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +//GDC1_SHUB_REGS_IF_CTL +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//GDC1_NGDC_MGCG_CTRL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +//GDC1_NGDC_RESERVED_0 +#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NGDC_RESERVED_1 +#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NBIF_GFX_DOORBELL_STATUS +#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +//GDC1_ATDMA_MISC_CNTL +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL +#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC1_S2A_MISC_CNTL +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC1_NGDC_EARLY_WAKEUP_CTRL +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//GDC1_NGDC_PG_MISC_CTRL +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10 +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//GDC1_NGDC_PGMST_CTRL +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8 +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//GDC1_NGDC_PGSLV_CTRL +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L + + +// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk +//GDCSOC_ERR_RSP_CNTL +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT 0x0 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT 0x1 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT 0x2 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT 0x3 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK 0x00000001L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK 0x00000002L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK 0x00000004L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK 0x00000008L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L +//GDCSOC_RAS_CENTRAL_STATUS +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT 0x0 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT 0x1 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT 0x2 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT 0x3 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK 0x00000001L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK 0x00000002L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK 0x00000004L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK 0x00000008L +//GDCSOC_RAS_LEAF0_CTRL +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//GDCSOC_RAS_LEAF1_CTRL +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//GDCSOC_RAS_LEAF2_CTRL +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//GDCSOC_RAS_LEAF3_CTRL +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//GDCSOC_RAS_LEAF4_CTRL +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +//GDCSOC_RAS_LEAF2_MISC_CTRL +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT 0x8 +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT 0x9 +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK__SHIFT 0xc +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP__SHIFT 0xd +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT 0x11 +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK 0x00000100L +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK 0x00000200L +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ_MASK 0x00000800L +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK_MASK 0x00001000L +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP_MASK 0x00002000L +#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK 0x00020000L +//GDCSOC_RAS_LEAF2_MISC_CTRL2 +#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT 0x15 +#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK 0x001FF800L +#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK 0x7FE00000L +//GDCSOC_RAS_LEAF0_STATUS +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF1_STATUS +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF2_STATUS +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF3_STATUS +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF4_STATUS +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L + + +// addressBlock: nbio_nbif0_gdc_sec_GDCSEC_DEC + + +// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC +//SHUB_PF_FLR_RST +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 +#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L +#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L +//SHUB_GFX_DRV_VPU_RST +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L +//SHUB_LINK_RESET +#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 +#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 +#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2 +#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT 0x3 +#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L +#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L +#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L +#define SHUB_LINK_RESET__LINK_P3_RESET_MASK 0x00000008L +//SHUB_HARD_RST_CTRL +#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SOFT_RST_CTRL +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SDP_PORT_RST +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1 +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2 +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3 +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 +#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6 +#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT 0x7 +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 +#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT 0xa +#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT 0xb +#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT 0xc +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT 0xd +#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L +#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L +#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK 0x00000080L +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L +#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK 0x00000400L +#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK 0x00000800L +#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK 0x00001000L +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK 0x00002000L +#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L + + +// addressBlock: nbio_nbif0_gdc_misc_GDCMISC_DEC + + +// addressBlock: nbio_nbif0_gdc_sec_misc_GDCSEC_MISC_DEC + + +// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect +//HST_CLK0_SW0_CL0_CNTL +#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//HST_CLK0_SW1_CL0_CNTL +#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_mca_shub_mca_map + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +//PSWUSCFG0_1_VENDOR_ID +#define PSWUSCFG0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define PSWUSCFG0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//PSWUSCFG0_1_DEVICE_ID +#define PSWUSCFG0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define PSWUSCFG0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//PSWUSCFG0_1_COMMAND +#define PSWUSCFG0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define PSWUSCFG0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define PSWUSCFG0_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define PSWUSCFG0_1_COMMAND__SERR_EN__SHIFT 0x8 +#define PSWUSCFG0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define PSWUSCFG0_1_COMMAND__INT_DIS__SHIFT 0xa +#define PSWUSCFG0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define PSWUSCFG0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define PSWUSCFG0_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define PSWUSCFG0_1_COMMAND__SERR_EN_MASK 0x0100L +#define PSWUSCFG0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define PSWUSCFG0_1_COMMAND__INT_DIS_MASK 0x0400L +//PSWUSCFG0_1_STATUS +#define PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define PSWUSCFG0_1_STATUS__INT_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_STATUS__CAP_LIST__SHIFT 0x4 +#define PSWUSCFG0_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define PSWUSCFG0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define PSWUSCFG0_1_STATUS__INT_STATUS_MASK 0x0008L +#define PSWUSCFG0_1_STATUS__CAP_LIST_MASK 0x0010L +#define PSWUSCFG0_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define PSWUSCFG0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//PSWUSCFG0_1_REVISION_ID +#define PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//PSWUSCFG0_1_PROG_INTERFACE +#define PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//PSWUSCFG0_1_SUB_CLASS +#define PSWUSCFG0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define PSWUSCFG0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//PSWUSCFG0_1_BASE_CLASS +#define PSWUSCFG0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define PSWUSCFG0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//PSWUSCFG0_1_CACHE_LINE +#define PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//PSWUSCFG0_1_LATENCY +#define PSWUSCFG0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define PSWUSCFG0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//PSWUSCFG0_1_HEADER +#define PSWUSCFG0_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define PSWUSCFG0_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define PSWUSCFG0_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define PSWUSCFG0_1_HEADER__DEVICE_TYPE_MASK 0x80L +//PSWUSCFG0_1_BIST +#define PSWUSCFG0_1_BIST__BIST_COMP__SHIFT 0x0 +#define PSWUSCFG0_1_BIST__BIST_STRT__SHIFT 0x6 +#define PSWUSCFG0_1_BIST__BIST_CAP__SHIFT 0x7 +#define PSWUSCFG0_1_BIST__BIST_COMP_MASK 0x0FL +#define PSWUSCFG0_1_BIST__BIST_STRT_MASK 0x40L +#define PSWUSCFG0_1_BIST__BIST_CAP_MASK 0x80L +//PSWUSCFG0_1_BASE_ADDR_1 +#define PSWUSCFG0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define PSWUSCFG0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_BASE_ADDR_2 +#define PSWUSCFG0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define PSWUSCFG0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//PSWUSCFG0_1_IO_BASE_LIMIT +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//PSWUSCFG0_1_SECONDARY_STATUS +#define PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//PSWUSCFG0_1_MEM_BASE_LIMIT +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//PSWUSCFG0_1_PREF_BASE_LIMIT +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//PSWUSCFG0_1_PREF_BASE_UPPER +#define PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PREF_LIMIT_UPPER +#define PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_IO_BASE_LIMIT_HI +#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//PSWUSCFG0_1_CAP_PTR +#define PSWUSCFG0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define PSWUSCFG0_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//PSWUSCFG0_1_ROM_BASE_ADDR +#define PSWUSCFG0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define PSWUSCFG0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//PSWUSCFG0_1_INTERRUPT_LINE +#define PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//PSWUSCFG0_1_INTERRUPT_PIN +#define PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//PSWUSCFG0_1_VENDOR_CAP_LIST +#define PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//PSWUSCFG0_1_ADAPTER_ID_W +#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//PSWUSCFG0_1_PMI_CAP_LIST +#define PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_1_PMI_CAP +#define PSWUSCFG0_1_PMI_CAP__VERSION__SHIFT 0x0 +#define PSWUSCFG0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define PSWUSCFG0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define PSWUSCFG0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define PSWUSCFG0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define PSWUSCFG0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define PSWUSCFG0_1_PMI_CAP__VERSION_MASK 0x0007L +#define PSWUSCFG0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define PSWUSCFG0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define PSWUSCFG0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define PSWUSCFG0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define PSWUSCFG0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//PSWUSCFG0_1_PMI_STATUS_CNTL +#define PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//PSWUSCFG0_1_PCIE_CAP_LIST +#define PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_1_PCIE_CAP +#define PSWUSCFG0_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define PSWUSCFG0_1_PCIE_CAP__VERSION_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//PSWUSCFG0_1_DEVICE_CAP +#define PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define PSWUSCFG0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define PSWUSCFG0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//PSWUSCFG0_1_DEVICE_CNTL +#define PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//PSWUSCFG0_1_DEVICE_STATUS +#define PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define PSWUSCFG0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define PSWUSCFG0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//PSWUSCFG0_1_LINK_CAP +#define PSWUSCFG0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define PSWUSCFG0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define PSWUSCFG0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define PSWUSCFG0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define PSWUSCFG0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define PSWUSCFG0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define PSWUSCFG0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//PSWUSCFG0_1_LINK_CNTL +#define PSWUSCFG0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define PSWUSCFG0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define PSWUSCFG0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define PSWUSCFG0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define PSWUSCFG0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//PSWUSCFG0_1_LINK_STATUS +#define PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//PSWUSCFG0_1_DEVICE_CAP2 +#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//PSWUSCFG0_1_DEVICE_CNTL2 +#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//PSWUSCFG0_1_DEVICE_STATUS2 +#define PSWUSCFG0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define PSWUSCFG0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//PSWUSCFG0_1_LINK_CAP2 +#define PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//PSWUSCFG0_1_LINK_CNTL2 +#define PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//PSWUSCFG0_1_LINK_STATUS2 +#define PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//PSWUSCFG0_1_MSI_CAP_LIST +#define PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_1_MSI_MSG_CNTL +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//PSWUSCFG0_1_MSI_MSG_ADDR_LO +#define PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PSWUSCFG0_1_MSI_MSG_ADDR_HI +#define PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_MSI_MSG_DATA +#define PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define PSWUSCFG0_1_MSI_MSG_DATA__MSI_EXT_DATA__SHIFT 0x10 +#define PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +#define PSWUSCFG0_1_MSI_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFF0000L +//PSWUSCFG0_1_MSI_MSG_DATA_64 +#define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x10 +#define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +#define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFF0000L +//PSWUSCFG0_1_SSID_CAP_LIST +#define PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PSWUSCFG0_1_SSID_CAP +#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PSWUSCFG0_1_PCIE_PORT_VC_CNTL +#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//PSWUSCFG0_1_PCIE_PORT_VC_STATUS +#define PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//PSWUSCFG0_1_PCIE_CORR_ERR_STATUS +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//PSWUSCFG0_1_PCIE_CORR_ERR_MASK +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//PSWUSCFG0_1_PCIE_HDR_LOG0 +#define PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_HDR_LOG1 +#define PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_HDR_LOG2 +#define PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_HDR_LOG3 +#define PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_LINK_CNTL3 +#define PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS +#define PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_ACS_CAP +#define PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define PSWUSCFG0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define PSWUSCFG0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//PSWUSCFG0_1_PCIE_ACS_CNTL +#define PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define PSWUSCFG0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define PSWUSCFG0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_MC_CAP +#define PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//PSWUSCFG0_1_PCIE_MC_CNTL +#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//PSWUSCFG0_1_PCIE_MC_ADDR0 +#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//PSWUSCFG0_1_PCIE_MC_ADDR1 +#define PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_MC_RCV0 +#define PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_MC_RCV1 +#define PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_LTR_CAP +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_PCIE_ARI_CAP +#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//PSWUSCFG0_1_PCIE_ARI_CNTL +#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_DATA_LINK_FEATURE_CAP +#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1 +#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L +#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL +#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS +#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_LINK_CAP_16GT +#define PSWUSCFG0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_LINK_CNTL_16GT +#define PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//PSWUSCFG0_1_LINK_STATUS_16GT +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT +#define PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT +#define PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_MARGINING_PORT_CAP +#define PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//PSWUSCFG0_1_MARGINING_PORT_STATUS +#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST +#define PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PSWUSCFG0_1_LINK_CAP_32GT +#define PSWUSCFG0_1_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED__SHIFT 0x1 +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED__SHIFT 0x8 +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED__SHIFT 0x9 +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED__SHIFT 0xa +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define PSWUSCFG0_1_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define PSWUSCFG0_1_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED_MASK 0x00000002L +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED_MASK 0x00000100L +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED_MASK 0x00000200L +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED_MASK 0x00000400L +#define PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//PSWUSCFG0_1_LINK_CNTL_32GT +#define PSWUSCFG0_1_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE__SHIFT 0x1 +#define PSWUSCFG0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED__SHIFT 0x8 +#define PSWUSCFG0_1_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE_MASK 0x00000001L +#define PSWUSCFG0_1_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE_MASK 0x00000002L +#define PSWUSCFG0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED_MASK 0x00000700L +//PSWUSCFG0_1_LINK_STATUS_32GT +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define PSWUSCFG0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define PSWUSCFG0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define PSWUSCFG0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL__SHIFT 0x6 +#define PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define PSWUSCFG0_1_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED__SHIFT 0xa +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define PSWUSCFG0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define PSWUSCFG0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define PSWUSCFG0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL_MASK 0x000000C0L +#define PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define PSWUSCFG0_1_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED_MASK 0x00000400L +//PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC1_VENDOR_ID +#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_DEVICE_ID +#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_COMMAND +#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC1_STATUS +#define BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_REVISION_ID +#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC1_PROG_INTERFACE +#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC1_SUB_CLASS +#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC1_BASE_CLASS +#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC1_CACHE_LINE +#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC1_LATENCY +#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC1_HEADER +#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC1_BIST +#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC1_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC1_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_CAP_PTR +#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC1_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC1_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC1_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_PMI_CAP +#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_PCIE_CAP +#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC1_DEVICE_CAP +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC1_DEVICE_CNTL +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC1_DEVICE_STATUS +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC1_LINK_CAP +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_LINK_CNTL +#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC1_LINK_STATUS +#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC1_SLOT_CAP +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC1_SLOT_CNTL +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC1_SLOT_STATUS +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC1_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_LINK_CAP2 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_LINK_CNTL2 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC1_LINK_STATUS2 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_SLOT_CAP2 +#define BIF_CFG_DEV0_RC1_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC1_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_SSID_CAP +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC1_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC1_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_AP_CAP +#define BIF_CFG_DEV0_RC1_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_RC1_AP_CNTL +#define BIF_CFG_DEV0_RC1_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_RC1_AP_DATA1 +#define BIF_CFG_DEV0_RC1_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_RC1_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_RC1_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_AP_DATA2 +#define BIF_CFG_DEV0_RC1_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_RTR_DATA1 +#define BIF_CFG_DEV0_RC1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_RC1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_RTR_DATA2 +#define BIF_CFG_DEV0_RC1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_COMMAND +#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_1_STATUS +#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_LATENCY +#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_HEADER +#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_1_BIST +#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_PMI_CAP +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_AP_CAP +#define BIF_CFG_DEV0_EPF0_1_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_1_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_1_AP_CNTL +#define BIF_CFG_DEV0_EPF0_1_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_1_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_1_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_1_AP_DATA1 +#define BIF_CFG_DEV0_EPF0_1_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_1_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_1_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_EPF0_1_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_1_AP_DATA2 +#define BIF_CFG_DEV0_EPF0_1_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_1_BIST +#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_1_BIST +#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_1_BIST +#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_1_BIST +#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_1_BIST +#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_1_BIST +#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_1_BIST +#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_1_BIST +#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF8_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF8_1_BIST +#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF9_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF9_1_BIST +#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF10_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF10_1_BIST +#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF11_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF11_1_BIST +#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF12_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF12_1_BIST +#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF13_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF13_1_BIST +#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF14_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF14_1_BIST +#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF15_1_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_HEADER +#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF15_1_BIST +#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_COMMAND +#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_1_STATUS +#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_REVISION_ID +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_LATENCY +#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_HEADER +#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_1_BIST +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_1_CAP_PTR +#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PMI_CAP +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_1_LINK_CAP +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MASK +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +//BIF_CFG_DEV0_EPF2_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_COMMAND +#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_1_STATUS +#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_REVISION_ID +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_LATENCY +#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_HEADER +#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF2_1_BIST +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF2_1_CAP_PTR +#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PMI_CAP +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_SBRN +#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_FLADJ +#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK 0x3FL +#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF2_1_LINK_CAP +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF2_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF2_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MASK +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF2_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF2_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +//BIF_CFG_DEV0_EPF3_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_COMMAND +#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_1_STATUS +#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_REVISION_ID +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_LATENCY +#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_HEADER +#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF3_1_BIST +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF3_1_CAP_PTR +#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PMI_CAP +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_SBRN +#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_FLADJ +#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK 0x3FL +#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF3_1_LINK_CAP +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF3_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF3_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MASK +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA1__VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA1__VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF3_1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L + +#define PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK 0x00010000L + +#endif diff --git a/extra/amdpci/headers/osssys_6_0_0_offset.h b/extra/amdpci/headers/osssys_6_0_0_offset.h new file mode 100644 index 0000000000..969e006b85 --- /dev/null +++ b/extra/amdpci/headers/osssys_6_0_0_offset.h @@ -0,0 +1,267 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _osssys_6_0_0_OFFSET_HEADER +#define _osssys_6_0_0_OFFSET_HEADER + + + +// addressBlock: osssys_osssysdec +// base address: 0x4280 +#define regIH_VMID_0_LUT 0x0000 +#define regIH_VMID_0_LUT_BASE_IDX 0 +#define regIH_VMID_1_LUT 0x0001 +#define regIH_VMID_1_LUT_BASE_IDX 0 +#define regIH_VMID_2_LUT 0x0002 +#define regIH_VMID_2_LUT_BASE_IDX 0 +#define regIH_VMID_3_LUT 0x0003 +#define regIH_VMID_3_LUT_BASE_IDX 0 +#define regIH_VMID_4_LUT 0x0004 +#define regIH_VMID_4_LUT_BASE_IDX 0 +#define regIH_VMID_5_LUT 0x0005 +#define regIH_VMID_5_LUT_BASE_IDX 0 +#define regIH_VMID_6_LUT 0x0006 +#define regIH_VMID_6_LUT_BASE_IDX 0 +#define regIH_VMID_7_LUT 0x0007 +#define regIH_VMID_7_LUT_BASE_IDX 0 +#define regIH_VMID_8_LUT 0x0008 +#define regIH_VMID_8_LUT_BASE_IDX 0 +#define regIH_VMID_9_LUT 0x0009 +#define regIH_VMID_9_LUT_BASE_IDX 0 +#define regIH_VMID_10_LUT 0x000a +#define regIH_VMID_10_LUT_BASE_IDX 0 +#define regIH_VMID_11_LUT 0x000b +#define regIH_VMID_11_LUT_BASE_IDX 0 +#define regIH_VMID_12_LUT 0x000c +#define regIH_VMID_12_LUT_BASE_IDX 0 +#define regIH_VMID_13_LUT 0x000d +#define regIH_VMID_13_LUT_BASE_IDX 0 +#define regIH_VMID_14_LUT 0x000e +#define regIH_VMID_14_LUT_BASE_IDX 0 +#define regIH_VMID_15_LUT 0x000f +#define regIH_VMID_15_LUT_BASE_IDX 0 +#define regIH_VMID_0_LUT_MM 0x0010 +#define regIH_VMID_0_LUT_MM_BASE_IDX 0 +#define regIH_VMID_1_LUT_MM 0x0011 +#define regIH_VMID_1_LUT_MM_BASE_IDX 0 +#define regIH_VMID_2_LUT_MM 0x0012 +#define regIH_VMID_2_LUT_MM_BASE_IDX 0 +#define regIH_VMID_3_LUT_MM 0x0013 +#define regIH_VMID_3_LUT_MM_BASE_IDX 0 +#define regIH_VMID_4_LUT_MM 0x0014 +#define regIH_VMID_4_LUT_MM_BASE_IDX 0 +#define regIH_VMID_5_LUT_MM 0x0015 +#define regIH_VMID_5_LUT_MM_BASE_IDX 0 +#define regIH_VMID_6_LUT_MM 0x0016 +#define regIH_VMID_6_LUT_MM_BASE_IDX 0 +#define regIH_VMID_7_LUT_MM 0x0017 +#define regIH_VMID_7_LUT_MM_BASE_IDX 0 +#define regIH_VMID_8_LUT_MM 0x0018 +#define regIH_VMID_8_LUT_MM_BASE_IDX 0 +#define regIH_VMID_9_LUT_MM 0x0019 +#define regIH_VMID_9_LUT_MM_BASE_IDX 0 +#define regIH_VMID_10_LUT_MM 0x001a +#define regIH_VMID_10_LUT_MM_BASE_IDX 0 +#define regIH_VMID_11_LUT_MM 0x001b +#define regIH_VMID_11_LUT_MM_BASE_IDX 0 +#define regIH_VMID_12_LUT_MM 0x001c +#define regIH_VMID_12_LUT_MM_BASE_IDX 0 +#define regIH_VMID_13_LUT_MM 0x001d +#define regIH_VMID_13_LUT_MM_BASE_IDX 0 +#define regIH_VMID_14_LUT_MM 0x001e +#define regIH_VMID_14_LUT_MM_BASE_IDX 0 +#define regIH_VMID_15_LUT_MM 0x001f +#define regIH_VMID_15_LUT_MM_BASE_IDX 0 +#define regIH_COOKIE_0 0x0020 +#define regIH_COOKIE_0_BASE_IDX 0 +#define regIH_COOKIE_1 0x0021 +#define regIH_COOKIE_1_BASE_IDX 0 +#define regIH_COOKIE_2 0x0022 +#define regIH_COOKIE_2_BASE_IDX 0 +#define regIH_COOKIE_3 0x0023 +#define regIH_COOKIE_3_BASE_IDX 0 +#define regIH_COOKIE_4 0x0024 +#define regIH_COOKIE_4_BASE_IDX 0 +#define regIH_COOKIE_5 0x0025 +#define regIH_COOKIE_5_BASE_IDX 0 +#define regIH_COOKIE_6 0x0026 +#define regIH_COOKIE_6_BASE_IDX 0 +#define regIH_COOKIE_7 0x0027 +#define regIH_COOKIE_7_BASE_IDX 0 +#define regIH_REGISTER_LAST_PART0 0x003f +#define regIH_REGISTER_LAST_PART0_BASE_IDX 0 +#define regIH_RB_CNTL 0x0080 +#define regIH_RB_CNTL_BASE_IDX 0 +#define regIH_RB_BASE 0x0081 +#define regIH_RB_BASE_BASE_IDX 0 +#define regIH_RB_BASE_HI 0x0082 +#define regIH_RB_BASE_HI_BASE_IDX 0 +#define regIH_RB_RPTR 0x0083 +#define regIH_RB_RPTR_BASE_IDX 0 +#define regIH_RB_WPTR 0x0084 +#define regIH_RB_WPTR_BASE_IDX 0 +#define regIH_RB_WPTR_ADDR_HI 0x0085 +#define regIH_RB_WPTR_ADDR_HI_BASE_IDX 0 +#define regIH_RB_WPTR_ADDR_LO 0x0086 +#define regIH_RB_WPTR_ADDR_LO_BASE_IDX 0 +#define regIH_DOORBELL_RPTR 0x0087 +#define regIH_DOORBELL_RPTR_BASE_IDX 0 +#define regIH_DOORBELL_RETRY_CAM 0x0088 +#define regIH_DOORBELL_RETRY_CAM_BASE_IDX 0 +#define regIH_RB_CNTL_RING1 0x008c +#define regIH_RB_CNTL_RING1_BASE_IDX 0 +#define regIH_RB_BASE_RING1 0x008d +#define regIH_RB_BASE_RING1_BASE_IDX 0 +#define regIH_RB_BASE_HI_RING1 0x008e +#define regIH_RB_BASE_HI_RING1_BASE_IDX 0 +#define regIH_RB_RPTR_RING1 0x008f +#define regIH_RB_RPTR_RING1_BASE_IDX 0 +#define regIH_RB_WPTR_RING1 0x0090 +#define regIH_RB_WPTR_RING1_BASE_IDX 0 +#define regIH_DOORBELL_RPTR_RING1 0x0093 +#define regIH_DOORBELL_RPTR_RING1_BASE_IDX 0 +#define regIH_RETRY_CAM_ACK 0x00a4 +#define regIH_RETRY_CAM_ACK_BASE_IDX 0 +#define regIH_VERSION 0x00a5 +#define regIH_VERSION_BASE_IDX 0 +#define regIH_CNTL 0x00c0 +#define regIH_CNTL_BASE_IDX 0 +#define regIH_CNTL2 0x00c1 +#define regIH_CNTL2_BASE_IDX 0 +#define regIH_STATUS 0x00c2 +#define regIH_STATUS_BASE_IDX 0 +#define regIH_PERFMON_CNTL 0x00c3 +#define regIH_PERFMON_CNTL_BASE_IDX 0 +#define regIH_PERFCOUNTER0_RESULT 0x00c4 +#define regIH_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define regIH_PERFCOUNTER1_RESULT 0x00c5 +#define regIH_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define regIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 +#define regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 +#define regIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 +#define regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 +#define regIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 +#define regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 +#define regIH_DSM_MATCH_FIELD_CONTROL 0x00ca +#define regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 +#define regIH_DSM_MATCH_DATA_CONTROL 0x00cb +#define regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 +#define regIH_DSM_MATCH_FCN_ID 0x00cc +#define regIH_DSM_MATCH_FCN_ID_BASE_IDX 0 +#define regIH_LIMIT_INT_RATE_CNTL 0x00cd +#define regIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 +#define regIH_VF_RB_STATUS 0x00ce +#define regIH_VF_RB_STATUS_BASE_IDX 0 +#define regIH_VF_RB_STATUS2 0x00cf +#define regIH_VF_RB_STATUS2_BASE_IDX 0 +#define regIH_VF_RB1_STATUS 0x00d0 +#define regIH_VF_RB1_STATUS_BASE_IDX 0 +#define regIH_VF_RB1_STATUS2 0x00d1 +#define regIH_VF_RB1_STATUS2_BASE_IDX 0 +#define regIH_RB_STATUS 0x00d4 +#define regIH_RB_STATUS_BASE_IDX 0 +#define regIH_INT_FLOOD_CNTL 0x00d5 +#define regIH_INT_FLOOD_CNTL_BASE_IDX 0 +#define regIH_RB0_INT_FLOOD_STATUS 0x00d6 +#define regIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 +#define regIH_RB1_INT_FLOOD_STATUS 0x00d7 +#define regIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 +#define regIH_INT_FLOOD_STATUS 0x00d9 +#define regIH_INT_FLOOD_STATUS_BASE_IDX 0 +#define regIH_STORM_CLIENT_LIST_CNTL 0x00da +#define regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 +#define regIH_CLK_CTRL 0x00db +#define regIH_CLK_CTRL_BASE_IDX 0 +#define regIH_INT_FLAGS 0x00dc +#define regIH_INT_FLAGS_BASE_IDX 0 +#define regIH_LAST_INT_INFO0 0x00dd +#define regIH_LAST_INT_INFO0_BASE_IDX 0 +#define regIH_LAST_INT_INFO1 0x00de +#define regIH_LAST_INT_INFO1_BASE_IDX 0 +#define regIH_LAST_INT_INFO2 0x00df +#define regIH_LAST_INT_INFO2_BASE_IDX 0 +#define regIH_SCRATCH 0x00e0 +#define regIH_SCRATCH_BASE_IDX 0 +#define regIH_CLIENT_CREDIT_ERROR 0x00e1 +#define regIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 +#define regIH_COOKIE_REC_VIOLATION_LOG 0x00e4 +#define regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 +#define regIH_CREDIT_STATUS 0x00e5 +#define regIH_CREDIT_STATUS_BASE_IDX 0 +#define regIH_MMHUB_ERROR 0x00e6 +#define regIH_MMHUB_ERROR_BASE_IDX 0 +#define regIH_MEM_POWER_CTRL 0x00e9 +#define regIH_MEM_POWER_CTRL_BASE_IDX 0 +#define regIH_VF_RB_STATUS3 0x00ea +#define regIH_VF_RB_STATUS3_BASE_IDX 0 +#define regIH_VF_RB_STATUS4 0x00eb +#define regIH_VF_RB_STATUS4_BASE_IDX 0 +#define regIH_VF_RB1_STATUS3 0x00ec +#define regIH_VF_RB1_STATUS3_BASE_IDX 0 +#define regIH_RETRY_INT_CAM_CNTL 0x00ef +#define regIH_RETRY_INT_CAM_CNTL_BASE_IDX 0 +#define regIH_MEM_POWER_CTRL2 0x00f0 +#define regIH_MEM_POWER_CTRL2_BASE_IDX 0 +#define regIH_MSI_STORM_CTRL 0x00f1 +#define regIH_MSI_STORM_CTRL_BASE_IDX 0 +#define regIH_MSI_STORM_CLIENT_INDEX 0x00f2 +#define regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX 0 +#define regIH_MSI_STORM_CLIENT_DATA 0x00f3 +#define regIH_MSI_STORM_CLIENT_DATA_BASE_IDX 0 +#define regIH_REGISTER_LAST_PART2 0x00ff +#define regIH_REGISTER_LAST_PART2_BASE_IDX 0 +#define regSEM_MAILBOX 0x010a +#define regSEM_MAILBOX_BASE_IDX 0 +#define regSEM_MAILBOX_CLEAR 0x010b +#define regSEM_MAILBOX_CLEAR_BASE_IDX 0 +#define regSEM_REGISTER_LAST_PART2 0x017f +#define regSEM_REGISTER_LAST_PART2_BASE_IDX 0 +#define regIH_CLIENT_CFG 0x0184 +#define regIH_CLIENT_CFG_BASE_IDX 0 +#define regIH_RING1_CLIENT_CFG_INDEX 0x0185 +#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX 0 +#define regIH_RING1_CLIENT_CFG_DATA 0x0186 +#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX 0 +#define regIH_CLIENT_CFG_INDEX 0x0188 +#define regIH_CLIENT_CFG_INDEX_BASE_IDX 0 +#define regIH_CLIENT_CFG_DATA 0x0189 +#define regIH_CLIENT_CFG_DATA_BASE_IDX 0 +#define regIH_CID_REMAP_INDEX 0x018b +#define regIH_CID_REMAP_INDEX_BASE_IDX 0 +#define regIH_CID_REMAP_DATA 0x018c +#define regIH_CID_REMAP_DATA_BASE_IDX 0 +#define regIH_CHICKEN 0x018d +#define regIH_CHICKEN_BASE_IDX 0 +#define regIH_INT_DROP_CNTL 0x018f +#define regIH_INT_DROP_CNTL_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_VALUE0 0x0190 +#define regIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_VALUE1 0x0191 +#define regIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_MASK0 0x0192 +#define regIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_MASK1 0x0193 +#define regIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 +#define regIH_REGISTER_LAST_PART1 0x019f +#define regIH_REGISTER_LAST_PART1_BASE_IDX 0 + +#endif diff --git a/extra/amdpci/headers/osssys_6_0_0_sh_mask.h b/extra/amdpci/headers/osssys_6_0_0_sh_mask.h new file mode 100644 index 0000000000..a672a91e58 --- /dev/null +++ b/extra/amdpci/headers/osssys_6_0_0_sh_mask.h @@ -0,0 +1,979 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _osssys_6_0_0_SH_MASK_HEADER +#define _osssys_6_0_0_SH_MASK_HEADER + + +// addressBlock: osssys_osssysdec +//IH_VMID_0_LUT +#define IH_VMID_0_LUT__PASID__SHIFT 0x0 +#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_1_LUT +#define IH_VMID_1_LUT__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_2_LUT +#define IH_VMID_2_LUT__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_3_LUT +#define IH_VMID_3_LUT__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_4_LUT +#define IH_VMID_4_LUT__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_5_LUT +#define IH_VMID_5_LUT__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_6_LUT +#define IH_VMID_6_LUT__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_7_LUT +#define IH_VMID_7_LUT__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_8_LUT +#define IH_VMID_8_LUT__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_9_LUT +#define IH_VMID_9_LUT__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_10_LUT +#define IH_VMID_10_LUT__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_11_LUT +#define IH_VMID_11_LUT__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_12_LUT +#define IH_VMID_12_LUT__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_13_LUT +#define IH_VMID_13_LUT__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_14_LUT +#define IH_VMID_14_LUT__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_15_LUT +#define IH_VMID_15_LUT__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_0_LUT_MM +#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_1_LUT_MM +#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_2_LUT_MM +#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_3_LUT_MM +#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_4_LUT_MM +#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_5_LUT_MM +#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_6_LUT_MM +#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_7_LUT_MM +#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_8_LUT_MM +#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_9_LUT_MM +#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_10_LUT_MM +#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_11_LUT_MM +#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_12_LUT_MM +#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_13_LUT_MM +#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_14_LUT_MM +#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_15_LUT_MM +#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_COOKIE_0 +#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 +#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 +#define IH_COOKIE_0__RING_ID__SHIFT 0x10 +#define IH_COOKIE_0__VM_ID__SHIFT 0x18 +#define IH_COOKIE_0__RESERVED__SHIFT 0x1c +#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f +#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL +#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L +#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L +#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L +#define IH_COOKIE_0__RESERVED_MASK 0x70000000L +#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L +//IH_COOKIE_1 +#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 +#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL +//IH_COOKIE_2 +#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 +#define IH_COOKIE_2__RESERVED__SHIFT 0x10 +#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f +#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL +#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L +#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L +//IH_COOKIE_3 +#define IH_COOKIE_3__PAS_ID__SHIFT 0x0 +#define IH_COOKIE_3__RESERVED__SHIFT 0x10 +#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f +#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL +#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L +#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L +//IH_COOKIE_4 +#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 +#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL +//IH_COOKIE_5 +#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 +#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL +//IH_COOKIE_6 +#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 +#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL +//IH_COOKIE_7 +#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 +#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL +//IH_REGISTER_LAST_PART0 +#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 +#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL +//IH_RB_CNTL +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 +#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa +#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb +#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 +#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 +#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 +#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 +#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 +#define IH_RB_CNTL__MC_RO__SHIFT 0x16 +#define IH_RB_CNTL__MC_VMID__SHIFT 0x18 +#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L +#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L +#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L +#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L +#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L +#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L +#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L +#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L +#define IH_RB_CNTL__MC_RO_MASK 0x00400000L +#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L +#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//IH_RB_BASE +#define IH_RB_BASE__ADDR__SHIFT 0x0 +#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//IH_RB_BASE_HI +#define IH_RB_BASE_HI__ADDR__SHIFT 0x0 +#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL +//IH_RB_RPTR +#define IH_RB_RPTR__OFFSET__SHIFT 0x2 +#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//IH_RB_WPTR +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 +#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L +#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL +#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L +#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L +//IH_RB_WPTR_ADDR_HI +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL +//IH_RB_WPTR_ADDR_LO +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//IH_DOORBELL_RPTR +#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 +#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c +#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL +#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L +//IH_DOORBELL_RETRY_CAM +#define IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT 0x0 +#define IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT 0x1c +#define IH_DOORBELL_RETRY_CAM__OFFSET_MASK 0x03FFFFFFL +#define IH_DOORBELL_RETRY_CAM__ENABLE_MASK 0x10000000L +//IH_RB_CNTL_RING1 +#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 +#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa +#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb +#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 +#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 +#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 +#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 +#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 +#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L +#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL +#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L +#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L +#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L +#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L +#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L +#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L +#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L +#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L +#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//IH_RB_BASE_RING1 +#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 +#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL +//IH_RB_BASE_HI_RING1 +#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 +#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL +//IH_RB_RPTR_RING1 +#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 +#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL +//IH_RB_WPTR_RING1 +#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 +#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 +#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L +#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL +#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L +#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L +//IH_DOORBELL_RPTR_RING1 +#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 +#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c +#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL +#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L +//IH_RETRY_CAM_ACK +#define IH_RETRY_CAM_ACK__INDEX__SHIFT 0x0 +#define IH_RETRY_CAM_ACK__INDEX_MASK 0x000003FFL +//IH_VERSION +#define IH_VERSION__MINVER__SHIFT 0x0 +#define IH_VERSION__MAJVER__SHIFT 0x8 +#define IH_VERSION__REV__SHIFT 0x10 +#define IH_VERSION__MINVER_MASK 0x0000007FL +#define IH_VERSION__MAJVER_MASK 0x00007F00L +#define IH_VERSION__REV_MASK 0x003F0000L +//IH_CNTL +#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 +#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 +#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 +#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL +#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L +#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L +//IH_CNTL2 +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L +//IH_STATUS +#define IH_STATUS__IDLE__SHIFT 0x0 +#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 +#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 +#define IH_STATUS__RB_FULL__SHIFT 0x3 +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 +#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa +#define IH_STATUS__SWITCH_READY__SHIFT 0xb +#define IH_STATUS__RB1_FULL__SHIFT 0xc +#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd +#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe +#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 +#define IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT 0x13 +#define IH_STATUS__ZSTATES_FENCE__SHIFT 0x14 +#define IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT 0x15 +#define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT 0x16 +#define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT 0x17 +#define IH_STATUS__IDLE_MASK 0x00000001L +#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L +#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L +#define IH_STATUS__RB_FULL_MASK 0x00000008L +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L +#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L +#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L +#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L +#define IH_STATUS__SWITCH_READY_MASK 0x00000800L +#define IH_STATUS__RB1_FULL_MASK 0x00001000L +#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L +#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L +#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L +#define IH_STATUS__RETRY_INT_CAM_IDLE_MASK 0x00080000L +#define IH_STATUS__ZSTATES_FENCE_MASK 0x00100000L +#define IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK 0x00200000L +#define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK 0x00400000L +#define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK 0x00800000L +//IH_PERFMON_CNTL +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L +//IH_PERFCOUNTER0_RESULT +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//IH_PERFCOUNTER1_RESULT +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_VALUE_BIT_31_0 +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_VALUE_BIT_63_32 +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_VALUE_BIT_95_64 +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_FIELD_CONTROL +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 +#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L +#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L +#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L +//IH_DSM_MATCH_DATA_CONTROL +#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL +//IH_DSM_MATCH_FCN_ID +#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x0 +#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x7 +#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000000FL +#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000080L +//IH_LIMIT_INT_RATE_CNTL +#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 +#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 +#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 +#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 +#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 +#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L +#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL +#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L +#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L +#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L +//IH_VF_RB_STATUS +#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL +//IH_VF_RB_STATUS2 +#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL +//IH_VF_RB1_STATUS +#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 +#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL +//IH_VF_RB1_STATUS2 +#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 +#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL +//IH_RB_STATUS +#define IH_RB_STATUS__RB_FULL__SHIFT 0x0 +#define IH_RB_STATUS__RB_FULL_DRAIN__SHIFT 0x1 +#define IH_RB_STATUS__RB_OVERFLOW__SHIFT 0x2 +#define IH_RB_STATUS__RB1_FULL__SHIFT 0x4 +#define IH_RB_STATUS__RB1_FULL_DRAIN__SHIFT 0x5 +#define IH_RB_STATUS__RB1_OVERFLOW__SHIFT 0x6 +#define IH_RB_STATUS__RB_FULL_MASK 0x00000001L +#define IH_RB_STATUS__RB_FULL_DRAIN_MASK 0x00000002L +#define IH_RB_STATUS__RB_OVERFLOW_MASK 0x00000004L +#define IH_RB_STATUS__RB1_FULL_MASK 0x00000010L +#define IH_RB_STATUS__RB1_FULL_DRAIN_MASK 0x00000020L +#define IH_RB_STATUS__RB1_OVERFLOW_MASK 0x00000040L +//IH_INT_FLOOD_CNTL +#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 +#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 +#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 +#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L +#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L +#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L +//IH_RB0_INT_FLOOD_STATUS +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L +//IH_RB1_INT_FLOOD_STATUS +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L +//IH_INT_FLOOD_STATUS +#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1d +#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e +#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x20000000L +#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L +//IH_STORM_CLIENT_LIST_CNTL +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L +//IH_CLK_CTRL +#define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x17 +#define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE__SHIFT 0x18 +#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19 +#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a +#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b +#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c +#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d +#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e +#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f +#define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK 0x00800000L +#define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE_MASK 0x01000000L +#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L +#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L +#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L +#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L +#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L +#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L +#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L +//IH_INT_FLAGS +#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 +#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 +#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 +#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 +#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 +#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 +#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 +#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 +#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 +#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 +#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa +#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb +#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc +#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd +#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe +#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf +#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 +#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 +#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 +#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 +#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 +#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 +#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 +#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 +#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 +#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 +#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a +#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b +#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c +#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d +#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e +#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f +#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L +#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L +#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L +#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L +#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L +#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L +#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L +#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L +#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L +#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L +#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L +#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L +#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L +#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L +#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L +#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L +#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L +#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L +#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L +#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L +#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L +#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L +#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L +#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L +#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L +#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L +#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L +#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L +#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L +#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L +#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L +#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L +//IH_LAST_INT_INFO0 +#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 +#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 +#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 +#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 +#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f +#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL +#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L +#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L +#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L +#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L +//IH_LAST_INT_INFO1 +#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 +#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL +//IH_LAST_INT_INFO2 +#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 +#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 +#define IH_LAST_INT_INFO2__VF__SHIFT 0x17 +#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL +#define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L +#define IH_LAST_INT_INFO2__VF_MASK 0x00800000L +//IH_SCRATCH +#define IH_SCRATCH__DATA__SHIFT 0x0 +#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL +//IH_CLIENT_CREDIT_ERROR +#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa +#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb +#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc +#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd +#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe +#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf +#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a +#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b +#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c +#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d +#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e +#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f +#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L +//IH_COOKIE_REC_VIOLATION_LOG +#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8 +#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10 +#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L +#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L +//IH_CREDIT_STATUS +#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 +#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 +#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 +#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 +#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 +#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 +#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 +#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 +#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 +#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa +#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb +#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc +#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd +#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe +#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf +#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 +#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 +#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 +#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 +#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 +#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 +#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 +#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 +#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 +#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 +#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a +#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b +#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c +#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d +#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e +#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f +#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L +#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L +#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L +#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L +#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L +#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L +#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L +#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L +#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L +#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L +#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L +#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L +#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L +#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L +#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L +#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L +#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L +#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L +#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L +#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L +#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L +#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L +#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L +#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L +#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L +#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L +#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L +#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L +#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L +#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L +#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L +//IH_MMHUB_ERROR +#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 +#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 +#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 +#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 +#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 +#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 +#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L +#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L +#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L +#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L +#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L +#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L +//IH_MEM_POWER_CTRL +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT 0x10 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT 0x11 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT 0x12 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT 0x13 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT 0x14 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK 0x00010000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK 0x00020000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK 0x00040000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK 0x00080000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK 0x00700000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L +//IH_VF_RB_STATUS3 +#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK 0x0000FFFFL +//IH_VF_RB_STATUS4 +#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK 0x0000FFFFL +//IH_VF_RB1_STATUS3 +#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 +#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK 0x0000FFFFL +//IH_RETRY_INT_CAM_CNTL +#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0 +#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8 +#define IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT 0x10 +#define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE__SHIFT 0x11 +#define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE__SHIFT 0x12 +#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14 +#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL +#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00003F00L +#define IH_RETRY_INT_CAM_CNTL__ENABLE_MASK 0x00010000L +#define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE_MASK 0x00020000L +#define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE_MASK 0x00040000L +#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L +//IH_MEM_POWER_CTRL2 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT 0x0 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT 0x1 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT 0x2 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT 0x3 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT 0x4 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK 0x00000001L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK 0x00000002L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK 0x00000004L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK 0x00000008L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK 0x00000070L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L +//IH_MSI_STORM_CTRL +#define IH_MSI_STORM_CTRL__DELAY__SHIFT 0x0 +#define IH_MSI_STORM_CTRL__DELAY_MASK 0x00000FFFL +//IH_MSI_STORM_CLIENT_INDEX +#define IH_MSI_STORM_CLIENT_INDEX__INDEX__SHIFT 0x0 +#define IH_MSI_STORM_CLIENT_INDEX__INDEX_MASK 0x00000007L +//IH_MSI_STORM_CLIENT_DATA +#define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID__SHIFT 0x0 +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID__SHIFT 0x8 +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 +#define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE__SHIFT 0x11 +#define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID__SHIFT 0x1f +#define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID_MASK 0x000000FFL +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MASK 0x0000FF00L +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L +#define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE_MASK 0x00020000L +#define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID_MASK 0x80000000L +//IH_REGISTER_LAST_PART2 +#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 +#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL +//SEM_MAILBOX +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 +#define SEM_MAILBOX__RESERVED__SHIFT 0x10 +#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL +#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L +//SEM_MAILBOX_CLEAR +#define SEM_MAILBOX_CLEAR__CLEAR__SHIFT 0x0 +#define SEM_MAILBOX_CLEAR__RESERVED__SHIFT 0x10 +#define SEM_MAILBOX_CLEAR__CLEAR_MASK 0x0000FFFFL +#define SEM_MAILBOX_CLEAR__RESERVED_MASK 0xFFFF0000L +//SEM_REGISTER_LAST_PART2 +#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 +#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL +//IH_CLIENT_CFG +#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 +#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000003FL +//IH_RING1_CLIENT_CFG_INDEX +#define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 +#define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK 0x00000007L +//IH_RING1_CLIENT_CFG_DATA +#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT 0x0 +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT 0x8 +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 +#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK 0x000000FFL +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK 0x0000FF00L +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L +//IH_CLIENT_CFG_INDEX +#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 +#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL +//IH_CLIENT_CFG_DATA +#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 +#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 +#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19 +#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L +#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L +#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L +//IH_CID_REMAP_INDEX +#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 +#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L +//IH_CID_REMAP_DATA +#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 +#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 +#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18 +#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL +#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L +#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L +//IH_CHICKEN +#define IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT 0x2 +#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 +#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 +#define IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK 0x00000004L +#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L +#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L +//IH_INT_DROP_CNTL +#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 +#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 +#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 +#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 +#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 +#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 +#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 +#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 +#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 +#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L +#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L +#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L +#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L +#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L +#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L +#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L +#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L +#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L +//IH_INT_DROP_MATCH_VALUE0 +#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 +#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 +#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 +#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 +#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 +#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL +#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L +#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x001F0000L +#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L +#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L +//IH_INT_DROP_MATCH_VALUE1 +#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 +#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL +//IH_INT_DROP_MATCH_MASK0 +#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 +#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 +#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 +#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 +#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 +#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL +#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L +#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x001F0000L +#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L +#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L +//IH_INT_DROP_MATCH_MASK1 +#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 +#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL +//IH_REGISTER_LAST_PART1 +#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 +#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL + +#endif diff --git a/extra/amdpci/headers/psp_gfx_if.h b/extra/amdpci/headers/psp_gfx_if.h new file mode 100644 index 0000000000..a85d3491f4 --- /dev/null +++ b/extra/amdpci/headers/psp_gfx_if.h @@ -0,0 +1,471 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _PSP_TEE_GFX_IF_H_ +#define _PSP_TEE_GFX_IF_H_ + +#define PSP_GFX_CMD_BUF_VERSION 0x00000001 + +#define GFX_CMD_STATUS_MASK 0x0000FFFF +#define GFX_CMD_ID_MASK 0x000F0000 +#define GFX_CMD_RESERVED_MASK 0x7FF00000 +#define GFX_CMD_RESPONSE_MASK 0x80000000 + +/* USBC PD FW version retrieval command */ +#define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000 + +/* TEE Gfx Command IDs for the register interface. +* Command ID must be between 0x00010000 and 0x000F0000. +*/ +enum psp_gfx_crtl_cmd_id +{ + GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ + GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ + GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ + GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ + GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */ + GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */ + GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */ + GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */ + GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to psp for updating write pointer of vf */ + GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */ + + GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ +}; + + +/*----------------------------------------------------------------------------- + NOTE: All physical addresses used in this interface are actually + GPU Virtual Addresses. +*/ + + +/* Control registers of the TEE Gfx interface. These are located in +* SRBM-to-PSP mailbox registers (total 8 registers). +*/ +struct psp_gfx_ctrl +{ + volatile unsigned int cmd_resp; /* +0 Command/Response register for Gfx commands */ + volatile unsigned int rbi_wptr; /* +4 Write pointer (index) of RBI ring */ + volatile unsigned int rbi_rptr; /* +8 Read pointer (index) of RBI ring */ + volatile unsigned int gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ + volatile unsigned int gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ + volatile unsigned int ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/ + volatile unsigned int ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */ + volatile unsigned int ring_buf_size; /* +28 Ring buffer size (in bytes) */ + +}; + + +/* Response flag is set in the command when command is completed by PSP. +* Used in the GFX_CTRL.CmdResp. +* When PSP GFX I/F is initialized, the flag is set. +*/ +#define GFX_FLAG_RESPONSE 0x80000000 + +/* TEE Gfx Command IDs for the ring buffer interface. */ +enum psp_gfx_cmd_id +{ + GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ + GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ + GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ + GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ + GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ + GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ + GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */ + GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */ + GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */ + GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */ + GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */ + GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F, /* Query GPUVA of the Fw Attestation DB */ + /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */ + GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */ + GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */ + GFX_CMD_ID_BOOT_CFG = 0x00000022, /* Boot Config */ + GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027, /* Configure spatial partitioning mode */ +}; + +/* PSP boot config sub-commands */ +enum psp_gfx_boot_config_cmd +{ + BOOTCFG_CMD_SET = 1, /* Set boot configuration settings */ + BOOTCFG_CMD_GET = 2, /* Get boot configuration settings */ + BOOTCFG_CMD_INVALIDATE = 3 /* Reset current boot configuration settings to VBIOS defaults */ +}; + +/* PSP boot config bitmask values */ +enum psp_gfx_boot_config +{ + BOOT_CONFIG_GECC = 0x1, +}; + +/* Command to load Trusted Application binary into PSP OS. */ +struct psp_gfx_cmd_load_ta +{ + unsigned int app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */ + unsigned int app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */ + unsigned int app_len; /* length of the TA binary in bytes */ + unsigned int cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */ + unsigned int cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */ + unsigned int cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ + + /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided + * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead + * of using global persistent buffer. + */ +}; + + +/* Command to Unload Trusted Application binary from PSP OS. */ +struct psp_gfx_cmd_unload_ta +{ + unsigned int session_id; /* Session ID of the loaded TA to be unloaded */ + +}; + + +/* Shared buffers for InvokeCommand. +*/ +struct psp_gfx_buf_desc +{ + unsigned int buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */ + unsigned int buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */ + unsigned int buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ + +}; + +/* Max number of descriptors for one shared buffer (in how many different +* physical locations one shared buffer can be stored). If buffer is too much +* fragmented, error will be returned. +*/ +#define GFX_BUF_MAX_DESC 64 + +struct psp_gfx_buf_list +{ + unsigned int num_desc; /* number of buffer descriptors in the list */ + unsigned int total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ + struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ + + /* total 776 bytes */ +}; + +/* Command to execute InvokeCommand entry point of the TA. */ +struct psp_gfx_cmd_invoke_cmd +{ + unsigned int session_id; /* Session ID of the TA to be executed */ + unsigned int ta_cmd_id; /* Command ID to be sent to TA */ + struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ + +}; + + +/* Command to setup TMR region. */ +struct psp_gfx_cmd_setup_tmr +{ + unsigned int buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */ + unsigned int buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */ + unsigned int buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ + union { + struct { + unsigned int sriov_enabled:1; /* whether the device runs under SR-IOV*/ + unsigned int virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/ + unsigned int reserved:30; + } bitfield; + unsigned int tmr_flags; + }; + unsigned int system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */ + unsigned int system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffer */ + +}; + +/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ +enum psp_gfx_fw_type { + GFX_FW_TYPE_NONE = 0, /* */ + GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */ + GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */ + GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */ + GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */ + GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */ + GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */ + GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */ + GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */ + GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */ + GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */ + GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */ + GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */ + GFX_FW_TYPE_VCN = 13, /* VCN RV */ + GFX_FW_TYPE_UVD = 14, /* UVD VG */ + GFX_FW_TYPE_VCE = 15, /* VCE VG */ + GFX_FW_TYPE_ISP = 16, /* ISP RV */ + GFX_FW_TYPE_ACP = 17, /* ACP RV */ + GFX_FW_TYPE_SMU = 18, /* SMU VG */ + GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */ + GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */ + GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */ + GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */ + GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */ + GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */ + GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */ + GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */ + GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */ + GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */ + GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */ + GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */ + GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */ + GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */ + GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */ + GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */ + GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */ + GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */ + GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */ + GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */ + GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */ + GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */ + GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */ + GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */ + GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */ + GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */ + GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */ + GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */ + GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */ + GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */ + GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */ + GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */ + GFX_FW_TYPE_DMUB = 51, /* DMUB RN */ + GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */ + GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */ + GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */ + GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */ + GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */ + GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */ + GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */ + GFX_FW_TYPE_CAP = 62, /* CAP_FW */ + GFX_FW_TYPE_SE2_TAP_DELAYS = 65, /* SE2 TAP DELAYS NV */ + GFX_FW_TYPE_SE3_TAP_DELAYS = 66, /* SE3 TAP DELAYS NV */ + GFX_FW_TYPE_REG_LIST = 67, /* REG_LIST MI */ + GFX_FW_TYPE_IMU_I = 68, /* IMU Instruction FW SOC21 */ + GFX_FW_TYPE_IMU_D = 69, /* IMU Data FW SOC21 */ + GFX_FW_TYPE_LSDMA = 70, /* LSDMA FW SOC21 */ + GFX_FW_TYPE_SDMA_UCODE_TH0 = 71, /* SDMA Thread 0/CTX SOC21 */ + GFX_FW_TYPE_SDMA_UCODE_TH1 = 72, /* SDMA Thread 1/CTL SOC21 */ + GFX_FW_TYPE_PPTABLE = 73, /* PPTABLE SOC21 */ + GFX_FW_TYPE_DISCRETE_USB4 = 74, /* dUSB4 FW SOC21 */ + GFX_FW_TYPE_TA = 75, /* SRIOV TA FW UUID SOC21 */ + GFX_FW_TYPE_RS64_MES = 76, /* RS64 MES ucode SOC21 */ + GFX_FW_TYPE_RS64_MES_STACK = 77, /* RS64 MES stack ucode SOC21 */ + GFX_FW_TYPE_RS64_KIQ = 78, /* RS64 KIQ ucode SOC21 */ + GFX_FW_TYPE_RS64_KIQ_STACK = 79, /* RS64 KIQ Heap stack SOC21 */ + GFX_FW_TYPE_ISP_DATA = 80, /* ISP DATA SOC21 */ + GFX_FW_TYPE_CP_MES_KIQ = 81, /* MES KIQ ucode SOC21 */ + GFX_FW_TYPE_MES_KIQ_STACK = 82, /* MES KIQ stack SOC21 */ + GFX_FW_TYPE_UMSCH_DATA = 83, /* User Mode Scheduler Data SOC21 */ + GFX_FW_TYPE_UMSCH_UCODE = 84, /* User Mode Scheduler Ucode SOC21 */ + GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85, /* User Mode Scheduler Command Buffer SOC21 */ + GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */ + GFX_FW_TYPE_RS64_PFP = 87, /* RS64 PFP SOC21 */ + GFX_FW_TYPE_RS64_ME = 88, /* RS64 ME SOC21 */ + GFX_FW_TYPE_RS64_MEC = 89, /* RS64 MEC SOC21 */ + GFX_FW_TYPE_RS64_PFP_P0_STACK = 90, /* RS64 PFP stack P0 SOC21 */ + GFX_FW_TYPE_RS64_PFP_P1_STACK = 91, /* RS64 PFP stack P1 SOC21 */ + GFX_FW_TYPE_RS64_ME_P0_STACK = 92, /* RS64 ME stack P0 SOC21 */ + GFX_FW_TYPE_RS64_ME_P1_STACK = 93, /* RS64 ME stack P1 SOC21 */ + GFX_FW_TYPE_RS64_MEC_P0_STACK = 94, /* RS64 MEC stack P0 SOC21 */ + GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */ + GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */ + GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */ + GFX_FW_TYPE_VPEC_FW1 = 100, /* VPEC FW1 To Save VPE */ + GFX_FW_TYPE_VPEC_FW2 = 101, /* VPEC FW2 To Save VPE */ + GFX_FW_TYPE_VPE = 102, + GFX_FW_TYPE_JPEG_RAM = 128, /**< JPEG Command buffer */ + GFX_FW_TYPE_P2S_TABLE = 129, + GFX_FW_TYPE_MAX +}; + +/* Command to load HW IP FW. */ +struct psp_gfx_cmd_load_ip_fw +{ + unsigned int fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ + unsigned int fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ + unsigned int fw_size; /* FW buffer size in bytes */ + enum psp_gfx_fw_type fw_type; /* FW type */ + +}; + +/* Command to save/restore HW IP FW. */ +struct psp_gfx_cmd_save_restore_ip_fw +{ + unsigned int save_fw; /* if set, command is used for saving fw otherwise for resetoring*/ + unsigned int save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */ + unsigned int save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */ + unsigned int buf_size; /* Size of the save/restore buffer in bytes */ + enum psp_gfx_fw_type fw_type; /* FW type */ +}; + +/* Command to setup register program */ +struct psp_gfx_cmd_reg_prog { + unsigned int reg_value; + unsigned int reg_id; +}; + +/* Command to load TOC */ +struct psp_gfx_cmd_load_toc +{ + unsigned int toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ + unsigned int toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ + unsigned int toc_size; /* FW buffer size in bytes */ +}; + +/* Dynamic boot configuration */ +struct psp_gfx_cmd_boot_cfg +{ + unsigned int timestamp; /* calendar time as number of seconds */ + enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process command data */ + unsigned int boot_config; /* dynamic boot configuration bitmask */ + unsigned int boot_config_valid; /* dynamic boot configuration valid bits bitmask */ +}; + +struct psp_gfx_cmd_sriov_spatial_part { + unsigned int mode; + unsigned int override_ips; + unsigned int override_xcds_avail; + unsigned int override_this_aid; +}; + +/* All GFX ring buffer commands. */ +union psp_gfx_commands +{ + struct psp_gfx_cmd_load_ta cmd_load_ta; + struct psp_gfx_cmd_unload_ta cmd_unload_ta; + struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; + struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; + struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; + struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw; + struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog; + struct psp_gfx_cmd_setup_tmr cmd_setup_vmr; + struct psp_gfx_cmd_load_toc cmd_load_toc; + struct psp_gfx_cmd_boot_cfg boot_cfg; + struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; +}; + +struct psp_gfx_uresp_reserved +{ + unsigned int reserved[8]; +}; + +/* Command-specific response for Fw Attestation Db */ +struct psp_gfx_uresp_fwar_db_info +{ + unsigned int fwar_db_addr_lo; + unsigned int fwar_db_addr_hi; +}; + +/* Command-specific response for boot config. */ +struct psp_gfx_uresp_bootcfg { + unsigned int boot_cfg; /* boot config data */ +}; + +/* Union of command-specific responses for GPCOM ring. */ +union psp_gfx_uresp { + struct psp_gfx_uresp_reserved reserved; + struct psp_gfx_uresp_bootcfg boot_cfg; + struct psp_gfx_uresp_fwar_db_info fwar_db_info; +}; + +/* Structure of GFX Response buffer. +* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI +* it is separate buffer. +*/ +struct psp_gfx_resp +{ + unsigned int status; /* +0 status of command execution */ + unsigned int session_id; /* +4 session ID in response to LoadTa command */ + unsigned int fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ + unsigned int fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ + unsigned int tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */ + + unsigned int reserved[11]; + + union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */ + + /* total 96 bytes */ +}; + +/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi +* and psp_gfx_rb_frame.cmd_buf_addr_lo. +*/ +struct psp_gfx_cmd_resp +{ + unsigned int buf_size; /* +0 total size of the buffer in bytes */ + unsigned int buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ + unsigned int cmd_id; /* +8 command ID */ + + /* These fields are used for RBI only. They are all 0 in GPCOM commands + */ + unsigned int resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */ + unsigned int resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */ + unsigned int resp_offset; /* +20 offset within response buffer */ + unsigned int resp_buf_size; /* +24 total size of the response buffer in bytes */ + + union psp_gfx_commands cmd; /* +28 command specific structures */ + + unsigned char reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; + + /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response + * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. + */ + struct psp_gfx_resp resp; /* +864 response */ + + unsigned char reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; + + /* total size 1024 bytes */ +}; + + +#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ + +/* Structure of the Ring Buffer Frame */ +struct psp_gfx_rb_frame +{ + unsigned int cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */ + unsigned int cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */ + unsigned int cmd_buf_size; /* +8 command buffer size in bytes */ + unsigned int fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */ + unsigned int fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */ + unsigned int fence_value; /* +20 Fence value */ + unsigned int sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ + unsigned int sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ + unsigned char vmid; /* +32 VMID value used for mapping of all addresses for this frame */ + unsigned char frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ + unsigned char reserved1[2]; /* +34 reserved, must be 0 */ + unsigned int reserved2[7]; /* +36 reserved, must be 0 */ + /* total 64 bytes */ +}; + +#define PSP_ERR_UNKNOWN_COMMAND 0x00000100 + +enum tee_error_code { + TEE_SUCCESS = 0x00000000, + TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A, +}; + +#endif /* _PSP_TEE_GFX_IF_H_ */ diff --git a/extra/amdpci/headers/smu13_driver_if_v13_0_0.h b/extra/amdpci/headers/smu13_driver_if_v13_0_0.h new file mode 100644 index 0000000000..95813513fc --- /dev/null +++ b/extra/amdpci/headers/smu13_driver_if_v13_0_0.h @@ -0,0 +1,1641 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU13_DRIVER_IF_V13_0_0_H +#define SMU13_DRIVER_IF_V13_0_0_H + +#define int32_t int +#define uint32_t unsigned int +#define int8_t signed char +#define uint8_t unsigned char +#define uint16_t unsigned short +#define int16_t short +#define uint64_t unsigned long long +#define bool _Bool + +#define SMU13_0_0_DRIVER_IF_VERSION 0x3D + +//Increment this version if SkuTable_t or BoardTable_t change +#define PPTABLE_VERSION 0x2B + +#define NUM_GFXCLK_DPM_LEVELS 16 +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_MP0CLK_DPM_LEVELS 2 +#define NUM_DCLK_DPM_LEVELS 8 +#define NUM_VCLK_DPM_LEVELS 8 +#define NUM_DISPCLK_DPM_LEVELS 8 +#define NUM_DPPCLK_DPM_LEVELS 8 +#define NUM_DPREFCLK_DPM_LEVELS 8 +#define NUM_DCFCLK_DPM_LEVELS 8 +#define NUM_DTBCLK_DPM_LEVELS 8 +#define NUM_UCLK_DPM_LEVELS 4 +#define NUM_LINK_LEVELS 3 +#define NUM_FCLK_DPM_LEVELS 8 +#define NUM_OD_FAN_MAX_POINTS 6 + +// Feature Control Defines +#define FEATURE_FW_DATA_READ_BIT 0 +#define FEATURE_DPM_GFXCLK_BIT 1 +#define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 +#define FEATURE_DPM_UCLK_BIT 3 +#define FEATURE_DPM_FCLK_BIT 4 +#define FEATURE_DPM_SOCCLK_BIT 5 +#define FEATURE_DPM_MP0CLK_BIT 6 +#define FEATURE_DPM_LINK_BIT 7 +#define FEATURE_DPM_DCN_BIT 8 +#define FEATURE_VMEMP_SCALING_BIT 9 +#define FEATURE_VDDIO_MEM_SCALING_BIT 10 +#define FEATURE_DS_GFXCLK_BIT 11 +#define FEATURE_DS_SOCCLK_BIT 12 +#define FEATURE_DS_FCLK_BIT 13 +#define FEATURE_DS_LCLK_BIT 14 +#define FEATURE_DS_DCFCLK_BIT 15 +#define FEATURE_DS_UCLK_BIT 16 +#define FEATURE_GFX_ULV_BIT 17 +#define FEATURE_FW_DSTATE_BIT 18 +#define FEATURE_GFXOFF_BIT 19 +#define FEATURE_BACO_BIT 20 +#define FEATURE_MM_DPM_BIT 21 +#define FEATURE_SOC_MPCLK_DS_BIT 22 +#define FEATURE_BACO_MPCLK_DS_BIT 23 +#define FEATURE_THROTTLERS_BIT 24 +#define FEATURE_SMARTSHIFT_BIT 25 +#define FEATURE_GTHR_BIT 26 +#define FEATURE_ACDC_BIT 27 +#define FEATURE_VR0HOT_BIT 28 +#define FEATURE_FW_CTF_BIT 29 +#define FEATURE_FAN_CONTROL_BIT 30 +#define FEATURE_GFX_DCS_BIT 31 +#define FEATURE_GFX_READ_MARGIN_BIT 32 +#define FEATURE_LED_DISPLAY_BIT 33 +#define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 +#define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 +#define FEATURE_OPTIMIZED_VMIN_BIT 36 +#define FEATURE_GFX_IMU_BIT 37 +#define FEATURE_BOOT_TIME_CAL_BIT 38 +#define FEATURE_GFX_PCC_DFLL_BIT 39 +#define FEATURE_SOC_CG_BIT 40 +#define FEATURE_DF_CSTATE_BIT 41 +#define FEATURE_GFX_EDC_BIT 42 +#define FEATURE_BOOT_POWER_OPT_BIT 43 +#define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 +#define FEATURE_DS_VCN_BIT 45 +#define FEATURE_BACO_CG_BIT 46 +#define FEATURE_MEM_TEMP_READ_BIT 47 +#define FEATURE_ATHUB_MMHUB_PG_BIT 48 +#define FEATURE_SOC_PCC_BIT 49 +#define FEATURE_EDC_PWRBRK_BIT 50 +#define FEATURE_BOMXCO_SVI3_PROG_BIT 51 +#define FEATURE_SPARE_52_BIT 52 +#define FEATURE_SPARE_53_BIT 53 +#define FEATURE_SPARE_54_BIT 54 +#define FEATURE_SPARE_55_BIT 55 +#define FEATURE_SPARE_56_BIT 56 +#define FEATURE_SPARE_57_BIT 57 +#define FEATURE_SPARE_58_BIT 58 +#define FEATURE_SPARE_59_BIT 59 +#define FEATURE_SPARE_60_BIT 60 +#define FEATURE_SPARE_61_BIT 61 +#define FEATURE_SPARE_62_BIT 62 +#define FEATURE_SPARE_63_BIT 63 +#define NUM_FEATURES 64 + +#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL +#define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ + (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ + (1 << FEATURE_DPM_UCLK_BIT) | \ + (1 << FEATURE_DPM_FCLK_BIT) | \ + (1 << FEATURE_DPM_SOCCLK_BIT) | \ + (1 << FEATURE_DPM_MP0CLK_BIT) | \ + (1 << FEATURE_DPM_LINK_BIT) | \ + (1 << FEATURE_DPM_DCN_BIT) | \ + (1 << FEATURE_DS_GFXCLK_BIT) | \ + (1 << FEATURE_DS_SOCCLK_BIT) | \ + (1 << FEATURE_DS_FCLK_BIT) | \ + (1 << FEATURE_DS_LCLK_BIT) | \ + (1 << FEATURE_DS_DCFCLK_BIT) | \ + (1 << FEATURE_DS_UCLK_BIT) | \ + (1ULL << FEATURE_DS_VCN_BIT)) + +//For use with feature control messages +typedef enum { + FEATURE_PWR_ALL, + FEATURE_PWR_S5, + FEATURE_PWR_BACO, + FEATURE_PWR_SOC, + FEATURE_PWR_GFX, + FEATURE_PWR_DOMAIN_COUNT, +} FEATURE_PWR_DOMAIN_e; + + +// Debug Overrides Bitmask +#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 +#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 +#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 +#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 +#define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 +#define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 +#define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 +#define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 +#define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 +#define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 +#define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 +#define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 +#define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 + +// VR Mapping Bit Defines +#define VR_MAPPING_VR_SELECT_MASK 0x01 +#define VR_MAPPING_VR_SELECT_SHIFT 0x00 + +#define VR_MAPPING_PLANE_SELECT_MASK 0x02 +#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 + +// PSI Bit Defines +#define PSI_SEL_VR0_PLANE0_PSI0 0x01 +#define PSI_SEL_VR0_PLANE0_PSI1 0x02 +#define PSI_SEL_VR0_PLANE1_PSI0 0x04 +#define PSI_SEL_VR0_PLANE1_PSI1 0x08 +#define PSI_SEL_VR1_PLANE0_PSI0 0x10 +#define PSI_SEL_VR1_PLANE0_PSI1 0x20 +#define PSI_SEL_VR1_PLANE1_PSI0 0x40 +#define PSI_SEL_VR1_PLANE1_PSI1 0x80 + +typedef enum { + SVI_PSI_0, // Full phase count (default) + SVI_PSI_1, // Phase count 1st level + SVI_PSI_2, // Phase count 2nd level + SVI_PSI_3, // Single phase operation + active diode emulation + SVI_PSI_4, // Single phase operation + passive diode emulation *optional* + SVI_PSI_5, // Reserved + SVI_PSI_6, // Power down to 0V (voltage regulation disabled) + SVI_PSI_7, // Automated phase shedding and diode emulation +} SVI_PSI_e; + +// Throttler Control/Status Bits +#define THROTTLER_TEMP_EDGE_BIT 0 +#define THROTTLER_TEMP_HOTSPOT_BIT 1 +#define THROTTLER_TEMP_HOTSPOT_G_BIT 2 +#define THROTTLER_TEMP_HOTSPOT_M_BIT 3 +#define THROTTLER_TEMP_MEM_BIT 4 +#define THROTTLER_TEMP_VR_GFX_BIT 5 +#define THROTTLER_TEMP_VR_MEM0_BIT 6 +#define THROTTLER_TEMP_VR_MEM1_BIT 7 +#define THROTTLER_TEMP_VR_SOC_BIT 8 +#define THROTTLER_TEMP_VR_U_BIT 9 +#define THROTTLER_TEMP_LIQUID0_BIT 10 +#define THROTTLER_TEMP_LIQUID1_BIT 11 +#define THROTTLER_TEMP_PLX_BIT 12 +#define THROTTLER_TDC_GFX_BIT 13 +#define THROTTLER_TDC_SOC_BIT 14 +#define THROTTLER_TDC_U_BIT 15 +#define THROTTLER_PPT0_BIT 16 +#define THROTTLER_PPT1_BIT 17 +#define THROTTLER_PPT2_BIT 18 +#define THROTTLER_PPT3_BIT 19 +#define THROTTLER_FIT_BIT 20 +#define THROTTLER_GFX_APCC_PLUS_BIT 21 +#define THROTTLER_COUNT 22 + +// FW DState Features Control Bits +#define FW_DSTATE_SOC_ULV_BIT 0 +#define FW_DSTATE_G6_HSR_BIT 1 +#define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 +#define FW_DSTATE_SMN_DS_BIT 3 +#define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 +#define FW_DSTATE_SOC_LIV_MIN_BIT 5 +#define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 +#define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 +#define FW_DSTATE_MALL_ALLOC_BIT 8 +#define FW_DSTATE_MEM_PSI_BIT 9 +#define FW_DSTATE_HSR_NON_STROBE_BIT 10 +#define FW_DSTATE_MP0_ENTER_WFI_BIT 11 +#define FW_DSTATE_U_ULV_BIT 12 +#define FW_DSTATE_MALL_FLUSH_BIT 13 +#define FW_DSTATE_SOC_PSI_BIT 14 +#define FW_DSTATE_U_PSI_BIT 15 +#define FW_DSTATE_UCP_DS_BIT 16 +#define FW_DSTATE_CSRCLK_DS_BIT 17 +#define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 +#define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 +#define FW_DSTATE_CLDO_PRG_BIT 20 +#define FW_DSTATE_DF_PLL_PWRDN_BIT 21 +#define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 +#define FW_DSTATE_GFX_PSI6_BIT 23 +#define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 + +//LED Display Mask & Control Bits +#define LED_DISPLAY_GFX_DPM_BIT 0 +#define LED_DISPLAY_PCIE_BIT 1 +#define LED_DISPLAY_ERROR_BIT 2 + + +#define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 +#define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 +#define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 + +typedef enum { + SMARTSHIFT_VERSION_1, + SMARTSHIFT_VERSION_2, + SMARTSHIFT_VERSION_3, +} SMARTSHIFT_VERSION_e; + +typedef enum { + FOPT_CALC_AC_CALC_DC, + FOPT_PPTABLE_AC_CALC_DC, + FOPT_CALC_AC_PPTABLE_DC, + FOPT_PPTABLE_AC_PPTABLE_DC, +} FOPT_CALC_e; + +typedef enum { + DRAM_BIT_WIDTH_DISABLED = 0, + DRAM_BIT_WIDTH_X_8 = 8, + DRAM_BIT_WIDTH_X_16 = 16, + DRAM_BIT_WIDTH_X_32 = 32, + DRAM_BIT_WIDTH_X_64 = 64, + DRAM_BIT_WIDTH_X_128 = 128, + DRAM_BIT_WIDTH_COUNT, +} DRAM_BIT_WIDTH_TYPE_e; + +//I2C Interface +#define NUM_I2C_CONTROLLERS 8 + +#define I2C_CONTROLLER_ENABLED 1 +#define I2C_CONTROLLER_DISABLED 0 + +#define MAX_SW_I2C_COMMANDS 24 + +typedef enum { + I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 + I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 + I2C_CONTROLLER_PORT_COUNT, +} I2cControllerPort_e; + +typedef enum { + I2C_CONTROLLER_NAME_VR_GFX = 0, + I2C_CONTROLLER_NAME_VR_SOC, + I2C_CONTROLLER_NAME_VR_VMEMP, + I2C_CONTROLLER_NAME_VR_VDDIO, + I2C_CONTROLLER_NAME_LIQUID0, + I2C_CONTROLLER_NAME_LIQUID1, + I2C_CONTROLLER_NAME_PLX, + I2C_CONTROLLER_NAME_FAN_INTAKE, + I2C_CONTROLLER_NAME_COUNT, +} I2cControllerName_e; + +typedef enum { + I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, + I2C_CONTROLLER_THROTTLER_VR_GFX, + I2C_CONTROLLER_THROTTLER_VR_SOC, + I2C_CONTROLLER_THROTTLER_VR_VMEMP, + I2C_CONTROLLER_THROTTLER_VR_VDDIO, + I2C_CONTROLLER_THROTTLER_LIQUID0, + I2C_CONTROLLER_THROTTLER_LIQUID1, + I2C_CONTROLLER_THROTTLER_PLX, + I2C_CONTROLLER_THROTTLER_FAN_INTAKE, + I2C_CONTROLLER_THROTTLER_INA3221, + I2C_CONTROLLER_THROTTLER_COUNT, +} I2cControllerThrottler_e; + +typedef enum { + I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, + I2C_CONTROLLER_PROTOCOL_VR_IR35217, + I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, + I2C_CONTROLLER_PROTOCOL_INA3221, + I2C_CONTROLLER_PROTOCOL_TMP_MAX6604, + I2C_CONTROLLER_PROTOCOL_COUNT, +} I2cControllerProtocol_e; + +typedef struct { + uint8_t Enabled; + uint8_t Speed; + uint8_t SlaveAddress; + uint8_t ControllerPort; + uint8_t ControllerName; + uint8_t ThermalThrotter; + uint8_t I2cProtocol; + uint8_t PaddingConfig; +} I2cControllerConfig_t; + +typedef enum { + I2C_PORT_SVD_SCL = 0, + I2C_PORT_GPIO, +} I2cPort_e; + +typedef enum { + I2C_SPEED_FAST_50K = 0, //50 Kbits/s + I2C_SPEED_FAST_100K, //100 Kbits/s + I2C_SPEED_FAST_400K, //400 Kbits/s + I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) + I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) + I2C_SPEED_HIGH_2M, //2.3 Mbits/s + I2C_SPEED_COUNT, +} I2cSpeed_e; + +typedef enum { + I2C_CMD_READ = 0, + I2C_CMD_WRITE, + I2C_CMD_COUNT, +} I2cCmdType_e; + +#define CMDCONFIG_STOP_BIT 0 +#define CMDCONFIG_RESTART_BIT 1 +#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write + +#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) +#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) +#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) + +typedef struct { + uint8_t ReadWriteData; //Return data for read. Data to send for write + uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write +} SwI2cCmd_t; //SW I2C Command Table + +typedef struct { + uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) + uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select + uint8_t SlaveAddress; //Slave address of device + uint8_t NumCmds; //Number of commands + + SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; +} SwI2cRequest_t; // SW I2C Request Table + +typedef struct { + SwI2cRequest_t SwI2cRequest; + + uint32_t Spare[8]; + uint32_t MmHubPadding[8]; // SMU internal use +} SwI2cRequestExternal_t; + +typedef struct { + uint64_t mca_umc_status; + uint64_t mca_umc_addr; + + uint16_t ce_count_lo_chip; + uint16_t ce_count_hi_chip; + + uint32_t eccPadding; +} EccInfo_t; + +typedef struct { + EccInfo_t EccInfo[24]; +} EccInfoTable_t; + +//D3HOT sequences +typedef enum { + BACO_SEQUENCE, + MSR_SEQUENCE, + BAMACO_SEQUENCE, + ULPS_SEQUENCE, + D3HOT_SEQUENCE_COUNT, +} D3HOTSequence_e; + +//This is aligned with RSMU PGFSM Register Mapping +typedef enum { + PG_DYNAMIC_MODE = 0, + PG_STATIC_MODE, +} PowerGatingMode_e; + +//This is aligned with RSMU PGFSM Register Mapping +typedef enum { + PG_POWER_DOWN = 0, + PG_POWER_UP, +} PowerGatingSettings_e; + +typedef struct { + uint32_t a; // store in IEEE float format in this variable + uint32_t b; // store in IEEE float format in this variable + uint32_t c; // store in IEEE float format in this variable +} QuadraticInt_t; + +typedef struct { + uint32_t m; // store in IEEE float format in this variable + uint32_t b; // store in IEEE float format in this variable +} LinearInt_t; + +typedef struct { + uint32_t a; // store in IEEE float format in this variable + uint32_t b; // store in IEEE float format in this variable + uint32_t c; // store in IEEE float format in this variable +} DroopInt_t; + +typedef enum { + DCS_ARCH_DISABLED, + DCS_ARCH_FADCS, + DCS_ARCH_ASYNC, +} DCS_ARCH_e; + +//Only Clks that have DPM descriptors are listed here +typedef enum { + PPCLK_GFXCLK = 0, + PPCLK_SOCCLK, + PPCLK_UCLK, + PPCLK_FCLK, + PPCLK_DCLK_0, + PPCLK_VCLK_0, + PPCLK_DCLK_1, + PPCLK_VCLK_1, + PPCLK_DISPCLK, + PPCLK_DPPCLK, + PPCLK_DPREFCLK, + PPCLK_DCFCLK, + PPCLK_DTBCLK, + PPCLK_COUNT, +} PPCLK_e; + +typedef enum { + VOLTAGE_MODE_PPTABLE = 0, + VOLTAGE_MODE_FUSES, + VOLTAGE_MODE_COUNT, +} VOLTAGE_MODE_e; + + +typedef enum { + AVFS_VOLTAGE_GFX = 0, + AVFS_VOLTAGE_SOC, + AVFS_VOLTAGE_COUNT, +} AVFS_VOLTAGE_TYPE_e; + +typedef enum { + AVFS_TEMP_COLD = 0, + AVFS_TEMP_HOT, + AVFS_TEMP_COUNT, +} AVFS_TEMP_e; + +typedef enum { + AVFS_D_G, + AVFS_D_M_B, + AVFS_D_M_S, + AVFS_D_COUNT, +} AVFS_D_e; + +typedef enum { + UCLK_DIV_BY_1 = 0, + UCLK_DIV_BY_2, + UCLK_DIV_BY_4, + UCLK_DIV_BY_8, +} UCLK_DIV_e; + +typedef enum { + GPIO_INT_POLARITY_ACTIVE_LOW = 0, + GPIO_INT_POLARITY_ACTIVE_HIGH, +} GpioIntPolarity_e; + +typedef enum { + PWR_CONFIG_TDP = 0, + PWR_CONFIG_TGP, + PWR_CONFIG_TCP_ESTIMATED, + PWR_CONFIG_TCP_MEASURED, +} PwrConfig_e; + +typedef struct { + uint8_t Padding; + uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM + uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used + uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e + LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) + uint32_t Padding3[3]; + uint16_t Padding4; + uint16_t FoptimalDc; //Foptimal frequency in DC power mode. + uint16_t FoptimalAc; //Foptimal frequency in AC power mode. + uint16_t Padding2; +} DpmDescriptor_t; + +typedef enum { + PPT_THROTTLER_PPT0, + PPT_THROTTLER_PPT1, + PPT_THROTTLER_PPT2, + PPT_THROTTLER_PPT3, + PPT_THROTTLER_COUNT +} PPT_THROTTLER_e; + +typedef enum { + TEMP_EDGE, + TEMP_HOTSPOT, + TEMP_HOTSPOT_G, + TEMP_HOTSPOT_M, + TEMP_MEM, + TEMP_VR_GFX, + TEMP_VR_MEM0, + TEMP_VR_MEM1, + TEMP_VR_SOC, + TEMP_VR_U, + TEMP_LIQUID0, + TEMP_LIQUID1, + TEMP_PLX, + TEMP_COUNT, +} TEMP_e; + +typedef enum { + TDC_THROTTLER_GFX, + TDC_THROTTLER_SOC, + TDC_THROTTLER_U, + TDC_THROTTLER_COUNT +} TDC_THROTTLER_e; + +typedef enum { + SVI_PLANE_GFX, + SVI_PLANE_SOC, + SVI_PLANE_VMEMP, + SVI_PLANE_VDDIO_MEM, + SVI_PLANE_U, + SVI_PLANE_COUNT, +} SVI_PLANE_e; + +typedef enum { + PMFW_VOLT_PLANE_GFX, + PMFW_VOLT_PLANE_SOC, + PMFW_VOLT_PLANE_COUNT +} PMFW_VOLT_PLANE_e; + +typedef enum { + CUSTOMER_VARIANT_ROW, + CUSTOMER_VARIANT_FALCON, + CUSTOMER_VARIANT_COUNT, +} CUSTOMER_VARIANT_e; + +typedef enum { + POWER_SOURCE_AC, + POWER_SOURCE_DC, + POWER_SOURCE_COUNT, +} POWER_SOURCE_e; + +typedef enum { + MEM_VENDOR_PLACEHOLDER0, + MEM_VENDOR_SAMSUNG, + MEM_VENDOR_INFINEON, + MEM_VENDOR_ELPIDA, + MEM_VENDOR_ETRON, + MEM_VENDOR_NANYA, + MEM_VENDOR_HYNIX, + MEM_VENDOR_MOSEL, + MEM_VENDOR_WINBOND, + MEM_VENDOR_ESMT, + MEM_VENDOR_PLACEHOLDER1, + MEM_VENDOR_PLACEHOLDER2, + MEM_VENDOR_PLACEHOLDER3, + MEM_VENDOR_PLACEHOLDER4, + MEM_VENDOR_PLACEHOLDER5, + MEM_VENDOR_MICRON, + MEM_VENDOR_COUNT, +} MEM_VENDOR_e; + +typedef enum { + PP_GRTAVFS_HW_CPO_CTL_ZONE0, + PP_GRTAVFS_HW_CPO_CTL_ZONE1, + PP_GRTAVFS_HW_CPO_CTL_ZONE2, + PP_GRTAVFS_HW_CPO_CTL_ZONE3, + PP_GRTAVFS_HW_CPO_CTL_ZONE4, + PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, + PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, + PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, + PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, + PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, + PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, + PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, + PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, + PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, + PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, + PP_GRTAVFS_HW_ZONE0_VF, + PP_GRTAVFS_HW_ZONE1_VF1, + PP_GRTAVFS_HW_ZONE2_VF2, + PP_GRTAVFS_HW_ZONE3_VF3, + PP_GRTAVFS_HW_VOLTAGE_GB, + PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, + PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, + PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, + PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, + PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, + PP_GRTAVFS_HW_RESERVED_0, + PP_GRTAVFS_HW_RESERVED_1, + PP_GRTAVFS_HW_RESERVED_2, + PP_GRTAVFS_HW_RESERVED_3, + PP_GRTAVFS_HW_RESERVED_4, + PP_GRTAVFS_HW_RESERVED_5, + PP_GRTAVFS_HW_RESERVED_6, + PP_GRTAVFS_HW_FUSE_COUNT, +} PP_GRTAVFS_HW_FUSE_e; + +typedef enum { + PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, + PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, + PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, + PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, + PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, + PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, + PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, + PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, + PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, + PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, + PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, + PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, + PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, + PP_GRTAVFS_FW_COMMON_FUSE_COUNT, +} PP_GRTAVFS_FW_COMMON_FUSE_e; + +typedef enum { + PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, + PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, + PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, + PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, + PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, + PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, + PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, + PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, + PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, + PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, + PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, + PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, + PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, + PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, + PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, + PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, + PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, + PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, + PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, + PP_GRTAVFS_FW_SEP_FUSE_COUNT, +} PP_GRTAVFS_FW_SEP_FUSE_e; + +#define PP_NUM_RTAVFS_PWL_ZONES 5 + +#define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 +#define PP_OD_FEATURE_PPT_BIT 2 +#define PP_OD_FEATURE_FAN_CURVE_BIT 3 +#define PP_OD_FEATURE_GFXCLK_BIT 7 +#define PP_OD_FEATURE_UCLK_BIT 8 +#define PP_OD_FEATURE_ZERO_FAN_BIT 9 +#define PP_OD_FEATURE_TEMPERATURE_BIT 10 +#define PP_OD_FEATURE_COUNT 13 + +// VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 +// Slope Q1.7, Offset Q1.2 +typedef struct { + int8_t Offset; // in Amps + uint8_t Padding; + uint16_t MaxCurrent; // in Amps +} SviTelemetryScale_t; + +#define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 + +typedef enum { + FAN_MODE_AUTO = 0, + FAN_MODE_MANUAL_LINEAR, +} FanMode_e; + +typedef struct { + uint32_t FeatureCtrlMask; + + //Voltage control + int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; + + uint32_t Reserved; + + //Frequency changes + int16_t GfxclkFmin; // MHz + int16_t GfxclkFmax; // MHz + uint16_t UclkFmin; // MHz + uint16_t UclkFmax; // MHz + + //PPT + int16_t Ppt; // % + int16_t Tdc; + + //Fan control + uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; + uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; + uint16_t FanMinimumPwm; + uint16_t AcousticTargetRpmThreshold; + uint16_t AcousticLimitRpmThreshold; + uint16_t FanTargetTemperature; // Degree Celcius + uint8_t FanZeroRpmEnable; + uint8_t FanZeroRpmStopTemp; + uint8_t FanMode; + uint8_t MaxOpTemp; + + uint32_t Spare[13]; + uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround +} OverDriveTable_t; + +typedef struct { + OverDriveTable_t OverDriveTable; + +} OverDriveTableExternal_t; + +typedef struct { + uint32_t FeatureCtrlMask; + + int16_t VoltageOffsetPerZoneBoundary; + uint16_t Reserved1; + + uint16_t Reserved2; + + int16_t GfxclkFmin; // MHz + int16_t GfxclkFmax; // MHz + uint16_t UclkFmin; // MHz + uint16_t UclkFmax; // MHz + + //PPT + int16_t Ppt; // % + int16_t Tdc; + + uint8_t FanLinearPwmPoints; + uint8_t FanLinearTempPoints; + uint16_t FanMinimumPwm; + uint16_t AcousticTargetRpmThreshold; + uint16_t AcousticLimitRpmThreshold; + uint16_t FanTargetTemperature; // Degree Celcius + uint8_t FanZeroRpmEnable; + uint8_t FanZeroRpmStopTemp; + uint8_t FanMode; + uint8_t MaxOpTemp; + + uint32_t Spare[13]; + +} OverDriveLimits_t; + + +typedef enum { + BOARD_GPIO_SMUIO_0, + BOARD_GPIO_SMUIO_1, + BOARD_GPIO_SMUIO_2, + BOARD_GPIO_SMUIO_3, + BOARD_GPIO_SMUIO_4, + BOARD_GPIO_SMUIO_5, + BOARD_GPIO_SMUIO_6, + BOARD_GPIO_SMUIO_7, + BOARD_GPIO_SMUIO_8, + BOARD_GPIO_SMUIO_9, + BOARD_GPIO_SMUIO_10, + BOARD_GPIO_SMUIO_11, + BOARD_GPIO_SMUIO_12, + BOARD_GPIO_SMUIO_13, + BOARD_GPIO_SMUIO_14, + BOARD_GPIO_SMUIO_15, + BOARD_GPIO_SMUIO_16, + BOARD_GPIO_SMUIO_17, + BOARD_GPIO_SMUIO_18, + BOARD_GPIO_SMUIO_19, + BOARD_GPIO_SMUIO_20, + BOARD_GPIO_SMUIO_21, + BOARD_GPIO_SMUIO_22, + BOARD_GPIO_SMUIO_23, + BOARD_GPIO_SMUIO_24, + BOARD_GPIO_SMUIO_25, + BOARD_GPIO_SMUIO_26, + BOARD_GPIO_SMUIO_27, + BOARD_GPIO_SMUIO_28, + BOARD_GPIO_SMUIO_29, + BOARD_GPIO_SMUIO_30, + BOARD_GPIO_SMUIO_31, + MAX_BOARD_GPIO_SMUIO_NUM, + BOARD_GPIO_DC_GEN_A, + BOARD_GPIO_DC_GEN_B, + BOARD_GPIO_DC_GEN_C, + BOARD_GPIO_DC_GEN_D, + BOARD_GPIO_DC_GEN_E, + BOARD_GPIO_DC_GEN_F, + BOARD_GPIO_DC_GEN_G, + BOARD_GPIO_DC_GENLK_CLK, + BOARD_GPIO_DC_GENLK_VSYNC, + BOARD_GPIO_DC_SWAPLOCK_A, + BOARD_GPIO_DC_SWAPLOCK_B, +} BOARD_GPIO_TYPE_e; + +#define INVALID_BOARD_GPIO 0xFF + +#define MARKETING_BASE_CLOCKS 0 +#define MARKETING_GAME_CLOCKS 1 +#define MARKETING_BOOST_CLOCKS 2 + +typedef struct { + //PLL 0 + uint16_t InitGfxclk_bypass; + uint16_t InitSocclk; + uint16_t InitMp0clk; + uint16_t InitMpioclk; + uint16_t InitSmnclk; + uint16_t InitUcpclk; + uint16_t InitCsrclk; + //PLL 1 + + uint16_t InitDprefclk; + uint16_t InitDcfclk; + uint16_t InitDtbclk; + //PLL 2 + uint16_t InitDclk; //assume same DCLK/VCLK for both instances + uint16_t InitVclk; + // PLL 3 + uint16_t InitUsbdfsclk; + uint16_t InitMp1clk; + uint16_t InitLclk; + uint16_t InitBaco400clk_bypass; + uint16_t InitBaco1200clk_bypass; + uint16_t InitBaco700clk_bypass; + // PLL 4 + uint16_t InitFclk; + // PLL 5 + uint16_t InitGfxclk_clkb; + + //PLL 6 + uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk + + uint8_t Padding[3]; + + uint32_t InitVcoFreqPll0; + uint32_t InitVcoFreqPll1; + uint32_t InitVcoFreqPll2; + uint32_t InitVcoFreqPll3; + uint32_t InitVcoFreqPll4; + uint32_t InitVcoFreqPll5; + uint32_t InitVcoFreqPll6; + + //encoding will change depending on SVI2/SVI3 + uint16_t InitGfx; // In mV(Q2) , should be 0? + uint16_t InitSoc; // In mV(Q2) + uint16_t InitU; // In Mv(Q2) + + uint16_t Padding2; + + uint32_t Spare[8]; + +} BootValues_t; + + +typedef struct { + uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts + uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps + + uint16_t Temperature[TEMP_COUNT]; // Celsius + + uint8_t PwmLimitMin; + uint8_t PwmLimitMax; + uint8_t FanTargetTemperature; + uint8_t Spare1[1]; + + uint16_t AcousticTargetRpmThresholdMin; + uint16_t AcousticTargetRpmThresholdMax; + + uint16_t AcousticLimitRpmThresholdMin; + uint16_t AcousticLimitRpmThresholdMax; + + uint16_t PccLimitMin; + uint16_t PccLimitMax; + + uint16_t FanStopTempMin; + uint16_t FanStopTempMax; + uint16_t FanStartTempMin; + uint16_t FanStartTempMax; + + uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; + uint32_t Spare[11]; + +} MsgLimits_t; + +typedef struct { + uint16_t BaseClockAc; + uint16_t GameClockAc; + uint16_t BoostClockAc; + uint16_t BaseClockDc; + uint16_t GameClockDc; + uint16_t BoostClockDc; + + uint32_t Reserved[4]; +} DriverReportedClocks_t; + +typedef struct { + uint8_t DcBtcEnabled; + uint8_t Padding[3]; + + uint16_t DcTol; // mV Q2 + uint16_t DcBtcGb; // mV Q2 + + uint16_t DcBtcMin; // mV Q2 + uint16_t DcBtcMax; // mV Q2 + + LinearInt_t DcBtcGbScalar; + +} AvfsDcBtcParams_t; + +typedef struct { + uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C + uint16_t VftFMin; // in MHz + uint16_t VInversion; // in mV Q2 + QuadraticInt_t qVft[AVFS_TEMP_COUNT]; + QuadraticInt_t qAvfsGb; + QuadraticInt_t qAvfsGb2; +} AvfsFuseOverride_t; + +typedef struct { + // SECTION: Version + + uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) + + // SECTION: Feature Control + uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping + + // SECTION: Miscellaneous Configuration + uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e + uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e + uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT + uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e + + // SECTION: Infrastructure Limits + uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported + uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported + + uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift + + //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars + //relative index 0 + uint8_t EnableLegacyPptLimit; + uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support + uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting + + uint8_t PaddingPpt[1]; + + uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature + + uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail + + uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input + + uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only + + uint16_t PaddingInfra; + + // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) + uint32_t FitControllerFailureRateLimit; //in IEEE float + //Expected GFX Duty Cycle at Vmax. + uint32_t FitControllerGfxDutyCycle; // in IEEE float + //Expected SOC Duty Cycle at Vmax. + uint32_t FitControllerSocDutyCycle; // in IEEE float + + //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. + uint32_t FitControllerSocOffset; //in IEEE float + + uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value + + // SECTION: Throttler settings + uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping + + // SECTION: FW DSTATE Settings + uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping + + // SECTION: Voltage Control Parameters + uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) + + uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) + uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE + + // Voltage Limits + uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled + uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled + + //Vmin Optimizations + int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin + int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin + uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. + uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. + uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. + uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. + uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin + uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot + uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold + + //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. + uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; + //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. + uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; + //Scalar coefficient of the PSM aging degradation function + uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM + //Exponential coefficient of the PSM aging degradation function + uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM + //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. + uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN + //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. + uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN + + uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; + uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; + + uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms + uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms + + QuadraticInt_t Vmin_droop; + uint32_t SpareVmin[9]; + + + //SECTION: DPM Configuration 1 + DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; + + uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz + uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz + + uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz + + // SECTION: DPM Configuration 2 + uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz + uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) + + uint8_t GfxclkSpare[2]; + uint16_t GfxclkFreqCap; + + //GFX Idle Power Settings + uint16_t GfxclkFgfxoffEntry; // in Mhz + uint16_t GfxclkFgfxoffExitImu; // in Mhz + uint16_t GfxclkFgfxoffExitRlc; // in Mhz + uint16_t GfxclkThrottleClock; //Used primarily in DCS + uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages + uint8_t GfxIdlePadding; + + uint8_t SmsRepairWRCKClkDivEn; + uint8_t SmsRepairWRCKClkDivVal; + uint8_t GfxOffEntryEarlyMGCGEn; + uint8_t GfxOffEntryForceCGCGEn; + uint8_t GfxOffEntryForceCGCGDelayEn; + uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds + + uint16_t GfxclkFreqGfxUlv; // in MHz + uint8_t GfxIdlePadding2[2]; + + uint32_t GfxOffEntryHysteresis; + uint32_t GfxoffSpare[15]; + + // GFX GPO + uint32_t DfllBtcMasterScalerM; + int32_t DfllBtcMasterScalerB; + uint32_t DfllBtcSlaveScalerM; + int32_t DfllBtcSlaveScalerB; + + uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg + uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg + + uint32_t DfllL2FrequencyBoostM; //Unitless (float) + uint32_t DfllL2FrequencyBoostB; //In MHz (integer) + uint32_t GfxGpoSpare[8]; + + // GFX DCS + + uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase + uint16_t PaddingDcs; + + uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase + uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. + + uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. + + uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. + uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. + + uint8_t FoptEnabled; + uint8_t DcsSpare2[3]; + uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation + uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation + + uint32_t DcsSpare[11]; + + // UCLK section + uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz + uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations + uint8_t PaddingMem[3]; + + uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. + uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 + + uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) + uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) + + //FCLK Section + + uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. + uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. + uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state + uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value + uint16_t PaddingFclk; + + // Link DPM Settings + uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 + uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 + uint16_t LclkFreq[NUM_LINK_LEVELS]; + + // SECTION: Fan Control + uint16_t FanStopTemp[TEMP_COUNT]; //Celsius + uint16_t FanStartTemp[TEMP_COUNT]; //Celsius + + uint16_t FanGain[TEMP_COUNT]; + uint16_t FanGainPadding; + + uint16_t FanPwmMin; + uint16_t AcousticTargetRpmThreshold; + uint16_t AcousticLimitRpmThreshold; + uint16_t FanMaximumRpm; + uint16_t MGpuAcousticLimitRpmThreshold; + uint16_t FanTargetGfxclk; + uint32_t TempInputSelectMask; + uint8_t FanZeroRpmEnable; + uint8_t FanTachEdgePerRev; + uint16_t FanTargetTemperature[TEMP_COUNT]; + + // The following are AFC override parameters. Leave at 0 to use FW defaults. + int16_t FuzzyFan_ErrorSetDelta; + int16_t FuzzyFan_ErrorRateSetDelta; + int16_t FuzzyFan_PwmSetDelta; + uint16_t FuzzyFan_Reserved; + + uint16_t FwCtfLimit[TEMP_COUNT]; + + uint16_t IntakeTempEnableRPM; + int16_t IntakeTempOffsetTemp; + uint16_t IntakeTempReleaseTemp; + uint16_t IntakeTempHighIntakeAcousticLimit; + uint16_t IntakeTempAcouticLimitReleaseRate; + + int16_t FanAbnormalTempLimitOffset; + uint16_t FanStalledTriggerRpm; + uint16_t FanAbnormalTriggerRpmCoeff; + uint16_t FanAbnormalDetectionEnable; + + uint8_t FanIntakeSensorSupport; + uint8_t FanIntakePadding[3]; + uint32_t FanSpare[13]; + + // SECTION: VDD_GFX AVFS + + uint8_t OverrideGfxAvfsFuses; + uint8_t GfxAvfsPadding[3]; + + uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding + uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; + + uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; + + uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; + uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; + + uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; + uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; + uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; + uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; + + uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; + + uint32_t dGbV_dT_vmin; + uint32_t dGbV_dT_vmax; + + //Unused: PMFW-9370 + uint32_t V2F_vmin_range_low; + uint32_t V2F_vmin_range_high; + uint32_t V2F_vmax_range_low; + uint32_t V2F_vmax_range_high; + + AvfsDcBtcParams_t DcBtcGfxParams; + + uint32_t GfxAvfsSpare[32]; + + //SECTION: VDD_SOC AVFS + + uint8_t OverrideSocAvfsFuses; + uint8_t MinSocAvfsRevision; + uint8_t SocAvfsPadding[2]; + + AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; + + DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb + + LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V + + QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V + + AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; + + uint32_t SocAvfsSpare[32]; + + //SECTION: Boot clock and voltage values + BootValues_t BootValues; + + //SECTION: Driver Reported Clocks + DriverReportedClocks_t DriverReportedClocks; + + //SECTION: Message Limits + MsgLimits_t MsgLimits; + + //SECTION: OverDrive Limits + OverDriveLimits_t OverDriveLimitsMin; + OverDriveLimits_t OverDriveLimitsBasicMax; + uint32_t reserved[22]; + + // SECTION: Advanced Options + uint32_t DebugOverrides; + + // Section: Total Board Power idle vs active coefficients + uint8_t TotalBoardPowerSupport; + uint8_t TotalBoardPowerPadding[3]; + + int16_t TotalIdleBoardPowerM; + int16_t TotalIdleBoardPowerB; + int16_t TotalBoardPowerM; + int16_t TotalBoardPowerB; + + //PMFW-11158 + QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; + QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; + QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; + + uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature limit associated with Hynix + uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature limit associated with Micron + uint16_t TemperatureFwCtfLimit_Hynix; + uint16_t TemperatureFwCtfLimit_Micron; + + // SECTION: Sku Reserved + uint32_t Spare[41]; + + // Padding for MMHUB - do not modify this + uint32_t MmHubPadding[8]; + +} SkuTable_t; + +typedef struct { + // SECTION: Version + uint32_t Version; //should be unique to each board type + + + // SECTION: I2C Control + I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; + + // SECTION: SVI2 Board Parameters + uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields + uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields + uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields + uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields + + uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + + //SECTION SVI3 Board Parameters + uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; + uint8_t VrPsiSupport[SVI_PLANE_COUNT]; + + uint8_t PaddingPsi[SVI_PLANE_COUNT]; + uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 + + // SECTION: Voltage Regulator Settings + SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; + uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) + + uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; + + // SECTION: GPIO Settings + + uint8_t LedOffGpio; + uint8_t FanOffGpio; + uint8_t GfxVrPowerStageOffGpio; + + uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching + uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching + uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event + uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event + + uint8_t GthrGpio; // GPIO pin configured for GTHR Event + uint8_t GthrPolarity; // replace GPIO polarity for GTHR + + // LED Display Settings + uint8_t LedPin0; // GPIO number for LedPin[0] + uint8_t LedPin1; // GPIO number for LedPin[1] + uint8_t LedPin2; // GPIO number for LedPin[2] + uint8_t LedEnableMask; + + uint8_t LedPcie; // GPIO number for PCIE results + uint8_t LedError; // GPIO number for Error Cases + + // SECTION: Clock Spread Spectrum + + // UCLK Spread Spectrum + uint8_t UclkTrainingModeSpreadPercent; + uint8_t UclkSpreadPadding; + uint16_t UclkSpreadFreq; // kHz + + // UCLK Spread Spectrum + uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; + + uint8_t GfxclkSpreadEnable; + + // FCLK Spread Spectrum + uint8_t FclkSpreadPercent; // Q4.4 + uint16_t FclkSpreadFreq; // kHz + + // Section: Memory Config + uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e + uint8_t PaddingMem1[7]; + + // SECTION: UMC feature flags + uint8_t HsrEnabled; + uint8_t VddqOffEnabled; + uint8_t PaddingUmcFlags[2]; + + uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued + uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS + + uint8_t FuseWritePowerMuxPresent; + uint8_t FuseWritePadding[3]; + + // SECTION: Board Reserved + uint32_t BoardSpare[63]; + + // SECTION: Structure Padding + + // Padding for MMHUB - do not modify this + uint32_t MmHubPadding[8]; +} BoardTable_t; + +#pragma pack(push, 1) +typedef struct { + SkuTable_t SkuTable; + BoardTable_t BoardTable; +} PPTable_t; +#pragma pack(pop) + +typedef struct { + // Time constant parameters for clock averages in ms + uint16_t GfxclkAverageLpfTau; + uint16_t FclkAverageLpfTau; + uint16_t UclkAverageLpfTau; + uint16_t GfxActivityLpfTau; + uint16_t UclkActivityLpfTau; + uint16_t SocketPowerLpfTau; + uint16_t VcnClkAverageLpfTau; + uint16_t VcnUsageAverageLpfTau; +} DriverSmuConfig_t; + +typedef struct { + DriverSmuConfig_t DriverSmuConfig; + + uint32_t Spare[8]; + // Padding - ignore + uint32_t MmHubPadding[8]; // SMU internal use +} DriverSmuConfigExternal_t; + + +typedef struct { + + uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz + uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz + + uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz + + uint16_t Padding; + + uint32_t Spare[32]; + + // Padding - ignore + uint32_t MmHubPadding[8]; // SMU internal use + +} DriverInfoTable_t; + +typedef struct { + uint32_t CurrClock[PPCLK_COUNT]; + + uint16_t AverageGfxclkFrequencyTarget; + uint16_t AverageGfxclkFrequencyPreDs; + uint16_t AverageGfxclkFrequencyPostDs; + uint16_t AverageFclkFrequencyPreDs; + uint16_t AverageFclkFrequencyPostDs; + uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock + uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock + uint16_t AverageVclk0Frequency ; + uint16_t AverageDclk0Frequency ; + uint16_t AverageVclk1Frequency ; + uint16_t AverageDclk1Frequency ; + uint16_t PCIeBusy; + uint16_t dGPU_W_MAX; + uint16_t padding; + + uint32_t MetricsCounter; + + uint16_t AvgVoltage[SVI_PLANE_COUNT]; + uint16_t AvgCurrent[SVI_PLANE_COUNT]; + + uint16_t AverageGfxActivity ; + uint16_t AverageUclkActivity ; + uint16_t Vcn0ActivityPercentage ; + uint16_t Vcn1ActivityPercentage ; + + uint32_t EnergyAccumulator; + uint16_t AverageSocketPower; + uint16_t AverageTotalBoardPower; + + uint16_t AvgTemperature[TEMP_COUNT]; + uint16_t AvgTemperatureFanIntake; + + uint8_t PcieRate ; + uint8_t PcieWidth ; + + uint8_t AvgFanPwm; + uint8_t Padding[1]; + uint16_t AvgFanRpm; + + + uint8_t ThrottlingPercentage[THROTTLER_COUNT]; + uint8_t VmaxThrottlingPercentage; + uint8_t Padding1[3]; + + //metrics for D3hot entry/exit and driver ARM msgs + uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; + uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; + uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; + + uint16_t ApuSTAPMSmartShiftLimit; + uint16_t ApuSTAPMLimit; + uint16_t AvgApuSocketPower; + + uint16_t AverageUclkActivity_MAX; + + uint32_t PublicSerialNumberLower; + uint32_t PublicSerialNumberUpper; + +} SmuMetrics_t; + +typedef struct { + SmuMetrics_t SmuMetrics; + uint32_t Spare[29]; + + // Padding - ignore + uint32_t MmHubPadding[8]; // SMU internal use +} SmuMetricsExternal_t; + +typedef struct { + uint8_t WmSetting; + uint8_t Flags; + uint8_t Padding[2]; + +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 + +typedef enum { + WATERMARKS_CLOCK_RANGE = 0, + WATERMARKS_DUMMY_PSTATE, + WATERMARKS_MALL, + WATERMARKS_COUNT, +} WATERMARKS_FLAGS_e; + +typedef struct { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; +} Watermarks_t; + +typedef struct { + Watermarks_t Watermarks; + uint32_t Spare[16]; + + uint32_t MmHubPadding[8]; // SMU internal use +} WatermarksExternal_t; + +typedef struct { + uint16_t avgPsmCount[214]; + uint16_t minPsmCount[214]; + float avgPsmVoltage[214]; + float minPsmVoltage[214]; +} AvfsDebugTable_t; + +typedef struct { + AvfsDebugTable_t AvfsDebugTable; + + uint32_t MmHubPadding[8]; // SMU internal use +} AvfsDebugTableExternal_t; + + +typedef struct { + uint8_t Gfx_ActiveHystLimit; + uint8_t Gfx_IdleHystLimit; + uint8_t Gfx_FPS; + uint8_t Gfx_MinActiveFreqType; + uint8_t Gfx_BoosterFreqType; + uint8_t PaddingGfx; + uint16_t Gfx_MinActiveFreq; // MHz + uint16_t Gfx_BoosterFreq; // MHz + uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms + uint32_t Gfx_PD_Data_limit_a; // Q16 + uint32_t Gfx_PD_Data_limit_b; // Q16 + uint32_t Gfx_PD_Data_limit_c; // Q16 + uint32_t Gfx_PD_Data_error_coeff; // Q16 + uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 + + uint8_t Fclk_ActiveHystLimit; + uint8_t Fclk_IdleHystLimit; + uint8_t Fclk_FPS; + uint8_t Fclk_MinActiveFreqType; + uint8_t Fclk_BoosterFreqType; + uint8_t PaddingFclk; + uint16_t Fclk_MinActiveFreq; // MHz + uint16_t Fclk_BoosterFreq; // MHz + uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms + uint32_t Fclk_PD_Data_limit_a; // Q16 + uint32_t Fclk_PD_Data_limit_b; // Q16 + uint32_t Fclk_PD_Data_limit_c; // Q16 + uint32_t Fclk_PD_Data_error_coeff; // Q16 + uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 + + uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 + uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; + uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; + uint16_t Mem_Fps; + uint8_t padding[2]; + +} DpmActivityMonitorCoeffInt_t; + + +typedef struct { + DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; + uint32_t MmHubPadding[8]; // SMU internal use +} DpmActivityMonitorCoeffIntExternal_t; + + + +// Workload bits +#define WORKLOAD_PPLIB_DEFAULT_BIT 0 +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 +#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 +#define WORKLOAD_PPLIB_VIDEO_BIT 3 +#define WORKLOAD_PPLIB_VR_BIT 4 +#define WORKLOAD_PPLIB_COMPUTE_BIT 5 +#define WORKLOAD_PPLIB_CUSTOM_BIT 6 +#define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 +#define WORKLOAD_PPLIB_COUNT 8 + + +// These defines are used with the following messages: +// SMC_MSG_TransferTableDram2Smu +// SMC_MSG_TransferTableSmu2Dram + +// Table transfer status +#define TABLE_TRANSFER_OK 0x0 +#define TABLE_TRANSFER_FAILED 0xFF +#define TABLE_TRANSFER_PENDING 0xAB + +// Table types +#define TABLE_PPTABLE 0 +#define TABLE_COMBO_PPTABLE 1 +#define TABLE_WATERMARKS 2 +#define TABLE_AVFS_PSM_DEBUG 3 +#define TABLE_PMSTATUSLOG 4 +#define TABLE_SMU_METRICS 5 +#define TABLE_DRIVER_SMU_CONFIG 6 +#define TABLE_ACTIVITY_MONITOR_COEFF 7 +#define TABLE_OVERDRIVE 8 +#define TABLE_I2C_COMMANDS 9 +#define TABLE_DRIVER_INFO 10 +#define TABLE_ECCINFO 11 +#define TABLE_WIFIBAND 12 +#define TABLE_COUNT 13 + +//IH Interupt ID +#define IH_INTERRUPT_ID_TO_DRIVER 0xFE +#define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 +#define IH_INTERRUPT_CONTEXT_ID_AC 0x3 +#define IH_INTERRUPT_CONTEXT_ID_DC 0x4 +#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 +#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 +#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 +#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 +#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 + +#endif diff --git a/extra/amdpci/headers/smu_v13_0_0_ppsmc.h b/extra/amdpci/headers/smu_v13_0_0_ppsmc.h new file mode 100644 index 0000000000..e862d323ca --- /dev/null +++ b/extra/amdpci/headers/smu_v13_0_0_ppsmc.h @@ -0,0 +1,150 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU_V13_0_0_PPSMC_H +#define SMU_V13_0_0_PPSMC_H + +#define PPSMC_VERSION 0x1 +#define DEBUGSMC_VERSION 0x1 + +// SMU Response Codes: +#define PPSMC_Result_OK 0x1 +#define PPSMC_Result_Failed 0xFF +#define PPSMC_Result_UnknownCmd 0xFE +#define PPSMC_Result_CmdRejectedPrereq 0xFD +#define PPSMC_Result_CmdRejectedBusy 0xFC + +// Message Definitions: +// BASIC +#define PPSMC_MSG_TestMessage 0x1 +#define PPSMC_MSG_GetSmuVersion 0x2 +#define PPSMC_MSG_GetDriverIfVersion 0x3 +#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4 +#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5 +#define PPSMC_MSG_EnableAllSmuFeatures 0x6 +#define PPSMC_MSG_DisableAllSmuFeatures 0x7 +#define PPSMC_MSG_EnableSmuFeaturesLow 0x8 +#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9 +#define PPSMC_MSG_DisableSmuFeaturesLow 0xA +#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB +#define PPSMC_MSG_GetRunningSmuFeaturesLow 0xC +#define PPSMC_MSG_GetRunningSmuFeaturesHigh 0xD +#define PPSMC_MSG_SetDriverDramAddrHigh 0xE +#define PPSMC_MSG_SetDriverDramAddrLow 0xF +#define PPSMC_MSG_SetToolsDramAddrHigh 0x10 +#define PPSMC_MSG_SetToolsDramAddrLow 0x11 +#define PPSMC_MSG_TransferTableSmu2Dram 0x12 +#define PPSMC_MSG_TransferTableDram2Smu 0x13 +#define PPSMC_MSG_UseDefaultPPTable 0x14 + +//BACO/BAMACO/BOMACO +#define PPSMC_MSG_EnterBaco 0x15 +#define PPSMC_MSG_ExitBaco 0x16 +#define PPSMC_MSG_ArmD3 0x17 +#define PPSMC_MSG_BacoAudioD3PME 0x18 + +//DPM +#define PPSMC_MSG_SetSoftMinByFreq 0x19 +#define PPSMC_MSG_SetSoftMaxByFreq 0x1A +#define PPSMC_MSG_SetHardMinByFreq 0x1B +#define PPSMC_MSG_SetHardMaxByFreq 0x1C +#define PPSMC_MSG_GetMinDpmFreq 0x1D +#define PPSMC_MSG_GetMaxDpmFreq 0x1E +#define PPSMC_MSG_GetDpmFreqByIndex 0x1F +#define PPSMC_MSG_OverridePcieParameters 0x20 + +//DramLog Set DramAddr +#define PPSMC_MSG_DramLogSetDramAddrHigh 0x21 +#define PPSMC_MSG_DramLogSetDramAddrLow 0x22 +#define PPSMC_MSG_DramLogSetDramSize 0x23 +#define PPSMC_MSG_SetWorkloadMask 0x24 + +#define PPSMC_MSG_GetVoltageByDpm 0x25 +#define PPSMC_MSG_SetVideoFps 0x26 +#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x27 + +//Power Gating +#define PPSMC_MSG_AllowGfxOff 0x28 +#define PPSMC_MSG_DisallowGfxOff 0x29 +#define PPSMC_MSG_PowerUpVcn 0x2A +#define PPSMC_MSG_PowerDownVcn 0x2B +#define PPSMC_MSG_PowerUpJpeg 0x2C +#define PPSMC_MSG_PowerDownJpeg 0x2D + +//Resets +#define PPSMC_MSG_PrepareMp1ForUnload 0x2E +#define PPSMC_MSG_Mode1Reset 0x2F +#define PPSMC_MSG_Mode2Reset 0x4F + +//Set SystemVirtual DramAddrHigh +#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x30 +#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x31 +//ACDC Power Source +#define PPSMC_MSG_SetPptLimit 0x32 +#define PPSMC_MSG_GetPptLimit 0x33 +#define PPSMC_MSG_ReenableAcDcInterrupt 0x34 +#define PPSMC_MSG_NotifyPowerSource 0x35 + +//BTC +#define PPSMC_MSG_RunDcBtc 0x36 + +//Debug +#define PPSMC_MSG_GetDebugData 0x37 + +//Others +#define PPSMC_MSG_SetTemperatureInputSelect 0x38 +#define PPSMC_MSG_SetFwDstatesMask 0x39 +#define PPSMC_MSG_SetThrottlerMask 0x3A + +#define PPSMC_MSG_SetExternalClientDfCstateAllow 0x3B + +#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x3C + +//STB to dram log +#define PPSMC_MSG_DumpSTBtoDram 0x3D +#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3E +#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3F +#define PPSMC_MSG_STBtoDramLogSetDramSize 0x40 + +#define PPSMC_MSG_SetGpoAllow 0x41 +#define PPSMC_MSG_AllowGfxDcs 0x42 +#define PPSMC_MSG_DisallowGfxDcs 0x43 +#define PPSMC_MSG_EnableAudioStutterWA 0x44 +#define PPSMC_MSG_PowerUpUmsch 0x45 +#define PPSMC_MSG_PowerDownUmsch 0x46 +#define PPSMC_MSG_SetDcsArch 0x47 +#define PPSMC_MSG_TriggerVFFLR 0x48 +#define PPSMC_MSG_SetNumBadMemoryPagesRetired 0x49 +#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A +#define PPSMC_MSG_SetPriorityDeltaGain 0x4B +#define PPSMC_MSG_AllowIHHostInterrupt 0x4C +#define PPSMC_MSG_DALNotPresent 0x4E +#define PPSMC_MSG_EnableUCLKShadow 0x51 +#define PPSMC_Message_Count 0x52 + +//Debug Dump Message +#define DEBUGSMC_MSG_TestMessage 0x1 +#define DEBUGSMC_MSG_GetDebugData 0x2 +#define DEBUGSMC_MSG_DebugDumpExit 0x3 +#define DEBUGSMC_Message_Count 0x4 +#endif diff --git a/extra/amdpci/headers/soc15_ih_clientid.h b/extra/amdpci/headers/soc15_ih_clientid.h new file mode 100644 index 0000000000..e1948613cc --- /dev/null +++ b/extra/amdpci/headers/soc15_ih_clientid.h @@ -0,0 +1,113 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SOC15_IH_CLIENTID_H__ +#define __SOC15_IH_CLIENTID_H__ + +/* + * Vega10+ IH clients + * Whenever this structure is updated, which should not happen, make sure + * soc15_ih_clientid_name in the below is also updated accordingly. + */ +enum soc15_ih_clientid { + SOC15_IH_CLIENTID_IH = 0x00, + SOC15_IH_CLIENTID_ACP = 0x01, + SOC15_IH_CLIENTID_ATHUB = 0x02, + SOC15_IH_CLIENTID_BIF = 0x03, + SOC15_IH_CLIENTID_DCE = 0x04, + SOC15_IH_CLIENTID_ISP = 0x05, + SOC15_IH_CLIENTID_PCIE0 = 0x06, + SOC15_IH_CLIENTID_RLC = 0x07, + SOC15_IH_CLIENTID_SDMA0 = 0x08, + SOC15_IH_CLIENTID_SDMA1 = 0x09, + SOC15_IH_CLIENTID_SE0SH = 0x0a, + SOC15_IH_CLIENTID_SE1SH = 0x0b, + SOC15_IH_CLIENTID_SE2SH = 0x0c, + SOC15_IH_CLIENTID_SE3SH = 0x0d, + SOC15_IH_CLIENTID_UVD1 = 0x0e, + SOC15_IH_CLIENTID_THM = 0x0f, + SOC15_IH_CLIENTID_UVD = 0x10, + SOC15_IH_CLIENTID_VCE0 = 0x11, + SOC15_IH_CLIENTID_VMC = 0x12, + SOC15_IH_CLIENTID_XDMA = 0x13, + SOC15_IH_CLIENTID_GRBM_CP = 0x14, + SOC15_IH_CLIENTID_ATS = 0x15, + SOC15_IH_CLIENTID_ROM_SMUIO = 0x16, + SOC15_IH_CLIENTID_DF = 0x17, + SOC15_IH_CLIENTID_VCE1 = 0x18, + SOC15_IH_CLIENTID_PWR = 0x19, + SOC15_IH_CLIENTID_RESERVED = 0x1a, + SOC15_IH_CLIENTID_UTCL2 = 0x1b, + SOC15_IH_CLIENTID_EA = 0x1c, + SOC15_IH_CLIENTID_UTCL2LOG = 0x1d, + SOC15_IH_CLIENTID_MP0 = 0x1e, + SOC15_IH_CLIENTID_MP1 = 0x1f, + + SOC15_IH_CLIENTID_MAX, + + SOC15_IH_CLIENTID_VCN = SOC15_IH_CLIENTID_UVD, + SOC15_IH_CLIENTID_VCN1 = SOC15_IH_CLIENTID_UVD1, + SOC15_IH_CLIENTID_SDMA2 = SOC15_IH_CLIENTID_ACP, + SOC15_IH_CLIENTID_SDMA3 = SOC15_IH_CLIENTID_DCE, + SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = SOC15_IH_CLIENTID_ISP, + SOC15_IH_CLIENTID_SDMA4 = SOC15_IH_CLIENTID_ISP, + SOC15_IH_CLIENTID_SDMA5 = SOC15_IH_CLIENTID_VCE0, + SOC15_IH_CLIENTID_SDMA6 = SOC15_IH_CLIENTID_XDMA, + SOC15_IH_CLIENTID_SDMA7 = SOC15_IH_CLIENTID_VCE1, + SOC15_IH_CLIENTID_VMC1 = SOC15_IH_CLIENTID_PCIE0, +}; + +extern const char *soc15_ih_clientid_name[]; + +/* + * soc21 IH clients + */ +enum soc21_ih_clientid { + SOC21_IH_CLIENTID_IH = 0x00, + SOC21_IH_CLIENTID_ATHUB = 0x02, + SOC21_IH_CLIENTID_BIF = 0x03, + SOC21_IH_CLIENTID_DCN = 0x04, + SOC21_IH_CLIENTID_ISP = 0x05, + SOC21_IH_CLIENTID_MP3 = 0x06, + SOC21_IH_CLIENTID_RLC = 0x07, + SOC21_IH_CLIENTID_GFX = 0x0a, + SOC21_IH_CLIENTID_IMU = 0x0b, + SOC21_IH_CLIENTID_VCN1 = 0x0e, + SOC21_IH_CLIENTID_THM = 0x0f, + SOC21_IH_CLIENTID_VCN = 0x10, + SOC21_IH_CLIENTID_VPE1 = 0x11, + SOC21_IH_CLIENTID_VMC = 0x12, + SOC21_IH_CLIENTID_GRBM_CP = 0x14, + SOC21_IH_CLIENTID_ROM_SMUIO = 0x16, + SOC21_IH_CLIENTID_DF = 0x17, + SOC21_IH_CLIENTID_VPE = 0x18, + SOC21_IH_CLIENTID_PWR = 0x19, + SOC21_IH_CLIENTID_LSDMA = 0x1a, + SOC21_IH_CLIENTID_MP0 = 0x1e, + SOC21_IH_CLIENTID_MP1 = 0x1f, + SOC21_IH_CLIENTID_MAX, +}; + +#endif + + diff --git a/extra/amdpci/headers/soc21_enum.h b/extra/amdpci/headers/soc21_enum.h new file mode 100644 index 0000000000..07d98bff7f --- /dev/null +++ b/extra/amdpci/headers/soc21_enum.h @@ -0,0 +1,22477 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#if !defined (_soc21_ENUM_HEADER) +#define _soc21_ENUM_HEADER + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * Chip Enums + *******************************************************/ + +/* + * DSM_DATA_SEL enum + */ + +typedef enum DSM_DATA_SEL { +DSM_DATA_SEL_DISABLE = 0x00000000, +DSM_DATA_SEL_0 = 0x00000001, +DSM_DATA_SEL_1 = 0x00000002, +DSM_DATA_SEL_BOTH = 0x00000003, +} DSM_DATA_SEL; + +/* + * DSM_ENABLE_ERROR_INJECT enum + */ + +typedef enum DSM_ENABLE_ERROR_INJECT { +DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, +DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, +} DSM_ENABLE_ERROR_INJECT; + +/* + * DSM_SELECT_INJECT_DELAY enum + */ + +typedef enum DSM_SELECT_INJECT_DELAY { +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, +} DSM_SELECT_INJECT_DELAY; + +/* + * DSM_SINGLE_WRITE enum + */ + +typedef enum DSM_SINGLE_WRITE { +DSM_SINGLE_WRITE_DIS = 0x00000000, +DSM_SINGLE_WRITE_EN = 0x00000001, +} DSM_SINGLE_WRITE; + +/* + * ENUM_NUM_SIMD_PER_CU enum + */ + +typedef enum ENUM_NUM_SIMD_PER_CU { +NUM_SIMD_PER_CU = 0x00000002, +} ENUM_NUM_SIMD_PER_CU; + +/* + * GATCL1RequestType enum + */ + +typedef enum GATCL1RequestType { +GATCL1_TYPE_NORMAL = 0x00000000, +GATCL1_TYPE_SHOOTDOWN = 0x00000001, +GATCL1_TYPE_BYPASS = 0x00000002, +} GATCL1RequestType; + +/* + * GL0V_CACHE_POLICIES enum + */ + +typedef enum GL0V_CACHE_POLICIES { +GL0V_CACHE_POLICY_MISS_LRU = 0x00000000, +GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001, +GL0V_CACHE_POLICY_HIT_LRU = 0x00000002, +GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003, +} GL0V_CACHE_POLICIES; + +/* + * GL1_CACHE_POLICIES enum + */ + +typedef enum GL1_CACHE_POLICIES { +GL1_CACHE_POLICY_MISS_LRU = 0x00000000, +GL1_CACHE_POLICY_MISS_EVICT = 0x00000001, +GL1_CACHE_POLICY_HIT_LRU = 0x00000002, +GL1_CACHE_POLICY_HIT_EVICT = 0x00000003, +} GL1_CACHE_POLICIES; + +/* + * GL1_CACHE_STORE_POLICIES enum + */ + +typedef enum GL1_CACHE_STORE_POLICIES { +GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000, +} GL1_CACHE_STORE_POLICIES; + +/* + * GL2_CACHE_POLICIES enum + */ + +typedef enum GL2_CACHE_POLICIES { +GL2_CACHE_POLICY_LRU = 0x00000000, +GL2_CACHE_POLICY_STREAM = 0x00000001, +GL2_CACHE_POLICY_NOA = 0x00000002, +GL2_CACHE_POLICY_BYPASS = 0x00000003, +} GL2_CACHE_POLICIES; + +/* + * Hdp_SurfaceEndian enum + */ + +typedef enum Hdp_SurfaceEndian { +HDP_ENDIAN_NONE = 0x00000000, +HDP_ENDIAN_8IN16 = 0x00000001, +HDP_ENDIAN_8IN32 = 0x00000002, +HDP_ENDIAN_8IN64 = 0x00000003, +} Hdp_SurfaceEndian; + +/* + * MTYPE enum + */ + +typedef enum MTYPE { +MTYPE_C_RW_US = 0x00000000, +MTYPE_RESERVED_1 = 0x00000001, +MTYPE_C_RO_S = 0x00000002, +MTYPE_UC = 0x00000003, +MTYPE_C_RW_S = 0x00000004, +MTYPE_RESERVED_5 = 0x00000005, +MTYPE_C_RO_US = 0x00000006, +MTYPE_RESERVED_7 = 0x00000007, +} MTYPE; + +/* + * PERFMON_COUNTER_MODE enum + */ + +typedef enum PERFMON_COUNTER_MODE { +PERFMON_COUNTER_MODE_ACCUM = 0x00000000, +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, +PERFMON_COUNTER_MODE_MAX = 0x00000002, +PERFMON_COUNTER_MODE_DIRTY = 0x00000003, +PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, +PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, +} PERFMON_COUNTER_MODE; + +/* + * PERFMON_SPM_MODE enum + */ + +typedef enum PERFMON_SPM_MODE { +PERFMON_SPM_MODE_OFF = 0x00000000, +PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, +PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, +PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, +PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, +PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, +PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, +PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, +PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, +} PERFMON_SPM_MODE; + +/* + * RMI_CID enum + */ + +typedef enum RMI_CID { +RMI_CID_CC = 0x00000000, +RMI_CID_FC = 0x00000001, +RMI_CID_CM = 0x00000002, +RMI_CID_DC = 0x00000003, +RMI_CID_Z = 0x00000004, +RMI_CID_S = 0x00000005, +RMI_CID_TILE = 0x00000006, +RMI_CID_ZPCPSD = 0x00000007, +} RMI_CID; + +/* + * ReadPolicy enum + */ + +typedef enum ReadPolicy { +CACHE_LRU_RD = 0x00000000, +CACHE_STREAM_RD = 0x00000001, +CACHE_NOA = 0x00000002, +RESERVED_RDPOLICY = 0x00000003, +} ReadPolicy; + +/* + * SDMA_PERFMON_SEL enum + */ + +typedef enum SDMA_PERFMON_SEL { +SDMA_PERFMON_SEL_CYCLE = 0x00000000, +SDMA_PERFMON_SEL_IDLE = 0x00000001, +SDMA_PERFMON_SEL_REG_IDLE = 0x00000002, +SDMA_PERFMON_SEL_RB_EMPTY = 0x00000003, +SDMA_PERFMON_SEL_RB_FULL = 0x00000004, +SDMA_PERFMON_SEL_RB_WPTR_WRAP = 0x00000005, +SDMA_PERFMON_SEL_RB_RPTR_WRAP = 0x00000006, +SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 0x00000007, +SDMA_PERFMON_SEL_RB_RPTR_WB = 0x00000008, +SDMA_PERFMON_SEL_RB_CMD_IDLE = 0x00000009, +SDMA_PERFMON_SEL_RB_CMD_FULL = 0x0000000a, +SDMA_PERFMON_SEL_IB_CMD_IDLE = 0x0000000b, +SDMA_PERFMON_SEL_IB_CMD_FULL = 0x0000000c, +SDMA_PERFMON_SEL_EX_IDLE = 0x0000000d, +SDMA_PERFMON_SEL_SRBM_REG_SEND = 0x0000000e, +SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, +SDMA_PERFMON_SEL_WR_BA_RTR = 0x00000010, +SDMA_PERFMON_SEL_MC_WR_IDLE = 0x00000011, +SDMA_PERFMON_SEL_MC_WR_COUNT = 0x00000012, +SDMA_PERFMON_SEL_RD_BA_RTR = 0x00000013, +SDMA_PERFMON_SEL_MC_RD_IDLE = 0x00000014, +SDMA_PERFMON_SEL_MC_RD_COUNT = 0x00000015, +SDMA_PERFMON_SEL_MC_RD_RET_STALL = 0x00000016, +SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 0x00000017, +SDMA_PERFMON_SEL_SEM_IDLE = 0x0000001a, +SDMA_PERFMON_SEL_SEM_REQ_STALL = 0x0000001b, +SDMA_PERFMON_SEL_SEM_REQ_COUNT = 0x0000001c, +SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 0x0000001d, +SDMA_PERFMON_SEL_SEM_RESP_FAIL = 0x0000001e, +SDMA_PERFMON_SEL_SEM_RESP_PASS = 0x0000001f, +SDMA_PERFMON_SEL_INT_IDLE = 0x00000020, +SDMA_PERFMON_SEL_INT_REQ_STALL = 0x00000021, +SDMA_PERFMON_SEL_INT_REQ_COUNT = 0x00000022, +SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 0x00000023, +SDMA_PERFMON_SEL_INT_RESP_RETRY = 0x00000024, +SDMA_PERFMON_SEL_NUM_PACKET = 0x00000025, +SDMA_PERFMON_SEL_CE_WREQ_IDLE = 0x00000027, +SDMA_PERFMON_SEL_CE_WR_IDLE = 0x00000028, +SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 0x00000029, +SDMA_PERFMON_SEL_CE_RREQ_IDLE = 0x0000002a, +SDMA_PERFMON_SEL_CE_OUT_IDLE = 0x0000002b, +SDMA_PERFMON_SEL_CE_IN_IDLE = 0x0000002c, +SDMA_PERFMON_SEL_CE_DST_IDLE = 0x0000002d, +SDMA_PERFMON_SEL_CE_AFIFO_FULL = 0x00000030, +SDMA_PERFMON_SEL_CE_INFO_FULL = 0x00000033, +SDMA_PERFMON_SEL_CE_INFO1_FULL = 0x00000034, +SDMA_PERFMON_SEL_CE_RD_STALL = 0x00000035, +SDMA_PERFMON_SEL_CE_WR_STALL = 0x00000036, +SDMA_PERFMON_SEL_GFX_SELECT = 0x00000037, +SDMA_PERFMON_SEL_RLC0_SELECT = 0x00000038, +SDMA_PERFMON_SEL_RLC1_SELECT = 0x00000039, +SDMA_PERFMON_SEL_PAGE_SELECT = 0x0000003a, +SDMA_PERFMON_SEL_CTX_CHANGE = 0x0000003b, +SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 0x0000003c, +SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 0x0000003d, +SDMA_PERFMON_SEL_DOORBELL = 0x0000003e, +SDMA_PERFMON_SEL_F32_L1_WR_VLD = 0x0000003f, +SDMA_PERFMON_SEL_CE_L1_WR_VLD = 0x00000040, +SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 0x00000041, +SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 0x00000042, +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 0x00000043, +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 0x00000044, +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045, +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046, +SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 0x00000047, +SDMA_PERFMON_SEL_UTCL2_RET_ACK = 0x00000048, +SDMA_PERFMON_SEL_UTCL2_FREE = 0x00000049, +SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 0x0000004a, +SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 0x0000004b, +SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 0x0000004c, +SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 0x0000004d, +SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 0x0000004e, +SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 0x0000004f, +SDMA_PERFMON_SEL_GPUVM_INV_LOW = 0x00000050, +SDMA_PERFMON_SEL_L1_WRL2_IDLE = 0x00000051, +SDMA_PERFMON_SEL_L1_RDL2_IDLE = 0x00000052, +SDMA_PERFMON_SEL_L1_WRMC_IDLE = 0x00000053, +SDMA_PERFMON_SEL_L1_RDMC_IDLE = 0x00000054, +SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 0x00000055, +SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 0x00000056, +SDMA_PERFMON_SEL_META_L2_REQ_SEND = 0x00000057, +SDMA_PERFMON_SEL_L2_META_RET_VLD = 0x00000058, +SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 0x00000059, +SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a, +SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b, +SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c, +SDMA_PERFMON_SEL_META_REQ_SEND = 0x0000005d, +SDMA_PERFMON_SEL_META_RTN_VLD = 0x0000005e, +SDMA_PERFMON_SEL_TLBI_SEND = 0x0000005f, +SDMA_PERFMON_SEL_TLBI_RTN = 0x00000060, +SDMA_PERFMON_SEL_GCR_SEND = 0x00000061, +SDMA_PERFMON_SEL_GCR_RTN = 0x00000062, +SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063, +SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064, +} SDMA_PERFMON_SEL; + +/* + * SDMA_PERF_SEL enum + */ + +typedef enum SDMA_PERF_SEL { +SDMA_PERF_SEL_CYCLE = 0x00000000, +SDMA_PERF_SEL_IDLE = 0x00000001, +SDMA_PERF_SEL_REG_IDLE = 0x00000002, +SDMA_PERF_SEL_RB_EMPTY = 0x00000003, +SDMA_PERF_SEL_RB_FULL = 0x00000004, +SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, +SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, +SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, +SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, +SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, +SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, +SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, +SDMA_PERF_SEL_EX_IDLE = 0x0000000d, +SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, +SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, +SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, +SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, +SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, +SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, +SDMA_PERF_SEL_SEM_IDLE = 0x00000018, +SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, +SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, +SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, +SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, +SDMA_PERF_SEL_INT_IDLE = 0x0000001e, +SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, +SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, +SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, +SDMA_PERF_SEL_NUM_PACKET = 0x00000023, +SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, +SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, +SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, +SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, +SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, +SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, +SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, +SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, +SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, +SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, +SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, +SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, +SDMA_PERF_SEL_GFX_SELECT = 0x00000035, +SDMA_PERF_SEL_RLC0_SELECT = 0x00000036, +SDMA_PERF_SEL_RLC1_SELECT = 0x00000037, +SDMA_PERF_SEL_PAGE_SELECT = 0x00000038, +SDMA_PERF_SEL_CTX_CHANGE = 0x00000039, +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, +SDMA_PERF_SEL_DOORBELL = 0x0000003c, +SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, +SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, +SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, +SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, +SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041, +SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042, +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043, +SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044, +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045, +SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046, +SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047, +SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048, +SDMA_PERF_SEL_UTCL2_FREE = 0x00000049, +SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a, +SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b, +SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c, +SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d, +SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e, +SDMA_PERF_SEL_GPUVM_INV_HIGH = 0x0000004f, +SDMA_PERF_SEL_GPUVM_INV_LOW = 0x00000050, +SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051, +SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052, +SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053, +SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054, +SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055, +SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056, +SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057, +SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058, +SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059, +SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a, +SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b, +SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c, +SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d, +SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e, +SDMA_PERF_SEL_TLBI_SEND = 0x0000005f, +SDMA_PERF_SEL_TLBI_RTN = 0x00000060, +SDMA_PERF_SEL_GCR_SEND = 0x00000061, +SDMA_PERF_SEL_GCR_RTN = 0x00000062, +SDMA_PERF_SEL_CGCG_FENCE = 0x00000063, +SDMA_PERF_SEL_CE_CH_WR_REQ = 0x00000064, +SDMA_PERF_SEL_CE_CH_WR_RET = 0x00000065, +SDMA_PERF_SEL_F32_CH_WR_REQ = 0x00000066, +SDMA_PERF_SEL_F32_CH_WR_RET = 0x00000067, +SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 0x00000068, +SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 0x00000069, +SDMA_PERF_SEL_RB_CH_RD_REQ = 0x0000006a, +SDMA_PERF_SEL_RB_CH_RD_RET = 0x0000006b, +SDMA_PERF_SEL_IB_CH_RD_REQ = 0x0000006c, +SDMA_PERF_SEL_IB_CH_RD_RET = 0x0000006d, +SDMA_PERF_SEL_WPTR_CH_RD_REQ = 0x0000006e, +SDMA_PERF_SEL_WPTR_CH_RD_RET = 0x0000006f, +SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x00000070, +SDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x00000071, +SDMA_PERF_SEL_CMD_OP_MATCH = 0x00000072, +SDMA_PERF_SEL_CMD_OP_START = 0x00000073, +SDMA_PERF_SEL_CMD_OP_END = 0x00000074, +SDMA_PERF_SEL_CE_BUSY = 0x00000075, +SDMA_PERF_SEL_CE_BUSY_START = 0x00000076, +SDMA_PERF_SEL_CE_BUSY_END = 0x00000077, +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000078, +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000079, +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x0000007a, +SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 0x0000007b, +SDMA_PERF_SEL_CH_CE_WRRET_VALID = 0x0000007c, +SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 0x0000007d, +SDMA_PERF_SEL_CH_CE_RDRET_VALID = 0x0000007e, +} SDMA_PERF_SEL; + +/* + * TCC_CACHE_POLICIES enum + */ + +typedef enum TCC_CACHE_POLICIES { +TCC_CACHE_POLICY_LRU = 0x00000000, +TCC_CACHE_POLICY_STREAM = 0x00000001, +} TCC_CACHE_POLICIES; + +/* + * TCC_MTYPE enum + */ + +typedef enum TCC_MTYPE { +MTYPE_NC = 0x00000000, +MTYPE_WC = 0x00000001, +MTYPE_CC = 0x00000002, +} TCC_MTYPE; + +/* + * UTCL0FaultType enum + */ + +typedef enum UTCL0FaultType { +UTCL0_XNACK_SUCCESS = 0x00000000, +UTCL0_XNACK_RETRY = 0x00000001, +UTCL0_XNACK_PRT = 0x00000002, +UTCL0_XNACK_NO_RETRY = 0x00000003, +} UTCL0FaultType; + +/* + * UTCL0RequestType enum + */ + +typedef enum UTCL0RequestType { +UTCL0_TYPE_NORMAL = 0x00000000, +UTCL0_TYPE_SHOOTDOWN = 0x00000001, +UTCL0_TYPE_BYPASS = 0x00000002, +} UTCL0RequestType; + +/* + * UTCL1FaultType enum + */ + +typedef enum UTCL1FaultType { +UTCL1_XNACK_SUCCESS = 0x00000000, +UTCL1_XNACK_RETRY = 0x00000001, +UTCL1_XNACK_PRT = 0x00000002, +UTCL1_XNACK_NO_RETRY = 0x00000003, +} UTCL1FaultType; + +/* + * UTCL1RequestType enum + */ + +typedef enum UTCL1RequestType { +UTCL1_TYPE_NORMAL = 0x00000000, +UTCL1_TYPE_SHOOTDOWN = 0x00000001, +UTCL1_TYPE_BYPASS = 0x00000002, +} UTCL1RequestType; + +/* + * VMEMCMD_RETURN_ORDER enum + */ + +typedef enum VMEMCMD_RETURN_ORDER { +VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000, +VMEMCMD_RETURN_IN_ORDER = 0x00000001, +VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002, +} VMEMCMD_RETURN_ORDER; + +/* + * WritePolicy enum + */ + +typedef enum WritePolicy { +CACHE_LRU_WR = 0x00000000, +CACHE_STREAM = 0x00000001, +CACHE_NOA_WR = 0x00000002, +CACHE_BYPASS = 0x00000003, +} WritePolicy; + +/******************************************************* + * CNVC_CFG Enums + *******************************************************/ + +/* + * CNVC_BYPASS enum + */ + +typedef enum CNVC_BYPASS { +CNVC_BYPASS_DISABLE = 0x00000000, +CNVC_BYPASS_EN = 0x00000001, +} CNVC_BYPASS; + +/* + * CNVC_COEF_FORMAT_ENUM enum + */ + +typedef enum CNVC_COEF_FORMAT_ENUM { +CNVC_FIX_S2_13 = 0x00000000, +CNVC_FIX_S3_12 = 0x00000001, +} CNVC_COEF_FORMAT_ENUM; + +/* + * CNVC_ENABLE enum + */ + +typedef enum CNVC_ENABLE { +CNVC_DIS = 0x00000000, +CNVC_EN = 0x00000001, +} CNVC_ENABLE; + +/* + * CNVC_PENDING enum + */ + +typedef enum CNVC_PENDING { +CNVC_NOT_PENDING = 0x00000000, +CNVC_YES_PENDING = 0x00000001, +} CNVC_PENDING; + +/* + * COLOR_KEYER_MODE enum + */ + +typedef enum COLOR_KEYER_MODE { +FORCE_00 = 0x00000000, +FORCE_FF = 0x00000001, +RANGE_00 = 0x00000002, +RANGE_FF = 0x00000003, +} COLOR_KEYER_MODE; + +/* + * DENORM_TRUNCATE enum + */ + +typedef enum DENORM_TRUNCATE { +CNVC_ROUND = 0x00000000, +CNVC_TRUNCATE = 0x00000001, +} DENORM_TRUNCATE; + +/* + * FORMAT_CROSSBAR enum + */ + +typedef enum FORMAT_CROSSBAR { +FORMAT_CROSSBAR_R = 0x00000000, +FORMAT_CROSSBAR_G = 0x00000001, +FORMAT_CROSSBAR_B = 0x00000002, +} FORMAT_CROSSBAR; + +/* + * PIX_EXPAND_MODE enum + */ + +typedef enum PIX_EXPAND_MODE { +PIX_DYNAMIC_EXPANSION = 0x00000000, +PIX_ZERO_EXPANSION = 0x00000001, +} PIX_EXPAND_MODE; + +/* + * PRE_CSC_MODE_ENUM enum + */ + +typedef enum PRE_CSC_MODE_ENUM { +PRE_CSC_BYPASS = 0x00000000, +PRE_CSC_SET_A = 0x00000001, +PRE_CSC_SET_B = 0x00000002, +} PRE_CSC_MODE_ENUM; + +/* + * PRE_DEGAM_MODE enum + */ + +typedef enum PRE_DEGAM_MODE { +PRE_DEGAM_BYPASS = 0x00000000, +PRE_DEGAM_ENABLE = 0x00000001, +} PRE_DEGAM_MODE; + +/* + * PRE_DEGAM_SELECT enum + */ + +typedef enum PRE_DEGAM_SELECT { +PRE_DEGAM_SRGB = 0x00000000, +PRE_DEGAM_GAMMA_22 = 0x00000001, +PRE_DEGAM_GAMMA_24 = 0x00000002, +PRE_DEGAM_GAMMA_26 = 0x00000003, +PRE_DEGAM_BT2020 = 0x00000004, +PRE_DEGAM_BT2100PQ = 0x00000005, +PRE_DEGAM_BT2100HLG = 0x00000006, +} PRE_DEGAM_SELECT; + +/* + * SURFACE_PIXEL_FORMAT enum + */ + +typedef enum SURFACE_PIXEL_FORMAT { +ARGB1555 = 0x00000001, +RGBA5551 = 0x00000002, +RGB565 = 0x00000003, +BGR565 = 0x00000004, +ARGB4444 = 0x00000005, +RGBA4444 = 0x00000006, +ARGB8888 = 0x00000008, +RGBA8888 = 0x00000009, +ARGB2101010 = 0x0000000a, +RGBA1010102 = 0x0000000b, +AYCrCb8888 = 0x0000000c, +YCrCbA8888 = 0x0000000d, +ACrYCb8888 = 0x0000000e, +CrYCbA8888 = 0x0000000f, +ARGB16161616_10MSB = 0x00000010, +RGBA16161616_10MSB = 0x00000011, +ARGB16161616_10LSB = 0x00000012, +RGBA16161616_10LSB = 0x00000013, +ARGB16161616_12MSB = 0x00000014, +RGBA16161616_12MSB = 0x00000015, +ARGB16161616_12LSB = 0x00000016, +RGBA16161616_12LSB = 0x00000017, +ARGB16161616_FLOAT = 0x00000018, +RGBA16161616_FLOAT = 0x00000019, +ARGB16161616_UNORM = 0x0000001a, +RGBA16161616_UNORM = 0x0000001b, +ARGB16161616_SNORM = 0x0000001c, +RGBA16161616_SNORM = 0x0000001d, +AYCrCb16161616_10MSB = 0x00000020, +AYCrCb16161616_10LSB = 0x00000021, +YCrCbA16161616_10MSB = 0x00000022, +YCrCbA16161616_10LSB = 0x00000023, +ACrYCb16161616_10MSB = 0x00000024, +ACrYCb16161616_10LSB = 0x00000025, +CrYCbA16161616_10MSB = 0x00000026, +CrYCbA16161616_10LSB = 0x00000027, +AYCrCb16161616_12MSB = 0x00000028, +AYCrCb16161616_12LSB = 0x00000029, +YCrCbA16161616_12MSB = 0x0000002a, +YCrCbA16161616_12LSB = 0x0000002b, +ACrYCb16161616_12MSB = 0x0000002c, +ACrYCb16161616_12LSB = 0x0000002d, +CrYCbA16161616_12MSB = 0x0000002e, +CrYCbA16161616_12LSB = 0x0000002f, +Y8_CrCb88_420_PLANAR = 0x00000040, +Y8_CbCr88_420_PLANAR = 0x00000041, +Y10_CrCb1010_420_PLANAR = 0x00000042, +Y10_CbCr1010_420_PLANAR = 0x00000043, +Y12_CrCb1212_420_PLANAR = 0x00000044, +Y12_CbCr1212_420_PLANAR = 0x00000045, +YCrYCb8888_422_PACKED = 0x00000048, +YCbYCr8888_422_PACKED = 0x00000049, +CrYCbY8888_422_PACKED = 0x0000004a, +CbYCrY8888_422_PACKED = 0x0000004b, +YCrYCb10101010_422_PACKED = 0x0000004c, +YCbYCr10101010_422_PACKED = 0x0000004d, +CrYCbY10101010_422_PACKED = 0x0000004e, +CbYCrY10101010_422_PACKED = 0x0000004f, +YCrYCb12121212_422_PACKED = 0x00000050, +YCbYCr12121212_422_PACKED = 0x00000051, +CrYCbY12121212_422_PACKED = 0x00000052, +CbYCrY12121212_422_PACKED = 0x00000053, +RGB111110_FIX = 0x00000070, +BGR101111_FIX = 0x00000071, +ACrYCb2101010 = 0x00000072, +CrYCbA1010102 = 0x00000073, +RGBE = 0x00000074, +RGB111110_FLOAT = 0x00000076, +BGR101111_FLOAT = 0x00000077, +MONO_8 = 0x00000078, +MONO_10MSB = 0x00000079, +MONO_10LSB = 0x0000007a, +MONO_12MSB = 0x0000007b, +MONO_12LSB = 0x0000007c, +MONO_16 = 0x0000007d, +} SURFACE_PIXEL_FORMAT; + +/* + * XNORM enum + */ + +typedef enum XNORM { +XNORM_A = 0x00000000, +XNORM_B = 0x00000001, +} XNORM; + +/******************************************************* + * CNVC_CUR Enums + *******************************************************/ + +/* + * CUR_ENABLE enum + */ + +typedef enum CUR_ENABLE { +CUR_DIS = 0x00000000, +CUR_EN = 0x00000001, +} CUR_ENABLE; + +/* + * CUR_EXPAND_MODE enum + */ + +typedef enum CUR_EXPAND_MODE { +CUR_DYNAMIC_EXPANSION = 0x00000000, +CUR_ZERO_EXPANSION = 0x00000001, +} CUR_EXPAND_MODE; + +/* + * CUR_INV_CLAMP enum + */ + +typedef enum CUR_INV_CLAMP { +CUR_CLAMP_DIS = 0x00000000, +CUR_CLAMP_EN = 0x00000001, +} CUR_INV_CLAMP; + +/* + * CUR_MODE enum + */ + +typedef enum CUR_MODE { +MONO_2BIT = 0x00000000, +COLOR_24BIT_1BIT_AND = 0x00000001, +COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, +COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, +COLOR_64BIT_FP_PREMULT = 0x00000004, +COLOR_64BIT_FP_UNPREMULT = 0x00000005, +} CUR_MODE; + +/* + * CUR_PENDING enum + */ + +typedef enum CUR_PENDING { +CUR_NOT_PENDING = 0x00000000, +CUR_YES_PENDING = 0x00000001, +} CUR_PENDING; + +/* + * CUR_ROM_EN enum + */ + +typedef enum CUR_ROM_EN { +CUR_FP_NO_ROM = 0x00000000, +CUR_FP_USE_ROM = 0x00000001, +} CUR_ROM_EN; + +/******************************************************* + * DSCL Enums + *******************************************************/ + +/* + * COEF_RAM_SELECT_RD enum + */ + +typedef enum COEF_RAM_SELECT_RD { +COEF_RAM_SELECT_BACK = 0x00000000, +COEF_RAM_SELECT_CURRENT = 0x00000001, +} COEF_RAM_SELECT_RD; + +/* + * DSCL_MODE_SEL enum + */ + +typedef enum DSCL_MODE_SEL { +DSCL_MODE_SCALING_444_BYPASS = 0x00000000, +DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001, +DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002, +DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003, +DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004, +DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005, +DSCL_MODE_DSCL_BYPASS = 0x00000006, +} DSCL_MODE_SEL; + +/* + * LB_ALPHA_EN enum + */ + +typedef enum LB_ALPHA_EN { +LB_ALPHA_DISABLE = 0x00000000, +LB_ALPHA_ENABLE = 0x00000001, +} LB_ALPHA_EN; + +/* + * LB_INTERLEAVE_EN enum + */ + +typedef enum LB_INTERLEAVE_EN { +LB_INTERLEAVE_DISABLE = 0x00000000, +LB_INTERLEAVE_ENABLE = 0x00000001, +} LB_INTERLEAVE_EN; + +/* + * LB_MEMORY_CONFIG enum + */ + +typedef enum LB_MEMORY_CONFIG { +LB_MEMORY_CONFIG_0 = 0x00000000, +LB_MEMORY_CONFIG_1 = 0x00000001, +LB_MEMORY_CONFIG_2 = 0x00000002, +LB_MEMORY_CONFIG_3 = 0x00000003, +} LB_MEMORY_CONFIG; + +/* + * OBUF_BYPASS_SEL enum + */ + +typedef enum OBUF_BYPASS_SEL { +OBUF_BYPASS_DIS = 0x00000000, +OBUF_BYPASS_EN = 0x00000001, +} OBUF_BYPASS_SEL; + +/* + * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum + */ + +typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL { +OBUF_FULL_RECOUT = 0x00000000, +OBUF_HALF_RECOUT = 0x00000001, +} OBUF_IS_HALF_RECOUT_WIDTH_SEL; + +/* + * OBUF_USE_FULL_BUFFER_SEL enum + */ + +typedef enum OBUF_USE_FULL_BUFFER_SEL { +OBUF_RECOUT = 0x00000000, +OBUF_FULL = 0x00000001, +} OBUF_USE_FULL_BUFFER_SEL; + +/* + * SCL_2TAP_HARDCODE enum + */ + +typedef enum SCL_2TAP_HARDCODE { +SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000, +SCL_COEF_2TAP_HARDCODE_ON = 0x00000001, +} SCL_2TAP_HARDCODE; + +/* + * SCL_ALPHA_COEF enum + */ + +typedef enum SCL_ALPHA_COEF { +SCL_ALPHA_COEF_FIRST = 0x00000000, +SCL_ALPHA_COEF_SECOND = 0x00000001, +} SCL_ALPHA_COEF; + +/* + * SCL_AUTOCAL_MODE enum + */ + +typedef enum SCL_AUTOCAL_MODE { +AUTOCAL_MODE_OFF = 0x00000000, +AUTOCAL_MODE_AUTOSCALE = 0x00000001, +AUTOCAL_MODE_AUTOCENTER = 0x00000002, +AUTOCAL_MODE_AUTOREPLICATE = 0x00000003, +} SCL_AUTOCAL_MODE; + +/* + * SCL_BOUNDARY enum + */ + +typedef enum SCL_BOUNDARY { +SCL_BOUNDARY_EDGE = 0x00000000, +SCL_BOUNDARY_BLACK = 0x00000001, +} SCL_BOUNDARY; + +/* + * SCL_CHROMA_COEF enum + */ + +typedef enum SCL_CHROMA_COEF { +SCL_CHROMA_COEF_FIRST = 0x00000000, +SCL_CHROMA_COEF_SECOND = 0x00000001, +} SCL_CHROMA_COEF; + +/* + * SCL_COEF_FILTER_TYPE_SEL enum + */ + +typedef enum SCL_COEF_FILTER_TYPE_SEL { +SCL_COEF_LUMA_VERT_FILTER = 0x00000000, +SCL_COEF_LUMA_HORZ_FILTER = 0x00000001, +SCL_COEF_CHROMA_VERT_FILTER = 0x00000002, +SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003, +} SCL_COEF_FILTER_TYPE_SEL; + +/* + * SCL_COEF_RAM_SEL enum + */ + +typedef enum SCL_COEF_RAM_SEL { +SCL_COEF_RAM_SEL_0 = 0x00000000, +SCL_COEF_RAM_SEL_1 = 0x00000001, +} SCL_COEF_RAM_SEL; + +/* + * SCL_SHARP_EN enum + */ + +typedef enum SCL_SHARP_EN { +SCL_SHARP_DISABLE = 0x00000000, +SCL_SHARP_ENABLE = 0x00000001, +} SCL_SHARP_EN; + +/******************************************************* + * CM Enums + *******************************************************/ + +/* + * CMC_3DLUT_30BIT_ENUM enum + */ + +typedef enum CMC_3DLUT_30BIT_ENUM { +CMC_3DLUT_36BIT = 0x00000000, +CMC_3DLUT_30BIT = 0x00000001, +} CMC_3DLUT_30BIT_ENUM; + +/* + * CMC_3DLUT_RAM_SEL enum + */ + +typedef enum CMC_3DLUT_RAM_SEL { +CMC_RAM0_ACCESS = 0x00000000, +CMC_RAM1_ACCESS = 0x00000001, +CMC_RAM2_ACCESS = 0x00000002, +CMC_RAM3_ACCESS = 0x00000003, +} CMC_3DLUT_RAM_SEL; + +/* + * CMC_3DLUT_SIZE_ENUM enum + */ + +typedef enum CMC_3DLUT_SIZE_ENUM { +CMC_3DLUT_17CUBE = 0x00000000, +CMC_3DLUT_9CUBE = 0x00000001, +} CMC_3DLUT_SIZE_ENUM; + +/* + * CMC_LUT_2_CONFIG_ENUM enum + */ + +typedef enum CMC_LUT_2_CONFIG_ENUM { +CMC_LUT_2CFG_NO_MEMORY = 0x00000000, +CMC_LUT_2CFG_MEMORY_A = 0x00000001, +CMC_LUT_2CFG_MEMORY_B = 0x00000002, +} CMC_LUT_2_CONFIG_ENUM; + +/* + * CMC_LUT_2_MODE_ENUM enum + */ + +typedef enum CMC_LUT_2_MODE_ENUM { +CMC_LUT_2_MODE_BYPASS = 0x00000000, +CMC_LUT_2_MODE_RAMA_LUT = 0x00000001, +CMC_LUT_2_MODE_RAMB_LUT = 0x00000002, +} CMC_LUT_2_MODE_ENUM; + +/* + * CMC_LUT_NUM_SEG enum + */ + +typedef enum CMC_LUT_NUM_SEG { +CMC_SEGMENTS_1 = 0x00000000, +CMC_SEGMENTS_2 = 0x00000001, +CMC_SEGMENTS_4 = 0x00000002, +CMC_SEGMENTS_8 = 0x00000003, +CMC_SEGMENTS_16 = 0x00000004, +CMC_SEGMENTS_32 = 0x00000005, +CMC_SEGMENTS_64 = 0x00000006, +CMC_SEGMENTS_128 = 0x00000007, +} CMC_LUT_NUM_SEG; + +/* + * CMC_LUT_RAM_SEL enum + */ + +typedef enum CMC_LUT_RAM_SEL { +CMC_RAMA_ACCESS = 0x00000000, +CMC_RAMB_ACCESS = 0x00000001, +} CMC_LUT_RAM_SEL; + +/* + * CM_BYPASS enum + */ + +typedef enum CM_BYPASS { +NON_BYPASS = 0x00000000, +BYPASS_EN = 0x00000001, +} CM_BYPASS; + +/* + * CM_COEF_FORMAT_ENUM enum + */ + +typedef enum CM_COEF_FORMAT_ENUM { +FIX_S2_13 = 0x00000000, +FIX_S3_12 = 0x00000001, +} CM_COEF_FORMAT_ENUM; + +/* + * CM_DATA_SIGNED enum + */ + +typedef enum CM_DATA_SIGNED { +UNSIGNED = 0x00000000, +SIGNED = 0x00000001, +} CM_DATA_SIGNED; + +/* + * CM_EN enum + */ + +typedef enum CM_EN { +CM_DISABLE = 0x00000000, +CM_ENABLE = 0x00000001, +} CM_EN; + +/* + * CM_GAMMA_LUT_MODE_ENUM enum + */ + +typedef enum CM_GAMMA_LUT_MODE_ENUM { +BYPASS = 0x00000000, +RESERVED_1 = 0x00000001, +RAM_LUT = 0x00000002, +RESERVED_3 = 0x00000003, +} CM_GAMMA_LUT_MODE_ENUM; + +/* + * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum + */ + +typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM { +ENABLE_PWL = 0x00000000, +DISABLE_PWL = 0x00000001, +} CM_GAMMA_LUT_PWL_DISABLE_ENUM; + +/* + * CM_GAMMA_LUT_SEL_ENUM enum + */ + +typedef enum CM_GAMMA_LUT_SEL_ENUM { +RAMA = 0x00000000, +RAMB = 0x00000001, +} CM_GAMMA_LUT_SEL_ENUM; + +/* + * CM_GAMUT_REMAP_MODE_ENUM enum + */ + +typedef enum CM_GAMUT_REMAP_MODE_ENUM { +BYPASS_GAMUT = 0x00000000, +GAMUT_COEF = 0x00000001, +GAMUT_COEF_B = 0x00000002, +} CM_GAMUT_REMAP_MODE_ENUM; + +/* + * CM_LUT_2_CONFIG_ENUM enum + */ + +typedef enum CM_LUT_2_CONFIG_ENUM { +LUT_2CFG_NO_MEMORY = 0x00000000, +LUT_2CFG_MEMORY_A = 0x00000001, +LUT_2CFG_MEMORY_B = 0x00000002, +} CM_LUT_2_CONFIG_ENUM; + +/* + * CM_LUT_2_MODE_ENUM enum + */ + +typedef enum CM_LUT_2_MODE_ENUM { +LUT_2_MODE_BYPASS = 0x00000000, +LUT_2_MODE_RAMA_LUT = 0x00000001, +LUT_2_MODE_RAMB_LUT = 0x00000002, +} CM_LUT_2_MODE_ENUM; + +/* + * CM_LUT_4_CONFIG_ENUM enum + */ + +typedef enum CM_LUT_4_CONFIG_ENUM { +LUT_4CFG_NO_MEMORY = 0x00000000, +LUT_4CFG_ROM_A = 0x00000001, +LUT_4CFG_ROM_B = 0x00000002, +LUT_4CFG_MEMORY_A = 0x00000003, +LUT_4CFG_MEMORY_B = 0x00000004, +} CM_LUT_4_CONFIG_ENUM; + +/* + * CM_LUT_4_MODE_ENUM enum + */ + +typedef enum CM_LUT_4_MODE_ENUM { +LUT_4_MODE_BYPASS = 0x00000000, +LUT_4_MODE_ROMA_LUT = 0x00000001, +LUT_4_MODE_ROMB_LUT = 0x00000002, +LUT_4_MODE_RAMA_LUT = 0x00000003, +LUT_4_MODE_RAMB_LUT = 0x00000004, +} CM_LUT_4_MODE_ENUM; + +/* + * CM_LUT_CONFIG_MODE enum + */ + +typedef enum CM_LUT_CONFIG_MODE { +DIFFERENT_RGB = 0x00000000, +ALL_USE_R = 0x00000001, +} CM_LUT_CONFIG_MODE; + +/* + * CM_LUT_NUM_SEG enum + */ + +typedef enum CM_LUT_NUM_SEG { +SEGMENTS_1 = 0x00000000, +SEGMENTS_2 = 0x00000001, +SEGMENTS_4 = 0x00000002, +SEGMENTS_8 = 0x00000003, +SEGMENTS_16 = 0x00000004, +SEGMENTS_32 = 0x00000005, +SEGMENTS_64 = 0x00000006, +SEGMENTS_128 = 0x00000007, +} CM_LUT_NUM_SEG; + +/* + * CM_LUT_RAM_SEL enum + */ + +typedef enum CM_LUT_RAM_SEL { +RAMA_ACCESS = 0x00000000, +RAMB_ACCESS = 0x00000001, +} CM_LUT_RAM_SEL; + +/* + * CM_LUT_READ_COLOR_SEL enum + */ + +typedef enum CM_LUT_READ_COLOR_SEL { +BLUE_LUT = 0x00000000, +GREEN_LUT = 0x00000001, +RED_LUT = 0x00000002, +} CM_LUT_READ_COLOR_SEL; + +/* + * CM_LUT_READ_DBG enum + */ + +typedef enum CM_LUT_READ_DBG { +DISABLE_DEBUG = 0x00000000, +ENABLE_DEBUG = 0x00000001, +} CM_LUT_READ_DBG; + +/* + * CM_PENDING enum + */ + +typedef enum CM_PENDING { +CM_NOT_PENDING = 0x00000000, +CM_YES_PENDING = 0x00000001, +} CM_PENDING; + +/* + * CM_POST_CSC_MODE_ENUM enum + */ + +typedef enum CM_POST_CSC_MODE_ENUM { +BYPASS_POST_CSC = 0x00000000, +COEF_POST_CSC = 0x00000001, +COEF_POST_CSC_B = 0x00000002, +} CM_POST_CSC_MODE_ENUM; + +/* + * CM_WRITE_BASE_ONLY enum + */ + +typedef enum CM_WRITE_BASE_ONLY { +WRITE_BOTH = 0x00000000, +WRITE_BASE_ONLY = 0x00000001, +} CM_WRITE_BASE_ONLY; + +/******************************************************* + * DPP_TOP Enums + *******************************************************/ + +/* + * CRC_CUR_SEL enum + */ + +typedef enum CRC_CUR_SEL { +CRC_CUR_0 = 0x00000000, +CRC_CUR_1 = 0x00000001, +} CRC_CUR_SEL; + +/* + * CRC_INTERLACE_SEL enum + */ + +typedef enum CRC_INTERLACE_SEL { +CRC_INTERLACE_0 = 0x00000000, +CRC_INTERLACE_1 = 0x00000001, +CRC_INTERLACE_2 = 0x00000002, +CRC_INTERLACE_3 = 0x00000003, +} CRC_INTERLACE_SEL; + +/* + * CRC_IN_CUR_SEL enum + */ + +typedef enum CRC_IN_CUR_SEL { +CRC_IN_CUR_0 = 0x00000000, +CRC_IN_CUR_1 = 0x00000001, +CRC_IN_CUR_2 = 0x00000002, +CRC_IN_CUR_3 = 0x00000003, +} CRC_IN_CUR_SEL; + +/* + * CRC_IN_PIX_SEL enum + */ + +typedef enum CRC_IN_PIX_SEL { +CRC_IN_PIX_0 = 0x00000000, +CRC_IN_PIX_1 = 0x00000001, +CRC_IN_PIX_2 = 0x00000002, +CRC_IN_PIX_3 = 0x00000003, +CRC_IN_PIX_4 = 0x00000004, +CRC_IN_PIX_5 = 0x00000005, +CRC_IN_PIX_6 = 0x00000006, +CRC_IN_PIX_7 = 0x00000007, +} CRC_IN_PIX_SEL; + +/* + * CRC_SRC_SEL enum + */ + +typedef enum CRC_SRC_SEL { +CRC_SRC_0 = 0x00000000, +CRC_SRC_1 = 0x00000001, +CRC_SRC_2 = 0x00000002, +CRC_SRC_3 = 0x00000003, +} CRC_SRC_SEL; + +/* + * CRC_STEREO_SEL enum + */ + +typedef enum CRC_STEREO_SEL { +CRC_STEREO_0 = 0x00000000, +CRC_STEREO_1 = 0x00000001, +CRC_STEREO_2 = 0x00000002, +CRC_STEREO_3 = 0x00000003, +} CRC_STEREO_SEL; + +/* + * TEST_CLK_SEL enum + */ + +typedef enum TEST_CLK_SEL { +TEST_CLK_SEL_0 = 0x00000000, +TEST_CLK_SEL_1 = 0x00000001, +TEST_CLK_SEL_2 = 0x00000002, +TEST_CLK_SEL_3 = 0x00000003, +TEST_CLK_SEL_4 = 0x00000004, +TEST_CLK_SEL_5 = 0x00000005, +TEST_CLK_SEL_6 = 0x00000006, +TEST_CLK_SEL_7 = 0x00000007, +} TEST_CLK_SEL; + +/******************************************************* + * DC_PERFMON Enums + *******************************************************/ + +/* + * PERFCOUNTER_ACTIVE enum + */ + +typedef enum PERFCOUNTER_ACTIVE { +PERFCOUNTER_IS_IDLE = 0x00000000, +PERFCOUNTER_IS_ACTIVE = 0x00000001, +} PERFCOUNTER_ACTIVE; + +/* + * PERFCOUNTER_CNT0_STATE enum + */ + +typedef enum PERFCOUNTER_CNT0_STATE { +PERFCOUNTER_CNT0_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT0_STATE_START = 0x00000001, +PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT0_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT0_STATE; + +/* + * PERFCOUNTER_CNT1_STATE enum + */ + +typedef enum PERFCOUNTER_CNT1_STATE { +PERFCOUNTER_CNT1_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT1_STATE_START = 0x00000001, +PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT1_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT1_STATE; + +/* + * PERFCOUNTER_CNT2_STATE enum + */ + +typedef enum PERFCOUNTER_CNT2_STATE { +PERFCOUNTER_CNT2_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT2_STATE_START = 0x00000001, +PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT2_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT2_STATE; + +/* + * PERFCOUNTER_CNT3_STATE enum + */ + +typedef enum PERFCOUNTER_CNT3_STATE { +PERFCOUNTER_CNT3_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT3_STATE_START = 0x00000001, +PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT3_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT3_STATE; + +/* + * PERFCOUNTER_CNT4_STATE enum + */ + +typedef enum PERFCOUNTER_CNT4_STATE { +PERFCOUNTER_CNT4_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT4_STATE_START = 0x00000001, +PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT4_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT4_STATE; + +/* + * PERFCOUNTER_CNT5_STATE enum + */ + +typedef enum PERFCOUNTER_CNT5_STATE { +PERFCOUNTER_CNT5_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT5_STATE_START = 0x00000001, +PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT5_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT5_STATE; + +/* + * PERFCOUNTER_CNT6_STATE enum + */ + +typedef enum PERFCOUNTER_CNT6_STATE { +PERFCOUNTER_CNT6_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT6_STATE_START = 0x00000001, +PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT6_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT6_STATE; + +/* + * PERFCOUNTER_CNT7_STATE enum + */ + +typedef enum PERFCOUNTER_CNT7_STATE { +PERFCOUNTER_CNT7_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT7_STATE_START = 0x00000001, +PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT7_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT7_STATE; + +/* + * PERFCOUNTER_CNTL_SEL enum + */ + +typedef enum PERFCOUNTER_CNTL_SEL { +PERFCOUNTER_CNTL_SEL_0 = 0x00000000, +PERFCOUNTER_CNTL_SEL_1 = 0x00000001, +PERFCOUNTER_CNTL_SEL_2 = 0x00000002, +PERFCOUNTER_CNTL_SEL_3 = 0x00000003, +PERFCOUNTER_CNTL_SEL_4 = 0x00000004, +PERFCOUNTER_CNTL_SEL_5 = 0x00000005, +PERFCOUNTER_CNTL_SEL_6 = 0x00000006, +PERFCOUNTER_CNTL_SEL_7 = 0x00000007, +} PERFCOUNTER_CNTL_SEL; + +/* + * PERFCOUNTER_CNTOFF_START_DIS enum + */ + +typedef enum PERFCOUNTER_CNTOFF_START_DIS { +PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000, +PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001, +} PERFCOUNTER_CNTOFF_START_DIS; + +/* + * PERFCOUNTER_COUNTED_VALUE_TYPE enum + */ + +typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000, +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001, +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002, +} PERFCOUNTER_COUNTED_VALUE_TYPE; + +/* + * PERFCOUNTER_CVALUE_SEL enum + */ + +typedef enum PERFCOUNTER_CVALUE_SEL { +PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000, +PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001, +PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002, +PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003, +PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004, +PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005, +PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006, +PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007, +} PERFCOUNTER_CVALUE_SEL; + +/* + * PERFCOUNTER_HW_CNTL_SEL enum + */ + +typedef enum PERFCOUNTER_HW_CNTL_SEL { +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000, +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001, +} PERFCOUNTER_HW_CNTL_SEL; + +/* + * PERFCOUNTER_HW_STOP1_SEL enum + */ + +typedef enum PERFCOUNTER_HW_STOP1_SEL { +PERFCOUNTER_HW_STOP1_0 = 0x00000000, +PERFCOUNTER_HW_STOP1_1 = 0x00000001, +} PERFCOUNTER_HW_STOP1_SEL; + +/* + * PERFCOUNTER_HW_STOP2_SEL enum + */ + +typedef enum PERFCOUNTER_HW_STOP2_SEL { +PERFCOUNTER_HW_STOP2_0 = 0x00000000, +PERFCOUNTER_HW_STOP2_1 = 0x00000001, +} PERFCOUNTER_HW_STOP2_SEL; + +/* + * PERFCOUNTER_INC_MODE enum + */ + +typedef enum PERFCOUNTER_INC_MODE { +PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000, +PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001, +PERFCOUNTER_INC_MODE_LSB = 0x00000002, +PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003, +PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004, +} PERFCOUNTER_INC_MODE; + +/* + * PERFCOUNTER_INT_EN enum + */ + +typedef enum PERFCOUNTER_INT_EN { +PERFCOUNTER_INT_DISABLE = 0x00000000, +PERFCOUNTER_INT_ENABLE = 0x00000001, +} PERFCOUNTER_INT_EN; + +/* + * PERFCOUNTER_INT_TYPE enum + */ + +typedef enum PERFCOUNTER_INT_TYPE { +PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000, +PERFCOUNTER_INT_TYPE_PULSE = 0x00000001, +} PERFCOUNTER_INT_TYPE; + +/* + * PERFCOUNTER_OFF_MASK enum + */ + +typedef enum PERFCOUNTER_OFF_MASK { +PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000, +PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001, +} PERFCOUNTER_OFF_MASK; + +/* + * PERFCOUNTER_RESTART_EN enum + */ + +typedef enum PERFCOUNTER_RESTART_EN { +PERFCOUNTER_RESTART_DISABLE = 0x00000000, +PERFCOUNTER_RESTART_ENABLE = 0x00000001, +} PERFCOUNTER_RESTART_EN; + +/* + * PERFCOUNTER_RUNEN_MODE enum + */ + +typedef enum PERFCOUNTER_RUNEN_MODE { +PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000, +PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001, +} PERFCOUNTER_RUNEN_MODE; + +/* + * PERFCOUNTER_STATE_SEL0 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL0 { +PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL0; + +/* + * PERFCOUNTER_STATE_SEL1 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL1 { +PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL1; + +/* + * PERFCOUNTER_STATE_SEL2 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL2 { +PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL2; + +/* + * PERFCOUNTER_STATE_SEL3 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL3 { +PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL3; + +/* + * PERFCOUNTER_STATE_SEL4 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL4 { +PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL4; + +/* + * PERFCOUNTER_STATE_SEL5 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL5 { +PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL5; + +/* + * PERFCOUNTER_STATE_SEL6 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL6 { +PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL6; + +/* + * PERFCOUNTER_STATE_SEL7 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL7 { +PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL7; + +/* + * PERFMON_CNTOFF_AND_OR enum + */ + +typedef enum PERFMON_CNTOFF_AND_OR { +PERFMON_CNTOFF_OR = 0x00000000, +PERFMON_CNTOFF_AND = 0x00000001, +} PERFMON_CNTOFF_AND_OR; + +/* + * PERFMON_CNTOFF_INT_EN enum + */ + +typedef enum PERFMON_CNTOFF_INT_EN { +PERFMON_CNTOFF_INT_DISABLE = 0x00000000, +PERFMON_CNTOFF_INT_ENABLE = 0x00000001, +} PERFMON_CNTOFF_INT_EN; + +/* + * PERFMON_CNTOFF_INT_TYPE enum + */ + +typedef enum PERFMON_CNTOFF_INT_TYPE { +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000, +PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001, +} PERFMON_CNTOFF_INT_TYPE; + +/* + * PERFMON_STATE enum + */ + +typedef enum PERFMON_STATE { +PERFMON_STATE_RESET = 0x00000000, +PERFMON_STATE_START = 0x00000001, +PERFMON_STATE_FREEZE = 0x00000002, +PERFMON_STATE_HW = 0x00000003, +} PERFMON_STATE; + +/******************************************************* + * HUBP Enums + *******************************************************/ + +/* + * BIGK_FRAGMENT_SIZE enum + */ + +typedef enum BIGK_FRAGMENT_SIZE { +VM_PG_SIZE_4KB = 0x00000000, +VM_PG_SIZE_8KB = 0x00000001, +VM_PG_SIZE_16KB = 0x00000002, +VM_PG_SIZE_32KB = 0x00000003, +VM_PG_SIZE_64KB = 0x00000004, +VM_PG_SIZE_128KB = 0x00000005, +VM_PG_SIZE_256KB = 0x00000006, +VM_PG_SIZE_512KB = 0x00000007, +VM_PG_SIZE_1024KB = 0x00000008, +VM_PG_SIZE_2048KB = 0x00000009, +} BIGK_FRAGMENT_SIZE; + +/* + * CHUNK_SIZE enum + */ + +typedef enum CHUNK_SIZE { +CHUNK_SIZE_1KB = 0x00000000, +CHUNK_SIZE_2KB = 0x00000001, +CHUNK_SIZE_4KB = 0x00000002, +CHUNK_SIZE_8KB = 0x00000003, +CHUNK_SIZE_16KB = 0x00000004, +CHUNK_SIZE_32KB = 0x00000005, +CHUNK_SIZE_64KB = 0x00000006, +} CHUNK_SIZE; + +/* + * COMPAT_LEVEL enum + */ + +typedef enum COMPAT_LEVEL { +ADDR_GEN_ZERO = 0x00000000, +ADDR_GEN_ONE = 0x00000001, +ADDR_GEN_TWO = 0x00000002, +ADDR_RESERVED = 0x00000003, +} COMPAT_LEVEL; + +/* + * DPTE_GROUP_SIZE enum + */ + +typedef enum DPTE_GROUP_SIZE { +DPTE_GROUP_SIZE_64B = 0x00000000, +DPTE_GROUP_SIZE_128B = 0x00000001, +DPTE_GROUP_SIZE_256B = 0x00000002, +DPTE_GROUP_SIZE_512B = 0x00000003, +DPTE_GROUP_SIZE_1024B = 0x00000004, +DPTE_GROUP_SIZE_2048B = 0x00000005, +} DPTE_GROUP_SIZE; + +/* + * FORCE_ONE_ROW_FOR_FRAME enum + */ + +typedef enum FORCE_ONE_ROW_FOR_FRAME { +FORCE_ONE_ROW_FOR_FRAME_0 = 0x00000000, +FORCE_ONE_ROW_FOR_FRAME_1 = 0x00000001, +} FORCE_ONE_ROW_FOR_FRAME; + +/* + * HUBP_BLANK_EN enum + */ + +typedef enum HUBP_BLANK_EN { +HUBP_BLANK_SW_DEASSERT = 0x00000000, +HUBP_BLANK_SW_ASSERT = 0x00000001, +} HUBP_BLANK_EN; + +/* + * HUBP_IN_BLANK enum + */ + +typedef enum HUBP_IN_BLANK { +HUBP_IN_ACTIVE = 0x00000000, +HUBP_IN_VBLANK = 0x00000001, +} HUBP_IN_BLANK; + +/* + * HUBP_MEASURE_WIN_MODE_DCFCLK enum + */ + +typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK { +HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000, +HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001, +HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002, +HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003, +} HUBP_MEASURE_WIN_MODE_DCFCLK; + +/* + * HUBP_NO_OUTSTANDING_REQ enum + */ + +typedef enum HUBP_NO_OUTSTANDING_REQ { +OUTSTANDING_REQ = 0x00000000, +NO_OUTSTANDING_REQ = 0x00000001, +} HUBP_NO_OUTSTANDING_REQ; + +/* + * HUBP_SOFT_RESET enum + */ + +typedef enum HUBP_SOFT_RESET { +HUBP_SOFT_RESET_ON = 0x00000000, +HUBP_SOFT_RESET_OFF = 0x00000001, +} HUBP_SOFT_RESET; + +/* + * HUBP_TTU_DISABLE enum + */ + +typedef enum HUBP_TTU_DISABLE { +HUBP_TTU_ENABLED = 0x00000000, +HUBP_TTU_DISABLED = 0x00000001, +} HUBP_TTU_DISABLE; + +/* + * HUBP_VREADY_AT_OR_AFTER_VSYNC enum + */ + +typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC { +VREADY_BEFORE_VSYNC = 0x00000000, +VREADY_AT_OR_AFTER_VSYNC = 0x00000001, +} HUBP_VREADY_AT_OR_AFTER_VSYNC; + +/* + * HUBP_VTG_SEL enum + */ + +typedef enum HUBP_VTG_SEL { +VTG_SEL_0 = 0x00000000, +VTG_SEL_1 = 0x00000001, +VTG_SEL_2 = 0x00000002, +VTG_SEL_3 = 0x00000003, +VTG_SEL_4 = 0x00000004, +VTG_SEL_5 = 0x00000005, +} HUBP_VTG_SEL; + +/* + * H_MIRROR_EN enum + */ + +typedef enum H_MIRROR_EN { +HW_MIRRORING_DISABLE = 0x00000000, +HW_MIRRORING_ENABLE = 0x00000001, +} H_MIRROR_EN; + +/* + * LEGACY_PIPE_INTERLEAVE enum + */ + +typedef enum LEGACY_PIPE_INTERLEAVE { +LEGACY_PIPE_INTERLEAVE_256B = 0x00000000, +LEGACY_PIPE_INTERLEAVE_512B = 0x00000001, +} LEGACY_PIPE_INTERLEAVE; + +/* + * META_CHUNK_SIZE enum + */ + +typedef enum META_CHUNK_SIZE { +META_CHUNK_SIZE_1KB = 0x00000000, +META_CHUNK_SIZE_2KB = 0x00000001, +META_CHUNK_SIZE_4KB = 0x00000002, +META_CHUNK_SIZE_8KB = 0x00000003, +} META_CHUNK_SIZE; + +/* + * META_LINEAR enum + */ + +typedef enum META_LINEAR { +META_SURF_TILED = 0x00000000, +META_SURF_LINEAR = 0x00000001, +} META_LINEAR; + +/* + * MIN_CHUNK_SIZE enum + */ + +typedef enum MIN_CHUNK_SIZE { +NO_MIN_CHUNK_SIZE = 0x00000000, +MIN_CHUNK_SIZE_256B = 0x00000001, +MIN_CHUNK_SIZE_512B = 0x00000002, +MIN_CHUNK_SIZE_1024B = 0x00000003, +} MIN_CHUNK_SIZE; + +/* + * MIN_META_CHUNK_SIZE enum + */ + +typedef enum MIN_META_CHUNK_SIZE { +NO_MIN_META_CHUNK_SIZE = 0x00000000, +MIN_META_CHUNK_SIZE_64B = 0x00000001, +MIN_META_CHUNK_SIZE_128B = 0x00000002, +MIN_META_CHUNK_SIZE_256B = 0x00000003, +} MIN_META_CHUNK_SIZE; + +/* + * PIPE_ALIGNED enum + */ + +typedef enum PIPE_ALIGNED { +PIPE_UNALIGNED_SURF = 0x00000000, +PIPE_ALIGNED_SURF = 0x00000001, +} PIPE_ALIGNED; + +/* + * PTE_BUFFER_MODE enum + */ + +typedef enum PTE_BUFFER_MODE { +PTE_BUFFER_MODE_0 = 0x00000000, +PTE_BUFFER_MODE_1 = 0x00000001, +} PTE_BUFFER_MODE; + +/* + * PTE_ROW_HEIGHT_LINEAR enum + */ + +typedef enum PTE_ROW_HEIGHT_LINEAR { +PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000, +PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001, +PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002, +PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003, +PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004, +PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005, +PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006, +PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007, +} PTE_ROW_HEIGHT_LINEAR; + +/* + * ROTATION_ANGLE enum + */ + +typedef enum ROTATION_ANGLE { +ROTATE_0_DEGREES = 0x00000000, +ROTATE_90_DEGREES = 0x00000001, +ROTATE_180_DEGREES = 0x00000002, +ROTATE_270_DEGREES = 0x00000003, +} ROTATION_ANGLE; + +/* + * SWATH_HEIGHT enum + */ + +typedef enum SWATH_HEIGHT { +SWATH_HEIGHT_1L = 0x00000000, +SWATH_HEIGHT_2L = 0x00000001, +SWATH_HEIGHT_4L = 0x00000002, +SWATH_HEIGHT_8L = 0x00000003, +SWATH_HEIGHT_16L = 0x00000004, +} SWATH_HEIGHT; + +/* + * USE_MALL_FOR_CURSOR enum + */ + +typedef enum USE_MALL_FOR_CURSOR { +USE_MALL_FOR_CURSOR_0 = 0x00000000, +USE_MALL_FOR_CURSOR_1 = 0x00000001, +} USE_MALL_FOR_CURSOR; + +/* + * USE_MALL_FOR_PSTATE_CHANGE enum + */ + +typedef enum USE_MALL_FOR_PSTATE_CHANGE { +USE_MALL_FOR_PSTATE_CHANGE_0 = 0x00000000, +USE_MALL_FOR_PSTATE_CHANGE_1 = 0x00000001, +} USE_MALL_FOR_PSTATE_CHANGE; + +/* + * USE_MALL_FOR_STATIC_SCREEN enum + */ + +typedef enum USE_MALL_FOR_STATIC_SCREEN { +USE_MALL_FOR_STATIC_SCREEN_0 = 0x00000000, +USE_MALL_FOR_STATIC_SCREEN_1 = 0x00000001, +} USE_MALL_FOR_STATIC_SCREEN; + +/* + * VMPG_SIZE enum + */ + +typedef enum VMPG_SIZE { +VMPG_SIZE_4KB = 0x00000000, +VMPG_SIZE_64KB = 0x00000001, +} VMPG_SIZE; + +/* + * VM_GROUP_SIZE enum + */ + +typedef enum VM_GROUP_SIZE { +VM_GROUP_SIZE_64B = 0x00000000, +VM_GROUP_SIZE_128B = 0x00000001, +VM_GROUP_SIZE_256B = 0x00000002, +VM_GROUP_SIZE_512B = 0x00000003, +VM_GROUP_SIZE_1024B = 0x00000004, +VM_GROUP_SIZE_2048B = 0x00000005, +} VM_GROUP_SIZE; + +/******************************************************* + * HUBPREQ Enums + *******************************************************/ + +/* + * DFQ_MIN_FREE_ENTRIES enum + */ + +typedef enum DFQ_MIN_FREE_ENTRIES { +DFQ_MIN_FREE_ENTRIES_0 = 0x00000000, +DFQ_MIN_FREE_ENTRIES_1 = 0x00000001, +DFQ_MIN_FREE_ENTRIES_2 = 0x00000002, +DFQ_MIN_FREE_ENTRIES_3 = 0x00000003, +DFQ_MIN_FREE_ENTRIES_4 = 0x00000004, +DFQ_MIN_FREE_ENTRIES_5 = 0x00000005, +DFQ_MIN_FREE_ENTRIES_6 = 0x00000006, +DFQ_MIN_FREE_ENTRIES_7 = 0x00000007, +} DFQ_MIN_FREE_ENTRIES; + +/* + * DFQ_NUM_ENTRIES enum + */ + +typedef enum DFQ_NUM_ENTRIES { +DFQ_NUM_ENTRIES_0 = 0x00000000, +DFQ_NUM_ENTRIES_1 = 0x00000001, +DFQ_NUM_ENTRIES_2 = 0x00000002, +DFQ_NUM_ENTRIES_3 = 0x00000003, +DFQ_NUM_ENTRIES_4 = 0x00000004, +DFQ_NUM_ENTRIES_5 = 0x00000005, +DFQ_NUM_ENTRIES_6 = 0x00000006, +DFQ_NUM_ENTRIES_7 = 0x00000007, +DFQ_NUM_ENTRIES_8 = 0x00000008, +} DFQ_NUM_ENTRIES; + +/* + * DFQ_SIZE enum + */ + +typedef enum DFQ_SIZE { +DFQ_SIZE_0 = 0x00000000, +DFQ_SIZE_1 = 0x00000001, +DFQ_SIZE_2 = 0x00000002, +DFQ_SIZE_3 = 0x00000003, +DFQ_SIZE_4 = 0x00000004, +DFQ_SIZE_5 = 0x00000005, +DFQ_SIZE_6 = 0x00000006, +DFQ_SIZE_7 = 0x00000007, +} DFQ_SIZE; + +/* + * DMDATA_VM_DONE enum + */ + +typedef enum DMDATA_VM_DONE { +DMDATA_VM_IS_NOT_DONE = 0x00000000, +DMDATA_VM_IS_DONE = 0x00000001, +} DMDATA_VM_DONE; + +/* + * EXPANSION_MODE enum + */ + +typedef enum EXPANSION_MODE { +EXPANSION_MODE_ZERO = 0x00000000, +EXPANSION_MODE_CONSERVATIVE = 0x00000001, +EXPANSION_MODE_OPTIMAL = 0x00000002, +} EXPANSION_MODE; + +/* + * FLIP_RATE enum + */ + +typedef enum FLIP_RATE { +FLIP_RATE_0 = 0x00000000, +FLIP_RATE_1 = 0x00000001, +FLIP_RATE_2 = 0x00000002, +FLIP_RATE_3 = 0x00000003, +FLIP_RATE_4 = 0x00000004, +FLIP_RATE_5 = 0x00000005, +FLIP_RATE_6 = 0x00000006, +FLIP_RATE_7 = 0x00000007, +} FLIP_RATE; + +/* + * INT_MASK enum + */ + +typedef enum INT_MASK { +INT_DISABLED = 0x00000000, +INT_ENABLED = 0x00000001, +} INT_MASK; + +/* + * PIPE_IN_FLUSH_URGENT enum + */ + +typedef enum PIPE_IN_FLUSH_URGENT { +PIPE_IN_FLUSH_URGENT_ENABLE = 0x00000000, +PIPE_IN_FLUSH_URGENT_DISABLE = 0x00000001, +} PIPE_IN_FLUSH_URGENT; + +/* + * PRQ_MRQ_FLUSH_URGENT enum + */ + +typedef enum PRQ_MRQ_FLUSH_URGENT { +PRQ_MRQ_FLUSH_URGENT_ENABLE = 0x00000000, +PRQ_MRQ_FLUSH_URGENT_DISABLE = 0x00000001, +} PRQ_MRQ_FLUSH_URGENT; + +/* + * ROW_TTU_MODE enum + */ + +typedef enum ROW_TTU_MODE { +END_OF_ROW_MODE = 0x00000000, +WATERMARK_MODE = 0x00000001, +} ROW_TTU_MODE; + +/* + * SURFACE_DCC enum + */ + +typedef enum SURFACE_DCC { +SURFACE_IS_NOT_DCC = 0x00000000, +SURFACE_IS_DCC = 0x00000001, +} SURFACE_DCC; + +/* + * SURFACE_DCC_IND_128B enum + */ + +typedef enum SURFACE_DCC_IND_128B { +SURFACE_DCC_IS_NOT_IND_128B = 0x00000000, +SURFACE_DCC_IS_IND_128B = 0x00000001, +} SURFACE_DCC_IND_128B; + +/* + * SURFACE_DCC_IND_64B enum + */ + +typedef enum SURFACE_DCC_IND_64B { +SURFACE_DCC_IS_NOT_IND_64B = 0x00000000, +SURFACE_DCC_IS_IND_64B = 0x00000001, +} SURFACE_DCC_IND_64B; + +/* + * SURFACE_DCC_IND_BLK enum + */ + +typedef enum SURFACE_DCC_IND_BLK { +SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0x00000000, +SURFACE_DCC_BLOCK_IS_IND_64B = 0x00000001, +SURFACE_DCC_BLOCK_IS_IND_128B = 0x00000002, +SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 0x00000003, +} SURFACE_DCC_IND_BLK; + +/* + * SURFACE_FLIP_AWAY_INT_TYPE enum + */ + +typedef enum SURFACE_FLIP_AWAY_INT_TYPE { +SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000, +SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001, +} SURFACE_FLIP_AWAY_INT_TYPE; + +/* + * SURFACE_FLIP_EXEC_DEBUG_MODE enum + */ + +typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE { +SURFACE_FLIP_EXEC_NORMAL_MODE = 0x00000000, +SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 0x00000001, +} SURFACE_FLIP_EXEC_DEBUG_MODE; + +/* + * SURFACE_FLIP_INT_TYPE enum + */ + +typedef enum SURFACE_FLIP_INT_TYPE { +SURFACE_FLIP_INT_LEVEL = 0x00000000, +SURFACE_FLIP_INT_PULSE = 0x00000001, +} SURFACE_FLIP_INT_TYPE; + +/* + * SURFACE_FLIP_IN_STEREOSYNC enum + */ + +typedef enum SURFACE_FLIP_IN_STEREOSYNC { +SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000, +SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001, +} SURFACE_FLIP_IN_STEREOSYNC; + +/* + * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum + */ + +typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC { +FLIP_ANY_FRAME = 0x00000000, +FLIP_LEFT_EYE = 0x00000001, +FLIP_RIGHT_EYE = 0x00000002, +SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003, +} SURFACE_FLIP_MODE_FOR_STEREOSYNC; + +/* + * SURFACE_FLIP_STEREO_SELECT_DISABLE enum + */ + +typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE { +SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000, +SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001, +} SURFACE_FLIP_STEREO_SELECT_DISABLE; + +/* + * SURFACE_FLIP_STEREO_SELECT_POLARITY enum + */ + +typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY { +SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000, +SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001, +} SURFACE_FLIP_STEREO_SELECT_POLARITY; + +/* + * SURFACE_FLIP_TYPE enum + */ + +typedef enum SURFACE_FLIP_TYPE { +SURFACE_V_FLIP = 0x00000000, +SURFACE_I_FLIP = 0x00000001, +} SURFACE_FLIP_TYPE; + +/* + * SURFACE_FLIP_VUPDATE_SKIP_NUM enum + */ + +typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM { +SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000, +SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001, +SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002, +SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003, +SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004, +SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005, +SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006, +SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007, +SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008, +SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009, +SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a, +SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b, +SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c, +SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d, +SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e, +SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f, +} SURFACE_FLIP_VUPDATE_SKIP_NUM; + +/* + * SURFACE_INUSE_RAED_NO_LATCH enum + */ + +typedef enum SURFACE_INUSE_RAED_NO_LATCH { +SURFACE_INUSE_IS_LATCHED = 0x00000000, +SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001, +} SURFACE_INUSE_RAED_NO_LATCH; + +/* + * SURFACE_TMZ enum + */ + +typedef enum SURFACE_TMZ { +SURFACE_IS_NOT_TMZ = 0x00000000, +SURFACE_IS_TMZ = 0x00000001, +} SURFACE_TMZ; + +/* + * SURFACE_UPDATE_LOCK enum + */ + +typedef enum SURFACE_UPDATE_LOCK { +SURFACE_UPDATE_IS_UNLOCKED = 0x00000000, +SURFACE_UPDATE_IS_LOCKED = 0x00000001, +} SURFACE_UPDATE_LOCK; + +/******************************************************* + * HUBPRET Enums + *******************************************************/ + +/* + * CROSSBAR_FOR_ALPHA enum + */ + +typedef enum CROSSBAR_FOR_ALPHA { +ALPHA_DATA_ONTO_ALPHA_PORT = 0x00000000, +Y_G_DATA_ONTO_ALPHA_PORT = 0x00000001, +CB_B_DATA_ONTO_ALPHA_PORT = 0x00000002, +CR_R_DATA_ONTO_ALPHA_PORT = 0x00000003, +} CROSSBAR_FOR_ALPHA; + +/* + * CROSSBAR_FOR_CB_B enum + */ + +typedef enum CROSSBAR_FOR_CB_B { +ALPHA_DATA_ONTO_CB_B_PORT = 0x00000000, +Y_G_DATA_ONTO_CB_B_PORT = 0x00000001, +CB_B_DATA_ONTO_CB_B_PORT = 0x00000002, +CR_R_DATA_ONTO_CB_B_PORT = 0x00000003, +} CROSSBAR_FOR_CB_B; + +/* + * CROSSBAR_FOR_CR_R enum + */ + +typedef enum CROSSBAR_FOR_CR_R { +ALPHA_DATA_ONTO_CR_R_PORT = 0x00000000, +Y_G_DATA_ONTO_CR_R_PORT = 0x00000001, +CB_B_DATA_ONTO_CR_R_PORT = 0x00000002, +CR_R_DATA_ONTO_CR_R_PORT = 0x00000003, +} CROSSBAR_FOR_CR_R; + +/* + * CROSSBAR_FOR_Y_G enum + */ + +typedef enum CROSSBAR_FOR_Y_G { +ALPHA_DATA_ONTO_Y_G_PORT = 0x00000000, +Y_G_DATA_ONTO_Y_G_PORT = 0x00000001, +CB_B_DATA_ONTO_Y_G_PORT = 0x00000002, +CR_R_DATA_ONTO_Y_G_PORT = 0x00000003, +} CROSSBAR_FOR_Y_G; + +/* + * DETILE_BUFFER_PACKER_ENABLE enum + */ + +typedef enum DETILE_BUFFER_PACKER_ENABLE { +DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000, +DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001, +} DETILE_BUFFER_PACKER_ENABLE; + +/* + * MEM_PWR_DIS_MODE enum + */ + +typedef enum MEM_PWR_DIS_MODE { +MEM_POWER_DIS_MODE_ENABLE = 0x00000000, +MEM_POWER_DIS_MODE_DISABLE = 0x00000001, +} MEM_PWR_DIS_MODE; + +/* + * MEM_PWR_FORCE_MODE enum + */ + +typedef enum MEM_PWR_FORCE_MODE { +MEM_POWER_FORCE_MODE_OFF = 0x00000000, +MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 0x00000001, +MEM_POWER_FORCE_MODE_DEEP_SLEEP = 0x00000002, +MEM_POWER_FORCE_MODE_SHUT_DOWN = 0x00000003, +} MEM_PWR_FORCE_MODE; + +/* + * MEM_PWR_STATUS enum + */ + +typedef enum MEM_PWR_STATUS { +MEM_POWER_STATUS_ON = 0x00000000, +MEM_POWER_STATUS_LIGHT_SLEEP = 0x00000001, +MEM_POWER_STATUS_DEEP_SLEEP = 0x00000002, +MEM_POWER_STATUS_SHUT_DOWN = 0x00000003, +} MEM_PWR_STATUS; + +/* + * PIPE_INT_MASK_MODE enum + */ + +typedef enum PIPE_INT_MASK_MODE { +PIPE_INT_MASK_MODE_DISABLE = 0x00000000, +PIPE_INT_MASK_MODE_ENABLE = 0x00000001, +} PIPE_INT_MASK_MODE; + +/* + * PIPE_INT_TYPE_MODE enum + */ + +typedef enum PIPE_INT_TYPE_MODE { +PIPE_INT_TYPE_MODE_DISABLE = 0x00000000, +PIPE_INT_TYPE_MODE_ENABLE = 0x00000001, +} PIPE_INT_TYPE_MODE; + +/* + * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum + */ + +typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE { +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, +} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE; + +/******************************************************* + * CURSOR Enums + *******************************************************/ + +/* + * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum + */ + +typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE { +CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, +CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, +CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, +} CROB_MEM_PWR_LIGHT_SLEEP_MODE; + +/* + * CURSOR_2X_MAGNIFY enum + */ + +typedef enum CURSOR_2X_MAGNIFY { +CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000, +CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001, +} CURSOR_2X_MAGNIFY; + +/* + * CURSOR_ENABLE enum + */ + +typedef enum CURSOR_ENABLE { +CURSOR_IS_DISABLE = 0x00000000, +CURSOR_IS_ENABLE = 0x00000001, +} CURSOR_ENABLE; + +/* + * CURSOR_LINES_PER_CHUNK enum + */ + +typedef enum CURSOR_LINES_PER_CHUNK { +CURSOR_LINE_PER_CHUNK_1 = 0x00000000, +CURSOR_LINE_PER_CHUNK_2 = 0x00000001, +CURSOR_LINE_PER_CHUNK_4 = 0x00000002, +CURSOR_LINE_PER_CHUNK_8 = 0x00000003, +CURSOR_LINE_PER_CHUNK_16 = 0x00000004, +} CURSOR_LINES_PER_CHUNK; + +/* + * CURSOR_MODE enum + */ + +typedef enum CURSOR_MODE { +CURSOR_MONO_2BIT = 0x00000000, +CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001, +CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, +CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, +CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004, +CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005, +} CURSOR_MODE; + +/* + * CURSOR_PERFMON_LATENCY_MEASURE_EN enum + */ + +typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN { +CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000, +CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001, +} CURSOR_PERFMON_LATENCY_MEASURE_EN; + +/* + * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum + */ + +typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL { +CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000, +CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001, +} CURSOR_PERFMON_LATENCY_MEASURE_SEL; + +/* + * CURSOR_PITCH enum + */ + +typedef enum CURSOR_PITCH { +CURSOR_PITCH_64_PIXELS = 0x00000000, +CURSOR_PITCH_128_PIXELS = 0x00000001, +CURSOR_PITCH_256_PIXELS = 0x00000002, +} CURSOR_PITCH; + +/* + * CURSOR_REQ_MODE enum + */ + +typedef enum CURSOR_REQ_MODE { +CURSOR_REQUEST_NORMALLY = 0x00000000, +CURSOR_REQUEST_EARLY = 0x00000001, +} CURSOR_REQ_MODE; + +/* + * CURSOR_SNOOP enum + */ + +typedef enum CURSOR_SNOOP { +CURSOR_IS_NOT_SNOOP = 0x00000000, +CURSOR_IS_SNOOP = 0x00000001, +} CURSOR_SNOOP; + +/* + * CURSOR_STEREO_EN enum + */ + +typedef enum CURSOR_STEREO_EN { +CURSOR_STEREO_IS_DISABLED = 0x00000000, +CURSOR_STEREO_IS_ENABLED = 0x00000001, +} CURSOR_STEREO_EN; + +/* + * CURSOR_SURFACE_TMZ enum + */ + +typedef enum CURSOR_SURFACE_TMZ { +CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000, +CURSOR_SURFACE_IS_TMZ = 0x00000001, +} CURSOR_SURFACE_TMZ; + +/* + * CURSOR_SYSTEM enum + */ + +typedef enum CURSOR_SYSTEM { +CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000, +CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001, +} CURSOR_SYSTEM; + +/* + * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum + */ + +typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS { +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000, +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001, +} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS; + +/* + * DMDATA_DONE enum + */ + +typedef enum DMDATA_DONE { +DMDATA_NOT_SENT_TO_DIG = 0x00000000, +DMDATA_SENT_TO_DIG = 0x00000001, +} DMDATA_DONE; + +/* + * DMDATA_MODE enum + */ + +typedef enum DMDATA_MODE { +DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000, +DMDATA_HARDWARE_UPDATE_MODE = 0x00000001, +} DMDATA_MODE; + +/* + * DMDATA_QOS_MODE enum + */ + +typedef enum DMDATA_QOS_MODE { +DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000, +DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001, +} DMDATA_QOS_MODE; + +/* + * DMDATA_REPEAT enum + */ + +typedef enum DMDATA_REPEAT { +DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000, +DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001, +} DMDATA_REPEAT; + +/* + * DMDATA_UNDERFLOW enum + */ + +typedef enum DMDATA_UNDERFLOW { +DMDATA_NOT_UNDERFLOW = 0x00000000, +DMDATA_UNDERFLOWED = 0x00000001, +} DMDATA_UNDERFLOW; + +/* + * DMDATA_UNDERFLOW_CLEAR enum + */ + +typedef enum DMDATA_UNDERFLOW_CLEAR { +DMDATA_DONT_CLEAR = 0x00000000, +DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001, +} DMDATA_UNDERFLOW_CLEAR; + +/* + * DMDATA_UPDATED enum + */ + +typedef enum DMDATA_UPDATED { +DMDATA_NOT_UPDATED = 0x00000000, +DMDATA_WAS_UPDATED = 0x00000001, +} DMDATA_UPDATED; + +/******************************************************* + * HUBBUB_SDPIF Enums + *******************************************************/ + +/* + * RESPONSE_STATUS enum + */ + +typedef enum RESPONSE_STATUS { +OKAY = 0x00000000, +EXOKAY = 0x00000001, +SLVERR = 0x00000002, +DECERR = 0x00000003, +EARLY = 0x00000004, +OKAY_NODATA = 0x00000005, +PROTVIOL = 0x00000006, +TRANSERR = 0x00000007, +CMPTO = 0x00000008, +CRS = 0x0000000c, +} RESPONSE_STATUS; + +/******************************************************* + * HUBBUB_RET_PATH Enums + *******************************************************/ + +/* + * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum + */ + +typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE { +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, +} DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE; + +/* + * DCHUBBUB_MEM_PWR_DIS_MODE enum + */ + +typedef enum DCHUBBUB_MEM_PWR_DIS_MODE { +DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0x00000000, +DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 0x00000001, +} DCHUBBUB_MEM_PWR_DIS_MODE; + +/* + * DCHUBBUB_MEM_PWR_MODE enum + */ + +typedef enum DCHUBBUB_MEM_PWR_MODE { +DCHUBBUB_MEM_POWER_MODE_OFF = 0x00000000, +DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 0x00000001, +DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 0x00000002, +DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 0x00000003, +} DCHUBBUB_MEM_PWR_MODE; + +/******************************************************* + * MPC_CFG Enums + *******************************************************/ + +/* + * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum + */ + +typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET { +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, +} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET; + +/* + * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum + */ + +typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET { +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, +} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET; + +/* + * MPC_CFG_ADR_VUPDATE_LOCK_SET enum + */ + +typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET { +MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000, +MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001, +} MPC_CFG_ADR_VUPDATE_LOCK_SET; + +/* + * MPC_CFG_CFG_VUPDATE_LOCK_SET enum + */ + +typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET { +MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, +MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, +} MPC_CFG_CFG_VUPDATE_LOCK_SET; + +/* + * MPC_CFG_CUR_VUPDATE_LOCK_SET enum + */ + +typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET { +MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, +MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, +} MPC_CFG_CUR_VUPDATE_LOCK_SET; + +/* + * MPC_CFG_MPC_TEST_CLK_SEL enum + */ + +typedef enum MPC_CFG_MPC_TEST_CLK_SEL { +MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000, +MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001, +MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002, +MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003, +} MPC_CFG_MPC_TEST_CLK_SEL; + +/* + * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN { +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, +} MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN; + +/* + * MPC_CRC_CALC_INTERLACE_MODE enum + */ + +typedef enum MPC_CRC_CALC_INTERLACE_MODE { +MPC_CRC_INTERLACE_MODE_TOP = 0x00000000, +MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, +MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002, +MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003, +} MPC_CRC_CALC_INTERLACE_MODE; + +/* + * MPC_CRC_CALC_MODE enum + */ + +typedef enum MPC_CRC_CALC_MODE { +MPC_CRC_ONE_SHOT_MODE = 0x00000000, +MPC_CRC_CONTINUOUS_MODE = 0x00000001, +} MPC_CRC_CALC_MODE; + +/* + * MPC_CRC_CALC_STEREO_MODE enum + */ + +typedef enum MPC_CRC_CALC_STEREO_MODE { +MPC_CRC_STEREO_MODE_LEFT = 0x00000000, +MPC_CRC_STEREO_MODE_RIGHT = 0x00000001, +MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002, +MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003, +} MPC_CRC_CALC_STEREO_MODE; + +/* + * MPC_CRC_SOURCE_SELECT enum + */ + +typedef enum MPC_CRC_SOURCE_SELECT { +MPC_CRC_SOURCE_SEL_DPP = 0x00000000, +MPC_CRC_SOURCE_SEL_OPP = 0x00000001, +MPC_CRC_SOURCE_SEL_DWB = 0x00000002, +MPC_CRC_SOURCE_SEL_OTHER = 0x00000003, +} MPC_CRC_SOURCE_SELECT; + +/* + * MPC_DEBUG_BUS1_DATA_SELECT enum + */ + +typedef enum MPC_DEBUG_BUS1_DATA_SELECT { +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0x00000000, +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 0x00000001, +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 0x00000002, +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 0x00000003, +} MPC_DEBUG_BUS1_DATA_SELECT; + +/* + * MPC_DEBUG_BUS2_DATA_SELECT enum + */ + +typedef enum MPC_DEBUG_BUS2_DATA_SELECT { +MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0x00000000, +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 0x00000001, +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 0x00000002, +MPC_DEBUG_BUS2_DATA_SELECT_RES = 0x00000003, +} MPC_DEBUG_BUS2_DATA_SELECT; + +/* + * MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT enum + */ + +typedef enum MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT { +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0x00000000, +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 0x00000001, +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 0x00000002, +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 0x00000003, +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 0x00000004, +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 0x00000005, +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 0x00000006, +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 0x00000007, +} MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT; + +/* + * MPC_DEBUG_BUS_MPCC_BYTE_SELECT enum + */ + +typedef enum MPC_DEBUG_BUS_MPCC_BYTE_SELECT { +MPC_DEBUG_BUS_MPCC_BYTE0 = 0x00000000, +MPC_DEBUG_BUS_MPCC_BYTE1 = 0x00000001, +MPC_DEBUG_BUS_MPCC_BYTE2 = 0x00000002, +MPC_DEBUG_BUS_MPCC_BYTE3 = 0x00000003, +} MPC_DEBUG_BUS_MPCC_BYTE_SELECT; + +/******************************************************* + * MPC_OCSC Enums + *******************************************************/ + +/* + * MPC_OCSC_COEF_FORMAT enum + */ + +typedef enum MPC_OCSC_COEF_FORMAT { +MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000, +MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001, +} MPC_OCSC_COEF_FORMAT; + +/* + * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN { +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, +} MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN; + +/* + * MPC_OUT_CSC_MODE enum + */ + +typedef enum MPC_OUT_CSC_MODE { +MPC_OUT_CSC_MODE_0 = 0x00000000, +MPC_OUT_CSC_MODE_1 = 0x00000001, +MPC_OUT_CSC_MODE_2 = 0x00000002, +MPC_OUT_CSC_MODE_RSV = 0x00000003, +} MPC_OUT_CSC_MODE; + +/* + * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum + */ + +typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE { +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000, +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001, +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002, +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003, +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004, +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005, +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006, +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007, +} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE; + +/* + * MPC_OUT_RATE_CONTROL_DISABLE_SET enum + */ + +typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET { +MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000, +MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001, +} MPC_OUT_RATE_CONTROL_DISABLE_SET; + +/******************************************************* + * MPCC Enums + *******************************************************/ + +/* + * MPCC_BG_COLOR_BPC enum + */ + +typedef enum MPCC_BG_COLOR_BPC { +MPCC_BG_COLOR_BPC_8bit = 0x00000000, +MPCC_BG_COLOR_BPC_9bit = 0x00000001, +MPCC_BG_COLOR_BPC_10bit = 0x00000002, +MPCC_BG_COLOR_BPC_11bit = 0x00000003, +MPCC_BG_COLOR_BPC_12bit = 0x00000004, +} MPCC_BG_COLOR_BPC; + +/* + * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum + */ + +typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY { +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000, +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001, +} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY; + +/* + * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum + */ + +typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE { +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000, +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001, +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002, +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003, +} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE; + +/* + * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum + */ + +typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE { +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000, +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001, +} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE; + +/* + * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum + */ + +typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE { +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000, +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001, +} MPCC_CONTROL_MPCC_BOT_GAIN_MODE; + +/* + * MPCC_CONTROL_MPCC_MODE enum + */ + +typedef enum MPCC_CONTROL_MPCC_MODE { +MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000, +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001, +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002, +MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003, +} MPCC_CONTROL_MPCC_MODE; + +/* + * MPCC_SM_CONTROL_MPCC_SM_EN enum + */ + +typedef enum MPCC_SM_CONTROL_MPCC_SM_EN { +MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000, +MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001, +} MPCC_SM_CONTROL_MPCC_SM_EN; + +/* + * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum + */ + +typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT { +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000, +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001, +} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT; + +/* + * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum + */ + +typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL { +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000, +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001, +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002, +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003, +} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL; + +/* + * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum + */ + +typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL { +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000, +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001, +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002, +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003, +} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL; + +/* + * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum + */ + +typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT { +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000, +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001, +} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT; + +/* + * MPCC_SM_CONTROL_MPCC_SM_MODE enum + */ + +typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE { +MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000, +MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002, +MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004, +MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006, +} MPCC_SM_CONTROL_MPCC_SM_MODE; + +/* + * MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN { +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, +} MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN; + +/******************************************************* + * MPCC_OGAM Enums + *******************************************************/ + +/* + * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum + */ + +typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM { +MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000, +MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001, +} MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM; + +/* + * MPCC_GAMUT_REMAP_MODE_ENUM enum + */ + +typedef enum MPCC_GAMUT_REMAP_MODE_ENUM { +MPCC_GAMUT_REMAP_MODE_0 = 0x00000000, +MPCC_GAMUT_REMAP_MODE_1 = 0x00000001, +MPCC_GAMUT_REMAP_MODE_2 = 0x00000002, +MPCC_GAMUT_REMAP_MODE_RSV = 0x00000003, +} MPCC_GAMUT_REMAP_MODE_ENUM; + +/* + * MPCC_OGAM_LUT_2_CONFIG_ENUM enum + */ + +typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM { +MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0x00000000, +MPCC_OGAM_LUT_2CFG_MEMORY_A = 0x00000001, +MPCC_OGAM_LUT_2CFG_MEMORY_B = 0x00000002, +} MPCC_OGAM_LUT_2_CONFIG_ENUM; + +/* + * MPCC_OGAM_LUT_CONFIG_MODE enum + */ + +typedef enum MPCC_OGAM_LUT_CONFIG_MODE { +MPCC_OGAM_DIFFERENT_RGB = 0x00000000, +MPCC_OGAM_ALL_USE_R = 0x00000001, +} MPCC_OGAM_LUT_CONFIG_MODE; + +/* + * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum + */ + +typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM { +MPCC_OGAM_ENABLE_PWL = 0x00000000, +MPCC_OGAM_DISABLE_PWL = 0x00000001, +} MPCC_OGAM_LUT_PWL_DISABLE_ENUM; + +/* + * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum + */ + +typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL { +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000, +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001, +} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL; + +/* + * MPCC_OGAM_LUT_RAM_SEL enum + */ + +typedef enum MPCC_OGAM_LUT_RAM_SEL { +MPCC_OGAM_RAMA_ACCESS = 0x00000000, +MPCC_OGAM_RAMB_ACCESS = 0x00000001, +} MPCC_OGAM_LUT_RAM_SEL; + +/* + * MPCC_OGAM_LUT_READ_COLOR_SEL enum + */ + +typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL { +MPCC_OGAM_BLUE_LUT = 0x00000000, +MPCC_OGAM_GREEN_LUT = 0x00000001, +MPCC_OGAM_RED_LUT = 0x00000002, +} MPCC_OGAM_LUT_READ_COLOR_SEL; + +/* + * MPCC_OGAM_LUT_READ_DBG enum + */ + +typedef enum MPCC_OGAM_LUT_READ_DBG { +MPCC_OGAM_DISABLE_DEBUG = 0x00000000, +MPCC_OGAM_ENABLE_DEBUG = 0x00000001, +} MPCC_OGAM_LUT_READ_DBG; + +/* + * MPCC_OGAM_LUT_SEL_ENUM enum + */ + +typedef enum MPCC_OGAM_LUT_SEL_ENUM { +MPCC_OGAM_RAMA = 0x00000000, +MPCC_OGAM_RAMB = 0x00000001, +} MPCC_OGAM_LUT_SEL_ENUM; + +/* + * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum + */ + +typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM { +MPCC_OGAM_MODE_0 = 0x00000000, +MPCC_OGAM_MODE_RSV1 = 0x00000001, +MPCC_OGAM_MODE_2 = 0x00000002, +MPCC_OGAM_MODE_RSV = 0x00000003, +} MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM; + +/* + * MPCC_OGAM_NUM_SEG enum + */ + +typedef enum MPCC_OGAM_NUM_SEG { +MPCC_OGAM_SEGMENTS_1 = 0x00000000, +MPCC_OGAM_SEGMENTS_2 = 0x00000001, +MPCC_OGAM_SEGMENTS_4 = 0x00000002, +MPCC_OGAM_SEGMENTS_8 = 0x00000003, +MPCC_OGAM_SEGMENTS_16 = 0x00000004, +MPCC_OGAM_SEGMENTS_32 = 0x00000005, +MPCC_OGAM_SEGMENTS_64 = 0x00000006, +MPCC_OGAM_SEGMENTS_128 = 0x00000007, +} MPCC_OGAM_NUM_SEG; + +/* + * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN { +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, +} MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN; + +/******************************************************* + * MPCC_MCM Enums + *******************************************************/ + +/* + * MPCC_MCM_3DLUT_30BIT_ENUM enum + */ + +typedef enum MPCC_MCM_3DLUT_30BIT_ENUM { +MPCC_MCM_3DLUT_36BIT = 0x00000000, +MPCC_MCM_3DLUT_30BIT = 0x00000001, +} MPCC_MCM_3DLUT_30BIT_ENUM; + +/* + * MPCC_MCM_3DLUT_RAM_SEL enum + */ + +typedef enum MPCC_MCM_3DLUT_RAM_SEL { +MPCC_MCM_RAM0_ACCESS = 0x00000000, +MPCC_MCM_RAM1_ACCESS = 0x00000001, +MPCC_MCM_RAM2_ACCESS = 0x00000002, +MPCC_MCM_RAM3_ACCESS = 0x00000003, +} MPCC_MCM_3DLUT_RAM_SEL; + +/* + * MPCC_MCM_3DLUT_SIZE_ENUM enum + */ + +typedef enum MPCC_MCM_3DLUT_SIZE_ENUM { +MPCC_MCM_3DLUT_17CUBE = 0x00000000, +MPCC_MCM_3DLUT_9CUBE = 0x00000001, +} MPCC_MCM_3DLUT_SIZE_ENUM; + +/* + * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum + */ + +typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM { +MPCC_MCM_GAMMA_LUT_BYPASS = 0x00000000, +MPCC_MCM_GAMMA_LUT_RESERVED_1 = 0x00000001, +MPCC_MCM_GAMMA_LUT_RAM_LUT = 0x00000002, +MPCC_MCM_GAMMA_LUT_RESERVED_3 = 0x00000003, +} MPCC_MCM_GAMMA_LUT_MODE_ENUM; + +/* + * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum + */ + +typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM { +MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0x00000000, +MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 0x00000001, +} MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM; + +/* + * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum + */ + +typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM { +MPCC_MCM_GAMMA_LUT_RAMA = 0x00000000, +MPCC_MCM_GAMMA_LUT_RAMB = 0x00000001, +} MPCC_MCM_GAMMA_LUT_SEL_ENUM; + +/* + * MPCC_MCM_LUT_2_MODE_ENUM enum + */ + +typedef enum MPCC_MCM_LUT_2_MODE_ENUM { +MPCC_MCM_LUT_2_MODE_BYPASS = 0x00000000, +MPCC_MCM_LUT_2_MODE_RAMA_LUT = 0x00000001, +MPCC_MCM_LUT_2_MODE_RAMB_LUT = 0x00000002, +} MPCC_MCM_LUT_2_MODE_ENUM; + +/* + * MPCC_MCM_LUT_CONFIG_MODE enum + */ + +typedef enum MPCC_MCM_LUT_CONFIG_MODE { +MPCC_MCM_LUT_DIFFERENT_RGB = 0x00000000, +MPCC_MCM_LUT_ALL_USE_R = 0x00000001, +} MPCC_MCM_LUT_CONFIG_MODE; + +/* + * MPCC_MCM_LUT_NUM_SEG enum + */ + +typedef enum MPCC_MCM_LUT_NUM_SEG { +MPCC_MCM_LUT_SEGMENTS_1 = 0x00000000, +MPCC_MCM_LUT_SEGMENTS_2 = 0x00000001, +MPCC_MCM_LUT_SEGMENTS_4 = 0x00000002, +MPCC_MCM_LUT_SEGMENTS_8 = 0x00000003, +MPCC_MCM_LUT_SEGMENTS_16 = 0x00000004, +MPCC_MCM_LUT_SEGMENTS_32 = 0x00000005, +MPCC_MCM_LUT_SEGMENTS_64 = 0x00000006, +MPCC_MCM_LUT_SEGMENTS_128 = 0x00000007, +} MPCC_MCM_LUT_NUM_SEG; + +/* + * MPCC_MCM_LUT_RAM_SEL enum + */ + +typedef enum MPCC_MCM_LUT_RAM_SEL { +MPCC_MCM_LUT_RAMA_ACCESS = 0x00000000, +MPCC_MCM_LUT_RAMB_ACCESS = 0x00000001, +} MPCC_MCM_LUT_RAM_SEL; + +/* + * MPCC_MCM_LUT_READ_COLOR_SEL enum + */ + +typedef enum MPCC_MCM_LUT_READ_COLOR_SEL { +MPCC_MCM_LUT_BLUE_LUT = 0x00000000, +MPCC_MCM_LUT_GREEN_LUT = 0x00000001, +MPCC_MCM_LUT_RED_LUT = 0x00000002, +} MPCC_MCM_LUT_READ_COLOR_SEL; + +/* + * MPCC_MCM_LUT_READ_DBG enum + */ + +typedef enum MPCC_MCM_LUT_READ_DBG { +MPCC_MCM_LUT_DISABLE_DEBUG = 0x00000000, +MPCC_MCM_LUT_ENABLE_DEBUG = 0x00000001, +} MPCC_MCM_LUT_READ_DBG; + +/* + * MPCC_MCM_MEM_PWR_FORCE_ENUM enum + */ + +typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM { +MPCC_MCM_MEM_PWR_FORCE_DIS = 0x00000000, +MPCC_MCM_MEM_PWR_FORCE_LS = 0x00000001, +MPCC_MCM_MEM_PWR_FORCE_DS = 0x00000002, +MPCC_MCM_MEM_PWR_FORCE_SD = 0x00000003, +} MPCC_MCM_MEM_PWR_FORCE_ENUM; + +/* + * MPCC_MCM_MEM_PWR_STATE_ENUM enum + */ + +typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM { +MPCC_MCM_MEM_PWR_STATE_ON = 0x00000000, +MPCC_MCM_MEM_PWR_STATE_LS = 0x00000001, +MPCC_MCM_MEM_PWR_STATE_DS = 0x00000002, +MPCC_MCM_MEM_PWR_STATE_SD = 0x00000003, +} MPCC_MCM_MEM_PWR_STATE_ENUM; + +/******************************************************* + * ABM Enums + *******************************************************/ + +/******************************************************* + * DPG Enums + *******************************************************/ + +/* + * ENUM_DPG_BIT_DEPTH enum + */ + +typedef enum ENUM_DPG_BIT_DEPTH { +ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000, +ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001, +ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002, +ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003, +} ENUM_DPG_BIT_DEPTH; + +/* + * ENUM_DPG_DYNAMIC_RANGE enum + */ + +typedef enum ENUM_DPG_DYNAMIC_RANGE { +ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000, +ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001, +} ENUM_DPG_DYNAMIC_RANGE; + +/* + * ENUM_DPG_EN enum + */ + +typedef enum ENUM_DPG_EN { +ENUM_DPG_DISABLE = 0x00000000, +ENUM_DPG_ENABLE = 0x00000001, +} ENUM_DPG_EN; + +/* + * ENUM_DPG_FIELD_POLARITY enum + */ + +typedef enum ENUM_DPG_FIELD_POLARITY { +ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000, +ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001, +} ENUM_DPG_FIELD_POLARITY; + +/* + * ENUM_DPG_MODE enum + */ + +typedef enum ENUM_DPG_MODE { +ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000, +ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001, +ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002, +ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003, +ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004, +ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005, +ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006, +ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007, +} ENUM_DPG_MODE; + +/******************************************************* + * FMT Enums + *******************************************************/ + +/* + * FMTMEM_PWR_DIS_CTRL enum + */ + +typedef enum FMTMEM_PWR_DIS_CTRL { +FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, +FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, +} FMTMEM_PWR_DIS_CTRL; + +/* + * FMTMEM_PWR_FORCE_CTRL enum + */ + +typedef enum FMTMEM_PWR_FORCE_CTRL { +FMTMEM_NO_FORCE_REQUEST = 0x00000000, +FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} FMTMEM_PWR_FORCE_CTRL; + +/* + * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000, +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001, +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002, +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003, +} FMT_BIT_DEPTH_CONTROL_25FRC_SEL; + +/* + * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000, +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001, +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002, +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003, +} FMT_BIT_DEPTH_CONTROL_50FRC_SEL; + +/* + * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000, +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001, +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002, +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003, +} FMT_BIT_DEPTH_CONTROL_75FRC_SEL; + +/* + * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000, +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001, +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002, +} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; + +/* + * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001, +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; + +/* + * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; + +/* + * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001, +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; + +/* + * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; + +/* + * FMT_CLAMP_CNTL_COLOR_FORMAT enum + */ + +typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000, +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001, +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002, +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003, +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004, +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005, +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006, +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007, +} FMT_CLAMP_CNTL_COLOR_FORMAT; + +/* + * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum + */ + +typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000, +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001, +} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; + +/* + * FMT_CONTROL_PIXEL_ENCODING enum + */ + +typedef enum FMT_CONTROL_PIXEL_ENCODING { +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000, +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001, +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002, +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003, +} FMT_CONTROL_PIXEL_ENCODING; + +/* + * FMT_CONTROL_SUBSAMPLING_MODE enum + */ + +typedef enum FMT_CONTROL_SUBSAMPLING_MODE { +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000, +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001, +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002, +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003, +} FMT_CONTROL_SUBSAMPLING_MODE; + +/* + * FMT_CONTROL_SUBSAMPLING_ORDER enum + */ + +typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000, +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001, +} FMT_CONTROL_SUBSAMPLING_ORDER; + +/* + * FMT_DEBUG_CNTL_COLOR_SELECT enum + */ + +typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000, +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001, +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002, +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003, +} FMT_DEBUG_CNTL_COLOR_SELECT; + +/* + * FMT_DYNAMIC_EXP_MODE enum + */ + +typedef enum FMT_DYNAMIC_EXP_MODE { +FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000, +FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001, +} FMT_DYNAMIC_EXP_MODE; + +/* + * FMT_FRAME_RANDOM_ENABLE_CONTROL enum + */ + +typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL { +FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000, +FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001, +} FMT_FRAME_RANDOM_ENABLE_CONTROL; + +/* + * FMT_POWER_STATE_ENUM enum + */ + +typedef enum FMT_POWER_STATE_ENUM { +FMT_POWER_STATE_ENUM_ON = 0x00000000, +FMT_POWER_STATE_ENUM_LS = 0x00000001, +FMT_POWER_STATE_ENUM_DS = 0x00000002, +FMT_POWER_STATE_ENUM_SD = 0x00000003, +} FMT_POWER_STATE_ENUM; + +/* + * FMT_RGB_RANDOM_ENABLE_CONTROL enum + */ + +typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL { +FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000, +FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001, +} FMT_RGB_RANDOM_ENABLE_CONTROL; + +/* + * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum + */ + +typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL { +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000, +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001, +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002, +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003, +} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL; + +/* + * FMT_SPATIAL_DITHER_MODE enum + */ + +typedef enum FMT_SPATIAL_DITHER_MODE { +FMT_SPATIAL_DITHER_MODE_0 = 0x00000000, +FMT_SPATIAL_DITHER_MODE_1 = 0x00000001, +FMT_SPATIAL_DITHER_MODE_2 = 0x00000002, +FMT_SPATIAL_DITHER_MODE_3 = 0x00000003, +} FMT_SPATIAL_DITHER_MODE; + +/* + * FMT_STEREOSYNC_OVERRIDE_CONTROL enum + */ + +typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL { +FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000, +FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001, +} FMT_STEREOSYNC_OVERRIDE_CONTROL; + +/* + * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum + */ + +typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000, +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001, +} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; + +/******************************************************* + * OPPBUF Enums + *******************************************************/ + +/* + * OPPBUF_DISPLAY_SEGMENTATION enum + */ + +typedef enum OPPBUF_DISPLAY_SEGMENTATION { +OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0x00000000, +OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 0x00000001, +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 0x00000002, +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 0x00000003, +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 0x00000004, +} OPPBUF_DISPLAY_SEGMENTATION; + +/******************************************************* + * OPP_PIPE Enums + *******************************************************/ + +/* + * OPP_PIPE_CLOCK_ENABLE_CONTROL enum + */ + +typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL { +OPP_PIPE_CLOCK_DISABLE = 0x00000000, +OPP_PIPE_CLOCK_ENABLE = 0x00000001, +} OPP_PIPE_CLOCK_ENABLE_CONTROL; + +/* + * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum + */ + +typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL { +OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000, +OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001, +} OPP_PIPE_DIGTIAL_BYPASS_CONTROL; + +/******************************************************* + * OPP_PIPE_CRC Enums + *******************************************************/ + +/* + * OPP_PIPE_CRC_CONT_EN enum + */ + +typedef enum OPP_PIPE_CRC_CONT_EN { +OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000, +OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001, +} OPP_PIPE_CRC_CONT_EN; + +/* + * OPP_PIPE_CRC_EN enum + */ + +typedef enum OPP_PIPE_CRC_EN { +OPP_PIPE_CRC_DISABLE = 0x00000000, +OPP_PIPE_CRC_ENABLE = 0x00000001, +} OPP_PIPE_CRC_EN; + +/* + * OPP_PIPE_CRC_INTERLACE_EN enum + */ + +typedef enum OPP_PIPE_CRC_INTERLACE_EN { +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000, +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001, +} OPP_PIPE_CRC_INTERLACE_EN; + +/* + * OPP_PIPE_CRC_INTERLACE_MODE enum + */ + +typedef enum OPP_PIPE_CRC_INTERLACE_MODE { +OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000, +OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002, +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003, +} OPP_PIPE_CRC_INTERLACE_MODE; + +/* + * OPP_PIPE_CRC_ONE_SHOT_PENDING enum + */ + +typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING { +OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000, +OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001, +} OPP_PIPE_CRC_ONE_SHOT_PENDING; + +/* + * OPP_PIPE_CRC_PIXEL_SELECT enum + */ + +typedef enum OPP_PIPE_CRC_PIXEL_SELECT { +OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000, +OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001, +OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002, +OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003, +} OPP_PIPE_CRC_PIXEL_SELECT; + +/* + * OPP_PIPE_CRC_SOURCE_SELECT enum + */ + +typedef enum OPP_PIPE_CRC_SOURCE_SELECT { +OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000, +OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001, +} OPP_PIPE_CRC_SOURCE_SELECT; + +/* + * OPP_PIPE_CRC_STEREO_EN enum + */ + +typedef enum OPP_PIPE_CRC_STEREO_EN { +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000, +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001, +} OPP_PIPE_CRC_STEREO_EN; + +/* + * OPP_PIPE_CRC_STEREO_MODE enum + */ + +typedef enum OPP_PIPE_CRC_STEREO_MODE { +OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000, +OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001, +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002, +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003, +} OPP_PIPE_CRC_STEREO_MODE; + +/******************************************************* + * OPP_TOP Enums + *******************************************************/ + +/* + * OPP_ABM_DEBUG_BUS_SELECT_CONTROL enum + */ + +typedef enum OPP_ABM_DEBUG_BUS_SELECT_CONTROL { +DEBUG_BUS_SELECT_ABM0 = 0x00000000, +DEBUG_BUS_SELECT_ABM1 = 0x00000001, +DEBUG_BUS_SELECT_ABM2 = 0x00000002, +DEBUG_BUS_SELECT_ABM3 = 0x00000003, +DEBUG_BUS_SELECT_ABM_RESERVED0 = 0x00000004, +DEBUG_BUS_SELECT_ABM_RESERVED1 = 0x00000005, +} OPP_ABM_DEBUG_BUS_SELECT_CONTROL; + +/* + * OPP_DPG_DEBUG_BUS_SELECT_CONTROL enum + */ + +typedef enum OPP_DPG_DEBUG_BUS_SELECT_CONTROL { +DEBUG_BUS_SELECT_DPG0 = 0x00000000, +DEBUG_BUS_SELECT_DPG1 = 0x00000001, +DEBUG_BUS_SELECT_DPG2 = 0x00000002, +DEBUG_BUS_SELECT_DPG3 = 0x00000003, +DEBUG_BUS_SELECT_DPG_RESERVED0 = 0x00000004, +DEBUG_BUS_SELECT_DPG_RESERVED1 = 0x00000005, +} OPP_DPG_DEBUG_BUS_SELECT_CONTROL; + +/* + * OPP_FMT_DEBUG_BUS_SELECT_CONTROL enum + */ + +typedef enum OPP_FMT_DEBUG_BUS_SELECT_CONTROL { +DEBUG_BUS_SELECT_FMT0 = 0x00000000, +DEBUG_BUS_SELECT_FMT1 = 0x00000001, +DEBUG_BUS_SELECT_FMT2 = 0x00000002, +DEBUG_BUS_SELECT_FMT3 = 0x00000003, +DEBUG_BUS_SELECT_FMT_RESERVED0 = 0x00000004, +DEBUG_BUS_SELECT_FMT_RESERVED1 = 0x00000005, +} OPP_FMT_DEBUG_BUS_SELECT_CONTROL; + +/* + * OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL enum + */ + +typedef enum OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL { +DEBUG_BUS_SELECT_OPPBUF0 = 0x00000000, +DEBUG_BUS_SELECT_OPPBUF1 = 0x00000001, +DEBUG_BUS_SELECT_OPPBUF2 = 0x00000002, +DEBUG_BUS_SELECT_OPPBUF3 = 0x00000003, +DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 0x00000004, +DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 0x00000005, +} OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL; + +/* + * OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL enum + */ + +typedef enum OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL { +DEBUG_BUS_SELECT_OPP_PIPE0 = 0x00000000, +DEBUG_BUS_SELECT_OPP_PIPE1 = 0x00000001, +DEBUG_BUS_SELECT_OPP_PIPE2 = 0x00000002, +DEBUG_BUS_SELECT_OPP_PIPE3 = 0x00000003, +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 0x00000004, +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 0x00000005, +} OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL; + +/* + * OPP_TEST_CLK_SEL_CONTROL enum + */ + +typedef enum OPP_TEST_CLK_SEL_CONTROL { +OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000, +OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001, +OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002, +OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 0x00000003, +OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 0x00000004, +OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 0x00000005, +OPP_TEST_CLK_SEL_RESERVED0 = 0x00000006, +OPP_TEST_CLK_SEL_RESERVED1 = 0x00000007, +OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000008, +OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000009, +OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x0000000a, +OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x0000000b, +OPP_TEST_CLK_SEL_RESERVED2 = 0x0000000c, +OPP_TEST_CLK_SEL_RESERVED3 = 0x0000000d, +} OPP_TEST_CLK_SEL_CONTROL; + +/* + * OPP_TOP_CLOCK_ENABLE_STATUS enum + */ + +typedef enum OPP_TOP_CLOCK_ENABLE_STATUS { +OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000, +OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001, +} OPP_TOP_CLOCK_ENABLE_STATUS; + +/* + * OPP_TOP_CLOCK_GATING_CONTROL enum + */ + +typedef enum OPP_TOP_CLOCK_GATING_CONTROL { +OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000, +OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001, +} OPP_TOP_CLOCK_GATING_CONTROL; + +/******************************************************* + * DSCRM Enums + *******************************************************/ + +/* + * ENUM_DSCRM_EN enum + */ + +typedef enum ENUM_DSCRM_EN { +ENUM_DSCRM_DISABLE = 0x00000000, +ENUM_DSCRM_ENABLE = 0x00000001, +} ENUM_DSCRM_EN; + +/******************************************************* + * OTG Enums + *******************************************************/ + +/* + * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum + */ + +typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000, +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001, +} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; + +/* + * MASTER_UPDATE_LOCK_SEL enum + */ + +typedef enum MASTER_UPDATE_LOCK_SEL { +MASTER_UPDATE_LOCK_SEL_0 = 0x00000000, +MASTER_UPDATE_LOCK_SEL_1 = 0x00000001, +MASTER_UPDATE_LOCK_SEL_2 = 0x00000002, +MASTER_UPDATE_LOCK_SEL_3 = 0x00000003, +MASTER_UPDATE_LOCK_SEL_RESERVED4 = 0x00000004, +MASTER_UPDATE_LOCK_SEL_RESERVED5 = 0x00000005, +} MASTER_UPDATE_LOCK_SEL; + +/* + * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum + */ + +typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000, +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001, +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002, +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003, +} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; + +/* + * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum + */ + +typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN { +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000, +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001, +} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN; + +/* + * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum + */ + +typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB { +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000, +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001, +} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB; + +/* + * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum + */ + +typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR { +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000, +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001, +} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR; + +/* + * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum + */ + +typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE { +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000, +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001, +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002, +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003, +} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE; + +/* + * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum + */ + +typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL { +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000, +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001, +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 0x00000002, +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003, +} OTG_CONTROL_OTG_DISABLE_POINT_CNTL; + +/* + * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum + */ + +typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL { +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000, +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001, +} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL; + +/* + * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum + */ + +typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY { +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000, +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001, +} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY; + +/* + * OTG_CONTROL_OTG_MASTER_EN enum + */ + +typedef enum OTG_CONTROL_OTG_MASTER_EN { +OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000, +OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001, +} OTG_CONTROL_OTG_MASTER_EN; + +/* + * OTG_CONTROL_OTG_OUT_MUX enum + */ + +typedef enum OTG_CONTROL_OTG_OUT_MUX { +OTG_CONTROL_OTG_OUT_MUX_0 = 0x00000000, +OTG_CONTROL_OTG_OUT_MUX_1 = 0x00000001, +OTG_CONTROL_OTG_OUT_MUX_2 = 0x00000002, +} OTG_CONTROL_OTG_OUT_MUX; + +/* + * OTG_CONTROL_OTG_START_POINT_CNTL enum + */ + +typedef enum OTG_CONTROL_OTG_START_POINT_CNTL { +OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000, +OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001, +} OTG_CONTROL_OTG_START_POINT_CNTL; + +/* + * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum + */ + +typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN { +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000, +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001, +} OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN; + +/* + * OTG_CRC_CNTL_OTG_CRC1_EN enum + */ + +typedef enum OTG_CRC_CNTL_OTG_CRC1_EN { +OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0x00000000, +OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 0x00000001, +} OTG_CRC_CNTL_OTG_CRC1_EN; + +/* + * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum + */ + +typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN { +OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000, +OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001, +} OTG_CRC_CNTL_OTG_CRC_CONT_EN; + +/* + * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum + */ + +typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE { +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0x00000000, +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 0x00000001, +} OTG_CRC_CNTL_OTG_CRC_CONT_MODE; + +/* + * OTG_CRC_CNTL_OTG_CRC_EN enum + */ + +typedef enum OTG_CRC_CNTL_OTG_CRC_EN { +OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000, +OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001, +} OTG_CRC_CNTL_OTG_CRC_EN; + +/* + * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum + */ + +typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE { +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000, +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002, +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003, +} OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE; + +/* + * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum + */ + +typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE { +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000, +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001, +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002, +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003, +} OTG_CRC_CNTL_OTG_CRC_STEREO_MODE; + +/* + * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum + */ + +typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS { +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000, +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001, +} OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS; + +/* + * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum + */ + +typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT { +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000, +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001, +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002, +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003, +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004, +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005, +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006, +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007, +} OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT; + +/* + * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum + */ + +typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT { +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000, +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001, +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002, +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003, +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004, +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005, +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006, +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007, +} OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT; + +/* + * OTG_DIG_UPDATE_VCOUNT_MODE enum + */ + +typedef enum OTG_DIG_UPDATE_VCOUNT_MODE { +OTG_DIG_UPDATE_VCOUNT_0 = 0x00000000, +OTG_DIG_UPDATE_VCOUNT_1 = 0x00000001, +} OTG_DIG_UPDATE_VCOUNT_MODE; + +/* + * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum + */ + +typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE { +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000, +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001, +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002, +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003, +} OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE; + +/* + * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum + */ + +typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY { +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000, +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001, +} OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY; + +/* + * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum + */ + +typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME { +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000, +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001, +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002, +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003, +} OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME; + +/* + * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum + */ + +typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN { +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000, +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001, +} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN; + +/* + * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum + */ + +typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY { +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001, +} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY; + +/* + * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum + */ + +typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY { +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001, +} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY; + +/* + * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum + */ + +typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT { +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 0x0000000f, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012, +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013, +} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT; + +/* + * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum + */ + +typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK { +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000, +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001, +} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK; + +/* + * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum + */ + +typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR { +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000, +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001, +} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR; + +/* + * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum + */ + +typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE { +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000, +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001, +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002, +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003, +} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE; + +/* + * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum + */ + +typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL { +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000, +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001, +} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL; + +/* + * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum + */ + +typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL { +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000, +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001, +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002, +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003, +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 0x00000004, +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 0x00000005, +} OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL; + +/* + * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum + */ + +typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL { +DIG_UPDATE_EYE_SEL_BOTH = 0x00000000, +DIG_UPDATE_EYE_SEL_LEFT = 0x00000001, +DIG_UPDATE_EYE_SEL_RIGHT = 0x00000002, +} OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL; + +/* + * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum + */ + +typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL { +DIG_UPDATE_FIELD_SEL_BOTH = 0x00000000, +DIG_UPDATE_FIELD_SEL_TOP = 0x00000001, +DIG_UPDATE_FIELD_SEL_BOTTOM = 0x00000002, +DIG_UPDATE_FIELD_SEL_RESERVED = 0x00000003, +} OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL; + +/* + * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum + */ + +typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD { +MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000, +MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001, +MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 0x00000002, +MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000003, +} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD; + +/* + * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum + */ + +typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL { +MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000, +MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001, +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002, +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003, +} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL; + +/* + * OTG_GLOBAL_UPDATE_LOCK_EN enum + */ + +typedef enum OTG_GLOBAL_UPDATE_LOCK_EN { +OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0x00000000, +OTG_GLOBAL_UPDATE_LOCK_ENABLE = 0x00000001, +} OTG_GLOBAL_UPDATE_LOCK_EN; + +/* + * OTG_GSL_MASTER_MODE enum + */ + +typedef enum OTG_GSL_MASTER_MODE { +OTG_GSL_MASTER_MODE_0 = 0x00000000, +OTG_GSL_MASTER_MODE_1 = 0x00000001, +OTG_GSL_MASTER_MODE_2 = 0x00000002, +OTG_GSL_MASTER_MODE_3 = 0x00000003, +} OTG_GSL_MASTER_MODE; + +/* + * OTG_HORZ_REPETITION_COUNT enum + */ + +typedef enum OTG_HORZ_REPETITION_COUNT { +OTG_HORZ_REPETITION_COUNT_0 = 0x00000000, +OTG_HORZ_REPETITION_COUNT_1 = 0x00000001, +OTG_HORZ_REPETITION_COUNT_2 = 0x00000002, +OTG_HORZ_REPETITION_COUNT_3 = 0x00000003, +OTG_HORZ_REPETITION_COUNT_4 = 0x00000004, +OTG_HORZ_REPETITION_COUNT_5 = 0x00000005, +OTG_HORZ_REPETITION_COUNT_6 = 0x00000006, +OTG_HORZ_REPETITION_COUNT_7 = 0x00000007, +OTG_HORZ_REPETITION_COUNT_8 = 0x00000008, +OTG_HORZ_REPETITION_COUNT_9 = 0x00000009, +OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a, +OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b, +OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c, +OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d, +OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e, +OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f, +} OTG_HORZ_REPETITION_COUNT; + +/* + * OTG_H_SYNC_A_POL enum + */ + +typedef enum OTG_H_SYNC_A_POL { +OTG_H_SYNC_A_POL_HIGH = 0x00000000, +OTG_H_SYNC_A_POL_LOW = 0x00000001, +} OTG_H_SYNC_A_POL; + +/* + * OTG_H_TIMING_DIV_MODE enum + */ + +typedef enum OTG_H_TIMING_DIV_MODE { +OTG_H_TIMING_DIV_MODE_NO_DIV = 0x00000000, +OTG_H_TIMING_DIV_MODE_DIV_BY2 = 0x00000001, +OTG_H_TIMING_DIV_MODE_RESERVED = 0x00000002, +OTG_H_TIMING_DIV_MODE_DIV_BY4 = 0x00000003, +} OTG_H_TIMING_DIV_MODE; + +/* + * OTG_H_TIMING_DIV_MODE_MANUAL enum + */ + +typedef enum OTG_H_TIMING_DIV_MODE_MANUAL { +OTG_H_TIMING_DIV_MODE_AUTO = 0x00000000, +OTG_H_TIMING_DIV_MODE_NOAUTO = 0x00000001, +} OTG_H_TIMING_DIV_MODE_MANUAL; + +/* + * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum + */ + +typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE { +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000, +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001, +} OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE; + +/* + * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum + */ + +typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD { +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000, +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001, +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002, +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003, +} OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD; + +/* + * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK { +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK; + +/* + * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE { +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE; + +/* + * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK { +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK; + +/* + * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE { +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE; + +/* + * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK { +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK; + +/* + * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE { +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE; + +/* + * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK { +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK; + +/* + * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE { +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE; + +/* + * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK { +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK; + +/* + * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE { +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE; + +/* + * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK { +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK; + +/* + * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE { +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE; + +/* + * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK { +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK; + +/* + * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum + */ + +typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE { +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000, +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001, +} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE; + +/* + * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum + */ + +typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE { +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000, +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001, +} OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; + +/* + * OTG_MASTER_UPDATE_LOCK_DB_EN enum + */ + +typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN { +OTG_MASTER_UPDATE_LOCK_DISABLE = 0x00000000, +OTG_MASTER_UPDATE_LOCK_ENABLE = 0x00000001, +} OTG_MASTER_UPDATE_LOCK_DB_EN; + +/* + * OTG_MASTER_UPDATE_LOCK_GSL_EN enum + */ + +typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN { +OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000, +OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001, +} OTG_MASTER_UPDATE_LOCK_GSL_EN; + +/* + * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum + */ + +typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE { +OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0x00000000, +OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 0x00000001, +} OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE; + +/* + * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum + */ + +typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL { +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000, +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001, +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002, +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003, +} OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL; + +/* + * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum + */ + +typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR { +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000, +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001, +} OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR; + +/* + * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum + */ + +typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR { +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000, +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001, +} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR; + +/* + * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum + */ + +typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE { +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000, +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001, +} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE; + +/* + * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum + */ + +typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE { +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000, +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001, +} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE; + +/* + * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum + */ + +typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE { +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000, +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001, +} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE; + +/* + * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum + */ + +typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE { +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000, +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001, +} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE; + +/* + * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum + */ + +typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL { +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0x00000000, +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 0x00000001, +} OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL; + +/* + * OTG_STEREO_CONTROL_OTG_STEREO_EN enum + */ + +typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN { +OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000, +OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001, +} OTG_STEREO_CONTROL_OTG_STEREO_EN; + +/* + * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum + */ + +typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY { +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000, +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001, +} OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY; + +/* + * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum + */ + +typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY { +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000, +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001, +} OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY; + +/* + * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum + */ + +typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE { +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000, +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001, +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002, +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003, +} OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE; + +/* + * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum + */ + +typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR { +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000, +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001, +} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR; + +/* + * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum + */ + +typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT { +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000, +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001, +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002, +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003, +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004, +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005, +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006, +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007, +} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT; + +/* + * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum + */ + +typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN { +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000, +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001, +} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN; + +/* + * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum + */ + +typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT { +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005, +} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT; + +/* + * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum + */ + +typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT { +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 0x0000000e, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017, +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018, +} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT; + +/* + * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum + */ + +typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL { +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, +} OTG_TRIGA_FALLING_EDGE_DETECT_CNTL; + +/* + * OTG_TRIGA_FREQUENCY_SELECT enum + */ + +typedef enum OTG_TRIGA_FREQUENCY_SELECT { +OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000, +OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001, +OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002, +OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003, +} OTG_TRIGA_FREQUENCY_SELECT; + +/* + * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum + */ + +typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL { +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, +} OTG_TRIGA_RISING_EDGE_DETECT_CNTL; + +/* + * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum + */ + +typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR { +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000, +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001, +} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR; + +/* + * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum + */ + +typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT { +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000, +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001, +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002, +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003, +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004, +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005, +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006, +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007, +} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT; + +/* + * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum + */ + +typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN { +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000, +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001, +} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN; + +/* + * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum + */ + +typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT { +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005, +} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT; + +/* + * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum + */ + +typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT { +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 0x0000000e, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017, +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018, +} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT; + +/* + * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum + */ + +typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL { +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, +} OTG_TRIGB_FALLING_EDGE_DETECT_CNTL; + +/* + * OTG_TRIGB_FREQUENCY_SELECT enum + */ + +typedef enum OTG_TRIGB_FREQUENCY_SELECT { +OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000, +OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001, +OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002, +OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003, +} OTG_TRIGB_FREQUENCY_SELECT; + +/* + * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum + */ + +typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL { +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, +} OTG_TRIGB_RISING_EDGE_DETECT_CNTL; + +/* + * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum + */ + +typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK { +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000, +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001, +} OTG_UPDATE_LOCK_OTG_UPDATE_LOCK; + +/* + * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR { +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR; + +/* + * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE { +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE; + +/* + * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE { +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE; + +/* + * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; + +/* + * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR { +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR; + +/* + * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE { +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE; + +/* + * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE { +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE; + +/* + * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR { +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR; + +/* + * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE { +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE; + +/* + * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum + */ + +typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE { +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000, +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001, +} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE; + +/* + * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum + */ + +typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE { +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000, +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001, +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002, +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003, +} OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE; + +/* + * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum + */ + +typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR { +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000, +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001, +} OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR; + +/* + * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum + */ + +typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR { +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000, +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001, +} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR; + +/* + * OTG_VUPDATE_BLOCK_DISABLE enum + */ + +typedef enum OTG_VUPDATE_BLOCK_DISABLE { +OTG_VUPDATE_BLOCK_DISABLE_OFF = 0x00000000, +OTG_VUPDATE_BLOCK_DISABLE_ON = 0x00000001, +} OTG_VUPDATE_BLOCK_DISABLE; + +/* + * OTG_V_SYNC_A_POL enum + */ + +typedef enum OTG_V_SYNC_A_POL { +OTG_V_SYNC_A_POL_HIGH = 0x00000000, +OTG_V_SYNC_A_POL_LOW = 0x00000001, +} OTG_V_SYNC_A_POL; + +/* + * OTG_V_SYNC_MODE enum + */ + +typedef enum OTG_V_SYNC_MODE { +OTG_V_SYNC_MODE_HSYNC = 0x00000000, +OTG_V_SYNC_MODE_HBLANK = 0x00000001, +} OTG_V_SYNC_MODE; + +/* + * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum + */ + +typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD { +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000, +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001, +} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD; + +/* + * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum + */ + +typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT { +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000, +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001, +} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT; + +/* + * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum + */ + +typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC { +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000, +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001, +} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC; + +/* + * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum + */ + +typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL { +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000, +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001, +} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL; + +/* + * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum + */ + +typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL { +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000, +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001, +} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL; + +/* + * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum + */ + +typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK { +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0x00000000, +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 0x00000001, +} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK; + +/******************************************************* + * OPTC_MISC Enums + *******************************************************/ + +/* + * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum + */ + +typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL { +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0x00000000, +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 0x00000001, +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 0x00000002, +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 0x00000003, +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 0x00000004, +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 0x00000005, +} OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL; + +/******************************************************* + * DMCUB Enums + *******************************************************/ + +/* + * DC_DMCUB_INT_TYPE enum + */ + +typedef enum DC_DMCUB_INT_TYPE { +INT_LEVEL = 0x00000000, +INT_PULSE = 0x00000001, +} DC_DMCUB_INT_TYPE; + +/* + * DC_DMCUB_TIMER_WINDOW enum + */ + +typedef enum DC_DMCUB_TIMER_WINDOW { +BITS_31_0 = 0x00000000, +BITS_32_1 = 0x00000001, +BITS_33_2 = 0x00000002, +BITS_34_3 = 0x00000003, +BITS_35_4 = 0x00000004, +BITS_36_5 = 0x00000005, +BITS_37_6 = 0x00000006, +BITS_38_7 = 0x00000007, +} DC_DMCUB_TIMER_WINDOW; + +/******************************************************* + * RBBMIF Enums + *******************************************************/ + +/* + * INVALID_REG_ACCESS_TYPE enum + */ + +typedef enum INVALID_REG_ACCESS_TYPE { +REG_UNALLOCATED_ADDR_WRITE = 0x00000000, +REG_UNALLOCATED_ADDR_READ = 0x00000001, +REG_VIRTUAL_WRITE = 0x00000002, +REG_VIRTUAL_READ = 0x00000003, +REG_SECURE_VIOLATE_WRITE = 0x00000004, +REG_SECURE_VIOLATE_READ = 0x00000005, +} INVALID_REG_ACCESS_TYPE; + +/******************************************************* + * IHC Enums + *******************************************************/ + +/* + * DMU_DC_GPU_TIMER_READ_SELECT enum + */ + +typedef enum DMU_DC_GPU_TIMER_READ_SELECT { +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000, +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001, +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002, +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003, +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004, +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005, +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006, +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007, +RESERVED_8 = 0x00000008, +RESERVED_9 = 0x00000009, +RESERVED_10 = 0x0000000a, +RESERVED_11 = 0x0000000b, +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c, +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d, +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e, +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f, +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010, +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011, +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012, +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013, +RESERVED_20 = 0x00000014, +RESERVED_21 = 0x00000015, +RESERVED_22 = 0x00000016, +RESERVED_23 = 0x00000017, +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018, +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019, +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a, +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b, +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c, +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d, +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e, +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f, +RESERVED_32 = 0x00000020, +RESERVED_33 = 0x00000021, +RESERVED_34 = 0x00000022, +RESERVED_35 = 0x00000023, +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024, +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025, +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026, +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027, +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028, +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029, +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a, +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b, +RESERVED_44 = 0x0000002c, +RESERVED_45 = 0x0000002d, +RESERVED_46 = 0x0000002e, +RESERVED_47 = 0x0000002f, +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030, +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031, +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032, +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033, +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034, +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035, +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036, +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037, +RESERVED_56 = 0x00000038, +RESERVED_57 = 0x00000039, +RESERVED_58 = 0x0000003a, +RESERVED_59 = 0x0000003b, +RESERVED_60 = 0x0000003c, +RESERVED_61 = 0x0000003d, +RESERVED_62 = 0x0000003e, +RESERVED_63 = 0x0000003f, +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040, +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041, +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042, +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043, +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044, +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045, +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046, +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047, +RESERVED_72 = 0x00000048, +RESERVED_73 = 0x00000049, +RESERVED_74 = 0x0000004a, +RESERVED_75 = 0x0000004b, +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c, +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d, +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e, +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f, +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050, +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051, +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052, +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053, +RESERVED_84 = 0x00000054, +RESERVED_85 = 0x00000055, +RESERVED_86 = 0x00000056, +RESERVED_87 = 0x00000057, +RESERVED_88 = 0x00000058, +RESERVED_89 = 0x00000059, +RESERVED_90 = 0x0000005a, +RESERVED_91 = 0x0000005b, +} DMU_DC_GPU_TIMER_READ_SELECT; + +/* + * DMU_DC_GPU_TIMER_START_POSITION enum + */ + +typedef enum DMU_DC_GPU_TIMER_START_POSITION { +DMU_GPU_TIMER_START_0_END_27 = 0x00000000, +DMU_GPU_TIMER_START_1_END_28 = 0x00000001, +DMU_GPU_TIMER_START_2_END_29 = 0x00000002, +DMU_GPU_TIMER_START_3_END_30 = 0x00000003, +DMU_GPU_TIMER_START_4_END_31 = 0x00000004, +DMU_GPU_TIMER_START_6_END_33 = 0x00000005, +DMU_GPU_TIMER_START_8_END_35 = 0x00000006, +DMU_GPU_TIMER_START_10_END_37 = 0x00000007, +} DMU_DC_GPU_TIMER_START_POSITION; + +/* + * IHC_INTERRUPT_DEST enum + */ + +typedef enum IHC_INTERRUPT_DEST { +INTERRUPT_SENT_TO_IH = 0x00000000, +INTERRUPT_SENT_TO_DMCUB = 0x00000001, +} IHC_INTERRUPT_DEST; + +/* + * IHC_INTERRUPT_LINE_STATUS enum + */ + +typedef enum IHC_INTERRUPT_LINE_STATUS { +INTERRUPT_LINE_NOT_ASSERTED = 0x00000000, +INTERRUPT_LINE_ASSERTED = 0x00000001, +} IHC_INTERRUPT_LINE_STATUS; + +/******************************************************* + * DMU_MISC Enums + *******************************************************/ + +/* + * DC_SMU_INTERRUPT_ENABLE enum + */ + +typedef enum DC_SMU_INTERRUPT_ENABLE { +DISABLE_THE_INTERRUPT = 0x00000000, +ENABLE_THE_INTERRUPT = 0x00000001, +} DC_SMU_INTERRUPT_ENABLE; + +/* + * DMU_CLOCK_ON enum + */ + +typedef enum DMU_CLOCK_ON { +DMU_CLOCK_STATUS_ON = 0x00000000, +DMU_CLOCK_STATUS_OFF = 0x00000001, +} DMU_CLOCK_ON; + +/* + * SMU_INTR enum + */ + +typedef enum SMU_INTR { +SMU_MSG_INTR_NOOP = 0x00000000, +SET_SMU_MSG_INTR = 0x00000001, +} SMU_INTR; + +/******************************************************* + * DCCG Enums + *******************************************************/ + +/* + * ALLOW_SR_ON_TRANS_REQ enum + */ + +typedef enum ALLOW_SR_ON_TRANS_REQ { +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000, +ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001, +} ALLOW_SR_ON_TRANS_REQ; + +/* + * AMCLOCK_ENABLE enum + */ + +typedef enum AMCLOCK_ENABLE { +ENABLE_AMCLK0 = 0x00000000, +ENABLE_AMCLK1 = 0x00000001, +} AMCLOCK_ENABLE; + +/* + * CLEAR_SMU_INTR enum + */ + +typedef enum CLEAR_SMU_INTR { +SMU_INTR_STATUS_NOOP = 0x00000000, +SMU_INTR_STATUS_CLEAR = 0x00000001, +} CLEAR_SMU_INTR; + +/* + * CLOCK_BRANCH_SOFT_RESET enum + */ + +typedef enum CLOCK_BRANCH_SOFT_RESET { +CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000, +CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001, +} CLOCK_BRANCH_SOFT_RESET; + +/* + * DCCG_AUDIO_DTO0_SOURCE_SEL enum + */ + +typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000, +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001, +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002, +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003, +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000004, +} DCCG_AUDIO_DTO0_SOURCE_SEL; + +/* + * DCCG_AUDIO_DTO2_SOURCE_SEL enum + */ + +typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000, +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 0x00000001, +} DCCG_AUDIO_DTO2_SOURCE_SEL; + +/* + * DCCG_AUDIO_DTO_SEL enum + */ + +typedef enum DCCG_AUDIO_DTO_SEL { +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000, +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001, +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002, +DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 0x00000003, +} DCCG_AUDIO_DTO_SEL; + +/* + * DCCG_AUDIO_DTO_USE_512FBR_DTO enum + */ + +typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000, +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001, +} DCCG_AUDIO_DTO_USE_512FBR_DTO; + +/* + * DCCG_DBG_BLOCK_SEL enum + */ + +typedef enum DCCG_DBG_BLOCK_SEL { +DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000, +DCCG_DBG_BLOCK_SEL_PMON = 0x00000001, +DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002, +} DCCG_DBG_BLOCK_SEL; + +/* + * DCCG_DBG_EN enum + */ + +typedef enum DCCG_DBG_EN { +DCCG_DBG_EN_DISABLE = 0x00000000, +DCCG_DBG_EN_ENABLE = 0x00000001, +} DCCG_DBG_EN; + +/* + * DCCG_DEEP_COLOR_CNTL enum + */ + +typedef enum DCCG_DEEP_COLOR_CNTL { +DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000, +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001, +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002, +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003, +} DCCG_DEEP_COLOR_CNTL; + +/* + * DCCG_FIFO_ERRDET_OVR_EN enum + */ + +typedef enum DCCG_FIFO_ERRDET_OVR_EN { +DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000, +DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001, +} DCCG_FIFO_ERRDET_OVR_EN; + +/* + * DCCG_FIFO_ERRDET_RESET enum + */ + +typedef enum DCCG_FIFO_ERRDET_RESET { +DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000, +DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001, +} DCCG_FIFO_ERRDET_RESET; + +/* + * DCCG_FIFO_ERRDET_STATE enum + */ + +typedef enum DCCG_FIFO_ERRDET_STATE { +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000, +DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001, +} DCCG_FIFO_ERRDET_STATE; + +/* + * DCCG_PERF_MODE_HSYNC enum + */ + +typedef enum DCCG_PERF_MODE_HSYNC { +DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000, +DCCG_PERF_MODE_HSYNC_START = 0x00000001, +} DCCG_PERF_MODE_HSYNC; + +/* + * DCCG_PERF_MODE_VSYNC enum + */ + +typedef enum DCCG_PERF_MODE_VSYNC { +DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000, +DCCG_PERF_MODE_VSYNC_START = 0x00000001, +} DCCG_PERF_MODE_VSYNC; + +/* + * DCCG_PERF_OTG_SELECT enum + */ + +typedef enum DCCG_PERF_OTG_SELECT { +DCCG_PERF_SEL_OTG0 = 0x00000000, +DCCG_PERF_SEL_OTG1 = 0x00000001, +DCCG_PERF_SEL_OTG2 = 0x00000002, +DCCG_PERF_SEL_OTG3 = 0x00000003, +DCCG_PERF_SEL_RESERVED = 0x00000004, +} DCCG_PERF_OTG_SELECT; + +/* + * DCCG_PERF_RUN enum + */ + +typedef enum DCCG_PERF_RUN { +DCCG_PERF_RUN_NOOP = 0x00000000, +DCCG_PERF_RUN_START = 0x00000001, +} DCCG_PERF_RUN; + +/* + * DC_MEM_GLOBAL_PWR_REQ_DIS enum + */ + +typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000, +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001, +} DC_MEM_GLOBAL_PWR_REQ_DIS; + +/* + * DIO_FIFO_ERROR enum + */ + +typedef enum DIO_FIFO_ERROR { +DIO_FIFO_ERROR_00 = 0x00000000, +DIO_FIFO_ERROR_01 = 0x00000001, +DIO_FIFO_ERROR_10 = 0x00000002, +DIO_FIFO_ERROR_11 = 0x00000003, +} DIO_FIFO_ERROR; + +/* + * DISABLE_CLOCK_GATING enum + */ + +typedef enum DISABLE_CLOCK_GATING { +CLOCK_GATING_ENABLED = 0x00000000, +CLOCK_GATING_DISABLED = 0x00000001, +} DISABLE_CLOCK_GATING; + +/* + * DISABLE_CLOCK_GATING_IN_DCO enum + */ + +typedef enum DISABLE_CLOCK_GATING_IN_DCO { +CLOCK_GATING_ENABLED_IN_DCO = 0x00000000, +CLOCK_GATING_DISABLED_IN_DCO = 0x00000001, +} DISABLE_CLOCK_GATING_IN_DCO; + +/* + * DISPCLK_CHG_FWD_CORR_DISABLE enum + */ + +typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000, +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001, +} DISPCLK_CHG_FWD_CORR_DISABLE; + +/* + * DISPCLK_FREQ_RAMP_DONE enum + */ + +typedef enum DISPCLK_FREQ_RAMP_DONE { +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000, +DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001, +} DISPCLK_FREQ_RAMP_DONE; + +/* + * DPREFCLK_SRC_SEL enum + */ + +typedef enum DPREFCLK_SRC_SEL { +DPREFCLK_SRC_SEL_CK = 0x00000000, +DPREFCLK_SRC_SEL_P0PLL = 0x00000001, +DPREFCLK_SRC_SEL_P1PLL = 0x00000002, +DPREFCLK_SRC_SEL_P2PLL = 0x00000003, +} DPREFCLK_SRC_SEL; + +/* + * DP_DTO_DS_DISABLE enum + */ + +typedef enum DP_DTO_DS_DISABLE { +DP_DTO_DESPREAD_DISABLE = 0x00000000, +DP_DTO_DESPREAD_ENABLE = 0x00000001, +} DP_DTO_DS_DISABLE; + +/* + * DS_HW_CAL_ENABLE enum + */ + +typedef enum DS_HW_CAL_ENABLE { +DS_HW_CAL_DIS = 0x00000000, +DS_HW_CAL_EN = 0x00000001, +} DS_HW_CAL_ENABLE; + +/* + * DS_JITTER_COUNT_SRC_SEL enum + */ + +typedef enum DS_JITTER_COUNT_SRC_SEL { +DS_JITTER_COUNT_SRC_SEL0 = 0x00000000, +DS_JITTER_COUNT_SRC_SEL1 = 0x00000001, +} DS_JITTER_COUNT_SRC_SEL; + +/* + * DS_REF_SRC enum + */ + +typedef enum DS_REF_SRC { +DS_REF_IS_XTALIN = 0x00000000, +DS_REF_IS_EXT_GENLOCK = 0x00000001, +DS_REF_IS_PCIE = 0x00000002, +} DS_REF_SRC; + +/* + * DVOACLKC_IN_PHASE enum + */ + +typedef enum DVOACLKC_IN_PHASE { +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001, +} DVOACLKC_IN_PHASE; + +/* + * DVOACLKC_MVP_IN_PHASE enum + */ + +typedef enum DVOACLKC_MVP_IN_PHASE { +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001, +} DVOACLKC_MVP_IN_PHASE; + +/* + * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum + */ + +typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE { +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000, +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001, +} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; + +/* + * DVOACLKD_IN_PHASE enum + */ + +typedef enum DVOACLKD_IN_PHASE { +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001, +} DVOACLKD_IN_PHASE; + +/* + * DVOACLK_COARSE_SKEW_CNTL enum + */ + +typedef enum DVOACLK_COARSE_SKEW_CNTL { +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004, +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005, +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006, +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007, +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008, +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009, +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a, +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b, +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c, +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d, +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e, +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f, +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010, +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011, +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012, +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013, +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014, +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015, +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016, +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017, +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018, +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019, +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a, +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b, +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c, +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d, +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e, +} DVOACLK_COARSE_SKEW_CNTL; + +/* + * DVOACLK_FINE_SKEW_CNTL enum + */ + +typedef enum DVOACLK_FINE_SKEW_CNTL { +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004, +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005, +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006, +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007, +} DVOACLK_FINE_SKEW_CNTL; + +/* + * DVO_ENABLE_RST enum + */ + +typedef enum DVO_ENABLE_RST { +DVO_ENABLE_RST_DISABLE = 0x00000000, +DVO_ENABLE_RST_ENABLE = 0x00000001, +} DVO_ENABLE_RST; + +/* + * ENABLE enum + */ + +typedef enum ENABLE { +DISABLE_THE_FEATURE = 0x00000000, +ENABLE_THE_FEATURE = 0x00000001, +} ENABLE; + +/* + * ENABLE_CLOCK enum + */ + +typedef enum ENABLE_CLOCK { +ENABLE_THE_REFCLK = 0x00000000, +ENABLE_THE_FUNC_CLOCK = 0x00000001, +} ENABLE_CLOCK; + +/* + * FORCE_DISABLE_CLOCK enum + */ + +typedef enum FORCE_DISABLE_CLOCK { +NOT_FORCE_THE_CLOCK_DISABLED = 0x00000000, +FORCE_THE_CLOCK_DISABLED = 0x00000001, +} FORCE_DISABLE_CLOCK; + +/* + * HDMICHARCLK_SRC_SEL enum + */ + +typedef enum HDMICHARCLK_SRC_SEL { +HDMICHARCLK_SRC_SEL_UNIPHYA = 0x00000000, +HDMICHARCLK_SRC_SEL_UNIPHYB = 0x00000001, +HDMICHARCLK_SRC_SEL_UNIPHYC = 0x00000002, +HDMICHARCLK_SRC_SEL_UNIPHYD = 0x00000003, +HDMICHARCLK_SRC_SEL_UNIPHYE = 0x00000004, +HDMICHARCLK_SRC_SEL_SRC_RESERVED = 0x00000005, +} HDMICHARCLK_SRC_SEL; + +/* + * HDMISTREAMCLK_DTO_FORCE_DIS enum + */ + +typedef enum HDMISTREAMCLK_DTO_FORCE_DIS { +DTO_FORCE_NO_BYPASS = 0x00000000, +DTO_FORCE_BYPASS = 0x00000001, +} HDMISTREAMCLK_DTO_FORCE_DIS; + +/* + * HDMISTREAMCLK_SRC_SEL enum + */ + +typedef enum HDMISTREAMCLK_SRC_SEL { +SEL_REFCLK0 = 0x00000000, +SEL_DTBCLK0 = 0x00000001, +SEL_DTBCLK1 = 0x00000002, +} HDMISTREAMCLK_SRC_SEL; + +/* + * JITTER_REMOVE_DISABLE enum + */ + +typedef enum JITTER_REMOVE_DISABLE { +ENABLE_JITTER_REMOVAL = 0x00000000, +DISABLE_JITTER_REMOVAL = 0x00000001, +} JITTER_REMOVE_DISABLE; + +/* + * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum + */ + +typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, +MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, +} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; + +/* + * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum + */ + +typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, +MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, +} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; + +/* + * OTG_ADD_PIXEL enum + */ + +typedef enum OTG_ADD_PIXEL { +OTG_ADD_PIXEL_NOOP = 0x00000000, +OTG_ADD_PIXEL_FORCE = 0x00000001, +} OTG_ADD_PIXEL; + +/* + * OTG_DROP_PIXEL enum + */ + +typedef enum OTG_DROP_PIXEL { +OTG_DROP_PIXEL_NOOP = 0x00000000, +OTG_DROP_PIXEL_FORCE = 0x00000001, +} OTG_DROP_PIXEL; + +/* + * PHYSYMCLK_FORCE_EN enum + */ + +typedef enum PHYSYMCLK_FORCE_EN { +PHYSYMCLK_FORCE_EN_DISABLE = 0x00000000, +PHYSYMCLK_FORCE_EN_ENABLE = 0x00000001, +} PHYSYMCLK_FORCE_EN; + +/* + * PHYSYMCLK_FORCE_SRC_SEL enum + */ + +typedef enum PHYSYMCLK_FORCE_SRC_SEL { +PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000, +PHYSYMCLK_FORCE_SRC_PHYD18CLK = 0x00000001, +PHYSYMCLK_FORCE_SRC_PHYD32CLK = 0x00000002, +} PHYSYMCLK_FORCE_SRC_SEL; + +/* + * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum + */ + +typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000004, +} PIPE_PHYPLL_PIXEL_RATE_SOURCE; + +/* + * PIPE_PIXEL_RATE_PLL_SOURCE enum + */ + +typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000, +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001, +} PIPE_PIXEL_RATE_PLL_SOURCE; + +/* + * PIPE_PIXEL_RATE_SOURCE enum + */ + +typedef enum PIPE_PIXEL_RATE_SOURCE { +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000, +PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001, +PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002, +} PIPE_PIXEL_RATE_SOURCE; + +/* + * PLL_CFG_IF_SOFT_RESET enum + */ + +typedef enum PLL_CFG_IF_SOFT_RESET { +PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000, +PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001, +} PLL_CFG_IF_SOFT_RESET; + +/* + * SYMCLK_FE_FORCE_EN enum + */ + +typedef enum SYMCLK_FE_FORCE_EN { +SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000, +SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001, +} SYMCLK_FE_FORCE_EN; + +/* + * SYMCLK_FE_FORCE_SRC enum + */ + +typedef enum SYMCLK_FE_FORCE_SRC { +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000, +SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001, +SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002, +SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003, +SYMCLK_FE_FORCE_SRC_RESERVED = 0x00000004, +} SYMCLK_FE_FORCE_SRC; + +/* + * TEST_CLK_DIV_SEL enum + */ + +typedef enum TEST_CLK_DIV_SEL { +NO_DIV = 0x00000000, +DIV_2 = 0x00000001, +DIV_4 = 0x00000002, +DIV_8 = 0x00000003, +} TEST_CLK_DIV_SEL; + +/* + * VSYNC_CNT_LATCH_MASK enum + */ + +typedef enum VSYNC_CNT_LATCH_MASK { +VSYNC_CNT_LATCH_MASK_0 = 0x00000000, +VSYNC_CNT_LATCH_MASK_1 = 0x00000001, +} VSYNC_CNT_LATCH_MASK; + +/* + * VSYNC_CNT_RESET_SEL enum + */ + +typedef enum VSYNC_CNT_RESET_SEL { +VSYNC_CNT_RESET_SEL_0 = 0x00000000, +VSYNC_CNT_RESET_SEL_1 = 0x00000001, +} VSYNC_CNT_RESET_SEL; + +/* + * XTAL_REF_CLOCK_SOURCE_SEL enum + */ + +typedef enum XTAL_REF_CLOCK_SOURCE_SEL { +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000, +XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001, +} XTAL_REF_CLOCK_SOURCE_SEL; + +/* + * XTAL_REF_SEL enum + */ + +typedef enum XTAL_REF_SEL { +XTAL_REF_SEL_1X = 0x00000000, +XTAL_REF_SEL_2X = 0x00000001, +} XTAL_REF_SEL; + +/******************************************************* + * HPD Enums + *******************************************************/ + +/* + * HPD_INT_CONTROL_ACK enum + */ + +typedef enum HPD_INT_CONTROL_ACK { +HPD_INT_CONTROL_ACK_0 = 0x00000000, +HPD_INT_CONTROL_ACK_1 = 0x00000001, +} HPD_INT_CONTROL_ACK; + +/* + * HPD_INT_CONTROL_POLARITY enum + */ + +typedef enum HPD_INT_CONTROL_POLARITY { +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000, +HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001, +} HPD_INT_CONTROL_POLARITY; + +/* + * HPD_INT_CONTROL_RX_INT_ACK enum + */ + +typedef enum HPD_INT_CONTROL_RX_INT_ACK { +HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000, +HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001, +} HPD_INT_CONTROL_RX_INT_ACK; + +/******************************************************* + * DP Enums + *******************************************************/ + +/* + * DPHY_8B10B_CUR_DISP enum + */ + +typedef enum DPHY_8B10B_CUR_DISP { +DPHY_8B10B_CUR_DISP_ZERO = 0x00000000, +DPHY_8B10B_CUR_DISP_ONE = 0x00000001, +} DPHY_8B10B_CUR_DISP; + +/* + * DPHY_8B10B_RESET enum + */ + +typedef enum DPHY_8B10B_RESET { +DPHY_8B10B_NOT_RESET = 0x00000000, +DPHY_8B10B_RESETET = 0x00000001, +} DPHY_8B10B_RESET; + +/* + * DPHY_ALT_SCRAMBLER_RESET_EN enum + */ + +typedef enum DPHY_ALT_SCRAMBLER_RESET_EN { +DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000, +DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001, +} DPHY_ALT_SCRAMBLER_RESET_EN; + +/* + * DPHY_ALT_SCRAMBLER_RESET_SEL enum + */ + +typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL { +DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000, +DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001, +} DPHY_ALT_SCRAMBLER_RESET_SEL; + +/* + * DPHY_ATEST_SEL_LANE0 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE0 { +DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE0; + +/* + * DPHY_ATEST_SEL_LANE1 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE1 { +DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE1; + +/* + * DPHY_ATEST_SEL_LANE2 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE2 { +DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE2; + +/* + * DPHY_ATEST_SEL_LANE3 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE3 { +DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE3; + +/* + * DPHY_BYPASS enum + */ + +typedef enum DPHY_BYPASS { +DPHY_8B10B_OUTPUT = 0x00000000, +DPHY_DBG_OUTPUT = 0x00000001, +} DPHY_BYPASS; + +/* + * DPHY_CRC_CONT_EN enum + */ + +typedef enum DPHY_CRC_CONT_EN { +DPHY_CRC_ONE_SHOT = 0x00000000, +DPHY_CRC_CONTINUOUS = 0x00000001, +} DPHY_CRC_CONT_EN; + +/* + * DPHY_CRC_EN enum + */ + +typedef enum DPHY_CRC_EN { +DPHY_CRC_DISABLED = 0x00000000, +DPHY_CRC_ENABLED = 0x00000001, +} DPHY_CRC_EN; + +/* + * DPHY_CRC_FIELD enum + */ + +typedef enum DPHY_CRC_FIELD { +DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000, +DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001, +} DPHY_CRC_FIELD; + +/* + * DPHY_CRC_MST_PHASE_ERROR_ACK enum + */ + +typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000, +DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001, +} DPHY_CRC_MST_PHASE_ERROR_ACK; + +/* + * DPHY_CRC_SEL enum + */ + +typedef enum DPHY_CRC_SEL { +DPHY_CRC_LANE0_SELECTED = 0x00000000, +DPHY_CRC_LANE1_SELECTED = 0x00000001, +DPHY_CRC_LANE2_SELECTED = 0x00000002, +DPHY_CRC_LANE3_SELECTED = 0x00000003, +} DPHY_CRC_SEL; + +/* + * DPHY_FEC_ENABLE enum + */ + +typedef enum DPHY_FEC_ENABLE { +DPHY_FEC_DISABLED = 0x00000000, +DPHY_FEC_ENABLED = 0x00000001, +} DPHY_FEC_ENABLE; + +/* + * DPHY_FEC_READY enum + */ + +typedef enum DPHY_FEC_READY { +DPHY_FEC_READY_EN = 0x00000000, +DPHY_FEC_READY_DIS = 0x00000001, +} DPHY_FEC_READY; + +/* + * DPHY_LOAD_BS_COUNT_START enum + */ + +typedef enum DPHY_LOAD_BS_COUNT_START { +DPHY_LOAD_BS_COUNT_STARTED = 0x00000000, +DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001, +} DPHY_LOAD_BS_COUNT_START; + +/* + * DPHY_PRBS_EN enum + */ + +typedef enum DPHY_PRBS_EN { +DPHY_PRBS_DISABLE = 0x00000000, +DPHY_PRBS_ENABLE = 0x00000001, +} DPHY_PRBS_EN; + +/* + * DPHY_PRBS_SEL enum + */ + +typedef enum DPHY_PRBS_SEL { +DPHY_PRBS7_SELECTED = 0x00000000, +DPHY_PRBS23_SELECTED = 0x00000001, +DPHY_PRBS11_SELECTED = 0x00000002, +} DPHY_PRBS_SEL; + +/* + * DPHY_RX_FAST_TRAINING_CAPABLE enum + */ + +typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000, +DPHY_FAST_TRAINING_CAPABLE = 0x00000001, +} DPHY_RX_FAST_TRAINING_CAPABLE; + +/* + * DPHY_SCRAMBLER_ADVANCE enum + */ + +typedef enum DPHY_SCRAMBLER_ADVANCE { +DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000, +DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001, +} DPHY_SCRAMBLER_ADVANCE; + +/* + * DPHY_SCRAMBLER_DIS enum + */ + +typedef enum DPHY_SCRAMBLER_DIS { +DPHY_SCR_ENABLED = 0x00000000, +DPHY_SCR_DISABLED = 0x00000001, +} DPHY_SCRAMBLER_DIS; + +/* + * DPHY_SCRAMBLER_KCODE enum + */ + +typedef enum DPHY_SCRAMBLER_KCODE { +DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000, +DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001, +} DPHY_SCRAMBLER_KCODE; + +/* + * DPHY_SCRAMBLER_SEL enum + */ + +typedef enum DPHY_SCRAMBLER_SEL { +DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000, +DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001, +} DPHY_SCRAMBLER_SEL; + +/* + * DPHY_SKEW_BYPASS enum + */ + +typedef enum DPHY_SKEW_BYPASS { +DPHY_WITH_SKEW = 0x00000000, +DPHY_NO_SKEW = 0x00000001, +} DPHY_SKEW_BYPASS; + +/* + * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum + */ + +typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM { +DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0x00000000, +DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 0x00000001, +} DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM; + +/* + * DPHY_SW_FAST_TRAINING_START enum + */ + +typedef enum DPHY_SW_FAST_TRAINING_START { +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000, +DPHY_SW_FAST_TRAINING_STARTED = 0x00000001, +} DPHY_SW_FAST_TRAINING_START; + +/* + * DPHY_TRAINING_PATTERN_SEL enum + */ + +typedef enum DPHY_TRAINING_PATTERN_SEL { +DPHY_TRAINING_PATTERN_1 = 0x00000000, +DPHY_TRAINING_PATTERN_2 = 0x00000001, +DPHY_TRAINING_PATTERN_3 = 0x00000002, +DPHY_TRAINING_PATTERN_4 = 0x00000003, +} DPHY_TRAINING_PATTERN_SEL; + +/* + * DP_COMPONENT_DEPTH enum + */ + +typedef enum DP_COMPONENT_DEPTH { +DP_COMPONENT_DEPTH_6BPC = 0x00000000, +DP_COMPONENT_DEPTH_8BPC = 0x00000001, +DP_COMPONENT_DEPTH_10BPC = 0x00000002, +DP_COMPONENT_DEPTH_12BPC = 0x00000003, +DP_COMPONENT_DEPTH_16BPC = 0x00000004, +} DP_COMPONENT_DEPTH; + +/* + * DP_CP_ENCRYPTION_TYPE enum + */ + +typedef enum DP_CP_ENCRYPTION_TYPE { +DP_CP_ENCRYPTION_TYPE_0 = 0x00000000, +DP_CP_ENCRYPTION_TYPE_1 = 0x00000001, +} DP_CP_ENCRYPTION_TYPE; + +/* + * DP_DPHY_8B10B_EXT_DISP enum + */ + +typedef enum DP_DPHY_8B10B_EXT_DISP { +DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000, +DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001, +} DP_DPHY_8B10B_EXT_DISP; + +/* + * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum + */ + +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000, +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001, +} DP_DPHY_FAST_TRAINING_COMPLETE_ACK; + +/* + * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum + */ + +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000, +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001, +} DP_DPHY_FAST_TRAINING_COMPLETE_MASK; + +/* + * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum + */ + +typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000, +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001, +} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; + +/* + * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum + */ + +typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { +DP_DPHY_HBR2_PASS_THROUGH = 0x00000000, +DP_DPHY_HBR2_PATTERN_1 = 0x00000001, +DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002, +DP_DPHY_HBR2_PATTERN_3 = 0x00000003, +DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006, +} DP_DPHY_HBR2_PATTERN_CONTROL_MODE; + +/* + * DP_DSC_MODE enum + */ + +typedef enum DP_DSC_MODE { +DP_DSC_DISABLE = 0x00000000, +DP_DSC_444_SIMPLE_422 = 0x00000001, +DP_DSC_NATIVE_422_420 = 0x00000002, +} DP_DSC_MODE; + +/* + * DP_EMBEDDED_PANEL_MODE enum + */ + +typedef enum DP_EMBEDDED_PANEL_MODE { +DP_EXTERNAL_PANEL = 0x00000000, +DP_EMBEDDED_PANEL = 0x00000001, +} DP_EMBEDDED_PANEL_MODE; + +/* + * DP_LINK_TRAINING_COMPLETE enum + */ + +typedef enum DP_LINK_TRAINING_COMPLETE { +DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000, +DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001, +} DP_LINK_TRAINING_COMPLETE; + +/* + * DP_LINK_TRAINING_SWITCH_MODE enum + */ + +typedef enum DP_LINK_TRAINING_SWITCH_MODE { +DP_LINK_TRAINING_SWITCH_TO_IDLE = 0x00000000, +DP_LINK_TRAINING_SWITCH_TO_VIDEO = 0x00000001, +} DP_LINK_TRAINING_SWITCH_MODE; + +/* + * DP_ML_PHY_SEQ_MODE enum + */ + +typedef enum DP_ML_PHY_SEQ_MODE { +DP_ML_PHY_SEQ_LINE_NUM = 0x00000000, +DP_ML_PHY_SEQ_IMMEDIATE = 0x00000001, +} DP_ML_PHY_SEQ_MODE; + +/* + * DP_MSA_V_TIMING_OVERRIDE_EN enum + */ + +typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { +MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000, +MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001, +} DP_MSA_V_TIMING_OVERRIDE_EN; + +/* + * DP_MSE_BLANK_CODE enum + */ + +typedef enum DP_MSE_BLANK_CODE { +DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000, +DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001, +} DP_MSE_BLANK_CODE; + +/* + * DP_MSE_LINK_LINE enum + */ + +typedef enum DP_MSE_LINK_LINE { +DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000, +DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001, +DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002, +DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003, +} DP_MSE_LINK_LINE; + +/* + * DP_MSE_SAT_ENCRYPT0 enum + */ + +typedef enum DP_MSE_SAT_ENCRYPT0 { +DP_MSE_SAT_ENCRYPT0_DISABLED = 0x00000000, +DP_MSE_SAT_ENCRYPT0_ENABLED = 0x00000001, +} DP_MSE_SAT_ENCRYPT0; + +/* + * DP_MSE_SAT_ENCRYPT1 enum + */ + +typedef enum DP_MSE_SAT_ENCRYPT1 { +DP_MSE_SAT_ENCRYPT1_DISABLED = 0x00000000, +DP_MSE_SAT_ENCRYPT1_ENABLED = 0x00000001, +} DP_MSE_SAT_ENCRYPT1; + +/* + * DP_MSE_SAT_ENCRYPT2 enum + */ + +typedef enum DP_MSE_SAT_ENCRYPT2 { +DP_MSE_SAT_ENCRYPT2_DISABLED = 0x00000000, +DP_MSE_SAT_ENCRYPT2_ENABLED = 0x00000001, +} DP_MSE_SAT_ENCRYPT2; + +/* + * DP_MSE_SAT_ENCRYPT3 enum + */ + +typedef enum DP_MSE_SAT_ENCRYPT3 { +DP_MSE_SAT_ENCRYPT3_DISABLED = 0x00000000, +DP_MSE_SAT_ENCRYPT3_ENABLED = 0x00000001, +} DP_MSE_SAT_ENCRYPT3; + +/* + * DP_MSE_SAT_ENCRYPT4 enum + */ + +typedef enum DP_MSE_SAT_ENCRYPT4 { +DP_MSE_SAT_ENCRYPT4_DISABLED = 0x00000000, +DP_MSE_SAT_ENCRYPT4_ENABLED = 0x00000001, +} DP_MSE_SAT_ENCRYPT4; + +/* + * DP_MSE_SAT_ENCRYPT5 enum + */ + +typedef enum DP_MSE_SAT_ENCRYPT5 { +DP_MSE_SAT_ENCRYPT5_DISABLED = 0x00000000, +DP_MSE_SAT_ENCRYPT5_ENABLED = 0x00000001, +} DP_MSE_SAT_ENCRYPT5; + +/* + * DP_MSE_SAT_UPDATE_ACT enum + */ + +typedef enum DP_MSE_SAT_UPDATE_ACT { +DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000, +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001, +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002, +} DP_MSE_SAT_UPDATE_ACT; + +/* + * DP_MSE_TIMESTAMP_MODE enum + */ + +typedef enum DP_MSE_TIMESTAMP_MODE { +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000, +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001, +} DP_MSE_TIMESTAMP_MODE; + +/* + * DP_MSE_ZERO_ENCODER enum + */ + +typedef enum DP_MSE_ZERO_ENCODER { +DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000, +DP_MSE_ZERO_FE_ENCODER = 0x00000001, +} DP_MSE_ZERO_ENCODER; + +/* + * DP_MSO_NUM_OF_SST_LINKS enum + */ + +typedef enum DP_MSO_NUM_OF_SST_LINKS { +DP_MSO_ONE_SSTLINK = 0x00000000, +DP_MSO_TWO_SSTLINK = 0x00000001, +DP_MSO_FOUR_SSTLINK = 0x00000002, +} DP_MSO_NUM_OF_SST_LINKS; + +/* + * DP_PIXEL_ENCODING enum + */ + +typedef enum DP_PIXEL_ENCODING { +DP_PIXEL_ENCODING_RGB444 = 0x00000000, +DP_PIXEL_ENCODING_YCBCR422 = 0x00000001, +DP_PIXEL_ENCODING_YCBCR444 = 0x00000002, +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003, +DP_PIXEL_ENCODING_Y_ONLY = 0x00000004, +DP_PIXEL_ENCODING_YCBCR420 = 0x00000005, +} DP_PIXEL_ENCODING; + +/* + * DP_PIXEL_PER_CYCLE_PROCESSING_NUM enum + */ + +typedef enum DP_PIXEL_PER_CYCLE_PROCESSING_NUM { +DP_ONE_PIXEL_PER_CYCLE = 0x00000000, +DP_TWO_PIXEL_PER_CYCLE = 0x00000001, +} DP_PIXEL_PER_CYCLE_PROCESSING_NUM; + +/* + * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum + */ + +typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, +} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; + +/* + * DP_SEC_ASP_PRIORITY enum + */ + +typedef enum DP_SEC_ASP_PRIORITY { +DP_SEC_ASP_LOW_PRIORITY = 0x00000000, +DP_SEC_ASP_HIGH_PRIORITY = 0x00000001, +} DP_SEC_ASP_PRIORITY; + +/* + * DP_SEC_AUDIO_MUTE enum + */ + +typedef enum DP_SEC_AUDIO_MUTE { +DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000, +DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001, +} DP_SEC_AUDIO_MUTE; + +/* + * DP_SEC_COLLISION_ACK enum + */ + +typedef enum DP_SEC_COLLISION_ACK { +DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000, +DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001, +} DP_SEC_COLLISION_ACK; + +/* + * DP_SEC_GSP0_PRIORITY enum + */ + +typedef enum DP_SEC_GSP0_PRIORITY { +SEC_GSP0_PRIORITY_LOW = 0x00000000, +SEC_GSP0_PRIORITY_HIGH = 0x00000001, +} DP_SEC_GSP0_PRIORITY; + +/* + * DP_SEC_GSP_SEND enum + */ + +typedef enum DP_SEC_GSP_SEND { +NOT_SENT = 0x00000000, +FORCE_SENT = 0x00000001, +} DP_SEC_GSP_SEND; + +/* + * DP_SEC_GSP_SEND_ANY_LINE enum + */ + +typedef enum DP_SEC_GSP_SEND_ANY_LINE { +SEND_AT_LINK_NUMBER = 0x00000000, +SEND_AT_EARLIEST_TIME = 0x00000001, +} DP_SEC_GSP_SEND_ANY_LINE; + +/* + * DP_SEC_GSP_SEND_PPS enum + */ + +typedef enum DP_SEC_GSP_SEND_PPS { +SEND_NORMAL_PACKET = 0x00000000, +SEND_PPS_PACKET = 0x00000001, +} DP_SEC_GSP_SEND_PPS; + +/* + * DP_SEC_LINE_REFERENCE enum + */ + +typedef enum DP_SEC_LINE_REFERENCE { +REFER_TO_DP_SOF = 0x00000000, +REFER_TO_OTG_SOF = 0x00000001, +} DP_SEC_LINE_REFERENCE; + +/* + * DP_SEC_TIMESTAMP_MODE enum + */ + +typedef enum DP_SEC_TIMESTAMP_MODE { +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000, +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001, +} DP_SEC_TIMESTAMP_MODE; + +/* + * DP_STEER_OVERFLOW_ACK enum + */ + +typedef enum DP_STEER_OVERFLOW_ACK { +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000, +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, +} DP_STEER_OVERFLOW_ACK; + +/* + * DP_STEER_OVERFLOW_MASK enum + */ + +typedef enum DP_STEER_OVERFLOW_MASK { +DP_STEER_OVERFLOW_MASKED = 0x00000000, +DP_STEER_OVERFLOW_UNMASK = 0x00000001, +} DP_STEER_OVERFLOW_MASK; + +/* + * DP_SYNC_POLARITY enum + */ + +typedef enum DP_SYNC_POLARITY { +DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000, +DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001, +} DP_SYNC_POLARITY; + +/* + * DP_TU_OVERFLOW_ACK enum + */ + +typedef enum DP_TU_OVERFLOW_ACK { +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000, +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, +} DP_TU_OVERFLOW_ACK; + +/* + * DP_UDI_LANES enum + */ + +typedef enum DP_UDI_LANES { +DP_UDI_1_LANE = 0x00000000, +DP_UDI_2_LANES = 0x00000001, +DP_UDI_LANES_RESERVED = 0x00000002, +DP_UDI_4_LANES = 0x00000003, +} DP_UDI_LANES; + +/* + * DP_VID_ENHANCED_FRAME_MODE enum + */ + +typedef enum DP_VID_ENHANCED_FRAME_MODE { +VID_NORMAL_FRAME_MODE = 0x00000000, +VID_ENHANCED_MODE = 0x00000001, +} DP_VID_ENHANCED_FRAME_MODE; + +/* + * DP_VID_M_N_DOUBLE_BUFFER_MODE enum + */ + +typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000, +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001, +} DP_VID_M_N_DOUBLE_BUFFER_MODE; + +/* + * DP_VID_M_N_GEN_EN enum + */ + +typedef enum DP_VID_M_N_GEN_EN { +DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000, +DP_VID_M_N_CALC_AUTO = 0x00000001, +} DP_VID_M_N_GEN_EN; + +/* + * DP_VID_N_MUL enum + */ + +typedef enum DP_VID_N_MUL { +DP_VID_M_1X_INPUT_PIXEL_RATE = 0x00000000, +DP_VID_M_2X_INPUT_PIXEL_RATE = 0x00000001, +DP_VID_M_4X_INPUT_PIXEL_RATE = 0x00000002, +DP_VID_M_8X_INPUT_PIXEL_RATE = 0x00000003, +} DP_VID_N_MUL; + +/* + * DP_VID_STREAM_DISABLE_ACK enum + */ + +typedef enum DP_VID_STREAM_DISABLE_ACK { +ID_STREAM_DISABLE_NO_ACK = 0x00000000, +ID_STREAM_DISABLE_ACKED = 0x00000001, +} DP_VID_STREAM_DISABLE_ACK; + +/* + * DP_VID_STREAM_DISABLE_MASK enum + */ + +typedef enum DP_VID_STREAM_DISABLE_MASK { +VID_STREAM_DISABLE_MASKED = 0x00000000, +VID_STREAM_DISABLE_UNMASK = 0x00000001, +} DP_VID_STREAM_DISABLE_MASK; + +/* + * DP_VID_STREAM_DIS_DEFER enum + */ + +typedef enum DP_VID_STREAM_DIS_DEFER { +DP_VID_STREAM_DIS_NO_DEFER = 0x00000000, +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001, +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002, +} DP_VID_STREAM_DIS_DEFER; + +/* + * DP_VID_VBID_FIELD_POL enum + */ + +typedef enum DP_VID_VBID_FIELD_POL { +DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000, +DP_VID_VBID_FIELD_POL_INV = 0x00000001, +} DP_VID_VBID_FIELD_POL; + +/* + * FEC_ACTIVE_STATUS enum + */ + +typedef enum FEC_ACTIVE_STATUS { +DPHY_FEC_NOT_ACTIVE = 0x00000000, +DPHY_FEC_ACTIVE = 0x00000001, +} FEC_ACTIVE_STATUS; + +/******************************************************* + * DIG Enums + *******************************************************/ + +/* + * DIG_BE_CNTL_HPD_SELECT enum + */ + +typedef enum DIG_BE_CNTL_HPD_SELECT { +DIG_BE_CNTL_HPD1 = 0x00000000, +DIG_BE_CNTL_HPD2 = 0x00000001, +DIG_BE_CNTL_HPD3 = 0x00000002, +DIG_BE_CNTL_HPD4 = 0x00000003, +DIG_BE_CNTL_HPD5 = 0x00000004, +DIG_BE_CNTL_NO_HPD = 0x00000005, +} DIG_BE_CNTL_HPD_SELECT; + +/* + * DIG_BE_CNTL_MODE enum + */ + +typedef enum DIG_BE_CNTL_MODE { +DIG_BE_DP_SST_MODE = 0x00000000, +DIG_BE_RESERVED1 = 0x00000001, +DIG_BE_TMDS_DVI_MODE = 0x00000002, +DIG_BE_TMDS_HDMI_MODE = 0x00000003, +DIG_BE_RESERVED4 = 0x00000004, +DIG_BE_DP_MST_MODE = 0x00000005, +DIG_BE_RESERVED2 = 0x00000006, +DIG_BE_RESERVED3 = 0x00000007, +} DIG_BE_CNTL_MODE; + +/* + * DIG_DIGITAL_BYPASS_ENABLE enum + */ + +typedef enum DIG_DIGITAL_BYPASS_ENABLE { +DIG_DIGITAL_BYPASS_OFF = 0x00000000, +DIG_DIGITAL_BYPASS_ON = 0x00000001, +} DIG_DIGITAL_BYPASS_ENABLE; + +/* + * DIG_DIGITAL_BYPASS_SEL enum + */ + +typedef enum DIG_DIGITAL_BYPASS_SEL { +DIG_DIGITAL_BYPASS_SEL_BYPASS = 0x00000000, +DIG_DIGITAL_BYPASS_SEL_36BPP = 0x00000001, +DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 0x00000002, +DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 0x00000003, +DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 0x00000004, +DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 0x00000005, +DIG_DIGITAL_BYPASS_SEL_ALPHA = 0x00000006, +} DIG_DIGITAL_BYPASS_SEL; + +/* + * DIG_FE_CNTL_SOURCE_SELECT enum + */ + +typedef enum DIG_FE_CNTL_SOURCE_SELECT { +DIG_FE_SOURCE_FROM_OTG0 = 0x00000000, +DIG_FE_SOURCE_FROM_OTG1 = 0x00000001, +DIG_FE_SOURCE_FROM_OTG2 = 0x00000002, +DIG_FE_SOURCE_FROM_OTG3 = 0x00000003, +DIG_FE_SOURCE_RESERVED = 0x00000004, +} DIG_FE_CNTL_SOURCE_SELECT; + +/* + * DIG_FE_CNTL_STEREOSYNC_SELECT enum + */ + +typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { +DIG_FE_STEREOSYNC_FROM_OTG0 = 0x00000000, +DIG_FE_STEREOSYNC_FROM_OTG1 = 0x00000001, +DIG_FE_STEREOSYNC_FROM_OTG2 = 0x00000002, +DIG_FE_STEREOSYNC_FROM_OTG3 = 0x00000003, +DIG_FE_STEREOSYNC_RESERVED = 0x00000004, +} DIG_FE_CNTL_STEREOSYNC_SELECT; + +/* + * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum + */ + +typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX { +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000, +DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001, +} DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX; + +/* + * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum + */ + +typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL { +DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000, +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001, +} DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL; + +/* + * DIG_FIFO_FORCE_RECAL_AVERAGE enum + */ + +typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE { +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000, +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001, +} DIG_FIFO_FORCE_RECAL_AVERAGE; + +/* + * DIG_FIFO_OUTPUT_PROCESSING_MODE enum + */ + +typedef enum DIG_FIFO_OUTPUT_PROCESSING_MODE { +DIG_FIFO_1_PIX_PER_CYCLE = 0x00000000, +DIG_FIFO_2_PIX_PER_CYCLE = 0x00000001, +} DIG_FIFO_OUTPUT_PROCESSING_MODE; + +/* + * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum + */ + +typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR { +DIG_FIFO_NO_ERROR_OCCURRED = 0x00000000, +DIG_FIFO_UNDERFLOW_OCCURRED = 0x00000001, +DIG_FIFO_OVERFLOW_OCCURRED = 0x00000002, +} DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR; + +/* + * DIG_FIFO_READ_CLOCK_SRC enum + */ + +typedef enum DIG_FIFO_READ_CLOCK_SRC { +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000, +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001, +} DIG_FIFO_READ_CLOCK_SRC; + +/* + * DIG_INPUT_PIXEL_SEL enum + */ + +typedef enum DIG_INPUT_PIXEL_SEL { +DIG_ALL_PIXEL = 0x00000000, +DIG_EVEN_PIXEL_ONLY = 0x00000001, +DIG_ODD_PIXEL_ONLY = 0x00000002, +} DIG_INPUT_PIXEL_SEL; + +/* + * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum + */ + +typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { +DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000, +DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001, +} DIG_OUTPUT_CRC_CNTL_LINK_SEL; + +/* + * DIG_OUTPUT_CRC_DATA_SEL enum + */ + +typedef enum DIG_OUTPUT_CRC_DATA_SEL { +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000, +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001, +DIG_OUTPUT_CRC_FOR_VBI = 0x00000002, +DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003, +} DIG_OUTPUT_CRC_DATA_SEL; + +/* + * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum + */ + +typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000, +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001, +} DIG_RANDOM_PATTERN_SEED_RAN_PAT; + +/* + * DIG_SL_PIXEL_GROUPING enum + */ + +typedef enum DIG_SL_PIXEL_GROUPING { +DIG_SINGLETON_PIXELS = 0x00000000, +DIG_PAIR_PIXELS = 0x00000001, +} DIG_SL_PIXEL_GROUPING; + +/* + * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum + */ + +typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000, +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001, +} DIG_TEST_PATTERN_EXTERNAL_RESET_EN; + +/* + * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum + */ + +typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { +DIG_10BIT_TEST_PATTERN = 0x00000000, +DIG_ALTERNATING_TEST_PATTERN = 0x00000001, +} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; + +/* + * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum + */ + +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { +DIG_TEST_PATTERN_NORMAL = 0x00000000, +DIG_TEST_PATTERN_RANDOM = 0x00000001, +} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; + +/* + * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum + */ + +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { +DIG_RANDOM_PATTERN_ENABLED = 0x00000000, +DIG_RANDOM_PATTERN_RESETED = 0x00000001, +} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; + +/* + * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum + */ + +typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { +DIG_IN_NORMAL_OPERATION = 0x00000000, +DIG_IN_DEBUG_MODE = 0x00000001, +} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; + +/* + * DOLBY_VISION_ENABLE enum + */ + +typedef enum DOLBY_VISION_ENABLE { +DOLBY_VISION_DISABLED = 0x00000000, +DOLBY_VISION_ENABLED = 0x00000001, +} DOLBY_VISION_ENABLE; + +/* + * HDMI_ACP_SEND enum + */ + +typedef enum HDMI_ACP_SEND { +HDMI_ACP_NOT_SEND = 0x00000000, +HDMI_ACP_PKT_SEND = 0x00000001, +} HDMI_ACP_SEND; + +/* + * HDMI_ACR_AUDIO_PRIORITY enum + */ + +typedef enum HDMI_ACR_AUDIO_PRIORITY { +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000, +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001, +} HDMI_ACR_AUDIO_PRIORITY; + +/* + * HDMI_ACR_CONT enum + */ + +typedef enum HDMI_ACR_CONT { +HDMI_ACR_CONT_DISABLE = 0x00000000, +HDMI_ACR_CONT_ENABLE = 0x00000001, +} HDMI_ACR_CONT; + +/* + * HDMI_ACR_N_MULTIPLE enum + */ + +typedef enum HDMI_ACR_N_MULTIPLE { +HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000, +HDMI_ACR_1_MULTIPLE = 0x00000001, +HDMI_ACR_2_MULTIPLE = 0x00000002, +HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003, +HDMI_ACR_4_MULTIPLE = 0x00000004, +HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005, +HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006, +HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007, +} HDMI_ACR_N_MULTIPLE; + +/* + * HDMI_ACR_SELECT enum + */ + +typedef enum HDMI_ACR_SELECT { +HDMI_ACR_SELECT_HW = 0x00000000, +HDMI_ACR_SELECT_32K = 0x00000001, +HDMI_ACR_SELECT_44K = 0x00000002, +HDMI_ACR_SELECT_48K = 0x00000003, +} HDMI_ACR_SELECT; + +/* + * HDMI_ACR_SEND enum + */ + +typedef enum HDMI_ACR_SEND { +HDMI_ACR_NOT_SEND = 0x00000000, +HDMI_ACR_PKT_SEND = 0x00000001, +} HDMI_ACR_SEND; + +/* + * HDMI_ACR_SOURCE enum + */ + +typedef enum HDMI_ACR_SOURCE { +HDMI_ACR_SOURCE_HW = 0x00000000, +HDMI_ACR_SOURCE_SW = 0x00000001, +} HDMI_ACR_SOURCE; + +/* + * HDMI_AUDIO_DELAY_EN enum + */ + +typedef enum HDMI_AUDIO_DELAY_EN { +HDMI_AUDIO_DELAY_DISABLE = 0x00000000, +HDMI_AUDIO_DELAY_58CLK = 0x00000001, +HDMI_AUDIO_DELAY_56CLK = 0x00000002, +HDMI_AUDIO_DELAY_RESERVED = 0x00000003, +} HDMI_AUDIO_DELAY_EN; + +/* + * HDMI_AUDIO_INFO_CONT enum + */ + +typedef enum HDMI_AUDIO_INFO_CONT { +HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000, +HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001, +} HDMI_AUDIO_INFO_CONT; + +/* + * HDMI_AUDIO_INFO_SEND enum + */ + +typedef enum HDMI_AUDIO_INFO_SEND { +HDMI_AUDIO_INFO_NOT_SEND = 0x00000000, +HDMI_AUDIO_INFO_PKT_SEND = 0x00000001, +} HDMI_AUDIO_INFO_SEND; + +/* + * HDMI_CLOCK_CHANNEL_RATE enum + */ + +typedef enum HDMI_CLOCK_CHANNEL_RATE { +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000, +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001, +} HDMI_CLOCK_CHANNEL_RATE; + +/* + * HDMI_DATA_SCRAMBLE_EN enum + */ + +typedef enum HDMI_DATA_SCRAMBLE_EN { +HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000, +HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001, +} HDMI_DATA_SCRAMBLE_EN; + +/* + * HDMI_DEEP_COLOR_DEPTH enum + */ + +typedef enum HDMI_DEEP_COLOR_DEPTH { +HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000, +HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001, +HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002, +HDMI_DEEP_COLOR_DEPTH_48BPP = 0x00000003, +} HDMI_DEEP_COLOR_DEPTH; + +/* + * HDMI_DEFAULT_PAHSE enum + */ + +typedef enum HDMI_DEFAULT_PAHSE { +HDMI_DEFAULT_PHASE_IS_0 = 0x00000000, +HDMI_DEFAULT_PHASE_IS_1 = 0x00000001, +} HDMI_DEFAULT_PAHSE; + +/* + * HDMI_ERROR_ACK enum + */ + +typedef enum HDMI_ERROR_ACK { +HDMI_ERROR_ACK_INT = 0x00000000, +HDMI_ERROR_NOT_ACK = 0x00000001, +} HDMI_ERROR_ACK; + +/* + * HDMI_ERROR_MASK enum + */ + +typedef enum HDMI_ERROR_MASK { +HDMI_ERROR_MASK_INT = 0x00000000, +HDMI_ERROR_NOT_MASK = 0x00000001, +} HDMI_ERROR_MASK; + +/* + * HDMI_GC_AVMUTE enum + */ + +typedef enum HDMI_GC_AVMUTE { +HDMI_GC_AVMUTE_SET = 0x00000000, +HDMI_GC_AVMUTE_UNSET = 0x00000001, +} HDMI_GC_AVMUTE; + +/* + * HDMI_GC_AVMUTE_CONT enum + */ + +typedef enum HDMI_GC_AVMUTE_CONT { +HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000, +HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001, +} HDMI_GC_AVMUTE_CONT; + +/* + * HDMI_GC_CONT enum + */ + +typedef enum HDMI_GC_CONT { +HDMI_GC_CONT_DISABLE = 0x00000000, +HDMI_GC_CONT_ENABLE = 0x00000001, +} HDMI_GC_CONT; + +/* + * HDMI_GC_SEND enum + */ + +typedef enum HDMI_GC_SEND { +HDMI_GC_NOT_SEND = 0x00000000, +HDMI_GC_PKT_SEND = 0x00000001, +} HDMI_GC_SEND; + +/* + * HDMI_GENERIC_CONT enum + */ + +typedef enum HDMI_GENERIC_CONT { +HDMI_GENERIC_CONT_DISABLE = 0x00000000, +HDMI_GENERIC_CONT_ENABLE = 0x00000001, +} HDMI_GENERIC_CONT; + +/* + * HDMI_GENERIC_SEND enum + */ + +typedef enum HDMI_GENERIC_SEND { +HDMI_GENERIC_NOT_SEND = 0x00000000, +HDMI_GENERIC_PKT_SEND = 0x00000001, +} HDMI_GENERIC_SEND; + +/* + * HDMI_ISRC_CONT enum + */ + +typedef enum HDMI_ISRC_CONT { +HDMI_ISRC_CONT_DISABLE = 0x00000000, +HDMI_ISRC_CONT_ENABLE = 0x00000001, +} HDMI_ISRC_CONT; + +/* + * HDMI_ISRC_SEND enum + */ + +typedef enum HDMI_ISRC_SEND { +HDMI_ISRC_NOT_SEND = 0x00000000, +HDMI_ISRC_PKT_SEND = 0x00000001, +} HDMI_ISRC_SEND; + +/* + * HDMI_KEEPOUT_MODE enum + */ + +typedef enum HDMI_KEEPOUT_MODE { +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000, +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001, +} HDMI_KEEPOUT_MODE; + +/* + * HDMI_METADATA_ENABLE enum + */ + +typedef enum HDMI_METADATA_ENABLE { +HDMI_METADATA_NOT_SEND = 0x00000000, +HDMI_METADATA_PKT_SEND = 0x00000001, +} HDMI_METADATA_ENABLE; + +/* + * HDMI_MPEG_INFO_CONT enum + */ + +typedef enum HDMI_MPEG_INFO_CONT { +HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000, +HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001, +} HDMI_MPEG_INFO_CONT; + +/* + * HDMI_MPEG_INFO_SEND enum + */ + +typedef enum HDMI_MPEG_INFO_SEND { +HDMI_MPEG_INFO_NOT_SEND = 0x00000000, +HDMI_MPEG_INFO_PKT_SEND = 0x00000001, +} HDMI_MPEG_INFO_SEND; + +/* + * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum + */ + +typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000, +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001, +} HDMI_NO_EXTRA_NULL_PACKET_FILLED; + +/* + * HDMI_NULL_SEND enum + */ + +typedef enum HDMI_NULL_SEND { +HDMI_NULL_NOT_SEND = 0x00000000, +HDMI_NULL_PKT_SEND = 0x00000001, +} HDMI_NULL_SEND; + +/* + * HDMI_PACKET_GEN_VERSION enum + */ + +typedef enum HDMI_PACKET_GEN_VERSION { +HDMI_PACKET_GEN_VERSION_OLD = 0x00000000, +HDMI_PACKET_GEN_VERSION_NEW = 0x00000001, +} HDMI_PACKET_GEN_VERSION; + +/* + * HDMI_PACKET_LINE_REFERENCE enum + */ + +typedef enum HDMI_PACKET_LINE_REFERENCE { +HDMI_PKT_LINE_REF_VSYNC = 0x00000000, +HDMI_PKT_LINE_REF_OTGSOF = 0x00000001, +} HDMI_PACKET_LINE_REFERENCE; + +/* + * HDMI_PACKING_PHASE_OVERRIDE enum + */ + +typedef enum HDMI_PACKING_PHASE_OVERRIDE { +HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000, +HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001, +} HDMI_PACKING_PHASE_OVERRIDE; + +/* + * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum + */ + +typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000, +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001, +} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; + +/* + * TMDS_COLOR_FORMAT enum + */ + +typedef enum TMDS_COLOR_FORMAT { +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000, +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001, +TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002, +TMDS_COLOR_FORMAT_RESERVED = 0x00000003, +} TMDS_COLOR_FORMAT; + +/* + * TMDS_CTL0_DATA_INVERT enum + */ + +typedef enum TMDS_CTL0_DATA_INVERT { +TMDS_CTL0_DATA_NORMAL = 0x00000000, +TMDS_CTL0_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL0_DATA_INVERT; + +/* + * TMDS_CTL0_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL0_DATA_MODULATION { +TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL0_DATA_MODULATION; + +/* + * TMDS_CTL0_DATA_SEL enum + */ + +typedef enum TMDS_CTL0_DATA_SEL { +TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006, +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007, +} TMDS_CTL0_DATA_SEL; + +/* + * TMDS_CTL0_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL0_PATTERN_OUT_EN { +TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL0_PATTERN_OUT_EN; + +/* + * TMDS_CTL1_DATA_INVERT enum + */ + +typedef enum TMDS_CTL1_DATA_INVERT { +TMDS_CTL1_DATA_NORMAL = 0x00000000, +TMDS_CTL1_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL1_DATA_INVERT; + +/* + * TMDS_CTL1_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL1_DATA_MODULATION { +TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL1_DATA_MODULATION; + +/* + * TMDS_CTL1_DATA_SEL enum + */ + +typedef enum TMDS_CTL1_DATA_SEL { +TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006, +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007, +} TMDS_CTL1_DATA_SEL; + +/* + * TMDS_CTL1_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL1_PATTERN_OUT_EN { +TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL1_PATTERN_OUT_EN; + +/* + * TMDS_CTL2_DATA_INVERT enum + */ + +typedef enum TMDS_CTL2_DATA_INVERT { +TMDS_CTL2_DATA_NORMAL = 0x00000000, +TMDS_CTL2_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL2_DATA_INVERT; + +/* + * TMDS_CTL2_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL2_DATA_MODULATION { +TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL2_DATA_MODULATION; + +/* + * TMDS_CTL2_DATA_SEL enum + */ + +typedef enum TMDS_CTL2_DATA_SEL { +TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006, +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007, +} TMDS_CTL2_DATA_SEL; + +/* + * TMDS_CTL2_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL2_PATTERN_OUT_EN { +TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL2_PATTERN_OUT_EN; + +/* + * TMDS_CTL3_DATA_INVERT enum + */ + +typedef enum TMDS_CTL3_DATA_INVERT { +TMDS_CTL3_DATA_NORMAL = 0x00000000, +TMDS_CTL3_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL3_DATA_INVERT; + +/* + * TMDS_CTL3_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL3_DATA_MODULATION { +TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL3_DATA_MODULATION; + +/* + * TMDS_CTL3_DATA_SEL enum + */ + +typedef enum TMDS_CTL3_DATA_SEL { +TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006, +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007, +} TMDS_CTL3_DATA_SEL; + +/* + * TMDS_CTL3_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL3_PATTERN_OUT_EN { +TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL3_PATTERN_OUT_EN; + +/* + * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum + */ + +typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000, +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001, +} TMDS_DATA_SYNCHRONIZATION_DSINTSEL; + +/* + * TMDS_PIXEL_ENCODING enum + */ + +typedef enum TMDS_PIXEL_ENCODING { +TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000, +TMDS_PIXEL_ENCODING_422 = 0x00000001, +} TMDS_PIXEL_ENCODING; + +/* + * TMDS_REG_TEST_OUTPUTA_CNTLA enum + */ + +typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000, +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001, +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002, +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003, +} TMDS_REG_TEST_OUTPUTA_CNTLA; + +/* + * TMDS_REG_TEST_OUTPUTB_CNTLB enum + */ + +typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000, +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001, +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002, +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003, +} TMDS_REG_TEST_OUTPUTB_CNTLB; + +/* + * TMDS_STEREOSYNC_CTL_SEL_REG enum + */ + +typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { +TMDS_STEREOSYNC_CTL0 = 0x00000000, +TMDS_STEREOSYNC_CTL1 = 0x00000001, +TMDS_STEREOSYNC_CTL2 = 0x00000002, +TMDS_STEREOSYNC_CTL3 = 0x00000003, +} TMDS_STEREOSYNC_CTL_SEL_REG; + +/* + * TMDS_SYNC_PHASE enum + */ + +typedef enum TMDS_SYNC_PHASE { +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000, +TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001, +} TMDS_SYNC_PHASE; + +/* + * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000, +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; + +/* + * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000, +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; + +/* + * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000, +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELA; + +/* + * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000, +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELB; + +/* + * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000, +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; + +/* + * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000, +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001, +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002, +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003, +} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; + +/* + * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000, +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; + +/* + * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000, +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; + +/* + * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000, +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; + +/* + * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000, +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; + +/* + * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000, +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001, +} TMDS_TRANSMITTER_ENABLE_HPD_MASK; + +/* + * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001, +} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; + +/* + * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001, +} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; + +/******************************************************* + * DP_AUX Enums + *******************************************************/ + +/* + * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum + */ + +typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000, +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001, +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002, +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003, +} DP_AUX_ARB_CONTROL_ARB_PRIORITY; + +/* + * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum + */ + +typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000, +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001, +} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; + +/* + * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum + */ + +typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000, +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001, +} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; + +/* + * DP_AUX_ARB_STATUS enum + */ + +typedef enum DP_AUX_ARB_STATUS { +DP_AUX_IDLE = 0x00000000, +DP_AUX_IN_USE_LS = 0x00000001, +DP_AUX_IN_USE_GTC = 0x00000002, +DP_AUX_IN_USE_SW = 0x00000003, +DP_AUX_IN_USE_PHYWAKE = 0x00000004, +} DP_AUX_ARB_STATUS; + +/* + * DP_AUX_CONTROL_HPD_SEL enum + */ + +typedef enum DP_AUX_CONTROL_HPD_SEL { +DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000, +DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001, +DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002, +DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003, +DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004, +DP_AUX_CONTROL_NO_HPD_SELECTED = 0x00000005, +} DP_AUX_CONTROL_HPD_SEL; + +/* + * DP_AUX_CONTROL_TEST_MODE enum + */ + +typedef enum DP_AUX_CONTROL_TEST_MODE { +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000, +DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001, +} DP_AUX_CONTROL_TEST_MODE; + +/* + * DP_AUX_DEFINITE_ERR_REACHED_ACK enum + */ + +typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000, +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001, +} DP_AUX_DEFINITE_ERR_REACHED_ACK; + +/* + * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000, +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; + +/* + * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000, +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; + +/* + * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000, +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; + +/* + * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003, +} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; + +/* + * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003, +} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; + +/* + * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007, +} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; + +/* + * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007, +} DP_AUX_DPHY_RX_CONTROL_START_WINDOW; + +/* + * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum + */ + +typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007, +} DP_AUX_DPHY_RX_DETECTION_THRESHOLD; + +/* + * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum + */ + +typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005, +} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; + +/* + * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum + */ + +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000, +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001, +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002, +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; + +/* + * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum + */ + +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000, +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; + +/* + * DP_AUX_ERR_OCCURRED_ACK enum + */ + +typedef enum DP_AUX_ERR_OCCURRED_ACK { +DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000, +DP_AUX_ERR_OCCURRED__ACK = 0x00000001, +} DP_AUX_ERR_OCCURRED_ACK; + +/* + * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum + */ + +typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000, +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001, +} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; + +/* + * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum + */ + +typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000, +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001, +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002, +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003, +} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; + +/* + * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum + */ + +typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000, +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001, +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002, +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003, +} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; + +/* + * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum + */ + +typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000, +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001, +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002, +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003, +} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; + +/* + * DP_AUX_INT_ACK enum + */ + +typedef enum DP_AUX_INT_ACK { +DP_AUX_INT__NOT_ACK = 0x00000000, +DP_AUX_INT__ACK = 0x00000001, +} DP_AUX_INT_ACK; + +/* + * DP_AUX_LS_UPDATE_ACK enum + */ + +typedef enum DP_AUX_LS_UPDATE_ACK { +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000, +DP_AUX_INT_LS_UPDATE_ACK = 0x00000001, +} DP_AUX_LS_UPDATE_ACK; + +/* + * DP_AUX_PHY_WAKE_PRIORITY enum + */ + +typedef enum DP_AUX_PHY_WAKE_PRIORITY { +DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0x00000000, +DP_AUX_PHY_WAKE_LOW_PRIORITY = 0x00000001, +} DP_AUX_PHY_WAKE_PRIORITY; + +/* + * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum + */ + +typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000, +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001, +} DP_AUX_POTENTIAL_ERR_REACHED_ACK; + +/* + * DP_AUX_RESET enum + */ + +typedef enum DP_AUX_RESET { +DP_AUX_RESET_DEASSERTED = 0x00000000, +DP_AUX_RESET_ASSERTED = 0x00000001, +} DP_AUX_RESET; + +/* + * DP_AUX_RESET_DONE enum + */ + +typedef enum DP_AUX_RESET_DONE { +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000, +DP_AUX_RESET_SEQUENCE_DONE = 0x00000001, +} DP_AUX_RESET_DONE; + +/* + * DP_AUX_RX_TIMEOUT_LEN_MUL enum + */ + +typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL { +DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0x00000000, +DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 0x00000001, +DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 0x00000002, +DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 0x00000003, +} DP_AUX_RX_TIMEOUT_LEN_MUL; + +/* + * DP_AUX_SW_CONTROL_LS_READ_TRIG enum + */ + +typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000, +DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001, +} DP_AUX_SW_CONTROL_LS_READ_TRIG; + +/* + * DP_AUX_SW_CONTROL_SW_GO enum + */ + +typedef enum DP_AUX_SW_CONTROL_SW_GO { +DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000, +DP_AUX_SW_CONTROL_SW__GO = 0x00000001, +} DP_AUX_SW_CONTROL_SW_GO; + +/* + * DP_AUX_TX_PRECHARGE_LEN_MUL enum + */ + +typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL { +DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0x00000000, +DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 0x00000001, +DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 0x00000002, +DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 0x00000003, +} DP_AUX_TX_PRECHARGE_LEN_MUL; + +/******************************************************* + * DOUT_I2C Enums + *******************************************************/ + +/* + * DOUT_I2C_ACK enum + */ + +typedef enum DOUT_I2C_ACK { +DOUT_I2C_NO_ACK = 0x00000000, +DOUT_I2C_ACK_TO_CLEAN = 0x00000001, +} DOUT_I2C_ACK; + +/* + * DOUT_I2C_ARBITRATION_ABORT_XFER enum + */ + +typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000, +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001, +} DOUT_I2C_ARBITRATION_ABORT_XFER; + +/* + * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum + */ + +typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000, +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001, +} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; + +/* + * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum + */ + +typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000, +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001, +} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; + +/* + * DOUT_I2C_ARBITRATION_SW_PRIORITY enum + */ + +typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000, +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001, +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002, +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003, +} DOUT_I2C_ARBITRATION_SW_PRIORITY; + +/* + * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum + */ + +typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000, +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001, +} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; + +/* + * DOUT_I2C_CONTROL_DBG_REF_SEL enum + */ + +typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000, +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001, +} DOUT_I2C_CONTROL_DBG_REF_SEL; + +/* + * DOUT_I2C_CONTROL_DDC_SELECT enum + */ + +typedef enum DOUT_I2C_CONTROL_DDC_SELECT { +DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000, +DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001, +DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002, +DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003, +DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004, +DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000005, +} DOUT_I2C_CONTROL_DDC_SELECT; + +/* + * DOUT_I2C_CONTROL_GO enum + */ + +typedef enum DOUT_I2C_CONTROL_GO { +DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000, +DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001, +} DOUT_I2C_CONTROL_GO; + +/* + * DOUT_I2C_CONTROL_SEND_RESET enum + */ + +typedef enum DOUT_I2C_CONTROL_SEND_RESET { +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000, +DOUT_I2C_CONTROL__SEND_RESET = 0x00000001, +} DOUT_I2C_CONTROL_SEND_RESET; + +/* + * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum + */ + +typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH { +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0x00000000, +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 0x00000001, +} DOUT_I2C_CONTROL_SEND_RESET_LENGTH; + +/* + * DOUT_I2C_CONTROL_SOFT_RESET enum + */ + +typedef enum DOUT_I2C_CONTROL_SOFT_RESET { +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000, +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001, +} DOUT_I2C_CONTROL_SOFT_RESET; + +/* + * DOUT_I2C_CONTROL_SW_STATUS_RESET enum + */ + +typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000, +DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001, +} DOUT_I2C_CONTROL_SW_STATUS_RESET; + +/* + * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum + */ + +typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { +DOUT_I2C_CONTROL_TRANS0 = 0x00000000, +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001, +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002, +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003, +} DOUT_I2C_CONTROL_TRANSACTION_COUNT; + +/* + * DOUT_I2C_DATA_INDEX_WRITE enum + */ + +typedef enum DOUT_I2C_DATA_INDEX_WRITE { +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000, +DOUT_I2C_DATA__INDEX_WRITE = 0x00000001, +} DOUT_I2C_DATA_INDEX_WRITE; + +/* + * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001, +} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; + +/* + * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; + +/* + * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000, +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; + +/* + * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000, +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001, +} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; + +/* + * DOUT_I2C_DDC_SPEED_THRESHOLD enum + */ + +typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000, +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001, +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002, +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003, +} DOUT_I2C_DDC_SPEED_THRESHOLD; + +/* + * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum + */ + +typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000, +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001, +} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; + +/* + * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum + */ + +typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000, +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001, +} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; + +/* + * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum + */ + +typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000, +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001, +} DOUT_I2C_TRANSACTION_STOP_ON_NACK; + +/******************************************************* + * DIO_MISC Enums + *******************************************************/ + +/* + * CLOCK_GATING_EN enum + */ + +typedef enum CLOCK_GATING_EN { +CLOCK_GATING_ENABLE = 0x00000000, +CLOCK_GATING_DISABLE = 0x00000001, +} CLOCK_GATING_EN; + +/* + * DAC_MUX_SELECT enum + */ + +typedef enum DAC_MUX_SELECT { +DAC_MUX_SELECT_DACA = 0x00000000, +DAC_MUX_SELECT_DACB = 0x00000001, +} DAC_MUX_SELECT; + +/* + * DIOMEM_PWR_DIS_CTRL enum + */ + +typedef enum DIOMEM_PWR_DIS_CTRL { +DIOMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, +DIOMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, +} DIOMEM_PWR_DIS_CTRL; + +/* + * DIOMEM_PWR_FORCE_CTRL enum + */ + +typedef enum DIOMEM_PWR_FORCE_CTRL { +DIOMEM_NO_FORCE_REQUEST = 0x00000000, +DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +DIOMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} DIOMEM_PWR_FORCE_CTRL; + +/* + * DIOMEM_PWR_FORCE_CTRL2 enum + */ + +typedef enum DIOMEM_PWR_FORCE_CTRL2 { +DIOMEM_NO_FORCE_REQ = 0x00000000, +DIOMEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001, +} DIOMEM_PWR_FORCE_CTRL2; + +/* + * DIOMEM_PWR_SEL_CTRL enum + */ + +typedef enum DIOMEM_PWR_SEL_CTRL { +DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, +DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, +DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, +} DIOMEM_PWR_SEL_CTRL; + +/* + * DIOMEM_PWR_SEL_CTRL2 enum + */ + +typedef enum DIOMEM_PWR_SEL_CTRL2 { +DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0x00000000, +DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, +} DIOMEM_PWR_SEL_CTRL2; + +/* + * DIO_DBG_BLOCK_SEL enum + */ + +typedef enum DIO_DBG_BLOCK_SEL { +DIO_DBG_BLOCK_SEL_DIO = 0x00000000, +DIO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b, +DIO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c, +DIO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d, +DIO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e, +DIO_DBG_BLOCK_SEL_DIGFE_E = 0x0000000f, +DIO_DBG_BLOCK_SEL_DIGA = 0x00000012, +DIO_DBG_BLOCK_SEL_DIGB = 0x00000013, +DIO_DBG_BLOCK_SEL_DIGC = 0x00000014, +DIO_DBG_BLOCK_SEL_DIGD = 0x00000015, +DIO_DBG_BLOCK_SEL_DIGE = 0x00000016, +DIO_DBG_BLOCK_SEL_DPFE_A = 0x00000019, +DIO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a, +DIO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b, +DIO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c, +DIO_DBG_BLOCK_SEL_DPFE_E = 0x0000001d, +DIO_DBG_BLOCK_SEL_DPA = 0x00000020, +DIO_DBG_BLOCK_SEL_DPB = 0x00000021, +DIO_DBG_BLOCK_SEL_DPC = 0x00000022, +DIO_DBG_BLOCK_SEL_DPD = 0x00000023, +DIO_DBG_BLOCK_SEL_DPE = 0x00000024, +DIO_DBG_BLOCK_SEL_AUX0 = 0x00000027, +DIO_DBG_BLOCK_SEL_AUX1 = 0x00000028, +DIO_DBG_BLOCK_SEL_AUX2 = 0x00000029, +DIO_DBG_BLOCK_SEL_AUX3 = 0x0000002a, +DIO_DBG_BLOCK_SEL_AUX4 = 0x0000002b, +DIO_DBG_BLOCK_SEL_PERFMON_DIO = 0x0000002d, +DIO_DBG_BLOCK_SEL_RESERVED = 0x0000002e, +} DIO_DBG_BLOCK_SEL; + +/* + * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum + */ + +typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE { +DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000, +DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001, +} DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE; + +/* + * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum + */ + +typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE { +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0x00000000, +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 0x00000001, +} DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE; + +/* + * ENUM_DIO_DCN_ACTIVE_STATUS enum + */ + +typedef enum ENUM_DIO_DCN_ACTIVE_STATUS { +ENUM_DCN_NOT_ACTIVE = 0x00000000, +ENUM_DCN_ACTIVE = 0x00000001, +} ENUM_DIO_DCN_ACTIVE_STATUS; + +/* + * GENERIC_STEREOSYNC_SEL enum + */ + +typedef enum GENERIC_STEREOSYNC_SEL { +GENERIC_STEREOSYNC_SEL_D1 = 0x00000000, +GENERIC_STEREOSYNC_SEL_D2 = 0x00000001, +GENERIC_STEREOSYNC_SEL_D3 = 0x00000002, +GENERIC_STEREOSYNC_SEL_D4 = 0x00000003, +GENERIC_STEREOSYNC_SEL_RESERVED = 0x00000004, +} GENERIC_STEREOSYNC_SEL; + +/* + * PM_ASSERT_RESET enum + */ + +typedef enum PM_ASSERT_RESET { +PM_ASSERT_RESET_0 = 0x00000000, +PM_ASSERT_RESET_1 = 0x00000001, +} PM_ASSERT_RESET; + +/* + * SOFT_RESET enum + */ + +typedef enum SOFT_RESET { +SOFT_RESET_0 = 0x00000000, +SOFT_RESET_1 = 0x00000001, +} SOFT_RESET; + +/* + * TMDS_MUX_SELECT enum + */ + +typedef enum TMDS_MUX_SELECT { +TMDS_MUX_SELECT_B = 0x00000000, +TMDS_MUX_SELECT_G = 0x00000001, +TMDS_MUX_SELECT_R = 0x00000002, +TMDS_MUX_SELECT_RESERVED = 0x00000003, +} TMDS_MUX_SELECT; + +/******************************************************* + * DME Enums + *******************************************************/ + +/* + * DME_MEM_POWER_STATE_ENUM enum + */ + +typedef enum DME_MEM_POWER_STATE_ENUM { +DME_MEM_POWER_STATE_ENUM_ON = 0x00000000, +DME_MEM_POWER_STATE_ENUM_LS = 0x00000001, +DME_MEM_POWER_STATE_ENUM_DS = 0x00000002, +DME_MEM_POWER_STATE_ENUM_SD = 0x00000003, +} DME_MEM_POWER_STATE_ENUM; + +/* + * DME_MEM_PWR_DIS_CTRL enum + */ + +typedef enum DME_MEM_PWR_DIS_CTRL { +DME_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, +DME_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, +} DME_MEM_PWR_DIS_CTRL; + +/* + * DME_MEM_PWR_FORCE_CTRL enum + */ + +typedef enum DME_MEM_PWR_FORCE_CTRL { +DME_MEM_NO_FORCE_REQUEST = 0x00000000, +DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +DME_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} DME_MEM_PWR_FORCE_CTRL; + +/* + * METADATA_HUBP_SEL enum + */ + +typedef enum METADATA_HUBP_SEL { +METADATA_HUBP_SEL_0 = 0x00000000, +METADATA_HUBP_SEL_1 = 0x00000001, +METADATA_HUBP_SEL_2 = 0x00000002, +METADATA_HUBP_SEL_3 = 0x00000003, +METADATA_HUBP_SEL_RESERVED = 0x00000004, +} METADATA_HUBP_SEL; + +/* + * METADATA_STREAM_TYPE_SEL enum + */ + +typedef enum METADATA_STREAM_TYPE_SEL { +METADATA_STREAM_DP = 0x00000000, +METADATA_STREAM_DVE = 0x00000001, +} METADATA_STREAM_TYPE_SEL; + +/******************************************************* + * VPG Enums + *******************************************************/ + +/* + * VPG_MEM_PWR_DIS_CTRL enum + */ + +typedef enum VPG_MEM_PWR_DIS_CTRL { +VPG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, +VPG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, +} VPG_MEM_PWR_DIS_CTRL; + +/* + * VPG_MEM_PWR_FORCE_CTRL enum + */ + +typedef enum VPG_MEM_PWR_FORCE_CTRL { +VPG_MEM_NO_FORCE_REQ = 0x00000000, +VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001, +} VPG_MEM_PWR_FORCE_CTRL; + +/******************************************************* + * AFMT Enums + *******************************************************/ + +/* + * AFMT_ACP_TYPE enum + */ + +typedef enum AFMT_ACP_TYPE { +ACP_TYPE_GENERIC_AUDIO = 0x00000000, +ACP_TYPE_ICE60958_AUDIO = 0x00000001, +ACP_TYPE_DVD_AUDIO = 0x00000002, +ACP_TYPE_SUPER_AUDIO_CD = 0x00000003, +} AFMT_ACP_TYPE; + +/* + * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum + */ + +typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { +AFMT_AUDIO_CRC_CH0_SIG = 0x00000000, +AFMT_AUDIO_CRC_CH1_SIG = 0x00000001, +AFMT_AUDIO_CRC_CH2_SIG = 0x00000002, +AFMT_AUDIO_CRC_CH3_SIG = 0x00000003, +AFMT_AUDIO_CRC_CH4_SIG = 0x00000004, +AFMT_AUDIO_CRC_CH5_SIG = 0x00000005, +AFMT_AUDIO_CRC_CH6_SIG = 0x00000006, +AFMT_AUDIO_CRC_CH7_SIG = 0x00000007, +AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008, +AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009, +AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a, +AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b, +AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c, +AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d, +AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e, +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f, +} AFMT_AUDIO_CRC_CONTROL_CH_SEL; + +/* + * AFMT_AUDIO_CRC_CONTROL_CONT enum + */ + +typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { +AFMT_AUDIO_CRC_ONESHOT = 0x00000000, +AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001, +} AFMT_AUDIO_CRC_CONTROL_CONT; + +/* + * AFMT_AUDIO_CRC_CONTROL_SOURCE enum + */ + +typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000, +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001, +} AFMT_AUDIO_CRC_CONTROL_SOURCE; + +/* + * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum + */ + +typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000, +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001, +} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; + +/* + * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum + */ + +typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { +AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000, +AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001, +} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; + +/* + * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum + */ + +typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000, +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001, +} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; + +/* + * AFMT_AUDIO_SRC_CONTROL_SELECT enum + */ + +typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000, +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001, +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002, +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003, +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004, +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005, +} AFMT_AUDIO_SRC_CONTROL_SELECT; + +/* + * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum + */ + +typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS { +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000, +HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001, +} AFMT_HDMI_AUDIO_SEND_MAX_PACKETS; + +/* + * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum + */ + +typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000, +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, +} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; + +/* + * AFMT_INTERRUPT_STATUS_CHG_MASK enum + */ + +typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { +AFMT_INTERRUPT_DISABLE = 0x00000000, +AFMT_INTERRUPT_ENABLE = 0x00000001, +} AFMT_INTERRUPT_STATUS_CHG_MASK; + +/* + * AFMT_MEM_PWR_DIS_CTRL enum + */ + +typedef enum AFMT_MEM_PWR_DIS_CTRL { +AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, +AFMT_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, +} AFMT_MEM_PWR_DIS_CTRL; + +/* + * AFMT_MEM_PWR_FORCE_CTRL enum + */ + +typedef enum AFMT_MEM_PWR_FORCE_CTRL { +AFMT_MEM_NO_FORCE_REQUEST = 0x00000000, +AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} AFMT_MEM_PWR_FORCE_CTRL; + +/* + * AFMT_RAMP_CONTROL0_SIGN enum + */ + +typedef enum AFMT_RAMP_CONTROL0_SIGN { +AFMT_RAMP_SIGNED = 0x00000000, +AFMT_RAMP_UNSIGNED = 0x00000001, +} AFMT_RAMP_CONTROL0_SIGN; + +/* + * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum + */ + +typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE { +AFMT_ACP_SOURCE_FROM_AZALIA = 0x00000000, +AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, +} AFMT_VBI_PACKET_CONTROL_ACP_SOURCE; + +/* + * AUDIO_LAYOUT_SELECT enum + */ + +typedef enum AUDIO_LAYOUT_SELECT { +AUDIO_LAYOUT_0 = 0x00000000, +AUDIO_LAYOUT_1 = 0x00000001, +} AUDIO_LAYOUT_SELECT; + +/******************************************************* + * HPO_TOP Enums + *******************************************************/ + +/* + * HPO_TOP_CLOCK_GATING_DISABLE enum + */ + +typedef enum HPO_TOP_CLOCK_GATING_DISABLE { +HPO_TOP_CLOCK_GATING_EN = 0x00000000, +HPO_TOP_CLOCK_GATING_DIS = 0x00000001, +} HPO_TOP_CLOCK_GATING_DISABLE; + +/* + * HPO_TOP_TEST_CLK_SEL enum + */ + +typedef enum HPO_TOP_TEST_CLK_SEL { +HPO_TOP_PERMANENT_DISPCLK = 0x00000000, +HPO_TOP_REGISTER_GATED_DISPCLK = 0x00000001, +HPO_TOP_PERMANENT_SOCCLK = 0x00000002, +HPO_TOP_TEST_CLOCK_RESERVED = 0x00000003, +HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 0x00000004, +HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 0x00000005, +HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 0x00000006, +HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 0x00000007, +HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 0x00000008, +HPO_TOP_PERMANENT_HDMICHARCLK0 = 0x00000009, +HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 0x0000000a, +HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 0x0000000b, +} HPO_TOP_TEST_CLK_SEL; + +/******************************************************* + * DP_STREAM_MAPPER Enums + *******************************************************/ + +/* + * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum + */ + +typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET { +DP_STREAM_MAPPER_LINK0 = 0x00000000, +DP_STREAM_MAPPER_LINK1 = 0x00000001, +DP_STREAM_MAPPER_RESERVED = 0x00000002, +} DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET; + +/******************************************************* + * HDMI_STREAM_ENC Enums + *******************************************************/ + +/* + * HDMI_STREAM_ENC_DB_DISABLE_CONTROL enum + */ + +typedef enum HDMI_STREAM_ENC_DB_DISABLE_CONTROL { +HDMI_STREAM_ENC_DB_ENABLE = 0x00000000, +HDMI_STREAM_ENC_DB_DISABLE = 0x00000001, +} HDMI_STREAM_ENC_DB_DISABLE_CONTROL; + +/* + * HDMI_STREAM_ENC_DSC_MODE enum + */ + +typedef enum HDMI_STREAM_ENC_DSC_MODE { +STREAM_DSC_DISABLE = 0x00000000, +STREAM_DSC_444_RGB = 0x00000001, +STREAM_DSC_NATIVE_422_420 = 0x00000002, +} HDMI_STREAM_ENC_DSC_MODE; + +/* + * HDMI_STREAM_ENC_ENABLE_CONTROL enum + */ + +typedef enum HDMI_STREAM_ENC_ENABLE_CONTROL { +HDMI_STREAM_ENC_DISABLE = 0x00000000, +HDMI_STREAM_ENC_ENABLE = 0x00000001, +} HDMI_STREAM_ENC_ENABLE_CONTROL; + +/* + * HDMI_STREAM_ENC_ODM_COMBINE_MODE enum + */ + +typedef enum HDMI_STREAM_ENC_ODM_COMBINE_MODE { +STREAM_ODM_COMBINE_1_SEGMENT = 0x00000000, +STREAM_ODM_COMBINE_2_SEGMENT = 0x00000001, +STREAM_ODM_COMBINE_RESERVED = 0x00000002, +STREAM_ODM_COMBINE_4_SEGMENT = 0x00000003, +} HDMI_STREAM_ENC_ODM_COMBINE_MODE; + +/* + * HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum + */ + +typedef enum HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR { +HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000, +HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001, +HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002, +} HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR; + +/* + * HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum + */ + +typedef enum HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT { +HDMI_STREAM_ENC_HARDWARE = 0x00000000, +HDMI_STREAM_ENC_PROGRAMMABLE = 0x00000001, +} HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT; + +/* + * HDMI_STREAM_ENC_PIXEL_ENCODING enum + */ + +typedef enum HDMI_STREAM_ENC_PIXEL_ENCODING { +STREAM_PIXEL_ENCODING_444_RGB = 0x00000000, +STREAM_PIXEL_ENCODING_422 = 0x00000001, +STREAM_PIXEL_ENCODING_420 = 0x00000002, +} HDMI_STREAM_ENC_PIXEL_ENCODING; + +/* + * HDMI_STREAM_ENC_READ_CLOCK_CONTROL enum + */ + +typedef enum HDMI_STREAM_ENC_READ_CLOCK_CONTROL { +HDMI_STREAM_ENC_DCCG = 0x00000000, +HDMI_STREAM_ENC_DISPLAY_PIPE = 0x00000001, +} HDMI_STREAM_ENC_READ_CLOCK_CONTROL; + +/* + * HDMI_STREAM_ENC_RESET_CONTROL enum + */ + +typedef enum HDMI_STREAM_ENC_RESET_CONTROL { +HDMI_STREAM_ENC_NOT_RESET = 0x00000000, +HDMI_STREAM_ENC_RESET = 0x00000001, +} HDMI_STREAM_ENC_RESET_CONTROL; + +/* + * HDMI_STREAM_ENC_STREAM_ACTIVE enum + */ + +typedef enum HDMI_STREAM_ENC_STREAM_ACTIVE { +HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000, +HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001, +} HDMI_STREAM_ENC_STREAM_ACTIVE; + +/******************************************************* + * HDMI_TB_ENC Enums + *******************************************************/ + +/* + * BORROWBUFFER_MEM_POWER_STATE_ENUM enum + */ + +typedef enum BORROWBUFFER_MEM_POWER_STATE_ENUM { +BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0x00000000, +BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 0x00000001, +BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 0x00000002, +BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 0x00000003, +} BORROWBUFFER_MEM_POWER_STATE_ENUM; + +/* + * HDMI_BORROW_MODE enum + */ + +typedef enum HDMI_BORROW_MODE { +TB_BORROW_MODE_NONE = 0x00000000, +TB_BORROW_MODE_ACTIVE = 0x00000001, +TB_BORROW_MODE_BLANK = 0x00000002, +TB_BORROW_MODE_RESERVED = 0x00000003, +} HDMI_BORROW_MODE; + +/* + * HDMI_TB_ENC_ACP_SEND enum + */ + +typedef enum HDMI_TB_ENC_ACP_SEND { +TB_ACP_NOT_SEND = 0x00000000, +TB_ACP_PKT_SEND = 0x00000001, +} HDMI_TB_ENC_ACP_SEND; + +/* + * HDMI_TB_ENC_ACR_AUDIO_PRIORITY enum + */ + +typedef enum HDMI_TB_ENC_ACR_AUDIO_PRIORITY { +TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000, +TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001, +} HDMI_TB_ENC_ACR_AUDIO_PRIORITY; + +/* + * HDMI_TB_ENC_ACR_CONT enum + */ + +typedef enum HDMI_TB_ENC_ACR_CONT { +TB_ACR_CONT_DISABLE = 0x00000000, +TB_ACR_CONT_ENABLE = 0x00000001, +} HDMI_TB_ENC_ACR_CONT; + +/* + * HDMI_TB_ENC_ACR_N_MULTIPLE enum + */ + +typedef enum HDMI_TB_ENC_ACR_N_MULTIPLE { +TB_ACR_0_MULTIPLE_RESERVED = 0x00000000, +TB_ACR_1_MULTIPLE = 0x00000001, +TB_ACR_2_MULTIPLE = 0x00000002, +TB_ACR_3_MULTIPLE_RESERVED = 0x00000003, +TB_ACR_4_MULTIPLE = 0x00000004, +TB_ACR_5_MULTIPLE_RESERVED = 0x00000005, +TB_ACR_6_MULTIPLE_RESERVED = 0x00000006, +TB_ACR_7_MULTIPLE_RESERVED = 0x00000007, +} HDMI_TB_ENC_ACR_N_MULTIPLE; + +/* + * HDMI_TB_ENC_ACR_SELECT enum + */ + +typedef enum HDMI_TB_ENC_ACR_SELECT { +TB_ACR_SELECT_HW = 0x00000000, +TB_ACR_SELECT_32K = 0x00000001, +TB_ACR_SELECT_44K = 0x00000002, +TB_ACR_SELECT_48K = 0x00000003, +} HDMI_TB_ENC_ACR_SELECT; + +/* + * HDMI_TB_ENC_ACR_SEND enum + */ + +typedef enum HDMI_TB_ENC_ACR_SEND { +TB_ACR_NOT_SEND = 0x00000000, +TB_ACR_PKT_SEND = 0x00000001, +} HDMI_TB_ENC_ACR_SEND; + +/* + * HDMI_TB_ENC_ACR_SOURCE enum + */ + +typedef enum HDMI_TB_ENC_ACR_SOURCE { +TB_ACR_SOURCE_HW = 0x00000000, +TB_ACR_SOURCE_SW = 0x00000001, +} HDMI_TB_ENC_ACR_SOURCE; + +/* + * HDMI_TB_ENC_AUDIO_INFO_CONT enum + */ + +typedef enum HDMI_TB_ENC_AUDIO_INFO_CONT { +TB_AUDIO_INFO_CONT_DISABLE = 0x00000000, +TB_AUDIO_INFO_CONT_ENABLE = 0x00000001, +} HDMI_TB_ENC_AUDIO_INFO_CONT; + +/* + * HDMI_TB_ENC_AUDIO_INFO_SEND enum + */ + +typedef enum HDMI_TB_ENC_AUDIO_INFO_SEND { +TB_AUDIO_INFO_NOT_SEND = 0x00000000, +TB_AUDIO_INFO_PKT_SEND = 0x00000001, +} HDMI_TB_ENC_AUDIO_INFO_SEND; + +/* + * HDMI_TB_ENC_CRC_SRC_SEL enum + */ + +typedef enum HDMI_TB_ENC_CRC_SRC_SEL { +TB_CRC_TB_ENC_INPUT = 0x00000000, +TB_CRC_DSC_PACKER = 0x00000001, +TB_CRC_DEEP_COLOR_PACKER = 0x00000002, +TB_CRC_ENCRYPTOR_INPUT = 0x00000003, +} HDMI_TB_ENC_CRC_SRC_SEL; + +/* + * HDMI_TB_ENC_CRC_TYPE enum + */ + +typedef enum HDMI_TB_ENC_CRC_TYPE { +TB_CRC_ALL_TRIBYTES = 0x00000000, +TB_CRC_ACTIVE_TRIBYTES = 0x00000001, +TB_CRC_DATAISLAND_TRIBYTES = 0x00000002, +TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 0x00000003, +} HDMI_TB_ENC_CRC_TYPE; + +/* + * HDMI_TB_ENC_DEEP_COLOR_DEPTH enum + */ + +typedef enum HDMI_TB_ENC_DEEP_COLOR_DEPTH { +TB_DEEP_COLOR_DEPTH_24BPP = 0x00000000, +TB_DEEP_COLOR_DEPTH_30BPP = 0x00000001, +TB_DEEP_COLOR_DEPTH_36BPP = 0x00000002, +TB_DEEP_COLOR_DEPTH_RESERVED = 0x00000003, +} HDMI_TB_ENC_DEEP_COLOR_DEPTH; + +/* + * HDMI_TB_ENC_DEFAULT_PAHSE enum + */ + +typedef enum HDMI_TB_ENC_DEFAULT_PAHSE { +TB_DEFAULT_PHASE_IS_0 = 0x00000000, +TB_DEFAULT_PHASE_IS_1 = 0x00000001, +} HDMI_TB_ENC_DEFAULT_PAHSE; + +/* + * HDMI_TB_ENC_DSC_MODE enum + */ + +typedef enum HDMI_TB_ENC_DSC_MODE { +TB_DSC_DISABLE = 0x00000000, +TB_DSC_444_RGB = 0x00000001, +TB_DSC_NATIVE_422_420 = 0x00000002, +} HDMI_TB_ENC_DSC_MODE; + +/* + * HDMI_TB_ENC_ENABLE enum + */ + +typedef enum HDMI_TB_ENC_ENABLE { +TB_DISABLE = 0x00000000, +TB_ENABLE = 0x00000001, +} HDMI_TB_ENC_ENABLE; + +/* + * HDMI_TB_ENC_GC_AVMUTE enum + */ + +typedef enum HDMI_TB_ENC_GC_AVMUTE { +TB_GC_AVMUTE_SET = 0x00000000, +TB_GC_AVMUTE_UNSET = 0x00000001, +} HDMI_TB_ENC_GC_AVMUTE; + +/* + * HDMI_TB_ENC_GC_AVMUTE_CONT enum + */ + +typedef enum HDMI_TB_ENC_GC_AVMUTE_CONT { +TB_GC_AVMUTE_CONT_DISABLE = 0x00000000, +TB_GC_AVMUTE_CONT_ENABLE = 0x00000001, +} HDMI_TB_ENC_GC_AVMUTE_CONT; + +/* + * HDMI_TB_ENC_GC_CONT enum + */ + +typedef enum HDMI_TB_ENC_GC_CONT { +TB_GC_CONT_DISABLE = 0x00000000, +TB_GC_CONT_ENABLE = 0x00000001, +} HDMI_TB_ENC_GC_CONT; + +/* + * HDMI_TB_ENC_GC_SEND enum + */ + +typedef enum HDMI_TB_ENC_GC_SEND { +TB_GC_NOT_SEND = 0x00000000, +TB_GC_PKT_SEND = 0x00000001, +} HDMI_TB_ENC_GC_SEND; + +/* + * HDMI_TB_ENC_GENERIC_CONT enum + */ + +typedef enum HDMI_TB_ENC_GENERIC_CONT { +TB_GENERIC_CONT_DISABLE = 0x00000000, +TB_GENERIC_CONT_ENABLE = 0x00000001, +} HDMI_TB_ENC_GENERIC_CONT; + +/* + * HDMI_TB_ENC_GENERIC_LOCK_EN enum + */ + +typedef enum HDMI_TB_ENC_GENERIC_LOCK_EN { +HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0x00000000, +HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 0x00000001, +} HDMI_TB_ENC_GENERIC_LOCK_EN; + +/* + * HDMI_TB_ENC_GENERIC_SEND enum + */ + +typedef enum HDMI_TB_ENC_GENERIC_SEND { +TB_GENERIC_NOT_SEND = 0x00000000, +TB_GENERIC_PKT_SEND = 0x00000001, +} HDMI_TB_ENC_GENERIC_SEND; + +/* + * HDMI_TB_ENC_ISRC_CONT enum + */ + +typedef enum HDMI_TB_ENC_ISRC_CONT { +TB_ISRC_CONT_DISABLE = 0x00000000, +TB_ISRC_CONT_ENABLE = 0x00000001, +} HDMI_TB_ENC_ISRC_CONT; + +/* + * HDMI_TB_ENC_ISRC_SEND enum + */ + +typedef enum HDMI_TB_ENC_ISRC_SEND { +TB_ISRC_NOT_SEND = 0x00000000, +TB_ISRC_PKT_SEND = 0x00000001, +} HDMI_TB_ENC_ISRC_SEND; + +/* + * HDMI_TB_ENC_METADATA_ENABLE enum + */ + +typedef enum HDMI_TB_ENC_METADATA_ENABLE { +TB_METADATA_NOT_SEND = 0x00000000, +TB_METADATA_PKT_SEND = 0x00000001, +} HDMI_TB_ENC_METADATA_ENABLE; + +/* + * HDMI_TB_ENC_PACKET_LINE_REFERENCE enum + */ + +typedef enum HDMI_TB_ENC_PACKET_LINE_REFERENCE { +TB_PKT_LINE_REF_END_OF_ACTIVE = 0x00000000, +TB_PKT_LINE_REF_OTGSOF = 0x00000001, +} HDMI_TB_ENC_PACKET_LINE_REFERENCE; + +/* + * HDMI_TB_ENC_PIXEL_ENCODING enum + */ + +typedef enum HDMI_TB_ENC_PIXEL_ENCODING { +TB_PIXEL_ENCODING_444_RGB = 0x00000000, +TB_PIXEL_ENCODING_422 = 0x00000001, +TB_PIXEL_ENCODING_420 = 0x00000002, +} HDMI_TB_ENC_PIXEL_ENCODING; + +/* + * HDMI_TB_ENC_RESET enum + */ + +typedef enum HDMI_TB_ENC_RESET { +TB_NOT_RESET = 0x00000000, +TB_RESET = 0x00000001, +} HDMI_TB_ENC_RESET; + +/* + * HDMI_TB_ENC_SYNC_PHASE enum + */ + +typedef enum HDMI_TB_ENC_SYNC_PHASE { +TB_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000, +TB_SYNC_PHASE_ON_FRAME_START = 0x00000001, +} HDMI_TB_ENC_SYNC_PHASE; + +/* + * INPUT_FIFO_ERROR_TYPE enum + */ + +typedef enum INPUT_FIFO_ERROR_TYPE { +TB_NO_ERROR_OCCURRED = 0x00000000, +TB_OVERFLOW_OCCURRED = 0x00000001, +} INPUT_FIFO_ERROR_TYPE; + +/******************************************************* + * DP_STREAM_ENC Enums + *******************************************************/ + +/* + * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum + */ + +typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR { +DP_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000, +DP_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001, +DP_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002, +} DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR; + +/* + * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum + */ + +typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT { +DP_STREAM_ENC_HARDWARE = 0x00000000, +DP_STREAM_ENC_PROGRAMMABLE = 0x00000001, +} DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT; + +/* + * DP_STREAM_ENC_READ_CLOCK_CONTROL enum + */ + +typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL { +DP_STREAM_ENC_DCCG = 0x00000000, +DP_STREAM_ENC_DISPLAY_PIPE = 0x00000001, +} DP_STREAM_ENC_READ_CLOCK_CONTROL; + +/* + * DP_STREAM_ENC_RESET_CONTROL enum + */ + +typedef enum DP_STREAM_ENC_RESET_CONTROL { +DP_STREAM_ENC_NOT_RESET = 0x00000000, +DP_STREAM_ENC_RESET = 0x00000001, +} DP_STREAM_ENC_RESET_CONTROL; + +/* + * DP_STREAM_ENC_STREAM_ACTIVE enum + */ + +typedef enum DP_STREAM_ENC_STREAM_ACTIVE { +DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000, +DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001, +} DP_STREAM_ENC_STREAM_ACTIVE; + +/******************************************************* + * DP_SYM32_ENC Enums + *******************************************************/ + +/* + * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum + */ + +typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE { +DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0x00000000, +DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 0x00000001, +} ENUM_DP_SYM32_ENC_AUDIO_MUTE; + +/* + * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum + */ + +typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE { +DP_SYM32_ENC_ONE_SHOT_MODE = 0x00000000, +DP_SYM32_ENC_CONTINUOUS_MODE = 0x00000001, +} ENUM_DP_SYM32_ENC_CONTINUOUS_MODE; + +/* + * ENUM_DP_SYM32_ENC_CRC_VALID enum + */ + +typedef enum ENUM_DP_SYM32_ENC_CRC_VALID { +DP_SYM32_ENC_CRC_NOT_VALID = 0x00000000, +DP_SYM32_ENC_CRC_VALID = 0x00000001, +} ENUM_DP_SYM32_ENC_CRC_VALID; + +/* + * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum + */ + +typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH { +DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0x00000000, +DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 0x00000001, +DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 0x00000002, +DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 0x00000003, +} ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH; + +/* + * ENUM_DP_SYM32_ENC_ENABLE enum + */ + +typedef enum ENUM_DP_SYM32_ENC_ENABLE { +DP_SYM32_ENC_DISABLE = 0x00000000, +DP_SYM32_ENC_ENABLE = 0x00000001, +} ENUM_DP_SYM32_ENC_ENABLE; + +/* + * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum + */ + +typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED { +DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0x00000000, +DP_SYM32_ENC_GSP_DEADLINE_MISSED = 0x00000001, +} ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED; + +/* + * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum + */ + +typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION { +DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0x00000000, +DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 0x00000001, +} ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION; + +/* + * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum + */ + +typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE { +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0x00000000, +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 0x00000001, +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 0x00000002, +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 0x00000003, +} ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE; + +/* + * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum + */ + +typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING { +DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0x00000000, +DP_SYM32_ENC_GSP_TRIGGER_PENDING = 0x00000001, +} ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING; + +/* + * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum + */ + +typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM { +DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0x00000000, +DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM; + +/* + * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum + */ + +typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS { +DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0x00000000, +DP_SYM32_ENC_OVERFLOW_OCCURRED = 0x00000001, +} ENUM_DP_SYM32_ENC_OVERFLOW_STATUS; + +/* + * ENUM_DP_SYM32_ENC_PENDING enum + */ + +typedef enum ENUM_DP_SYM32_ENC_PENDING { +DP_SYM32_ENC_NOT_PENDING = 0x00000000, +DP_SYM32_ENC_PENDING = 0x00000001, +} ENUM_DP_SYM32_ENC_PENDING; + +/* + * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum + */ + +typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING { +DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000, +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 0x00000001, +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 0x00000002, +DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 0x00000003, +} ENUM_DP_SYM32_ENC_PIXEL_ENCODING; + +/* + * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum + */ + +typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE { +DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0x00000000, +DP_SYM32_ENC_COMPRESSED_FORMAT = 0x00000001, +} ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE; + +/* + * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum + */ + +typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM { +DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0x00000000, +DP_SYM32_ENC_POWER_STATE_ENUM_LS = 0x00000001, +DP_SYM32_ENC_POWER_STATE_ENUM_DS = 0x00000002, +DP_SYM32_ENC_POWER_STATE_ENUM_SD = 0x00000003, +} ENUM_DP_SYM32_ENC_POWER_STATE_ENUM; + +/* + * ENUM_DP_SYM32_ENC_RESET enum + */ + +typedef enum ENUM_DP_SYM32_ENC_RESET { +DP_SYM32_ENC_NOT_RESET = 0x00000000, +DP_SYM32_ENC_RESET = 0x00000001, +} ENUM_DP_SYM32_ENC_RESET; + +/* + * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum + */ + +typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY { +DP_SYM32_ENC_SDP_LOW_PRIORITY = 0x00000000, +DP_SYM32_ENC_SDP_HIGH_PRIORITY = 0x00000001, +} ENUM_DP_SYM32_ENC_SDP_PRIORITY; + +/* + * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum + */ + +typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE { +DP_SYM32_ENC_DP_SOF = 0x00000000, +DP_SYM32_ENC_OTG_SOF = 0x00000001, +} ENUM_DP_SYM32_ENC_SOF_REFERENCE; + +/* + * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum + */ + +typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER { +DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0x00000000, +DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 0x00000001, +DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 0x00000002, +} ENUM_DP_SYM32_ENC_VID_STREAM_DEFER; + +/******************************************************* + * DP_DPHY_SYM32 Enums + *******************************************************/ + +/* + * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT { +DP_DPHY_SYM32_CRC_END_LLCP = 0x00000000, +DP_DPHY_SYM32_CRC_END_PS_ONLY = 0x00000001, +DP_DPHY_SYM32_CRC_END_PS_LT_SR = 0x00000002, +DP_DPHY_SYM32_CRC_END_PS_ANY = 0x00000003, +} ENUM_DP_DPHY_SYM32_CRC_END_EVENT; + +/* + * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT { +DP_DPHY_SYM32_CRC_START_LLCP = 0x00000000, +DP_DPHY_SYM32_CRC_START_PS_ONLY = 0x00000001, +DP_DPHY_SYM32_CRC_START_PS_LT_SR = 0x00000002, +DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 0x00000003, +DP_DPHY_SYM32_CRC_START_TP_START = 0x00000004, +} ENUM_DP_DPHY_SYM32_CRC_START_EVENT; + +/* + * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE { +DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0x00000000, +DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 0x00000001, +DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 0x00000002, +} ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE; + +/* + * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS { +DP_DPHY_SYM32_CRC_USE_END_EVENT = 0x00000000, +DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 0x00000001, +} ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS; + +/* + * ENUM_DP_DPHY_SYM32_ENABLE enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_ENABLE { +DP_DPHY_SYM32_DISABLE = 0x00000000, +DP_DPHY_SYM32_ENABLE = 0x00000001, +} ENUM_DP_DPHY_SYM32_ENABLE; + +/* + * ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE { +DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0x00000000, +DP_DPHY_SYM32_ENCRYPT_TYPE1 = 0x00000001, +} ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE; + +/* + * ENUM_DP_DPHY_SYM32_MODE enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_MODE { +DP_DPHY_SYM32_LT_TPS1 = 0x00000000, +DP_DPHY_SYM32_LT_TPS2 = 0x00000001, +DP_DPHY_SYM32_ACTIVE = 0x00000002, +DP_DPHY_SYM32_TEST = 0x00000003, +} ENUM_DP_DPHY_SYM32_MODE; + +/* + * ENUM_DP_DPHY_SYM32_NUM_LANES enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES { +DP_DPHY_SYM32_1LANE = 0x00000000, +DP_DPHY_SYM32_2LANE = 0x00000001, +DP_DPHY_SYM32_RESERVED = 0x00000002, +DP_DPHY_SYM32_4LANE = 0x00000003, +} ENUM_DP_DPHY_SYM32_NUM_LANES; + +/* + * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING { +DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0x00000000, +DP_DPHY_SYM32_RATE_UPDATE_PENDING = 0x00000001, +} ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING; + +/* + * ENUM_DP_DPHY_SYM32_RESET enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_RESET { +DP_DPHY_SYM32_NOT_RESET = 0x00000000, +DP_DPHY_SYM32_RESET = 0x00000001, +} ENUM_DP_DPHY_SYM32_RESET; + +/* + * ENUM_DP_DPHY_SYM32_RESET_STATUS enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS { +DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0x00000000, +DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 0x00000001, +} ENUM_DP_DPHY_SYM32_RESET_STATUS; + +/* + * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE { +DP_DPHY_SYM32_SAT_NO_UPDATE = 0x00000000, +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 0x00000001, +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 0x00000002, +} ENUM_DP_DPHY_SYM32_SAT_UPDATE; + +/* + * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING { +DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0x00000000, +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 0x00000001, +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 0x00000002, +} ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING; + +/* + * ENUM_DP_DPHY_SYM32_STATUS enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_STATUS { +DP_DPHY_SYM32_STATUS_IDLE = 0x00000000, +DP_DPHY_SYM32_STATUS_ENABLED = 0x00000001, +} ENUM_DP_DPHY_SYM32_STATUS; + +/* + * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE { +DP_DPHY_SYM32_STREAM_OVR_NONE = 0x00000000, +DP_DPHY_SYM32_STREAM_OVR_REPLACE = 0x00000001, +DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 0x00000002, +} ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE; + +/* + * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE { +DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0x00000000, +DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 0x00000001, +} ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE; + +/* + * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL { +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0x00000000, +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 0x00000001, +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 0x00000002, +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 0x00000003, +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 0x00000004, +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 0x00000005, +} ENUM_DP_DPHY_SYM32_TP_PRBS_SEL; + +/* + * ENUM_DP_DPHY_SYM32_TP_SELECT enum + */ + +typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT { +DP_DPHY_SYM32_TP_SELECT_TPS1 = 0x00000000, +DP_DPHY_SYM32_TP_SELECT_TPS2 = 0x00000001, +DP_DPHY_SYM32_TP_SELECT_PRBS = 0x00000002, +DP_DPHY_SYM32_TP_SELECT_CUSTOM = 0x00000003, +DP_DPHY_SYM32_TP_SELECT_SQUARE = 0x00000004, +} ENUM_DP_DPHY_SYM32_TP_SELECT; + +/******************************************************* + * APG Enums + *******************************************************/ + +/* + * APG_AUDIO_CRC_CONTROL_CH_SEL enum + */ + +typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL { +APG_AUDIO_CRC_CH0_SIG = 0x00000000, +APG_AUDIO_CRC_CH1_SIG = 0x00000001, +APG_AUDIO_CRC_CH2_SIG = 0x00000002, +APG_AUDIO_CRC_CH3_SIG = 0x00000003, +APG_AUDIO_CRC_CH4_SIG = 0x00000004, +APG_AUDIO_CRC_CH5_SIG = 0x00000005, +APG_AUDIO_CRC_CH6_SIG = 0x00000006, +APG_AUDIO_CRC_CH7_SIG = 0x00000007, +APG_AUDIO_CRC_RESERVED_8 = 0x00000008, +APG_AUDIO_CRC_RESERVED_9 = 0x00000009, +APG_AUDIO_CRC_RESERVED_10 = 0x0000000a, +APG_AUDIO_CRC_RESERVED_11 = 0x0000000b, +APG_AUDIO_CRC_RESERVED_12 = 0x0000000c, +APG_AUDIO_CRC_RESERVED_13 = 0x0000000d, +APG_AUDIO_CRC_RESERVED_14 = 0x0000000e, +APG_AUDIO_CRC_RESERVED_15 = 0x0000000f, +} APG_AUDIO_CRC_CONTROL_CH_SEL; + +/* + * APG_AUDIO_CRC_CONTROL_CONT enum + */ + +typedef enum APG_AUDIO_CRC_CONTROL_CONT { +APG_AUDIO_CRC_ONESHOT = 0x00000000, +APG_AUDIO_CRC_CONTINUOUS = 0x00000001, +} APG_AUDIO_CRC_CONTROL_CONT; + +/* + * APG_DBG_ACP_TYPE enum + */ + +typedef enum APG_DBG_ACP_TYPE { +APG_ACP_TYPE_GENERIC_AUDIO = 0x00000000, +APG_ACP_TYPE_ICE60958_AUDIO = 0x00000001, +APG_ACP_TYPE_DVD_AUDIO = 0x00000002, +APG_ACP_TYPE_SUPER_AUDIO_CD = 0x00000003, +} APG_DBG_ACP_TYPE; + +/* + * APG_DBG_AUDIO_DTO_BASE enum + */ + +typedef enum APG_DBG_AUDIO_DTO_BASE { +BASE_RATE_48KHZ = 0x00000000, +BASE_RATE_44P1KHZ = 0x00000001, +} APG_DBG_AUDIO_DTO_BASE; + +/* + * APG_DBG_AUDIO_DTO_DIV enum + */ + +typedef enum APG_DBG_AUDIO_DTO_DIV { +DIVISOR_BY1 = 0x00000000, +DIVISOR_BY2_RESERVED = 0x00000001, +DIVISOR_BY3 = 0x00000002, +DIVISOR_BY4_RESERVED = 0x00000003, +DIVISOR_BY5_RESERVED = 0x00000004, +DIVISOR_BY6_RESERVED = 0x00000005, +DIVISOR_BY7_RESERVED = 0x00000006, +DIVISOR_BY8_RESERVED = 0x00000007, +} APG_DBG_AUDIO_DTO_DIV; + +/* + * APG_DBG_AUDIO_DTO_MULTI enum + */ + +typedef enum APG_DBG_AUDIO_DTO_MULTI { +MULTIPLE_BY1 = 0x00000000, +MULTIPLE_BY2 = 0x00000001, +MULTIPLE_BY3_RESERVED = 0x00000002, +MULTIPLE_BY4 = 0x00000003, +MULTIPLE_RESERVED = 0x00000004, +} APG_DBG_AUDIO_DTO_MULTI; + +/* + * APG_DBG_MUX_SEL enum + */ + +typedef enum APG_DBG_MUX_SEL { +APG_FUNCTIONAL_MODE = 0x00000000, +APG_DEBUG_AUDIO_MODE = 0x00000001, +} APG_DBG_MUX_SEL; + +/* + * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum + */ + +typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE { +APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, +} APG_DP_ASP_CHANNEL_COUNT_OVERRIDE; + +/* + * APG_MEM_POWER_STATE enum + */ + +typedef enum APG_MEM_POWER_STATE { +APG_MEM_POWER_STATE_ON = 0x00000000, +APG_MEM_POWER_STATE_LS = 0x00000001, +APG_MEM_POWER_STATE_DS = 0x00000002, +APG_MEM_POWER_STATE_SD = 0x00000003, +} APG_MEM_POWER_STATE; + +/* + * APG_MEM_PWR_DIS_CTRL enum + */ + +typedef enum APG_MEM_PWR_DIS_CTRL { +APG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, +APG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, +} APG_MEM_PWR_DIS_CTRL; + +/* + * APG_MEM_PWR_FORCE_CTRL enum + */ + +typedef enum APG_MEM_PWR_FORCE_CTRL { +APG_MEM_NO_FORCE_REQUEST = 0x00000000, +APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +APG_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} APG_MEM_PWR_FORCE_CTRL; + +/* + * APG_PACKET_CONTROL_ACP_SOURCE enum + */ + +typedef enum APG_PACKET_CONTROL_ACP_SOURCE { +APG_ACP_SOURCE_NO_OVERRIDE = 0x00000000, +APG_ACP_OVERRIDE = 0x00000001, +} APG_PACKET_CONTROL_ACP_SOURCE; + +/* + * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum + */ + +typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE { +APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0x00000000, +APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 0x00000001, +} APG_PACKET_CONTROL_AUDIO_INFO_SOURCE; + +/* + * APG_RAMP_CONTROL_SIGN enum + */ + +typedef enum APG_RAMP_CONTROL_SIGN { +APG_RAMP_SIGNED = 0x00000000, +APG_RAMP_UNSIGNED = 0x00000001, +} APG_RAMP_CONTROL_SIGN; + +/******************************************************* + * DCIO Enums + *******************************************************/ + +/* + * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum + */ + +typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005, +} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; + +/* + * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum + */ + +typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { +DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000, +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001, +DCIO_TEST_CLK_SEL_SOCCLK = 0x00000002, +} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; + +/* + * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum + */ + +typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000, +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001, +} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; + +/* + * DCIO_DBG_ASYNC_4BIT_SEL enum + */ + +typedef enum DCIO_DBG_ASYNC_4BIT_SEL { +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000, +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001, +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002, +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003, +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004, +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005, +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006, +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007, +} DCIO_DBG_ASYNC_4BIT_SEL; + +/* + * DCIO_DBG_ASYNC_BLOCK_SEL enum + */ + +typedef enum DCIO_DBG_ASYNC_BLOCK_SEL { +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000, +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001, +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002, +DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 0x00000003, +} DCIO_DBG_ASYNC_BLOCK_SEL; + +/* + * DCIO_DCRXPHY_SOFT_RESET enum + */ + +typedef enum DCIO_DCRXPHY_SOFT_RESET { +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000, +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001, +} DCIO_DCRXPHY_SOFT_RESET; + +/* + * DCIO_DC_GENERICA_SEL enum + */ + +typedef enum DCIO_DC_GENERICA_SEL { +DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001, +DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a, +DCIO_GENERICA_SEL_SYNCEN = 0x0000000b, +} DCIO_DC_GENERICA_SEL; + +/* + * DCIO_DC_GENERICB_SEL enum + */ + +typedef enum DCIO_DC_GENERICB_SEL { +DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001, +DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a, +DCIO_GENERICB_SEL_SYNCEN = 0x0000000b, +} DCIO_DC_GENERICB_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000, +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001, +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002, +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003, +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004, +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005, +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { +DCIO_UNIPHYA_FBDIV_CLK = 0x00000000, +DCIO_UNIPHYB_FBDIV_CLK = 0x00000001, +DCIO_UNIPHYC_FBDIV_CLK = 0x00000002, +DCIO_UNIPHYD_FBDIV_CLK = 0x00000003, +DCIO_UNIPHYE_FBDIV_CLK = 0x00000004, +DCIO_UNIPHYF_FBDIV_CLK = 0x00000005, +DCIO_UNIPHYG_FBDIV_CLK = 0x00000006, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000, +DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001, +DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002, +DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003, +DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004, +DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005, +DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000, +DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001, +DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002, +DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003, +DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004, +DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005, +DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006, +} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; + +/* + * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum + */ + +typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000, +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001, +} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; + +/* + * DCIO_DC_GPU_TIMER_READ_SELECT enum + */ + +typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005, +} DCIO_DC_GPU_TIMER_READ_SELECT; + +/* + * DCIO_DC_GPU_TIMER_START_POSITION enum + */ + +typedef enum DCIO_DC_GPU_TIMER_START_POSITION { +DCIO_GPU_TIMER_START_0_END_27 = 0x00000000, +DCIO_GPU_TIMER_START_1_END_28 = 0x00000001, +DCIO_GPU_TIMER_START_2_END_29 = 0x00000002, +DCIO_GPU_TIMER_START_3_END_30 = 0x00000003, +DCIO_GPU_TIMER_START_4_END_31 = 0x00000004, +DCIO_GPU_TIMER_START_6_END_33 = 0x00000005, +DCIO_GPU_TIMER_START_8_END_35 = 0x00000006, +DCIO_GPU_TIMER_START_10_END_37 = 0x00000007, +} DCIO_DC_GPU_TIMER_START_POSITION; + +/* + * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum + */ + +typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000, +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001, +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002, +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003, +} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; + +/* + * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum + */ + +typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000, +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001, +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002, +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003, +} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; + +/* + * DCIO_DIO_EXT_VSYNC_MASK enum + */ + +typedef enum DCIO_DIO_EXT_VSYNC_MASK { +DCIO_EXT_VSYNC_MASK_NONE = 0x00000000, +DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001, +DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002, +DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003, +DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004, +DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005, +DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006, +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007, +} DCIO_DIO_EXT_VSYNC_MASK; + +/* + * DCIO_DIO_OTG_EXT_VSYNC_MUX enum + */ + +typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX { +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000, +DCIO_EXT_VSYNC_MUX_OTG0 = 0x00000001, +DCIO_EXT_VSYNC_MUX_OTG1 = 0x00000002, +DCIO_EXT_VSYNC_MUX_OTG2 = 0x00000003, +DCIO_EXT_VSYNC_MUX_OTG3 = 0x00000004, +DCIO_EXT_VSYNC_MUX_OTG4 = 0x00000005, +DCIO_EXT_VSYNC_MUX_OTG5 = 0x00000006, +DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007, +} DCIO_DIO_OTG_EXT_VSYNC_MUX; + +/* + * DCIO_DPCS_INTERRUPT_MASK enum + */ + +typedef enum DCIO_DPCS_INTERRUPT_MASK { +DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000, +DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001, +} DCIO_DPCS_INTERRUPT_MASK; + +/* + * DCIO_DPCS_INTERRUPT_TYPE enum + */ + +typedef enum DCIO_DPCS_INTERRUPT_TYPE { +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, +} DCIO_DPCS_INTERRUPT_TYPE; + +/* + * DCIO_DSYNC_SOFT_RESET enum + */ + +typedef enum DCIO_DSYNC_SOFT_RESET { +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000, +DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001, +} DCIO_DSYNC_SOFT_RESET; + +/* + * DCIO_GENLK_CLK_GSL_MASK enum + */ + +typedef enum DCIO_GENLK_CLK_GSL_MASK { +DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000, +DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001, +DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002, +} DCIO_GENLK_CLK_GSL_MASK; + +/* + * DCIO_GENLK_VSYNC_GSL_MASK enum + */ + +typedef enum DCIO_GENLK_VSYNC_GSL_MASK { +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000, +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001, +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002, +} DCIO_GENLK_VSYNC_GSL_MASK; + +/* + * DCIO_GSL_SEL enum + */ + +typedef enum DCIO_GSL_SEL { +DCIO_GSL_SEL_GROUP_0 = 0x00000000, +DCIO_GSL_SEL_GROUP_1 = 0x00000001, +DCIO_GSL_SEL_GROUP_2 = 0x00000002, +} DCIO_GSL_SEL; + +/* + * DCIO_PHY_HPO_ENC_SRC_SEL enum + */ + +typedef enum DCIO_PHY_HPO_ENC_SRC_SEL { +HPO_SRC0 = 0x00000000, +HPO_SRC_RESERVED = 0x00000001, +} DCIO_PHY_HPO_ENC_SRC_SEL; + +/* + * DCIO_SWAPLOCK_A_GSL_MASK enum + */ + +typedef enum DCIO_SWAPLOCK_A_GSL_MASK { +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000, +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001, +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002, +} DCIO_SWAPLOCK_A_GSL_MASK; + +/* + * DCIO_SWAPLOCK_B_GSL_MASK enum + */ + +typedef enum DCIO_SWAPLOCK_B_GSL_MASK { +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000, +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001, +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002, +} DCIO_SWAPLOCK_B_GSL_MASK; + +/* + * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum + */ + +typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000, +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001, +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002, +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003, +} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; + +/* + * DCIO_UNIPHY_IMPCAL_SEL enum + */ + +typedef enum DCIO_UNIPHY_IMPCAL_SEL { +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000, +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001, +} DCIO_UNIPHY_IMPCAL_SEL; + +/* + * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum + */ + +typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000, +DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001, +} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; + +/* + * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum + */ + +typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000, +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001, +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002, +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003, +} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; + +/******************************************************* + * DCIO_CHIP Enums + *******************************************************/ + +/* + * DCIOCHIP_AUX_ALL_PWR_OK enum + */ + +typedef enum DCIOCHIP_AUX_ALL_PWR_OK { +DCIOCHIP_AUX_ALL_PWR_OK_0 = 0x00000000, +DCIOCHIP_AUX_ALL_PWR_OK_1 = 0x00000001, +} DCIOCHIP_AUX_ALL_PWR_OK; + +/* + * DCIOCHIP_AUX_CSEL0P9 enum + */ + +typedef enum DCIOCHIP_AUX_CSEL0P9 { +DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000, +DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001, +} DCIOCHIP_AUX_CSEL0P9; + +/* + * DCIOCHIP_AUX_CSEL1P1 enum + */ + +typedef enum DCIOCHIP_AUX_CSEL1P1 { +DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000, +DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001, +} DCIOCHIP_AUX_CSEL1P1; + +/* + * DCIOCHIP_AUX_FALLSLEWSEL enum + */ + +typedef enum DCIOCHIP_AUX_FALLSLEWSEL { +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000, +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001, +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002, +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003, +} DCIOCHIP_AUX_FALLSLEWSEL; + +/* + * DCIOCHIP_AUX_HYS_TUNE enum + */ + +typedef enum DCIOCHIP_AUX_HYS_TUNE { +DCIOCHIP_AUX_HYS_TUNE_0 = 0x00000000, +DCIOCHIP_AUX_HYS_TUNE_1 = 0x00000001, +DCIOCHIP_AUX_HYS_TUNE_2 = 0x00000002, +DCIOCHIP_AUX_HYS_TUNE_3 = 0x00000003, +} DCIOCHIP_AUX_HYS_TUNE; + +/* + * DCIOCHIP_AUX_RECEIVER_SEL enum + */ + +typedef enum DCIOCHIP_AUX_RECEIVER_SEL { +DCIOCHIP_AUX_RECEIVER_SEL_0 = 0x00000000, +DCIOCHIP_AUX_RECEIVER_SEL_1 = 0x00000001, +DCIOCHIP_AUX_RECEIVER_SEL_2 = 0x00000002, +DCIOCHIP_AUX_RECEIVER_SEL_3 = 0x00000003, +} DCIOCHIP_AUX_RECEIVER_SEL; + +/* + * DCIOCHIP_AUX_RSEL0P9 enum + */ + +typedef enum DCIOCHIP_AUX_RSEL0P9 { +DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000, +DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001, +} DCIOCHIP_AUX_RSEL0P9; + +/* + * DCIOCHIP_AUX_RSEL1P1 enum + */ + +typedef enum DCIOCHIP_AUX_RSEL1P1 { +DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000, +DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001, +} DCIOCHIP_AUX_RSEL1P1; + +/* + * DCIOCHIP_AUX_SPIKESEL enum + */ + +typedef enum DCIOCHIP_AUX_SPIKESEL { +DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000, +DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001, +} DCIOCHIP_AUX_SPIKESEL; + +/* + * DCIOCHIP_AUX_VOD_TUNE enum + */ + +typedef enum DCIOCHIP_AUX_VOD_TUNE { +DCIOCHIP_AUX_VOD_TUNE_0 = 0x00000000, +DCIOCHIP_AUX_VOD_TUNE_1 = 0x00000001, +DCIOCHIP_AUX_VOD_TUNE_2 = 0x00000002, +DCIOCHIP_AUX_VOD_TUNE_3 = 0x00000003, +} DCIOCHIP_AUX_VOD_TUNE; + +/* + * DCIOCHIP_GPIO_MASK_EN enum + */ + +typedef enum DCIOCHIP_GPIO_MASK_EN { +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000, +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001, +} DCIOCHIP_GPIO_MASK_EN; + +/* + * DCIOCHIP_HPD_SEL enum + */ + +typedef enum DCIOCHIP_HPD_SEL { +DCIOCHIP_HPD_SEL_ASYNC = 0x00000000, +DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001, +} DCIOCHIP_HPD_SEL; + +/* + * DCIOCHIP_I2C_COMPSEL enum + */ + +typedef enum DCIOCHIP_I2C_COMPSEL { +DCIOCHIP_I2C_REC_SCHMIT = 0x00000000, +DCIOCHIP_I2C_REC_COMPARATOR = 0x00000001, +} DCIOCHIP_I2C_COMPSEL; + +/* + * DCIOCHIP_I2C_FALLSLEWSEL enum + */ + +typedef enum DCIOCHIP_I2C_FALLSLEWSEL { +DCIOCHIP_I2C_FALLSLEWSEL_00 = 0x00000000, +DCIOCHIP_I2C_FALLSLEWSEL_01 = 0x00000001, +DCIOCHIP_I2C_FALLSLEWSEL_10 = 0x00000002, +DCIOCHIP_I2C_FALLSLEWSEL_11 = 0x00000003, +} DCIOCHIP_I2C_FALLSLEWSEL; + +/* + * DCIOCHIP_I2C_RECEIVER_SEL enum + */ + +typedef enum DCIOCHIP_I2C_RECEIVER_SEL { +DCIOCHIP_I2C_RECEIVER_SEL_0 = 0x00000000, +DCIOCHIP_I2C_RECEIVER_SEL_1 = 0x00000001, +DCIOCHIP_I2C_RECEIVER_SEL_2 = 0x00000002, +DCIOCHIP_I2C_RECEIVER_SEL_3 = 0x00000003, +} DCIOCHIP_I2C_RECEIVER_SEL; + +/* + * DCIOCHIP_I2C_VPH_1V2_EN enum + */ + +typedef enum DCIOCHIP_I2C_VPH_1V2_EN { +DCIOCHIP_I2C_VPH_1V2_EN_0 = 0x00000000, +DCIOCHIP_I2C_VPH_1V2_EN_1 = 0x00000001, +} DCIOCHIP_I2C_VPH_1V2_EN; + +/* + * DCIOCHIP_INVERT enum + */ + +typedef enum DCIOCHIP_INVERT { +DCIOCHIP_POL_NON_INVERT = 0x00000000, +DCIOCHIP_POL_INVERT = 0x00000001, +} DCIOCHIP_INVERT; + +/* + * DCIOCHIP_MASK enum + */ + +typedef enum DCIOCHIP_MASK { +DCIOCHIP_MASK_DISABLE = 0x00000000, +DCIOCHIP_MASK_ENABLE = 0x00000001, +} DCIOCHIP_MASK; + +/* + * DCIOCHIP_PAD_MODE enum + */ + +typedef enum DCIOCHIP_PAD_MODE { +DCIOCHIP_PAD_MODE_DDC = 0x00000000, +DCIOCHIP_PAD_MODE_DP = 0x00000001, +} DCIOCHIP_PAD_MODE; + +/* + * DCIOCHIP_PD_EN enum + */ + +typedef enum DCIOCHIP_PD_EN { +DCIOCHIP_PD_EN_NOTALLOW = 0x00000000, +DCIOCHIP_PD_EN_ALLOW = 0x00000001, +} DCIOCHIP_PD_EN; + +/* + * DCIOCHIP_REF_27_SRC_SEL enum + */ + +typedef enum DCIOCHIP_REF_27_SRC_SEL { +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000, +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001, +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002, +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003, +} DCIOCHIP_REF_27_SRC_SEL; + +/******************************************************* + * PWRSEQ Enums + *******************************************************/ + +/* + * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum + */ + +typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000, +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001, +} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; + +/* + * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum + */ + +typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN { +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0x00000000, +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 0x00000001, +} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN; + +/* + * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum + */ + +typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000, +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001, +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002, +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003, +} PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; + +/* + * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum + */ + +typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN { +PWRSEQ_BL_PWM_DISABLE = 0x00000000, +PWRSEQ_BL_PWM_ENABLE = 0x00000001, +} PWRSEQ_BL_PWM_CNTL_BL_PWM_EN; + +/* + * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum + */ + +typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { +PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0x00000000, +PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 0x00000001, +} PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; + +/* + * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum + */ + +typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000, +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001, +} PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; + +/* + * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum + */ + +typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000, +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001, +} PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; + +/* + * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum + */ + +typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK { +PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000, +PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001, +} PWRSEQ_BL_PWM_GRP1_REG_LOCK; + +/* + * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum + */ + +typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START { +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000, +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001, +} PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START; + +/* + * PWRSEQ_GPIO_MASK_EN enum + */ + +typedef enum PWRSEQ_GPIO_MASK_EN { +PWRSEQ_GPIO_MASK_EN_HARDWARE = 0x00000000, +PWRSEQ_GPIO_MASK_EN_SOFTWARE = 0x00000001, +} PWRSEQ_GPIO_MASK_EN; + +/* + * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum + */ + +typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON { +PWRSEQ_PANEL_BLON_OFF = 0x00000000, +PWRSEQ_PANEL_BLON_ON = 0x00000001, +} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON; + +/* + * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum + */ + +typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL { +PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0x00000000, +PWRSEQ_PANEL_BLON_POL_INVERT = 0x00000001, +} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL; + +/* + * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum + */ + +typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON { +PWRSEQ_PANEL_DIGON_OFF = 0x00000000, +PWRSEQ_PANEL_DIGON_ON = 0x00000001, +} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON; + +/* + * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum + */ + +typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL { +PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0x00000000, +PWRSEQ_PANEL_DIGON_POL_INVERT = 0x00000001, +} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL; + +/* + * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum + */ + +typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL { +PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0x00000000, +PWRSEQ_PANEL_SYNCEN_POL_INVERT = 0x00000001, +} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL; + +/* + * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum + */ + +typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE { +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000, +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001, +} PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE; + +/* + * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum + */ + +typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN { +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0x00000000, +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001, +} PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN; + +/******************************************************* + * AZCONTROLLER Enums + *******************************************************/ + +/* + * AZ_CORB_SIZE enum + */ + +typedef enum AZ_CORB_SIZE { +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000, +AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001, +AZ_CORB_SIZE_256ENTRIES = 0x00000002, +AZ_CORB_SIZE_RESERVED = 0x00000003, +} AZ_CORB_SIZE; + +/* + * AZ_GLOBAL_CAPABILITIES enum + */ + +typedef enum AZ_GLOBAL_CAPABILITIES { +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000, +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001, +} AZ_GLOBAL_CAPABILITIES; + +/* + * AZ_RIRB_SIZE enum + */ + +typedef enum AZ_RIRB_SIZE { +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000, +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001, +AZ_RIRB_SIZE_256ENTRIES = 0x00000002, +AZ_RIRB_SIZE_UNDEFINED = 0x00000003, +} AZ_RIRB_SIZE; + +/* + * AZ_RIRB_WRITE_POINTER_RESET enum + */ + +typedef enum AZ_RIRB_WRITE_POINTER_RESET { +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000, +AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001, +} AZ_RIRB_WRITE_POINTER_RESET; + +/* + * AZ_STATE_CHANGE_STATUS enum + */ + +typedef enum AZ_STATE_CHANGE_STATUS { +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000, +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001, +} AZ_STATE_CHANGE_STATUS; + +/* + * CORB_READ_POINTER_RESET enum + */ + +typedef enum CORB_READ_POINTER_RESET { +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000, +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001, +} CORB_READ_POINTER_RESET; + +/* + * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum + */ + +typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000, +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001, +} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS; + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; + +/* + * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum + */ + +typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000, +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001, +} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; + +/* + * GLOBAL_CONTROL_CONTROLLER_RESET enum + */ + +typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000, +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001, +} GLOBAL_CONTROL_CONTROLLER_RESET; + +/* + * GLOBAL_CONTROL_FLUSH_CONTROL enum + */ + +typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000, +FLUSH_CONTROL_FLUSH_STARTED = 0x00000001, +} GLOBAL_CONTROL_FLUSH_CONTROL; + +/* + * GLOBAL_STATUS_FLUSH_STATUS enum + */ + +typedef enum GLOBAL_STATUS_FLUSH_STATUS { +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000, +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001, +} GLOBAL_STATUS_FLUSH_STATUS; + +/* + * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum + */ + +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000, +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; + +/* + * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum + */ + +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000, +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; + +/* + * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum + */ + +typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, +} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; + +/* + * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum + */ + +typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, +} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; + +/* + * STREAM_0_SYNCHRONIZATION enum + */ + +typedef enum STREAM_0_SYNCHRONIZATION { +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_0_SYNCHRONIZATION; + +/* + * STREAM_10_SYNCHRONIZATION enum + */ + +typedef enum STREAM_10_SYNCHRONIZATION { +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_10_SYNCHRONIZATION; + +/* + * STREAM_11_SYNCHRONIZATION enum + */ + +typedef enum STREAM_11_SYNCHRONIZATION { +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_11_SYNCHRONIZATION; + +/* + * STREAM_12_SYNCHRONIZATION enum + */ + +typedef enum STREAM_12_SYNCHRONIZATION { +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_12_SYNCHRONIZATION; + +/* + * STREAM_13_SYNCHRONIZATION enum + */ + +typedef enum STREAM_13_SYNCHRONIZATION { +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_13_SYNCHRONIZATION; + +/* + * STREAM_14_SYNCHRONIZATION enum + */ + +typedef enum STREAM_14_SYNCHRONIZATION { +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_14_SYNCHRONIZATION; + +/* + * STREAM_15_SYNCHRONIZATION enum + */ + +typedef enum STREAM_15_SYNCHRONIZATION { +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_15_SYNCHRONIZATION; + +/* + * STREAM_1_SYNCHRONIZATION enum + */ + +typedef enum STREAM_1_SYNCHRONIZATION { +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_1_SYNCHRONIZATION; + +/* + * STREAM_2_SYNCHRONIZATION enum + */ + +typedef enum STREAM_2_SYNCHRONIZATION { +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_2_SYNCHRONIZATION; + +/* + * STREAM_3_SYNCHRONIZATION enum + */ + +typedef enum STREAM_3_SYNCHRONIZATION { +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_3_SYNCHRONIZATION; + +/* + * STREAM_4_SYNCHRONIZATION enum + */ + +typedef enum STREAM_4_SYNCHRONIZATION { +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_4_SYNCHRONIZATION; + +/* + * STREAM_5_SYNCHRONIZATION enum + */ + +typedef enum STREAM_5_SYNCHRONIZATION { +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_5_SYNCHRONIZATION; + +/* + * STREAM_6_SYNCHRONIZATION enum + */ + +typedef enum STREAM_6_SYNCHRONIZATION { +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_6_SYNCHRONIZATION; + +/* + * STREAM_7_SYNCHRONIZATION enum + */ + +typedef enum STREAM_7_SYNCHRONIZATION { +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_7_SYNCHRONIZATION; + +/* + * STREAM_8_SYNCHRONIZATION enum + */ + +typedef enum STREAM_8_SYNCHRONIZATION { +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_8_SYNCHRONIZATION; + +/* + * STREAM_9_SYNCHRONIZATION enum + */ + +typedef enum STREAM_9_SYNCHRONIZATION { +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_9_SYNCHRONIZATION; + +/******************************************************* + * AZENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE { +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e, +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f, +} AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; + +/******************************************************* + * AZF0CONTROLLER Enums + *******************************************************/ + +/* + * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum + */ + +typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET { +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000, +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001, +} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET; + +/* + * MEM_PWR_DIS_CTRL enum + */ + +typedef enum MEM_PWR_DIS_CTRL { +ENABLE_MEM_PWR_CTRL = 0x00000000, +DISABLE_MEM_PWR_CTRL = 0x00000001, +} MEM_PWR_DIS_CTRL; + +/* + * MEM_PWR_FORCE_CTRL enum + */ + +typedef enum MEM_PWR_FORCE_CTRL { +NO_FORCE_REQUEST = 0x00000000, +FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} MEM_PWR_FORCE_CTRL; + +/* + * MEM_PWR_FORCE_CTRL2 enum + */ + +typedef enum MEM_PWR_FORCE_CTRL2 { +NO_FORCE_REQ = 0x00000000, +FORCE_LIGHT_SLEEP_REQ = 0x00000001, +} MEM_PWR_FORCE_CTRL2; + +/* + * MEM_PWR_SEL_CTRL enum + */ + +typedef enum MEM_PWR_SEL_CTRL { +DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, +DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, +DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, +} MEM_PWR_SEL_CTRL; + +/* + * MEM_PWR_SEL_CTRL2 enum + */ + +typedef enum MEM_PWR_SEL_CTRL2 { +DYNAMIC_DEEP_SLEEP_EN = 0x00000000, +DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, +} MEM_PWR_SEL_CTRL2; + +/******************************************************* + * AZF0ROOT Enums + *******************************************************/ + +/* + * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum + */ + +typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007, +} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; + +/* + * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum + */ + +typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007, +} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; + +/******************************************************* + * AZINPUTENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; + +/******************************************************* + * AZROOT Enums + *******************************************************/ + +/* + * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum + */ + +typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000, +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001, +} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; + +/******************************************************* + * AZF0STREAM Enums + *******************************************************/ + +/* + * AZ_LATENCY_COUNTER_CONTROL enum + */ + +typedef enum AZ_LATENCY_COUNTER_CONTROL { +AZ_LATENCY_COUNTER_NO_RESET = 0x00000000, +AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001, +} AZ_LATENCY_COUNTER_CONTROL; + +/******************************************************* + * AZSTREAM Enums + *******************************************************/ + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; + +/******************************************************* + * AZF0ENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, +} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; + +/* + * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; + +/******************************************************* + * AZF0INPUTENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; + +/******************************************************* + * DSCC Enums + *******************************************************/ + +/* + * DSCC_BITS_PER_COMPONENT_ENUM enum + */ + +typedef enum DSCC_BITS_PER_COMPONENT_ENUM { +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, +} DSCC_BITS_PER_COMPONENT_ENUM; + +/* + * DSCC_DSC_VERSION_MAJOR_ENUM enum + */ + +typedef enum DSCC_DSC_VERSION_MAJOR_ENUM { +DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001, +} DSCC_DSC_VERSION_MAJOR_ENUM; + +/* + * DSCC_DSC_VERSION_MINOR_ENUM enum + */ + +typedef enum DSCC_DSC_VERSION_MINOR_ENUM { +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001, +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002, +} DSCC_DSC_VERSION_MINOR_ENUM; + +/* + * DSCC_ENABLE_ENUM enum + */ + +typedef enum DSCC_ENABLE_ENUM { +DSCC_ENABLE_ENUM_DISABLED = 0x00000000, +DSCC_ENABLE_ENUM_ENABLED = 0x00000001, +} DSCC_ENABLE_ENUM; + +/* + * DSCC_ICH_RESET_ENUM enum + */ + +typedef enum DSCC_ICH_RESET_ENUM { +DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 0x00000001, +DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 0x00000002, +DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 0x00000004, +DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 0x00000008, +} DSCC_ICH_RESET_ENUM; + +/* + * DSCC_LINEBUF_DEPTH_ENUM enum + */ + +typedef enum DSCC_LINEBUF_DEPTH_ENUM { +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008, +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009, +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a, +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b, +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c, +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d, +} DSCC_LINEBUF_DEPTH_ENUM; + +/* + * DSCC_MEM_PWR_DIS_ENUM enum + */ + +typedef enum DSCC_MEM_PWR_DIS_ENUM { +DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0x00000000, +DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 0x00000001, +} DSCC_MEM_PWR_DIS_ENUM; + +/* + * DSCC_MEM_PWR_FORCE_ENUM enum + */ + +typedef enum DSCC_MEM_PWR_FORCE_ENUM { +DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000, +DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} DSCC_MEM_PWR_FORCE_ENUM; + +/* + * POWER_STATE_ENUM enum + */ + +typedef enum POWER_STATE_ENUM { +POWER_STATE_ENUM_ON = 0x00000000, +POWER_STATE_ENUM_LS = 0x00000001, +POWER_STATE_ENUM_DS = 0x00000002, +POWER_STATE_ENUM_SD = 0x00000003, +} POWER_STATE_ENUM; + +/******************************************************* + * DSCCIF Enums + *******************************************************/ + +/* + * DSCCIF_BITS_PER_COMPONENT_ENUM enum + */ + +typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM { +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, +} DSCCIF_BITS_PER_COMPONENT_ENUM; + +/* + * DSCCIF_ENABLE_ENUM enum + */ + +typedef enum DSCCIF_ENABLE_ENUM { +DSCCIF_ENABLE_ENUM_DISABLED = 0x00000000, +DSCCIF_ENABLE_ENUM_ENABLED = 0x00000001, +} DSCCIF_ENABLE_ENUM; + +/* + * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum + */ + +typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM { +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0x00000000, +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001, +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002, +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003, +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004, +} DSCCIF_INPUT_PIXEL_FORMAT_ENUM; + +/******************************************************* + * DSC_TOP Enums + *******************************************************/ + +/* + * CLOCK_GATING_DISABLE_ENUM enum + */ + +typedef enum CLOCK_GATING_DISABLE_ENUM { +CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000, +CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001, +} CLOCK_GATING_DISABLE_ENUM; + +/* + * ENABLE_ENUM enum + */ + +typedef enum ENABLE_ENUM { +ENABLE_ENUM_DISABLED = 0x00000000, +ENABLE_ENUM_ENABLED = 0x00000001, +} ENABLE_ENUM; + +/* + * TEST_CLOCK_MUX_SELECT_ENUM enum + */ + +typedef enum TEST_CLOCK_MUX_SELECT_ENUM { +TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000, +TEST_CLOCK_MUX_SELECT_DISPCLK_G = 0x00000001, +TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000002, +TEST_CLOCK_MUX_SELECT_DSCCLK_P = 0x00000003, +TEST_CLOCK_MUX_SELECT_DSCCLK_G = 0x00000004, +TEST_CLOCK_MUX_SELECT_DSCCLK_R = 0x00000005, +} TEST_CLOCK_MUX_SELECT_ENUM; + +/******************************************************* + * DWB_TOP Enums + *******************************************************/ + +/* + * DWB_CRC_CONT_EN_ENUM enum + */ + +typedef enum DWB_CRC_CONT_EN_ENUM { +DWB_CRC_CONT_EN_ONE_SHOT = 0x00000000, +DWB_CRC_CONT_EN_CONT = 0x00000001, +} DWB_CRC_CONT_EN_ENUM; + +/* + * DWB_CRC_SRC_SEL_ENUM enum + */ + +typedef enum DWB_CRC_SRC_SEL_ENUM { +DWB_CRC_SRC_SEL_DWB_IN = 0x00000000, +DWB_CRC_SRC_SEL_OGAM_OUT = 0x00000001, +DWB_CRC_SRC_SEL_DWB_OUT = 0x00000002, +} DWB_CRC_SRC_SEL_ENUM; + +/* + * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum + */ + +typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM { +DWB_DATA_OVERFLOW_INT_TYPE_0 = 0x00000000, +DWB_DATA_OVERFLOW_INT_TYPE_1 = 0x00000001, +} DWB_DATA_OVERFLOW_INT_TYPE_ENUM; + +/* + * DWB_DATA_OVERFLOW_TYPE_ENUM enum + */ + +typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM { +DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0x00000000, +DWB_DATA_OVERFLOW_TYPE_BUFFER = 0x00000001, +DWB_DATA_OVERFLOW_TYPE_VUPDATE = 0x00000002, +DWB_DATA_OVERFLOW_TYPE_VREADY = 0x00000003, +} DWB_DATA_OVERFLOW_TYPE_ENUM; + +/* + * DWB_DEBUG_SEL_ENUM enum + */ + +typedef enum DWB_DEBUG_SEL_ENUM { +DWB_DEBUG_SEL_FC = 0x00000000, +DWB_DEBUG_SEL_RESERVED = 0x00000001, +DWB_DEBUG_SEL_DWBCP = 0x00000002, +DWB_DEBUG_SEL_PERFMON = 0x00000003, +} DWB_DEBUG_SEL_ENUM; + +/* + * DWB_MEM_PWR_FORCE_ENUM enum + */ + +typedef enum DWB_MEM_PWR_FORCE_ENUM { +DWB_MEM_PWR_FORCE_DIS = 0x00000000, +DWB_MEM_PWR_FORCE_LS = 0x00000001, +DWB_MEM_PWR_FORCE_DS = 0x00000002, +DWB_MEM_PWR_FORCE_SD = 0x00000003, +} DWB_MEM_PWR_FORCE_ENUM; + +/* + * DWB_MEM_PWR_STATE_ENUM enum + */ + +typedef enum DWB_MEM_PWR_STATE_ENUM { +DWB_MEM_PWR_STATE_ON = 0x00000000, +DWB_MEM_PWR_STATE_LS = 0x00000001, +DWB_MEM_PWR_STATE_DS = 0x00000002, +DWB_MEM_PWR_STATE_SD = 0x00000003, +} DWB_MEM_PWR_STATE_ENUM; + +/* + * DWB_TEST_CLK_SEL_ENUM enum + */ + +typedef enum DWB_TEST_CLK_SEL_ENUM { +DWB_TEST_CLK_SEL_R = 0x00000000, +DWB_TEST_CLK_SEL_G = 0x00000001, +DWB_TEST_CLK_SEL_P = 0x00000002, +} DWB_TEST_CLK_SEL_ENUM; + +/* + * FC_EYE_SELECTION_ENUM enum + */ + +typedef enum FC_EYE_SELECTION_ENUM { +FC_EYE_SELECTION_STEREO_DIS = 0x00000000, +FC_EYE_SELECTION_LEFT_EYE = 0x00000001, +FC_EYE_SELECTION_RIGHT_EYE = 0x00000002, +} FC_EYE_SELECTION_ENUM; + +/* + * FC_FRAME_CAPTURE_RATE_ENUM enum + */ + +typedef enum FC_FRAME_CAPTURE_RATE_ENUM { +FC_FRAME_CAPTURE_RATE_FULL = 0x00000000, +FC_FRAME_CAPTURE_RATE_HALF = 0x00000001, +FC_FRAME_CAPTURE_RATE_THIRD = 0x00000002, +FC_FRAME_CAPTURE_RATE_QUARTER = 0x00000003, +} FC_FRAME_CAPTURE_RATE_ENUM; + +/* + * FC_STEREO_EYE_POLARITY_ENUM enum + */ + +typedef enum FC_STEREO_EYE_POLARITY_ENUM { +FC_STEREO_EYE_POLARITY_LEFT = 0x00000000, +FC_STEREO_EYE_POLARITY_RIGHT = 0x00000001, +} FC_STEREO_EYE_POLARITY_ENUM; + +/******************************************************* + * DWBCP Enums + *******************************************************/ + +/* + * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum + */ + +typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM { +DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000, +DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001, +} DWB_GAMUT_REMAP_COEF_FORMAT_ENUM; + +/* + * DWB_GAMUT_REMAP_MODE_ENUM enum + */ + +typedef enum DWB_GAMUT_REMAP_MODE_ENUM { +DWB_GAMUT_REMAP_MODE_BYPASS = 0x00000000, +DWB_GAMUT_REMAP_MODE_COEF_A = 0x00000001, +DWB_GAMUT_REMAP_MODE_COEF_B = 0x00000002, +DWB_GAMUT_REMAP_MODE_RESERVED = 0x00000003, +} DWB_GAMUT_REMAP_MODE_ENUM; + +/* + * DWB_LUT_NUM_SEG enum + */ + +typedef enum DWB_LUT_NUM_SEG { +DWB_SEGMENTS_1 = 0x00000000, +DWB_SEGMENTS_2 = 0x00000001, +DWB_SEGMENTS_4 = 0x00000002, +DWB_SEGMENTS_8 = 0x00000003, +DWB_SEGMENTS_16 = 0x00000004, +DWB_SEGMENTS_32 = 0x00000005, +DWB_SEGMENTS_64 = 0x00000006, +DWB_SEGMENTS_128 = 0x00000007, +} DWB_LUT_NUM_SEG; + +/* + * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum + */ + +typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM { +DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0x00000000, +DWB_OGAM_LUT_CONFIG_MODE_SAME = 0x00000001, +} DWB_OGAM_LUT_CONFIG_MODE_ENUM; + +/* + * DWB_OGAM_LUT_HOST_SEL_ENUM enum + */ + +typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM { +DWB_OGAM_LUT_HOST_SEL_RAMA = 0x00000000, +DWB_OGAM_LUT_HOST_SEL_RAMB = 0x00000001, +} DWB_OGAM_LUT_HOST_SEL_ENUM; + +/* + * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum + */ + +typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM { +DWB_OGAM_LUT_READ_COLOR_SEL_B = 0x00000000, +DWB_OGAM_LUT_READ_COLOR_SEL_G = 0x00000001, +DWB_OGAM_LUT_READ_COLOR_SEL_R = 0x00000002, +DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 0x00000003, +} DWB_OGAM_LUT_READ_COLOR_SEL_ENUM; + +/* + * DWB_OGAM_LUT_READ_DBG_ENUM enum + */ + +typedef enum DWB_OGAM_LUT_READ_DBG_ENUM { +DWB_OGAM_LUT_READ_DBG_DISABLE = 0x00000000, +DWB_OGAM_LUT_READ_DBG_ENABLE = 0x00000001, +} DWB_OGAM_LUT_READ_DBG_ENUM; + +/* + * DWB_OGAM_MODE_ENUM enum + */ + +typedef enum DWB_OGAM_MODE_ENUM { +DWB_OGAM_MODE_BYPASS = 0x00000000, +DWB_OGAM_MODE_RESERVED = 0x00000001, +DWB_OGAM_MODE_RAM_LUT_ENABLED = 0x00000002, +} DWB_OGAM_MODE_ENUM; + +/* + * DWB_OGAM_PWL_DISABLE_ENUM enum + */ + +typedef enum DWB_OGAM_PWL_DISABLE_ENUM { +DWB_OGAM_PWL_DISABLE_FALSE = 0x00000000, +DWB_OGAM_PWL_DISABLE_TRUE = 0x00000001, +} DWB_OGAM_PWL_DISABLE_ENUM; + +/* + * DWB_OGAM_SELECT_ENUM enum + */ + +typedef enum DWB_OGAM_SELECT_ENUM { +DWB_OGAM_SELECT_A = 0x00000000, +DWB_OGAM_SELECT_B = 0x00000001, +} DWB_OGAM_SELECT_ENUM; + +/******************************************************* + * RDPCSPIPE Enums + *******************************************************/ + +/* + * RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN { +RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0x00000000, +RDPCSPIPE_EXT_PCLK_EN_ENABLE = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN { +RDPCSPIPE_APBCLK_DISABLE = 0x00000000, +RDPCSPIPE_APBCLK_ENABLE = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON { +RDPCS_PIPE_CLK_CLOCK_OFF = 0x00000000, +RDPCS_PIPE_CLK_CLOCK_ON = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN { +RDPCS_PIPE_CLK_DISABLE = 0x00000000, +RDPCS_PIPE_CLK_ENABLE = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS { +RDPCS_PIPE_CLK_GATE_ENABLE = 0x00000000, +RDPCS_PIPE_CLK_GATE_DISABLE = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON { +RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0x00000000, +RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON { +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0x00000000, +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN { +RDPCSPIPE_SRAMCLK_DISABLE = 0x00000000, +RDPCSPIPE_SRAMCLK_ENABLE = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS { +RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0x00000000, +RDPCSPIPE_SRAMCLK_GATE_DISABLE = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS; + +/* + * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum + */ + +typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS { +RDPCSPIPE_SRAMCLK_NOT_PASS = 0x00000000, +RDPCSPIPE_SRAMCLK_PASS = 0x00000001, +} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS; + +/* + * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN enum + */ + +typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN { +RDPCS_PIPE_FIFO_DISABLE = 0x00000000, +RDPCS_PIPE_FIFO_ENABLE = 0x00000001, +} RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN; + +/* + * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN enum + */ + +typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN { +RDPCS_PIPE_FIFO_LANE_DISABLE = 0x00000000, +RDPCS_PIPE_FIFO_LANE_ENABLE = 0x00000001, +} RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN; + +/* + * RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET enum + */ + +typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET { +RDPCS_PIPE_SOFT_RESET_DISABLE = 0x00000000, +RDPCS_PIPE_SOFT_RESET_ENABLE = 0x00000001, +} RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET; + +/* + * RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET enum + */ + +typedef enum RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET { +RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0x00000000, +RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 0x00000001, +} RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET; + +/* + * RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK enum + */ + +typedef enum RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK { +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0x00000000, +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 0x00000001, +} RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK; + +/* + * RDPCSPIPE_DBG_OCLA_SEL enum + */ + +typedef enum RDPCSPIPE_DBG_OCLA_SEL { +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0x00000000, +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 0x00000001, +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 0x00000002, +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 0x00000003, +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 0x00000004, +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 0x00000005, +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 0x00000006, +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 0x00000007, +} RDPCSPIPE_DBG_OCLA_SEL; + +/* + * RDPCSPIPE_ENC_TYPE enum + */ + +typedef enum RDPCSPIPE_ENC_TYPE { +HDMI_TMDS_OR_DP_8B10B = 0x00000000, +HDMI_FRL = 0x00000001, +DP_128B132B = 0x00000002, +} RDPCSPIPE_ENC_TYPE; + +/* + * RDPCSPIPE_FIFO_EMPTY enum + */ + +typedef enum RDPCSPIPE_FIFO_EMPTY { +RDPCSPIPE_FIFO_NOT_EMPTY = 0x00000000, +RDPCSPIPE_FIFO_IS_EMPTY = 0x00000001, +} RDPCSPIPE_FIFO_EMPTY; + +/* + * RDPCSPIPE_FIFO_FULL enum + */ + +typedef enum RDPCSPIPE_FIFO_FULL { +RDPCSPIPE_FIFO_NOT_FULL = 0x00000000, +RDPCSPIPE_FIFO_IS_FULL = 0x00000001, +} RDPCSPIPE_FIFO_FULL; + +/* + * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK enum + */ + +typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK { +RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0x00000000, +RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 0x00000001, +} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK; + +/* + * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum + */ + +typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE { +RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0x00000000, +RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 0x00000001, +} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE; + +/* + * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum + */ + +typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK { +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000, +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001, +} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK; + +/* + * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum + */ + +typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE { +RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0x00000000, +RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 0x00000001, +} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE; + +/* + * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum + */ + +typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK { +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000, +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001, +} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK; + +/* + * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK enum + */ + +typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK { +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0x00000000, +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 0x00000001, +} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK; + +/* + * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum + */ + +typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK { +RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0x00000000, +RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 0x00000001, +} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK; + +/* + * RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK enum + */ + +typedef enum RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK { +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0x00000000, +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 0x00000001, +} RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK; + +/* + * RDPCSPIPE_PACK_MODE enum + */ + +typedef enum RDPCSPIPE_PACK_MODE { +TIGHT_PACK = 0x00000000, +LOOSE_PACK = 0x00000001, +} RDPCSPIPE_PACK_MODE; + +/* + * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL { +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0x00000000, +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 0x00000001, +} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL; + +/* + * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL { +RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0x00000000, +RDPCSPIPE_PHY_CR_PARA_SEL_CR = 0x00000001, +} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL; + +/* + * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE { +RDPCSPIPE_PHY_REF_RANGE_0 = 0x00000000, +RDPCSPIPE_PHY_REF_RANGE_1 = 0x00000001, +RDPCSPIPE_PHY_REF_RANGE_2 = 0x00000002, +RDPCSPIPE_PHY_REF_RANGE_3 = 0x00000003, +RDPCSPIPE_PHY_REF_RANGE_4 = 0x00000004, +RDPCSPIPE_PHY_REF_RANGE_5 = 0x00000005, +RDPCSPIPE_PHY_REF_RANGE_6 = 0x00000006, +RDPCSPIPE_PHY_REF_RANGE_7 = 0x00000007, +} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE; + +/* + * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE { +RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0x00000000, +RDPCSPIPE_SRAM_EXT_LD_DONE = 0x00000001, +} RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE; + +/* + * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE { +RDPCSPIPE_SRAM_INIT_NOT_DONE = 0x00000000, +RDPCSPIPE_SRAM_INIT_DONE = 0x00000001, +} RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE; + +/* + * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV { +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0x00000000, +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 0x00000001, +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 0x00000002, +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 0x00000003, +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 0x00000004, +} RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV; + +/* + * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV { +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000, +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001, +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002, +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003, +} RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV; + +/* + * RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV { +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000000, +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 0x00000001, +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 0x00000002, +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 0x00000003, +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 0x00000004, +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 0x00000005, +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 0x00000006, +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 0x00000007, +} RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV; + +/* + * RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL { +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0x00000000, +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 0x00000001, +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 0x00000002, +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 0x00000003, +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 0x00000004, +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 0x00000005, +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 0x00000006, +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 0x00000007, +} RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL; + +/* + * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT { +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000, +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 0x00000001, +} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT; + +/* + * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE { +RDPCSPIPE_PHY_DP_TX_RATE = 0x00000000, +RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 0x00000001, +RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 0x00000002, +} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE; + +/* + * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH { +RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0x00000000, +RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 0x00000001, +RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 0x00000002, +RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 0x00000003, +} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH; + +/* + * RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum + */ + +typedef enum RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE { +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0x00000000, +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 0x00000001, +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 0x00000002, +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 0x00000003, +} RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE; + +/* + * RDPCSPIPE_PHY_IF_WIDTH enum + */ + +typedef enum RDPCSPIPE_PHY_IF_WIDTH { +PHY_IF_WIDTH_10BIT = 0x00000000, +PHY_IF_WIDTH_20BIT = 0x00000001, +PHY_IF_WIDTH_40BIT = 0x00000002, +PHY_IF_WIDTH_80BIT = 0x00000003, +} RDPCSPIPE_PHY_IF_WIDTH; + +/* + * RDPCSPIPE_PHY_RATE enum + */ + +typedef enum RDPCSPIPE_PHY_RATE { +PHY_DP_RATE_1P62 = 0x00000000, +PHY_DP_RATE_2P7 = 0x00000001, +PHY_DP_RATE_5P4 = 0x00000002, +PHY_DP_RATE_8P1 = 0x00000003, +PHY_DP_RATE_2P16 = 0x00000004, +PHY_DP_RATE_2P43 = 0x00000005, +PHY_DP_RATE_3P24 = 0x00000006, +PHY_DP_RATE_4P32 = 0x00000007, +PHY_DP_RATE_10P = 0x00000008, +PHY_DP_RATE_13P5 = 0x00000009, +PHY_DP_RATE_20P = 0x0000000a, +PHY_CUSTOM_RATE = 0x0000000f, +} RDPCSPIPE_PHY_RATE; + +/* + * RDPCSPIPE_PHY_REF_ALT_CLK_EN enum + */ + +typedef enum RDPCSPIPE_PHY_REF_ALT_CLK_EN { +RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0x00000000, +RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 0x00000001, +} RDPCSPIPE_PHY_REF_ALT_CLK_EN; + +/* + * RDPCSPIPE_TEST_CLK_SEL enum + */ + +typedef enum RDPCSPIPE_TEST_CLK_SEL { +RDPCSPIPE_TEST_CLK_SEL_NONE = 0x00000000, +RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 0x00000001, +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002, +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003, +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004, +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005, +RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 0x00000006, +RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 0x00000007, +RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 0x00000008, +RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 0x00000009, +RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 0x0000000a, +RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 0x0000000b, +RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 0x0000000c, +RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d, +RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 0x0000000e, +RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 0x0000000f, +RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 0x00000010, +RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 0x00000011, +} RDPCSPIPE_TEST_CLK_SEL; + +/* + * RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB enum + */ + +typedef enum RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB { +RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0x00000000, +RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 0x00000001, +} RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB; + +/* + * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum + */ + +typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE { +RDPCSPIPE_MEM_PWR_NO_FORCE = 0x00000000, +RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 0x00000001, +RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 0x00000002, +RDPCSPIPE_MEM_PWR_SHUT_DOWN = 0x00000003, +} RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE; + +/* + * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum + */ + +typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE { +RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0x00000000, +RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 0x00000001, +RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 0x00000002, +RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 0x00000003, +} RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE; + +/* + * RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum + */ + +typedef enum RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK { +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0x00000000, +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 0x00000001, +} RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK; + +/******************************************************* + * GDS Enums + *******************************************************/ + +/* + * GDS_PERFCOUNT_SELECT enum + */ + +typedef enum GDS_PERFCOUNT_SELECT { +GDS_PERF_SEL_WR_COMP = 0x00000000, +GDS_PERF_SEL_WBUF_WR = 0x00000001, +GDS_PERF_SEL_SE0_NORET = 0x00000002, +GDS_PERF_SEL_SE0_RET = 0x00000003, +GDS_PERF_SEL_SE0_ORD_CNT = 0x00000004, +GDS_PERF_SEL_SE0_2COMP_REQ = 0x00000005, +GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 0x00000006, +GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 0x00000007, +GDS_PERF_SEL_SE0_GDS_WR_OP = 0x00000008, +GDS_PERF_SEL_SE0_GDS_RD_OP = 0x00000009, +GDS_PERF_SEL_SE0_GDS_ATOM_OP = 0x0000000a, +GDS_PERF_SEL_SE0_GDS_REL_OP = 0x0000000b, +GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 0x0000000c, +GDS_PERF_SEL_SE0_GDS_BYTE_OP = 0x0000000d, +GDS_PERF_SEL_SE0_GDS_SHORT_OP = 0x0000000e, +GDS_PERF_SEL_SE1_NORET = 0x0000000f, +GDS_PERF_SEL_SE1_RET = 0x00000010, +GDS_PERF_SEL_SE1_ORD_CNT = 0x00000011, +GDS_PERF_SEL_SE1_2COMP_REQ = 0x00000012, +GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 0x00000013, +GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 0x00000014, +GDS_PERF_SEL_SE1_GDS_WR_OP = 0x00000015, +GDS_PERF_SEL_SE1_GDS_RD_OP = 0x00000016, +GDS_PERF_SEL_SE1_GDS_ATOM_OP = 0x00000017, +GDS_PERF_SEL_SE1_GDS_REL_OP = 0x00000018, +GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 0x00000019, +GDS_PERF_SEL_SE1_GDS_BYTE_OP = 0x0000001a, +GDS_PERF_SEL_SE1_GDS_SHORT_OP = 0x0000001b, +GDS_PERF_SEL_SE2_NORET = 0x0000001c, +GDS_PERF_SEL_SE2_RET = 0x0000001d, +GDS_PERF_SEL_SE2_ORD_CNT = 0x0000001e, +GDS_PERF_SEL_SE2_2COMP_REQ = 0x0000001f, +GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 0x00000020, +GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 0x00000021, +GDS_PERF_SEL_SE2_GDS_WR_OP = 0x00000022, +GDS_PERF_SEL_SE2_GDS_RD_OP = 0x00000023, +GDS_PERF_SEL_SE2_GDS_ATOM_OP = 0x00000024, +GDS_PERF_SEL_SE2_GDS_REL_OP = 0x00000025, +GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 0x00000026, +GDS_PERF_SEL_SE2_GDS_BYTE_OP = 0x00000027, +GDS_PERF_SEL_SE2_GDS_SHORT_OP = 0x00000028, +GDS_PERF_SEL_SE3_NORET = 0x00000029, +GDS_PERF_SEL_SE3_RET = 0x0000002a, +GDS_PERF_SEL_SE3_ORD_CNT = 0x0000002b, +GDS_PERF_SEL_SE3_2COMP_REQ = 0x0000002c, +GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 0x0000002d, +GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 0x0000002e, +GDS_PERF_SEL_SE3_GDS_WR_OP = 0x0000002f, +GDS_PERF_SEL_SE3_GDS_RD_OP = 0x00000030, +GDS_PERF_SEL_SE3_GDS_ATOM_OP = 0x00000031, +GDS_PERF_SEL_SE3_GDS_REL_OP = 0x00000032, +GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 0x00000033, +GDS_PERF_SEL_SE3_GDS_BYTE_OP = 0x00000034, +GDS_PERF_SEL_SE3_GDS_SHORT_OP = 0x00000035, +GDS_PERF_SEL_SE4_NORET = 0x00000036, +GDS_PERF_SEL_SE4_RET = 0x00000037, +GDS_PERF_SEL_SE4_ORD_CNT = 0x00000038, +GDS_PERF_SEL_SE4_2COMP_REQ = 0x00000039, +GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 0x0000003a, +GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 0x0000003b, +GDS_PERF_SEL_SE4_GDS_WR_OP = 0x0000003c, +GDS_PERF_SEL_SE4_GDS_RD_OP = 0x0000003d, +GDS_PERF_SEL_SE4_GDS_ATOM_OP = 0x0000003e, +GDS_PERF_SEL_SE4_GDS_REL_OP = 0x0000003f, +GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 0x00000040, +GDS_PERF_SEL_SE4_GDS_BYTE_OP = 0x00000041, +GDS_PERF_SEL_SE4_GDS_SHORT_OP = 0x00000042, +GDS_PERF_SEL_SE5_NORET = 0x00000043, +GDS_PERF_SEL_SE5_RET = 0x00000044, +GDS_PERF_SEL_SE5_ORD_CNT = 0x00000045, +GDS_PERF_SEL_SE5_2COMP_REQ = 0x00000046, +GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 0x00000047, +GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 0x00000048, +GDS_PERF_SEL_SE5_GDS_WR_OP = 0x00000049, +GDS_PERF_SEL_SE5_GDS_RD_OP = 0x0000004a, +GDS_PERF_SEL_SE5_GDS_ATOM_OP = 0x0000004b, +GDS_PERF_SEL_SE5_GDS_REL_OP = 0x0000004c, +GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 0x0000004d, +GDS_PERF_SEL_SE5_GDS_BYTE_OP = 0x0000004e, +GDS_PERF_SEL_SE5_GDS_SHORT_OP = 0x0000004f, +GDS_PERF_SEL_SE6_NORET = 0x00000050, +GDS_PERF_SEL_SE6_RET = 0x00000051, +GDS_PERF_SEL_SE6_ORD_CNT = 0x00000052, +GDS_PERF_SEL_SE6_2COMP_REQ = 0x00000053, +GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 0x00000054, +GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 0x00000055, +GDS_PERF_SEL_SE6_GDS_WR_OP = 0x00000056, +GDS_PERF_SEL_SE6_GDS_RD_OP = 0x00000057, +GDS_PERF_SEL_SE6_GDS_ATOM_OP = 0x00000058, +GDS_PERF_SEL_SE6_GDS_REL_OP = 0x00000059, +GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 0x0000005a, +GDS_PERF_SEL_SE6_GDS_BYTE_OP = 0x0000005b, +GDS_PERF_SEL_SE6_GDS_SHORT_OP = 0x0000005c, +GDS_PERF_SEL_SE7_NORET = 0x0000005d, +GDS_PERF_SEL_SE7_RET = 0x0000005e, +GDS_PERF_SEL_SE7_ORD_CNT = 0x0000005f, +GDS_PERF_SEL_SE7_2COMP_REQ = 0x00000060, +GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 0x00000061, +GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 0x00000062, +GDS_PERF_SEL_SE7_GDS_WR_OP = 0x00000063, +GDS_PERF_SEL_SE7_GDS_RD_OP = 0x00000064, +GDS_PERF_SEL_SE7_GDS_ATOM_OP = 0x00000065, +GDS_PERF_SEL_SE7_GDS_REL_OP = 0x00000066, +GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 0x00000067, +GDS_PERF_SEL_SE7_GDS_BYTE_OP = 0x00000068, +GDS_PERF_SEL_SE7_GDS_SHORT_OP = 0x00000069, +GDS_PERF_SEL_GWS_RELEASED = 0x0000006a, +GDS_PERF_SEL_GWS_BYPASS = 0x0000006b, +} GDS_PERFCOUNT_SELECT; + +/******************************************************* + * CB Enums + *******************************************************/ + +/* + * BlendOp enum + */ + +typedef enum BlendOp { +BLEND_ZERO = 0x00000000, +BLEND_ONE = 0x00000001, +BLEND_SRC_COLOR = 0x00000002, +BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, +BLEND_SRC_ALPHA = 0x00000004, +BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, +BLEND_DST_ALPHA = 0x00000006, +BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, +BLEND_DST_COLOR = 0x00000008, +BLEND_ONE_MINUS_DST_COLOR = 0x00000009, +BLEND_SRC_ALPHA_SATURATE = 0x0000000a, +BLEND_CONSTANT_COLOR = 0x0000000b, +BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000c, +BLEND_SRC1_COLOR = 0x0000000d, +BLEND_INV_SRC1_COLOR = 0x0000000e, +BLEND_SRC1_ALPHA = 0x0000000f, +BLEND_INV_SRC1_ALPHA = 0x00000010, +BLEND_CONSTANT_ALPHA = 0x00000011, +BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000012, +} BlendOp; + +/* + * BlendOpt enum + */ + +typedef enum BlendOpt { +FORCE_OPT_AUTO = 0x00000000, +FORCE_OPT_DISABLE = 0x00000001, +FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, +FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, +} BlendOpt; + +/* + * CBMode enum + */ + +typedef enum CBMode { +CB_DISABLE = 0x00000000, +CB_NORMAL = 0x00000001, +CB_ELIMINATE_FAST_CLEAR = 0x00000002, +CB_DCC_DECOMPRESS = 0x00000003, +CB_RESERVED = 0x00000004, +} CBMode; + +/* + * CBPerfClearFilterSel enum + */ + +typedef enum CBPerfClearFilterSel { +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, +} CBPerfClearFilterSel; + +/* + * CBPerfOpFilterSel enum + */ + +typedef enum CBPerfOpFilterSel { +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, +CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, +} CBPerfOpFilterSel; + +/* + * CBPerfSel enum + */ + +typedef enum CBPerfSel { +CB_PERF_SEL_NONE = 0x00000000, +CB_PERF_SEL_DRAWN_PIXEL = 0x00000001, +CB_PERF_SEL_DRAWN_QUAD = 0x00000002, +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000003, +CB_PERF_SEL_DRAWN_TILE = 0x00000004, +CB_PERF_SEL_FILTER_DRAWN_PIXEL = 0x00000005, +CB_PERF_SEL_FILTER_DRAWN_QUAD = 0x00000006, +CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 0x00000007, +CB_PERF_SEL_FILTER_DRAWN_TILE = 0x00000008, +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 0x00000009, +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 0x0000000a, +CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 0x0000000b, +CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 0x0000000c, +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x0000000d, +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000000e, +CB_PERF_SEL_CC_MC_READ_REQUEST = 0x0000000f, +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000010, +CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 0x00000011, +CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 0x00000012, +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 0x00000013, +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 0x00000014, +CB_PERF_SEL_RESERVED_21 = 0x00000015, +CB_PERF_SEL_RESERVED_22 = 0x00000016, +CB_PERF_SEL_RESERVED_23 = 0x00000017, +CB_PERF_SEL_RESERVED_24 = 0x00000018, +CB_PERF_SEL_RESERVED_25 = 0x00000019, +CB_PERF_SEL_RESERVED_26 = 0x0000001a, +CB_PERF_SEL_RESERVED_27 = 0x0000001b, +CB_PERF_SEL_RESERVED_28 = 0x0000001c, +CB_PERF_SEL_RESERVED_29 = 0x0000001d, +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 0x0000001e, +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 0x0000001f, +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 0x00000020, +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 0x00000021, +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 0x00000022, +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 0x00000023, +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 0x00000024, +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 0x00000025, +CB_PERF_SEL_RESERVED_38 = 0x00000026, +CB_PERF_SEL_RESERVED_39 = 0x00000027, +CB_PERF_SEL_RESERVED_40 = 0x00000028, +CB_PERF_SEL_RESERVED_41 = 0x00000029, +CB_PERF_SEL_RESERVED_42 = 0x0000002a, +CB_PERF_SEL_RESERVED_43 = 0x0000002b, +CB_PERF_SEL_RESERVED_44 = 0x0000002c, +CB_PERF_SEL_RESERVED_45 = 0x0000002d, +CB_PERF_SEL_RESERVED_46 = 0x0000002e, +CB_PERF_SEL_RESERVED_47 = 0x0000002f, +CB_PERF_SEL_RESERVED_48 = 0x00000030, +CB_PERF_SEL_RESERVED_49 = 0x00000031, +CB_PERF_SEL_STATIC_CLOCK_EN = 0x00000032, +CB_PERF_SEL_PERFMON_CLOCK_EN = 0x00000033, +CB_PERF_SEL_BLEND_CLOCK_EN = 0x00000034, +CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 0x00000035, +CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 0x00000036, +CB_PERF_SEL_GRBM_CLOCK_EN = 0x00000037, +CB_PERF_SEL_MEMARB_CLOCK_EN = 0x00000038, +CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 0x00000039, +CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 0x0000003a, +CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 0x0000003b, +CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 0x0000003c, +CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 0x0000003d, +CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 0x0000003e, +CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 0x0000003f, +CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 0x00000040, +CB_PERF_SEL_RESERVED_65 = 0x00000041, +CB_PERF_SEL_RESERVED_66 = 0x00000042, +CB_PERF_SEL_RESERVED_67 = 0x00000043, +CB_PERF_SEL_RESERVED_68 = 0x00000044, +CB_PERF_SEL_RESERVED_69 = 0x00000045, +CB_PERF_SEL_RESERVED_70 = 0x00000046, +CB_PERF_SEL_RESERVED_71 = 0x00000047, +CB_PERF_SEL_RESERVED_72 = 0x00000048, +CB_PERF_SEL_RESERVED_73 = 0x00000049, +CB_PERF_SEL_RESERVED_74 = 0x0000004a, +CB_PERF_SEL_RESERVED_75 = 0x0000004b, +CB_PERF_SEL_RESERVED_76 = 0x0000004c, +CB_PERF_SEL_RESERVED_77 = 0x0000004d, +CB_PERF_SEL_RESERVED_78 = 0x0000004e, +CB_PERF_SEL_RESERVED_79 = 0x0000004f, +CB_PERF_SEL_RESERVED_80 = 0x00000050, +CB_PERF_SEL_RESERVED_81 = 0x00000051, +CB_PERF_SEL_RESERVED_82 = 0x00000052, +CB_PERF_SEL_RESERVED_83 = 0x00000053, +CB_PERF_SEL_RESERVED_84 = 0x00000054, +CB_PERF_SEL_RESERVED_85 = 0x00000055, +CB_PERF_SEL_RESERVED_86 = 0x00000056, +CB_PERF_SEL_RESERVED_87 = 0x00000057, +CB_PERF_SEL_RESERVED_88 = 0x00000058, +CB_PERF_SEL_RESERVED_89 = 0x00000059, +CB_PERF_SEL_RESERVED_90 = 0x0000005a, +CB_PERF_SEL_RESERVED_91 = 0x0000005b, +CB_PERF_SEL_RESERVED_92 = 0x0000005c, +CB_PERF_SEL_RESERVED_93 = 0x0000005d, +CB_PERF_SEL_RESERVED_94 = 0x0000005e, +CB_PERF_SEL_RESERVED_95 = 0x0000005f, +CB_PERF_SEL_RESERVED_96 = 0x00000060, +CB_PERF_SEL_RESERVED_97 = 0x00000061, +CB_PERF_SEL_RESERVED_98 = 0x00000062, +CB_PERF_SEL_RESERVED_99 = 0x00000063, +CB_PERF_SEL_CC_TAG_HIT = 0x00000064, +CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000065, +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000066, +CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 0x00000067, +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000068, +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000069, +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000006a, +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000006b, +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x0000006c, +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x0000006d, +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x0000006e, +CB_PERF_SEL_CC_CACHE_STALL = 0x0000006f, +CB_PERF_SEL_CC_CACHE_FLUSH = 0x00000070, +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x00000071, +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x00000072, +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x00000073, +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x00000074, +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x00000075, +CB_PERF_SEL_RESERVED_118 = 0x00000076, +CB_PERF_SEL_RESERVED_119 = 0x00000077, +CB_PERF_SEL_RESERVED_120 = 0x00000078, +CB_PERF_SEL_RESERVED_121 = 0x00000079, +CB_PERF_SEL_RESERVED_122 = 0x0000007a, +CB_PERF_SEL_RESERVED_123 = 0x0000007b, +CB_PERF_SEL_RESERVED_124 = 0x0000007c, +CB_PERF_SEL_RESERVED_125 = 0x0000007d, +CB_PERF_SEL_RESERVED_126 = 0x0000007e, +CB_PERF_SEL_RESERVED_127 = 0x0000007f, +CB_PERF_SEL_RESERVED_128 = 0x00000080, +CB_PERF_SEL_RESERVED_129 = 0x00000081, +CB_PERF_SEL_RESERVED_130 = 0x00000082, +CB_PERF_SEL_RESERVED_131 = 0x00000083, +CB_PERF_SEL_RESERVED_132 = 0x00000084, +CB_PERF_SEL_RESERVED_133 = 0x00000085, +CB_PERF_SEL_RESERVED_134 = 0x00000086, +CB_PERF_SEL_RESERVED_135 = 0x00000087, +CB_PERF_SEL_RESERVED_136 = 0x00000088, +CB_PERF_SEL_RESERVED_137 = 0x00000089, +CB_PERF_SEL_RESERVED_138 = 0x0000008a, +CB_PERF_SEL_RESERVED_139 = 0x0000008b, +CB_PERF_SEL_RESERVED_140 = 0x0000008c, +CB_PERF_SEL_RESERVED_141 = 0x0000008d, +CB_PERF_SEL_RESERVED_142 = 0x0000008e, +CB_PERF_SEL_RESERVED_143 = 0x0000008f, +CB_PERF_SEL_RESERVED_144 = 0x00000090, +CB_PERF_SEL_RESERVED_145 = 0x00000091, +CB_PERF_SEL_RESERVED_146 = 0x00000092, +CB_PERF_SEL_RESERVED_147 = 0x00000093, +CB_PERF_SEL_RESERVED_148 = 0x00000094, +CB_PERF_SEL_RESERVED_149 = 0x00000095, +CB_PERF_SEL_DCC_CACHE_PERF_HIT = 0x00000096, +CB_PERF_SEL_DCC_CACHE_TAG_MISS = 0x00000097, +CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 0x00000098, +CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 0x00000099, +CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000009a, +CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000009b, +CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000009c, +CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 0x0000009d, +CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 0x0000009e, +CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 0x0000009f, +CB_PERF_SEL_DCC_CACHE_STALL = 0x000000a0, +CB_PERF_SEL_DCC_CACHE_FLUSH = 0x000000a1, +CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 0x000000a2, +CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000a3, +CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 0x000000a4, +CB_PERF_SEL_RESERVED_165 = 0x000000a5, +CB_PERF_SEL_RESERVED_166 = 0x000000a6, +CB_PERF_SEL_RESERVED_167 = 0x000000a7, +CB_PERF_SEL_RESERVED_168 = 0x000000a8, +CB_PERF_SEL_RESERVED_169 = 0x000000a9, +CB_PERF_SEL_RESERVED_170 = 0x000000aa, +CB_PERF_SEL_RESERVED_171 = 0x000000ab, +CB_PERF_SEL_RESERVED_172 = 0x000000ac, +CB_PERF_SEL_RESERVED_173 = 0x000000ad, +CB_PERF_SEL_RESERVED_174 = 0x000000ae, +CB_PERF_SEL_RESERVED_175 = 0x000000af, +CB_PERF_SEL_RESERVED_176 = 0x000000b0, +CB_PERF_SEL_RESERVED_177 = 0x000000b1, +CB_PERF_SEL_RESERVED_178 = 0x000000b2, +CB_PERF_SEL_RESERVED_179 = 0x000000b3, +CB_PERF_SEL_RESERVED_180 = 0x000000b4, +CB_PERF_SEL_RESERVED_181 = 0x000000b5, +CB_PERF_SEL_RESERVED_182 = 0x000000b6, +CB_PERF_SEL_RESERVED_183 = 0x000000b7, +CB_PERF_SEL_RESERVED_184 = 0x000000b8, +CB_PERF_SEL_RESERVED_185 = 0x000000b9, +CB_PERF_SEL_RESERVED_186 = 0x000000ba, +CB_PERF_SEL_RESERVED_187 = 0x000000bb, +CB_PERF_SEL_RESERVED_188 = 0x000000bc, +CB_PERF_SEL_RESERVED_189 = 0x000000bd, +CB_PERF_SEL_RESERVED_190 = 0x000000be, +CB_PERF_SEL_RESERVED_191 = 0x000000bf, +CB_PERF_SEL_RESERVED_192 = 0x000000c0, +CB_PERF_SEL_RESERVED_193 = 0x000000c1, +CB_PERF_SEL_RESERVED_194 = 0x000000c2, +CB_PERF_SEL_RESERVED_195 = 0x000000c3, +CB_PERF_SEL_RESERVED_196 = 0x000000c4, +CB_PERF_SEL_RESERVED_197 = 0x000000c5, +CB_PERF_SEL_RESERVED_198 = 0x000000c6, +CB_PERF_SEL_RESERVED_199 = 0x000000c7, +CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000c8, +CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000c9, +CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000ca, +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000cb, +CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 0x000000cc, +CB_PERF_SEL_RESERVED_205 = 0x000000cd, +CB_PERF_SEL_RESERVED_206 = 0x000000ce, +CB_PERF_SEL_RESERVED_207 = 0x000000cf, +CB_PERF_SEL_RESERVED_208 = 0x000000d0, +CB_PERF_SEL_RESERVED_209 = 0x000000d1, +CB_PERF_SEL_RESERVED_210 = 0x000000d2, +CB_PERF_SEL_RESERVED_211 = 0x000000d3, +CB_PERF_SEL_RESERVED_212 = 0x000000d4, +CB_PERF_SEL_RESERVED_213 = 0x000000d5, +CB_PERF_SEL_RESERVED_214 = 0x000000d6, +CB_PERF_SEL_RESERVED_215 = 0x000000d7, +CB_PERF_SEL_RESERVED_216 = 0x000000d8, +CB_PERF_SEL_RESERVED_217 = 0x000000d9, +CB_PERF_SEL_RESERVED_218 = 0x000000da, +CB_PERF_SEL_RESERVED_219 = 0x000000db, +CB_PERF_SEL_RESERVED_220 = 0x000000dc, +CB_PERF_SEL_RESERVED_221 = 0x000000dd, +CB_PERF_SEL_RESERVED_222 = 0x000000de, +CB_PERF_SEL_RESERVED_223 = 0x000000df, +CB_PERF_SEL_RESERVED_224 = 0x000000e0, +CB_PERF_SEL_RESERVED_225 = 0x000000e1, +CB_PERF_SEL_RESERVED_226 = 0x000000e2, +CB_PERF_SEL_RESERVED_227 = 0x000000e3, +CB_PERF_SEL_RESERVED_228 = 0x000000e4, +CB_PERF_SEL_RESERVED_229 = 0x000000e5, +CB_PERF_SEL_RESERVED_230 = 0x000000e6, +CB_PERF_SEL_RESERVED_231 = 0x000000e7, +CB_PERF_SEL_RESERVED_232 = 0x000000e8, +CB_PERF_SEL_RESERVED_233 = 0x000000e9, +CB_PERF_SEL_RESERVED_234 = 0x000000ea, +CB_PERF_SEL_RESERVED_235 = 0x000000eb, +CB_PERF_SEL_RESERVED_236 = 0x000000ec, +CB_PERF_SEL_RESERVED_237 = 0x000000ed, +CB_PERF_SEL_RESERVED_238 = 0x000000ee, +CB_PERF_SEL_RESERVED_239 = 0x000000ef, +CB_PERF_SEL_RESERVED_240 = 0x000000f0, +CB_PERF_SEL_RESERVED_241 = 0x000000f1, +CB_PERF_SEL_RESERVED_242 = 0x000000f2, +CB_PERF_SEL_RESERVED_243 = 0x000000f3, +CB_PERF_SEL_RESERVED_244 = 0x000000f4, +CB_PERF_SEL_RESERVED_245 = 0x000000f5, +CB_PERF_SEL_RESERVED_246 = 0x000000f6, +CB_PERF_SEL_RESERVED_247 = 0x000000f7, +CB_PERF_SEL_RESERVED_248 = 0x000000f8, +CB_PERF_SEL_RESERVED_249 = 0x000000f9, +CB_PERF_SEL_EVENT = 0x000000fa, +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x000000fb, +CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x000000fc, +CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x000000fd, +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x000000fe, +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x000000ff, +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000100, +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000101, +CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000102, +CB_PERF_SEL_RESERVED_259 = 0x00000103, +CB_PERF_SEL_RESERVED_260 = 0x00000104, +CB_PERF_SEL_RESERVED_261 = 0x00000105, +CB_PERF_SEL_RESERVED_262 = 0x00000106, +CB_PERF_SEL_RESERVED_263 = 0x00000107, +CB_PERF_SEL_RESERVED_264 = 0x00000108, +CB_PERF_SEL_RESERVED_265 = 0x00000109, +CB_PERF_SEL_RESERVED_266 = 0x0000010a, +CB_PERF_SEL_RESERVED_267 = 0x0000010b, +CB_PERF_SEL_RESERVED_268 = 0x0000010c, +CB_PERF_SEL_RESERVED_269 = 0x0000010d, +CB_PERF_SEL_RESERVED_270 = 0x0000010e, +CB_PERF_SEL_RESERVED_271 = 0x0000010f, +CB_PERF_SEL_RESERVED_272 = 0x00000110, +CB_PERF_SEL_RESERVED_273 = 0x00000111, +CB_PERF_SEL_RESERVED_274 = 0x00000112, +CB_PERF_SEL_RESERVED_275 = 0x00000113, +CB_PERF_SEL_RESERVED_276 = 0x00000114, +CB_PERF_SEL_RESERVED_277 = 0x00000115, +CB_PERF_SEL_RESERVED_278 = 0x00000116, +CB_PERF_SEL_RESERVED_279 = 0x00000117, +CB_PERF_SEL_RESERVED_280 = 0x00000118, +CB_PERF_SEL_RESERVED_281 = 0x00000119, +CB_PERF_SEL_RESERVED_282 = 0x0000011a, +CB_PERF_SEL_RESERVED_283 = 0x0000011b, +CB_PERF_SEL_RESERVED_284 = 0x0000011c, +CB_PERF_SEL_RESERVED_285 = 0x0000011d, +CB_PERF_SEL_RESERVED_286 = 0x0000011e, +CB_PERF_SEL_RESERVED_287 = 0x0000011f, +CB_PERF_SEL_RESERVED_288 = 0x00000120, +CB_PERF_SEL_RESERVED_289 = 0x00000121, +CB_PERF_SEL_RESERVED_290 = 0x00000122, +CB_PERF_SEL_RESERVED_291 = 0x00000123, +CB_PERF_SEL_RESERVED_292 = 0x00000124, +CB_PERF_SEL_RESERVED_293 = 0x00000125, +CB_PERF_SEL_RESERVED_294 = 0x00000126, +CB_PERF_SEL_RESERVED_295 = 0x00000127, +CB_PERF_SEL_RESERVED_296 = 0x00000128, +CB_PERF_SEL_RESERVED_297 = 0x00000129, +CB_PERF_SEL_RESERVED_298 = 0x0000012a, +CB_PERF_SEL_RESERVED_299 = 0x0000012b, +CB_PERF_SEL_NACK_CC_READ = 0x0000012c, +CB_PERF_SEL_NACK_CC_WRITE = 0x0000012d, +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x0000012e, +CB_PERF_SEL_RESERVED_303 = 0x0000012f, +CB_PERF_SEL_RESERVED_304 = 0x00000130, +CB_PERF_SEL_RESERVED_305 = 0x00000131, +CB_PERF_SEL_RESERVED_306 = 0x00000132, +CB_PERF_SEL_RESERVED_307 = 0x00000133, +CB_PERF_SEL_RESERVED_308 = 0x00000134, +CB_PERF_SEL_RESERVED_309 = 0x00000135, +CB_PERF_SEL_RESERVED_310 = 0x00000136, +CB_PERF_SEL_RESERVED_311 = 0x00000137, +CB_PERF_SEL_RESERVED_312 = 0x00000138, +CB_PERF_SEL_RESERVED_313 = 0x00000139, +CB_PERF_SEL_RESERVED_314 = 0x0000013a, +CB_PERF_SEL_RESERVED_315 = 0x0000013b, +CB_PERF_SEL_RESERVED_316 = 0x0000013c, +CB_PERF_SEL_RESERVED_317 = 0x0000013d, +CB_PERF_SEL_RESERVED_318 = 0x0000013e, +CB_PERF_SEL_RESERVED_319 = 0x0000013f, +CB_PERF_SEL_RESERVED_320 = 0x00000140, +CB_PERF_SEL_RESERVED_321 = 0x00000141, +CB_PERF_SEL_RESERVED_322 = 0x00000142, +CB_PERF_SEL_RESERVED_323 = 0x00000143, +CB_PERF_SEL_RESERVED_324 = 0x00000144, +CB_PERF_SEL_RESERVED_325 = 0x00000145, +CB_PERF_SEL_RESERVED_326 = 0x00000146, +CB_PERF_SEL_RESERVED_327 = 0x00000147, +CB_PERF_SEL_RESERVED_328 = 0x00000148, +CB_PERF_SEL_RESERVED_329 = 0x00000149, +CB_PERF_SEL_RESERVED_330 = 0x0000014a, +CB_PERF_SEL_RESERVED_331 = 0x0000014b, +CB_PERF_SEL_RESERVED_332 = 0x0000014c, +CB_PERF_SEL_RESERVED_333 = 0x0000014d, +CB_PERF_SEL_RESERVED_334 = 0x0000014e, +CB_PERF_SEL_RESERVED_335 = 0x0000014f, +CB_PERF_SEL_RESERVED_336 = 0x00000150, +CB_PERF_SEL_RESERVED_337 = 0x00000151, +CB_PERF_SEL_RESERVED_338 = 0x00000152, +CB_PERF_SEL_RESERVED_339 = 0x00000153, +CB_PERF_SEL_RESERVED_340 = 0x00000154, +CB_PERF_SEL_RESERVED_341 = 0x00000155, +CB_PERF_SEL_RESERVED_342 = 0x00000156, +CB_PERF_SEL_RESERVED_343 = 0x00000157, +CB_PERF_SEL_RESERVED_344 = 0x00000158, +CB_PERF_SEL_RESERVED_345 = 0x00000159, +CB_PERF_SEL_RESERVED_346 = 0x0000015a, +CB_PERF_SEL_RESERVED_347 = 0x0000015b, +CB_PERF_SEL_RESERVED_348 = 0x0000015c, +CB_PERF_SEL_RESERVED_349 = 0x0000015d, +CB_PERF_SEL_RESERVED_350 = 0x0000015e, +CB_PERF_SEL_RESERVED_351 = 0x0000015f, +CB_PERF_SEL_RESERVED_352 = 0x00000160, +CB_PERF_SEL_RESERVED_353 = 0x00000161, +CB_PERF_SEL_RESERVED_354 = 0x00000162, +CB_PERF_SEL_RESERVED_355 = 0x00000163, +CB_PERF_SEL_RESERVED_356 = 0x00000164, +CB_PERF_SEL_RESERVED_357 = 0x00000165, +CB_PERF_SEL_RESERVED_358 = 0x00000166, +CB_PERF_SEL_RESERVED_359 = 0x00000167, +CB_PERF_SEL_RESERVED_360 = 0x00000168, +CB_PERF_SEL_RESERVED_361 = 0x00000169, +CB_PERF_SEL_RESERVED_362 = 0x0000016a, +CB_PERF_SEL_RESERVED_363 = 0x0000016b, +CB_PERF_SEL_RESERVED_364 = 0x0000016c, +CB_PERF_SEL_RESERVED_365 = 0x0000016d, +CB_PERF_SEL_RESERVED_366 = 0x0000016e, +CB_PERF_SEL_RESERVED_367 = 0x0000016f, +CB_PERF_SEL_RESERVED_368 = 0x00000170, +CB_PERF_SEL_RESERVED_369 = 0x00000171, +CB_PERF_SEL_RESERVED_370 = 0x00000172, +CB_PERF_SEL_RESERVED_371 = 0x00000173, +CB_PERF_SEL_RESERVED_372 = 0x00000174, +CB_PERF_SEL_RESERVED_373 = 0x00000175, +CB_PERF_SEL_RESERVED_374 = 0x00000176, +CB_PERF_SEL_RESERVED_375 = 0x00000177, +CB_PERF_SEL_RESERVED_376 = 0x00000178, +CB_PERF_SEL_RESERVED_377 = 0x00000179, +CB_PERF_SEL_RESERVED_378 = 0x0000017a, +CB_PERF_SEL_RESERVED_379 = 0x0000017b, +CB_PERF_SEL_RESERVED_380 = 0x0000017c, +CB_PERF_SEL_RESERVED_381 = 0x0000017d, +CB_PERF_SEL_RESERVED_382 = 0x0000017e, +CB_PERF_SEL_RESERVED_383 = 0x0000017f, +CB_PERF_SEL_RESERVED_384 = 0x00000180, +CB_PERF_SEL_RESERVED_385 = 0x00000181, +CB_PERF_SEL_RESERVED_386 = 0x00000182, +CB_PERF_SEL_RESERVED_387 = 0x00000183, +CB_PERF_SEL_RESERVED_388 = 0x00000184, +CB_PERF_SEL_RESERVED_389 = 0x00000185, +CB_PERF_SEL_RESERVED_390 = 0x00000186, +CB_PERF_SEL_RESERVED_391 = 0x00000187, +CB_PERF_SEL_RESERVED_392 = 0x00000188, +CB_PERF_SEL_RESERVED_393 = 0x00000189, +CB_PERF_SEL_RESERVED_394 = 0x0000018a, +CB_PERF_SEL_RESERVED_395 = 0x0000018b, +CB_PERF_SEL_RESERVED_396 = 0x0000018c, +CB_PERF_SEL_RESERVED_397 = 0x0000018d, +CB_PERF_SEL_RESERVED_398 = 0x0000018e, +CB_PERF_SEL_RESERVED_399 = 0x0000018f, +CB_PERF_SEL_RESERVED_400 = 0x00000190, +CB_PERF_SEL_RESERVED_401 = 0x00000191, +CB_PERF_SEL_RESERVED_402 = 0x00000192, +CB_PERF_SEL_RESERVED_403 = 0x00000193, +CB_PERF_SEL_RESERVED_404 = 0x00000194, +CB_PERF_SEL_RESERVED_405 = 0x00000195, +CB_PERF_SEL_RESERVED_406 = 0x00000196, +CB_PERF_SEL_RESERVED_407 = 0x00000197, +CB_PERF_SEL_RESERVED_408 = 0x00000198, +CB_PERF_SEL_RESERVED_409 = 0x00000199, +CB_PERF_SEL_RESERVED_410 = 0x0000019a, +CB_PERF_SEL_RESERVED_411 = 0x0000019b, +CB_PERF_SEL_RESERVED_412 = 0x0000019c, +CB_PERF_SEL_RESERVED_413 = 0x0000019d, +CB_PERF_SEL_RESERVED_414 = 0x0000019e, +CB_PERF_SEL_RESERVED_415 = 0x0000019f, +CB_PERF_SEL_RESERVED_416 = 0x000001a0, +CB_PERF_SEL_RESERVED_417 = 0x000001a1, +CB_PERF_SEL_RESERVED_418 = 0x000001a2, +CB_PERF_SEL_RESERVED_419 = 0x000001a3, +CB_PERF_SEL_RESERVED_420 = 0x000001a4, +CB_PERF_SEL_RESERVED_421 = 0x000001a5, +CB_PERF_SEL_RESERVED_422 = 0x000001a6, +CB_PERF_SEL_RESERVED_423 = 0x000001a7, +CB_PERF_SEL_RESERVED_424 = 0x000001a8, +CB_PERF_SEL_RESERVED_425 = 0x000001a9, +CB_PERF_SEL_RESERVED_426 = 0x000001aa, +CB_PERF_SEL_RESERVED_427 = 0x000001ab, +CB_PERF_SEL_RESERVED_428 = 0x000001ac, +CB_PERF_SEL_RESERVED_429 = 0x000001ad, +CB_PERF_SEL_RESERVED_430 = 0x000001ae, +CB_PERF_SEL_RESERVED_431 = 0x000001af, +CB_PERF_SEL_RESERVED_432 = 0x000001b0, +CB_PERF_SEL_RESERVED_433 = 0x000001b1, +CB_PERF_SEL_RESERVED_434 = 0x000001b2, +CB_PERF_SEL_RESERVED_435 = 0x000001b3, +CB_PERF_SEL_RESERVED_436 = 0x000001b4, +CB_PERF_SEL_RESERVED_437 = 0x000001b5, +CB_PERF_SEL_RESERVED_438 = 0x000001b6, +CB_PERF_SEL_RESERVED_439 = 0x000001b7, +CB_PERF_SEL_RESERVED_440 = 0x000001b8, +CB_PERF_SEL_RESERVED_441 = 0x000001b9, +CB_PERF_SEL_RESERVED_442 = 0x000001ba, +CB_PERF_SEL_RESERVED_443 = 0x000001bb, +CB_PERF_SEL_RESERVED_444 = 0x000001bc, +CB_PERF_SEL_RESERVED_445 = 0x000001bd, +CB_PERF_SEL_RESERVED_446 = 0x000001be, +CB_PERF_SEL_RESERVED_447 = 0x000001bf, +CB_PERF_SEL_RESERVED_448 = 0x000001c0, +CB_PERF_SEL_RESERVED_449 = 0x000001c1, +CB_PERF_SEL_RESERVED_450 = 0x000001c2, +CB_PERF_SEL_RESERVED_451 = 0x000001c3, +CB_PERF_SEL_RESERVED_452 = 0x000001c4, +CB_PERF_SEL_RESERVED_453 = 0x000001c5, +CB_PERF_SEL_RESERVED_454 = 0x000001c6, +CB_PERF_SEL_RESERVED_455 = 0x000001c7, +CB_PERF_SEL_RESERVED_456 = 0x000001c8, +CB_PERF_SEL_RESERVED_457 = 0x000001c9, +CB_PERF_SEL_RESERVED_458 = 0x000001ca, +CB_PERF_SEL_RESERVED_459 = 0x000001cb, +CB_PERF_SEL_RESERVED_460 = 0x000001cc, +CB_PERF_SEL_RESERVED_461 = 0x000001cd, +CB_PERF_SEL_RESERVED_462 = 0x000001ce, +CB_PERF_SEL_RESERVED_463 = 0x000001cf, +CB_PERF_SEL_RESERVED_464 = 0x000001d0, +CB_PERF_SEL_RESERVED_465 = 0x000001d1, +} CBPerfSel; + +/* + * CBRamList enum + */ + +typedef enum CBRamList { +CB_DCG_CCC_CAS_TAG_ARRAY = 0x00000000, +CB_DCG_CCC_CAS_FRAG_PTR = 0x00000001, +CB_DCG_CCC_CAS_COLOR_PTR = 0x00000002, +CB_DCG_CCC_CAS_SURF_PARAM = 0x00000003, +CB_DCG_CCC_CAS_KEYID = 0x00000004, +CB_DCG_BACKEND_RDLAT_FIFO = 0x00000005, +CB_DCG_FRONTEND_RDLAT_FIFO = 0x00000006, +CB_DCG_SRC_FIFO = 0x00000007, +CB_DCG_COLOR_STORE = 0x00000008, +CB_DCG_COLOR_STORE_DIRTY_BYTE = 0x00000009, +CB_DCG_FMASK_CACHE_STORE = 0x0000000a, +CB_DCG_READ_SKID_FIFO = 0x0000000b, +CB_DCG_QUAD_PTR_FIFO = 0x0000000c, +CB_DCG_OUTPUT_FIFO = 0x0000000d, +CB_DCG_DCC_CACHE = 0x0000000e, +CB_DCG_DCC_DIRTY_BITS = 0x0000000f, +CB_DCG_QBLOCK_ALLOC = 0x00000010, +} CBRamList; + +/* + * CmaskCode enum + */ + +typedef enum CmaskCode { +CMASK_CLR00_F0 = 0x00000000, +CMASK_CLR00_F1 = 0x00000001, +CMASK_CLR00_F2 = 0x00000002, +CMASK_CLR00_FX = 0x00000003, +CMASK_CLR01_F0 = 0x00000004, +CMASK_CLR01_F1 = 0x00000005, +CMASK_CLR01_F2 = 0x00000006, +CMASK_CLR01_FX = 0x00000007, +CMASK_CLR10_F0 = 0x00000008, +CMASK_CLR10_F1 = 0x00000009, +CMASK_CLR10_F2 = 0x0000000a, +CMASK_CLR10_FX = 0x0000000b, +CMASK_CLR11_F0 = 0x0000000c, +CMASK_CLR11_F1 = 0x0000000d, +CMASK_CLR11_F2 = 0x0000000e, +CMASK_CLR11_FX = 0x0000000f, +} CmaskCode; + +/* + * CombFunc enum + */ + +typedef enum CombFunc { +COMB_DST_PLUS_SRC = 0x00000000, +COMB_SRC_MINUS_DST = 0x00000001, +COMB_MIN_DST_SRC = 0x00000002, +COMB_MAX_DST_SRC = 0x00000003, +COMB_DST_MINUS_SRC = 0x00000004, +} CombFunc; + +/* + * MemArbMode enum + */ + +typedef enum MemArbMode { +MEM_ARB_MODE_FIXED = 0x00000000, +MEM_ARB_MODE_AGE = 0x00000001, +MEM_ARB_MODE_WEIGHT = 0x00000002, +MEM_ARB_MODE_BOTH = 0x00000003, +} MemArbMode; + +/* + * SourceFormat enum + */ + +typedef enum SourceFormat { +EXPORT_4C_32BPC = 0x00000000, +EXPORT_4C_16BPC = 0x00000001, +EXPORT_2C_32BPC_GR = 0x00000002, +EXPORT_2C_32BPC_AR = 0x00000003, +} SourceFormat; + +/******************************************************* + * SC Enums + *******************************************************/ + +/* + * BinEventCntl enum + */ + +typedef enum BinEventCntl { +BINNER_BREAK_BATCH = 0x00000000, +BINNER_PIPELINE = 0x00000001, +BINNER_DROP = 0x00000002, +BINNER_PIPELINE_BREAK = 0x00000003, +} BinEventCntl; + +/* + * BinMapMode enum + */ + +typedef enum BinMapMode { +BIN_MAP_MODE_NONE = 0x00000000, +BIN_MAP_MODE_RTA_INDEX = 0x00000001, +BIN_MAP_MODE_POPS = 0x00000002, +} BinMapMode; + +/* + * BinSizeExtend enum + */ + +typedef enum BinSizeExtend { +BIN_SIZE_32_PIXELS = 0x00000000, +BIN_SIZE_64_PIXELS = 0x00000001, +BIN_SIZE_128_PIXELS = 0x00000002, +BIN_SIZE_256_PIXELS = 0x00000003, +BIN_SIZE_512_PIXELS = 0x00000004, +} BinSizeExtend; + +/* + * BinningMode enum + */ + +typedef enum BinningMode { +BINNING_ALLOWED = 0x00000000, +FORCE_BINNING_ON = 0x00000001, +DISABLE_BINNING_USE_NEW_SC = 0x00000002, +DISABLE_BINNING_USE_LEGACY_SC = 0x00000003, +} BinningMode; + +/* + * CovToShaderSel enum + */ + +typedef enum CovToShaderSel { +INPUT_COVERAGE = 0x00000000, +INPUT_INNER_COVERAGE = 0x00000001, +INPUT_DEPTH_COVERAGE = 0x00000002, +RAW = 0x00000003, +} CovToShaderSel; + +/* + * PkrMap enum + */ + +typedef enum PkrMap { +RASTER_CONFIG_PKR_MAP_0 = 0x00000000, +RASTER_CONFIG_PKR_MAP_1 = 0x00000001, +RASTER_CONFIG_PKR_MAP_2 = 0x00000002, +RASTER_CONFIG_PKR_MAP_3 = 0x00000003, +} PkrMap; + +/* + * PkrXsel enum + */ + +typedef enum PkrXsel { +RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, +RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, +RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, +RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, +} PkrXsel; + +/* + * PkrXsel2 enum + */ + +typedef enum PkrXsel2 { +RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, +RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, +RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, +RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, +} PkrXsel2; + +/* + * PkrYsel enum + */ + +typedef enum PkrYsel { +RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, +RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, +RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, +RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, +} PkrYsel; + +/* + * RbMap enum + */ + +typedef enum RbMap { +RASTER_CONFIG_RB_MAP_0 = 0x00000000, +RASTER_CONFIG_RB_MAP_1 = 0x00000001, +RASTER_CONFIG_RB_MAP_2 = 0x00000002, +RASTER_CONFIG_RB_MAP_3 = 0x00000003, +} RbMap; + +/* + * RbXsel enum + */ + +typedef enum RbXsel { +RASTER_CONFIG_RB_XSEL_0 = 0x00000000, +RASTER_CONFIG_RB_XSEL_1 = 0x00000001, +} RbXsel; + +/* + * RbXsel2 enum + */ + +typedef enum RbXsel2 { +RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, +RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, +RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, +RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, +} RbXsel2; + +/* + * RbYsel enum + */ + +typedef enum RbYsel { +RASTER_CONFIG_RB_YSEL_0 = 0x00000000, +RASTER_CONFIG_RB_YSEL_1 = 0x00000001, +} RbYsel; + +/* + * SC_PERFCNT_SEL enum + */ + +typedef enum SC_PERFCNT_SEL { +SC_SRPS_WINDOW_VALID = 0x00000000, +SC_PSSW_WINDOW_VALID = 0x00000001, +SC_TPQZ_WINDOW_VALID = 0x00000002, +SC_QZQP_WINDOW_VALID = 0x00000003, +SC_TRPK_WINDOW_VALID = 0x00000004, +SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, +SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, +SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, +SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, +SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, +SC_STARVED_BY_PA = 0x0000000a, +SC_STALLED_BY_PRIMFIFO = 0x0000000b, +SC_STALLED_BY_DB_TILE = 0x0000000c, +SC_STARVED_BY_DB_TILE = 0x0000000d, +SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, +SC_STALLED_BY_TILEFIFO = 0x0000000f, +SC_STALLED_BY_DB_QUAD = 0x00000010, +SC_STARVED_BY_DB_QUAD = 0x00000011, +SC_STALLED_BY_QUADFIFO = 0x00000012, +SC_STALLED_BY_BCI = 0x00000013, +SC_STALLED_BY_SPI = 0x00000014, +SC_SCISSOR_DISCARD = 0x00000015, +SC_BB_DISCARD = 0x00000016, +SC_SUPERTILE_COUNT = 0x00000017, +SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, +SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, +SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, +SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, +SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, +SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, +SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, +SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, +SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, +SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, +SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, +SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, +SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, +SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, +SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, +SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, +SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, +SC_TILE_PER_PRIM_H0 = 0x00000029, +SC_TILE_PER_PRIM_H1 = 0x0000002a, +SC_TILE_PER_PRIM_H2 = 0x0000002b, +SC_TILE_PER_PRIM_H3 = 0x0000002c, +SC_TILE_PER_PRIM_H4 = 0x0000002d, +SC_TILE_PER_PRIM_H5 = 0x0000002e, +SC_TILE_PER_PRIM_H6 = 0x0000002f, +SC_TILE_PER_PRIM_H7 = 0x00000030, +SC_TILE_PER_PRIM_H8 = 0x00000031, +SC_TILE_PER_PRIM_H9 = 0x00000032, +SC_TILE_PER_PRIM_H10 = 0x00000033, +SC_TILE_PER_PRIM_H11 = 0x00000034, +SC_TILE_PER_PRIM_H12 = 0x00000035, +SC_TILE_PER_PRIM_H13 = 0x00000036, +SC_TILE_PER_PRIM_H14 = 0x00000037, +SC_TILE_PER_PRIM_H15 = 0x00000038, +SC_TILE_PER_PRIM_H16 = 0x00000039, +SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, +SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, +SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, +SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, +SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, +SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, +SC_TILE_PER_SUPERTILE_H6 = 0x00000040, +SC_TILE_PER_SUPERTILE_H7 = 0x00000041, +SC_TILE_PER_SUPERTILE_H8 = 0x00000042, +SC_TILE_PER_SUPERTILE_H9 = 0x00000043, +SC_TILE_PER_SUPERTILE_H10 = 0x00000044, +SC_TILE_PER_SUPERTILE_H11 = 0x00000045, +SC_TILE_PER_SUPERTILE_H12 = 0x00000046, +SC_TILE_PER_SUPERTILE_H13 = 0x00000047, +SC_TILE_PER_SUPERTILE_H14 = 0x00000048, +SC_TILE_PER_SUPERTILE_H15 = 0x00000049, +SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, +SC_TILE_PICKED_H1 = 0x0000004b, +SC_TILE_PICKED_H2 = 0x0000004c, +SC_TILE_PICKED_H3 = 0x0000004d, +SC_TILE_PICKED_H4 = 0x0000004e, +SC_QZ0_TILE_COUNT = 0x0000004f, +SC_QZ1_TILE_COUNT = 0x00000050, +SC_QZ2_TILE_COUNT = 0x00000051, +SC_QZ3_TILE_COUNT = 0x00000052, +SC_QZ0_TILE_COVERED_COUNT = 0x00000053, +SC_QZ1_TILE_COVERED_COUNT = 0x00000054, +SC_QZ2_TILE_COVERED_COUNT = 0x00000055, +SC_QZ3_TILE_COVERED_COUNT = 0x00000056, +SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057, +SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00000058, +SC_QZ2_TILE_NOT_COVERED_COUNT = 0x00000059, +SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005a, +SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b, +SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c, +SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d, +SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e, +SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f, +SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060, +SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061, +SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062, +SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063, +SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064, +SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065, +SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066, +SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067, +SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068, +SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069, +SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a, +SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b, +SC_QZ1_QUAD_PER_TILE_H0 = 0x0000006c, +SC_QZ1_QUAD_PER_TILE_H1 = 0x0000006d, +SC_QZ1_QUAD_PER_TILE_H2 = 0x0000006e, +SC_QZ1_QUAD_PER_TILE_H3 = 0x0000006f, +SC_QZ1_QUAD_PER_TILE_H4 = 0x00000070, +SC_QZ1_QUAD_PER_TILE_H5 = 0x00000071, +SC_QZ1_QUAD_PER_TILE_H6 = 0x00000072, +SC_QZ1_QUAD_PER_TILE_H7 = 0x00000073, +SC_QZ1_QUAD_PER_TILE_H8 = 0x00000074, +SC_QZ1_QUAD_PER_TILE_H9 = 0x00000075, +SC_QZ1_QUAD_PER_TILE_H10 = 0x00000076, +SC_QZ1_QUAD_PER_TILE_H11 = 0x00000077, +SC_QZ1_QUAD_PER_TILE_H12 = 0x00000078, +SC_QZ1_QUAD_PER_TILE_H13 = 0x00000079, +SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007a, +SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007b, +SC_QZ1_QUAD_PER_TILE_H16 = 0x0000007c, +SC_QZ2_QUAD_PER_TILE_H0 = 0x0000007d, +SC_QZ2_QUAD_PER_TILE_H1 = 0x0000007e, +SC_QZ2_QUAD_PER_TILE_H2 = 0x0000007f, +SC_QZ2_QUAD_PER_TILE_H3 = 0x00000080, +SC_QZ2_QUAD_PER_TILE_H4 = 0x00000081, +SC_QZ2_QUAD_PER_TILE_H5 = 0x00000082, +SC_QZ2_QUAD_PER_TILE_H6 = 0x00000083, +SC_QZ2_QUAD_PER_TILE_H7 = 0x00000084, +SC_QZ2_QUAD_PER_TILE_H8 = 0x00000085, +SC_QZ2_QUAD_PER_TILE_H9 = 0x00000086, +SC_QZ2_QUAD_PER_TILE_H10 = 0x00000087, +SC_QZ2_QUAD_PER_TILE_H11 = 0x00000088, +SC_QZ2_QUAD_PER_TILE_H12 = 0x00000089, +SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008a, +SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008b, +SC_QZ2_QUAD_PER_TILE_H15 = 0x0000008c, +SC_QZ2_QUAD_PER_TILE_H16 = 0x0000008d, +SC_QZ3_QUAD_PER_TILE_H0 = 0x0000008e, +SC_QZ3_QUAD_PER_TILE_H1 = 0x0000008f, +SC_QZ3_QUAD_PER_TILE_H2 = 0x00000090, +SC_QZ3_QUAD_PER_TILE_H3 = 0x00000091, +SC_QZ3_QUAD_PER_TILE_H4 = 0x00000092, +SC_QZ3_QUAD_PER_TILE_H5 = 0x00000093, +SC_QZ3_QUAD_PER_TILE_H6 = 0x00000094, +SC_QZ3_QUAD_PER_TILE_H7 = 0x00000095, +SC_QZ3_QUAD_PER_TILE_H8 = 0x00000096, +SC_QZ3_QUAD_PER_TILE_H9 = 0x00000097, +SC_QZ3_QUAD_PER_TILE_H10 = 0x00000098, +SC_QZ3_QUAD_PER_TILE_H11 = 0x00000099, +SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009a, +SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009b, +SC_QZ3_QUAD_PER_TILE_H14 = 0x0000009c, +SC_QZ3_QUAD_PER_TILE_H15 = 0x0000009d, +SC_QZ3_QUAD_PER_TILE_H16 = 0x0000009e, +SC_QZ0_QUAD_COUNT = 0x0000009f, +SC_QZ1_QUAD_COUNT = 0x000000a0, +SC_QZ2_QUAD_COUNT = 0x000000a1, +SC_QZ3_QUAD_COUNT = 0x000000a2, +SC_P0_HIZ_TILE_COUNT = 0x000000a3, +SC_P1_HIZ_TILE_COUNT = 0x000000a4, +SC_P2_HIZ_TILE_COUNT = 0x000000a5, +SC_P3_HIZ_TILE_COUNT = 0x000000a6, +SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7, +SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8, +SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9, +SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa, +SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab, +SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac, +SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad, +SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae, +SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af, +SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0, +SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1, +SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2, +SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3, +SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4, +SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5, +SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6, +SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7, +SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000b8, +SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000b9, +SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000ba, +SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bb, +SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000bc, +SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000bd, +SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000be, +SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000bf, +SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c0, +SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c1, +SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c2, +SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c3, +SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c4, +SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c5, +SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000c6, +SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000c7, +SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000c8, +SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000c9, +SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ca, +SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cb, +SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000cc, +SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000cd, +SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000ce, +SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000cf, +SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d0, +SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d1, +SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d2, +SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d3, +SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d4, +SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d5, +SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000d6, +SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000d7, +SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000d8, +SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000d9, +SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000da, +SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000db, +SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000dc, +SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000dd, +SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000de, +SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000df, +SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e0, +SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e1, +SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e2, +SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e3, +SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e4, +SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e5, +SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000e6, +SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000e7, +SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000e8, +SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000e9, +SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ea, +SC_P0_HIZ_QUAD_COUNT = 0x000000eb, +SC_P1_HIZ_QUAD_COUNT = 0x000000ec, +SC_P2_HIZ_QUAD_COUNT = 0x000000ed, +SC_P3_HIZ_QUAD_COUNT = 0x000000ee, +SC_P0_DETAIL_QUAD_COUNT = 0x000000ef, +SC_P1_DETAIL_QUAD_COUNT = 0x000000f0, +SC_P2_DETAIL_QUAD_COUNT = 0x000000f1, +SC_P3_DETAIL_QUAD_COUNT = 0x000000f2, +SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3, +SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4, +SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5, +SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6, +SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, +SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, +SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, +SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, +SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, +SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, +SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, +SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, +SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, +SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000100, +SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000101, +SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000102, +SC_EARLYZ_QUAD_COUNT = 0x00000103, +SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104, +SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105, +SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106, +SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107, +SC_PKR_QUAD_PER_ROW_H1 = 0x00000108, +SC_PKR_QUAD_PER_ROW_H2 = 0x00000109, +SC_PKR_4X2_QUAD_SPLIT = 0x0000010a, +SC_PKR_4X2_FILL_QUAD = 0x0000010b, +SC_PKR_END_OF_VECTOR = 0x0000010c, +SC_PKR_CONTROL_XFER = 0x0000010d, +SC_PKR_DBHANG_FORCE_EOV = 0x0000010e, +SC_REG_SCLK_BUSY = 0x0000010f, +SC_GRP0_DYN_SCLK_BUSY = 0x00000110, +SC_GRP1_DYN_SCLK_BUSY = 0x00000111, +SC_GRP2_DYN_SCLK_BUSY = 0x00000112, +SC_GRP3_DYN_SCLK_BUSY = 0x00000113, +SC_GRP4_DYN_SCLK_BUSY = 0x00000114, +SC_PA0_SC_DATA_FIFO_RD = 0x00000115, +SC_PA0_SC_DATA_FIFO_WE = 0x00000116, +SC_PA1_SC_DATA_FIFO_RD = 0x00000117, +SC_PA1_SC_DATA_FIFO_WE = 0x00000118, +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119, +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a, +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b, +SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c, +SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d, +SC_PS_ARB_SC_BUSY = 0x0000011e, +SC_PS_ARB_PA_SC_BUSY = 0x0000011f, +SC_PA2_SC_DATA_FIFO_RD = 0x00000120, +SC_PA2_SC_DATA_FIFO_WE = 0x00000121, +SC_PA3_SC_DATA_FIFO_RD = 0x00000122, +SC_PA3_SC_DATA_FIFO_WE = 0x00000123, +SC_PA_SC_DEALLOC_0_0_WE = 0x00000124, +SC_PA_SC_DEALLOC_0_1_WE = 0x00000125, +SC_PA_SC_DEALLOC_1_0_WE = 0x00000126, +SC_PA_SC_DEALLOC_1_1_WE = 0x00000127, +SC_PA_SC_DEALLOC_2_0_WE = 0x00000128, +SC_PA_SC_DEALLOC_2_1_WE = 0x00000129, +SC_PA_SC_DEALLOC_3_0_WE = 0x0000012a, +SC_PA_SC_DEALLOC_3_1_WE = 0x0000012b, +SC_PA0_SC_EOP_WE = 0x0000012c, +SC_PA0_SC_EOPG_WE = 0x0000012d, +SC_PA0_SC_EVENT_WE = 0x0000012e, +SC_PA1_SC_EOP_WE = 0x0000012f, +SC_PA1_SC_EOPG_WE = 0x00000130, +SC_PA1_SC_EVENT_WE = 0x00000131, +SC_PA2_SC_EOP_WE = 0x00000132, +SC_PA2_SC_EOPG_WE = 0x00000133, +SC_PA2_SC_EVENT_WE = 0x00000134, +SC_PA3_SC_EOP_WE = 0x00000135, +SC_PA3_SC_EOPG_WE = 0x00000136, +SC_PA3_SC_EVENT_WE = 0x00000137, +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138, +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x00000139, +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013a, +SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013b, +SC_PS_ARB_EVENT_SYNC_POP = 0x0000013c, +SC_PS_ENG_MULTICYCLE_BUBBLE = 0x0000013d, +SC_PA0_SC_FPOV_WE = 0x0000013e, +SC_PA1_SC_FPOV_WE = 0x0000013f, +SC_PA2_SC_FPOV_WE = 0x00000140, +SC_PA3_SC_FPOV_WE = 0x00000141, +SC_PA0_SC_LPOV_WE = 0x00000142, +SC_PA1_SC_LPOV_WE = 0x00000143, +SC_PA2_SC_LPOV_WE = 0x00000144, +SC_PA3_SC_LPOV_WE = 0x00000145, +SC_SPI_DEALLOC_0_0 = 0x00000146, +SC_SPI_DEALLOC_0_1 = 0x00000147, +SC_SPI_DEALLOC_0_2 = 0x00000148, +SC_SPI_DEALLOC_1_0 = 0x00000149, +SC_SPI_DEALLOC_1_1 = 0x0000014a, +SC_SPI_DEALLOC_1_2 = 0x0000014b, +SC_SPI_DEALLOC_2_0 = 0x0000014c, +SC_SPI_DEALLOC_2_1 = 0x0000014d, +SC_SPI_DEALLOC_2_2 = 0x0000014e, +SC_SPI_DEALLOC_3_0 = 0x0000014f, +SC_SPI_DEALLOC_3_1 = 0x00000150, +SC_SPI_DEALLOC_3_2 = 0x00000151, +SC_SPI_FPOV_0 = 0x00000152, +SC_SPI_FPOV_1 = 0x00000153, +SC_SPI_FPOV_2 = 0x00000154, +SC_SPI_FPOV_3 = 0x00000155, +SC_SPI_EVENT = 0x00000156, +SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157, +SC_PS_TS_EVENT_FIFO_POP = 0x00000158, +SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159, +SC_PS_CTX_DONE_FIFO_POP = 0x0000015a, +SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015b, +SC_EOP_SYNC_WINDOW = 0x0000015c, +SC_PA0_SC_NULL_WE = 0x0000015d, +SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e, +SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x0000015f, +SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160, +SC_PA0_SC_DEALLOC_0_RD = 0x00000161, +SC_PA0_SC_DEALLOC_1_RD = 0x00000162, +SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000163, +SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000164, +SC_PA1_SC_DEALLOC_0_RD = 0x00000165, +SC_PA1_SC_DEALLOC_1_RD = 0x00000166, +SC_PA1_SC_NULL_WE = 0x00000167, +SC_PA1_SC_NULL_DEALLOC_WE = 0x00000168, +SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x00000169, +SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016a, +SC_PA2_SC_DEALLOC_0_RD = 0x0000016b, +SC_PA2_SC_DEALLOC_1_RD = 0x0000016c, +SC_PA2_SC_NULL_WE = 0x0000016d, +SC_PA2_SC_NULL_DEALLOC_WE = 0x0000016e, +SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x0000016f, +SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000170, +SC_PA3_SC_DEALLOC_0_RD = 0x00000171, +SC_PA3_SC_DEALLOC_1_RD = 0x00000172, +SC_PA3_SC_NULL_WE = 0x00000173, +SC_PA3_SC_NULL_DEALLOC_WE = 0x00000174, +SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175, +SC_PS_PA0_SC_FIFO_FULL = 0x00000176, +SC_RESERVED_0 = 0x00000177, +SC_PS_PA1_SC_FIFO_EMPTY = 0x00000178, +SC_PS_PA1_SC_FIFO_FULL = 0x00000179, +SC_RESERVED_1 = 0x0000017a, +SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017b, +SC_PS_PA2_SC_FIFO_FULL = 0x0000017c, +SC_RESERVED_2 = 0x0000017d, +SC_PS_PA3_SC_FIFO_EMPTY = 0x0000017e, +SC_PS_PA3_SC_FIFO_FULL = 0x0000017f, +SC_RESERVED_3 = 0x00000180, +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000181, +SC_BUSY_CNT_NOT_ZERO = 0x00000182, +SC_BM_BUSY = 0x00000183, +SC_BACKEND_BUSY = 0x00000184, +SC_SCF_SCB_INTERFACE_BUSY = 0x00000185, +SC_SCB_BUSY = 0x00000186, +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187, +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188, +SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189, +SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a, +SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b, +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c, +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d, +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e, +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f, +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190, +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191, +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192, +SC_PBB_BUSY = 0x00000193, +SC_PBB_BUSY_AND_NO_SENDS = 0x00000194, +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195, +SC_PBB_NUM_BINS = 0x00000196, +SC_PBB_END_OF_BIN = 0x00000197, +SC_PBB_END_OF_BATCH = 0x00000198, +SC_PBB_PRIMBIN_PROCESSED = 0x00000199, +SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a, +SC_PBB_NONBINNED_PRIM = 0x0000019b, +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c, +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d, +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e, +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f, +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0, +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1, +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2, +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3, +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4, +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5, +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6, +SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001a7, +SC_POPS_FORCE_EOV = 0x000001a8, +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 0x000001a9, +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 0x000001aa, +SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 0x000001ab, +SC_FULL_FULL_QUAD = 0x000001ac, +SC_FULL_HALF_QUAD = 0x000001ad, +SC_FULL_QTR_QUAD = 0x000001ae, +SC_HALF_FULL_QUAD = 0x000001af, +SC_HALF_HALF_QUAD = 0x000001b0, +SC_HALF_QTR_QUAD = 0x000001b1, +SC_QTR_FULL_QUAD = 0x000001b2, +SC_QTR_HALF_QUAD = 0x000001b3, +SC_QTR_QTR_QUAD = 0x000001b4, +SC_GRP5_DYN_SCLK_BUSY = 0x000001b5, +SC_GRP6_DYN_SCLK_BUSY = 0x000001b6, +SC_GRP7_DYN_SCLK_BUSY = 0x000001b7, +SC_GRP8_DYN_SCLK_BUSY = 0x000001b8, +SC_GRP9_DYN_SCLK_BUSY = 0x000001b9, +SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba, +SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb, +SC_PK_BUSY = 0x000001bc, +SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd, +SC_PK_DEALLOC_WAVE_BREAK = 0x000001be, +SC_SPI_SEND = 0x000001bf, +SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0, +SC_SPI_CREDIT_AT_MAX = 0x000001c1, +SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2, +SC_BCI_SEND = 0x000001c3, +SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4, +SC_BCI_CREDIT_AT_MAX = 0x000001c5, +SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6, +SC_SPIBC_FULL_FREEZE = 0x000001c7, +SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8, +SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9, +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da, +SC_DB0_TILE_INTERFACE_BUSY = 0x000001db, +SC_DB0_TILE_INTERFACE_SEND = 0x000001dc, +SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd, +SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001de, +SC_DB0_TILE_INTERFACE_SEND_SOP = 0x000001df, +SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0, +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1, +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2, +SC_DB1_TILE_INTERFACE_BUSY = 0x000001e3, +SC_DB1_TILE_INTERFACE_SEND = 0x000001e4, +SC_DB1_TILE_INTERFACE_SEND_EVENT = 0x000001e5, +SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001e6, +SC_DB1_TILE_INTERFACE_SEND_SOP = 0x000001e7, +SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e8, +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e9, +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea, +SC_BACKEND_PRIM_FIFO_FULL = 0x000001eb, +SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec, +SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed, +SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee, +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef, +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0, +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1, +SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 0x000001f2, +SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3, +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4, +SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 0x000001f5, +SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 0x000001f6, +SC_STALLED_BY_DB0_TILEFIFO = 0x000001f7, +SC_DB0_QUAD_INTF_SEND = 0x000001f8, +SC_DB0_QUAD_INTF_BUSY = 0x000001f9, +SC_DB0_QUAD_INTF_STALLED_BY_DB = 0x000001fa, +SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 0x000001fb, +SC_DB0_QUAD_INTF_IDLE = 0x000001fc, +SC_DB1_QUAD_INTF_SEND = 0x000001fd, +SC_STALLED_BY_DB1_TILEFIFO = 0x000001fe, +SC_DB1_QUAD_INTF_BUSY = 0x000001ff, +SC_DB1_QUAD_INTF_STALLED_BY_DB = 0x00000200, +SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 0x00000201, +SC_DB1_QUAD_INTF_IDLE = 0x00000202, +SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 0x00000203, +SC_PKR_WAVE_BREAK_FULL_TILE = 0x00000204, +SC_FSR_WALKED = 0x00000205, +SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 0x00000206, +SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 0x00000207, +SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 0x00000208, +SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x00000209, +SC_DB0_TILE_MASK_FIFO_FULL = 0x0000020a, +SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 0x0000020b, +SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x0000020c, +SC_DB1_TILE_MASK_FIFO_FULL = 0x0000020d, +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 0x0000020e, +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 0x0000020f, +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 0x00000210, +SC_PS_PM_PFF_PW_FULL = 0x00000211, +SC_PS_PM_ZFF_PW_FULL = 0x00000212, +SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 0x00000213, +SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 0x00000214, +SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x00000215, +SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x00000216, +SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 0x00000217, +SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 0x00000218, +SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 0x00000219, +SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 0x0000021a, +SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 0x0000021b, +SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 0x0000021c, +SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x0000021d, +SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 0x0000021e, +SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x0000021f, +SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 0x00000220, +SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 0x00000221, +SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 0x00000222, +SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 0x00000223, +SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 0x00000224, +SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 0x00000225, +SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000226, +SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000227, +SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 0x00000228, +SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 0x00000229, +SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 0x0000022a, +SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 0x0000022b, +SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 0x0000022c, +SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 0x0000022d, +SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 0x0000022e, +SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 0x0000022f, +SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 0x00000230, +SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 0x00000231, +SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 0x00000232, +SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 0x00000233, +SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 0x00000234, +SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 0x00000235, +SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 0x00000236, +SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 0x00000237, +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 0x00000238, +SC_PBB_RESERVED = 0x00000239, +SC_BM_BE0_STALLED = 0x0000023a, +SC_BM_BE1_STALLED = 0x0000023b, +SC_BM_BE2_STALLED = 0x0000023c, +SC_BM_BE3_STALLED = 0x0000023d, +SC_BM_MULTI_ACCUM_1_BE_STALLED = 0x0000023e, +SC_BM_MULTI_ACCUM_2_BE_STALLED = 0x0000023f, +SC_BM_MULTI_ACCUM_3_BE_STALLED = 0x00000240, +SC_BM_MULTI_ACCUM_4_BE_STALLED = 0x00000241, +} SC_PERFCNT_SEL; + +/* + * ScMap enum + */ + +typedef enum ScMap { +RASTER_CONFIG_SC_MAP_0 = 0x00000000, +RASTER_CONFIG_SC_MAP_1 = 0x00000001, +RASTER_CONFIG_SC_MAP_2 = 0x00000002, +RASTER_CONFIG_SC_MAP_3 = 0x00000003, +} ScMap; + +/* + * ScUncertaintyRegionMode enum + */ + +typedef enum ScUncertaintyRegionMode { +SC_HALF_LSB = 0x00000000, +SC_LSB_ONE_SIDED = 0x00000001, +SC_LSB_TWO_SIDED = 0x00000002, +} ScUncertaintyRegionMode; + +/* + * ScUncertaintyRegionMult enum + */ + +typedef enum ScUncertaintyRegionMult { +SC_UR_1X = 0x00000000, +SC_UR_2X = 0x00000001, +SC_UR_4X = 0x00000002, +SC_UR_8X = 0x00000003, +} ScUncertaintyRegionMult; + +/* + * ScXsel enum + */ + +typedef enum ScXsel { +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, +} ScXsel; + +/* + * ScYsel enum + */ + +typedef enum ScYsel { +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, +} ScYsel; + +/* + * SeMap enum + */ + +typedef enum SeMap { +RASTER_CONFIG_SE_MAP_0 = 0x00000000, +RASTER_CONFIG_SE_MAP_1 = 0x00000001, +RASTER_CONFIG_SE_MAP_2 = 0x00000002, +RASTER_CONFIG_SE_MAP_3 = 0x00000003, +} SeMap; + +/* + * SePairMap enum + */ + +typedef enum SePairMap { +RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, +RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, +RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, +RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, +} SePairMap; + +/* + * SePairXsel enum + */ + +typedef enum SePairXsel { +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, +} SePairXsel; + +/* + * SePairYsel enum + */ + +typedef enum SePairYsel { +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, +} SePairYsel; + +/* + * SeXsel enum + */ + +typedef enum SeXsel { +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, +} SeXsel; + +/* + * SeYsel enum + */ + +typedef enum SeYsel { +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, +} SeYsel; + +/* + * VRSCombinerModeSC enum + */ + +typedef enum VRSCombinerModeSC { +SC_VRS_COMB_MODE_PASSTHRU = 0x00000000, +SC_VRS_COMB_MODE_OVERRIDE = 0x00000001, +SC_VRS_COMB_MODE_MIN = 0x00000002, +SC_VRS_COMB_MODE_MAX = 0x00000003, +SC_VRS_COMB_MODE_SATURATE = 0x00000004, +} VRSCombinerModeSC; + +/* + * VRSrate enum + */ + +typedef enum VRSrate { +VRS_SHADING_RATE_1X1 = 0x00000000, +VRS_SHADING_RATE_1X2 = 0x00000001, +VRS_SHADING_RATE_UNDEFINED0 = 0x00000002, +VRS_SHADING_RATE_UNDEFINED1 = 0x00000003, +VRS_SHADING_RATE_2X1 = 0x00000004, +VRS_SHADING_RATE_2X2 = 0x00000005, +VRS_SHADING_RATE_2X4 = 0x00000006, +VRS_SHADING_RATE_UNDEFINED2 = 0x00000007, +VRS_SHADING_RATE_UNDEFINED3 = 0x00000008, +VRS_SHADING_RATE_4X2 = 0x00000009, +VRS_SHADING_RATE_4X4 = 0x0000000a, +VRS_SHADING_RATE_UNDEFINED4 = 0x0000000b, +VRS_SHADING_RATE_16X_SSAA = 0x0000000c, +VRS_SHADING_RATE_8X_SSAA = 0x0000000d, +VRS_SHADING_RATE_4X_SSAA = 0x0000000e, +VRS_SHADING_RATE_2X_SSAA = 0x0000000f, +} VRSrate; + +/******************************************************* + * TC Enums + *******************************************************/ + +/* + * TC_EA_CID enum + */ + +typedef enum TC_EA_CID { +TC_EA_CID_RT = 0x00000000, +TC_EA_CID_FMASK = 0x00000001, +TC_EA_CID_DCC = 0x00000002, +TC_EA_CID_TCPMETA = 0x00000003, +TC_EA_CID_Z = 0x00000004, +TC_EA_CID_STENCIL = 0x00000005, +TC_EA_CID_HTILE = 0x00000006, +TC_EA_CID_MISC = 0x00000007, +TC_EA_CID_TCP = 0x00000008, +TC_EA_CID_SQC = 0x00000009, +TC_EA_CID_CPF = 0x0000000a, +TC_EA_CID_CPG = 0x0000000b, +TC_EA_CID_IA = 0x0000000c, +TC_EA_CID_WD = 0x0000000d, +TC_EA_CID_PA = 0x0000000e, +TC_EA_CID_UTCL2_TPI = 0x0000000f, +} TC_EA_CID; + +/* + * TC_NACKS enum + */ + +typedef enum TC_NACKS { +TC_NACK_NO_FAULT = 0x00000000, +TC_NACK_PAGE_FAULT = 0x00000001, +TC_NACK_PROTECTION_FAULT = 0x00000002, +TC_NACK_DATA_ERROR = 0x00000003, +} TC_NACKS; + +/* + * TC_OP enum + */ + +typedef enum TC_OP { +TC_OP_READ = 0x00000000, +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, +TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, +TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, +TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, +TC_OP_RESERVED_FADD_RTN_32 = 0x00000005, +TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, +TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, +TC_OP_PROBE_FILTER = 0x0000000c, +TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, +TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, +TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, +TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, +TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, +TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, +TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, +TC_OP_ATOMIC_AND_RTN_32 = 0x00000015, +TC_OP_ATOMIC_OR_RTN_32 = 0x00000016, +TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017, +TC_OP_ATOMIC_INC_RTN_32 = 0x00000018, +TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019, +TC_OP_WBINVL1_VOL = 0x0000001a, +TC_OP_WBINVL1_SD = 0x0000001b, +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c, +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d, +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e, +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f, +TC_OP_WRITE = 0x00000020, +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, +TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, +TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, +TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, +TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, +TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, +TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, +TC_OP_WBINVL2_SD = 0x0000002c, +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e, +TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, +TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, +TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, +TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, +TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, +TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, +TC_OP_ATOMIC_AND_RTN_64 = 0x00000035, +TC_OP_ATOMIC_OR_RTN_64 = 0x00000036, +TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037, +TC_OP_ATOMIC_INC_RTN_64 = 0x00000038, +TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039, +TC_OP_WBL2_NC = 0x0000003a, +TC_OP_WBL2_WC = 0x0000003b, +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, +TC_OP_WBINVL1 = 0x00000040, +TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, +TC_OP_ATOMIC_FMIN_32 = 0x00000042, +TC_OP_ATOMIC_FMAX_32 = 0x00000043, +TC_OP_RESERVED_FOP_32_0 = 0x00000044, +TC_OP_RESERVED_FADD_32 = 0x00000045, +TC_OP_RESERVED_FOP_32_2 = 0x00000046, +TC_OP_ATOMIC_SWAP_32 = 0x00000047, +TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, +TC_OP_INV_METADATA = 0x0000004c, +TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, +TC_OP_ATOMIC_ADD_32 = 0x0000004f, +TC_OP_ATOMIC_SUB_32 = 0x00000050, +TC_OP_ATOMIC_SMIN_32 = 0x00000051, +TC_OP_ATOMIC_UMIN_32 = 0x00000052, +TC_OP_ATOMIC_SMAX_32 = 0x00000053, +TC_OP_ATOMIC_UMAX_32 = 0x00000054, +TC_OP_ATOMIC_AND_32 = 0x00000055, +TC_OP_ATOMIC_OR_32 = 0x00000056, +TC_OP_ATOMIC_XOR_32 = 0x00000057, +TC_OP_ATOMIC_INC_32 = 0x00000058, +TC_OP_ATOMIC_DEC_32 = 0x00000059, +TC_OP_INVL2_NC = 0x0000005a, +TC_OP_NOP_RTN0 = 0x0000005b, +TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, +TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, +TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, +TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, +TC_OP_WBINVL2 = 0x00000060, +TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, +TC_OP_ATOMIC_FMIN_64 = 0x00000062, +TC_OP_ATOMIC_FMAX_64 = 0x00000063, +TC_OP_RESERVED_FOP_64_0 = 0x00000064, +TC_OP_RESERVED_FOP_64_1 = 0x00000065, +TC_OP_RESERVED_FOP_64_2 = 0x00000066, +TC_OP_ATOMIC_SWAP_64 = 0x00000067, +TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, +TC_OP_ATOMIC_ADD_64 = 0x0000006f, +TC_OP_ATOMIC_SUB_64 = 0x00000070, +TC_OP_ATOMIC_SMIN_64 = 0x00000071, +TC_OP_ATOMIC_UMIN_64 = 0x00000072, +TC_OP_ATOMIC_SMAX_64 = 0x00000073, +TC_OP_ATOMIC_UMAX_64 = 0x00000074, +TC_OP_ATOMIC_AND_64 = 0x00000075, +TC_OP_ATOMIC_OR_64 = 0x00000076, +TC_OP_ATOMIC_XOR_64 = 0x00000077, +TC_OP_ATOMIC_INC_64 = 0x00000078, +TC_OP_ATOMIC_DEC_64 = 0x00000079, +TC_OP_WBINVL2_NC = 0x0000007a, +TC_OP_NOP_ACK = 0x0000007b, +TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, +TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, +TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, +TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, +} TC_OP; + +/* + * TC_OP_MASKS enum + */ + +typedef enum TC_OP_MASKS { +TC_OP_MASK_FLUSH_DENROM = 0x00000008, +TC_OP_MASK_64 = 0x00000020, +TC_OP_MASK_NO_RTN = 0x00000040, +} TC_OP_MASKS; + +/******************************************************* + * GL2 Enums + *******************************************************/ + +/* + * GL2_EA_CID enum + */ + +typedef enum GL2_EA_CID { +GL2_EA_CID_CLIENT = 0x00000000, +GL2_EA_CID_SDMA = 0x00000001, +GL2_EA_CID_RLC = 0x00000002, +GL2_EA_CID_SQC = 0x00000003, +GL2_EA_CID_CP = 0x00000004, +GL2_EA_CID_CPDMA = 0x00000005, +GL2_EA_CID_UTCL2 = 0x00000006, +GL2_EA_CID_RT = 0x00000007, +GL2_EA_CID_FMASK = 0x00000008, +GL2_EA_CID_DCC = 0x00000009, +GL2_EA_CID_Z_STENCIL = 0x0000000a, +GL2_EA_CID_ZPCPSD = 0x0000000b, +GL2_EA_CID_HTILE = 0x0000000c, +GL2_EA_CID_MES = 0x0000000d, +GL2_EA_CID_TCPMETA = 0x0000000f, +} GL2_EA_CID; + +/* + * GL2_NACKS enum + */ + +typedef enum GL2_NACKS { +GL2_NACK_NO_FAULT = 0x00000000, +GL2_NACK_PAGE_FAULT = 0x00000001, +GL2_NACK_PROTECTION_FAULT = 0x00000002, +GL2_NACK_DATA_ERROR = 0x00000003, +} GL2_NACKS; + +/* + * GL2_OP enum + */ + +typedef enum GL2_OP { +GL2_OP_READ = 0x00000000, +GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, +GL2_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, +GL2_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, +GL2_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, +GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, +GL2_OP_PROBE_FILTER = 0x0000000c, +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d, +GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, +GL2_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, +GL2_OP_ATOMIC_SUB_RTN_32 = 0x00000010, +GL2_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, +GL2_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, +GL2_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, +GL2_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, +GL2_OP_ATOMIC_AND_RTN_32 = 0x00000015, +GL2_OP_ATOMIC_OR_RTN_32 = 0x00000016, +GL2_OP_ATOMIC_XOR_RTN_32 = 0x00000017, +GL2_OP_ATOMIC_INC_RTN_32 = 0x00000018, +GL2_OP_ATOMIC_DEC_RTN_32 = 0x00000019, +GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 0x0000001a, +GL2_OP_WRITE = 0x00000020, +GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, +GL2_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, +GL2_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, +GL2_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, +GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, +GL2_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, +GL2_OP_ATOMIC_SUB_RTN_64 = 0x00000030, +GL2_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, +GL2_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, +GL2_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, +GL2_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, +GL2_OP_ATOMIC_AND_RTN_64 = 0x00000035, +GL2_OP_ATOMIC_OR_RTN_64 = 0x00000036, +GL2_OP_ATOMIC_XOR_RTN_64 = 0x00000037, +GL2_OP_ATOMIC_INC_RTN_64 = 0x00000038, +GL2_OP_ATOMIC_DEC_RTN_64 = 0x00000039, +GL2_OP_GL1_INV = 0x00000040, +GL2_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, +GL2_OP_ATOMIC_FMIN_32 = 0x00000042, +GL2_OP_ATOMIC_FMAX_32 = 0x00000043, +GL2_OP_ATOMIC_SWAP_32 = 0x00000047, +GL2_OP_ATOMIC_CMPSWAP_32 = 0x00000048, +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, +GL2_OP_ATOMIC_UMIN_8 = 0x0000004c, +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d, +GL2_OP_ATOMIC_ADD_32 = 0x0000004f, +GL2_OP_ATOMIC_SUB_32 = 0x00000050, +GL2_OP_ATOMIC_SMIN_32 = 0x00000051, +GL2_OP_ATOMIC_UMIN_32 = 0x00000052, +GL2_OP_ATOMIC_SMAX_32 = 0x00000053, +GL2_OP_ATOMIC_UMAX_32 = 0x00000054, +GL2_OP_ATOMIC_AND_32 = 0x00000055, +GL2_OP_ATOMIC_OR_32 = 0x00000056, +GL2_OP_ATOMIC_XOR_32 = 0x00000057, +GL2_OP_ATOMIC_INC_32 = 0x00000058, +GL2_OP_ATOMIC_DEC_32 = 0x00000059, +GL2_OP_NOP_RTN0 = 0x0000005b, +GL2_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, +GL2_OP_ATOMIC_FMIN_64 = 0x00000062, +GL2_OP_ATOMIC_FMAX_64 = 0x00000063, +GL2_OP_ATOMIC_SWAP_64 = 0x00000067, +GL2_OP_ATOMIC_CMPSWAP_64 = 0x00000068, +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, +GL2_OP_ATOMIC_ADD_64 = 0x0000006f, +GL2_OP_ATOMIC_SUB_64 = 0x00000070, +GL2_OP_ATOMIC_SMIN_64 = 0x00000071, +GL2_OP_ATOMIC_UMIN_64 = 0x00000072, +GL2_OP_ATOMIC_SMAX_64 = 0x00000073, +GL2_OP_ATOMIC_UMAX_64 = 0x00000074, +GL2_OP_ATOMIC_AND_64 = 0x00000075, +GL2_OP_ATOMIC_OR_64 = 0x00000076, +GL2_OP_ATOMIC_XOR_64 = 0x00000077, +GL2_OP_ATOMIC_INC_64 = 0x00000078, +GL2_OP_ATOMIC_DEC_64 = 0x00000079, +GL2_OP_ATOMIC_UMAX_8 = 0x0000007a, +GL2_OP_NOP_ACK = 0x0000007b, +} GL2_OP; + +/* + * GL2_OP_MASKS enum + */ + +typedef enum GL2_OP_MASKS { +GL2_OP_MASK_FLUSH_DENROM = 0x00000008, +GL2_OP_MASK_64 = 0x00000020, +GL2_OP_MASK_NO_RTN = 0x00000040, +} GL2_OP_MASKS; + +/******************************************************* + * RLC Enums + *******************************************************/ + +/* + * RLC_DOORBELL_MODE enum + */ + +typedef enum RLC_DOORBELL_MODE { +RLC_DOORBELL_MODE_DISABLE = 0x00000000, +RLC_DOORBELL_MODE_ENABLE = 0x00000001, +RLC_DOORBELL_MODE_ENABLE_PF = 0x00000002, +RLC_DOORBELL_MODE_ENABLE_PF_VF = 0x00000003, +} RLC_DOORBELL_MODE; + +/* + * RLC_PERFCOUNTER_SEL enum + */ + +typedef enum RLC_PERFCOUNTER_SEL { +RLC_PERF_SEL_POWER_FEATURE_0 = 0x00000000, +RLC_PERF_SEL_POWER_FEATURE_1 = 0x00000001, +RLC_PERF_SEL_CP_INTERRUPT = 0x00000002, +RLC_PERF_SEL_GRBM_INTERRUPT = 0x00000003, +RLC_PERF_SEL_SPM_INTERRUPT = 0x00000004, +RLC_PERF_SEL_IH_INTERRUPT = 0x00000005, +RLC_PERF_SEL_SERDES_COMMAND_WRITE = 0x00000006, +} RLC_PERFCOUNTER_SEL; + +/* + * RLC_PERFMON_STATE enum + */ + +typedef enum RLC_PERFMON_STATE { +RLC_PERFMON_STATE_RESET = 0x00000000, +RLC_PERFMON_STATE_ENABLE = 0x00000001, +RLC_PERFMON_STATE_DISABLE = 0x00000002, +RLC_PERFMON_STATE_RESERVED_3 = 0x00000003, +RLC_PERFMON_STATE_RESERVED_4 = 0x00000004, +RLC_PERFMON_STATE_RESERVED_5 = 0x00000005, +RLC_PERFMON_STATE_RESERVED_6 = 0x00000006, +RLC_PERFMON_STATE_ROLLOVER = 0x00000007, +} RLC_PERFMON_STATE; + +/* + * RSPM_CMD enum + */ + +typedef enum RSPM_CMD { +RSPM_CMD_INVALID = 0x00000000, +RSPM_CMD_IDLE = 0x00000001, +RSPM_CMD_CALIBRATE = 0x00000002, +RSPM_CMD_SPM_RESET = 0x00000003, +RSPM_CMD_SPM_START = 0x00000004, +RSPM_CMD_SPM_STOP = 0x00000005, +RSPM_CMD_PERF_RESET = 0x00000006, +RSPM_CMD_PERF_SAMPLE = 0x00000007, +RSPM_CMD_PROF_START = 0x00000008, +RSPM_CMD_PROF_STOP = 0x00000009, +RSPM_CMD_FORCE_SAMPLE = 0x0000000a, +} RSPM_CMD; + +/******************************************************* + * SPI Enums + *******************************************************/ + +/* + * CLKGATE_BASE_MODE enum + */ + +typedef enum CLKGATE_BASE_MODE { +MULT_8 = 0x00000000, +MULT_16 = 0x00000001, +} CLKGATE_BASE_MODE; + +/* + * CLKGATE_SM_MODE enum + */ + +typedef enum CLKGATE_SM_MODE { +ON_SEQ = 0x00000000, +OFF_SEQ = 0x00000001, +PROG_SEQ = 0x00000002, +READ_SEQ = 0x00000003, +SM_MODE_RESERVED = 0x00000004, +} CLKGATE_SM_MODE; + +/* + * SPI_FOG_MODE enum + */ + +typedef enum SPI_FOG_MODE { +SPI_FOG_NONE = 0x00000000, +SPI_FOG_EXP = 0x00000001, +SPI_FOG_EXP2 = 0x00000002, +SPI_FOG_LINEAR = 0x00000003, +} SPI_FOG_MODE; + +/* + * SPI_LB_WAVES_SELECT enum + */ + +typedef enum SPI_LB_WAVES_SELECT { +HS_GS = 0x00000000, +PS = 0x00000001, +CS_NA = 0x00000002, +SPI_LB_WAVES_RSVD = 0x00000003, +} SPI_LB_WAVES_SELECT; + +/* + * SPI_PERFCNT_SEL enum + */ + +typedef enum SPI_PERFCNT_SEL { +SPI_PERF_GS_WINDOW_VALID = 0x00000001, +SPI_PERF_GS_BUSY = 0x00000002, +SPI_PERF_GS_CRAWLER_STALL = 0x00000003, +SPI_PERF_GS_EVENT_WAVE = 0x00000004, +SPI_PERF_GS_WAVE = 0x00000005, +SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000006, +SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000007, +SPI_PERF_GS_FIRST_SUBGRP = 0x00000008, +SPI_PERF_GS_HS_DEALLOC = 0x00000009, +SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000000a, +SPI_PERF_GS_POS0_STALL = 0x0000000b, +SPI_PERF_GS_POS1_STALL = 0x0000000c, +SPI_PERF_GS_INDX0_STALL = 0x0000000d, +SPI_PERF_GS_INDX1_STALL = 0x0000000e, +SPI_PERF_GS_PWS_STALL = 0x0000000f, +SPI_PERF_HS_WINDOW_VALID = 0x00000015, +SPI_PERF_HS_BUSY = 0x00000016, +SPI_PERF_HS_CRAWLER_STALL = 0x00000017, +SPI_PERF_HS_FIRST_WAVE = 0x00000018, +SPI_PERF_HS_OFFCHIP_LDS_STALL = 0x00000019, +SPI_PERF_HS_EVENT_WAVE = 0x0000001a, +SPI_PERF_HS_WAVE = 0x0000001b, +SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000001c, +SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000001d, +SPI_PERF_HS_PWS_STALL = 0x0000001e, +SPI_PERF_CSGN_WINDOW_VALID = 0x00000025, +SPI_PERF_CSGN_BUSY = 0x00000026, +SPI_PERF_CSGN_NUM_THREADGROUPS = 0x00000027, +SPI_PERF_CSGN_CRAWLER_STALL = 0x00000028, +SPI_PERF_CSGN_EVENT_WAVE = 0x00000029, +SPI_PERF_CSGN_WAVE = 0x0000002a, +SPI_PERF_CSGN_PWS_STALL = 0x0000002b, +SPI_PERF_CSN_WINDOW_VALID = 0x0000002c, +SPI_PERF_CSN_BUSY = 0x0000002d, +SPI_PERF_CSN_NUM_THREADGROUPS = 0x0000002e, +SPI_PERF_CSN_CRAWLER_STALL = 0x0000002f, +SPI_PERF_CSN_EVENT_WAVE = 0x00000030, +SPI_PERF_CSN_WAVE = 0x00000031, +SPI_PERF_PS0_WINDOW_VALID = 0x00000035, +SPI_PERF_PS1_WINDOW_VALID = 0x00000036, +SPI_PERF_PS2_WINDOW_VALID = 0x00000037, +SPI_PERF_PS3_WINDOW_VALID = 0x00000038, +SPI_PERF_PS0_BUSY = 0x00000039, +SPI_PERF_PS1_BUSY = 0x0000003a, +SPI_PERF_PS2_BUSY = 0x0000003b, +SPI_PERF_PS3_BUSY = 0x0000003c, +SPI_PERF_PS0_ACTIVE = 0x0000003d, +SPI_PERF_PS1_ACTIVE = 0x0000003e, +SPI_PERF_PS2_ACTIVE = 0x0000003f, +SPI_PERF_PS3_ACTIVE = 0x00000040, +SPI_PERF_PS0_DEALLOC = 0x00000041, +SPI_PERF_PS1_DEALLOC = 0x00000042, +SPI_PERF_PS2_DEALLOC = 0x00000043, +SPI_PERF_PS3_DEALLOC = 0x00000044, +SPI_PERF_PS0_EVENT_WAVE = 0x00000045, +SPI_PERF_PS1_EVENT_WAVE = 0x00000046, +SPI_PERF_PS2_EVENT_WAVE = 0x00000047, +SPI_PERF_PS3_EVENT_WAVE = 0x00000048, +SPI_PERF_PS0_WAVE = 0x00000049, +SPI_PERF_PS1_WAVE = 0x0000004a, +SPI_PERF_PS2_WAVE = 0x0000004b, +SPI_PERF_PS3_WAVE = 0x0000004c, +SPI_PERF_PS0_OPT_WAVE = 0x0000004d, +SPI_PERF_PS1_OPT_WAVE = 0x0000004e, +SPI_PERF_PS2_OPT_WAVE = 0x0000004f, +SPI_PERF_PS3_OPT_WAVE = 0x00000050, +SPI_PERF_PS0_PRIM_BIN0 = 0x00000051, +SPI_PERF_PS1_PRIM_BIN0 = 0x00000052, +SPI_PERF_PS2_PRIM_BIN0 = 0x00000053, +SPI_PERF_PS3_PRIM_BIN0 = 0x00000054, +SPI_PERF_PS0_PRIM_BIN1 = 0x00000055, +SPI_PERF_PS1_PRIM_BIN1 = 0x00000056, +SPI_PERF_PS2_PRIM_BIN1 = 0x00000057, +SPI_PERF_PS3_PRIM_BIN1 = 0x00000058, +SPI_PERF_PS0_CRAWLER_STALL = 0x00000059, +SPI_PERF_PS1_CRAWLER_STALL = 0x0000005a, +SPI_PERF_PS2_CRAWLER_STALL = 0x0000005b, +SPI_PERF_PS3_CRAWLER_STALL = 0x0000005c, +SPI_PERF_PS_PERS_UPD_FULL0 = 0x0000005d, +SPI_PERF_PS_PERS_UPD_FULL1 = 0x0000005e, +SPI_PERF_PS0_2_WAVE_GROUPS = 0x0000005f, +SPI_PERF_PS1_2_WAVE_GROUPS = 0x00000060, +SPI_PERF_PS2_2_WAVE_GROUPS = 0x00000061, +SPI_PERF_PS3_2_WAVE_GROUPS = 0x00000062, +SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 0x00000063, +SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 0x00000064, +SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 0x00000065, +SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 0x00000066, +SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 0x00000067, +SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 0x00000068, +SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 0x00000069, +SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 0x0000006a, +SPI_PERF_PS_PWS_STALL = 0x0000006b, +SPI_PERF_RA_PIPE_REQ_BIN2 = 0x0000008d, +SPI_PERF_RA_TASK_REQ_BIN3 = 0x0000008e, +SPI_PERF_RA_WR_CTL_FULL = 0x0000008f, +SPI_PERF_RA_REQ_NO_ALLOC = 0x00000090, +SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000091, +SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000092, +SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000093, +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x00000094, +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x00000095, +SPI_PERF_RA_RES_STALL_PS = 0x00000096, +SPI_PERF_RA_RES_STALL_GS = 0x00000097, +SPI_PERF_RA_RES_STALL_HS = 0x00000098, +SPI_PERF_RA_RES_STALL_CSG = 0x00000099, +SPI_PERF_RA_RES_STALL_CSN = 0x0000009a, +SPI_PERF_RA_TMP_STALL_PS = 0x0000009b, +SPI_PERF_RA_TMP_STALL_GS = 0x0000009c, +SPI_PERF_RA_TMP_STALL_HS = 0x0000009d, +SPI_PERF_RA_TMP_STALL_CSG = 0x0000009e, +SPI_PERF_RA_TMP_STALL_CSN = 0x0000009f, +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x000000a0, +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x000000a1, +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x000000a2, +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x000000a3, +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x000000a4, +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x000000a5, +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x000000a6, +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x000000a7, +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x000000a8, +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x000000a9, +SPI_PERF_RA_LDS_CU_FULL_PS = 0x000000aa, +SPI_PERF_RA_LDS_CU_FULL_HS = 0x000000ab, +SPI_PERF_RA_LDS_CU_FULL_GS = 0x000000ac, +SPI_PERF_RA_LDS_CU_FULL_CSG = 0x000000ad, +SPI_PERF_RA_LDS_CU_FULL_CSN = 0x000000ae, +SPI_PERF_RA_BAR_CU_FULL_HS = 0x000000af, +SPI_PERF_RA_BAR_CU_FULL_CSG = 0x000000b0, +SPI_PERF_RA_BAR_CU_FULL_CSN = 0x000000b1, +SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x000000b2, +SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x000000b3, +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x000000b4, +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x000000b5, +SPI_PERF_RA_WVLIM_STALL_PS = 0x000000b6, +SPI_PERF_RA_WVLIM_STALL_GS = 0x000000b7, +SPI_PERF_RA_WVLIM_STALL_HS = 0x000000b8, +SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000b9, +SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000ba, +SPI_PERF_RA_GS_LOCK = 0x000000bb, +SPI_PERF_RA_HS_LOCK = 0x000000bc, +SPI_PERF_RA_CSG_LOCK = 0x000000bd, +SPI_PERF_RA_CSN_LOCK = 0x000000be, +SPI_PERF_RA_RSV_UPD = 0x000000bf, +SPI_PERF_RA_PRE_ALLOC_STALL = 0x000000c0, +SPI_PERF_RA_GFX_UNDER_TUNNEL = 0x000000c1, +SPI_PERF_RA_CSC_UNDER_TUNNEL = 0x000000c2, +SPI_PERF_RA_WVALLOC_STALL = 0x000000c3, +SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 0x000000c4, +SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 0x000000c5, +SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 0x000000c6, +SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 0x000000c7, +SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 0x000000c8, +SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 0x000000c9, +SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 0x000000ca, +SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 0x000000cb, +SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 0x000000cc, +SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 0x000000cd, +SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 0x000000ce, +SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 0x000000cf, +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 0x000000d0, +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 0x000000d1, +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 0x000000d2, +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 0x000000d3, +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 0x000000d4, +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 0x000000d5, +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 0x000000d6, +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 0x000000d7, +SPI_PERF_EXP_ARB_COL_CNT = 0x000000d8, +SPI_PERF_EXP_ARB_POS_CNT = 0x000000d9, +SPI_PERF_EXP_ARB_GDS_CNT = 0x000000da, +SPI_PERF_EXP_ARB_IDX_CNT = 0x000000db, +SPI_PERF_EXP_WITH_CONFLICT = 0x000000dc, +SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 0x000000dd, +SPI_PERF_GS_EXP_DONE = 0x000000de, +SPI_PERF_PS_EXP_DONE = 0x000000df, +SPI_PERF_PS_EXP_ARB_CONFLICT = 0x000000e0, +SPI_PERF_PS_EXP_ALLOC = 0x000000e1, +SPI_PERF_PS0_WAVEID_STARVED = 0x000000e2, +SPI_PERF_PS1_WAVEID_STARVED = 0x000000e3, +SPI_PERF_PS2_WAVEID_STARVED = 0x000000e4, +SPI_PERF_PS3_WAVEID_STARVED = 0x000000e5, +SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 0x000000e6, +SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 0x000000e7, +SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 0x000000e8, +SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 0x000000e9, +SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 0x000000ea, +SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 0x000000eb, +SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 0x000000ec, +SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 0x000000ed, +SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 0x000000ee, +SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 0x000000ef, +SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 0x000000f0, +SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 0x000000f1, +SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 0x000000f2, +SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 0x000000f3, +SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 0x000000f4, +SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 0x000000f5, +SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x000000f6, +SPI_PERF_PIX_ALLOC_PEND_CNT = 0x000000fd, +SPI_PERF_EXPORT_SCB0_STALL = 0x000000fe, +SPI_PERF_EXPORT_SCB1_STALL = 0x000000ff, +SPI_PERF_EXPORT_SCB2_STALL = 0x00000100, +SPI_PERF_EXPORT_SCB3_STALL = 0x00000101, +SPI_PERF_EXPORT_DB0_STALL = 0x00000102, +SPI_PERF_EXPORT_DB1_STALL = 0x00000103, +SPI_PERF_EXPORT_DB2_STALL = 0x00000104, +SPI_PERF_EXPORT_DB3_STALL = 0x00000105, +SPI_PERF_EXPORT_DB4_STALL = 0x00000106, +SPI_PERF_EXPORT_DB5_STALL = 0x00000107, +SPI_PERF_EXPORT_DB6_STALL = 0x00000108, +SPI_PERF_EXPORT_DB7_STALL = 0x00000109, +SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x0000010a, +SPI_PERF_GS_NGG_STALL_MSG_VAL = 0x0000010b, +SPI_PERF_SWC_PS_WR = 0x0000010c, +SPI_PERF_SWC_GS_WR = 0x0000010d, +SPI_PERF_SWC_HS_WR = 0x0000010e, +SPI_PERF_SWC_CSGN_WR = 0x0000010f, +SPI_PERF_SWC_CSN_WR = 0x00000110, +SPI_PERF_VWC_PS_WR = 0x00000111, +SPI_PERF_VWC_ES_WR = 0x00000112, +SPI_PERF_VWC_GS_WR = 0x00000113, +SPI_PERF_VWC_LS_WR = 0x00000114, +SPI_PERF_VWC_HS_WR = 0x00000115, +SPI_PERF_VWC_CSGN_WR = 0x00000116, +SPI_PERF_VWC_CSN_WR = 0x00000117, +SPI_PERF_EXP_THROT_UPSTEP = 0x00000118, +SPI_PERF_EXP_THROT_DOWNSTEP = 0x00000119, +SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 0x0000011a, +SPI_PERF_BUSY = 0x0000011b, +} SPI_PERFCNT_SEL; + +/* + * SPI_PNT_SPRITE_OVERRIDE enum + */ + +typedef enum SPI_PNT_SPRITE_OVERRIDE { +SPI_PNT_SPRITE_SEL_0 = 0x00000000, +SPI_PNT_SPRITE_SEL_1 = 0x00000001, +SPI_PNT_SPRITE_SEL_S = 0x00000002, +SPI_PNT_SPRITE_SEL_T = 0x00000003, +SPI_PNT_SPRITE_SEL_NONE = 0x00000004, +} SPI_PNT_SPRITE_OVERRIDE; + +/* + * SPI_PS_LDS_GROUP_SIZE enum + */ + +typedef enum SPI_PS_LDS_GROUP_SIZE { +SPI_PS_LDS_GROUP_1 = 0x00000000, +SPI_PS_LDS_GROUP_2 = 0x00000001, +SPI_PS_LDS_GROUP_4 = 0x00000002, +} SPI_PS_LDS_GROUP_SIZE; + +/* + * SPI_SAMPLE_CNTL enum + */ + +typedef enum SPI_SAMPLE_CNTL { +CENTROIDS_ONLY = 0x00000000, +CENTERS_ONLY = 0x00000001, +CENTROIDS_AND_CENTERS = 0x00000002, +UNDEF = 0x00000003, +} SPI_SAMPLE_CNTL; + +/* + * SPI_SHADER_EX_FORMAT enum + */ + +typedef enum SPI_SHADER_EX_FORMAT { +SPI_SHADER_ZERO = 0x00000000, +SPI_SHADER_32_R = 0x00000001, +SPI_SHADER_32_GR = 0x00000002, +SPI_SHADER_32_AR = 0x00000003, +SPI_SHADER_FP16_ABGR = 0x00000004, +SPI_SHADER_UNORM16_ABGR = 0x00000005, +SPI_SHADER_SNORM16_ABGR = 0x00000006, +SPI_SHADER_UINT16_ABGR = 0x00000007, +SPI_SHADER_SINT16_ABGR = 0x00000008, +SPI_SHADER_32_ABGR = 0x00000009, +} SPI_SHADER_EX_FORMAT; + +/* + * SPI_SHADER_FORMAT enum + */ + +typedef enum SPI_SHADER_FORMAT { +SPI_SHADER_NONE = 0x00000000, +SPI_SHADER_1COMP = 0x00000001, +SPI_SHADER_2COMP = 0x00000002, +SPI_SHADER_4COMPRESS = 0x00000003, +SPI_SHADER_4COMP = 0x00000004, +} SPI_SHADER_FORMAT; + +/******************************************************* + * SQ Enums + *******************************************************/ + +/* + * SH_MEM_ADDRESS_MODE enum + */ + +typedef enum SH_MEM_ADDRESS_MODE { +SH_MEM_ADDRESS_MODE_64 = 0x00000000, +SH_MEM_ADDRESS_MODE_32 = 0x00000001, +} SH_MEM_ADDRESS_MODE; + +/* + * SH_MEM_ALIGNMENT_MODE enum + */ + +typedef enum SH_MEM_ALIGNMENT_MODE { +SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, +SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, +} SH_MEM_ALIGNMENT_MODE; + +/* + * SQG_PERF_SEL enum + */ + +typedef enum SQG_PERF_SEL { +SQG_PERF_SEL_NONE = 0x00000000, +SQG_PERF_SEL_MSG_BUS_BUSY = 0x00000001, +SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000002, +SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000003, +SQG_PERF_SEL_EXP_BUS0_BUSY = 0x00000004, +SQG_PERF_SEL_EXP_BUS1_BUSY = 0x00000005, +SQG_PERF_SEL_TTRACE_REQS = 0x00000006, +SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000007, +SQG_PERF_SEL_TTRACE_STALL = 0x00000008, +SQG_PERF_SEL_TTRACE_LOST_PACKETS = 0x00000009, +SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x0000000a, +SQG_PERF_SEL_EVENTS = 0x0000000b, +SQG_PERF_SEL_WAVES_RESTORED = 0x0000000c, +SQG_PERF_SEL_WAVES_SAVED = 0x0000000d, +SQG_PERF_SEL_ACCUM_PREV = 0x0000000e, +SQG_PERF_SEL_CYCLES = 0x0000000f, +SQG_PERF_SEL_BUSY_CYCLES = 0x00000010, +SQG_PERF_SEL_WAVE_CYCLES = 0x00000011, +SQG_PERF_SEL_MSG = 0x00000012, +SQG_PERF_SEL_MSG_INTERRUPT = 0x00000013, +SQG_PERF_SEL_WAVES = 0x00000014, +SQG_PERF_SEL_WAVES_32 = 0x00000015, +SQG_PERF_SEL_WAVES_64 = 0x00000016, +SQG_PERF_SEL_LEVEL_WAVES = 0x00000017, +SQG_PERF_SEL_ITEMS = 0x00000018, +SQG_PERF_SEL_WAVE32_ITEMS = 0x00000019, +SQG_PERF_SEL_WAVE64_ITEMS = 0x0000001a, +SQG_PERF_SEL_PS_QUADS = 0x0000001b, +SQG_PERF_SEL_WAVES_EQ_64 = 0x0000001c, +SQG_PERF_SEL_WAVES_EQ_32 = 0x0000001d, +SQG_PERF_SEL_WAVES_LT_64 = 0x0000001e, +SQG_PERF_SEL_WAVES_LT_48 = 0x0000001f, +SQG_PERF_SEL_WAVES_LT_32 = 0x00000020, +SQG_PERF_SEL_WAVES_LT_16 = 0x00000021, +SQG_PERF_SEL_DUMMY_LAST = 0x00000022, +} SQG_PERF_SEL; + +/* + * SQ_CAC_POWER_SEL enum + */ + +typedef enum SQ_CAC_POWER_SEL { +SQ_CAC_POWER_VALU = 0x00000000, +SQ_CAC_POWER_VALU0 = 0x00000001, +SQ_CAC_POWER_VALU1 = 0x00000002, +SQ_CAC_POWER_VALU2 = 0x00000003, +SQ_CAC_POWER_GPR_RD = 0x00000004, +SQ_CAC_POWER_GPR_WR = 0x00000005, +SQ_CAC_POWER_LDS_BUSY = 0x00000006, +SQ_CAC_POWER_ALU_BUSY = 0x00000007, +SQ_CAC_POWER_TEX_BUSY = 0x00000008, +} SQ_CAC_POWER_SEL; + +/* + * SQ_EDC_INFO_SOURCE enum + */ + +typedef enum SQ_EDC_INFO_SOURCE { +SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, +SQ_EDC_INFO_SOURCE_INST = 0x00000001, +SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, +SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, +SQ_EDC_INFO_SOURCE_LDS = 0x00000004, +SQ_EDC_INFO_SOURCE_GDS = 0x00000005, +SQ_EDC_INFO_SOURCE_TA = 0x00000006, +} SQ_EDC_INFO_SOURCE; + +/* + * SQ_IBUF_ST enum + */ + +typedef enum SQ_IBUF_ST { +SQ_IBUF_IB_IDLE = 0x00000000, +SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, +SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, +SQ_IBUF_IB_LE_4DW = 0x00000003, +SQ_IBUF_IB_WAIT_DRET = 0x00000004, +SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, +SQ_IBUF_IB_DRET = 0x00000006, +SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, +} SQ_IBUF_ST; + +/* + * SQ_IMG_FILTER_TYPE enum + */ + +typedef enum SQ_IMG_FILTER_TYPE { +SQ_IMG_FILTER_MODE_BLEND = 0x00000000, +SQ_IMG_FILTER_MODE_MIN = 0x00000001, +SQ_IMG_FILTER_MODE_MAX = 0x00000002, +} SQ_IMG_FILTER_TYPE; + +/* + * SQ_IND_CMD_CMD enum + */ + +typedef enum SQ_IND_CMD_CMD { +SQ_IND_CMD_CMD_NULL = 0x00000000, +SQ_IND_CMD_CMD_SETHALT = 0x00000001, +SQ_IND_CMD_CMD_SAVECTX = 0x00000002, +SQ_IND_CMD_CMD_KILL = 0x00000003, +SQ_IND_CMD_CMD_TRAP_AFTER_INST = 0x00000004, +SQ_IND_CMD_CMD_TRAP = 0x00000005, +SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006, +SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007, +SQ_IND_CMD_CMD_SINGLE_STEP = 0x00000008, +} SQ_IND_CMD_CMD; + +/* + * SQ_IND_CMD_MODE enum + */ + +typedef enum SQ_IND_CMD_MODE { +SQ_IND_CMD_MODE_SINGLE = 0x00000000, +SQ_IND_CMD_MODE_BROADCAST = 0x00000001, +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, +SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, +SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, +} SQ_IND_CMD_MODE; + +/* + * SQ_INST_STR_ST enum + */ + +typedef enum SQ_INST_STR_ST { +SQ_INST_STR_IB_WAVE_NORML = 0x00000000, +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000004, +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000005, +} SQ_INST_STR_ST; + +/* + * SQ_INST_TYPE enum + */ + +typedef enum SQ_INST_TYPE { +SQ_INST_TYPE_VALU = 0x00000000, +SQ_INST_TYPE_SCALAR = 0x00000001, +SQ_INST_TYPE_TEX = 0x00000002, +SQ_INST_TYPE_LDS = 0x00000003, +SQ_INST_TYPE_LDS_DIRECT = 0x00000004, +SQ_INST_TYPE_EXP = 0x00000005, +SQ_INST_TYPE_MSG = 0x00000006, +SQ_INST_TYPE_BARRIER = 0x00000007, +SQ_INST_TYPE_BRANCH_NOT_TAKEN = 0x00000008, +SQ_INST_TYPE_BRANCH_TAKEN = 0x00000009, +SQ_INST_TYPE_JUMP = 0x0000000a, +SQ_INST_TYPE_OTHER = 0x0000000b, +SQ_INST_TYPE_NONE = 0x0000000c, +} SQ_INST_TYPE; + +/* + * SQ_LLC_CTL enum + */ + +typedef enum SQ_LLC_CTL { +SQ_LLC_0 = 0x00000000, +SQ_LLC_1 = 0x00000001, +SQ_LLC_RSVD_2 = 0x00000002, +SQ_LLC_BYPASS = 0x00000003, +} SQ_LLC_CTL; + +/* + * SQ_NO_INST_ISSUE enum + */ + +typedef enum SQ_NO_INST_ISSUE { +SQ_NO_INST_ISSUE_NO_INSTS = 0x00000000, +SQ_NO_INST_ISSUE_ALU_DEP = 0x00000001, +SQ_NO_INST_ISSUE_S_WAITCNT = 0x00000002, +SQ_NO_INST_ISSUE_NO_ARB_WIN = 0x00000003, +SQ_NO_INST_ISSUE_SLEEP_WAIT = 0x00000004, +SQ_NO_INST_ISSUE_BARRIER_WAIT = 0x00000005, +SQ_NO_INST_ISSUE_OTHER = 0x00000006, +} SQ_NO_INST_ISSUE; + +/* + * SQ_OOB_SELECT enum + */ + +typedef enum SQ_OOB_SELECT { +SQ_OOB_INDEX_AND_OFFSET = 0x00000000, +SQ_OOB_INDEX_ONLY = 0x00000001, +SQ_OOB_NUM_RECORDS_0 = 0x00000002, +SQ_OOB_COMPLETE = 0x00000003, +} SQ_OOB_SELECT; + +/* + * SQ_PERF_SEL enum + */ + +typedef enum SQ_PERF_SEL { +SQ_PERF_SEL_NONE = 0x00000000, +SQ_PERF_SEL_ACCUM_PREV = 0x00000001, +SQ_PERF_SEL_CYCLES = 0x00000002, +SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, +SQ_PERF_SEL_WAVES = 0x00000004, +SQ_PERF_SEL_WAVES_32 = 0x00000005, +SQ_PERF_SEL_WAVES_64 = 0x00000006, +SQ_PERF_SEL_LEVEL_WAVES = 0x00000007, +SQ_PERF_SEL_ITEMS = 0x00000008, +SQ_PERF_SEL_WAVE32_ITEMS = 0x00000009, +SQ_PERF_SEL_WAVE64_ITEMS = 0x0000000a, +SQ_PERF_SEL_PS_QUADS = 0x0000000b, +SQ_PERF_SEL_EVENTS = 0x0000000c, +SQ_PERF_SEL_WAVES_EQ_32 = 0x0000000d, +SQ_PERF_SEL_WAVES_EQ_64 = 0x0000000e, +SQ_PERF_SEL_WAVES_LT_64 = 0x0000000f, +SQ_PERF_SEL_WAVES_LT_48 = 0x00000010, +SQ_PERF_SEL_WAVES_LT_32 = 0x00000011, +SQ_PERF_SEL_WAVES_LT_16 = 0x00000012, +SQ_PERF_SEL_WAVES_RESTORED = 0x00000013, +SQ_PERF_SEL_WAVES_SAVED = 0x00000014, +SQ_PERF_SEL_MSG = 0x00000015, +SQ_PERF_SEL_MSG_INTERRUPT = 0x00000016, +SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x00000017, +SQ_PERF_SEL_WAVE_CYCLES = 0x00000018, +SQ_PERF_SEL_WAVE_READY = 0x00000019, +SQ_PERF_SEL_WAIT_INST_ANY = 0x0000001a, +SQ_PERF_SEL_WAIT_INST_VALU = 0x0000001b, +SQ_PERF_SEL_WAIT_INST_SCA = 0x0000001c, +SQ_PERF_SEL_WAIT_INST_LDS = 0x0000001d, +SQ_PERF_SEL_WAIT_INST_TEX = 0x0000001e, +SQ_PERF_SEL_WAIT_INST_FLAT = 0x0000001f, +SQ_PERF_SEL_WAIT_INST_VMEM = 0x00000020, +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000021, +SQ_PERF_SEL_WAIT_INST_BR_MSG = 0x00000022, +SQ_PERF_SEL_WAIT_ANY = 0x00000023, +SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000024, +SQ_PERF_SEL_WAIT_CNT_VMVS = 0x00000025, +SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000026, +SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000027, +SQ_PERF_SEL_WAIT_TTRACE = 0x00000028, +SQ_PERF_SEL_WAIT_IFETCH = 0x00000029, +SQ_PERF_SEL_WAIT_BARRIER = 0x0000002a, +SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x0000002b, +SQ_PERF_SEL_WAIT_SLEEP = 0x0000002c, +SQ_PERF_SEL_WAIT_DELAY_ALU = 0x0000002d, +SQ_PERF_SEL_WAIT_DEPCTR = 0x0000002e, +SQ_PERF_SEL_WAIT_OTHER = 0x0000002f, +SQ_PERF_SEL_INSTS_ALL = 0x00000030, +SQ_PERF_SEL_INSTS_BRANCH = 0x00000031, +SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 0x00000032, +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 0x00000033, +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 0x00000034, +SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000035, +SQ_PERF_SEL_INSTS_GDS = 0x00000036, +SQ_PERF_SEL_INSTS_EXP = 0x00000037, +SQ_PERF_SEL_INSTS_FLAT = 0x00000038, +SQ_PERF_SEL_INSTS_LDS = 0x00000039, +SQ_PERF_SEL_INSTS_SALU = 0x0000003a, +SQ_PERF_SEL_INSTS_SMEM = 0x0000003b, +SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000003c, +SQ_PERF_SEL_INSTS_SENDMSG = 0x0000003d, +SQ_PERF_SEL_INSTS_VALU = 0x0000003e, +SQ_PERF_SEL_INSTS_VALU_TRANS32 = 0x0000003f, +SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 0x00000040, +SQ_PERF_SEL_INSTS_TEX = 0x00000041, +SQ_PERF_SEL_INSTS_TEX_LOAD = 0x00000042, +SQ_PERF_SEL_INSTS_TEX_STORE = 0x00000043, +SQ_PERF_SEL_INSTS_DELAY_ALU = 0x00000044, +SQ_PERF_SEL_INSTS_INTERNAL = 0x00000045, +SQ_PERF_SEL_INSTS_WAVE32 = 0x00000046, +SQ_PERF_SEL_INSTS_WAVE32_FLAT = 0x00000047, +SQ_PERF_SEL_INSTS_WAVE32_LDS = 0x00000048, +SQ_PERF_SEL_INSTS_WAVE32_VALU = 0x00000049, +SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 0x0000004a, +SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 0x0000004b, +SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 0x0000004c, +SQ_PERF_SEL_INSTS_WAVE32_TEX = 0x0000004d, +SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 0x0000004e, +SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 0x0000004f, +SQ_PERF_SEL_ITEM_CYCLES_VALU = 0x00000050, +SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 0x00000051, +SQ_PERF_SEL_WAVE32_INSTS = 0x00000052, +SQ_PERF_SEL_WAVE64_INSTS = 0x00000053, +SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 0x00000054, +SQ_PERF_SEL_WAVE64_HALF_SKIP = 0x00000055, +SQ_PERF_SEL_INST_LEVEL_EXP = 0x00000056, +SQ_PERF_SEL_INST_LEVEL_GDS = 0x00000057, +SQ_PERF_SEL_INST_LEVEL_LDS = 0x00000058, +SQ_PERF_SEL_INST_LEVEL_SMEM = 0x00000059, +SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 0x0000005a, +SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 0x0000005b, +SQ_PERF_SEL_IFETCH_REQS = 0x0000005c, +SQ_PERF_SEL_IFETCH_LEVEL = 0x0000005d, +SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x0000005e, +SQ_PERF_SEL_VALU_SGATHER_STALL = 0x0000005f, +SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 0x00000060, +SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x00000061, +SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 0x00000062, +SQ_PERF_SEL_SALU_SGATHER_STALL = 0x00000063, +SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000064, +SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 0x00000065, +SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 0x00000066, +SQ_PERF_SEL_INST_CYCLES_VALU = 0x00000067, +SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 0x00000068, +SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 0x00000069, +SQ_PERF_SEL_INST_CYCLES_VMEM = 0x0000006a, +SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 0x0000006b, +SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 0x0000006c, +SQ_PERF_SEL_INST_CYCLES_LDS = 0x0000006d, +SQ_PERF_SEL_INST_CYCLES_TEX = 0x0000006e, +SQ_PERF_SEL_INST_CYCLES_FLAT = 0x0000006f, +SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x00000070, +SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000071, +SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000072, +SQ_PERF_SEL_VALU_STARVE = 0x00000073, +SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 0x00000074, +SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 0x00000075, +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000076, +SQ_PERF_SEL_VMEM_BUS_ACTIVE = 0x00000077, +SQ_PERF_SEL_VMEM_BUS_STALL = 0x00000078, +SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x00000079, +SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x0000007a, +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x0000007b, +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x0000007c, +SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 0x0000007d, +SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 0x0000007e, +SQ_PERF_SEL_SALU_PIPE_STALL = 0x0000007f, +SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 0x00000080, +SQ_PERF_SEL_MSG_BUS_BUSY = 0x00000081, +SQ_PERF_SEL_EXP_REQ_BUS_STALL = 0x00000082, +SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000083, +SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000084, +SQ_PERF_SEL_EXP_BUS0_BUSY = 0x00000085, +SQ_PERF_SEL_EXP_BUS1_BUSY = 0x00000086, +SQ_PERF_SEL_INST_CACHE_REQ_STALL = 0x00000087, +SQ_PERF_SEL_USER0 = 0x00000088, +SQ_PERF_SEL_USER1 = 0x00000089, +SQ_PERF_SEL_USER2 = 0x0000008a, +SQ_PERF_SEL_USER3 = 0x0000008b, +SQ_PERF_SEL_USER4 = 0x0000008c, +SQ_PERF_SEL_USER5 = 0x0000008d, +SQ_PERF_SEL_USER6 = 0x0000008e, +SQ_PERF_SEL_USER7 = 0x0000008f, +SQ_PERF_SEL_USER8 = 0x00000090, +SQ_PERF_SEL_USER9 = 0x00000091, +SQ_PERF_SEL_USER10 = 0x00000092, +SQ_PERF_SEL_USER11 = 0x00000093, +SQ_PERF_SEL_USER12 = 0x00000094, +SQ_PERF_SEL_USER13 = 0x00000095, +SQ_PERF_SEL_USER14 = 0x00000096, +SQ_PERF_SEL_USER15 = 0x00000097, +SQ_PERF_SEL_USER_LEVEL0 = 0x00000098, +SQ_PERF_SEL_USER_LEVEL1 = 0x00000099, +SQ_PERF_SEL_USER_LEVEL2 = 0x0000009a, +SQ_PERF_SEL_USER_LEVEL3 = 0x0000009b, +SQ_PERF_SEL_USER_LEVEL4 = 0x0000009c, +SQ_PERF_SEL_USER_LEVEL5 = 0x0000009d, +SQ_PERF_SEL_USER_LEVEL6 = 0x0000009e, +SQ_PERF_SEL_USER_LEVEL7 = 0x0000009f, +SQ_PERF_SEL_USER_LEVEL8 = 0x000000a0, +SQ_PERF_SEL_USER_LEVEL9 = 0x000000a1, +SQ_PERF_SEL_USER_LEVEL10 = 0x000000a2, +SQ_PERF_SEL_USER_LEVEL11 = 0x000000a3, +SQ_PERF_SEL_USER_LEVEL12 = 0x000000a4, +SQ_PERF_SEL_USER_LEVEL13 = 0x000000a5, +SQ_PERF_SEL_USER_LEVEL14 = 0x000000a6, +SQ_PERF_SEL_USER_LEVEL15 = 0x000000a7, +SQ_PERF_SEL_VALU_RETURN_SDST = 0x000000a8, +SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 0x000000a9, +SQ_PERF_SEL_INSTS_VALU_TRANS = 0x000000aa, +SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 0x000000ab, +SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 0x000000ac, +SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 0x000000ad, +SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 0x000000ae, +SQ_PERF_SEL_INSTS_VALU_VINTERP = 0x000000af, +SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 0x000000b0, +SQ_PERF_SEL_OVERFLOW_PREV = 0x000000b1, +SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 0x000000b2, +SQ_PERF_SEL_INSTS_VALU_1_PASS = 0x000000b3, +SQ_PERF_SEL_INSTS_VALU_2_PASS = 0x000000b4, +SQ_PERF_SEL_INSTS_VALU_4_PASS = 0x000000b5, +SQ_PERF_SEL_INSTS_VALU_DP = 0x000000b6, +SQ_PERF_SEL_SP_CONST_CYCLES = 0x000000b7, +SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 0x000000b8, +SQ_PERF_SEL_ITEMS_VALU = 0x000000b9, +SQ_PERF_SEL_ITEMS_MAX_VALU = 0x000000ba, +SQ_PERF_SEL_ITEM_CYCLES_VMEM = 0x000000bb, +SQ_PERF_SEL_DUMMY_END = 0x000000bc, +SQ_PERF_SEL_DUMMY_LAST = 0x000000ff, +SQC_PERF_SEL_LDS_BANK_CONFLICT = 0x00000100, +SQC_PERF_SEL_LDS_ADDR_CONFLICT = 0x00000101, +SQC_PERF_SEL_LDS_UNALIGNED_STALL = 0x00000102, +SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000103, +SQC_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000104, +SQC_PERF_SEL_LDS_IDX_ACTIVE = 0x00000105, +SQC_PERF_SEL_LDS_ADDR_STALL = 0x00000106, +SQC_PERF_SEL_LDS_ADDR_ACTIVE = 0x00000107, +SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 0x00000108, +SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000109, +SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 0x0000010a, +SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 0x0000010b, +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010c, +SQC_PERF_SEL_ICACHE_REQ = 0x0000010d, +SQC_PERF_SEL_ICACHE_HITS = 0x0000010e, +SQC_PERF_SEL_ICACHE_MISSES = 0x0000010f, +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000110, +SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000111, +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000112, +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000113, +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000114, +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000115, +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000116, +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000117, +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000118, +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000119, +SQC_PERF_SEL_TC_REQ = 0x0000011a, +SQC_PERF_SEL_TC_INST_REQ = 0x0000011b, +SQC_PERF_SEL_TC_DATA_READ_REQ = 0x0000011c, +SQC_PERF_SEL_TC_STALL = 0x0000011d, +SQC_PERF_SEL_TC_STARVE = 0x0000011e, +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000011f, +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000120, +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000121, +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000122, +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000123, +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000124, +SQC_PERF_SEL_DCACHE_REQ = 0x00000125, +SQC_PERF_SEL_DCACHE_HITS = 0x00000126, +SQC_PERF_SEL_DCACHE_MISSES = 0x00000127, +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000128, +SQC_PERF_SEL_DCACHE_INVAL_INST = 0x00000129, +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012a, +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x0000012b, +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000012c, +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000012d, +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x0000012e, +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x0000012f, +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000130, +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000131, +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000132, +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000133, +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000134, +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000135, +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000136, +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x00000137, +SQC_PERF_SEL_SQ_DCACHE_REQS = 0x00000138, +SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x00000139, +SQC_PERF_SEL_TD_VGPR_BUSY = 0x0000013a, +SQC_PERF_SEL_LDS_VGPR_BUSY = 0x0000013b, +SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 0x0000013c, +SQC_PERF_SEL_ICACHE_GCR = 0x0000013d, +SQC_PERF_SEL_ICACHE_GCR_HITS = 0x0000013e, +SQC_PERF_SEL_DCACHE_GCR = 0x0000013f, +SQC_PERF_SEL_DCACHE_GCR_HITS = 0x00000140, +SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 0x00000141, +SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 0x00000142, +SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 0x00000143, +SQC_PERF_SEL_DUMMY_LAST = 0x00000144, +SP_PERF_SEL_DST_BUF_ALLOC_STALL = 0x000001c0, +SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 0x000001c1, +SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 0x000001c2, +SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 0x000001c3, +SP_PERF_SEL_DST_BUF_ODD_DIRTY = 0x000001c4, +SP_PERF_SEL_SRC_CACHE_HIT_B0 = 0x000001c5, +SP_PERF_SEL_SRC_CACHE_HIT_B1 = 0x000001c6, +SP_PERF_SEL_SRC_CACHE_HIT_B2 = 0x000001c7, +SP_PERF_SEL_SRC_CACHE_HIT_B3 = 0x000001c8, +SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 0x000001c9, +SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 0x000001ca, +SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 0x000001cb, +SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 0x000001cc, +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 0x000001cd, +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 0x000001ce, +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 0x000001cf, +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 0x000001d0, +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 0x000001d1, +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 0x000001d2, +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 0x000001d3, +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 0x000001d4, +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 0x000001d5, +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 0x000001d6, +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 0x000001d7, +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 0x000001d8, +SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 0x000001d9, +SP_PERF_SEL_VALU_OPERAND = 0x000001da, +SP_PERF_SEL_VALU_VGPR_OPERAND = 0x000001db, +SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 0x000001dc, +SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 0x000001dd, +SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 0x000001de, +SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 0x000001df, +SP_PERF_SEL_VALU_STALL = 0x000001e0, +SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 0x000001e1, +SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 0x000001e2, +SP_PERF_SEL_VALU_STALL_VDST_FWD = 0x000001e3, +SP_PERF_SEL_VALU_STALL_SDST_FWD = 0x000001e4, +SP_PERF_SEL_VALU_STALL_DST_STALL = 0x000001e5, +SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 0x000001e6, +SP_PERF_SEL_VGPR_VMEM_RD = 0x000001e7, +SP_PERF_SEL_VGPR_EXP_RD = 0x000001e8, +SP_PERF_SEL_VGPR_SPI_WR = 0x000001e9, +SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 0x000001ea, +SP_PERF_SEL_VGPR_WR = 0x000001eb, +SP_PERF_SEL_VGPR_RD = 0x000001ec, +SP_PERF_SEL_DUMMY_LAST = 0x000001ed, +SQ_PERF_SEL_NONE2 = 0x000001ff, +} SQ_PERF_SEL; + +/* + * SQ_ROUND_MODE enum + */ + +typedef enum SQ_ROUND_MODE { +SQ_ROUND_NEAREST_EVEN = 0x00000000, +SQ_ROUND_PLUS_INFINITY = 0x00000001, +SQ_ROUND_MINUS_INFINITY = 0x00000002, +SQ_ROUND_TO_ZERO = 0x00000003, +} SQ_ROUND_MODE; + +/* + * SQ_RSRC_BUF_TYPE enum + */ + +typedef enum SQ_RSRC_BUF_TYPE { +SQ_RSRC_BUF = 0x00000000, +SQ_RSRC_BUF_RSVD_1 = 0x00000001, +SQ_RSRC_BUF_RSVD_2 = 0x00000002, +SQ_RSRC_BUF_RSVD_3 = 0x00000003, +} SQ_RSRC_BUF_TYPE; + +/* + * SQ_RSRC_FLAT_TYPE enum + */ + +typedef enum SQ_RSRC_FLAT_TYPE { +SQ_RSRC_FLAT_RSVD_0 = 0x00000000, +SQ_RSRC_FLAT = 0x00000001, +SQ_RSRC_FLAT_RSVD_2 = 0x00000002, +SQ_RSRC_FLAT_RSVD_3 = 0x00000003, +} SQ_RSRC_FLAT_TYPE; + +/* + * SQ_RSRC_IMG_TYPE enum + */ + +typedef enum SQ_RSRC_IMG_TYPE { +SQ_RSRC_IMG_RSVD_0 = 0x00000000, +SQ_RSRC_IMG_RSVD_1 = 0x00000001, +SQ_RSRC_IMG_RSVD_2 = 0x00000002, +SQ_RSRC_IMG_RSVD_3 = 0x00000003, +SQ_RSRC_IMG_RSVD_4 = 0x00000004, +SQ_RSRC_IMG_RSVD_5 = 0x00000005, +SQ_RSRC_IMG_RSVD_6 = 0x00000006, +SQ_RSRC_IMG_RSVD_7 = 0x00000007, +SQ_RSRC_IMG_1D = 0x00000008, +SQ_RSRC_IMG_2D = 0x00000009, +SQ_RSRC_IMG_3D = 0x0000000a, +SQ_RSRC_IMG_CUBE = 0x0000000b, +SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, +SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, +SQ_RSRC_IMG_2D_MSAA = 0x0000000e, +SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, +} SQ_RSRC_IMG_TYPE; + +/* + * SQ_SEL_XYZW01 enum + */ + +typedef enum SQ_SEL_XYZW01 { +SQ_SEL_0 = 0x00000000, +SQ_SEL_1 = 0x00000001, +SQ_SEL_N_BC_1 = 0x00000002, +SQ_SEL_RESERVED_1 = 0x00000003, +SQ_SEL_X = 0x00000004, +SQ_SEL_Y = 0x00000005, +SQ_SEL_Z = 0x00000006, +SQ_SEL_W = 0x00000007, +} SQ_SEL_XYZW01; + +/* + * SQ_TEX_ANISO_RATIO enum + */ + +typedef enum SQ_TEX_ANISO_RATIO { +SQ_TEX_ANISO_RATIO_1 = 0x00000000, +SQ_TEX_ANISO_RATIO_2 = 0x00000001, +SQ_TEX_ANISO_RATIO_4 = 0x00000002, +SQ_TEX_ANISO_RATIO_8 = 0x00000003, +SQ_TEX_ANISO_RATIO_16 = 0x00000004, +} SQ_TEX_ANISO_RATIO; + +/* + * SQ_TEX_BORDER_COLOR enum + */ + +typedef enum SQ_TEX_BORDER_COLOR { +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, +SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, +} SQ_TEX_BORDER_COLOR; + +/* + * SQ_TEX_CLAMP enum + */ + +typedef enum SQ_TEX_CLAMP { +SQ_TEX_WRAP = 0x00000000, +SQ_TEX_MIRROR = 0x00000001, +SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, +SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, +SQ_TEX_CLAMP_BORDER = 0x00000006, +SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, +} SQ_TEX_CLAMP; + +/* + * SQ_TEX_DEPTH_COMPARE enum + */ + +typedef enum SQ_TEX_DEPTH_COMPARE { +SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, +SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, +SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, +SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, +SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, +} SQ_TEX_DEPTH_COMPARE; + +/* + * SQ_TEX_MIP_FILTER enum + */ + +typedef enum SQ_TEX_MIP_FILTER { +SQ_TEX_MIP_FILTER_NONE = 0x00000000, +SQ_TEX_MIP_FILTER_POINT = 0x00000001, +SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003, +} SQ_TEX_MIP_FILTER; + +/* + * SQ_TEX_XY_FILTER enum + */ + +typedef enum SQ_TEX_XY_FILTER { +SQ_TEX_XY_FILTER_POINT = 0x00000000, +SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, +SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, +} SQ_TEX_XY_FILTER; + +/* + * SQ_TEX_Z_FILTER enum + */ + +typedef enum SQ_TEX_Z_FILTER { +SQ_TEX_Z_FILTER_NONE = 0x00000000, +SQ_TEX_Z_FILTER_POINT = 0x00000001, +SQ_TEX_Z_FILTER_LINEAR = 0x00000002, +} SQ_TEX_Z_FILTER; + +/* + * SQ_TT_MODE enum + */ + +typedef enum SQ_TT_MODE { +SQ_TT_MODE_OFF = 0x00000000, +SQ_TT_MODE_ON = 0x00000001, +SQ_TT_MODE_GLOBAL = 0x00000002, +SQ_TT_MODE_DETAIL = 0x00000003, +} SQ_TT_MODE; + +/* + * SQ_TT_RT_FREQ enum + */ + +typedef enum SQ_TT_RT_FREQ { +SQ_TT_RT_FREQ_NEVER = 0x00000000, +SQ_TT_RT_FREQ_1024_CLK = 0x00000001, +SQ_TT_RT_FREQ_4096_CLK = 0x00000002, +} SQ_TT_RT_FREQ; + +/* + * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum + */ + +typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE { +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 0x00000001, +SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 0x00000002, +} SQ_TT_TOKEN_MASK_INST_EXCLUDE; + +/* + * SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT enum + */ + +typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT { +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0x00000000, +SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 0x00000001, +} SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT; + +/* + * SQ_TT_TOKEN_MASK_REG_EXCLUDE enum + */ + +typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE { +SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 0x00000001, +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 0x00000002, +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 0x00000004, +} SQ_TT_TOKEN_MASK_REG_EXCLUDE; + +/* + * SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT enum + */ + +typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT { +SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0x00000000, +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 0x00000001, +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 0x00000002, +} SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT; + +/* + * SQ_TT_TOKEN_MASK_REG_INCLUDE enum + */ + +typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE { +SQ_TT_TOKEN_MASK_SQDEC_BIT = 0x00000001, +SQ_TT_TOKEN_MASK_SHDEC_BIT = 0x00000002, +SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 0x00000004, +SQ_TT_TOKEN_MASK_COMP_BIT = 0x00000008, +SQ_TT_TOKEN_MASK_CONTEXT_BIT = 0x00000010, +SQ_TT_TOKEN_MASK_CONFIG_BIT = 0x00000020, +SQ_TT_TOKEN_MASK_ALL_BIT = 0x00000040, +SQ_TT_TOKEN_MASK_RSVD_BIT = 0x00000080, +} SQ_TT_TOKEN_MASK_REG_INCLUDE; + +/* + * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum + */ + +typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT { +SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0x00000000, +SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 0x00000001, +SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 0x00000002, +SQ_TT_TOKEN_MASK_COMP_SHIFT = 0x00000003, +SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 0x00000004, +SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 0x00000005, +SQ_TT_TOKEN_MASK_ALL_SHIFT = 0x00000006, +SQ_TT_TOKEN_MASK_RSVD_SHIFT = 0x00000007, +} SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT; + +/* + * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum + */ + +typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT { +SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0x00000000, +SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 0x00000001, +SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 0x00000002, +SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 0x00000003, +SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 0x00000004, +SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 0x00000005, +SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 0x00000006, +SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 0x00000007, +SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 0x00000008, +SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 0x00000009, +SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 0x0000000a, +SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 0x0000000b, +} SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT; + +/* + * SQ_TT_UTIL_TIMER enum + */ + +typedef enum SQ_TT_UTIL_TIMER { +SQ_TT_UTIL_TIMER_100_CLK = 0x00000000, +SQ_TT_UTIL_TIMER_250_CLK = 0x00000001, +} SQ_TT_UTIL_TIMER; + +/* + * SQ_TT_WAVESTART_MODE enum + */ + +typedef enum SQ_TT_WAVESTART_MODE { +SQ_TT_WAVESTART_MODE_SHORT = 0x00000000, +SQ_TT_WAVESTART_MODE_ALLOC = 0x00000001, +SQ_TT_WAVESTART_MODE_PBB_ID = 0x00000002, +} SQ_TT_WAVESTART_MODE; + +/* + * SQ_TT_WTYPE_INCLUDE enum + */ + +typedef enum SQ_TT_WTYPE_INCLUDE { +SQ_TT_WTYPE_INCLUDE_PS_BIT = 0x00000001, +SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 0x00000002, +SQ_TT_WTYPE_INCLUDE_GS_BIT = 0x00000004, +SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 0x00000008, +SQ_TT_WTYPE_INCLUDE_HS_BIT = 0x00000010, +SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 0x00000020, +SQ_TT_WTYPE_INCLUDE_CS_BIT = 0x00000040, +} SQ_TT_WTYPE_INCLUDE; + +/* + * SQ_TT_WTYPE_INCLUDE_SHIFT enum + */ + +typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT { +SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0x00000000, +SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 0x00000001, +SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 0x00000002, +SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 0x00000003, +SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 0x00000004, +SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 0x00000005, +SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 0x00000006, +} SQ_TT_WTYPE_INCLUDE_SHIFT; + +/* + * SQ_WATCH_MODES enum + */ + +typedef enum SQ_WATCH_MODES { +SQ_WATCH_MODE_READ = 0x00000000, +SQ_WATCH_MODE_NONREAD = 0x00000001, +SQ_WATCH_MODE_ATOMIC = 0x00000002, +SQ_WATCH_MODE_ALL = 0x00000003, +} SQ_WATCH_MODES; + +/* + * SQ_WAVE_FWD_PROG_INTERVAL enum + */ + +typedef enum SQ_WAVE_FWD_PROG_INTERVAL { +SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0x00000000, +SQ_WAVE_FWD_PROG_INTERVAL_256 = 0x00000001, +SQ_WAVE_FWD_PROG_INTERVAL_1024 = 0x00000002, +SQ_WAVE_FWD_PROG_INTERVAL_4096 = 0x00000003, +} SQ_WAVE_FWD_PROG_INTERVAL; + +/* + * SQ_WAVE_IB_ECC_ST enum + */ + +typedef enum SQ_WAVE_IB_ECC_ST { +SQ_WAVE_IB_ECC_CLEAN = 0x00000000, +SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, +SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, +} SQ_WAVE_IB_ECC_ST; + +/* + * SQ_WAVE_SCHED_MODES enum + */ + +typedef enum SQ_WAVE_SCHED_MODES { +SQ_WAVE_SCHED_MODE_NORMAL = 0x00000000, +SQ_WAVE_SCHED_MODE_EXPERT = 0x00000001, +SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 0x00000002, +} SQ_WAVE_SCHED_MODES; + +/* + * SQ_WAVE_TYPE enum + */ + +typedef enum SQ_WAVE_TYPE { +SQ_WAVE_TYPE_PS = 0x00000000, +SQ_WAVE_TYPE_RSVD0 = 0x00000001, +SQ_WAVE_TYPE_GS = 0x00000002, +SQ_WAVE_TYPE_RSVD1 = 0x00000003, +SQ_WAVE_TYPE_HS = 0x00000004, +SQ_WAVE_TYPE_RSVD2 = 0x00000005, +SQ_WAVE_TYPE_CS = 0x00000006, +SQ_WAVE_TYPE_PS1 = 0x00000007, +SQ_WAVE_TYPE_PS2 = 0x00000008, +SQ_WAVE_TYPE_PS3 = 0x00000009, +} SQ_WAVE_TYPE; + +/* + * SQ_WAVE_TYPE value + */ + +#define SQ_WAVE_TYPE_PS0 0x00000000 + +/* + * SQIND_PARTITIONS value + */ + +#define SQIND_GLOBAL_REGS_OFFSET 0x00000000 +#define SQIND_GLOBAL_REGS_SIZE 0x00000008 +#define SQIND_LOCAL_REGS_OFFSET 0x00000008 +#define SQIND_LOCAL_REGS_SIZE 0x00000008 +#define SQIND_WAVE_HWREGS_OFFSET 0x00000100 +#define SQIND_WAVE_HWREGS_SIZE 0x00000100 +#define SQIND_WAVE_SGPRS_OFFSET 0x00000200 +#define SQIND_WAVE_SGPRS_SIZE 0x00000200 +#define SQIND_WAVE_VGPRS_OFFSET 0x00000400 +#define SQIND_WAVE_VGPRS_SIZE 0x00000400 + +/* + * SQ_GFXDEC value + */ + +#define SQ_GFXDEC_BEGIN 0x0000a000 +#define SQ_GFXDEC_END 0x0000c000 +#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a + +/* + * SQDEC value + */ + +#define SQDEC_BEGIN 0x00002300 +#define SQDEC_END 0x000023ff + +/* + * SQPERFSDEC value + */ + +#define SQPERFSDEC_BEGIN 0x0000d9c0 +#define SQPERFSDEC_END 0x0000da40 + +/* + * SQPERFDDEC value + */ + +#define SQPERFDDEC_BEGIN 0x0000d1c0 +#define SQPERFDDEC_END 0x0000d240 + +/* + * SQGFXUDEC value + */ + +#define SQGFXUDEC_BEGIN 0x0000c330 +#define SQGFXUDEC_END 0x0000c380 + +/* + * SQPWRDEC value + */ + +#define SQPWRDEC_BEGIN 0x0000f08c +#define SQPWRDEC_END 0x0000f094 + +/* + * SQ_DISPATCHER value + */ + +#define SQ_DISPATCHER_GFX_MIN 0x00000010 +#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 + +/* + * SQ_MAX value + */ + +#define SQ_MAX_PGM_SGPRS 0x00000068 +#define SQ_MAX_PGM_VGPRS 0x00000100 + +/* + * SQ_EXCP_BITS value + */ + +#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000 +#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007 +#define SQ_EX_MODE_EXCP_INVALID 0x00000000 +#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001 +#define SQ_EX_MODE_EXCP_DIV0 0x00000002 +#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003 +#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004 +#define SQ_EX_MODE_EXCP_INEXACT 0x00000005 +#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006 +#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007 +#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008 + +/* + * SQ_EXCP_HI_BITS value + */ + +#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000 +#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001 +#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002 + +/* + * HW_INSERTED_INST_ID value + */ + +#define INST_ID_PRIV_START 0x80000000 +#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 +#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 +#define INST_ID_HW_TRAP 0xfffffff2 +#define INST_ID_KILL_SEQ 0xfffffff3 +#define INST_ID_SPI_WREXEC 0xfffffff4 +#define INST_ID_HW_TRAP_GET_TBA 0xfffffff5 +#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe + +/* + * SIMM16_WAITCNT_PARTITIONS value + */ + +#define SIMM16_WAITCNT_EXP_CNT_START 0x00000000 +#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003 +#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000004 +#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000006 +#define SIMM16_WAITCNT_VM_CNT_START 0x0000000a +#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000006 +#define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000 +#define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001 +#define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001 +#define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001 +#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002 +#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003 +#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START 0x00000006 +#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE 0x00000001 +#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000007 +#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001 +#define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000008 +#define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003 +#define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000b +#define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000005 + +/* + * SIMM16_WAIT_EVENT_PARTITIONS value + */ + +#define SIMM16_WAIT_EVENT_EXP_RDY_START 0x00000000 +#define SIMM16_WAIT_EVENT_EXP_RDY_SIZE 0x00000001 + +/* + * SQ_WAVE_IB_DEP_COUNTER_SIZES value + */ + +#define SQ_WAVE_IB_DEP_SA_SDST_SIZE 0x00000004 +#define SQ_WAVE_IB_DEP_SA_EXEC_SIZE 0x00000002 +#define SQ_WAVE_IB_DEP_SA_M0_SIZE 0x00000001 +#define SQ_WAVE_IB_DEP_VM_VSRC_SIZE 0x00000004 +#define SQ_WAVE_IB_DEP_HOLD_CNT_SIZE 0x00000001 +#define SQ_WAVE_IB_DEP_VA_SSRC_SIZE 0x00000003 +#define SQ_WAVE_IB_DEP_VA_SDST_SIZE 0x00000004 +#define SQ_WAVE_IB_DEP_VA_VCC_SIZE 0x00000003 +#define SQ_WAVE_IB_DEP_VA_EXEC_SIZE 0x00000002 +#define SQ_WAVE_IB_DEP_VA_VDST_SIZE 0x00000005 +#define SQ_WAVE_IB_DEP_LDS_DIR_SIZE 0x00000003 + +/* + * SQ_EDC_FUE_CNTL_BITS value + */ + +#define SQ_EDC_FUE_CNTL_SIMD0 0x00000000 +#define SQ_EDC_FUE_CNTL_SIMD1 0x00000001 +#define SQ_EDC_FUE_CNTL_SIMD2 0x00000002 +#define SQ_EDC_FUE_CNTL_SIMD3 0x00000003 +#define SQ_EDC_FUE_CNTL_SQ 0x00000004 +#define SQ_EDC_FUE_CNTL_LDS 0x00000005 +#define SQ_EDC_FUE_CNTL_TD 0x00000006 +#define SQ_EDC_FUE_CNTL_TA 0x00000007 +#define SQ_EDC_FUE_CNTL_TCP 0x00000008 + +/******************************************************* + * COMP Enums + *******************************************************/ + +/* + * CSCNTL_TYPE enum + */ + +typedef enum CSCNTL_TYPE { +CSCNTL_TYPE_TG = 0x00000000, +CSCNTL_TYPE_STATE = 0x00000001, +CSCNTL_TYPE_EVENT = 0x00000002, +CSCNTL_TYPE_PRIVATE = 0x00000003, +} CSCNTL_TYPE; + +/* + * CSDATA_TYPE enum + */ + +typedef enum CSDATA_TYPE { +CSDATA_TYPE_TG = 0x00000000, +CSDATA_TYPE_STATE = 0x00000001, +CSDATA_TYPE_EVENT = 0x00000002, +CSDATA_TYPE_PRIVATE = 0x00000003, +} CSDATA_TYPE; + +/* + * CSDATA_TYPE_WIDTH value + */ + +#define CSDATA_TYPE_WIDTH 0x00000002 + +/* + * CSDATA_ADDR_WIDTH value + */ + +#define CSDATA_ADDR_WIDTH 0x00000007 + +/* + * CSDATA_DATA_WIDTH value + */ + +#define CSDATA_DATA_WIDTH 0x00000020 + +/* + * CSCNTL_TYPE_WIDTH value + */ + +#define CSCNTL_TYPE_WIDTH 0x00000002 + +/* + * CSCNTL_ADDR_WIDTH value + */ + +#define CSCNTL_ADDR_WIDTH 0x00000007 + +/* + * CSCNTL_DATA_WIDTH value + */ + +#define CSCNTL_DATA_WIDTH 0x00000020 + +/******************************************************* + * GE Enums + *******************************************************/ + +/* + * GE1_PERFCOUNT_SELECT enum + */ + +typedef enum GE1_PERFCOUNT_SELECT { +ge1_assembler_busy = 0x00000000, +ge1_assembler_stalled = 0x00000001, +ge1_dma_busy = 0x00000002, +ge1_dma_lat_bin_0 = 0x00000003, +ge1_dma_lat_bin_1 = 0x00000004, +ge1_dma_lat_bin_2 = 0x00000005, +ge1_dma_lat_bin_3 = 0x00000006, +ge1_dma_lat_bin_4 = 0x00000007, +ge1_dma_lat_bin_5 = 0x00000008, +ge1_dma_lat_bin_6 = 0x00000009, +ge1_dma_lat_bin_7 = 0x0000000a, +ge1_dma_return_cl0 = 0x0000000b, +ge1_dma_return_cl1 = 0x0000000c, +ge1_dma_utcl1_consecutive_retry_event = 0x0000000d, +ge1_dma_utcl1_request_event = 0x0000000e, +ge1_dma_utcl1_retry_event = 0x0000000f, +ge1_dma_utcl1_stall_event = 0x00000010, +ge1_dma_utcl1_stall_utcl2_event = 0x00000011, +ge1_dma_utcl1_translation_hit_event = 0x00000012, +ge1_dma_utcl1_translation_miss_event = 0x00000013, +ge1_assembler_dma_starved = 0x00000014, +ge1_rbiu_di_fifo_stalled_p0 = 0x00000015, +ge1_rbiu_di_fifo_starved_p0 = 0x00000016, +ge1_rbiu_dr_fifo_stalled_p0 = 0x00000017, +ge1_rbiu_dr_fifo_starved_p0 = 0x00000018, +ge1_sclk_reg_vld = 0x00000019, +ge1_stat_busy = 0x0000001a, +ge1_stat_no_dma_busy = 0x0000001b, +ge1_pipe0_to_pipe1 = 0x0000001c, +ge1_pipe1_to_pipe0 = 0x0000001d, +ge1_dma_return_size_cl0 = 0x0000001e, +ge1_dma_return_size_cl1 = 0x0000001f, +ge1_small_draws_one_instance = 0x00000020, +ge1_sclk_input_vld = 0x00000021, +ge1_prim_group_limit_hit = 0x00000022, +ge1_unopt_multi_instance_draws = 0x00000023, +ge1_rbiu_di_fifo_stalled_p1 = 0x00000024, +ge1_rbiu_di_fifo_starved_p1 = 0x00000025, +ge1_rbiu_dr_fifo_stalled_p1 = 0x00000026, +ge1_rbiu_dr_fifo_starved_p1 = 0x00000027, +} GE1_PERFCOUNT_SELECT; + +/* + * GE2_DIST_PERFCOUNT_SELECT enum + */ + +typedef enum GE2_DIST_PERFCOUNT_SELECT { +ge_dist_hs_done = 0x00000000, +ge_dist_hs_done_latency_se0 = 0x00000001, +ge_dist_hs_done_latency_se1 = 0x00000002, +ge_dist_hs_done_latency_se2 = 0x00000003, +ge_dist_hs_done_latency_se3 = 0x00000004, +ge_dist_hs_done_latency_se4 = 0x00000005, +ge_dist_hs_done_latency_se5 = 0x00000006, +ge_dist_hs_done_latency_se6 = 0x00000007, +ge_dist_hs_done_latency_se7 = 0x00000008, +ge_dist_inside_tf_bin_0 = 0x00000009, +ge_dist_inside_tf_bin_1 = 0x0000000a, +ge_dist_inside_tf_bin_2 = 0x0000000b, +ge_dist_inside_tf_bin_3 = 0x0000000c, +ge_dist_inside_tf_bin_4 = 0x0000000d, +ge_dist_inside_tf_bin_5 = 0x0000000e, +ge_dist_inside_tf_bin_6 = 0x0000000f, +ge_dist_inside_tf_bin_7 = 0x00000010, +ge_dist_inside_tf_bin_8 = 0x00000011, +ge_dist_null_patch = 0x00000012, +ge_dist_sclk_core_vld = 0x00000013, +ge_dist_sclk_wd_te11_vld = 0x00000014, +ge_dist_tfreq_lat_bin_0 = 0x00000015, +ge_dist_tfreq_lat_bin_1 = 0x00000016, +ge_dist_tfreq_lat_bin_2 = 0x00000017, +ge_dist_tfreq_lat_bin_3 = 0x00000018, +ge_dist_tfreq_lat_bin_4 = 0x00000019, +ge_dist_tfreq_lat_bin_5 = 0x0000001a, +ge_dist_tfreq_lat_bin_6 = 0x0000001b, +ge_dist_tfreq_lat_bin_7 = 0x0000001c, +ge_dist_tfreq_utcl1_consecutive_retry_event = 0x0000001d, +ge_dist_tfreq_utcl1_request_event = 0x0000001e, +ge_dist_tfreq_utcl1_retry_event = 0x0000001f, +ge_dist_tfreq_utcl1_stall_event = 0x00000020, +ge_dist_tfreq_utcl1_stall_utcl2_event = 0x00000021, +ge_dist_tfreq_utcl1_translation_hit_event = 0x00000022, +ge_dist_tfreq_utcl1_translation_miss_event = 0x00000023, +ge_dist_vs_pc_stall = 0x00000024, +ge_dist_pc_feorder_fifo_full = 0x00000025, +ge_dist_pc_ge_manager_busy = 0x00000026, +ge_dist_pc_req_stall_se0 = 0x00000027, +ge_dist_pc_req_stall_se1 = 0x00000028, +ge_dist_pc_req_stall_se2 = 0x00000029, +ge_dist_pc_req_stall_se3 = 0x0000002a, +ge_dist_pc_req_stall_se4 = 0x0000002b, +ge_dist_pc_req_stall_se5 = 0x0000002c, +ge_dist_pc_req_stall_se6 = 0x0000002d, +ge_dist_pc_req_stall_se7 = 0x0000002e, +ge_dist_pc_space_zero = 0x0000002f, +ge_dist_sclk_input_vld = 0x00000030, +ge_dist_reserved = 0x00000031, +ge_dist_wd_te11_busy = 0x00000032, +ge_dist_te11_starved = 0x00000033, +ge_dist_switch_mode_stall = 0x00000034, +ge_all_tf_eq = 0x00000035, +ge_all_tf2 = 0x00000036, +ge_all_tf3 = 0x00000037, +ge_all_tf4 = 0x00000038, +ge_all_tf5 = 0x00000039, +ge_all_tf6 = 0x0000003a, +ge_se0_te11_starved_on_hs_done = 0x0000003b, +ge_se1_te11_starved_on_hs_done = 0x0000003c, +ge_se2_te11_starved_on_hs_done = 0x0000003d, +ge_se3_te11_starved_on_hs_done = 0x0000003e, +ge_se4_te11_starved_on_hs_done = 0x0000003f, +ge_se5_te11_starved_on_hs_done = 0x00000040, +ge_se6_te11_starved_on_hs_done = 0x00000041, +ge_se7_te11_starved_on_hs_done = 0x00000042, +ge_dist_op_fifo_full_starve = 0x00000043, +ge_dist_hs_done_se0 = 0x00000044, +ge_dist_hs_done_se1 = 0x00000045, +ge_dist_hs_done_se2 = 0x00000046, +ge_dist_hs_done_se3 = 0x00000047, +ge_dist_hs_done_se4 = 0x00000048, +ge_dist_hs_done_se5 = 0x00000049, +ge_dist_hs_done_se6 = 0x0000004a, +ge_dist_hs_done_se7 = 0x0000004b, +ge_dist_hs_done_latency = 0x0000004c, +ge_dist_distributer_busy = 0x0000004d, +ge_tf_ret_data_stalling_hs_done = 0x0000004e, +ge_num_of_no_dist_patches = 0x0000004f, +ge_num_of_donut_dist_patches = 0x00000050, +ge_num_of_patch_dist_patches = 0x00000051, +ge_num_of_se_switches_due_to_patch_accum = 0x00000052, +ge_num_of_se_switches_due_to_donut = 0x00000053, +ge_num_of_se_switches_due_to_trap = 0x00000054, +ge_num_of_hs_alloc_events = 0x00000055, +ge_agm_gcr_req = 0x00000056, +ge_agm_gcr_tag_stall = 0x00000057, +ge_agm_gcr_crd_stall = 0x00000058, +ge_agm_gcr_stall = 0x00000059, +ge_agm_gcr_latency = 0x0000005a, +ge_distclk_vld = 0x0000005b, +} GE2_DIST_PERFCOUNT_SELECT; + +/* + * GE2_SE_PERFCOUNT_SELECT enum + */ + +typedef enum GE2_SE_PERFCOUNT_SELECT { +ge_se_ds_prims = 0x00000000, +ge_se_es_thread_groups = 0x00000001, +ge_se_esvert_stalled_gsprim = 0x00000002, +ge_se_hs_tfm_stall = 0x00000003, +ge_se_hs_tgs_active_high_water_mark = 0x00000004, +ge_se_hs_thread_groups = 0x00000005, +ge_se_reused_es_indices = 0x00000006, +ge_se_sclk_ngg_vld = 0x00000007, +ge_se_sclk_te11_vld = 0x00000008, +ge_se_spi_esvert_eov = 0x00000009, +ge_se_spi_esvert_stalled = 0x0000000a, +ge_se_spi_esvert_starved_busy = 0x0000000b, +ge_se_spi_esvert_valid = 0x0000000c, +ge_se_spi_gsprim_cont = 0x0000000d, +ge_se_spi_gsprim_eov = 0x0000000e, +ge_se_spi_gsprim_stalled = 0x0000000f, +ge_se_spi_gsprim_starved_busy = 0x00000010, +ge_se_spi_gsprim_valid = 0x00000011, +ge_se_spi_gssubgrp_is_event = 0x00000012, +ge_se_spi_gssubgrp_send = 0x00000013, +ge_se_spi_hsvert_eov = 0x00000014, +ge_se_spi_hsvert_stalled = 0x00000015, +ge_se_spi_hsvert_starved_busy = 0x00000016, +ge_se_spi_hsvert_valid = 0x00000017, +ge_se_spi_hswave_is_event = 0x00000018, +ge_se_spi_hswave_send = 0x00000019, +ge_se_spi_lsvert_eov = 0x0000001a, +ge_se_spi_lsvert_stalled = 0x0000001b, +ge_se_spi_lsvert_starved_busy = 0x0000001c, +ge_se_spi_lsvert_valid = 0x0000001d, +ge_se_spi_hsvert_fifo_full_stall = 0x0000001e, +ge_se_spi_tgrp_fifo_stall = 0x0000001f, +ge_spi_hsgrp_spi_stall = 0x00000020, +ge_se_spi_gssubgrp_event_window_active = 0x00000021, +ge_se_hs_input_stall = 0x00000022, +ge_se_sending_vert_or_prim = 0x00000023, +ge_se_sclk_input_vld = 0x00000024, +ge_spi_lswave_fifo_full_stall = 0x00000025, +ge_spi_hswave_fifo_full_stall = 0x00000026, +ge_hs_tif_stall = 0x00000027, +ge_csb_spi_bp = 0x00000028, +ge_ngg_starving_for_pc_grant = 0x00000029, +ge_pa0_csb_eop = 0x0000002a, +ge_pa1_csb_eop = 0x0000002b, +ge_ngg_starved_idle = 0x0000002c, +ge_gsprim_send = 0x0000002d, +ge_esvert_send = 0x0000002e, +ge_ngg_starved_after_work = 0x0000002f, +ge_ngg_subgrp_fifo_stall = 0x00000030, +ge_ngg_ord_id_req_stall = 0x00000031, +ge_ngg_indx_bus_stall = 0x00000032, +ge_hs_stall_tfmm_fifo_full = 0x00000033, +ge_gs_issue_rtr_stalled = 0x00000034, +ge_gsprim_stalled_esvert = 0x00000035, +ge_gsthread_stalled = 0x00000036, +ge_te11_stall_prim_funnel = 0x00000037, +ge_te11_stall_vert_funnel = 0x00000038, +ge_ngg_attr_grp_alloc = 0x00000039, +ge_ngg_attr_discard_alloc = 0x0000003a, +ge_ngg_pc_space_not_avail = 0x0000003b, +ge_ngg_agm_req_stall = 0x0000003c, +ge_ngg_spi_esvert_partial_eov = 0x0000003d, +ge_ngg_spi_gsprim_partial_eov = 0x0000003e, +ge_spi_gsgrp_valid = 0x0000003f, +ge_ngg_attr_grp_latency = 0x00000040, +ge_ngg_reuse_prim_limit_hit = 0x00000041, +ge_ngg_reuse_vert_limit_hit = 0x00000042, +ge_te11_con_stall = 0x00000043, +ge_te11_compactor_starved = 0x00000044, +ge_ngg_stall_tess_off_tess_on = 0x00000045, +ge_ngg_stall_tess_on_tess_off = 0x00000046, +} GE2_SE_PERFCOUNT_SELECT; + +/* + * VGT_DETECT_ONE enum + */ + +typedef enum VGT_DETECT_ONE { +ENABLE_TF1_OPT = 0x00000000, +DISABLE_TF1_OPT = 0x00000001, +} VGT_DETECT_ONE; + +/* + * VGT_DETECT_ZERO enum + */ + +typedef enum VGT_DETECT_ZERO { +ENABLE_TF0_OPT = 0x00000000, +DISABLE_TF0_OPT = 0x00000001, +} VGT_DETECT_ZERO; + +/* + * VGT_DIST_MODE enum + */ + +typedef enum VGT_DIST_MODE { +NO_DIST = 0x00000000, +PATCHES = 0x00000001, +DONUTS = 0x00000002, +TRAPEZOIDS = 0x00000003, +} VGT_DIST_MODE; + +/* + * VGT_DI_INDEX_SIZE enum + */ + +typedef enum VGT_DI_INDEX_SIZE { +DI_INDEX_SIZE_16_BIT = 0x00000000, +DI_INDEX_SIZE_32_BIT = 0x00000001, +DI_INDEX_SIZE_8_BIT = 0x00000002, +} VGT_DI_INDEX_SIZE; + +/* + * VGT_DI_MAJOR_MODE_SELECT enum + */ + +typedef enum VGT_DI_MAJOR_MODE_SELECT { +DI_MAJOR_MODE_0 = 0x00000000, +DI_MAJOR_MODE_1 = 0x00000001, +} VGT_DI_MAJOR_MODE_SELECT; + +/* + * VGT_DI_PRIM_TYPE enum + */ + +typedef enum VGT_DI_PRIM_TYPE { +DI_PT_NONE = 0x00000000, +DI_PT_POINTLIST = 0x00000001, +DI_PT_LINELIST = 0x00000002, +DI_PT_LINESTRIP = 0x00000003, +DI_PT_TRILIST = 0x00000004, +DI_PT_TRIFAN = 0x00000005, +DI_PT_TRISTRIP = 0x00000006, +DI_PT_2D_RECTANGLE = 0x00000007, +DI_PT_UNUSED_1 = 0x00000008, +DI_PT_PATCH = 0x00000009, +DI_PT_LINELIST_ADJ = 0x0000000a, +DI_PT_LINESTRIP_ADJ = 0x0000000b, +DI_PT_TRILIST_ADJ = 0x0000000c, +DI_PT_TRISTRIP_ADJ = 0x0000000d, +DI_PT_UNUSED_3 = 0x0000000e, +DI_PT_UNUSED_4 = 0x0000000f, +DI_PT_UNUSED_5 = 0x00000010, +DI_PT_RECTLIST = 0x00000011, +DI_PT_LINELOOP = 0x00000012, +DI_PT_QUADLIST = 0x00000013, +DI_PT_QUADSTRIP = 0x00000014, +DI_PT_POLYGON = 0x00000015, +} VGT_DI_PRIM_TYPE; + +/* + * VGT_DI_SOURCE_SELECT enum + */ + +typedef enum VGT_DI_SOURCE_SELECT { +DI_SRC_SEL_DMA = 0x00000000, +DI_SRC_SEL_IMMEDIATE = 0x00000001, +DI_SRC_SEL_AUTO_INDEX = 0x00000002, +DI_SRC_SEL_RESERVED = 0x00000003, +} VGT_DI_SOURCE_SELECT; + +/* + * VGT_DMA_BUF_TYPE enum + */ + +typedef enum VGT_DMA_BUF_TYPE { +VGT_DMA_BUF_MEM = 0x00000000, +VGT_DMA_BUF_RING = 0x00000001, +VGT_DMA_BUF_SETUP = 0x00000002, +VGT_DMA_PTR_UPDATE = 0x00000003, +} VGT_DMA_BUF_TYPE; + +/* + * VGT_DMA_SWAP_MODE enum + */ + +typedef enum VGT_DMA_SWAP_MODE { +VGT_DMA_SWAP_NONE = 0x00000000, +VGT_DMA_SWAP_16_BIT = 0x00000001, +VGT_DMA_SWAP_32_BIT = 0x00000002, +VGT_DMA_SWAP_WORD = 0x00000003, +} VGT_DMA_SWAP_MODE; + +/* + * VGT_EVENT_TYPE enum + */ + +typedef enum VGT_EVENT_TYPE { +Reserved_0x00 = 0x00000000, +SAMPLE_STREAMOUTSTATS1 = 0x00000001, +SAMPLE_STREAMOUTSTATS2 = 0x00000002, +SAMPLE_STREAMOUTSTATS3 = 0x00000003, +CACHE_FLUSH_TS = 0x00000004, +CONTEXT_DONE = 0x00000005, +CACHE_FLUSH = 0x00000006, +CS_PARTIAL_FLUSH = 0x00000007, +VGT_STREAMOUT_SYNC = 0x00000008, +Reserved_0x09 = 0x00000009, +VGT_STREAMOUT_RESET = 0x0000000a, +END_OF_PIPE_INCR_DE = 0x0000000b, +END_OF_PIPE_IB_END = 0x0000000c, +RST_PIX_CNT = 0x0000000d, +BREAK_BATCH = 0x0000000e, +VS_PARTIAL_FLUSH = 0x0000000f, +PS_PARTIAL_FLUSH = 0x00000010, +FLUSH_HS_OUTPUT = 0x00000011, +FLUSH_DFSM = 0x00000012, +RESET_TO_LOWEST_VGT = 0x00000013, +CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, +WAIT_SYNC = 0x00000015, +CACHE_FLUSH_AND_INV_EVENT = 0x00000016, +PERFCOUNTER_START = 0x00000017, +PERFCOUNTER_STOP = 0x00000018, +PIPELINESTAT_START = 0x00000019, +PIPELINESTAT_STOP = 0x0000001a, +PERFCOUNTER_SAMPLE = 0x0000001b, +FLUSH_ES_OUTPUT = 0x0000001c, +BIN_CONF_OVERRIDE_CHECK = 0x0000001d, +SAMPLE_PIPELINESTAT = 0x0000001e, +SO_VGTSTREAMOUT_FLUSH = 0x0000001f, +SAMPLE_STREAMOUTSTATS = 0x00000020, +RESET_VTX_CNT = 0x00000021, +BLOCK_CONTEXT_DONE = 0x00000022, +CS_CONTEXT_DONE = 0x00000023, +VGT_FLUSH = 0x00000024, +TGID_ROLLOVER = 0x00000025, +SQ_NON_EVENT = 0x00000026, +SC_SEND_DB_VPZ = 0x00000027, +BOTTOM_OF_PIPE_TS = 0x00000028, +FLUSH_SX_TS = 0x00000029, +DB_CACHE_FLUSH_AND_INV = 0x0000002a, +FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, +FLUSH_AND_INV_DB_META = 0x0000002c, +FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, +FLUSH_AND_INV_CB_META = 0x0000002e, +CS_DONE = 0x0000002f, +PS_DONE = 0x00000030, +FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, +SX_CB_RAT_ACK_REQUEST = 0x00000032, +THREAD_TRACE_START = 0x00000033, +THREAD_TRACE_STOP = 0x00000034, +THREAD_TRACE_MARKER = 0x00000035, +THREAD_TRACE_DRAW = 0x00000036, +THREAD_TRACE_FINISH = 0x00000037, +PIXEL_PIPE_STAT_CONTROL = 0x00000038, +PIXEL_PIPE_STAT_DUMP = 0x00000039, +PIXEL_PIPE_STAT_RESET = 0x0000003a, +CONTEXT_SUSPEND = 0x0000003b, +OFFCHIP_HS_DEALLOC = 0x0000003c, +ENABLE_NGG_PIPELINE = 0x0000003d, +ENABLE_LEGACY_PIPELINE = 0x0000003e, +DRAW_DONE = 0x0000003f, +} VGT_EVENT_TYPE; + +/* + * VGT_GROUP_CONV_SEL enum + */ + +typedef enum VGT_GROUP_CONV_SEL { +VGT_GRP_INDEX_16 = 0x00000000, +VGT_GRP_INDEX_32 = 0x00000001, +VGT_GRP_UINT_16 = 0x00000002, +VGT_GRP_UINT_32 = 0x00000003, +VGT_GRP_SINT_16 = 0x00000004, +VGT_GRP_SINT_32 = 0x00000005, +VGT_GRP_FLOAT_32 = 0x00000006, +VGT_GRP_AUTO_PRIM = 0x00000007, +VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, +} VGT_GROUP_CONV_SEL; + +/* + * VGT_GS_MODE_TYPE enum + */ + +typedef enum VGT_GS_MODE_TYPE { +GS_OFF = 0x00000000, +GS_SCENARIO_A = 0x00000001, +GS_SCENARIO_B = 0x00000002, +GS_SCENARIO_G = 0x00000003, +GS_SCENARIO_C = 0x00000004, +SPRITE_EN = 0x00000005, +} VGT_GS_MODE_TYPE; + +/* + * VGT_GS_OUTPRIM_TYPE enum + */ + +typedef enum VGT_GS_OUTPRIM_TYPE { +POINTLIST = 0x00000000, +LINESTRIP = 0x00000001, +TRISTRIP = 0x00000002, +RECT_2D = 0x00000003, +RECTLIST = 0x00000004, +} VGT_GS_OUTPRIM_TYPE; + +/* + * VGT_INDEX_TYPE_MODE enum + */ + +typedef enum VGT_INDEX_TYPE_MODE { +VGT_INDEX_16 = 0x00000000, +VGT_INDEX_32 = 0x00000001, +VGT_INDEX_8 = 0x00000002, +} VGT_INDEX_TYPE_MODE; + +/* + * VGT_OUTPATH_SELECT enum + */ + +typedef enum VGT_OUTPATH_SELECT { +VGT_OUTPATH_VTX_REUSE = 0x00000000, +VGT_OUTPATH_GS_BLOCK = 0x00000001, +VGT_OUTPATH_HS_BLOCK = 0x00000002, +VGT_OUTPATH_PRIM_GEN = 0x00000003, +VGT_OUTPATH_TE_PRIM_GEN = 0x00000004, +VGT_OUTPATH_TE_GS_BLOCK = 0x00000005, +VGT_OUTPATH_TE_OUTPUT = 0x00000006, +} VGT_OUTPATH_SELECT; + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +typedef enum VGT_OUT_PRIM_TYPE { +VGT_OUT_POINT = 0x00000000, +VGT_OUT_LINE = 0x00000001, +VGT_OUT_TRI = 0x00000002, +VGT_OUT_RECT_V0 = 0x00000003, +VGT_OUT_RECT_V1 = 0x00000004, +VGT_OUT_RECT_V2 = 0x00000005, +VGT_OUT_RECT_V3 = 0x00000006, +VGT_OUT_2D_RECT = 0x00000007, +VGT_TE_QUAD = 0x00000008, +VGT_TE_PRIM_INDEX_LINE = 0x00000009, +VGT_TE_PRIM_INDEX_TRI = 0x0000000a, +VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, +VGT_OUT_LINE_ADJ = 0x0000000c, +VGT_OUT_TRI_ADJ = 0x0000000d, +VGT_OUT_PATCH = 0x0000000e, +} VGT_OUT_PRIM_TYPE; + +/* + * VGT_RDREQ_POLICY enum + */ + +typedef enum VGT_RDREQ_POLICY { +VGT_POLICY_LRU = 0x00000000, +VGT_POLICY_STREAM = 0x00000001, +VGT_POLICY_BYPASS = 0x00000002, +} VGT_RDREQ_POLICY; + +/* + * VGT_STAGES_ES_EN enum + */ + +typedef enum VGT_STAGES_ES_EN { +ES_STAGE_OFF = 0x00000000, +ES_STAGE_DS = 0x00000001, +ES_STAGE_REAL = 0x00000002, +RESERVED_ES = 0x00000003, +} VGT_STAGES_ES_EN; + +/* + * VGT_STAGES_GS_EN enum + */ + +typedef enum VGT_STAGES_GS_EN { +GS_STAGE_OFF = 0x00000000, +GS_STAGE_ON = 0x00000001, +} VGT_STAGES_GS_EN; + +/* + * VGT_STAGES_HS_EN enum + */ + +typedef enum VGT_STAGES_HS_EN { +HS_STAGE_OFF = 0x00000000, +HS_STAGE_ON = 0x00000001, +} VGT_STAGES_HS_EN; + +/* + * VGT_STAGES_LS_EN enum + */ + +typedef enum VGT_STAGES_LS_EN { +LS_STAGE_OFF = 0x00000000, +LS_STAGE_ON = 0x00000001, +CS_STAGE_ON = 0x00000002, +RESERVED_LS = 0x00000003, +} VGT_STAGES_LS_EN; + +/* + * VGT_STAGES_VS_EN enum + */ + +typedef enum VGT_STAGES_VS_EN { +VS_STAGE_REAL = 0x00000000, +VS_STAGE_DS = 0x00000001, +VS_STAGE_COPY_SHADER = 0x00000002, +RESERVED_VS = 0x00000003, +} VGT_STAGES_VS_EN; + +/* + * VGT_TESS_PARTITION enum + */ + +typedef enum VGT_TESS_PARTITION { +PART_INTEGER = 0x00000000, +PART_POW2 = 0x00000001, +PART_FRAC_ODD = 0x00000002, +PART_FRAC_EVEN = 0x00000003, +} VGT_TESS_PARTITION; + +/* + * VGT_TESS_TOPOLOGY enum + */ + +typedef enum VGT_TESS_TOPOLOGY { +OUTPUT_POINT = 0x00000000, +OUTPUT_LINE = 0x00000001, +OUTPUT_TRIANGLE_CW = 0x00000002, +OUTPUT_TRIANGLE_CCW = 0x00000003, +} VGT_TESS_TOPOLOGY; + +/* + * VGT_TESS_TYPE enum + */ + +typedef enum VGT_TESS_TYPE { +TESS_ISOLINE = 0x00000000, +TESS_TRIANGLE = 0x00000001, +TESS_QUAD = 0x00000002, +} VGT_TESS_TYPE; + +/* + * WD_IA_DRAW_REG_XFER enum + */ + +typedef enum WD_IA_DRAW_REG_XFER { +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000, +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001, +WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002, +WD_IA_DRAW_REG_XFER_GE_CNTL = 0x00000003, +WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 0x00000004, +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 0x00000005, +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 0x00000006, +WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 0x00000007, +WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 0x00000008, +} WD_IA_DRAW_REG_XFER; + +/* + * WD_IA_DRAW_SOURCE enum + */ + +typedef enum WD_IA_DRAW_SOURCE { +WD_IA_DRAW_SOURCE_DMA = 0x00000000, +WD_IA_DRAW_SOURCE_IMMD = 0x00000001, +WD_IA_DRAW_SOURCE_AUTO = 0x00000002, +WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, +} WD_IA_DRAW_SOURCE; + +/* + * WD_IA_DRAW_TYPE enum + */ + +typedef enum WD_IA_DRAW_TYPE { +WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, +WD_IA_DRAW_TYPE_REG_XFER = 0x00000001, +WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, +WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, +WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, +WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, +WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, +WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, +} WD_IA_DRAW_TYPE; + +/* + * GS_THREADID_SIZE value + */ + +#define GSTHREADID_SIZE 0x00000002 + +/******************************************************* + * GB Enums + *******************************************************/ + +/* + * GB_EDC_DED_MODE enum + */ + +typedef enum GB_EDC_DED_MODE { +GB_EDC_DED_MODE_LOG = 0x00000000, +GB_EDC_DED_MODE_HALT = 0x00000001, +GB_EDC_DED_MODE_INT_HALT = 0x00000002, +} GB_EDC_DED_MODE; + +/* + * VALUE_GB_TILING_CONFIG_TABLE_SIZE value + */ + +#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020 + +/* + * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value + */ + +#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010 + +/******************************************************* + * GLX Enums + *******************************************************/ + +/* + * CHA_PERF_SEL enum + */ + +typedef enum CHA_PERF_SEL { +CHA_PERF_SEL_BUSY = 0x00000000, +CHA_PERF_SEL_STALL_CHC0 = 0x00000001, +CHA_PERF_SEL_STALL_CHC1 = 0x00000002, +CHA_PERF_SEL_STALL_CHC2 = 0x00000003, +CHA_PERF_SEL_STALL_CHC3 = 0x00000004, +CHA_PERF_SEL_STALL_CHC4 = 0x00000005, +CHA_PERF_SEL_STALL_CHC5 = 0x00000006, +CHA_PERF_SEL_REQUEST_CHC0 = 0x00000007, +CHA_PERF_SEL_REQUEST_CHC1 = 0x00000008, +CHA_PERF_SEL_REQUEST_CHC2 = 0x00000009, +CHA_PERF_SEL_REQUEST_CHC3 = 0x0000000a, +CHA_PERF_SEL_REQUEST_CHC4 = 0x0000000b, +CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 0x0000000c, +CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 0x0000000d, +CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 0x0000000e, +CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 0x0000000f, +CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 0x00000010, +CHA_PERF_SEL_IO_32B_WDS_CHC0 = 0x00000011, +CHA_PERF_SEL_IO_32B_WDS_CHC1 = 0x00000012, +CHA_PERF_SEL_IO_32B_WDS_CHC2 = 0x00000013, +CHA_PERF_SEL_IO_32B_WDS_CHC3 = 0x00000014, +CHA_PERF_SEL_IO_32B_WDS_CHC4 = 0x00000015, +CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 0x00000016, +CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 0x00000017, +CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 0x00000018, +CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 0x00000019, +CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 0x0000001a, +CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 0x0000001b, +CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 0x0000001c, +CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 0x0000001d, +CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 0x0000001e, +CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 0x0000001f, +CHA_PERF_SEL_ARB_REQUESTS = 0x00000020, +CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000021, +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 0x00000022, +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 0x00000023, +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 0x00000024, +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 0x00000025, +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 0x00000026, +CHA_PERF_SEL_CYCLE = 0x00000027, +} CHA_PERF_SEL; + +/* + * CHCG_PERF_SEL enum + */ + +typedef enum CHCG_PERF_SEL { +CHCG_PERF_SEL_CYCLE = 0x00000000, +CHCG_PERF_SEL_BUSY = 0x00000001, +CHCG_PERF_SEL_STARVE = 0x00000002, +CHCG_PERF_SEL_ARB_RET_LEVEL = 0x00000003, +CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004, +CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005, +CHCG_PERF_SEL_REQ = 0x00000006, +CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007, +CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008, +CHCG_PERF_SEL_REQ_NOP_ACK = 0x00000009, +CHCG_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a, +CHCG_PERF_SEL_REQ_READ = 0x0000000b, +CHCG_PERF_SEL_REQ_READ_128B = 0x0000000c, +CHCG_PERF_SEL_REQ_READ_32B = 0x0000000d, +CHCG_PERF_SEL_REQ_READ_64B = 0x0000000e, +CHCG_PERF_SEL_REQ_WRITE = 0x0000000f, +CHCG_PERF_SEL_REQ_WRITE_32B = 0x00000010, +CHCG_PERF_SEL_REQ_WRITE_64B = 0x00000011, +CHCG_PERF_SEL_STALL_GUS_GL1 = 0x00000012, +CHCG_PERF_SEL_STALL_BUFFER_FULL = 0x00000013, +CHCG_PERF_SEL_REQ_CLIENT0 = 0x00000014, +CHCG_PERF_SEL_REQ_CLIENT1 = 0x00000015, +CHCG_PERF_SEL_REQ_CLIENT2 = 0x00000016, +CHCG_PERF_SEL_REQ_CLIENT3 = 0x00000017, +CHCG_PERF_SEL_REQ_CLIENT4 = 0x00000018, +CHCG_PERF_SEL_REQ_CLIENT5 = 0x00000019, +CHCG_PERF_SEL_REQ_CLIENT6 = 0x0000001a, +CHCG_PERF_SEL_REQ_CLIENT7 = 0x0000001b, +CHCG_PERF_SEL_REQ_CLIENT8 = 0x0000001c, +CHCG_PERF_SEL_REQ_CLIENT9 = 0x0000001d, +CHCG_PERF_SEL_REQ_CLIENT10 = 0x0000001e, +CHCG_PERF_SEL_REQ_CLIENT11 = 0x0000001f, +CHCG_PERF_SEL_REQ_CLIENT12 = 0x00000020, +CHCG_PERF_SEL_REQ_CLIENT13 = 0x00000021, +CHCG_PERF_SEL_REQ_CLIENT14 = 0x00000022, +CHCG_PERF_SEL_REQ_CLIENT15 = 0x00000023, +CHCG_PERF_SEL_REQ_CLIENT16 = 0x00000024, +CHCG_PERF_SEL_REQ_CLIENT17 = 0x00000025, +CHCG_PERF_SEL_REQ_CLIENT18 = 0x00000026, +CHCG_PERF_SEL_REQ_CLIENT19 = 0x00000027, +CHCG_PERF_SEL_REQ_CLIENT20 = 0x00000028, +CHCG_PERF_SEL_REQ_CLIENT21 = 0x00000029, +CHCG_PERF_SEL_REQ_CLIENT22 = 0x0000002a, +CHCG_PERF_SEL_REQ_CLIENT23 = 0x0000002b, +} CHCG_PERF_SEL; + +/* + * CHC_PERF_SEL enum + */ + +typedef enum CHC_PERF_SEL { +CHC_PERF_SEL_CYCLE = 0x00000000, +CHC_PERF_SEL_BUSY = 0x00000001, +CHC_PERF_SEL_STARVE = 0x00000002, +CHC_PERF_SEL_ARB_RET_LEVEL = 0x00000003, +CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004, +CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005, +CHC_PERF_SEL_REQ = 0x00000006, +CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007, +CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008, +CHC_PERF_SEL_REQ_NOP_ACK = 0x00000009, +CHC_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a, +CHC_PERF_SEL_REQ_READ = 0x0000000b, +CHC_PERF_SEL_REQ_READ_128B = 0x0000000c, +CHC_PERF_SEL_REQ_READ_32B = 0x0000000d, +CHC_PERF_SEL_REQ_READ_64B = 0x0000000e, +CHC_PERF_SEL_REQ_WRITE = 0x0000000f, +CHC_PERF_SEL_REQ_WRITE_32B = 0x00000010, +CHC_PERF_SEL_REQ_WRITE_64B = 0x00000011, +CHC_PERF_SEL_STALL_GL2_GL1 = 0x00000012, +CHC_PERF_SEL_STALL_BUFFER_FULL = 0x00000013, +CHC_PERF_SEL_REQ_CLIENT0 = 0x00000014, +CHC_PERF_SEL_REQ_CLIENT1 = 0x00000015, +CHC_PERF_SEL_REQ_CLIENT2 = 0x00000016, +CHC_PERF_SEL_REQ_CLIENT3 = 0x00000017, +CHC_PERF_SEL_REQ_CLIENT4 = 0x00000018, +CHC_PERF_SEL_REQ_CLIENT5 = 0x00000019, +CHC_PERF_SEL_REQ_CLIENT6 = 0x0000001a, +CHC_PERF_SEL_REQ_CLIENT7 = 0x0000001b, +CHC_PERF_SEL_REQ_CLIENT8 = 0x0000001c, +CHC_PERF_SEL_REQ_CLIENT9 = 0x0000001d, +CHC_PERF_SEL_REQ_CLIENT10 = 0x0000001e, +CHC_PERF_SEL_REQ_CLIENT11 = 0x0000001f, +CHC_PERF_SEL_REQ_CLIENT12 = 0x00000020, +CHC_PERF_SEL_REQ_CLIENT13 = 0x00000021, +CHC_PERF_SEL_REQ_CLIENT14 = 0x00000022, +CHC_PERF_SEL_REQ_CLIENT15 = 0x00000023, +CHC_PERF_SEL_REQ_CLIENT16 = 0x00000024, +CHC_PERF_SEL_REQ_CLIENT17 = 0x00000025, +CHC_PERF_SEL_REQ_CLIENT18 = 0x00000026, +CHC_PERF_SEL_REQ_CLIENT19 = 0x00000027, +CHC_PERF_SEL_REQ_CLIENT20 = 0x00000028, +CHC_PERF_SEL_REQ_CLIENT21 = 0x00000029, +CHC_PERF_SEL_REQ_CLIENT22 = 0x0000002a, +CHC_PERF_SEL_REQ_CLIENT23 = 0x0000002b, +} CHC_PERF_SEL; + +/* + * GL1A_PERF_SEL enum + */ + +typedef enum GL1A_PERF_SEL { +GL1A_PERF_SEL_BUSY = 0x00000000, +GL1A_PERF_SEL_STALL_GL1C0 = 0x00000001, +GL1A_PERF_SEL_STALL_GL1C1 = 0x00000002, +GL1A_PERF_SEL_STALL_GL1C2 = 0x00000003, +GL1A_PERF_SEL_STALL_GL1C3 = 0x00000004, +GL1A_PERF_SEL_REQUEST_GL1C0 = 0x00000005, +GL1A_PERF_SEL_REQUEST_GL1C1 = 0x00000006, +GL1A_PERF_SEL_REQUEST_GL1C2 = 0x00000007, +GL1A_PERF_SEL_REQUEST_GL1C3 = 0x00000008, +GL1A_PERF_SEL_WDS_32B_GL1C0 = 0x00000009, +GL1A_PERF_SEL_WDS_32B_GL1C1 = 0x0000000a, +GL1A_PERF_SEL_WDS_32B_GL1C2 = 0x0000000b, +GL1A_PERF_SEL_WDS_32B_GL1C3 = 0x0000000c, +GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 0x0000000d, +GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 0x0000000e, +GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 0x0000000f, +GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 0x00000010, +GL1A_PERF_SEL_ARB_REQUESTS = 0x00000011, +GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000012, +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 0x00000013, +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 0x00000014, +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 0x00000015, +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 0x00000016, +GL1A_PERF_SEL_CYCLE = 0x00000017, +} GL1A_PERF_SEL; + +/* + * GL1C_PERF_SEL enum + */ + +typedef enum GL1C_PERF_SEL { +GL1C_PERF_SEL_CYCLE = 0x00000000, +GL1C_PERF_SEL_BUSY = 0x00000001, +GL1C_PERF_SEL_STARVE = 0x00000002, +GL1C_PERF_SEL_ARB_RET_LEVEL = 0x00000003, +GL1C_PERF_SEL_GL2_REQ_READ = 0x00000004, +GL1C_PERF_SEL_GL2_REQ_READ_128B = 0x00000005, +GL1C_PERF_SEL_GL2_REQ_READ_32B = 0x00000006, +GL1C_PERF_SEL_GL2_REQ_READ_64B = 0x00000007, +GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000008, +GL1C_PERF_SEL_GL2_REQ_WRITE = 0x00000009, +GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 0x0000000a, +GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 0x0000000b, +GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x0000000c, +GL1C_PERF_SEL_GL2_REQ_PREFETCH = 0x0000000d, +GL1C_PERF_SEL_REQ = 0x0000000e, +GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x0000000f, +GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000010, +GL1C_PERF_SEL_REQ_SHADER_INV = 0x00000011, +GL1C_PERF_SEL_REQ_MISS = 0x00000012, +GL1C_PERF_SEL_REQ_NOP_ACK = 0x00000013, +GL1C_PERF_SEL_REQ_NOP_RTN0 = 0x00000014, +GL1C_PERF_SEL_REQ_READ = 0x00000015, +GL1C_PERF_SEL_REQ_READ_128B = 0x00000016, +GL1C_PERF_SEL_REQ_READ_32B = 0x00000017, +GL1C_PERF_SEL_REQ_READ_64B = 0x00000018, +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 0x00000019, +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 0x0000001a, +GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 0x0000001b, +GL1C_PERF_SEL_REQ_WRITE = 0x0000001c, +GL1C_PERF_SEL_REQ_WRITE_32B = 0x0000001d, +GL1C_PERF_SEL_REQ_WRITE_64B = 0x0000001e, +GL1C_PERF_SEL_STALL_GL2_GL1 = 0x0000001f, +GL1C_PERF_SEL_STALL_LFIFO_FULL = 0x00000020, +GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 0x00000021, +GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 0x00000022, +GL1C_PERF_SEL_STALL_GCR_INV = 0x00000023, +GL1C_PERF_SEL_STALL_VM = 0x00000024, +GL1C_PERF_SEL_REQ_CLIENT0 = 0x00000025, +GL1C_PERF_SEL_REQ_CLIENT1 = 0x00000026, +GL1C_PERF_SEL_REQ_CLIENT2 = 0x00000027, +GL1C_PERF_SEL_REQ_CLIENT3 = 0x00000028, +GL1C_PERF_SEL_REQ_CLIENT4 = 0x00000029, +GL1C_PERF_SEL_REQ_CLIENT5 = 0x0000002a, +GL1C_PERF_SEL_REQ_CLIENT6 = 0x0000002b, +GL1C_PERF_SEL_REQ_CLIENT7 = 0x0000002c, +GL1C_PERF_SEL_REQ_CLIENT8 = 0x0000002d, +GL1C_PERF_SEL_REQ_CLIENT9 = 0x0000002e, +GL1C_PERF_SEL_REQ_CLIENT10 = 0x0000002f, +GL1C_PERF_SEL_REQ_CLIENT11 = 0x00000030, +GL1C_PERF_SEL_REQ_CLIENT12 = 0x00000031, +GL1C_PERF_SEL_REQ_CLIENT13 = 0x00000032, +GL1C_PERF_SEL_REQ_CLIENT14 = 0x00000033, +GL1C_PERF_SEL_REQ_CLIENT15 = 0x00000034, +GL1C_PERF_SEL_REQ_CLIENT16 = 0x00000035, +GL1C_PERF_SEL_REQ_CLIENT17 = 0x00000036, +GL1C_PERF_SEL_REQ_CLIENT18 = 0x00000037, +GL1C_PERF_SEL_REQ_CLIENT19 = 0x00000038, +GL1C_PERF_SEL_REQ_CLIENT20 = 0x00000039, +GL1C_PERF_SEL_REQ_CLIENT21 = 0x0000003a, +GL1C_PERF_SEL_REQ_CLIENT22 = 0x0000003b, +GL1C_PERF_SEL_REQ_CLIENT23 = 0x0000003c, +GL1C_PERF_SEL_REQ_CLIENT24 = 0x0000003d, +GL1C_PERF_SEL_REQ_CLIENT25 = 0x0000003e, +GL1C_PERF_SEL_REQ_CLIENT26 = 0x0000003f, +GL1C_PERF_SEL_REQ_CLIENT27 = 0x00000040, +GL1C_PERF_SEL_UTCL0_REQUEST = 0x00000041, +GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000042, +GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000043, +GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000044, +GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 0x00000045, +GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000046, +GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000047, +GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000048, +GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000049, +GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x0000004a, +GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x0000004b, +GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000004c, +GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 0x0000004d, +GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x0000004e, +GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 0x0000004f, +GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 0x00000050, +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000051, +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000052, +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000053, +} GL1C_PERF_SEL; + +/******************************************************* + * GL1H Enums + *******************************************************/ + +/* + * GL1H_REQ_PERF_SEL enum + */ + +typedef enum GL1H_REQ_PERF_SEL { +GL1H_REQ_PERF_SEL_BUSY = 0x00000000, +GL1H_REQ_PERF_SEL_STALL_GL1_0 = 0x00000001, +GL1H_REQ_PERF_SEL_STALL_GL1_1 = 0x00000002, +GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 0x00000003, +GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 0x00000004, +GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 0x00000005, +GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 0x00000006, +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 0x00000007, +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 0x00000008, +GL1H_REQ_PERF_SEL_ARB_REQUESTS = 0x00000009, +GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x0000000a, +GL1H_REQ_PERF_SEL_CYCLE = 0x0000000b, +} GL1H_REQ_PERF_SEL; + +/******************************************************* + * TA Enums + *******************************************************/ + +/* + * TA_PERFCOUNT_SEL enum + */ + +typedef enum TA_PERFCOUNT_SEL { +TA_PERF_SEL_NULL = 0x00000000, +TA_PERF_SEL_image_sampler_has_offset_instructions = 0x00000001, +TA_PERF_SEL_image_sampler_has_bias_instructions = 0x00000002, +TA_PERF_SEL_image_sampler_has_reference_instructions = 0x00000003, +TA_PERF_SEL_image_sampler_has_ds_instructions = 0x00000004, +TA_PERF_SEL_image_sampler_has_dt_instructions = 0x00000005, +TA_PERF_SEL_image_sampler_has_dr_instructions = 0x00000006, +TA_PERF_SEL_gradient_busy = 0x00000007, +TA_PERF_SEL_gradient_fifo_busy = 0x00000008, +TA_PERF_SEL_lod_busy = 0x00000009, +TA_PERF_SEL_lod_fifo_busy = 0x0000000a, +TA_PERF_SEL_addresser_busy = 0x0000000b, +TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, +TA_PERF_SEL_aligner_busy = 0x0000000d, +TA_PERF_SEL_write_path_busy = 0x0000000e, +TA_PERF_SEL_ta_busy = 0x0000000f, +TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 0x00000010, +TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 0x00000011, +TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 0x00000012, +TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 0x00000013, +TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 0x00000014, +TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 0x00000015, +TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 0x00000016, +TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 0x00000017, +TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 0x00000018, +TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 0x00000019, +TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 0x0000001a, +TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 0x0000001b, +TA_PERF_SEL_image_sampler_has_t_instructions = 0x0000001c, +TA_PERF_SEL_image_sampler_has_r_instructions = 0x0000001d, +TA_PERF_SEL_image_sampler_has_q_instructions = 0x0000001e, +TA_PERF_SEL_total_wavefronts = 0x00000020, +TA_PERF_SEL_gradient_cycles = 0x00000021, +TA_PERF_SEL_walker_cycles = 0x00000022, +TA_PERF_SEL_aligner_cycles = 0x00000023, +TA_PERF_SEL_image_wavefronts = 0x00000024, +TA_PERF_SEL_image_read_wavefronts = 0x00000025, +TA_PERF_SEL_image_store_wavefronts = 0x00000026, +TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, +TA_PERF_SEL_image_sampler_total_cycles = 0x00000028, +TA_PERF_SEL_image_nosampler_total_cycles = 0x00000029, +TA_PERF_SEL_flat_total_cycles = 0x0000002a, +TA_PERF_SEL_bvh_total_cycles = 0x0000002b, +TA_PERF_SEL_buffer_wavefronts = 0x0000002c, +TA_PERF_SEL_buffer_load_wavefronts = 0x0000002d, +TA_PERF_SEL_buffer_store_wavefronts = 0x0000002e, +TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, +TA_PERF_SEL_buffer_total_cycles = 0x00000031, +TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 0x00000032, +TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 0x00000033, +TA_PERF_SEL_buffer_has_index_instructions = 0x00000034, +TA_PERF_SEL_buffer_has_offset_instructions = 0x00000035, +TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, +TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, +TA_PERF_SEL_image_sampler_wavefronts = 0x00000038, +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, +TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, +TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, +TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, +TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f, +TA_PERF_SEL_color_1_cycle_quads = 0x00000040, +TA_PERF_SEL_color_2_cycle_quads = 0x00000041, +TA_PERF_SEL_color_3_cycle_quads = 0x00000042, +TA_PERF_SEL_mip_1_cycle_quads = 0x00000044, +TA_PERF_SEL_mip_2_cycle_quads = 0x00000045, +TA_PERF_SEL_vol_1_cycle_quads = 0x00000046, +TA_PERF_SEL_vol_2_cycle_quads = 0x00000047, +TA_PERF_SEL_sampler_op_quads = 0x00000048, +TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, +TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, +TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, +TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, +TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, +TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, +TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, +TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, +TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, +TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, +TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, +TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, +TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, +TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, +TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, +TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, +TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, +TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, +TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, +TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, +TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, +TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, +TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, +TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, +TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, +TA_PERF_SEL_store_write_data_input_cycles = 0x00000062, +TA_PERF_SEL_store_write_data_output_cycles = 0x00000063, +TA_PERF_SEL_flat_wavefronts = 0x00000064, +TA_PERF_SEL_flat_load_wavefronts = 0x00000065, +TA_PERF_SEL_flat_store_wavefronts = 0x00000066, +TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067, +TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 0x00000068, +TA_PERF_SEL_register_clk_valid_cycles = 0x00000069, +TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 0x0000006a, +TA_PERF_SEL_harvestable_clk_enabled_cycles = 0x0000006b, +TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 0x0000006c, +TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 0x0000006d, +TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 0x0000006e, +TA_PERF_SEL_store_2_write_data_vgpr_instructions = 0x00000072, +TA_PERF_SEL_store_3_write_data_vgpr_instructions = 0x00000073, +TA_PERF_SEL_store_4_write_data_vgpr_instructions = 0x00000074, +TA_PERF_SEL_store_has_x_instructions = 0x00000075, +TA_PERF_SEL_store_has_y_instructions = 0x00000076, +TA_PERF_SEL_store_has_z_instructions = 0x00000077, +TA_PERF_SEL_store_has_w_instructions = 0x00000078, +TA_PERF_SEL_image_nosampler_has_t_instructions = 0x00000079, +TA_PERF_SEL_image_nosampler_has_r_instructions = 0x0000007a, +TA_PERF_SEL_image_nosampler_has_q_instructions = 0x0000007b, +TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 0x0000007c, +TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 0x0000007d, +TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 0x0000007e, +TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 0x0000007f, +TA_PERF_SEL_in_busy = 0x00000080, +TA_PERF_SEL_in_fifos_busy = 0x00000081, +TA_PERF_SEL_in_cfifo_busy = 0x00000082, +TA_PERF_SEL_in_qfifo_busy = 0x00000083, +TA_PERF_SEL_in_wfifo_busy = 0x00000084, +TA_PERF_SEL_in_rfifo_busy = 0x00000085, +TA_PERF_SEL_bf_busy = 0x00000086, +TA_PERF_SEL_ns_busy = 0x00000087, +TA_PERF_SEL_smp_busy_ns_idle = 0x00000088, +TA_PERF_SEL_smp_idle_ns_busy = 0x00000089, +TA_PERF_SEL_vmemcmd_cycles = 0x00000090, +TA_PERF_SEL_vmemreq_cycles = 0x00000091, +TA_PERF_SEL_in_waiting_on_req_cycles = 0x00000092, +TA_PERF_SEL_in_addr_cycles = 0x00000096, +TA_PERF_SEL_in_data_cycles = 0x00000097, +TA_PERF_SEL_latency_ram_weights_written_cycles = 0x0000009a, +TA_PERF_SEL_latency_ram_ws_required_quads = 0x0000009b, +TA_PERF_SEL_latency_ram_whv_required_quads = 0x0000009c, +TA_PERF_SEL_latency_ram_ws_required_instructions = 0x0000009d, +TA_PERF_SEL_latency_ram_whv_required_instructions = 0x0000009e, +TA_PERF_SEL_latency_ram_ref_required_instructions = 0x0000009f, +TA_PERF_SEL_point_sampled_quads = 0x000000a0, +TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 0x000000a2, +TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 0x000000a3, +TA_PERF_SEL_atomic_write_data_input_cycles = 0x000000a4, +TA_PERF_SEL_atomic_write_data_output_cycles = 0x000000a5, +TA_PERF_SEL_num_unlit_nodes_ta_opt = 0x000000ad, +TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 0x000000ae, +TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 0x000000af, +TA_PERF_SEL_num_of_bvh_valid_first_tri = 0x000000b0, +TA_PERF_SEL_num_of_bvh_valid_second_tri = 0x000000b1, +TA_PERF_SEL_num_of_bvh_valid_third_tri = 0x000000b2, +TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 0x000000b3, +TA_PERF_SEL_num_of_bvh_valid_fp16_box = 0x000000b4, +TA_PERF_SEL_num_of_bvh_valid_fp32_box = 0x000000b5, +TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 0x000000b6, +TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 0x000000b7, +TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 0x000000b8, +TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 0x000000b9, +TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 0x000000ba, +TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 0x000000bb, +TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 0x000000bc, +TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 0x000000bd, +TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 0x000000be, +TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 0x000000bf, +TA_PERF_SEL_image_sampler_1_op_burst = 0x000000c0, +TA_PERF_SEL_image_sampler_2to3_op_burst = 0x000000c1, +TA_PERF_SEL_image_sampler_4to7_op_burst = 0x000000c2, +TA_PERF_SEL_image_sampler_ge8_op_burst = 0x000000c3, +TA_PERF_SEL_image_linked_1_op_burst = 0x000000c4, +TA_PERF_SEL_image_linked_2to3_op_burst = 0x000000c5, +TA_PERF_SEL_image_linked_4to7_op_burst = 0x000000c6, +TA_PERF_SEL_image_linked_ge8_op_burst = 0x000000c7, +TA_PERF_SEL_image_bvh_1_op_burst = 0x000000c8, +TA_PERF_SEL_image_bvh_2to3_op_burst = 0x000000c9, +TA_PERF_SEL_image_bvh_4to7_op_burst = 0x000000ca, +TA_PERF_SEL_image_bvh_ge8_op_burst = 0x000000cb, +TA_PERF_SEL_image_nosampler_1_op_burst = 0x000000cc, +TA_PERF_SEL_image_nosampler_2to3_op_burst = 0x000000cd, +TA_PERF_SEL_image_nosampler_4to31_op_burst = 0x000000ce, +TA_PERF_SEL_image_nosampler_ge32_op_burst = 0x000000cf, +TA_PERF_SEL_buffer_flat_1_op_burst = 0x000000d0, +TA_PERF_SEL_buffer_flat_2to3_op_burst = 0x000000d1, +TA_PERF_SEL_buffer_flat_4to31_op_burst = 0x000000d2, +TA_PERF_SEL_buffer_flat_ge32_op_burst = 0x000000d3, +TA_PERF_SEL_write_1_op_burst = 0x000000d4, +TA_PERF_SEL_write_2to3_op_burst = 0x000000d5, +TA_PERF_SEL_write_4to31_op_burst = 0x000000d6, +TA_PERF_SEL_write_ge32_op_burst = 0x000000d7, +TA_PERF_SEL_ibubble_1_cycle_burst = 0x000000d8, +TA_PERF_SEL_ibubble_2to3_cycle_burst = 0x000000d9, +TA_PERF_SEL_ibubble_4to15_cycle_burst = 0x000000da, +TA_PERF_SEL_ibubble_16to31_cycle_burst = 0x000000db, +TA_PERF_SEL_ibubble_32to63_cycle_burst = 0x000000dc, +TA_PERF_SEL_ibubble_ge64_cycle_burst = 0x000000dd, +TA_PERF_SEL_sampler_clk_valid_cycles = 0x000000e0, +TA_PERF_SEL_nonsampler_clk_valid_cycles = 0x000000e1, +TA_PERF_SEL_buffer_flat_clk_valid_cycles = 0x000000e2, +TA_PERF_SEL_write_data_clk_valid_cycles = 0x000000e3, +TA_PERF_SEL_gradient_clk_valid_cycles = 0x000000e4, +TA_PERF_SEL_lod_aniso_clk_valid_cycles = 0x000000e5, +TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 0x000000e6, +TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 0x000000e7, +TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 0x000000e8, +TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 0x000000e9, +TA_PERF_SEL_aligner_clk_valid_cycles = 0x000000ea, +TA_PERF_SEL_tcreq_clk_valid_cycles = 0x000000eb, +} TA_PERFCOUNT_SEL; + +/* + * TEX_BC_SWIZZLE enum + */ + +typedef enum TEX_BC_SWIZZLE { +TEX_BC_Swizzle_XYZW = 0x00000000, +TEX_BC_Swizzle_XWYZ = 0x00000001, +TEX_BC_Swizzle_WZYX = 0x00000002, +TEX_BC_Swizzle_WXYZ = 0x00000003, +TEX_BC_Swizzle_ZYXW = 0x00000004, +TEX_BC_Swizzle_YXWZ = 0x00000005, +} TEX_BC_SWIZZLE; + +/* + * TEX_BORDER_COLOR_TYPE enum + */ + +typedef enum TEX_BORDER_COLOR_TYPE { +TEX_BorderColor_TransparentBlack = 0x00000000, +TEX_BorderColor_OpaqueBlack = 0x00000001, +TEX_BorderColor_OpaqueWhite = 0x00000002, +TEX_BorderColor_Register = 0x00000003, +} TEX_BORDER_COLOR_TYPE; + +/* + * TEX_CHROMA_KEY enum + */ + +typedef enum TEX_CHROMA_KEY { +TEX_ChromaKey_Disabled = 0x00000000, +TEX_ChromaKey_Kill = 0x00000001, +TEX_ChromaKey_Blend = 0x00000002, +TEX_ChromaKey_RESERVED_3 = 0x00000003, +} TEX_CHROMA_KEY; + +/* + * TEX_CLAMP enum + */ + +typedef enum TEX_CLAMP { +TEX_Clamp_Repeat = 0x00000000, +TEX_Clamp_Mirror = 0x00000001, +TEX_Clamp_ClampToLast = 0x00000002, +TEX_Clamp_MirrorOnceToLast = 0x00000003, +TEX_Clamp_ClampHalfToBorder = 0x00000004, +TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, +TEX_Clamp_ClampToBorder = 0x00000006, +TEX_Clamp_MirrorOnceToBorder = 0x00000007, +} TEX_CLAMP; + +/* + * TEX_COORD_TYPE enum + */ + +typedef enum TEX_COORD_TYPE { +TEX_CoordType_Unnormalized = 0x00000000, +TEX_CoordType_Normalized = 0x00000001, +} TEX_COORD_TYPE; + +/* + * TEX_DEPTH_COMPARE_FUNCTION enum + */ + +typedef enum TEX_DEPTH_COMPARE_FUNCTION { +TEX_DepthCompareFunction_Never = 0x00000000, +TEX_DepthCompareFunction_Less = 0x00000001, +TEX_DepthCompareFunction_Equal = 0x00000002, +TEX_DepthCompareFunction_LessEqual = 0x00000003, +TEX_DepthCompareFunction_Greater = 0x00000004, +TEX_DepthCompareFunction_NotEqual = 0x00000005, +TEX_DepthCompareFunction_GreaterEqual = 0x00000006, +TEX_DepthCompareFunction_Always = 0x00000007, +} TEX_DEPTH_COMPARE_FUNCTION; + +/* + * TEX_FORMAT_COMP enum + */ + +typedef enum TEX_FORMAT_COMP { +TEX_FormatComp_Unsigned = 0x00000000, +TEX_FormatComp_Signed = 0x00000001, +TEX_FormatComp_UnsignedBiased = 0x00000002, +TEX_FormatComp_RESERVED_3 = 0x00000003, +} TEX_FORMAT_COMP; + +/* + * TEX_MAX_ANISO_RATIO enum + */ + +typedef enum TEX_MAX_ANISO_RATIO { +TEX_MaxAnisoRatio_1to1 = 0x00000000, +TEX_MaxAnisoRatio_2to1 = 0x00000001, +TEX_MaxAnisoRatio_4to1 = 0x00000002, +TEX_MaxAnisoRatio_8to1 = 0x00000003, +TEX_MaxAnisoRatio_16to1 = 0x00000004, +TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, +TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, +TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, +} TEX_MAX_ANISO_RATIO; + +/* + * TEX_MIP_FILTER enum + */ + +typedef enum TEX_MIP_FILTER { +TEX_MipFilter_None = 0x00000000, +TEX_MipFilter_Point = 0x00000001, +TEX_MipFilter_Linear = 0x00000002, +TEX_MipFilter_Point_Aniso_Adj = 0x00000003, +} TEX_MIP_FILTER; + +/* + * TEX_REQUEST_SIZE enum + */ + +typedef enum TEX_REQUEST_SIZE { +TEX_RequestSize_32B = 0x00000000, +TEX_RequestSize_64B = 0x00000001, +TEX_RequestSize_128B = 0x00000002, +TEX_RequestSize_2X64B = 0x00000003, +} TEX_REQUEST_SIZE; + +/* + * TEX_SAMPLER_TYPE enum + */ + +typedef enum TEX_SAMPLER_TYPE { +TEX_SamplerType_Invalid = 0x00000000, +TEX_SamplerType_Valid = 0x00000001, +} TEX_SAMPLER_TYPE; + +/* + * TEX_XY_FILTER enum + */ + +typedef enum TEX_XY_FILTER { +TEX_XYFilter_Point = 0x00000000, +TEX_XYFilter_Linear = 0x00000001, +TEX_XYFilter_AnisoPoint = 0x00000002, +TEX_XYFilter_AnisoLinear = 0x00000003, +} TEX_XY_FILTER; + +/* + * TEX_Z_FILTER enum + */ + +typedef enum TEX_Z_FILTER { +TEX_ZFilter_None = 0x00000000, +TEX_ZFilter_Point = 0x00000001, +TEX_ZFilter_Linear = 0x00000002, +TEX_ZFilter_RESERVED_3 = 0x00000003, +} TEX_Z_FILTER; + +/* + * TVX_TYPE enum + */ + +typedef enum TVX_TYPE { +TVX_Type_InvalidTextureResource = 0x00000000, +TVX_Type_InvalidVertexBuffer = 0x00000001, +TVX_Type_ValidTextureResource = 0x00000002, +TVX_Type_ValidVertexBuffer = 0x00000003, +} TVX_TYPE; + +/******************************************************* + * TCP Enums + *******************************************************/ + +/* + * TA_TC_ADDR_MODES enum + */ + +typedef enum TA_TC_ADDR_MODES { +TA_TC_ADDR_MODE_DEFAULT = 0x00000000, +TA_TC_ADDR_MODE_COMP0 = 0x00000001, +TA_TC_ADDR_MODE_COMP1 = 0x00000002, +TA_TC_ADDR_MODE_COMP2 = 0x00000003, +TA_TC_ADDR_MODE_COMP3 = 0x00000004, +TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, +TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, +} TA_TC_ADDR_MODES; + +/* + * TA_TC_REQ_MODES enum + */ + +typedef enum TA_TC_REQ_MODES { +TA_TC_REQ_MODE_BORDER = 0x00000000, +TA_TC_REQ_MODE_TEX2 = 0x00000001, +TA_TC_REQ_MODE_TEX1 = 0x00000002, +TA_TC_REQ_MODE_TEX0 = 0x00000003, +TA_TC_REQ_MODE_NORMAL = 0x00000004, +TA_TC_REQ_MODE_DWORD = 0x00000005, +TA_TC_REQ_MODE_BYTE = 0x00000006, +TA_TC_REQ_MODE_BYTE_NV = 0x00000007, +} TA_TC_REQ_MODES; + +/* + * TCP_CACHE_POLICIES enum + */ + +typedef enum TCP_CACHE_POLICIES { +TCP_CACHE_POLICY_MISS_LRU = 0x00000000, +TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, +TCP_CACHE_POLICY_HIT_LRU = 0x00000002, +TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, +} TCP_CACHE_POLICIES; + +/* + * TCP_CACHE_STORE_POLICIES enum + */ + +typedef enum TCP_CACHE_STORE_POLICIES { +TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000, +TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001, +} TCP_CACHE_STORE_POLICIES; + +/* + * TCP_DSM_DATA_SEL enum + */ + +typedef enum TCP_DSM_DATA_SEL { +TCP_DSM_DISABLE = 0x00000000, +TCP_DSM_SEL0 = 0x00000001, +TCP_DSM_SEL1 = 0x00000002, +TCP_DSM_SEL_BOTH = 0x00000003, +} TCP_DSM_DATA_SEL; + +/* + * TCP_DSM_INJECT_SEL enum + */ + +typedef enum TCP_DSM_INJECT_SEL { +TCP_DSM_INJECT_SEL0 = 0x00000000, +TCP_DSM_INJECT_SEL1 = 0x00000001, +TCP_DSM_INJECT_SEL2 = 0x00000002, +TCP_DSM_INJECT_SEL3 = 0x00000003, +} TCP_DSM_INJECT_SEL; + +/* + * TCP_DSM_SINGLE_WRITE enum + */ + +typedef enum TCP_DSM_SINGLE_WRITE { +TCP_DSM_SINGLE_WRITE_DIS = 0x00000000, +TCP_DSM_SINGLE_WRITE_EN = 0x00000001, +} TCP_DSM_SINGLE_WRITE; + +/* + * TCP_OPCODE_TYPE enum + */ + +typedef enum TCP_OPCODE_TYPE { +TCP_OPCODE_READ = 0x00000000, +TCP_OPCODE_WRITE = 0x00000001, +TCP_OPCODE_ATOMIC = 0x00000002, +TCP_OPCODE_INV = 0x00000003, +TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004, +TCP_OPCODE_SAMPLER = 0x00000005, +TCP_OPCODE_LOAD = 0x00000006, +TCP_OPCODE_GATHERH = 0x00000007, +} TCP_OPCODE_TYPE; + +/* + * TCP_PERFCOUNT_SELECT enum + */ + +typedef enum TCP_PERFCOUNT_SELECT { +TCP_PERF_SEL_GATE_EN1 = 0x00000000, +TCP_PERF_SEL_GATE_EN2 = 0x00000001, +TCP_PERF_SEL_TA_REQ = 0x00000002, +TCP_PERF_SEL_TA_REQ_STATE_READ = 0x00000003, +TCP_PERF_SEL_TA_REQ_READ = 0x00000004, +TCP_PERF_SEL_TA_REQ_WRITE = 0x00000005, +TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 0x00000006, +TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 0x00000007, +TCP_PERF_SEL_TA_REQ_GL0_INV = 0x00000008, +TCP_PERF_SEL_REQ = 0x00000009, +TCP_PERF_SEL_REQ_READ = 0x0000000a, +TCP_PERF_SEL_REQ_READ_HIT_EVICT = 0x0000000b, +TCP_PERF_SEL_REQ_READ_HIT_LRU = 0x0000000c, +TCP_PERF_SEL_REQ_READ_MISS_EVICT = 0x0000000d, +TCP_PERF_SEL_REQ_WRITE = 0x0000000e, +TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 0x0000000f, +TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 0x00000010, +TCP_PERF_SEL_REQ_NON_READ = 0x00000011, +TCP_PERF_SEL_REQ_MISS = 0x00000012, +TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 0x00000013, +TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 0x00000014, +TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 0x00000015, +TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 0x00000016, +TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 0x00000017, +TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 0x00000018, +TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 0x00000019, +TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 0x0000001a, +TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 0x0000001b, +TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 0x0000001c, +TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 0x0000001d, +TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 0x0000001e, +TCP_PERF_SEL_GL1_REQ_READ = 0x0000001f, +TCP_PERF_SEL_GL1_REQ_READ_128B = 0x00000020, +TCP_PERF_SEL_GL1_REQ_READ_64B = 0x00000021, +TCP_PERF_SEL_GL1_REQ_WRITE = 0x00000022, +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 0x00000023, +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 0x00000024, +TCP_PERF_SEL_GL1_READ_LATENCY = 0x00000025, +TCP_PERF_SEL_GL1_WRITE_LATENCY = 0x00000026, +TCP_PERF_SEL_TCP_LATENCY = 0x00000027, +TCP_PERF_SEL_TCP_TA_REQ_STALL = 0x00000028, +TCP_PERF_SEL_TA_TCP_REQ_STARVE = 0x00000029, +TCP_PERF_SEL_DATA_FIFO_STALL = 0x0000002a, +TCP_PERF_SEL_LOD_STALL = 0x0000002b, +TCP_PERF_SEL_POWER_STALL = 0x0000002c, +TCP_PERF_SEL_ALLOC_STALL = 0x0000002d, +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x0000002e, +TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 0x0000002f, +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 0x00000030, +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 0x00000031, +TCP_PERF_SEL_LFIFO_STALL = 0x00000032, +TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 0x00000033, +TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 0x00000034, +TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 0x00000035, +TCP_PERF_SEL_GL1_GRANT_READ_STALL = 0x00000036, +TCP_PERF_SEL_GL1_PENDING_STALL = 0x00000037, +TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 0x00000038, +TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 0x00000039, +TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 0x0000003a, +TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 0x0000003b, +TCP_PERF_SEL_READ_DATACONFLICT_STALL = 0x0000003c, +TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 0x0000003d, +TCP_PERF_SEL_TD_TCP_STALL = 0x0000003e, +} TCP_PERFCOUNT_SELECT; + +/* + * TCP_WATCH_MODES enum + */ + +typedef enum TCP_WATCH_MODES { +TCP_WATCH_MODE_READ = 0x00000000, +TCP_WATCH_MODE_NONREAD = 0x00000001, +TCP_WATCH_MODE_ATOMIC = 0x00000002, +TCP_WATCH_MODE_ALL = 0x00000003, +} TCP_WATCH_MODES; + +/******************************************************* + * TD Enums + *******************************************************/ + +/* + * TD_PERFCOUNT_SEL enum + */ + +typedef enum TD_PERFCOUNT_SEL { +TD_PERF_SEL_none = 0x00000000, +TD_PERF_SEL_td_busy = 0x00000001, +TD_PERF_SEL_input_busy = 0x00000002, +TD_PERF_SEL_sampler_lerp_busy = 0x00000003, +TD_PERF_SEL_sampler_out_busy = 0x00000004, +TD_PERF_SEL_nofilter_busy = 0x00000005, +TD_PERF_SEL_ray_tracing_bvh4_busy = 0x00000006, +TD_PERF_SEL_sampler_core_sclk_en = 0x00000007, +TD_PERF_SEL_sampler_preformatter_sclk_en = 0x00000008, +TD_PERF_SEL_sampler_bilerp_sclk_en = 0x00000009, +TD_PERF_SEL_sampler_bypass_sclk_en = 0x0000000a, +TD_PERF_SEL_sampler_minmax_sclk_en = 0x0000000b, +TD_PERF_SEL_sampler_accum_sclk_en = 0x0000000c, +TD_PERF_SEL_sampler_format_flt_sclk_en = 0x0000000d, +TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 0x0000000e, +TD_PERF_SEL_sampler_out_sclk_en = 0x0000000f, +TD_PERF_SEL_nofilter_sclk_en = 0x00000010, +TD_PERF_SEL_nofilter_d32_sclk_en = 0x00000011, +TD_PERF_SEL_nofilter_d16_sclk_en = 0x00000012, +TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 0x00000016, +TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 0x00000017, +TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 0x00000018, +TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 0x00000019, +TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x0000001a, +TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x0000001b, +TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 0x0000001c, +TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 0x0000001d, +TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 0x0000001e, +TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 0x0000001f, +TD_PERF_SEL_core_state_ram_max_cnt = 0x00000020, +TD_PERF_SEL_core_state_rams_read = 0x00000021, +TD_PERF_SEL_weight_data_rams_read = 0x00000022, +TD_PERF_SEL_reference_data_rams_read = 0x00000023, +TD_PERF_SEL_tc_td_ram_fifo_full = 0x00000024, +TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 0x00000025, +TD_PERF_SEL_tc_td_data_fifo_full = 0x00000026, +TD_PERF_SEL_input_state_fifo_full = 0x00000027, +TD_PERF_SEL_ta_data_stall = 0x00000028, +TD_PERF_SEL_tc_data_stall = 0x00000029, +TD_PERF_SEL_tc_ram_stall = 0x0000002a, +TD_PERF_SEL_lds_stall = 0x0000002b, +TD_PERF_SEL_sampler_pkr_full = 0x0000002c, +TD_PERF_SEL_sampler_pkr_full_due_to_arb = 0x0000002d, +TD_PERF_SEL_nofilter_pkr_full = 0x0000002e, +TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 0x0000002f, +TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 0x00000030, +TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 0x00000031, +TD_PERF_SEL_gather4_instr = 0x00000032, +TD_PERF_SEL_gather4h_instr = 0x00000033, +TD_PERF_SEL_sample_instr = 0x00000036, +TD_PERF_SEL_sample_c_instr = 0x00000037, +TD_PERF_SEL_load_instr = 0x00000038, +TD_PERF_SEL_ldfptr_instr = 0x00000039, +TD_PERF_SEL_write_ack_instr = 0x0000003a, +TD_PERF_SEL_d16_en_instr = 0x0000003b, +TD_PERF_SEL_bypassLerp_instr = 0x0000003c, +TD_PERF_SEL_min_max_filter_instr = 0x0000003d, +TD_PERF_SEL_one_comp_return_instr = 0x0000003e, +TD_PERF_SEL_two_comp_return_instr = 0x0000003f, +TD_PERF_SEL_three_comp_return_instr = 0x00000040, +TD_PERF_SEL_four_comp_return_instr = 0x00000041, +TD_PERF_SEL_user_defined_border = 0x00000042, +TD_PERF_SEL_white_border = 0x00000043, +TD_PERF_SEL_opaque_black_border = 0x00000044, +TD_PERF_SEL_lod_warn_from_ta = 0x00000045, +TD_PERF_SEL_instruction_dest_is_lds = 0x00000046, +TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 0x00000047, +TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 0x00000048, +TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 0x00000049, +TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 0x0000004a, +TD_PERF_SEL_out_of_order_instr = 0x0000004b, +TD_PERF_SEL_total_num_instr = 0x0000004c, +TD_PERF_SEL_total_num_instr_with_perf_wdw = 0x0000004d, +TD_PERF_SEL_total_num_sampler_instr = 0x0000004e, +TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 0x0000004f, +TD_PERF_SEL_total_num_nofilter_instr = 0x00000050, +TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 0x00000051, +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 0x00000052, +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 0x00000053, +TD_PERF_SEL_mixmode_instr = 0x00000054, +TD_PERF_SEL_mixmode_resource = 0x00000055, +TD_PERF_SEL_status_packet = 0x00000056, +TD_PERF_SEL_address_cmd_poison = 0x00000057, +TD_PERF_SEL_data_poison = 0x00000058, +TD_PERF_SEL_done_scoreboard_max_stored_cnt = 0x00000059, +TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 0x0000005a, +TD_PERF_SEL_done_scoreboard_not_empty = 0x0000005b, +TD_PERF_SEL_done_scoreboard_is_full = 0x0000005c, +TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x0000005d, +TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x0000005e, +TD_PERF_SEL_nofilter_formatters_turned_on = 0x0000005f, +TD_PERF_SEL_nofilter_insert_extra_comps = 0x00000060, +TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000061, +TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x00000062, +TD_PERF_SEL_msaa_load_instr = 0x00000063, +TD_PERF_SEL_blend_prt_with_prt_default_0 = 0x00000064, +TD_PERF_SEL_blend_prt_with_prt_default_1 = 0x00000065, +TD_PERF_SEL_resmap_instr = 0x00000066, +TD_PERF_SEL_prt_ack_instr = 0x00000067, +TD_PERF_SEL_resmap_with_volume_filtering = 0x00000068, +TD_PERF_SEL_resmap_with_aniso_filtering = 0x00000069, +TD_PERF_SEL_resmap_with_no_more_filtering = 0x0000006a, +TD_PERF_SEL_resmap_with_cubemap_corner = 0x0000006b, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 0x0000006c, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 0x0000006d, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 0x0000006e, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 0x0000006f, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 0x00000070, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 0x00000071, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 0x00000072, +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 0x00000073, +TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 0x00000074, +TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 0x00000075, +TD_PERF_SEL_ray_tracing_bvh4_tri_node = 0x00000076, +TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 0x00000077, +TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 0x00000078, +TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 0x00000079, +TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 0x0000007a, +TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 0x0000007b, +TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 0x0000007c, +TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 0x0000007d, +TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 0x0000007e, +TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 0x0000007f, +TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 0x00000080, +TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 0x00000081, +TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 0x00000082, +TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 0x00000083, +TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 0x00000084, +TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 0x00000085, +TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 0x00000086, +TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 0x00000087, +TD_PERF_SEL_burst_bin_sampler_1 = 0x00000088, +TD_PERF_SEL_burst_bin_sampler_2to8 = 0x00000089, +TD_PERF_SEL_burst_bin_sampler_9to16 = 0x0000008a, +TD_PERF_SEL_burst_bin_sampler_gt16 = 0x0000008b, +TD_PERF_SEL_burst_bin_gather_1 = 0x0000008c, +TD_PERF_SEL_burst_bin_gather_2to8 = 0x0000008d, +TD_PERF_SEL_burst_bin_gather_9to16 = 0x0000008e, +TD_PERF_SEL_burst_bin_gather_gt16 = 0x0000008f, +TD_PERF_SEL_burst_bin_nofilter_1 = 0x00000090, +TD_PERF_SEL_burst_bin_nofilter_2to4 = 0x00000091, +TD_PERF_SEL_burst_bin_nofilter_5to7 = 0x00000092, +TD_PERF_SEL_burst_bin_nofilter_8to16 = 0x00000093, +TD_PERF_SEL_burst_bin_nofilter_gt16 = 0x00000094, +TD_PERF_SEL_burst_bin_bvh4_1 = 0x00000095, +TD_PERF_SEL_burst_bin_bvh4_2to8 = 0x00000096, +TD_PERF_SEL_burst_bin_bvh4_9to16 = 0x00000097, +TD_PERF_SEL_burst_bin_bvh4_gt16 = 0x00000098, +TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 0x00000099, +TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 0x0000009a, +TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 0x0000009b, +TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 0x0000009c, +TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 0x0000009d, +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 0x0000009e, +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 0x0000009f, +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 0x000000a0, +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 0x000000a1, +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 0x000000a2, +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 0x000000a3, +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 0x000000a4, +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 0x000000a5, +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 0x000000a6, +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 0x000000a7, +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 0x000000a8, +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 0x000000a9, +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 0x000000aa, +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 0x000000ab, +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 0x000000ac, +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 0x000000ad, +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 0x000000ae, +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 0x000000af, +TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 0x000000b0, +TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 0x000000b1, +TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 0x000000b2, +TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 0x000000b3, +TD_PERF_SEL_preempting_nofilter_max_cnt = 0x000000b4, +TD_PERF_SEL_sampler_lerp0_active = 0x000000b5, +TD_PERF_SEL_sampler_lerp1_active = 0x000000b6, +TD_PERF_SEL_sampler_lerp2_active = 0x000000b7, +TD_PERF_SEL_sampler_lerp3_active = 0x000000b8, +TD_PERF_SEL_nofilter_total_num_comps_to_lds = 0x000000b9, +TD_PERF_SEL_nofilter_byte_cycling_4cycles = 0x000000ba, +TD_PERF_SEL_nofilter_byte_cycling_8cycles = 0x000000bb, +TD_PERF_SEL_nofilter_byte_cycling_16cycles = 0x000000bc, +TD_PERF_SEL_nofilter_dword_cycling_2cycles = 0x000000bd, +TD_PERF_SEL_nofilter_dword_cycling_4cycles = 0x000000be, +TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 0x000000bf, +TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 0x000000c0, +} TD_PERFCOUNT_SEL; + +/******************************************************* + * GL2C Enums + *******************************************************/ + +/* + * GL2A_PERF_SEL enum + */ + +typedef enum GL2A_PERF_SEL { +GL2A_PERF_SEL_NONE = 0x00000000, +GL2A_PERF_SEL_CYCLE = 0x00000001, +GL2A_PERF_SEL_BUSY = 0x00000002, +GL2A_PERF_SEL_REQ_GL2C0 = 0x00000003, +GL2A_PERF_SEL_REQ_GL2C1 = 0x00000004, +GL2A_PERF_SEL_REQ_GL2C2 = 0x00000005, +GL2A_PERF_SEL_REQ_GL2C3 = 0x00000006, +GL2A_PERF_SEL_REQ_GL2C4 = 0x00000007, +GL2A_PERF_SEL_REQ_GL2C5 = 0x00000008, +GL2A_PERF_SEL_REQ_GL2C6 = 0x00000009, +GL2A_PERF_SEL_REQ_GL2C7 = 0x0000000a, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 0x0000000b, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 0x0000000c, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 0x0000000d, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 0x0000000e, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 0x0000000f, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 0x00000010, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 0x00000011, +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 0x00000012, +GL2A_PERF_SEL_REQ_BURST_GL2C0 = 0x00000013, +GL2A_PERF_SEL_REQ_BURST_GL2C1 = 0x00000014, +GL2A_PERF_SEL_REQ_BURST_GL2C2 = 0x00000015, +GL2A_PERF_SEL_REQ_BURST_GL2C3 = 0x00000016, +GL2A_PERF_SEL_REQ_BURST_GL2C4 = 0x00000017, +GL2A_PERF_SEL_REQ_BURST_GL2C5 = 0x00000018, +GL2A_PERF_SEL_REQ_BURST_GL2C6 = 0x00000019, +GL2A_PERF_SEL_REQ_BURST_GL2C7 = 0x0000001a, +GL2A_PERF_SEL_REQ_STALL_GL2C0 = 0x0000001b, +GL2A_PERF_SEL_REQ_STALL_GL2C1 = 0x0000001c, +GL2A_PERF_SEL_REQ_STALL_GL2C2 = 0x0000001d, +GL2A_PERF_SEL_REQ_STALL_GL2C3 = 0x0000001e, +GL2A_PERF_SEL_REQ_STALL_GL2C4 = 0x0000001f, +GL2A_PERF_SEL_REQ_STALL_GL2C5 = 0x00000020, +GL2A_PERF_SEL_REQ_STALL_GL2C6 = 0x00000021, +GL2A_PERF_SEL_REQ_STALL_GL2C7 = 0x00000022, +GL2A_PERF_SEL_RTN_STALL_GL2C0 = 0x00000023, +GL2A_PERF_SEL_RTN_STALL_GL2C1 = 0x00000024, +GL2A_PERF_SEL_RTN_STALL_GL2C2 = 0x00000025, +GL2A_PERF_SEL_RTN_STALL_GL2C3 = 0x00000026, +GL2A_PERF_SEL_RTN_STALL_GL2C4 = 0x00000027, +GL2A_PERF_SEL_RTN_STALL_GL2C5 = 0x00000028, +GL2A_PERF_SEL_RTN_STALL_GL2C6 = 0x00000029, +GL2A_PERF_SEL_RTN_STALL_GL2C7 = 0x0000002a, +GL2A_PERF_SEL_RTN_CLIENT0 = 0x0000002b, +GL2A_PERF_SEL_RTN_CLIENT1 = 0x0000002c, +GL2A_PERF_SEL_RTN_CLIENT2 = 0x0000002d, +GL2A_PERF_SEL_RTN_CLIENT3 = 0x0000002e, +GL2A_PERF_SEL_RTN_CLIENT4 = 0x0000002f, +GL2A_PERF_SEL_RTN_CLIENT5 = 0x00000030, +GL2A_PERF_SEL_RTN_CLIENT6 = 0x00000031, +GL2A_PERF_SEL_RTN_CLIENT7 = 0x00000032, +GL2A_PERF_SEL_RTN_CLIENT8 = 0x00000033, +GL2A_PERF_SEL_RTN_CLIENT9 = 0x00000034, +GL2A_PERF_SEL_RTN_CLIENT10 = 0x00000035, +GL2A_PERF_SEL_RTN_CLIENT11 = 0x00000036, +GL2A_PERF_SEL_RTN_CLIENT12 = 0x00000037, +GL2A_PERF_SEL_RTN_CLIENT13 = 0x00000038, +GL2A_PERF_SEL_RTN_CLIENT14 = 0x00000039, +GL2A_PERF_SEL_RTN_CLIENT15 = 0x0000003a, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 0x0000003b, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 0x0000003c, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 0x0000003d, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 0x0000003e, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 0x0000003f, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 0x00000040, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 0x00000041, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 0x00000042, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 0x00000043, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 0x00000044, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 0x00000045, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 0x00000046, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 0x00000047, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 0x00000048, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 0x00000049, +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 0x0000004a, +GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 0x0000004b, +GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 0x0000004c, +GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 0x0000004d, +GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 0x0000004e, +GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 0x0000004f, +GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 0x00000050, +GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 0x00000051, +GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 0x00000052, +GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 0x00000053, +GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 0x00000054, +GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 0x00000055, +GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 0x00000056, +GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 0x00000057, +GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 0x00000058, +GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 0x00000059, +GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 0x0000005a, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 0x0000005b, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 0x0000005c, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 0x0000005d, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 0x0000005e, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 0x0000005f, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 0x00000060, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 0x00000061, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 0x00000062, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 0x00000063, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 0x00000064, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 0x00000065, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 0x00000067, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 0x00000068, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 0x00000069, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 0x0000006a, +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 0x0000006b, +} GL2A_PERF_SEL; + +/* + * GL2C_PERF_SEL enum + */ + +typedef enum GL2C_PERF_SEL { +GL2C_PERF_SEL_NONE = 0x00000000, +GL2C_PERF_SEL_CYCLE = 0x00000001, +GL2C_PERF_SEL_BUSY = 0x00000002, +GL2C_PERF_SEL_REQ = 0x00000003, +GL2C_PERF_SEL_VOL_REQ = 0x00000004, +GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 0x00000005, +GL2C_PERF_SEL_READ = 0x00000006, +GL2C_PERF_SEL_WRITE = 0x00000007, +GL2C_PERF_SEL_ATOMIC = 0x00000008, +GL2C_PERF_SEL_NOP_ACK = 0x00000009, +GL2C_PERF_SEL_NOP_RTN0 = 0x0000000a, +GL2C_PERF_SEL_PROBE = 0x0000000b, +GL2C_PERF_SEL_PROBE_ALL = 0x0000000c, +GL2C_PERF_SEL_INTERNAL_PROBE = 0x0000000d, +GL2C_PERF_SEL_COMPRESSED_READ_REQ = 0x0000000e, +GL2C_PERF_SEL_METADATA_READ_REQ = 0x0000000f, +GL2C_PERF_SEL_CLIENT0_REQ = 0x00000010, +GL2C_PERF_SEL_CLIENT1_REQ = 0x00000011, +GL2C_PERF_SEL_CLIENT2_REQ = 0x00000012, +GL2C_PERF_SEL_CLIENT3_REQ = 0x00000013, +GL2C_PERF_SEL_CLIENT4_REQ = 0x00000014, +GL2C_PERF_SEL_CLIENT5_REQ = 0x00000015, +GL2C_PERF_SEL_CLIENT6_REQ = 0x00000016, +GL2C_PERF_SEL_CLIENT7_REQ = 0x00000017, +GL2C_PERF_SEL_CLIENT8_REQ = 0x00000018, +GL2C_PERF_SEL_CLIENT9_REQ = 0x00000019, +GL2C_PERF_SEL_CLIENT10_REQ = 0x0000001a, +GL2C_PERF_SEL_CLIENT11_REQ = 0x0000001b, +GL2C_PERF_SEL_CLIENT12_REQ = 0x0000001c, +GL2C_PERF_SEL_CLIENT13_REQ = 0x0000001d, +GL2C_PERF_SEL_CLIENT14_REQ = 0x0000001e, +GL2C_PERF_SEL_CLIENT15_REQ = 0x0000001f, +GL2C_PERF_SEL_C_RW_S_REQ = 0x00000020, +GL2C_PERF_SEL_C_RW_US_REQ = 0x00000021, +GL2C_PERF_SEL_C_RO_S_REQ = 0x00000022, +GL2C_PERF_SEL_C_RO_US_REQ = 0x00000023, +GL2C_PERF_SEL_UC_REQ = 0x00000024, +GL2C_PERF_SEL_LRU_REQ = 0x00000025, +GL2C_PERF_SEL_STREAM_REQ = 0x00000026, +GL2C_PERF_SEL_BYPASS_REQ = 0x00000027, +GL2C_PERF_SEL_NOA_REQ = 0x00000028, +GL2C_PERF_SEL_SHARED_REQ = 0x00000029, +GL2C_PERF_SEL_HIT = 0x0000002a, +GL2C_PERF_SEL_MISS = 0x0000002b, +GL2C_PERF_SEL_FULL_HIT = 0x0000002c, +GL2C_PERF_SEL_PARTIAL_32B_HIT = 0x0000002d, +GL2C_PERF_SEL_PARTIAL_64B_HIT = 0x0000002e, +GL2C_PERF_SEL_PARTIAL_96B_HIT = 0x0000002f, +GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000030, +GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000031, +GL2C_PERF_SEL_UNCACHED_WRITE = 0x00000032, +GL2C_PERF_SEL_WRITEBACK = 0x00000033, +GL2C_PERF_SEL_NORMAL_WRITEBACK = 0x00000034, +GL2C_PERF_SEL_EVICT = 0x00000035, +GL2C_PERF_SEL_NORMAL_EVICT = 0x00000036, +GL2C_PERF_SEL_PROBE_EVICT = 0x00000037, +GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 0x00000038, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 0x00000039, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 0x0000003a, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 0x0000003b, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 0x0000003c, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 0x0000003d, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 0x0000003e, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 0x0000003f, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 0x00000040, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 0x00000041, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 0x00000042, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 0x00000043, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 0x00000044, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 0x00000045, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 0x00000046, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 0x00000047, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 0x00000048, +GL2C_PERF_SEL_READ_32_REQ = 0x00000049, +GL2C_PERF_SEL_READ_64_REQ = 0x0000004a, +GL2C_PERF_SEL_READ_128_REQ = 0x0000004b, +GL2C_PERF_SEL_WRITE_32_REQ = 0x0000004c, +GL2C_PERF_SEL_WRITE_64_REQ = 0x0000004d, +GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 0x0000004e, +GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 0x0000004f, +GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 0x00000050, +GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 0x00000051, +GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 0x00000052, +GL2C_PERF_SEL_MC_WRREQ = 0x00000053, +GL2C_PERF_SEL_EA_WRREQ_SNOOP = 0x00000054, +GL2C_PERF_SEL_EA_WRREQ_64B = 0x00000055, +GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x00000056, +GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000057, +GL2C_PERF_SEL_MC_WRREQ_STALL = 0x00000058, +GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x00000059, +GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x0000005a, +GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x0000005b, +GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x0000005c, +GL2C_PERF_SEL_MC_WRREQ_LEVEL = 0x0000005d, +GL2C_PERF_SEL_EA_ATOMIC = 0x0000005e, +GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 0x0000005f, +GL2C_PERF_SEL_MC_RDREQ = 0x00000060, +GL2C_PERF_SEL_EA_RDREQ_SNOOP = 0x00000061, +GL2C_PERF_SEL_EA_RDREQ_SPLIT = 0x00000062, +GL2C_PERF_SEL_EA_RDREQ_32B = 0x00000063, +GL2C_PERF_SEL_EA_RDREQ_64B = 0x00000064, +GL2C_PERF_SEL_EA_RDREQ_96B = 0x00000065, +GL2C_PERF_SEL_EA_RDREQ_128B = 0x00000066, +GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000067, +GL2C_PERF_SEL_EA_RD_MDC_32B = 0x00000068, +GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000069, +GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x0000006a, +GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x0000006b, +GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x0000006c, +GL2C_PERF_SEL_MC_RDREQ_LEVEL = 0x0000006d, +GL2C_PERF_SEL_EA_RDREQ_DRAM = 0x0000006e, +GL2C_PERF_SEL_EA_WRREQ_DRAM = 0x0000006f, +GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 0x00000070, +GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 0x00000071, +GL2C_PERF_SEL_ONION_READ = 0x00000072, +GL2C_PERF_SEL_ONION_WRITE = 0x00000073, +GL2C_PERF_SEL_IO_READ = 0x00000074, +GL2C_PERF_SEL_IO_WRITE = 0x00000075, +GL2C_PERF_SEL_GARLIC_READ = 0x00000076, +GL2C_PERF_SEL_GARLIC_WRITE = 0x00000077, +GL2C_PERF_SEL_EA_OUTSTANDING = 0x00000078, +GL2C_PERF_SEL_LATENCY_FIFO_FULL = 0x00000079, +GL2C_PERF_SEL_SRC_FIFO_FULL = 0x0000007a, +GL2C_PERF_SEL_TAG_STALL = 0x0000007b, +GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000007c, +GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000007d, +GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000007e, +GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000007f, +GL2C_PERF_SEL_TAG_PROBE_STALL = 0x00000080, +GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000081, +GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 0x00000082, +GL2C_PERF_SEL_TAG_READ_DST_STALL = 0x00000083, +GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000084, +GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000085, +GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000086, +GL2C_PERF_SEL_BUBBLE = 0x00000087, +GL2C_PERF_SEL_IB_REQ = 0x00000088, +GL2C_PERF_SEL_IB_STALL = 0x00000089, +GL2C_PERF_SEL_IB_TAG_STALL = 0x0000008a, +GL2C_PERF_SEL_IB_CM_STALL = 0x0000008b, +GL2C_PERF_SEL_RETURN_ACK = 0x0000008c, +GL2C_PERF_SEL_RETURN_DATA = 0x0000008d, +GL2C_PERF_SEL_EA_RDRET_NACK = 0x0000008e, +GL2C_PERF_SEL_EA_WRRET_NACK = 0x0000008f, +GL2C_PERF_SEL_GL2A_LEVEL = 0x00000090, +GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000091, +GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 0x00000092, +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000093, +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000094, +GL2C_PERF_SEL_GCR_INV = 0x00000095, +GL2C_PERF_SEL_GCR_WB = 0x00000096, +GL2C_PERF_SEL_GCR_DISCARD = 0x00000097, +GL2C_PERF_SEL_GCR_RANGE = 0x00000098, +GL2C_PERF_SEL_GCR_ALL = 0x00000099, +GL2C_PERF_SEL_GCR_VOL = 0x0000009a, +GL2C_PERF_SEL_GCR_UNSHARED = 0x0000009b, +GL2C_PERF_SEL_GCR_MDC_INV = 0x0000009c, +GL2C_PERF_SEL_GCR_GL2_INV_ALL = 0x0000009d, +GL2C_PERF_SEL_GCR_GL2_WB_ALL = 0x0000009e, +GL2C_PERF_SEL_GCR_MDC_INV_ALL = 0x0000009f, +GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 0x000000a0, +GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 0x000000a1, +GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 0x000000a2, +GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 0x000000a3, +GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 0x000000a4, +GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 0x000000a5, +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 0x000000a6, +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x000000a7, +GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 0x000000a8, +GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 0x000000a9, +GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 0x000000aa, +GL2C_PERF_SEL_GCR_INVL2_VOL_START = 0x000000ab, +GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 0x000000ac, +GL2C_PERF_SEL_GCR_WBL2_VOL_START = 0x000000ad, +GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 0x000000ae, +GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 0x000000af, +GL2C_PERF_SEL_GCR_WBINVL2_START = 0x000000b0, +GL2C_PERF_SEL_MDC_INV_METADATA = 0x000000b1, +GL2C_PERF_SEL_MDC_REQ = 0x000000b2, +GL2C_PERF_SEL_MDC_LEVEL = 0x000000b3, +GL2C_PERF_SEL_MDC_TAG_HIT = 0x000000b4, +GL2C_PERF_SEL_MDC_SECTOR_HIT = 0x000000b5, +GL2C_PERF_SEL_MDC_SECTOR_MISS = 0x000000b6, +GL2C_PERF_SEL_MDC_TAG_STALL = 0x000000b7, +GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x000000b8, +GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x000000b9, +GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x000000ba, +GL2C_PERF_SEL_CM_CHANNEL0_REQ = 0x000000bb, +GL2C_PERF_SEL_CM_CHANNEL1_REQ = 0x000000bc, +GL2C_PERF_SEL_CM_CHANNEL2_REQ = 0x000000bd, +GL2C_PERF_SEL_CM_CHANNEL3_REQ = 0x000000be, +GL2C_PERF_SEL_CM_CHANNEL4_REQ = 0x000000bf, +GL2C_PERF_SEL_CM_CHANNEL5_REQ = 0x000000c0, +GL2C_PERF_SEL_CM_CHANNEL6_REQ = 0x000000c1, +GL2C_PERF_SEL_CM_CHANNEL7_REQ = 0x000000c2, +GL2C_PERF_SEL_CM_CHANNEL8_REQ = 0x000000c3, +GL2C_PERF_SEL_CM_CHANNEL9_REQ = 0x000000c4, +GL2C_PERF_SEL_CM_CHANNEL10_REQ = 0x000000c5, +GL2C_PERF_SEL_CM_CHANNEL11_REQ = 0x000000c6, +GL2C_PERF_SEL_CM_CHANNEL12_REQ = 0x000000c7, +GL2C_PERF_SEL_CM_CHANNEL13_REQ = 0x000000c8, +GL2C_PERF_SEL_CM_CHANNEL14_REQ = 0x000000c9, +GL2C_PERF_SEL_CM_CHANNEL15_REQ = 0x000000ca, +GL2C_PERF_SEL_CM_CHANNEL16_REQ = 0x000000cb, +GL2C_PERF_SEL_CM_CHANNEL17_REQ = 0x000000cc, +GL2C_PERF_SEL_CM_CHANNEL18_REQ = 0x000000cd, +GL2C_PERF_SEL_CM_CHANNEL19_REQ = 0x000000ce, +GL2C_PERF_SEL_CM_CHANNEL20_REQ = 0x000000cf, +GL2C_PERF_SEL_CM_CHANNEL21_REQ = 0x000000d0, +GL2C_PERF_SEL_CM_CHANNEL22_REQ = 0x000000d1, +GL2C_PERF_SEL_CM_CHANNEL23_REQ = 0x000000d2, +GL2C_PERF_SEL_CM_CHANNEL24_REQ = 0x000000d3, +GL2C_PERF_SEL_CM_CHANNEL25_REQ = 0x000000d4, +GL2C_PERF_SEL_CM_CHANNEL26_REQ = 0x000000d5, +GL2C_PERF_SEL_CM_CHANNEL27_REQ = 0x000000d6, +GL2C_PERF_SEL_CM_CHANNEL28_REQ = 0x000000d7, +GL2C_PERF_SEL_CM_CHANNEL29_REQ = 0x000000d8, +GL2C_PERF_SEL_CM_CHANNEL30_REQ = 0x000000d9, +GL2C_PERF_SEL_CM_CHANNEL31_REQ = 0x000000da, +GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 0x000000db, +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 0x000000dc, +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 0x000000dd, +GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 0x000000de, +GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 0x000000df, +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 0x000000e0, +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 0x000000e1, +GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 0x000000e2, +GL2C_PERF_SEL_CM_COMP_READ_REQ = 0x000000e3, +GL2C_PERF_SEL_CM_READ_BACK_REQ = 0x000000e4, +GL2C_PERF_SEL_CM_METADATA_WR_REQ = 0x000000e5, +GL2C_PERF_SEL_CM_WR_ACK_REQ = 0x000000e6, +GL2C_PERF_SEL_CM_NO_ACK_REQ = 0x000000e7, +GL2C_PERF_SEL_CM_NOOP_REQ = 0x000000e8, +GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 0x000000e9, +GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 0x000000ea, +GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 0x000000eb, +GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 0x000000ec, +GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 0x000000ed, +GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 0x000000ee, +GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 0x000000ef, +GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 0x000000f0, +GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 0x000000f1, +GL2C_PERF_SEL_CM_RVF_FULL = 0x000000f2, +GL2C_PERF_SEL_CM_SDR_FULL = 0x000000f3, +GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 0x000000f4, +GL2C_PERF_SEL_CM_DCC_STALL = 0x000000f5, +GL2C_PERF_SEL_CM_DCC_IN_XFC = 0x000000f6, +GL2C_PERF_SEL_CM_DCC_OUT_XFC = 0x000000f7, +GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 0x000000f8, +GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 0x000000f9, +GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 0x000000fa, +GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 0x000000fb, +GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 0x000000fc, +GL2C_PERF_SEL_CM_DCC_OUT_CONST = 0x000000fd, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 0x000000fe, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 0x000000ff, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 0x00000100, +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 0x00000101, +} GL2C_PERF_SEL; + +/******************************************************* + * GRBM Enums + *******************************************************/ + +/* + * GRBM_PERF_SEL enum + */ + +typedef enum GRBM_PERF_SEL { +GRBM_PERF_SEL_COUNT = 0x00000000, +GRBM_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, +GRBM_PERF_SEL_CP_BUSY = 0x00000003, +GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, +GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, +GRBM_PERF_SEL_CB_BUSY = 0x00000006, +GRBM_PERF_SEL_DB_BUSY = 0x00000007, +GRBM_PERF_SEL_PA_BUSY = 0x00000008, +GRBM_PERF_SEL_SC_BUSY = 0x00000009, +GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, +GRBM_PERF_SEL_SX_BUSY = 0x0000000c, +GRBM_PERF_SEL_TA_BUSY = 0x0000000d, +GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, +GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, +GRBM_PERF_SEL_GDS_BUSY = 0x00000019, +GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, +GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, +GRBM_PERF_SEL_TCP_BUSY = 0x0000001c, +GRBM_PERF_SEL_CPG_BUSY = 0x0000001d, +GRBM_PERF_SEL_CPC_BUSY = 0x0000001e, +GRBM_PERF_SEL_CPF_BUSY = 0x0000001f, +GRBM_PERF_SEL_GE_BUSY = 0x00000020, +GRBM_PERF_SEL_GE_NO_DMA_BUSY = 0x00000021, +GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022, +GRBM_PERF_SEL_EA_BUSY = 0x00000023, +GRBM_PERF_SEL_RMI_BUSY = 0x00000024, +GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025, +GRBM_PERF_SEL_UTCL1_BUSY = 0x00000027, +GRBM_PERF_SEL_GL2CC_BUSY = 0x00000028, +GRBM_PERF_SEL_SDMA_BUSY = 0x00000029, +GRBM_PERF_SEL_CH_BUSY = 0x0000002a, +GRBM_PERF_SEL_PH_BUSY = 0x0000002b, +GRBM_PERF_SEL_PMM_BUSY = 0x0000002c, +GRBM_PERF_SEL_GUS_BUSY = 0x0000002d, +GRBM_PERF_SEL_GL1CC_BUSY = 0x0000002e, +GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 0x0000002f, +GRBM_PERF_SEL_GL1H_BUSY = 0x00000030, +GRBM_PERF_SEL_PC_BUSY = 0x00000031, +} GRBM_PERF_SEL; + +/* + * GRBM_SE0_PERF_SEL enum + */ + +typedef enum GRBM_SE0_PERF_SEL { +GRBM_SE0_PERF_SEL_COUNT = 0x00000000, +GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE0_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE0_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE0_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE0_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE0_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE0_PERF_SEL; + +/* + * GRBM_SE1_PERF_SEL enum + */ + +typedef enum GRBM_SE1_PERF_SEL { +GRBM_SE1_PERF_SEL_COUNT = 0x00000000, +GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE1_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE1_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE1_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE1_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE1_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE1_PERF_SEL; + +/* + * GRBM_SE2_PERF_SEL enum + */ + +typedef enum GRBM_SE2_PERF_SEL { +GRBM_SE2_PERF_SEL_COUNT = 0x00000000, +GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE2_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE2_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE2_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE2_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE2_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE2_PERF_SEL; + +/* + * GRBM_SE3_PERF_SEL enum + */ + +typedef enum GRBM_SE3_PERF_SEL { +GRBM_SE3_PERF_SEL_COUNT = 0x00000000, +GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE3_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE3_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE3_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE3_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE3_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE3_PERF_SEL; + +/* + * GRBM_SE4_PERF_SEL enum + */ + +typedef enum GRBM_SE4_PERF_SEL { +GRBM_SE4_PERF_SEL_COUNT = 0x00000000, +GRBM_SE4_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE4_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE4_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE4_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE4_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE4_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE4_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE4_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE4_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE4_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE4_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE4_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE4_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE4_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE4_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE4_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE4_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE4_PERF_SEL; + +/* + * GRBM_SE5_PERF_SEL enum + */ + +typedef enum GRBM_SE5_PERF_SEL { +GRBM_SE5_PERF_SEL_COUNT = 0x00000000, +GRBM_SE5_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE5_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE5_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE5_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE5_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE5_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE5_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE5_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE5_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE5_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE5_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE5_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE5_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE5_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE5_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE5_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE5_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE5_PERF_SEL; + +/* + * GRBM_SE6_PERF_SEL enum + */ + +typedef enum GRBM_SE6_PERF_SEL { +GRBM_SE6_PERF_SEL_COUNT = 0x00000000, +GRBM_SE6_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE6_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE6_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE6_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE6_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE6_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE6_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE6_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE6_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE6_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE6_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE6_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE6_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE6_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE6_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE6_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE6_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE6_PERF_SEL; + +/* + * GRBM_SE7_PERF_SEL enum + */ + +typedef enum GRBM_SE7_PERF_SEL { +GRBM_SE7_PERF_SEL_COUNT = 0x00000000, +GRBM_SE7_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE7_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE7_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE7_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE7_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE7_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE7_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE7_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE7_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE7_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE7_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE7_PERF_SEL_RMI_BUSY = 0x0000000f, +GRBM_SE7_PERF_SEL_UTCL1_BUSY = 0x00000010, +GRBM_SE7_PERF_SEL_TCP_BUSY = 0x00000011, +GRBM_SE7_PERF_SEL_GL1CC_BUSY = 0x00000012, +GRBM_SE7_PERF_SEL_GL1H_BUSY = 0x00000013, +GRBM_SE7_PERF_SEL_PC_BUSY = 0x00000014, +} GRBM_SE7_PERF_SEL; + +/* + * PIPE_COMPAT_LEVEL enum + */ + +typedef enum PIPE_COMPAT_LEVEL { +GEN_ZERO = 0x00000000, +GEN_ONE = 0x00000001, +GEN_TWO = 0x00000002, +GEN_RESERVED = 0x00000003, +} PIPE_COMPAT_LEVEL; + +/******************************************************* + * CP Enums + *******************************************************/ + +/* + * CPC_LATENCY_STATS_SEL enum + */ + +typedef enum CPC_LATENCY_STATS_SEL { +CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, +CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, +CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, +CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, +CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, +CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, +CPC_LATENCY_STATS_SEL_INVAL_MAX = 0x00000006, +CPC_LATENCY_STATS_SEL_INVAL_MIN = 0x00000007, +CPC_LATENCY_STATS_SEL_INVAL_LAST = 0x00000008, +} CPC_LATENCY_STATS_SEL; + +/* + * CPC_PERFCOUNT_SEL enum + */ + +typedef enum CPC_PERFCOUNT_SEL { +CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 0x00000009, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 0x0000000a, +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 0x00000011, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 0x00000012, +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016, +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017, +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018, +CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019, +CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a, +CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b, +CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c, +CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d, +CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e, +CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f, +CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020, +CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021, +CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022, +CPC_PERF_SEL_CPC_GCRIU_BUSY = 0x00000023, +CPC_PERF_SEL_CPC_GCRIU_IDLE = 0x00000024, +CPC_PERF_SEL_CPC_GCRIU_STALL = 0x00000025, +CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000026, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028, +CPC_PERF_SEL_CPC_UTCL2IU_XACK = 0x00000029, +CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 0x0000002a, +CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 0x0000002b, +CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 0x0000002c, +CPC_PERF_SEL_MES_THREAD0 = 0x0000002d, +CPC_PERF_SEL_MES_THREAD1 = 0x0000002e, +} CPC_PERFCOUNT_SEL; + +/* + * CPF_LATENCY_STATS_SEL enum + */ + +typedef enum CPF_LATENCY_STATS_SEL { +CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, +CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, +CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, +CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, +CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, +CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, +CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006, +CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007, +CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008, +CPF_LATENCY_STATS_SEL_INVAL_MAX = 0x00000009, +CPF_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000a, +CPF_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000b, +} CPF_LATENCY_STATS_SEL; + +/* + * CPF_PERFCOUNTWINDOW_SEL enum + */ + +typedef enum CPF_PERFCOUNTWINDOW_SEL { +CPF_PERFWINDOW_SEL_CSF = 0x00000000, +CPF_PERFWINDOW_SEL_HQD1 = 0x00000001, +CPF_PERFWINDOW_SEL_HQD2 = 0x00000002, +CPF_PERFWINDOW_SEL_RDMA = 0x00000003, +CPF_PERFWINDOW_SEL_RWPP = 0x00000004, +} CPF_PERFCOUNTWINDOW_SEL; + +/* + * CPF_PERFCOUNT_SEL enum + */ + +typedef enum CPF_PERFCOUNT_SEL { +CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 0x00000007, +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, +CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, +CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x0000000f, +CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000010, +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011, +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012, +CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013, +CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014, +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015, +CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000016, +CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000017, +CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000018, +CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000019, +CPF_PERF_SEL_CPF_STAT_STALL = 0x0000001a, +CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001b, +CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001c, +CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001d, +CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001e, +CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001f, +CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x00000020, +CPF_PERF_SEL_CPF_GCRIU_BUSY = 0x00000021, +CPF_PERF_SEL_CPF_GCRIU_IDLE = 0x00000022, +CPF_PERF_SEL_CPF_GCRIU_STALL = 0x00000023, +CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000024, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 0x00000025, +CPF_PERF_SEL_CPF_UTCL2IU_XACK = 0x00000026, +CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 0x00000027, +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 0x00000028, +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 0x00000029, +CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 0x0000002a, +CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 0x0000002b, +} CPF_PERFCOUNT_SEL; + +/* + * CPF_SCRATCH_REG_ATOMIC_OP enum + */ + +typedef enum CPF_SCRATCH_REG_ATOMIC_OP { +CPF_SCRATCH_REG_ATOMIC_ADD = 0x00000000, +CPF_SCRATCH_REG_ATOMIC_SUB = 0x00000001, +CPF_SCRATCH_REG_ATOMIC_OR = 0x00000002, +CPF_SCRATCH_REG_ATOMIC_AND = 0x00000003, +CPF_SCRATCH_REG_ATOMIC_NOT = 0x00000004, +CPF_SCRATCH_REG_ATOMIC_MIN = 0x00000005, +CPF_SCRATCH_REG_ATOMIC_MAX = 0x00000006, +CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 0x00000007, +} CPF_SCRATCH_REG_ATOMIC_OP; + +/* + * CPG_LATENCY_STATS_SEL enum + */ + +typedef enum CPG_LATENCY_STATS_SEL { +CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, +CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, +CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, +CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, +CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, +CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, +CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006, +CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007, +CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008, +CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009, +CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a, +CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b, +CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000c, +CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x0000000d, +CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x0000000e, +CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000f, +CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x00000010, +CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x00000011, +} CPG_LATENCY_STATS_SEL; + +/* + * CPG_PERFCOUNTWINDOW_SEL enum + */ + +typedef enum CPG_PERFCOUNTWINDOW_SEL { +CPG_PERFWINDOW_SEL_PFP = 0x00000000, +CPG_PERFWINDOW_SEL_ME = 0x00000001, +CPG_PERFWINDOW_SEL_CE = 0x00000002, +CPG_PERFWINDOW_SEL_MES = 0x00000003, +CPG_PERFWINDOW_SEL_MEC1 = 0x00000004, +CPG_PERFWINDOW_SEL_MEC2 = 0x00000005, +CPG_PERFWINDOW_SEL_DFY = 0x00000006, +CPG_PERFWINDOW_SEL_DMA = 0x00000007, +CPG_PERFWINDOW_SEL_SHADOW = 0x00000008, +CPG_PERFWINDOW_SEL_RB = 0x00000009, +CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a, +CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b, +CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c, +CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d, +CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e, +CPG_PERFWINDOW_SEL_PQ3 = 0x0000000f, +CPG_PERFWINDOW_SEL_MEMWR = 0x00000010, +CPG_PERFWINDOW_SEL_MEMRD = 0x00000011, +CPG_PERFWINDOW_SEL_VGT0 = 0x00000012, +CPG_PERFWINDOW_SEL_VGT1 = 0x00000013, +CPG_PERFWINDOW_SEL_APPEND = 0x00000014, +CPG_PERFWINDOW_SEL_QURD = 0x00000015, +CPG_PERFWINDOW_SEL_DDID = 0x00000016, +CPG_PERFWINDOW_SEL_SR = 0x00000017, +CPG_PERFWINDOW_SEL_QU_EOP = 0x00000018, +CPG_PERFWINDOW_SEL_QU_STRM = 0x00000019, +CPG_PERFWINDOW_SEL_QU_PIPE = 0x0000001a, +CPG_PERFWINDOW_SEL_RESERVED1 = 0x0000001b, +CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001c, +CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001d, +CPG_PERFWINDOW_SEL_CPG_IC = 0x0000001e, +} CPG_PERFCOUNTWINDOW_SEL; + +/* + * CPG_PERFCOUNT_SEL enum + */ + +typedef enum CPG_PERFCOUNT_SEL { +CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, +CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, +CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, +CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, +CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000022, +CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000023, +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e, +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f, +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030, +CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031, +CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000032, +CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000033, +CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000034, +CPG_PERF_SEL_CPG_STAT_STALL = 0x00000035, +CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000036, +CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000037, +CPG_PERF_SEL_CPG_TCIU_STALL = 0x00000038, +CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000039, +CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x0000003a, +CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003b, +CPG_PERF_SEL_CPG_GCRIU_BUSY = 0x0000003c, +CPG_PERF_SEL_CPG_GCRIU_IDLE = 0x0000003d, +CPG_PERF_SEL_CPG_GCRIU_STALL = 0x0000003e, +CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x0000003f, +CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 0x00000040, +CPG_PERF_SEL_CPG_UTCL2IU_XACK = 0x00000041, +CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 0x00000042, +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043, +CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 0x00000044, +CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 0x00000045, +CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 0x00000046, +CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 0x00000047, +CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 0x00000048, +CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 0x00000049, +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 0x0000004a, +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 0x0000004b, +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 0x0000004c, +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 0x0000004d, +CPG_PERF_SEL_DMA_BUSY = 0x0000004e, +CPG_PERF_SEL_DMA_STARVED = 0x0000004f, +CPG_PERF_SEL_DMA_STALLED = 0x00000050, +CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 0x00000051, +CPG_PERF_SEL_PFP_PWS_STALLED0 = 0x00000052, +CPG_PERF_SEL_ME_PWS_STALLED0 = 0x00000053, +CPG_PERF_SEL_PFP_PWS_STALLED1 = 0x00000054, +CPG_PERF_SEL_ME_PWS_STALLED1 = 0x00000055, +} CPG_PERFCOUNT_SEL; + +/* + * CP_ALPHA_TAG_RAM_SEL enum + */ + +typedef enum CP_ALPHA_TAG_RAM_SEL { +CPG_TAG_RAM = 0x00000000, +CPC_TAG_RAM = 0x00000001, +CPF_TAG_RAM = 0x00000002, +RSV_TAG_RAM = 0x00000003, +} CP_ALPHA_TAG_RAM_SEL; + +/* + * CP_DDID_CNTL_MODE enum + */ + +typedef enum CP_DDID_CNTL_MODE { +STALL = 0x00000000, +OVERRUN = 0x00000001, +} CP_DDID_CNTL_MODE; + +/* + * CP_DDID_CNTL_SIZE enum + */ + +typedef enum CP_DDID_CNTL_SIZE { +SIZE_8K = 0x00000000, +SIZE_16K = 0x00000001, +} CP_DDID_CNTL_SIZE; + +/* + * CP_DDID_CNTL_VMID_SEL enum + */ + +typedef enum CP_DDID_CNTL_VMID_SEL { +DDID_VMID_PIPE = 0x00000000, +DDID_VMID_CNTL = 0x00000001, +} CP_DDID_CNTL_VMID_SEL; + +/* + * CP_ME_ID enum + */ + +typedef enum CP_ME_ID { +ME_ID0 = 0x00000000, +ME_ID1 = 0x00000001, +ME_ID2 = 0x00000002, +ME_ID3 = 0x00000003, +} CP_ME_ID; + +/* + * CP_PERFMON_ENABLE_MODE enum + */ + +typedef enum CP_PERFMON_ENABLE_MODE { +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, +} CP_PERFMON_ENABLE_MODE; + +/* + * CP_PERFMON_STATE enum + */ + +typedef enum CP_PERFMON_STATE { +CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, +CP_PERFMON_STATE_START_COUNTING = 0x00000001, +CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, +CP_PERFMON_STATE_RESERVED_3 = 0x00000003, +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, +} CP_PERFMON_STATE; + +/* + * CP_PIPE_ID enum + */ + +typedef enum CP_PIPE_ID { +PIPE_ID0 = 0x00000000, +PIPE_ID1 = 0x00000001, +PIPE_ID2 = 0x00000002, +PIPE_ID3 = 0x00000003, +} CP_PIPE_ID; + +/* + * CP_RING_ID enum + */ + +typedef enum CP_RING_ID { +RINGID0 = 0x00000000, +RINGID1 = 0x00000001, +RINGID2 = 0x00000002, +RINGID3 = 0x00000003, +} CP_RING_ID; + +/* + * SPM_PERFMON_STATE enum + */ + +typedef enum SPM_PERFMON_STATE { +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, +STRM_PERFMON_STATE_START_COUNTING = 0x00000001, +STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, +STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, +} SPM_PERFMON_STATE; + +/* + * SEM_RESPONSE value + */ + +#define SEM_ECC_ERROR 0x00000000 +#define SEM_TRANS_ERROR 0x00000001 +#define SEM_RESP_FAILED 0x00000002 +#define SEM_RESP_PASSED 0x00000003 + +/* + * IQ_RETRY_TYPE value + */ + +#define IQ_QUEUE_SLEEP 0x00000000 +#define IQ_OFFLOAD_RETRY 0x00000001 +#define IQ_SCH_WAVE_MSG 0x00000002 +#define IQ_SEM_REARM 0x00000003 +#define IQ_DEQUEUE_RETRY 0x00000004 + +/* + * IQ_INTR_TYPE value + */ + +#define IQ_INTR_TYPE_PQ 0x00000000 +#define IQ_INTR_TYPE_IB 0x00000001 +#define IQ_INTR_TYPE_MQD 0x00000002 + +/* + * VMID_SIZE value + */ + +#define VMID_SZ 0x00000004 + +/* + * SRCID_SECURE value + */ + +#define SRCID_RLC 0x00000000 +#define SRCID_RLCV 0x00000006 +#define SRCID_SECURE_CP 0x00000007 +#define SRCID_NONSECURE_CP 0x00000001 +#define SRCID_SECURE_CP_RCIU 0x00000007 +#define SRCID_NONSECURE_CP_RCIU 0x00000001 + +/* + * CONFIG_SPACE value + */ + +#define CONFIG_SPACE_START 0x00002000 +#define CONFIG_SPACE_END 0x00009fff + +/* + * CONFIG_SPACE1 value + */ + +#define CONFIG_SPACE1_START 0x00002000 +#define CONFIG_SPACE1_END 0x00002bff + +/* + * CONFIG_SPACE2 value + */ + +#define CONFIG_SPACE2_START 0x00003000 +#define CONFIG_SPACE2_END 0x00009fff + +/* + * UCONFIG_SPACE value + */ + +#define UCONFIG_SPACE_START 0x0000c000 +#define UCONFIG_SPACE_END 0x0000ffff + +/* + * PERSISTENT_SPACE value + */ + +#define PERSISTENT_SPACE_START 0x00002c00 +#define PERSISTENT_SPACE_END 0x00002fff + +/* + * CONTEXT_SPACE value + */ + +#define CONTEXT_SPACE_START 0x0000a000 +#define CONTEXT_SPACE_END 0x0000a3ff + +/******************************************************* + * SX Enums + *******************************************************/ + +/* + * SX_BLEND_OPT enum + */ + +typedef enum SX_BLEND_OPT { +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, +} SX_BLEND_OPT; + +/* + * SX_DOWNCONVERT_FORMAT enum + */ + +typedef enum SX_DOWNCONVERT_FORMAT { +SX_RT_EXPORT_NO_CONVERSION = 0x00000000, +SX_RT_EXPORT_32_R = 0x00000001, +SX_RT_EXPORT_32_A = 0x00000002, +SX_RT_EXPORT_10_11_11 = 0x00000003, +SX_RT_EXPORT_2_10_10_10 = 0x00000004, +SX_RT_EXPORT_8_8_8_8 = 0x00000005, +SX_RT_EXPORT_5_6_5 = 0x00000006, +SX_RT_EXPORT_1_5_5_5 = 0x00000007, +SX_RT_EXPORT_4_4_4_4 = 0x00000008, +SX_RT_EXPORT_16_16_GR = 0x00000009, +SX_RT_EXPORT_16_16_AR = 0x0000000a, +SX_RT_EXPORT_9_9_9_E5 = 0x0000000b, +SX_RT_EXPORT_2_10_10_10_7E3 = 0x0000000c, +SX_RT_EXPORT_2_10_10_10_6E4 = 0x0000000d, +} SX_DOWNCONVERT_FORMAT; + +/* + * SX_OPT_COMB_FCN enum + */ + +typedef enum SX_OPT_COMB_FCN { +OPT_COMB_NONE = 0x00000000, +OPT_COMB_ADD = 0x00000001, +OPT_COMB_SUBTRACT = 0x00000002, +OPT_COMB_MIN = 0x00000003, +OPT_COMB_MAX = 0x00000004, +OPT_COMB_REVSUBTRACT = 0x00000005, +OPT_COMB_BLEND_DISABLED = 0x00000006, +OPT_COMB_SAFE_ADD = 0x00000007, +} SX_OPT_COMB_FCN; + +/* + * SX_PERFCOUNTER_VALS enum + */ + +typedef enum SX_PERFCOUNTER_VALS { +SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000, +SX_PERF_SEL_PA_REQ = 0x00000001, +SX_PERF_SEL_PA_POS = 0x00000002, +SX_PERF_SEL_CLOCK = 0x00000003, +SX_PERF_SEL_GATE_EN1 = 0x00000004, +SX_PERF_SEL_GATE_EN2 = 0x00000005, +SX_PERF_SEL_GATE_EN3 = 0x00000006, +SX_PERF_SEL_GATE_EN4 = 0x00000007, +SX_PERF_SEL_SH_POS_STARVE = 0x00000008, +SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009, +SX_PERF_SEL_SH_POS_STALL = 0x0000000a, +SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b, +SX_PERF_SEL_DB0_PIXELS = 0x0000000c, +SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d, +SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e, +SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f, +SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010, +SX_PERF_SEL_DB1_PIXELS = 0x00000011, +SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012, +SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013, +SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014, +SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015, +SX_PERF_SEL_DB2_PIXELS = 0x00000016, +SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017, +SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018, +SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019, +SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a, +SX_PERF_SEL_DB3_PIXELS = 0x0000001b, +SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c, +SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d, +SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e, +SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f, +SX_PERF_SEL_COL_BUSY = 0x00000020, +SX_PERF_SEL_POS_BUSY = 0x00000021, +SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 0x00000022, +SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 0x00000023, +SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 0x00000024, +SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 0x00000025, +SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 0x00000026, +SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 0x00000027, +SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 0x00000028, +SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 0x00000029, +SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 0x0000002a, +SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 0x0000002b, +SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 0x0000002c, +SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 0x0000002d, +SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 0x0000002e, +SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 0x0000002f, +SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 0x00000030, +SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 0x00000031, +SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 0x00000032, +SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 0x00000033, +SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 0x00000034, +SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 0x00000035, +SX_PERF_SEL_PA_REQ_LATENCY = 0x00000036, +SX_PERF_SEL_POS_SCBD_STALL = 0x00000037, +SX_PERF_SEL_CLOCK_DROP_STALL = 0x00000038, +SX_PERF_SEL_GATE_EN5 = 0x00000039, +SX_PERF_SEL_GATE_EN6 = 0x0000003a, +SX_PERF_SEL_DB0_SIZE = 0x0000003b, +SX_PERF_SEL_DB1_SIZE = 0x0000003c, +SX_PERF_SEL_DB2_SIZE = 0x0000003d, +SX_PERF_SEL_DB3_SIZE = 0x0000003e, +SX_PERF_SEL_IDX_STALL_CYCLES = 0x0000003f, +SX_PERF_SEL_IDX_IDLE_CYCLES = 0x00000040, +SX_PERF_SEL_IDX_REQ = 0x00000041, +SX_PERF_SEL_IDX_RET = 0x00000042, +SX_PERF_SEL_IDX_REQ_LATENCY = 0x00000043, +SX_PERF_SEL_IDX_SCBD_STALL = 0x00000044, +SX_PERF_SEL_GATE_EN7 = 0x00000045, +SX_PERF_SEL_GATE_EN8 = 0x00000046, +SX_PERF_SEL_SH_IDX_STARVE = 0x00000047, +SX_PERF_SEL_IDX_BUSY = 0x00000048, +SX_PERF_SEL_PA_POS_BANK_CONF = 0x00000049, +SX_PERF_SEL_DB0_END_OF_WAVE = 0x0000004a, +SX_PERF_SEL_DB0_4X2_DISCARD = 0x0000004b, +SX_PERF_SEL_DB1_END_OF_WAVE = 0x0000004c, +SX_PERF_SEL_DB1_4X2_DISCARD = 0x0000004d, +SX_PERF_SEL_DB2_END_OF_WAVE = 0x0000004e, +SX_PERF_SEL_DB2_4X2_DISCARD = 0x0000004f, +SX_PERF_SEL_DB3_END_OF_WAVE = 0x00000050, +SX_PERF_SEL_DB3_4X2_DISCARD = 0x00000051, +} SX_PERFCOUNTER_VALS; + +/******************************************************* + * DB Enums + *******************************************************/ + +/* + * CompareFrag enum + */ + +typedef enum CompareFrag { +FRAG_NEVER = 0x00000000, +FRAG_LESS = 0x00000001, +FRAG_EQUAL = 0x00000002, +FRAG_LEQUAL = 0x00000003, +FRAG_GREATER = 0x00000004, +FRAG_NOTEQUAL = 0x00000005, +FRAG_GEQUAL = 0x00000006, +FRAG_ALWAYS = 0x00000007, +} CompareFrag; + +/* + * ConservativeZExport enum + */ + +typedef enum ConservativeZExport { +EXPORT_ANY_Z = 0x00000000, +EXPORT_LESS_THAN_Z = 0x00000001, +EXPORT_GREATER_THAN_Z = 0x00000002, +EXPORT_RESERVED = 0x00000003, +} ConservativeZExport; + +/* + * DFSMFlushEvents enum + */ + +typedef enum DFSMFlushEvents { +DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000, +DB_FLUSH_AND_INV_DB_META = 0x00000001, +DB_CACHE_FLUSH = 0x00000002, +DB_CACHE_FLUSH_TS = 0x00000003, +DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004, +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005, +DB_VPORT_CHANGED_EVENT = 0x00000006, +DB_CONTEXT_DONE_EVENT = 0x00000007, +DB_BREAK_BATCH_EVENT = 0x00000008, +DB_INVOKE_CHANGE_EVENT = 0x00000009, +DB_CONTEXT_SUSPEND_EVENT = 0x0000000a, +} DFSMFlushEvents; + +/* + * DbMemArbWatermarks enum + */ + +typedef enum DbMemArbWatermarks { +TRANSFERRED_64_BYTES = 0x00000000, +TRANSFERRED_128_BYTES = 0x00000001, +TRANSFERRED_256_BYTES = 0x00000002, +TRANSFERRED_512_BYTES = 0x00000003, +TRANSFERRED_1024_BYTES = 0x00000004, +TRANSFERRED_2048_BYTES = 0x00000005, +TRANSFERRED_4096_BYTES = 0x00000006, +TRANSFERRED_8192_BYTES = 0x00000007, +} DbMemArbWatermarks; + +/* + * DbPRTFaultBehavior enum + */ + +typedef enum DbPRTFaultBehavior { +FAULT_ZERO = 0x00000000, +FAULT_ONE = 0x00000001, +FAULT_FAIL = 0x00000002, +FAULT_PASS = 0x00000003, +} DbPRTFaultBehavior; + +/* + * DbPSLControl enum + */ + +typedef enum DbPSLControl { +PSLC_AUTO = 0x00000000, +PSLC_ON_HANG_ONLY = 0x00000001, +PSLC_ASAP = 0x00000002, +PSLC_COUNTDOWN = 0x00000003, +} DbPSLControl; + +/* + * ForceControl enum + */ + +typedef enum ForceControl { +FORCE_OFF = 0x00000000, +FORCE_ENABLE = 0x00000001, +FORCE_DISABLE = 0x00000002, +FORCE_RESERVED = 0x00000003, +} ForceControl; + +/* + * OreoMode enum + */ + +typedef enum OreoMode { +OMODE_BLEND = 0x00000000, +OMODE_O_THEN_B = 0x00000001, +OMODE_P_THEN_O_THEN_B = 0x00000002, +OMODE_RESERVED_3 = 0x00000003, +} OreoMode; + +/* + * PerfCounter_Vals enum + */ + +typedef enum PerfCounter_Vals { +DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, +DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, +DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, +DB_PERF_SEL_SC_DB_tile_events = 0x00000003, +DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, +DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, +DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, +DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, +DB_PERF_SEL_hiz_tile_culled = 0x00000008, +DB_PERF_SEL_his_tile_culled = 0x00000009, +DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, +DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, +DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, +DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, +DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, +DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, +DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, +DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, +DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, +DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, +DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, +DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, +DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, +DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, +DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, +DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, +DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, +DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, +DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, +DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020, +DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021, +DB_PERF_SEL_DB_CB_tile_sends = 0x00000022, +DB_PERF_SEL_DB_CB_tile_busy = 0x00000023, +DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024, +DB_PERF_SEL_SX_DB_quad_sends = 0x00000025, +DB_PERF_SEL_SX_DB_quad_busy = 0x00000026, +DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027, +DB_PERF_SEL_SX_DB_quad_quads = 0x00000028, +DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029, +DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a, +DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b, +DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c, +DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d, +DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e, +DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f, +DB_PERF_SEL_tile_rd_sends = 0x00000030, +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031, +DB_PERF_SEL_quad_rd_sends = 0x00000032, +DB_PERF_SEL_quad_rd_busy = 0x00000033, +DB_PERF_SEL_quad_rd_mi_stall = 0x00000034, +DB_PERF_SEL_quad_rd_rw_collision = 0x00000035, +DB_PERF_SEL_quad_rd_tag_stall = 0x00000036, +DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037, +DB_PERF_SEL_quad_rd_panic = 0x00000038, +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039, +DB_PERF_SEL_quad_rdret_sends = 0x0000003a, +DB_PERF_SEL_quad_rdret_busy = 0x0000003b, +DB_PERF_SEL_tile_wr_sends = 0x0000003c, +DB_PERF_SEL_tile_wr_acks = 0x0000003d, +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e, +DB_PERF_SEL_quad_wr_sends = 0x0000003f, +DB_PERF_SEL_quad_wr_busy = 0x00000040, +DB_PERF_SEL_quad_wr_mi_stall = 0x00000041, +DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042, +DB_PERF_SEL_quad_wr_acks = 0x00000043, +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044, +DB_PERF_SEL_Tile_Cache_misses = 0x00000045, +DB_PERF_SEL_Tile_Cache_hits = 0x00000046, +DB_PERF_SEL_Tile_Cache_flushes = 0x00000047, +DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048, +DB_PERF_SEL_Tile_Cache_starves = 0x00000049, +DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a, +DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b, +DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c, +DB_PERF_SEL_tcp_preloader_reads = 0x0000004d, +DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e, +DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f, +DB_PERF_SEL_tcp_preloader_flushes = 0x00000050, +DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051, +DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052, +DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053, +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054, +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055, +DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056, +DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057, +DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058, +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059, +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a, +DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b, +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c, +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d, +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e, +DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f, +DB_PERF_SEL_Stencil_Cache_hits = 0x00000060, +DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061, +DB_PERF_SEL_Stencil_Cache_starves = 0x00000062, +DB_PERF_SEL_Stencil_Cache_frees = 0x00000063, +DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064, +DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065, +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066, +DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067, +DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068, +DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069, +DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a, +DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b, +DB_PERF_SEL_Z_Cache_frees = 0x0000006c, +DB_PERF_SEL_Plane_Cache_misses = 0x0000006d, +DB_PERF_SEL_Plane_Cache_hits = 0x0000006e, +DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f, +DB_PERF_SEL_Plane_Cache_starves = 0x00000070, +DB_PERF_SEL_Plane_Cache_frees = 0x00000071, +DB_PERF_SEL_flush_expanded_stencil = 0x00000072, +DB_PERF_SEL_flush_compressed_stencil = 0x00000073, +DB_PERF_SEL_flush_single_stencil = 0x00000074, +DB_PERF_SEL_planes_flushed = 0x00000075, +DB_PERF_SEL_flush_1plane = 0x00000076, +DB_PERF_SEL_flush_2plane = 0x00000077, +DB_PERF_SEL_flush_3plane = 0x00000078, +DB_PERF_SEL_flush_4plane = 0x00000079, +DB_PERF_SEL_flush_5plane = 0x0000007a, +DB_PERF_SEL_flush_6plane = 0x0000007b, +DB_PERF_SEL_flush_7plane = 0x0000007c, +DB_PERF_SEL_flush_8plane = 0x0000007d, +DB_PERF_SEL_flush_9plane = 0x0000007e, +DB_PERF_SEL_flush_10plane = 0x0000007f, +DB_PERF_SEL_flush_11plane = 0x00000080, +DB_PERF_SEL_flush_12plane = 0x00000081, +DB_PERF_SEL_flush_13plane = 0x00000082, +DB_PERF_SEL_flush_14plane = 0x00000083, +DB_PERF_SEL_flush_15plane = 0x00000084, +DB_PERF_SEL_flush_16plane = 0x00000085, +DB_PERF_SEL_flush_expanded_z = 0x00000086, +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087, +DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088, +DB_PERF_SEL_dk_tile_sends = 0x00000089, +DB_PERF_SEL_dk_tile_busy = 0x0000008a, +DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b, +DB_PERF_SEL_dk_tile_stalls = 0x0000008c, +DB_PERF_SEL_dk_squad_sends = 0x0000008d, +DB_PERF_SEL_dk_squad_busy = 0x0000008e, +DB_PERF_SEL_dk_squad_stalls = 0x0000008f, +DB_PERF_SEL_Op_Pipe_Busy = 0x00000090, +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091, +DB_PERF_SEL_qc_busy = 0x00000092, +DB_PERF_SEL_qc_xfc = 0x00000093, +DB_PERF_SEL_qc_conflicts = 0x00000094, +DB_PERF_SEL_qc_full_stall = 0x00000095, +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096, +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097, +DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098, +DB_PERF_SEL_tl_busy = 0x00000099, +DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a, +DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b, +DB_PERF_SEL_tl_stencil_stall = 0x0000009c, +DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d, +DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e, +DB_PERF_SEL_tl_events = 0x0000009f, +DB_PERF_SEL_tl_summarize_squads = 0x000000a0, +DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1, +DB_PERF_SEL_tl_expand_squads = 0x000000a2, +DB_PERF_SEL_tl_preZ_squads = 0x000000a3, +DB_PERF_SEL_tl_postZ_squads = 0x000000a4, +DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5, +DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6, +DB_PERF_SEL_tl_tile_ops = 0x000000a7, +DB_PERF_SEL_tl_in_xfc = 0x000000a8, +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9, +DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa, +DB_PERF_SEL_tl_out_xfc = 0x000000ab, +DB_PERF_SEL_tl_out_squads = 0x000000ac, +DB_PERF_SEL_zf_plane_multicycle = 0x000000ad, +DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae, +DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af, +DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0, +DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1, +DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2, +DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3, +DB_PERF_SEL_ts_tc_update_stall = 0x000000b4, +DB_PERF_SEL_sc_kick_start = 0x000000b5, +DB_PERF_SEL_sc_kick_end = 0x000000b6, +DB_PERF_SEL_clock_reg_active = 0x000000b7, +DB_PERF_SEL_clock_main_active = 0x000000b8, +DB_PERF_SEL_clock_mem_export_active = 0x000000b9, +DB_PERF_SEL_esr_ps_out_busy = 0x000000ba, +DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb, +DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc, +DB_PERF_SEL_etr_out_send = 0x000000bd, +DB_PERF_SEL_etr_out_busy = 0x000000be, +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf, +DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0, +DB_PERF_SEL_etr_out_esr_stall = 0x000000c1, +DB_PERF_SEL_esr_ps_vic_busy = 0x000000c2, +DB_PERF_SEL_esr_ps_vic_stall = 0x000000c3, +DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4, +DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5, +DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6, +DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7, +DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8, +DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9, +DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca, +DB_PERF_SEL_postzl_se_busy = 0x000000cb, +DB_PERF_SEL_postzl_se_stall = 0x000000cc, +DB_PERF_SEL_postzl_partial_launch = 0x000000cd, +DB_PERF_SEL_postzl_full_launch = 0x000000ce, +DB_PERF_SEL_postzl_partial_waiting = 0x000000cf, +DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0, +DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1, +DB_PERF_SEL_prezl_tile_mem_stall = 0x000000d2, +DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3, +DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4, +DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5, +DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6, +DB_PERF_SEL_mi_rdreq_busy = 0x000000d7, +DB_PERF_SEL_mi_rdreq_stall = 0x000000d8, +DB_PERF_SEL_mi_wrreq_busy = 0x000000d9, +DB_PERF_SEL_mi_wrreq_stall = 0x000000da, +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db, +DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc, +DB_PERF_SEL_prezl_src_in_sends = 0x000000dd, +DB_PERF_SEL_prezl_src_in_stall = 0x000000de, +DB_PERF_SEL_prezl_src_in_squads = 0x000000df, +DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0, +DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1, +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2, +DB_PERF_SEL_prezl_src_out_stall = 0x000000e3, +DB_PERF_SEL_postzl_src_in_sends = 0x000000e4, +DB_PERF_SEL_postzl_src_in_stall = 0x000000e5, +DB_PERF_SEL_postzl_src_in_squads = 0x000000e6, +DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7, +DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8, +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9, +DB_PERF_SEL_postzl_src_out_stall = 0x000000ea, +DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb, +DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec, +DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed, +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee, +DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef, +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0, +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1, +DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2, +DB_PERF_SEL_depth_bounds_tile_culled = 0x000000f3, +DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4, +DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5, +DB_PERF_SEL_flush_compressed = 0x000000f6, +DB_PERF_SEL_flush_plane_le4 = 0x000000f7, +DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8, +DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9, +DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa, +DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb, +DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc, +DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd, +DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe, +DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff, +DB_PERF_SEL_di_dt_stall = 0x00000100, +Spare_257 = 0x00000101, +DB_PERF_SEL_DB_SC_s_tile_rate = 0x00000102, +DB_PERF_SEL_DB_SC_c_tile_rate = 0x00000103, +DB_PERF_SEL_DB_SC_z_tile_rate = 0x00000104, +DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000105, +DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000106, +DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000107, +DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000108, +DB_PERF_SEL_CB_DB_rdreq_sends = 0x00000109, +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010a, +DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010b, +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010c, +DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010d, +DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010e, +DB_PERF_SEL_DB_CB_wrret_ack = 0x0000010f, +DB_PERF_SEL_DB_CB_wrret_nack = 0x00000110, +DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x00000111, +DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x00000112, +DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000113, +DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000114, +DB_PERF_SEL_unmapped_z_tile_culled = 0x00000115, +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000116, +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000117, +DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 0x00000118, +DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 0x00000119, +DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 0x0000011a, +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 0x0000011b, +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 0x0000011c, +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 0x0000011d, +DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 0x0000011e, +DB_PERF_SEL_DB_CB_context_dones = 0x0000011f, +DB_PERF_SEL_DB_CB_eop_dones = 0x00000120, +DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x00000121, +DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x00000122, +DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000123, +DB_PERF_SEL_SC_DB_tile_backface = 0x00000124, +DB_PERF_SEL_SC_DB_quad_quads = 0x00000125, +DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000126, +DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000127, +DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000128, +DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000129, +DB_PERF_SEL_DB_SC_quad_double_quad = 0x0000012a, +DB_PERF_SEL_SX_DB_quad_export_quads = 0x0000012b, +DB_PERF_SEL_SX_DB_quad_double_format = 0x0000012c, +DB_PERF_SEL_SX_DB_quad_fast_format = 0x0000012d, +DB_PERF_SEL_SX_DB_quad_slow_format = 0x0000012e, +DB_PERF_SEL_quad_rd_sends_unc = 0x0000012f, +DB_PERF_SEL_quad_rd_mi_stall_unc = 0x00000130, +DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 0x00000131, +DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 0x00000132, +DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 0x00000133, +DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 0x00000134, +DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 0x00000135, +DB_PERF_SEL_noz_waiting_for_postz_done = 0x00000136, +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 0x00000137, +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 0x00000138, +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 0x00000139, +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 0x0000013a, +DB_PERF_SEL_RMI_rd_tile_32byte_req = 0x0000013b, +DB_PERF_SEL_RMI_rd_z_32byte_req = 0x0000013c, +DB_PERF_SEL_RMI_rd_s_32byte_req = 0x0000013d, +DB_PERF_SEL_RMI_wr_tile_32byte_req = 0x0000013e, +DB_PERF_SEL_RMI_wr_z_32byte_req = 0x0000013f, +DB_PERF_SEL_RMI_wr_s_32byte_req = 0x00000140, +DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 0x00000141, +DB_PERF_SEL_RMI_rd_tile_32byte_ret = 0x00000142, +DB_PERF_SEL_RMI_rd_z_32byte_ret = 0x00000143, +DB_PERF_SEL_RMI_rd_s_32byte_ret = 0x00000144, +DB_PERF_SEL_RMI_wr_tile_32byte_ack = 0x00000145, +DB_PERF_SEL_RMI_wr_z_32byte_ack = 0x00000146, +DB_PERF_SEL_RMI_wr_s_32byte_ack = 0x00000147, +DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 0x00000148, +DB_PERF_SEL_esr_vic_sqq_busy = 0x00000149, +DB_PERF_SEL_esr_vic_sqq_stall = 0x0000014a, +DB_PERF_SEL_esr_psi_vic_tile_rate = 0x0000014b, +DB_PERF_SEL_esr_vic_footprint_match_2x2 = 0x0000014c, +DB_PERF_SEL_esr_vic_footprint_match_2x1 = 0x0000014d, +DB_PERF_SEL_esr_vic_footprint_match_1x2 = 0x0000014e, +DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 0x0000014f, +DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 0x00000150, +DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 0x00000151, +DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 0x00000152, +DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 0x00000153, +DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 0x00000154, +DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 0x00000155, +DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 0x00000156, +DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 0x00000157, +DB_PERF_SEL_ts_events_pws_enable = 0x00000158, +DB_PERF_SEL_ps_events_pws_enable = 0x00000159, +DB_PERF_SEL_cs_events_pws_enable = 0x0000015a, +DB_PERF_SEL_DB_SC_quad_noz_tiles = 0x0000015b, +DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 0x0000015c, +} PerfCounter_Vals; + +/* + * PixelPipeCounterId enum + */ + +typedef enum PixelPipeCounterId { +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, +PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, +PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, +PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004, +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005, +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006, +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007, +} PixelPipeCounterId; + +/* + * PixelPipeStride enum + */ + +typedef enum PixelPipeStride { +PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, +PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, +PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, +PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, +} PixelPipeStride; + +/* + * RingCounterControl enum + */ + +typedef enum RingCounterControl { +COUNTER_RING_SPLIT = 0x00000000, +COUNTER_RING_0 = 0x00000001, +COUNTER_RING_1 = 0x00000002, +} RingCounterControl; + +/* + * StencilOp enum + */ + +typedef enum StencilOp { +STENCIL_KEEP = 0x00000000, +STENCIL_ZERO = 0x00000001, +STENCIL_ONES = 0x00000002, +STENCIL_REPLACE_TEST = 0x00000003, +STENCIL_REPLACE_OP = 0x00000004, +STENCIL_ADD_CLAMP = 0x00000005, +STENCIL_SUB_CLAMP = 0x00000006, +STENCIL_INVERT = 0x00000007, +STENCIL_ADD_WRAP = 0x00000008, +STENCIL_SUB_WRAP = 0x00000009, +STENCIL_AND = 0x0000000a, +STENCIL_OR = 0x0000000b, +STENCIL_XOR = 0x0000000c, +STENCIL_NAND = 0x0000000d, +STENCIL_NOR = 0x0000000e, +STENCIL_XNOR = 0x0000000f, +} StencilOp; + +/* + * ZLimitSumm enum + */ + +typedef enum ZLimitSumm { +FORCE_SUMM_OFF = 0x00000000, +FORCE_SUMM_MINZ = 0x00000001, +FORCE_SUMM_MAXZ = 0x00000002, +FORCE_SUMM_BOTH = 0x00000003, +} ZLimitSumm; + +/* + * ZModeForce enum + */ + +typedef enum ZModeForce { +NO_FORCE = 0x00000000, +FORCE_EARLY_Z = 0x00000001, +FORCE_LATE_Z = 0x00000002, +FORCE_RE_Z = 0x00000003, +} ZModeForce; + +/* + * ZOrder enum + */ + +typedef enum ZOrder { +LATE_Z = 0x00000000, +EARLY_Z_THEN_LATE_Z = 0x00000001, +RE_Z = 0x00000002, +EARLY_Z_THEN_RE_Z = 0x00000003, +} ZOrder; + +/* + * ZSamplePosition enum + */ + +typedef enum ZSamplePosition { +Z_SAMPLE_CENTER = 0x00000000, +Z_SAMPLE_CENTROID = 0x00000001, +} ZSamplePosition; + +/* + * ZpassControl enum + */ + +typedef enum ZpassControl { +ZPASS_DISABLE = 0x00000000, +ZPASS_SAMPLES = 0x00000001, +ZPASS_PIXELS = 0x00000002, +} ZpassControl; + +/******************************************************* + * PA Enums + *******************************************************/ + +/* + * SU_PERFCNT_SEL enum + */ + +typedef enum SU_PERFCNT_SEL { +PERF_PAPC_PASX_REQ = 0x00000000, +PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, +PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, +PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, +PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, +PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, +PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, +PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, +PERF_PAPC_PA_INPUT_PRIM = 0x00000008, +PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, +PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, +PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, +PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, +PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, +PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, +PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, +PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, +PERF_PAPC_SU_INPUT_PRIM = 0x00000031, +PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, +PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, +PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, +PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, +PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, +PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, +PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, +PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, +PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, +PERF_PAPC_PASX_REC_IDLE = 0x00000050, +PERF_PAPC_PASX_REC_BUSY = 0x00000051, +PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, +PERF_PAPC_PASX_REC_STALLED = 0x00000053, +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, +PERF_PAPC_CCGSM_IDLE = 0x00000056, +PERF_PAPC_CCGSM_BUSY = 0x00000057, +PERF_PAPC_CCGSM_STALLED = 0x00000058, +PERF_PAPC_CLPRIM_IDLE = 0x00000059, +PERF_PAPC_CLPRIM_BUSY = 0x0000005a, +PERF_PAPC_CLPRIM_STALLED = 0x0000005b, +PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, +PERF_PAPC_CLIPSM_IDLE = 0x0000005d, +PERF_PAPC_CLIPSM_BUSY = 0x0000005e, +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, +PERF_PAPC_CLIPGA_IDLE = 0x00000064, +PERF_PAPC_CLIPGA_BUSY = 0x00000065, +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, +PERF_PAPC_CLIPGA_STALLED = 0x00000067, +PERF_PAPC_CLIP_IDLE = 0x00000068, +PERF_PAPC_CLIP_BUSY = 0x00000069, +PERF_PAPC_SU_IDLE = 0x0000006a, +PERF_PAPC_SU_BUSY = 0x0000006b, +PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, +PERF_PAPC_SU_STALLED_SC = 0x0000006d, +PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, +PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, +PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, +PERF_PAPC_PASX_SE0_REQ = 0x00000072, +PERF_PAPC_PASX_SE1_REQ = 0x00000073, +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, +PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, +PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, +PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, +PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, +PERF_PAPC_SU_CULLED_PRIM = 0x00000087, +PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088, +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089, +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a, +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b, +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c, +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d, +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e, +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f, +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090, +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091, +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092, +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093, +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094, +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095, +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096, +PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097, +PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098, +PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099, +PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a, +PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b, +PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c, +PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d, +PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e, +PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f, +PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0, +PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1, +PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2, +PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3, +PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4, +PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5, +PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 0x000000a6, +PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 0x000000a7, +PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 0x000000a8, +PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000aa, +PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ab, +PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ac, +PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ad, +PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ae, +PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000af, +PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000b0, +PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b1, +PERF_PA_VERTEX_FIFO_FULL = 0x000000b3, +PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 0x000000b4, +PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 0x000000b6, +PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 0x000000b7, +PERF_PA_PIPE0_SWITCHED_GEN = 0x000000b9, +PERF_PA_PIPE1_SWITCHED_GEN = 0x000000ba, +PERF_ENGG_CSB_MACHINE_IS_STARVED = 0x000000bc, +PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x000000bd, +PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 0x000000be, +PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 0x000000bf, +PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 0x000000c0, +PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 0x000000c1, +PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 0x000000c2, +PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 0x000000c3, +PERF_ENGG_CSB_NULL_SUBGROUP = 0x000000c4, +PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 0x000000c5, +PERF_ENGG_CSB_GE_MEMORY_FULL = 0x000000c6, +PERF_ENGG_CSB_GE_MEMORY_EMPTY = 0x000000c7, +PERF_ENGG_CSB_SPI_MEMORY_FULL = 0x000000c8, +PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 0x000000c9, +PERF_ENGG_CSB_DELAY_BIN00 = 0x000000ca, +PERF_ENGG_CSB_DELAY_BIN01 = 0x000000cb, +PERF_ENGG_CSB_DELAY_BIN02 = 0x000000cc, +PERF_ENGG_CSB_DELAY_BIN03 = 0x000000cd, +PERF_ENGG_CSB_DELAY_BIN04 = 0x000000ce, +PERF_ENGG_CSB_DELAY_BIN05 = 0x000000cf, +PERF_ENGG_CSB_DELAY_BIN06 = 0x000000d0, +PERF_ENGG_CSB_DELAY_BIN07 = 0x000000d1, +PERF_ENGG_CSB_DELAY_BIN08 = 0x000000d2, +PERF_ENGG_CSB_DELAY_BIN09 = 0x000000d3, +PERF_ENGG_CSB_DELAY_BIN10 = 0x000000d4, +PERF_ENGG_CSB_DELAY_BIN11 = 0x000000d5, +PERF_ENGG_CSB_DELAY_BIN12 = 0x000000d6, +PERF_ENGG_CSB_DELAY_BIN13 = 0x000000d7, +PERF_ENGG_CSB_DELAY_BIN14 = 0x000000d8, +PERF_ENGG_CSB_DELAY_BIN15 = 0x000000d9, +PERF_ENGG_CSB_SPI_DELAY_BIN00 = 0x000000da, +PERF_ENGG_CSB_SPI_DELAY_BIN01 = 0x000000db, +PERF_ENGG_CSB_SPI_DELAY_BIN02 = 0x000000dc, +PERF_ENGG_CSB_SPI_DELAY_BIN03 = 0x000000dd, +PERF_ENGG_CSB_SPI_DELAY_BIN04 = 0x000000de, +PERF_ENGG_CSB_SPI_DELAY_BIN05 = 0x000000df, +PERF_ENGG_CSB_SPI_DELAY_BIN06 = 0x000000e0, +PERF_ENGG_CSB_SPI_DELAY_BIN07 = 0x000000e1, +PERF_ENGG_CSB_SPI_DELAY_BIN08 = 0x000000e2, +PERF_ENGG_CSB_SPI_DELAY_BIN09 = 0x000000e3, +PERF_ENGG_CSB_SPI_DELAY_BIN10 = 0x000000e4, +PERF_ENGG_INDEX_REQ_NULL_REQUEST = 0x000000e5, +PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 0x000000e6, +PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 0x000000e7, +PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 0x000000e8, +PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 0x000000e9, +PERF_ENGG_INDEX_REQ_STARVED = 0x000000ea, +PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000eb, +PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000ec, +PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x000000ed, +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 0x000000ee, +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 0x000000ef, +PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x000000f0, +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 0x000000f1, +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x000000f2, +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x000000f3, +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x000000f4, +PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 0x000000f5, +PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x000000f6, +PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x000000f7, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x000000f8, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x000000f9, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 0x000000fa, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 0x000000fb, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 0x000000fc, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x000000fd, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x000000fe, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 0x000000ff, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 0x00000100, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 0x00000101, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 0x00000102, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 0x00000103, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 0x00000104, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 0x00000105, +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 0x00000106, +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x00000107, +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x00000108, +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 0x00000109, +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x0000010a, +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x0000010b, +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x0000010c, +PERF_ENGG_POS_REQ_STARVED = 0x0000010d, +PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 0x0000010e, +PERF_ENGG_BUSY = 0x0000010f, +PERF_CLIPSM_CULL_PRIMS_CNT = 0x00000110, +PERF_PH_SEND_1_SC = 0x00000111, +PERF_PH_SEND_2_SC = 0x00000112, +PERF_PH_SEND_3_SC = 0x00000113, +PERF_PH_SEND_4_SC = 0x00000114, +PERF_OUTPUT_PRIM_1_SC = 0x00000115, +PERF_OUTPUT_PRIM_2_SC = 0x00000116, +PERF_OUTPUT_PRIM_3_SC = 0x00000117, +PERF_OUTPUT_PRIM_4_SC = 0x00000118, +} SU_PERFCNT_SEL; + +/******************************************************* + * PH Enums + *******************************************************/ + +/* + * PH_PERFCNT_SEL enum + */ + +typedef enum PH_PERFCNT_SEL { +PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0x00000000, +PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001, +PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002, +PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003, +PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 0x00000004, +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 0x00000005, +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006, +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007, +PH_PERF_SEL_SC0_ARB_BUSY = 0x00000008, +PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 0x00000009, +PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 0x0000000a, +PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 0x0000000b, +PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c, +PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 0x0000000d, +PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e, +PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 0x0000000f, +PH_PERF_SEL_SC0_SEND = 0x00000010, +PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011, +PH_PERF_SEL_SC0_CREDIT_AT_MAX = 0x00000012, +PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013, +PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000014, +PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000015, +PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000016, +PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000017, +PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 0x00000018, +PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 0x00000019, +PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 0x0000001a, +PH_PERF_SEL_SC0_PA0_FIFO_FULL = 0x0000001b, +PH_PERF_SEL_SC0_PA0_NULL_WE = 0x0000001c, +PH_PERF_SEL_SC0_PA0_EVENT_WE = 0x0000001d, +PH_PERF_SEL_SC0_PA0_FPOV_WE = 0x0000001e, +PH_PERF_SEL_SC0_PA0_LPOV_WE = 0x0000001f, +PH_PERF_SEL_SC0_PA0_EOP_WE = 0x00000020, +PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 0x00000021, +PH_PERF_SEL_SC0_PA0_EOPG_WE = 0x00000022, +PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 0x00000023, +PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 0x00000024, +PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 0x00000025, +PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 0x00000026, +PH_PERF_SEL_SC0_PA1_FIFO_FULL = 0x00000027, +PH_PERF_SEL_SC0_PA1_NULL_WE = 0x00000028, +PH_PERF_SEL_SC0_PA1_EVENT_WE = 0x00000029, +PH_PERF_SEL_SC0_PA1_FPOV_WE = 0x0000002a, +PH_PERF_SEL_SC0_PA1_LPOV_WE = 0x0000002b, +PH_PERF_SEL_SC0_PA1_EOP_WE = 0x0000002c, +PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 0x0000002d, +PH_PERF_SEL_SC0_PA1_EOPG_WE = 0x0000002e, +PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 0x0000002f, +PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 0x00000030, +PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 0x00000031, +PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 0x00000032, +PH_PERF_SEL_SC0_PA2_FIFO_FULL = 0x00000033, +PH_PERF_SEL_SC0_PA2_NULL_WE = 0x00000034, +PH_PERF_SEL_SC0_PA2_EVENT_WE = 0x00000035, +PH_PERF_SEL_SC0_PA2_FPOV_WE = 0x00000036, +PH_PERF_SEL_SC0_PA2_LPOV_WE = 0x00000037, +PH_PERF_SEL_SC0_PA2_EOP_WE = 0x00000038, +PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 0x00000039, +PH_PERF_SEL_SC0_PA2_EOPG_WE = 0x0000003a, +PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 0x0000003b, +PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 0x0000003c, +PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 0x0000003d, +PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 0x0000003e, +PH_PERF_SEL_SC0_PA3_FIFO_FULL = 0x0000003f, +PH_PERF_SEL_SC0_PA3_NULL_WE = 0x00000040, +PH_PERF_SEL_SC0_PA3_EVENT_WE = 0x00000041, +PH_PERF_SEL_SC0_PA3_FPOV_WE = 0x00000042, +PH_PERF_SEL_SC0_PA3_LPOV_WE = 0x00000043, +PH_PERF_SEL_SC0_PA3_EOP_WE = 0x00000044, +PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 0x00000045, +PH_PERF_SEL_SC0_PA3_EOPG_WE = 0x00000046, +PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 0x00000047, +PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 0x00000048, +PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 0x00000049, +PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 0x0000004a, +PH_PERF_SEL_SC0_PA4_FIFO_FULL = 0x0000004b, +PH_PERF_SEL_SC0_PA4_NULL_WE = 0x0000004c, +PH_PERF_SEL_SC0_PA4_EVENT_WE = 0x0000004d, +PH_PERF_SEL_SC0_PA4_FPOV_WE = 0x0000004e, +PH_PERF_SEL_SC0_PA4_LPOV_WE = 0x0000004f, +PH_PERF_SEL_SC0_PA4_EOP_WE = 0x00000050, +PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 0x00000051, +PH_PERF_SEL_SC0_PA4_EOPG_WE = 0x00000052, +PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 0x00000053, +PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 0x00000054, +PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 0x00000055, +PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 0x00000056, +PH_PERF_SEL_SC0_PA5_FIFO_FULL = 0x00000057, +PH_PERF_SEL_SC0_PA5_NULL_WE = 0x00000058, +PH_PERF_SEL_SC0_PA5_EVENT_WE = 0x00000059, +PH_PERF_SEL_SC0_PA5_FPOV_WE = 0x0000005a, +PH_PERF_SEL_SC0_PA5_LPOV_WE = 0x0000005b, +PH_PERF_SEL_SC0_PA5_EOP_WE = 0x0000005c, +PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 0x0000005d, +PH_PERF_SEL_SC0_PA5_EOPG_WE = 0x0000005e, +PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 0x0000005f, +PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 0x00000060, +PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 0x00000061, +PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 0x00000062, +PH_PERF_SEL_SC0_PA6_FIFO_FULL = 0x00000063, +PH_PERF_SEL_SC0_PA6_NULL_WE = 0x00000064, +PH_PERF_SEL_SC0_PA6_EVENT_WE = 0x00000065, +PH_PERF_SEL_SC0_PA6_FPOV_WE = 0x00000066, +PH_PERF_SEL_SC0_PA6_LPOV_WE = 0x00000067, +PH_PERF_SEL_SC0_PA6_EOP_WE = 0x00000068, +PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 0x00000069, +PH_PERF_SEL_SC0_PA6_EOPG_WE = 0x0000006a, +PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 0x0000006b, +PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 0x0000006c, +PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 0x0000006d, +PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 0x0000006e, +PH_PERF_SEL_SC0_PA7_FIFO_FULL = 0x0000006f, +PH_PERF_SEL_SC0_PA7_NULL_WE = 0x00000070, +PH_PERF_SEL_SC0_PA7_EVENT_WE = 0x00000071, +PH_PERF_SEL_SC0_PA7_FPOV_WE = 0x00000072, +PH_PERF_SEL_SC0_PA7_LPOV_WE = 0x00000073, +PH_PERF_SEL_SC0_PA7_EOP_WE = 0x00000074, +PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 0x00000075, +PH_PERF_SEL_SC0_PA7_EOPG_WE = 0x00000076, +PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 0x00000077, +PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 0x00000078, +PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079, +PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a, +PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b, +PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 0x0000007c, +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 0x0000007d, +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e, +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f, +PH_PERF_SEL_SC1_ARB_BUSY = 0x00000080, +PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 0x00000081, +PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 0x00000082, +PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 0x00000083, +PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084, +PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 0x00000085, +PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086, +PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 0x00000087, +PH_PERF_SEL_SC1_SEND = 0x00000088, +PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089, +PH_PERF_SEL_SC1_CREDIT_AT_MAX = 0x0000008a, +PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b, +PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008c, +PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008d, +PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008e, +PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008f, +PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 0x00000090, +PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 0x00000091, +PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 0x00000092, +PH_PERF_SEL_SC1_PA0_FIFO_FULL = 0x00000093, +PH_PERF_SEL_SC1_PA0_NULL_WE = 0x00000094, +PH_PERF_SEL_SC1_PA0_EVENT_WE = 0x00000095, +PH_PERF_SEL_SC1_PA0_FPOV_WE = 0x00000096, +PH_PERF_SEL_SC1_PA0_LPOV_WE = 0x00000097, +PH_PERF_SEL_SC1_PA0_EOP_WE = 0x00000098, +PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 0x00000099, +PH_PERF_SEL_SC1_PA0_EOPG_WE = 0x0000009a, +PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 0x0000009b, +PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 0x0000009c, +PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 0x0000009d, +PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 0x0000009e, +PH_PERF_SEL_SC1_PA1_FIFO_FULL = 0x0000009f, +PH_PERF_SEL_SC1_PA1_NULL_WE = 0x000000a0, +PH_PERF_SEL_SC1_PA1_EVENT_WE = 0x000000a1, +PH_PERF_SEL_SC1_PA1_FPOV_WE = 0x000000a2, +PH_PERF_SEL_SC1_PA1_LPOV_WE = 0x000000a3, +PH_PERF_SEL_SC1_PA1_EOP_WE = 0x000000a4, +PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 0x000000a5, +PH_PERF_SEL_SC1_PA1_EOPG_WE = 0x000000a6, +PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 0x000000a7, +PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 0x000000a8, +PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 0x000000a9, +PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 0x000000aa, +PH_PERF_SEL_SC1_PA2_FIFO_FULL = 0x000000ab, +PH_PERF_SEL_SC1_PA2_NULL_WE = 0x000000ac, +PH_PERF_SEL_SC1_PA2_EVENT_WE = 0x000000ad, +PH_PERF_SEL_SC1_PA2_FPOV_WE = 0x000000ae, +PH_PERF_SEL_SC1_PA2_LPOV_WE = 0x000000af, +PH_PERF_SEL_SC1_PA2_EOP_WE = 0x000000b0, +PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 0x000000b1, +PH_PERF_SEL_SC1_PA2_EOPG_WE = 0x000000b2, +PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 0x000000b3, +PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 0x000000b4, +PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 0x000000b5, +PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 0x000000b6, +PH_PERF_SEL_SC1_PA3_FIFO_FULL = 0x000000b7, +PH_PERF_SEL_SC1_PA3_NULL_WE = 0x000000b8, +PH_PERF_SEL_SC1_PA3_EVENT_WE = 0x000000b9, +PH_PERF_SEL_SC1_PA3_FPOV_WE = 0x000000ba, +PH_PERF_SEL_SC1_PA3_LPOV_WE = 0x000000bb, +PH_PERF_SEL_SC1_PA3_EOP_WE = 0x000000bc, +PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 0x000000bd, +PH_PERF_SEL_SC1_PA3_EOPG_WE = 0x000000be, +PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 0x000000bf, +PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 0x000000c0, +PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 0x000000c1, +PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 0x000000c2, +PH_PERF_SEL_SC1_PA4_FIFO_FULL = 0x000000c3, +PH_PERF_SEL_SC1_PA4_NULL_WE = 0x000000c4, +PH_PERF_SEL_SC1_PA4_EVENT_WE = 0x000000c5, +PH_PERF_SEL_SC1_PA4_FPOV_WE = 0x000000c6, +PH_PERF_SEL_SC1_PA4_LPOV_WE = 0x000000c7, +PH_PERF_SEL_SC1_PA4_EOP_WE = 0x000000c8, +PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 0x000000c9, +PH_PERF_SEL_SC1_PA4_EOPG_WE = 0x000000ca, +PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 0x000000cb, +PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 0x000000cc, +PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 0x000000cd, +PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 0x000000ce, +PH_PERF_SEL_SC1_PA5_FIFO_FULL = 0x000000cf, +PH_PERF_SEL_SC1_PA5_NULL_WE = 0x000000d0, +PH_PERF_SEL_SC1_PA5_EVENT_WE = 0x000000d1, +PH_PERF_SEL_SC1_PA5_FPOV_WE = 0x000000d2, +PH_PERF_SEL_SC1_PA5_LPOV_WE = 0x000000d3, +PH_PERF_SEL_SC1_PA5_EOP_WE = 0x000000d4, +PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 0x000000d5, +PH_PERF_SEL_SC1_PA5_EOPG_WE = 0x000000d6, +PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 0x000000d7, +PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 0x000000d8, +PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 0x000000d9, +PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 0x000000da, +PH_PERF_SEL_SC1_PA6_FIFO_FULL = 0x000000db, +PH_PERF_SEL_SC1_PA6_NULL_WE = 0x000000dc, +PH_PERF_SEL_SC1_PA6_EVENT_WE = 0x000000dd, +PH_PERF_SEL_SC1_PA6_FPOV_WE = 0x000000de, +PH_PERF_SEL_SC1_PA6_LPOV_WE = 0x000000df, +PH_PERF_SEL_SC1_PA6_EOP_WE = 0x000000e0, +PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 0x000000e1, +PH_PERF_SEL_SC1_PA6_EOPG_WE = 0x000000e2, +PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 0x000000e3, +PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 0x000000e4, +PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 0x000000e5, +PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 0x000000e6, +PH_PERF_SEL_SC1_PA7_FIFO_FULL = 0x000000e7, +PH_PERF_SEL_SC1_PA7_NULL_WE = 0x000000e8, +PH_PERF_SEL_SC1_PA7_EVENT_WE = 0x000000e9, +PH_PERF_SEL_SC1_PA7_FPOV_WE = 0x000000ea, +PH_PERF_SEL_SC1_PA7_LPOV_WE = 0x000000eb, +PH_PERF_SEL_SC1_PA7_EOP_WE = 0x000000ec, +PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 0x000000ed, +PH_PERF_SEL_SC1_PA7_EOPG_WE = 0x000000ee, +PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 0x000000ef, +PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 0x000000f0, +PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1, +PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2, +PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3, +PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 0x000000f4, +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 0x000000f5, +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6, +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7, +PH_PERF_SEL_SC2_ARB_BUSY = 0x000000f8, +PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 0x000000f9, +PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 0x000000fa, +PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 0x000000fb, +PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc, +PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 0x000000fd, +PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe, +PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 0x000000ff, +PH_PERF_SEL_SC2_SEND = 0x00000100, +PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101, +PH_PERF_SEL_SC2_CREDIT_AT_MAX = 0x00000102, +PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103, +PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000104, +PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000105, +PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000106, +PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000107, +PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 0x00000108, +PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 0x00000109, +PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 0x0000010a, +PH_PERF_SEL_SC2_PA0_FIFO_FULL = 0x0000010b, +PH_PERF_SEL_SC2_PA0_NULL_WE = 0x0000010c, +PH_PERF_SEL_SC2_PA0_EVENT_WE = 0x0000010d, +PH_PERF_SEL_SC2_PA0_FPOV_WE = 0x0000010e, +PH_PERF_SEL_SC2_PA0_LPOV_WE = 0x0000010f, +PH_PERF_SEL_SC2_PA0_EOP_WE = 0x00000110, +PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 0x00000111, +PH_PERF_SEL_SC2_PA0_EOPG_WE = 0x00000112, +PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 0x00000113, +PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 0x00000114, +PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 0x00000115, +PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 0x00000116, +PH_PERF_SEL_SC2_PA1_FIFO_FULL = 0x00000117, +PH_PERF_SEL_SC2_PA1_NULL_WE = 0x00000118, +PH_PERF_SEL_SC2_PA1_EVENT_WE = 0x00000119, +PH_PERF_SEL_SC2_PA1_FPOV_WE = 0x0000011a, +PH_PERF_SEL_SC2_PA1_LPOV_WE = 0x0000011b, +PH_PERF_SEL_SC2_PA1_EOP_WE = 0x0000011c, +PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 0x0000011d, +PH_PERF_SEL_SC2_PA1_EOPG_WE = 0x0000011e, +PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 0x0000011f, +PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 0x00000120, +PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 0x00000121, +PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 0x00000122, +PH_PERF_SEL_SC2_PA2_FIFO_FULL = 0x00000123, +PH_PERF_SEL_SC2_PA2_NULL_WE = 0x00000124, +PH_PERF_SEL_SC2_PA2_EVENT_WE = 0x00000125, +PH_PERF_SEL_SC2_PA2_FPOV_WE = 0x00000126, +PH_PERF_SEL_SC2_PA2_LPOV_WE = 0x00000127, +PH_PERF_SEL_SC2_PA2_EOP_WE = 0x00000128, +PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 0x00000129, +PH_PERF_SEL_SC2_PA2_EOPG_WE = 0x0000012a, +PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 0x0000012b, +PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 0x0000012c, +PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 0x0000012d, +PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 0x0000012e, +PH_PERF_SEL_SC2_PA3_FIFO_FULL = 0x0000012f, +PH_PERF_SEL_SC2_PA3_NULL_WE = 0x00000130, +PH_PERF_SEL_SC2_PA3_EVENT_WE = 0x00000131, +PH_PERF_SEL_SC2_PA3_FPOV_WE = 0x00000132, +PH_PERF_SEL_SC2_PA3_LPOV_WE = 0x00000133, +PH_PERF_SEL_SC2_PA3_EOP_WE = 0x00000134, +PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 0x00000135, +PH_PERF_SEL_SC2_PA3_EOPG_WE = 0x00000136, +PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 0x00000137, +PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 0x00000138, +PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 0x00000139, +PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 0x0000013a, +PH_PERF_SEL_SC2_PA4_FIFO_FULL = 0x0000013b, +PH_PERF_SEL_SC2_PA4_NULL_WE = 0x0000013c, +PH_PERF_SEL_SC2_PA4_EVENT_WE = 0x0000013d, +PH_PERF_SEL_SC2_PA4_FPOV_WE = 0x0000013e, +PH_PERF_SEL_SC2_PA4_LPOV_WE = 0x0000013f, +PH_PERF_SEL_SC2_PA4_EOP_WE = 0x00000140, +PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 0x00000141, +PH_PERF_SEL_SC2_PA4_EOPG_WE = 0x00000142, +PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 0x00000143, +PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 0x00000144, +PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 0x00000145, +PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 0x00000146, +PH_PERF_SEL_SC2_PA5_FIFO_FULL = 0x00000147, +PH_PERF_SEL_SC2_PA5_NULL_WE = 0x00000148, +PH_PERF_SEL_SC2_PA5_EVENT_WE = 0x00000149, +PH_PERF_SEL_SC2_PA5_FPOV_WE = 0x0000014a, +PH_PERF_SEL_SC2_PA5_LPOV_WE = 0x0000014b, +PH_PERF_SEL_SC2_PA5_EOP_WE = 0x0000014c, +PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 0x0000014d, +PH_PERF_SEL_SC2_PA5_EOPG_WE = 0x0000014e, +PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 0x0000014f, +PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 0x00000150, +PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 0x00000151, +PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 0x00000152, +PH_PERF_SEL_SC2_PA6_FIFO_FULL = 0x00000153, +PH_PERF_SEL_SC2_PA6_NULL_WE = 0x00000154, +PH_PERF_SEL_SC2_PA6_EVENT_WE = 0x00000155, +PH_PERF_SEL_SC2_PA6_FPOV_WE = 0x00000156, +PH_PERF_SEL_SC2_PA6_LPOV_WE = 0x00000157, +PH_PERF_SEL_SC2_PA6_EOP_WE = 0x00000158, +PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 0x00000159, +PH_PERF_SEL_SC2_PA6_EOPG_WE = 0x0000015a, +PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 0x0000015b, +PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 0x0000015c, +PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 0x0000015d, +PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 0x0000015e, +PH_PERF_SEL_SC2_PA7_FIFO_FULL = 0x0000015f, +PH_PERF_SEL_SC2_PA7_NULL_WE = 0x00000160, +PH_PERF_SEL_SC2_PA7_EVENT_WE = 0x00000161, +PH_PERF_SEL_SC2_PA7_FPOV_WE = 0x00000162, +PH_PERF_SEL_SC2_PA7_LPOV_WE = 0x00000163, +PH_PERF_SEL_SC2_PA7_EOP_WE = 0x00000164, +PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 0x00000165, +PH_PERF_SEL_SC2_PA7_EOPG_WE = 0x00000166, +PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 0x00000167, +PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 0x00000168, +PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169, +PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a, +PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b, +PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 0x0000016c, +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 0x0000016d, +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e, +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f, +PH_PERF_SEL_SC3_ARB_BUSY = 0x00000170, +PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 0x00000171, +PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 0x00000172, +PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 0x00000173, +PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174, +PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 0x00000175, +PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176, +PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 0x00000177, +PH_PERF_SEL_SC3_SEND = 0x00000178, +PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179, +PH_PERF_SEL_SC3_CREDIT_AT_MAX = 0x0000017a, +PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b, +PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017c, +PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017d, +PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017e, +PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017f, +PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 0x00000180, +PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 0x00000181, +PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 0x00000182, +PH_PERF_SEL_SC3_PA0_FIFO_FULL = 0x00000183, +PH_PERF_SEL_SC3_PA0_NULL_WE = 0x00000184, +PH_PERF_SEL_SC3_PA0_EVENT_WE = 0x00000185, +PH_PERF_SEL_SC3_PA0_FPOV_WE = 0x00000186, +PH_PERF_SEL_SC3_PA0_LPOV_WE = 0x00000187, +PH_PERF_SEL_SC3_PA0_EOP_WE = 0x00000188, +PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 0x00000189, +PH_PERF_SEL_SC3_PA0_EOPG_WE = 0x0000018a, +PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 0x0000018b, +PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 0x0000018c, +PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 0x0000018d, +PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 0x0000018e, +PH_PERF_SEL_SC3_PA1_FIFO_FULL = 0x0000018f, +PH_PERF_SEL_SC3_PA1_NULL_WE = 0x00000190, +PH_PERF_SEL_SC3_PA1_EVENT_WE = 0x00000191, +PH_PERF_SEL_SC3_PA1_FPOV_WE = 0x00000192, +PH_PERF_SEL_SC3_PA1_LPOV_WE = 0x00000193, +PH_PERF_SEL_SC3_PA1_EOP_WE = 0x00000194, +PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 0x00000195, +PH_PERF_SEL_SC3_PA1_EOPG_WE = 0x00000196, +PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 0x00000197, +PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 0x00000198, +PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 0x00000199, +PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 0x0000019a, +PH_PERF_SEL_SC3_PA2_FIFO_FULL = 0x0000019b, +PH_PERF_SEL_SC3_PA2_NULL_WE = 0x0000019c, +PH_PERF_SEL_SC3_PA2_EVENT_WE = 0x0000019d, +PH_PERF_SEL_SC3_PA2_FPOV_WE = 0x0000019e, +PH_PERF_SEL_SC3_PA2_LPOV_WE = 0x0000019f, +PH_PERF_SEL_SC3_PA2_EOP_WE = 0x000001a0, +PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 0x000001a1, +PH_PERF_SEL_SC3_PA2_EOPG_WE = 0x000001a2, +PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 0x000001a3, +PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 0x000001a4, +PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 0x000001a5, +PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 0x000001a6, +PH_PERF_SEL_SC3_PA3_FIFO_FULL = 0x000001a7, +PH_PERF_SEL_SC3_PA3_NULL_WE = 0x000001a8, +PH_PERF_SEL_SC3_PA3_EVENT_WE = 0x000001a9, +PH_PERF_SEL_SC3_PA3_FPOV_WE = 0x000001aa, +PH_PERF_SEL_SC3_PA3_LPOV_WE = 0x000001ab, +PH_PERF_SEL_SC3_PA3_EOP_WE = 0x000001ac, +PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 0x000001ad, +PH_PERF_SEL_SC3_PA3_EOPG_WE = 0x000001ae, +PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 0x000001af, +PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 0x000001b0, +PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 0x000001b1, +PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 0x000001b2, +PH_PERF_SEL_SC3_PA4_FIFO_FULL = 0x000001b3, +PH_PERF_SEL_SC3_PA4_NULL_WE = 0x000001b4, +PH_PERF_SEL_SC3_PA4_EVENT_WE = 0x000001b5, +PH_PERF_SEL_SC3_PA4_FPOV_WE = 0x000001b6, +PH_PERF_SEL_SC3_PA4_LPOV_WE = 0x000001b7, +PH_PERF_SEL_SC3_PA4_EOP_WE = 0x000001b8, +PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 0x000001b9, +PH_PERF_SEL_SC3_PA4_EOPG_WE = 0x000001ba, +PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 0x000001bb, +PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 0x000001bc, +PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 0x000001bd, +PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 0x000001be, +PH_PERF_SEL_SC3_PA5_FIFO_FULL = 0x000001bf, +PH_PERF_SEL_SC3_PA5_NULL_WE = 0x000001c0, +PH_PERF_SEL_SC3_PA5_EVENT_WE = 0x000001c1, +PH_PERF_SEL_SC3_PA5_FPOV_WE = 0x000001c2, +PH_PERF_SEL_SC3_PA5_LPOV_WE = 0x000001c3, +PH_PERF_SEL_SC3_PA5_EOP_WE = 0x000001c4, +PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 0x000001c5, +PH_PERF_SEL_SC3_PA5_EOPG_WE = 0x000001c6, +PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 0x000001c7, +PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 0x000001c8, +PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 0x000001c9, +PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 0x000001ca, +PH_PERF_SEL_SC3_PA6_FIFO_FULL = 0x000001cb, +PH_PERF_SEL_SC3_PA6_NULL_WE = 0x000001cc, +PH_PERF_SEL_SC3_PA6_EVENT_WE = 0x000001cd, +PH_PERF_SEL_SC3_PA6_FPOV_WE = 0x000001ce, +PH_PERF_SEL_SC3_PA6_LPOV_WE = 0x000001cf, +PH_PERF_SEL_SC3_PA6_EOP_WE = 0x000001d0, +PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 0x000001d1, +PH_PERF_SEL_SC3_PA6_EOPG_WE = 0x000001d2, +PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 0x000001d3, +PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 0x000001d4, +PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 0x000001d5, +PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 0x000001d6, +PH_PERF_SEL_SC3_PA7_FIFO_FULL = 0x000001d7, +PH_PERF_SEL_SC3_PA7_NULL_WE = 0x000001d8, +PH_PERF_SEL_SC3_PA7_EVENT_WE = 0x000001d9, +PH_PERF_SEL_SC3_PA7_FPOV_WE = 0x000001da, +PH_PERF_SEL_SC3_PA7_LPOV_WE = 0x000001db, +PH_PERF_SEL_SC3_PA7_EOP_WE = 0x000001dc, +PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 0x000001dd, +PH_PERF_SEL_SC3_PA7_EOPG_WE = 0x000001de, +PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 0x000001df, +PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 0x000001e0, +PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1, +PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2, +PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3, +PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 0x000001e4, +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 0x000001e5, +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6, +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7, +PH_PERF_SEL_SC4_ARB_BUSY = 0x000001e8, +PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 0x000001e9, +PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 0x000001ea, +PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 0x000001eb, +PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec, +PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 0x000001ed, +PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee, +PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 0x000001ef, +PH_PERF_SEL_SC4_SEND = 0x000001f0, +PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1, +PH_PERF_SEL_SC4_CREDIT_AT_MAX = 0x000001f2, +PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3, +PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f4, +PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f5, +PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f6, +PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f7, +PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 0x000001f8, +PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 0x000001f9, +PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 0x000001fa, +PH_PERF_SEL_SC4_PA0_FIFO_FULL = 0x000001fb, +PH_PERF_SEL_SC4_PA0_NULL_WE = 0x000001fc, +PH_PERF_SEL_SC4_PA0_EVENT_WE = 0x000001fd, +PH_PERF_SEL_SC4_PA0_FPOV_WE = 0x000001fe, +PH_PERF_SEL_SC4_PA0_LPOV_WE = 0x000001ff, +PH_PERF_SEL_SC4_PA0_EOP_WE = 0x00000200, +PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 0x00000201, +PH_PERF_SEL_SC4_PA0_EOPG_WE = 0x00000202, +PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 0x00000203, +PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 0x00000204, +PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 0x00000205, +PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 0x00000206, +PH_PERF_SEL_SC4_PA1_FIFO_FULL = 0x00000207, +PH_PERF_SEL_SC4_PA1_NULL_WE = 0x00000208, +PH_PERF_SEL_SC4_PA1_EVENT_WE = 0x00000209, +PH_PERF_SEL_SC4_PA1_FPOV_WE = 0x0000020a, +PH_PERF_SEL_SC4_PA1_LPOV_WE = 0x0000020b, +PH_PERF_SEL_SC4_PA1_EOP_WE = 0x0000020c, +PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 0x0000020d, +PH_PERF_SEL_SC4_PA1_EOPG_WE = 0x0000020e, +PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 0x0000020f, +PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 0x00000210, +PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 0x00000211, +PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 0x00000212, +PH_PERF_SEL_SC4_PA2_FIFO_FULL = 0x00000213, +PH_PERF_SEL_SC4_PA2_NULL_WE = 0x00000214, +PH_PERF_SEL_SC4_PA2_EVENT_WE = 0x00000215, +PH_PERF_SEL_SC4_PA2_FPOV_WE = 0x00000216, +PH_PERF_SEL_SC4_PA2_LPOV_WE = 0x00000217, +PH_PERF_SEL_SC4_PA2_EOP_WE = 0x00000218, +PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 0x00000219, +PH_PERF_SEL_SC4_PA2_EOPG_WE = 0x0000021a, +PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 0x0000021b, +PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 0x0000021c, +PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 0x0000021d, +PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 0x0000021e, +PH_PERF_SEL_SC4_PA3_FIFO_FULL = 0x0000021f, +PH_PERF_SEL_SC4_PA3_NULL_WE = 0x00000220, +PH_PERF_SEL_SC4_PA3_EVENT_WE = 0x00000221, +PH_PERF_SEL_SC4_PA3_FPOV_WE = 0x00000222, +PH_PERF_SEL_SC4_PA3_LPOV_WE = 0x00000223, +PH_PERF_SEL_SC4_PA3_EOP_WE = 0x00000224, +PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 0x00000225, +PH_PERF_SEL_SC4_PA3_EOPG_WE = 0x00000226, +PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 0x00000227, +PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 0x00000228, +PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 0x00000229, +PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 0x0000022a, +PH_PERF_SEL_SC4_PA4_FIFO_FULL = 0x0000022b, +PH_PERF_SEL_SC4_PA4_NULL_WE = 0x0000022c, +PH_PERF_SEL_SC4_PA4_EVENT_WE = 0x0000022d, +PH_PERF_SEL_SC4_PA4_FPOV_WE = 0x0000022e, +PH_PERF_SEL_SC4_PA4_LPOV_WE = 0x0000022f, +PH_PERF_SEL_SC4_PA4_EOP_WE = 0x00000230, +PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 0x00000231, +PH_PERF_SEL_SC4_PA4_EOPG_WE = 0x00000232, +PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 0x00000233, +PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 0x00000234, +PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 0x00000235, +PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 0x00000236, +PH_PERF_SEL_SC4_PA5_FIFO_FULL = 0x00000237, +PH_PERF_SEL_SC4_PA5_NULL_WE = 0x00000238, +PH_PERF_SEL_SC4_PA5_EVENT_WE = 0x00000239, +PH_PERF_SEL_SC4_PA5_FPOV_WE = 0x0000023a, +PH_PERF_SEL_SC4_PA5_LPOV_WE = 0x0000023b, +PH_PERF_SEL_SC4_PA5_EOP_WE = 0x0000023c, +PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 0x0000023d, +PH_PERF_SEL_SC4_PA5_EOPG_WE = 0x0000023e, +PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 0x0000023f, +PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 0x00000240, +PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 0x00000241, +PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 0x00000242, +PH_PERF_SEL_SC4_PA6_FIFO_FULL = 0x00000243, +PH_PERF_SEL_SC4_PA6_NULL_WE = 0x00000244, +PH_PERF_SEL_SC4_PA6_EVENT_WE = 0x00000245, +PH_PERF_SEL_SC4_PA6_FPOV_WE = 0x00000246, +PH_PERF_SEL_SC4_PA6_LPOV_WE = 0x00000247, +PH_PERF_SEL_SC4_PA6_EOP_WE = 0x00000248, +PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 0x00000249, +PH_PERF_SEL_SC4_PA6_EOPG_WE = 0x0000024a, +PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 0x0000024b, +PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 0x0000024c, +PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 0x0000024d, +PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 0x0000024e, +PH_PERF_SEL_SC4_PA7_FIFO_FULL = 0x0000024f, +PH_PERF_SEL_SC4_PA7_NULL_WE = 0x00000250, +PH_PERF_SEL_SC4_PA7_EVENT_WE = 0x00000251, +PH_PERF_SEL_SC4_PA7_FPOV_WE = 0x00000252, +PH_PERF_SEL_SC4_PA7_LPOV_WE = 0x00000253, +PH_PERF_SEL_SC4_PA7_EOP_WE = 0x00000254, +PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 0x00000255, +PH_PERF_SEL_SC4_PA7_EOPG_WE = 0x00000256, +PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 0x00000257, +PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 0x00000258, +PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259, +PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a, +PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b, +PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 0x0000025c, +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 0x0000025d, +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e, +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f, +PH_PERF_SEL_SC5_ARB_BUSY = 0x00000260, +PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 0x00000261, +PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 0x00000262, +PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 0x00000263, +PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264, +PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 0x00000265, +PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266, +PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 0x00000267, +PH_PERF_SEL_SC5_SEND = 0x00000268, +PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269, +PH_PERF_SEL_SC5_CREDIT_AT_MAX = 0x0000026a, +PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b, +PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026c, +PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026d, +PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026e, +PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026f, +PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 0x00000270, +PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 0x00000271, +PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 0x00000272, +PH_PERF_SEL_SC5_PA0_FIFO_FULL = 0x00000273, +PH_PERF_SEL_SC5_PA0_NULL_WE = 0x00000274, +PH_PERF_SEL_SC5_PA0_EVENT_WE = 0x00000275, +PH_PERF_SEL_SC5_PA0_FPOV_WE = 0x00000276, +PH_PERF_SEL_SC5_PA0_LPOV_WE = 0x00000277, +PH_PERF_SEL_SC5_PA0_EOP_WE = 0x00000278, +PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 0x00000279, +PH_PERF_SEL_SC5_PA0_EOPG_WE = 0x0000027a, +PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 0x0000027b, +PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 0x0000027c, +PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 0x0000027d, +PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 0x0000027e, +PH_PERF_SEL_SC5_PA1_FIFO_FULL = 0x0000027f, +PH_PERF_SEL_SC5_PA1_NULL_WE = 0x00000280, +PH_PERF_SEL_SC5_PA1_EVENT_WE = 0x00000281, +PH_PERF_SEL_SC5_PA1_FPOV_WE = 0x00000282, +PH_PERF_SEL_SC5_PA1_LPOV_WE = 0x00000283, +PH_PERF_SEL_SC5_PA1_EOP_WE = 0x00000284, +PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 0x00000285, +PH_PERF_SEL_SC5_PA1_EOPG_WE = 0x00000286, +PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 0x00000287, +PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 0x00000288, +PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 0x00000289, +PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 0x0000028a, +PH_PERF_SEL_SC5_PA2_FIFO_FULL = 0x0000028b, +PH_PERF_SEL_SC5_PA2_NULL_WE = 0x0000028c, +PH_PERF_SEL_SC5_PA2_EVENT_WE = 0x0000028d, +PH_PERF_SEL_SC5_PA2_FPOV_WE = 0x0000028e, +PH_PERF_SEL_SC5_PA2_LPOV_WE = 0x0000028f, +PH_PERF_SEL_SC5_PA2_EOP_WE = 0x00000290, +PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 0x00000291, +PH_PERF_SEL_SC5_PA2_EOPG_WE = 0x00000292, +PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 0x00000293, +PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 0x00000294, +PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 0x00000295, +PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 0x00000296, +PH_PERF_SEL_SC5_PA3_FIFO_FULL = 0x00000297, +PH_PERF_SEL_SC5_PA3_NULL_WE = 0x00000298, +PH_PERF_SEL_SC5_PA3_EVENT_WE = 0x00000299, +PH_PERF_SEL_SC5_PA3_FPOV_WE = 0x0000029a, +PH_PERF_SEL_SC5_PA3_LPOV_WE = 0x0000029b, +PH_PERF_SEL_SC5_PA3_EOP_WE = 0x0000029c, +PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 0x0000029d, +PH_PERF_SEL_SC5_PA3_EOPG_WE = 0x0000029e, +PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 0x0000029f, +PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 0x000002a0, +PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 0x000002a1, +PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 0x000002a2, +PH_PERF_SEL_SC5_PA4_FIFO_FULL = 0x000002a3, +PH_PERF_SEL_SC5_PA4_NULL_WE = 0x000002a4, +PH_PERF_SEL_SC5_PA4_EVENT_WE = 0x000002a5, +PH_PERF_SEL_SC5_PA4_FPOV_WE = 0x000002a6, +PH_PERF_SEL_SC5_PA4_LPOV_WE = 0x000002a7, +PH_PERF_SEL_SC5_PA4_EOP_WE = 0x000002a8, +PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 0x000002a9, +PH_PERF_SEL_SC5_PA4_EOPG_WE = 0x000002aa, +PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 0x000002ab, +PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 0x000002ac, +PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 0x000002ad, +PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 0x000002ae, +PH_PERF_SEL_SC5_PA5_FIFO_FULL = 0x000002af, +PH_PERF_SEL_SC5_PA5_NULL_WE = 0x000002b0, +PH_PERF_SEL_SC5_PA5_EVENT_WE = 0x000002b1, +PH_PERF_SEL_SC5_PA5_FPOV_WE = 0x000002b2, +PH_PERF_SEL_SC5_PA5_LPOV_WE = 0x000002b3, +PH_PERF_SEL_SC5_PA5_EOP_WE = 0x000002b4, +PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 0x000002b5, +PH_PERF_SEL_SC5_PA5_EOPG_WE = 0x000002b6, +PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 0x000002b7, +PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 0x000002b8, +PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 0x000002b9, +PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 0x000002ba, +PH_PERF_SEL_SC5_PA6_FIFO_FULL = 0x000002bb, +PH_PERF_SEL_SC5_PA6_NULL_WE = 0x000002bc, +PH_PERF_SEL_SC5_PA6_EVENT_WE = 0x000002bd, +PH_PERF_SEL_SC5_PA6_FPOV_WE = 0x000002be, +PH_PERF_SEL_SC5_PA6_LPOV_WE = 0x000002bf, +PH_PERF_SEL_SC5_PA6_EOP_WE = 0x000002c0, +PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 0x000002c1, +PH_PERF_SEL_SC5_PA6_EOPG_WE = 0x000002c2, +PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 0x000002c3, +PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 0x000002c4, +PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 0x000002c5, +PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 0x000002c6, +PH_PERF_SEL_SC5_PA7_FIFO_FULL = 0x000002c7, +PH_PERF_SEL_SC5_PA7_NULL_WE = 0x000002c8, +PH_PERF_SEL_SC5_PA7_EVENT_WE = 0x000002c9, +PH_PERF_SEL_SC5_PA7_FPOV_WE = 0x000002ca, +PH_PERF_SEL_SC5_PA7_LPOV_WE = 0x000002cb, +PH_PERF_SEL_SC5_PA7_EOP_WE = 0x000002cc, +PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 0x000002cd, +PH_PERF_SEL_SC5_PA7_EOPG_WE = 0x000002ce, +PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 0x000002cf, +PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 0x000002d0, +PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1, +PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2, +PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3, +PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 0x000002d4, +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 0x000002d5, +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6, +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7, +PH_PERF_SEL_SC6_ARB_BUSY = 0x000002d8, +PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 0x000002d9, +PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 0x000002da, +PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 0x000002db, +PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc, +PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 0x000002dd, +PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de, +PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 0x000002df, +PH_PERF_SEL_SC6_SEND = 0x000002e0, +PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1, +PH_PERF_SEL_SC6_CREDIT_AT_MAX = 0x000002e2, +PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3, +PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e4, +PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e5, +PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e6, +PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e7, +PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 0x000002e8, +PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 0x000002e9, +PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 0x000002ea, +PH_PERF_SEL_SC6_PA0_FIFO_FULL = 0x000002eb, +PH_PERF_SEL_SC6_PA0_NULL_WE = 0x000002ec, +PH_PERF_SEL_SC6_PA0_EVENT_WE = 0x000002ed, +PH_PERF_SEL_SC6_PA0_FPOV_WE = 0x000002ee, +PH_PERF_SEL_SC6_PA0_LPOV_WE = 0x000002ef, +PH_PERF_SEL_SC6_PA0_EOP_WE = 0x000002f0, +PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 0x000002f1, +PH_PERF_SEL_SC6_PA0_EOPG_WE = 0x000002f2, +PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 0x000002f3, +PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 0x000002f4, +PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 0x000002f5, +PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 0x000002f6, +PH_PERF_SEL_SC6_PA1_FIFO_FULL = 0x000002f7, +PH_PERF_SEL_SC6_PA1_NULL_WE = 0x000002f8, +PH_PERF_SEL_SC6_PA1_EVENT_WE = 0x000002f9, +PH_PERF_SEL_SC6_PA1_FPOV_WE = 0x000002fa, +PH_PERF_SEL_SC6_PA1_LPOV_WE = 0x000002fb, +PH_PERF_SEL_SC6_PA1_EOP_WE = 0x000002fc, +PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 0x000002fd, +PH_PERF_SEL_SC6_PA1_EOPG_WE = 0x000002fe, +PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 0x000002ff, +PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 0x00000300, +PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 0x00000301, +PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 0x00000302, +PH_PERF_SEL_SC6_PA2_FIFO_FULL = 0x00000303, +PH_PERF_SEL_SC6_PA2_NULL_WE = 0x00000304, +PH_PERF_SEL_SC6_PA2_EVENT_WE = 0x00000305, +PH_PERF_SEL_SC6_PA2_FPOV_WE = 0x00000306, +PH_PERF_SEL_SC6_PA2_LPOV_WE = 0x00000307, +PH_PERF_SEL_SC6_PA2_EOP_WE = 0x00000308, +PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 0x00000309, +PH_PERF_SEL_SC6_PA2_EOPG_WE = 0x0000030a, +PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 0x0000030b, +PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 0x0000030c, +PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 0x0000030d, +PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 0x0000030e, +PH_PERF_SEL_SC6_PA3_FIFO_FULL = 0x0000030f, +PH_PERF_SEL_SC6_PA3_NULL_WE = 0x00000310, +PH_PERF_SEL_SC6_PA3_EVENT_WE = 0x00000311, +PH_PERF_SEL_SC6_PA3_FPOV_WE = 0x00000312, +PH_PERF_SEL_SC6_PA3_LPOV_WE = 0x00000313, +PH_PERF_SEL_SC6_PA3_EOP_WE = 0x00000314, +PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 0x00000315, +PH_PERF_SEL_SC6_PA3_EOPG_WE = 0x00000316, +PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 0x00000317, +PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 0x00000318, +PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 0x00000319, +PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 0x0000031a, +PH_PERF_SEL_SC6_PA4_FIFO_FULL = 0x0000031b, +PH_PERF_SEL_SC6_PA4_NULL_WE = 0x0000031c, +PH_PERF_SEL_SC6_PA4_EVENT_WE = 0x0000031d, +PH_PERF_SEL_SC6_PA4_FPOV_WE = 0x0000031e, +PH_PERF_SEL_SC6_PA4_LPOV_WE = 0x0000031f, +PH_PERF_SEL_SC6_PA4_EOP_WE = 0x00000320, +PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 0x00000321, +PH_PERF_SEL_SC6_PA4_EOPG_WE = 0x00000322, +PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 0x00000323, +PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 0x00000324, +PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 0x00000325, +PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 0x00000326, +PH_PERF_SEL_SC6_PA5_FIFO_FULL = 0x00000327, +PH_PERF_SEL_SC6_PA5_NULL_WE = 0x00000328, +PH_PERF_SEL_SC6_PA5_EVENT_WE = 0x00000329, +PH_PERF_SEL_SC6_PA5_FPOV_WE = 0x0000032a, +PH_PERF_SEL_SC6_PA5_LPOV_WE = 0x0000032b, +PH_PERF_SEL_SC6_PA5_EOP_WE = 0x0000032c, +PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 0x0000032d, +PH_PERF_SEL_SC6_PA5_EOPG_WE = 0x0000032e, +PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 0x0000032f, +PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 0x00000330, +PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 0x00000331, +PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 0x00000332, +PH_PERF_SEL_SC6_PA6_FIFO_FULL = 0x00000333, +PH_PERF_SEL_SC6_PA6_NULL_WE = 0x00000334, +PH_PERF_SEL_SC6_PA6_EVENT_WE = 0x00000335, +PH_PERF_SEL_SC6_PA6_FPOV_WE = 0x00000336, +PH_PERF_SEL_SC6_PA6_LPOV_WE = 0x00000337, +PH_PERF_SEL_SC6_PA6_EOP_WE = 0x00000338, +PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 0x00000339, +PH_PERF_SEL_SC6_PA6_EOPG_WE = 0x0000033a, +PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 0x0000033b, +PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 0x0000033c, +PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 0x0000033d, +PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 0x0000033e, +PH_PERF_SEL_SC6_PA7_FIFO_FULL = 0x0000033f, +PH_PERF_SEL_SC6_PA7_NULL_WE = 0x00000340, +PH_PERF_SEL_SC6_PA7_EVENT_WE = 0x00000341, +PH_PERF_SEL_SC6_PA7_FPOV_WE = 0x00000342, +PH_PERF_SEL_SC6_PA7_LPOV_WE = 0x00000343, +PH_PERF_SEL_SC6_PA7_EOP_WE = 0x00000344, +PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 0x00000345, +PH_PERF_SEL_SC6_PA7_EOPG_WE = 0x00000346, +PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 0x00000347, +PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 0x00000348, +PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349, +PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a, +PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b, +PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 0x0000034c, +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 0x0000034d, +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e, +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f, +PH_PERF_SEL_SC7_ARB_BUSY = 0x00000350, +PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 0x00000351, +PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 0x00000352, +PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 0x00000353, +PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354, +PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 0x00000355, +PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356, +PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 0x00000357, +PH_PERF_SEL_SC7_SEND = 0x00000358, +PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359, +PH_PERF_SEL_SC7_CREDIT_AT_MAX = 0x0000035a, +PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b, +PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035c, +PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035d, +PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035e, +PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035f, +PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 0x00000360, +PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 0x00000361, +PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 0x00000362, +PH_PERF_SEL_SC7_PA0_FIFO_FULL = 0x00000363, +PH_PERF_SEL_SC7_PA0_NULL_WE = 0x00000364, +PH_PERF_SEL_SC7_PA0_EVENT_WE = 0x00000365, +PH_PERF_SEL_SC7_PA0_FPOV_WE = 0x00000366, +PH_PERF_SEL_SC7_PA0_LPOV_WE = 0x00000367, +PH_PERF_SEL_SC7_PA0_EOP_WE = 0x00000368, +PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 0x00000369, +PH_PERF_SEL_SC7_PA0_EOPG_WE = 0x0000036a, +PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 0x0000036b, +PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 0x0000036c, +PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 0x0000036d, +PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 0x0000036e, +PH_PERF_SEL_SC7_PA1_FIFO_FULL = 0x0000036f, +PH_PERF_SEL_SC7_PA1_NULL_WE = 0x00000370, +PH_PERF_SEL_SC7_PA1_EVENT_WE = 0x00000371, +PH_PERF_SEL_SC7_PA1_FPOV_WE = 0x00000372, +PH_PERF_SEL_SC7_PA1_LPOV_WE = 0x00000373, +PH_PERF_SEL_SC7_PA1_EOP_WE = 0x00000374, +PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 0x00000375, +PH_PERF_SEL_SC7_PA1_EOPG_WE = 0x00000376, +PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 0x00000377, +PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 0x00000378, +PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 0x00000379, +PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 0x0000037a, +PH_PERF_SEL_SC7_PA2_FIFO_FULL = 0x0000037b, +PH_PERF_SEL_SC7_PA2_NULL_WE = 0x0000037c, +PH_PERF_SEL_SC7_PA2_EVENT_WE = 0x0000037d, +PH_PERF_SEL_SC7_PA2_FPOV_WE = 0x0000037e, +PH_PERF_SEL_SC7_PA2_LPOV_WE = 0x0000037f, +PH_PERF_SEL_SC7_PA2_EOP_WE = 0x00000380, +PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 0x00000381, +PH_PERF_SEL_SC7_PA2_EOPG_WE = 0x00000382, +PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 0x00000383, +PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 0x00000384, +PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 0x00000385, +PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 0x00000386, +PH_PERF_SEL_SC7_PA3_FIFO_FULL = 0x00000387, +PH_PERF_SEL_SC7_PA3_NULL_WE = 0x00000388, +PH_PERF_SEL_SC7_PA3_EVENT_WE = 0x00000389, +PH_PERF_SEL_SC7_PA3_FPOV_WE = 0x0000038a, +PH_PERF_SEL_SC7_PA3_LPOV_WE = 0x0000038b, +PH_PERF_SEL_SC7_PA3_EOP_WE = 0x0000038c, +PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 0x0000038d, +PH_PERF_SEL_SC7_PA3_EOPG_WE = 0x0000038e, +PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 0x0000038f, +PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 0x00000390, +PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 0x00000391, +PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 0x00000392, +PH_PERF_SEL_SC7_PA4_FIFO_FULL = 0x00000393, +PH_PERF_SEL_SC7_PA4_NULL_WE = 0x00000394, +PH_PERF_SEL_SC7_PA4_EVENT_WE = 0x00000395, +PH_PERF_SEL_SC7_PA4_FPOV_WE = 0x00000396, +PH_PERF_SEL_SC7_PA4_LPOV_WE = 0x00000397, +PH_PERF_SEL_SC7_PA4_EOP_WE = 0x00000398, +PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 0x00000399, +PH_PERF_SEL_SC7_PA4_EOPG_WE = 0x0000039a, +PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 0x0000039b, +PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 0x0000039c, +PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 0x0000039d, +PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 0x0000039e, +PH_PERF_SEL_SC7_PA5_FIFO_FULL = 0x0000039f, +PH_PERF_SEL_SC7_PA5_NULL_WE = 0x000003a0, +PH_PERF_SEL_SC7_PA5_EVENT_WE = 0x000003a1, +PH_PERF_SEL_SC7_PA5_FPOV_WE = 0x000003a2, +PH_PERF_SEL_SC7_PA5_LPOV_WE = 0x000003a3, +PH_PERF_SEL_SC7_PA5_EOP_WE = 0x000003a4, +PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 0x000003a5, +PH_PERF_SEL_SC7_PA5_EOPG_WE = 0x000003a6, +PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 0x000003a7, +PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 0x000003a8, +PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 0x000003a9, +PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 0x000003aa, +PH_PERF_SEL_SC7_PA6_FIFO_FULL = 0x000003ab, +PH_PERF_SEL_SC7_PA6_NULL_WE = 0x000003ac, +PH_PERF_SEL_SC7_PA6_EVENT_WE = 0x000003ad, +PH_PERF_SEL_SC7_PA6_FPOV_WE = 0x000003ae, +PH_PERF_SEL_SC7_PA6_LPOV_WE = 0x000003af, +PH_PERF_SEL_SC7_PA6_EOP_WE = 0x000003b0, +PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 0x000003b1, +PH_PERF_SEL_SC7_PA6_EOPG_WE = 0x000003b2, +PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 0x000003b3, +PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 0x000003b4, +PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 0x000003b5, +PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 0x000003b6, +PH_PERF_SEL_SC7_PA7_FIFO_FULL = 0x000003b7, +PH_PERF_SEL_SC7_PA7_NULL_WE = 0x000003b8, +PH_PERF_SEL_SC7_PA7_EVENT_WE = 0x000003b9, +PH_PERF_SEL_SC7_PA7_FPOV_WE = 0x000003ba, +PH_PERF_SEL_SC7_PA7_LPOV_WE = 0x000003bb, +PH_PERF_SEL_SC7_PA7_EOP_WE = 0x000003bc, +PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 0x000003bd, +PH_PERF_SEL_SC7_PA7_EOPG_WE = 0x000003be, +PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 0x000003bf, +PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 0x000003c0, +PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 0x000003c1, +PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 0x000003c2, +PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 0x000003c3, +PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 0x000003c4, +PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 0x000003c5, +PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 0x000003c6, +PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 0x000003c7, +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 0x000003c8, +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 0x000003c9, +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 0x000003ca, +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 0x000003cb, +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 0x000003cc, +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 0x000003cd, +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 0x000003ce, +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 0x000003cf, +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d0, +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d1, +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d2, +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d3, +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d4, +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d5, +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d6, +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d7, +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d8, +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d9, +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003da, +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003db, +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dc, +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dd, +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003de, +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003df, +PH_PERF_SC0_FIFO_STATUS_0 = 0x000003e0, +PH_PERF_SC0_FIFO_STATUS_1 = 0x000003e1, +PH_PERF_SC0_FIFO_STATUS_2 = 0x000003e2, +PH_PERF_SC0_FIFO_STATUS_3 = 0x000003e3, +PH_PERF_SC1_FIFO_STATUS_0 = 0x000003e4, +PH_PERF_SC1_FIFO_STATUS_1 = 0x000003e5, +PH_PERF_SC1_FIFO_STATUS_2 = 0x000003e6, +PH_PERF_SC1_FIFO_STATUS_3 = 0x000003e7, +PH_PERF_SC2_FIFO_STATUS_0 = 0x000003e8, +PH_PERF_SC2_FIFO_STATUS_1 = 0x000003e9, +PH_PERF_SC2_FIFO_STATUS_2 = 0x000003ea, +PH_PERF_SC2_FIFO_STATUS_3 = 0x000003eb, +PH_PERF_SC3_FIFO_STATUS_0 = 0x000003ec, +PH_PERF_SC3_FIFO_STATUS_1 = 0x000003ed, +PH_PERF_SC3_FIFO_STATUS_2 = 0x000003ee, +PH_PERF_SC3_FIFO_STATUS_3 = 0x000003ef, +PH_PERF_SC4_FIFO_STATUS_0 = 0x000003f0, +PH_PERF_SC4_FIFO_STATUS_1 = 0x000003f1, +PH_PERF_SC4_FIFO_STATUS_2 = 0x000003f2, +PH_PERF_SC4_FIFO_STATUS_3 = 0x000003f3, +PH_PERF_SC5_FIFO_STATUS_0 = 0x000003f4, +PH_PERF_SC5_FIFO_STATUS_1 = 0x000003f5, +PH_PERF_SC5_FIFO_STATUS_2 = 0x000003f6, +PH_PERF_SC5_FIFO_STATUS_3 = 0x000003f7, +PH_PERF_SC6_FIFO_STATUS_0 = 0x000003f8, +PH_PERF_SC6_FIFO_STATUS_1 = 0x000003f9, +PH_PERF_SC6_FIFO_STATUS_2 = 0x000003fa, +PH_PERF_SC6_FIFO_STATUS_3 = 0x000003fb, +PH_PERF_SC7_FIFO_STATUS_0 = 0x000003fc, +PH_PERF_SC7_FIFO_STATUS_1 = 0x000003fd, +PH_PERF_SC7_FIFO_STATUS_2 = 0x000003fe, +PH_PERF_SC7_FIFO_STATUS_3 = 0x000003ff, +} PH_PERFCNT_SEL; + +/* + * PhSPIstatusMode enum + */ + +typedef enum PhSPIstatusMode { +PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0x00000000, +PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 0x00000001, +PH_SPI_MODE_DISABLED = 0x00000002, +} PhSPIstatusMode; + +/******************************************************* + * RMI Enums + *******************************************************/ + +/* + * RMIPerfSel enum + */ + +typedef enum RMIPerfSel { +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000000, +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000001, +} RMIPerfSel; + +/******************************************************* + * PMM Enums + *******************************************************/ + +/* + * GCRPerfSel enum + */ + +typedef enum GCRPerfSel { +GCR_PERF_SEL_NONE = 0x00000000, +GCR_PERF_SEL_SDMA0_ALL_REQ = 0x00000001, +GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 0x00000002, +GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 0x00000003, +GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 0x00000004, +GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 0x00000005, +GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 0x00000006, +GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 0x00000007, +GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 0x00000008, +GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 0x00000009, +GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 0x0000000a, +GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 0x0000000b, +GCR_PERF_SEL_SDMA0_METADATA_REQ = 0x0000000c, +GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 0x0000000d, +GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 0x0000000e, +GCR_PERF_SEL_SDMA0_TCP_REQ = 0x0000000f, +GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 0x00000010, +GCR_PERF_SEL_SDMA1_ALL_REQ = 0x00000011, +GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 0x00000012, +GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 0x00000013, +GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 0x00000014, +GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 0x00000015, +GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 0x00000016, +GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 0x00000017, +GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 0x00000018, +GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 0x00000019, +GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 0x0000001a, +GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 0x0000001b, +GCR_PERF_SEL_SDMA1_METADATA_REQ = 0x0000001c, +GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 0x0000001d, +GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 0x0000001e, +GCR_PERF_SEL_SDMA1_TCP_REQ = 0x0000001f, +GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 0x00000020, +GCR_PERF_SEL_CPC_ALL_REQ = 0x00000021, +GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 0x00000022, +GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 0x00000023, +GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 0x00000024, +GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 0x00000025, +GCR_PERF_SEL_CPC_GL2_ALL_REQ = 0x00000026, +GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 0x00000027, +GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 0x00000028, +GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 0x00000029, +GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 0x0000002a, +GCR_PERF_SEL_CPC_GL1_ALL_REQ = 0x0000002b, +GCR_PERF_SEL_CPC_METADATA_REQ = 0x0000002c, +GCR_PERF_SEL_CPC_SQC_DATA_REQ = 0x0000002d, +GCR_PERF_SEL_CPC_SQC_INST_REQ = 0x0000002e, +GCR_PERF_SEL_CPC_TCP_REQ = 0x0000002f, +GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 0x00000030, +GCR_PERF_SEL_CPG_ALL_REQ = 0x00000031, +GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 0x00000032, +GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 0x00000033, +GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 0x00000034, +GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 0x00000035, +GCR_PERF_SEL_CPG_GL2_ALL_REQ = 0x00000036, +GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 0x00000037, +GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 0x00000038, +GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 0x00000039, +GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 0x0000003a, +GCR_PERF_SEL_CPG_GL1_ALL_REQ = 0x0000003b, +GCR_PERF_SEL_CPG_METADATA_REQ = 0x0000003c, +GCR_PERF_SEL_CPG_SQC_DATA_REQ = 0x0000003d, +GCR_PERF_SEL_CPG_SQC_INST_REQ = 0x0000003e, +GCR_PERF_SEL_CPG_TCP_REQ = 0x0000003f, +GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 0x00000040, +GCR_PERF_SEL_CPF_ALL_REQ = 0x00000041, +GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 0x00000042, +GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 0x00000043, +GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 0x00000044, +GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 0x00000045, +GCR_PERF_SEL_CPF_GL2_ALL_REQ = 0x00000046, +GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 0x00000047, +GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 0x00000048, +GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 0x00000049, +GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 0x0000004a, +GCR_PERF_SEL_CPF_GL1_ALL_REQ = 0x0000004b, +GCR_PERF_SEL_CPF_METADATA_REQ = 0x0000004c, +GCR_PERF_SEL_CPF_SQC_DATA_REQ = 0x0000004d, +GCR_PERF_SEL_CPF_SQC_INST_REQ = 0x0000004e, +GCR_PERF_SEL_CPF_TCP_REQ = 0x0000004f, +GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 0x00000050, +GCR_PERF_SEL_VIRT_REQ = 0x00000051, +GCR_PERF_SEL_PHY_REQ = 0x00000052, +GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 0x00000053, +GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 0x00000054, +GCR_PERF_SEL_ALL_REQ = 0x00000055, +GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056, +GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057, +GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058, +GCR_PERF_SEL_UTCL2_REQ = 0x00000059, +GCR_PERF_SEL_UTCL2_RET = 0x0000005a, +GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 0x0000005b, +GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 0x0000005c, +GCR_PERF_SEL_UTCL2_FILTERED_RET = 0x0000005d, +GCR_PERF_SEL_RLC_ALL_REQ = 0x0000005e, +GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 0x0000005f, +GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 0x00000060, +GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 0x00000061, +GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 0x00000062, +GCR_PERF_SEL_RLC_GL2_ALL_REQ = 0x00000063, +GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 0x00000064, +GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 0x00000065, +GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 0x00000066, +GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 0x00000067, +GCR_PERF_SEL_RLC_GL1_ALL_REQ = 0x00000068, +GCR_PERF_SEL_RLC_METADATA_REQ = 0x00000069, +GCR_PERF_SEL_RLC_SQC_DATA_REQ = 0x0000006a, +GCR_PERF_SEL_RLC_SQC_INST_REQ = 0x0000006b, +GCR_PERF_SEL_RLC_TCP_REQ = 0x0000006c, +GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 0x0000006d, +GCR_PERF_SEL_PM_ALL_REQ = 0x0000006e, +GCR_PERF_SEL_PM_GL2_RANGE_REQ = 0x0000006f, +GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 0x00000070, +GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 0x00000071, +GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 0x00000072, +GCR_PERF_SEL_PM_GL2_ALL_REQ = 0x00000073, +GCR_PERF_SEL_PM_GL1_RANGE_REQ = 0x00000074, +GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 0x00000075, +GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 0x00000076, +GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 0x00000077, +GCR_PERF_SEL_PM_GL1_ALL_REQ = 0x00000078, +GCR_PERF_SEL_PM_METADATA_REQ = 0x00000079, +GCR_PERF_SEL_PM_SQC_DATA_REQ = 0x0000007a, +GCR_PERF_SEL_PM_SQC_INST_REQ = 0x0000007b, +GCR_PERF_SEL_PM_TCP_REQ = 0x0000007c, +GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 0x0000007d, +GCR_PERF_SEL_PIO_ALL_REQ = 0x0000007e, +GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 0x0000007f, +GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 0x00000080, +GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 0x00000081, +GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 0x00000082, +GCR_PERF_SEL_PIO_GL2_ALL_REQ = 0x00000083, +GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 0x00000084, +GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 0x00000085, +GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 0x00000086, +GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 0x00000087, +GCR_PERF_SEL_PIO_GL1_ALL_REQ = 0x00000088, +GCR_PERF_SEL_PIO_METADATA_REQ = 0x00000089, +GCR_PERF_SEL_PIO_SQC_DATA_REQ = 0x0000008a, +GCR_PERF_SEL_PIO_SQC_INST_REQ = 0x0000008b, +GCR_PERF_SEL_PIO_TCP_REQ = 0x0000008c, +GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 0x0000008d, +} GCRPerfSel; + +/******************************************************* + * UTCL1 Enums + *******************************************************/ + +/* + * UTCL1PerfSel enum + */ + +typedef enum UTCL1PerfSel { +UTCL1_PERF_SEL_NONE = 0x00000000, +UTCL1_PERF_SEL_REQS = 0x00000001, +UTCL1_PERF_SEL_HITS = 0x00000002, +UTCL1_PERF_SEL_MISSES = 0x00000003, +UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 0x00000004, +UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 0x00000005, +UTCL1_PERF_SEL_UTCL2_REQS = 0x00000006, +UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 0x00000007, +UTCL1_PERF_SEL_UTCL2_RET_FAULT = 0x00000008, +UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 0x00000009, +UTCL1_PERF_SEL_STALL_MH_FULL = 0x0000000a, +UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 0x0000000b, +UTCL1_PERF_SEL_UTCL2_RET_CNT = 0x0000000c, +UTCL1_PERF_SEL_RTNS = 0x0000000d, +UTCL1_PERF_SEL_XLAT_REQ_BUSY = 0x0000000e, +UTCL1_PERF_SEL_BYPASS_REQS = 0x0000000f, +UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 0x00000010, +UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 0x00000011, +UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 0x00000012, +UTCL1_PERF_SEL_CP_INVREQS = 0x00000013, +UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 0x00000014, +UTCL1_PERF_SEL_RANGE_INVREQS = 0x00000015, +UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 0x00000016, +} UTCL1PerfSel; + +/******************************************************* + * IH Enums + *******************************************************/ + +/* + * IH_CLIENT_TYPE enum + */ + +typedef enum IH_CLIENT_TYPE { +IH_GFX_VMID_CLIENT = 0x00000000, +IH_MM_VMID_CLIENT = 0x00000001, +IH_MULTI_VMID_CLIENT = 0x00000002, +IH_CLIENT_TYPE_RESERVED = 0x00000003, +} IH_CLIENT_TYPE; + +/* + * IH_INTERFACE_TYPE enum + */ + +typedef enum IH_INTERFACE_TYPE { +IH_LEGACY_INTERFACE = 0x00000000, +IH_REGISTER_WRITE_INTERFACE = 0x00000001, +} IH_INTERFACE_TYPE; + +/* + * IH_PERF_SEL enum + */ + +typedef enum IH_PERF_SEL { +IH_PERF_SEL_CYCLE = 0x00000000, +IH_PERF_SEL_IDLE = 0x00000001, +IH_PERF_SEL_INPUT_IDLE = 0x00000002, +IH_PERF_SEL_BUFFER_IDLE = 0x00000003, +IH_PERF_SEL_RB0_FULL = 0x00000004, +IH_PERF_SEL_RB0_OVERFLOW = 0x00000005, +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006, +IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007, +IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008, +IH_PERF_SEL_MC_WR_IDLE = 0x00000009, +IH_PERF_SEL_MC_WR_COUNT = 0x0000000a, +IH_PERF_SEL_MC_WR_STALL = 0x0000000b, +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c, +IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d, +IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e, +IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f, +IH_PERF_SEL_RB1_FULL = 0x00000010, +IH_PERF_SEL_RB1_OVERFLOW = 0x00000011, +IH_PERF_SEL_COOKIE_REC_ERROR = 0x00000012, +IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013, +IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014, +IH_PERF_SEL_RB2_FULL = 0x00000015, +IH_PERF_SEL_RB2_OVERFLOW = 0x00000016, +IH_PERF_SEL_CLIENT_CREDIT_ERROR = 0x00000017, +IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018, +IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019, +IH_PERF_SEL_STORM_CLIENT_INT_DROP = 0x0000001a, +IH_PERF_SEL_SELF_IV_VALID = 0x0000001b, +IH_PERF_SEL_BUFFER_FIFO_FULL = 0x0000001c, +IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001d, +IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001e, +IH_PERF_SEL_RB0_FULL_VF2 = 0x0000001f, +IH_PERF_SEL_RB0_FULL_VF3 = 0x00000020, +IH_PERF_SEL_RB0_FULL_VF4 = 0x00000021, +IH_PERF_SEL_RB0_FULL_VF5 = 0x00000022, +IH_PERF_SEL_RB0_FULL_VF6 = 0x00000023, +IH_PERF_SEL_RB0_FULL_VF7 = 0x00000024, +IH_PERF_SEL_RB0_FULL_VF8 = 0x00000025, +IH_PERF_SEL_RB0_FULL_VF9 = 0x00000026, +IH_PERF_SEL_RB0_FULL_VF10 = 0x00000027, +IH_PERF_SEL_RB0_FULL_VF11 = 0x00000028, +IH_PERF_SEL_RB0_FULL_VF12 = 0x00000029, +IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002a, +IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002b, +IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002c, +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002d, +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002e, +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x0000002f, +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000030, +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000031, +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000032, +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000033, +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000034, +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000035, +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000036, +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000037, +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000038, +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x00000039, +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003a, +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003b, +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003c, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003d, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003e, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x0000003f, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000040, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000041, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000042, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000043, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000044, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000045, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000046, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000047, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000048, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x00000049, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004a, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004b, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004c, +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004d, +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004e, +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x0000004f, +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000050, +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000051, +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000052, +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000053, +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000054, +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000055, +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000056, +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000057, +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000058, +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x00000059, +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005a, +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005b, +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005c, +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005d, +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005e, +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x0000005f, +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000060, +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000061, +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000062, +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000063, +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000064, +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000065, +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000066, +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000067, +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000068, +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x00000069, +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006a, +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006b, +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006c, +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006d, +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006e, +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x0000006f, +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000070, +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000071, +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000072, +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000073, +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000074, +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000075, +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000076, +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000077, +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000078, +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x00000079, +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007a, +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007b, +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007c, +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007d, +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007e, +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x0000007f, +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000080, +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000081, +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000082, +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000083, +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000084, +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000085, +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000086, +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000087, +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000088, +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x00000089, +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008a, +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008b, +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008c, +IH_PERF_SEL_CLIENT0_INT = 0x0000008d, +IH_PERF_SEL_CLIENT1_INT = 0x0000008e, +IH_PERF_SEL_CLIENT2_INT = 0x0000008f, +IH_PERF_SEL_CLIENT3_INT = 0x00000090, +IH_PERF_SEL_CLIENT4_INT = 0x00000091, +IH_PERF_SEL_CLIENT5_INT = 0x00000092, +IH_PERF_SEL_CLIENT6_INT = 0x00000093, +IH_PERF_SEL_CLIENT7_INT = 0x00000094, +IH_PERF_SEL_CLIENT8_INT = 0x00000095, +IH_PERF_SEL_CLIENT9_INT = 0x00000096, +IH_PERF_SEL_CLIENT10_INT = 0x00000097, +IH_PERF_SEL_CLIENT11_INT = 0x00000098, +IH_PERF_SEL_CLIENT12_INT = 0x00000099, +IH_PERF_SEL_CLIENT13_INT = 0x0000009a, +IH_PERF_SEL_CLIENT14_INT = 0x0000009b, +IH_PERF_SEL_CLIENT15_INT = 0x0000009c, +IH_PERF_SEL_CLIENT16_INT = 0x0000009d, +IH_PERF_SEL_CLIENT17_INT = 0x0000009e, +IH_PERF_SEL_CLIENT18_INT = 0x0000009f, +IH_PERF_SEL_CLIENT19_INT = 0x000000a0, +IH_PERF_SEL_CLIENT20_INT = 0x000000a1, +IH_PERF_SEL_CLIENT21_INT = 0x000000a2, +IH_PERF_SEL_CLIENT22_INT = 0x000000a3, +IH_PERF_SEL_CLIENT23_INT = 0x000000a4, +IH_PERF_SEL_CLIENT24_INT = 0x000000a5, +IH_PERF_SEL_CLIENT25_INT = 0x000000a6, +IH_PERF_SEL_CLIENT26_INT = 0x000000a7, +IH_PERF_SEL_CLIENT27_INT = 0x000000a8, +IH_PERF_SEL_CLIENT28_INT = 0x000000a9, +IH_PERF_SEL_CLIENT29_INT = 0x000000aa, +IH_PERF_SEL_CLIENT30_INT = 0x000000ab, +IH_PERF_SEL_CLIENT31_INT = 0x000000ac, +IH_PERF_SEL_RB1_FULL_VF0 = 0x000000ad, +IH_PERF_SEL_RB1_FULL_VF1 = 0x000000ae, +IH_PERF_SEL_RB1_FULL_VF2 = 0x000000af, +IH_PERF_SEL_RB1_FULL_VF3 = 0x000000b0, +IH_PERF_SEL_RB1_FULL_VF4 = 0x000000b1, +IH_PERF_SEL_RB1_FULL_VF5 = 0x000000b2, +IH_PERF_SEL_RB1_FULL_VF6 = 0x000000b3, +IH_PERF_SEL_RB1_FULL_VF7 = 0x000000b4, +IH_PERF_SEL_RB1_FULL_VF8 = 0x000000b5, +IH_PERF_SEL_RB1_FULL_VF9 = 0x000000b6, +IH_PERF_SEL_RB1_FULL_VF10 = 0x000000b7, +IH_PERF_SEL_RB1_FULL_VF11 = 0x000000b8, +IH_PERF_SEL_RB1_FULL_VF12 = 0x000000b9, +IH_PERF_SEL_RB1_FULL_VF13 = 0x000000ba, +IH_PERF_SEL_RB1_FULL_VF14 = 0x000000bb, +IH_PERF_SEL_RB1_FULL_VF15 = 0x000000bc, +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000bd, +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000be, +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000bf, +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000c0, +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000c1, +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000c2, +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000c3, +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000c4, +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000c5, +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000c6, +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000c7, +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000c8, +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000c9, +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000ca, +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000cb, +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000cc, +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x000000cd, +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x000000ce, +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x000000cf, +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x000000d0, +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x000000d1, +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x000000d2, +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x000000d3, +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x000000d4, +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x000000d5, +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x000000d6, +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x000000d7, +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x000000d8, +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x000000d9, +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x000000da, +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x000000db, +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x000000dc, +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x000000dd, +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x000000de, +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x000000df, +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x000000e0, +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x000000e1, +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x000000e2, +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x000000e3, +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x000000e4, +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x000000e5, +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x000000e6, +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x000000e7, +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x000000e8, +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x000000e9, +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x000000ea, +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x000000eb, +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x000000ec, +IH_PERF_SEL_RB2_FULL_VF0 = 0x000000ed, +IH_PERF_SEL_RB2_FULL_VF1 = 0x000000ee, +IH_PERF_SEL_RB2_FULL_VF2 = 0x000000ef, +IH_PERF_SEL_RB2_FULL_VF3 = 0x000000f0, +IH_PERF_SEL_RB2_FULL_VF4 = 0x000000f1, +IH_PERF_SEL_RB2_FULL_VF5 = 0x000000f2, +IH_PERF_SEL_RB2_FULL_VF6 = 0x000000f3, +IH_PERF_SEL_RB2_FULL_VF7 = 0x000000f4, +IH_PERF_SEL_RB2_FULL_VF8 = 0x000000f5, +IH_PERF_SEL_RB2_FULL_VF9 = 0x000000f6, +IH_PERF_SEL_RB2_FULL_VF10 = 0x000000f7, +IH_PERF_SEL_RB2_FULL_VF11 = 0x000000f8, +IH_PERF_SEL_RB2_FULL_VF12 = 0x000000f9, +IH_PERF_SEL_RB2_FULL_VF13 = 0x000000fa, +IH_PERF_SEL_RB2_FULL_VF14 = 0x000000fb, +IH_PERF_SEL_RB2_FULL_VF15 = 0x000000fc, +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x000000fd, +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x000000fe, +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x000000ff, +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x00000100, +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000101, +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000102, +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000103, +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000104, +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000105, +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000106, +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000107, +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000108, +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000109, +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x0000010a, +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000010b, +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000010c, +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000010d, +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000010e, +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000010f, +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x00000110, +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000111, +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000112, +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000113, +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000114, +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000115, +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000116, +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000117, +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000118, +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000119, +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x0000011a, +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000011b, +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000011c, +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000011d, +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000011e, +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000011f, +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x00000120, +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000121, +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000122, +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000123, +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000124, +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000125, +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000126, +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000127, +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000128, +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000129, +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x0000012a, +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000012b, +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000012c, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 0x0000012d, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 0x0000012e, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 0x0000012f, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 0x00000130, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 0x00000131, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 0x00000132, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 0x00000133, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 0x00000134, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 0x00000135, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 0x00000136, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 0x00000137, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 0x00000138, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 0x00000139, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 0x0000013a, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 0x0000013b, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 0x0000013c, +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 0x0000013d, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 0x0000013e, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 0x0000013f, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 0x00000140, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 0x00000141, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 0x00000142, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 0x00000143, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 0x00000144, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 0x00000145, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 0x00000146, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 0x00000147, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 0x00000148, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 0x00000149, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 0x0000014a, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 0x0000014b, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 0x0000014c, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 0x0000014d, +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 0x0000014e, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 0x0000014f, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 0x00000150, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 0x00000151, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 0x00000152, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 0x00000153, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 0x00000154, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 0x00000155, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 0x00000156, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 0x00000157, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 0x00000158, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 0x00000159, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 0x0000015a, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 0x0000015b, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 0x0000015c, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 0x0000015d, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 0x0000015e, +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 0x0000015f, +IH_PERF_SEL_RB0_LOAD_RPTR = 0x00000160, +IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 0x00000161, +IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 0x00000162, +IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 0x00000163, +IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 0x00000164, +IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 0x00000165, +IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 0x00000166, +IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 0x00000167, +IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 0x00000168, +IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 0x00000169, +IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 0x0000016a, +IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 0x0000016b, +IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 0x0000016c, +IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 0x0000016d, +IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 0x0000016e, +IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 0x0000016f, +IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 0x00000170, +IH_PERF_SEL_RB1_LOAD_RPTR = 0x00000171, +IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 0x00000172, +IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 0x00000173, +IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 0x00000174, +IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 0x00000175, +IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 0x00000176, +IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 0x00000177, +IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 0x00000178, +IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 0x00000179, +IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 0x0000017a, +IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 0x0000017b, +IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 0x0000017c, +IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 0x0000017d, +IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 0x0000017e, +IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 0x0000017f, +IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 0x00000180, +IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 0x00000181, +IH_PERF_SEL_RB2_LOAD_RPTR = 0x00000182, +IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 0x00000183, +IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 0x00000184, +IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 0x00000185, +IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 0x00000186, +IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 0x00000187, +IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 0x00000188, +IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 0x00000189, +IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 0x0000018a, +IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 0x0000018b, +IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 0x0000018c, +IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 0x0000018d, +IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 0x0000018e, +IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 0x0000018f, +IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 0x00000190, +IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 0x00000191, +IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 0x00000192, +} IH_PERF_SEL; + +/* + * IH_RING_ID enum + */ + +typedef enum IH_RING_ID { +IH_RING_ID_INTERRUPT = 0x00000000, +IH_RING_ID_REQUEST = 0x00000001, +IH_RING_ID_TRANSLATION = 0x00000002, +IH_RING_ID_RESERVED = 0x00000003, +} IH_RING_ID; + +/* + * IH_VF_RB_SELECT enum + */ + +typedef enum IH_VF_RB_SELECT { +IH_VF_RB_SELECT_CLIENT_FCN_ID = 0x00000000, +IH_VF_RB_SELECT_IH_FCN_ID = 0x00000001, +IH_VF_RB_SELECT_PF = 0x00000002, +IH_VF_RB_SELECT_RESERVED = 0x00000003, +} IH_VF_RB_SELECT; + +/******************************************************* + * SEM Enums + *******************************************************/ + +/* + * SEM_PERF_SEL enum + */ + +typedef enum SEM_PERF_SEL { +SEM_PERF_SEL_CYCLE = 0x00000000, +SEM_PERF_SEL_IDLE = 0x00000001, +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, +SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 0x00000004, +SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 0x00000005, +SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000006, +SEM_PERF_SEL_UVD1_REQ_SIGNAL = 0x00000007, +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000008, +SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000009, +SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x0000000a, +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x0000000b, +SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x0000000c, +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000d, +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000e, +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000f, +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x00000010, +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x00000011, +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x00000012, +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000013, +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000014, +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000015, +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000016, +SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000017, +SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000018, +SEM_PERF_SEL_SDMA2_REQ_WAIT = 0x00000019, +SEM_PERF_SEL_SDMA3_REQ_WAIT = 0x0000001a, +SEM_PERF_SEL_UVD_REQ_WAIT = 0x0000001b, +SEM_PERF_SEL_UVD1_REQ_WAIT = 0x0000001c, +SEM_PERF_SEL_VCE0_REQ_WAIT = 0x0000001d, +SEM_PERF_SEL_ACP_REQ_WAIT = 0x0000001e, +SEM_PERF_SEL_ISP_REQ_WAIT = 0x0000001f, +SEM_PERF_SEL_VCE1_REQ_WAIT = 0x00000020, +SEM_PERF_SEL_VP8_REQ_WAIT = 0x00000021, +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x00000022, +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x00000023, +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x00000024, +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x00000025, +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000026, +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000027, +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000028, +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000029, +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x0000002a, +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x0000002b, +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x0000002c, +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x0000002d, +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x0000002e, +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x0000002f, +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x00000030, +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x00000031, +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x00000032, +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x00000033, +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x00000034, +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x00000035, +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000036, +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000037, +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000038, +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000039, +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x0000003a, +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x0000003b, +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x0000003c, +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x0000003d, +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x0000003e, +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x0000003f, +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x00000040, +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x00000041, +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x00000042, +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x00000043, +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x00000044, +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x00000045, +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000046, +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000047, +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000048, +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000049, +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x0000004a, +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x0000004b, +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x0000004c, +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x0000004d, +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x0000004e, +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x0000004f, +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x00000050, +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x00000051, +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x00000052, +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x00000053, +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x00000054, +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x00000055, +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000056, +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000057, +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000058, +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000059, +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x0000005a, +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x0000005b, +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x0000005c, +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x0000005d, +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x0000005e, +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x0000005f, +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x00000060, +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x00000061, +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x00000062, +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x00000063, +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x00000064, +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x00000065, +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000066, +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000067, +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000068, +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000069, +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x0000006a, +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x0000006b, +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x0000006c, +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x0000006d, +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x0000006e, +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x0000006f, +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x00000070, +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x00000071, +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x00000072, +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x00000073, +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x00000074, +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x00000075, +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000076, +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000077, +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000078, +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000079, +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x0000007a, +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x0000007b, +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x0000007c, +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x0000007d, +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x0000007e, +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x0000007f, +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x00000080, +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x00000081, +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x00000082, +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x00000083, +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x00000084, +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x00000085, +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000086, +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000087, +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000088, +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000089, +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x0000008a, +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x0000008b, +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x0000008c, +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x0000008d, +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x0000008e, +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x0000008f, +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x00000090, +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x00000091, +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x00000092, +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x00000093, +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x00000094, +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x00000095, +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000096, +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000097, +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000098, +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000099, +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x0000009a, +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x0000009b, +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x0000009c, +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x0000009d, +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x0000009e, +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x0000009f, +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x000000a0, +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x000000a1, +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x000000a2, +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x000000a3, +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x000000a4, +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x000000a5, +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a6, +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a7, +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a8, +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a9, +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000aa, +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000ab, +SEM_PERF_SEL_MC_RD_REQ = 0x000000ac, +SEM_PERF_SEL_MC_RD_RET = 0x000000ad, +SEM_PERF_SEL_MC_WR_REQ = 0x000000ae, +SEM_PERF_SEL_MC_WR_RET = 0x000000af, +SEM_PERF_SEL_ATC_REQ = 0x000000b0, +SEM_PERF_SEL_ATC_RET = 0x000000b1, +SEM_PERF_SEL_ATC_XNACK = 0x000000b2, +SEM_PERF_SEL_ATC_INVALIDATION = 0x000000b3, +SEM_PERF_SEL_ATC_VM_INVALIDATION = 0x000000b4, +} SEM_PERF_SEL; + +/******************************************************* + * LSDMA Enums + *******************************************************/ + +/* + * LSDMA_PERF_SEL enum + */ + +typedef enum LSDMA_PERF_SEL { +LSDMA_PERF_SEL_CYCLE = 0x00000000, +LSDMA_PERF_SEL_IDLE = 0x00000001, +LSDMA_PERF_SEL_REG_IDLE = 0x00000002, +LSDMA_PERF_SEL_RB_EMPTY = 0x00000003, +LSDMA_PERF_SEL_RB_FULL = 0x00000004, +LSDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, +LSDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, +LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, +LSDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, +LSDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, +LSDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, +LSDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, +LSDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, +LSDMA_PERF_SEL_EX_IDLE = 0x0000000d, +LSDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, +LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, +LSDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, +LSDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, +LSDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, +LSDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, +LSDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, +LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, +LSDMA_PERF_SEL_SEM_IDLE = 0x00000018, +LSDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, +LSDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, +LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, +LSDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, +LSDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, +LSDMA_PERF_SEL_INT_IDLE = 0x0000001e, +LSDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, +LSDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, +LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, +LSDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, +LSDMA_PERF_SEL_NUM_PACKET = 0x00000023, +LSDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, +LSDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, +LSDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, +LSDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, +LSDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, +LSDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, +LSDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, +LSDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, +LSDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, +LSDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, +LSDMA_PERF_SEL_CE_RD_STALL = 0x00000033, +LSDMA_PERF_SEL_CE_WR_STALL = 0x00000034, +LSDMA_PERF_SEL_GFX_SELECT = 0x00000035, +LSDMA_PERF_SEL_RLC0_SELECT = 0x00000036, +LSDMA_PERF_SEL_RLC1_SELECT = 0x00000037, +LSDMA_PERF_SEL_PAGE_SELECT = 0x00000038, +LSDMA_PERF_SEL_CTX_CHANGE = 0x00000039, +LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, +LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, +LSDMA_PERF_SEL_DOORBELL = 0x0000003c, +LSDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, +LSDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, +LSDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, +LSDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, +LSDMA_PERF_SEL_CE_L1_STALL = 0x00000041, +LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042, +LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043, +LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044, +LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045, +LSDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046, +LSDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047, +LSDMA_PERF_SEL_ATCL2_FREE = 0x00000048, +LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049, +LSDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a, +LSDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b, +LSDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c, +LSDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d, +LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e, +LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f, +LSDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050, +LSDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051, +LSDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052, +LSDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053, +LSDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054, +LSDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055, +LSDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056, +LSDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057, +LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058, +LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059, +LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a, +LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b, +LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c, +LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d, +LSDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e, +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 0x0000005f, +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 0x00000060, +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 0x00000061, +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 0x00000062, +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 0x00000063, +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 0x00000064, +LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 0x00000065, +LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 0x00000066, +LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 0x00000067, +LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 0x00000068, +LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 0x00000069, +LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 0x0000006a, +LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000006b, +LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x0000006c, +LSDMA_PERF_SEL_CMD_OP_MATCH = 0x0000006d, +LSDMA_PERF_SEL_CMD_OP_START = 0x0000006e, +LSDMA_PERF_SEL_CMD_OP_END = 0x0000006f, +LSDMA_PERF_SEL_CE_BUSY = 0x00000070, +LSDMA_PERF_SEL_CE_BUSY_START = 0x00000071, +LSDMA_PERF_SEL_CE_BUSY_END = 0x00000072, +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000073, +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000074, +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x00000075, +LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 0x00000076, +LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 0x00000077, +LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 0x00000078, +LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 0x00000079, +LSDMA_PERF_SEL_DRAM_ECC = 0x0000007a, +LSDMA_PERF_SEL_NACK_GEN_ERR = 0x0000007b, +} LSDMA_PERF_SEL; + +/******************************************************* + * SMUIO_ROM Enums + *******************************************************/ + +/* + * ROM_SIGNATURE value + */ + +#define ROM_SIGNATURE 0x0000aa55 + +/******************************************************* + * UVD_EFC Enums + *******************************************************/ + +/* + * EFC_SURFACE_PIXEL_FORMAT enum + */ + +typedef enum EFC_SURFACE_PIXEL_FORMAT { +EFC_ARGB1555 = 0x00000001, +EFC_RGBA5551 = 0x00000002, +EFC_RGB565 = 0x00000003, +EFC_BGR565 = 0x00000004, +EFC_ARGB4444 = 0x00000005, +EFC_RGBA4444 = 0x00000006, +EFC_ARGB8888 = 0x00000008, +EFC_RGBA8888 = 0x00000009, +EFC_ARGB2101010 = 0x0000000a, +EFC_RGBA1010102 = 0x0000000b, +EFC_AYCrCb8888 = 0x0000000c, +EFC_YCrCbA8888 = 0x0000000d, +EFC_ACrYCb8888 = 0x0000000e, +EFC_CrYCbA8888 = 0x0000000f, +EFC_ARGB16161616_10MSB = 0x00000010, +EFC_RGBA16161616_10MSB = 0x00000011, +EFC_ARGB16161616_10LSB = 0x00000012, +EFC_RGBA16161616_10LSB = 0x00000013, +EFC_ARGB16161616_12MSB = 0x00000014, +EFC_RGBA16161616_12MSB = 0x00000015, +EFC_ARGB16161616_12LSB = 0x00000016, +EFC_RGBA16161616_12LSB = 0x00000017, +EFC_ARGB16161616_FLOAT = 0x00000018, +EFC_RGBA16161616_FLOAT = 0x00000019, +EFC_ARGB16161616_UNORM = 0x0000001a, +EFC_RGBA16161616_UNORM = 0x0000001b, +EFC_ARGB16161616_SNORM = 0x0000001c, +EFC_RGBA16161616_SNORM = 0x0000001d, +EFC_AYCrCb16161616_10MSB = 0x00000020, +EFC_AYCrCb16161616_10LSB = 0x00000021, +EFC_YCrCbA16161616_10MSB = 0x00000022, +EFC_YCrCbA16161616_10LSB = 0x00000023, +EFC_ACrYCb16161616_10MSB = 0x00000024, +EFC_ACrYCb16161616_10LSB = 0x00000025, +EFC_CrYCbA16161616_10MSB = 0x00000026, +EFC_CrYCbA16161616_10LSB = 0x00000027, +EFC_AYCrCb16161616_12MSB = 0x00000028, +EFC_AYCrCb16161616_12LSB = 0x00000029, +EFC_YCrCbA16161616_12MSB = 0x0000002a, +EFC_YCrCbA16161616_12LSB = 0x0000002b, +EFC_ACrYCb16161616_12MSB = 0x0000002c, +EFC_ACrYCb16161616_12LSB = 0x0000002d, +EFC_CrYCbA16161616_12MSB = 0x0000002e, +EFC_CrYCbA16161616_12LSB = 0x0000002f, +EFC_Y8_CrCb88_420_PLANAR = 0x00000040, +EFC_Y8_CbCr88_420_PLANAR = 0x00000041, +EFC_Y10_CrCb1010_420_PLANAR = 0x00000042, +EFC_Y10_CbCr1010_420_PLANAR = 0x00000043, +EFC_Y12_CrCb1212_420_PLANAR = 0x00000044, +EFC_Y12_CbCr1212_420_PLANAR = 0x00000045, +EFC_YCrYCb8888_422_PACKED = 0x00000048, +EFC_YCbYCr8888_422_PACKED = 0x00000049, +EFC_CrYCbY8888_422_PACKED = 0x0000004a, +EFC_CbYCrY8888_422_PACKED = 0x0000004b, +EFC_YCrYCb10101010_422_PACKED = 0x0000004c, +EFC_YCbYCr10101010_422_PACKED = 0x0000004d, +EFC_CrYCbY10101010_422_PACKED = 0x0000004e, +EFC_CbYCrY10101010_422_PACKED = 0x0000004f, +EFC_YCrYCb12121212_422_PACKED = 0x00000050, +EFC_YCbYCr12121212_422_PACKED = 0x00000051, +EFC_CrYCbY12121212_422_PACKED = 0x00000052, +EFC_CbYCrY12121212_422_PACKED = 0x00000053, +EFC_RGB111110_FIX = 0x00000070, +EFC_BGR101111_FIX = 0x00000071, +EFC_ACrYCb2101010 = 0x00000072, +EFC_CrYCbA1010102 = 0x00000073, +EFC_RGB111110_FLOAT = 0x00000076, +EFC_BGR101111_FLOAT = 0x00000077, +EFC_MONO_8 = 0x00000078, +EFC_MONO_10MSB = 0x00000079, +EFC_MONO_10LSB = 0x0000007a, +EFC_MONO_12MSB = 0x0000007b, +EFC_MONO_12LSB = 0x0000007c, +EFC_MONO_16 = 0x0000007d, +} EFC_SURFACE_PIXEL_FORMAT; + +#endif /*_soc21_ENUM_HEADER*/ diff --git a/extra/amdpci/headers/v11_structs.h b/extra/amdpci/headers/v11_structs.h new file mode 100644 index 0000000000..cfc28a7599 --- /dev/null +++ b/extra/amdpci/headers/v11_structs.h @@ -0,0 +1,1194 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef V11_STRUCTS_H_ +#define V11_STRUCTS_H_ + +#define uint32_t unsigned int +#define uint8_t unsigned char +#define uint16_t unsigned short +#define uint64_t unsigned long long + +struct v11_gfx_mqd { + uint32_t shadow_base_lo; // offset: 0 (0x0) + uint32_t shadow_base_hi; // offset: 1 (0x1) + uint32_t gds_bkup_base_lo; // offset: 2 (0x2) + uint32_t gds_bkup_base_hi; // offset: 3 (0x3) + uint32_t fw_work_area_base_lo; // offset: 4 (0x4) + uint32_t fw_work_area_base_hi; // offset: 5 (0x5) + uint32_t shadow_initialized; // offset: 6 (0x6) + uint32_t ib_vmid; // offset: 7 (0x7) + uint32_t reserved_8; // offset: 8 (0x8) + uint32_t reserved_9; // offset: 9 (0x9) + uint32_t reserved_10; // offset: 10 (0xA) + uint32_t reserved_11; // offset: 11 (0xB) + uint32_t reserved_12; // offset: 12 (0xC) + uint32_t reserved_13; // offset: 13 (0xD) + uint32_t reserved_14; // offset: 14 (0xE) + uint32_t reserved_15; // offset: 15 (0xF) + uint32_t reserved_16; // offset: 16 (0x10) + uint32_t reserved_17; // offset: 17 (0x11) + uint32_t reserved_18; // offset: 18 (0x12) + uint32_t reserved_19; // offset: 19 (0x13) + uint32_t reserved_20; // offset: 20 (0x14) + uint32_t reserved_21; // offset: 21 (0x15) + uint32_t reserved_22; // offset: 22 (0x16) + uint32_t reserved_23; // offset: 23 (0x17) + uint32_t reserved_24; // offset: 24 (0x18) + uint32_t reserved_25; // offset: 25 (0x19) + uint32_t reserved_26; // offset: 26 (0x1A) + uint32_t reserved_27; // offset: 27 (0x1B) + uint32_t reserved_28; // offset: 28 (0x1C) + uint32_t reserved_29; // offset: 29 (0x1D) + uint32_t reserved_30; // offset: 30 (0x1E) + uint32_t reserved_31; // offset: 31 (0x1F) + uint32_t reserved_32; // offset: 32 (0x20) + uint32_t reserved_33; // offset: 33 (0x21) + uint32_t reserved_34; // offset: 34 (0x22) + uint32_t reserved_35; // offset: 35 (0x23) + uint32_t reserved_36; // offset: 36 (0x24) + uint32_t reserved_37; // offset: 37 (0x25) + uint32_t reserved_38; // offset: 38 (0x26) + uint32_t reserved_39; // offset: 39 (0x27) + uint32_t reserved_40; // offset: 40 (0x28) + uint32_t reserved_41; // offset: 41 (0x29) + uint32_t reserved_42; // offset: 42 (0x2A) + uint32_t reserved_43; // offset: 43 (0x2B) + uint32_t reserved_44; // offset: 44 (0x2C) + uint32_t reserved_45; // offset: 45 (0x2D) + uint32_t reserved_46; // offset: 46 (0x2E) + uint32_t reserved_47; // offset: 47 (0x2F) + uint32_t reserved_48; // offset: 48 (0x30) + uint32_t reserved_49; // offset: 49 (0x31) + uint32_t reserved_50; // offset: 50 (0x32) + uint32_t reserved_51; // offset: 51 (0x33) + uint32_t reserved_52; // offset: 52 (0x34) + uint32_t reserved_53; // offset: 53 (0x35) + uint32_t reserved_54; // offset: 54 (0x36) + uint32_t reserved_55; // offset: 55 (0x37) + uint32_t reserved_56; // offset: 56 (0x38) + uint32_t reserved_57; // offset: 57 (0x39) + uint32_t reserved_58; // offset: 58 (0x3A) + uint32_t reserved_59; // offset: 59 (0x3B) + uint32_t reserved_60; // offset: 60 (0x3C) + uint32_t reserved_61; // offset: 61 (0x3D) + uint32_t reserved_62; // offset: 62 (0x3E) + uint32_t reserved_63; // offset: 63 (0x3F) + uint32_t reserved_64; // offset: 64 (0x40) + uint32_t reserved_65; // offset: 65 (0x41) + uint32_t reserved_66; // offset: 66 (0x42) + uint32_t reserved_67; // offset: 67 (0x43) + uint32_t reserved_68; // offset: 68 (0x44) + uint32_t reserved_69; // offset: 69 (0x45) + uint32_t reserved_70; // offset: 70 (0x46) + uint32_t reserved_71; // offset: 71 (0x47) + uint32_t reserved_72; // offset: 72 (0x48) + uint32_t reserved_73; // offset: 73 (0x49) + uint32_t reserved_74; // offset: 74 (0x4A) + uint32_t reserved_75; // offset: 75 (0x4B) + uint32_t reserved_76; // offset: 76 (0x4C) + uint32_t reserved_77; // offset: 77 (0x4D) + uint32_t reserved_78; // offset: 78 (0x4E) + uint32_t reserved_79; // offset: 79 (0x4F) + uint32_t reserved_80; // offset: 80 (0x50) + uint32_t reserved_81; // offset: 81 (0x51) + uint32_t reserved_82; // offset: 82 (0x52) + uint32_t reserved_83; // offset: 83 (0x53) + uint32_t checksum_lo; // offset: 84 (0x54) + uint32_t checksum_hi; // offset: 85 (0x55) + uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) + uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) + uint32_t reserved_88; // offset: 88 (0x58) + uint32_t reserved_89; // offset: 89 (0x59) + uint32_t reserved_90; // offset: 90 (0x5A) + uint32_t reserved_91; // offset: 91 (0x5B) + uint32_t cp_mqd_query_wave_count; // offset: 92 (0x5C) + uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93 (0x5D) + uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94 (0x5E) + uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95 (0x5F) + uint32_t reserved_96; // offset: 96 (0x60) + uint32_t reserved_97; // offset: 97 (0x61) + uint32_t reserved_98; // offset: 98 (0x62) + uint32_t reserved_99; // offset: 99 (0x63) + uint32_t reserved_100; // offset: 100 (0x64) + uint32_t reserved_101; // offset: 101 (0x65) + uint32_t reserved_102; // offset: 102 (0x66) + uint32_t reserved_103; // offset: 103 (0x67) + uint32_t control_buf_addr_lo; // offset: 104 (0x68) + uint32_t control_buf_addr_hi; // offset: 105 (0x69) + uint32_t disable_queue; // offset: 106 (0x6A) + uint32_t reserved_107; // offset: 107 (0x6B) + uint32_t reserved_108; // offset: 108 (0x6C) + uint32_t reserved_109; // offset: 109 (0x6D) + uint32_t reserved_110; // offset: 110 (0x6E) + uint32_t reserved_111; // offset: 111 (0x6F) + uint32_t reserved_112; // offset: 112 (0x70) + uint32_t reserved_113; // offset: 113 (0x71) + uint32_t reserved_114; // offset: 114 (0x72) + uint32_t reserved_115; // offset: 115 (0x73) + uint32_t reserved_116; // offset: 116 (0x74) + uint32_t reserved_117; // offset: 117 (0x75) + uint32_t reserved_118; // offset: 118 (0x76) + uint32_t reserved_119; // offset: 119 (0x77) + uint32_t reserved_120; // offset: 120 (0x78) + uint32_t reserved_121; // offset: 121 (0x79) + uint32_t reserved_122; // offset: 122 (0x7A) + uint32_t reserved_123; // offset: 123 (0x7B) + uint32_t reserved_124; // offset: 124 (0x7C) + uint32_t reserved_125; // offset: 125 (0x7D) + uint32_t reserved_126; // offset: 126 (0x7E) + uint32_t reserved_127; // offset: 127 (0x7F) + uint32_t cp_mqd_base_addr; // offset: 128 (0x80) + uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) + uint32_t cp_gfx_hqd_active; // offset: 130 (0x82) + uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83) + uint32_t reserved_131; // offset: 132 (0x84) + uint32_t reserved_132; // offset: 133 (0x85) + uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86) + uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87) + uint32_t cp_gfx_hqd_base; // offset: 136 (0x88) + uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89) + uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A) + uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B) + uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C) + uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D) + uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E) + uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F) + uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90) + uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91) + uint32_t reserved_146; // offset: 146 (0x92) + uint32_t reserved_147; // offset: 147 (0x93) + uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94) + uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95) + uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96) + uint32_t reserved_151; // offset: 151 (0x97) + uint32_t reserved_152; // offset: 152 (0x98) + uint32_t reserved_153; // offset: 153 (0x99) + uint32_t reserved_154; // offset: 154 (0x9A) + uint32_t reserved_155; // offset: 155 (0x9B) + uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C) + uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D) + uint32_t reserved_158; // offset: 158 (0x9E) + uint32_t reserved_159; // offset: 159 (0x9F) + uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0) + uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1) + uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2) + uint32_t reserved_163; // offset: 163 (0xA3) + uint32_t reserved_164; // offset: 164 (0xA4) + uint32_t reserved_165; // offset: 165 (0xA5) + uint32_t reserved_166; // offset: 166 (0xA6) + uint32_t reserved_167; // offset: 167 (0xA7) + uint32_t reserved_168; // offset: 168 (0xA8) + uint32_t reserved_169; // offset: 169 (0xA9) + uint32_t cp_num_prim_needed_count0_lo; // offset: 170 (0xAA) + uint32_t cp_num_prim_needed_count0_hi; // offset: 171 (0xAB) + uint32_t cp_num_prim_needed_count1_lo; // offset: 172 (0xAC) + uint32_t cp_num_prim_needed_count1_hi; // offset: 173 (0xAD) + uint32_t cp_num_prim_needed_count2_lo; // offset: 174 (0xAE) + uint32_t cp_num_prim_needed_count2_hi; // offset: 175 (0xAF) + uint32_t cp_num_prim_needed_count3_lo; // offset: 176 (0xB0) + uint32_t cp_num_prim_needed_count3_hi; // offset: 177 (0xB1) + uint32_t cp_num_prim_written_count0_lo; // offset: 178 (0xB2) + uint32_t cp_num_prim_written_count0_hi; // offset: 179 (0xB3) + uint32_t cp_num_prim_written_count1_lo; // offset: 180 (0xB4) + uint32_t cp_num_prim_written_count1_hi; // offset: 181 (0xB5) + uint32_t cp_num_prim_written_count2_lo; // offset: 182 (0xB6) + uint32_t cp_num_prim_written_count2_hi; // offset: 183 (0xB7) + uint32_t cp_num_prim_written_count3_lo; // offset: 184 (0xB8) + uint32_t cp_num_prim_written_count3_hi; // offset: 185 (0xB9) + uint32_t reserved_186; // offset: 186 (0xBA) + uint32_t reserved_187; // offset: 187 (0xBB) + uint32_t reserved_188; // offset: 188 (0xBC) + uint32_t reserved_189; // offset: 189 (0xBD) + uint32_t mp1_smn_fps_cnt; // offset: 190 (0xBE) + uint32_t sq_thread_trace_buf0_base; // offset: 191 (0xBF) + uint32_t sq_thread_trace_buf0_size; // offset: 192 (0xC0) + uint32_t sq_thread_trace_buf1_base; // offset: 193 (0xC1) + uint32_t sq_thread_trace_buf1_size; // offset: 194 (0xC2) + uint32_t sq_thread_trace_wptr; // offset: 195 (0xC3) + uint32_t sq_thread_trace_mask; // offset: 196 (0xC4) + uint32_t sq_thread_trace_token_mask; // offset: 197 (0xC5) + uint32_t sq_thread_trace_ctrl; // offset: 198 (0xC6) + uint32_t sq_thread_trace_status; // offset: 199 (0xC7) + uint32_t sq_thread_trace_dropped_cntr; // offset: 200 (0xC8) + uint32_t sq_thread_trace_finish_done_debug; // offset: 201 (0xC9) + uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202 (0xCA) + uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203 (0xCB) + uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204 (0xCC) + uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205 (0xCD) + uint32_t reserved_206; // offset: 206 (0xCE) + uint32_t reserved_207; // offset: 207 (0xCF) + uint32_t cp_sc_psinvoc_count0_lo; // offset: 208 (0xD0) + uint32_t cp_sc_psinvoc_count0_hi; // offset: 209 (0xD1) + uint32_t cp_pa_cprim_count_lo; // offset: 210 (0xD2) + uint32_t cp_pa_cprim_count_hi; // offset: 211 (0xD3) + uint32_t cp_pa_cinvoc_count_lo; // offset: 212 (0xD4) + uint32_t cp_pa_cinvoc_count_hi; // offset: 213 (0xD5) + uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214 (0xD6) + uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215 (0xD7) + uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216 (0xD8) + uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217 (0xD9) + uint32_t cp_vgt_gsprim_count_lo; // offset: 218 (0xDA) + uint32_t cp_vgt_gsprim_count_hi; // offset: 219 (0xDB) + uint32_t cp_vgt_iaprim_count_lo; // offset: 220 (0xDC) + uint32_t cp_vgt_iaprim_count_hi; // offset: 221 (0xDD) + uint32_t cp_vgt_iavert_count_lo; // offset: 222 (0xDE) + uint32_t cp_vgt_iavert_count_hi; // offset: 223 (0xDF) + uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224 (0xE0) + uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225 (0xE1) + uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226 (0xE2) + uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227 (0xE3) + uint32_t cp_vgt_csinvoc_count_lo; // offset: 228 (0xE4) + uint32_t cp_vgt_csinvoc_count_hi; // offset: 229 (0xE5) + uint32_t reserved_230; // offset: 230 (0xE6) + uint32_t reserved_231; // offset: 231 (0xE7) + uint32_t reserved_232; // offset: 232 (0xE8) + uint32_t reserved_233; // offset: 233 (0xE9) + uint32_t reserved_234; // offset: 234 (0xEA) + uint32_t reserved_235; // offset: 235 (0xEB) + uint32_t reserved_236; // offset: 236 (0xEC) + uint32_t reserved_237; // offset: 237 (0xED) + uint32_t reserved_238; // offset: 238 (0xEE) + uint32_t reserved_239; // offset: 239 (0xEF) + uint32_t reserved_240; // offset: 240 (0xF0) + uint32_t reserved_241; // offset: 241 (0xF1) + uint32_t reserved_242; // offset: 242 (0xF2) + uint32_t reserved_243; // offset: 243 (0xF3) + uint32_t reserved_244; // offset: 244 (0xF4) + uint32_t reserved_245; // offset: 245 (0xF5) + uint32_t reserved_246; // offset: 246 (0xF6) + uint32_t reserved_247; // offset: 247 (0xF7) + uint32_t reserved_248; // offset: 248 (0xF8) + uint32_t reserved_249; // offset: 249 (0xF9) + uint32_t reserved_250; // offset: 250 (0xFA) + uint32_t reserved_251; // offset: 251 (0xFB) + uint32_t reserved_252; // offset: 252 (0xFC) + uint32_t reserved_253; // offset: 253 (0xFD) + uint32_t reserved_254; // offset: 254 (0xFE) + uint32_t reserved_255; // offset: 255 (0xFF) + uint32_t reserved_256; // offset: 256 (0x100) + uint32_t reserved_257; // offset: 257 (0x101) + uint32_t reserved_258; // offset: 258 (0x102) + uint32_t reserved_259; // offset: 259 (0x103) + uint32_t reserved_260; // offset: 260 (0x104) + uint32_t reserved_261; // offset: 261 (0x105) + uint32_t reserved_262; // offset: 262 (0x106) + uint32_t reserved_263; // offset: 263 (0x107) + uint32_t reserved_264; // offset: 264 (0x108) + uint32_t reserved_265; // offset: 265 (0x109) + uint32_t reserved_266; // offset: 266 (0x10A) + uint32_t reserved_267; // offset: 267 (0x10B) + uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268 (0x10C) + uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269 (0x10D) + uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270 (0x10E) + uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271 (0x10F) + uint32_t reserved_272; // offset: 272 (0x110) + uint32_t reserved_273; // offset: 273 (0x111) + uint32_t reserved_274; // offset: 274 (0x112) + uint32_t reserved_275; // offset: 275 (0x113) + uint32_t vgt_dma_max_size; // offset: 276 (0x114) + uint32_t vgt_dma_num_instances; // offset: 277 (0x115) + uint32_t reserved_278; // offset: 278 (0x116) + uint32_t reserved_279; // offset: 279 (0x117) + uint32_t reserved_280; // offset: 280 (0x118) + uint32_t reserved_281; // offset: 281 (0x119) + uint32_t reserved_282; // offset: 282 (0x11A) + uint32_t reserved_283; // offset: 283 (0x11B) + uint32_t reserved_284; // offset: 284 (0x11C) + uint32_t reserved_285; // offset: 285 (0x11D) + uint32_t reserved_286; // offset: 286 (0x11E) + uint32_t reserved_287; // offset: 287 (0x11F) + uint32_t it_set_base_ib_addr_lo; // offset: 288 (0x120) + uint32_t it_set_base_ib_addr_hi; // offset: 289 (0x121) + uint32_t reserved_290; // offset: 290 (0x122) + uint32_t reserved_291; // offset: 291 (0x123) + uint32_t reserved_292; // offset: 292 (0x124) + uint32_t reserved_293; // offset: 293 (0x125) + uint32_t reserved_294; // offset: 294 (0x126) + uint32_t reserved_295; // offset: 295 (0x127) + uint32_t reserved_296; // offset: 296 (0x128) + uint32_t reserved_297; // offset: 297 (0x129) + uint32_t reserved_298; // offset: 298 (0x12A) + uint32_t reserved_299; // offset: 299 (0x12B) + uint32_t reserved_300; // offset: 300 (0x12C) + uint32_t reserved_301; // offset: 301 (0x12D) + uint32_t reserved_302; // offset: 302 (0x12E) + uint32_t reserved_303; // offset: 303 (0x12F) + uint32_t reserved_304; // offset: 304 (0x130) + uint32_t reserved_305; // offset: 305 (0x131) + uint32_t reserved_306; // offset: 306 (0x132) + uint32_t reserved_307; // offset: 307 (0x133) + uint32_t reserved_308; // offset: 308 (0x134) + uint32_t reserved_309; // offset: 309 (0x135) + uint32_t reserved_310; // offset: 310 (0x136) + uint32_t reserved_311; // offset: 311 (0x137) + uint32_t reserved_312; // offset: 312 (0x138) + uint32_t reserved_313; // offset: 313 (0x139) + uint32_t reserved_314; // offset: 314 (0x13A) + uint32_t reserved_315; // offset: 315 (0x13B) + uint32_t reserved_316; // offset: 316 (0x13C) + uint32_t reserved_317; // offset: 317 (0x13D) + uint32_t reserved_318; // offset: 318 (0x13E) + uint32_t reserved_319; // offset: 319 (0x13F) + uint32_t reserved_320; // offset: 320 (0x140) + uint32_t reserved_321; // offset: 321 (0x141) + uint32_t reserved_322; // offset: 322 (0x142) + uint32_t reserved_323; // offset: 323 (0x143) + uint32_t reserved_324; // offset: 324 (0x144) + uint32_t reserved_325; // offset: 325 (0x145) + uint32_t reserved_326; // offset: 326 (0x146) + uint32_t reserved_327; // offset: 327 (0x147) + uint32_t reserved_328; // offset: 328 (0x148) + uint32_t reserved_329; // offset: 329 (0x149) + uint32_t reserved_330; // offset: 330 (0x14A) + uint32_t reserved_331; // offset: 331 (0x14B) + uint32_t reserved_332; // offset: 332 (0x14C) + uint32_t reserved_333; // offset: 333 (0x14D) + uint32_t reserved_334; // offset: 334 (0x14E) + uint32_t reserved_335; // offset: 335 (0x14F) + uint32_t reserved_336; // offset: 336 (0x150) + uint32_t reserved_337; // offset: 337 (0x151) + uint32_t reserved_338; // offset: 338 (0x152) + uint32_t reserved_339; // offset: 339 (0x153) + uint32_t reserved_340; // offset: 340 (0x154) + uint32_t reserved_341; // offset: 341 (0x155) + uint32_t reserved_342; // offset: 342 (0x156) + uint32_t reserved_343; // offset: 343 (0x157) + uint32_t reserved_344; // offset: 344 (0x158) + uint32_t reserved_345; // offset: 345 (0x159) + uint32_t reserved_346; // offset: 346 (0x15A) + uint32_t reserved_347; // offset: 347 (0x15B) + uint32_t reserved_348; // offset: 348 (0x15C) + uint32_t reserved_349; // offset: 349 (0x15D) + uint32_t reserved_350; // offset: 350 (0x15E) + uint32_t reserved_351; // offset: 351 (0x15F) + uint32_t reserved_352; // offset: 352 (0x160) + uint32_t reserved_353; // offset: 353 (0x161) + uint32_t reserved_354; // offset: 354 (0x162) + uint32_t reserved_355; // offset: 355 (0x163) + uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356 (0x164) + uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357 (0x165) + uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358 (0x166) + uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359 (0x167) + uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360 (0x168) + uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361 (0x169) + uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362 (0x16A) + uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363 (0x16B) + uint32_t db_occlusion_count0_low_00; // offset: 364 (0x16C) + uint32_t db_occlusion_count0_hi_00; // offset: 365 (0x16D) + uint32_t db_occlusion_count1_low_00; // offset: 366 (0x16E) + uint32_t db_occlusion_count1_hi_00; // offset: 367 (0x16F) + uint32_t db_occlusion_count2_low_00; // offset: 368 (0x170) + uint32_t db_occlusion_count2_hi_00; // offset: 369 (0x171) + uint32_t db_occlusion_count3_low_00; // offset: 370 (0x172) + uint32_t db_occlusion_count3_hi_00; // offset: 371 (0x173) + uint32_t db_occlusion_count0_low_01; // offset: 372 (0x174) + uint32_t db_occlusion_count0_hi_01; // offset: 373 (0x175) + uint32_t db_occlusion_count1_low_01; // offset: 374 (0x176) + uint32_t db_occlusion_count1_hi_01; // offset: 375 (0x177) + uint32_t db_occlusion_count2_low_01; // offset: 376 (0x178) + uint32_t db_occlusion_count2_hi_01; // offset: 377 (0x179) + uint32_t db_occlusion_count3_low_01; // offset: 378 (0x17A) + uint32_t db_occlusion_count3_hi_01; // offset: 379 (0x17B) + uint32_t db_occlusion_count0_low_02; // offset: 380 (0x17C) + uint32_t db_occlusion_count0_hi_02; // offset: 381 (0x17D) + uint32_t db_occlusion_count1_low_02; // offset: 382 (0x17E) + uint32_t db_occlusion_count1_hi_02; // offset: 383 (0x17F) + uint32_t db_occlusion_count2_low_02; // offset: 384 (0x180) + uint32_t db_occlusion_count2_hi_02; // offset: 385 (0x181) + uint32_t db_occlusion_count3_low_02; // offset: 386 (0x182) + uint32_t db_occlusion_count3_hi_02; // offset: 387 (0x183) + uint32_t db_occlusion_count0_low_03; // offset: 388 (0x184) + uint32_t db_occlusion_count0_hi_03; // offset: 389 (0x185) + uint32_t db_occlusion_count1_low_03; // offset: 390 (0x186) + uint32_t db_occlusion_count1_hi_03; // offset: 391 (0x187) + uint32_t db_occlusion_count2_low_03; // offset: 392 (0x188) + uint32_t db_occlusion_count2_hi_03; // offset: 393 (0x189) + uint32_t db_occlusion_count3_low_03; // offset: 394 (0x18A) + uint32_t db_occlusion_count3_hi_03; // offset: 395 (0x18B) + uint32_t db_occlusion_count0_low_04; // offset: 396 (0x18C) + uint32_t db_occlusion_count0_hi_04; // offset: 397 (0x18D) + uint32_t db_occlusion_count1_low_04; // offset: 398 (0x18E) + uint32_t db_occlusion_count1_hi_04; // offset: 399 (0x18F) + uint32_t db_occlusion_count2_low_04; // offset: 400 (0x190) + uint32_t db_occlusion_count2_hi_04; // offset: 401 (0x191) + uint32_t db_occlusion_count3_low_04; // offset: 402 (0x192) + uint32_t db_occlusion_count3_hi_04; // offset: 403 (0x193) + uint32_t db_occlusion_count0_low_05; // offset: 404 (0x194) + uint32_t db_occlusion_count0_hi_05; // offset: 405 (0x195) + uint32_t db_occlusion_count1_low_05; // offset: 406 (0x196) + uint32_t db_occlusion_count1_hi_05; // offset: 407 (0x197) + uint32_t db_occlusion_count2_low_05; // offset: 408 (0x198) + uint32_t db_occlusion_count2_hi_05; // offset: 409 (0x199) + uint32_t db_occlusion_count3_low_05; // offset: 410 (0x19A) + uint32_t db_occlusion_count3_hi_05; // offset: 411 (0x19B) + uint32_t db_occlusion_count0_low_06; // offset: 412 (0x19C) + uint32_t db_occlusion_count0_hi_06; // offset: 413 (0x19D) + uint32_t db_occlusion_count1_low_06; // offset: 414 (0x19E) + uint32_t db_occlusion_count1_hi_06; // offset: 415 (0x19F) + uint32_t db_occlusion_count2_low_06; // offset: 416 (0x1A0) + uint32_t db_occlusion_count2_hi_06; // offset: 417 (0x1A1) + uint32_t db_occlusion_count3_low_06; // offset: 418 (0x1A2) + uint32_t db_occlusion_count3_hi_06; // offset: 419 (0x1A3) + uint32_t db_occlusion_count0_low_07; // offset: 420 (0x1A4) + uint32_t db_occlusion_count0_hi_07; // offset: 421 (0x1A5) + uint32_t db_occlusion_count1_low_07; // offset: 422 (0x1A6) + uint32_t db_occlusion_count1_hi_07; // offset: 423 (0x1A7) + uint32_t db_occlusion_count2_low_07; // offset: 424 (0x1A8) + uint32_t db_occlusion_count2_hi_07; // offset: 425 (0x1A9) + uint32_t db_occlusion_count3_low_07; // offset: 426 (0x1AA) + uint32_t db_occlusion_count3_hi_07; // offset: 427 (0x1AB) + uint32_t db_occlusion_count0_low_10; // offset: 428 (0x1AC) + uint32_t db_occlusion_count0_hi_10; // offset: 429 (0x1AD) + uint32_t db_occlusion_count1_low_10; // offset: 430 (0x1AE) + uint32_t db_occlusion_count1_hi_10; // offset: 431 (0x1AF) + uint32_t db_occlusion_count2_low_10; // offset: 432 (0x1B0) + uint32_t db_occlusion_count2_hi_10; // offset: 433 (0x1B1) + uint32_t db_occlusion_count3_low_10; // offset: 434 (0x1B2) + uint32_t db_occlusion_count3_hi_10; // offset: 435 (0x1B3) + uint32_t db_occlusion_count0_low_11; // offset: 436 (0x1B4) + uint32_t db_occlusion_count0_hi_11; // offset: 437 (0x1B5) + uint32_t db_occlusion_count1_low_11; // offset: 438 (0x1B6) + uint32_t db_occlusion_count1_hi_11; // offset: 439 (0x1B7) + uint32_t db_occlusion_count2_low_11; // offset: 440 (0x1B8) + uint32_t db_occlusion_count2_hi_11; // offset: 441 (0x1B9) + uint32_t db_occlusion_count3_low_11; // offset: 442 (0x1BA) + uint32_t db_occlusion_count3_hi_11; // offset: 443 (0x1BB) + uint32_t db_occlusion_count0_low_12; // offset: 444 (0x1BC) + uint32_t db_occlusion_count0_hi_12; // offset: 445 (0x1BD) + uint32_t db_occlusion_count1_low_12; // offset: 446 (0x1BE) + uint32_t db_occlusion_count1_hi_12; // offset: 447 (0x1BF) + uint32_t db_occlusion_count2_low_12; // offset: 448 (0x1C0) + uint32_t db_occlusion_count2_hi_12; // offset: 449 (0x1C1) + uint32_t db_occlusion_count3_low_12; // offset: 450 (0x1C2) + uint32_t db_occlusion_count3_hi_12; // offset: 451 (0x1C3) + uint32_t db_occlusion_count0_low_13; // offset: 452 (0x1C4) + uint32_t db_occlusion_count0_hi_13; // offset: 453 (0x1C5) + uint32_t db_occlusion_count1_low_13; // offset: 454 (0x1C6) + uint32_t db_occlusion_count1_hi_13; // offset: 455 (0x1C7) + uint32_t db_occlusion_count2_low_13; // offset: 456 (0x1C8) + uint32_t db_occlusion_count2_hi_13; // offset: 457 (0x1C9) + uint32_t db_occlusion_count3_low_13; // offset: 458 (0x1CA) + uint32_t db_occlusion_count3_hi_13; // offset: 459 (0x1CB) + uint32_t db_occlusion_count0_low_14; // offset: 460 (0x1CC) + uint32_t db_occlusion_count0_hi_14; // offset: 461 (0x1CD) + uint32_t db_occlusion_count1_low_14; // offset: 462 (0x1CE) + uint32_t db_occlusion_count1_hi_14; // offset: 463 (0x1CF) + uint32_t db_occlusion_count2_low_14; // offset: 464 (0x1D0) + uint32_t db_occlusion_count2_hi_14; // offset: 465 (0x1D1) + uint32_t db_occlusion_count3_low_14; // offset: 466 (0x1D2) + uint32_t db_occlusion_count3_hi_14; // offset: 467 (0x1D3) + uint32_t db_occlusion_count0_low_15; // offset: 468 (0x1D4) + uint32_t db_occlusion_count0_hi_15; // offset: 469 (0x1D5) + uint32_t db_occlusion_count1_low_15; // offset: 470 (0x1D6) + uint32_t db_occlusion_count1_hi_15; // offset: 471 (0x1D7) + uint32_t db_occlusion_count2_low_15; // offset: 472 (0x1D8) + uint32_t db_occlusion_count2_hi_15; // offset: 473 (0x1D9) + uint32_t db_occlusion_count3_low_15; // offset: 474 (0x1DA) + uint32_t db_occlusion_count3_hi_15; // offset: 475 (0x1DB) + uint32_t db_occlusion_count0_low_16; // offset: 476 (0x1DC) + uint32_t db_occlusion_count0_hi_16; // offset: 477 (0x1DD) + uint32_t db_occlusion_count1_low_16; // offset: 478 (0x1DE) + uint32_t db_occlusion_count1_hi_16; // offset: 479 (0x1DF) + uint32_t db_occlusion_count2_low_16; // offset: 480 (0x1E0) + uint32_t db_occlusion_count2_hi_16; // offset: 481 (0x1E1) + uint32_t db_occlusion_count3_low_16; // offset: 482 (0x1E2) + uint32_t db_occlusion_count3_hi_16; // offset: 483 (0x1E3) + uint32_t db_occlusion_count0_low_17; // offset: 484 (0x1E4) + uint32_t db_occlusion_count0_hi_17; // offset: 485 (0x1E5) + uint32_t db_occlusion_count1_low_17; // offset: 486 (0x1E6) + uint32_t db_occlusion_count1_hi_17; // offset: 487 (0x1E7) + uint32_t db_occlusion_count2_low_17; // offset: 488 (0x1E8) + uint32_t db_occlusion_count2_hi_17; // offset: 489 (0x1E9) + uint32_t db_occlusion_count3_low_17; // offset: 490 (0x1EA) + uint32_t db_occlusion_count3_hi_17; // offset: 491 (0x1EB) + uint32_t reserved_492; // offset: 492 (0x1EC) + uint32_t reserved_493; // offset: 493 (0x1ED) + uint32_t reserved_494; // offset: 494 (0x1EE) + uint32_t reserved_495; // offset: 495 (0x1EF) + uint32_t reserved_496; // offset: 496 (0x1F0) + uint32_t reserved_497; // offset: 497 (0x1F1) + uint32_t reserved_498; // offset: 498 (0x1F2) + uint32_t reserved_499; // offset: 499 (0x1F3) + uint32_t reserved_500; // offset: 500 (0x1F4) + uint32_t reserved_501; // offset: 501 (0x1F5) + uint32_t reserved_502; // offset: 502 (0x1F6) + uint32_t reserved_503; // offset: 503 (0x1F7) + uint32_t reserved_504; // offset: 504 (0x1F8) + uint32_t reserved_505; // offset: 505 (0x1F9) + uint32_t reserved_506; // offset: 506 (0x1FA) + uint32_t reserved_507; // offset: 507 (0x1FB) + uint32_t reserved_508; // offset: 508 (0x1FC) + uint32_t reserved_509; // offset: 509 (0x1FD) + uint32_t reserved_510; // offset: 510 (0x1FE) + uint32_t reserved_511; // offset: 511 (0x1FF) +}; + +struct v11_sdma_mqd { + uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0) + uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1) + uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2) + uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3) + uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4 (0x4) + uint32_t sdmax_rlcx_rb_wptr; // offset: 5 (0x5) + uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6 (0x6) + uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 7 (0x7) + uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 8 (0x8) + uint32_t sdmax_rlcx_ib_cntl; // offset: 9 (0x9) + uint32_t sdmax_rlcx_ib_rptr; // offset: 10 (0xA) + uint32_t sdmax_rlcx_ib_offset; // offset: 11 (0xB) + uint32_t sdmax_rlcx_ib_base_lo; // offset: 12 (0xC) + uint32_t sdmax_rlcx_ib_base_hi; // offset: 13 (0xD) + uint32_t sdmax_rlcx_ib_size; // offset: 14 (0xE) + uint32_t sdmax_rlcx_skip_cntl; // offset: 15 (0xF) + uint32_t sdmax_rlcx_context_status; // offset: 16 (0x10) + uint32_t sdmax_rlcx_doorbell; // offset: 17 (0x11) + uint32_t sdmax_rlcx_doorbell_log; // offset: 18 (0x12) + uint32_t sdmax_rlcx_doorbell_offset; // offset: 19 (0x13) + uint32_t sdmax_rlcx_csa_addr_lo; // offset: 20 (0x14) + uint32_t sdmax_rlcx_csa_addr_hi; // offset: 21 (0x15) + uint32_t sdmax_rlcx_sched_cntl; // offset: 22 (0x16) + uint32_t sdmax_rlcx_ib_sub_remain; // offset: 23 (0x17) + uint32_t sdmax_rlcx_preempt; // offset: 24 (0x18) + uint32_t sdmax_rlcx_dummy_reg; // offset: 25 (0x19) + uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 26 (0x1A) + uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 27 (0x1B) + uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 28 (0x1C) + uint32_t sdmax_rlcx_minor_ptr_update; // offset: 29 (0x1D) + uint32_t sdmax_rlcx_rb_preempt; // offset: 30 (0x1E) + uint32_t sdmax_rlcx_midcmd_data0; // offset: 31 (0x1F) + uint32_t sdmax_rlcx_midcmd_data1; // offset: 32 (0x20) + uint32_t sdmax_rlcx_midcmd_data2; // offset: 33 (0x21) + uint32_t sdmax_rlcx_midcmd_data3; // offset: 34 (0x22) + uint32_t sdmax_rlcx_midcmd_data4; // offset: 35 (0x23) + uint32_t sdmax_rlcx_midcmd_data5; // offset: 36 (0x24) + uint32_t sdmax_rlcx_midcmd_data6; // offset: 37 (0x25) + uint32_t sdmax_rlcx_midcmd_data7; // offset: 38 (0x26) + uint32_t sdmax_rlcx_midcmd_data8; // offset: 39 (0x27) + uint32_t sdmax_rlcx_midcmd_data9; // offset: 40 (0x28) + uint32_t sdmax_rlcx_midcmd_data10; // offset: 41 (0x29) + uint32_t sdmax_rlcx_midcmd_cntl; // offset: 42 (0x2A) + uint32_t sdmax_rlcx_f32_dbg0; // offset: 43 (0x2B) + uint32_t sdmax_rlcx_f32_dbg1; // offset: 44 (0x2C) + uint32_t reserved_45; // offset: 45 (0x2D) + uint32_t reserved_46; // offset: 46 (0x2E) + uint32_t reserved_47; // offset: 47 (0x2F) + uint32_t reserved_48; // offset: 48 (0x30) + uint32_t reserved_49; // offset: 49 (0x31) + uint32_t reserved_50; // offset: 50 (0x32) + uint32_t reserved_51; // offset: 51 (0x33) + uint32_t reserved_52; // offset: 52 (0x34) + uint32_t reserved_53; // offset: 53 (0x35) + uint32_t reserved_54; // offset: 54 (0x36) + uint32_t reserved_55; // offset: 55 (0x37) + uint32_t reserved_56; // offset: 56 (0x38) + uint32_t reserved_57; // offset: 57 (0x39) + uint32_t reserved_58; // offset: 58 (0x3A) + uint32_t reserved_59; // offset: 59 (0x3B) + uint32_t reserved_60; // offset: 60 (0x3C) + uint32_t reserved_61; // offset: 61 (0x3D) + uint32_t reserved_62; // offset: 62 (0x3E) + uint32_t reserved_63; // offset: 63 (0x3F) + uint32_t reserved_64; // offset: 64 (0x40) + uint32_t reserved_65; // offset: 65 (0x41) + uint32_t reserved_66; // offset: 66 (0x42) + uint32_t reserved_67; // offset: 67 (0x43) + uint32_t reserved_68; // offset: 68 (0x44) + uint32_t reserved_69; // offset: 69 (0x45) + uint32_t reserved_70; // offset: 70 (0x46) + uint32_t reserved_71; // offset: 0 (0x47) + uint32_t reserved_72; // offset: 1 (0x48) + uint32_t reserved_73; // offset: 2 (0x49) + uint32_t reserved_74; // offset: 3 (0x4A) + uint32_t reserved_75; // offset: 4 (0x4B) + uint32_t reserved_76; // offset: 5 (0x4C) + uint32_t reserved_77; // offset: 6 (0x4D) + uint32_t reserved_78; // offset: 7 (0x4E) + uint32_t reserved_79; // offset: 79 (0x4F) + uint32_t reserved_80; // offset: 80 (0x50) + uint32_t reserved_81; // offset: 81 (0x51) + uint32_t reserved_82; // offset: 82 (0x52) + uint32_t reserved_83; // offset: 83 (0x53) + uint32_t reserved_84; // offset: 84 (0x54) + uint32_t reserved_85; // offset: 85 (0x55) + uint32_t reserved_86; // offset: 86 (0x56) + uint32_t reserved_87; // offset: 87 (0x57) + uint32_t reserved_88; // offset: 88 (0x58) + uint32_t reserved_89; // offset: 89 (0x59) + uint32_t reserved_90; // offset: 90 (0x5A) + uint32_t reserved_91; // offset: 91 (0x5B) + uint32_t reserved_92; // offset: 92 (0x5C) + uint32_t reserved_93; // offset: 93 (0x5D) + uint32_t reserved_94; // offset: 94 (0x5E) + uint32_t reserved_95; // offset: 95 (0x5F) + uint32_t reserved_96; // offset: 96 (0x60) + uint32_t reserved_97; // offset: 97 (0x61) + uint32_t reserved_98; // offset: 98 (0x62) + uint32_t reserved_99; // offset: 99 (0x63) + uint32_t reserved_100; // offset: 100 (0x64) + uint32_t reserved_101; // offset: 101 (0x65) + uint32_t reserved_102; // offset: 102 (0x66) + uint32_t reserved_103; // offset: 103 (0x67) + uint32_t reserved_104; // offset: 104 (0x68) + uint32_t reserved_105; // offset: 105 (0x69) + uint32_t reserved_106; // offset: 106 (0x6A) + uint32_t reserved_107; // offset: 107 (0x6B) + uint32_t reserved_108; // offset: 108 (0x6C) + uint32_t reserved_109; // offset: 109 (0x6D) + uint32_t reserved_110; // offset: 110 (0x6E) + uint32_t reserved_111; // offset: 111 (0x6F) + uint32_t reserved_112; // offset: 112 (0x70) + uint32_t reserved_113; // offset: 113 (0x71) + uint32_t reserved_114; // offset: 114 (0x72) + uint32_t reserved_115; // offset: 115 (0x73) + uint32_t reserved_116; // offset: 116 (0x74) + uint32_t reserved_117; // offset: 117 (0x75) + uint32_t reserved_118; // offset: 118 (0x76) + uint32_t reserved_119; // offset: 119 (0x77) + uint32_t reserved_120; // offset: 120 (0x78) + uint32_t reserved_121; // offset: 121 (0x79) + uint32_t reserved_122; // offset: 122 (0x7A) + uint32_t reserved_123; // offset: 123 (0x7B) + uint32_t reserved_124; // offset: 124 (0x7C) + uint32_t reserved_125; // offset: 125 (0x7D) + /* reserved_126,127: repurposed for driver-internal use */ + uint32_t sdma_engine_id; + uint32_t sdma_queue_id; +}; + +struct v11_compute_mqd { + uint32_t header; // offset: 0 (0x0) + uint32_t compute_dispatch_initiator; // offset: 1 (0x1) + uint32_t compute_dim_x; // offset: 2 (0x2) + uint32_t compute_dim_y; // offset: 3 (0x3) + uint32_t compute_dim_z; // offset: 4 (0x4) + uint32_t compute_start_x; // offset: 5 (0x5) + uint32_t compute_start_y; // offset: 6 (0x6) + uint32_t compute_start_z; // offset: 7 (0x7) + uint32_t compute_num_thread_x; // offset: 8 (0x8) + uint32_t compute_num_thread_y; // offset: 9 (0x9) + uint32_t compute_num_thread_z; // offset: 10 (0xA) + uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) + uint32_t compute_perfcount_enable; // offset: 12 (0xC) + uint32_t compute_pgm_lo; // offset: 13 (0xD) + uint32_t compute_pgm_hi; // offset: 14 (0xE) + uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) + uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) + uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) + uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) + uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) + uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) + uint32_t compute_vmid; // offset: 21 (0x15) + uint32_t compute_resource_limits; // offset: 22 (0x16) + uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17) + uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18) + uint32_t compute_tmpring_size; // offset: 25 (0x19) + uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A) + uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B) + uint32_t compute_restart_x; // offset: 28 (0x1C) + uint32_t compute_restart_y; // offset: 29 (0x1D) + uint32_t compute_restart_z; // offset: 30 (0x1E) + uint32_t compute_thread_trace_enable; // offset: 31 (0x1F) + uint32_t compute_misc_reserved; // offset: 32 (0x20) + uint32_t compute_dispatch_id; // offset: 33 (0x21) + uint32_t compute_threadgroup_id; // offset: 34 (0x22) + uint32_t compute_req_ctrl; // offset: 35 (0x23) + uint32_t reserved_36; // offset: 36 (0x24) + uint32_t compute_user_accum_0; // offset: 37 (0x25) + uint32_t compute_user_accum_1; // offset: 38 (0x26) + uint32_t compute_user_accum_2; // offset: 39 (0x27) + uint32_t compute_user_accum_3; // offset: 40 (0x28) + uint32_t compute_pgm_rsrc3; // offset: 41 (0x29) + uint32_t compute_ddid_index; // offset: 42 (0x2A) + uint32_t compute_shader_chksum; // offset: 43 (0x2B) + uint32_t compute_static_thread_mgmt_se4; // offset: 44 (0x2C) + uint32_t compute_static_thread_mgmt_se5; // offset: 45 (0x2D) + uint32_t compute_static_thread_mgmt_se6; // offset: 46 (0x2E) + uint32_t compute_static_thread_mgmt_se7; // offset: 47 (0x2F) + uint32_t compute_dispatch_interleave; // offset: 48 (0x30) + uint32_t compute_relaunch; // offset: 49 (0x31) + uint32_t compute_wave_restore_addr_lo; // offset: 50 (0x32) + uint32_t compute_wave_restore_addr_hi; // offset: 51 (0x33) + uint32_t compute_wave_restore_control; // offset: 52 (0x34) + uint32_t reserved_53; // offset: 53 (0x35) + uint32_t reserved_54; // offset: 54 (0x36) + uint32_t reserved_55; // offset: 55 (0x37) + uint32_t reserved_56; // offset: 56 (0x38) + uint32_t reserved_57; // offset: 57 (0x39) + uint32_t reserved_58; // offset: 58 (0x3A) + uint32_t reserved_59; // offset: 59 (0x3B) + uint32_t reserved_60; // offset: 60 (0x3C) + uint32_t reserved_61; // offset: 61 (0x3D) + uint32_t reserved_62; // offset: 62 (0x3E) + uint32_t reserved_63; // offset: 63 (0x3F) + uint32_t reserved_64; // offset: 64 (0x40) + uint32_t compute_user_data_0; // offset: 65 (0x41) + uint32_t compute_user_data_1; // offset: 66 (0x42) + uint32_t compute_user_data_2; // offset: 67 (0x43) + uint32_t compute_user_data_3; // offset: 68 (0x44) + uint32_t compute_user_data_4; // offset: 69 (0x45) + uint32_t compute_user_data_5; // offset: 70 (0x46) + uint32_t compute_user_data_6; // offset: 71 (0x47) + uint32_t compute_user_data_7; // offset: 72 (0x48) + uint32_t compute_user_data_8; // offset: 73 (0x49) + uint32_t compute_user_data_9; // offset: 74 (0x4A) + uint32_t compute_user_data_10; // offset: 75 (0x4B) + uint32_t compute_user_data_11; // offset: 76 (0x4C) + uint32_t compute_user_data_12; // offset: 77 (0x4D) + uint32_t compute_user_data_13; // offset: 78 (0x4E) + uint32_t compute_user_data_14; // offset: 79 (0x4F) + uint32_t compute_user_data_15; // offset: 80 (0x50) + uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51) + uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52) + uint32_t reserved_83; // offset: 83 (0x53) + uint32_t reserved_84; // offset: 84 (0x54) + uint32_t reserved_85; // offset: 85 (0x55) + uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) + uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) + uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58) + uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59) + uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A) + uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B) + uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C) + uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D) + uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E) + uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F) + uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60) + uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61) + uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62) + uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63) + uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64) + uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65) + uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66) + uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67) + uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68) + uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69) + uint32_t disable_queue; // offset: 106 (0x6A) + uint32_t reserved_107; // offset: 107 (0x6B) + uint32_t gds_cs_ctxsw_cnt0; // offset: 108 (0x6C) + uint32_t gds_cs_ctxsw_cnt1; // offset: 109 (0x6D) + uint32_t gds_cs_ctxsw_cnt2; // offset: 110 (0x6E) + uint32_t gds_cs_ctxsw_cnt3; // offset: 111 (0x6F) + uint32_t reserved_112; // offset: 112 (0x70) + uint32_t reserved_113; // offset: 113 (0x71) + uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) + uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) + uint32_t cp_packet_id_lo; // offset: 116 (0x74) + uint32_t cp_packet_id_hi; // offset: 117 (0x75) + uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) + uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) + uint32_t gds_save_base_addr_lo; // offset: 120 (0x78) + uint32_t gds_save_base_addr_hi; // offset: 121 (0x79) + uint32_t gds_save_mask_lo; // offset: 122 (0x7A) + uint32_t gds_save_mask_hi; // offset: 123 (0x7B) + uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) + uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) + uint32_t reserved_126; // offset: 126 (0x7E) + uint32_t reserved_127; // offset: 127 (0x7F) + uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) + uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) + uint32_t cp_hqd_active; // offset: 130 (0x82) + uint32_t cp_hqd_vmid; // offset: 131 (0x83) + uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) + uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) + uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) + uint32_t cp_hqd_quantum; // offset: 135 (0x87) + uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) + uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) + uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) + uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) + uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) + uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) + uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) + uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) + uint32_t reserved_144; // offset: 144 (0x90) + uint32_t cp_hqd_pq_control; // offset: 145 (0x91) + uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) + uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) + uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) + uint32_t cp_hqd_ib_control; // offset: 149 (0x95) + uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) + uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) + uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) + uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) + uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) + uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) + uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) + uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) + uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) + uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) + uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) + uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) + uint32_t cp_mqd_control; // offset: 162 (0xA2) + uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) + uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) + uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) + uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) + uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) + uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) + uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) + uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) + uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) + uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) + uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) + uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) + uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) + uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) + uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) + uint32_t cp_hqd_gds_resource_state; // offset: 178 (0xB2) + uint32_t cp_hqd_error; // offset: 179 (0xB3) + uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) + uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) + uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) + uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) + uint32_t reserved_184; // offset: 184 (0xB8) + uint32_t reserved_185; // offset: 185 (0xB9) + uint32_t reserved_186; // offset: 186 (0xBA) + uint32_t reserved_187; // offset: 187 (0xBB) + uint32_t reserved_188; // offset: 188 (0xBC) + uint32_t reserved_189; // offset: 189 (0xBD) + uint32_t reserved_190; // offset: 190 (0xBE) + uint32_t reserved_191; // offset: 191 (0xBF) + uint32_t iqtimer_pkt_header; // offset: 192 (0xC0) + uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1) + uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2) + uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3) + uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4) + uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5) + uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6) + uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7) + uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8) + uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9) + uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA) + uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB) + uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC) + uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD) + uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE) + uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF) + uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0) + uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1) + uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2) + uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3) + uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4) + uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5) + uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6) + uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7) + uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8) + uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9) + uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA) + uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB) + uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC) + uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD) + uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE) + uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF) + uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0) + uint32_t reserved_225; // offset: 225 (0xE1) + uint32_t reserved_226; // offset: 226 (0xE2) + uint32_t reserved_227; // offset: 227 (0xE3) + uint32_t set_resources_header; // offset: 228 (0xE4) + uint32_t set_resources_dw1; // offset: 229 (0xE5) + uint32_t set_resources_dw2; // offset: 230 (0xE6) + uint32_t set_resources_dw3; // offset: 231 (0xE7) + uint32_t set_resources_dw4; // offset: 232 (0xE8) + uint32_t set_resources_dw5; // offset: 233 (0xE9) + uint32_t set_resources_dw6; // offset: 234 (0xEA) + uint32_t set_resources_dw7; // offset: 235 (0xEB) + uint32_t reserved_236; // offset: 236 (0xEC) + uint32_t reserved_237; // offset: 237 (0xED) + uint32_t reserved_238; // offset: 238 (0xEE) + uint32_t reserved_239; // offset: 239 (0xEF) + uint32_t queue_doorbell_id0; // offset: 240 (0xF0) + uint32_t queue_doorbell_id1; // offset: 241 (0xF1) + uint32_t queue_doorbell_id2; // offset: 242 (0xF2) + uint32_t queue_doorbell_id3; // offset: 243 (0xF3) + uint32_t queue_doorbell_id4; // offset: 244 (0xF4) + uint32_t queue_doorbell_id5; // offset: 245 (0xF5) + uint32_t queue_doorbell_id6; // offset: 246 (0xF6) + uint32_t queue_doorbell_id7; // offset: 247 (0xF7) + uint32_t queue_doorbell_id8; // offset: 248 (0xF8) + uint32_t queue_doorbell_id9; // offset: 249 (0xF9) + uint32_t queue_doorbell_id10; // offset: 250 (0xFA) + uint32_t queue_doorbell_id11; // offset: 251 (0xFB) + uint32_t queue_doorbell_id12; // offset: 252 (0xFC) + uint32_t queue_doorbell_id13; // offset: 253 (0xFD) + uint32_t queue_doorbell_id14; // offset: 254 (0xFE) + uint32_t queue_doorbell_id15; // offset: 255 (0xFF) + uint32_t control_buf_addr_lo; // offset: 256 (0x100) + uint32_t control_buf_addr_hi; // offset: 257 (0x101) + uint32_t control_buf_wptr_lo; // offset: 258 (0x102) + uint32_t control_buf_wptr_hi; // offset: 259 (0x103) + uint32_t control_buf_dptr_lo; // offset: 260 (0x104) + uint32_t control_buf_dptr_hi; // offset: 261 (0x105) + uint32_t control_buf_num_entries; // offset: 262 (0x106) + uint32_t draw_ring_addr_lo; // offset: 263 (0x107) + uint32_t draw_ring_addr_hi; // offset: 264 (0x108) + uint32_t reserved_265; // offset: 265 (0x109) + uint32_t reserved_266; // offset: 266 (0x10A) + uint32_t reserved_267; // offset: 267 (0x10B) + uint32_t reserved_268; // offset: 268 (0x10C) + uint32_t reserved_269; // offset: 269 (0x10D) + uint32_t reserved_270; // offset: 270 (0x10E) + uint32_t reserved_271; // offset: 271 (0x10F) + uint32_t reserved_272; // offset: 272 (0x110) + uint32_t reserved_273; // offset: 273 (0x111) + uint32_t reserved_274; // offset: 274 (0x112) + uint32_t reserved_275; // offset: 275 (0x113) + uint32_t reserved_276; // offset: 276 (0x114) + uint32_t reserved_277; // offset: 277 (0x115) + uint32_t reserved_278; // offset: 278 (0x116) + uint32_t reserved_279; // offset: 279 (0x117) + uint32_t reserved_280; // offset: 280 (0x118) + uint32_t reserved_281; // offset: 281 (0x119) + uint32_t reserved_282; // offset: 282 (0x11A) + uint32_t reserved_283; // offset: 283 (0x11B) + uint32_t reserved_284; // offset: 284 (0x11C) + uint32_t reserved_285; // offset: 285 (0x11D) + uint32_t reserved_286; // offset: 286 (0x11E) + uint32_t reserved_287; // offset: 287 (0x11F) + uint32_t reserved_288; // offset: 288 (0x120) + uint32_t reserved_289; // offset: 289 (0x121) + uint32_t reserved_290; // offset: 290 (0x122) + uint32_t reserved_291; // offset: 291 (0x123) + uint32_t reserved_292; // offset: 292 (0x124) + uint32_t reserved_293; // offset: 293 (0x125) + uint32_t reserved_294; // offset: 294 (0x126) + uint32_t reserved_295; // offset: 295 (0x127) + uint32_t reserved_296; // offset: 296 (0x128) + uint32_t reserved_297; // offset: 297 (0x129) + uint32_t reserved_298; // offset: 298 (0x12A) + uint32_t reserved_299; // offset: 299 (0x12B) + uint32_t reserved_300; // offset: 300 (0x12C) + uint32_t reserved_301; // offset: 301 (0x12D) + uint32_t reserved_302; // offset: 302 (0x12E) + uint32_t reserved_303; // offset: 303 (0x12F) + uint32_t reserved_304; // offset: 304 (0x130) + uint32_t reserved_305; // offset: 305 (0x131) + uint32_t reserved_306; // offset: 306 (0x132) + uint32_t reserved_307; // offset: 307 (0x133) + uint32_t reserved_308; // offset: 308 (0x134) + uint32_t reserved_309; // offset: 309 (0x135) + uint32_t reserved_310; // offset: 310 (0x136) + uint32_t reserved_311; // offset: 311 (0x137) + uint32_t reserved_312; // offset: 312 (0x138) + uint32_t reserved_313; // offset: 313 (0x139) + uint32_t reserved_314; // offset: 314 (0x13A) + uint32_t reserved_315; // offset: 315 (0x13B) + uint32_t reserved_316; // offset: 316 (0x13C) + uint32_t reserved_317; // offset: 317 (0x13D) + uint32_t reserved_318; // offset: 318 (0x13E) + uint32_t reserved_319; // offset: 319 (0x13F) + uint32_t reserved_320; // offset: 320 (0x140) + uint32_t reserved_321; // offset: 321 (0x141) + uint32_t reserved_322; // offset: 322 (0x142) + uint32_t reserved_323; // offset: 323 (0x143) + uint32_t reserved_324; // offset: 324 (0x144) + uint32_t reserved_325; // offset: 325 (0x145) + uint32_t reserved_326; // offset: 326 (0x146) + uint32_t reserved_327; // offset: 327 (0x147) + uint32_t reserved_328; // offset: 328 (0x148) + uint32_t reserved_329; // offset: 329 (0x149) + uint32_t reserved_330; // offset: 330 (0x14A) + uint32_t reserved_331; // offset: 331 (0x14B) + uint32_t reserved_332; // offset: 332 (0x14C) + uint32_t reserved_333; // offset: 333 (0x14D) + uint32_t reserved_334; // offset: 334 (0x14E) + uint32_t reserved_335; // offset: 335 (0x14F) + uint32_t reserved_336; // offset: 336 (0x150) + uint32_t reserved_337; // offset: 337 (0x151) + uint32_t reserved_338; // offset: 338 (0x152) + uint32_t reserved_339; // offset: 339 (0x153) + uint32_t reserved_340; // offset: 340 (0x154) + uint32_t reserved_341; // offset: 341 (0x155) + uint32_t reserved_342; // offset: 342 (0x156) + uint32_t reserved_343; // offset: 343 (0x157) + uint32_t reserved_344; // offset: 344 (0x158) + uint32_t reserved_345; // offset: 345 (0x159) + uint32_t reserved_346; // offset: 346 (0x15A) + uint32_t reserved_347; // offset: 347 (0x15B) + uint32_t reserved_348; // offset: 348 (0x15C) + uint32_t reserved_349; // offset: 349 (0x15D) + uint32_t reserved_350; // offset: 350 (0x15E) + uint32_t reserved_351; // offset: 351 (0x15F) + uint32_t reserved_352; // offset: 352 (0x160) + uint32_t reserved_353; // offset: 353 (0x161) + uint32_t reserved_354; // offset: 354 (0x162) + uint32_t reserved_355; // offset: 355 (0x163) + uint32_t reserved_356; // offset: 356 (0x164) + uint32_t reserved_357; // offset: 357 (0x165) + uint32_t reserved_358; // offset: 358 (0x166) + uint32_t reserved_359; // offset: 359 (0x167) + uint32_t reserved_360; // offset: 360 (0x168) + uint32_t reserved_361; // offset: 361 (0x169) + uint32_t reserved_362; // offset: 362 (0x16A) + uint32_t reserved_363; // offset: 363 (0x16B) + uint32_t reserved_364; // offset: 364 (0x16C) + uint32_t reserved_365; // offset: 365 (0x16D) + uint32_t reserved_366; // offset: 366 (0x16E) + uint32_t reserved_367; // offset: 367 (0x16F) + uint32_t reserved_368; // offset: 368 (0x170) + uint32_t reserved_369; // offset: 369 (0x171) + uint32_t reserved_370; // offset: 370 (0x172) + uint32_t reserved_371; // offset: 371 (0x173) + uint32_t reserved_372; // offset: 372 (0x174) + uint32_t reserved_373; // offset: 373 (0x175) + uint32_t reserved_374; // offset: 374 (0x176) + uint32_t reserved_375; // offset: 375 (0x177) + uint32_t reserved_376; // offset: 376 (0x178) + uint32_t reserved_377; // offset: 377 (0x179) + uint32_t reserved_378; // offset: 378 (0x17A) + uint32_t reserved_379; // offset: 379 (0x17B) + uint32_t reserved_380; // offset: 380 (0x17C) + uint32_t reserved_381; // offset: 381 (0x17D) + uint32_t reserved_382; // offset: 382 (0x17E) + uint32_t reserved_383; // offset: 383 (0x17F) + uint32_t reserved_384; // offset: 384 (0x180) + uint32_t reserved_385; // offset: 385 (0x181) + uint32_t reserved_386; // offset: 386 (0x182) + uint32_t reserved_387; // offset: 387 (0x183) + uint32_t reserved_388; // offset: 388 (0x184) + uint32_t reserved_389; // offset: 389 (0x185) + uint32_t reserved_390; // offset: 390 (0x186) + uint32_t reserved_391; // offset: 391 (0x187) + uint32_t reserved_392; // offset: 392 (0x188) + uint32_t reserved_393; // offset: 393 (0x189) + uint32_t reserved_394; // offset: 394 (0x18A) + uint32_t reserved_395; // offset: 395 (0x18B) + uint32_t reserved_396; // offset: 396 (0x18C) + uint32_t reserved_397; // offset: 397 (0x18D) + uint32_t reserved_398; // offset: 398 (0x18E) + uint32_t reserved_399; // offset: 399 (0x18F) + uint32_t reserved_400; // offset: 400 (0x190) + uint32_t reserved_401; // offset: 401 (0x191) + uint32_t reserved_402; // offset: 402 (0x192) + uint32_t reserved_403; // offset: 403 (0x193) + uint32_t reserved_404; // offset: 404 (0x194) + uint32_t reserved_405; // offset: 405 (0x195) + uint32_t reserved_406; // offset: 406 (0x196) + uint32_t reserved_407; // offset: 407 (0x197) + uint32_t reserved_408; // offset: 408 (0x198) + uint32_t reserved_409; // offset: 409 (0x199) + uint32_t reserved_410; // offset: 410 (0x19A) + uint32_t reserved_411; // offset: 411 (0x19B) + uint32_t reserved_412; // offset: 412 (0x19C) + uint32_t reserved_413; // offset: 413 (0x19D) + uint32_t reserved_414; // offset: 414 (0x19E) + uint32_t reserved_415; // offset: 415 (0x19F) + uint32_t reserved_416; // offset: 416 (0x1A0) + uint32_t reserved_417; // offset: 417 (0x1A1) + uint32_t reserved_418; // offset: 418 (0x1A2) + uint32_t reserved_419; // offset: 419 (0x1A3) + uint32_t reserved_420; // offset: 420 (0x1A4) + uint32_t reserved_421; // offset: 421 (0x1A5) + uint32_t reserved_422; // offset: 422 (0x1A6) + uint32_t reserved_423; // offset: 423 (0x1A7) + uint32_t reserved_424; // offset: 424 (0x1A8) + uint32_t reserved_425; // offset: 425 (0x1A9) + uint32_t reserved_426; // offset: 426 (0x1AA) + uint32_t reserved_427; // offset: 427 (0x1AB) + uint32_t reserved_428; // offset: 428 (0x1AC) + uint32_t reserved_429; // offset: 429 (0x1AD) + uint32_t reserved_430; // offset: 430 (0x1AE) + uint32_t reserved_431; // offset: 431 (0x1AF) + uint32_t reserved_432; // offset: 432 (0x1B0) + uint32_t reserved_433; // offset: 433 (0x1B1) + uint32_t reserved_434; // offset: 434 (0x1B2) + uint32_t reserved_435; // offset: 435 (0x1B3) + uint32_t reserved_436; // offset: 436 (0x1B4) + uint32_t reserved_437; // offset: 437 (0x1B5) + uint32_t reserved_438; // offset: 438 (0x1B6) + uint32_t reserved_439; // offset: 439 (0x1B7) + uint32_t reserved_440; // offset: 440 (0x1B8) + uint32_t reserved_441; // offset: 441 (0x1B9) + uint32_t reserved_442; // offset: 442 (0x1BA) + uint32_t reserved_443; // offset: 443 (0x1BB) + uint32_t reserved_444; // offset: 444 (0x1BC) + uint32_t reserved_445; // offset: 445 (0x1BD) + uint32_t reserved_446; // offset: 446 (0x1BE) + uint32_t reserved_447; // offset: 447 (0x1BF) + uint32_t gws_0_val; // offset: 448 (0x1C0) + uint32_t gws_1_val; // offset: 449 (0x1C1) + uint32_t gws_2_val; // offset: 450 (0x1C2) + uint32_t gws_3_val; // offset: 451 (0x1C3) + uint32_t gws_4_val; // offset: 452 (0x1C4) + uint32_t gws_5_val; // offset: 453 (0x1C5) + uint32_t gws_6_val; // offset: 454 (0x1C6) + uint32_t gws_7_val; // offset: 455 (0x1C7) + uint32_t gws_8_val; // offset: 456 (0x1C8) + uint32_t gws_9_val; // offset: 457 (0x1C9) + uint32_t gws_10_val; // offset: 458 (0x1CA) + uint32_t gws_11_val; // offset: 459 (0x1CB) + uint32_t gws_12_val; // offset: 460 (0x1CC) + uint32_t gws_13_val; // offset: 461 (0x1CD) + uint32_t gws_14_val; // offset: 462 (0x1CE) + uint32_t gws_15_val; // offset: 463 (0x1CF) + uint32_t gws_16_val; // offset: 464 (0x1D0) + uint32_t gws_17_val; // offset: 465 (0x1D1) + uint32_t gws_18_val; // offset: 466 (0x1D2) + uint32_t gws_19_val; // offset: 467 (0x1D3) + uint32_t gws_20_val; // offset: 468 (0x1D4) + uint32_t gws_21_val; // offset: 469 (0x1D5) + uint32_t gws_22_val; // offset: 470 (0x1D6) + uint32_t gws_23_val; // offset: 471 (0x1D7) + uint32_t gws_24_val; // offset: 472 (0x1D8) + uint32_t gws_25_val; // offset: 473 (0x1D9) + uint32_t gws_26_val; // offset: 474 (0x1DA) + uint32_t gws_27_val; // offset: 475 (0x1DB) + uint32_t gws_28_val; // offset: 476 (0x1DC) + uint32_t gws_29_val; // offset: 477 (0x1DD) + uint32_t gws_30_val; // offset: 478 (0x1DE) + uint32_t gws_31_val; // offset: 479 (0x1DF) + uint32_t gws_32_val; // offset: 480 (0x1E0) + uint32_t gws_33_val; // offset: 481 (0x1E1) + uint32_t gws_34_val; // offset: 482 (0x1E2) + uint32_t gws_35_val; // offset: 483 (0x1E3) + uint32_t gws_36_val; // offset: 484 (0x1E4) + uint32_t gws_37_val; // offset: 485 (0x1E5) + uint32_t gws_38_val; // offset: 486 (0x1E6) + uint32_t gws_39_val; // offset: 487 (0x1E7) + uint32_t gws_40_val; // offset: 488 (0x1E8) + uint32_t gws_41_val; // offset: 489 (0x1E9) + uint32_t gws_42_val; // offset: 490 (0x1EA) + uint32_t gws_43_val; // offset: 491 (0x1EB) + uint32_t gws_44_val; // offset: 492 (0x1EC) + uint32_t gws_45_val; // offset: 493 (0x1ED) + uint32_t gws_46_val; // offset: 494 (0x1EE) + uint32_t gws_47_val; // offset: 495 (0x1EF) + uint32_t gws_48_val; // offset: 496 (0x1F0) + uint32_t gws_49_val; // offset: 497 (0x1F1) + uint32_t gws_50_val; // offset: 498 (0x1F2) + uint32_t gws_51_val; // offset: 499 (0x1F3) + uint32_t gws_52_val; // offset: 500 (0x1F4) + uint32_t gws_53_val; // offset: 501 (0x1F5) + uint32_t gws_54_val; // offset: 502 (0x1F6) + uint32_t gws_55_val; // offset: 503 (0x1F7) + uint32_t gws_56_val; // offset: 504 (0x1F8) + uint32_t gws_57_val; // offset: 505 (0x1F9) + uint32_t gws_58_val; // offset: 506 (0x1FA) + uint32_t gws_59_val; // offset: 507 (0x1FB) + uint32_t gws_60_val; // offset: 508 (0x1FC) + uint32_t gws_61_val; // offset: 509 (0x1FD) + uint32_t gws_62_val; // offset: 510 (0x1FE) + uint32_t gws_63_val; // offset: 511 (0x1FF) +}; + +#endif /* V11_STRUCTS_H_ */ diff --git a/extra/amdpci/proclogs.py b/extra/amdpci/proclogs.py new file mode 100644 index 0000000000..6eb1e0d37a --- /dev/null +++ b/extra/amdpci/proclogs.py @@ -0,0 +1,56 @@ +import re, ctypes, sys + +from tinygrad.runtime.autogen import libpciaccess +from tinygrad.runtime.autogen.am import am, mp_11_0, mp_13_0_0, nbio_4_3_0, mmhub_3_0_0, gc_11_0_0, osssys_6_0_0 + +def parse_amdgpu_logs(log_content, register_names=None): + register_map = register_names or REGISTER_NAMES + + final = "" + def replace_register(match): + register = match.group(1) + return f"Reading register {register_map.get(int(register, base=16), register)}" + + pattern = r'Reading register (0x[0-9a-fA-F]+)' + + processed_log = re.sub(pattern, replace_register, log_content) + + def replace_register_2(match): + register = match.group(1) + return f"Writing register {register_map.get(int(register, base=16), register)}" + + pattern = r'Writing register (0x[0-9a-fA-F]+)' + processed_log = re.sub(pattern, replace_register_2, processed_log) + + lines = processed_log.split('\n') + + in_trace = False + cleaned_lines = [] + + return '\n'.join(cleaned_lines) + +def main(): + regs_offset = {13: {0: [3072, 37784576]}, 28: {0: [93184, 37754880], 1: [201327616, 201461760], 2: [209716224, 209850368], 3: [218104832, 218238976], 4: [226493440, 226627584], 5: [234882048, 235016192], 6: [243270656, 243404800]}, 21: {0: [28672, 12582912, 37795840, 130023424, 306184192], 1: [201326592, 201463808, 201465856, 204210176, 204472320], 2: [209715200, 209852416, 209854464, 212598784, 212860928], 3: [218103808, 218241024, 218243072, 220987392, 221249536], 4: [226492416, 226629632, 226631680, 229376000, 229638144], 5: [234881024, 235018240, 235020288, 237764608, 238026752], 6: [243269632, 243406848, 243408896, 246153216, 246415360]}, 22: {0: [18, 192, 13504, 36864, 37764096]}, 1: {0: [4704, 40960, 114688, 37760000]}, 2: {0: [3872, 37790720]}, 11: {0: [70656, 38103040]}, 12: {0: [106496, 37783552]}, 15: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 16: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 14: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 26: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 23: {0: [4256, 37789696]}, 33: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 25: {0: []}, 3: {0: [4704, 40960, 114688, 37760000]}, 4: {0: [4704, 40960, 114688, 37760000]}, 24: {0: [92160, 92672, 37752832, 54788096]}, 27: {0: [91648, 37751808], 1: [201339904, 201458176], 2: [209728512, 209846784], 3: [218117120, 218235392], 4: [226505728, 226624000], 5: [234894336, 235012608], 6: [243282944, 243401216]}, 29: {0: [201342976, 201344000, 205520896, 205537280], 1: [209731584, 209732608, 213909504, 213925888], 2: [218120192, 218121216, 222298112, 222314496], 3: [226508800, 226509824, 230686720, 230703104], 4: [234897408, 234898432, 239075328, 239091712], 5: [243286016, 243287040, 247463936, 247480320]}, 17: {0: [30720, 32256], 1: [31488, 73728]}} + + def _prepare_registers(modules): + for base, m in modules: + for k, regval in m.__dict__.items(): + if k.startswith("reg") and not k.endswith("_BASE_IDX") and (base_idx:=getattr(m, f"{k}_BASE_IDX", None)) is not None: + REGISTER_NAMES[regs_offset[am.__dict__.get(f"{base}_HWIP")][0][base_idx] + regval] = k + + _prepare_registers([("MP0", mp_13_0_0), ("NBIO", nbio_4_3_0), ("MMHUB", mmhub_3_0_0), ("GC", gc_11_0_0), ("OSSSYS", osssys_6_0_0)]) + + with open(sys.argv[1], 'r') as f: + log_content = log_content_them = f.read() + + processed_log = parse_amdgpu_logs(log_content) + + with open(sys.argv[2], 'w') as f: + f.write(processed_log) + +if __name__ == '__main__': + if len(sys.argv) != 3: + print("Usage: ") + sys.exit(1) + + main() \ No newline at end of file diff --git a/setup.py b/setup.py index d4048c756b..5e058b898b 100644 --- a/setup.py +++ b/setup.py @@ -15,7 +15,7 @@ setup(name='tinygrad', long_description=long_description, long_description_content_type='text/markdown', packages = ['tinygrad', 'tinygrad.runtime.autogen', 'tinygrad.codegen', 'tinygrad.nn', 'tinygrad.renderer', 'tinygrad.engine', - 'tinygrad.runtime', 'tinygrad.runtime.support', 'tinygrad.runtime.graph', 'tinygrad.shape'], + 'tinygrad.runtime', 'tinygrad.runtime.support', 'tinygrad.runtime.support.am', 'tinygrad.runtime.graph', 'tinygrad.shape'], package_data = {'tinygrad': ['py.typed']}, classifiers=[ "Programming Language :: Python :: 3", diff --git a/test/external/external_fuzz_ampt.py b/test/external/external_fuzz_ampt.py new file mode 100644 index 0000000000..2785772c01 --- /dev/null +++ b/test/external/external_fuzz_ampt.py @@ -0,0 +1,104 @@ +import random +from tinygrad.helpers import round_up +from tinygrad.runtime.support.am.amdev import AMMemoryManager +from test.external.external_test_am import helper_read_entry_components, FakeAM + +class AMPTFuzzer: + def __init__(self, total_size): + self.total_size = total_size + self.alloc_payload = 0 + self.d = FakeAM() + + self.allocations: dict[int, tuple[int, int]] = {} # ptr -> (size, pattern) + + self.min_alloc_size = 0x1000 + self.max_alloc_size = int(total_size * 0.1) + self.alloc_probability = 0.7 + + def generate_pattern(self, ptr: int, size: int) -> int: return random.randint(0, 0xff) + + def fill_memory(self, va, size: int, pattern: int): + internal_va = va.va_addr - AMMemoryManager.va_allocator.base + pages = list(self.d.mm.page_table_walker(self.d.mm.root_page_table, vaddr=internal_va, size=size)) + + for _vaddr, _offset, _pte_idx, _n_ptes, _pte_covers, _pt in pages: + for i in range(_n_ptes): + pte = helper_read_entry_components(_pt.get_entry(_pte_idx + i)) + self.d.vram[pte['paddr']] = pattern # Mark this page + assert pte['valid'] == 1 + + # If page has contigous fragment, all range should be this valid memory + frags_cnt = pte['fragment'] + contig_range = (1 << (frags_cnt + 12)) + start_vaddr = _vaddr & ~(contig_range - 1) + start_paddr = pte['paddr'] - (_vaddr - start_vaddr) + contig_ptes = contig_range // _pte_covers + assert contig_ptes > 0 + frags_l = list(self.d.mm.page_table_walker(self.d.mm.root_page_table, vaddr=start_vaddr, size=contig_range)) + for f_vaddr, f_offset, f_pte_idx, f_n_ptes, f_pte_covers, f_pt in frags_l: + for j in range(f_n_ptes): + f_pte = helper_read_entry_components(f_pt.get_entry(f_pte_idx + j)) + assert f_pte['valid'] == 1 + assert f_pte['paddr'] == start_paddr+f_offset+j*f_pte_covers, f"paddr {f_pte['paddr']:#x} not {start_paddr+f_offset+j*f_pte_covers:#x}" + + _vaddr += _pte_covers + _offset += _pte_covers + + return pages + + def verify_memory(self, pages, pattern: int) -> bool: + for _vaddr, _offset, _pte_idx, _n_ptes, _pte_covers, _pt in pages: + for i in range(_n_ptes): + pte = helper_read_entry_components(_pt.get_entry(_pte_idx + i)) + if self.d.vram[pte['paddr']] != pattern: return False + if pte['valid'] == 0: return False + + return True + + def random_alloc(self): + if self.total_size - self.alloc_payload < self.min_alloc_size: return None + + size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload)) + size = round_up(size, (2 << 20) if size > (4 << 20) else (4 << 10)) + + try: ptr = self.d.mm.valloc(size) + except MemoryError: + print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%") + return None + + pattern = self.generate_pattern(ptr, size) + pages = self.fill_memory(ptr, size, pattern) + self.allocations[ptr] = (size, pattern, pages) + self.alloc_payload += size + print(f"Allocated {size} bytes at {ptr.va_addr:x}, pattern: {pattern:02x}") + return ptr + + def random_free(self) -> bool: + if not self.allocations: return False + + ptr = random.choice(list(self.allocations.keys())) + size, pattern, pages = self.allocations[ptr] + + # Verify pattern before freeing + if not self.verify_memory(pages, pattern): + raise RuntimeError(f"Memory corruption detected at {ptr.va_addr:x}!") + + print(f"Freeing {size} bytes at {ptr.va_addr:x}, pattern verified: {pattern:02x}") + self.alloc_payload -= size + self.d.mm.vfree(ptr) + del self.allocations[ptr] + return True + + def run(self): + for i in range(10000000): + if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc() + else: self.random_free() + + print("\nCleaning up remaining allocations...") + while self.allocations: self.random_free() + + print("Fuzzing completed successfully!") + +if __name__ == "__main__": + fuzzer = AMPTFuzzer(1 << 30) + fuzzer.run() diff --git a/test/external/external_fuzz_tlsf.py b/test/external/external_fuzz_tlsf.py new file mode 100644 index 0000000000..50f2478a83 --- /dev/null +++ b/test/external/external_fuzz_tlsf.py @@ -0,0 +1,76 @@ +import random +from typing import Dict, Optional + +from tinygrad.runtime.support.allocator import TLSFAllocator + +class AllocatorFuzzer: + def __init__(self, total_size): + self.total_size = total_size + self.alloc_payload = 0 + self.mv = memoryview(bytearray(total_size)) + self.alloctor = TLSFAllocator(total_size, block_size=16) + + self.allocations: Dict[int, tuple[int, int]] = {} # ptr -> (size, pattern) + + self.min_alloc_size = 16 + self.max_alloc_size = int(total_size * 0.3) + self.alloc_probability = 0.7 + + def generate_pattern(self, ptr: int, size: int) -> int: return (ptr * 31 + size * 17) & 0xFF + + def fill_memory(self, ptr: int, size: int, pattern: int): + for i in range(min(size, 32)): + self.mv[ptr + i] = pattern + self.mv[ptr + (size - 1 - i)] = pattern + + def verify_memory(self, ptr: int, size: int, pattern: int) -> bool: + for i in range(min(size, 32)): + assert self.mv[ptr + i] == pattern + assert self.mv[ptr + (size - 1 - i)] == pattern + return True + + def random_alloc(self) -> Optional[int]: + size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload)) + + try: + ptr = self.alloctor.alloc(size) + except MemoryError: + print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%") + return None + + pattern = self.generate_pattern(ptr, size) + self.fill_memory(ptr, size, pattern) + self.allocations[ptr] = (size, pattern) + self.alloc_payload += size + print(f"Allocated {size} bytes at {ptr:x}, pattern: {pattern:02x}") + return ptr + + def random_free(self) -> bool: + if not self.allocations: return False + + ptr = random.choice(list(self.allocations.keys())) + size, pattern = self.allocations[ptr] + + # Verify pattern before freeing + if not self.verify_memory(ptr, size, pattern): + raise RuntimeError(f"Memory corruption detected at {ptr:x}!") + + print(f"Freeing {size} bytes at {ptr:x}, pattern verified: {pattern:02x}") + self.alloc_payload -= size + self.alloctor.free(ptr) + del self.allocations[ptr] + return True + + def run(self): + for i in range(10000000): + if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc() + else: self.random_free() + + print("\nCleaning up remaining allocations...") + while self.allocations: self.random_free() + + print("Fuzzing completed successfully!") + +if __name__ == "__main__": + fuzzer = AllocatorFuzzer(1 << 30) + fuzzer.run() diff --git a/test/external/external_test_am.py b/test/external/external_test_am.py new file mode 100644 index 0000000000..eb3d2c3ae6 --- /dev/null +++ b/test/external/external_test_am.py @@ -0,0 +1,162 @@ +import unittest +from tinygrad.runtime.support.am.amdev import AMMemoryManager + +class FakeGMC: + def flush_tlb(self, *args, **kwargs): pass + +class FakePCIRegion: + def __init__(self): self.base_addr = 0xc12300000000 + +class FakePCIDev: + def __init__(self): self.regions = [FakePCIRegion()] + +class FakeAM: + def __init__(self): + self.pcidev = FakePCIDev() + self.vram = memoryview(bytearray(4 << 30)) + self.gmc = FakeGMC() + self.mm = AMMemoryManager(self, vram_size=4 << 30) + +# * PTE format: +# * 63:59 reserved +# * 58:57 reserved +# * 56 F +# * 55 L +# * 54 reserved +# * 53:52 SW +# * 51 T +# * 50:48 mtype +# * 47:12 4k physical page base address +# * 11:7 fragment +# * 6 write +# * 5 read +# * 4 exe +# * 3 Z +# * 2 snooped +# * 1 system +# * 0 valid +def helper_read_entry_components(entry_val): + return {"paddr": entry_val & 0x0000FFFFFFFFF000, "fragment":(entry_val >> 7) & 0x1f, "valid": entry_val & 0x1, + "read": (entry_val >> 5) & 0x1, "write": (entry_val >> 6) & 0x1, "exec": (entry_val >> 4) & 0x1, + "mtype": (entry_val >> 48) & 0x7, "T": (entry_val >> 51) & 0x1, "L": (entry_val >> 55) & 0x1, "F": (entry_val >> 56) & 0x1} + +class TestAMPageTable(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.d = [FakeAM() for _ in range(2)] + + def test_page_table_walkers(self): + mm = self.d[0].mm + + for va,sz in [(0x10000, 0x3000), (0x11000, 0x300000), (0x10000, 0x2000), (0x11000, 0x5000), + (0x2000000, 0x2000), (0x4000000, 0x4000000), (0x38000, 0x303000), (0x8000, 0x1000)]: + exteranl_va = va + AMMemoryManager.va_allocator.base + mm.map_range(vaddr=exteranl_va, size=sz, paddr=va) + + results = list(mm.page_table_walker(mm.root_page_table, vaddr=va, size=sz)) + + total_covered = 0 + for tup in results: + _vaddr, _offset, _pte_idx, _n_ptes, _pte_covers, _pt = tup + total_covered += _n_ptes * _pte_covers + + assert total_covered == sz, f"Expected total coverage {total_covered} to be {sz}" + + for tup in results: + _vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup + for i in range(n_ptes): + pte = helper_read_entry_components(pt.get_entry(pte_idx + i)) + assert pte['paddr'] == va + _offset + i * pte_covers, f"Expected paddr {pte['paddr']:#x} to be {va + _offset + i * pte_covers:#x}" + assert pte['valid'] == 1 + + mm.unmap_range(va, sz, free_paddrs=False) + + for tup in results: + _vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup + for i in range(n_ptes): + pte = helper_read_entry_components(pt.get_entry(pte_idx + i)) + assert pte['paddr'] == 0 + assert pte['valid'] == 0 + + def test_double_map(self): + mm0 = self.d[0].mm + + for va,sz in [(0x10000, 0x3000), (0x1000000, 0x1000000), (0x12000, 0x4000)]: + exteranl_va = va + AMMemoryManager.va_allocator.base + mm0.map_range(vaddr=exteranl_va, size=sz, paddr=va) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va, size=0x1000, paddr=va) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va, size=0x100000, paddr=va) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va + 0x1000, size=0x1000, paddr=va) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddr=va) + + mm0.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False) + + # Finally can map and check paddrs + mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddr=0xdead0000) + for tup in mm0.page_table_walker(mm0.root_page_table, vaddr=va + 0x2000, size=0x100000): + _vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup + for i in range(n_ptes): + pte = helper_read_entry_components(pt.get_entry(pte_idx + i)) + assert pte['paddr'] == 0xdead0000 + _offset + i * pte_covers, f"paddr {pte['paddr']:#x} not {0xdead0000 + _offset + i * pte_covers:#x}" + assert pte['valid'] == 1 + + mm0.unmap_range(vaddr=exteranl_va + 0x2000, size=0x100000, free_paddrs=False) + + def test_map_from(self): + mm0 = self.d[0].mm + mm1 = self.d[1].mm + + for va,sz in [(0x10000, 0x3000), (0x11000, 0x300000), (0x10000, 0x2000), (0x11000, 0x5000), + (0x2000000, 0x2000), (0x4000000, 0x4000000), (0x38000, 0x303000), (0x8000, 0x1000)]: + exteranl_va = va + AMMemoryManager.va_allocator.base + mm0.map_range(vaddr=exteranl_va, size=sz, paddr=va) + mm1.map_range(vaddr=exteranl_va, size=sz, paddr=va) + + with self.assertRaises(AssertionError): + mm0.map_from(vaddr=exteranl_va, size=sz, from_adev=mm0.adev) # self mapping -- bad + + with self.assertRaises(AssertionError): + mm0.map_from(vaddr=exteranl_va, size=sz, from_adev=mm1.adev) # mapping from mm1 to same addrs -- bad + + mm0.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False) # unmap from mm0 + mm0.map_from(vaddr=exteranl_va, size=sz, from_adev=mm1.adev) # mapping from mm1 to same addrs -- ok + + d1_pci_base = self.d[1].pcidev.regions[0].base_addr + for tup in mm0.page_table_walker(mm0.root_page_table, vaddr=va, size=sz): + _vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup + for i in range(n_ptes): + pte = helper_read_entry_components(pt.get_entry(pte_idx + i)) + assert pte['paddr'] == d1_pci_base + va + _offset + i * pte_covers, f"paddr {pte['paddr']:#x} not {d1_pci_base+va+_offset+i*pte_covers:#x}" + assert pte['valid'] == 1 + + mm0.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False) + mm1.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False) + + def test_try_bad_unmap(self): + mm0 = self.d[0].mm + + with self.assertRaises(AssertionError): + mm0.unmap_range(0x10000, 0x3000, free_paddrs=False) + + mm0.map_range(0x10000, 0x3000, 0x10000) + mm0.unmap_range(0x10000, 0x3000, free_paddrs=False) + + with self.assertRaises(AssertionError): + mm0.unmap_range(0x10000, 0x3000, free_paddrs=False) + + mm0.map_range(0x10000, 0x3000, 0x10000) + mm0.unmap_range(0x10000, 0x3000, free_paddrs=False) + + with self.assertRaises(AssertionError): + mm0.unmap_range(0x10000, 0x3000, free_paddrs=False) + +if __name__ == "__main__": + unittest.main() diff --git a/test/external/external_test_tlsf.py b/test/external/external_test_tlsf.py new file mode 100644 index 0000000000..aa780fdd50 --- /dev/null +++ b/test/external/external_test_tlsf.py @@ -0,0 +1,78 @@ +import unittest +from tinygrad.runtime.support.allocator import TLSFAllocator + +class TestTLSFAllocator(unittest.TestCase): + def setUp(self): + self.allocator = TLSFAllocator(1024, block_size=16) + + def test_basic_alloc_free(self): + addr1 = self.allocator.alloc(32) + self.assertEqual(addr1, 0) + + addr2 = self.allocator.alloc(64) + self.assertEqual(addr2, 32) + + self.allocator.free(addr1) + addr3 = self.allocator.alloc(32) + self.assertEqual(addr3, 0) + + def test_block_size_alignment(self): + addr1 = self.allocator.alloc(20) + addr2 = self.allocator.alloc(35) + + self.assertEqual(addr1 % 16, 0) + self.assertEqual(addr2 % 16, 0) + + def test_merge_blocks(self): + addr1 = self.allocator.alloc(32) + addr2 = self.allocator.alloc(32) + self.allocator.alloc(32) + + self.allocator.free(addr1) + self.allocator.free(addr2) + addr4 = self.allocator.alloc(64) + self.assertEqual(addr4, addr1) + + def test_split_blocks(self): + addr1 = self.allocator.alloc(128) + self.allocator.free(addr1) + + addr2 = self.allocator.alloc(32) + self.assertEqual(addr2, addr1) + + addr3 = self.allocator.alloc(32) + self.assertEqual(addr3, addr1 + 32) + + def test_out_of_memory(self): + with self.assertRaises(MemoryError): + self.allocator.alloc(2048) + + def test_fragmentation_handling(self): + addrs = [] + for _ in range(5): + addrs.append(self.allocator.alloc(32)) + + # Free alternate blocks + for i in range(0, len(addrs), 2): + self.allocator.free(addrs[i]) + + def test_custom_start_address(self): + allocator = TLSFAllocator(1024, start_addr=1000) + addr1 = allocator.alloc(32) + self.assertEqual(addr1, 1000) + + addr2 = allocator.alloc(64) + self.assertEqual(addr2, 1032) + + def test_block_tracking(self): + addr1 = self.allocator.alloc(32) + addr2 = self.allocator.alloc(64) + + self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) + self.assertTrue(addr2 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) + + self.allocator.free(addr1) + self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) + +if __name__ == '__main__': + unittest.main() diff --git a/test/mockgpu/amd/amddriver.py b/test/mockgpu/amd/amddriver.py index 2005dc0fef..0100254945 100644 --- a/test/mockgpu/amd/amddriver.py +++ b/test/mockgpu/amd/amddriver.py @@ -76,6 +76,7 @@ class AMDDriver(VirtDriver): self.doorbells[gpu_id] = memoryview(bytearray(0x2000)) self.gpus[gpu_id] = AMDGPU(gpu_id) self.tracked_files += [ + VirtFile('/sys/module/amdgpu', functools.partial(TextFileDesc, text="1")), VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}', functools.partial(DirFileDesc, child_names=['gpu_id', 'properties'])), VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/gpu_id', functools.partial(TextFileDesc, text=f"{gpu_id}")), VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/properties', diff --git a/tinygrad/helpers.py b/tinygrad/helpers.py index 58dc61756a..0c4544f1d3 100644 --- a/tinygrad/helpers.py +++ b/tinygrad/helpers.py @@ -43,6 +43,8 @@ def fromimport(mod, frm): return getattr(__import__(mod, fromlist=[frm]), frm) def strip_parens(fst:str): return fst[1:-1] if fst[0] == '(' and fst[-1] == ')' and fst[1:-1].find('(') <= fst[1:-1].find(')') else fst def ceildiv(num, amt): return int(ret) if isinstance((ret:=-(num//-amt)), float) else ret def round_up(num:int, amt:int) -> int: return (num+amt-1)//amt * amt +def lo32(x:Any) -> Any: return x & 0xFFFFFFFF # Any is sint +def hi32(x:Any) -> Any: return x >> 32 # Any is sint def data64(data:Any) -> tuple[Any, Any]: return (data >> 32, data & 0xFFFFFFFF) # Any is sint def data64_le(data:Any) -> tuple[Any, Any]: return (data & 0xFFFFFFFF, data >> 32) # Any is sint def merge_dicts(ds:Iterable[dict[T,U]]) -> dict[T,U]: diff --git a/tinygrad/runtime/autogen/am/am.py b/tinygrad/runtime/autogen/am/am.py new file mode 100644 index 0000000000..9d5a8a3c7d --- /dev/null +++ b/tinygrad/runtime/autogen/am/am.py @@ -0,0 +1,43707 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + +class AsDictMixin: + @classmethod + def as_dict(cls, self): + result = {} + if not isinstance(self, AsDictMixin): + # not a structure, assume it's already a python object + return self + if not hasattr(cls, "_fields_"): + return result + # sys.version_info >= (3, 5) + # for (field, *_) in cls._fields_: # noqa + for field_tuple in cls._fields_: # noqa + field = field_tuple[0] + if field.startswith('PADDING_'): + continue + value = getattr(self, field) + type_ = type(value) + if hasattr(value, "_length_") and hasattr(value, "_type_"): + # array + if not hasattr(type_, "as_dict"): + value = [v for v in value] + else: + type_ = type_._type_ + value = [type_.as_dict(v) for v in value] + elif hasattr(value, "contents") and hasattr(value, "_type_"): + # pointer + try: + if not hasattr(type_, "as_dict"): + value = value.contents + else: + type_ = type_._type_ + value = type_.as_dict(value.contents) + except ValueError: + # nullptr + value = None + elif isinstance(value, AsDictMixin): + # other structure + value = type_.as_dict(value) + result[field] = value + return result + + +class Structure(ctypes.Structure, AsDictMixin): + + def __init__(self, *args, **kwds): + # We don't want to use positional arguments fill PADDING_* fields + + args = dict(zip(self.__class__._field_names_(), args)) + args.update(kwds) + super(Structure, self).__init__(**args) + + @classmethod + def _field_names_(cls): + if hasattr(cls, '_fields_'): + return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) + else: + return () + + @classmethod + def get_type(cls, field): + for f in cls._fields_: + if f[0] == field: + return f[1] + return None + + @classmethod + def bind(cls, bound_fields): + fields = {} + for name, type_ in cls._fields_: + if hasattr(type_, "restype"): + if name in bound_fields: + if bound_fields[name] is None: + fields[name] = type_() + else: + # use a closure to capture the callback from the loop scope + fields[name] = ( + type_((lambda callback: lambda *args: callback(*args))( + bound_fields[name])) + ) + del bound_fields[name] + else: + # default callback implementation (does nothing) + try: + default_ = type_(0).restype().value + except TypeError: + default_ = None + fields[name] = type_(( + lambda default_: lambda *args: default_)(default_)) + else: + # not a callback function, use default initialization + if name in bound_fields: + fields[name] = bound_fields[name] + del bound_fields[name] + else: + fields[name] = type_() + if len(bound_fields) != 0: + raise ValueError( + "Cannot bind the following unknown callback(s) {}.{}".format( + cls.__name__, bound_fields.keys() + )) + return cls(**fields) + + +class Union(ctypes.Union, AsDictMixin): + pass + + + +c_int128 = ctypes.c_ubyte*16 +c_uint128 = c_int128 +void = None +if ctypes.sizeof(ctypes.c_longdouble) == 16: + c_long_double_t = ctypes.c_longdouble +else: + c_long_double_t = ctypes.c_ubyte*16 + +def string_cast(char_pointer, encoding='utf-8', errors='strict'): + value = ctypes.cast(char_pointer, ctypes.c_char_p).value + if value is not None and encoding is not None: + value = value.decode(encoding, errors=errors) + return value + + +def char_pointer_cast(string, encoding='utf-8'): + if encoding is not None: + try: + string = string.encode(encoding) + except AttributeError: + # In Python3, bytes has no encode attribute + pass + string = ctypes.c_char_p(string) + return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) + + + + + +V11_STRUCTS_H_ = True # macro +uint32_t = True # macro +uint8_t = True # macro +uint16_t = True # macro +uint64_t = True # macro +class struct_v11_gfx_mqd(Structure): + pass + +struct_v11_gfx_mqd._pack_ = 1 # source:False +struct_v11_gfx_mqd._fields_ = [ + ('shadow_base_lo', ctypes.c_uint32), + ('shadow_base_hi', ctypes.c_uint32), + ('gds_bkup_base_lo', ctypes.c_uint32), + ('gds_bkup_base_hi', ctypes.c_uint32), + ('fw_work_area_base_lo', ctypes.c_uint32), + ('fw_work_area_base_hi', ctypes.c_uint32), + ('shadow_initialized', ctypes.c_uint32), + ('ib_vmid', ctypes.c_uint32), + ('reserved_8', ctypes.c_uint32), + ('reserved_9', ctypes.c_uint32), + ('reserved_10', ctypes.c_uint32), + ('reserved_11', ctypes.c_uint32), + ('reserved_12', ctypes.c_uint32), + ('reserved_13', ctypes.c_uint32), + ('reserved_14', ctypes.c_uint32), + ('reserved_15', ctypes.c_uint32), + ('reserved_16', ctypes.c_uint32), + ('reserved_17', ctypes.c_uint32), + ('reserved_18', ctypes.c_uint32), + ('reserved_19', ctypes.c_uint32), + ('reserved_20', ctypes.c_uint32), + ('reserved_21', ctypes.c_uint32), + ('reserved_22', ctypes.c_uint32), + ('reserved_23', ctypes.c_uint32), + ('reserved_24', ctypes.c_uint32), + ('reserved_25', ctypes.c_uint32), + ('reserved_26', ctypes.c_uint32), + ('reserved_27', ctypes.c_uint32), + ('reserved_28', ctypes.c_uint32), + ('reserved_29', ctypes.c_uint32), + ('reserved_30', ctypes.c_uint32), + ('reserved_31', ctypes.c_uint32), + ('reserved_32', ctypes.c_uint32), + ('reserved_33', ctypes.c_uint32), + ('reserved_34', ctypes.c_uint32), + ('reserved_35', ctypes.c_uint32), + ('reserved_36', ctypes.c_uint32), + ('reserved_37', ctypes.c_uint32), + ('reserved_38', ctypes.c_uint32), + ('reserved_39', ctypes.c_uint32), + ('reserved_40', ctypes.c_uint32), + ('reserved_41', ctypes.c_uint32), + ('reserved_42', ctypes.c_uint32), + ('reserved_43', ctypes.c_uint32), + ('reserved_44', ctypes.c_uint32), + ('reserved_45', ctypes.c_uint32), + ('reserved_46', ctypes.c_uint32), + ('reserved_47', ctypes.c_uint32), + ('reserved_48', ctypes.c_uint32), + ('reserved_49', ctypes.c_uint32), + ('reserved_50', ctypes.c_uint32), + ('reserved_51', ctypes.c_uint32), + ('reserved_52', ctypes.c_uint32), + ('reserved_53', ctypes.c_uint32), + ('reserved_54', ctypes.c_uint32), + ('reserved_55', ctypes.c_uint32), + ('reserved_56', ctypes.c_uint32), + ('reserved_57', ctypes.c_uint32), + ('reserved_58', ctypes.c_uint32), + ('reserved_59', ctypes.c_uint32), + ('reserved_60', ctypes.c_uint32), + ('reserved_61', ctypes.c_uint32), + ('reserved_62', ctypes.c_uint32), + ('reserved_63', ctypes.c_uint32), + ('reserved_64', ctypes.c_uint32), + ('reserved_65', ctypes.c_uint32), + ('reserved_66', ctypes.c_uint32), + ('reserved_67', ctypes.c_uint32), + ('reserved_68', ctypes.c_uint32), + ('reserved_69', ctypes.c_uint32), + ('reserved_70', ctypes.c_uint32), + ('reserved_71', ctypes.c_uint32), + ('reserved_72', ctypes.c_uint32), + ('reserved_73', ctypes.c_uint32), + ('reserved_74', ctypes.c_uint32), + ('reserved_75', ctypes.c_uint32), + ('reserved_76', ctypes.c_uint32), + ('reserved_77', ctypes.c_uint32), + ('reserved_78', ctypes.c_uint32), + ('reserved_79', ctypes.c_uint32), + ('reserved_80', ctypes.c_uint32), + ('reserved_81', ctypes.c_uint32), + ('reserved_82', ctypes.c_uint32), + ('reserved_83', ctypes.c_uint32), + ('checksum_lo', ctypes.c_uint32), + ('checksum_hi', ctypes.c_uint32), + ('cp_mqd_query_time_lo', ctypes.c_uint32), + ('cp_mqd_query_time_hi', ctypes.c_uint32), + ('reserved_88', ctypes.c_uint32), + ('reserved_89', ctypes.c_uint32), + ('reserved_90', ctypes.c_uint32), + ('reserved_91', ctypes.c_uint32), + ('cp_mqd_query_wave_count', ctypes.c_uint32), + ('cp_mqd_query_gfx_hqd_rptr', ctypes.c_uint32), + ('cp_mqd_query_gfx_hqd_wptr', ctypes.c_uint32), + ('cp_mqd_query_gfx_hqd_offset', ctypes.c_uint32), + ('reserved_96', ctypes.c_uint32), + ('reserved_97', ctypes.c_uint32), + ('reserved_98', ctypes.c_uint32), + ('reserved_99', ctypes.c_uint32), + ('reserved_100', ctypes.c_uint32), + ('reserved_101', ctypes.c_uint32), + ('reserved_102', ctypes.c_uint32), + ('reserved_103', ctypes.c_uint32), + ('control_buf_addr_lo', ctypes.c_uint32), + ('control_buf_addr_hi', ctypes.c_uint32), + ('disable_queue', ctypes.c_uint32), + ('reserved_107', ctypes.c_uint32), + ('reserved_108', ctypes.c_uint32), + ('reserved_109', ctypes.c_uint32), + ('reserved_110', ctypes.c_uint32), + ('reserved_111', ctypes.c_uint32), + ('reserved_112', ctypes.c_uint32), + ('reserved_113', ctypes.c_uint32), + ('reserved_114', ctypes.c_uint32), + ('reserved_115', ctypes.c_uint32), + ('reserved_116', ctypes.c_uint32), + ('reserved_117', ctypes.c_uint32), + ('reserved_118', ctypes.c_uint32), + ('reserved_119', ctypes.c_uint32), + ('reserved_120', ctypes.c_uint32), + ('reserved_121', ctypes.c_uint32), + ('reserved_122', ctypes.c_uint32), + ('reserved_123', ctypes.c_uint32), + ('reserved_124', ctypes.c_uint32), + ('reserved_125', ctypes.c_uint32), + ('reserved_126', ctypes.c_uint32), + ('reserved_127', ctypes.c_uint32), + ('cp_mqd_base_addr', ctypes.c_uint32), + ('cp_mqd_base_addr_hi', ctypes.c_uint32), + ('cp_gfx_hqd_active', ctypes.c_uint32), + ('cp_gfx_hqd_vmid', ctypes.c_uint32), + ('reserved_131', ctypes.c_uint32), + ('reserved_132', ctypes.c_uint32), + ('cp_gfx_hqd_queue_priority', ctypes.c_uint32), + ('cp_gfx_hqd_quantum', ctypes.c_uint32), + ('cp_gfx_hqd_base', ctypes.c_uint32), + ('cp_gfx_hqd_base_hi', ctypes.c_uint32), + ('cp_gfx_hqd_rptr', ctypes.c_uint32), + ('cp_gfx_hqd_rptr_addr', ctypes.c_uint32), + ('cp_gfx_hqd_rptr_addr_hi', ctypes.c_uint32), + ('cp_rb_wptr_poll_addr_lo', ctypes.c_uint32), + ('cp_rb_wptr_poll_addr_hi', ctypes.c_uint32), + ('cp_rb_doorbell_control', ctypes.c_uint32), + ('cp_gfx_hqd_offset', ctypes.c_uint32), + ('cp_gfx_hqd_cntl', ctypes.c_uint32), + ('reserved_146', ctypes.c_uint32), + ('reserved_147', ctypes.c_uint32), + ('cp_gfx_hqd_csmd_rptr', ctypes.c_uint32), + ('cp_gfx_hqd_wptr', ctypes.c_uint32), + ('cp_gfx_hqd_wptr_hi', ctypes.c_uint32), + ('reserved_151', ctypes.c_uint32), + ('reserved_152', ctypes.c_uint32), + ('reserved_153', ctypes.c_uint32), + ('reserved_154', ctypes.c_uint32), + ('reserved_155', ctypes.c_uint32), + ('cp_gfx_hqd_mapped', ctypes.c_uint32), + ('cp_gfx_hqd_que_mgr_control', ctypes.c_uint32), + ('reserved_158', ctypes.c_uint32), + ('reserved_159', ctypes.c_uint32), + ('cp_gfx_hqd_hq_status0', ctypes.c_uint32), + ('cp_gfx_hqd_hq_control0', ctypes.c_uint32), + ('cp_gfx_mqd_control', ctypes.c_uint32), + ('reserved_163', ctypes.c_uint32), + ('reserved_164', ctypes.c_uint32), + ('reserved_165', ctypes.c_uint32), + ('reserved_166', ctypes.c_uint32), + ('reserved_167', ctypes.c_uint32), + ('reserved_168', ctypes.c_uint32), + ('reserved_169', ctypes.c_uint32), + ('cp_num_prim_needed_count0_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count0_hi', ctypes.c_uint32), + ('cp_num_prim_needed_count1_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count1_hi', ctypes.c_uint32), + ('cp_num_prim_needed_count2_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count2_hi', ctypes.c_uint32), + ('cp_num_prim_needed_count3_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count3_hi', ctypes.c_uint32), + ('cp_num_prim_written_count0_lo', ctypes.c_uint32), + ('cp_num_prim_written_count0_hi', ctypes.c_uint32), + ('cp_num_prim_written_count1_lo', ctypes.c_uint32), + ('cp_num_prim_written_count1_hi', ctypes.c_uint32), + ('cp_num_prim_written_count2_lo', ctypes.c_uint32), + ('cp_num_prim_written_count2_hi', ctypes.c_uint32), + ('cp_num_prim_written_count3_lo', ctypes.c_uint32), + ('cp_num_prim_written_count3_hi', ctypes.c_uint32), + ('reserved_186', ctypes.c_uint32), + ('reserved_187', ctypes.c_uint32), + ('reserved_188', ctypes.c_uint32), + ('reserved_189', ctypes.c_uint32), + ('mp1_smn_fps_cnt', ctypes.c_uint32), + ('sq_thread_trace_buf0_base', ctypes.c_uint32), + ('sq_thread_trace_buf0_size', ctypes.c_uint32), + ('sq_thread_trace_buf1_base', ctypes.c_uint32), + ('sq_thread_trace_buf1_size', ctypes.c_uint32), + ('sq_thread_trace_wptr', ctypes.c_uint32), + ('sq_thread_trace_mask', ctypes.c_uint32), + ('sq_thread_trace_token_mask', ctypes.c_uint32), + ('sq_thread_trace_ctrl', ctypes.c_uint32), + ('sq_thread_trace_status', ctypes.c_uint32), + ('sq_thread_trace_dropped_cntr', ctypes.c_uint32), + ('sq_thread_trace_finish_done_debug', ctypes.c_uint32), + ('sq_thread_trace_gfx_draw_cntr', ctypes.c_uint32), + ('sq_thread_trace_gfx_marker_cntr', ctypes.c_uint32), + ('sq_thread_trace_hp3d_draw_cntr', ctypes.c_uint32), + ('sq_thread_trace_hp3d_marker_cntr', ctypes.c_uint32), + ('reserved_206', ctypes.c_uint32), + ('reserved_207', ctypes.c_uint32), + ('cp_sc_psinvoc_count0_lo', ctypes.c_uint32), + ('cp_sc_psinvoc_count0_hi', ctypes.c_uint32), + ('cp_pa_cprim_count_lo', ctypes.c_uint32), + ('cp_pa_cprim_count_hi', ctypes.c_uint32), + ('cp_pa_cinvoc_count_lo', ctypes.c_uint32), + ('cp_pa_cinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_vsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_vsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_gsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_gsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_gsprim_count_lo', ctypes.c_uint32), + ('cp_vgt_gsprim_count_hi', ctypes.c_uint32), + ('cp_vgt_iaprim_count_lo', ctypes.c_uint32), + ('cp_vgt_iaprim_count_hi', ctypes.c_uint32), + ('cp_vgt_iavert_count_lo', ctypes.c_uint32), + ('cp_vgt_iavert_count_hi', ctypes.c_uint32), + ('cp_vgt_hsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_hsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_dsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_dsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_csinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_csinvoc_count_hi', ctypes.c_uint32), + ('reserved_230', ctypes.c_uint32), + ('reserved_231', ctypes.c_uint32), + ('reserved_232', ctypes.c_uint32), + ('reserved_233', ctypes.c_uint32), + ('reserved_234', ctypes.c_uint32), + ('reserved_235', ctypes.c_uint32), + ('reserved_236', ctypes.c_uint32), + ('reserved_237', ctypes.c_uint32), + ('reserved_238', ctypes.c_uint32), + ('reserved_239', ctypes.c_uint32), + ('reserved_240', ctypes.c_uint32), + ('reserved_241', ctypes.c_uint32), + ('reserved_242', ctypes.c_uint32), + ('reserved_243', ctypes.c_uint32), + ('reserved_244', ctypes.c_uint32), + ('reserved_245', ctypes.c_uint32), + ('reserved_246', ctypes.c_uint32), + ('reserved_247', ctypes.c_uint32), + ('reserved_248', ctypes.c_uint32), + ('reserved_249', ctypes.c_uint32), + ('reserved_250', ctypes.c_uint32), + ('reserved_251', ctypes.c_uint32), + ('reserved_252', ctypes.c_uint32), + ('reserved_253', ctypes.c_uint32), + ('reserved_254', ctypes.c_uint32), + ('reserved_255', ctypes.c_uint32), + ('reserved_256', ctypes.c_uint32), + ('reserved_257', ctypes.c_uint32), + ('reserved_258', ctypes.c_uint32), + ('reserved_259', ctypes.c_uint32), + ('reserved_260', ctypes.c_uint32), + ('reserved_261', ctypes.c_uint32), + ('reserved_262', ctypes.c_uint32), + ('reserved_263', ctypes.c_uint32), + ('reserved_264', ctypes.c_uint32), + ('reserved_265', ctypes.c_uint32), + ('reserved_266', ctypes.c_uint32), + ('reserved_267', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_0', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_1', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_2', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_3', ctypes.c_uint32), + ('reserved_272', ctypes.c_uint32), + ('reserved_273', ctypes.c_uint32), + ('reserved_274', ctypes.c_uint32), + ('reserved_275', ctypes.c_uint32), + ('vgt_dma_max_size', ctypes.c_uint32), + ('vgt_dma_num_instances', ctypes.c_uint32), + ('reserved_278', ctypes.c_uint32), + ('reserved_279', ctypes.c_uint32), + ('reserved_280', ctypes.c_uint32), + ('reserved_281', ctypes.c_uint32), + ('reserved_282', ctypes.c_uint32), + ('reserved_283', ctypes.c_uint32), + ('reserved_284', ctypes.c_uint32), + ('reserved_285', ctypes.c_uint32), + ('reserved_286', ctypes.c_uint32), + ('reserved_287', ctypes.c_uint32), + ('it_set_base_ib_addr_lo', ctypes.c_uint32), + ('it_set_base_ib_addr_hi', ctypes.c_uint32), + ('reserved_290', ctypes.c_uint32), + ('reserved_291', ctypes.c_uint32), + ('reserved_292', ctypes.c_uint32), + ('reserved_293', ctypes.c_uint32), + ('reserved_294', ctypes.c_uint32), + ('reserved_295', ctypes.c_uint32), + ('reserved_296', ctypes.c_uint32), + ('reserved_297', ctypes.c_uint32), + ('reserved_298', ctypes.c_uint32), + ('reserved_299', ctypes.c_uint32), + ('reserved_300', ctypes.c_uint32), + ('reserved_301', ctypes.c_uint32), + ('reserved_302', ctypes.c_uint32), + ('reserved_303', ctypes.c_uint32), + ('reserved_304', ctypes.c_uint32), + ('reserved_305', ctypes.c_uint32), + ('reserved_306', ctypes.c_uint32), + ('reserved_307', ctypes.c_uint32), + ('reserved_308', ctypes.c_uint32), + ('reserved_309', ctypes.c_uint32), + ('reserved_310', ctypes.c_uint32), + ('reserved_311', ctypes.c_uint32), + ('reserved_312', ctypes.c_uint32), + ('reserved_313', ctypes.c_uint32), + ('reserved_314', ctypes.c_uint32), + ('reserved_315', ctypes.c_uint32), + ('reserved_316', ctypes.c_uint32), + ('reserved_317', ctypes.c_uint32), + ('reserved_318', ctypes.c_uint32), + ('reserved_319', ctypes.c_uint32), + ('reserved_320', ctypes.c_uint32), + ('reserved_321', ctypes.c_uint32), + ('reserved_322', ctypes.c_uint32), + ('reserved_323', ctypes.c_uint32), + ('reserved_324', ctypes.c_uint32), + ('reserved_325', ctypes.c_uint32), + ('reserved_326', ctypes.c_uint32), + ('reserved_327', ctypes.c_uint32), + ('reserved_328', ctypes.c_uint32), + ('reserved_329', ctypes.c_uint32), + ('reserved_330', ctypes.c_uint32), + ('reserved_331', ctypes.c_uint32), + ('reserved_332', ctypes.c_uint32), + ('reserved_333', ctypes.c_uint32), + ('reserved_334', ctypes.c_uint32), + ('reserved_335', ctypes.c_uint32), + ('reserved_336', ctypes.c_uint32), + ('reserved_337', ctypes.c_uint32), + ('reserved_338', ctypes.c_uint32), + ('reserved_339', ctypes.c_uint32), + ('reserved_340', ctypes.c_uint32), + ('reserved_341', ctypes.c_uint32), + ('reserved_342', ctypes.c_uint32), + ('reserved_343', ctypes.c_uint32), + ('reserved_344', ctypes.c_uint32), + ('reserved_345', ctypes.c_uint32), + ('reserved_346', ctypes.c_uint32), + ('reserved_347', ctypes.c_uint32), + ('reserved_348', ctypes.c_uint32), + ('reserved_349', ctypes.c_uint32), + ('reserved_350', ctypes.c_uint32), + ('reserved_351', ctypes.c_uint32), + ('reserved_352', ctypes.c_uint32), + ('reserved_353', ctypes.c_uint32), + ('reserved_354', ctypes.c_uint32), + ('reserved_355', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_ps', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_vs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_gs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_hs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_ps', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_vs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_gs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_hs', ctypes.c_uint32), + ('db_occlusion_count0_low_00', ctypes.c_uint32), + ('db_occlusion_count0_hi_00', ctypes.c_uint32), + ('db_occlusion_count1_low_00', ctypes.c_uint32), + ('db_occlusion_count1_hi_00', ctypes.c_uint32), + ('db_occlusion_count2_low_00', ctypes.c_uint32), + ('db_occlusion_count2_hi_00', ctypes.c_uint32), + ('db_occlusion_count3_low_00', ctypes.c_uint32), + ('db_occlusion_count3_hi_00', ctypes.c_uint32), + ('db_occlusion_count0_low_01', ctypes.c_uint32), + ('db_occlusion_count0_hi_01', ctypes.c_uint32), + ('db_occlusion_count1_low_01', ctypes.c_uint32), + ('db_occlusion_count1_hi_01', ctypes.c_uint32), + ('db_occlusion_count2_low_01', ctypes.c_uint32), + ('db_occlusion_count2_hi_01', ctypes.c_uint32), + ('db_occlusion_count3_low_01', ctypes.c_uint32), + ('db_occlusion_count3_hi_01', ctypes.c_uint32), + ('db_occlusion_count0_low_02', ctypes.c_uint32), + ('db_occlusion_count0_hi_02', ctypes.c_uint32), + ('db_occlusion_count1_low_02', ctypes.c_uint32), + ('db_occlusion_count1_hi_02', ctypes.c_uint32), + ('db_occlusion_count2_low_02', ctypes.c_uint32), + ('db_occlusion_count2_hi_02', ctypes.c_uint32), + ('db_occlusion_count3_low_02', ctypes.c_uint32), + ('db_occlusion_count3_hi_02', ctypes.c_uint32), + ('db_occlusion_count0_low_03', ctypes.c_uint32), + ('db_occlusion_count0_hi_03', ctypes.c_uint32), + ('db_occlusion_count1_low_03', ctypes.c_uint32), + ('db_occlusion_count1_hi_03', ctypes.c_uint32), + ('db_occlusion_count2_low_03', ctypes.c_uint32), + ('db_occlusion_count2_hi_03', ctypes.c_uint32), + ('db_occlusion_count3_low_03', ctypes.c_uint32), + ('db_occlusion_count3_hi_03', ctypes.c_uint32), + ('db_occlusion_count0_low_04', ctypes.c_uint32), + ('db_occlusion_count0_hi_04', ctypes.c_uint32), + ('db_occlusion_count1_low_04', ctypes.c_uint32), + ('db_occlusion_count1_hi_04', ctypes.c_uint32), + ('db_occlusion_count2_low_04', ctypes.c_uint32), + ('db_occlusion_count2_hi_04', ctypes.c_uint32), + ('db_occlusion_count3_low_04', ctypes.c_uint32), + ('db_occlusion_count3_hi_04', ctypes.c_uint32), + ('db_occlusion_count0_low_05', ctypes.c_uint32), + ('db_occlusion_count0_hi_05', ctypes.c_uint32), + ('db_occlusion_count1_low_05', ctypes.c_uint32), + ('db_occlusion_count1_hi_05', ctypes.c_uint32), + ('db_occlusion_count2_low_05', ctypes.c_uint32), + ('db_occlusion_count2_hi_05', ctypes.c_uint32), + ('db_occlusion_count3_low_05', ctypes.c_uint32), + ('db_occlusion_count3_hi_05', ctypes.c_uint32), + ('db_occlusion_count0_low_06', ctypes.c_uint32), + ('db_occlusion_count0_hi_06', ctypes.c_uint32), + ('db_occlusion_count1_low_06', ctypes.c_uint32), + ('db_occlusion_count1_hi_06', ctypes.c_uint32), + ('db_occlusion_count2_low_06', ctypes.c_uint32), + ('db_occlusion_count2_hi_06', ctypes.c_uint32), + ('db_occlusion_count3_low_06', ctypes.c_uint32), + ('db_occlusion_count3_hi_06', ctypes.c_uint32), + ('db_occlusion_count0_low_07', ctypes.c_uint32), + ('db_occlusion_count0_hi_07', ctypes.c_uint32), + ('db_occlusion_count1_low_07', ctypes.c_uint32), + ('db_occlusion_count1_hi_07', ctypes.c_uint32), + ('db_occlusion_count2_low_07', ctypes.c_uint32), + ('db_occlusion_count2_hi_07', ctypes.c_uint32), + ('db_occlusion_count3_low_07', ctypes.c_uint32), + ('db_occlusion_count3_hi_07', ctypes.c_uint32), + ('db_occlusion_count0_low_10', ctypes.c_uint32), + ('db_occlusion_count0_hi_10', ctypes.c_uint32), + ('db_occlusion_count1_low_10', ctypes.c_uint32), + ('db_occlusion_count1_hi_10', ctypes.c_uint32), + ('db_occlusion_count2_low_10', ctypes.c_uint32), + ('db_occlusion_count2_hi_10', ctypes.c_uint32), + ('db_occlusion_count3_low_10', ctypes.c_uint32), + ('db_occlusion_count3_hi_10', ctypes.c_uint32), + ('db_occlusion_count0_low_11', ctypes.c_uint32), + ('db_occlusion_count0_hi_11', ctypes.c_uint32), + ('db_occlusion_count1_low_11', ctypes.c_uint32), + ('db_occlusion_count1_hi_11', ctypes.c_uint32), + ('db_occlusion_count2_low_11', ctypes.c_uint32), + ('db_occlusion_count2_hi_11', ctypes.c_uint32), + ('db_occlusion_count3_low_11', ctypes.c_uint32), + ('db_occlusion_count3_hi_11', ctypes.c_uint32), + ('db_occlusion_count0_low_12', ctypes.c_uint32), + ('db_occlusion_count0_hi_12', ctypes.c_uint32), + ('db_occlusion_count1_low_12', ctypes.c_uint32), + ('db_occlusion_count1_hi_12', ctypes.c_uint32), + ('db_occlusion_count2_low_12', ctypes.c_uint32), + ('db_occlusion_count2_hi_12', ctypes.c_uint32), + ('db_occlusion_count3_low_12', ctypes.c_uint32), + ('db_occlusion_count3_hi_12', ctypes.c_uint32), + ('db_occlusion_count0_low_13', ctypes.c_uint32), + ('db_occlusion_count0_hi_13', ctypes.c_uint32), + ('db_occlusion_count1_low_13', ctypes.c_uint32), + ('db_occlusion_count1_hi_13', ctypes.c_uint32), + ('db_occlusion_count2_low_13', ctypes.c_uint32), + ('db_occlusion_count2_hi_13', ctypes.c_uint32), + ('db_occlusion_count3_low_13', ctypes.c_uint32), + ('db_occlusion_count3_hi_13', ctypes.c_uint32), + ('db_occlusion_count0_low_14', ctypes.c_uint32), + ('db_occlusion_count0_hi_14', ctypes.c_uint32), + ('db_occlusion_count1_low_14', ctypes.c_uint32), + ('db_occlusion_count1_hi_14', ctypes.c_uint32), + ('db_occlusion_count2_low_14', ctypes.c_uint32), + ('db_occlusion_count2_hi_14', ctypes.c_uint32), + ('db_occlusion_count3_low_14', ctypes.c_uint32), + ('db_occlusion_count3_hi_14', ctypes.c_uint32), + ('db_occlusion_count0_low_15', ctypes.c_uint32), + ('db_occlusion_count0_hi_15', ctypes.c_uint32), + ('db_occlusion_count1_low_15', ctypes.c_uint32), + ('db_occlusion_count1_hi_15', ctypes.c_uint32), + ('db_occlusion_count2_low_15', ctypes.c_uint32), + ('db_occlusion_count2_hi_15', ctypes.c_uint32), + ('db_occlusion_count3_low_15', ctypes.c_uint32), + ('db_occlusion_count3_hi_15', ctypes.c_uint32), + ('db_occlusion_count0_low_16', ctypes.c_uint32), + ('db_occlusion_count0_hi_16', ctypes.c_uint32), + ('db_occlusion_count1_low_16', ctypes.c_uint32), + ('db_occlusion_count1_hi_16', ctypes.c_uint32), + ('db_occlusion_count2_low_16', ctypes.c_uint32), + ('db_occlusion_count2_hi_16', ctypes.c_uint32), + ('db_occlusion_count3_low_16', ctypes.c_uint32), + ('db_occlusion_count3_hi_16', ctypes.c_uint32), + ('db_occlusion_count0_low_17', ctypes.c_uint32), + ('db_occlusion_count0_hi_17', ctypes.c_uint32), + ('db_occlusion_count1_low_17', ctypes.c_uint32), + ('db_occlusion_count1_hi_17', ctypes.c_uint32), + ('db_occlusion_count2_low_17', ctypes.c_uint32), + ('db_occlusion_count2_hi_17', ctypes.c_uint32), + ('db_occlusion_count3_low_17', ctypes.c_uint32), + ('db_occlusion_count3_hi_17', ctypes.c_uint32), + ('reserved_492', ctypes.c_uint32), + ('reserved_493', ctypes.c_uint32), + ('reserved_494', ctypes.c_uint32), + ('reserved_495', ctypes.c_uint32), + ('reserved_496', ctypes.c_uint32), + ('reserved_497', ctypes.c_uint32), + ('reserved_498', ctypes.c_uint32), + ('reserved_499', ctypes.c_uint32), + ('reserved_500', ctypes.c_uint32), + ('reserved_501', ctypes.c_uint32), + ('reserved_502', ctypes.c_uint32), + ('reserved_503', ctypes.c_uint32), + ('reserved_504', ctypes.c_uint32), + ('reserved_505', ctypes.c_uint32), + ('reserved_506', ctypes.c_uint32), + ('reserved_507', ctypes.c_uint32), + ('reserved_508', ctypes.c_uint32), + ('reserved_509', ctypes.c_uint32), + ('reserved_510', ctypes.c_uint32), + ('reserved_511', ctypes.c_uint32), +] + +class struct_v11_sdma_mqd(Structure): + pass + +struct_v11_sdma_mqd._pack_ = 1 # source:False +struct_v11_sdma_mqd._fields_ = [ + ('sdmax_rlcx_rb_cntl', ctypes.c_uint32), + ('sdmax_rlcx_rb_base', ctypes.c_uint32), + ('sdmax_rlcx_rb_base_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr_addr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr_addr_lo', ctypes.c_uint32), + ('sdmax_rlcx_ib_cntl', ctypes.c_uint32), + ('sdmax_rlcx_ib_rptr', ctypes.c_uint32), + ('sdmax_rlcx_ib_offset', ctypes.c_uint32), + ('sdmax_rlcx_ib_base_lo', ctypes.c_uint32), + ('sdmax_rlcx_ib_base_hi', ctypes.c_uint32), + ('sdmax_rlcx_ib_size', ctypes.c_uint32), + ('sdmax_rlcx_skip_cntl', ctypes.c_uint32), + ('sdmax_rlcx_context_status', ctypes.c_uint32), + ('sdmax_rlcx_doorbell', ctypes.c_uint32), + ('sdmax_rlcx_doorbell_log', ctypes.c_uint32), + ('sdmax_rlcx_doorbell_offset', ctypes.c_uint32), + ('sdmax_rlcx_csa_addr_lo', ctypes.c_uint32), + ('sdmax_rlcx_csa_addr_hi', ctypes.c_uint32), + ('sdmax_rlcx_sched_cntl', ctypes.c_uint32), + ('sdmax_rlcx_ib_sub_remain', ctypes.c_uint32), + ('sdmax_rlcx_preempt', ctypes.c_uint32), + ('sdmax_rlcx_dummy_reg', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr_poll_addr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr_poll_addr_lo', ctypes.c_uint32), + ('sdmax_rlcx_rb_aql_cntl', ctypes.c_uint32), + ('sdmax_rlcx_minor_ptr_update', ctypes.c_uint32), + ('sdmax_rlcx_rb_preempt', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data0', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data1', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data2', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data3', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data4', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data5', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data6', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data7', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data8', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data9', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data10', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_cntl', ctypes.c_uint32), + ('sdmax_rlcx_f32_dbg0', ctypes.c_uint32), + ('sdmax_rlcx_f32_dbg1', ctypes.c_uint32), + ('reserved_45', ctypes.c_uint32), + ('reserved_46', ctypes.c_uint32), + ('reserved_47', ctypes.c_uint32), + ('reserved_48', ctypes.c_uint32), + ('reserved_49', ctypes.c_uint32), + ('reserved_50', ctypes.c_uint32), + ('reserved_51', ctypes.c_uint32), + ('reserved_52', ctypes.c_uint32), + ('reserved_53', ctypes.c_uint32), + ('reserved_54', ctypes.c_uint32), + ('reserved_55', ctypes.c_uint32), + ('reserved_56', ctypes.c_uint32), + ('reserved_57', ctypes.c_uint32), + ('reserved_58', ctypes.c_uint32), + ('reserved_59', ctypes.c_uint32), + ('reserved_60', ctypes.c_uint32), + ('reserved_61', ctypes.c_uint32), + ('reserved_62', ctypes.c_uint32), + ('reserved_63', ctypes.c_uint32), + ('reserved_64', ctypes.c_uint32), + ('reserved_65', ctypes.c_uint32), + ('reserved_66', ctypes.c_uint32), + ('reserved_67', ctypes.c_uint32), + ('reserved_68', ctypes.c_uint32), + ('reserved_69', ctypes.c_uint32), + ('reserved_70', ctypes.c_uint32), + ('reserved_71', ctypes.c_uint32), + ('reserved_72', ctypes.c_uint32), + ('reserved_73', ctypes.c_uint32), + ('reserved_74', ctypes.c_uint32), + ('reserved_75', ctypes.c_uint32), + ('reserved_76', ctypes.c_uint32), + ('reserved_77', ctypes.c_uint32), + ('reserved_78', ctypes.c_uint32), + ('reserved_79', ctypes.c_uint32), + ('reserved_80', ctypes.c_uint32), + ('reserved_81', ctypes.c_uint32), + ('reserved_82', ctypes.c_uint32), + ('reserved_83', ctypes.c_uint32), + ('reserved_84', ctypes.c_uint32), + ('reserved_85', ctypes.c_uint32), + ('reserved_86', ctypes.c_uint32), + ('reserved_87', ctypes.c_uint32), + ('reserved_88', ctypes.c_uint32), + ('reserved_89', ctypes.c_uint32), + ('reserved_90', ctypes.c_uint32), + ('reserved_91', ctypes.c_uint32), + ('reserved_92', ctypes.c_uint32), + ('reserved_93', ctypes.c_uint32), + ('reserved_94', ctypes.c_uint32), + ('reserved_95', ctypes.c_uint32), + ('reserved_96', ctypes.c_uint32), + ('reserved_97', ctypes.c_uint32), + ('reserved_98', ctypes.c_uint32), + ('reserved_99', ctypes.c_uint32), + ('reserved_100', ctypes.c_uint32), + ('reserved_101', ctypes.c_uint32), + ('reserved_102', ctypes.c_uint32), + ('reserved_103', ctypes.c_uint32), + ('reserved_104', ctypes.c_uint32), + ('reserved_105', ctypes.c_uint32), + ('reserved_106', ctypes.c_uint32), + ('reserved_107', ctypes.c_uint32), + ('reserved_108', ctypes.c_uint32), + ('reserved_109', ctypes.c_uint32), + ('reserved_110', ctypes.c_uint32), + ('reserved_111', ctypes.c_uint32), + ('reserved_112', ctypes.c_uint32), + ('reserved_113', ctypes.c_uint32), + ('reserved_114', ctypes.c_uint32), + ('reserved_115', ctypes.c_uint32), + ('reserved_116', ctypes.c_uint32), + ('reserved_117', ctypes.c_uint32), + ('reserved_118', ctypes.c_uint32), + ('reserved_119', ctypes.c_uint32), + ('reserved_120', ctypes.c_uint32), + ('reserved_121', ctypes.c_uint32), + ('reserved_122', ctypes.c_uint32), + ('reserved_123', ctypes.c_uint32), + ('reserved_124', ctypes.c_uint32), + ('reserved_125', ctypes.c_uint32), + ('sdma_engine_id', ctypes.c_uint32), + ('sdma_queue_id', ctypes.c_uint32), +] + +class struct_v11_compute_mqd(Structure): + pass + +struct_v11_compute_mqd._pack_ = 1 # source:False +struct_v11_compute_mqd._fields_ = [ + ('header', ctypes.c_uint32), + ('compute_dispatch_initiator', ctypes.c_uint32), + ('compute_dim_x', ctypes.c_uint32), + ('compute_dim_y', ctypes.c_uint32), + ('compute_dim_z', ctypes.c_uint32), + ('compute_start_x', ctypes.c_uint32), + ('compute_start_y', ctypes.c_uint32), + ('compute_start_z', ctypes.c_uint32), + ('compute_num_thread_x', ctypes.c_uint32), + ('compute_num_thread_y', ctypes.c_uint32), + ('compute_num_thread_z', ctypes.c_uint32), + ('compute_pipelinestat_enable', ctypes.c_uint32), + ('compute_perfcount_enable', ctypes.c_uint32), + ('compute_pgm_lo', ctypes.c_uint32), + ('compute_pgm_hi', ctypes.c_uint32), + ('compute_dispatch_pkt_addr_lo', ctypes.c_uint32), + ('compute_dispatch_pkt_addr_hi', ctypes.c_uint32), + ('compute_dispatch_scratch_base_lo', ctypes.c_uint32), + ('compute_dispatch_scratch_base_hi', ctypes.c_uint32), + ('compute_pgm_rsrc1', ctypes.c_uint32), + ('compute_pgm_rsrc2', ctypes.c_uint32), + ('compute_vmid', ctypes.c_uint32), + ('compute_resource_limits', ctypes.c_uint32), + ('compute_static_thread_mgmt_se0', ctypes.c_uint32), + ('compute_static_thread_mgmt_se1', ctypes.c_uint32), + ('compute_tmpring_size', ctypes.c_uint32), + ('compute_static_thread_mgmt_se2', ctypes.c_uint32), + ('compute_static_thread_mgmt_se3', ctypes.c_uint32), + ('compute_restart_x', ctypes.c_uint32), + ('compute_restart_y', ctypes.c_uint32), + ('compute_restart_z', ctypes.c_uint32), + ('compute_thread_trace_enable', ctypes.c_uint32), + ('compute_misc_reserved', ctypes.c_uint32), + ('compute_dispatch_id', ctypes.c_uint32), + ('compute_threadgroup_id', ctypes.c_uint32), + ('compute_req_ctrl', ctypes.c_uint32), + ('reserved_36', ctypes.c_uint32), + ('compute_user_accum_0', ctypes.c_uint32), + ('compute_user_accum_1', ctypes.c_uint32), + ('compute_user_accum_2', ctypes.c_uint32), + ('compute_user_accum_3', ctypes.c_uint32), + ('compute_pgm_rsrc3', ctypes.c_uint32), + ('compute_ddid_index', ctypes.c_uint32), + ('compute_shader_chksum', ctypes.c_uint32), + ('compute_static_thread_mgmt_se4', ctypes.c_uint32), + ('compute_static_thread_mgmt_se5', ctypes.c_uint32), + ('compute_static_thread_mgmt_se6', ctypes.c_uint32), + ('compute_static_thread_mgmt_se7', ctypes.c_uint32), + ('compute_dispatch_interleave', ctypes.c_uint32), + ('compute_relaunch', ctypes.c_uint32), + ('compute_wave_restore_addr_lo', ctypes.c_uint32), + ('compute_wave_restore_addr_hi', ctypes.c_uint32), + ('compute_wave_restore_control', ctypes.c_uint32), + ('reserved_53', ctypes.c_uint32), + ('reserved_54', ctypes.c_uint32), + ('reserved_55', ctypes.c_uint32), + ('reserved_56', ctypes.c_uint32), + ('reserved_57', ctypes.c_uint32), + ('reserved_58', ctypes.c_uint32), + ('reserved_59', ctypes.c_uint32), + ('reserved_60', ctypes.c_uint32), + ('reserved_61', ctypes.c_uint32), + ('reserved_62', ctypes.c_uint32), + ('reserved_63', ctypes.c_uint32), + ('reserved_64', ctypes.c_uint32), + ('compute_user_data_0', ctypes.c_uint32), + ('compute_user_data_1', ctypes.c_uint32), + ('compute_user_data_2', ctypes.c_uint32), + ('compute_user_data_3', ctypes.c_uint32), + ('compute_user_data_4', ctypes.c_uint32), + ('compute_user_data_5', ctypes.c_uint32), + ('compute_user_data_6', ctypes.c_uint32), + ('compute_user_data_7', ctypes.c_uint32), + ('compute_user_data_8', ctypes.c_uint32), + ('compute_user_data_9', ctypes.c_uint32), + ('compute_user_data_10', ctypes.c_uint32), + ('compute_user_data_11', ctypes.c_uint32), + ('compute_user_data_12', ctypes.c_uint32), + ('compute_user_data_13', ctypes.c_uint32), + ('compute_user_data_14', ctypes.c_uint32), + ('compute_user_data_15', ctypes.c_uint32), + ('cp_compute_csinvoc_count_lo', ctypes.c_uint32), + ('cp_compute_csinvoc_count_hi', ctypes.c_uint32), + ('reserved_83', ctypes.c_uint32), + ('reserved_84', ctypes.c_uint32), + ('reserved_85', ctypes.c_uint32), + ('cp_mqd_query_time_lo', ctypes.c_uint32), + ('cp_mqd_query_time_hi', ctypes.c_uint32), + ('cp_mqd_connect_start_time_lo', ctypes.c_uint32), + ('cp_mqd_connect_start_time_hi', ctypes.c_uint32), + ('cp_mqd_connect_end_time_lo', ctypes.c_uint32), + ('cp_mqd_connect_end_time_hi', ctypes.c_uint32), + ('cp_mqd_connect_end_wf_count', ctypes.c_uint32), + ('cp_mqd_connect_end_pq_rptr', ctypes.c_uint32), + ('cp_mqd_connect_end_pq_wptr', ctypes.c_uint32), + ('cp_mqd_connect_end_ib_rptr', ctypes.c_uint32), + ('cp_mqd_readindex_lo', ctypes.c_uint32), + ('cp_mqd_readindex_hi', ctypes.c_uint32), + ('cp_mqd_save_start_time_lo', ctypes.c_uint32), + ('cp_mqd_save_start_time_hi', ctypes.c_uint32), + ('cp_mqd_save_end_time_lo', ctypes.c_uint32), + ('cp_mqd_save_end_time_hi', ctypes.c_uint32), + ('cp_mqd_restore_start_time_lo', ctypes.c_uint32), + ('cp_mqd_restore_start_time_hi', ctypes.c_uint32), + ('cp_mqd_restore_end_time_lo', ctypes.c_uint32), + ('cp_mqd_restore_end_time_hi', ctypes.c_uint32), + ('disable_queue', ctypes.c_uint32), + ('reserved_107', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt0', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt1', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt2', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt3', ctypes.c_uint32), + ('reserved_112', ctypes.c_uint32), + ('reserved_113', ctypes.c_uint32), + ('cp_pq_exe_status_lo', ctypes.c_uint32), + ('cp_pq_exe_status_hi', ctypes.c_uint32), + ('cp_packet_id_lo', ctypes.c_uint32), + ('cp_packet_id_hi', ctypes.c_uint32), + ('cp_packet_exe_status_lo', ctypes.c_uint32), + ('cp_packet_exe_status_hi', ctypes.c_uint32), + ('gds_save_base_addr_lo', ctypes.c_uint32), + ('gds_save_base_addr_hi', ctypes.c_uint32), + ('gds_save_mask_lo', ctypes.c_uint32), + ('gds_save_mask_hi', ctypes.c_uint32), + ('ctx_save_base_addr_lo', ctypes.c_uint32), + ('ctx_save_base_addr_hi', ctypes.c_uint32), + ('reserved_126', ctypes.c_uint32), + ('reserved_127', ctypes.c_uint32), + ('cp_mqd_base_addr_lo', ctypes.c_uint32), + ('cp_mqd_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_active', ctypes.c_uint32), + ('cp_hqd_vmid', ctypes.c_uint32), + ('cp_hqd_persistent_state', ctypes.c_uint32), + ('cp_hqd_pipe_priority', ctypes.c_uint32), + ('cp_hqd_queue_priority', ctypes.c_uint32), + ('cp_hqd_quantum', ctypes.c_uint32), + ('cp_hqd_pq_base_lo', ctypes.c_uint32), + ('cp_hqd_pq_base_hi', ctypes.c_uint32), + ('cp_hqd_pq_rptr', ctypes.c_uint32), + ('cp_hqd_pq_rptr_report_addr_lo', ctypes.c_uint32), + ('cp_hqd_pq_rptr_report_addr_hi', ctypes.c_uint32), + ('cp_hqd_pq_wptr_poll_addr_lo', ctypes.c_uint32), + ('cp_hqd_pq_wptr_poll_addr_hi', ctypes.c_uint32), + ('cp_hqd_pq_doorbell_control', ctypes.c_uint32), + ('reserved_144', ctypes.c_uint32), + ('cp_hqd_pq_control', ctypes.c_uint32), + ('cp_hqd_ib_base_addr_lo', ctypes.c_uint32), + ('cp_hqd_ib_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_ib_rptr', ctypes.c_uint32), + ('cp_hqd_ib_control', ctypes.c_uint32), + ('cp_hqd_iq_timer', ctypes.c_uint32), + ('cp_hqd_iq_rptr', ctypes.c_uint32), + ('cp_hqd_dequeue_request', ctypes.c_uint32), + ('cp_hqd_dma_offload', ctypes.c_uint32), + ('cp_hqd_sema_cmd', ctypes.c_uint32), + ('cp_hqd_msg_type', ctypes.c_uint32), + ('cp_hqd_atomic0_preop_lo', ctypes.c_uint32), + ('cp_hqd_atomic0_preop_hi', ctypes.c_uint32), + ('cp_hqd_atomic1_preop_lo', ctypes.c_uint32), + ('cp_hqd_atomic1_preop_hi', ctypes.c_uint32), + ('cp_hqd_hq_status0', ctypes.c_uint32), + ('cp_hqd_hq_control0', ctypes.c_uint32), + ('cp_mqd_control', ctypes.c_uint32), + ('cp_hqd_hq_status1', ctypes.c_uint32), + ('cp_hqd_hq_control1', ctypes.c_uint32), + ('cp_hqd_eop_base_addr_lo', ctypes.c_uint32), + ('cp_hqd_eop_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_eop_control', ctypes.c_uint32), + ('cp_hqd_eop_rptr', ctypes.c_uint32), + ('cp_hqd_eop_wptr', ctypes.c_uint32), + ('cp_hqd_eop_done_events', ctypes.c_uint32), + ('cp_hqd_ctx_save_base_addr_lo', ctypes.c_uint32), + ('cp_hqd_ctx_save_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_ctx_save_control', ctypes.c_uint32), + ('cp_hqd_cntl_stack_offset', ctypes.c_uint32), + ('cp_hqd_cntl_stack_size', ctypes.c_uint32), + ('cp_hqd_wg_state_offset', ctypes.c_uint32), + ('cp_hqd_ctx_save_size', ctypes.c_uint32), + ('cp_hqd_gds_resource_state', ctypes.c_uint32), + ('cp_hqd_error', ctypes.c_uint32), + ('cp_hqd_eop_wptr_mem', ctypes.c_uint32), + ('cp_hqd_aql_control', ctypes.c_uint32), + ('cp_hqd_pq_wptr_lo', ctypes.c_uint32), + ('cp_hqd_pq_wptr_hi', ctypes.c_uint32), + ('reserved_184', ctypes.c_uint32), + ('reserved_185', ctypes.c_uint32), + ('reserved_186', ctypes.c_uint32), + ('reserved_187', ctypes.c_uint32), + ('reserved_188', ctypes.c_uint32), + ('reserved_189', ctypes.c_uint32), + ('reserved_190', ctypes.c_uint32), + ('reserved_191', ctypes.c_uint32), + ('iqtimer_pkt_header', ctypes.c_uint32), + ('iqtimer_pkt_dw0', ctypes.c_uint32), + ('iqtimer_pkt_dw1', ctypes.c_uint32), + ('iqtimer_pkt_dw2', ctypes.c_uint32), + ('iqtimer_pkt_dw3', ctypes.c_uint32), + ('iqtimer_pkt_dw4', ctypes.c_uint32), + ('iqtimer_pkt_dw5', ctypes.c_uint32), + ('iqtimer_pkt_dw6', ctypes.c_uint32), + ('iqtimer_pkt_dw7', ctypes.c_uint32), + ('iqtimer_pkt_dw8', ctypes.c_uint32), + ('iqtimer_pkt_dw9', ctypes.c_uint32), + ('iqtimer_pkt_dw10', ctypes.c_uint32), + ('iqtimer_pkt_dw11', ctypes.c_uint32), + ('iqtimer_pkt_dw12', ctypes.c_uint32), + ('iqtimer_pkt_dw13', ctypes.c_uint32), + ('iqtimer_pkt_dw14', ctypes.c_uint32), + ('iqtimer_pkt_dw15', ctypes.c_uint32), + ('iqtimer_pkt_dw16', ctypes.c_uint32), + ('iqtimer_pkt_dw17', ctypes.c_uint32), + ('iqtimer_pkt_dw18', ctypes.c_uint32), + ('iqtimer_pkt_dw19', ctypes.c_uint32), + ('iqtimer_pkt_dw20', ctypes.c_uint32), + ('iqtimer_pkt_dw21', ctypes.c_uint32), + ('iqtimer_pkt_dw22', ctypes.c_uint32), + ('iqtimer_pkt_dw23', ctypes.c_uint32), + ('iqtimer_pkt_dw24', ctypes.c_uint32), + ('iqtimer_pkt_dw25', ctypes.c_uint32), + ('iqtimer_pkt_dw26', ctypes.c_uint32), + ('iqtimer_pkt_dw27', ctypes.c_uint32), + ('iqtimer_pkt_dw28', ctypes.c_uint32), + ('iqtimer_pkt_dw29', ctypes.c_uint32), + ('iqtimer_pkt_dw30', ctypes.c_uint32), + ('iqtimer_pkt_dw31', ctypes.c_uint32), + ('reserved_225', ctypes.c_uint32), + ('reserved_226', ctypes.c_uint32), + ('reserved_227', ctypes.c_uint32), + ('set_resources_header', ctypes.c_uint32), + ('set_resources_dw1', ctypes.c_uint32), + ('set_resources_dw2', ctypes.c_uint32), + ('set_resources_dw3', ctypes.c_uint32), + ('set_resources_dw4', ctypes.c_uint32), + ('set_resources_dw5', ctypes.c_uint32), + ('set_resources_dw6', ctypes.c_uint32), + ('set_resources_dw7', ctypes.c_uint32), + ('reserved_236', ctypes.c_uint32), + ('reserved_237', ctypes.c_uint32), + ('reserved_238', ctypes.c_uint32), + ('reserved_239', ctypes.c_uint32), + ('queue_doorbell_id0', ctypes.c_uint32), + ('queue_doorbell_id1', ctypes.c_uint32), + ('queue_doorbell_id2', ctypes.c_uint32), + ('queue_doorbell_id3', ctypes.c_uint32), + ('queue_doorbell_id4', ctypes.c_uint32), + ('queue_doorbell_id5', ctypes.c_uint32), + ('queue_doorbell_id6', ctypes.c_uint32), + ('queue_doorbell_id7', ctypes.c_uint32), + ('queue_doorbell_id8', ctypes.c_uint32), + ('queue_doorbell_id9', ctypes.c_uint32), + ('queue_doorbell_id10', ctypes.c_uint32), + ('queue_doorbell_id11', ctypes.c_uint32), + ('queue_doorbell_id12', ctypes.c_uint32), + ('queue_doorbell_id13', ctypes.c_uint32), + ('queue_doorbell_id14', ctypes.c_uint32), + ('queue_doorbell_id15', ctypes.c_uint32), + ('control_buf_addr_lo', ctypes.c_uint32), + ('control_buf_addr_hi', ctypes.c_uint32), + ('control_buf_wptr_lo', ctypes.c_uint32), + ('control_buf_wptr_hi', ctypes.c_uint32), + ('control_buf_dptr_lo', ctypes.c_uint32), + ('control_buf_dptr_hi', ctypes.c_uint32), + ('control_buf_num_entries', ctypes.c_uint32), + ('draw_ring_addr_lo', ctypes.c_uint32), + ('draw_ring_addr_hi', ctypes.c_uint32), + ('reserved_265', ctypes.c_uint32), + ('reserved_266', ctypes.c_uint32), + ('reserved_267', ctypes.c_uint32), + ('reserved_268', ctypes.c_uint32), + ('reserved_269', ctypes.c_uint32), + ('reserved_270', ctypes.c_uint32), + ('reserved_271', ctypes.c_uint32), + ('reserved_272', ctypes.c_uint32), + ('reserved_273', ctypes.c_uint32), + ('reserved_274', ctypes.c_uint32), + ('reserved_275', ctypes.c_uint32), + ('reserved_276', ctypes.c_uint32), + ('reserved_277', ctypes.c_uint32), + ('reserved_278', ctypes.c_uint32), + ('reserved_279', ctypes.c_uint32), + ('reserved_280', ctypes.c_uint32), + ('reserved_281', ctypes.c_uint32), + ('reserved_282', ctypes.c_uint32), + ('reserved_283', ctypes.c_uint32), + ('reserved_284', ctypes.c_uint32), + ('reserved_285', ctypes.c_uint32), + ('reserved_286', ctypes.c_uint32), + ('reserved_287', ctypes.c_uint32), + ('reserved_288', ctypes.c_uint32), + ('reserved_289', ctypes.c_uint32), + ('reserved_290', ctypes.c_uint32), + ('reserved_291', ctypes.c_uint32), + ('reserved_292', ctypes.c_uint32), + ('reserved_293', ctypes.c_uint32), + ('reserved_294', ctypes.c_uint32), + ('reserved_295', ctypes.c_uint32), + ('reserved_296', ctypes.c_uint32), + ('reserved_297', ctypes.c_uint32), + ('reserved_298', ctypes.c_uint32), + ('reserved_299', ctypes.c_uint32), + ('reserved_300', ctypes.c_uint32), + ('reserved_301', ctypes.c_uint32), + ('reserved_302', ctypes.c_uint32), + ('reserved_303', ctypes.c_uint32), + ('reserved_304', ctypes.c_uint32), + ('reserved_305', ctypes.c_uint32), + ('reserved_306', ctypes.c_uint32), + ('reserved_307', ctypes.c_uint32), + ('reserved_308', ctypes.c_uint32), + ('reserved_309', ctypes.c_uint32), + ('reserved_310', ctypes.c_uint32), + ('reserved_311', ctypes.c_uint32), + ('reserved_312', ctypes.c_uint32), + ('reserved_313', ctypes.c_uint32), + ('reserved_314', ctypes.c_uint32), + ('reserved_315', ctypes.c_uint32), + ('reserved_316', ctypes.c_uint32), + ('reserved_317', ctypes.c_uint32), + ('reserved_318', ctypes.c_uint32), + ('reserved_319', ctypes.c_uint32), + ('reserved_320', ctypes.c_uint32), + ('reserved_321', ctypes.c_uint32), + ('reserved_322', ctypes.c_uint32), + ('reserved_323', ctypes.c_uint32), + ('reserved_324', ctypes.c_uint32), + ('reserved_325', ctypes.c_uint32), + ('reserved_326', ctypes.c_uint32), + ('reserved_327', ctypes.c_uint32), + ('reserved_328', ctypes.c_uint32), + ('reserved_329', ctypes.c_uint32), + ('reserved_330', ctypes.c_uint32), + ('reserved_331', ctypes.c_uint32), + ('reserved_332', ctypes.c_uint32), + ('reserved_333', ctypes.c_uint32), + ('reserved_334', ctypes.c_uint32), + ('reserved_335', ctypes.c_uint32), + ('reserved_336', ctypes.c_uint32), + ('reserved_337', ctypes.c_uint32), + ('reserved_338', ctypes.c_uint32), + ('reserved_339', ctypes.c_uint32), + ('reserved_340', ctypes.c_uint32), + ('reserved_341', ctypes.c_uint32), + ('reserved_342', ctypes.c_uint32), + ('reserved_343', ctypes.c_uint32), + ('reserved_344', ctypes.c_uint32), + ('reserved_345', ctypes.c_uint32), + ('reserved_346', ctypes.c_uint32), + ('reserved_347', ctypes.c_uint32), + ('reserved_348', ctypes.c_uint32), + ('reserved_349', ctypes.c_uint32), + ('reserved_350', ctypes.c_uint32), + ('reserved_351', ctypes.c_uint32), + ('reserved_352', ctypes.c_uint32), + ('reserved_353', ctypes.c_uint32), + ('reserved_354', ctypes.c_uint32), + ('reserved_355', ctypes.c_uint32), + ('reserved_356', ctypes.c_uint32), + ('reserved_357', ctypes.c_uint32), + ('reserved_358', ctypes.c_uint32), + ('reserved_359', ctypes.c_uint32), + ('reserved_360', ctypes.c_uint32), + ('reserved_361', ctypes.c_uint32), + ('reserved_362', ctypes.c_uint32), + ('reserved_363', ctypes.c_uint32), + ('reserved_364', ctypes.c_uint32), + ('reserved_365', ctypes.c_uint32), + ('reserved_366', ctypes.c_uint32), + ('reserved_367', ctypes.c_uint32), + ('reserved_368', ctypes.c_uint32), + ('reserved_369', ctypes.c_uint32), + ('reserved_370', ctypes.c_uint32), + ('reserved_371', ctypes.c_uint32), + ('reserved_372', ctypes.c_uint32), + ('reserved_373', ctypes.c_uint32), + ('reserved_374', ctypes.c_uint32), + ('reserved_375', ctypes.c_uint32), + ('reserved_376', ctypes.c_uint32), + ('reserved_377', ctypes.c_uint32), + ('reserved_378', ctypes.c_uint32), + ('reserved_379', ctypes.c_uint32), + ('reserved_380', ctypes.c_uint32), + ('reserved_381', ctypes.c_uint32), + ('reserved_382', ctypes.c_uint32), + ('reserved_383', ctypes.c_uint32), + ('reserved_384', ctypes.c_uint32), + ('reserved_385', ctypes.c_uint32), + ('reserved_386', ctypes.c_uint32), + ('reserved_387', ctypes.c_uint32), + ('reserved_388', ctypes.c_uint32), + ('reserved_389', ctypes.c_uint32), + ('reserved_390', ctypes.c_uint32), + ('reserved_391', ctypes.c_uint32), + ('reserved_392', ctypes.c_uint32), + ('reserved_393', ctypes.c_uint32), + ('reserved_394', ctypes.c_uint32), + ('reserved_395', ctypes.c_uint32), + ('reserved_396', ctypes.c_uint32), + ('reserved_397', ctypes.c_uint32), + ('reserved_398', ctypes.c_uint32), + ('reserved_399', ctypes.c_uint32), + ('reserved_400', ctypes.c_uint32), + ('reserved_401', ctypes.c_uint32), + ('reserved_402', ctypes.c_uint32), + ('reserved_403', ctypes.c_uint32), + ('reserved_404', ctypes.c_uint32), + ('reserved_405', ctypes.c_uint32), + ('reserved_406', ctypes.c_uint32), + ('reserved_407', ctypes.c_uint32), + ('reserved_408', ctypes.c_uint32), + ('reserved_409', ctypes.c_uint32), + ('reserved_410', ctypes.c_uint32), + ('reserved_411', ctypes.c_uint32), + ('reserved_412', ctypes.c_uint32), + ('reserved_413', ctypes.c_uint32), + ('reserved_414', ctypes.c_uint32), + ('reserved_415', ctypes.c_uint32), + ('reserved_416', ctypes.c_uint32), + ('reserved_417', ctypes.c_uint32), + ('reserved_418', ctypes.c_uint32), + ('reserved_419', ctypes.c_uint32), + ('reserved_420', ctypes.c_uint32), + ('reserved_421', ctypes.c_uint32), + ('reserved_422', ctypes.c_uint32), + ('reserved_423', ctypes.c_uint32), + ('reserved_424', ctypes.c_uint32), + ('reserved_425', ctypes.c_uint32), + ('reserved_426', ctypes.c_uint32), + ('reserved_427', ctypes.c_uint32), + ('reserved_428', ctypes.c_uint32), + ('reserved_429', ctypes.c_uint32), + ('reserved_430', ctypes.c_uint32), + ('reserved_431', ctypes.c_uint32), + ('reserved_432', ctypes.c_uint32), + ('reserved_433', ctypes.c_uint32), + ('reserved_434', ctypes.c_uint32), + ('reserved_435', ctypes.c_uint32), + ('reserved_436', ctypes.c_uint32), + ('reserved_437', ctypes.c_uint32), + ('reserved_438', ctypes.c_uint32), + ('reserved_439', ctypes.c_uint32), + ('reserved_440', ctypes.c_uint32), + ('reserved_441', ctypes.c_uint32), + ('reserved_442', ctypes.c_uint32), + ('reserved_443', ctypes.c_uint32), + ('reserved_444', ctypes.c_uint32), + ('reserved_445', ctypes.c_uint32), + ('reserved_446', ctypes.c_uint32), + ('reserved_447', ctypes.c_uint32), + ('gws_0_val', ctypes.c_uint32), + ('gws_1_val', ctypes.c_uint32), + ('gws_2_val', ctypes.c_uint32), + ('gws_3_val', ctypes.c_uint32), + ('gws_4_val', ctypes.c_uint32), + ('gws_5_val', ctypes.c_uint32), + ('gws_6_val', ctypes.c_uint32), + ('gws_7_val', ctypes.c_uint32), + ('gws_8_val', ctypes.c_uint32), + ('gws_9_val', ctypes.c_uint32), + ('gws_10_val', ctypes.c_uint32), + ('gws_11_val', ctypes.c_uint32), + ('gws_12_val', ctypes.c_uint32), + ('gws_13_val', ctypes.c_uint32), + ('gws_14_val', ctypes.c_uint32), + ('gws_15_val', ctypes.c_uint32), + ('gws_16_val', ctypes.c_uint32), + ('gws_17_val', ctypes.c_uint32), + ('gws_18_val', ctypes.c_uint32), + ('gws_19_val', ctypes.c_uint32), + ('gws_20_val', ctypes.c_uint32), + ('gws_21_val', ctypes.c_uint32), + ('gws_22_val', ctypes.c_uint32), + ('gws_23_val', ctypes.c_uint32), + ('gws_24_val', ctypes.c_uint32), + ('gws_25_val', ctypes.c_uint32), + ('gws_26_val', ctypes.c_uint32), + ('gws_27_val', ctypes.c_uint32), + ('gws_28_val', ctypes.c_uint32), + ('gws_29_val', ctypes.c_uint32), + ('gws_30_val', ctypes.c_uint32), + ('gws_31_val', ctypes.c_uint32), + ('gws_32_val', ctypes.c_uint32), + ('gws_33_val', ctypes.c_uint32), + ('gws_34_val', ctypes.c_uint32), + ('gws_35_val', ctypes.c_uint32), + ('gws_36_val', ctypes.c_uint32), + ('gws_37_val', ctypes.c_uint32), + ('gws_38_val', ctypes.c_uint32), + ('gws_39_val', ctypes.c_uint32), + ('gws_40_val', ctypes.c_uint32), + ('gws_41_val', ctypes.c_uint32), + ('gws_42_val', ctypes.c_uint32), + ('gws_43_val', ctypes.c_uint32), + ('gws_44_val', ctypes.c_uint32), + ('gws_45_val', ctypes.c_uint32), + ('gws_46_val', ctypes.c_uint32), + ('gws_47_val', ctypes.c_uint32), + ('gws_48_val', ctypes.c_uint32), + ('gws_49_val', ctypes.c_uint32), + ('gws_50_val', ctypes.c_uint32), + ('gws_51_val', ctypes.c_uint32), + ('gws_52_val', ctypes.c_uint32), + ('gws_53_val', ctypes.c_uint32), + ('gws_54_val', ctypes.c_uint32), + ('gws_55_val', ctypes.c_uint32), + ('gws_56_val', ctypes.c_uint32), + ('gws_57_val', ctypes.c_uint32), + ('gws_58_val', ctypes.c_uint32), + ('gws_59_val', ctypes.c_uint32), + ('gws_60_val', ctypes.c_uint32), + ('gws_61_val', ctypes.c_uint32), + ('gws_62_val', ctypes.c_uint32), + ('gws_63_val', ctypes.c_uint32), +] + +__AMDGPU_VM_H__ = True # macro +AMDGPU_VM_MAX_UPDATE_SIZE = 0x3FFFF # macro +# def AMDGPU_VM_PTE_COUNT(adev): # macro +# return (1<<(adev)->vm_manager.block_size) +AMDGPU_PTE_VALID = (1<<0) # macro +AMDGPU_PTE_SYSTEM = (1<<1) # macro +AMDGPU_PTE_SNOOPED = (1<<2) # macro +AMDGPU_PTE_TMZ = (1<<3) # macro +AMDGPU_PTE_EXECUTABLE = (1<<4) # macro +AMDGPU_PTE_READABLE = (1<<5) # macro +AMDGPU_PTE_WRITEABLE = (1<<6) # macro +def AMDGPU_PTE_FRAG(x): # macro + return ((x&0x1f)<<7) +AMDGPU_PTE_PRT = (1<<51) # macro +AMDGPU_PDE_PTE = (1<<54) # macro +AMDGPU_PTE_LOG = (1<<55) # macro +AMDGPU_PTE_TF = (1<<56) # macro +AMDGPU_PTE_NOALLOC = (1<<58) # macro +def AMDGPU_PDE_BFS(a): # macro + return (a<<59) +AMDGPU_VM_NORETRY_FLAGS = ((1<<4)|(1<<54)|(1<<56)) # macro +AMDGPU_VM_NORETRY_FLAGS_TF = ((1<<0)|(1<<1)|(1<<51)) # macro +def AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype): # macro + return ((mtype)<<57) +AMDGPU_PTE_MTYPE_VG10_MASK = AMDGPU_PTE_MTYPE_VG10_SHIFT ( 3 ) # macro +def AMDGPU_PTE_MTYPE_VG10(flags, mtype): # macro + return (((flags)&(~AMDGPU_PTE_MTYPE_VG10_SHIFT(3)))|AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) +AMDGPU_MTYPE_NC = 0 # macro +AMDGPU_MTYPE_CC = 2 # macro +AMDGPU_PTE_DEFAULT_ATC = ((1<<1)|(1<<2)|(1<<4)|(1<<5)|(1<<6)|AMDGPU_PTE_MTYPE_VG10(0, 2)) # macro +def AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype): # macro + return ((mtype)<<48) +AMDGPU_PTE_MTYPE_NV10_MASK = AMDGPU_PTE_MTYPE_NV10_SHIFT ( 7 ) # macro +def AMDGPU_PTE_MTYPE_NV10(flags, mtype): # macro + return (((flags)&(~AMDGPU_PTE_MTYPE_NV10_SHIFT(7)))|AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) +AMDGPU_PTE_PRT_GFX12 = (1<<56) # macro +def AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype): # macro + return ((mtype)<<54) +AMDGPU_PTE_MTYPE_GFX12_MASK = AMDGPU_PTE_MTYPE_GFX12_SHIFT ( 3 ) # macro +def AMDGPU_PTE_MTYPE_GFX12(flags, mtype): # macro + return (((flags)&(~AMDGPU_PTE_MTYPE_GFX12_SHIFT(3)))|AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) +AMDGPU_PTE_IS_PTE = (1<<63) # macro +def AMDGPU_PDE_BFS_GFX12(a): # macro + return (((a)&0x1f)<<58) +AMDGPU_PDE_PTE_GFX12 = (1<<63) # macro +AMDGPU_VM_FAULT_STOP_NEVER = 0 # macro +AMDGPU_VM_FAULT_STOP_FIRST = 1 # macro +AMDGPU_VM_FAULT_STOP_ALWAYS = 2 # macro +AMDGPU_VM_RESERVED_VRAM = (8<<20) # macro +AMDGPU_MAX_VMHUBS = 13 # macro +AMDGPU_GFXHUB_START = 0 # macro +AMDGPU_MMHUB0_START = 8 # macro +AMDGPU_MMHUB1_START = 12 # macro +def AMDGPU_GFXHUB(x): # macro + return (0+(x)) +def AMDGPU_MMHUB0(x): # macro + return (8+(x)) +def AMDGPU_MMHUB1(x): # macro + return (12+(x)) +def AMDGPU_IS_GFXHUB(x): # macro + return ((x)>=0 and (x)<8) +def AMDGPU_IS_MMHUB0(x): # macro + return ((x)>=8 and (x)<12) +def AMDGPU_IS_MMHUB1(x): # macro + return ((x)>=12 and (x)<13) +AMDGPU_VA_RESERVED_CSA_SIZE = (2<<20) # macro +# def AMDGPU_VA_RESERVED_CSA_START(adev): # macro +# return (((adev)->vm_manager.max_pfn<=IP_VERSION(12,0,0))?(1<<56):(1<<51)) +# def AMDGPU_PDE_BFS_FLAG(adev, a): # macro +# return ((amdgpu_ip_version((adev),GC_HWIP,0)>=IP_VERSION(12,0,0))?AMDGPU_PDE_BFS_GFX12(a):AMDGPU_PDE_BFS(a)) +# def AMDGPU_PDE_PTE_FLAG(adev): # macro +# return ((amdgpu_ip_version((adev),GC_HWIP,0)>=IP_VERSION(12,0,0))?(1<<63):(1<<54)) +hw_id_map = [['GC_HWIP', '11'],['HDP_HWIP', '41'],['SDMA0_HWIP', '42'],['SDMA1_HWIP', '43'],['SDMA2_HWIP', '68'],['SDMA3_HWIP', '69'],['LSDMA_HWIP', '91'],['MMHUB_HWIP', '34'],['ATHUB_HWIP', '35'],['NBIO_HWIP', '108'],['MP0_HWIP', '255'],['MP1_HWIP', '1'],['UVD_HWIP', '12'],['VCE_HWIP', '32'],['DF_HWIP', '46'],['DCE_HWIP', '271'],['OSSSYS_HWIP', '40'],['SMUIO_HWIP', '4'],['PWR_HWIP', '10'],['NBIF_HWIP', '108'],['THM_HWIP', '3'],['CLK_HWIP', '6'],['UMC_HWIP', '150'],['XGMI_HWIP', '200'],['DCI_HWIP', '15'],['PCIE_HWIP', '70'],['VPE_HWIP', '21'],['ISP_HWIP', '44']] # Variable ctypes.c_int32 * 35 +__AMDGPU_UCODE_H__ = True # macro +int32_t = True # macro +int8_t = True # macro +int16_t = True # macro +AMDGPU_SDMA0_UCODE_LOADED = 0x00000001 # macro +AMDGPU_SDMA1_UCODE_LOADED = 0x00000002 # macro +AMDGPU_CPCE_UCODE_LOADED = 0x00000004 # macro +AMDGPU_CPPFP_UCODE_LOADED = 0x00000008 # macro +AMDGPU_CPME_UCODE_LOADED = 0x00000010 # macro +AMDGPU_CPMEC1_UCODE_LOADED = 0x00000020 # macro +AMDGPU_CPMEC2_UCODE_LOADED = 0x00000040 # macro +AMDGPU_CPRLC_UCODE_LOADED = 0x00000100 # macro +class struct_common_firmware_header(Structure): + pass + +struct_common_firmware_header._pack_ = 1 # source:False +struct_common_firmware_header._fields_ = [ + ('size_bytes', ctypes.c_uint32), + ('header_size_bytes', ctypes.c_uint32), + ('header_version_major', ctypes.c_uint16), + ('header_version_minor', ctypes.c_uint16), + ('ip_version_major', ctypes.c_uint16), + ('ip_version_minor', ctypes.c_uint16), + ('ucode_version', ctypes.c_uint32), + ('ucode_size_bytes', ctypes.c_uint32), + ('ucode_array_offset_bytes', ctypes.c_uint32), + ('crc32', ctypes.c_uint32), +] + +class struct_mc_firmware_header_v1_0(Structure): + pass + +struct_mc_firmware_header_v1_0._pack_ = 1 # source:False +struct_mc_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('io_debug_size_bytes', ctypes.c_uint32), + ('io_debug_array_offset_bytes', ctypes.c_uint32), +] + +class struct_smc_firmware_header_v1_0(Structure): + pass + +struct_smc_firmware_header_v1_0._pack_ = 1 # source:False +struct_smc_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_start_addr', ctypes.c_uint32), +] + +class struct_smc_firmware_header_v2_0(Structure): + pass + +struct_smc_firmware_header_v2_0._pack_ = 1 # source:False +struct_smc_firmware_header_v2_0._fields_ = [ + ('v1_0', struct_smc_firmware_header_v1_0), + ('ppt_offset_bytes', ctypes.c_uint32), + ('ppt_size_bytes', ctypes.c_uint32), +] + +class struct_smc_soft_pptable_entry(Structure): + pass + +struct_smc_soft_pptable_entry._pack_ = 1 # source:False +struct_smc_soft_pptable_entry._fields_ = [ + ('id', ctypes.c_uint32), + ('ppt_offset_bytes', ctypes.c_uint32), + ('ppt_size_bytes', ctypes.c_uint32), +] + +class struct_smc_firmware_header_v2_1(Structure): + pass + +struct_smc_firmware_header_v2_1._pack_ = 1 # source:False +struct_smc_firmware_header_v2_1._fields_ = [ + ('v1_0', struct_smc_firmware_header_v1_0), + ('pptable_count', ctypes.c_uint32), + ('pptable_entry_offset', ctypes.c_uint32), +] + +class struct_psp_fw_legacy_bin_desc(Structure): + pass + +struct_psp_fw_legacy_bin_desc._pack_ = 1 # source:False +struct_psp_fw_legacy_bin_desc._fields_ = [ + ('fw_version', ctypes.c_uint32), + ('offset_bytes', ctypes.c_uint32), + ('size_bytes', ctypes.c_uint32), +] + +class struct_psp_firmware_header_v1_0(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('header', struct_common_firmware_header), + ('sos', struct_psp_fw_legacy_bin_desc), + ] + +class struct_psp_firmware_header_v1_1(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('v1_0', struct_psp_firmware_header_v1_0), + ('toc', struct_psp_fw_legacy_bin_desc), + ('kdb', struct_psp_fw_legacy_bin_desc), + ] + +class struct_psp_firmware_header_v1_2(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('v1_0', struct_psp_firmware_header_v1_0), + ('res', struct_psp_fw_legacy_bin_desc), + ('kdb', struct_psp_fw_legacy_bin_desc), + ] + +class struct_psp_firmware_header_v1_3(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('v1_1', struct_psp_firmware_header_v1_1), + ('spl', struct_psp_fw_legacy_bin_desc), + ('rl', struct_psp_fw_legacy_bin_desc), + ('sys_drv_aux', struct_psp_fw_legacy_bin_desc), + ('sos_aux', struct_psp_fw_legacy_bin_desc), + ] + +class struct_psp_fw_bin_desc(Structure): + pass + +struct_psp_fw_bin_desc._pack_ = 1 # source:False +struct_psp_fw_bin_desc._fields_ = [ + ('fw_type', ctypes.c_uint32), + ('fw_version', ctypes.c_uint32), + ('offset_bytes', ctypes.c_uint32), + ('size_bytes', ctypes.c_uint32), +] + +# UCODE_MAX_PSP_PACKAGING = (((ctypes.sizeof(amdgpu_firmware_header)-ctypes.sizeof(struct_common_firmware_header)-4)/ctypes.sizeof(struct_psp_fw_bin_desc))*2) # macro + +# values for enumeration 'psp_fw_type' +psp_fw_type__enumvalues = { + 0: 'PSP_FW_TYPE_UNKOWN', + 1: 'PSP_FW_TYPE_PSP_SOS', + 2: 'PSP_FW_TYPE_PSP_SYS_DRV', + 3: 'PSP_FW_TYPE_PSP_KDB', + 4: 'PSP_FW_TYPE_PSP_TOC', + 5: 'PSP_FW_TYPE_PSP_SPL', + 6: 'PSP_FW_TYPE_PSP_RL', + 7: 'PSP_FW_TYPE_PSP_SOC_DRV', + 8: 'PSP_FW_TYPE_PSP_INTF_DRV', + 9: 'PSP_FW_TYPE_PSP_DBG_DRV', + 10: 'PSP_FW_TYPE_PSP_RAS_DRV', + 11: 'PSP_FW_TYPE_PSP_IPKEYMGR_DRV', + 12: 'PSP_FW_TYPE_MAX_INDEX', +} +PSP_FW_TYPE_UNKOWN = 0 +PSP_FW_TYPE_PSP_SOS = 1 +PSP_FW_TYPE_PSP_SYS_DRV = 2 +PSP_FW_TYPE_PSP_KDB = 3 +PSP_FW_TYPE_PSP_TOC = 4 +PSP_FW_TYPE_PSP_SPL = 5 +PSP_FW_TYPE_PSP_RL = 6 +PSP_FW_TYPE_PSP_SOC_DRV = 7 +PSP_FW_TYPE_PSP_INTF_DRV = 8 +PSP_FW_TYPE_PSP_DBG_DRV = 9 +PSP_FW_TYPE_PSP_RAS_DRV = 10 +PSP_FW_TYPE_PSP_IPKEYMGR_DRV = 11 +PSP_FW_TYPE_MAX_INDEX = 12 +psp_fw_type = ctypes.c_uint32 # enum +class struct_psp_firmware_header_v2_0(Structure): + pass + +struct_psp_firmware_header_v2_0._pack_ = 1 # source:False +struct_psp_firmware_header_v2_0._fields_ = [ + ('header', struct_common_firmware_header), + ('psp_fw_bin_count', ctypes.c_uint32), + ('psp_fw_bin', struct_psp_fw_bin_desc * 1), +] + +class struct_psp_firmware_header_v2_1(Structure): + pass + +struct_psp_firmware_header_v2_1._pack_ = 1 # source:False +struct_psp_firmware_header_v2_1._fields_ = [ + ('header', struct_common_firmware_header), + ('psp_fw_bin_count', ctypes.c_uint32), + ('psp_aux_fw_bin_index', ctypes.c_uint32), + ('psp_fw_bin', struct_psp_fw_bin_desc * 1), +] + +class struct_ta_firmware_header_v1_0(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('header', struct_common_firmware_header), + ('xgmi', struct_psp_fw_legacy_bin_desc), + ('ras', struct_psp_fw_legacy_bin_desc), + ('hdcp', struct_psp_fw_legacy_bin_desc), + ('dtm', struct_psp_fw_legacy_bin_desc), + ('securedisplay', struct_psp_fw_legacy_bin_desc), + ] + + +# values for enumeration 'ta_fw_type' +ta_fw_type__enumvalues = { + 0: 'TA_FW_TYPE_UNKOWN', + 1: 'TA_FW_TYPE_PSP_ASD', + 2: 'TA_FW_TYPE_PSP_XGMI', + 3: 'TA_FW_TYPE_PSP_RAS', + 4: 'TA_FW_TYPE_PSP_HDCP', + 5: 'TA_FW_TYPE_PSP_DTM', + 6: 'TA_FW_TYPE_PSP_RAP', + 7: 'TA_FW_TYPE_PSP_SECUREDISPLAY', + 8: 'TA_FW_TYPE_MAX_INDEX', +} +TA_FW_TYPE_UNKOWN = 0 +TA_FW_TYPE_PSP_ASD = 1 +TA_FW_TYPE_PSP_XGMI = 2 +TA_FW_TYPE_PSP_RAS = 3 +TA_FW_TYPE_PSP_HDCP = 4 +TA_FW_TYPE_PSP_DTM = 5 +TA_FW_TYPE_PSP_RAP = 6 +TA_FW_TYPE_PSP_SECUREDISPLAY = 7 +TA_FW_TYPE_MAX_INDEX = 8 +ta_fw_type = ctypes.c_uint32 # enum +class struct_ta_firmware_header_v2_0(Structure): + pass + +struct_ta_firmware_header_v2_0._pack_ = 1 # source:False +struct_ta_firmware_header_v2_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ta_fw_bin_count', ctypes.c_uint32), + ('ta_fw_bin', struct_psp_fw_bin_desc * 1), +] + +class struct_gfx_firmware_header_v1_0(Structure): + pass + +struct_gfx_firmware_header_v1_0._pack_ = 1 # source:False +struct_gfx_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('jt_offset', ctypes.c_uint32), + ('jt_size', ctypes.c_uint32), +] + +class struct_gfx_firmware_header_v2_0(Structure): + pass + +struct_gfx_firmware_header_v2_0._pack_ = 1 # source:False +struct_gfx_firmware_header_v2_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ucode_size_bytes', ctypes.c_uint32), + ('ucode_offset_bytes', ctypes.c_uint32), + ('data_size_bytes', ctypes.c_uint32), + ('data_offset_bytes', ctypes.c_uint32), + ('ucode_start_addr_lo', ctypes.c_uint32), + ('ucode_start_addr_hi', ctypes.c_uint32), +] + +class struct_mes_firmware_header_v1_0(Structure): + pass + +struct_mes_firmware_header_v1_0._pack_ = 1 # source:False +struct_mes_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('mes_ucode_version', ctypes.c_uint32), + ('mes_ucode_size_bytes', ctypes.c_uint32), + ('mes_ucode_offset_bytes', ctypes.c_uint32), + ('mes_ucode_data_version', ctypes.c_uint32), + ('mes_ucode_data_size_bytes', ctypes.c_uint32), + ('mes_ucode_data_offset_bytes', ctypes.c_uint32), + ('mes_uc_start_addr_lo', ctypes.c_uint32), + ('mes_uc_start_addr_hi', ctypes.c_uint32), + ('mes_data_start_addr_lo', ctypes.c_uint32), + ('mes_data_start_addr_hi', ctypes.c_uint32), +] + +class struct_rlc_firmware_header_v1_0(Structure): + pass + +struct_rlc_firmware_header_v1_0._pack_ = 1 # source:False +struct_rlc_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('save_and_restore_offset', ctypes.c_uint32), + ('clear_state_descriptor_offset', ctypes.c_uint32), + ('avail_scratch_ram_locations', ctypes.c_uint32), + ('master_pkt_description_offset', ctypes.c_uint32), +] + +class struct_rlc_firmware_header_v2_0(Structure): + pass + +struct_rlc_firmware_header_v2_0._pack_ = 1 # source:False +struct_rlc_firmware_header_v2_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('jt_offset', ctypes.c_uint32), + ('jt_size', ctypes.c_uint32), + ('save_and_restore_offset', ctypes.c_uint32), + ('clear_state_descriptor_offset', ctypes.c_uint32), + ('avail_scratch_ram_locations', ctypes.c_uint32), + ('reg_restore_list_size', ctypes.c_uint32), + ('reg_list_format_start', ctypes.c_uint32), + ('reg_list_format_separate_start', ctypes.c_uint32), + ('starting_offsets_start', ctypes.c_uint32), + ('reg_list_format_size_bytes', ctypes.c_uint32), + ('reg_list_format_array_offset_bytes', ctypes.c_uint32), + ('reg_list_size_bytes', ctypes.c_uint32), + ('reg_list_array_offset_bytes', ctypes.c_uint32), + ('reg_list_format_separate_size_bytes', ctypes.c_uint32), + ('reg_list_format_separate_array_offset_bytes', ctypes.c_uint32), + ('reg_list_separate_size_bytes', ctypes.c_uint32), + ('reg_list_separate_array_offset_bytes', ctypes.c_uint32), +] + +class struct_rlc_firmware_header_v2_1(Structure): + pass + +struct_rlc_firmware_header_v2_1._pack_ = 1 # source:False +struct_rlc_firmware_header_v2_1._fields_ = [ + ('v2_0', struct_rlc_firmware_header_v2_0), + ('reg_list_format_direct_reg_list_length', ctypes.c_uint32), + ('save_restore_list_cntl_ucode_ver', ctypes.c_uint32), + ('save_restore_list_cntl_feature_ver', ctypes.c_uint32), + ('save_restore_list_cntl_size_bytes', ctypes.c_uint32), + ('save_restore_list_cntl_offset_bytes', ctypes.c_uint32), + ('save_restore_list_gpm_ucode_ver', ctypes.c_uint32), + ('save_restore_list_gpm_feature_ver', ctypes.c_uint32), + ('save_restore_list_gpm_size_bytes', ctypes.c_uint32), + ('save_restore_list_gpm_offset_bytes', ctypes.c_uint32), + ('save_restore_list_srm_ucode_ver', ctypes.c_uint32), + ('save_restore_list_srm_feature_ver', ctypes.c_uint32), + ('save_restore_list_srm_size_bytes', ctypes.c_uint32), + ('save_restore_list_srm_offset_bytes', ctypes.c_uint32), +] + +class struct_rlc_firmware_header_v2_2(Structure): + pass + +struct_rlc_firmware_header_v2_2._pack_ = 1 # source:False +struct_rlc_firmware_header_v2_2._fields_ = [ + ('v2_1', struct_rlc_firmware_header_v2_1), + ('rlc_iram_ucode_size_bytes', ctypes.c_uint32), + ('rlc_iram_ucode_offset_bytes', ctypes.c_uint32), + ('rlc_dram_ucode_size_bytes', ctypes.c_uint32), + ('rlc_dram_ucode_offset_bytes', ctypes.c_uint32), +] + +class struct_rlc_firmware_header_v2_3(Structure): + pass + +struct_rlc_firmware_header_v2_3._pack_ = 1 # source:False +struct_rlc_firmware_header_v2_3._fields_ = [ + ('v2_2', struct_rlc_firmware_header_v2_2), + ('rlcp_ucode_version', ctypes.c_uint32), + ('rlcp_ucode_feature_version', ctypes.c_uint32), + ('rlcp_ucode_size_bytes', ctypes.c_uint32), + ('rlcp_ucode_offset_bytes', ctypes.c_uint32), + ('rlcv_ucode_version', ctypes.c_uint32), + ('rlcv_ucode_feature_version', ctypes.c_uint32), + ('rlcv_ucode_size_bytes', ctypes.c_uint32), + ('rlcv_ucode_offset_bytes', ctypes.c_uint32), +] + +class struct_rlc_firmware_header_v2_4(Structure): + pass + +struct_rlc_firmware_header_v2_4._pack_ = 1 # source:False +struct_rlc_firmware_header_v2_4._fields_ = [ + ('v2_3', struct_rlc_firmware_header_v2_3), + ('global_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('global_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se0_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se0_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se1_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se1_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se2_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se2_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se3_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se3_tap_delays_ucode_offset_bytes', ctypes.c_uint32), +] + +class struct_sdma_firmware_header_v1_0(Structure): + pass + +struct_sdma_firmware_header_v1_0._pack_ = 1 # source:False +struct_sdma_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ucode_change_version', ctypes.c_uint32), + ('jt_offset', ctypes.c_uint32), + ('jt_size', ctypes.c_uint32), +] + +class struct_sdma_firmware_header_v1_1(Structure): + pass + +struct_sdma_firmware_header_v1_1._pack_ = 1 # source:False +struct_sdma_firmware_header_v1_1._fields_ = [ + ('v1_0', struct_sdma_firmware_header_v1_0), + ('digest_size', ctypes.c_uint32), +] + +class struct_sdma_firmware_header_v2_0(Structure): + pass + +struct_sdma_firmware_header_v2_0._pack_ = 1 # source:False +struct_sdma_firmware_header_v2_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ctx_ucode_size_bytes', ctypes.c_uint32), + ('ctx_jt_offset', ctypes.c_uint32), + ('ctx_jt_size', ctypes.c_uint32), + ('ctl_ucode_offset', ctypes.c_uint32), + ('ctl_ucode_size_bytes', ctypes.c_uint32), + ('ctl_jt_offset', ctypes.c_uint32), + ('ctl_jt_size', ctypes.c_uint32), +] + +class struct_vpe_firmware_header_v1_0(Structure): + pass + +struct_vpe_firmware_header_v1_0._pack_ = 1 # source:False +struct_vpe_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ctx_ucode_size_bytes', ctypes.c_uint32), + ('ctx_jt_offset', ctypes.c_uint32), + ('ctx_jt_size', ctypes.c_uint32), + ('ctl_ucode_offset', ctypes.c_uint32), + ('ctl_ucode_size_bytes', ctypes.c_uint32), + ('ctl_jt_offset', ctypes.c_uint32), + ('ctl_jt_size', ctypes.c_uint32), +] + +class struct_umsch_mm_firmware_header_v1_0(Structure): + pass + +struct_umsch_mm_firmware_header_v1_0._pack_ = 1 # source:False +struct_umsch_mm_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('umsch_mm_ucode_version', ctypes.c_uint32), + ('umsch_mm_ucode_size_bytes', ctypes.c_uint32), + ('umsch_mm_ucode_offset_bytes', ctypes.c_uint32), + ('umsch_mm_ucode_data_version', ctypes.c_uint32), + ('umsch_mm_ucode_data_size_bytes', ctypes.c_uint32), + ('umsch_mm_ucode_data_offset_bytes', ctypes.c_uint32), + ('umsch_mm_irq_start_addr_lo', ctypes.c_uint32), + ('umsch_mm_irq_start_addr_hi', ctypes.c_uint32), + ('umsch_mm_uc_start_addr_lo', ctypes.c_uint32), + ('umsch_mm_uc_start_addr_hi', ctypes.c_uint32), + ('umsch_mm_data_start_addr_lo', ctypes.c_uint32), + ('umsch_mm_data_start_addr_hi', ctypes.c_uint32), +] + +class struct_sdma_firmware_header_v3_0(Structure): + pass + +struct_sdma_firmware_header_v3_0._pack_ = 1 # source:False +struct_sdma_firmware_header_v3_0._fields_ = [ + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ucode_offset_bytes', ctypes.c_uint32), + ('ucode_size_bytes', ctypes.c_uint32), +] + +class struct_gpu_info_firmware_v1_0(Structure): + pass + +struct_gpu_info_firmware_v1_0._pack_ = 1 # source:False +struct_gpu_info_firmware_v1_0._fields_ = [ + ('gc_num_se', ctypes.c_uint32), + ('gc_num_cu_per_sh', ctypes.c_uint32), + ('gc_num_sh_per_se', ctypes.c_uint32), + ('gc_num_rb_per_se', ctypes.c_uint32), + ('gc_num_tccs', ctypes.c_uint32), + ('gc_num_gprs', ctypes.c_uint32), + ('gc_num_max_gs_thds', ctypes.c_uint32), + ('gc_gs_table_depth', ctypes.c_uint32), + ('gc_gsprim_buff_depth', ctypes.c_uint32), + ('gc_parameter_cache_depth', ctypes.c_uint32), + ('gc_double_offchip_lds_buffer', ctypes.c_uint32), + ('gc_wave_size', ctypes.c_uint32), + ('gc_max_waves_per_simd', ctypes.c_uint32), + ('gc_max_scratch_slots_per_cu', ctypes.c_uint32), + ('gc_lds_size', ctypes.c_uint32), +] + +class struct_gpu_info_firmware_v1_1(Structure): + pass + +struct_gpu_info_firmware_v1_1._pack_ = 1 # source:False +struct_gpu_info_firmware_v1_1._fields_ = [ + ('v1_0', struct_gpu_info_firmware_v1_0), + ('num_sc_per_sh', ctypes.c_uint32), + ('num_packer_per_sc', ctypes.c_uint32), +] + +class struct_gpu_info_firmware_header_v1_0(Structure): + pass + +struct_gpu_info_firmware_header_v1_0._pack_ = 1 # source:False +struct_gpu_info_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('version_major', ctypes.c_uint16), + ('version_minor', ctypes.c_uint16), +] + +class struct_dmcu_firmware_header_v1_0(Structure): + pass + +struct_dmcu_firmware_header_v1_0._pack_ = 1 # source:False +struct_dmcu_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('intv_offset_bytes', ctypes.c_uint32), + ('intv_size_bytes', ctypes.c_uint32), +] + +class struct_dmcub_firmware_header_v1_0(Structure): + pass + +struct_dmcub_firmware_header_v1_0._pack_ = 1 # source:False +struct_dmcub_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('inst_const_bytes', ctypes.c_uint32), + ('bss_data_bytes', ctypes.c_uint32), +] + +class struct_imu_firmware_header_v1_0(Structure): + pass + +struct_imu_firmware_header_v1_0._pack_ = 1 # source:False +struct_imu_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('imu_iram_ucode_size_bytes', ctypes.c_uint32), + ('imu_iram_ucode_offset_bytes', ctypes.c_uint32), + ('imu_dram_ucode_size_bytes', ctypes.c_uint32), + ('imu_dram_ucode_offset_bytes', ctypes.c_uint32), +] + +class union_amdgpu_firmware_header(Union): + pass + +union_amdgpu_firmware_header._pack_ = 1 # source:False +union_amdgpu_firmware_header._fields_ = [ + ('common', struct_common_firmware_header), + ('mc', struct_mc_firmware_header_v1_0), + ('smc', struct_smc_firmware_header_v1_0), + ('smc_v2_0', struct_smc_firmware_header_v2_0), + ('psp', struct_psp_firmware_header_v1_0), + ('psp_v1_1', struct_psp_firmware_header_v1_1), + ('psp_v1_3', struct_psp_firmware_header_v1_3), + ('psp_v2_0', struct_psp_firmware_header_v2_0), + ('psp_v2_1', struct_psp_firmware_header_v2_0), + ('ta', struct_ta_firmware_header_v1_0), + ('ta_v2_0', struct_ta_firmware_header_v2_0), + ('gfx', struct_gfx_firmware_header_v1_0), + ('gfx_v2_0', struct_gfx_firmware_header_v2_0), + ('rlc', struct_rlc_firmware_header_v1_0), + ('rlc_v2_0', struct_rlc_firmware_header_v2_0), + ('rlc_v2_1', struct_rlc_firmware_header_v2_1), + ('rlc_v2_2', struct_rlc_firmware_header_v2_2), + ('rlc_v2_3', struct_rlc_firmware_header_v2_3), + ('rlc_v2_4', struct_rlc_firmware_header_v2_4), + ('sdma', struct_sdma_firmware_header_v1_0), + ('sdma_v1_1', struct_sdma_firmware_header_v1_1), + ('sdma_v2_0', struct_sdma_firmware_header_v2_0), + ('sdma_v3_0', struct_sdma_firmware_header_v3_0), + ('gpu_info', struct_gpu_info_firmware_header_v1_0), + ('dmcu', struct_dmcu_firmware_header_v1_0), + ('dmcub', struct_dmcub_firmware_header_v1_0), + ('imu', struct_imu_firmware_header_v1_0), + ('raw', ctypes.c_ubyte * 256), +] + + +# values for enumeration 'AMDGPU_UCODE_ID' +AMDGPU_UCODE_ID__enumvalues = { + 0: 'AMDGPU_UCODE_ID_CAP', + 1: 'AMDGPU_UCODE_ID_SDMA0', + 2: 'AMDGPU_UCODE_ID_SDMA1', + 3: 'AMDGPU_UCODE_ID_SDMA2', + 4: 'AMDGPU_UCODE_ID_SDMA3', + 5: 'AMDGPU_UCODE_ID_SDMA4', + 6: 'AMDGPU_UCODE_ID_SDMA5', + 7: 'AMDGPU_UCODE_ID_SDMA6', + 8: 'AMDGPU_UCODE_ID_SDMA7', + 9: 'AMDGPU_UCODE_ID_SDMA_UCODE_TH0', + 10: 'AMDGPU_UCODE_ID_SDMA_UCODE_TH1', + 11: 'AMDGPU_UCODE_ID_SDMA_RS64', + 12: 'AMDGPU_UCODE_ID_CP_CE', + 13: 'AMDGPU_UCODE_ID_CP_PFP', + 14: 'AMDGPU_UCODE_ID_CP_ME', + 15: 'AMDGPU_UCODE_ID_CP_RS64_PFP', + 16: 'AMDGPU_UCODE_ID_CP_RS64_ME', + 17: 'AMDGPU_UCODE_ID_CP_RS64_MEC', + 18: 'AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK', + 19: 'AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK', + 20: 'AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK', + 21: 'AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK', + 22: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK', + 23: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK', + 24: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK', + 25: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK', + 26: 'AMDGPU_UCODE_ID_CP_MEC1', + 27: 'AMDGPU_UCODE_ID_CP_MEC1_JT', + 28: 'AMDGPU_UCODE_ID_CP_MEC2', + 29: 'AMDGPU_UCODE_ID_CP_MEC2_JT', + 30: 'AMDGPU_UCODE_ID_CP_MES', + 31: 'AMDGPU_UCODE_ID_CP_MES_DATA', + 32: 'AMDGPU_UCODE_ID_CP_MES1', + 33: 'AMDGPU_UCODE_ID_CP_MES1_DATA', + 34: 'AMDGPU_UCODE_ID_IMU_I', + 35: 'AMDGPU_UCODE_ID_IMU_D', + 36: 'AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS', + 37: 'AMDGPU_UCODE_ID_SE0_TAP_DELAYS', + 38: 'AMDGPU_UCODE_ID_SE1_TAP_DELAYS', + 39: 'AMDGPU_UCODE_ID_SE2_TAP_DELAYS', + 40: 'AMDGPU_UCODE_ID_SE3_TAP_DELAYS', + 41: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL', + 42: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM', + 43: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM', + 44: 'AMDGPU_UCODE_ID_RLC_IRAM', + 45: 'AMDGPU_UCODE_ID_RLC_DRAM', + 46: 'AMDGPU_UCODE_ID_RLC_P', + 47: 'AMDGPU_UCODE_ID_RLC_V', + 48: 'AMDGPU_UCODE_ID_RLC_G', + 49: 'AMDGPU_UCODE_ID_STORAGE', + 50: 'AMDGPU_UCODE_ID_SMC', + 51: 'AMDGPU_UCODE_ID_PPTABLE', + 52: 'AMDGPU_UCODE_ID_UVD', + 53: 'AMDGPU_UCODE_ID_UVD1', + 54: 'AMDGPU_UCODE_ID_VCE', + 55: 'AMDGPU_UCODE_ID_VCN', + 56: 'AMDGPU_UCODE_ID_VCN1', + 57: 'AMDGPU_UCODE_ID_DMCU_ERAM', + 58: 'AMDGPU_UCODE_ID_DMCU_INTV', + 59: 'AMDGPU_UCODE_ID_VCN0_RAM', + 60: 'AMDGPU_UCODE_ID_VCN1_RAM', + 61: 'AMDGPU_UCODE_ID_DMCUB', + 62: 'AMDGPU_UCODE_ID_VPE_CTX', + 63: 'AMDGPU_UCODE_ID_VPE_CTL', + 64: 'AMDGPU_UCODE_ID_VPE', + 65: 'AMDGPU_UCODE_ID_UMSCH_MM_UCODE', + 66: 'AMDGPU_UCODE_ID_UMSCH_MM_DATA', + 67: 'AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER', + 68: 'AMDGPU_UCODE_ID_P2S_TABLE', + 69: 'AMDGPU_UCODE_ID_JPEG_RAM', + 70: 'AMDGPU_UCODE_ID_ISP', + 71: 'AMDGPU_UCODE_ID_MAXIMUM', +} +AMDGPU_UCODE_ID_CAP = 0 +AMDGPU_UCODE_ID_SDMA0 = 1 +AMDGPU_UCODE_ID_SDMA1 = 2 +AMDGPU_UCODE_ID_SDMA2 = 3 +AMDGPU_UCODE_ID_SDMA3 = 4 +AMDGPU_UCODE_ID_SDMA4 = 5 +AMDGPU_UCODE_ID_SDMA5 = 6 +AMDGPU_UCODE_ID_SDMA6 = 7 +AMDGPU_UCODE_ID_SDMA7 = 8 +AMDGPU_UCODE_ID_SDMA_UCODE_TH0 = 9 +AMDGPU_UCODE_ID_SDMA_UCODE_TH1 = 10 +AMDGPU_UCODE_ID_SDMA_RS64 = 11 +AMDGPU_UCODE_ID_CP_CE = 12 +AMDGPU_UCODE_ID_CP_PFP = 13 +AMDGPU_UCODE_ID_CP_ME = 14 +AMDGPU_UCODE_ID_CP_RS64_PFP = 15 +AMDGPU_UCODE_ID_CP_RS64_ME = 16 +AMDGPU_UCODE_ID_CP_RS64_MEC = 17 +AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK = 18 +AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK = 19 +AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK = 20 +AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK = 21 +AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK = 22 +AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK = 23 +AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK = 24 +AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK = 25 +AMDGPU_UCODE_ID_CP_MEC1 = 26 +AMDGPU_UCODE_ID_CP_MEC1_JT = 27 +AMDGPU_UCODE_ID_CP_MEC2 = 28 +AMDGPU_UCODE_ID_CP_MEC2_JT = 29 +AMDGPU_UCODE_ID_CP_MES = 30 +AMDGPU_UCODE_ID_CP_MES_DATA = 31 +AMDGPU_UCODE_ID_CP_MES1 = 32 +AMDGPU_UCODE_ID_CP_MES1_DATA = 33 +AMDGPU_UCODE_ID_IMU_I = 34 +AMDGPU_UCODE_ID_IMU_D = 35 +AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS = 36 +AMDGPU_UCODE_ID_SE0_TAP_DELAYS = 37 +AMDGPU_UCODE_ID_SE1_TAP_DELAYS = 38 +AMDGPU_UCODE_ID_SE2_TAP_DELAYS = 39 +AMDGPU_UCODE_ID_SE3_TAP_DELAYS = 40 +AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL = 41 +AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM = 42 +AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM = 43 +AMDGPU_UCODE_ID_RLC_IRAM = 44 +AMDGPU_UCODE_ID_RLC_DRAM = 45 +AMDGPU_UCODE_ID_RLC_P = 46 +AMDGPU_UCODE_ID_RLC_V = 47 +AMDGPU_UCODE_ID_RLC_G = 48 +AMDGPU_UCODE_ID_STORAGE = 49 +AMDGPU_UCODE_ID_SMC = 50 +AMDGPU_UCODE_ID_PPTABLE = 51 +AMDGPU_UCODE_ID_UVD = 52 +AMDGPU_UCODE_ID_UVD1 = 53 +AMDGPU_UCODE_ID_VCE = 54 +AMDGPU_UCODE_ID_VCN = 55 +AMDGPU_UCODE_ID_VCN1 = 56 +AMDGPU_UCODE_ID_DMCU_ERAM = 57 +AMDGPU_UCODE_ID_DMCU_INTV = 58 +AMDGPU_UCODE_ID_VCN0_RAM = 59 +AMDGPU_UCODE_ID_VCN1_RAM = 60 +AMDGPU_UCODE_ID_DMCUB = 61 +AMDGPU_UCODE_ID_VPE_CTX = 62 +AMDGPU_UCODE_ID_VPE_CTL = 63 +AMDGPU_UCODE_ID_VPE = 64 +AMDGPU_UCODE_ID_UMSCH_MM_UCODE = 65 +AMDGPU_UCODE_ID_UMSCH_MM_DATA = 66 +AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER = 67 +AMDGPU_UCODE_ID_P2S_TABLE = 68 +AMDGPU_UCODE_ID_JPEG_RAM = 69 +AMDGPU_UCODE_ID_ISP = 70 +AMDGPU_UCODE_ID_MAXIMUM = 71 +AMDGPU_UCODE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'AMDGPU_UCODE_STATUS' +AMDGPU_UCODE_STATUS__enumvalues = { + 0: 'AMDGPU_UCODE_STATUS_INVALID', + 1: 'AMDGPU_UCODE_STATUS_NOT_LOADED', + 2: 'AMDGPU_UCODE_STATUS_LOADED', +} +AMDGPU_UCODE_STATUS_INVALID = 0 +AMDGPU_UCODE_STATUS_NOT_LOADED = 1 +AMDGPU_UCODE_STATUS_LOADED = 2 +AMDGPU_UCODE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'amdgpu_firmware_load_type' +amdgpu_firmware_load_type__enumvalues = { + 0: 'AMDGPU_FW_LOAD_DIRECT', + 1: 'AMDGPU_FW_LOAD_PSP', + 2: 'AMDGPU_FW_LOAD_SMU', + 3: 'AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO', +} +AMDGPU_FW_LOAD_DIRECT = 0 +AMDGPU_FW_LOAD_PSP = 1 +AMDGPU_FW_LOAD_SMU = 2 +AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO = 3 +amdgpu_firmware_load_type = ctypes.c_uint32 # enum +class struct_amdgpu_firmware_info(Structure): + pass + +class struct_firmware(Structure): + pass + +struct_amdgpu_firmware_info._pack_ = 1 # source:False +struct_amdgpu_firmware_info._fields_ = [ + ('ucode_id', AMDGPU_UCODE_ID), + ('PADDING_0', ctypes.c_ubyte * 4), + ('fw', ctypes.POINTER(struct_firmware)), + ('mc_addr', ctypes.c_uint64), + ('kaddr', ctypes.POINTER(None)), + ('ucode_size', ctypes.c_uint32), + ('tmr_mc_addr_lo', ctypes.c_uint32), + ('tmr_mc_addr_hi', ctypes.c_uint32), + ('PADDING_1', ctypes.c_ubyte * 4), +] + +_soc21_ENUM_HEADER = True # macro +SQ_WAVE_TYPE_PS0 = 0x00000000 # macro +SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro +SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro +SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro +SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro +SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro +SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro +SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro +SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro +SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro +SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro +SQ_GFXDEC_BEGIN = 0x0000a000 # macro +SQ_GFXDEC_END = 0x0000c000 # macro +SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro +SQDEC_BEGIN = 0x00002300 # macro +SQDEC_END = 0x000023ff # macro +SQPERFSDEC_BEGIN = 0x0000d9c0 # macro +SQPERFSDEC_END = 0x0000da40 # macro +SQPERFDDEC_BEGIN = 0x0000d1c0 # macro +SQPERFDDEC_END = 0x0000d240 # macro +SQGFXUDEC_BEGIN = 0x0000c330 # macro +SQGFXUDEC_END = 0x0000c380 # macro +SQPWRDEC_BEGIN = 0x0000f08c # macro +SQPWRDEC_END = 0x0000f094 # macro +SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro +SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro +SQ_MAX_PGM_SGPRS = 0x00000068 # macro +SQ_MAX_PGM_VGPRS = 0x00000100 # macro +SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro +SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro +SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro +SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro +SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro +SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro +SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro +SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro +SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro +SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro +SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro +INST_ID_PRIV_START = 0x80000000 # macro +INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro +INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro +INST_ID_HW_TRAP = 0xfffffff2 # macro +INST_ID_KILL_SEQ = 0xfffffff3 # macro +INST_ID_SPI_WREXEC = 0xfffffff4 # macro +INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro +INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro +SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro +SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro +SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro +SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000006 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000007 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000008 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000b # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000005 # macro +SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro +SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro +SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro +SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro +SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro +SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro +SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro +SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro +SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro +CSDATA_TYPE_WIDTH = 0x00000002 # macro +CSDATA_ADDR_WIDTH = 0x00000007 # macro +CSDATA_DATA_WIDTH = 0x00000020 # macro +CSCNTL_TYPE_WIDTH = 0x00000002 # macro +CSCNTL_ADDR_WIDTH = 0x00000007 # macro +CSCNTL_DATA_WIDTH = 0x00000020 # macro +GSTHREADID_SIZE = 0x00000002 # macro +GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro +GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro +SEM_ECC_ERROR = 0x00000000 # macro +SEM_TRANS_ERROR = 0x00000001 # macro +SEM_RESP_FAILED = 0x00000002 # macro +SEM_RESP_PASSED = 0x00000003 # macro +IQ_QUEUE_SLEEP = 0x00000000 # macro +IQ_OFFLOAD_RETRY = 0x00000001 # macro +IQ_SCH_WAVE_MSG = 0x00000002 # macro +IQ_SEM_REARM = 0x00000003 # macro +IQ_DEQUEUE_RETRY = 0x00000004 # macro +IQ_INTR_TYPE_PQ = 0x00000000 # macro +IQ_INTR_TYPE_IB = 0x00000001 # macro +IQ_INTR_TYPE_MQD = 0x00000002 # macro +VMID_SZ = 0x00000004 # macro +SRCID_RLC = 0x00000000 # macro +SRCID_RLCV = 0x00000006 # macro +SRCID_SECURE_CP = 0x00000007 # macro +SRCID_NONSECURE_CP = 0x00000001 # macro +SRCID_SECURE_CP_RCIU = 0x00000007 # macro +SRCID_NONSECURE_CP_RCIU = 0x00000001 # macro +CONFIG_SPACE_START = 0x00002000 # macro +CONFIG_SPACE_END = 0x00009fff # macro +CONFIG_SPACE1_START = 0x00002000 # macro +CONFIG_SPACE1_END = 0x00002bff # macro +CONFIG_SPACE2_START = 0x00003000 # macro +CONFIG_SPACE2_END = 0x00009fff # macro +UCONFIG_SPACE_START = 0x0000c000 # macro +UCONFIG_SPACE_END = 0x0000ffff # macro +PERSISTENT_SPACE_START = 0x00002c00 # macro +PERSISTENT_SPACE_END = 0x00002fff # macro +CONTEXT_SPACE_START = 0x0000a000 # macro +CONTEXT_SPACE_END = 0x0000a3ff # macro +ROM_SIGNATURE = 0x0000aa55 # macro + +# values for enumeration 'DSM_DATA_SEL' +DSM_DATA_SEL__enumvalues = { + 0: 'DSM_DATA_SEL_DISABLE', + 1: 'DSM_DATA_SEL_0', + 2: 'DSM_DATA_SEL_1', + 3: 'DSM_DATA_SEL_BOTH', +} +DSM_DATA_SEL_DISABLE = 0 +DSM_DATA_SEL_0 = 1 +DSM_DATA_SEL_1 = 2 +DSM_DATA_SEL_BOTH = 3 +DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_ENABLE_ERROR_INJECT' +DSM_ENABLE_ERROR_INJECT__enumvalues = { + 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', +} +DSM_ENABLE_ERROR_INJECT_FED_IN = 0 +DSM_ENABLE_ERROR_INJECT_SINGLE = 1 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3 +DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SELECT_INJECT_DELAY' +DSM_SELECT_INJECT_DELAY__enumvalues = { + 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', + 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', +} +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 +DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SINGLE_WRITE' +DSM_SINGLE_WRITE__enumvalues = { + 0: 'DSM_SINGLE_WRITE_DIS', + 1: 'DSM_SINGLE_WRITE_EN', +} +DSM_SINGLE_WRITE_DIS = 0 +DSM_SINGLE_WRITE_EN = 1 +DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_NUM_SIMD_PER_CU' +ENUM_NUM_SIMD_PER_CU__enumvalues = { + 2: 'NUM_SIMD_PER_CU', +} +NUM_SIMD_PER_CU = 2 +ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum + +# values for enumeration 'GATCL1RequestType' +GATCL1RequestType__enumvalues = { + 0: 'GATCL1_TYPE_NORMAL', + 1: 'GATCL1_TYPE_SHOOTDOWN', + 2: 'GATCL1_TYPE_BYPASS', +} +GATCL1_TYPE_NORMAL = 0 +GATCL1_TYPE_SHOOTDOWN = 1 +GATCL1_TYPE_BYPASS = 2 +GATCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'GL0V_CACHE_POLICIES' +GL0V_CACHE_POLICIES__enumvalues = { + 0: 'GL0V_CACHE_POLICY_MISS_LRU', + 1: 'GL0V_CACHE_POLICY_MISS_EVICT', + 2: 'GL0V_CACHE_POLICY_HIT_LRU', + 3: 'GL0V_CACHE_POLICY_HIT_EVICT', +} +GL0V_CACHE_POLICY_MISS_LRU = 0 +GL0V_CACHE_POLICY_MISS_EVICT = 1 +GL0V_CACHE_POLICY_HIT_LRU = 2 +GL0V_CACHE_POLICY_HIT_EVICT = 3 +GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_POLICIES' +GL1_CACHE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_POLICY_MISS_LRU', + 1: 'GL1_CACHE_POLICY_MISS_EVICT', + 2: 'GL1_CACHE_POLICY_HIT_LRU', + 3: 'GL1_CACHE_POLICY_HIT_EVICT', +} +GL1_CACHE_POLICY_MISS_LRU = 0 +GL1_CACHE_POLICY_MISS_EVICT = 1 +GL1_CACHE_POLICY_HIT_LRU = 2 +GL1_CACHE_POLICY_HIT_EVICT = 3 +GL1_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_STORE_POLICIES' +GL1_CACHE_STORE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_STORE_POLICY_BYPASS', +} +GL1_CACHE_STORE_POLICY_BYPASS = 0 +GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_CACHE_POLICIES' +GL2_CACHE_POLICIES__enumvalues = { + 0: 'GL2_CACHE_POLICY_LRU', + 1: 'GL2_CACHE_POLICY_STREAM', + 2: 'GL2_CACHE_POLICY_NOA', + 3: 'GL2_CACHE_POLICY_BYPASS', +} +GL2_CACHE_POLICY_LRU = 0 +GL2_CACHE_POLICY_STREAM = 1 +GL2_CACHE_POLICY_NOA = 2 +GL2_CACHE_POLICY_BYPASS = 3 +GL2_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'Hdp_SurfaceEndian' +Hdp_SurfaceEndian__enumvalues = { + 0: 'HDP_ENDIAN_NONE', + 1: 'HDP_ENDIAN_8IN16', + 2: 'HDP_ENDIAN_8IN32', + 3: 'HDP_ENDIAN_8IN64', +} +HDP_ENDIAN_NONE = 0 +HDP_ENDIAN_8IN16 = 1 +HDP_ENDIAN_8IN32 = 2 +HDP_ENDIAN_8IN64 = 3 +Hdp_SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'MTYPE' +MTYPE__enumvalues = { + 0: 'MTYPE_C_RW_US', + 1: 'MTYPE_RESERVED_1', + 2: 'MTYPE_C_RO_S', + 3: 'MTYPE_UC', + 4: 'MTYPE_C_RW_S', + 5: 'MTYPE_RESERVED_5', + 6: 'MTYPE_C_RO_US', + 7: 'MTYPE_RESERVED_7', +} +MTYPE_C_RW_US = 0 +MTYPE_RESERVED_1 = 1 +MTYPE_C_RO_S = 2 +MTYPE_UC = 3 +MTYPE_C_RW_S = 4 +MTYPE_RESERVED_5 = 5 +MTYPE_C_RO_US = 6 +MTYPE_RESERVED_7 = 7 +MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_COUNTER_MODE' +PERFMON_COUNTER_MODE__enumvalues = { + 0: 'PERFMON_COUNTER_MODE_ACCUM', + 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 2: 'PERFMON_COUNTER_MODE_MAX', + 3: 'PERFMON_COUNTER_MODE_DIRTY', + 4: 'PERFMON_COUNTER_MODE_SAMPLE', + 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 15: 'PERFMON_COUNTER_MODE_RESERVED', +} +PERFMON_COUNTER_MODE_ACCUM = 0 +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 +PERFMON_COUNTER_MODE_MAX = 2 +PERFMON_COUNTER_MODE_DIRTY = 3 +PERFMON_COUNTER_MODE_SAMPLE = 4 +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 +PERFMON_COUNTER_MODE_RESERVED = 15 +PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_SPM_MODE' +PERFMON_SPM_MODE__enumvalues = { + 0: 'PERFMON_SPM_MODE_OFF', + 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', + 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', + 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 5: 'PERFMON_SPM_MODE_RESERVED_5', + 6: 'PERFMON_SPM_MODE_RESERVED_6', + 7: 'PERFMON_SPM_MODE_RESERVED_7', + 8: 'PERFMON_SPM_MODE_TEST_MODE_0', + 9: 'PERFMON_SPM_MODE_TEST_MODE_1', + 10: 'PERFMON_SPM_MODE_TEST_MODE_2', +} +PERFMON_SPM_MODE_OFF = 0 +PERFMON_SPM_MODE_16BIT_CLAMP = 1 +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 +PERFMON_SPM_MODE_32BIT_CLAMP = 3 +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 +PERFMON_SPM_MODE_RESERVED_5 = 5 +PERFMON_SPM_MODE_RESERVED_6 = 6 +PERFMON_SPM_MODE_RESERVED_7 = 7 +PERFMON_SPM_MODE_TEST_MODE_0 = 8 +PERFMON_SPM_MODE_TEST_MODE_1 = 9 +PERFMON_SPM_MODE_TEST_MODE_2 = 10 +PERFMON_SPM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RMI_CID' +RMI_CID__enumvalues = { + 0: 'RMI_CID_CC', + 1: 'RMI_CID_FC', + 2: 'RMI_CID_CM', + 3: 'RMI_CID_DC', + 4: 'RMI_CID_Z', + 5: 'RMI_CID_S', + 6: 'RMI_CID_TILE', + 7: 'RMI_CID_ZPCPSD', +} +RMI_CID_CC = 0 +RMI_CID_FC = 1 +RMI_CID_CM = 2 +RMI_CID_DC = 3 +RMI_CID_Z = 4 +RMI_CID_S = 5 +RMI_CID_TILE = 6 +RMI_CID_ZPCPSD = 7 +RMI_CID = ctypes.c_uint32 # enum + +# values for enumeration 'ReadPolicy' +ReadPolicy__enumvalues = { + 0: 'CACHE_LRU_RD', + 1: 'CACHE_STREAM_RD', + 2: 'CACHE_NOA', + 3: 'RESERVED_RDPOLICY', +} +CACHE_LRU_RD = 0 +CACHE_STREAM_RD = 1 +CACHE_NOA = 2 +RESERVED_RDPOLICY = 3 +ReadPolicy = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERFMON_SEL' +SDMA_PERFMON_SEL__enumvalues = { + 0: 'SDMA_PERFMON_SEL_CYCLE', + 1: 'SDMA_PERFMON_SEL_IDLE', + 2: 'SDMA_PERFMON_SEL_REG_IDLE', + 3: 'SDMA_PERFMON_SEL_RB_EMPTY', + 4: 'SDMA_PERFMON_SEL_RB_FULL', + 5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERFMON_SEL_RB_RPTR_WB', + 9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERFMON_SEL_RB_CMD_FULL', + 11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 13: 'SDMA_PERFMON_SEL_EX_IDLE', + 14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERFMON_SEL_WR_BA_RTR', + 17: 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 18: 'SDMA_PERFMON_SEL_MC_WR_COUNT', + 19: 'SDMA_PERFMON_SEL_RD_BA_RTR', + 20: 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 21: 'SDMA_PERFMON_SEL_MC_RD_COUNT', + 22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 26: 'SDMA_PERFMON_SEL_SEM_IDLE', + 27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 32: 'SDMA_PERFMON_SEL_INT_IDLE', + 33: 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 37: 'SDMA_PERFMON_SEL_NUM_PACKET', + 39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', + 40: 'SDMA_PERFMON_SEL_CE_WR_IDLE', + 41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', + 42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', + 43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE', + 44: 'SDMA_PERFMON_SEL_CE_IN_IDLE', + 45: 'SDMA_PERFMON_SEL_CE_DST_IDLE', + 48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', + 51: 'SDMA_PERFMON_SEL_CE_INFO_FULL', + 52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL', + 53: 'SDMA_PERFMON_SEL_CE_RD_STALL', + 54: 'SDMA_PERFMON_SEL_CE_WR_STALL', + 55: 'SDMA_PERFMON_SEL_GFX_SELECT', + 56: 'SDMA_PERFMON_SEL_RLC0_SELECT', + 57: 'SDMA_PERFMON_SEL_RLC1_SELECT', + 58: 'SDMA_PERFMON_SEL_PAGE_SELECT', + 59: 'SDMA_PERFMON_SEL_CTX_CHANGE', + 60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', + 61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 62: 'SDMA_PERFMON_SEL_DOORBELL', + 63: 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERFMON_SEL_UTCL2_FREE', + 74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERFMON_SEL_META_REQ_SEND', + 94: 'SDMA_PERFMON_SEL_META_RTN_VLD', + 95: 'SDMA_PERFMON_SEL_TLBI_SEND', + 96: 'SDMA_PERFMON_SEL_TLBI_RTN', + 97: 'SDMA_PERFMON_SEL_GCR_SEND', + 98: 'SDMA_PERFMON_SEL_GCR_RTN', + 99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', +} +SDMA_PERFMON_SEL_CYCLE = 0 +SDMA_PERFMON_SEL_IDLE = 1 +SDMA_PERFMON_SEL_REG_IDLE = 2 +SDMA_PERFMON_SEL_RB_EMPTY = 3 +SDMA_PERFMON_SEL_RB_FULL = 4 +SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5 +SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6 +SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERFMON_SEL_RB_RPTR_WB = 8 +SDMA_PERFMON_SEL_RB_CMD_IDLE = 9 +SDMA_PERFMON_SEL_RB_CMD_FULL = 10 +SDMA_PERFMON_SEL_IB_CMD_IDLE = 11 +SDMA_PERFMON_SEL_IB_CMD_FULL = 12 +SDMA_PERFMON_SEL_EX_IDLE = 13 +SDMA_PERFMON_SEL_SRBM_REG_SEND = 14 +SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERFMON_SEL_WR_BA_RTR = 16 +SDMA_PERFMON_SEL_MC_WR_IDLE = 17 +SDMA_PERFMON_SEL_MC_WR_COUNT = 18 +SDMA_PERFMON_SEL_RD_BA_RTR = 19 +SDMA_PERFMON_SEL_MC_RD_IDLE = 20 +SDMA_PERFMON_SEL_MC_RD_COUNT = 21 +SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22 +SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23 +SDMA_PERFMON_SEL_SEM_IDLE = 26 +SDMA_PERFMON_SEL_SEM_REQ_STALL = 27 +SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28 +SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29 +SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30 +SDMA_PERFMON_SEL_SEM_RESP_PASS = 31 +SDMA_PERFMON_SEL_INT_IDLE = 32 +SDMA_PERFMON_SEL_INT_REQ_STALL = 33 +SDMA_PERFMON_SEL_INT_REQ_COUNT = 34 +SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35 +SDMA_PERFMON_SEL_INT_RESP_RETRY = 36 +SDMA_PERFMON_SEL_NUM_PACKET = 37 +SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39 +SDMA_PERFMON_SEL_CE_WR_IDLE = 40 +SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41 +SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42 +SDMA_PERFMON_SEL_CE_OUT_IDLE = 43 +SDMA_PERFMON_SEL_CE_IN_IDLE = 44 +SDMA_PERFMON_SEL_CE_DST_IDLE = 45 +SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48 +SDMA_PERFMON_SEL_CE_INFO_FULL = 51 +SDMA_PERFMON_SEL_CE_INFO1_FULL = 52 +SDMA_PERFMON_SEL_CE_RD_STALL = 53 +SDMA_PERFMON_SEL_CE_WR_STALL = 54 +SDMA_PERFMON_SEL_GFX_SELECT = 55 +SDMA_PERFMON_SEL_RLC0_SELECT = 56 +SDMA_PERFMON_SEL_RLC1_SELECT = 57 +SDMA_PERFMON_SEL_PAGE_SELECT = 58 +SDMA_PERFMON_SEL_CTX_CHANGE = 59 +SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60 +SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61 +SDMA_PERFMON_SEL_DOORBELL = 62 +SDMA_PERFMON_SEL_F32_L1_WR_VLD = 63 +SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64 +SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72 +SDMA_PERFMON_SEL_UTCL2_FREE = 73 +SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80 +SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81 +SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82 +SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83 +SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84 +SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87 +SDMA_PERFMON_SEL_L2_META_RET_VLD = 88 +SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERFMON_SEL_META_REQ_SEND = 93 +SDMA_PERFMON_SEL_META_RTN_VLD = 94 +SDMA_PERFMON_SEL_TLBI_SEND = 95 +SDMA_PERFMON_SEL_TLBI_RTN = 96 +SDMA_PERFMON_SEL_GCR_SEND = 97 +SDMA_PERFMON_SEL_GCR_RTN = 98 +SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99 +SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100 +SDMA_PERFMON_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERF_SEL' +SDMA_PERF_SEL__enumvalues = { + 0: 'SDMA_PERF_SEL_CYCLE', + 1: 'SDMA_PERF_SEL_IDLE', + 2: 'SDMA_PERF_SEL_REG_IDLE', + 3: 'SDMA_PERF_SEL_RB_EMPTY', + 4: 'SDMA_PERF_SEL_RB_FULL', + 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERF_SEL_RB_RPTR_WB', + 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERF_SEL_RB_CMD_FULL', + 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERF_SEL_IB_CMD_FULL', + 13: 'SDMA_PERF_SEL_EX_IDLE', + 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERF_SEL_MC_WR_IDLE', + 17: 'SDMA_PERF_SEL_MC_WR_COUNT', + 18: 'SDMA_PERF_SEL_MC_RD_IDLE', + 19: 'SDMA_PERF_SEL_MC_RD_COUNT', + 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'SDMA_PERF_SEL_SEM_IDLE', + 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'SDMA_PERF_SEL_INT_IDLE', + 31: 'SDMA_PERF_SEL_INT_REQ_STALL', + 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'SDMA_PERF_SEL_NUM_PACKET', + 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'SDMA_PERF_SEL_CE_WR_IDLE', + 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'SDMA_PERF_SEL_CE_IN_IDLE', + 43: 'SDMA_PERF_SEL_CE_DST_IDLE', + 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'SDMA_PERF_SEL_CE_INFO_FULL', + 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'SDMA_PERF_SEL_CE_RD_STALL', + 52: 'SDMA_PERF_SEL_CE_WR_STALL', + 53: 'SDMA_PERF_SEL_GFX_SELECT', + 54: 'SDMA_PERF_SEL_RLC0_SELECT', + 55: 'SDMA_PERF_SEL_RLC1_SELECT', + 56: 'SDMA_PERF_SEL_PAGE_SELECT', + 57: 'SDMA_PERF_SEL_CTX_CHANGE', + 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'SDMA_PERF_SEL_DOORBELL', + 61: 'SDMA_PERF_SEL_RD_BA_RTR', + 62: 'SDMA_PERF_SEL_WR_BA_RTR', + 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERF_SEL_UTCL2_FREE', + 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERF_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERF_SEL_META_REQ_SEND', + 94: 'SDMA_PERF_SEL_META_RTN_VLD', + 95: 'SDMA_PERF_SEL_TLBI_SEND', + 96: 'SDMA_PERF_SEL_TLBI_RTN', + 97: 'SDMA_PERF_SEL_GCR_SEND', + 98: 'SDMA_PERF_SEL_GCR_RTN', + 99: 'SDMA_PERF_SEL_CGCG_FENCE', + 100: 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 101: 'SDMA_PERF_SEL_CE_CH_WR_RET', + 102: 'SDMA_PERF_SEL_F32_CH_WR_REQ', + 103: 'SDMA_PERF_SEL_F32_CH_WR_RET', + 104: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', + 105: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', + 106: 'SDMA_PERF_SEL_RB_CH_RD_REQ', + 107: 'SDMA_PERF_SEL_RB_CH_RD_RET', + 108: 'SDMA_PERF_SEL_IB_CH_RD_REQ', + 109: 'SDMA_PERF_SEL_IB_CH_RD_RET', + 110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET', + 112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 114: 'SDMA_PERF_SEL_CMD_OP_MATCH', + 115: 'SDMA_PERF_SEL_CMD_OP_START', + 116: 'SDMA_PERF_SEL_CMD_OP_END', + 117: 'SDMA_PERF_SEL_CE_BUSY', + 118: 'SDMA_PERF_SEL_CE_BUSY_START', + 119: 'SDMA_PERF_SEL_CE_BUSY_END', + 120: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 121: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 122: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', + 124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', + 125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', +} +SDMA_PERF_SEL_CYCLE = 0 +SDMA_PERF_SEL_IDLE = 1 +SDMA_PERF_SEL_REG_IDLE = 2 +SDMA_PERF_SEL_RB_EMPTY = 3 +SDMA_PERF_SEL_RB_FULL = 4 +SDMA_PERF_SEL_RB_WPTR_WRAP = 5 +SDMA_PERF_SEL_RB_RPTR_WRAP = 6 +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERF_SEL_RB_RPTR_WB = 8 +SDMA_PERF_SEL_RB_CMD_IDLE = 9 +SDMA_PERF_SEL_RB_CMD_FULL = 10 +SDMA_PERF_SEL_IB_CMD_IDLE = 11 +SDMA_PERF_SEL_IB_CMD_FULL = 12 +SDMA_PERF_SEL_EX_IDLE = 13 +SDMA_PERF_SEL_SRBM_REG_SEND = 14 +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERF_SEL_MC_WR_IDLE = 16 +SDMA_PERF_SEL_MC_WR_COUNT = 17 +SDMA_PERF_SEL_MC_RD_IDLE = 18 +SDMA_PERF_SEL_MC_RD_COUNT = 19 +SDMA_PERF_SEL_MC_RD_RET_STALL = 20 +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +SDMA_PERF_SEL_SEM_IDLE = 24 +SDMA_PERF_SEL_SEM_REQ_STALL = 25 +SDMA_PERF_SEL_SEM_REQ_COUNT = 26 +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +SDMA_PERF_SEL_SEM_RESP_FAIL = 28 +SDMA_PERF_SEL_SEM_RESP_PASS = 29 +SDMA_PERF_SEL_INT_IDLE = 30 +SDMA_PERF_SEL_INT_REQ_STALL = 31 +SDMA_PERF_SEL_INT_REQ_COUNT = 32 +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +SDMA_PERF_SEL_INT_RESP_RETRY = 34 +SDMA_PERF_SEL_NUM_PACKET = 35 +SDMA_PERF_SEL_CE_WREQ_IDLE = 37 +SDMA_PERF_SEL_CE_WR_IDLE = 38 +SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +SDMA_PERF_SEL_CE_RREQ_IDLE = 40 +SDMA_PERF_SEL_CE_OUT_IDLE = 41 +SDMA_PERF_SEL_CE_IN_IDLE = 42 +SDMA_PERF_SEL_CE_DST_IDLE = 43 +SDMA_PERF_SEL_CE_AFIFO_FULL = 46 +SDMA_PERF_SEL_CE_INFO_FULL = 49 +SDMA_PERF_SEL_CE_INFO1_FULL = 50 +SDMA_PERF_SEL_CE_RD_STALL = 51 +SDMA_PERF_SEL_CE_WR_STALL = 52 +SDMA_PERF_SEL_GFX_SELECT = 53 +SDMA_PERF_SEL_RLC0_SELECT = 54 +SDMA_PERF_SEL_RLC1_SELECT = 55 +SDMA_PERF_SEL_PAGE_SELECT = 56 +SDMA_PERF_SEL_CTX_CHANGE = 57 +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +SDMA_PERF_SEL_DOORBELL = 60 +SDMA_PERF_SEL_RD_BA_RTR = 61 +SDMA_PERF_SEL_WR_BA_RTR = 62 +SDMA_PERF_SEL_F32_L1_WR_VLD = 63 +SDMA_PERF_SEL_CE_L1_WR_VLD = 64 +SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERF_SEL_UTCL2_RET_ACK = 72 +SDMA_PERF_SEL_UTCL2_FREE = 73 +SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERF_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERF_SEL_GPUVM_INV_LOW = 80 +SDMA_PERF_SEL_L1_WRL2_IDLE = 81 +SDMA_PERF_SEL_L1_RDL2_IDLE = 82 +SDMA_PERF_SEL_L1_WRMC_IDLE = 83 +SDMA_PERF_SEL_L1_RDMC_IDLE = 84 +SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERF_SEL_META_L2_REQ_SEND = 87 +SDMA_PERF_SEL_L2_META_RET_VLD = 88 +SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERF_SEL_META_REQ_SEND = 93 +SDMA_PERF_SEL_META_RTN_VLD = 94 +SDMA_PERF_SEL_TLBI_SEND = 95 +SDMA_PERF_SEL_TLBI_RTN = 96 +SDMA_PERF_SEL_GCR_SEND = 97 +SDMA_PERF_SEL_GCR_RTN = 98 +SDMA_PERF_SEL_CGCG_FENCE = 99 +SDMA_PERF_SEL_CE_CH_WR_REQ = 100 +SDMA_PERF_SEL_CE_CH_WR_RET = 101 +SDMA_PERF_SEL_F32_CH_WR_REQ = 102 +SDMA_PERF_SEL_F32_CH_WR_RET = 103 +SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 104 +SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 105 +SDMA_PERF_SEL_RB_CH_RD_REQ = 106 +SDMA_PERF_SEL_RB_CH_RD_RET = 107 +SDMA_PERF_SEL_IB_CH_RD_REQ = 108 +SDMA_PERF_SEL_IB_CH_RD_RET = 109 +SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110 +SDMA_PERF_SEL_WPTR_CH_RD_RET = 111 +SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112 +SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113 +SDMA_PERF_SEL_CMD_OP_MATCH = 114 +SDMA_PERF_SEL_CMD_OP_START = 115 +SDMA_PERF_SEL_CMD_OP_END = 116 +SDMA_PERF_SEL_CE_BUSY = 117 +SDMA_PERF_SEL_CE_BUSY_START = 118 +SDMA_PERF_SEL_CE_BUSY_END = 119 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 120 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 121 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 122 +SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123 +SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124 +SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125 +SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126 +SDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_CACHE_POLICIES' +TCC_CACHE_POLICIES__enumvalues = { + 0: 'TCC_CACHE_POLICY_LRU', + 1: 'TCC_CACHE_POLICY_STREAM', +} +TCC_CACHE_POLICY_LRU = 0 +TCC_CACHE_POLICY_STREAM = 1 +TCC_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_MTYPE' +TCC_MTYPE__enumvalues = { + 0: 'MTYPE_NC', + 1: 'MTYPE_WC', + 2: 'MTYPE_CC', +} +MTYPE_NC = 0 +MTYPE_WC = 1 +MTYPE_CC = 2 +TCC_MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0FaultType' +UTCL0FaultType__enumvalues = { + 0: 'UTCL0_XNACK_SUCCESS', + 1: 'UTCL0_XNACK_RETRY', + 2: 'UTCL0_XNACK_PRT', + 3: 'UTCL0_XNACK_NO_RETRY', +} +UTCL0_XNACK_SUCCESS = 0 +UTCL0_XNACK_RETRY = 1 +UTCL0_XNACK_PRT = 2 +UTCL0_XNACK_NO_RETRY = 3 +UTCL0FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0RequestType' +UTCL0RequestType__enumvalues = { + 0: 'UTCL0_TYPE_NORMAL', + 1: 'UTCL0_TYPE_SHOOTDOWN', + 2: 'UTCL0_TYPE_BYPASS', +} +UTCL0_TYPE_NORMAL = 0 +UTCL0_TYPE_SHOOTDOWN = 1 +UTCL0_TYPE_BYPASS = 2 +UTCL0RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1FaultType' +UTCL1FaultType__enumvalues = { + 0: 'UTCL1_XNACK_SUCCESS', + 1: 'UTCL1_XNACK_RETRY', + 2: 'UTCL1_XNACK_PRT', + 3: 'UTCL1_XNACK_NO_RETRY', +} +UTCL1_XNACK_SUCCESS = 0 +UTCL1_XNACK_RETRY = 1 +UTCL1_XNACK_PRT = 2 +UTCL1_XNACK_NO_RETRY = 3 +UTCL1FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1RequestType' +UTCL1RequestType__enumvalues = { + 0: 'UTCL1_TYPE_NORMAL', + 1: 'UTCL1_TYPE_SHOOTDOWN', + 2: 'UTCL1_TYPE_BYPASS', +} +UTCL1_TYPE_NORMAL = 0 +UTCL1_TYPE_SHOOTDOWN = 1 +UTCL1_TYPE_BYPASS = 2 +UTCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'VMEMCMD_RETURN_ORDER' +VMEMCMD_RETURN_ORDER__enumvalues = { + 0: 'VMEMCMD_RETURN_OUT_OF_ORDER', + 1: 'VMEMCMD_RETURN_IN_ORDER', + 2: 'VMEMCMD_RETURN_IN_ORDER_READ', +} +VMEMCMD_RETURN_OUT_OF_ORDER = 0 +VMEMCMD_RETURN_IN_ORDER = 1 +VMEMCMD_RETURN_IN_ORDER_READ = 2 +VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'WritePolicy' +WritePolicy__enumvalues = { + 0: 'CACHE_LRU_WR', + 1: 'CACHE_STREAM', + 2: 'CACHE_NOA_WR', + 3: 'CACHE_BYPASS', +} +CACHE_LRU_WR = 0 +CACHE_STREAM = 1 +CACHE_NOA_WR = 2 +CACHE_BYPASS = 3 +WritePolicy = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_BYPASS' +CNVC_BYPASS__enumvalues = { + 0: 'CNVC_BYPASS_DISABLE', + 1: 'CNVC_BYPASS_EN', +} +CNVC_BYPASS_DISABLE = 0 +CNVC_BYPASS_EN = 1 +CNVC_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_COEF_FORMAT_ENUM' +CNVC_COEF_FORMAT_ENUM__enumvalues = { + 0: 'CNVC_FIX_S2_13', + 1: 'CNVC_FIX_S3_12', +} +CNVC_FIX_S2_13 = 0 +CNVC_FIX_S3_12 = 1 +CNVC_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_ENABLE' +CNVC_ENABLE__enumvalues = { + 0: 'CNVC_DIS', + 1: 'CNVC_EN', +} +CNVC_DIS = 0 +CNVC_EN = 1 +CNVC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_PENDING' +CNVC_PENDING__enumvalues = { + 0: 'CNVC_NOT_PENDING', + 1: 'CNVC_YES_PENDING', +} +CNVC_NOT_PENDING = 0 +CNVC_YES_PENDING = 1 +CNVC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'COLOR_KEYER_MODE' +COLOR_KEYER_MODE__enumvalues = { + 0: 'FORCE_00', + 1: 'FORCE_FF', + 2: 'RANGE_00', + 3: 'RANGE_FF', +} +FORCE_00 = 0 +FORCE_FF = 1 +RANGE_00 = 2 +RANGE_FF = 3 +COLOR_KEYER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DENORM_TRUNCATE' +DENORM_TRUNCATE__enumvalues = { + 0: 'CNVC_ROUND', + 1: 'CNVC_TRUNCATE', +} +CNVC_ROUND = 0 +CNVC_TRUNCATE = 1 +DENORM_TRUNCATE = ctypes.c_uint32 # enum + +# values for enumeration 'FORMAT_CROSSBAR' +FORMAT_CROSSBAR__enumvalues = { + 0: 'FORMAT_CROSSBAR_R', + 1: 'FORMAT_CROSSBAR_G', + 2: 'FORMAT_CROSSBAR_B', +} +FORMAT_CROSSBAR_R = 0 +FORMAT_CROSSBAR_G = 1 +FORMAT_CROSSBAR_B = 2 +FORMAT_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'PIX_EXPAND_MODE' +PIX_EXPAND_MODE__enumvalues = { + 0: 'PIX_DYNAMIC_EXPANSION', + 1: 'PIX_ZERO_EXPANSION', +} +PIX_DYNAMIC_EXPANSION = 0 +PIX_ZERO_EXPANSION = 1 +PIX_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_CSC_MODE_ENUM' +PRE_CSC_MODE_ENUM__enumvalues = { + 0: 'PRE_CSC_BYPASS', + 1: 'PRE_CSC_SET_A', + 2: 'PRE_CSC_SET_B', +} +PRE_CSC_BYPASS = 0 +PRE_CSC_SET_A = 1 +PRE_CSC_SET_B = 2 +PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_MODE' +PRE_DEGAM_MODE__enumvalues = { + 0: 'PRE_DEGAM_BYPASS', + 1: 'PRE_DEGAM_ENABLE', +} +PRE_DEGAM_BYPASS = 0 +PRE_DEGAM_ENABLE = 1 +PRE_DEGAM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_SELECT' +PRE_DEGAM_SELECT__enumvalues = { + 0: 'PRE_DEGAM_SRGB', + 1: 'PRE_DEGAM_GAMMA_22', + 2: 'PRE_DEGAM_GAMMA_24', + 3: 'PRE_DEGAM_GAMMA_26', + 4: 'PRE_DEGAM_BT2020', + 5: 'PRE_DEGAM_BT2100PQ', + 6: 'PRE_DEGAM_BT2100HLG', +} +PRE_DEGAM_SRGB = 0 +PRE_DEGAM_GAMMA_22 = 1 +PRE_DEGAM_GAMMA_24 = 2 +PRE_DEGAM_GAMMA_26 = 3 +PRE_DEGAM_BT2020 = 4 +PRE_DEGAM_BT2100PQ = 5 +PRE_DEGAM_BT2100HLG = 6 +PRE_DEGAM_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_PIXEL_FORMAT' +SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'ARGB1555', + 2: 'RGBA5551', + 3: 'RGB565', + 4: 'BGR565', + 5: 'ARGB4444', + 6: 'RGBA4444', + 8: 'ARGB8888', + 9: 'RGBA8888', + 10: 'ARGB2101010', + 11: 'RGBA1010102', + 12: 'AYCrCb8888', + 13: 'YCrCbA8888', + 14: 'ACrYCb8888', + 15: 'CrYCbA8888', + 16: 'ARGB16161616_10MSB', + 17: 'RGBA16161616_10MSB', + 18: 'ARGB16161616_10LSB', + 19: 'RGBA16161616_10LSB', + 20: 'ARGB16161616_12MSB', + 21: 'RGBA16161616_12MSB', + 22: 'ARGB16161616_12LSB', + 23: 'RGBA16161616_12LSB', + 24: 'ARGB16161616_FLOAT', + 25: 'RGBA16161616_FLOAT', + 26: 'ARGB16161616_UNORM', + 27: 'RGBA16161616_UNORM', + 28: 'ARGB16161616_SNORM', + 29: 'RGBA16161616_SNORM', + 32: 'AYCrCb16161616_10MSB', + 33: 'AYCrCb16161616_10LSB', + 34: 'YCrCbA16161616_10MSB', + 35: 'YCrCbA16161616_10LSB', + 36: 'ACrYCb16161616_10MSB', + 37: 'ACrYCb16161616_10LSB', + 38: 'CrYCbA16161616_10MSB', + 39: 'CrYCbA16161616_10LSB', + 40: 'AYCrCb16161616_12MSB', + 41: 'AYCrCb16161616_12LSB', + 42: 'YCrCbA16161616_12MSB', + 43: 'YCrCbA16161616_12LSB', + 44: 'ACrYCb16161616_12MSB', + 45: 'ACrYCb16161616_12LSB', + 46: 'CrYCbA16161616_12MSB', + 47: 'CrYCbA16161616_12LSB', + 64: 'Y8_CrCb88_420_PLANAR', + 65: 'Y8_CbCr88_420_PLANAR', + 66: 'Y10_CrCb1010_420_PLANAR', + 67: 'Y10_CbCr1010_420_PLANAR', + 68: 'Y12_CrCb1212_420_PLANAR', + 69: 'Y12_CbCr1212_420_PLANAR', + 72: 'YCrYCb8888_422_PACKED', + 73: 'YCbYCr8888_422_PACKED', + 74: 'CrYCbY8888_422_PACKED', + 75: 'CbYCrY8888_422_PACKED', + 76: 'YCrYCb10101010_422_PACKED', + 77: 'YCbYCr10101010_422_PACKED', + 78: 'CrYCbY10101010_422_PACKED', + 79: 'CbYCrY10101010_422_PACKED', + 80: 'YCrYCb12121212_422_PACKED', + 81: 'YCbYCr12121212_422_PACKED', + 82: 'CrYCbY12121212_422_PACKED', + 83: 'CbYCrY12121212_422_PACKED', + 112: 'RGB111110_FIX', + 113: 'BGR101111_FIX', + 114: 'ACrYCb2101010', + 115: 'CrYCbA1010102', + 116: 'RGBE', + 118: 'RGB111110_FLOAT', + 119: 'BGR101111_FLOAT', + 120: 'MONO_8', + 121: 'MONO_10MSB', + 122: 'MONO_10LSB', + 123: 'MONO_12MSB', + 124: 'MONO_12LSB', + 125: 'MONO_16', +} +ARGB1555 = 1 +RGBA5551 = 2 +RGB565 = 3 +BGR565 = 4 +ARGB4444 = 5 +RGBA4444 = 6 +ARGB8888 = 8 +RGBA8888 = 9 +ARGB2101010 = 10 +RGBA1010102 = 11 +AYCrCb8888 = 12 +YCrCbA8888 = 13 +ACrYCb8888 = 14 +CrYCbA8888 = 15 +ARGB16161616_10MSB = 16 +RGBA16161616_10MSB = 17 +ARGB16161616_10LSB = 18 +RGBA16161616_10LSB = 19 +ARGB16161616_12MSB = 20 +RGBA16161616_12MSB = 21 +ARGB16161616_12LSB = 22 +RGBA16161616_12LSB = 23 +ARGB16161616_FLOAT = 24 +RGBA16161616_FLOAT = 25 +ARGB16161616_UNORM = 26 +RGBA16161616_UNORM = 27 +ARGB16161616_SNORM = 28 +RGBA16161616_SNORM = 29 +AYCrCb16161616_10MSB = 32 +AYCrCb16161616_10LSB = 33 +YCrCbA16161616_10MSB = 34 +YCrCbA16161616_10LSB = 35 +ACrYCb16161616_10MSB = 36 +ACrYCb16161616_10LSB = 37 +CrYCbA16161616_10MSB = 38 +CrYCbA16161616_10LSB = 39 +AYCrCb16161616_12MSB = 40 +AYCrCb16161616_12LSB = 41 +YCrCbA16161616_12MSB = 42 +YCrCbA16161616_12LSB = 43 +ACrYCb16161616_12MSB = 44 +ACrYCb16161616_12LSB = 45 +CrYCbA16161616_12MSB = 46 +CrYCbA16161616_12LSB = 47 +Y8_CrCb88_420_PLANAR = 64 +Y8_CbCr88_420_PLANAR = 65 +Y10_CrCb1010_420_PLANAR = 66 +Y10_CbCr1010_420_PLANAR = 67 +Y12_CrCb1212_420_PLANAR = 68 +Y12_CbCr1212_420_PLANAR = 69 +YCrYCb8888_422_PACKED = 72 +YCbYCr8888_422_PACKED = 73 +CrYCbY8888_422_PACKED = 74 +CbYCrY8888_422_PACKED = 75 +YCrYCb10101010_422_PACKED = 76 +YCbYCr10101010_422_PACKED = 77 +CrYCbY10101010_422_PACKED = 78 +CbYCrY10101010_422_PACKED = 79 +YCrYCb12121212_422_PACKED = 80 +YCbYCr12121212_422_PACKED = 81 +CrYCbY12121212_422_PACKED = 82 +CbYCrY12121212_422_PACKED = 83 +RGB111110_FIX = 112 +BGR101111_FIX = 113 +ACrYCb2101010 = 114 +CrYCbA1010102 = 115 +RGBE = 116 +RGB111110_FLOAT = 118 +BGR101111_FLOAT = 119 +MONO_8 = 120 +MONO_10MSB = 121 +MONO_10LSB = 122 +MONO_12MSB = 123 +MONO_12LSB = 124 +MONO_16 = 125 +SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'XNORM' +XNORM__enumvalues = { + 0: 'XNORM_A', + 1: 'XNORM_B', +} +XNORM_A = 0 +XNORM_B = 1 +XNORM = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ENABLE' +CUR_ENABLE__enumvalues = { + 0: 'CUR_DIS', + 1: 'CUR_EN', +} +CUR_DIS = 0 +CUR_EN = 1 +CUR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_EXPAND_MODE' +CUR_EXPAND_MODE__enumvalues = { + 0: 'CUR_DYNAMIC_EXPANSION', + 1: 'CUR_ZERO_EXPANSION', +} +CUR_DYNAMIC_EXPANSION = 0 +CUR_ZERO_EXPANSION = 1 +CUR_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_INV_CLAMP' +CUR_INV_CLAMP__enumvalues = { + 0: 'CUR_CLAMP_DIS', + 1: 'CUR_CLAMP_EN', +} +CUR_CLAMP_DIS = 0 +CUR_CLAMP_EN = 1 +CUR_INV_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_MODE' +CUR_MODE__enumvalues = { + 0: 'MONO_2BIT', + 1: 'COLOR_24BIT_1BIT_AND', + 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'COLOR_64BIT_FP_PREMULT', + 5: 'COLOR_64BIT_FP_UNPREMULT', +} +MONO_2BIT = 0 +COLOR_24BIT_1BIT_AND = 1 +COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +COLOR_64BIT_FP_PREMULT = 4 +COLOR_64BIT_FP_UNPREMULT = 5 +CUR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_PENDING' +CUR_PENDING__enumvalues = { + 0: 'CUR_NOT_PENDING', + 1: 'CUR_YES_PENDING', +} +CUR_NOT_PENDING = 0 +CUR_YES_PENDING = 1 +CUR_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ROM_EN' +CUR_ROM_EN__enumvalues = { + 0: 'CUR_FP_NO_ROM', + 1: 'CUR_FP_USE_ROM', +} +CUR_FP_NO_ROM = 0 +CUR_FP_USE_ROM = 1 +CUR_ROM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'COEF_RAM_SELECT_RD' +COEF_RAM_SELECT_RD__enumvalues = { + 0: 'COEF_RAM_SELECT_BACK', + 1: 'COEF_RAM_SELECT_CURRENT', +} +COEF_RAM_SELECT_BACK = 0 +COEF_RAM_SELECT_CURRENT = 1 +COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum + +# values for enumeration 'DSCL_MODE_SEL' +DSCL_MODE_SEL__enumvalues = { + 0: 'DSCL_MODE_SCALING_444_BYPASS', + 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', + 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', + 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', + 6: 'DSCL_MODE_DSCL_BYPASS', +} +DSCL_MODE_SCALING_444_BYPASS = 0 +DSCL_MODE_SCALING_444_RGB_ENABLE = 1 +DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 +DSCL_MODE_SCALING_YCBCR_ENABLE = 3 +DSCL_MODE_LUMA_SCALING_BYPASS = 4 +DSCL_MODE_CHROMA_SCALING_BYPASS = 5 +DSCL_MODE_DSCL_BYPASS = 6 +DSCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LB_ALPHA_EN' +LB_ALPHA_EN__enumvalues = { + 0: 'LB_ALPHA_DISABLE', + 1: 'LB_ALPHA_ENABLE', +} +LB_ALPHA_DISABLE = 0 +LB_ALPHA_ENABLE = 1 +LB_ALPHA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERLEAVE_EN' +LB_INTERLEAVE_EN__enumvalues = { + 0: 'LB_INTERLEAVE_DISABLE', + 1: 'LB_INTERLEAVE_ENABLE', +} +LB_INTERLEAVE_DISABLE = 0 +LB_INTERLEAVE_ENABLE = 1 +LB_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MEMORY_CONFIG' +LB_MEMORY_CONFIG__enumvalues = { + 0: 'LB_MEMORY_CONFIG_0', + 1: 'LB_MEMORY_CONFIG_1', + 2: 'LB_MEMORY_CONFIG_2', + 3: 'LB_MEMORY_CONFIG_3', +} +LB_MEMORY_CONFIG_0 = 0 +LB_MEMORY_CONFIG_1 = 1 +LB_MEMORY_CONFIG_2 = 2 +LB_MEMORY_CONFIG_3 = 3 +LB_MEMORY_CONFIG = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_BYPASS_SEL' +OBUF_BYPASS_SEL__enumvalues = { + 0: 'OBUF_BYPASS_DIS', + 1: 'OBUF_BYPASS_EN', +} +OBUF_BYPASS_DIS = 0 +OBUF_BYPASS_EN = 1 +OBUF_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' +OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { + 0: 'OBUF_FULL_RECOUT', + 1: 'OBUF_HALF_RECOUT', +} +OBUF_FULL_RECOUT = 0 +OBUF_HALF_RECOUT = 1 +OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' +OBUF_USE_FULL_BUFFER_SEL__enumvalues = { + 0: 'OBUF_RECOUT', + 1: 'OBUF_FULL', +} +OBUF_RECOUT = 0 +OBUF_FULL = 1 +OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_2TAP_HARDCODE' +SCL_2TAP_HARDCODE__enumvalues = { + 0: 'SCL_COEF_2TAP_HARDCODE_OFF', + 1: 'SCL_COEF_2TAP_HARDCODE_ON', +} +SCL_COEF_2TAP_HARDCODE_OFF = 0 +SCL_COEF_2TAP_HARDCODE_ON = 1 +SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_ALPHA_COEF' +SCL_ALPHA_COEF__enumvalues = { + 0: 'SCL_ALPHA_COEF_FIRST', + 1: 'SCL_ALPHA_COEF_SECOND', +} +SCL_ALPHA_COEF_FIRST = 0 +SCL_ALPHA_COEF_SECOND = 1 +SCL_ALPHA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_AUTOCAL_MODE' +SCL_AUTOCAL_MODE__enumvalues = { + 0: 'AUTOCAL_MODE_OFF', + 1: 'AUTOCAL_MODE_AUTOSCALE', + 2: 'AUTOCAL_MODE_AUTOCENTER', + 3: 'AUTOCAL_MODE_AUTOREPLICATE', +} +AUTOCAL_MODE_OFF = 0 +AUTOCAL_MODE_AUTOSCALE = 1 +AUTOCAL_MODE_AUTOCENTER = 2 +AUTOCAL_MODE_AUTOREPLICATE = 3 +SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BOUNDARY' +SCL_BOUNDARY__enumvalues = { + 0: 'SCL_BOUNDARY_EDGE', + 1: 'SCL_BOUNDARY_BLACK', +} +SCL_BOUNDARY_EDGE = 0 +SCL_BOUNDARY_BLACK = 1 +SCL_BOUNDARY = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_CHROMA_COEF' +SCL_CHROMA_COEF__enumvalues = { + 0: 'SCL_CHROMA_COEF_FIRST', + 1: 'SCL_CHROMA_COEF_SECOND', +} +SCL_CHROMA_COEF_FIRST = 0 +SCL_CHROMA_COEF_SECOND = 1 +SCL_CHROMA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' +SCL_COEF_FILTER_TYPE_SEL__enumvalues = { + 0: 'SCL_COEF_LUMA_VERT_FILTER', + 1: 'SCL_COEF_LUMA_HORZ_FILTER', + 2: 'SCL_COEF_CHROMA_VERT_FILTER', + 3: 'SCL_COEF_CHROMA_HORZ_FILTER', +} +SCL_COEF_LUMA_VERT_FILTER = 0 +SCL_COEF_LUMA_HORZ_FILTER = 1 +SCL_COEF_CHROMA_VERT_FILTER = 2 +SCL_COEF_CHROMA_HORZ_FILTER = 3 +SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_RAM_SEL' +SCL_COEF_RAM_SEL__enumvalues = { + 0: 'SCL_COEF_RAM_SEL_0', + 1: 'SCL_COEF_RAM_SEL_1', +} +SCL_COEF_RAM_SEL_0 = 0 +SCL_COEF_RAM_SEL_1 = 1 +SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_SHARP_EN' +SCL_SHARP_EN__enumvalues = { + 0: 'SCL_SHARP_DISABLE', + 1: 'SCL_SHARP_ENABLE', +} +SCL_SHARP_DISABLE = 0 +SCL_SHARP_ENABLE = 1 +SCL_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_30BIT_ENUM' +CMC_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'CMC_3DLUT_36BIT', + 1: 'CMC_3DLUT_30BIT', +} +CMC_3DLUT_36BIT = 0 +CMC_3DLUT_30BIT = 1 +CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_RAM_SEL' +CMC_3DLUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAM0_ACCESS', + 1: 'CMC_RAM1_ACCESS', + 2: 'CMC_RAM2_ACCESS', + 3: 'CMC_RAM3_ACCESS', +} +CMC_RAM0_ACCESS = 0 +CMC_RAM1_ACCESS = 1 +CMC_RAM2_ACCESS = 2 +CMC_RAM3_ACCESS = 3 +CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_SIZE_ENUM' +CMC_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'CMC_3DLUT_17CUBE', + 1: 'CMC_3DLUT_9CUBE', +} +CMC_3DLUT_17CUBE = 0 +CMC_3DLUT_9CUBE = 1 +CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' +CMC_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'CMC_LUT_2CFG_NO_MEMORY', + 1: 'CMC_LUT_2CFG_MEMORY_A', + 2: 'CMC_LUT_2CFG_MEMORY_B', +} +CMC_LUT_2CFG_NO_MEMORY = 0 +CMC_LUT_2CFG_MEMORY_A = 1 +CMC_LUT_2CFG_MEMORY_B = 2 +CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_MODE_ENUM' +CMC_LUT_2_MODE_ENUM__enumvalues = { + 0: 'CMC_LUT_2_MODE_BYPASS', + 1: 'CMC_LUT_2_MODE_RAMA_LUT', + 2: 'CMC_LUT_2_MODE_RAMB_LUT', +} +CMC_LUT_2_MODE_BYPASS = 0 +CMC_LUT_2_MODE_RAMA_LUT = 1 +CMC_LUT_2_MODE_RAMB_LUT = 2 +CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_NUM_SEG' +CMC_LUT_NUM_SEG__enumvalues = { + 0: 'CMC_SEGMENTS_1', + 1: 'CMC_SEGMENTS_2', + 2: 'CMC_SEGMENTS_4', + 3: 'CMC_SEGMENTS_8', + 4: 'CMC_SEGMENTS_16', + 5: 'CMC_SEGMENTS_32', + 6: 'CMC_SEGMENTS_64', + 7: 'CMC_SEGMENTS_128', +} +CMC_SEGMENTS_1 = 0 +CMC_SEGMENTS_2 = 1 +CMC_SEGMENTS_4 = 2 +CMC_SEGMENTS_8 = 3 +CMC_SEGMENTS_16 = 4 +CMC_SEGMENTS_32 = 5 +CMC_SEGMENTS_64 = 6 +CMC_SEGMENTS_128 = 7 +CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_RAM_SEL' +CMC_LUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAMA_ACCESS', + 1: 'CMC_RAMB_ACCESS', +} +CMC_RAMA_ACCESS = 0 +CMC_RAMB_ACCESS = 1 +CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_BYPASS' +CM_BYPASS__enumvalues = { + 0: 'NON_BYPASS', + 1: 'BYPASS_EN', +} +NON_BYPASS = 0 +BYPASS_EN = 1 +CM_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CM_COEF_FORMAT_ENUM' +CM_COEF_FORMAT_ENUM__enumvalues = { + 0: 'FIX_S2_13', + 1: 'FIX_S3_12', +} +FIX_S2_13 = 0 +FIX_S3_12 = 1 +CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_DATA_SIGNED' +CM_DATA_SIGNED__enumvalues = { + 0: 'UNSIGNED', + 1: 'SIGNED', +} +UNSIGNED = 0 +SIGNED = 1 +CM_DATA_SIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'CM_EN' +CM_EN__enumvalues = { + 0: 'CM_DISABLE', + 1: 'CM_ENABLE', +} +CM_DISABLE = 0 +CM_ENABLE = 1 +CM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM' +CM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'BYPASS', + 1: 'RESERVED_1', + 2: 'RAM_LUT', + 3: 'RESERVED_3', +} +BYPASS = 0 +RESERVED_1 = 1 +RAM_LUT = 2 +RESERVED_3 = 3 +CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM' +CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'ENABLE_PWL', + 1: 'DISABLE_PWL', +} +ENABLE_PWL = 0 +DISABLE_PWL = 1 +CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM' +CM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'RAMA', + 1: 'RAMB', +} +RAMA = 0 +RAMB = 1 +CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM' +CM_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'BYPASS_GAMUT', + 1: 'GAMUT_COEF', + 2: 'GAMUT_COEF_B', +} +BYPASS_GAMUT = 0 +GAMUT_COEF = 1 +GAMUT_COEF_B = 2 +CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_CONFIG_ENUM' +CM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'LUT_2CFG_NO_MEMORY', + 1: 'LUT_2CFG_MEMORY_A', + 2: 'LUT_2CFG_MEMORY_B', +} +LUT_2CFG_NO_MEMORY = 0 +LUT_2CFG_MEMORY_A = 1 +LUT_2CFG_MEMORY_B = 2 +CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_MODE_ENUM' +CM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'LUT_2_MODE_BYPASS', + 1: 'LUT_2_MODE_RAMA_LUT', + 2: 'LUT_2_MODE_RAMB_LUT', +} +LUT_2_MODE_BYPASS = 0 +LUT_2_MODE_RAMA_LUT = 1 +LUT_2_MODE_RAMB_LUT = 2 +CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_CONFIG_ENUM' +CM_LUT_4_CONFIG_ENUM__enumvalues = { + 0: 'LUT_4CFG_NO_MEMORY', + 1: 'LUT_4CFG_ROM_A', + 2: 'LUT_4CFG_ROM_B', + 3: 'LUT_4CFG_MEMORY_A', + 4: 'LUT_4CFG_MEMORY_B', +} +LUT_4CFG_NO_MEMORY = 0 +LUT_4CFG_ROM_A = 1 +LUT_4CFG_ROM_B = 2 +LUT_4CFG_MEMORY_A = 3 +LUT_4CFG_MEMORY_B = 4 +CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_MODE_ENUM' +CM_LUT_4_MODE_ENUM__enumvalues = { + 0: 'LUT_4_MODE_BYPASS', + 1: 'LUT_4_MODE_ROMA_LUT', + 2: 'LUT_4_MODE_ROMB_LUT', + 3: 'LUT_4_MODE_RAMA_LUT', + 4: 'LUT_4_MODE_RAMB_LUT', +} +LUT_4_MODE_BYPASS = 0 +LUT_4_MODE_ROMA_LUT = 1 +LUT_4_MODE_ROMB_LUT = 2 +LUT_4_MODE_RAMA_LUT = 3 +LUT_4_MODE_RAMB_LUT = 4 +CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_CONFIG_MODE' +CM_LUT_CONFIG_MODE__enumvalues = { + 0: 'DIFFERENT_RGB', + 1: 'ALL_USE_R', +} +DIFFERENT_RGB = 0 +ALL_USE_R = 1 +CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_NUM_SEG' +CM_LUT_NUM_SEG__enumvalues = { + 0: 'SEGMENTS_1', + 1: 'SEGMENTS_2', + 2: 'SEGMENTS_4', + 3: 'SEGMENTS_8', + 4: 'SEGMENTS_16', + 5: 'SEGMENTS_32', + 6: 'SEGMENTS_64', + 7: 'SEGMENTS_128', +} +SEGMENTS_1 = 0 +SEGMENTS_2 = 1 +SEGMENTS_4 = 2 +SEGMENTS_8 = 3 +SEGMENTS_16 = 4 +SEGMENTS_32 = 5 +SEGMENTS_64 = 6 +SEGMENTS_128 = 7 +CM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_RAM_SEL' +CM_LUT_RAM_SEL__enumvalues = { + 0: 'RAMA_ACCESS', + 1: 'RAMB_ACCESS', +} +RAMA_ACCESS = 0 +RAMB_ACCESS = 1 +CM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_COLOR_SEL' +CM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'BLUE_LUT', + 1: 'GREEN_LUT', + 2: 'RED_LUT', +} +BLUE_LUT = 0 +GREEN_LUT = 1 +RED_LUT = 2 +CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_DBG' +CM_LUT_READ_DBG__enumvalues = { + 0: 'DISABLE_DEBUG', + 1: 'ENABLE_DEBUG', +} +DISABLE_DEBUG = 0 +ENABLE_DEBUG = 1 +CM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_PENDING' +CM_PENDING__enumvalues = { + 0: 'CM_NOT_PENDING', + 1: 'CM_YES_PENDING', +} +CM_NOT_PENDING = 0 +CM_YES_PENDING = 1 +CM_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CM_POST_CSC_MODE_ENUM' +CM_POST_CSC_MODE_ENUM__enumvalues = { + 0: 'BYPASS_POST_CSC', + 1: 'COEF_POST_CSC', + 2: 'COEF_POST_CSC_B', +} +BYPASS_POST_CSC = 0 +COEF_POST_CSC = 1 +COEF_POST_CSC_B = 2 +CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_WRITE_BASE_ONLY' +CM_WRITE_BASE_ONLY__enumvalues = { + 0: 'WRITE_BOTH', + 1: 'WRITE_BASE_ONLY', +} +WRITE_BOTH = 0 +WRITE_BASE_ONLY = 1 +CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_CUR_SEL' +CRC_CUR_SEL__enumvalues = { + 0: 'CRC_CUR_0', + 1: 'CRC_CUR_1', +} +CRC_CUR_0 = 0 +CRC_CUR_1 = 1 +CRC_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_INTERLACE_SEL' +CRC_INTERLACE_SEL__enumvalues = { + 0: 'CRC_INTERLACE_0', + 1: 'CRC_INTERLACE_1', + 2: 'CRC_INTERLACE_2', + 3: 'CRC_INTERLACE_3', +} +CRC_INTERLACE_0 = 0 +CRC_INTERLACE_1 = 1 +CRC_INTERLACE_2 = 2 +CRC_INTERLACE_3 = 3 +CRC_INTERLACE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_CUR_SEL' +CRC_IN_CUR_SEL__enumvalues = { + 0: 'CRC_IN_CUR_0', + 1: 'CRC_IN_CUR_1', + 2: 'CRC_IN_CUR_2', + 3: 'CRC_IN_CUR_3', +} +CRC_IN_CUR_0 = 0 +CRC_IN_CUR_1 = 1 +CRC_IN_CUR_2 = 2 +CRC_IN_CUR_3 = 3 +CRC_IN_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_PIX_SEL' +CRC_IN_PIX_SEL__enumvalues = { + 0: 'CRC_IN_PIX_0', + 1: 'CRC_IN_PIX_1', + 2: 'CRC_IN_PIX_2', + 3: 'CRC_IN_PIX_3', + 4: 'CRC_IN_PIX_4', + 5: 'CRC_IN_PIX_5', + 6: 'CRC_IN_PIX_6', + 7: 'CRC_IN_PIX_7', +} +CRC_IN_PIX_0 = 0 +CRC_IN_PIX_1 = 1 +CRC_IN_PIX_2 = 2 +CRC_IN_PIX_3 = 3 +CRC_IN_PIX_4 = 4 +CRC_IN_PIX_5 = 5 +CRC_IN_PIX_6 = 6 +CRC_IN_PIX_7 = 7 +CRC_IN_PIX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_SRC_SEL' +CRC_SRC_SEL__enumvalues = { + 0: 'CRC_SRC_0', + 1: 'CRC_SRC_1', + 2: 'CRC_SRC_2', + 3: 'CRC_SRC_3', +} +CRC_SRC_0 = 0 +CRC_SRC_1 = 1 +CRC_SRC_2 = 2 +CRC_SRC_3 = 3 +CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_STEREO_SEL' +CRC_STEREO_SEL__enumvalues = { + 0: 'CRC_STEREO_0', + 1: 'CRC_STEREO_1', + 2: 'CRC_STEREO_2', + 3: 'CRC_STEREO_3', +} +CRC_STEREO_0 = 0 +CRC_STEREO_1 = 1 +CRC_STEREO_2 = 2 +CRC_STEREO_3 = 3 +CRC_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_SEL' +TEST_CLK_SEL__enumvalues = { + 0: 'TEST_CLK_SEL_0', + 1: 'TEST_CLK_SEL_1', + 2: 'TEST_CLK_SEL_2', + 3: 'TEST_CLK_SEL_3', + 4: 'TEST_CLK_SEL_4', + 5: 'TEST_CLK_SEL_5', + 6: 'TEST_CLK_SEL_6', + 7: 'TEST_CLK_SEL_7', +} +TEST_CLK_SEL_0 = 0 +TEST_CLK_SEL_1 = 1 +TEST_CLK_SEL_2 = 2 +TEST_CLK_SEL_3 = 3 +TEST_CLK_SEL_4 = 4 +TEST_CLK_SEL_5 = 5 +TEST_CLK_SEL_6 = 6 +TEST_CLK_SEL_7 = 7 +TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_ACTIVE' +PERFCOUNTER_ACTIVE__enumvalues = { + 0: 'PERFCOUNTER_IS_IDLE', + 1: 'PERFCOUNTER_IS_ACTIVE', +} +PERFCOUNTER_IS_IDLE = 0 +PERFCOUNTER_IS_ACTIVE = 1 +PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT0_STATE' +PERFCOUNTER_CNT0_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT0_STATE_RESET', + 1: 'PERFCOUNTER_CNT0_STATE_START', + 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT0_STATE_HW', +} +PERFCOUNTER_CNT0_STATE_RESET = 0 +PERFCOUNTER_CNT0_STATE_START = 1 +PERFCOUNTER_CNT0_STATE_FREEZE = 2 +PERFCOUNTER_CNT0_STATE_HW = 3 +PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT1_STATE' +PERFCOUNTER_CNT1_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT1_STATE_RESET', + 1: 'PERFCOUNTER_CNT1_STATE_START', + 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT1_STATE_HW', +} +PERFCOUNTER_CNT1_STATE_RESET = 0 +PERFCOUNTER_CNT1_STATE_START = 1 +PERFCOUNTER_CNT1_STATE_FREEZE = 2 +PERFCOUNTER_CNT1_STATE_HW = 3 +PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT2_STATE' +PERFCOUNTER_CNT2_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT2_STATE_RESET', + 1: 'PERFCOUNTER_CNT2_STATE_START', + 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT2_STATE_HW', +} +PERFCOUNTER_CNT2_STATE_RESET = 0 +PERFCOUNTER_CNT2_STATE_START = 1 +PERFCOUNTER_CNT2_STATE_FREEZE = 2 +PERFCOUNTER_CNT2_STATE_HW = 3 +PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT3_STATE' +PERFCOUNTER_CNT3_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT3_STATE_RESET', + 1: 'PERFCOUNTER_CNT3_STATE_START', + 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT3_STATE_HW', +} +PERFCOUNTER_CNT3_STATE_RESET = 0 +PERFCOUNTER_CNT3_STATE_START = 1 +PERFCOUNTER_CNT3_STATE_FREEZE = 2 +PERFCOUNTER_CNT3_STATE_HW = 3 +PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT4_STATE' +PERFCOUNTER_CNT4_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT4_STATE_RESET', + 1: 'PERFCOUNTER_CNT4_STATE_START', + 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT4_STATE_HW', +} +PERFCOUNTER_CNT4_STATE_RESET = 0 +PERFCOUNTER_CNT4_STATE_START = 1 +PERFCOUNTER_CNT4_STATE_FREEZE = 2 +PERFCOUNTER_CNT4_STATE_HW = 3 +PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT5_STATE' +PERFCOUNTER_CNT5_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT5_STATE_RESET', + 1: 'PERFCOUNTER_CNT5_STATE_START', + 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT5_STATE_HW', +} +PERFCOUNTER_CNT5_STATE_RESET = 0 +PERFCOUNTER_CNT5_STATE_START = 1 +PERFCOUNTER_CNT5_STATE_FREEZE = 2 +PERFCOUNTER_CNT5_STATE_HW = 3 +PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT6_STATE' +PERFCOUNTER_CNT6_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT6_STATE_RESET', + 1: 'PERFCOUNTER_CNT6_STATE_START', + 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT6_STATE_HW', +} +PERFCOUNTER_CNT6_STATE_RESET = 0 +PERFCOUNTER_CNT6_STATE_START = 1 +PERFCOUNTER_CNT6_STATE_FREEZE = 2 +PERFCOUNTER_CNT6_STATE_HW = 3 +PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT7_STATE' +PERFCOUNTER_CNT7_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT7_STATE_RESET', + 1: 'PERFCOUNTER_CNT7_STATE_START', + 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT7_STATE_HW', +} +PERFCOUNTER_CNT7_STATE_RESET = 0 +PERFCOUNTER_CNT7_STATE_START = 1 +PERFCOUNTER_CNT7_STATE_FREEZE = 2 +PERFCOUNTER_CNT7_STATE_HW = 3 +PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTL_SEL' +PERFCOUNTER_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_CNTL_SEL_0', + 1: 'PERFCOUNTER_CNTL_SEL_1', + 2: 'PERFCOUNTER_CNTL_SEL_2', + 3: 'PERFCOUNTER_CNTL_SEL_3', + 4: 'PERFCOUNTER_CNTL_SEL_4', + 5: 'PERFCOUNTER_CNTL_SEL_5', + 6: 'PERFCOUNTER_CNTL_SEL_6', + 7: 'PERFCOUNTER_CNTL_SEL_7', +} +PERFCOUNTER_CNTL_SEL_0 = 0 +PERFCOUNTER_CNTL_SEL_1 = 1 +PERFCOUNTER_CNTL_SEL_2 = 2 +PERFCOUNTER_CNTL_SEL_3 = 3 +PERFCOUNTER_CNTL_SEL_4 = 4 +PERFCOUNTER_CNTL_SEL_5 = 5 +PERFCOUNTER_CNTL_SEL_6 = 6 +PERFCOUNTER_CNTL_SEL_7 = 7 +PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' +PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { + 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', + 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', +} +PERFCOUNTER_CNTOFF_START_ENABLE = 0 +PERFCOUNTER_CNTOFF_START_DISABLE = 1 +PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' +PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { + 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', +} +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 +PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CVALUE_SEL' +PERFCOUNTER_CVALUE_SEL__enumvalues = { + 0: 'PERFCOUNTER_CVALUE_SEL_47_0', + 1: 'PERFCOUNTER_CVALUE_SEL_15_0', + 2: 'PERFCOUNTER_CVALUE_SEL_31_16', + 3: 'PERFCOUNTER_CVALUE_SEL_47_32', + 4: 'PERFCOUNTER_CVALUE_SEL_11_0', + 5: 'PERFCOUNTER_CVALUE_SEL_23_12', + 6: 'PERFCOUNTER_CVALUE_SEL_35_24', + 7: 'PERFCOUNTER_CVALUE_SEL_47_36', +} +PERFCOUNTER_CVALUE_SEL_47_0 = 0 +PERFCOUNTER_CVALUE_SEL_15_0 = 1 +PERFCOUNTER_CVALUE_SEL_31_16 = 2 +PERFCOUNTER_CVALUE_SEL_47_32 = 3 +PERFCOUNTER_CVALUE_SEL_11_0 = 4 +PERFCOUNTER_CVALUE_SEL_23_12 = 5 +PERFCOUNTER_CVALUE_SEL_35_24 = 6 +PERFCOUNTER_CVALUE_SEL_47_36 = 7 +PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' +PERFCOUNTER_HW_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', + 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', +} +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 +PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' +PERFCOUNTER_HW_STOP1_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP1_0', + 1: 'PERFCOUNTER_HW_STOP1_1', +} +PERFCOUNTER_HW_STOP1_0 = 0 +PERFCOUNTER_HW_STOP1_1 = 1 +PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' +PERFCOUNTER_HW_STOP2_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP2_0', + 1: 'PERFCOUNTER_HW_STOP2_1', +} +PERFCOUNTER_HW_STOP2_0 = 0 +PERFCOUNTER_HW_STOP2_1 = 1 +PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INC_MODE' +PERFCOUNTER_INC_MODE__enumvalues = { + 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', + 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', + 2: 'PERFCOUNTER_INC_MODE_LSB', + 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', + 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', +} +PERFCOUNTER_INC_MODE_MULTI_BIT = 0 +PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 +PERFCOUNTER_INC_MODE_LSB = 2 +PERFCOUNTER_INC_MODE_POS_EDGE = 3 +PERFCOUNTER_INC_MODE_NEG_EDGE = 4 +PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_EN' +PERFCOUNTER_INT_EN__enumvalues = { + 0: 'PERFCOUNTER_INT_DISABLE', + 1: 'PERFCOUNTER_INT_ENABLE', +} +PERFCOUNTER_INT_DISABLE = 0 +PERFCOUNTER_INT_ENABLE = 1 +PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_TYPE' +PERFCOUNTER_INT_TYPE__enumvalues = { + 0: 'PERFCOUNTER_INT_TYPE_LEVEL', + 1: 'PERFCOUNTER_INT_TYPE_PULSE', +} +PERFCOUNTER_INT_TYPE_LEVEL = 0 +PERFCOUNTER_INT_TYPE_PULSE = 1 +PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_OFF_MASK' +PERFCOUNTER_OFF_MASK__enumvalues = { + 0: 'PERFCOUNTER_OFF_MASK_DISABLE', + 1: 'PERFCOUNTER_OFF_MASK_ENABLE', +} +PERFCOUNTER_OFF_MASK_DISABLE = 0 +PERFCOUNTER_OFF_MASK_ENABLE = 1 +PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RESTART_EN' +PERFCOUNTER_RESTART_EN__enumvalues = { + 0: 'PERFCOUNTER_RESTART_DISABLE', + 1: 'PERFCOUNTER_RESTART_ENABLE', +} +PERFCOUNTER_RESTART_DISABLE = 0 +PERFCOUNTER_RESTART_ENABLE = 1 +PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RUNEN_MODE' +PERFCOUNTER_RUNEN_MODE__enumvalues = { + 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', +} +PERFCOUNTER_RUNEN_MODE_LEVEL = 0 +PERFCOUNTER_RUNEN_MODE_EDGE = 1 +PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL0' +PERFCOUNTER_STATE_SEL0__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', +} +PERFCOUNTER_STATE_SEL0_GLOBAL = 0 +PERFCOUNTER_STATE_SEL0_LOCAL = 1 +PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL1' +PERFCOUNTER_STATE_SEL1__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', +} +PERFCOUNTER_STATE_SEL1_GLOBAL = 0 +PERFCOUNTER_STATE_SEL1_LOCAL = 1 +PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL2' +PERFCOUNTER_STATE_SEL2__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', +} +PERFCOUNTER_STATE_SEL2_GLOBAL = 0 +PERFCOUNTER_STATE_SEL2_LOCAL = 1 +PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL3' +PERFCOUNTER_STATE_SEL3__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', +} +PERFCOUNTER_STATE_SEL3_GLOBAL = 0 +PERFCOUNTER_STATE_SEL3_LOCAL = 1 +PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL4' +PERFCOUNTER_STATE_SEL4__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', +} +PERFCOUNTER_STATE_SEL4_GLOBAL = 0 +PERFCOUNTER_STATE_SEL4_LOCAL = 1 +PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL5' +PERFCOUNTER_STATE_SEL5__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', +} +PERFCOUNTER_STATE_SEL5_GLOBAL = 0 +PERFCOUNTER_STATE_SEL5_LOCAL = 1 +PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL6' +PERFCOUNTER_STATE_SEL6__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', +} +PERFCOUNTER_STATE_SEL6_GLOBAL = 0 +PERFCOUNTER_STATE_SEL6_LOCAL = 1 +PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL7' +PERFCOUNTER_STATE_SEL7__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', +} +PERFCOUNTER_STATE_SEL7_GLOBAL = 0 +PERFCOUNTER_STATE_SEL7_LOCAL = 1 +PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_AND_OR' +PERFMON_CNTOFF_AND_OR__enumvalues = { + 0: 'PERFMON_CNTOFF_OR', + 1: 'PERFMON_CNTOFF_AND', +} +PERFMON_CNTOFF_OR = 0 +PERFMON_CNTOFF_AND = 1 +PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_EN' +PERFMON_CNTOFF_INT_EN__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_DISABLE', + 1: 'PERFMON_CNTOFF_INT_ENABLE', +} +PERFMON_CNTOFF_INT_DISABLE = 0 +PERFMON_CNTOFF_INT_ENABLE = 1 +PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' +PERFMON_CNTOFF_INT_TYPE__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', + 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', +} +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 +PERFMON_CNTOFF_INT_TYPE_PULSE = 1 +PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_STATE' +PERFMON_STATE__enumvalues = { + 0: 'PERFMON_STATE_RESET', + 1: 'PERFMON_STATE_START', + 2: 'PERFMON_STATE_FREEZE', + 3: 'PERFMON_STATE_HW', +} +PERFMON_STATE_RESET = 0 +PERFMON_STATE_START = 1 +PERFMON_STATE_FREEZE = 2 +PERFMON_STATE_HW = 3 +PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'BIGK_FRAGMENT_SIZE' +BIGK_FRAGMENT_SIZE__enumvalues = { + 0: 'VM_PG_SIZE_4KB', + 1: 'VM_PG_SIZE_8KB', + 2: 'VM_PG_SIZE_16KB', + 3: 'VM_PG_SIZE_32KB', + 4: 'VM_PG_SIZE_64KB', + 5: 'VM_PG_SIZE_128KB', + 6: 'VM_PG_SIZE_256KB', + 7: 'VM_PG_SIZE_512KB', + 8: 'VM_PG_SIZE_1024KB', + 9: 'VM_PG_SIZE_2048KB', +} +VM_PG_SIZE_4KB = 0 +VM_PG_SIZE_8KB = 1 +VM_PG_SIZE_16KB = 2 +VM_PG_SIZE_32KB = 3 +VM_PG_SIZE_64KB = 4 +VM_PG_SIZE_128KB = 5 +VM_PG_SIZE_256KB = 6 +VM_PG_SIZE_512KB = 7 +VM_PG_SIZE_1024KB = 8 +VM_PG_SIZE_2048KB = 9 +BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CHUNK_SIZE' +CHUNK_SIZE__enumvalues = { + 0: 'CHUNK_SIZE_1KB', + 1: 'CHUNK_SIZE_2KB', + 2: 'CHUNK_SIZE_4KB', + 3: 'CHUNK_SIZE_8KB', + 4: 'CHUNK_SIZE_16KB', + 5: 'CHUNK_SIZE_32KB', + 6: 'CHUNK_SIZE_64KB', +} +CHUNK_SIZE_1KB = 0 +CHUNK_SIZE_2KB = 1 +CHUNK_SIZE_4KB = 2 +CHUNK_SIZE_8KB = 3 +CHUNK_SIZE_16KB = 4 +CHUNK_SIZE_32KB = 5 +CHUNK_SIZE_64KB = 6 +CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'COMPAT_LEVEL' +COMPAT_LEVEL__enumvalues = { + 0: 'ADDR_GEN_ZERO', + 1: 'ADDR_GEN_ONE', + 2: 'ADDR_GEN_TWO', + 3: 'ADDR_RESERVED', +} +ADDR_GEN_ZERO = 0 +ADDR_GEN_ONE = 1 +ADDR_GEN_TWO = 2 +ADDR_RESERVED = 3 +COMPAT_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPTE_GROUP_SIZE' +DPTE_GROUP_SIZE__enumvalues = { + 0: 'DPTE_GROUP_SIZE_64B', + 1: 'DPTE_GROUP_SIZE_128B', + 2: 'DPTE_GROUP_SIZE_256B', + 3: 'DPTE_GROUP_SIZE_512B', + 4: 'DPTE_GROUP_SIZE_1024B', + 5: 'DPTE_GROUP_SIZE_2048B', +} +DPTE_GROUP_SIZE_64B = 0 +DPTE_GROUP_SIZE_128B = 1 +DPTE_GROUP_SIZE_256B = 2 +DPTE_GROUP_SIZE_512B = 3 +DPTE_GROUP_SIZE_1024B = 4 +DPTE_GROUP_SIZE_2048B = 5 +DPTE_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME' +FORCE_ONE_ROW_FOR_FRAME__enumvalues = { + 0: 'FORCE_ONE_ROW_FOR_FRAME_0', + 1: 'FORCE_ONE_ROW_FOR_FRAME_1', +} +FORCE_ONE_ROW_FOR_FRAME_0 = 0 +FORCE_ONE_ROW_FOR_FRAME_1 = 1 +FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_BLANK_EN' +HUBP_BLANK_EN__enumvalues = { + 0: 'HUBP_BLANK_SW_DEASSERT', + 1: 'HUBP_BLANK_SW_ASSERT', +} +HUBP_BLANK_SW_DEASSERT = 0 +HUBP_BLANK_SW_ASSERT = 1 +HUBP_BLANK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_IN_BLANK' +HUBP_IN_BLANK__enumvalues = { + 0: 'HUBP_IN_ACTIVE', + 1: 'HUBP_IN_VBLANK', +} +HUBP_IN_ACTIVE = 0 +HUBP_IN_VBLANK = 1 +HUBP_IN_BLANK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' +HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { + 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', +} +HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 +HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 +HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 +HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 +HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' +HUBP_NO_OUTSTANDING_REQ__enumvalues = { + 0: 'OUTSTANDING_REQ', + 1: 'NO_OUTSTANDING_REQ', +} +OUTSTANDING_REQ = 0 +NO_OUTSTANDING_REQ = 1 +HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_SOFT_RESET' +HUBP_SOFT_RESET__enumvalues = { + 0: 'HUBP_SOFT_RESET_ON', + 1: 'HUBP_SOFT_RESET_OFF', +} +HUBP_SOFT_RESET_ON = 0 +HUBP_SOFT_RESET_OFF = 1 +HUBP_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_TTU_DISABLE' +HUBP_TTU_DISABLE__enumvalues = { + 0: 'HUBP_TTU_ENABLED', + 1: 'HUBP_TTU_DISABLED', +} +HUBP_TTU_ENABLED = 0 +HUBP_TTU_DISABLED = 1 +HUBP_TTU_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' +HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { + 0: 'VREADY_BEFORE_VSYNC', + 1: 'VREADY_AT_OR_AFTER_VSYNC', +} +VREADY_BEFORE_VSYNC = 0 +VREADY_AT_OR_AFTER_VSYNC = 1 +HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VTG_SEL' +HUBP_VTG_SEL__enumvalues = { + 0: 'VTG_SEL_0', + 1: 'VTG_SEL_1', + 2: 'VTG_SEL_2', + 3: 'VTG_SEL_3', + 4: 'VTG_SEL_4', + 5: 'VTG_SEL_5', +} +VTG_SEL_0 = 0 +VTG_SEL_1 = 1 +VTG_SEL_2 = 2 +VTG_SEL_3 = 3 +VTG_SEL_4 = 4 +VTG_SEL_5 = 5 +HUBP_VTG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'H_MIRROR_EN' +H_MIRROR_EN__enumvalues = { + 0: 'HW_MIRRORING_DISABLE', + 1: 'HW_MIRRORING_ENABLE', +} +HW_MIRRORING_DISABLE = 0 +HW_MIRRORING_ENABLE = 1 +H_MIRROR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LEGACY_PIPE_INTERLEAVE' +LEGACY_PIPE_INTERLEAVE__enumvalues = { + 0: 'LEGACY_PIPE_INTERLEAVE_256B', + 1: 'LEGACY_PIPE_INTERLEAVE_512B', +} +LEGACY_PIPE_INTERLEAVE_256B = 0 +LEGACY_PIPE_INTERLEAVE_512B = 1 +LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum + +# values for enumeration 'META_CHUNK_SIZE' +META_CHUNK_SIZE__enumvalues = { + 0: 'META_CHUNK_SIZE_1KB', + 1: 'META_CHUNK_SIZE_2KB', + 2: 'META_CHUNK_SIZE_4KB', + 3: 'META_CHUNK_SIZE_8KB', +} +META_CHUNK_SIZE_1KB = 0 +META_CHUNK_SIZE_2KB = 1 +META_CHUNK_SIZE_4KB = 2 +META_CHUNK_SIZE_8KB = 3 +META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'META_LINEAR' +META_LINEAR__enumvalues = { + 0: 'META_SURF_TILED', + 1: 'META_SURF_LINEAR', +} +META_SURF_TILED = 0 +META_SURF_LINEAR = 1 +META_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_CHUNK_SIZE' +MIN_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_CHUNK_SIZE', + 1: 'MIN_CHUNK_SIZE_256B', + 2: 'MIN_CHUNK_SIZE_512B', + 3: 'MIN_CHUNK_SIZE_1024B', +} +NO_MIN_CHUNK_SIZE = 0 +MIN_CHUNK_SIZE_256B = 1 +MIN_CHUNK_SIZE_512B = 2 +MIN_CHUNK_SIZE_1024B = 3 +MIN_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_META_CHUNK_SIZE' +MIN_META_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_META_CHUNK_SIZE', + 1: 'MIN_META_CHUNK_SIZE_64B', + 2: 'MIN_META_CHUNK_SIZE_128B', + 3: 'MIN_META_CHUNK_SIZE_256B', +} +NO_MIN_META_CHUNK_SIZE = 0 +MIN_META_CHUNK_SIZE_64B = 1 +MIN_META_CHUNK_SIZE_128B = 2 +MIN_META_CHUNK_SIZE_256B = 3 +MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_ALIGNED' +PIPE_ALIGNED__enumvalues = { + 0: 'PIPE_UNALIGNED_SURF', + 1: 'PIPE_ALIGNED_SURF', +} +PIPE_UNALIGNED_SURF = 0 +PIPE_ALIGNED_SURF = 1 +PIPE_ALIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_BUFFER_MODE' +PTE_BUFFER_MODE__enumvalues = { + 0: 'PTE_BUFFER_MODE_0', + 1: 'PTE_BUFFER_MODE_1', +} +PTE_BUFFER_MODE_0 = 0 +PTE_BUFFER_MODE_1 = 1 +PTE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' +PTE_ROW_HEIGHT_LINEAR__enumvalues = { + 0: 'PTE_ROW_HEIGHT_LINEAR_8L', + 1: 'PTE_ROW_HEIGHT_LINEAR_16L', + 2: 'PTE_ROW_HEIGHT_LINEAR_32L', + 3: 'PTE_ROW_HEIGHT_LINEAR_64L', + 4: 'PTE_ROW_HEIGHT_LINEAR_128L', + 5: 'PTE_ROW_HEIGHT_LINEAR_256L', + 6: 'PTE_ROW_HEIGHT_LINEAR_512L', + 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', +} +PTE_ROW_HEIGHT_LINEAR_8L = 0 +PTE_ROW_HEIGHT_LINEAR_16L = 1 +PTE_ROW_HEIGHT_LINEAR_32L = 2 +PTE_ROW_HEIGHT_LINEAR_64L = 3 +PTE_ROW_HEIGHT_LINEAR_128L = 4 +PTE_ROW_HEIGHT_LINEAR_256L = 5 +PTE_ROW_HEIGHT_LINEAR_512L = 6 +PTE_ROW_HEIGHT_LINEAR_1024L = 7 +PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'ROTATION_ANGLE' +ROTATION_ANGLE__enumvalues = { + 0: 'ROTATE_0_DEGREES', + 1: 'ROTATE_90_DEGREES', + 2: 'ROTATE_180_DEGREES', + 3: 'ROTATE_270_DEGREES', +} +ROTATE_0_DEGREES = 0 +ROTATE_90_DEGREES = 1 +ROTATE_180_DEGREES = 2 +ROTATE_270_DEGREES = 3 +ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'SWATH_HEIGHT' +SWATH_HEIGHT__enumvalues = { + 0: 'SWATH_HEIGHT_1L', + 1: 'SWATH_HEIGHT_2L', + 2: 'SWATH_HEIGHT_4L', + 3: 'SWATH_HEIGHT_8L', + 4: 'SWATH_HEIGHT_16L', +} +SWATH_HEIGHT_1L = 0 +SWATH_HEIGHT_2L = 1 +SWATH_HEIGHT_4L = 2 +SWATH_HEIGHT_8L = 3 +SWATH_HEIGHT_16L = 4 +SWATH_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_CURSOR' +USE_MALL_FOR_CURSOR__enumvalues = { + 0: 'USE_MALL_FOR_CURSOR_0', + 1: 'USE_MALL_FOR_CURSOR_1', +} +USE_MALL_FOR_CURSOR_0 = 0 +USE_MALL_FOR_CURSOR_1 = 1 +USE_MALL_FOR_CURSOR = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_PSTATE_CHANGE' +USE_MALL_FOR_PSTATE_CHANGE__enumvalues = { + 0: 'USE_MALL_FOR_PSTATE_CHANGE_0', + 1: 'USE_MALL_FOR_PSTATE_CHANGE_1', +} +USE_MALL_FOR_PSTATE_CHANGE_0 = 0 +USE_MALL_FOR_PSTATE_CHANGE_1 = 1 +USE_MALL_FOR_PSTATE_CHANGE = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_STATIC_SCREEN' +USE_MALL_FOR_STATIC_SCREEN__enumvalues = { + 0: 'USE_MALL_FOR_STATIC_SCREEN_0', + 1: 'USE_MALL_FOR_STATIC_SCREEN_1', +} +USE_MALL_FOR_STATIC_SCREEN_0 = 0 +USE_MALL_FOR_STATIC_SCREEN_1 = 1 +USE_MALL_FOR_STATIC_SCREEN = ctypes.c_uint32 # enum + +# values for enumeration 'VMPG_SIZE' +VMPG_SIZE__enumvalues = { + 0: 'VMPG_SIZE_4KB', + 1: 'VMPG_SIZE_64KB', +} +VMPG_SIZE_4KB = 0 +VMPG_SIZE_64KB = 1 +VMPG_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VM_GROUP_SIZE' +VM_GROUP_SIZE__enumvalues = { + 0: 'VM_GROUP_SIZE_64B', + 1: 'VM_GROUP_SIZE_128B', + 2: 'VM_GROUP_SIZE_256B', + 3: 'VM_GROUP_SIZE_512B', + 4: 'VM_GROUP_SIZE_1024B', + 5: 'VM_GROUP_SIZE_2048B', +} +VM_GROUP_SIZE_64B = 0 +VM_GROUP_SIZE_128B = 1 +VM_GROUP_SIZE_256B = 2 +VM_GROUP_SIZE_512B = 3 +VM_GROUP_SIZE_1024B = 4 +VM_GROUP_SIZE_2048B = 5 +VM_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_MIN_FREE_ENTRIES' +DFQ_MIN_FREE_ENTRIES__enumvalues = { + 0: 'DFQ_MIN_FREE_ENTRIES_0', + 1: 'DFQ_MIN_FREE_ENTRIES_1', + 2: 'DFQ_MIN_FREE_ENTRIES_2', + 3: 'DFQ_MIN_FREE_ENTRIES_3', + 4: 'DFQ_MIN_FREE_ENTRIES_4', + 5: 'DFQ_MIN_FREE_ENTRIES_5', + 6: 'DFQ_MIN_FREE_ENTRIES_6', + 7: 'DFQ_MIN_FREE_ENTRIES_7', +} +DFQ_MIN_FREE_ENTRIES_0 = 0 +DFQ_MIN_FREE_ENTRIES_1 = 1 +DFQ_MIN_FREE_ENTRIES_2 = 2 +DFQ_MIN_FREE_ENTRIES_3 = 3 +DFQ_MIN_FREE_ENTRIES_4 = 4 +DFQ_MIN_FREE_ENTRIES_5 = 5 +DFQ_MIN_FREE_ENTRIES_6 = 6 +DFQ_MIN_FREE_ENTRIES_7 = 7 +DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_NUM_ENTRIES' +DFQ_NUM_ENTRIES__enumvalues = { + 0: 'DFQ_NUM_ENTRIES_0', + 1: 'DFQ_NUM_ENTRIES_1', + 2: 'DFQ_NUM_ENTRIES_2', + 3: 'DFQ_NUM_ENTRIES_3', + 4: 'DFQ_NUM_ENTRIES_4', + 5: 'DFQ_NUM_ENTRIES_5', + 6: 'DFQ_NUM_ENTRIES_6', + 7: 'DFQ_NUM_ENTRIES_7', + 8: 'DFQ_NUM_ENTRIES_8', +} +DFQ_NUM_ENTRIES_0 = 0 +DFQ_NUM_ENTRIES_1 = 1 +DFQ_NUM_ENTRIES_2 = 2 +DFQ_NUM_ENTRIES_3 = 3 +DFQ_NUM_ENTRIES_4 = 4 +DFQ_NUM_ENTRIES_5 = 5 +DFQ_NUM_ENTRIES_6 = 6 +DFQ_NUM_ENTRIES_7 = 7 +DFQ_NUM_ENTRIES_8 = 8 +DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_SIZE' +DFQ_SIZE__enumvalues = { + 0: 'DFQ_SIZE_0', + 1: 'DFQ_SIZE_1', + 2: 'DFQ_SIZE_2', + 3: 'DFQ_SIZE_3', + 4: 'DFQ_SIZE_4', + 5: 'DFQ_SIZE_5', + 6: 'DFQ_SIZE_6', + 7: 'DFQ_SIZE_7', +} +DFQ_SIZE_0 = 0 +DFQ_SIZE_1 = 1 +DFQ_SIZE_2 = 2 +DFQ_SIZE_3 = 3 +DFQ_SIZE_4 = 4 +DFQ_SIZE_5 = 5 +DFQ_SIZE_6 = 6 +DFQ_SIZE_7 = 7 +DFQ_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_VM_DONE' +DMDATA_VM_DONE__enumvalues = { + 0: 'DMDATA_VM_IS_NOT_DONE', + 1: 'DMDATA_VM_IS_DONE', +} +DMDATA_VM_IS_NOT_DONE = 0 +DMDATA_VM_IS_DONE = 1 +DMDATA_VM_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'EXPANSION_MODE' +EXPANSION_MODE__enumvalues = { + 0: 'EXPANSION_MODE_ZERO', + 1: 'EXPANSION_MODE_CONSERVATIVE', + 2: 'EXPANSION_MODE_OPTIMAL', +} +EXPANSION_MODE_ZERO = 0 +EXPANSION_MODE_CONSERVATIVE = 1 +EXPANSION_MODE_OPTIMAL = 2 +EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FLIP_RATE' +FLIP_RATE__enumvalues = { + 0: 'FLIP_RATE_0', + 1: 'FLIP_RATE_1', + 2: 'FLIP_RATE_2', + 3: 'FLIP_RATE_3', + 4: 'FLIP_RATE_4', + 5: 'FLIP_RATE_5', + 6: 'FLIP_RATE_6', + 7: 'FLIP_RATE_7', +} +FLIP_RATE_0 = 0 +FLIP_RATE_1 = 1 +FLIP_RATE_2 = 2 +FLIP_RATE_3 = 3 +FLIP_RATE_4 = 4 +FLIP_RATE_5 = 5 +FLIP_RATE_6 = 6 +FLIP_RATE_7 = 7 +FLIP_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'INT_MASK' +INT_MASK__enumvalues = { + 0: 'INT_DISABLED', + 1: 'INT_ENABLED', +} +INT_DISABLED = 0 +INT_ENABLED = 1 +INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_IN_FLUSH_URGENT' +PIPE_IN_FLUSH_URGENT__enumvalues = { + 0: 'PIPE_IN_FLUSH_URGENT_ENABLE', + 1: 'PIPE_IN_FLUSH_URGENT_DISABLE', +} +PIPE_IN_FLUSH_URGENT_ENABLE = 0 +PIPE_IN_FLUSH_URGENT_DISABLE = 1 +PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'PRQ_MRQ_FLUSH_URGENT' +PRQ_MRQ_FLUSH_URGENT__enumvalues = { + 0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE', + 1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE', +} +PRQ_MRQ_FLUSH_URGENT_ENABLE = 0 +PRQ_MRQ_FLUSH_URGENT_DISABLE = 1 +PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'ROW_TTU_MODE' +ROW_TTU_MODE__enumvalues = { + 0: 'END_OF_ROW_MODE', + 1: 'WATERMARK_MODE', +} +END_OF_ROW_MODE = 0 +WATERMARK_MODE = 1 +ROW_TTU_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC' +SURFACE_DCC__enumvalues = { + 0: 'SURFACE_IS_NOT_DCC', + 1: 'SURFACE_IS_DCC', +} +SURFACE_IS_NOT_DCC = 0 +SURFACE_IS_DCC = 1 +SURFACE_DCC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_128B' +SURFACE_DCC_IND_128B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_128B', + 1: 'SURFACE_DCC_IS_IND_128B', +} +SURFACE_DCC_IS_NOT_IND_128B = 0 +SURFACE_DCC_IS_IND_128B = 1 +SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_64B' +SURFACE_DCC_IND_64B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_64B', + 1: 'SURFACE_DCC_IS_IND_64B', +} +SURFACE_DCC_IS_NOT_IND_64B = 0 +SURFACE_DCC_IS_IND_64B = 1 +SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_BLK' +SURFACE_DCC_IND_BLK__enumvalues = { + 0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', + 1: 'SURFACE_DCC_BLOCK_IS_IND_64B', + 2: 'SURFACE_DCC_BLOCK_IS_IND_128B', + 3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', +} +SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0 +SURFACE_DCC_BLOCK_IS_IND_64B = 1 +SURFACE_DCC_BLOCK_IS_IND_128B = 2 +SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3 +SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' +SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', + 1: 'SURFACE_FLIP_AWAY_INT_PULSE', +} +SURFACE_FLIP_AWAY_INT_LEVEL = 0 +SURFACE_FLIP_AWAY_INT_PULSE = 1 +SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE' +SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = { + 0: 'SURFACE_FLIP_EXEC_NORMAL_MODE', + 1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', +} +SURFACE_FLIP_EXEC_NORMAL_MODE = 0 +SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1 +SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_INT_TYPE' +SURFACE_FLIP_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_INT_LEVEL', + 1: 'SURFACE_FLIP_INT_PULSE', +} +SURFACE_FLIP_INT_LEVEL = 0 +SURFACE_FLIP_INT_PULSE = 1 +SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' +SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { + 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', +} +SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 +SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 +SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' +SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { + 0: 'FLIP_ANY_FRAME', + 1: 'FLIP_LEFT_EYE', + 2: 'FLIP_RIGHT_EYE', + 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', +} +FLIP_ANY_FRAME = 0 +FLIP_LEFT_EYE = 1 +FLIP_RIGHT_EYE = 2 +SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 +SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' +SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', +} +SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 +SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 +SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' +SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', +} +SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 +SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 +SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_TYPE' +SURFACE_FLIP_TYPE__enumvalues = { + 0: 'SURFACE_V_FLIP', + 1: 'SURFACE_I_FLIP', +} +SURFACE_V_FLIP = 0 +SURFACE_I_FLIP = 1 +SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' +SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { + 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', + 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', +} +SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 +SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 +SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 +SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 +SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 +SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 +SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 +SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 +SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 +SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 +SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 +SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 +SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 +SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 +SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 +SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 +SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' +SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { + 0: 'SURFACE_INUSE_IS_LATCHED', + 1: 'SURFACE_INUSE_IS_NOT_LATCHED', +} +SURFACE_INUSE_IS_LATCHED = 0 +SURFACE_INUSE_IS_NOT_LATCHED = 1 +SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_TMZ' +SURFACE_TMZ__enumvalues = { + 0: 'SURFACE_IS_NOT_TMZ', + 1: 'SURFACE_IS_TMZ', +} +SURFACE_IS_NOT_TMZ = 0 +SURFACE_IS_TMZ = 1 +SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_UPDATE_LOCK' +SURFACE_UPDATE_LOCK__enumvalues = { + 0: 'SURFACE_UPDATE_IS_UNLOCKED', + 1: 'SURFACE_UPDATE_IS_LOCKED', +} +SURFACE_UPDATE_IS_UNLOCKED = 0 +SURFACE_UPDATE_IS_LOCKED = 1 +SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_ALPHA' +CROSSBAR_FOR_ALPHA__enumvalues = { + 0: 'ALPHA_DATA_ONTO_ALPHA_PORT', + 1: 'Y_G_DATA_ONTO_ALPHA_PORT', + 2: 'CB_B_DATA_ONTO_ALPHA_PORT', + 3: 'CR_R_DATA_ONTO_ALPHA_PORT', +} +ALPHA_DATA_ONTO_ALPHA_PORT = 0 +Y_G_DATA_ONTO_ALPHA_PORT = 1 +CB_B_DATA_ONTO_ALPHA_PORT = 2 +CR_R_DATA_ONTO_ALPHA_PORT = 3 +CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CB_B' +CROSSBAR_FOR_CB_B__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CB_B_PORT', + 1: 'Y_G_DATA_ONTO_CB_B_PORT', + 2: 'CB_B_DATA_ONTO_CB_B_PORT', + 3: 'CR_R_DATA_ONTO_CB_B_PORT', +} +ALPHA_DATA_ONTO_CB_B_PORT = 0 +Y_G_DATA_ONTO_CB_B_PORT = 1 +CB_B_DATA_ONTO_CB_B_PORT = 2 +CR_R_DATA_ONTO_CB_B_PORT = 3 +CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CR_R' +CROSSBAR_FOR_CR_R__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CR_R_PORT', + 1: 'Y_G_DATA_ONTO_CR_R_PORT', + 2: 'CB_B_DATA_ONTO_CR_R_PORT', + 3: 'CR_R_DATA_ONTO_CR_R_PORT', +} +ALPHA_DATA_ONTO_CR_R_PORT = 0 +Y_G_DATA_ONTO_CR_R_PORT = 1 +CB_B_DATA_ONTO_CR_R_PORT = 2 +CR_R_DATA_ONTO_CR_R_PORT = 3 +CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_Y_G' +CROSSBAR_FOR_Y_G__enumvalues = { + 0: 'ALPHA_DATA_ONTO_Y_G_PORT', + 1: 'Y_G_DATA_ONTO_Y_G_PORT', + 2: 'CB_B_DATA_ONTO_Y_G_PORT', + 3: 'CR_R_DATA_ONTO_Y_G_PORT', +} +ALPHA_DATA_ONTO_Y_G_PORT = 0 +Y_G_DATA_ONTO_Y_G_PORT = 1 +CB_B_DATA_ONTO_Y_G_PORT = 2 +CR_R_DATA_ONTO_Y_G_PORT = 3 +CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum + +# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' +DETILE_BUFFER_PACKER_ENABLE__enumvalues = { + 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', + 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', +} +DETILE_BUFFER_PACKER_IS_DISABLE = 0 +DETILE_BUFFER_PACKER_IS_ENABLE = 1 +DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_MODE' +MEM_PWR_DIS_MODE__enumvalues = { + 0: 'MEM_POWER_DIS_MODE_ENABLE', + 1: 'MEM_POWER_DIS_MODE_DISABLE', +} +MEM_POWER_DIS_MODE_ENABLE = 0 +MEM_POWER_DIS_MODE_DISABLE = 1 +MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_MODE' +MEM_PWR_FORCE_MODE__enumvalues = { + 0: 'MEM_POWER_FORCE_MODE_OFF', + 1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', + 2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN', +} +MEM_POWER_FORCE_MODE_OFF = 0 +MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1 +MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2 +MEM_POWER_FORCE_MODE_SHUT_DOWN = 3 +MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_STATUS' +MEM_PWR_STATUS__enumvalues = { + 0: 'MEM_POWER_STATUS_ON', + 1: 'MEM_POWER_STATUS_LIGHT_SLEEP', + 2: 'MEM_POWER_STATUS_DEEP_SLEEP', + 3: 'MEM_POWER_STATUS_SHUT_DOWN', +} +MEM_POWER_STATUS_ON = 0 +MEM_POWER_STATUS_LIGHT_SLEEP = 1 +MEM_POWER_STATUS_DEEP_SLEEP = 2 +MEM_POWER_STATUS_SHUT_DOWN = 3 +MEM_PWR_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_MASK_MODE' +PIPE_INT_MASK_MODE__enumvalues = { + 0: 'PIPE_INT_MASK_MODE_DISABLE', + 1: 'PIPE_INT_MASK_MODE_ENABLE', +} +PIPE_INT_MASK_MODE_DISABLE = 0 +PIPE_INT_MASK_MODE_ENABLE = 1 +PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_TYPE_MODE' +PIPE_INT_TYPE_MODE__enumvalues = { + 0: 'PIPE_INT_TYPE_MODE_DISABLE', + 1: 'PIPE_INT_TYPE_MODE_ENABLE', +} +PIPE_INT_TYPE_MODE_DISABLE = 0 +PIPE_INT_TYPE_MODE_ENABLE = 1 +PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', +} +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' +CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_2X_MAGNIFY' +CURSOR_2X_MAGNIFY__enumvalues = { + 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', + 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', +} +CURSOR_2X_MAGNIFY_IS_DISABLE = 0 +CURSOR_2X_MAGNIFY_IS_ENABLE = 1 +CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_ENABLE' +CURSOR_ENABLE__enumvalues = { + 0: 'CURSOR_IS_DISABLE', + 1: 'CURSOR_IS_ENABLE', +} +CURSOR_IS_DISABLE = 0 +CURSOR_IS_ENABLE = 1 +CURSOR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_LINES_PER_CHUNK' +CURSOR_LINES_PER_CHUNK__enumvalues = { + 0: 'CURSOR_LINE_PER_CHUNK_1', + 1: 'CURSOR_LINE_PER_CHUNK_2', + 2: 'CURSOR_LINE_PER_CHUNK_4', + 3: 'CURSOR_LINE_PER_CHUNK_8', + 4: 'CURSOR_LINE_PER_CHUNK_16', +} +CURSOR_LINE_PER_CHUNK_1 = 0 +CURSOR_LINE_PER_CHUNK_2 = 1 +CURSOR_LINE_PER_CHUNK_4 = 2 +CURSOR_LINE_PER_CHUNK_8 = 3 +CURSOR_LINE_PER_CHUNK_16 = 4 +CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_MODE' +CURSOR_MODE__enumvalues = { + 0: 'CURSOR_MONO_2BIT', + 1: 'CURSOR_COLOR_24BIT_1BIT_AND', + 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', + 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', +} +CURSOR_MONO_2BIT = 0 +CURSOR_COLOR_24BIT_1BIT_AND = 1 +CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +CURSOR_COLOR_64BIT_FP_PREMULT = 4 +CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 +CURSOR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' +CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', +} +CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 +CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 +CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' +CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', +} +CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 +CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 +CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PITCH' +CURSOR_PITCH__enumvalues = { + 0: 'CURSOR_PITCH_64_PIXELS', + 1: 'CURSOR_PITCH_128_PIXELS', + 2: 'CURSOR_PITCH_256_PIXELS', +} +CURSOR_PITCH_64_PIXELS = 0 +CURSOR_PITCH_128_PIXELS = 1 +CURSOR_PITCH_256_PIXELS = 2 +CURSOR_PITCH = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_REQ_MODE' +CURSOR_REQ_MODE__enumvalues = { + 0: 'CURSOR_REQUEST_NORMALLY', + 1: 'CURSOR_REQUEST_EARLY', +} +CURSOR_REQUEST_NORMALLY = 0 +CURSOR_REQUEST_EARLY = 1 +CURSOR_REQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SNOOP' +CURSOR_SNOOP__enumvalues = { + 0: 'CURSOR_IS_NOT_SNOOP', + 1: 'CURSOR_IS_SNOOP', +} +CURSOR_IS_NOT_SNOOP = 0 +CURSOR_IS_SNOOP = 1 +CURSOR_SNOOP = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_STEREO_EN' +CURSOR_STEREO_EN__enumvalues = { + 0: 'CURSOR_STEREO_IS_DISABLED', + 1: 'CURSOR_STEREO_IS_ENABLED', +} +CURSOR_STEREO_IS_DISABLED = 0 +CURSOR_STEREO_IS_ENABLED = 1 +CURSOR_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SURFACE_TMZ' +CURSOR_SURFACE_TMZ__enumvalues = { + 0: 'CURSOR_SURFACE_IS_NOT_TMZ', + 1: 'CURSOR_SURFACE_IS_TMZ', +} +CURSOR_SURFACE_IS_NOT_TMZ = 0 +CURSOR_SURFACE_IS_TMZ = 1 +CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SYSTEM' +CURSOR_SYSTEM__enumvalues = { + 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', + 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', +} +CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 +CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 +CURSOR_SYSTEM = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { + 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', +} +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_DONE' +DMDATA_DONE__enumvalues = { + 0: 'DMDATA_NOT_SENT_TO_DIG', + 1: 'DMDATA_SENT_TO_DIG', +} +DMDATA_NOT_SENT_TO_DIG = 0 +DMDATA_SENT_TO_DIG = 1 +DMDATA_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_MODE' +DMDATA_MODE__enumvalues = { + 0: 'DMDATA_SOFTWARE_UPDATE_MODE', + 1: 'DMDATA_HARDWARE_UPDATE_MODE', +} +DMDATA_SOFTWARE_UPDATE_MODE = 0 +DMDATA_HARDWARE_UPDATE_MODE = 1 +DMDATA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_QOS_MODE' +DMDATA_QOS_MODE__enumvalues = { + 0: 'DMDATA_QOS_LEVEL_FROM_TTU', + 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', +} +DMDATA_QOS_LEVEL_FROM_TTU = 0 +DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 +DMDATA_QOS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_REPEAT' +DMDATA_REPEAT__enumvalues = { + 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', + 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', +} +DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 +DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 +DMDATA_REPEAT = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW' +DMDATA_UNDERFLOW__enumvalues = { + 0: 'DMDATA_NOT_UNDERFLOW', + 1: 'DMDATA_UNDERFLOWED', +} +DMDATA_NOT_UNDERFLOW = 0 +DMDATA_UNDERFLOWED = 1 +DMDATA_UNDERFLOW = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' +DMDATA_UNDERFLOW_CLEAR__enumvalues = { + 0: 'DMDATA_DONT_CLEAR', + 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', +} +DMDATA_DONT_CLEAR = 0 +DMDATA_CLEAR_UNDERFLOW_STATUS = 1 +DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UPDATED' +DMDATA_UPDATED__enumvalues = { + 0: 'DMDATA_NOT_UPDATED', + 1: 'DMDATA_WAS_UPDATED', +} +DMDATA_NOT_UPDATED = 0 +DMDATA_WAS_UPDATED = 1 +DMDATA_UPDATED = ctypes.c_uint32 # enum + +# values for enumeration 'RESPONSE_STATUS' +RESPONSE_STATUS__enumvalues = { + 0: 'OKAY', + 1: 'EXOKAY', + 2: 'SLVERR', + 3: 'DECERR', + 4: 'EARLY', + 5: 'OKAY_NODATA', + 6: 'PROTVIOL', + 7: 'TRANSERR', + 8: 'CMPTO', + 12: 'CRS', +} +OKAY = 0 +EXOKAY = 1 +SLVERR = 2 +DECERR = 3 +EARLY = 4 +OKAY_NODATA = 5 +PROTVIOL = 6 +TRANSERR = 7 +CMPTO = 8 +CRS = 12 +RESPONSE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE' +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE' +DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', +} +DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0 +DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1 +DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_MODE' +DCHUBBUB_MEM_PWR_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_MODE_OFF', + 1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', +} +DCHUBBUB_MEM_POWER_MODE_OFF = 0 +DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1 +DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2 +DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3 +DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' +MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' +MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { + 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', + 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', + 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', +} +MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 +MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 +MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 +MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 +MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN' +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' +MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { + 0: 'MPC_CRC_INTERLACE_MODE_TOP', + 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', + 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', +} +MPC_CRC_INTERLACE_MODE_TOP = 0 +MPC_CRC_INTERLACE_MODE_BOTTOM = 1 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_MODE' +MPC_CRC_CALC_MODE__enumvalues = { + 0: 'MPC_CRC_ONE_SHOT_MODE', + 1: 'MPC_CRC_CONTINUOUS_MODE', +} +MPC_CRC_ONE_SHOT_MODE = 0 +MPC_CRC_CONTINUOUS_MODE = 1 +MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' +MPC_CRC_CALC_STEREO_MODE__enumvalues = { + 0: 'MPC_CRC_STEREO_MODE_LEFT', + 1: 'MPC_CRC_STEREO_MODE_RIGHT', + 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', +} +MPC_CRC_STEREO_MODE_LEFT = 0 +MPC_CRC_STEREO_MODE_RIGHT = 1 +MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 +MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_SOURCE_SELECT' +MPC_CRC_SOURCE_SELECT__enumvalues = { + 0: 'MPC_CRC_SOURCE_SEL_DPP', + 1: 'MPC_CRC_SOURCE_SEL_OPP', + 2: 'MPC_CRC_SOURCE_SEL_DWB', + 3: 'MPC_CRC_SOURCE_SEL_OTHER', +} +MPC_CRC_SOURCE_SEL_DPP = 0 +MPC_CRC_SOURCE_SEL_OPP = 1 +MPC_CRC_SOURCE_SEL_DWB = 2 +MPC_CRC_SOURCE_SEL_OTHER = 3 +MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS1_DATA_SELECT' +MPC_DEBUG_BUS1_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', + 1: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', + 2: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', + 3: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', +} +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 1 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 2 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 3 +MPC_DEBUG_BUS1_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS2_DATA_SELECT' +MPC_DEBUG_BUS2_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', + 1: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', + 2: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', + 3: 'MPC_DEBUG_BUS2_DATA_SELECT_RES', +} +MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0 +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 1 +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 2 +MPC_DEBUG_BUS2_DATA_SELECT_RES = 3 +MPC_DEBUG_BUS2_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT' +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', + 1: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', + 2: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', + 3: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', + 4: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', + 5: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', + 6: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', + 7: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', +} +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 1 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 2 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 3 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 4 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 5 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 6 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 7 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT' +MPC_DEBUG_BUS_MPCC_BYTE_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS_MPCC_BYTE0', + 1: 'MPC_DEBUG_BUS_MPCC_BYTE1', + 2: 'MPC_DEBUG_BUS_MPCC_BYTE2', + 3: 'MPC_DEBUG_BUS_MPCC_BYTE3', +} +MPC_DEBUG_BUS_MPCC_BYTE0 = 0 +MPC_DEBUG_BUS_MPCC_BYTE1 = 1 +MPC_DEBUG_BUS_MPCC_BYTE2 = 2 +MPC_DEBUG_BUS_MPCC_BYTE3 = 3 +MPC_DEBUG_BUS_MPCC_BYTE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_COEF_FORMAT' +MPC_OCSC_COEF_FORMAT__enumvalues = { + 0: 'MPC_OCSC_COEF_FORMAT_S2_13', + 1: 'MPC_OCSC_COEF_FORMAT_S3_12', +} +MPC_OCSC_COEF_FORMAT_S2_13 = 0 +MPC_OCSC_COEF_FORMAT_S3_12 = 1 +MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN' +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_CSC_MODE' +MPC_OUT_CSC_MODE__enumvalues = { + 0: 'MPC_OUT_CSC_MODE_0', + 1: 'MPC_OUT_CSC_MODE_1', + 2: 'MPC_OUT_CSC_MODE_2', + 3: 'MPC_OUT_CSC_MODE_RSV', +} +MPC_OUT_CSC_MODE_0 = 0 +MPC_OUT_CSC_MODE_1 = 1 +MPC_OUT_CSC_MODE_2 = 2 +MPC_OUT_CSC_MODE_RSV = 3 +MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { + 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', +} +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' +MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { + 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', +} +MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 +MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 +MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_BG_COLOR_BPC' +MPCC_BG_COLOR_BPC__enumvalues = { + 0: 'MPCC_BG_COLOR_BPC_8bit', + 1: 'MPCC_BG_COLOR_BPC_9bit', + 2: 'MPCC_BG_COLOR_BPC_10bit', + 3: 'MPCC_BG_COLOR_BPC_11bit', + 4: 'MPCC_BG_COLOR_BPC_12bit', +} +MPCC_BG_COLOR_BPC_8bit = 0 +MPCC_BG_COLOR_BPC_9bit = 1 +MPCC_BG_COLOR_BPC_10bit = 2 +MPCC_BG_COLOR_BPC_11bit = 3 +MPCC_BG_COLOR_BPC_12bit = 4 +MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', +} +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', +} +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', +} +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' +MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', +} +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_MODE' +MPCC_CONTROL_MPCC_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', +} +MPCC_CONTROL_MPCC_MODE_BYPASS = 0 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 +MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 +MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' +MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' +MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 +MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 +MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 +MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN' +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', +} +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM' +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM' +MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_MODE_0', + 1: 'MPCC_GAMUT_REMAP_MODE_1', + 2: 'MPCC_GAMUT_REMAP_MODE_2', + 3: 'MPCC_GAMUT_REMAP_MODE_RSV', +} +MPCC_GAMUT_REMAP_MODE_0 = 0 +MPCC_GAMUT_REMAP_MODE_1 = 1 +MPCC_GAMUT_REMAP_MODE_2 = 2 +MPCC_GAMUT_REMAP_MODE_RSV = 3 +MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM' +MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B', +} +MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0 +MPCC_OGAM_LUT_2CFG_MEMORY_A = 1 +MPCC_OGAM_LUT_2CFG_MEMORY_B = 2 +MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE' +MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_OGAM_DIFFERENT_RGB', + 1: 'MPCC_OGAM_ALL_USE_R', +} +MPCC_OGAM_DIFFERENT_RGB = 0 +MPCC_OGAM_ALL_USE_R = 1 +MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM' +MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_ENABLE_PWL', + 1: 'MPCC_OGAM_DISABLE_PWL', +} +MPCC_OGAM_ENABLE_PWL = 0 +MPCC_OGAM_DISABLE_PWL = 1 +MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', +} +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_RAMA_ACCESS', + 1: 'MPCC_OGAM_RAMB_ACCESS', +} +MPCC_OGAM_RAMA_ACCESS = 0 +MPCC_OGAM_RAMB_ACCESS = 1 +MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL' +MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_OGAM_BLUE_LUT', + 1: 'MPCC_OGAM_GREEN_LUT', + 2: 'MPCC_OGAM_RED_LUT', +} +MPCC_OGAM_BLUE_LUT = 0 +MPCC_OGAM_GREEN_LUT = 1 +MPCC_OGAM_RED_LUT = 2 +MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_DBG' +MPCC_OGAM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_OGAM_DISABLE_DEBUG', + 1: 'MPCC_OGAM_ENABLE_DEBUG', +} +MPCC_OGAM_DISABLE_DEBUG = 0 +MPCC_OGAM_ENABLE_DEBUG = 1 +MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM' +MPCC_OGAM_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_OGAM_RAMA', + 1: 'MPCC_OGAM_RAMB', +} +MPCC_OGAM_RAMA = 0 +MPCC_OGAM_RAMB = 1 +MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM' +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_MODE_0', + 1: 'MPCC_OGAM_MODE_RSV1', + 2: 'MPCC_OGAM_MODE_2', + 3: 'MPCC_OGAM_MODE_RSV', +} +MPCC_OGAM_MODE_0 = 0 +MPCC_OGAM_MODE_RSV1 = 1 +MPCC_OGAM_MODE_2 = 2 +MPCC_OGAM_MODE_RSV = 3 +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_NUM_SEG' +MPCC_OGAM_NUM_SEG__enumvalues = { + 0: 'MPCC_OGAM_SEGMENTS_1', + 1: 'MPCC_OGAM_SEGMENTS_2', + 2: 'MPCC_OGAM_SEGMENTS_4', + 3: 'MPCC_OGAM_SEGMENTS_8', + 4: 'MPCC_OGAM_SEGMENTS_16', + 5: 'MPCC_OGAM_SEGMENTS_32', + 6: 'MPCC_OGAM_SEGMENTS_64', + 7: 'MPCC_OGAM_SEGMENTS_128', +} +MPCC_OGAM_SEGMENTS_1 = 0 +MPCC_OGAM_SEGMENTS_2 = 1 +MPCC_OGAM_SEGMENTS_4 = 2 +MPCC_OGAM_SEGMENTS_8 = 3 +MPCC_OGAM_SEGMENTS_16 = 4 +MPCC_OGAM_SEGMENTS_32 = 5 +MPCC_OGAM_SEGMENTS_64 = 6 +MPCC_OGAM_SEGMENTS_128 = 7 +MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN' +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', +} +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM' +MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_36BIT', + 1: 'MPCC_MCM_3DLUT_30BIT', +} +MPCC_MCM_3DLUT_36BIT = 0 +MPCC_MCM_3DLUT_30BIT = 1 +MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL' +MPCC_MCM_3DLUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_RAM0_ACCESS', + 1: 'MPCC_MCM_RAM1_ACCESS', + 2: 'MPCC_MCM_RAM2_ACCESS', + 3: 'MPCC_MCM_RAM3_ACCESS', +} +MPCC_MCM_RAM0_ACCESS = 0 +MPCC_MCM_RAM1_ACCESS = 1 +MPCC_MCM_RAM2_ACCESS = 2 +MPCC_MCM_RAM3_ACCESS = 3 +MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM' +MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_17CUBE', + 1: 'MPCC_MCM_3DLUT_9CUBE', +} +MPCC_MCM_3DLUT_17CUBE = 0 +MPCC_MCM_3DLUT_9CUBE = 1 +MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM' +MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_BYPASS', + 1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1', + 2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3', +} +MPCC_MCM_GAMMA_LUT_BYPASS = 0 +MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1 +MPCC_MCM_GAMMA_LUT_RAM_LUT = 2 +MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3 +MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM' +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', +} +MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0 +MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1 +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM' +MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_RAMA', + 1: 'MPCC_MCM_GAMMA_LUT_RAMB', +} +MPCC_MCM_GAMMA_LUT_RAMA = 0 +MPCC_MCM_GAMMA_LUT_RAMB = 1 +MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM' +MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_LUT_2_MODE_BYPASS', + 1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', +} +MPCC_MCM_LUT_2_MODE_BYPASS = 0 +MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1 +MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2 +MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE' +MPCC_MCM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_MCM_LUT_DIFFERENT_RGB', + 1: 'MPCC_MCM_LUT_ALL_USE_R', +} +MPCC_MCM_LUT_DIFFERENT_RGB = 0 +MPCC_MCM_LUT_ALL_USE_R = 1 +MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_NUM_SEG' +MPCC_MCM_LUT_NUM_SEG__enumvalues = { + 0: 'MPCC_MCM_LUT_SEGMENTS_1', + 1: 'MPCC_MCM_LUT_SEGMENTS_2', + 2: 'MPCC_MCM_LUT_SEGMENTS_4', + 3: 'MPCC_MCM_LUT_SEGMENTS_8', + 4: 'MPCC_MCM_LUT_SEGMENTS_16', + 5: 'MPCC_MCM_LUT_SEGMENTS_32', + 6: 'MPCC_MCM_LUT_SEGMENTS_64', + 7: 'MPCC_MCM_LUT_SEGMENTS_128', +} +MPCC_MCM_LUT_SEGMENTS_1 = 0 +MPCC_MCM_LUT_SEGMENTS_2 = 1 +MPCC_MCM_LUT_SEGMENTS_4 = 2 +MPCC_MCM_LUT_SEGMENTS_8 = 3 +MPCC_MCM_LUT_SEGMENTS_16 = 4 +MPCC_MCM_LUT_SEGMENTS_32 = 5 +MPCC_MCM_LUT_SEGMENTS_64 = 6 +MPCC_MCM_LUT_SEGMENTS_128 = 7 +MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_RAM_SEL' +MPCC_MCM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_RAMA_ACCESS', + 1: 'MPCC_MCM_LUT_RAMB_ACCESS', +} +MPCC_MCM_LUT_RAMA_ACCESS = 0 +MPCC_MCM_LUT_RAMB_ACCESS = 1 +MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL' +MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_BLUE_LUT', + 1: 'MPCC_MCM_LUT_GREEN_LUT', + 2: 'MPCC_MCM_LUT_RED_LUT', +} +MPCC_MCM_LUT_BLUE_LUT = 0 +MPCC_MCM_LUT_GREEN_LUT = 1 +MPCC_MCM_LUT_RED_LUT = 2 +MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_DBG' +MPCC_MCM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_MCM_LUT_DISABLE_DEBUG', + 1: 'MPCC_MCM_LUT_ENABLE_DEBUG', +} +MPCC_MCM_LUT_DISABLE_DEBUG = 0 +MPCC_MCM_LUT_ENABLE_DEBUG = 1 +MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM' +MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 1: 'MPCC_MCM_MEM_PWR_FORCE_LS', + 2: 'MPCC_MCM_MEM_PWR_FORCE_DS', + 3: 'MPCC_MCM_MEM_PWR_FORCE_SD', +} +MPCC_MCM_MEM_PWR_FORCE_DIS = 0 +MPCC_MCM_MEM_PWR_FORCE_LS = 1 +MPCC_MCM_MEM_PWR_FORCE_DS = 2 +MPCC_MCM_MEM_PWR_FORCE_SD = 3 +MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM' +MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_STATE_ON', + 1: 'MPCC_MCM_MEM_PWR_STATE_LS', + 2: 'MPCC_MCM_MEM_PWR_STATE_DS', + 3: 'MPCC_MCM_MEM_PWR_STATE_SD', +} +MPCC_MCM_MEM_PWR_STATE_ON = 0 +MPCC_MCM_MEM_PWR_STATE_LS = 1 +MPCC_MCM_MEM_PWR_STATE_DS = 2 +MPCC_MCM_MEM_PWR_STATE_SD = 3 +MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_BIT_DEPTH' +ENUM_DPG_BIT_DEPTH__enumvalues = { + 0: 'ENUM_DPG_BIT_DEPTH_6BPC', + 1: 'ENUM_DPG_BIT_DEPTH_8BPC', + 2: 'ENUM_DPG_BIT_DEPTH_10BPC', + 3: 'ENUM_DPG_BIT_DEPTH_12BPC', +} +ENUM_DPG_BIT_DEPTH_6BPC = 0 +ENUM_DPG_BIT_DEPTH_8BPC = 1 +ENUM_DPG_BIT_DEPTH_10BPC = 2 +ENUM_DPG_BIT_DEPTH_12BPC = 3 +ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' +ENUM_DPG_DYNAMIC_RANGE__enumvalues = { + 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', + 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', +} +ENUM_DPG_DYNAMIC_RANGE_VESA = 0 +ENUM_DPG_DYNAMIC_RANGE_CEA = 1 +ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_EN' +ENUM_DPG_EN__enumvalues = { + 0: 'ENUM_DPG_DISABLE', + 1: 'ENUM_DPG_ENABLE', +} +ENUM_DPG_DISABLE = 0 +ENUM_DPG_ENABLE = 1 +ENUM_DPG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_FIELD_POLARITY' +ENUM_DPG_FIELD_POLARITY__enumvalues = { + 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', +} +ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 +ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 +ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_MODE' +ENUM_DPG_MODE__enumvalues = { + 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 3: 'ENUM_DPG_MODE_VERTICAL_BAR', + 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', + 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', + 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', +} +ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 +ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 +ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 +ENUM_DPG_MODE_VERTICAL_BAR = 3 +ENUM_DPG_MODE_HORIZONTAL_BAR = 4 +ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 +ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 +ENUM_DPG_MODE_RGB_XR_BIAS = 7 +ENUM_DPG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_DIS_CTRL' +FMTMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', +} +FMTMEM_ENABLE_MEM_PWR_CTRL = 0 +FMTMEM_DISABLE_MEM_PWR_CTRL = 1 +FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' +FMTMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'FMTMEM_NO_FORCE_REQUEST', + 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', +} +FMTMEM_NO_FORCE_REQUEST = 0 +FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 +FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' +FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' +FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', +} +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' +FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' +FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { + 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', +} +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 +FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { + 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', +} +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' +FMT_CONTROL_PIXEL_ENCODING__enumvalues = { + 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', +} +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 +FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' +FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', +} +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 +FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' +FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', +} +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 +FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' +FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { + 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', +} +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 +FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DYNAMIC_EXP_MODE' +FMT_DYNAMIC_EXP_MODE__enumvalues = { + 0: 'FMT_DYNAMIC_EXP_MODE_10to12', + 1: 'FMT_DYNAMIC_EXP_MODE_8to12', +} +FMT_DYNAMIC_EXP_MODE_10to12 = 0 +FMT_DYNAMIC_EXP_MODE_8to12 = 1 +FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' +FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', +} +FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 +FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 +FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_POWER_STATE_ENUM' +FMT_POWER_STATE_ENUM__enumvalues = { + 0: 'FMT_POWER_STATE_ENUM_ON', + 1: 'FMT_POWER_STATE_ENUM_LS', + 2: 'FMT_POWER_STATE_ENUM_DS', + 3: 'FMT_POWER_STATE_ENUM_SD', +} +FMT_POWER_STATE_ENUM_ON = 0 +FMT_POWER_STATE_ENUM_LS = 1 +FMT_POWER_STATE_ENUM_DS = 2 +FMT_POWER_STATE_ENUM_SD = 3 +FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' +FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', +} +FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 +FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 +FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', +} +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_MODE' +FMT_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_MODE_0', + 1: 'FMT_SPATIAL_DITHER_MODE_1', + 2: 'FMT_SPATIAL_DITHER_MODE_2', + 3: 'FMT_SPATIAL_DITHER_MODE_3', +} +FMT_SPATIAL_DITHER_MODE_0 = 0 +FMT_SPATIAL_DITHER_MODE_1 = 1 +FMT_SPATIAL_DITHER_MODE_2 = 2 +FMT_SPATIAL_DITHER_MODE_3 = 3 +FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' +FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { + 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', +} +FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 +FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 +FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum + +# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION' +OPPBUF_DISPLAY_SEGMENTATION__enumvalues = { + 0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', +} +OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0 +OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 +OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' +OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { + 0: 'OPP_PIPE_CLOCK_DISABLE', + 1: 'OPP_PIPE_CLOCK_ENABLE', +} +OPP_PIPE_CLOCK_DISABLE = 0 +OPP_PIPE_CLOCK_ENABLE = 1 +OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' +OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { + 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', +} +OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 +OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 +OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_CONT_EN' +OPP_PIPE_CRC_CONT_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', + 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', +} +OPP_PIPE_CRC_MODE_ONE_SHOT = 0 +OPP_PIPE_CRC_MODE_CONTINUOUS = 1 +OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_EN' +OPP_PIPE_CRC_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_DISABLE', + 1: 'OPP_PIPE_CRC_ENABLE', +} +OPP_PIPE_CRC_DISABLE = 0 +OPP_PIPE_CRC_ENABLE = 1 +OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' +OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', +} +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 +OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' +OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', + 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', +} +OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 +OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 +OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' +OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { + 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', +} +OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 +OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 +OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' +OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', +} +OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 +OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 +OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 +OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 +OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' +OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', +} +OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 +OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 +OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' +OPP_PIPE_CRC_STEREO_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', +} +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 +OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' +OPP_PIPE_CRC_STEREO_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', + 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', +} +OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 +OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 +OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL' +OPP_ABM_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_ABM0', + 1: 'DEBUG_BUS_SELECT_ABM1', + 2: 'DEBUG_BUS_SELECT_ABM2', + 3: 'DEBUG_BUS_SELECT_ABM3', + 4: 'DEBUG_BUS_SELECT_ABM_RESERVED0', + 5: 'DEBUG_BUS_SELECT_ABM_RESERVED1', +} +DEBUG_BUS_SELECT_ABM0 = 0 +DEBUG_BUS_SELECT_ABM1 = 1 +DEBUG_BUS_SELECT_ABM2 = 2 +DEBUG_BUS_SELECT_ABM3 = 3 +DEBUG_BUS_SELECT_ABM_RESERVED0 = 4 +DEBUG_BUS_SELECT_ABM_RESERVED1 = 5 +OPP_ABM_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL' +OPP_DPG_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_DPG0', + 1: 'DEBUG_BUS_SELECT_DPG1', + 2: 'DEBUG_BUS_SELECT_DPG2', + 3: 'DEBUG_BUS_SELECT_DPG3', + 4: 'DEBUG_BUS_SELECT_DPG_RESERVED0', + 5: 'DEBUG_BUS_SELECT_DPG_RESERVED1', +} +DEBUG_BUS_SELECT_DPG0 = 0 +DEBUG_BUS_SELECT_DPG1 = 1 +DEBUG_BUS_SELECT_DPG2 = 2 +DEBUG_BUS_SELECT_DPG3 = 3 +DEBUG_BUS_SELECT_DPG_RESERVED0 = 4 +DEBUG_BUS_SELECT_DPG_RESERVED1 = 5 +OPP_DPG_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL' +OPP_FMT_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_FMT0', + 1: 'DEBUG_BUS_SELECT_FMT1', + 2: 'DEBUG_BUS_SELECT_FMT2', + 3: 'DEBUG_BUS_SELECT_FMT3', + 4: 'DEBUG_BUS_SELECT_FMT_RESERVED0', + 5: 'DEBUG_BUS_SELECT_FMT_RESERVED1', +} +DEBUG_BUS_SELECT_FMT0 = 0 +DEBUG_BUS_SELECT_FMT1 = 1 +DEBUG_BUS_SELECT_FMT2 = 2 +DEBUG_BUS_SELECT_FMT3 = 3 +DEBUG_BUS_SELECT_FMT_RESERVED0 = 4 +DEBUG_BUS_SELECT_FMT_RESERVED1 = 5 +OPP_FMT_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL' +OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_OPPBUF0', + 1: 'DEBUG_BUS_SELECT_OPPBUF1', + 2: 'DEBUG_BUS_SELECT_OPPBUF2', + 3: 'DEBUG_BUS_SELECT_OPPBUF3', + 4: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', + 5: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', +} +DEBUG_BUS_SELECT_OPPBUF0 = 0 +DEBUG_BUS_SELECT_OPPBUF1 = 1 +DEBUG_BUS_SELECT_OPPBUF2 = 2 +DEBUG_BUS_SELECT_OPPBUF3 = 3 +DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 4 +DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 5 +OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL' +OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_OPP_PIPE0', + 1: 'DEBUG_BUS_SELECT_OPP_PIPE1', + 2: 'DEBUG_BUS_SELECT_OPP_PIPE2', + 3: 'DEBUG_BUS_SELECT_OPP_PIPE3', + 4: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', + 5: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', +} +DEBUG_BUS_SELECT_OPP_PIPE0 = 0 +DEBUG_BUS_SELECT_OPP_PIPE1 = 1 +DEBUG_BUS_SELECT_OPP_PIPE2 = 2 +DEBUG_BUS_SELECT_OPP_PIPE3 = 3 +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 4 +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 5 +OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' +OPP_TEST_CLK_SEL_CONTROL__enumvalues = { + 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', + 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', + 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', + 3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', + 5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 6: 'OPP_TEST_CLK_SEL_RESERVED0', + 7: 'OPP_TEST_CLK_SEL_RESERVED1', + 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', + 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', + 11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 12: 'OPP_TEST_CLK_SEL_RESERVED2', + 13: 'OPP_TEST_CLK_SEL_RESERVED3', +} +OPP_TEST_CLK_SEL_DISPCLK_P = 0 +OPP_TEST_CLK_SEL_DISPCLK_R = 1 +OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 +OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3 +OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4 +OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5 +OPP_TEST_CLK_SEL_RESERVED0 = 6 +OPP_TEST_CLK_SEL_RESERVED1 = 7 +OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8 +OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9 +OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10 +OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11 +OPP_TEST_CLK_SEL_RESERVED2 = 12 +OPP_TEST_CLK_SEL_RESERVED3 = 13 +OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' +OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { + 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', + 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', +} +OPP_TOP_CLOCK_DISABLED_STATUS = 0 +OPP_TOP_CLOCK_ENABLED_STATUS = 1 +OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' +OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { + 0: 'OPP_TOP_CLOCK_GATING_ENABLED', + 1: 'OPP_TOP_CLOCK_GATING_DISABLED', +} +OPP_TOP_CLOCK_GATING_ENABLED = 0 +OPP_TOP_CLOCK_GATING_DISABLED = 1 +OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DSCRM_EN' +ENUM_DSCRM_EN__enumvalues = { + 0: 'ENUM_DSCRM_DISABLE', + 1: 'ENUM_DSCRM_ENABLE', +} +ENUM_DSCRM_DISABLE = 0 +ENUM_DSCRM_ENABLE = 1 +ENUM_DSCRM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_SEL' +MASTER_UPDATE_LOCK_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_SEL_0', + 1: 'MASTER_UPDATE_LOCK_SEL_1', + 2: 'MASTER_UPDATE_LOCK_SEL_2', + 3: 'MASTER_UPDATE_LOCK_SEL_3', + 4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5', +} +MASTER_UPDATE_LOCK_SEL_0 = 0 +MASTER_UPDATE_LOCK_SEL_1 = 1 +MASTER_UPDATE_LOCK_SEL_2 = 2 +MASTER_UPDATE_LOCK_SEL_3 = 3 +MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4 +MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5 +MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' +OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', +} +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', +} +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', +} +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' +OTG_CONTROL_OTG_MASTER_EN__enumvalues = { + 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', +} +OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 +OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 +OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX' +OTG_CONTROL_OTG_OUT_MUX__enumvalues = { + 0: 'OTG_CONTROL_OTG_OUT_MUX_0', + 1: 'OTG_CONTROL_OTG_OUT_MUX_1', + 2: 'OTG_CONTROL_OTG_OUT_MUX_2', +} +OTG_CONTROL_OTG_OUT_MUX_0 = 0 +OTG_CONTROL_OTG_OUT_MUX_1 = 1 +OTG_CONTROL_OTG_OUT_MUX_2 = 2 +OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' +OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', +} +OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 +OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { + 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', +} +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN' +OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' +OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE' +OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', +} +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' +OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', +} +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', +} +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE' +OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = { + 0: 'OTG_DIG_UPDATE_VCOUNT_0', + 1: 'OTG_DIG_UPDATE_VCOUNT_1', +} +OTG_DIG_UPDATE_VCOUNT_0 = 0 +OTG_DIG_UPDATE_VCOUNT_1 = 1 +OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE' +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { + 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', +} +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { + 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', +} +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { + 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', +} +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = { + 0: 'DIG_UPDATE_EYE_SEL_BOTH', + 1: 'DIG_UPDATE_EYE_SEL_LEFT', + 2: 'DIG_UPDATE_EYE_SEL_RIGHT', +} +DIG_UPDATE_EYE_SEL_BOTH = 0 +DIG_UPDATE_EYE_SEL_LEFT = 1 +DIG_UPDATE_EYE_SEL_RIGHT = 2 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = { + 0: 'DIG_UPDATE_FIELD_SEL_BOTH', + 1: 'DIG_UPDATE_FIELD_SEL_TOP', + 2: 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 3: 'DIG_UPDATE_FIELD_SEL_RESERVED', +} +DIG_UPDATE_FIELD_SEL_BOTH = 0 +DIG_UPDATE_FIELD_SEL_TOP = 1 +DIG_UPDATE_FIELD_SEL_BOTTOM = 2 +DIG_UPDATE_FIELD_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', +} +MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 +MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 +MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2 +MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', +} +MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN' +OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = { + 0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', + 1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', +} +OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0 +OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1 +OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GSL_MASTER_MODE' +OTG_GSL_MASTER_MODE__enumvalues = { + 0: 'OTG_GSL_MASTER_MODE_0', + 1: 'OTG_GSL_MASTER_MODE_1', + 2: 'OTG_GSL_MASTER_MODE_2', + 3: 'OTG_GSL_MASTER_MODE_3', +} +OTG_GSL_MASTER_MODE_0 = 0 +OTG_GSL_MASTER_MODE_1 = 1 +OTG_GSL_MASTER_MODE_2 = 2 +OTG_GSL_MASTER_MODE_3 = 3 +OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_HORZ_REPETITION_COUNT' +OTG_HORZ_REPETITION_COUNT__enumvalues = { + 0: 'OTG_HORZ_REPETITION_COUNT_0', + 1: 'OTG_HORZ_REPETITION_COUNT_1', + 2: 'OTG_HORZ_REPETITION_COUNT_2', + 3: 'OTG_HORZ_REPETITION_COUNT_3', + 4: 'OTG_HORZ_REPETITION_COUNT_4', + 5: 'OTG_HORZ_REPETITION_COUNT_5', + 6: 'OTG_HORZ_REPETITION_COUNT_6', + 7: 'OTG_HORZ_REPETITION_COUNT_7', + 8: 'OTG_HORZ_REPETITION_COUNT_8', + 9: 'OTG_HORZ_REPETITION_COUNT_9', + 10: 'OTG_HORZ_REPETITION_COUNT_10', + 11: 'OTG_HORZ_REPETITION_COUNT_11', + 12: 'OTG_HORZ_REPETITION_COUNT_12', + 13: 'OTG_HORZ_REPETITION_COUNT_13', + 14: 'OTG_HORZ_REPETITION_COUNT_14', + 15: 'OTG_HORZ_REPETITION_COUNT_15', +} +OTG_HORZ_REPETITION_COUNT_0 = 0 +OTG_HORZ_REPETITION_COUNT_1 = 1 +OTG_HORZ_REPETITION_COUNT_2 = 2 +OTG_HORZ_REPETITION_COUNT_3 = 3 +OTG_HORZ_REPETITION_COUNT_4 = 4 +OTG_HORZ_REPETITION_COUNT_5 = 5 +OTG_HORZ_REPETITION_COUNT_6 = 6 +OTG_HORZ_REPETITION_COUNT_7 = 7 +OTG_HORZ_REPETITION_COUNT_8 = 8 +OTG_HORZ_REPETITION_COUNT_9 = 9 +OTG_HORZ_REPETITION_COUNT_10 = 10 +OTG_HORZ_REPETITION_COUNT_11 = 11 +OTG_HORZ_REPETITION_COUNT_12 = 12 +OTG_HORZ_REPETITION_COUNT_13 = 13 +OTG_HORZ_REPETITION_COUNT_14 = 14 +OTG_HORZ_REPETITION_COUNT_15 = 15 +OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_SYNC_A_POL' +OTG_H_SYNC_A_POL__enumvalues = { + 0: 'OTG_H_SYNC_A_POL_HIGH', + 1: 'OTG_H_SYNC_A_POL_LOW', +} +OTG_H_SYNC_A_POL_HIGH = 0 +OTG_H_SYNC_A_POL_LOW = 1 +OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE' +OTG_H_TIMING_DIV_MODE__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_NO_DIV', + 1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2', + 2: 'OTG_H_TIMING_DIV_MODE_RESERVED', + 3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4', +} +OTG_H_TIMING_DIV_MODE_NO_DIV = 0 +OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1 +OTG_H_TIMING_DIV_MODE_RESERVED = 2 +OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3 +OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL' +OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_AUTO', + 1: 'OTG_H_TIMING_DIV_MODE_NOAUTO', +} +OTG_H_TIMING_DIV_MODE_AUTO = 0 +OTG_H_TIMING_DIV_MODE_NOAUTO = 1 +OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { + 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', +} +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN' +OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 1: 'OTG_MASTER_UPDATE_LOCK_ENABLE', +} +OTG_MASTER_UPDATE_LOCK_DISABLE = 0 +OTG_MASTER_UPDATE_LOCK_ENABLE = 1 +OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' +OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', +} +OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 +OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 +OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE' +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', +} +OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0 +OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1 +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { + 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', +} +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { + 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', +} +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL' +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', +} +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' +OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { + 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', +} +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', +} +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' +OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', +} +OTG_TRIGA_FREQUENCY_SELECT_0 = 0 +OTG_TRIGA_FREQUENCY_SELECT_1 = 1 +OTG_TRIGA_FREQUENCY_SELECT_2 = 2 +OTG_TRIGA_FREQUENCY_SELECT_3 = 3 +OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' +OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', +} +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' +OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', +} +OTG_TRIGB_FREQUENCY_SELECT_0 = 0 +OTG_TRIGB_FREQUENCY_SELECT_1 = 1 +OTG_TRIGB_FREQUENCY_SELECT_2 = 2 +OTG_TRIGB_FREQUENCY_SELECT_3 = 3 +OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' +OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { + 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', +} +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', +} +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', +} +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { + 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', +} +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE' +OTG_VUPDATE_BLOCK_DISABLE__enumvalues = { + 0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 1: 'OTG_VUPDATE_BLOCK_DISABLE_ON', +} +OTG_VUPDATE_BLOCK_DISABLE_OFF = 0 +OTG_VUPDATE_BLOCK_DISABLE_ON = 1 +OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_A_POL' +OTG_V_SYNC_A_POL__enumvalues = { + 0: 'OTG_V_SYNC_A_POL_HIGH', + 1: 'OTG_V_SYNC_A_POL_LOW', +} +OTG_V_SYNC_A_POL_HIGH = 0 +OTG_V_SYNC_A_POL_LOW = 1 +OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_MODE' +OTG_V_SYNC_MODE__enumvalues = { + 0: 'OTG_V_SYNC_MODE_HSYNC', + 1: 'OTG_V_SYNC_MODE_HBLANK', +} +OTG_V_SYNC_MODE_HSYNC = 0 +OTG_V_SYNC_MODE_HBLANK = 1 +OTG_V_SYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', +} +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK' +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = { + 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', +} +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL' +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = { + 0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', +} +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_INT_TYPE' +DC_DMCUB_INT_TYPE__enumvalues = { + 0: 'INT_LEVEL', + 1: 'INT_PULSE', +} +INT_LEVEL = 0 +INT_PULSE = 1 +DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_TIMER_WINDOW' +DC_DMCUB_TIMER_WINDOW__enumvalues = { + 0: 'BITS_31_0', + 1: 'BITS_32_1', + 2: 'BITS_33_2', + 3: 'BITS_34_3', + 4: 'BITS_35_4', + 5: 'BITS_36_5', + 6: 'BITS_37_6', + 7: 'BITS_38_7', +} +BITS_31_0 = 0 +BITS_32_1 = 1 +BITS_33_2 = 2 +BITS_34_3 = 3 +BITS_35_4 = 4 +BITS_36_5 = 5 +BITS_37_6 = 6 +BITS_38_7 = 7 +DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'INVALID_REG_ACCESS_TYPE' +INVALID_REG_ACCESS_TYPE__enumvalues = { + 0: 'REG_UNALLOCATED_ADDR_WRITE', + 1: 'REG_UNALLOCATED_ADDR_READ', + 2: 'REG_VIRTUAL_WRITE', + 3: 'REG_VIRTUAL_READ', + 4: 'REG_SECURE_VIOLATE_WRITE', + 5: 'REG_SECURE_VIOLATE_READ', +} +REG_UNALLOCATED_ADDR_WRITE = 0 +REG_UNALLOCATED_ADDR_READ = 1 +REG_VIRTUAL_WRITE = 2 +REG_VIRTUAL_READ = 3 +REG_SECURE_VIOLATE_WRITE = 4 +REG_SECURE_VIOLATE_READ = 5 +INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' +DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 8: 'RESERVED_8', + 9: 'RESERVED_9', + 10: 'RESERVED_10', + 11: 'RESERVED_11', + 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 20: 'RESERVED_20', + 21: 'RESERVED_21', + 22: 'RESERVED_22', + 23: 'RESERVED_23', + 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 32: 'RESERVED_32', + 33: 'RESERVED_33', + 34: 'RESERVED_34', + 35: 'RESERVED_35', + 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 44: 'RESERVED_44', + 45: 'RESERVED_45', + 46: 'RESERVED_46', + 47: 'RESERVED_47', + 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 56: 'RESERVED_56', + 57: 'RESERVED_57', + 58: 'RESERVED_58', + 59: 'RESERVED_59', + 60: 'RESERVED_60', + 61: 'RESERVED_61', + 62: 'RESERVED_62', + 63: 'RESERVED_63', + 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 72: 'RESERVED_72', + 73: 'RESERVED_73', + 74: 'RESERVED_74', + 75: 'RESERVED_75', + 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 84: 'RESERVED_84', + 85: 'RESERVED_85', + 86: 'RESERVED_86', + 87: 'RESERVED_87', + 88: 'RESERVED_88', + 89: 'RESERVED_89', + 90: 'RESERVED_90', + 91: 'RESERVED_91', +} +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 +RESERVED_8 = 8 +RESERVED_9 = 9 +RESERVED_10 = 10 +RESERVED_11 = 11 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 +RESERVED_20 = 20 +RESERVED_21 = 21 +RESERVED_22 = 22 +RESERVED_23 = 23 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 +RESERVED_32 = 32 +RESERVED_33 = 33 +RESERVED_34 = 34 +RESERVED_35 = 35 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 +RESERVED_44 = 44 +RESERVED_45 = 45 +RESERVED_46 = 46 +RESERVED_47 = 47 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 +RESERVED_56 = 56 +RESERVED_57 = 57 +RESERVED_58 = 58 +RESERVED_59 = 59 +RESERVED_60 = 60 +RESERVED_61 = 61 +RESERVED_62 = 62 +RESERVED_63 = 63 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 +RESERVED_72 = 72 +RESERVED_73 = 73 +RESERVED_74 = 74 +RESERVED_75 = 75 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 +RESERVED_84 = 84 +RESERVED_85 = 85 +RESERVED_86 = 86 +RESERVED_87 = 87 +RESERVED_88 = 88 +RESERVED_89 = 89 +RESERVED_90 = 90 +RESERVED_91 = 91 +DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' +DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DMU_GPU_TIMER_START_0_END_27', + 1: 'DMU_GPU_TIMER_START_1_END_28', + 2: 'DMU_GPU_TIMER_START_2_END_29', + 3: 'DMU_GPU_TIMER_START_3_END_30', + 4: 'DMU_GPU_TIMER_START_4_END_31', + 5: 'DMU_GPU_TIMER_START_6_END_33', + 6: 'DMU_GPU_TIMER_START_8_END_35', + 7: 'DMU_GPU_TIMER_START_10_END_37', +} +DMU_GPU_TIMER_START_0_END_27 = 0 +DMU_GPU_TIMER_START_1_END_28 = 1 +DMU_GPU_TIMER_START_2_END_29 = 2 +DMU_GPU_TIMER_START_3_END_30 = 3 +DMU_GPU_TIMER_START_4_END_31 = 4 +DMU_GPU_TIMER_START_6_END_33 = 5 +DMU_GPU_TIMER_START_8_END_35 = 6 +DMU_GPU_TIMER_START_10_END_37 = 7 +DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_DEST' +IHC_INTERRUPT_DEST__enumvalues = { + 0: 'INTERRUPT_SENT_TO_IH', + 1: 'INTERRUPT_SENT_TO_DMCUB', +} +INTERRUPT_SENT_TO_IH = 0 +INTERRUPT_SENT_TO_DMCUB = 1 +IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' +IHC_INTERRUPT_LINE_STATUS__enumvalues = { + 0: 'INTERRUPT_LINE_NOT_ASSERTED', + 1: 'INTERRUPT_LINE_ASSERTED', +} +INTERRUPT_LINE_NOT_ASSERTED = 0 +INTERRUPT_LINE_ASSERTED = 1 +IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' +DC_SMU_INTERRUPT_ENABLE__enumvalues = { + 0: 'DISABLE_THE_INTERRUPT', + 1: 'ENABLE_THE_INTERRUPT', +} +DISABLE_THE_INTERRUPT = 0 +ENABLE_THE_INTERRUPT = 1 +DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_CLOCK_ON' +DMU_CLOCK_ON__enumvalues = { + 0: 'DMU_CLOCK_STATUS_ON', + 1: 'DMU_CLOCK_STATUS_OFF', +} +DMU_CLOCK_STATUS_ON = 0 +DMU_CLOCK_STATUS_OFF = 1 +DMU_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'SMU_INTR' +SMU_INTR__enumvalues = { + 0: 'SMU_MSG_INTR_NOOP', + 1: 'SET_SMU_MSG_INTR', +} +SMU_MSG_INTR_NOOP = 0 +SET_SMU_MSG_INTR = 1 +SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' +ALLOW_SR_ON_TRANS_REQ__enumvalues = { + 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', +} +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 +ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 +ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'AMCLOCK_ENABLE' +AMCLOCK_ENABLE__enumvalues = { + 0: 'ENABLE_AMCLK0', + 1: 'ENABLE_AMCLK1', +} +ENABLE_AMCLK0 = 0 +ENABLE_AMCLK1 = 1 +AMCLOCK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CLEAR_SMU_INTR' +CLEAR_SMU_INTR__enumvalues = { + 0: 'SMU_INTR_STATUS_NOOP', + 1: 'SMU_INTR_STATUS_CLEAR', +} +SMU_INTR_STATUS_NOOP = 0 +SMU_INTR_STATUS_CLEAR = 1 +CLEAR_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' +CLOCK_BRANCH_SOFT_RESET__enumvalues = { + 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', +} +CLOCK_BRANCH_SOFT_RESET_NOOP = 0 +CLOCK_BRANCH_SOFT_RESET_FORCE = 1 +CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' +DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', +} +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4 +DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' +DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', +} +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1 +DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_SEL' +DCCG_AUDIO_DTO_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', + 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 3: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', +} +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 3 +DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' +DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { + 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', +} +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 +DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_BLOCK_SEL' +DCCG_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCCG_DBG_BLOCK_SEL_DCCG', + 1: 'DCCG_DBG_BLOCK_SEL_PMON', + 2: 'DCCG_DBG_BLOCK_SEL_PMON2', +} +DCCG_DBG_BLOCK_SEL_DCCG = 0 +DCCG_DBG_BLOCK_SEL_PMON = 1 +DCCG_DBG_BLOCK_SEL_PMON2 = 2 +DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_EN' +DCCG_DBG_EN__enumvalues = { + 0: 'DCCG_DBG_EN_DISABLE', + 1: 'DCCG_DBG_EN_ENABLE', +} +DCCG_DBG_EN_DISABLE = 0 +DCCG_DBG_EN_ENABLE = 1 +DCCG_DBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DEEP_COLOR_CNTL' +DCCG_DEEP_COLOR_CNTL__enumvalues = { + 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', + 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', + 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', +} +DCCG_DEEP_COLOR_DTO_DISABLE = 0 +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 +DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' +DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', + 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', +} +DCCG_FIFO_ERRDET_OVR_DISABLE = 0 +DCCG_FIFO_ERRDET_OVR_ENABLE = 1 +DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_RESET' +DCCG_FIFO_ERRDET_RESET__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', + 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', +} +DCCG_FIFO_ERRDET_RESET_NOOP = 0 +DCCG_FIFO_ERRDET_RESET_FORCE = 1 +DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_STATE' +DCCG_FIFO_ERRDET_STATE__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', +} +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 +DCCG_FIFO_ERRDET_STATE_DETECTION = 1 +DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_HSYNC' +DCCG_PERF_MODE_HSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_HSYNC_NOOP', + 1: 'DCCG_PERF_MODE_HSYNC_START', +} +DCCG_PERF_MODE_HSYNC_NOOP = 0 +DCCG_PERF_MODE_HSYNC_START = 1 +DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_VSYNC' +DCCG_PERF_MODE_VSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_VSYNC_NOOP', + 1: 'DCCG_PERF_MODE_VSYNC_START', +} +DCCG_PERF_MODE_VSYNC_NOOP = 0 +DCCG_PERF_MODE_VSYNC_START = 1 +DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_OTG_SELECT' +DCCG_PERF_OTG_SELECT__enumvalues = { + 0: 'DCCG_PERF_SEL_OTG0', + 1: 'DCCG_PERF_SEL_OTG1', + 2: 'DCCG_PERF_SEL_OTG2', + 3: 'DCCG_PERF_SEL_OTG3', + 4: 'DCCG_PERF_SEL_RESERVED', +} +DCCG_PERF_SEL_OTG0 = 0 +DCCG_PERF_SEL_OTG1 = 1 +DCCG_PERF_SEL_OTG2 = 2 +DCCG_PERF_SEL_OTG3 = 3 +DCCG_PERF_SEL_RESERVED = 4 +DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_RUN' +DCCG_PERF_RUN__enumvalues = { + 0: 'DCCG_PERF_RUN_NOOP', + 1: 'DCCG_PERF_RUN_START', +} +DCCG_PERF_RUN_NOOP = 0 +DCCG_PERF_RUN_START = 1 +DCCG_PERF_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' +DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { + 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', +} +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 +DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_FIFO_ERROR' +DIO_FIFO_ERROR__enumvalues = { + 0: 'DIO_FIFO_ERROR_00', + 1: 'DIO_FIFO_ERROR_01', + 2: 'DIO_FIFO_ERROR_10', + 3: 'DIO_FIFO_ERROR_11', +} +DIO_FIFO_ERROR_00 = 0 +DIO_FIFO_ERROR_01 = 1 +DIO_FIFO_ERROR_10 = 2 +DIO_FIFO_ERROR_11 = 3 +DIO_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING' +DISABLE_CLOCK_GATING__enumvalues = { + 0: 'CLOCK_GATING_ENABLED', + 1: 'CLOCK_GATING_DISABLED', +} +CLOCK_GATING_ENABLED = 0 +CLOCK_GATING_DISABLED = 1 +DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' +DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { + 0: 'CLOCK_GATING_ENABLED_IN_DCO', + 1: 'CLOCK_GATING_DISABLED_IN_DCO', +} +CLOCK_GATING_ENABLED_IN_DCO = 0 +CLOCK_GATING_DISABLED_IN_DCO = 1 +DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' +DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { + 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', +} +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 +DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' +DISPCLK_FREQ_RAMP_DONE__enumvalues = { + 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', + 1: 'DISPCLK_FREQ_RAMP_COMPLETED', +} +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 +DISPCLK_FREQ_RAMP_COMPLETED = 1 +DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DPREFCLK_SRC_SEL' +DPREFCLK_SRC_SEL__enumvalues = { + 0: 'DPREFCLK_SRC_SEL_CK', + 1: 'DPREFCLK_SRC_SEL_P0PLL', + 2: 'DPREFCLK_SRC_SEL_P1PLL', + 3: 'DPREFCLK_SRC_SEL_P2PLL', +} +DPREFCLK_SRC_SEL_CK = 0 +DPREFCLK_SRC_SEL_P0PLL = 1 +DPREFCLK_SRC_SEL_P1PLL = 2 +DPREFCLK_SRC_SEL_P2PLL = 3 +DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DTO_DS_DISABLE' +DP_DTO_DS_DISABLE__enumvalues = { + 0: 'DP_DTO_DESPREAD_DISABLE', + 1: 'DP_DTO_DESPREAD_ENABLE', +} +DP_DTO_DESPREAD_DISABLE = 0 +DP_DTO_DESPREAD_ENABLE = 1 +DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_HW_CAL_ENABLE' +DS_HW_CAL_ENABLE__enumvalues = { + 0: 'DS_HW_CAL_DIS', + 1: 'DS_HW_CAL_EN', +} +DS_HW_CAL_DIS = 0 +DS_HW_CAL_EN = 1 +DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_JITTER_COUNT_SRC_SEL' +DS_JITTER_COUNT_SRC_SEL__enumvalues = { + 0: 'DS_JITTER_COUNT_SRC_SEL0', + 1: 'DS_JITTER_COUNT_SRC_SEL1', +} +DS_JITTER_COUNT_SRC_SEL0 = 0 +DS_JITTER_COUNT_SRC_SEL1 = 1 +DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DS_REF_SRC' +DS_REF_SRC__enumvalues = { + 0: 'DS_REF_IS_XTALIN', + 1: 'DS_REF_IS_EXT_GENLOCK', + 2: 'DS_REF_IS_PCIE', +} +DS_REF_IS_XTALIN = 0 +DS_REF_IS_EXT_GENLOCK = 1 +DS_REF_IS_PCIE = 2 +DS_REF_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_IN_PHASE' +DVOACLKC_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_IN_PHASE' +DVOACLKC_MVP_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { + 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', +} +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKD_IN_PHASE' +DVOACLKD_IN_PHASE__enumvalues = { + 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' +DVOACLK_COARSE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', +} +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 +DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' +DVOACLK_FINE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', +} +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 +DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_ENABLE_RST' +DVO_ENABLE_RST__enumvalues = { + 0: 'DVO_ENABLE_RST_DISABLE', + 1: 'DVO_ENABLE_RST_ENABLE', +} +DVO_ENABLE_RST_DISABLE = 0 +DVO_ENABLE_RST_ENABLE = 1 +DVO_ENABLE_RST = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE' +ENABLE__enumvalues = { + 0: 'DISABLE_THE_FEATURE', + 1: 'ENABLE_THE_FEATURE', +} +DISABLE_THE_FEATURE = 0 +ENABLE_THE_FEATURE = 1 +ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_CLOCK' +ENABLE_CLOCK__enumvalues = { + 0: 'ENABLE_THE_REFCLK', + 1: 'ENABLE_THE_FUNC_CLOCK', +} +ENABLE_THE_REFCLK = 0 +ENABLE_THE_FUNC_CLOCK = 1 +ENABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_DISABLE_CLOCK' +FORCE_DISABLE_CLOCK__enumvalues = { + 0: 'NOT_FORCE_THE_CLOCK_DISABLED', + 1: 'FORCE_THE_CLOCK_DISABLED', +} +NOT_FORCE_THE_CLOCK_DISABLED = 0 +FORCE_THE_CLOCK_DISABLED = 1 +FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMICHARCLK_SRC_SEL' +HDMICHARCLK_SRC_SEL__enumvalues = { + 0: 'HDMICHARCLK_SRC_SEL_UNIPHYA', + 1: 'HDMICHARCLK_SRC_SEL_UNIPHYB', + 2: 'HDMICHARCLK_SRC_SEL_UNIPHYC', + 3: 'HDMICHARCLK_SRC_SEL_UNIPHYD', + 4: 'HDMICHARCLK_SRC_SEL_UNIPHYE', + 5: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', +} +HDMICHARCLK_SRC_SEL_UNIPHYA = 0 +HDMICHARCLK_SRC_SEL_UNIPHYB = 1 +HDMICHARCLK_SRC_SEL_UNIPHYC = 2 +HDMICHARCLK_SRC_SEL_UNIPHYD = 3 +HDMICHARCLK_SRC_SEL_UNIPHYE = 4 +HDMICHARCLK_SRC_SEL_SRC_RESERVED = 5 +HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMISTREAMCLK_DTO_FORCE_DIS' +HDMISTREAMCLK_DTO_FORCE_DIS__enumvalues = { + 0: 'DTO_FORCE_NO_BYPASS', + 1: 'DTO_FORCE_BYPASS', +} +DTO_FORCE_NO_BYPASS = 0 +DTO_FORCE_BYPASS = 1 +HDMISTREAMCLK_DTO_FORCE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'HDMISTREAMCLK_SRC_SEL' +HDMISTREAMCLK_SRC_SEL__enumvalues = { + 0: 'SEL_REFCLK0', + 1: 'SEL_DTBCLK0', + 2: 'SEL_DTBCLK1', +} +SEL_REFCLK0 = 0 +SEL_DTBCLK0 = 1 +SEL_DTBCLK1 = 2 +HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'JITTER_REMOVE_DISABLE' +JITTER_REMOVE_DISABLE__enumvalues = { + 0: 'ENABLE_JITTER_REMOVAL', + 1: 'DISABLE_JITTER_REMOVAL', +} +ENABLE_JITTER_REMOVAL = 0 +DISABLE_JITTER_REMOVAL = 1 +JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_ADD_PIXEL' +OTG_ADD_PIXEL__enumvalues = { + 0: 'OTG_ADD_PIXEL_NOOP', + 1: 'OTG_ADD_PIXEL_FORCE', +} +OTG_ADD_PIXEL_NOOP = 0 +OTG_ADD_PIXEL_FORCE = 1 +OTG_ADD_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DROP_PIXEL' +OTG_DROP_PIXEL__enumvalues = { + 0: 'OTG_DROP_PIXEL_NOOP', + 1: 'OTG_DROP_PIXEL_FORCE', +} +OTG_DROP_PIXEL_NOOP = 0 +OTG_DROP_PIXEL_FORCE = 1 +OTG_DROP_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_EN' +PHYSYMCLK_FORCE_EN__enumvalues = { + 0: 'PHYSYMCLK_FORCE_EN_DISABLE', + 1: 'PHYSYMCLK_FORCE_EN_ENABLE', +} +PHYSYMCLK_FORCE_EN_DISABLE = 0 +PHYSYMCLK_FORCE_EN_ENABLE = 1 +PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL' +PHYSYMCLK_FORCE_SRC_SEL__enumvalues = { + 0: 'PHYSYMCLK_FORCE_SRC_SYMCLK', + 1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', + 2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', +} +PHYSYMCLK_FORCE_SRC_SYMCLK = 0 +PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1 +PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2 +PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' +PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', +} +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4 +PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' +PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', + 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', +} +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 +PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' +PIPE_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', + 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', +} +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 +PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 +PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 +PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PLL_CFG_IF_SOFT_RESET' +PLL_CFG_IF_SOFT_RESET__enumvalues = { + 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', + 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', +} +PLL_CFG_IF_SOFT_RESET_NOOP = 0 +PLL_CFG_IF_SOFT_RESET_FORCE = 1 +PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_EN' +SYMCLK_FE_FORCE_EN__enumvalues = { + 0: 'SYMCLK_FE_FORCE_EN_DISABLE', + 1: 'SYMCLK_FE_FORCE_EN_ENABLE', +} +SYMCLK_FE_FORCE_EN_DISABLE = 0 +SYMCLK_FE_FORCE_EN_ENABLE = 1 +SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_SRC' +SYMCLK_FE_FORCE_SRC__enumvalues = { + 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', + 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', + 4: 'SYMCLK_FE_FORCE_SRC_RESERVED', +} +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 +SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 +SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 +SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 +SYMCLK_FE_FORCE_SRC_RESERVED = 4 +SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_DIV_SEL' +TEST_CLK_DIV_SEL__enumvalues = { + 0: 'NO_DIV', + 1: 'DIV_2', + 2: 'DIV_4', + 3: 'DIV_8', +} +NO_DIV = 0 +DIV_2 = 1 +DIV_4 = 2 +DIV_8 = 3 +TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_LATCH_MASK' +VSYNC_CNT_LATCH_MASK__enumvalues = { + 0: 'VSYNC_CNT_LATCH_MASK_0', + 1: 'VSYNC_CNT_LATCH_MASK_1', +} +VSYNC_CNT_LATCH_MASK_0 = 0 +VSYNC_CNT_LATCH_MASK_1 = 1 +VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_RESET_SEL' +VSYNC_CNT_RESET_SEL__enumvalues = { + 0: 'VSYNC_CNT_RESET_SEL_0', + 1: 'VSYNC_CNT_RESET_SEL_1', +} +VSYNC_CNT_RESET_SEL_0 = 0 +VSYNC_CNT_RESET_SEL_1 = 1 +VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' +XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', + 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', +} +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 +XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 +XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_SEL' +XTAL_REF_SEL__enumvalues = { + 0: 'XTAL_REF_SEL_1X', + 1: 'XTAL_REF_SEL_2X', +} +XTAL_REF_SEL_1X = 0 +XTAL_REF_SEL_2X = 1 +XTAL_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_ACK' +HPD_INT_CONTROL_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_ACK_0', + 1: 'HPD_INT_CONTROL_ACK_1', +} +HPD_INT_CONTROL_ACK_0 = 0 +HPD_INT_CONTROL_ACK_1 = 1 +HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_POLARITY' +HPD_INT_CONTROL_POLARITY__enumvalues = { + 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', + 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', +} +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 +HPD_INT_CONTROL_GEN_INT_ON_CON = 1 +HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' +HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', + 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', +} +HPD_INT_CONTROL_RX_INT_ACK_0 = 0 +HPD_INT_CONTROL_RX_INT_ACK_1 = 1 +HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_CUR_DISP' +DPHY_8B10B_CUR_DISP__enumvalues = { + 0: 'DPHY_8B10B_CUR_DISP_ZERO', + 1: 'DPHY_8B10B_CUR_DISP_ONE', +} +DPHY_8B10B_CUR_DISP_ZERO = 0 +DPHY_8B10B_CUR_DISP_ONE = 1 +DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_RESET' +DPHY_8B10B_RESET__enumvalues = { + 0: 'DPHY_8B10B_NOT_RESET', + 1: 'DPHY_8B10B_RESETET', +} +DPHY_8B10B_NOT_RESET = 0 +DPHY_8B10B_RESETET = 1 +DPHY_8B10B_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' +DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', +} +DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 +DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' +DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', +} +DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 +DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE0' +DPHY_ATEST_SEL_LANE0__enumvalues = { + 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE0_REG_PATTERN', +} +DPHY_ATEST_LANE0_PRBS_PATTERN = 0 +DPHY_ATEST_LANE0_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE1' +DPHY_ATEST_SEL_LANE1__enumvalues = { + 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE1_REG_PATTERN', +} +DPHY_ATEST_LANE1_PRBS_PATTERN = 0 +DPHY_ATEST_LANE1_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE2' +DPHY_ATEST_SEL_LANE2__enumvalues = { + 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE2_REG_PATTERN', +} +DPHY_ATEST_LANE2_PRBS_PATTERN = 0 +DPHY_ATEST_LANE2_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE3' +DPHY_ATEST_SEL_LANE3__enumvalues = { + 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE3_REG_PATTERN', +} +DPHY_ATEST_LANE3_PRBS_PATTERN = 0 +DPHY_ATEST_LANE3_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_BYPASS' +DPHY_BYPASS__enumvalues = { + 0: 'DPHY_8B10B_OUTPUT', + 1: 'DPHY_DBG_OUTPUT', +} +DPHY_8B10B_OUTPUT = 0 +DPHY_DBG_OUTPUT = 1 +DPHY_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_CONT_EN' +DPHY_CRC_CONT_EN__enumvalues = { + 0: 'DPHY_CRC_ONE_SHOT', + 1: 'DPHY_CRC_CONTINUOUS', +} +DPHY_CRC_ONE_SHOT = 0 +DPHY_CRC_CONTINUOUS = 1 +DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_EN' +DPHY_CRC_EN__enumvalues = { + 0: 'DPHY_CRC_DISABLED', + 1: 'DPHY_CRC_ENABLED', +} +DPHY_CRC_DISABLED = 0 +DPHY_CRC_ENABLED = 1 +DPHY_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_FIELD' +DPHY_CRC_FIELD__enumvalues = { + 0: 'DPHY_CRC_START_FROM_TOP_FIELD', + 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', +} +DPHY_CRC_START_FROM_TOP_FIELD = 0 +DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 +DPHY_CRC_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' +DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { + 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', + 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', +} +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 +DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 +DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_SEL' +DPHY_CRC_SEL__enumvalues = { + 0: 'DPHY_CRC_LANE0_SELECTED', + 1: 'DPHY_CRC_LANE1_SELECTED', + 2: 'DPHY_CRC_LANE2_SELECTED', + 3: 'DPHY_CRC_LANE3_SELECTED', +} +DPHY_CRC_LANE0_SELECTED = 0 +DPHY_CRC_LANE1_SELECTED = 1 +DPHY_CRC_LANE2_SELECTED = 2 +DPHY_CRC_LANE3_SELECTED = 3 +DPHY_CRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_ENABLE' +DPHY_FEC_ENABLE__enumvalues = { + 0: 'DPHY_FEC_DISABLED', + 1: 'DPHY_FEC_ENABLED', +} +DPHY_FEC_DISABLED = 0 +DPHY_FEC_ENABLED = 1 +DPHY_FEC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_READY' +DPHY_FEC_READY__enumvalues = { + 0: 'DPHY_FEC_READY_EN', + 1: 'DPHY_FEC_READY_DIS', +} +DPHY_FEC_READY_EN = 0 +DPHY_FEC_READY_DIS = 1 +DPHY_FEC_READY = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_LOAD_BS_COUNT_START' +DPHY_LOAD_BS_COUNT_START__enumvalues = { + 0: 'DPHY_LOAD_BS_COUNT_STARTED', + 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', +} +DPHY_LOAD_BS_COUNT_STARTED = 0 +DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 +DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_EN' +DPHY_PRBS_EN__enumvalues = { + 0: 'DPHY_PRBS_DISABLE', + 1: 'DPHY_PRBS_ENABLE', +} +DPHY_PRBS_DISABLE = 0 +DPHY_PRBS_ENABLE = 1 +DPHY_PRBS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_SEL' +DPHY_PRBS_SEL__enumvalues = { + 0: 'DPHY_PRBS7_SELECTED', + 1: 'DPHY_PRBS23_SELECTED', + 2: 'DPHY_PRBS11_SELECTED', +} +DPHY_PRBS7_SELECTED = 0 +DPHY_PRBS23_SELECTED = 1 +DPHY_PRBS11_SELECTED = 2 +DPHY_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' +DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { + 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 1: 'DPHY_FAST_TRAINING_CAPABLE', +} +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 +DPHY_FAST_TRAINING_CAPABLE = 1 +DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' +DPHY_SCRAMBLER_ADVANCE__enumvalues = { + 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', +} +DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 +DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 +DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_DIS' +DPHY_SCRAMBLER_DIS__enumvalues = { + 0: 'DPHY_SCR_ENABLED', + 1: 'DPHY_SCR_DISABLED', +} +DPHY_SCR_ENABLED = 0 +DPHY_SCR_DISABLED = 1 +DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_KCODE' +DPHY_SCRAMBLER_KCODE__enumvalues = { + 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', + 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', +} +DPHY_SCRAMBLER_KCODE_DISABLED = 0 +DPHY_SCRAMBLER_KCODE_ENABLED = 1 +DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_SEL' +DPHY_SCRAMBLER_SEL__enumvalues = { + 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', + 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', +} +DPHY_SCRAMBLER_SEL_LANE_DATA = 0 +DPHY_SCRAMBLER_SEL_DBG_DATA = 1 +DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SKEW_BYPASS' +DPHY_SKEW_BYPASS__enumvalues = { + 0: 'DPHY_WITH_SKEW', + 1: 'DPHY_NO_SKEW', +} +DPHY_WITH_SKEW = 0 +DPHY_NO_SKEW = 1 +DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM' +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = { + 0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', +} +DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SW_FAST_TRAINING_START' +DPHY_SW_FAST_TRAINING_START__enumvalues = { + 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 1: 'DPHY_SW_FAST_TRAINING_STARTED', +} +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 +DPHY_SW_FAST_TRAINING_STARTED = 1 +DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' +DPHY_TRAINING_PATTERN_SEL__enumvalues = { + 0: 'DPHY_TRAINING_PATTERN_1', + 1: 'DPHY_TRAINING_PATTERN_2', + 2: 'DPHY_TRAINING_PATTERN_3', + 3: 'DPHY_TRAINING_PATTERN_4', +} +DPHY_TRAINING_PATTERN_1 = 0 +DPHY_TRAINING_PATTERN_2 = 1 +DPHY_TRAINING_PATTERN_3 = 2 +DPHY_TRAINING_PATTERN_4 = 3 +DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPONENT_DEPTH' +DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_COMPONENT_DEPTH_6BPC', + 1: 'DP_COMPONENT_DEPTH_8BPC', + 2: 'DP_COMPONENT_DEPTH_10BPC', + 3: 'DP_COMPONENT_DEPTH_12BPC', + 4: 'DP_COMPONENT_DEPTH_16BPC', +} +DP_COMPONENT_DEPTH_6BPC = 0 +DP_COMPONENT_DEPTH_8BPC = 1 +DP_COMPONENT_DEPTH_10BPC = 2 +DP_COMPONENT_DEPTH_12BPC = 3 +DP_COMPONENT_DEPTH_16BPC = 4 +DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DP_CP_ENCRYPTION_TYPE' +DP_CP_ENCRYPTION_TYPE__enumvalues = { + 0: 'DP_CP_ENCRYPTION_TYPE_0', + 1: 'DP_CP_ENCRYPTION_TYPE_1', +} +DP_CP_ENCRYPTION_TYPE_0 = 0 +DP_CP_ENCRYPTION_TYPE_1 = 1 +DP_CP_ENCRYPTION_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' +DP_DPHY_8B10B_EXT_DISP__enumvalues = { + 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', +} +DP_DPHY_8B10B_EXT_DISP_ZERO = 0 +DP_DPHY_8B10B_EXT_DISP_ONE = 1 +DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' +DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' +DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', +} +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' +DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { + 0: 'DP_DPHY_HBR2_PASS_THROUGH', + 1: 'DP_DPHY_HBR2_PATTERN_1', + 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', + 3: 'DP_DPHY_HBR2_PATTERN_3', + 6: 'DP_DPHY_HBR2_PATTERN_2_POS', +} +DP_DPHY_HBR2_PASS_THROUGH = 0 +DP_DPHY_HBR2_PATTERN_1 = 1 +DP_DPHY_HBR2_PATTERN_2_NEG = 2 +DP_DPHY_HBR2_PATTERN_3 = 3 +DP_DPHY_HBR2_PATTERN_2_POS = 6 +DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DSC_MODE' +DP_DSC_MODE__enumvalues = { + 0: 'DP_DSC_DISABLE', + 1: 'DP_DSC_444_SIMPLE_422', + 2: 'DP_DSC_NATIVE_422_420', +} +DP_DSC_DISABLE = 0 +DP_DSC_444_SIMPLE_422 = 1 +DP_DSC_NATIVE_422_420 = 2 +DP_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_EMBEDDED_PANEL_MODE' +DP_EMBEDDED_PANEL_MODE__enumvalues = { + 0: 'DP_EXTERNAL_PANEL', + 1: 'DP_EMBEDDED_PANEL', +} +DP_EXTERNAL_PANEL = 0 +DP_EMBEDDED_PANEL = 1 +DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_COMPLETE' +DP_LINK_TRAINING_COMPLETE__enumvalues = { + 0: 'DP_LINK_TRAINING_NOT_COMPLETE', + 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', +} +DP_LINK_TRAINING_NOT_COMPLETE = 0 +DP_LINK_TRAINING_ALREADY_COMPLETE = 1 +DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' +DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { + 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', +} +DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 +DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 +DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_ML_PHY_SEQ_MODE' +DP_ML_PHY_SEQ_MODE__enumvalues = { + 0: 'DP_ML_PHY_SEQ_LINE_NUM', + 1: 'DP_ML_PHY_SEQ_IMMEDIATE', +} +DP_ML_PHY_SEQ_LINE_NUM = 0 +DP_ML_PHY_SEQ_IMMEDIATE = 1 +DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' +DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { + 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', + 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', +} +MSA_V_TIMING_OVERRIDE_DISABLED = 0 +MSA_V_TIMING_OVERRIDE_ENABLED = 1 +DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_BLANK_CODE' +DP_MSE_BLANK_CODE__enumvalues = { + 0: 'DP_MSE_BLANK_CODE_SF_FILLED', + 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', +} +DP_MSE_BLANK_CODE_SF_FILLED = 0 +DP_MSE_BLANK_CODE_ZERO_FILLED = 1 +DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_LINK_LINE' +DP_MSE_LINK_LINE__enumvalues = { + 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', + 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', + 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', + 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', +} +DP_MSE_LINK_LINE_32_MTP_LONG = 0 +DP_MSE_LINK_LINE_64_MTP_LONG = 1 +DP_MSE_LINK_LINE_128_MTP_LONG = 2 +DP_MSE_LINK_LINE_256_MTP_LONG = 3 +DP_MSE_LINK_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT0' +DP_MSE_SAT_ENCRYPT0__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT0_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT0_ENABLED', +} +DP_MSE_SAT_ENCRYPT0_DISABLED = 0 +DP_MSE_SAT_ENCRYPT0_ENABLED = 1 +DP_MSE_SAT_ENCRYPT0 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT1' +DP_MSE_SAT_ENCRYPT1__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT1_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT1_ENABLED', +} +DP_MSE_SAT_ENCRYPT1_DISABLED = 0 +DP_MSE_SAT_ENCRYPT1_ENABLED = 1 +DP_MSE_SAT_ENCRYPT1 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT2' +DP_MSE_SAT_ENCRYPT2__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT2_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT2_ENABLED', +} +DP_MSE_SAT_ENCRYPT2_DISABLED = 0 +DP_MSE_SAT_ENCRYPT2_ENABLED = 1 +DP_MSE_SAT_ENCRYPT2 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT3' +DP_MSE_SAT_ENCRYPT3__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT3_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT3_ENABLED', +} +DP_MSE_SAT_ENCRYPT3_DISABLED = 0 +DP_MSE_SAT_ENCRYPT3_ENABLED = 1 +DP_MSE_SAT_ENCRYPT3 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT4' +DP_MSE_SAT_ENCRYPT4__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT4_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT4_ENABLED', +} +DP_MSE_SAT_ENCRYPT4_DISABLED = 0 +DP_MSE_SAT_ENCRYPT4_ENABLED = 1 +DP_MSE_SAT_ENCRYPT4 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT5' +DP_MSE_SAT_ENCRYPT5__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT5_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT5_ENABLED', +} +DP_MSE_SAT_ENCRYPT5_DISABLED = 0 +DP_MSE_SAT_ENCRYPT5_ENABLED = 1 +DP_MSE_SAT_ENCRYPT5 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' +DP_MSE_SAT_UPDATE_ACT__enumvalues = { + 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', + 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', +} +DP_MSE_SAT_UPDATE_NO_ACTION = 0 +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 +DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_TIMESTAMP_MODE' +DP_MSE_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', +} +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 +DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_ZERO_ENCODER' +DP_MSE_ZERO_ENCODER__enumvalues = { + 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', + 1: 'DP_MSE_ZERO_FE_ENCODER', +} +DP_MSE_NOT_ZERO_FE_ENCODER = 0 +DP_MSE_ZERO_FE_ENCODER = 1 +DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' +DP_MSO_NUM_OF_SST_LINKS__enumvalues = { + 0: 'DP_MSO_ONE_SSTLINK', + 1: 'DP_MSO_TWO_SSTLINK', + 2: 'DP_MSO_FOUR_SSTLINK', +} +DP_MSO_ONE_SSTLINK = 0 +DP_MSO_TWO_SSTLINK = 1 +DP_MSO_FOUR_SSTLINK = 2 +DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING' +DP_PIXEL_ENCODING__enumvalues = { + 0: 'DP_PIXEL_ENCODING_RGB444', + 1: 'DP_PIXEL_ENCODING_YCBCR422', + 2: 'DP_PIXEL_ENCODING_YCBCR444', + 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 4: 'DP_PIXEL_ENCODING_Y_ONLY', + 5: 'DP_PIXEL_ENCODING_YCBCR420', +} +DP_PIXEL_ENCODING_RGB444 = 0 +DP_PIXEL_ENCODING_YCBCR422 = 1 +DP_PIXEL_ENCODING_YCBCR444 = 2 +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 +DP_PIXEL_ENCODING_Y_ONLY = 4 +DP_PIXEL_ENCODING_YCBCR420 = 5 +DP_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM' +DP_PIXEL_PER_CYCLE_PROCESSING_NUM__enumvalues = { + 0: 'DP_ONE_PIXEL_PER_CYCLE', + 1: 'DP_TWO_PIXEL_PER_CYCLE', +} +DP_ONE_PIXEL_PER_CYCLE = 0 +DP_TWO_PIXEL_PER_CYCLE = 1 +DP_PIXEL_PER_CYCLE_PROCESSING_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_PRIORITY' +DP_SEC_ASP_PRIORITY__enumvalues = { + 0: 'DP_SEC_ASP_LOW_PRIORITY', + 1: 'DP_SEC_ASP_HIGH_PRIORITY', +} +DP_SEC_ASP_LOW_PRIORITY = 0 +DP_SEC_ASP_HIGH_PRIORITY = 1 +DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_AUDIO_MUTE' +DP_SEC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', + 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', +} +DP_SEC_AUDIO_MUTE_HW_CTRL = 0 +DP_SEC_AUDIO_MUTE_SW_CTRL = 1 +DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_COLLISION_ACK' +DP_SEC_COLLISION_ACK__enumvalues = { + 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', + 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', +} +DP_SEC_COLLISION_ACK_NO_EFFECT = 0 +DP_SEC_COLLISION_ACK_CLR_FLAG = 1 +DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_PRIORITY' +DP_SEC_GSP0_PRIORITY__enumvalues = { + 0: 'SEC_GSP0_PRIORITY_LOW', + 1: 'SEC_GSP0_PRIORITY_HIGH', +} +SEC_GSP0_PRIORITY_LOW = 0 +SEC_GSP0_PRIORITY_HIGH = 1 +DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND' +DP_SEC_GSP_SEND__enumvalues = { + 0: 'NOT_SENT', + 1: 'FORCE_SENT', +} +NOT_SENT = 0 +FORCE_SENT = 1 +DP_SEC_GSP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' +DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { + 0: 'SEND_AT_LINK_NUMBER', + 1: 'SEND_AT_EARLIEST_TIME', +} +SEND_AT_LINK_NUMBER = 0 +SEND_AT_EARLIEST_TIME = 1 +DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_PPS' +DP_SEC_GSP_SEND_PPS__enumvalues = { + 0: 'SEND_NORMAL_PACKET', + 1: 'SEND_PPS_PACKET', +} +SEND_NORMAL_PACKET = 0 +SEND_PPS_PACKET = 1 +DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_LINE_REFERENCE' +DP_SEC_LINE_REFERENCE__enumvalues = { + 0: 'REFER_TO_DP_SOF', + 1: 'REFER_TO_OTG_SOF', +} +REFER_TO_DP_SOF = 0 +REFER_TO_OTG_SOF = 1 +DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_TIMESTAMP_MODE' +DP_SEC_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', +} +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 +DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_ACK' +DP_STEER_OVERFLOW_ACK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_MASK' +DP_STEER_OVERFLOW_MASK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_MASKED', + 1: 'DP_STEER_OVERFLOW_UNMASK', +} +DP_STEER_OVERFLOW_MASKED = 0 +DP_STEER_OVERFLOW_UNMASK = 1 +DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SYNC_POLARITY' +DP_SYNC_POLARITY__enumvalues = { + 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', + 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', +} +DP_SYNC_POLARITY_ACTIVE_HIGH = 0 +DP_SYNC_POLARITY_ACTIVE_LOW = 1 +DP_SYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_TU_OVERFLOW_ACK' +DP_TU_OVERFLOW_ACK__enumvalues = { + 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_UDI_LANES' +DP_UDI_LANES__enumvalues = { + 0: 'DP_UDI_1_LANE', + 1: 'DP_UDI_2_LANES', + 2: 'DP_UDI_LANES_RESERVED', + 3: 'DP_UDI_4_LANES', +} +DP_UDI_1_LANE = 0 +DP_UDI_2_LANES = 1 +DP_UDI_LANES_RESERVED = 2 +DP_UDI_4_LANES = 3 +DP_UDI_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' +DP_VID_ENHANCED_FRAME_MODE__enumvalues = { + 0: 'VID_NORMAL_FRAME_MODE', + 1: 'VID_ENHANCED_MODE', +} +VID_NORMAL_FRAME_MODE = 0 +VID_ENHANCED_MODE = 1 +DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' +DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { + 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', +} +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 +DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_GEN_EN' +DP_VID_M_N_GEN_EN__enumvalues = { + 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', + 1: 'DP_VID_M_N_CALC_AUTO', +} +DP_VID_M_N_PROGRAMMED_VIA_REG = 0 +DP_VID_M_N_CALC_AUTO = 1 +DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_N_MUL' +DP_VID_N_MUL__enumvalues = { + 0: 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 1: 'DP_VID_M_2X_INPUT_PIXEL_RATE', + 2: 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 3: 'DP_VID_M_8X_INPUT_PIXEL_RATE', +} +DP_VID_M_1X_INPUT_PIXEL_RATE = 0 +DP_VID_M_2X_INPUT_PIXEL_RATE = 1 +DP_VID_M_4X_INPUT_PIXEL_RATE = 2 +DP_VID_M_8X_INPUT_PIXEL_RATE = 3 +DP_VID_N_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' +DP_VID_STREAM_DISABLE_ACK__enumvalues = { + 0: 'ID_STREAM_DISABLE_NO_ACK', + 1: 'ID_STREAM_DISABLE_ACKED', +} +ID_STREAM_DISABLE_NO_ACK = 0 +ID_STREAM_DISABLE_ACKED = 1 +DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' +DP_VID_STREAM_DISABLE_MASK__enumvalues = { + 0: 'VID_STREAM_DISABLE_MASKED', + 1: 'VID_STREAM_DISABLE_UNMASK', +} +VID_STREAM_DISABLE_MASKED = 0 +VID_STREAM_DISABLE_UNMASK = 1 +DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DIS_DEFER' +DP_VID_STREAM_DIS_DEFER__enumvalues = { + 0: 'DP_VID_STREAM_DIS_NO_DEFER', + 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', +} +DP_VID_STREAM_DIS_NO_DEFER = 0 +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 +DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_VBID_FIELD_POL' +DP_VID_VBID_FIELD_POL__enumvalues = { + 0: 'DP_VID_VBID_FIELD_POL_NORMAL', + 1: 'DP_VID_VBID_FIELD_POL_INV', +} +DP_VID_VBID_FIELD_POL_NORMAL = 0 +DP_VID_VBID_FIELD_POL_INV = 1 +DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum + +# values for enumeration 'FEC_ACTIVE_STATUS' +FEC_ACTIVE_STATUS__enumvalues = { + 0: 'DPHY_FEC_NOT_ACTIVE', + 1: 'DPHY_FEC_ACTIVE', +} +DPHY_FEC_NOT_ACTIVE = 0 +DPHY_FEC_ACTIVE = 1 +FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' +DIG_BE_CNTL_HPD_SELECT__enumvalues = { + 0: 'DIG_BE_CNTL_HPD1', + 1: 'DIG_BE_CNTL_HPD2', + 2: 'DIG_BE_CNTL_HPD3', + 3: 'DIG_BE_CNTL_HPD4', + 4: 'DIG_BE_CNTL_HPD5', + 5: 'DIG_BE_CNTL_NO_HPD', +} +DIG_BE_CNTL_HPD1 = 0 +DIG_BE_CNTL_HPD2 = 1 +DIG_BE_CNTL_HPD3 = 2 +DIG_BE_CNTL_HPD4 = 3 +DIG_BE_CNTL_HPD5 = 4 +DIG_BE_CNTL_NO_HPD = 5 +DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_MODE' +DIG_BE_CNTL_MODE__enumvalues = { + 0: 'DIG_BE_DP_SST_MODE', + 1: 'DIG_BE_RESERVED1', + 2: 'DIG_BE_TMDS_DVI_MODE', + 3: 'DIG_BE_TMDS_HDMI_MODE', + 4: 'DIG_BE_RESERVED4', + 5: 'DIG_BE_DP_MST_MODE', + 6: 'DIG_BE_RESERVED2', + 7: 'DIG_BE_RESERVED3', +} +DIG_BE_DP_SST_MODE = 0 +DIG_BE_RESERVED1 = 1 +DIG_BE_TMDS_DVI_MODE = 2 +DIG_BE_TMDS_HDMI_MODE = 3 +DIG_BE_RESERVED4 = 4 +DIG_BE_DP_MST_MODE = 5 +DIG_BE_RESERVED2 = 6 +DIG_BE_RESERVED3 = 7 +DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE' +DIG_DIGITAL_BYPASS_ENABLE__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_OFF', + 1: 'DIG_DIGITAL_BYPASS_ON', +} +DIG_DIGITAL_BYPASS_OFF = 0 +DIG_DIGITAL_BYPASS_ON = 1 +DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' +DIG_DIGITAL_BYPASS_SEL__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', +} +DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 +DIG_DIGITAL_BYPASS_SEL_36BPP = 1 +DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 +DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 +DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 +DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 +DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 +DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' +DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { + 0: 'DIG_FE_SOURCE_FROM_OTG0', + 1: 'DIG_FE_SOURCE_FROM_OTG1', + 2: 'DIG_FE_SOURCE_FROM_OTG2', + 3: 'DIG_FE_SOURCE_FROM_OTG3', + 4: 'DIG_FE_SOURCE_RESERVED', +} +DIG_FE_SOURCE_FROM_OTG0 = 0 +DIG_FE_SOURCE_FROM_OTG1 = 1 +DIG_FE_SOURCE_FROM_OTG2 = 2 +DIG_FE_SOURCE_FROM_OTG3 = 3 +DIG_FE_SOURCE_RESERVED = 4 +DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' +DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { + 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', + 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', + 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', + 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', + 4: 'DIG_FE_STEREOSYNC_RESERVED', +} +DIG_FE_STEREOSYNC_FROM_OTG0 = 0 +DIG_FE_STEREOSYNC_FROM_OTG1 = 1 +DIG_FE_STEREOSYNC_FROM_OTG2 = 2 +DIG_FE_STEREOSYNC_FROM_OTG3 = 3 +DIG_FE_STEREOSYNC_RESERVED = 4 +DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX' +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', + 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', +} +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 +DIG_FIFO_FORCE_RECOMP_MINMAX = 1 +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL' +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', +} +DIG_FIFO_USE_OVERWRITE_LEVEL = 0 +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE' +DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', +} +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 +DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OUTPUT_PROCESSING_MODE' +DIG_FIFO_OUTPUT_PROCESSING_MODE__enumvalues = { + 0: 'DIG_FIFO_1_PIX_PER_CYCLE', + 1: 'DIG_FIFO_2_PIX_PER_CYCLE', +} +DIG_FIFO_1_PIX_PER_CYCLE = 0 +DIG_FIFO_2_PIX_PER_CYCLE = 1 +DIG_FIFO_OUTPUT_PROCESSING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR' +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DIG_FIFO_NO_ERROR_OCCURRED', + 1: 'DIG_FIFO_UNDERFLOW_OCCURRED', + 2: 'DIG_FIFO_OVERFLOW_OCCURRED', +} +DIG_FIFO_NO_ERROR_OCCURRED = 0 +DIG_FIFO_UNDERFLOW_OCCURRED = 1 +DIG_FIFO_OVERFLOW_OCCURRED = 2 +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' +DIG_FIFO_READ_CLOCK_SRC__enumvalues = { + 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', +} +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 +DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_INPUT_PIXEL_SEL' +DIG_INPUT_PIXEL_SEL__enumvalues = { + 0: 'DIG_ALL_PIXEL', + 1: 'DIG_EVEN_PIXEL_ONLY', + 2: 'DIG_ODD_PIXEL_ONLY', +} +DIG_ALL_PIXEL = 0 +DIG_EVEN_PIXEL_ONLY = 1 +DIG_ODD_PIXEL_ONLY = 2 +DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' +DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_ON_LINK0', + 1: 'DIG_OUTPUT_CRC_ON_LINK1', +} +DIG_OUTPUT_CRC_ON_LINK0 = 0 +DIG_OUTPUT_CRC_ON_LINK1 = 1 +DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' +DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 2: 'DIG_OUTPUT_CRC_FOR_VBI', + 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', +} +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 +DIG_OUTPUT_CRC_FOR_VBI = 2 +DIG_OUTPUT_CRC_FOR_AUDIO = 3 +DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' +DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', +} +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 +DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_SL_PIXEL_GROUPING' +DIG_SL_PIXEL_GROUPING__enumvalues = { + 0: 'DIG_SINGLETON_PIXELS', + 1: 'DIG_PAIR_PIXELS', +} +DIG_SINGLETON_PIXELS = 0 +DIG_PAIR_PIXELS = 1 +DIG_SL_PIXEL_GROUPING = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' +DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', +} +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 +DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { + 0: 'DIG_10BIT_TEST_PATTERN', + 1: 'DIG_ALTERNATING_TEST_PATTERN', +} +DIG_10BIT_TEST_PATTERN = 0 +DIG_ALTERNATING_TEST_PATTERN = 1 +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_NORMAL', + 1: 'DIG_TEST_PATTERN_RANDOM', +} +DIG_TEST_PATTERN_NORMAL = 0 +DIG_TEST_PATTERN_RANDOM = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_ENABLED', + 1: 'DIG_RANDOM_PATTERN_RESETED', +} +DIG_RANDOM_PATTERN_ENABLED = 0 +DIG_RANDOM_PATTERN_RESETED = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_IN_NORMAL_OPERATION', + 1: 'DIG_IN_DEBUG_MODE', +} +DIG_IN_NORMAL_OPERATION = 0 +DIG_IN_DEBUG_MODE = 1 +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOLBY_VISION_ENABLE' +DOLBY_VISION_ENABLE__enumvalues = { + 0: 'DOLBY_VISION_DISABLED', + 1: 'DOLBY_VISION_ENABLED', +} +DOLBY_VISION_DISABLED = 0 +DOLBY_VISION_ENABLED = 1 +DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACP_SEND' +HDMI_ACP_SEND__enumvalues = { + 0: 'HDMI_ACP_NOT_SEND', + 1: 'HDMI_ACP_PKT_SEND', +} +HDMI_ACP_NOT_SEND = 0 +HDMI_ACP_PKT_SEND = 1 +HDMI_ACP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' +HDMI_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_CONT' +HDMI_ACR_CONT__enumvalues = { + 0: 'HDMI_ACR_CONT_DISABLE', + 1: 'HDMI_ACR_CONT_ENABLE', +} +HDMI_ACR_CONT_DISABLE = 0 +HDMI_ACR_CONT_ENABLE = 1 +HDMI_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_N_MULTIPLE' +HDMI_ACR_N_MULTIPLE__enumvalues = { + 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', + 1: 'HDMI_ACR_1_MULTIPLE', + 2: 'HDMI_ACR_2_MULTIPLE', + 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', + 4: 'HDMI_ACR_4_MULTIPLE', + 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', + 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', + 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', +} +HDMI_ACR_0_MULTIPLE_RESERVED = 0 +HDMI_ACR_1_MULTIPLE = 1 +HDMI_ACR_2_MULTIPLE = 2 +HDMI_ACR_3_MULTIPLE_RESERVED = 3 +HDMI_ACR_4_MULTIPLE = 4 +HDMI_ACR_5_MULTIPLE_RESERVED = 5 +HDMI_ACR_6_MULTIPLE_RESERVED = 6 +HDMI_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SELECT' +HDMI_ACR_SELECT__enumvalues = { + 0: 'HDMI_ACR_SELECT_HW', + 1: 'HDMI_ACR_SELECT_32K', + 2: 'HDMI_ACR_SELECT_44K', + 3: 'HDMI_ACR_SELECT_48K', +} +HDMI_ACR_SELECT_HW = 0 +HDMI_ACR_SELECT_32K = 1 +HDMI_ACR_SELECT_44K = 2 +HDMI_ACR_SELECT_48K = 3 +HDMI_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SEND' +HDMI_ACR_SEND__enumvalues = { + 0: 'HDMI_ACR_NOT_SEND', + 1: 'HDMI_ACR_PKT_SEND', +} +HDMI_ACR_NOT_SEND = 0 +HDMI_ACR_PKT_SEND = 1 +HDMI_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SOURCE' +HDMI_ACR_SOURCE__enumvalues = { + 0: 'HDMI_ACR_SOURCE_HW', + 1: 'HDMI_ACR_SOURCE_SW', +} +HDMI_ACR_SOURCE_HW = 0 +HDMI_ACR_SOURCE_SW = 1 +HDMI_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_DELAY_EN' +HDMI_AUDIO_DELAY_EN__enumvalues = { + 0: 'HDMI_AUDIO_DELAY_DISABLE', + 1: 'HDMI_AUDIO_DELAY_58CLK', + 2: 'HDMI_AUDIO_DELAY_56CLK', + 3: 'HDMI_AUDIO_DELAY_RESERVED', +} +HDMI_AUDIO_DELAY_DISABLE = 0 +HDMI_AUDIO_DELAY_58CLK = 1 +HDMI_AUDIO_DELAY_56CLK = 2 +HDMI_AUDIO_DELAY_RESERVED = 3 +HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_CONT' +HDMI_AUDIO_INFO_CONT__enumvalues = { + 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', + 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', +} +HDMI_AUDIO_INFO_CONT_DISABLE = 0 +HDMI_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_SEND' +HDMI_AUDIO_INFO_SEND__enumvalues = { + 0: 'HDMI_AUDIO_INFO_NOT_SEND', + 1: 'HDMI_AUDIO_INFO_PKT_SEND', +} +HDMI_AUDIO_INFO_NOT_SEND = 0 +HDMI_AUDIO_INFO_PKT_SEND = 1 +HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' +HDMI_CLOCK_CHANNEL_RATE__enumvalues = { + 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', +} +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 +HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' +HDMI_DATA_SCRAMBLE_EN__enumvalues = { + 0: 'HDMI_DATA_SCRAMBLE_DISABLE', + 1: 'HDMI_DATA_SCRAMBLE_ENABLE', +} +HDMI_DATA_SCRAMBLE_DISABLE = 0 +HDMI_DATA_SCRAMBLE_ENABLE = 1 +HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' +HDMI_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', +} +HDMI_DEEP_COLOR_DEPTH_24BPP = 0 +HDMI_DEEP_COLOR_DEPTH_30BPP = 1 +HDMI_DEEP_COLOR_DEPTH_36BPP = 2 +HDMI_DEEP_COLOR_DEPTH_48BPP = 3 +HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEFAULT_PAHSE' +HDMI_DEFAULT_PAHSE__enumvalues = { + 0: 'HDMI_DEFAULT_PHASE_IS_0', + 1: 'HDMI_DEFAULT_PHASE_IS_1', +} +HDMI_DEFAULT_PHASE_IS_0 = 0 +HDMI_DEFAULT_PHASE_IS_1 = 1 +HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_ACK' +HDMI_ERROR_ACK__enumvalues = { + 0: 'HDMI_ERROR_ACK_INT', + 1: 'HDMI_ERROR_NOT_ACK', +} +HDMI_ERROR_ACK_INT = 0 +HDMI_ERROR_NOT_ACK = 1 +HDMI_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_MASK' +HDMI_ERROR_MASK__enumvalues = { + 0: 'HDMI_ERROR_MASK_INT', + 1: 'HDMI_ERROR_NOT_MASK', +} +HDMI_ERROR_MASK_INT = 0 +HDMI_ERROR_NOT_MASK = 1 +HDMI_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE' +HDMI_GC_AVMUTE__enumvalues = { + 0: 'HDMI_GC_AVMUTE_SET', + 1: 'HDMI_GC_AVMUTE_UNSET', +} +HDMI_GC_AVMUTE_SET = 0 +HDMI_GC_AVMUTE_UNSET = 1 +HDMI_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE_CONT' +HDMI_GC_AVMUTE_CONT__enumvalues = { + 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', + 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', +} +HDMI_GC_AVMUTE_CONT_DISABLE = 0 +HDMI_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_CONT' +HDMI_GC_CONT__enumvalues = { + 0: 'HDMI_GC_CONT_DISABLE', + 1: 'HDMI_GC_CONT_ENABLE', +} +HDMI_GC_CONT_DISABLE = 0 +HDMI_GC_CONT_ENABLE = 1 +HDMI_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_SEND' +HDMI_GC_SEND__enumvalues = { + 0: 'HDMI_GC_NOT_SEND', + 1: 'HDMI_GC_PKT_SEND', +} +HDMI_GC_NOT_SEND = 0 +HDMI_GC_PKT_SEND = 1 +HDMI_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_CONT' +HDMI_GENERIC_CONT__enumvalues = { + 0: 'HDMI_GENERIC_CONT_DISABLE', + 1: 'HDMI_GENERIC_CONT_ENABLE', +} +HDMI_GENERIC_CONT_DISABLE = 0 +HDMI_GENERIC_CONT_ENABLE = 1 +HDMI_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_SEND' +HDMI_GENERIC_SEND__enumvalues = { + 0: 'HDMI_GENERIC_NOT_SEND', + 1: 'HDMI_GENERIC_PKT_SEND', +} +HDMI_GENERIC_NOT_SEND = 0 +HDMI_GENERIC_PKT_SEND = 1 +HDMI_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_CONT' +HDMI_ISRC_CONT__enumvalues = { + 0: 'HDMI_ISRC_CONT_DISABLE', + 1: 'HDMI_ISRC_CONT_ENABLE', +} +HDMI_ISRC_CONT_DISABLE = 0 +HDMI_ISRC_CONT_ENABLE = 1 +HDMI_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_SEND' +HDMI_ISRC_SEND__enumvalues = { + 0: 'HDMI_ISRC_NOT_SEND', + 1: 'HDMI_ISRC_PKT_SEND', +} +HDMI_ISRC_NOT_SEND = 0 +HDMI_ISRC_PKT_SEND = 1 +HDMI_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_KEEPOUT_MODE' +HDMI_KEEPOUT_MODE__enumvalues = { + 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', +} +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 +HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_METADATA_ENABLE' +HDMI_METADATA_ENABLE__enumvalues = { + 0: 'HDMI_METADATA_NOT_SEND', + 1: 'HDMI_METADATA_PKT_SEND', +} +HDMI_METADATA_NOT_SEND = 0 +HDMI_METADATA_PKT_SEND = 1 +HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_CONT' +HDMI_MPEG_INFO_CONT__enumvalues = { + 0: 'HDMI_MPEG_INFO_CONT_DISABLE', + 1: 'HDMI_MPEG_INFO_CONT_ENABLE', +} +HDMI_MPEG_INFO_CONT_DISABLE = 0 +HDMI_MPEG_INFO_CONT_ENABLE = 1 +HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_SEND' +HDMI_MPEG_INFO_SEND__enumvalues = { + 0: 'HDMI_MPEG_INFO_NOT_SEND', + 1: 'HDMI_MPEG_INFO_PKT_SEND', +} +HDMI_MPEG_INFO_NOT_SEND = 0 +HDMI_MPEG_INFO_PKT_SEND = 1 +HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' +HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { + 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', + 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', +} +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 +HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NULL_SEND' +HDMI_NULL_SEND__enumvalues = { + 0: 'HDMI_NULL_NOT_SEND', + 1: 'HDMI_NULL_PKT_SEND', +} +HDMI_NULL_NOT_SEND = 0 +HDMI_NULL_PKT_SEND = 1 +HDMI_NULL_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_GEN_VERSION' +HDMI_PACKET_GEN_VERSION__enumvalues = { + 0: 'HDMI_PACKET_GEN_VERSION_OLD', + 1: 'HDMI_PACKET_GEN_VERSION_NEW', +} +HDMI_PACKET_GEN_VERSION_OLD = 0 +HDMI_PACKET_GEN_VERSION_NEW = 1 +HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' +HDMI_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'HDMI_PKT_LINE_REF_VSYNC', + 1: 'HDMI_PKT_LINE_REF_OTGSOF', +} +HDMI_PKT_LINE_REF_VSYNC = 0 +HDMI_PKT_LINE_REF_OTGSOF = 1 +HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' +HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { + 0: 'HDMI_PACKING_PHASE_SET_BY_HW', + 1: 'HDMI_PACKING_PHASE_SET_BY_SW', +} +HDMI_PACKING_PHASE_SET_BY_HW = 0 +HDMI_PACKING_PHASE_SET_BY_SW = 1 +HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', +} +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_COLOR_FORMAT' +TMDS_COLOR_FORMAT__enumvalues = { + 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', + 3: 'TMDS_COLOR_FORMAT_RESERVED', +} +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 +TMDS_COLOR_FORMAT_DUAL30BPP = 2 +TMDS_COLOR_FORMAT_RESERVED = 3 +TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_INVERT' +TMDS_CTL0_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL0_DATA_NORMAL', + 1: 'TMDS_CTL0_DATA_INVERT_EN', +} +TMDS_CTL0_DATA_NORMAL = 0 +TMDS_CTL0_DATA_INVERT_EN = 1 +TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_MODULATION' +TMDS_CTL0_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', +} +TMDS_CTL0_DATA_MODULATION_DISABLE = 0 +TMDS_CTL0_DATA_MODULATION_BIT0 = 1 +TMDS_CTL0_DATA_MODULATION_BIT1 = 2 +TMDS_CTL0_DATA_MODULATION_BIT2 = 3 +TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_SEL' +TMDS_CTL0_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', +} +TMDS_CTL0_DATA_SEL0_RESERVED = 0 +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL0_DATA_SEL2_VSYNC = 2 +TMDS_CTL0_DATA_SEL3_RESERVED = 3 +TMDS_CTL0_DATA_SEL4_HSYNC = 4 +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 +TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' +TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', +} +TMDS_CTL0_PATTERN_OUT_DISABLE = 0 +TMDS_CTL0_PATTERN_OUT_ENABLE = 1 +TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_INVERT' +TMDS_CTL1_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL1_DATA_NORMAL', + 1: 'TMDS_CTL1_DATA_INVERT_EN', +} +TMDS_CTL1_DATA_NORMAL = 0 +TMDS_CTL1_DATA_INVERT_EN = 1 +TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_MODULATION' +TMDS_CTL1_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', +} +TMDS_CTL1_DATA_MODULATION_DISABLE = 0 +TMDS_CTL1_DATA_MODULATION_BIT0 = 1 +TMDS_CTL1_DATA_MODULATION_BIT1 = 2 +TMDS_CTL1_DATA_MODULATION_BIT2 = 3 +TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_SEL' +TMDS_CTL1_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL1_DATA_SEL0_RESERVED = 0 +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL1_DATA_SEL2_VSYNC = 2 +TMDS_CTL1_DATA_SEL3_RESERVED = 3 +TMDS_CTL1_DATA_SEL4_HSYNC = 4 +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' +TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', +} +TMDS_CTL1_PATTERN_OUT_DISABLE = 0 +TMDS_CTL1_PATTERN_OUT_ENABLE = 1 +TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_INVERT' +TMDS_CTL2_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL2_DATA_NORMAL', + 1: 'TMDS_CTL2_DATA_INVERT_EN', +} +TMDS_CTL2_DATA_NORMAL = 0 +TMDS_CTL2_DATA_INVERT_EN = 1 +TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_MODULATION' +TMDS_CTL2_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', +} +TMDS_CTL2_DATA_MODULATION_DISABLE = 0 +TMDS_CTL2_DATA_MODULATION_BIT0 = 1 +TMDS_CTL2_DATA_MODULATION_BIT1 = 2 +TMDS_CTL2_DATA_MODULATION_BIT2 = 3 +TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_SEL' +TMDS_CTL2_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL2_DATA_SEL0_RESERVED = 0 +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL2_DATA_SEL2_VSYNC = 2 +TMDS_CTL2_DATA_SEL3_RESERVED = 3 +TMDS_CTL2_DATA_SEL4_HSYNC = 4 +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' +TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', +} +TMDS_CTL2_PATTERN_OUT_DISABLE = 0 +TMDS_CTL2_PATTERN_OUT_ENABLE = 1 +TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_INVERT' +TMDS_CTL3_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL3_DATA_NORMAL', + 1: 'TMDS_CTL3_DATA_INVERT_EN', +} +TMDS_CTL3_DATA_NORMAL = 0 +TMDS_CTL3_DATA_INVERT_EN = 1 +TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_MODULATION' +TMDS_CTL3_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', +} +TMDS_CTL3_DATA_MODULATION_DISABLE = 0 +TMDS_CTL3_DATA_MODULATION_BIT0 = 1 +TMDS_CTL3_DATA_MODULATION_BIT1 = 2 +TMDS_CTL3_DATA_MODULATION_BIT2 = 3 +TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_SEL' +TMDS_CTL3_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL3_DATA_SEL0_RESERVED = 0 +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL3_DATA_SEL2_VSYNC = 2 +TMDS_CTL3_DATA_SEL3_RESERVED = 3 +TMDS_CTL3_DATA_SEL4_HSYNC = 4 +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' +TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', +} +TMDS_CTL3_PATTERN_OUT_DISABLE = 0 +TMDS_CTL3_PATTERN_OUT_ENABLE = 1 +TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' +TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { + 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', +} +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_PIXEL_ENCODING' +TMDS_PIXEL_ENCODING__enumvalues = { + 0: 'TMDS_PIXEL_ENCODING_444_OR_420', + 1: 'TMDS_PIXEL_ENCODING_422', +} +TMDS_PIXEL_ENCODING_444_OR_420 = 0 +TMDS_PIXEL_ENCODING_422 = 1 +TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' +TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', +} +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 +TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' +TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', + 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', +} +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 +TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' +TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { + 0: 'TMDS_STEREOSYNC_CTL0', + 1: 'TMDS_STEREOSYNC_CTL1', + 2: 'TMDS_STEREOSYNC_CTL2', + 3: 'TMDS_STEREOSYNC_CTL3', +} +TMDS_STEREOSYNC_CTL0 = 0 +TMDS_STEREOSYNC_CTL1 = 1 +TMDS_STEREOSYNC_CTL2 = 2 +TMDS_STEREOSYNC_CTL3 = 3 +TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_SYNC_PHASE' +TMDS_SYNC_PHASE__enumvalues = { + 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', +} +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TMDS_SYNC_PHASE_ON_FRAME_START = 1 +TMDS_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' +TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' +TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', +} +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', +} +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', +} +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', +} +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' +DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', +} +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 +DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', +} +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', +} +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_STATUS' +DP_AUX_ARB_STATUS__enumvalues = { + 0: 'DP_AUX_IDLE', + 1: 'DP_AUX_IN_USE_LS', + 2: 'DP_AUX_IN_USE_GTC', + 3: 'DP_AUX_IN_USE_SW', + 4: 'DP_AUX_IN_USE_PHYWAKE', +} +DP_AUX_IDLE = 0 +DP_AUX_IN_USE_LS = 1 +DP_AUX_IN_USE_GTC = 2 +DP_AUX_IN_USE_SW = 3 +DP_AUX_IN_USE_PHYWAKE = 4 +DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' +DP_AUX_CONTROL_HPD_SEL__enumvalues = { + 0: 'DP_AUX_CONTROL_HPD1_SELECTED', + 1: 'DP_AUX_CONTROL_HPD2_SELECTED', + 2: 'DP_AUX_CONTROL_HPD3_SELECTED', + 3: 'DP_AUX_CONTROL_HPD4_SELECTED', + 4: 'DP_AUX_CONTROL_HPD5_SELECTED', + 5: 'DP_AUX_CONTROL_NO_HPD_SELECTED', +} +DP_AUX_CONTROL_HPD1_SELECTED = 0 +DP_AUX_CONTROL_HPD2_SELECTED = 1 +DP_AUX_CONTROL_HPD3_SELECTED = 2 +DP_AUX_CONTROL_HPD4_SELECTED = 3 +DP_AUX_CONTROL_HPD5_SELECTED = 4 +DP_AUX_CONTROL_NO_HPD_SELECTED = 5 +DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' +DP_AUX_CONTROL_TEST_MODE__enumvalues = { + 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', +} +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 +DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 +DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' +DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { + 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', +} +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 +DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', +} +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', +} +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { + 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', +} +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', +} +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' +DP_AUX_ERR_OCCURRED_ACK__enumvalues = { + 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 1: 'DP_AUX_ERR_OCCURRED__ACK', +} +DP_AUX_ERR_OCCURRED__NOT_ACK = 0 +DP_AUX_ERR_OCCURRED__ACK = 1 +DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', +} +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', +} +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', +} +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', +} +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_INT_ACK' +DP_AUX_INT_ACK__enumvalues = { + 0: 'DP_AUX_INT__NOT_ACK', + 1: 'DP_AUX_INT__ACK', +} +DP_AUX_INT__NOT_ACK = 0 +DP_AUX_INT__ACK = 1 +DP_AUX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_LS_UPDATE_ACK' +DP_AUX_LS_UPDATE_ACK__enumvalues = { + 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', + 1: 'DP_AUX_INT_LS_UPDATE_ACK', +} +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 +DP_AUX_INT_LS_UPDATE_ACK = 1 +DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' +DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { + 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', +} +DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 +DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 +DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' +DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { + 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', + 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', +} +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 +DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET' +DP_AUX_RESET__enumvalues = { + 0: 'DP_AUX_RESET_DEASSERTED', + 1: 'DP_AUX_RESET_ASSERTED', +} +DP_AUX_RESET_DEASSERTED = 0 +DP_AUX_RESET_ASSERTED = 1 +DP_AUX_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET_DONE' +DP_AUX_RESET_DONE__enumvalues = { + 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 1: 'DP_AUX_RESET_SEQUENCE_DONE', +} +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 +DP_AUX_RESET_SEQUENCE_DONE = 1 +DP_AUX_RESET_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' +DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { + 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', + 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', +} +DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 +DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 +DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 +DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 +DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' +DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', +} +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 +DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 +DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' +DP_AUX_SW_CONTROL_SW_GO__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 1: 'DP_AUX_SW_CONTROL_SW__GO', +} +DP_AUX_SW_CONTROL_SW__NOT_GO = 0 +DP_AUX_SW_CONTROL_SW__GO = 1 +DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' +DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { + 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', + 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', + 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', +} +DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 +DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 +DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 +DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 +DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ACK' +DOUT_I2C_ACK__enumvalues = { + 0: 'DOUT_I2C_NO_ACK', + 1: 'DOUT_I2C_ACK_TO_CLEAN', +} +DOUT_I2C_NO_ACK = 0 +DOUT_I2C_ACK_TO_CLEAN = 1 +DOUT_I2C_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' +DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', +} +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 +DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', +} +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', +} +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' +DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', +} +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 +DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', +} +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' +DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', +} +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 +DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' +DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', + 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', + 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', + 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', + 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', + 5: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', +} +DOUT_I2C_CONTROL_SELECT_DDC1 = 0 +DOUT_I2C_CONTROL_SELECT_DDC2 = 1 +DOUT_I2C_CONTROL_SELECT_DDC3 = 2 +DOUT_I2C_CONTROL_SELECT_DDC4 = 3 +DOUT_I2C_CONTROL_SELECT_DDC5 = 4 +DOUT_I2C_CONTROL_SELECT_DDCVGA = 5 +DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_GO' +DOUT_I2C_CONTROL_GO__enumvalues = { + 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 1: 'DOUT_I2C_CONTROL_START_TRANSFER', +} +DOUT_I2C_CONTROL_STOP_TRANSFER = 0 +DOUT_I2C_CONTROL_START_TRANSFER = 1 +DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' +DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 1: 'DOUT_I2C_CONTROL__SEND_RESET', +} +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 +DOUT_I2C_CONTROL__SEND_RESET = 1 +DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' +DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { + 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', +} +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 +DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' +DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', +} +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 +DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' +DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', +} +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 +DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 +DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' +DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_TRANS0', + 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', +} +DOUT_I2C_CONTROL_TRANS0 = 0 +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 +DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' +DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { + 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 1: 'DOUT_I2C_DATA__INDEX_WRITE', +} +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 +DOUT_I2C_DATA__INDEX_WRITE = 1 +DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', +} +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', +} +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' +DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { + 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', +} +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 +DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', +} +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { + 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', +} +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' +DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { + 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', +} +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 +DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_EN' +CLOCK_GATING_EN__enumvalues = { + 0: 'CLOCK_GATING_ENABLE', + 1: 'CLOCK_GATING_DISABLE', +} +CLOCK_GATING_ENABLE = 0 +CLOCK_GATING_DISABLE = 1 +CLOCK_GATING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DAC_MUX_SELECT' +DAC_MUX_SELECT__enumvalues = { + 0: 'DAC_MUX_SELECT_DACA', + 1: 'DAC_MUX_SELECT_DACB', +} +DAC_MUX_SELECT_DACA = 0 +DAC_MUX_SELECT_DACB = 1 +DAC_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_DIS_CTRL' +DIOMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', +} +DIOMEM_ENABLE_MEM_PWR_CTRL = 0 +DIOMEM_DISABLE_MEM_PWR_CTRL = 1 +DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' +DIOMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQUEST', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', +} +DIOMEM_NO_FORCE_REQUEST = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 +DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' +DIOMEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQ', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', +} +DIOMEM_NO_FORCE_REQ = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 +DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL' +DIOMEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 +DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' +DIOMEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', +} +DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 +DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 +DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_DBG_BLOCK_SEL' +DIO_DBG_BLOCK_SEL__enumvalues = { + 0: 'DIO_DBG_BLOCK_SEL_DIO', + 11: 'DIO_DBG_BLOCK_SEL_DIGFE_A', + 12: 'DIO_DBG_BLOCK_SEL_DIGFE_B', + 13: 'DIO_DBG_BLOCK_SEL_DIGFE_C', + 14: 'DIO_DBG_BLOCK_SEL_DIGFE_D', + 15: 'DIO_DBG_BLOCK_SEL_DIGFE_E', + 18: 'DIO_DBG_BLOCK_SEL_DIGA', + 19: 'DIO_DBG_BLOCK_SEL_DIGB', + 20: 'DIO_DBG_BLOCK_SEL_DIGC', + 21: 'DIO_DBG_BLOCK_SEL_DIGD', + 22: 'DIO_DBG_BLOCK_SEL_DIGE', + 25: 'DIO_DBG_BLOCK_SEL_DPFE_A', + 26: 'DIO_DBG_BLOCK_SEL_DPFE_B', + 27: 'DIO_DBG_BLOCK_SEL_DPFE_C', + 28: 'DIO_DBG_BLOCK_SEL_DPFE_D', + 29: 'DIO_DBG_BLOCK_SEL_DPFE_E', + 32: 'DIO_DBG_BLOCK_SEL_DPA', + 33: 'DIO_DBG_BLOCK_SEL_DPB', + 34: 'DIO_DBG_BLOCK_SEL_DPC', + 35: 'DIO_DBG_BLOCK_SEL_DPD', + 36: 'DIO_DBG_BLOCK_SEL_DPE', + 39: 'DIO_DBG_BLOCK_SEL_AUX0', + 40: 'DIO_DBG_BLOCK_SEL_AUX1', + 41: 'DIO_DBG_BLOCK_SEL_AUX2', + 42: 'DIO_DBG_BLOCK_SEL_AUX3', + 43: 'DIO_DBG_BLOCK_SEL_AUX4', + 45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', + 46: 'DIO_DBG_BLOCK_SEL_RESERVED', +} +DIO_DBG_BLOCK_SEL_DIO = 0 +DIO_DBG_BLOCK_SEL_DIGFE_A = 11 +DIO_DBG_BLOCK_SEL_DIGFE_B = 12 +DIO_DBG_BLOCK_SEL_DIGFE_C = 13 +DIO_DBG_BLOCK_SEL_DIGFE_D = 14 +DIO_DBG_BLOCK_SEL_DIGFE_E = 15 +DIO_DBG_BLOCK_SEL_DIGA = 18 +DIO_DBG_BLOCK_SEL_DIGB = 19 +DIO_DBG_BLOCK_SEL_DIGC = 20 +DIO_DBG_BLOCK_SEL_DIGD = 21 +DIO_DBG_BLOCK_SEL_DIGE = 22 +DIO_DBG_BLOCK_SEL_DPFE_A = 25 +DIO_DBG_BLOCK_SEL_DPFE_B = 26 +DIO_DBG_BLOCK_SEL_DPFE_C = 27 +DIO_DBG_BLOCK_SEL_DPFE_D = 28 +DIO_DBG_BLOCK_SEL_DPFE_E = 29 +DIO_DBG_BLOCK_SEL_DPA = 32 +DIO_DBG_BLOCK_SEL_DPB = 33 +DIO_DBG_BLOCK_SEL_DPC = 34 +DIO_DBG_BLOCK_SEL_DPD = 35 +DIO_DBG_BLOCK_SEL_DPE = 36 +DIO_DBG_BLOCK_SEL_AUX0 = 39 +DIO_DBG_BLOCK_SEL_AUX1 = 40 +DIO_DBG_BLOCK_SEL_AUX2 = 41 +DIO_DBG_BLOCK_SEL_AUX3 = 42 +DIO_DBG_BLOCK_SEL_AUX4 = 43 +DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45 +DIO_DBG_BLOCK_SEL_RESERVED = 46 +DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { + 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', +} +DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 +DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE' +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = { + 0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', +} +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS' +ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = { + 0: 'ENUM_DCN_NOT_ACTIVE', + 1: 'ENUM_DCN_ACTIVE', +} +ENUM_DCN_NOT_ACTIVE = 0 +ENUM_DCN_ACTIVE = 1 +ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_STEREOSYNC_SEL' +GENERIC_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERIC_STEREOSYNC_SEL_D1', + 1: 'GENERIC_STEREOSYNC_SEL_D2', + 2: 'GENERIC_STEREOSYNC_SEL_D3', + 3: 'GENERIC_STEREOSYNC_SEL_D4', + 4: 'GENERIC_STEREOSYNC_SEL_RESERVED', +} +GENERIC_STEREOSYNC_SEL_D1 = 0 +GENERIC_STEREOSYNC_SEL_D2 = 1 +GENERIC_STEREOSYNC_SEL_D3 = 2 +GENERIC_STEREOSYNC_SEL_D4 = 3 +GENERIC_STEREOSYNC_SEL_RESERVED = 4 +GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PM_ASSERT_RESET' +PM_ASSERT_RESET__enumvalues = { + 0: 'PM_ASSERT_RESET_0', + 1: 'PM_ASSERT_RESET_1', +} +PM_ASSERT_RESET_0 = 0 +PM_ASSERT_RESET_1 = 1 +PM_ASSERT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SOFT_RESET' +SOFT_RESET__enumvalues = { + 0: 'SOFT_RESET_0', + 1: 'SOFT_RESET_1', +} +SOFT_RESET_0 = 0 +SOFT_RESET_1 = 1 +SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_MUX_SELECT' +TMDS_MUX_SELECT__enumvalues = { + 0: 'TMDS_MUX_SELECT_B', + 1: 'TMDS_MUX_SELECT_G', + 2: 'TMDS_MUX_SELECT_R', + 3: 'TMDS_MUX_SELECT_RESERVED', +} +TMDS_MUX_SELECT_B = 0 +TMDS_MUX_SELECT_G = 1 +TMDS_MUX_SELECT_R = 2 +TMDS_MUX_SELECT_RESERVED = 3 +TMDS_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_POWER_STATE_ENUM' +DME_MEM_POWER_STATE_ENUM__enumvalues = { + 0: 'DME_MEM_POWER_STATE_ENUM_ON', + 1: 'DME_MEM_POWER_STATE_ENUM_LS', + 2: 'DME_MEM_POWER_STATE_ENUM_DS', + 3: 'DME_MEM_POWER_STATE_ENUM_SD', +} +DME_MEM_POWER_STATE_ENUM_ON = 0 +DME_MEM_POWER_STATE_ENUM_LS = 1 +DME_MEM_POWER_STATE_ENUM_DS = 2 +DME_MEM_POWER_STATE_ENUM_SD = 3 +DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_DIS_CTRL' +DME_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DME_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'DME_MEM_DISABLE_MEM_PWR_CTRL', +} +DME_MEM_ENABLE_MEM_PWR_CTRL = 0 +DME_MEM_DISABLE_MEM_PWR_CTRL = 1 +DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_FORCE_CTRL' +DME_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DME_MEM_NO_FORCE_REQUEST', + 1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', +} +DME_MEM_NO_FORCE_REQUEST = 0 +DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_HUBP_SEL' +METADATA_HUBP_SEL__enumvalues = { + 0: 'METADATA_HUBP_SEL_0', + 1: 'METADATA_HUBP_SEL_1', + 2: 'METADATA_HUBP_SEL_2', + 3: 'METADATA_HUBP_SEL_3', + 4: 'METADATA_HUBP_SEL_RESERVED', +} +METADATA_HUBP_SEL_0 = 0 +METADATA_HUBP_SEL_1 = 1 +METADATA_HUBP_SEL_2 = 2 +METADATA_HUBP_SEL_3 = 3 +METADATA_HUBP_SEL_RESERVED = 4 +METADATA_HUBP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_STREAM_TYPE_SEL' +METADATA_STREAM_TYPE_SEL__enumvalues = { + 0: 'METADATA_STREAM_DP', + 1: 'METADATA_STREAM_DVE', +} +METADATA_STREAM_DP = 0 +METADATA_STREAM_DVE = 1 +METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_DIS_CTRL' +VPG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL', +} +VPG_MEM_ENABLE_MEM_PWR_CTRL = 0 +VPG_MEM_DISABLE_MEM_PWR_CTRL = 1 +VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL' +VPG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'VPG_MEM_NO_FORCE_REQ', + 1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', +} +VPG_MEM_NO_FORCE_REQ = 0 +VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1 +VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_ACP_TYPE' +AFMT_ACP_TYPE__enumvalues = { + 0: 'ACP_TYPE_GENERIC_AUDIO', + 1: 'ACP_TYPE_ICE60958_AUDIO', + 2: 'ACP_TYPE_DVD_AUDIO', + 3: 'ACP_TYPE_SUPER_AUDIO_CD', +} +ACP_TYPE_GENERIC_AUDIO = 0 +ACP_TYPE_ICE60958_AUDIO = 1 +ACP_TYPE_DVD_AUDIO = 2 +ACP_TYPE_SUPER_AUDIO_CD = 3 +AFMT_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' +AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'AFMT_AUDIO_CRC_CH0_SIG', + 1: 'AFMT_AUDIO_CRC_CH1_SIG', + 2: 'AFMT_AUDIO_CRC_CH2_SIG', + 3: 'AFMT_AUDIO_CRC_CH3_SIG', + 4: 'AFMT_AUDIO_CRC_CH4_SIG', + 5: 'AFMT_AUDIO_CRC_CH5_SIG', + 6: 'AFMT_AUDIO_CRC_CH6_SIG', + 7: 'AFMT_AUDIO_CRC_CH7_SIG', + 8: 'AFMT_AUDIO_CRC_RESERVED_8', + 9: 'AFMT_AUDIO_CRC_RESERVED_9', + 10: 'AFMT_AUDIO_CRC_RESERVED_10', + 11: 'AFMT_AUDIO_CRC_RESERVED_11', + 12: 'AFMT_AUDIO_CRC_RESERVED_12', + 13: 'AFMT_AUDIO_CRC_RESERVED_13', + 14: 'AFMT_AUDIO_CRC_RESERVED_14', + 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', +} +AFMT_AUDIO_CRC_CH0_SIG = 0 +AFMT_AUDIO_CRC_CH1_SIG = 1 +AFMT_AUDIO_CRC_CH2_SIG = 2 +AFMT_AUDIO_CRC_CH3_SIG = 3 +AFMT_AUDIO_CRC_CH4_SIG = 4 +AFMT_AUDIO_CRC_CH5_SIG = 5 +AFMT_AUDIO_CRC_CH6_SIG = 6 +AFMT_AUDIO_CRC_CH7_SIG = 7 +AFMT_AUDIO_CRC_RESERVED_8 = 8 +AFMT_AUDIO_CRC_RESERVED_9 = 9 +AFMT_AUDIO_CRC_RESERVED_10 = 10 +AFMT_AUDIO_CRC_RESERVED_11 = 11 +AFMT_AUDIO_CRC_RESERVED_12 = 12 +AFMT_AUDIO_CRC_RESERVED_13 = 13 +AFMT_AUDIO_CRC_RESERVED_14 = 14 +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 +AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' +AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'AFMT_AUDIO_CRC_ONESHOT', + 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', +} +AFMT_AUDIO_CRC_ONESHOT = 0 +AFMT_AUDIO_CRC_AUTO_RESTART = 1 +AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' +AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { + 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', +} +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 +AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { + 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', +} +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { + 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', +} +AFMT_AUDIO_PACKET_SENT_DISABLED = 0 +AFMT_AUDIO_PACKET_SENT_ENABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { + 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', +} +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' +AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { + 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', +} +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 +AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS' +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { + 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', +} +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 +HDMI_SEND_MAX_AUDIO_PACKETS = 1 +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' +AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { + 0: 'AFMT_INTERRUPT_DISABLE', + 1: 'AFMT_INTERRUPT_ENABLE', +} +AFMT_INTERRUPT_DISABLE = 0 +AFMT_INTERRUPT_ENABLE = 1 +AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL' +AFMT_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', +} +AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0 +AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1 +AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL' +AFMT_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'AFMT_MEM_NO_FORCE_REQUEST', + 1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', +} +AFMT_MEM_NO_FORCE_REQUEST = 0 +AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' +AFMT_RAMP_CONTROL0_SIGN__enumvalues = { + 0: 'AFMT_RAMP_SIGNED', + 1: 'AFMT_RAMP_UNSIGNED', +} +AFMT_RAMP_SIGNED = 0 +AFMT_RAMP_UNSIGNED = 1 +AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE' +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'AFMT_ACP_SOURCE_FROM_AZALIA', + 1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_ACP_SOURCE_FROM_AZALIA = 0 +AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AUDIO_LAYOUT_SELECT' +AUDIO_LAYOUT_SELECT__enumvalues = { + 0: 'AUDIO_LAYOUT_0', + 1: 'AUDIO_LAYOUT_1', +} +AUDIO_LAYOUT_0 = 0 +AUDIO_LAYOUT_1 = 1 +AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE' +HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = { + 0: 'HPO_TOP_CLOCK_GATING_EN', + 1: 'HPO_TOP_CLOCK_GATING_DIS', +} +HPO_TOP_CLOCK_GATING_EN = 0 +HPO_TOP_CLOCK_GATING_DIS = 1 +HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_TEST_CLK_SEL' +HPO_TOP_TEST_CLK_SEL__enumvalues = { + 0: 'HPO_TOP_PERMANENT_DISPCLK', + 1: 'HPO_TOP_REGISTER_GATED_DISPCLK', + 2: 'HPO_TOP_PERMANENT_SOCCLK', + 3: 'HPO_TOP_TEST_CLOCK_RESERVED', + 4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', + 5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', + 7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 9: 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', +} +HPO_TOP_PERMANENT_DISPCLK = 0 +HPO_TOP_REGISTER_GATED_DISPCLK = 1 +HPO_TOP_PERMANENT_SOCCLK = 2 +HPO_TOP_TEST_CLOCK_RESERVED = 3 +HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4 +HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5 +HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6 +HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7 +HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8 +HPO_TOP_PERMANENT_HDMICHARCLK0 = 9 +HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10 +HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11 +HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET' +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = { + 0: 'DP_STREAM_MAPPER_LINK0', + 1: 'DP_STREAM_MAPPER_LINK1', + 2: 'DP_STREAM_MAPPER_RESERVED', +} +DP_STREAM_MAPPER_LINK0 = 0 +DP_STREAM_MAPPER_LINK1 = 1 +DP_STREAM_MAPPER_RESERVED = 2 +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL' +HDMI_STREAM_ENC_DB_DISABLE_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DB_ENABLE', + 1: 'HDMI_STREAM_ENC_DB_DISABLE', +} +HDMI_STREAM_ENC_DB_ENABLE = 0 +HDMI_STREAM_ENC_DB_DISABLE = 1 +HDMI_STREAM_ENC_DB_DISABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_DSC_MODE' +HDMI_STREAM_ENC_DSC_MODE__enumvalues = { + 0: 'STREAM_DSC_DISABLE', + 1: 'STREAM_DSC_444_RGB', + 2: 'STREAM_DSC_NATIVE_422_420', +} +STREAM_DSC_DISABLE = 0 +STREAM_DSC_444_RGB = 1 +STREAM_DSC_NATIVE_422_420 = 2 +HDMI_STREAM_ENC_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_ENABLE_CONTROL' +HDMI_STREAM_ENC_ENABLE_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DISABLE', + 1: 'HDMI_STREAM_ENC_ENABLE', +} +HDMI_STREAM_ENC_DISABLE = 0 +HDMI_STREAM_ENC_ENABLE = 1 +HDMI_STREAM_ENC_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_ODM_COMBINE_MODE' +HDMI_STREAM_ENC_ODM_COMBINE_MODE__enumvalues = { + 0: 'STREAM_ODM_COMBINE_1_SEGMENT', + 1: 'STREAM_ODM_COMBINE_2_SEGMENT', + 2: 'STREAM_ODM_COMBINE_RESERVED', + 3: 'STREAM_ODM_COMBINE_4_SEGMENT', +} +STREAM_ODM_COMBINE_1_SEGMENT = 0 +STREAM_ODM_COMBINE_2_SEGMENT = 1 +STREAM_ODM_COMBINE_RESERVED = 2 +STREAM_ODM_COMBINE_4_SEGMENT = 3 +HDMI_STREAM_ENC_ODM_COMBINE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' +HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', + 1: 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', + 2: 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', +} +HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0 +HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 1 +HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 2 +HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT' +HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { + 0: 'HDMI_STREAM_ENC_HARDWARE', + 1: 'HDMI_STREAM_ENC_PROGRAMMABLE', +} +HDMI_STREAM_ENC_HARDWARE = 0 +HDMI_STREAM_ENC_PROGRAMMABLE = 1 +HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_PIXEL_ENCODING' +HDMI_STREAM_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'STREAM_PIXEL_ENCODING_444_RGB', + 1: 'STREAM_PIXEL_ENCODING_422', + 2: 'STREAM_PIXEL_ENCODING_420', +} +STREAM_PIXEL_ENCODING_444_RGB = 0 +STREAM_PIXEL_ENCODING_422 = 1 +STREAM_PIXEL_ENCODING_420 = 2 +HDMI_STREAM_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL' +HDMI_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DCCG', + 1: 'HDMI_STREAM_ENC_DISPLAY_PIPE', +} +HDMI_STREAM_ENC_DCCG = 0 +HDMI_STREAM_ENC_DISPLAY_PIPE = 1 +HDMI_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_RESET_CONTROL' +HDMI_STREAM_ENC_RESET_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_NOT_RESET', + 1: 'HDMI_STREAM_ENC_RESET', +} +HDMI_STREAM_ENC_NOT_RESET = 0 +HDMI_STREAM_ENC_RESET = 1 +HDMI_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_STREAM_ACTIVE' +HDMI_STREAM_ENC_STREAM_ACTIVE__enumvalues = { + 0: 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 1: 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', +} +HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 +HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 +HDMI_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'BORROWBUFFER_MEM_POWER_STATE_ENUM' +BORROWBUFFER_MEM_POWER_STATE_ENUM__enumvalues = { + 0: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', + 1: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', + 2: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', + 3: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', +} +BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0 +BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 1 +BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 2 +BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 3 +BORROWBUFFER_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_BORROW_MODE' +HDMI_BORROW_MODE__enumvalues = { + 0: 'TB_BORROW_MODE_NONE', + 1: 'TB_BORROW_MODE_ACTIVE', + 2: 'TB_BORROW_MODE_BLANK', + 3: 'TB_BORROW_MODE_RESERVED', +} +TB_BORROW_MODE_NONE = 0 +TB_BORROW_MODE_ACTIVE = 1 +TB_BORROW_MODE_BLANK = 2 +TB_BORROW_MODE_RESERVED = 3 +HDMI_BORROW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACP_SEND' +HDMI_TB_ENC_ACP_SEND__enumvalues = { + 0: 'TB_ACP_NOT_SEND', + 1: 'TB_ACP_PKT_SEND', +} +TB_ACP_NOT_SEND = 0 +TB_ACP_PKT_SEND = 1 +HDMI_TB_ENC_ACP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY' +HDMI_TB_ENC_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_TB_ENC_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_CONT' +HDMI_TB_ENC_ACR_CONT__enumvalues = { + 0: 'TB_ACR_CONT_DISABLE', + 1: 'TB_ACR_CONT_ENABLE', +} +TB_ACR_CONT_DISABLE = 0 +TB_ACR_CONT_ENABLE = 1 +HDMI_TB_ENC_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_N_MULTIPLE' +HDMI_TB_ENC_ACR_N_MULTIPLE__enumvalues = { + 0: 'TB_ACR_0_MULTIPLE_RESERVED', + 1: 'TB_ACR_1_MULTIPLE', + 2: 'TB_ACR_2_MULTIPLE', + 3: 'TB_ACR_3_MULTIPLE_RESERVED', + 4: 'TB_ACR_4_MULTIPLE', + 5: 'TB_ACR_5_MULTIPLE_RESERVED', + 6: 'TB_ACR_6_MULTIPLE_RESERVED', + 7: 'TB_ACR_7_MULTIPLE_RESERVED', +} +TB_ACR_0_MULTIPLE_RESERVED = 0 +TB_ACR_1_MULTIPLE = 1 +TB_ACR_2_MULTIPLE = 2 +TB_ACR_3_MULTIPLE_RESERVED = 3 +TB_ACR_4_MULTIPLE = 4 +TB_ACR_5_MULTIPLE_RESERVED = 5 +TB_ACR_6_MULTIPLE_RESERVED = 6 +TB_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_TB_ENC_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SELECT' +HDMI_TB_ENC_ACR_SELECT__enumvalues = { + 0: 'TB_ACR_SELECT_HW', + 1: 'TB_ACR_SELECT_32K', + 2: 'TB_ACR_SELECT_44K', + 3: 'TB_ACR_SELECT_48K', +} +TB_ACR_SELECT_HW = 0 +TB_ACR_SELECT_32K = 1 +TB_ACR_SELECT_44K = 2 +TB_ACR_SELECT_48K = 3 +HDMI_TB_ENC_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SEND' +HDMI_TB_ENC_ACR_SEND__enumvalues = { + 0: 'TB_ACR_NOT_SEND', + 1: 'TB_ACR_PKT_SEND', +} +TB_ACR_NOT_SEND = 0 +TB_ACR_PKT_SEND = 1 +HDMI_TB_ENC_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SOURCE' +HDMI_TB_ENC_ACR_SOURCE__enumvalues = { + 0: 'TB_ACR_SOURCE_HW', + 1: 'TB_ACR_SOURCE_SW', +} +TB_ACR_SOURCE_HW = 0 +TB_ACR_SOURCE_SW = 1 +HDMI_TB_ENC_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_CONT' +HDMI_TB_ENC_AUDIO_INFO_CONT__enumvalues = { + 0: 'TB_AUDIO_INFO_CONT_DISABLE', + 1: 'TB_AUDIO_INFO_CONT_ENABLE', +} +TB_AUDIO_INFO_CONT_DISABLE = 0 +TB_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_TB_ENC_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_SEND' +HDMI_TB_ENC_AUDIO_INFO_SEND__enumvalues = { + 0: 'TB_AUDIO_INFO_NOT_SEND', + 1: 'TB_AUDIO_INFO_PKT_SEND', +} +TB_AUDIO_INFO_NOT_SEND = 0 +TB_AUDIO_INFO_PKT_SEND = 1 +HDMI_TB_ENC_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_CRC_SRC_SEL' +HDMI_TB_ENC_CRC_SRC_SEL__enumvalues = { + 0: 'TB_CRC_TB_ENC_INPUT', + 1: 'TB_CRC_DSC_PACKER', + 2: 'TB_CRC_DEEP_COLOR_PACKER', + 3: 'TB_CRC_ENCRYPTOR_INPUT', +} +TB_CRC_TB_ENC_INPUT = 0 +TB_CRC_DSC_PACKER = 1 +TB_CRC_DEEP_COLOR_PACKER = 2 +TB_CRC_ENCRYPTOR_INPUT = 3 +HDMI_TB_ENC_CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_CRC_TYPE' +HDMI_TB_ENC_CRC_TYPE__enumvalues = { + 0: 'TB_CRC_ALL_TRIBYTES', + 1: 'TB_CRC_ACTIVE_TRIBYTES', + 2: 'TB_CRC_DATAISLAND_TRIBYTES', + 3: 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', +} +TB_CRC_ALL_TRIBYTES = 0 +TB_CRC_ACTIVE_TRIBYTES = 1 +TB_CRC_DATAISLAND_TRIBYTES = 2 +TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 3 +HDMI_TB_ENC_CRC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DEEP_COLOR_DEPTH' +HDMI_TB_ENC_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'TB_DEEP_COLOR_DEPTH_24BPP', + 1: 'TB_DEEP_COLOR_DEPTH_30BPP', + 2: 'TB_DEEP_COLOR_DEPTH_36BPP', + 3: 'TB_DEEP_COLOR_DEPTH_RESERVED', +} +TB_DEEP_COLOR_DEPTH_24BPP = 0 +TB_DEEP_COLOR_DEPTH_30BPP = 1 +TB_DEEP_COLOR_DEPTH_36BPP = 2 +TB_DEEP_COLOR_DEPTH_RESERVED = 3 +HDMI_TB_ENC_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DEFAULT_PAHSE' +HDMI_TB_ENC_DEFAULT_PAHSE__enumvalues = { + 0: 'TB_DEFAULT_PHASE_IS_0', + 1: 'TB_DEFAULT_PHASE_IS_1', +} +TB_DEFAULT_PHASE_IS_0 = 0 +TB_DEFAULT_PHASE_IS_1 = 1 +HDMI_TB_ENC_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DSC_MODE' +HDMI_TB_ENC_DSC_MODE__enumvalues = { + 0: 'TB_DSC_DISABLE', + 1: 'TB_DSC_444_RGB', + 2: 'TB_DSC_NATIVE_422_420', +} +TB_DSC_DISABLE = 0 +TB_DSC_444_RGB = 1 +TB_DSC_NATIVE_422_420 = 2 +HDMI_TB_ENC_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ENABLE' +HDMI_TB_ENC_ENABLE__enumvalues = { + 0: 'TB_DISABLE', + 1: 'TB_ENABLE', +} +TB_DISABLE = 0 +TB_ENABLE = 1 +HDMI_TB_ENC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE' +HDMI_TB_ENC_GC_AVMUTE__enumvalues = { + 0: 'TB_GC_AVMUTE_SET', + 1: 'TB_GC_AVMUTE_UNSET', +} +TB_GC_AVMUTE_SET = 0 +TB_GC_AVMUTE_UNSET = 1 +HDMI_TB_ENC_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE_CONT' +HDMI_TB_ENC_GC_AVMUTE_CONT__enumvalues = { + 0: 'TB_GC_AVMUTE_CONT_DISABLE', + 1: 'TB_GC_AVMUTE_CONT_ENABLE', +} +TB_GC_AVMUTE_CONT_DISABLE = 0 +TB_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_TB_ENC_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_CONT' +HDMI_TB_ENC_GC_CONT__enumvalues = { + 0: 'TB_GC_CONT_DISABLE', + 1: 'TB_GC_CONT_ENABLE', +} +TB_GC_CONT_DISABLE = 0 +TB_GC_CONT_ENABLE = 1 +HDMI_TB_ENC_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_SEND' +HDMI_TB_ENC_GC_SEND__enumvalues = { + 0: 'TB_GC_NOT_SEND', + 1: 'TB_GC_PKT_SEND', +} +TB_GC_NOT_SEND = 0 +TB_GC_PKT_SEND = 1 +HDMI_TB_ENC_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_CONT' +HDMI_TB_ENC_GENERIC_CONT__enumvalues = { + 0: 'TB_GENERIC_CONT_DISABLE', + 1: 'TB_GENERIC_CONT_ENABLE', +} +TB_GENERIC_CONT_DISABLE = 0 +TB_GENERIC_CONT_ENABLE = 1 +HDMI_TB_ENC_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_LOCK_EN' +HDMI_TB_ENC_GENERIC_LOCK_EN__enumvalues = { + 0: 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', + 1: 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', +} +HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0 +HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 1 +HDMI_TB_ENC_GENERIC_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_SEND' +HDMI_TB_ENC_GENERIC_SEND__enumvalues = { + 0: 'TB_GENERIC_NOT_SEND', + 1: 'TB_GENERIC_PKT_SEND', +} +TB_GENERIC_NOT_SEND = 0 +TB_GENERIC_PKT_SEND = 1 +HDMI_TB_ENC_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ISRC_CONT' +HDMI_TB_ENC_ISRC_CONT__enumvalues = { + 0: 'TB_ISRC_CONT_DISABLE', + 1: 'TB_ISRC_CONT_ENABLE', +} +TB_ISRC_CONT_DISABLE = 0 +TB_ISRC_CONT_ENABLE = 1 +HDMI_TB_ENC_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ISRC_SEND' +HDMI_TB_ENC_ISRC_SEND__enumvalues = { + 0: 'TB_ISRC_NOT_SEND', + 1: 'TB_ISRC_PKT_SEND', +} +TB_ISRC_NOT_SEND = 0 +TB_ISRC_PKT_SEND = 1 +HDMI_TB_ENC_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_METADATA_ENABLE' +HDMI_TB_ENC_METADATA_ENABLE__enumvalues = { + 0: 'TB_METADATA_NOT_SEND', + 1: 'TB_METADATA_PKT_SEND', +} +TB_METADATA_NOT_SEND = 0 +TB_METADATA_PKT_SEND = 1 +HDMI_TB_ENC_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_PACKET_LINE_REFERENCE' +HDMI_TB_ENC_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'TB_PKT_LINE_REF_END_OF_ACTIVE', + 1: 'TB_PKT_LINE_REF_OTGSOF', +} +TB_PKT_LINE_REF_END_OF_ACTIVE = 0 +TB_PKT_LINE_REF_OTGSOF = 1 +HDMI_TB_ENC_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_PIXEL_ENCODING' +HDMI_TB_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'TB_PIXEL_ENCODING_444_RGB', + 1: 'TB_PIXEL_ENCODING_422', + 2: 'TB_PIXEL_ENCODING_420', +} +TB_PIXEL_ENCODING_444_RGB = 0 +TB_PIXEL_ENCODING_422 = 1 +TB_PIXEL_ENCODING_420 = 2 +HDMI_TB_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_RESET' +HDMI_TB_ENC_RESET__enumvalues = { + 0: 'TB_NOT_RESET', + 1: 'TB_RESET', +} +TB_NOT_RESET = 0 +TB_RESET = 1 +HDMI_TB_ENC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_SYNC_PHASE' +HDMI_TB_ENC_SYNC_PHASE__enumvalues = { + 0: 'TB_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TB_SYNC_PHASE_ON_FRAME_START', +} +TB_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TB_SYNC_PHASE_ON_FRAME_START = 1 +HDMI_TB_ENC_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'INPUT_FIFO_ERROR_TYPE' +INPUT_FIFO_ERROR_TYPE__enumvalues = { + 0: 'TB_NO_ERROR_OCCURRED', + 1: 'TB_OVERFLOW_OCCURRED', +} +TB_NO_ERROR_OCCURRED = 0 +TB_OVERFLOW_OCCURRED = 1 +INPUT_FIFO_ERROR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED', +} +DP_STREAM_ENC_NO_ERROR_OCCURRED = 0 +DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1 +DP_STREAM_ENC_OVERFLOW_OCCURRED = 2 +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT' +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { + 0: 'DP_STREAM_ENC_HARDWARE', + 1: 'DP_STREAM_ENC_PROGRAMMABLE', +} +DP_STREAM_ENC_HARDWARE = 0 +DP_STREAM_ENC_PROGRAMMABLE = 1 +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL' +DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_DCCG', + 1: 'DP_STREAM_ENC_DISPLAY_PIPE', +} +DP_STREAM_ENC_DCCG = 0 +DP_STREAM_ENC_DISPLAY_PIPE = 1 +DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL' +DP_STREAM_ENC_RESET_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_NOT_RESET', + 1: 'DP_STREAM_ENC_RESET', +} +DP_STREAM_ENC_NOT_RESET = 0 +DP_STREAM_ENC_RESET = 1 +DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE' +DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = { + 0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', +} +DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 +DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 +DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE' +ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', +} +DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0 +DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1 +ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE' +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = { + 0: 'DP_SYM32_ENC_ONE_SHOT_MODE', + 1: 'DP_SYM32_ENC_CONTINUOUS_MODE', +} +DP_SYM32_ENC_ONE_SHOT_MODE = 0 +DP_SYM32_ENC_CONTINUOUS_MODE = 1 +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID' +ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = { + 0: 'DP_SYM32_ENC_CRC_NOT_VALID', + 1: 'DP_SYM32_ENC_CRC_VALID', +} +DP_SYM32_ENC_CRC_NOT_VALID = 0 +DP_SYM32_ENC_CRC_VALID = 1 +ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH' +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', +} +DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0 +DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1 +DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2 +DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3 +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE' +ENUM_DP_SYM32_ENC_ENABLE__enumvalues = { + 0: 'DP_SYM32_ENC_DISABLE', + 1: 'DP_SYM32_ENC_ENABLE', +} +DP_SYM32_ENC_DISABLE = 0 +DP_SYM32_ENC_ENABLE = 1 +ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED' +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', +} +DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0 +DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1 +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION' +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', +} +DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0 +DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1 +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE' +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', +} +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3 +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING' +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', +} +DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0 +DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1 +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM' +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', +} +DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0 +DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1 +DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2 +DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3 +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS' +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = { + 0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', + 1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED', +} +DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0 +DP_SYM32_ENC_OVERFLOW_OCCURRED = 1 +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING' +ENUM_DP_SYM32_ENC_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_PENDING', + 1: 'DP_SYM32_ENC_PENDING', +} +DP_SYM32_ENC_NOT_PENDING = 0 +DP_SYM32_ENC_PENDING = 1 +ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', +} +DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2 +DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = { + 0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 1: 'DP_SYM32_ENC_COMPRESSED_FORMAT', +} +DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0 +DP_SYM32_ENC_COMPRESSED_FORMAT = 1 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM' +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', +} +DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0 +DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1 +DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2 +DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3 +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_RESET' +ENUM_DP_SYM32_ENC_RESET__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_RESET', + 1: 'DP_SYM32_ENC_RESET', +} +DP_SYM32_ENC_NOT_RESET = 0 +DP_SYM32_ENC_RESET = 1 +ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY' +ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', +} +DP_SYM32_ENC_SDP_LOW_PRIORITY = 0 +DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1 +ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE' +ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = { + 0: 'DP_SYM32_ENC_DP_SOF', + 1: 'DP_SYM32_ENC_OTG_SOF', +} +DP_SYM32_ENC_DP_SOF = 0 +DP_SYM32_ENC_OTG_SOF = 1 +ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER' +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = { + 0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', + 1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', +} +DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2 +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT' +ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_END_LLCP', + 1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_END_PS_ANY', +} +DP_DPHY_SYM32_CRC_END_LLCP = 0 +DP_DPHY_SYM32_CRC_END_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_END_PS_ANY = 3 +ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT' +ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_START_LLCP', + 1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 4: 'DP_DPHY_SYM32_CRC_START_TP_START', +} +DP_DPHY_SYM32_CRC_START_LLCP = 0 +DP_DPHY_SYM32_CRC_START_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3 +DP_DPHY_SYM32_CRC_START_TP_START = 4 +ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE' +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', +} +DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0 +DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1 +DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2 +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS' +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', +} +DP_DPHY_SYM32_CRC_USE_END_EVENT = 0 +DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1 +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE' +ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_DISABLE', + 1: 'DP_DPHY_SYM32_ENABLE', +} +DP_DPHY_SYM32_DISABLE = 0 +DP_DPHY_SYM32_ENABLE = 1 +ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE' +ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE__enumvalues = { + 0: 'DP_DPHY_SYM32_ENCRYPT_TYPE0', + 1: 'DP_DPHY_SYM32_ENCRYPT_TYPE1', +} +DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0 +DP_DPHY_SYM32_ENCRYPT_TYPE1 = 1 +ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE' +ENUM_DP_DPHY_SYM32_MODE__enumvalues = { + 0: 'DP_DPHY_SYM32_LT_TPS1', + 1: 'DP_DPHY_SYM32_LT_TPS2', + 2: 'DP_DPHY_SYM32_ACTIVE', + 3: 'DP_DPHY_SYM32_TEST', +} +DP_DPHY_SYM32_LT_TPS1 = 0 +DP_DPHY_SYM32_LT_TPS2 = 1 +DP_DPHY_SYM32_ACTIVE = 2 +DP_DPHY_SYM32_TEST = 3 +ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES' +ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = { + 0: 'DP_DPHY_SYM32_1LANE', + 1: 'DP_DPHY_SYM32_2LANE', + 2: 'DP_DPHY_SYM32_RESERVED', + 3: 'DP_DPHY_SYM32_4LANE', +} +DP_DPHY_SYM32_1LANE = 0 +DP_DPHY_SYM32_2LANE = 1 +DP_DPHY_SYM32_RESERVED = 2 +DP_DPHY_SYM32_4LANE = 3 +ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', +} +DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0 +DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1 +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET' +ENUM_DP_DPHY_SYM32_RESET__enumvalues = { + 0: 'DP_DPHY_SYM32_NOT_RESET', + 1: 'DP_DPHY_SYM32_RESET', +} +DP_DPHY_SYM32_NOT_RESET = 0 +DP_DPHY_SYM32_RESET = 1 +ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS' +ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', +} +DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0 +DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1 +ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE' +ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', +} +DP_DPHY_SYM32_SAT_NO_UPDATE = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', +} +DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS' +ENUM_DP_DPHY_SYM32_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_STATUS_IDLE', + 1: 'DP_DPHY_SYM32_STATUS_ENABLED', +} +DP_DPHY_SYM32_STATUS_IDLE = 0 +DP_DPHY_SYM32_STATUS_ENABLED = 1 +ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', +} +DP_DPHY_SYM32_STREAM_OVR_NONE = 0 +DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1 +DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2 +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', + 1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', +} +DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0 +DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1 +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL' +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', +} +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5 +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT' +ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 1: 'DP_DPHY_SYM32_TP_SELECT_TPS2', + 2: 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', + 4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE', +} +DP_DPHY_SYM32_TP_SELECT_TPS1 = 0 +DP_DPHY_SYM32_TP_SELECT_TPS2 = 1 +DP_DPHY_SYM32_TP_SELECT_PRBS = 2 +DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3 +DP_DPHY_SYM32_TP_SELECT_SQUARE = 4 +ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL' +APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'APG_AUDIO_CRC_CH0_SIG', + 1: 'APG_AUDIO_CRC_CH1_SIG', + 2: 'APG_AUDIO_CRC_CH2_SIG', + 3: 'APG_AUDIO_CRC_CH3_SIG', + 4: 'APG_AUDIO_CRC_CH4_SIG', + 5: 'APG_AUDIO_CRC_CH5_SIG', + 6: 'APG_AUDIO_CRC_CH6_SIG', + 7: 'APG_AUDIO_CRC_CH7_SIG', + 8: 'APG_AUDIO_CRC_RESERVED_8', + 9: 'APG_AUDIO_CRC_RESERVED_9', + 10: 'APG_AUDIO_CRC_RESERVED_10', + 11: 'APG_AUDIO_CRC_RESERVED_11', + 12: 'APG_AUDIO_CRC_RESERVED_12', + 13: 'APG_AUDIO_CRC_RESERVED_13', + 14: 'APG_AUDIO_CRC_RESERVED_14', + 15: 'APG_AUDIO_CRC_RESERVED_15', +} +APG_AUDIO_CRC_CH0_SIG = 0 +APG_AUDIO_CRC_CH1_SIG = 1 +APG_AUDIO_CRC_CH2_SIG = 2 +APG_AUDIO_CRC_CH3_SIG = 3 +APG_AUDIO_CRC_CH4_SIG = 4 +APG_AUDIO_CRC_CH5_SIG = 5 +APG_AUDIO_CRC_CH6_SIG = 6 +APG_AUDIO_CRC_CH7_SIG = 7 +APG_AUDIO_CRC_RESERVED_8 = 8 +APG_AUDIO_CRC_RESERVED_9 = 9 +APG_AUDIO_CRC_RESERVED_10 = 10 +APG_AUDIO_CRC_RESERVED_11 = 11 +APG_AUDIO_CRC_RESERVED_12 = 12 +APG_AUDIO_CRC_RESERVED_13 = 13 +APG_AUDIO_CRC_RESERVED_14 = 14 +APG_AUDIO_CRC_RESERVED_15 = 15 +APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT' +APG_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'APG_AUDIO_CRC_ONESHOT', + 1: 'APG_AUDIO_CRC_CONTINUOUS', +} +APG_AUDIO_CRC_ONESHOT = 0 +APG_AUDIO_CRC_CONTINUOUS = 1 +APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_ACP_TYPE' +APG_DBG_ACP_TYPE__enumvalues = { + 0: 'APG_ACP_TYPE_GENERIC_AUDIO', + 1: 'APG_ACP_TYPE_ICE60958_AUDIO', + 2: 'APG_ACP_TYPE_DVD_AUDIO', + 3: 'APG_ACP_TYPE_SUPER_AUDIO_CD', +} +APG_ACP_TYPE_GENERIC_AUDIO = 0 +APG_ACP_TYPE_ICE60958_AUDIO = 1 +APG_ACP_TYPE_DVD_AUDIO = 2 +APG_ACP_TYPE_SUPER_AUDIO_CD = 3 +APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_BASE' +APG_DBG_AUDIO_DTO_BASE__enumvalues = { + 0: 'BASE_RATE_48KHZ', + 1: 'BASE_RATE_44P1KHZ', +} +BASE_RATE_48KHZ = 0 +BASE_RATE_44P1KHZ = 1 +APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_DIV' +APG_DBG_AUDIO_DTO_DIV__enumvalues = { + 0: 'DIVISOR_BY1', + 1: 'DIVISOR_BY2_RESERVED', + 2: 'DIVISOR_BY3', + 3: 'DIVISOR_BY4_RESERVED', + 4: 'DIVISOR_BY5_RESERVED', + 5: 'DIVISOR_BY6_RESERVED', + 6: 'DIVISOR_BY7_RESERVED', + 7: 'DIVISOR_BY8_RESERVED', +} +DIVISOR_BY1 = 0 +DIVISOR_BY2_RESERVED = 1 +DIVISOR_BY3 = 2 +DIVISOR_BY4_RESERVED = 3 +DIVISOR_BY5_RESERVED = 4 +DIVISOR_BY6_RESERVED = 5 +DIVISOR_BY7_RESERVED = 6 +DIVISOR_BY8_RESERVED = 7 +APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI' +APG_DBG_AUDIO_DTO_MULTI__enumvalues = { + 0: 'MULTIPLE_BY1', + 1: 'MULTIPLE_BY2', + 2: 'MULTIPLE_BY3_RESERVED', + 3: 'MULTIPLE_BY4', + 4: 'MULTIPLE_RESERVED', +} +MULTIPLE_BY1 = 0 +MULTIPLE_BY2 = 1 +MULTIPLE_BY3_RESERVED = 2 +MULTIPLE_BY4 = 3 +MULTIPLE_RESERVED = 4 +APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_MUX_SEL' +APG_DBG_MUX_SEL__enumvalues = { + 0: 'APG_FUNCTIONAL_MODE', + 1: 'APG_DEBUG_AUDIO_MODE', +} +APG_FUNCTIONAL_MODE = 0 +APG_DEBUG_AUDIO_MODE = 1 +APG_DBG_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE' +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_POWER_STATE' +APG_MEM_POWER_STATE__enumvalues = { + 0: 'APG_MEM_POWER_STATE_ON', + 1: 'APG_MEM_POWER_STATE_LS', + 2: 'APG_MEM_POWER_STATE_DS', + 3: 'APG_MEM_POWER_STATE_SD', +} +APG_MEM_POWER_STATE_ON = 0 +APG_MEM_POWER_STATE_LS = 1 +APG_MEM_POWER_STATE_DS = 2 +APG_MEM_POWER_STATE_SD = 3 +APG_MEM_POWER_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_DIS_CTRL' +APG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'APG_MEM_DISABLE_MEM_PWR_CTRL', +} +APG_MEM_ENABLE_MEM_PWR_CTRL = 0 +APG_MEM_DISABLE_MEM_PWR_CTRL = 1 +APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_FORCE_CTRL' +APG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'APG_MEM_NO_FORCE_REQUEST', + 1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', +} +APG_MEM_NO_FORCE_REQUEST = 0 +APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE' +APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'APG_ACP_SOURCE_NO_OVERRIDE', + 1: 'APG_ACP_OVERRIDE', +} +APG_ACP_SOURCE_NO_OVERRIDE = 0 +APG_ACP_OVERRIDE = 1 +APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE' +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', +} +APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0 +APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1 +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_RAMP_CONTROL_SIGN' +APG_RAMP_CONTROL_SIGN__enumvalues = { + 0: 'APG_RAMP_SIGNED', + 1: 'APG_RAMP_UNSIGNED', +} +APG_RAMP_SIGNED = 0 +APG_RAMP_UNSIGNED = 1 +APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', +} +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { + 0: 'DCIO_TEST_CLK_SEL_DISPCLK', + 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', + 2: 'DCIO_TEST_CLK_SEL_SOCCLK', +} +DCIO_TEST_CLK_SEL_DISPCLK = 0 +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 +DCIO_TEST_CLK_SEL_SOCCLK = 2 +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { + 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', +} +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' +DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', + 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', +} +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 +DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' +DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', + 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', +} +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 +DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3 +DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' +DCIO_DCRXPHY_SOFT_RESET__enumvalues = { + 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', +} +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 +DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICA_SEL' +DCIO_DC_GENERICA_SEL__enumvalues = { + 1: 'DCIO_GENERICA_SEL_STEREOSYNC', + 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 11: 'DCIO_GENERICA_SEL_SYNCEN', +} +DCIO_GENERICA_SEL_STEREOSYNC = 1 +DCIO_GENERICA_SEL_GENERICA_DCCG = 10 +DCIO_GENERICA_SEL_SYNCEN = 11 +DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICB_SEL' +DCIO_DC_GENERICB_SEL__enumvalues = { + 1: 'DCIO_GENERICB_SEL_STEREOSYNC', + 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 11: 'DCIO_GENERICB_SEL_SYNCEN', +} +DCIO_GENERICB_SEL_STEREOSYNC = 1 +DCIO_GENERICB_SEL_GENERICB_DCCG = 10 +DCIO_GENERICB_SEL_SYNCEN = 11 +DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', +} +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_CLK', +} +DCIO_UNIPHYA_FBDIV_CLK = 0 +DCIO_UNIPHYB_FBDIV_CLK = 1 +DCIO_UNIPHYC_FBDIV_CLK = 2 +DCIO_UNIPHYD_FBDIV_CLK = 3 +DCIO_UNIPHYE_FBDIV_CLK = 4 +DCIO_UNIPHYF_FBDIV_CLK = 5 +DCIO_UNIPHYG_FBDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', +} +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 +DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 +DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 +DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 +DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 +DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 +DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', + 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', + 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', + 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', + 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', + 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', + 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', +} +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 +DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 +DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 +DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 +DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 +DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 +DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { + 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', + 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', +} +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' +DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', +} +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 +DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' +DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DCIO_GPU_TIMER_START_0_END_27', + 1: 'DCIO_GPU_TIMER_START_1_END_28', + 2: 'DCIO_GPU_TIMER_START_2_END_29', + 3: 'DCIO_GPU_TIMER_START_3_END_30', + 4: 'DCIO_GPU_TIMER_START_4_END_31', + 5: 'DCIO_GPU_TIMER_START_6_END_33', + 6: 'DCIO_GPU_TIMER_START_8_END_35', + 7: 'DCIO_GPU_TIMER_START_10_END_37', +} +DCIO_GPU_TIMER_START_0_END_27 = 0 +DCIO_GPU_TIMER_START_1_END_28 = 1 +DCIO_GPU_TIMER_START_2_END_29 = 2 +DCIO_GPU_TIMER_START_3_END_30 = 3 +DCIO_GPU_TIMER_START_4_END_31 = 4 +DCIO_GPU_TIMER_START_6_END_33 = 5 +DCIO_GPU_TIMER_START_8_END_35 = 6 +DCIO_GPU_TIMER_START_10_END_37 = 7 +DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', +} +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', +} +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' +DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MASK_NONE', + 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', + 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', + 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', + 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', + 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', + 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', + 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', +} +DCIO_EXT_VSYNC_MASK_NONE = 0 +DCIO_EXT_VSYNC_MASK_PIPE0 = 1 +DCIO_EXT_VSYNC_MASK_PIPE1 = 2 +DCIO_EXT_VSYNC_MASK_PIPE2 = 3 +DCIO_EXT_VSYNC_MASK_PIPE3 = 4 +DCIO_EXT_VSYNC_MASK_PIPE4 = 5 +DCIO_EXT_VSYNC_MASK_PIPE5 = 6 +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 +DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' +DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 1: 'DCIO_EXT_VSYNC_MUX_OTG0', + 2: 'DCIO_EXT_VSYNC_MUX_OTG1', + 3: 'DCIO_EXT_VSYNC_MUX_OTG2', + 4: 'DCIO_EXT_VSYNC_MUX_OTG3', + 5: 'DCIO_EXT_VSYNC_MUX_OTG4', + 6: 'DCIO_EXT_VSYNC_MUX_OTG5', + 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', +} +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 +DCIO_EXT_VSYNC_MUX_OTG0 = 1 +DCIO_EXT_VSYNC_MUX_OTG1 = 2 +DCIO_EXT_VSYNC_MUX_OTG2 = 3 +DCIO_EXT_VSYNC_MUX_OTG3 = 4 +DCIO_EXT_VSYNC_MUX_OTG4 = 5 +DCIO_EXT_VSYNC_MUX_OTG5 = 6 +DCIO_EXT_VSYNC_MUX_GENERICB = 7 +DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' +DCIO_DPCS_INTERRUPT_MASK__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_DISABLE', + 1: 'DCIO_DPCS_INTERRUPT_ENABLE', +} +DCIO_DPCS_INTERRUPT_DISABLE = 0 +DCIO_DPCS_INTERRUPT_ENABLE = 1 +DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' +DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', +} +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 +DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DSYNC_SOFT_RESET' +DCIO_DSYNC_SOFT_RESET__enumvalues = { + 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', +} +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 +DCIO_DSYNC_SOFT_RESET_ASSERT = 1 +DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' +DCIO_GENLK_CLK_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', + 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', +} +DCIO_GENLK_CLK_GSL_MASK_NO = 0 +DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 +DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 +DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' +DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', +} +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 +DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_SEL' +DCIO_GSL_SEL__enumvalues = { + 0: 'DCIO_GSL_SEL_GROUP_0', + 1: 'DCIO_GSL_SEL_GROUP_1', + 2: 'DCIO_GSL_SEL_GROUP_2', +} +DCIO_GSL_SEL_GROUP_0 = 0 +DCIO_GSL_SEL_GROUP_1 = 1 +DCIO_GSL_SEL_GROUP_2 = 2 +DCIO_GSL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL' +DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = { + 0: 'HPO_SRC0', + 1: 'HPO_SRC_RESERVED', +} +HPO_SRC0 = 0 +HPO_SRC_RESERVED = 1 +DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' +DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' +DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', +} +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' +DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { + 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', +} +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 +DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', +} +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 +DCIO_UNIPHY_CHANNEL_INVERTED = 1 +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { + 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', +} +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' +DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { + 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', + 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', +} +DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 +DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 +DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' +DCIOCHIP_AUX_CSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', +} +DCIOCHIP_AUX_CSEL_DEC1P0 = 0 +DCIOCHIP_AUX_CSEL_DEC0P9 = 1 +DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' +DCIOCHIP_AUX_CSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_INC1P0', + 1: 'DCIOCHIP_AUX_CSEL_INC1P1', +} +DCIOCHIP_AUX_CSEL_INC1P0 = 0 +DCIOCHIP_AUX_CSEL_INC1P1 = 1 +DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' +DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', + 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', +} +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 +DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' +DCIOCHIP_AUX_HYS_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_HYS_TUNE_0', + 1: 'DCIOCHIP_AUX_HYS_TUNE_1', + 2: 'DCIOCHIP_AUX_HYS_TUNE_2', + 3: 'DCIOCHIP_AUX_HYS_TUNE_3', +} +DCIOCHIP_AUX_HYS_TUNE_0 = 0 +DCIOCHIP_AUX_HYS_TUNE_1 = 1 +DCIOCHIP_AUX_HYS_TUNE_2 = 2 +DCIOCHIP_AUX_HYS_TUNE_3 = 3 +DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' +DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', + 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', +} +DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 +DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 +DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 +DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 +DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' +DCIOCHIP_AUX_RSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', +} +DCIOCHIP_AUX_RSEL_DEC1P0 = 0 +DCIOCHIP_AUX_RSEL_DEC0P9 = 1 +DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' +DCIOCHIP_AUX_RSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_INC1P0', + 1: 'DCIOCHIP_AUX_RSEL_INC1P1', +} +DCIOCHIP_AUX_RSEL_INC1P0 = 0 +DCIOCHIP_AUX_RSEL_INC1P1 = 1 +DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' +DCIOCHIP_AUX_SPIKESEL__enumvalues = { + 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', + 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', +} +DCIOCHIP_AUX_SPIKESEL_50NS = 0 +DCIOCHIP_AUX_SPIKESEL_10NS = 1 +DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' +DCIOCHIP_AUX_VOD_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_VOD_TUNE_0', + 1: 'DCIOCHIP_AUX_VOD_TUNE_1', + 2: 'DCIOCHIP_AUX_VOD_TUNE_2', + 3: 'DCIOCHIP_AUX_VOD_TUNE_3', +} +DCIOCHIP_AUX_VOD_TUNE_0 = 0 +DCIOCHIP_AUX_VOD_TUNE_1 = 1 +DCIOCHIP_AUX_VOD_TUNE_2 = 2 +DCIOCHIP_AUX_VOD_TUNE_3 = 3 +DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' +DCIOCHIP_GPIO_MASK_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', +} +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 +DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_HPD_SEL' +DCIOCHIP_HPD_SEL__enumvalues = { + 0: 'DCIOCHIP_HPD_SEL_ASYNC', + 1: 'DCIOCHIP_HPD_SEL_CLOCKED', +} +DCIOCHIP_HPD_SEL_ASYNC = 0 +DCIOCHIP_HPD_SEL_CLOCKED = 1 +DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_COMPSEL' +DCIOCHIP_I2C_COMPSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_REC_SCHMIT', + 1: 'DCIOCHIP_I2C_REC_COMPARATOR', +} +DCIOCHIP_I2C_REC_SCHMIT = 0 +DCIOCHIP_I2C_REC_COMPARATOR = 1 +DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' +DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', + 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', + 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', +} +DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 +DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 +DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 +DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 +DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' +DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', + 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', +} +DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 +DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 +DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 +DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 +DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' +DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { + 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', + 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', +} +DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 +DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 +DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_INVERT' +DCIOCHIP_INVERT__enumvalues = { + 0: 'DCIOCHIP_POL_NON_INVERT', + 1: 'DCIOCHIP_POL_INVERT', +} +DCIOCHIP_POL_NON_INVERT = 0 +DCIOCHIP_POL_INVERT = 1 +DCIOCHIP_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK' +DCIOCHIP_MASK__enumvalues = { + 0: 'DCIOCHIP_MASK_DISABLE', + 1: 'DCIOCHIP_MASK_ENABLE', +} +DCIOCHIP_MASK_DISABLE = 0 +DCIOCHIP_MASK_ENABLE = 1 +DCIOCHIP_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PAD_MODE' +DCIOCHIP_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_PAD_MODE_DDC', + 1: 'DCIOCHIP_PAD_MODE_DP', +} +DCIOCHIP_PAD_MODE_DDC = 0 +DCIOCHIP_PAD_MODE_DP = 1 +DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PD_EN' +DCIOCHIP_PD_EN__enumvalues = { + 0: 'DCIOCHIP_PD_EN_NOTALLOW', + 1: 'DCIOCHIP_PD_EN_ALLOW', +} +DCIOCHIP_PD_EN_NOTALLOW = 0 +DCIOCHIP_PD_EN_ALLOW = 1 +DCIOCHIP_PD_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' +DCIOCHIP_REF_27_SRC_SEL__enumvalues = { + 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', +} +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 +DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', +} +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', +} +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0 +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { + 0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', +} +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_DISABLE', + 1: 'PWRSEQ_BL_PWM_ENABLE', +} +PWRSEQ_BL_PWM_DISABLE = 0 +PWRSEQ_BL_PWM_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', +} +PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0 +PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', +} +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', +} +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK' +PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START' +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_GPIO_MASK_EN' +PWRSEQ_GPIO_MASK_EN__enumvalues = { + 0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', +} +PWRSEQ_GPIO_MASK_EN_HARDWARE = 0 +PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1 +PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_OFF', + 1: 'PWRSEQ_PANEL_BLON_ON', +} +PWRSEQ_PANEL_BLON_OFF = 0 +PWRSEQ_PANEL_BLON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_BLON_POL_INVERT', +} +PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_BLON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_OFF', + 1: 'PWRSEQ_PANEL_DIGON_ON', +} +PWRSEQ_PANEL_DIGON_OFF = 0 +PWRSEQ_PANEL_DIGON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_DIGON_POL_INVERT', +} +PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_DIGON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', +} +PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0 +PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE' +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { + 0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', +} +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0 +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN' +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = { + 0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', +} +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0 +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1 +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_CORB_SIZE' +AZ_CORB_SIZE__enumvalues = { + 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_CORB_SIZE_256ENTRIES', + 3: 'AZ_CORB_SIZE_RESERVED', +} +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 +AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 +AZ_CORB_SIZE_256ENTRIES = 2 +AZ_CORB_SIZE_RESERVED = 3 +AZ_CORB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_GLOBAL_CAPABILITIES' +AZ_GLOBAL_CAPABILITIES__enumvalues = { + 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', +} +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 +AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_SIZE' +AZ_RIRB_SIZE__enumvalues = { + 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_RIRB_SIZE_256ENTRIES', + 3: 'AZ_RIRB_SIZE_UNDEFINED', +} +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 +AZ_RIRB_SIZE_256ENTRIES = 2 +AZ_RIRB_SIZE_UNDEFINED = 3 +AZ_RIRB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' +AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { + 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', + 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', +} +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 +AZ_RIRB_WRITE_POINTER_DO_RESET = 1 +AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_STATE_CHANGE_STATUS' +AZ_STATE_CHANGE_STATUS__enumvalues = { + 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', +} +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 +AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'CORB_READ_POINTER_RESET' +CORB_READ_POINTER_RESET__enumvalues = { + 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', +} +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 +CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { + 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', +} +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { + 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', + 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', +} +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' +GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { + 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', +} +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 +GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' +GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { + 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 1: 'FLUSH_CONTROL_FLUSH_STARTED', +} +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 +FLUSH_CONTROL_FLUSH_STARTED = 1 +GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' +GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { + 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', +} +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 +GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_0_SYNCHRONIZATION' +STREAM_0_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_10_SYNCHRONIZATION' +STREAM_10_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_11_SYNCHRONIZATION' +STREAM_11_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_12_SYNCHRONIZATION' +STREAM_12_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_13_SYNCHRONIZATION' +STREAM_13_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_14_SYNCHRONIZATION' +STREAM_14_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_15_SYNCHRONIZATION' +STREAM_15_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_1_SYNCHRONIZATION' +STREAM_1_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_2_SYNCHRONIZATION' +STREAM_2_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_3_SYNCHRONIZATION' +STREAM_3_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_4_SYNCHRONIZATION' +STREAM_4_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_5_SYNCHRONIZATION' +STREAM_5_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_6_SYNCHRONIZATION' +STREAM_6_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_7_SYNCHRONIZATION' +STREAM_7_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_8_SYNCHRONIZATION' +STREAM_8_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_9_SYNCHRONIZATION' +STREAM_9_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', +} +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { + 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', +} +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_CTRL' +MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'ENABLE_MEM_PWR_CTRL', + 1: 'DISABLE_MEM_PWR_CTRL', +} +ENABLE_MEM_PWR_CTRL = 0 +DISABLE_MEM_PWR_CTRL = 1 +MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL' +MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'NO_FORCE_REQUEST', + 1: 'FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FORCE_DEEP_SLEEP_REQUEST', + 3: 'FORCE_SHUT_DOWN_REQUEST', +} +NO_FORCE_REQUEST = 0 +FORCE_LIGHT_SLEEP_REQUEST = 1 +FORCE_DEEP_SLEEP_REQUEST = 2 +FORCE_SHUT_DOWN_REQUEST = 3 +MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL2' +MEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'NO_FORCE_REQ', + 1: 'FORCE_LIGHT_SLEEP_REQ', +} +NO_FORCE_REQ = 0 +FORCE_LIGHT_SLEEP_REQ = 1 +MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL' +MEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DYNAMIC_SHUT_DOWN_ENABLE = 0 +DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL2' +MEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DYNAMIC_DEEP_SLEEP_EN', + 1: 'DYNAMIC_LIGHT_SLEEP_EN', +} +DYNAMIC_DEEP_SLEEP_EN = 0 +DYNAMIC_LIGHT_SLEEP_EN = 1 +MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { + 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', +} +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' +AZ_LATENCY_COUNTER_CONTROL__enumvalues = { + 0: 'AZ_LATENCY_COUNTER_NO_RESET', + 1: 'AZ_LATENCY_COUNTER_RESET_DONE', +} +AZ_LATENCY_COUNTER_NO_RESET = 0 +AZ_LATENCY_COUNTER_RESET_DONE = 1 +AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', +} +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' +DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' +DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', +} +DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 +DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' +DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', +} +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 +DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ENABLE_ENUM' +DSCC_ENABLE_ENUM__enumvalues = { + 0: 'DSCC_ENABLE_ENUM_DISABLED', + 1: 'DSCC_ENABLE_ENUM_ENABLED', +} +DSCC_ENABLE_ENUM_DISABLED = 0 +DSCC_ENABLE_ENUM_ENABLED = 1 +DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ICH_RESET_ENUM' +DSCC_ICH_RESET_ENUM__enumvalues = { + 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', +} +DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 +DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 +DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 +DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 +DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' +DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { + 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', +} +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 +DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' +DSCC_MEM_PWR_DIS_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', + 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', +} +DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 +DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 +DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' +DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', +} +DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 +DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'POWER_STATE_ENUM' +POWER_STATE_ENUM__enumvalues = { + 0: 'POWER_STATE_ENUM_ON', + 1: 'POWER_STATE_ENUM_LS', + 2: 'POWER_STATE_ENUM_DS', + 3: 'POWER_STATE_ENUM_SD', +} +POWER_STATE_ENUM_ON = 0 +POWER_STATE_ENUM_LS = 1 +POWER_STATE_ENUM_DS = 2 +POWER_STATE_ENUM_SD = 3 +POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' +DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_ENABLE_ENUM' +DSCCIF_ENABLE_ENUM__enumvalues = { + 0: 'DSCCIF_ENABLE_ENUM_DISABLED', + 1: 'DSCCIF_ENABLE_ENUM_ENABLED', +} +DSCCIF_ENABLE_ENUM_DISABLED = 0 +DSCCIF_ENABLE_ENUM_ENABLED = 1 +DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' +DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { + 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', +} +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' +CLOCK_GATING_DISABLE_ENUM__enumvalues = { + 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', + 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', +} +CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 +CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 +CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_ENUM' +ENABLE_ENUM__enumvalues = { + 0: 'ENABLE_ENUM_DISABLED', + 1: 'ENABLE_ENUM_ENABLED', +} +ENABLE_ENUM_DISABLED = 0 +ENABLE_ENUM_ENABLED = 1 +ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' +TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { + 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', +} +TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 +TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 +TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 +TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 +TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 +TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 +TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_CONT_EN_ENUM' +DWB_CRC_CONT_EN_ENUM__enumvalues = { + 0: 'DWB_CRC_CONT_EN_ONE_SHOT', + 1: 'DWB_CRC_CONT_EN_CONT', +} +DWB_CRC_CONT_EN_ONE_SHOT = 0 +DWB_CRC_CONT_EN_CONT = 1 +DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_SRC_SEL_ENUM' +DWB_CRC_SRC_SEL_ENUM__enumvalues = { + 0: 'DWB_CRC_SRC_SEL_DWB_IN', + 1: 'DWB_CRC_SRC_SEL_OGAM_OUT', + 2: 'DWB_CRC_SRC_SEL_DWB_OUT', +} +DWB_CRC_SRC_SEL_DWB_IN = 0 +DWB_CRC_SRC_SEL_OGAM_OUT = 1 +DWB_CRC_SRC_SEL_DWB_OUT = 2 +DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM' +DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_INT_TYPE_0', + 1: 'DWB_DATA_OVERFLOW_INT_TYPE_1', +} +DWB_DATA_OVERFLOW_INT_TYPE_0 = 0 +DWB_DATA_OVERFLOW_INT_TYPE_1 = 1 +DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM' +DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER', + 2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 3: 'DWB_DATA_OVERFLOW_TYPE_VREADY', +} +DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0 +DWB_DATA_OVERFLOW_TYPE_BUFFER = 1 +DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2 +DWB_DATA_OVERFLOW_TYPE_VREADY = 3 +DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DEBUG_SEL_ENUM' +DWB_DEBUG_SEL_ENUM__enumvalues = { + 0: 'DWB_DEBUG_SEL_FC', + 1: 'DWB_DEBUG_SEL_RESERVED', + 2: 'DWB_DEBUG_SEL_DWBCP', + 3: 'DWB_DEBUG_SEL_PERFMON', +} +DWB_DEBUG_SEL_FC = 0 +DWB_DEBUG_SEL_RESERVED = 1 +DWB_DEBUG_SEL_DWBCP = 2 +DWB_DEBUG_SEL_PERFMON = 3 +DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM' +DWB_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_FORCE_DIS', + 1: 'DWB_MEM_PWR_FORCE_LS', + 2: 'DWB_MEM_PWR_FORCE_DS', + 3: 'DWB_MEM_PWR_FORCE_SD', +} +DWB_MEM_PWR_FORCE_DIS = 0 +DWB_MEM_PWR_FORCE_LS = 1 +DWB_MEM_PWR_FORCE_DS = 2 +DWB_MEM_PWR_FORCE_SD = 3 +DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_STATE_ENUM' +DWB_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_STATE_ON', + 1: 'DWB_MEM_PWR_STATE_LS', + 2: 'DWB_MEM_PWR_STATE_DS', + 3: 'DWB_MEM_PWR_STATE_SD', +} +DWB_MEM_PWR_STATE_ON = 0 +DWB_MEM_PWR_STATE_LS = 1 +DWB_MEM_PWR_STATE_DS = 2 +DWB_MEM_PWR_STATE_SD = 3 +DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_TEST_CLK_SEL_ENUM' +DWB_TEST_CLK_SEL_ENUM__enumvalues = { + 0: 'DWB_TEST_CLK_SEL_R', + 1: 'DWB_TEST_CLK_SEL_G', + 2: 'DWB_TEST_CLK_SEL_P', +} +DWB_TEST_CLK_SEL_R = 0 +DWB_TEST_CLK_SEL_G = 1 +DWB_TEST_CLK_SEL_P = 2 +DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_EYE_SELECTION_ENUM' +FC_EYE_SELECTION_ENUM__enumvalues = { + 0: 'FC_EYE_SELECTION_STEREO_DIS', + 1: 'FC_EYE_SELECTION_LEFT_EYE', + 2: 'FC_EYE_SELECTION_RIGHT_EYE', +} +FC_EYE_SELECTION_STEREO_DIS = 0 +FC_EYE_SELECTION_LEFT_EYE = 1 +FC_EYE_SELECTION_RIGHT_EYE = 2 +FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM' +FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = { + 0: 'FC_FRAME_CAPTURE_RATE_FULL', + 1: 'FC_FRAME_CAPTURE_RATE_HALF', + 2: 'FC_FRAME_CAPTURE_RATE_THIRD', + 3: 'FC_FRAME_CAPTURE_RATE_QUARTER', +} +FC_FRAME_CAPTURE_RATE_FULL = 0 +FC_FRAME_CAPTURE_RATE_HALF = 1 +FC_FRAME_CAPTURE_RATE_THIRD = 2 +FC_FRAME_CAPTURE_RATE_QUARTER = 3 +FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM' +FC_STEREO_EYE_POLARITY_ENUM__enumvalues = { + 0: 'FC_STEREO_EYE_POLARITY_LEFT', + 1: 'FC_STEREO_EYE_POLARITY_RIGHT', +} +FC_STEREO_EYE_POLARITY_LEFT = 0 +FC_STEREO_EYE_POLARITY_RIGHT = 1 +FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM' +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM' +DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_MODE_BYPASS', + 1: 'DWB_GAMUT_REMAP_MODE_COEF_A', + 2: 'DWB_GAMUT_REMAP_MODE_COEF_B', + 3: 'DWB_GAMUT_REMAP_MODE_RESERVED', +} +DWB_GAMUT_REMAP_MODE_BYPASS = 0 +DWB_GAMUT_REMAP_MODE_COEF_A = 1 +DWB_GAMUT_REMAP_MODE_COEF_B = 2 +DWB_GAMUT_REMAP_MODE_RESERVED = 3 +DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_LUT_NUM_SEG' +DWB_LUT_NUM_SEG__enumvalues = { + 0: 'DWB_SEGMENTS_1', + 1: 'DWB_SEGMENTS_2', + 2: 'DWB_SEGMENTS_4', + 3: 'DWB_SEGMENTS_8', + 4: 'DWB_SEGMENTS_16', + 5: 'DWB_SEGMENTS_32', + 6: 'DWB_SEGMENTS_64', + 7: 'DWB_SEGMENTS_128', +} +DWB_SEGMENTS_1 = 0 +DWB_SEGMENTS_2 = 1 +DWB_SEGMENTS_4 = 2 +DWB_SEGMENTS_8 = 3 +DWB_SEGMENTS_16 = 4 +DWB_SEGMENTS_32 = 5 +DWB_SEGMENTS_64 = 6 +DWB_SEGMENTS_128 = 7 +DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM' +DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', + 1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME', +} +DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0 +DWB_OGAM_LUT_CONFIG_MODE_SAME = 1 +DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM' +DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_HOST_SEL_RAMA', + 1: 'DWB_OGAM_LUT_HOST_SEL_RAMB', +} +DWB_OGAM_LUT_HOST_SEL_RAMA = 0 +DWB_OGAM_LUT_HOST_SEL_RAMB = 1 +DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM' +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G', + 2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', +} +DWB_OGAM_LUT_READ_COLOR_SEL_B = 0 +DWB_OGAM_LUT_READ_COLOR_SEL_G = 1 +DWB_OGAM_LUT_READ_COLOR_SEL_R = 2 +DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3 +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM' +DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_DBG_DISABLE', + 1: 'DWB_OGAM_LUT_READ_DBG_ENABLE', +} +DWB_OGAM_LUT_READ_DBG_DISABLE = 0 +DWB_OGAM_LUT_READ_DBG_ENABLE = 1 +DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_MODE_ENUM' +DWB_OGAM_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_MODE_BYPASS', + 1: 'DWB_OGAM_MODE_RESERVED', + 2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED', +} +DWB_OGAM_MODE_BYPASS = 0 +DWB_OGAM_MODE_RESERVED = 1 +DWB_OGAM_MODE_RAM_LUT_ENABLED = 2 +DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM' +DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = { + 0: 'DWB_OGAM_PWL_DISABLE_FALSE', + 1: 'DWB_OGAM_PWL_DISABLE_TRUE', +} +DWB_OGAM_PWL_DISABLE_FALSE = 0 +DWB_OGAM_PWL_DISABLE_TRUE = 1 +DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_SELECT_ENUM' +DWB_OGAM_SELECT_ENUM__enumvalues = { + 0: 'DWB_OGAM_SELECT_A', + 1: 'DWB_OGAM_SELECT_B', +} +DWB_OGAM_SELECT_A = 0 +DWB_OGAM_SELECT_B = 1 +DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN' +RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN__enumvalues = { + 0: 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', + 1: 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', +} +RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0 +RDPCSPIPE_EXT_PCLK_EN_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN__enumvalues = { + 0: 'RDPCSPIPE_APBCLK_DISABLE', + 1: 'RDPCSPIPE_APBCLK_ENABLE', +} +RDPCSPIPE_APBCLK_DISABLE = 0 +RDPCSPIPE_APBCLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_PIPE_CLK_CLOCK_OFF', + 1: 'RDPCS_PIPE_CLK_CLOCK_ON', +} +RDPCS_PIPE_CLK_CLOCK_OFF = 0 +RDPCS_PIPE_CLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN__enumvalues = { + 0: 'RDPCS_PIPE_CLK_DISABLE', + 1: 'RDPCS_PIPE_CLK_ENABLE', +} +RDPCS_PIPE_CLK_DISABLE = 0 +RDPCS_PIPE_CLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS__enumvalues = { + 0: 'RDPCS_PIPE_CLK_GATE_ENABLE', + 1: 'RDPCS_PIPE_CLK_GATE_DISABLE', +} +RDPCS_PIPE_CLK_GATE_ENABLE = 0 +RDPCS_PIPE_CLK_GATE_DISABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', + 1: 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', +} +RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0 +RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { + 0: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', + 1: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', +} +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0 +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_DISABLE', + 1: 'RDPCSPIPE_SRAMCLK_ENABLE', +} +RDPCSPIPE_SRAMCLK_DISABLE = 0 +RDPCSPIPE_SRAMCLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', + 1: 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', +} +RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0 +RDPCSPIPE_SRAMCLK_GATE_DISABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_NOT_PASS', + 1: 'RDPCSPIPE_SRAMCLK_PASS', +} +RDPCSPIPE_SRAMCLK_NOT_PASS = 0 +RDPCSPIPE_SRAMCLK_PASS = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN' +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN__enumvalues = { + 0: 'RDPCS_PIPE_FIFO_DISABLE', + 1: 'RDPCS_PIPE_FIFO_ENABLE', +} +RDPCS_PIPE_FIFO_DISABLE = 0 +RDPCS_PIPE_FIFO_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN' +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN__enumvalues = { + 0: 'RDPCS_PIPE_FIFO_LANE_DISABLE', + 1: 'RDPCS_PIPE_FIFO_LANE_ENABLE', +} +RDPCS_PIPE_FIFO_LANE_DISABLE = 0 +RDPCS_PIPE_FIFO_LANE_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET' +RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET__enumvalues = { + 0: 'RDPCS_PIPE_SOFT_RESET_DISABLE', + 1: 'RDPCS_PIPE_SOFT_RESET_ENABLE', +} +RDPCS_PIPE_SOFT_RESET_DISABLE = 0 +RDPCS_PIPE_SOFT_RESET_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET' +RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { + 0: 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', + 1: 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', +} +RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0 +RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK' +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', + 1: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', +} +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0 +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 1 +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_DBG_OCLA_SEL' +RDPCSPIPE_DBG_OCLA_SEL__enumvalues = { + 0: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', + 1: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', + 2: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', + 3: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', + 4: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', + 5: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', + 6: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', + 7: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', +} +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 1 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 2 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 3 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 4 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 5 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 6 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 7 +RDPCSPIPE_DBG_OCLA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_ENC_TYPE' +RDPCSPIPE_ENC_TYPE__enumvalues = { + 0: 'HDMI_TMDS_OR_DP_8B10B', + 1: 'HDMI_FRL', + 2: 'DP_128B132B', +} +HDMI_TMDS_OR_DP_8B10B = 0 +HDMI_FRL = 1 +DP_128B132B = 2 +RDPCSPIPE_ENC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_FIFO_EMPTY' +RDPCSPIPE_FIFO_EMPTY__enumvalues = { + 0: 'RDPCSPIPE_FIFO_NOT_EMPTY', + 1: 'RDPCSPIPE_FIFO_IS_EMPTY', +} +RDPCSPIPE_FIFO_NOT_EMPTY = 0 +RDPCSPIPE_FIFO_IS_EMPTY = 1 +RDPCSPIPE_FIFO_EMPTY = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_FIFO_FULL' +RDPCSPIPE_FIFO_FULL__enumvalues = { + 0: 'RDPCSPIPE_FIFO_NOT_FULL', + 1: 'RDPCSPIPE_FIFO_IS_FULL', +} +RDPCSPIPE_FIFO_NOT_FULL = 0 +RDPCSPIPE_FIFO_IS_FULL = 1 +RDPCSPIPE_FIFO_FULL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK__enumvalues = { + 0: 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', + 1: 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', +} +RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0 +RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { + 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', + 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', +} +RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0 +RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', +} +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { + 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', + 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', +} +RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0 +RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', +} +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', +} +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0 +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', +} +RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0 +RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK' +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK__enumvalues = { + 0: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', + 1: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', +} +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0 +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 1 +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PACK_MODE' +RDPCSPIPE_PACK_MODE__enumvalues = { + 0: 'TIGHT_PACK', + 1: 'LOOSE_PACK', +} +TIGHT_PACK = 0 +LOOSE_PACK = 1 +RDPCSPIPE_PACK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { + 0: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', + 1: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', +} +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0 +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { + 0: 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', + 1: 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', +} +RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0 +RDPCSPIPE_PHY_CR_PARA_SEL_CR = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { + 0: 'RDPCSPIPE_PHY_REF_RANGE_0', + 1: 'RDPCSPIPE_PHY_REF_RANGE_1', + 2: 'RDPCSPIPE_PHY_REF_RANGE_2', + 3: 'RDPCSPIPE_PHY_REF_RANGE_3', + 4: 'RDPCSPIPE_PHY_REF_RANGE_4', + 5: 'RDPCSPIPE_PHY_REF_RANGE_5', + 6: 'RDPCSPIPE_PHY_REF_RANGE_6', + 7: 'RDPCSPIPE_PHY_REF_RANGE_7', +} +RDPCSPIPE_PHY_REF_RANGE_0 = 0 +RDPCSPIPE_PHY_REF_RANGE_1 = 1 +RDPCSPIPE_PHY_REF_RANGE_2 = 2 +RDPCSPIPE_PHY_REF_RANGE_3 = 3 +RDPCSPIPE_PHY_REF_RANGE_4 = 4 +RDPCSPIPE_PHY_REF_RANGE_5 = 5 +RDPCSPIPE_PHY_REF_RANGE_6 = 6 +RDPCSPIPE_PHY_REF_RANGE_7 = 7 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { + 0: 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', + 1: 'RDPCSPIPE_SRAM_EXT_LD_DONE', +} +RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0 +RDPCSPIPE_SRAM_EXT_LD_DONE = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { + 0: 'RDPCSPIPE_SRAM_INIT_NOT_DONE', + 1: 'RDPCSPIPE_SRAM_INIT_DONE', +} +RDPCSPIPE_SRAM_INIT_NOT_DONE = 0 +RDPCSPIPE_SRAM_INIT_DONE = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', + 1: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', + 2: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', + 3: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', + 4: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', +} +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 1: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 2: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 3: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', +} +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' +RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', + 1: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', + 2: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', + 3: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', + 4: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', + 5: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', + 6: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', + 7: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', +} +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 +RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' +RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', + 1: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', + 2: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', + 3: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', + 4: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', + 5: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', + 6: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', + 7: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', +} +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 1 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 2 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 3 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 4 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 5 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 6 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 7 +RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 1: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', +} +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 1 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_RATE', + 1: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', + 2: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', +} +RDPCSPIPE_PHY_DP_TX_RATE = 0 +RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 1 +RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 2 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', + 1: 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', + 2: 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', + 3: 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', +} +RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0 +RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 1 +RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 2 +RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 3 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' +RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { + 0: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', + 1: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', + 2: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', + 3: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', +} +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0 +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 1 +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 2 +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 3 +RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_IF_WIDTH' +RDPCSPIPE_PHY_IF_WIDTH__enumvalues = { + 0: 'PHY_IF_WIDTH_10BIT', + 1: 'PHY_IF_WIDTH_20BIT', + 2: 'PHY_IF_WIDTH_40BIT', + 3: 'PHY_IF_WIDTH_80BIT', +} +PHY_IF_WIDTH_10BIT = 0 +PHY_IF_WIDTH_20BIT = 1 +PHY_IF_WIDTH_40BIT = 2 +PHY_IF_WIDTH_80BIT = 3 +RDPCSPIPE_PHY_IF_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_RATE' +RDPCSPIPE_PHY_RATE__enumvalues = { + 0: 'PHY_DP_RATE_1P62', + 1: 'PHY_DP_RATE_2P7', + 2: 'PHY_DP_RATE_5P4', + 3: 'PHY_DP_RATE_8P1', + 4: 'PHY_DP_RATE_2P16', + 5: 'PHY_DP_RATE_2P43', + 6: 'PHY_DP_RATE_3P24', + 7: 'PHY_DP_RATE_4P32', + 8: 'PHY_DP_RATE_10P', + 9: 'PHY_DP_RATE_13P5', + 10: 'PHY_DP_RATE_20P', + 15: 'PHY_CUSTOM_RATE', +} +PHY_DP_RATE_1P62 = 0 +PHY_DP_RATE_2P7 = 1 +PHY_DP_RATE_5P4 = 2 +PHY_DP_RATE_8P1 = 3 +PHY_DP_RATE_2P16 = 4 +PHY_DP_RATE_2P43 = 5 +PHY_DP_RATE_3P24 = 6 +PHY_DP_RATE_4P32 = 7 +PHY_DP_RATE_10P = 8 +PHY_DP_RATE_13P5 = 9 +PHY_DP_RATE_20P = 10 +PHY_CUSTOM_RATE = 15 +RDPCSPIPE_PHY_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_REF_ALT_CLK_EN' +RDPCSPIPE_PHY_REF_ALT_CLK_EN__enumvalues = { + 0: 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', + 1: 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', +} +RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0 +RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 1 +RDPCSPIPE_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_TEST_CLK_SEL' +RDPCSPIPE_TEST_CLK_SEL__enumvalues = { + 0: 'RDPCSPIPE_TEST_CLK_SEL_NONE', + 1: 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', + 2: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 3: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 4: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 5: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 6: 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', + 7: 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', + 8: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 9: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 10: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 11: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 12: 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 13: 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 14: 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 15: 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', + 16: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', + 17: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', +} +RDPCSPIPE_TEST_CLK_SEL_NONE = 0 +RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 1 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 +RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 6 +RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 7 +RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 +RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 +RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 +RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 +RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 +RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 +RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 +RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 15 +RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 16 +RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 17 +RDPCSPIPE_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB' +RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = { + 0: 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', + 1: 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', +} +RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0 +RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 1 +RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { + 0: 'RDPCSPIPE_MEM_PWR_NO_FORCE', + 1: 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', + 2: 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', + 3: 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', +} +RDPCSPIPE_MEM_PWR_NO_FORCE = 0 +RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 1 +RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 2 +RDPCSPIPE_MEM_PWR_SHUT_DOWN = 3 +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { + 0: 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', + 1: 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 2: 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 3: 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', +} +RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0 +RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 +RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 +RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK' +RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = { + 0: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', + 1: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', +} +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0 +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 1 +RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum + +# values for enumeration 'GDS_PERFCOUNT_SELECT' +GDS_PERFCOUNT_SELECT__enumvalues = { + 0: 'GDS_PERF_SEL_WR_COMP', + 1: 'GDS_PERF_SEL_WBUF_WR', + 2: 'GDS_PERF_SEL_SE0_NORET', + 3: 'GDS_PERF_SEL_SE0_RET', + 4: 'GDS_PERF_SEL_SE0_ORD_CNT', + 5: 'GDS_PERF_SEL_SE0_2COMP_REQ', + 6: 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', + 7: 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', + 8: 'GDS_PERF_SEL_SE0_GDS_WR_OP', + 9: 'GDS_PERF_SEL_SE0_GDS_RD_OP', + 10: 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', + 11: 'GDS_PERF_SEL_SE0_GDS_REL_OP', + 12: 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', + 13: 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', + 14: 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', + 15: 'GDS_PERF_SEL_SE1_NORET', + 16: 'GDS_PERF_SEL_SE1_RET', + 17: 'GDS_PERF_SEL_SE1_ORD_CNT', + 18: 'GDS_PERF_SEL_SE1_2COMP_REQ', + 19: 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', + 20: 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', + 21: 'GDS_PERF_SEL_SE1_GDS_WR_OP', + 22: 'GDS_PERF_SEL_SE1_GDS_RD_OP', + 23: 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', + 24: 'GDS_PERF_SEL_SE1_GDS_REL_OP', + 25: 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', + 26: 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', + 27: 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', + 28: 'GDS_PERF_SEL_SE2_NORET', + 29: 'GDS_PERF_SEL_SE2_RET', + 30: 'GDS_PERF_SEL_SE2_ORD_CNT', + 31: 'GDS_PERF_SEL_SE2_2COMP_REQ', + 32: 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', + 33: 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', + 34: 'GDS_PERF_SEL_SE2_GDS_WR_OP', + 35: 'GDS_PERF_SEL_SE2_GDS_RD_OP', + 36: 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', + 37: 'GDS_PERF_SEL_SE2_GDS_REL_OP', + 38: 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', + 39: 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', + 40: 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', + 41: 'GDS_PERF_SEL_SE3_NORET', + 42: 'GDS_PERF_SEL_SE3_RET', + 43: 'GDS_PERF_SEL_SE3_ORD_CNT', + 44: 'GDS_PERF_SEL_SE3_2COMP_REQ', + 45: 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', + 46: 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', + 47: 'GDS_PERF_SEL_SE3_GDS_WR_OP', + 48: 'GDS_PERF_SEL_SE3_GDS_RD_OP', + 49: 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', + 50: 'GDS_PERF_SEL_SE3_GDS_REL_OP', + 51: 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', + 52: 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', + 53: 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', + 54: 'GDS_PERF_SEL_SE4_NORET', + 55: 'GDS_PERF_SEL_SE4_RET', + 56: 'GDS_PERF_SEL_SE4_ORD_CNT', + 57: 'GDS_PERF_SEL_SE4_2COMP_REQ', + 58: 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', + 59: 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', + 60: 'GDS_PERF_SEL_SE4_GDS_WR_OP', + 61: 'GDS_PERF_SEL_SE4_GDS_RD_OP', + 62: 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', + 63: 'GDS_PERF_SEL_SE4_GDS_REL_OP', + 64: 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', + 65: 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', + 66: 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', + 67: 'GDS_PERF_SEL_SE5_NORET', + 68: 'GDS_PERF_SEL_SE5_RET', + 69: 'GDS_PERF_SEL_SE5_ORD_CNT', + 70: 'GDS_PERF_SEL_SE5_2COMP_REQ', + 71: 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', + 72: 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', + 73: 'GDS_PERF_SEL_SE5_GDS_WR_OP', + 74: 'GDS_PERF_SEL_SE5_GDS_RD_OP', + 75: 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', + 76: 'GDS_PERF_SEL_SE5_GDS_REL_OP', + 77: 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', + 78: 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', + 79: 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', + 80: 'GDS_PERF_SEL_SE6_NORET', + 81: 'GDS_PERF_SEL_SE6_RET', + 82: 'GDS_PERF_SEL_SE6_ORD_CNT', + 83: 'GDS_PERF_SEL_SE6_2COMP_REQ', + 84: 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', + 85: 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', + 86: 'GDS_PERF_SEL_SE6_GDS_WR_OP', + 87: 'GDS_PERF_SEL_SE6_GDS_RD_OP', + 88: 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', + 89: 'GDS_PERF_SEL_SE6_GDS_REL_OP', + 90: 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', + 91: 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', + 92: 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', + 93: 'GDS_PERF_SEL_SE7_NORET', + 94: 'GDS_PERF_SEL_SE7_RET', + 95: 'GDS_PERF_SEL_SE7_ORD_CNT', + 96: 'GDS_PERF_SEL_SE7_2COMP_REQ', + 97: 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', + 98: 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', + 99: 'GDS_PERF_SEL_SE7_GDS_WR_OP', + 100: 'GDS_PERF_SEL_SE7_GDS_RD_OP', + 101: 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', + 102: 'GDS_PERF_SEL_SE7_GDS_REL_OP', + 103: 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', + 104: 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', + 105: 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', + 106: 'GDS_PERF_SEL_GWS_RELEASED', + 107: 'GDS_PERF_SEL_GWS_BYPASS', +} +GDS_PERF_SEL_WR_COMP = 0 +GDS_PERF_SEL_WBUF_WR = 1 +GDS_PERF_SEL_SE0_NORET = 2 +GDS_PERF_SEL_SE0_RET = 3 +GDS_PERF_SEL_SE0_ORD_CNT = 4 +GDS_PERF_SEL_SE0_2COMP_REQ = 5 +GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 6 +GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 7 +GDS_PERF_SEL_SE0_GDS_WR_OP = 8 +GDS_PERF_SEL_SE0_GDS_RD_OP = 9 +GDS_PERF_SEL_SE0_GDS_ATOM_OP = 10 +GDS_PERF_SEL_SE0_GDS_REL_OP = 11 +GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 12 +GDS_PERF_SEL_SE0_GDS_BYTE_OP = 13 +GDS_PERF_SEL_SE0_GDS_SHORT_OP = 14 +GDS_PERF_SEL_SE1_NORET = 15 +GDS_PERF_SEL_SE1_RET = 16 +GDS_PERF_SEL_SE1_ORD_CNT = 17 +GDS_PERF_SEL_SE1_2COMP_REQ = 18 +GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 19 +GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 20 +GDS_PERF_SEL_SE1_GDS_WR_OP = 21 +GDS_PERF_SEL_SE1_GDS_RD_OP = 22 +GDS_PERF_SEL_SE1_GDS_ATOM_OP = 23 +GDS_PERF_SEL_SE1_GDS_REL_OP = 24 +GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 25 +GDS_PERF_SEL_SE1_GDS_BYTE_OP = 26 +GDS_PERF_SEL_SE1_GDS_SHORT_OP = 27 +GDS_PERF_SEL_SE2_NORET = 28 +GDS_PERF_SEL_SE2_RET = 29 +GDS_PERF_SEL_SE2_ORD_CNT = 30 +GDS_PERF_SEL_SE2_2COMP_REQ = 31 +GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 32 +GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 33 +GDS_PERF_SEL_SE2_GDS_WR_OP = 34 +GDS_PERF_SEL_SE2_GDS_RD_OP = 35 +GDS_PERF_SEL_SE2_GDS_ATOM_OP = 36 +GDS_PERF_SEL_SE2_GDS_REL_OP = 37 +GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 38 +GDS_PERF_SEL_SE2_GDS_BYTE_OP = 39 +GDS_PERF_SEL_SE2_GDS_SHORT_OP = 40 +GDS_PERF_SEL_SE3_NORET = 41 +GDS_PERF_SEL_SE3_RET = 42 +GDS_PERF_SEL_SE3_ORD_CNT = 43 +GDS_PERF_SEL_SE3_2COMP_REQ = 44 +GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 45 +GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 46 +GDS_PERF_SEL_SE3_GDS_WR_OP = 47 +GDS_PERF_SEL_SE3_GDS_RD_OP = 48 +GDS_PERF_SEL_SE3_GDS_ATOM_OP = 49 +GDS_PERF_SEL_SE3_GDS_REL_OP = 50 +GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 51 +GDS_PERF_SEL_SE3_GDS_BYTE_OP = 52 +GDS_PERF_SEL_SE3_GDS_SHORT_OP = 53 +GDS_PERF_SEL_SE4_NORET = 54 +GDS_PERF_SEL_SE4_RET = 55 +GDS_PERF_SEL_SE4_ORD_CNT = 56 +GDS_PERF_SEL_SE4_2COMP_REQ = 57 +GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 58 +GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 59 +GDS_PERF_SEL_SE4_GDS_WR_OP = 60 +GDS_PERF_SEL_SE4_GDS_RD_OP = 61 +GDS_PERF_SEL_SE4_GDS_ATOM_OP = 62 +GDS_PERF_SEL_SE4_GDS_REL_OP = 63 +GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 64 +GDS_PERF_SEL_SE4_GDS_BYTE_OP = 65 +GDS_PERF_SEL_SE4_GDS_SHORT_OP = 66 +GDS_PERF_SEL_SE5_NORET = 67 +GDS_PERF_SEL_SE5_RET = 68 +GDS_PERF_SEL_SE5_ORD_CNT = 69 +GDS_PERF_SEL_SE5_2COMP_REQ = 70 +GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 71 +GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 72 +GDS_PERF_SEL_SE5_GDS_WR_OP = 73 +GDS_PERF_SEL_SE5_GDS_RD_OP = 74 +GDS_PERF_SEL_SE5_GDS_ATOM_OP = 75 +GDS_PERF_SEL_SE5_GDS_REL_OP = 76 +GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 77 +GDS_PERF_SEL_SE5_GDS_BYTE_OP = 78 +GDS_PERF_SEL_SE5_GDS_SHORT_OP = 79 +GDS_PERF_SEL_SE6_NORET = 80 +GDS_PERF_SEL_SE6_RET = 81 +GDS_PERF_SEL_SE6_ORD_CNT = 82 +GDS_PERF_SEL_SE6_2COMP_REQ = 83 +GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 84 +GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 85 +GDS_PERF_SEL_SE6_GDS_WR_OP = 86 +GDS_PERF_SEL_SE6_GDS_RD_OP = 87 +GDS_PERF_SEL_SE6_GDS_ATOM_OP = 88 +GDS_PERF_SEL_SE6_GDS_REL_OP = 89 +GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 90 +GDS_PERF_SEL_SE6_GDS_BYTE_OP = 91 +GDS_PERF_SEL_SE6_GDS_SHORT_OP = 92 +GDS_PERF_SEL_SE7_NORET = 93 +GDS_PERF_SEL_SE7_RET = 94 +GDS_PERF_SEL_SE7_ORD_CNT = 95 +GDS_PERF_SEL_SE7_2COMP_REQ = 96 +GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 97 +GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 98 +GDS_PERF_SEL_SE7_GDS_WR_OP = 99 +GDS_PERF_SEL_SE7_GDS_RD_OP = 100 +GDS_PERF_SEL_SE7_GDS_ATOM_OP = 101 +GDS_PERF_SEL_SE7_GDS_REL_OP = 102 +GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 103 +GDS_PERF_SEL_SE7_GDS_BYTE_OP = 104 +GDS_PERF_SEL_SE7_GDS_SHORT_OP = 105 +GDS_PERF_SEL_GWS_RELEASED = 106 +GDS_PERF_SEL_GWS_BYPASS = 107 +GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOp' +BlendOp__enumvalues = { + 0: 'BLEND_ZERO', + 1: 'BLEND_ONE', + 2: 'BLEND_SRC_COLOR', + 3: 'BLEND_ONE_MINUS_SRC_COLOR', + 4: 'BLEND_SRC_ALPHA', + 5: 'BLEND_ONE_MINUS_SRC_ALPHA', + 6: 'BLEND_DST_ALPHA', + 7: 'BLEND_ONE_MINUS_DST_ALPHA', + 8: 'BLEND_DST_COLOR', + 9: 'BLEND_ONE_MINUS_DST_COLOR', + 10: 'BLEND_SRC_ALPHA_SATURATE', + 11: 'BLEND_CONSTANT_COLOR', + 12: 'BLEND_ONE_MINUS_CONSTANT_COLOR', + 13: 'BLEND_SRC1_COLOR', + 14: 'BLEND_INV_SRC1_COLOR', + 15: 'BLEND_SRC1_ALPHA', + 16: 'BLEND_INV_SRC1_ALPHA', + 17: 'BLEND_CONSTANT_ALPHA', + 18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', +} +BLEND_ZERO = 0 +BLEND_ONE = 1 +BLEND_SRC_COLOR = 2 +BLEND_ONE_MINUS_SRC_COLOR = 3 +BLEND_SRC_ALPHA = 4 +BLEND_ONE_MINUS_SRC_ALPHA = 5 +BLEND_DST_ALPHA = 6 +BLEND_ONE_MINUS_DST_ALPHA = 7 +BLEND_DST_COLOR = 8 +BLEND_ONE_MINUS_DST_COLOR = 9 +BLEND_SRC_ALPHA_SATURATE = 10 +BLEND_CONSTANT_COLOR = 11 +BLEND_ONE_MINUS_CONSTANT_COLOR = 12 +BLEND_SRC1_COLOR = 13 +BLEND_INV_SRC1_COLOR = 14 +BLEND_SRC1_ALPHA = 15 +BLEND_INV_SRC1_ALPHA = 16 +BLEND_CONSTANT_ALPHA = 17 +BLEND_ONE_MINUS_CONSTANT_ALPHA = 18 +BlendOp = ctypes.c_uint32 # enum +GL__ZERO = BLEND_ZERO # macro +GL__ONE = BLEND_ONE # macro +GL__SRC_COLOR = BLEND_SRC_COLOR # macro +GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro +GL__DST_COLOR = BLEND_DST_COLOR # macro +GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro +GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro +GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro +GL__DST_ALPHA = BLEND_DST_ALPHA # macro +GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro +GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro +GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro +GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro +GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro +GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro + +# values for enumeration 'BlendOpt' +BlendOpt__enumvalues = { + 0: 'FORCE_OPT_AUTO', + 1: 'FORCE_OPT_DISABLE', + 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', + 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', + 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', +} +FORCE_OPT_AUTO = 0 +FORCE_OPT_DISABLE = 1 +FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 +FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 +BlendOpt = ctypes.c_uint32 # enum + +# values for enumeration 'CBMode' +CBMode__enumvalues = { + 0: 'CB_DISABLE', + 1: 'CB_NORMAL', + 2: 'CB_ELIMINATE_FAST_CLEAR', + 3: 'CB_DCC_DECOMPRESS', + 4: 'CB_RESERVED', +} +CB_DISABLE = 0 +CB_NORMAL = 1 +CB_ELIMINATE_FAST_CLEAR = 2 +CB_DCC_DECOMPRESS = 3 +CB_RESERVED = 4 +CBMode = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfClearFilterSel' +CBPerfClearFilterSel__enumvalues = { + 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', +} +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 +CBPerfClearFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfOpFilterSel' +CBPerfOpFilterSel__enumvalues = { + 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', +} +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 +CB_PERF_OP_FILTER_SEL_RESOLVE = 2 +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 +CBPerfOpFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfSel' +CBPerfSel__enumvalues = { + 0: 'CB_PERF_SEL_NONE', + 1: 'CB_PERF_SEL_DRAWN_PIXEL', + 2: 'CB_PERF_SEL_DRAWN_QUAD', + 3: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', + 4: 'CB_PERF_SEL_DRAWN_TILE', + 5: 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', + 6: 'CB_PERF_SEL_FILTER_DRAWN_QUAD', + 7: 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', + 8: 'CB_PERF_SEL_FILTER_DRAWN_TILE', + 9: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', + 10: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', + 11: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', + 12: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', + 13: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 14: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 15: 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 16: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 17: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 18: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', + 19: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 20: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 21: 'CB_PERF_SEL_RESERVED_21', + 22: 'CB_PERF_SEL_RESERVED_22', + 23: 'CB_PERF_SEL_RESERVED_23', + 24: 'CB_PERF_SEL_RESERVED_24', + 25: 'CB_PERF_SEL_RESERVED_25', + 26: 'CB_PERF_SEL_RESERVED_26', + 27: 'CB_PERF_SEL_RESERVED_27', + 28: 'CB_PERF_SEL_RESERVED_28', + 29: 'CB_PERF_SEL_RESERVED_29', + 30: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', + 31: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', + 32: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', + 33: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', + 34: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', + 35: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', + 36: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', + 37: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', + 38: 'CB_PERF_SEL_RESERVED_38', + 39: 'CB_PERF_SEL_RESERVED_39', + 40: 'CB_PERF_SEL_RESERVED_40', + 41: 'CB_PERF_SEL_RESERVED_41', + 42: 'CB_PERF_SEL_RESERVED_42', + 43: 'CB_PERF_SEL_RESERVED_43', + 44: 'CB_PERF_SEL_RESERVED_44', + 45: 'CB_PERF_SEL_RESERVED_45', + 46: 'CB_PERF_SEL_RESERVED_46', + 47: 'CB_PERF_SEL_RESERVED_47', + 48: 'CB_PERF_SEL_RESERVED_48', + 49: 'CB_PERF_SEL_RESERVED_49', + 50: 'CB_PERF_SEL_STATIC_CLOCK_EN', + 51: 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 52: 'CB_PERF_SEL_BLEND_CLOCK_EN', + 53: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 54: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 55: 'CB_PERF_SEL_GRBM_CLOCK_EN', + 56: 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 57: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 58: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 59: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 60: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 61: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 62: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 63: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 64: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 65: 'CB_PERF_SEL_RESERVED_65', + 66: 'CB_PERF_SEL_RESERVED_66', + 67: 'CB_PERF_SEL_RESERVED_67', + 68: 'CB_PERF_SEL_RESERVED_68', + 69: 'CB_PERF_SEL_RESERVED_69', + 70: 'CB_PERF_SEL_RESERVED_70', + 71: 'CB_PERF_SEL_RESERVED_71', + 72: 'CB_PERF_SEL_RESERVED_72', + 73: 'CB_PERF_SEL_RESERVED_73', + 74: 'CB_PERF_SEL_RESERVED_74', + 75: 'CB_PERF_SEL_RESERVED_75', + 76: 'CB_PERF_SEL_RESERVED_76', + 77: 'CB_PERF_SEL_RESERVED_77', + 78: 'CB_PERF_SEL_RESERVED_78', + 79: 'CB_PERF_SEL_RESERVED_79', + 80: 'CB_PERF_SEL_RESERVED_80', + 81: 'CB_PERF_SEL_RESERVED_81', + 82: 'CB_PERF_SEL_RESERVED_82', + 83: 'CB_PERF_SEL_RESERVED_83', + 84: 'CB_PERF_SEL_RESERVED_84', + 85: 'CB_PERF_SEL_RESERVED_85', + 86: 'CB_PERF_SEL_RESERVED_86', + 87: 'CB_PERF_SEL_RESERVED_87', + 88: 'CB_PERF_SEL_RESERVED_88', + 89: 'CB_PERF_SEL_RESERVED_89', + 90: 'CB_PERF_SEL_RESERVED_90', + 91: 'CB_PERF_SEL_RESERVED_91', + 92: 'CB_PERF_SEL_RESERVED_92', + 93: 'CB_PERF_SEL_RESERVED_93', + 94: 'CB_PERF_SEL_RESERVED_94', + 95: 'CB_PERF_SEL_RESERVED_95', + 96: 'CB_PERF_SEL_RESERVED_96', + 97: 'CB_PERF_SEL_RESERVED_97', + 98: 'CB_PERF_SEL_RESERVED_98', + 99: 'CB_PERF_SEL_RESERVED_99', + 100: 'CB_PERF_SEL_CC_TAG_HIT', + 101: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 102: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', + 103: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 104: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 105: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 106: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 107: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 108: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 109: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 110: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 111: 'CB_PERF_SEL_CC_CACHE_STALL', + 112: 'CB_PERF_SEL_CC_CACHE_FLUSH', + 113: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 114: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 115: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 116: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 117: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 118: 'CB_PERF_SEL_RESERVED_118', + 119: 'CB_PERF_SEL_RESERVED_119', + 120: 'CB_PERF_SEL_RESERVED_120', + 121: 'CB_PERF_SEL_RESERVED_121', + 122: 'CB_PERF_SEL_RESERVED_122', + 123: 'CB_PERF_SEL_RESERVED_123', + 124: 'CB_PERF_SEL_RESERVED_124', + 125: 'CB_PERF_SEL_RESERVED_125', + 126: 'CB_PERF_SEL_RESERVED_126', + 127: 'CB_PERF_SEL_RESERVED_127', + 128: 'CB_PERF_SEL_RESERVED_128', + 129: 'CB_PERF_SEL_RESERVED_129', + 130: 'CB_PERF_SEL_RESERVED_130', + 131: 'CB_PERF_SEL_RESERVED_131', + 132: 'CB_PERF_SEL_RESERVED_132', + 133: 'CB_PERF_SEL_RESERVED_133', + 134: 'CB_PERF_SEL_RESERVED_134', + 135: 'CB_PERF_SEL_RESERVED_135', + 136: 'CB_PERF_SEL_RESERVED_136', + 137: 'CB_PERF_SEL_RESERVED_137', + 138: 'CB_PERF_SEL_RESERVED_138', + 139: 'CB_PERF_SEL_RESERVED_139', + 140: 'CB_PERF_SEL_RESERVED_140', + 141: 'CB_PERF_SEL_RESERVED_141', + 142: 'CB_PERF_SEL_RESERVED_142', + 143: 'CB_PERF_SEL_RESERVED_143', + 144: 'CB_PERF_SEL_RESERVED_144', + 145: 'CB_PERF_SEL_RESERVED_145', + 146: 'CB_PERF_SEL_RESERVED_146', + 147: 'CB_PERF_SEL_RESERVED_147', + 148: 'CB_PERF_SEL_RESERVED_148', + 149: 'CB_PERF_SEL_RESERVED_149', + 150: 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', + 151: 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', + 152: 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', + 153: 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', + 154: 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 155: 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 156: 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 157: 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', + 158: 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', + 159: 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', + 160: 'CB_PERF_SEL_DCC_CACHE_STALL', + 161: 'CB_PERF_SEL_DCC_CACHE_FLUSH', + 162: 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', + 163: 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 164: 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', + 165: 'CB_PERF_SEL_RESERVED_165', + 166: 'CB_PERF_SEL_RESERVED_166', + 167: 'CB_PERF_SEL_RESERVED_167', + 168: 'CB_PERF_SEL_RESERVED_168', + 169: 'CB_PERF_SEL_RESERVED_169', + 170: 'CB_PERF_SEL_RESERVED_170', + 171: 'CB_PERF_SEL_RESERVED_171', + 172: 'CB_PERF_SEL_RESERVED_172', + 173: 'CB_PERF_SEL_RESERVED_173', + 174: 'CB_PERF_SEL_RESERVED_174', + 175: 'CB_PERF_SEL_RESERVED_175', + 176: 'CB_PERF_SEL_RESERVED_176', + 177: 'CB_PERF_SEL_RESERVED_177', + 178: 'CB_PERF_SEL_RESERVED_178', + 179: 'CB_PERF_SEL_RESERVED_179', + 180: 'CB_PERF_SEL_RESERVED_180', + 181: 'CB_PERF_SEL_RESERVED_181', + 182: 'CB_PERF_SEL_RESERVED_182', + 183: 'CB_PERF_SEL_RESERVED_183', + 184: 'CB_PERF_SEL_RESERVED_184', + 185: 'CB_PERF_SEL_RESERVED_185', + 186: 'CB_PERF_SEL_RESERVED_186', + 187: 'CB_PERF_SEL_RESERVED_187', + 188: 'CB_PERF_SEL_RESERVED_188', + 189: 'CB_PERF_SEL_RESERVED_189', + 190: 'CB_PERF_SEL_RESERVED_190', + 191: 'CB_PERF_SEL_RESERVED_191', + 192: 'CB_PERF_SEL_RESERVED_192', + 193: 'CB_PERF_SEL_RESERVED_193', + 194: 'CB_PERF_SEL_RESERVED_194', + 195: 'CB_PERF_SEL_RESERVED_195', + 196: 'CB_PERF_SEL_RESERVED_196', + 197: 'CB_PERF_SEL_RESERVED_197', + 198: 'CB_PERF_SEL_RESERVED_198', + 199: 'CB_PERF_SEL_RESERVED_199', + 200: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 201: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 202: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 203: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 204: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 205: 'CB_PERF_SEL_RESERVED_205', + 206: 'CB_PERF_SEL_RESERVED_206', + 207: 'CB_PERF_SEL_RESERVED_207', + 208: 'CB_PERF_SEL_RESERVED_208', + 209: 'CB_PERF_SEL_RESERVED_209', + 210: 'CB_PERF_SEL_RESERVED_210', + 211: 'CB_PERF_SEL_RESERVED_211', + 212: 'CB_PERF_SEL_RESERVED_212', + 213: 'CB_PERF_SEL_RESERVED_213', + 214: 'CB_PERF_SEL_RESERVED_214', + 215: 'CB_PERF_SEL_RESERVED_215', + 216: 'CB_PERF_SEL_RESERVED_216', + 217: 'CB_PERF_SEL_RESERVED_217', + 218: 'CB_PERF_SEL_RESERVED_218', + 219: 'CB_PERF_SEL_RESERVED_219', + 220: 'CB_PERF_SEL_RESERVED_220', + 221: 'CB_PERF_SEL_RESERVED_221', + 222: 'CB_PERF_SEL_RESERVED_222', + 223: 'CB_PERF_SEL_RESERVED_223', + 224: 'CB_PERF_SEL_RESERVED_224', + 225: 'CB_PERF_SEL_RESERVED_225', + 226: 'CB_PERF_SEL_RESERVED_226', + 227: 'CB_PERF_SEL_RESERVED_227', + 228: 'CB_PERF_SEL_RESERVED_228', + 229: 'CB_PERF_SEL_RESERVED_229', + 230: 'CB_PERF_SEL_RESERVED_230', + 231: 'CB_PERF_SEL_RESERVED_231', + 232: 'CB_PERF_SEL_RESERVED_232', + 233: 'CB_PERF_SEL_RESERVED_233', + 234: 'CB_PERF_SEL_RESERVED_234', + 235: 'CB_PERF_SEL_RESERVED_235', + 236: 'CB_PERF_SEL_RESERVED_236', + 237: 'CB_PERF_SEL_RESERVED_237', + 238: 'CB_PERF_SEL_RESERVED_238', + 239: 'CB_PERF_SEL_RESERVED_239', + 240: 'CB_PERF_SEL_RESERVED_240', + 241: 'CB_PERF_SEL_RESERVED_241', + 242: 'CB_PERF_SEL_RESERVED_242', + 243: 'CB_PERF_SEL_RESERVED_243', + 244: 'CB_PERF_SEL_RESERVED_244', + 245: 'CB_PERF_SEL_RESERVED_245', + 246: 'CB_PERF_SEL_RESERVED_246', + 247: 'CB_PERF_SEL_RESERVED_247', + 248: 'CB_PERF_SEL_RESERVED_248', + 249: 'CB_PERF_SEL_RESERVED_249', + 250: 'CB_PERF_SEL_EVENT', + 251: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 252: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 253: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 254: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 255: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 256: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 257: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 258: 'CB_PERF_SEL_CC_SURFACE_SYNC', + 259: 'CB_PERF_SEL_RESERVED_259', + 260: 'CB_PERF_SEL_RESERVED_260', + 261: 'CB_PERF_SEL_RESERVED_261', + 262: 'CB_PERF_SEL_RESERVED_262', + 263: 'CB_PERF_SEL_RESERVED_263', + 264: 'CB_PERF_SEL_RESERVED_264', + 265: 'CB_PERF_SEL_RESERVED_265', + 266: 'CB_PERF_SEL_RESERVED_266', + 267: 'CB_PERF_SEL_RESERVED_267', + 268: 'CB_PERF_SEL_RESERVED_268', + 269: 'CB_PERF_SEL_RESERVED_269', + 270: 'CB_PERF_SEL_RESERVED_270', + 271: 'CB_PERF_SEL_RESERVED_271', + 272: 'CB_PERF_SEL_RESERVED_272', + 273: 'CB_PERF_SEL_RESERVED_273', + 274: 'CB_PERF_SEL_RESERVED_274', + 275: 'CB_PERF_SEL_RESERVED_275', + 276: 'CB_PERF_SEL_RESERVED_276', + 277: 'CB_PERF_SEL_RESERVED_277', + 278: 'CB_PERF_SEL_RESERVED_278', + 279: 'CB_PERF_SEL_RESERVED_279', + 280: 'CB_PERF_SEL_RESERVED_280', + 281: 'CB_PERF_SEL_RESERVED_281', + 282: 'CB_PERF_SEL_RESERVED_282', + 283: 'CB_PERF_SEL_RESERVED_283', + 284: 'CB_PERF_SEL_RESERVED_284', + 285: 'CB_PERF_SEL_RESERVED_285', + 286: 'CB_PERF_SEL_RESERVED_286', + 287: 'CB_PERF_SEL_RESERVED_287', + 288: 'CB_PERF_SEL_RESERVED_288', + 289: 'CB_PERF_SEL_RESERVED_289', + 290: 'CB_PERF_SEL_RESERVED_290', + 291: 'CB_PERF_SEL_RESERVED_291', + 292: 'CB_PERF_SEL_RESERVED_292', + 293: 'CB_PERF_SEL_RESERVED_293', + 294: 'CB_PERF_SEL_RESERVED_294', + 295: 'CB_PERF_SEL_RESERVED_295', + 296: 'CB_PERF_SEL_RESERVED_296', + 297: 'CB_PERF_SEL_RESERVED_297', + 298: 'CB_PERF_SEL_RESERVED_298', + 299: 'CB_PERF_SEL_RESERVED_299', + 300: 'CB_PERF_SEL_NACK_CC_READ', + 301: 'CB_PERF_SEL_NACK_CC_WRITE', + 302: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 303: 'CB_PERF_SEL_RESERVED_303', + 304: 'CB_PERF_SEL_RESERVED_304', + 305: 'CB_PERF_SEL_RESERVED_305', + 306: 'CB_PERF_SEL_RESERVED_306', + 307: 'CB_PERF_SEL_RESERVED_307', + 308: 'CB_PERF_SEL_RESERVED_308', + 309: 'CB_PERF_SEL_RESERVED_309', + 310: 'CB_PERF_SEL_RESERVED_310', + 311: 'CB_PERF_SEL_RESERVED_311', + 312: 'CB_PERF_SEL_RESERVED_312', + 313: 'CB_PERF_SEL_RESERVED_313', + 314: 'CB_PERF_SEL_RESERVED_314', + 315: 'CB_PERF_SEL_RESERVED_315', + 316: 'CB_PERF_SEL_RESERVED_316', + 317: 'CB_PERF_SEL_RESERVED_317', + 318: 'CB_PERF_SEL_RESERVED_318', + 319: 'CB_PERF_SEL_RESERVED_319', + 320: 'CB_PERF_SEL_RESERVED_320', + 321: 'CB_PERF_SEL_RESERVED_321', + 322: 'CB_PERF_SEL_RESERVED_322', + 323: 'CB_PERF_SEL_RESERVED_323', + 324: 'CB_PERF_SEL_RESERVED_324', + 325: 'CB_PERF_SEL_RESERVED_325', + 326: 'CB_PERF_SEL_RESERVED_326', + 327: 'CB_PERF_SEL_RESERVED_327', + 328: 'CB_PERF_SEL_RESERVED_328', + 329: 'CB_PERF_SEL_RESERVED_329', + 330: 'CB_PERF_SEL_RESERVED_330', + 331: 'CB_PERF_SEL_RESERVED_331', + 332: 'CB_PERF_SEL_RESERVED_332', + 333: 'CB_PERF_SEL_RESERVED_333', + 334: 'CB_PERF_SEL_RESERVED_334', + 335: 'CB_PERF_SEL_RESERVED_335', + 336: 'CB_PERF_SEL_RESERVED_336', + 337: 'CB_PERF_SEL_RESERVED_337', + 338: 'CB_PERF_SEL_RESERVED_338', + 339: 'CB_PERF_SEL_RESERVED_339', + 340: 'CB_PERF_SEL_RESERVED_340', + 341: 'CB_PERF_SEL_RESERVED_341', + 342: 'CB_PERF_SEL_RESERVED_342', + 343: 'CB_PERF_SEL_RESERVED_343', + 344: 'CB_PERF_SEL_RESERVED_344', + 345: 'CB_PERF_SEL_RESERVED_345', + 346: 'CB_PERF_SEL_RESERVED_346', + 347: 'CB_PERF_SEL_RESERVED_347', + 348: 'CB_PERF_SEL_RESERVED_348', + 349: 'CB_PERF_SEL_RESERVED_349', + 350: 'CB_PERF_SEL_RESERVED_350', + 351: 'CB_PERF_SEL_RESERVED_351', + 352: 'CB_PERF_SEL_RESERVED_352', + 353: 'CB_PERF_SEL_RESERVED_353', + 354: 'CB_PERF_SEL_RESERVED_354', + 355: 'CB_PERF_SEL_RESERVED_355', + 356: 'CB_PERF_SEL_RESERVED_356', + 357: 'CB_PERF_SEL_RESERVED_357', + 358: 'CB_PERF_SEL_RESERVED_358', + 359: 'CB_PERF_SEL_RESERVED_359', + 360: 'CB_PERF_SEL_RESERVED_360', + 361: 'CB_PERF_SEL_RESERVED_361', + 362: 'CB_PERF_SEL_RESERVED_362', + 363: 'CB_PERF_SEL_RESERVED_363', + 364: 'CB_PERF_SEL_RESERVED_364', + 365: 'CB_PERF_SEL_RESERVED_365', + 366: 'CB_PERF_SEL_RESERVED_366', + 367: 'CB_PERF_SEL_RESERVED_367', + 368: 'CB_PERF_SEL_RESERVED_368', + 369: 'CB_PERF_SEL_RESERVED_369', + 370: 'CB_PERF_SEL_RESERVED_370', + 371: 'CB_PERF_SEL_RESERVED_371', + 372: 'CB_PERF_SEL_RESERVED_372', + 373: 'CB_PERF_SEL_RESERVED_373', + 374: 'CB_PERF_SEL_RESERVED_374', + 375: 'CB_PERF_SEL_RESERVED_375', + 376: 'CB_PERF_SEL_RESERVED_376', + 377: 'CB_PERF_SEL_RESERVED_377', + 378: 'CB_PERF_SEL_RESERVED_378', + 379: 'CB_PERF_SEL_RESERVED_379', + 380: 'CB_PERF_SEL_RESERVED_380', + 381: 'CB_PERF_SEL_RESERVED_381', + 382: 'CB_PERF_SEL_RESERVED_382', + 383: 'CB_PERF_SEL_RESERVED_383', + 384: 'CB_PERF_SEL_RESERVED_384', + 385: 'CB_PERF_SEL_RESERVED_385', + 386: 'CB_PERF_SEL_RESERVED_386', + 387: 'CB_PERF_SEL_RESERVED_387', + 388: 'CB_PERF_SEL_RESERVED_388', + 389: 'CB_PERF_SEL_RESERVED_389', + 390: 'CB_PERF_SEL_RESERVED_390', + 391: 'CB_PERF_SEL_RESERVED_391', + 392: 'CB_PERF_SEL_RESERVED_392', + 393: 'CB_PERF_SEL_RESERVED_393', + 394: 'CB_PERF_SEL_RESERVED_394', + 395: 'CB_PERF_SEL_RESERVED_395', + 396: 'CB_PERF_SEL_RESERVED_396', + 397: 'CB_PERF_SEL_RESERVED_397', + 398: 'CB_PERF_SEL_RESERVED_398', + 399: 'CB_PERF_SEL_RESERVED_399', + 400: 'CB_PERF_SEL_RESERVED_400', + 401: 'CB_PERF_SEL_RESERVED_401', + 402: 'CB_PERF_SEL_RESERVED_402', + 403: 'CB_PERF_SEL_RESERVED_403', + 404: 'CB_PERF_SEL_RESERVED_404', + 405: 'CB_PERF_SEL_RESERVED_405', + 406: 'CB_PERF_SEL_RESERVED_406', + 407: 'CB_PERF_SEL_RESERVED_407', + 408: 'CB_PERF_SEL_RESERVED_408', + 409: 'CB_PERF_SEL_RESERVED_409', + 410: 'CB_PERF_SEL_RESERVED_410', + 411: 'CB_PERF_SEL_RESERVED_411', + 412: 'CB_PERF_SEL_RESERVED_412', + 413: 'CB_PERF_SEL_RESERVED_413', + 414: 'CB_PERF_SEL_RESERVED_414', + 415: 'CB_PERF_SEL_RESERVED_415', + 416: 'CB_PERF_SEL_RESERVED_416', + 417: 'CB_PERF_SEL_RESERVED_417', + 418: 'CB_PERF_SEL_RESERVED_418', + 419: 'CB_PERF_SEL_RESERVED_419', + 420: 'CB_PERF_SEL_RESERVED_420', + 421: 'CB_PERF_SEL_RESERVED_421', + 422: 'CB_PERF_SEL_RESERVED_422', + 423: 'CB_PERF_SEL_RESERVED_423', + 424: 'CB_PERF_SEL_RESERVED_424', + 425: 'CB_PERF_SEL_RESERVED_425', + 426: 'CB_PERF_SEL_RESERVED_426', + 427: 'CB_PERF_SEL_RESERVED_427', + 428: 'CB_PERF_SEL_RESERVED_428', + 429: 'CB_PERF_SEL_RESERVED_429', + 430: 'CB_PERF_SEL_RESERVED_430', + 431: 'CB_PERF_SEL_RESERVED_431', + 432: 'CB_PERF_SEL_RESERVED_432', + 433: 'CB_PERF_SEL_RESERVED_433', + 434: 'CB_PERF_SEL_RESERVED_434', + 435: 'CB_PERF_SEL_RESERVED_435', + 436: 'CB_PERF_SEL_RESERVED_436', + 437: 'CB_PERF_SEL_RESERVED_437', + 438: 'CB_PERF_SEL_RESERVED_438', + 439: 'CB_PERF_SEL_RESERVED_439', + 440: 'CB_PERF_SEL_RESERVED_440', + 441: 'CB_PERF_SEL_RESERVED_441', + 442: 'CB_PERF_SEL_RESERVED_442', + 443: 'CB_PERF_SEL_RESERVED_443', + 444: 'CB_PERF_SEL_RESERVED_444', + 445: 'CB_PERF_SEL_RESERVED_445', + 446: 'CB_PERF_SEL_RESERVED_446', + 447: 'CB_PERF_SEL_RESERVED_447', + 448: 'CB_PERF_SEL_RESERVED_448', + 449: 'CB_PERF_SEL_RESERVED_449', + 450: 'CB_PERF_SEL_RESERVED_450', + 451: 'CB_PERF_SEL_RESERVED_451', + 452: 'CB_PERF_SEL_RESERVED_452', + 453: 'CB_PERF_SEL_RESERVED_453', + 454: 'CB_PERF_SEL_RESERVED_454', + 455: 'CB_PERF_SEL_RESERVED_455', + 456: 'CB_PERF_SEL_RESERVED_456', + 457: 'CB_PERF_SEL_RESERVED_457', + 458: 'CB_PERF_SEL_RESERVED_458', + 459: 'CB_PERF_SEL_RESERVED_459', + 460: 'CB_PERF_SEL_RESERVED_460', + 461: 'CB_PERF_SEL_RESERVED_461', + 462: 'CB_PERF_SEL_RESERVED_462', + 463: 'CB_PERF_SEL_RESERVED_463', + 464: 'CB_PERF_SEL_RESERVED_464', + 465: 'CB_PERF_SEL_RESERVED_465', +} +CB_PERF_SEL_NONE = 0 +CB_PERF_SEL_DRAWN_PIXEL = 1 +CB_PERF_SEL_DRAWN_QUAD = 2 +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 3 +CB_PERF_SEL_DRAWN_TILE = 4 +CB_PERF_SEL_FILTER_DRAWN_PIXEL = 5 +CB_PERF_SEL_FILTER_DRAWN_QUAD = 6 +CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 7 +CB_PERF_SEL_FILTER_DRAWN_TILE = 8 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 9 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 10 +CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 11 +CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 12 +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 13 +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 14 +CB_PERF_SEL_CC_MC_READ_REQUEST = 15 +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 16 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 17 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 18 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 19 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 20 +CB_PERF_SEL_RESERVED_21 = 21 +CB_PERF_SEL_RESERVED_22 = 22 +CB_PERF_SEL_RESERVED_23 = 23 +CB_PERF_SEL_RESERVED_24 = 24 +CB_PERF_SEL_RESERVED_25 = 25 +CB_PERF_SEL_RESERVED_26 = 26 +CB_PERF_SEL_RESERVED_27 = 27 +CB_PERF_SEL_RESERVED_28 = 28 +CB_PERF_SEL_RESERVED_29 = 29 +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 30 +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 31 +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 32 +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 33 +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 34 +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 35 +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 36 +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 37 +CB_PERF_SEL_RESERVED_38 = 38 +CB_PERF_SEL_RESERVED_39 = 39 +CB_PERF_SEL_RESERVED_40 = 40 +CB_PERF_SEL_RESERVED_41 = 41 +CB_PERF_SEL_RESERVED_42 = 42 +CB_PERF_SEL_RESERVED_43 = 43 +CB_PERF_SEL_RESERVED_44 = 44 +CB_PERF_SEL_RESERVED_45 = 45 +CB_PERF_SEL_RESERVED_46 = 46 +CB_PERF_SEL_RESERVED_47 = 47 +CB_PERF_SEL_RESERVED_48 = 48 +CB_PERF_SEL_RESERVED_49 = 49 +CB_PERF_SEL_STATIC_CLOCK_EN = 50 +CB_PERF_SEL_PERFMON_CLOCK_EN = 51 +CB_PERF_SEL_BLEND_CLOCK_EN = 52 +CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 53 +CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 54 +CB_PERF_SEL_GRBM_CLOCK_EN = 55 +CB_PERF_SEL_MEMARB_CLOCK_EN = 56 +CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 57 +CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 58 +CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 59 +CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 60 +CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 61 +CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 62 +CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 63 +CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 64 +CB_PERF_SEL_RESERVED_65 = 65 +CB_PERF_SEL_RESERVED_66 = 66 +CB_PERF_SEL_RESERVED_67 = 67 +CB_PERF_SEL_RESERVED_68 = 68 +CB_PERF_SEL_RESERVED_69 = 69 +CB_PERF_SEL_RESERVED_70 = 70 +CB_PERF_SEL_RESERVED_71 = 71 +CB_PERF_SEL_RESERVED_72 = 72 +CB_PERF_SEL_RESERVED_73 = 73 +CB_PERF_SEL_RESERVED_74 = 74 +CB_PERF_SEL_RESERVED_75 = 75 +CB_PERF_SEL_RESERVED_76 = 76 +CB_PERF_SEL_RESERVED_77 = 77 +CB_PERF_SEL_RESERVED_78 = 78 +CB_PERF_SEL_RESERVED_79 = 79 +CB_PERF_SEL_RESERVED_80 = 80 +CB_PERF_SEL_RESERVED_81 = 81 +CB_PERF_SEL_RESERVED_82 = 82 +CB_PERF_SEL_RESERVED_83 = 83 +CB_PERF_SEL_RESERVED_84 = 84 +CB_PERF_SEL_RESERVED_85 = 85 +CB_PERF_SEL_RESERVED_86 = 86 +CB_PERF_SEL_RESERVED_87 = 87 +CB_PERF_SEL_RESERVED_88 = 88 +CB_PERF_SEL_RESERVED_89 = 89 +CB_PERF_SEL_RESERVED_90 = 90 +CB_PERF_SEL_RESERVED_91 = 91 +CB_PERF_SEL_RESERVED_92 = 92 +CB_PERF_SEL_RESERVED_93 = 93 +CB_PERF_SEL_RESERVED_94 = 94 +CB_PERF_SEL_RESERVED_95 = 95 +CB_PERF_SEL_RESERVED_96 = 96 +CB_PERF_SEL_RESERVED_97 = 97 +CB_PERF_SEL_RESERVED_98 = 98 +CB_PERF_SEL_RESERVED_99 = 99 +CB_PERF_SEL_CC_TAG_HIT = 100 +CB_PERF_SEL_CC_CACHE_TAG_MISS = 101 +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 102 +CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 103 +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 104 +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 105 +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 106 +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 107 +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 108 +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 109 +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 110 +CB_PERF_SEL_CC_CACHE_STALL = 111 +CB_PERF_SEL_CC_CACHE_FLUSH = 112 +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 113 +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 114 +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 115 +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 116 +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 117 +CB_PERF_SEL_RESERVED_118 = 118 +CB_PERF_SEL_RESERVED_119 = 119 +CB_PERF_SEL_RESERVED_120 = 120 +CB_PERF_SEL_RESERVED_121 = 121 +CB_PERF_SEL_RESERVED_122 = 122 +CB_PERF_SEL_RESERVED_123 = 123 +CB_PERF_SEL_RESERVED_124 = 124 +CB_PERF_SEL_RESERVED_125 = 125 +CB_PERF_SEL_RESERVED_126 = 126 +CB_PERF_SEL_RESERVED_127 = 127 +CB_PERF_SEL_RESERVED_128 = 128 +CB_PERF_SEL_RESERVED_129 = 129 +CB_PERF_SEL_RESERVED_130 = 130 +CB_PERF_SEL_RESERVED_131 = 131 +CB_PERF_SEL_RESERVED_132 = 132 +CB_PERF_SEL_RESERVED_133 = 133 +CB_PERF_SEL_RESERVED_134 = 134 +CB_PERF_SEL_RESERVED_135 = 135 +CB_PERF_SEL_RESERVED_136 = 136 +CB_PERF_SEL_RESERVED_137 = 137 +CB_PERF_SEL_RESERVED_138 = 138 +CB_PERF_SEL_RESERVED_139 = 139 +CB_PERF_SEL_RESERVED_140 = 140 +CB_PERF_SEL_RESERVED_141 = 141 +CB_PERF_SEL_RESERVED_142 = 142 +CB_PERF_SEL_RESERVED_143 = 143 +CB_PERF_SEL_RESERVED_144 = 144 +CB_PERF_SEL_RESERVED_145 = 145 +CB_PERF_SEL_RESERVED_146 = 146 +CB_PERF_SEL_RESERVED_147 = 147 +CB_PERF_SEL_RESERVED_148 = 148 +CB_PERF_SEL_RESERVED_149 = 149 +CB_PERF_SEL_DCC_CACHE_PERF_HIT = 150 +CB_PERF_SEL_DCC_CACHE_TAG_MISS = 151 +CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 152 +CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 153 +CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 154 +CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 155 +CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 156 +CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 157 +CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 158 +CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 159 +CB_PERF_SEL_DCC_CACHE_STALL = 160 +CB_PERF_SEL_DCC_CACHE_FLUSH = 161 +CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 162 +CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 163 +CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 164 +CB_PERF_SEL_RESERVED_165 = 165 +CB_PERF_SEL_RESERVED_166 = 166 +CB_PERF_SEL_RESERVED_167 = 167 +CB_PERF_SEL_RESERVED_168 = 168 +CB_PERF_SEL_RESERVED_169 = 169 +CB_PERF_SEL_RESERVED_170 = 170 +CB_PERF_SEL_RESERVED_171 = 171 +CB_PERF_SEL_RESERVED_172 = 172 +CB_PERF_SEL_RESERVED_173 = 173 +CB_PERF_SEL_RESERVED_174 = 174 +CB_PERF_SEL_RESERVED_175 = 175 +CB_PERF_SEL_RESERVED_176 = 176 +CB_PERF_SEL_RESERVED_177 = 177 +CB_PERF_SEL_RESERVED_178 = 178 +CB_PERF_SEL_RESERVED_179 = 179 +CB_PERF_SEL_RESERVED_180 = 180 +CB_PERF_SEL_RESERVED_181 = 181 +CB_PERF_SEL_RESERVED_182 = 182 +CB_PERF_SEL_RESERVED_183 = 183 +CB_PERF_SEL_RESERVED_184 = 184 +CB_PERF_SEL_RESERVED_185 = 185 +CB_PERF_SEL_RESERVED_186 = 186 +CB_PERF_SEL_RESERVED_187 = 187 +CB_PERF_SEL_RESERVED_188 = 188 +CB_PERF_SEL_RESERVED_189 = 189 +CB_PERF_SEL_RESERVED_190 = 190 +CB_PERF_SEL_RESERVED_191 = 191 +CB_PERF_SEL_RESERVED_192 = 192 +CB_PERF_SEL_RESERVED_193 = 193 +CB_PERF_SEL_RESERVED_194 = 194 +CB_PERF_SEL_RESERVED_195 = 195 +CB_PERF_SEL_RESERVED_196 = 196 +CB_PERF_SEL_RESERVED_197 = 197 +CB_PERF_SEL_RESERVED_198 = 198 +CB_PERF_SEL_RESERVED_199 = 199 +CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 200 +CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 201 +CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 202 +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 203 +CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 204 +CB_PERF_SEL_RESERVED_205 = 205 +CB_PERF_SEL_RESERVED_206 = 206 +CB_PERF_SEL_RESERVED_207 = 207 +CB_PERF_SEL_RESERVED_208 = 208 +CB_PERF_SEL_RESERVED_209 = 209 +CB_PERF_SEL_RESERVED_210 = 210 +CB_PERF_SEL_RESERVED_211 = 211 +CB_PERF_SEL_RESERVED_212 = 212 +CB_PERF_SEL_RESERVED_213 = 213 +CB_PERF_SEL_RESERVED_214 = 214 +CB_PERF_SEL_RESERVED_215 = 215 +CB_PERF_SEL_RESERVED_216 = 216 +CB_PERF_SEL_RESERVED_217 = 217 +CB_PERF_SEL_RESERVED_218 = 218 +CB_PERF_SEL_RESERVED_219 = 219 +CB_PERF_SEL_RESERVED_220 = 220 +CB_PERF_SEL_RESERVED_221 = 221 +CB_PERF_SEL_RESERVED_222 = 222 +CB_PERF_SEL_RESERVED_223 = 223 +CB_PERF_SEL_RESERVED_224 = 224 +CB_PERF_SEL_RESERVED_225 = 225 +CB_PERF_SEL_RESERVED_226 = 226 +CB_PERF_SEL_RESERVED_227 = 227 +CB_PERF_SEL_RESERVED_228 = 228 +CB_PERF_SEL_RESERVED_229 = 229 +CB_PERF_SEL_RESERVED_230 = 230 +CB_PERF_SEL_RESERVED_231 = 231 +CB_PERF_SEL_RESERVED_232 = 232 +CB_PERF_SEL_RESERVED_233 = 233 +CB_PERF_SEL_RESERVED_234 = 234 +CB_PERF_SEL_RESERVED_235 = 235 +CB_PERF_SEL_RESERVED_236 = 236 +CB_PERF_SEL_RESERVED_237 = 237 +CB_PERF_SEL_RESERVED_238 = 238 +CB_PERF_SEL_RESERVED_239 = 239 +CB_PERF_SEL_RESERVED_240 = 240 +CB_PERF_SEL_RESERVED_241 = 241 +CB_PERF_SEL_RESERVED_242 = 242 +CB_PERF_SEL_RESERVED_243 = 243 +CB_PERF_SEL_RESERVED_244 = 244 +CB_PERF_SEL_RESERVED_245 = 245 +CB_PERF_SEL_RESERVED_246 = 246 +CB_PERF_SEL_RESERVED_247 = 247 +CB_PERF_SEL_RESERVED_248 = 248 +CB_PERF_SEL_RESERVED_249 = 249 +CB_PERF_SEL_EVENT = 250 +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 251 +CB_PERF_SEL_EVENT_CONTEXT_DONE = 252 +CB_PERF_SEL_EVENT_CACHE_FLUSH = 253 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 254 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 255 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 256 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 257 +CB_PERF_SEL_CC_SURFACE_SYNC = 258 +CB_PERF_SEL_RESERVED_259 = 259 +CB_PERF_SEL_RESERVED_260 = 260 +CB_PERF_SEL_RESERVED_261 = 261 +CB_PERF_SEL_RESERVED_262 = 262 +CB_PERF_SEL_RESERVED_263 = 263 +CB_PERF_SEL_RESERVED_264 = 264 +CB_PERF_SEL_RESERVED_265 = 265 +CB_PERF_SEL_RESERVED_266 = 266 +CB_PERF_SEL_RESERVED_267 = 267 +CB_PERF_SEL_RESERVED_268 = 268 +CB_PERF_SEL_RESERVED_269 = 269 +CB_PERF_SEL_RESERVED_270 = 270 +CB_PERF_SEL_RESERVED_271 = 271 +CB_PERF_SEL_RESERVED_272 = 272 +CB_PERF_SEL_RESERVED_273 = 273 +CB_PERF_SEL_RESERVED_274 = 274 +CB_PERF_SEL_RESERVED_275 = 275 +CB_PERF_SEL_RESERVED_276 = 276 +CB_PERF_SEL_RESERVED_277 = 277 +CB_PERF_SEL_RESERVED_278 = 278 +CB_PERF_SEL_RESERVED_279 = 279 +CB_PERF_SEL_RESERVED_280 = 280 +CB_PERF_SEL_RESERVED_281 = 281 +CB_PERF_SEL_RESERVED_282 = 282 +CB_PERF_SEL_RESERVED_283 = 283 +CB_PERF_SEL_RESERVED_284 = 284 +CB_PERF_SEL_RESERVED_285 = 285 +CB_PERF_SEL_RESERVED_286 = 286 +CB_PERF_SEL_RESERVED_287 = 287 +CB_PERF_SEL_RESERVED_288 = 288 +CB_PERF_SEL_RESERVED_289 = 289 +CB_PERF_SEL_RESERVED_290 = 290 +CB_PERF_SEL_RESERVED_291 = 291 +CB_PERF_SEL_RESERVED_292 = 292 +CB_PERF_SEL_RESERVED_293 = 293 +CB_PERF_SEL_RESERVED_294 = 294 +CB_PERF_SEL_RESERVED_295 = 295 +CB_PERF_SEL_RESERVED_296 = 296 +CB_PERF_SEL_RESERVED_297 = 297 +CB_PERF_SEL_RESERVED_298 = 298 +CB_PERF_SEL_RESERVED_299 = 299 +CB_PERF_SEL_NACK_CC_READ = 300 +CB_PERF_SEL_NACK_CC_WRITE = 301 +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 302 +CB_PERF_SEL_RESERVED_303 = 303 +CB_PERF_SEL_RESERVED_304 = 304 +CB_PERF_SEL_RESERVED_305 = 305 +CB_PERF_SEL_RESERVED_306 = 306 +CB_PERF_SEL_RESERVED_307 = 307 +CB_PERF_SEL_RESERVED_308 = 308 +CB_PERF_SEL_RESERVED_309 = 309 +CB_PERF_SEL_RESERVED_310 = 310 +CB_PERF_SEL_RESERVED_311 = 311 +CB_PERF_SEL_RESERVED_312 = 312 +CB_PERF_SEL_RESERVED_313 = 313 +CB_PERF_SEL_RESERVED_314 = 314 +CB_PERF_SEL_RESERVED_315 = 315 +CB_PERF_SEL_RESERVED_316 = 316 +CB_PERF_SEL_RESERVED_317 = 317 +CB_PERF_SEL_RESERVED_318 = 318 +CB_PERF_SEL_RESERVED_319 = 319 +CB_PERF_SEL_RESERVED_320 = 320 +CB_PERF_SEL_RESERVED_321 = 321 +CB_PERF_SEL_RESERVED_322 = 322 +CB_PERF_SEL_RESERVED_323 = 323 +CB_PERF_SEL_RESERVED_324 = 324 +CB_PERF_SEL_RESERVED_325 = 325 +CB_PERF_SEL_RESERVED_326 = 326 +CB_PERF_SEL_RESERVED_327 = 327 +CB_PERF_SEL_RESERVED_328 = 328 +CB_PERF_SEL_RESERVED_329 = 329 +CB_PERF_SEL_RESERVED_330 = 330 +CB_PERF_SEL_RESERVED_331 = 331 +CB_PERF_SEL_RESERVED_332 = 332 +CB_PERF_SEL_RESERVED_333 = 333 +CB_PERF_SEL_RESERVED_334 = 334 +CB_PERF_SEL_RESERVED_335 = 335 +CB_PERF_SEL_RESERVED_336 = 336 +CB_PERF_SEL_RESERVED_337 = 337 +CB_PERF_SEL_RESERVED_338 = 338 +CB_PERF_SEL_RESERVED_339 = 339 +CB_PERF_SEL_RESERVED_340 = 340 +CB_PERF_SEL_RESERVED_341 = 341 +CB_PERF_SEL_RESERVED_342 = 342 +CB_PERF_SEL_RESERVED_343 = 343 +CB_PERF_SEL_RESERVED_344 = 344 +CB_PERF_SEL_RESERVED_345 = 345 +CB_PERF_SEL_RESERVED_346 = 346 +CB_PERF_SEL_RESERVED_347 = 347 +CB_PERF_SEL_RESERVED_348 = 348 +CB_PERF_SEL_RESERVED_349 = 349 +CB_PERF_SEL_RESERVED_350 = 350 +CB_PERF_SEL_RESERVED_351 = 351 +CB_PERF_SEL_RESERVED_352 = 352 +CB_PERF_SEL_RESERVED_353 = 353 +CB_PERF_SEL_RESERVED_354 = 354 +CB_PERF_SEL_RESERVED_355 = 355 +CB_PERF_SEL_RESERVED_356 = 356 +CB_PERF_SEL_RESERVED_357 = 357 +CB_PERF_SEL_RESERVED_358 = 358 +CB_PERF_SEL_RESERVED_359 = 359 +CB_PERF_SEL_RESERVED_360 = 360 +CB_PERF_SEL_RESERVED_361 = 361 +CB_PERF_SEL_RESERVED_362 = 362 +CB_PERF_SEL_RESERVED_363 = 363 +CB_PERF_SEL_RESERVED_364 = 364 +CB_PERF_SEL_RESERVED_365 = 365 +CB_PERF_SEL_RESERVED_366 = 366 +CB_PERF_SEL_RESERVED_367 = 367 +CB_PERF_SEL_RESERVED_368 = 368 +CB_PERF_SEL_RESERVED_369 = 369 +CB_PERF_SEL_RESERVED_370 = 370 +CB_PERF_SEL_RESERVED_371 = 371 +CB_PERF_SEL_RESERVED_372 = 372 +CB_PERF_SEL_RESERVED_373 = 373 +CB_PERF_SEL_RESERVED_374 = 374 +CB_PERF_SEL_RESERVED_375 = 375 +CB_PERF_SEL_RESERVED_376 = 376 +CB_PERF_SEL_RESERVED_377 = 377 +CB_PERF_SEL_RESERVED_378 = 378 +CB_PERF_SEL_RESERVED_379 = 379 +CB_PERF_SEL_RESERVED_380 = 380 +CB_PERF_SEL_RESERVED_381 = 381 +CB_PERF_SEL_RESERVED_382 = 382 +CB_PERF_SEL_RESERVED_383 = 383 +CB_PERF_SEL_RESERVED_384 = 384 +CB_PERF_SEL_RESERVED_385 = 385 +CB_PERF_SEL_RESERVED_386 = 386 +CB_PERF_SEL_RESERVED_387 = 387 +CB_PERF_SEL_RESERVED_388 = 388 +CB_PERF_SEL_RESERVED_389 = 389 +CB_PERF_SEL_RESERVED_390 = 390 +CB_PERF_SEL_RESERVED_391 = 391 +CB_PERF_SEL_RESERVED_392 = 392 +CB_PERF_SEL_RESERVED_393 = 393 +CB_PERF_SEL_RESERVED_394 = 394 +CB_PERF_SEL_RESERVED_395 = 395 +CB_PERF_SEL_RESERVED_396 = 396 +CB_PERF_SEL_RESERVED_397 = 397 +CB_PERF_SEL_RESERVED_398 = 398 +CB_PERF_SEL_RESERVED_399 = 399 +CB_PERF_SEL_RESERVED_400 = 400 +CB_PERF_SEL_RESERVED_401 = 401 +CB_PERF_SEL_RESERVED_402 = 402 +CB_PERF_SEL_RESERVED_403 = 403 +CB_PERF_SEL_RESERVED_404 = 404 +CB_PERF_SEL_RESERVED_405 = 405 +CB_PERF_SEL_RESERVED_406 = 406 +CB_PERF_SEL_RESERVED_407 = 407 +CB_PERF_SEL_RESERVED_408 = 408 +CB_PERF_SEL_RESERVED_409 = 409 +CB_PERF_SEL_RESERVED_410 = 410 +CB_PERF_SEL_RESERVED_411 = 411 +CB_PERF_SEL_RESERVED_412 = 412 +CB_PERF_SEL_RESERVED_413 = 413 +CB_PERF_SEL_RESERVED_414 = 414 +CB_PERF_SEL_RESERVED_415 = 415 +CB_PERF_SEL_RESERVED_416 = 416 +CB_PERF_SEL_RESERVED_417 = 417 +CB_PERF_SEL_RESERVED_418 = 418 +CB_PERF_SEL_RESERVED_419 = 419 +CB_PERF_SEL_RESERVED_420 = 420 +CB_PERF_SEL_RESERVED_421 = 421 +CB_PERF_SEL_RESERVED_422 = 422 +CB_PERF_SEL_RESERVED_423 = 423 +CB_PERF_SEL_RESERVED_424 = 424 +CB_PERF_SEL_RESERVED_425 = 425 +CB_PERF_SEL_RESERVED_426 = 426 +CB_PERF_SEL_RESERVED_427 = 427 +CB_PERF_SEL_RESERVED_428 = 428 +CB_PERF_SEL_RESERVED_429 = 429 +CB_PERF_SEL_RESERVED_430 = 430 +CB_PERF_SEL_RESERVED_431 = 431 +CB_PERF_SEL_RESERVED_432 = 432 +CB_PERF_SEL_RESERVED_433 = 433 +CB_PERF_SEL_RESERVED_434 = 434 +CB_PERF_SEL_RESERVED_435 = 435 +CB_PERF_SEL_RESERVED_436 = 436 +CB_PERF_SEL_RESERVED_437 = 437 +CB_PERF_SEL_RESERVED_438 = 438 +CB_PERF_SEL_RESERVED_439 = 439 +CB_PERF_SEL_RESERVED_440 = 440 +CB_PERF_SEL_RESERVED_441 = 441 +CB_PERF_SEL_RESERVED_442 = 442 +CB_PERF_SEL_RESERVED_443 = 443 +CB_PERF_SEL_RESERVED_444 = 444 +CB_PERF_SEL_RESERVED_445 = 445 +CB_PERF_SEL_RESERVED_446 = 446 +CB_PERF_SEL_RESERVED_447 = 447 +CB_PERF_SEL_RESERVED_448 = 448 +CB_PERF_SEL_RESERVED_449 = 449 +CB_PERF_SEL_RESERVED_450 = 450 +CB_PERF_SEL_RESERVED_451 = 451 +CB_PERF_SEL_RESERVED_452 = 452 +CB_PERF_SEL_RESERVED_453 = 453 +CB_PERF_SEL_RESERVED_454 = 454 +CB_PERF_SEL_RESERVED_455 = 455 +CB_PERF_SEL_RESERVED_456 = 456 +CB_PERF_SEL_RESERVED_457 = 457 +CB_PERF_SEL_RESERVED_458 = 458 +CB_PERF_SEL_RESERVED_459 = 459 +CB_PERF_SEL_RESERVED_460 = 460 +CB_PERF_SEL_RESERVED_461 = 461 +CB_PERF_SEL_RESERVED_462 = 462 +CB_PERF_SEL_RESERVED_463 = 463 +CB_PERF_SEL_RESERVED_464 = 464 +CB_PERF_SEL_RESERVED_465 = 465 +CBPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBRamList' +CBRamList__enumvalues = { + 0: 'CB_DCG_CCC_CAS_TAG_ARRAY', + 1: 'CB_DCG_CCC_CAS_FRAG_PTR', + 2: 'CB_DCG_CCC_CAS_COLOR_PTR', + 3: 'CB_DCG_CCC_CAS_SURF_PARAM', + 4: 'CB_DCG_CCC_CAS_KEYID', + 5: 'CB_DCG_BACKEND_RDLAT_FIFO', + 6: 'CB_DCG_FRONTEND_RDLAT_FIFO', + 7: 'CB_DCG_SRC_FIFO', + 8: 'CB_DCG_COLOR_STORE', + 9: 'CB_DCG_COLOR_STORE_DIRTY_BYTE', + 10: 'CB_DCG_FMASK_CACHE_STORE', + 11: 'CB_DCG_READ_SKID_FIFO', + 12: 'CB_DCG_QUAD_PTR_FIFO', + 13: 'CB_DCG_OUTPUT_FIFO', + 14: 'CB_DCG_DCC_CACHE', + 15: 'CB_DCG_DCC_DIRTY_BITS', + 16: 'CB_DCG_QBLOCK_ALLOC', +} +CB_DCG_CCC_CAS_TAG_ARRAY = 0 +CB_DCG_CCC_CAS_FRAG_PTR = 1 +CB_DCG_CCC_CAS_COLOR_PTR = 2 +CB_DCG_CCC_CAS_SURF_PARAM = 3 +CB_DCG_CCC_CAS_KEYID = 4 +CB_DCG_BACKEND_RDLAT_FIFO = 5 +CB_DCG_FRONTEND_RDLAT_FIFO = 6 +CB_DCG_SRC_FIFO = 7 +CB_DCG_COLOR_STORE = 8 +CB_DCG_COLOR_STORE_DIRTY_BYTE = 9 +CB_DCG_FMASK_CACHE_STORE = 10 +CB_DCG_READ_SKID_FIFO = 11 +CB_DCG_QUAD_PTR_FIFO = 12 +CB_DCG_OUTPUT_FIFO = 13 +CB_DCG_DCC_CACHE = 14 +CB_DCG_DCC_DIRTY_BITS = 15 +CB_DCG_QBLOCK_ALLOC = 16 +CBRamList = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskCode' +CmaskCode__enumvalues = { + 0: 'CMASK_CLR00_F0', + 1: 'CMASK_CLR00_F1', + 2: 'CMASK_CLR00_F2', + 3: 'CMASK_CLR00_FX', + 4: 'CMASK_CLR01_F0', + 5: 'CMASK_CLR01_F1', + 6: 'CMASK_CLR01_F2', + 7: 'CMASK_CLR01_FX', + 8: 'CMASK_CLR10_F0', + 9: 'CMASK_CLR10_F1', + 10: 'CMASK_CLR10_F2', + 11: 'CMASK_CLR10_FX', + 12: 'CMASK_CLR11_F0', + 13: 'CMASK_CLR11_F1', + 14: 'CMASK_CLR11_F2', + 15: 'CMASK_CLR11_FX', +} +CMASK_CLR00_F0 = 0 +CMASK_CLR00_F1 = 1 +CMASK_CLR00_F2 = 2 +CMASK_CLR00_FX = 3 +CMASK_CLR01_F0 = 4 +CMASK_CLR01_F1 = 5 +CMASK_CLR01_F2 = 6 +CMASK_CLR01_FX = 7 +CMASK_CLR10_F0 = 8 +CMASK_CLR10_F1 = 9 +CMASK_CLR10_F2 = 10 +CMASK_CLR10_FX = 11 +CMASK_CLR11_F0 = 12 +CMASK_CLR11_F1 = 13 +CMASK_CLR11_F2 = 14 +CMASK_CLR11_FX = 15 +CmaskCode = ctypes.c_uint32 # enum + +# values for enumeration 'CombFunc' +CombFunc__enumvalues = { + 0: 'COMB_DST_PLUS_SRC', + 1: 'COMB_SRC_MINUS_DST', + 2: 'COMB_MIN_DST_SRC', + 3: 'COMB_MAX_DST_SRC', + 4: 'COMB_DST_MINUS_SRC', +} +COMB_DST_PLUS_SRC = 0 +COMB_SRC_MINUS_DST = 1 +COMB_MIN_DST_SRC = 2 +COMB_MAX_DST_SRC = 3 +COMB_DST_MINUS_SRC = 4 +CombFunc = ctypes.c_uint32 # enum + +# values for enumeration 'MemArbMode' +MemArbMode__enumvalues = { + 0: 'MEM_ARB_MODE_FIXED', + 1: 'MEM_ARB_MODE_AGE', + 2: 'MEM_ARB_MODE_WEIGHT', + 3: 'MEM_ARB_MODE_BOTH', +} +MEM_ARB_MODE_FIXED = 0 +MEM_ARB_MODE_AGE = 1 +MEM_ARB_MODE_WEIGHT = 2 +MEM_ARB_MODE_BOTH = 3 +MemArbMode = ctypes.c_uint32 # enum + +# values for enumeration 'SourceFormat' +SourceFormat__enumvalues = { + 0: 'EXPORT_4C_32BPC', + 1: 'EXPORT_4C_16BPC', + 2: 'EXPORT_2C_32BPC_GR', + 3: 'EXPORT_2C_32BPC_AR', +} +EXPORT_4C_32BPC = 0 +EXPORT_4C_16BPC = 1 +EXPORT_2C_32BPC_GR = 2 +EXPORT_2C_32BPC_AR = 3 +SourceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'BinEventCntl' +BinEventCntl__enumvalues = { + 0: 'BINNER_BREAK_BATCH', + 1: 'BINNER_PIPELINE', + 2: 'BINNER_DROP', + 3: 'BINNER_PIPELINE_BREAK', +} +BINNER_BREAK_BATCH = 0 +BINNER_PIPELINE = 1 +BINNER_DROP = 2 +BINNER_PIPELINE_BREAK = 3 +BinEventCntl = ctypes.c_uint32 # enum + +# values for enumeration 'BinMapMode' +BinMapMode__enumvalues = { + 0: 'BIN_MAP_MODE_NONE', + 1: 'BIN_MAP_MODE_RTA_INDEX', + 2: 'BIN_MAP_MODE_POPS', +} +BIN_MAP_MODE_NONE = 0 +BIN_MAP_MODE_RTA_INDEX = 1 +BIN_MAP_MODE_POPS = 2 +BinMapMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinSizeExtend' +BinSizeExtend__enumvalues = { + 0: 'BIN_SIZE_32_PIXELS', + 1: 'BIN_SIZE_64_PIXELS', + 2: 'BIN_SIZE_128_PIXELS', + 3: 'BIN_SIZE_256_PIXELS', + 4: 'BIN_SIZE_512_PIXELS', +} +BIN_SIZE_32_PIXELS = 0 +BIN_SIZE_64_PIXELS = 1 +BIN_SIZE_128_PIXELS = 2 +BIN_SIZE_256_PIXELS = 3 +BIN_SIZE_512_PIXELS = 4 +BinSizeExtend = ctypes.c_uint32 # enum + +# values for enumeration 'BinningMode' +BinningMode__enumvalues = { + 0: 'BINNING_ALLOWED', + 1: 'FORCE_BINNING_ON', + 2: 'DISABLE_BINNING_USE_NEW_SC', + 3: 'DISABLE_BINNING_USE_LEGACY_SC', +} +BINNING_ALLOWED = 0 +FORCE_BINNING_ON = 1 +DISABLE_BINNING_USE_NEW_SC = 2 +DISABLE_BINNING_USE_LEGACY_SC = 3 +BinningMode = ctypes.c_uint32 # enum + +# values for enumeration 'CovToShaderSel' +CovToShaderSel__enumvalues = { + 0: 'INPUT_COVERAGE', + 1: 'INPUT_INNER_COVERAGE', + 2: 'INPUT_DEPTH_COVERAGE', + 3: 'RAW', +} +INPUT_COVERAGE = 0 +INPUT_INNER_COVERAGE = 1 +INPUT_DEPTH_COVERAGE = 2 +RAW = 3 +CovToShaderSel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrMap' +PkrMap__enumvalues = { + 0: 'RASTER_CONFIG_PKR_MAP_0', + 1: 'RASTER_CONFIG_PKR_MAP_1', + 2: 'RASTER_CONFIG_PKR_MAP_2', + 3: 'RASTER_CONFIG_PKR_MAP_3', +} +RASTER_CONFIG_PKR_MAP_0 = 0 +RASTER_CONFIG_PKR_MAP_1 = 1 +RASTER_CONFIG_PKR_MAP_2 = 2 +RASTER_CONFIG_PKR_MAP_3 = 3 +PkrMap = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel' +PkrXsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL_0', + 1: 'RASTER_CONFIG_PKR_XSEL_1', + 2: 'RASTER_CONFIG_PKR_XSEL_2', + 3: 'RASTER_CONFIG_PKR_XSEL_3', +} +RASTER_CONFIG_PKR_XSEL_0 = 0 +RASTER_CONFIG_PKR_XSEL_1 = 1 +RASTER_CONFIG_PKR_XSEL_2 = 2 +RASTER_CONFIG_PKR_XSEL_3 = 3 +PkrXsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel2' +PkrXsel2__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL2_0', + 1: 'RASTER_CONFIG_PKR_XSEL2_1', + 2: 'RASTER_CONFIG_PKR_XSEL2_2', + 3: 'RASTER_CONFIG_PKR_XSEL2_3', +} +RASTER_CONFIG_PKR_XSEL2_0 = 0 +RASTER_CONFIG_PKR_XSEL2_1 = 1 +RASTER_CONFIG_PKR_XSEL2_2 = 2 +RASTER_CONFIG_PKR_XSEL2_3 = 3 +PkrXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'PkrYsel' +PkrYsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_YSEL_0', + 1: 'RASTER_CONFIG_PKR_YSEL_1', + 2: 'RASTER_CONFIG_PKR_YSEL_2', + 3: 'RASTER_CONFIG_PKR_YSEL_3', +} +RASTER_CONFIG_PKR_YSEL_0 = 0 +RASTER_CONFIG_PKR_YSEL_1 = 1 +RASTER_CONFIG_PKR_YSEL_2 = 2 +RASTER_CONFIG_PKR_YSEL_3 = 3 +PkrYsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbMap' +RbMap__enumvalues = { + 0: 'RASTER_CONFIG_RB_MAP_0', + 1: 'RASTER_CONFIG_RB_MAP_1', + 2: 'RASTER_CONFIG_RB_MAP_2', + 3: 'RASTER_CONFIG_RB_MAP_3', +} +RASTER_CONFIG_RB_MAP_0 = 0 +RASTER_CONFIG_RB_MAP_1 = 1 +RASTER_CONFIG_RB_MAP_2 = 2 +RASTER_CONFIG_RB_MAP_3 = 3 +RbMap = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel' +RbXsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL_0', + 1: 'RASTER_CONFIG_RB_XSEL_1', +} +RASTER_CONFIG_RB_XSEL_0 = 0 +RASTER_CONFIG_RB_XSEL_1 = 1 +RbXsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel2' +RbXsel2__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL2_0', + 1: 'RASTER_CONFIG_RB_XSEL2_1', + 2: 'RASTER_CONFIG_RB_XSEL2_2', + 3: 'RASTER_CONFIG_RB_XSEL2_3', +} +RASTER_CONFIG_RB_XSEL2_0 = 0 +RASTER_CONFIG_RB_XSEL2_1 = 1 +RASTER_CONFIG_RB_XSEL2_2 = 2 +RASTER_CONFIG_RB_XSEL2_3 = 3 +RbXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'RbYsel' +RbYsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_YSEL_0', + 1: 'RASTER_CONFIG_RB_YSEL_1', +} +RASTER_CONFIG_RB_YSEL_0 = 0 +RASTER_CONFIG_RB_YSEL_1 = 1 +RbYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SC_PERFCNT_SEL' +SC_PERFCNT_SEL__enumvalues = { + 0: 'SC_SRPS_WINDOW_VALID', + 1: 'SC_PSSW_WINDOW_VALID', + 2: 'SC_TPQZ_WINDOW_VALID', + 3: 'SC_QZQP_WINDOW_VALID', + 4: 'SC_TRPK_WINDOW_VALID', + 5: 'SC_SRPS_WINDOW_VALID_BUSY', + 6: 'SC_PSSW_WINDOW_VALID_BUSY', + 7: 'SC_TPQZ_WINDOW_VALID_BUSY', + 8: 'SC_QZQP_WINDOW_VALID_BUSY', + 9: 'SC_TRPK_WINDOW_VALID_BUSY', + 10: 'SC_STARVED_BY_PA', + 11: 'SC_STALLED_BY_PRIMFIFO', + 12: 'SC_STALLED_BY_DB_TILE', + 13: 'SC_STARVED_BY_DB_TILE', + 14: 'SC_STALLED_BY_TILEORDERFIFO', + 15: 'SC_STALLED_BY_TILEFIFO', + 16: 'SC_STALLED_BY_DB_QUAD', + 17: 'SC_STARVED_BY_DB_QUAD', + 18: 'SC_STALLED_BY_QUADFIFO', + 19: 'SC_STALLED_BY_BCI', + 20: 'SC_STALLED_BY_SPI', + 21: 'SC_SCISSOR_DISCARD', + 22: 'SC_BB_DISCARD', + 23: 'SC_SUPERTILE_COUNT', + 24: 'SC_SUPERTILE_PER_PRIM_H0', + 25: 'SC_SUPERTILE_PER_PRIM_H1', + 26: 'SC_SUPERTILE_PER_PRIM_H2', + 27: 'SC_SUPERTILE_PER_PRIM_H3', + 28: 'SC_SUPERTILE_PER_PRIM_H4', + 29: 'SC_SUPERTILE_PER_PRIM_H5', + 30: 'SC_SUPERTILE_PER_PRIM_H6', + 31: 'SC_SUPERTILE_PER_PRIM_H7', + 32: 'SC_SUPERTILE_PER_PRIM_H8', + 33: 'SC_SUPERTILE_PER_PRIM_H9', + 34: 'SC_SUPERTILE_PER_PRIM_H10', + 35: 'SC_SUPERTILE_PER_PRIM_H11', + 36: 'SC_SUPERTILE_PER_PRIM_H12', + 37: 'SC_SUPERTILE_PER_PRIM_H13', + 38: 'SC_SUPERTILE_PER_PRIM_H14', + 39: 'SC_SUPERTILE_PER_PRIM_H15', + 40: 'SC_SUPERTILE_PER_PRIM_H16', + 41: 'SC_TILE_PER_PRIM_H0', + 42: 'SC_TILE_PER_PRIM_H1', + 43: 'SC_TILE_PER_PRIM_H2', + 44: 'SC_TILE_PER_PRIM_H3', + 45: 'SC_TILE_PER_PRIM_H4', + 46: 'SC_TILE_PER_PRIM_H5', + 47: 'SC_TILE_PER_PRIM_H6', + 48: 'SC_TILE_PER_PRIM_H7', + 49: 'SC_TILE_PER_PRIM_H8', + 50: 'SC_TILE_PER_PRIM_H9', + 51: 'SC_TILE_PER_PRIM_H10', + 52: 'SC_TILE_PER_PRIM_H11', + 53: 'SC_TILE_PER_PRIM_H12', + 54: 'SC_TILE_PER_PRIM_H13', + 55: 'SC_TILE_PER_PRIM_H14', + 56: 'SC_TILE_PER_PRIM_H15', + 57: 'SC_TILE_PER_PRIM_H16', + 58: 'SC_TILE_PER_SUPERTILE_H0', + 59: 'SC_TILE_PER_SUPERTILE_H1', + 60: 'SC_TILE_PER_SUPERTILE_H2', + 61: 'SC_TILE_PER_SUPERTILE_H3', + 62: 'SC_TILE_PER_SUPERTILE_H4', + 63: 'SC_TILE_PER_SUPERTILE_H5', + 64: 'SC_TILE_PER_SUPERTILE_H6', + 65: 'SC_TILE_PER_SUPERTILE_H7', + 66: 'SC_TILE_PER_SUPERTILE_H8', + 67: 'SC_TILE_PER_SUPERTILE_H9', + 68: 'SC_TILE_PER_SUPERTILE_H10', + 69: 'SC_TILE_PER_SUPERTILE_H11', + 70: 'SC_TILE_PER_SUPERTILE_H12', + 71: 'SC_TILE_PER_SUPERTILE_H13', + 72: 'SC_TILE_PER_SUPERTILE_H14', + 73: 'SC_TILE_PER_SUPERTILE_H15', + 74: 'SC_TILE_PER_SUPERTILE_H16', + 75: 'SC_TILE_PICKED_H1', + 76: 'SC_TILE_PICKED_H2', + 77: 'SC_TILE_PICKED_H3', + 78: 'SC_TILE_PICKED_H4', + 79: 'SC_QZ0_TILE_COUNT', + 80: 'SC_QZ1_TILE_COUNT', + 81: 'SC_QZ2_TILE_COUNT', + 82: 'SC_QZ3_TILE_COUNT', + 83: 'SC_QZ0_TILE_COVERED_COUNT', + 84: 'SC_QZ1_TILE_COVERED_COUNT', + 85: 'SC_QZ2_TILE_COVERED_COUNT', + 86: 'SC_QZ3_TILE_COVERED_COUNT', + 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 88: 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 89: 'SC_QZ2_TILE_NOT_COVERED_COUNT', + 90: 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 91: 'SC_QZ0_QUAD_PER_TILE_H0', + 92: 'SC_QZ0_QUAD_PER_TILE_H1', + 93: 'SC_QZ0_QUAD_PER_TILE_H2', + 94: 'SC_QZ0_QUAD_PER_TILE_H3', + 95: 'SC_QZ0_QUAD_PER_TILE_H4', + 96: 'SC_QZ0_QUAD_PER_TILE_H5', + 97: 'SC_QZ0_QUAD_PER_TILE_H6', + 98: 'SC_QZ0_QUAD_PER_TILE_H7', + 99: 'SC_QZ0_QUAD_PER_TILE_H8', + 100: 'SC_QZ0_QUAD_PER_TILE_H9', + 101: 'SC_QZ0_QUAD_PER_TILE_H10', + 102: 'SC_QZ0_QUAD_PER_TILE_H11', + 103: 'SC_QZ0_QUAD_PER_TILE_H12', + 104: 'SC_QZ0_QUAD_PER_TILE_H13', + 105: 'SC_QZ0_QUAD_PER_TILE_H14', + 106: 'SC_QZ0_QUAD_PER_TILE_H15', + 107: 'SC_QZ0_QUAD_PER_TILE_H16', + 108: 'SC_QZ1_QUAD_PER_TILE_H0', + 109: 'SC_QZ1_QUAD_PER_TILE_H1', + 110: 'SC_QZ1_QUAD_PER_TILE_H2', + 111: 'SC_QZ1_QUAD_PER_TILE_H3', + 112: 'SC_QZ1_QUAD_PER_TILE_H4', + 113: 'SC_QZ1_QUAD_PER_TILE_H5', + 114: 'SC_QZ1_QUAD_PER_TILE_H6', + 115: 'SC_QZ1_QUAD_PER_TILE_H7', + 116: 'SC_QZ1_QUAD_PER_TILE_H8', + 117: 'SC_QZ1_QUAD_PER_TILE_H9', + 118: 'SC_QZ1_QUAD_PER_TILE_H10', + 119: 'SC_QZ1_QUAD_PER_TILE_H11', + 120: 'SC_QZ1_QUAD_PER_TILE_H12', + 121: 'SC_QZ1_QUAD_PER_TILE_H13', + 122: 'SC_QZ1_QUAD_PER_TILE_H14', + 123: 'SC_QZ1_QUAD_PER_TILE_H15', + 124: 'SC_QZ1_QUAD_PER_TILE_H16', + 125: 'SC_QZ2_QUAD_PER_TILE_H0', + 126: 'SC_QZ2_QUAD_PER_TILE_H1', + 127: 'SC_QZ2_QUAD_PER_TILE_H2', + 128: 'SC_QZ2_QUAD_PER_TILE_H3', + 129: 'SC_QZ2_QUAD_PER_TILE_H4', + 130: 'SC_QZ2_QUAD_PER_TILE_H5', + 131: 'SC_QZ2_QUAD_PER_TILE_H6', + 132: 'SC_QZ2_QUAD_PER_TILE_H7', + 133: 'SC_QZ2_QUAD_PER_TILE_H8', + 134: 'SC_QZ2_QUAD_PER_TILE_H9', + 135: 'SC_QZ2_QUAD_PER_TILE_H10', + 136: 'SC_QZ2_QUAD_PER_TILE_H11', + 137: 'SC_QZ2_QUAD_PER_TILE_H12', + 138: 'SC_QZ2_QUAD_PER_TILE_H13', + 139: 'SC_QZ2_QUAD_PER_TILE_H14', + 140: 'SC_QZ2_QUAD_PER_TILE_H15', + 141: 'SC_QZ2_QUAD_PER_TILE_H16', + 142: 'SC_QZ3_QUAD_PER_TILE_H0', + 143: 'SC_QZ3_QUAD_PER_TILE_H1', + 144: 'SC_QZ3_QUAD_PER_TILE_H2', + 145: 'SC_QZ3_QUAD_PER_TILE_H3', + 146: 'SC_QZ3_QUAD_PER_TILE_H4', + 147: 'SC_QZ3_QUAD_PER_TILE_H5', + 148: 'SC_QZ3_QUAD_PER_TILE_H6', + 149: 'SC_QZ3_QUAD_PER_TILE_H7', + 150: 'SC_QZ3_QUAD_PER_TILE_H8', + 151: 'SC_QZ3_QUAD_PER_TILE_H9', + 152: 'SC_QZ3_QUAD_PER_TILE_H10', + 153: 'SC_QZ3_QUAD_PER_TILE_H11', + 154: 'SC_QZ3_QUAD_PER_TILE_H12', + 155: 'SC_QZ3_QUAD_PER_TILE_H13', + 156: 'SC_QZ3_QUAD_PER_TILE_H14', + 157: 'SC_QZ3_QUAD_PER_TILE_H15', + 158: 'SC_QZ3_QUAD_PER_TILE_H16', + 159: 'SC_QZ0_QUAD_COUNT', + 160: 'SC_QZ1_QUAD_COUNT', + 161: 'SC_QZ2_QUAD_COUNT', + 162: 'SC_QZ3_QUAD_COUNT', + 163: 'SC_P0_HIZ_TILE_COUNT', + 164: 'SC_P1_HIZ_TILE_COUNT', + 165: 'SC_P2_HIZ_TILE_COUNT', + 166: 'SC_P3_HIZ_TILE_COUNT', + 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 184: 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 185: 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 186: 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 187: 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 188: 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 189: 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 190: 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 191: 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 192: 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 193: 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 194: 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 195: 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 196: 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 197: 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 198: 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 199: 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 200: 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 201: 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 202: 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 203: 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 204: 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 205: 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 206: 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 207: 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 208: 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 209: 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 210: 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 211: 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 212: 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 213: 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 214: 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 215: 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 216: 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 217: 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 218: 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 219: 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 220: 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 221: 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 222: 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 223: 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 224: 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 225: 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 226: 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 227: 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 228: 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 229: 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 230: 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 231: 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 232: 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 233: 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 234: 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 235: 'SC_P0_HIZ_QUAD_COUNT', + 236: 'SC_P1_HIZ_QUAD_COUNT', + 237: 'SC_P2_HIZ_QUAD_COUNT', + 238: 'SC_P3_HIZ_QUAD_COUNT', + 239: 'SC_P0_DETAIL_QUAD_COUNT', + 240: 'SC_P1_DETAIL_QUAD_COUNT', + 241: 'SC_P2_DETAIL_QUAD_COUNT', + 242: 'SC_P3_DETAIL_QUAD_COUNT', + 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 259: 'SC_EARLYZ_QUAD_COUNT', + 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', + 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', + 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', + 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', + 264: 'SC_PKR_QUAD_PER_ROW_H1', + 265: 'SC_PKR_QUAD_PER_ROW_H2', + 266: 'SC_PKR_4X2_QUAD_SPLIT', + 267: 'SC_PKR_4X2_FILL_QUAD', + 268: 'SC_PKR_END_OF_VECTOR', + 269: 'SC_PKR_CONTROL_XFER', + 270: 'SC_PKR_DBHANG_FORCE_EOV', + 271: 'SC_REG_SCLK_BUSY', + 272: 'SC_GRP0_DYN_SCLK_BUSY', + 273: 'SC_GRP1_DYN_SCLK_BUSY', + 274: 'SC_GRP2_DYN_SCLK_BUSY', + 275: 'SC_GRP3_DYN_SCLK_BUSY', + 276: 'SC_GRP4_DYN_SCLK_BUSY', + 277: 'SC_PA0_SC_DATA_FIFO_RD', + 278: 'SC_PA0_SC_DATA_FIFO_WE', + 279: 'SC_PA1_SC_DATA_FIFO_RD', + 280: 'SC_PA1_SC_DATA_FIFO_WE', + 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', + 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 284: 'SC_PS_ARB_STALLED_FROM_BELOW', + 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', + 286: 'SC_PS_ARB_SC_BUSY', + 287: 'SC_PS_ARB_PA_SC_BUSY', + 288: 'SC_PA2_SC_DATA_FIFO_RD', + 289: 'SC_PA2_SC_DATA_FIFO_WE', + 290: 'SC_PA3_SC_DATA_FIFO_RD', + 291: 'SC_PA3_SC_DATA_FIFO_WE', + 292: 'SC_PA_SC_DEALLOC_0_0_WE', + 293: 'SC_PA_SC_DEALLOC_0_1_WE', + 294: 'SC_PA_SC_DEALLOC_1_0_WE', + 295: 'SC_PA_SC_DEALLOC_1_1_WE', + 296: 'SC_PA_SC_DEALLOC_2_0_WE', + 297: 'SC_PA_SC_DEALLOC_2_1_WE', + 298: 'SC_PA_SC_DEALLOC_3_0_WE', + 299: 'SC_PA_SC_DEALLOC_3_1_WE', + 300: 'SC_PA0_SC_EOP_WE', + 301: 'SC_PA0_SC_EOPG_WE', + 302: 'SC_PA0_SC_EVENT_WE', + 303: 'SC_PA1_SC_EOP_WE', + 304: 'SC_PA1_SC_EOPG_WE', + 305: 'SC_PA1_SC_EVENT_WE', + 306: 'SC_PA2_SC_EOP_WE', + 307: 'SC_PA2_SC_EOPG_WE', + 308: 'SC_PA2_SC_EVENT_WE', + 309: 'SC_PA3_SC_EOP_WE', + 310: 'SC_PA3_SC_EOPG_WE', + 311: 'SC_PA3_SC_EVENT_WE', + 312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 315: 'SC_PS_ARB_EOP_POP_SYNC_POP', + 316: 'SC_PS_ARB_EVENT_SYNC_POP', + 317: 'SC_PS_ENG_MULTICYCLE_BUBBLE', + 318: 'SC_PA0_SC_FPOV_WE', + 319: 'SC_PA1_SC_FPOV_WE', + 320: 'SC_PA2_SC_FPOV_WE', + 321: 'SC_PA3_SC_FPOV_WE', + 322: 'SC_PA0_SC_LPOV_WE', + 323: 'SC_PA1_SC_LPOV_WE', + 324: 'SC_PA2_SC_LPOV_WE', + 325: 'SC_PA3_SC_LPOV_WE', + 326: 'SC_SPI_DEALLOC_0_0', + 327: 'SC_SPI_DEALLOC_0_1', + 328: 'SC_SPI_DEALLOC_0_2', + 329: 'SC_SPI_DEALLOC_1_0', + 330: 'SC_SPI_DEALLOC_1_1', + 331: 'SC_SPI_DEALLOC_1_2', + 332: 'SC_SPI_DEALLOC_2_0', + 333: 'SC_SPI_DEALLOC_2_1', + 334: 'SC_SPI_DEALLOC_2_2', + 335: 'SC_SPI_DEALLOC_3_0', + 336: 'SC_SPI_DEALLOC_3_1', + 337: 'SC_SPI_DEALLOC_3_2', + 338: 'SC_SPI_FPOV_0', + 339: 'SC_SPI_FPOV_1', + 340: 'SC_SPI_FPOV_2', + 341: 'SC_SPI_FPOV_3', + 342: 'SC_SPI_EVENT', + 343: 'SC_PS_TS_EVENT_FIFO_PUSH', + 344: 'SC_PS_TS_EVENT_FIFO_POP', + 345: 'SC_PS_CTX_DONE_FIFO_PUSH', + 346: 'SC_PS_CTX_DONE_FIFO_POP', + 347: 'SC_MULTICYCLE_BUBBLE_FREEZE', + 348: 'SC_EOP_SYNC_WINDOW', + 349: 'SC_PA0_SC_NULL_WE', + 350: 'SC_PA0_SC_NULL_DEALLOC_WE', + 351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', + 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 353: 'SC_PA0_SC_DEALLOC_0_RD', + 354: 'SC_PA0_SC_DEALLOC_1_RD', + 355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 356: 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 357: 'SC_PA1_SC_DEALLOC_0_RD', + 358: 'SC_PA1_SC_DEALLOC_1_RD', + 359: 'SC_PA1_SC_NULL_WE', + 360: 'SC_PA1_SC_NULL_DEALLOC_WE', + 361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 362: 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 363: 'SC_PA2_SC_DEALLOC_0_RD', + 364: 'SC_PA2_SC_DEALLOC_1_RD', + 365: 'SC_PA2_SC_NULL_WE', + 366: 'SC_PA2_SC_NULL_DEALLOC_WE', + 367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 368: 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 369: 'SC_PA3_SC_DEALLOC_0_RD', + 370: 'SC_PA3_SC_DEALLOC_1_RD', + 371: 'SC_PA3_SC_NULL_WE', + 372: 'SC_PA3_SC_NULL_DEALLOC_WE', + 373: 'SC_PS_PA0_SC_FIFO_EMPTY', + 374: 'SC_PS_PA0_SC_FIFO_FULL', + 375: 'SC_RESERVED_0', + 376: 'SC_PS_PA1_SC_FIFO_EMPTY', + 377: 'SC_PS_PA1_SC_FIFO_FULL', + 378: 'SC_RESERVED_1', + 379: 'SC_PS_PA2_SC_FIFO_EMPTY', + 380: 'SC_PS_PA2_SC_FIFO_FULL', + 381: 'SC_RESERVED_2', + 382: 'SC_PS_PA3_SC_FIFO_EMPTY', + 383: 'SC_PS_PA3_SC_FIFO_FULL', + 384: 'SC_RESERVED_3', + 385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', + 386: 'SC_BUSY_CNT_NOT_ZERO', + 387: 'SC_BM_BUSY', + 388: 'SC_BACKEND_BUSY', + 389: 'SC_SCF_SCB_INTERFACE_BUSY', + 390: 'SC_SCB_BUSY', + 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', + 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 403: 'SC_PBB_BUSY', + 404: 'SC_PBB_BUSY_AND_NO_SENDS', + 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 406: 'SC_PBB_NUM_BINS', + 407: 'SC_PBB_END_OF_BIN', + 408: 'SC_PBB_END_OF_BATCH', + 409: 'SC_PBB_PRIMBIN_PROCESSED', + 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', + 411: 'SC_PBB_NONBINNED_PRIM', + 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', + 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 423: 'SC_POPS_INTRA_WAVE_OVERLAPS', + 424: 'SC_POPS_FORCE_EOV', + 425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 428: 'SC_FULL_FULL_QUAD', + 429: 'SC_FULL_HALF_QUAD', + 430: 'SC_FULL_QTR_QUAD', + 431: 'SC_HALF_FULL_QUAD', + 432: 'SC_HALF_HALF_QUAD', + 433: 'SC_HALF_QTR_QUAD', + 434: 'SC_QTR_FULL_QUAD', + 435: 'SC_QTR_HALF_QUAD', + 436: 'SC_QTR_QTR_QUAD', + 437: 'SC_GRP5_DYN_SCLK_BUSY', + 438: 'SC_GRP6_DYN_SCLK_BUSY', + 439: 'SC_GRP7_DYN_SCLK_BUSY', + 440: 'SC_GRP8_DYN_SCLK_BUSY', + 441: 'SC_GRP9_DYN_SCLK_BUSY', + 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', + 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 444: 'SC_PK_BUSY', + 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', + 446: 'SC_PK_DEALLOC_WAVE_BREAK', + 447: 'SC_SPI_SEND', + 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 449: 'SC_SPI_CREDIT_AT_MAX', + 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 451: 'SC_BCI_SEND', + 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 453: 'SC_BCI_CREDIT_AT_MAX', + 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 455: 'SC_SPIBC_FULL_FREEZE', + 456: 'SC_PW_BM_PASS_EMPTY_PRIM', + 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 475: 'SC_DB0_TILE_INTERFACE_BUSY', + 476: 'SC_DB0_TILE_INTERFACE_SEND', + 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 479: 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 483: 'SC_DB1_TILE_INTERFACE_BUSY', + 484: 'SC_DB1_TILE_INTERFACE_SEND', + 485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 487: 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 491: 'SC_BACKEND_PRIM_FIFO_FULL', + 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 503: 'SC_STALLED_BY_DB0_TILEFIFO', + 504: 'SC_DB0_QUAD_INTF_SEND', + 505: 'SC_DB0_QUAD_INTF_BUSY', + 506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB', + 507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', + 508: 'SC_DB0_QUAD_INTF_IDLE', + 509: 'SC_DB1_QUAD_INTF_SEND', + 510: 'SC_STALLED_BY_DB1_TILEFIFO', + 511: 'SC_DB1_QUAD_INTF_BUSY', + 512: 'SC_DB1_QUAD_INTF_STALLED_BY_DB', + 513: 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', + 514: 'SC_DB1_QUAD_INTF_IDLE', + 515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', + 516: 'SC_PKR_WAVE_BREAK_FULL_TILE', + 517: 'SC_FSR_WALKED', + 518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', + 519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 522: 'SC_DB0_TILE_MASK_FIFO_FULL', + 523: 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', + 524: 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 525: 'SC_DB1_TILE_MASK_FIFO_FULL', + 526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 529: 'SC_PS_PM_PFF_PW_FULL', + 530: 'SC_PS_PM_ZFF_PW_FULL', + 531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 532: 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', + 533: 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 534: 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 539: 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', + 540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 547: 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', + 548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 568: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', + 569: 'SC_PBB_RESERVED', + 570: 'SC_BM_BE0_STALLED', + 571: 'SC_BM_BE1_STALLED', + 572: 'SC_BM_BE2_STALLED', + 573: 'SC_BM_BE3_STALLED', + 574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED', +} +SC_SRPS_WINDOW_VALID = 0 +SC_PSSW_WINDOW_VALID = 1 +SC_TPQZ_WINDOW_VALID = 2 +SC_QZQP_WINDOW_VALID = 3 +SC_TRPK_WINDOW_VALID = 4 +SC_SRPS_WINDOW_VALID_BUSY = 5 +SC_PSSW_WINDOW_VALID_BUSY = 6 +SC_TPQZ_WINDOW_VALID_BUSY = 7 +SC_QZQP_WINDOW_VALID_BUSY = 8 +SC_TRPK_WINDOW_VALID_BUSY = 9 +SC_STARVED_BY_PA = 10 +SC_STALLED_BY_PRIMFIFO = 11 +SC_STALLED_BY_DB_TILE = 12 +SC_STARVED_BY_DB_TILE = 13 +SC_STALLED_BY_TILEORDERFIFO = 14 +SC_STALLED_BY_TILEFIFO = 15 +SC_STALLED_BY_DB_QUAD = 16 +SC_STARVED_BY_DB_QUAD = 17 +SC_STALLED_BY_QUADFIFO = 18 +SC_STALLED_BY_BCI = 19 +SC_STALLED_BY_SPI = 20 +SC_SCISSOR_DISCARD = 21 +SC_BB_DISCARD = 22 +SC_SUPERTILE_COUNT = 23 +SC_SUPERTILE_PER_PRIM_H0 = 24 +SC_SUPERTILE_PER_PRIM_H1 = 25 +SC_SUPERTILE_PER_PRIM_H2 = 26 +SC_SUPERTILE_PER_PRIM_H3 = 27 +SC_SUPERTILE_PER_PRIM_H4 = 28 +SC_SUPERTILE_PER_PRIM_H5 = 29 +SC_SUPERTILE_PER_PRIM_H6 = 30 +SC_SUPERTILE_PER_PRIM_H7 = 31 +SC_SUPERTILE_PER_PRIM_H8 = 32 +SC_SUPERTILE_PER_PRIM_H9 = 33 +SC_SUPERTILE_PER_PRIM_H10 = 34 +SC_SUPERTILE_PER_PRIM_H11 = 35 +SC_SUPERTILE_PER_PRIM_H12 = 36 +SC_SUPERTILE_PER_PRIM_H13 = 37 +SC_SUPERTILE_PER_PRIM_H14 = 38 +SC_SUPERTILE_PER_PRIM_H15 = 39 +SC_SUPERTILE_PER_PRIM_H16 = 40 +SC_TILE_PER_PRIM_H0 = 41 +SC_TILE_PER_PRIM_H1 = 42 +SC_TILE_PER_PRIM_H2 = 43 +SC_TILE_PER_PRIM_H3 = 44 +SC_TILE_PER_PRIM_H4 = 45 +SC_TILE_PER_PRIM_H5 = 46 +SC_TILE_PER_PRIM_H6 = 47 +SC_TILE_PER_PRIM_H7 = 48 +SC_TILE_PER_PRIM_H8 = 49 +SC_TILE_PER_PRIM_H9 = 50 +SC_TILE_PER_PRIM_H10 = 51 +SC_TILE_PER_PRIM_H11 = 52 +SC_TILE_PER_PRIM_H12 = 53 +SC_TILE_PER_PRIM_H13 = 54 +SC_TILE_PER_PRIM_H14 = 55 +SC_TILE_PER_PRIM_H15 = 56 +SC_TILE_PER_PRIM_H16 = 57 +SC_TILE_PER_SUPERTILE_H0 = 58 +SC_TILE_PER_SUPERTILE_H1 = 59 +SC_TILE_PER_SUPERTILE_H2 = 60 +SC_TILE_PER_SUPERTILE_H3 = 61 +SC_TILE_PER_SUPERTILE_H4 = 62 +SC_TILE_PER_SUPERTILE_H5 = 63 +SC_TILE_PER_SUPERTILE_H6 = 64 +SC_TILE_PER_SUPERTILE_H7 = 65 +SC_TILE_PER_SUPERTILE_H8 = 66 +SC_TILE_PER_SUPERTILE_H9 = 67 +SC_TILE_PER_SUPERTILE_H10 = 68 +SC_TILE_PER_SUPERTILE_H11 = 69 +SC_TILE_PER_SUPERTILE_H12 = 70 +SC_TILE_PER_SUPERTILE_H13 = 71 +SC_TILE_PER_SUPERTILE_H14 = 72 +SC_TILE_PER_SUPERTILE_H15 = 73 +SC_TILE_PER_SUPERTILE_H16 = 74 +SC_TILE_PICKED_H1 = 75 +SC_TILE_PICKED_H2 = 76 +SC_TILE_PICKED_H3 = 77 +SC_TILE_PICKED_H4 = 78 +SC_QZ0_TILE_COUNT = 79 +SC_QZ1_TILE_COUNT = 80 +SC_QZ2_TILE_COUNT = 81 +SC_QZ3_TILE_COUNT = 82 +SC_QZ0_TILE_COVERED_COUNT = 83 +SC_QZ1_TILE_COVERED_COUNT = 84 +SC_QZ2_TILE_COVERED_COUNT = 85 +SC_QZ3_TILE_COVERED_COUNT = 86 +SC_QZ0_TILE_NOT_COVERED_COUNT = 87 +SC_QZ1_TILE_NOT_COVERED_COUNT = 88 +SC_QZ2_TILE_NOT_COVERED_COUNT = 89 +SC_QZ3_TILE_NOT_COVERED_COUNT = 90 +SC_QZ0_QUAD_PER_TILE_H0 = 91 +SC_QZ0_QUAD_PER_TILE_H1 = 92 +SC_QZ0_QUAD_PER_TILE_H2 = 93 +SC_QZ0_QUAD_PER_TILE_H3 = 94 +SC_QZ0_QUAD_PER_TILE_H4 = 95 +SC_QZ0_QUAD_PER_TILE_H5 = 96 +SC_QZ0_QUAD_PER_TILE_H6 = 97 +SC_QZ0_QUAD_PER_TILE_H7 = 98 +SC_QZ0_QUAD_PER_TILE_H8 = 99 +SC_QZ0_QUAD_PER_TILE_H9 = 100 +SC_QZ0_QUAD_PER_TILE_H10 = 101 +SC_QZ0_QUAD_PER_TILE_H11 = 102 +SC_QZ0_QUAD_PER_TILE_H12 = 103 +SC_QZ0_QUAD_PER_TILE_H13 = 104 +SC_QZ0_QUAD_PER_TILE_H14 = 105 +SC_QZ0_QUAD_PER_TILE_H15 = 106 +SC_QZ0_QUAD_PER_TILE_H16 = 107 +SC_QZ1_QUAD_PER_TILE_H0 = 108 +SC_QZ1_QUAD_PER_TILE_H1 = 109 +SC_QZ1_QUAD_PER_TILE_H2 = 110 +SC_QZ1_QUAD_PER_TILE_H3 = 111 +SC_QZ1_QUAD_PER_TILE_H4 = 112 +SC_QZ1_QUAD_PER_TILE_H5 = 113 +SC_QZ1_QUAD_PER_TILE_H6 = 114 +SC_QZ1_QUAD_PER_TILE_H7 = 115 +SC_QZ1_QUAD_PER_TILE_H8 = 116 +SC_QZ1_QUAD_PER_TILE_H9 = 117 +SC_QZ1_QUAD_PER_TILE_H10 = 118 +SC_QZ1_QUAD_PER_TILE_H11 = 119 +SC_QZ1_QUAD_PER_TILE_H12 = 120 +SC_QZ1_QUAD_PER_TILE_H13 = 121 +SC_QZ1_QUAD_PER_TILE_H14 = 122 +SC_QZ1_QUAD_PER_TILE_H15 = 123 +SC_QZ1_QUAD_PER_TILE_H16 = 124 +SC_QZ2_QUAD_PER_TILE_H0 = 125 +SC_QZ2_QUAD_PER_TILE_H1 = 126 +SC_QZ2_QUAD_PER_TILE_H2 = 127 +SC_QZ2_QUAD_PER_TILE_H3 = 128 +SC_QZ2_QUAD_PER_TILE_H4 = 129 +SC_QZ2_QUAD_PER_TILE_H5 = 130 +SC_QZ2_QUAD_PER_TILE_H6 = 131 +SC_QZ2_QUAD_PER_TILE_H7 = 132 +SC_QZ2_QUAD_PER_TILE_H8 = 133 +SC_QZ2_QUAD_PER_TILE_H9 = 134 +SC_QZ2_QUAD_PER_TILE_H10 = 135 +SC_QZ2_QUAD_PER_TILE_H11 = 136 +SC_QZ2_QUAD_PER_TILE_H12 = 137 +SC_QZ2_QUAD_PER_TILE_H13 = 138 +SC_QZ2_QUAD_PER_TILE_H14 = 139 +SC_QZ2_QUAD_PER_TILE_H15 = 140 +SC_QZ2_QUAD_PER_TILE_H16 = 141 +SC_QZ3_QUAD_PER_TILE_H0 = 142 +SC_QZ3_QUAD_PER_TILE_H1 = 143 +SC_QZ3_QUAD_PER_TILE_H2 = 144 +SC_QZ3_QUAD_PER_TILE_H3 = 145 +SC_QZ3_QUAD_PER_TILE_H4 = 146 +SC_QZ3_QUAD_PER_TILE_H5 = 147 +SC_QZ3_QUAD_PER_TILE_H6 = 148 +SC_QZ3_QUAD_PER_TILE_H7 = 149 +SC_QZ3_QUAD_PER_TILE_H8 = 150 +SC_QZ3_QUAD_PER_TILE_H9 = 151 +SC_QZ3_QUAD_PER_TILE_H10 = 152 +SC_QZ3_QUAD_PER_TILE_H11 = 153 +SC_QZ3_QUAD_PER_TILE_H12 = 154 +SC_QZ3_QUAD_PER_TILE_H13 = 155 +SC_QZ3_QUAD_PER_TILE_H14 = 156 +SC_QZ3_QUAD_PER_TILE_H15 = 157 +SC_QZ3_QUAD_PER_TILE_H16 = 158 +SC_QZ0_QUAD_COUNT = 159 +SC_QZ1_QUAD_COUNT = 160 +SC_QZ2_QUAD_COUNT = 161 +SC_QZ3_QUAD_COUNT = 162 +SC_P0_HIZ_TILE_COUNT = 163 +SC_P1_HIZ_TILE_COUNT = 164 +SC_P2_HIZ_TILE_COUNT = 165 +SC_P3_HIZ_TILE_COUNT = 166 +SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 +SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 +SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 +SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 +SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 +SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 +SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 +SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 +SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 +SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 +SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 +SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 +SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 +SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 +SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 +SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 +SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 +SC_P1_HIZ_QUAD_PER_TILE_H0 = 184 +SC_P1_HIZ_QUAD_PER_TILE_H1 = 185 +SC_P1_HIZ_QUAD_PER_TILE_H2 = 186 +SC_P1_HIZ_QUAD_PER_TILE_H3 = 187 +SC_P1_HIZ_QUAD_PER_TILE_H4 = 188 +SC_P1_HIZ_QUAD_PER_TILE_H5 = 189 +SC_P1_HIZ_QUAD_PER_TILE_H6 = 190 +SC_P1_HIZ_QUAD_PER_TILE_H7 = 191 +SC_P1_HIZ_QUAD_PER_TILE_H8 = 192 +SC_P1_HIZ_QUAD_PER_TILE_H9 = 193 +SC_P1_HIZ_QUAD_PER_TILE_H10 = 194 +SC_P1_HIZ_QUAD_PER_TILE_H11 = 195 +SC_P1_HIZ_QUAD_PER_TILE_H12 = 196 +SC_P1_HIZ_QUAD_PER_TILE_H13 = 197 +SC_P1_HIZ_QUAD_PER_TILE_H14 = 198 +SC_P1_HIZ_QUAD_PER_TILE_H15 = 199 +SC_P1_HIZ_QUAD_PER_TILE_H16 = 200 +SC_P2_HIZ_QUAD_PER_TILE_H0 = 201 +SC_P2_HIZ_QUAD_PER_TILE_H1 = 202 +SC_P2_HIZ_QUAD_PER_TILE_H2 = 203 +SC_P2_HIZ_QUAD_PER_TILE_H3 = 204 +SC_P2_HIZ_QUAD_PER_TILE_H4 = 205 +SC_P2_HIZ_QUAD_PER_TILE_H5 = 206 +SC_P2_HIZ_QUAD_PER_TILE_H6 = 207 +SC_P2_HIZ_QUAD_PER_TILE_H7 = 208 +SC_P2_HIZ_QUAD_PER_TILE_H8 = 209 +SC_P2_HIZ_QUAD_PER_TILE_H9 = 210 +SC_P2_HIZ_QUAD_PER_TILE_H10 = 211 +SC_P2_HIZ_QUAD_PER_TILE_H11 = 212 +SC_P2_HIZ_QUAD_PER_TILE_H12 = 213 +SC_P2_HIZ_QUAD_PER_TILE_H13 = 214 +SC_P2_HIZ_QUAD_PER_TILE_H14 = 215 +SC_P2_HIZ_QUAD_PER_TILE_H15 = 216 +SC_P2_HIZ_QUAD_PER_TILE_H16 = 217 +SC_P3_HIZ_QUAD_PER_TILE_H0 = 218 +SC_P3_HIZ_QUAD_PER_TILE_H1 = 219 +SC_P3_HIZ_QUAD_PER_TILE_H2 = 220 +SC_P3_HIZ_QUAD_PER_TILE_H3 = 221 +SC_P3_HIZ_QUAD_PER_TILE_H4 = 222 +SC_P3_HIZ_QUAD_PER_TILE_H5 = 223 +SC_P3_HIZ_QUAD_PER_TILE_H6 = 224 +SC_P3_HIZ_QUAD_PER_TILE_H7 = 225 +SC_P3_HIZ_QUAD_PER_TILE_H8 = 226 +SC_P3_HIZ_QUAD_PER_TILE_H9 = 227 +SC_P3_HIZ_QUAD_PER_TILE_H10 = 228 +SC_P3_HIZ_QUAD_PER_TILE_H11 = 229 +SC_P3_HIZ_QUAD_PER_TILE_H12 = 230 +SC_P3_HIZ_QUAD_PER_TILE_H13 = 231 +SC_P3_HIZ_QUAD_PER_TILE_H14 = 232 +SC_P3_HIZ_QUAD_PER_TILE_H15 = 233 +SC_P3_HIZ_QUAD_PER_TILE_H16 = 234 +SC_P0_HIZ_QUAD_COUNT = 235 +SC_P1_HIZ_QUAD_COUNT = 236 +SC_P2_HIZ_QUAD_COUNT = 237 +SC_P3_HIZ_QUAD_COUNT = 238 +SC_P0_DETAIL_QUAD_COUNT = 239 +SC_P1_DETAIL_QUAD_COUNT = 240 +SC_P2_DETAIL_QUAD_COUNT = 241 +SC_P3_DETAIL_QUAD_COUNT = 242 +SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 +SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 +SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 +SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 +SC_P1_DETAIL_QUAD_WITH_1_PIX = 247 +SC_P1_DETAIL_QUAD_WITH_2_PIX = 248 +SC_P1_DETAIL_QUAD_WITH_3_PIX = 249 +SC_P1_DETAIL_QUAD_WITH_4_PIX = 250 +SC_P2_DETAIL_QUAD_WITH_1_PIX = 251 +SC_P2_DETAIL_QUAD_WITH_2_PIX = 252 +SC_P2_DETAIL_QUAD_WITH_3_PIX = 253 +SC_P2_DETAIL_QUAD_WITH_4_PIX = 254 +SC_P3_DETAIL_QUAD_WITH_1_PIX = 255 +SC_P3_DETAIL_QUAD_WITH_2_PIX = 256 +SC_P3_DETAIL_QUAD_WITH_3_PIX = 257 +SC_P3_DETAIL_QUAD_WITH_4_PIX = 258 +SC_EARLYZ_QUAD_COUNT = 259 +SC_EARLYZ_QUAD_WITH_1_PIX = 260 +SC_EARLYZ_QUAD_WITH_2_PIX = 261 +SC_EARLYZ_QUAD_WITH_3_PIX = 262 +SC_EARLYZ_QUAD_WITH_4_PIX = 263 +SC_PKR_QUAD_PER_ROW_H1 = 264 +SC_PKR_QUAD_PER_ROW_H2 = 265 +SC_PKR_4X2_QUAD_SPLIT = 266 +SC_PKR_4X2_FILL_QUAD = 267 +SC_PKR_END_OF_VECTOR = 268 +SC_PKR_CONTROL_XFER = 269 +SC_PKR_DBHANG_FORCE_EOV = 270 +SC_REG_SCLK_BUSY = 271 +SC_GRP0_DYN_SCLK_BUSY = 272 +SC_GRP1_DYN_SCLK_BUSY = 273 +SC_GRP2_DYN_SCLK_BUSY = 274 +SC_GRP3_DYN_SCLK_BUSY = 275 +SC_GRP4_DYN_SCLK_BUSY = 276 +SC_PA0_SC_DATA_FIFO_RD = 277 +SC_PA0_SC_DATA_FIFO_WE = 278 +SC_PA1_SC_DATA_FIFO_RD = 279 +SC_PA1_SC_DATA_FIFO_WE = 280 +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 +SC_PS_ARB_STALLED_FROM_BELOW = 284 +SC_PS_ARB_STARVED_FROM_ABOVE = 285 +SC_PS_ARB_SC_BUSY = 286 +SC_PS_ARB_PA_SC_BUSY = 287 +SC_PA2_SC_DATA_FIFO_RD = 288 +SC_PA2_SC_DATA_FIFO_WE = 289 +SC_PA3_SC_DATA_FIFO_RD = 290 +SC_PA3_SC_DATA_FIFO_WE = 291 +SC_PA_SC_DEALLOC_0_0_WE = 292 +SC_PA_SC_DEALLOC_0_1_WE = 293 +SC_PA_SC_DEALLOC_1_0_WE = 294 +SC_PA_SC_DEALLOC_1_1_WE = 295 +SC_PA_SC_DEALLOC_2_0_WE = 296 +SC_PA_SC_DEALLOC_2_1_WE = 297 +SC_PA_SC_DEALLOC_3_0_WE = 298 +SC_PA_SC_DEALLOC_3_1_WE = 299 +SC_PA0_SC_EOP_WE = 300 +SC_PA0_SC_EOPG_WE = 301 +SC_PA0_SC_EVENT_WE = 302 +SC_PA1_SC_EOP_WE = 303 +SC_PA1_SC_EOPG_WE = 304 +SC_PA1_SC_EVENT_WE = 305 +SC_PA2_SC_EOP_WE = 306 +SC_PA2_SC_EOPG_WE = 307 +SC_PA2_SC_EVENT_WE = 308 +SC_PA3_SC_EOP_WE = 309 +SC_PA3_SC_EOPG_WE = 310 +SC_PA3_SC_EVENT_WE = 311 +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312 +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313 +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314 +SC_PS_ARB_EOP_POP_SYNC_POP = 315 +SC_PS_ARB_EVENT_SYNC_POP = 316 +SC_PS_ENG_MULTICYCLE_BUBBLE = 317 +SC_PA0_SC_FPOV_WE = 318 +SC_PA1_SC_FPOV_WE = 319 +SC_PA2_SC_FPOV_WE = 320 +SC_PA3_SC_FPOV_WE = 321 +SC_PA0_SC_LPOV_WE = 322 +SC_PA1_SC_LPOV_WE = 323 +SC_PA2_SC_LPOV_WE = 324 +SC_PA3_SC_LPOV_WE = 325 +SC_SPI_DEALLOC_0_0 = 326 +SC_SPI_DEALLOC_0_1 = 327 +SC_SPI_DEALLOC_0_2 = 328 +SC_SPI_DEALLOC_1_0 = 329 +SC_SPI_DEALLOC_1_1 = 330 +SC_SPI_DEALLOC_1_2 = 331 +SC_SPI_DEALLOC_2_0 = 332 +SC_SPI_DEALLOC_2_1 = 333 +SC_SPI_DEALLOC_2_2 = 334 +SC_SPI_DEALLOC_3_0 = 335 +SC_SPI_DEALLOC_3_1 = 336 +SC_SPI_DEALLOC_3_2 = 337 +SC_SPI_FPOV_0 = 338 +SC_SPI_FPOV_1 = 339 +SC_SPI_FPOV_2 = 340 +SC_SPI_FPOV_3 = 341 +SC_SPI_EVENT = 342 +SC_PS_TS_EVENT_FIFO_PUSH = 343 +SC_PS_TS_EVENT_FIFO_POP = 344 +SC_PS_CTX_DONE_FIFO_PUSH = 345 +SC_PS_CTX_DONE_FIFO_POP = 346 +SC_MULTICYCLE_BUBBLE_FREEZE = 347 +SC_EOP_SYNC_WINDOW = 348 +SC_PA0_SC_NULL_WE = 349 +SC_PA0_SC_NULL_DEALLOC_WE = 350 +SC_PA0_SC_DATA_FIFO_EOPG_RD = 351 +SC_PA0_SC_DATA_FIFO_EOP_RD = 352 +SC_PA0_SC_DEALLOC_0_RD = 353 +SC_PA0_SC_DEALLOC_1_RD = 354 +SC_PA1_SC_DATA_FIFO_EOPG_RD = 355 +SC_PA1_SC_DATA_FIFO_EOP_RD = 356 +SC_PA1_SC_DEALLOC_0_RD = 357 +SC_PA1_SC_DEALLOC_1_RD = 358 +SC_PA1_SC_NULL_WE = 359 +SC_PA1_SC_NULL_DEALLOC_WE = 360 +SC_PA2_SC_DATA_FIFO_EOPG_RD = 361 +SC_PA2_SC_DATA_FIFO_EOP_RD = 362 +SC_PA2_SC_DEALLOC_0_RD = 363 +SC_PA2_SC_DEALLOC_1_RD = 364 +SC_PA2_SC_NULL_WE = 365 +SC_PA2_SC_NULL_DEALLOC_WE = 366 +SC_PA3_SC_DATA_FIFO_EOPG_RD = 367 +SC_PA3_SC_DATA_FIFO_EOP_RD = 368 +SC_PA3_SC_DEALLOC_0_RD = 369 +SC_PA3_SC_DEALLOC_1_RD = 370 +SC_PA3_SC_NULL_WE = 371 +SC_PA3_SC_NULL_DEALLOC_WE = 372 +SC_PS_PA0_SC_FIFO_EMPTY = 373 +SC_PS_PA0_SC_FIFO_FULL = 374 +SC_RESERVED_0 = 375 +SC_PS_PA1_SC_FIFO_EMPTY = 376 +SC_PS_PA1_SC_FIFO_FULL = 377 +SC_RESERVED_1 = 378 +SC_PS_PA2_SC_FIFO_EMPTY = 379 +SC_PS_PA2_SC_FIFO_FULL = 380 +SC_RESERVED_2 = 381 +SC_PS_PA3_SC_FIFO_EMPTY = 382 +SC_PS_PA3_SC_FIFO_FULL = 383 +SC_RESERVED_3 = 384 +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385 +SC_BUSY_CNT_NOT_ZERO = 386 +SC_BM_BUSY = 387 +SC_BACKEND_BUSY = 388 +SC_SCF_SCB_INTERFACE_BUSY = 389 +SC_SCB_BUSY = 390 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 +SC_PBB_BIN_HIST_NUM_PRIMS = 393 +SC_PBB_BATCH_HIST_NUM_PRIMS = 394 +SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 +SC_PBB_BUSY = 403 +SC_PBB_BUSY_AND_NO_SENDS = 404 +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 +SC_PBB_NUM_BINS = 406 +SC_PBB_END_OF_BIN = 407 +SC_PBB_END_OF_BATCH = 408 +SC_PBB_PRIMBIN_PROCESSED = 409 +SC_PBB_PRIM_ADDED_TO_BATCH = 410 +SC_PBB_NONBINNED_PRIM = 411 +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 +SC_POPS_INTRA_WAVE_OVERLAPS = 423 +SC_POPS_FORCE_EOV = 424 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426 +SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427 +SC_FULL_FULL_QUAD = 428 +SC_FULL_HALF_QUAD = 429 +SC_FULL_QTR_QUAD = 430 +SC_HALF_FULL_QUAD = 431 +SC_HALF_HALF_QUAD = 432 +SC_HALF_QTR_QUAD = 433 +SC_QTR_FULL_QUAD = 434 +SC_QTR_HALF_QUAD = 435 +SC_QTR_QTR_QUAD = 436 +SC_GRP5_DYN_SCLK_BUSY = 437 +SC_GRP6_DYN_SCLK_BUSY = 438 +SC_GRP7_DYN_SCLK_BUSY = 439 +SC_GRP8_DYN_SCLK_BUSY = 440 +SC_GRP9_DYN_SCLK_BUSY = 441 +SC_PS_TO_BE_SCLK_GATE_STALL = 442 +SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 +SC_PK_BUSY = 444 +SC_PK_MAX_DEALLOC_FORCE_EOV = 445 +SC_PK_DEALLOC_WAVE_BREAK = 446 +SC_SPI_SEND = 447 +SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 +SC_SPI_CREDIT_AT_MAX = 449 +SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 +SC_BCI_SEND = 451 +SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 +SC_BCI_CREDIT_AT_MAX = 453 +SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 +SC_SPIBC_FULL_FREEZE = 455 +SC_PW_BM_PASS_EMPTY_PRIM = 456 +SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 +SC_DB0_TILE_INTERFACE_BUSY = 475 +SC_DB0_TILE_INTERFACE_SEND = 476 +SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 +SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478 +SC_DB0_TILE_INTERFACE_SEND_SOP = 479 +SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 +SC_DB1_TILE_INTERFACE_BUSY = 483 +SC_DB1_TILE_INTERFACE_SEND = 484 +SC_DB1_TILE_INTERFACE_SEND_EVENT = 485 +SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486 +SC_DB1_TILE_INTERFACE_SEND_SOP = 487 +SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490 +SC_BACKEND_PRIM_FIFO_FULL = 491 +SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 +SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 +SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 +SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 +SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 +SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501 +SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502 +SC_STALLED_BY_DB0_TILEFIFO = 503 +SC_DB0_QUAD_INTF_SEND = 504 +SC_DB0_QUAD_INTF_BUSY = 505 +SC_DB0_QUAD_INTF_STALLED_BY_DB = 506 +SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507 +SC_DB0_QUAD_INTF_IDLE = 508 +SC_DB1_QUAD_INTF_SEND = 509 +SC_STALLED_BY_DB1_TILEFIFO = 510 +SC_DB1_QUAD_INTF_BUSY = 511 +SC_DB1_QUAD_INTF_STALLED_BY_DB = 512 +SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 513 +SC_DB1_QUAD_INTF_IDLE = 514 +SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515 +SC_PKR_WAVE_BREAK_FULL_TILE = 516 +SC_FSR_WALKED = 517 +SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518 +SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519 +SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520 +SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521 +SC_DB0_TILE_MASK_FIFO_FULL = 522 +SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 523 +SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 524 +SC_DB1_TILE_MASK_FIFO_FULL = 525 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528 +SC_PS_PM_PFF_PW_FULL = 529 +SC_PS_PM_ZFF_PW_FULL = 530 +SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531 +SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 532 +SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 533 +SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 534 +SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535 +SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536 +SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537 +SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538 +SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 539 +SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540 +SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541 +SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542 +SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543 +SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544 +SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545 +SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546 +SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 547 +SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548 +SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549 +SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550 +SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551 +SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552 +SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553 +SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554 +SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555 +SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556 +SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557 +SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558 +SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559 +SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560 +SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561 +SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562 +SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563 +SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564 +SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565 +SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566 +SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 568 +SC_PBB_RESERVED = 569 +SC_BM_BE0_STALLED = 570 +SC_BM_BE1_STALLED = 571 +SC_BM_BE2_STALLED = 572 +SC_BM_BE3_STALLED = 573 +SC_BM_MULTI_ACCUM_1_BE_STALLED = 574 +SC_BM_MULTI_ACCUM_2_BE_STALLED = 575 +SC_BM_MULTI_ACCUM_3_BE_STALLED = 576 +SC_BM_MULTI_ACCUM_4_BE_STALLED = 577 +SC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ScMap' +ScMap__enumvalues = { + 0: 'RASTER_CONFIG_SC_MAP_0', + 1: 'RASTER_CONFIG_SC_MAP_1', + 2: 'RASTER_CONFIG_SC_MAP_2', + 3: 'RASTER_CONFIG_SC_MAP_3', +} +RASTER_CONFIG_SC_MAP_0 = 0 +RASTER_CONFIG_SC_MAP_1 = 1 +RASTER_CONFIG_SC_MAP_2 = 2 +RASTER_CONFIG_SC_MAP_3 = 3 +ScMap = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMode' +ScUncertaintyRegionMode__enumvalues = { + 0: 'SC_HALF_LSB', + 1: 'SC_LSB_ONE_SIDED', + 2: 'SC_LSB_TWO_SIDED', +} +SC_HALF_LSB = 0 +SC_LSB_ONE_SIDED = 1 +SC_LSB_TWO_SIDED = 2 +ScUncertaintyRegionMode = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMult' +ScUncertaintyRegionMult__enumvalues = { + 0: 'SC_UR_1X', + 1: 'SC_UR_2X', + 2: 'SC_UR_4X', + 3: 'SC_UR_8X', +} +SC_UR_1X = 0 +SC_UR_2X = 1 +SC_UR_4X = 2 +SC_UR_8X = 3 +ScUncertaintyRegionMult = ctypes.c_uint32 # enum + +# values for enumeration 'ScXsel' +ScXsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 +ScXsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScYsel' +ScYsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 +ScYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeMap' +SeMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_MAP_0', + 1: 'RASTER_CONFIG_SE_MAP_1', + 2: 'RASTER_CONFIG_SE_MAP_2', + 3: 'RASTER_CONFIG_SE_MAP_3', +} +RASTER_CONFIG_SE_MAP_0 = 0 +RASTER_CONFIG_SE_MAP_1 = 1 +RASTER_CONFIG_SE_MAP_2 = 2 +RASTER_CONFIG_SE_MAP_3 = 3 +SeMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairMap' +SePairMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', + 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', + 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', + 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', +} +RASTER_CONFIG_SE_PAIR_MAP_0 = 0 +RASTER_CONFIG_SE_PAIR_MAP_1 = 1 +RASTER_CONFIG_SE_PAIR_MAP_2 = 2 +RASTER_CONFIG_SE_PAIR_MAP_3 = 3 +SePairMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairXsel' +SePairXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 +SePairXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairYsel' +SePairYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 +SePairYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeXsel' +SeXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 +SeXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeYsel' +SeYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 +SeYsel = ctypes.c_uint32 # enum + +# values for enumeration 'VRSCombinerModeSC' +VRSCombinerModeSC__enumvalues = { + 0: 'SC_VRS_COMB_MODE_PASSTHRU', + 1: 'SC_VRS_COMB_MODE_OVERRIDE', + 2: 'SC_VRS_COMB_MODE_MIN', + 3: 'SC_VRS_COMB_MODE_MAX', + 4: 'SC_VRS_COMB_MODE_SATURATE', +} +SC_VRS_COMB_MODE_PASSTHRU = 0 +SC_VRS_COMB_MODE_OVERRIDE = 1 +SC_VRS_COMB_MODE_MIN = 2 +SC_VRS_COMB_MODE_MAX = 3 +SC_VRS_COMB_MODE_SATURATE = 4 +VRSCombinerModeSC = ctypes.c_uint32 # enum + +# values for enumeration 'VRSrate' +VRSrate__enumvalues = { + 0: 'VRS_SHADING_RATE_1X1', + 1: 'VRS_SHADING_RATE_1X2', + 2: 'VRS_SHADING_RATE_UNDEFINED0', + 3: 'VRS_SHADING_RATE_UNDEFINED1', + 4: 'VRS_SHADING_RATE_2X1', + 5: 'VRS_SHADING_RATE_2X2', + 6: 'VRS_SHADING_RATE_2X4', + 7: 'VRS_SHADING_RATE_UNDEFINED2', + 8: 'VRS_SHADING_RATE_UNDEFINED3', + 9: 'VRS_SHADING_RATE_4X2', + 10: 'VRS_SHADING_RATE_4X4', + 11: 'VRS_SHADING_RATE_UNDEFINED4', + 12: 'VRS_SHADING_RATE_16X_SSAA', + 13: 'VRS_SHADING_RATE_8X_SSAA', + 14: 'VRS_SHADING_RATE_4X_SSAA', + 15: 'VRS_SHADING_RATE_2X_SSAA', +} +VRS_SHADING_RATE_1X1 = 0 +VRS_SHADING_RATE_1X2 = 1 +VRS_SHADING_RATE_UNDEFINED0 = 2 +VRS_SHADING_RATE_UNDEFINED1 = 3 +VRS_SHADING_RATE_2X1 = 4 +VRS_SHADING_RATE_2X2 = 5 +VRS_SHADING_RATE_2X4 = 6 +VRS_SHADING_RATE_UNDEFINED2 = 7 +VRS_SHADING_RATE_UNDEFINED3 = 8 +VRS_SHADING_RATE_4X2 = 9 +VRS_SHADING_RATE_4X4 = 10 +VRS_SHADING_RATE_UNDEFINED4 = 11 +VRS_SHADING_RATE_16X_SSAA = 12 +VRS_SHADING_RATE_8X_SSAA = 13 +VRS_SHADING_RATE_4X_SSAA = 14 +VRS_SHADING_RATE_2X_SSAA = 15 +VRSrate = ctypes.c_uint32 # enum + +# values for enumeration 'TC_EA_CID' +TC_EA_CID__enumvalues = { + 0: 'TC_EA_CID_RT', + 1: 'TC_EA_CID_FMASK', + 2: 'TC_EA_CID_DCC', + 3: 'TC_EA_CID_TCPMETA', + 4: 'TC_EA_CID_Z', + 5: 'TC_EA_CID_STENCIL', + 6: 'TC_EA_CID_HTILE', + 7: 'TC_EA_CID_MISC', + 8: 'TC_EA_CID_TCP', + 9: 'TC_EA_CID_SQC', + 10: 'TC_EA_CID_CPF', + 11: 'TC_EA_CID_CPG', + 12: 'TC_EA_CID_IA', + 13: 'TC_EA_CID_WD', + 14: 'TC_EA_CID_PA', + 15: 'TC_EA_CID_UTCL2_TPI', +} +TC_EA_CID_RT = 0 +TC_EA_CID_FMASK = 1 +TC_EA_CID_DCC = 2 +TC_EA_CID_TCPMETA = 3 +TC_EA_CID_Z = 4 +TC_EA_CID_STENCIL = 5 +TC_EA_CID_HTILE = 6 +TC_EA_CID_MISC = 7 +TC_EA_CID_TCP = 8 +TC_EA_CID_SQC = 9 +TC_EA_CID_CPF = 10 +TC_EA_CID_CPG = 11 +TC_EA_CID_IA = 12 +TC_EA_CID_WD = 13 +TC_EA_CID_PA = 14 +TC_EA_CID_UTCL2_TPI = 15 +TC_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'TC_NACKS' +TC_NACKS__enumvalues = { + 0: 'TC_NACK_NO_FAULT', + 1: 'TC_NACK_PAGE_FAULT', + 2: 'TC_NACK_PROTECTION_FAULT', + 3: 'TC_NACK_DATA_ERROR', +} +TC_NACK_NO_FAULT = 0 +TC_NACK_PAGE_FAULT = 1 +TC_NACK_PROTECTION_FAULT = 2 +TC_NACK_DATA_ERROR = 3 +TC_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP' +TC_OP__enumvalues = { + 0: 'TC_OP_READ', + 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'TC_OP_ATOMIC_FMIN_RTN_32', + 3: 'TC_OP_ATOMIC_FMAX_RTN_32', + 4: 'TC_OP_RESERVED_FOP_RTN_32_0', + 5: 'TC_OP_RESERVED_FADD_RTN_32', + 6: 'TC_OP_RESERVED_FOP_RTN_32_2', + 7: 'TC_OP_ATOMIC_SWAP_RTN_32', + 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'TC_OP_PROBE_FILTER', + 13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'TC_OP_ATOMIC_ADD_RTN_32', + 16: 'TC_OP_ATOMIC_SUB_RTN_32', + 17: 'TC_OP_ATOMIC_SMIN_RTN_32', + 18: 'TC_OP_ATOMIC_UMIN_RTN_32', + 19: 'TC_OP_ATOMIC_SMAX_RTN_32', + 20: 'TC_OP_ATOMIC_UMAX_RTN_32', + 21: 'TC_OP_ATOMIC_AND_RTN_32', + 22: 'TC_OP_ATOMIC_OR_RTN_32', + 23: 'TC_OP_ATOMIC_XOR_RTN_32', + 24: 'TC_OP_ATOMIC_INC_RTN_32', + 25: 'TC_OP_ATOMIC_DEC_RTN_32', + 26: 'TC_OP_WBINVL1_VOL', + 27: 'TC_OP_WBINVL1_SD', + 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 32: 'TC_OP_WRITE', + 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'TC_OP_ATOMIC_FMIN_RTN_64', + 35: 'TC_OP_ATOMIC_FMAX_RTN_64', + 36: 'TC_OP_RESERVED_FOP_RTN_64_0', + 37: 'TC_OP_RESERVED_FOP_RTN_64_1', + 38: 'TC_OP_RESERVED_FOP_RTN_64_2', + 39: 'TC_OP_ATOMIC_SWAP_RTN_64', + 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 44: 'TC_OP_WBINVL2_SD', + 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 47: 'TC_OP_ATOMIC_ADD_RTN_64', + 48: 'TC_OP_ATOMIC_SUB_RTN_64', + 49: 'TC_OP_ATOMIC_SMIN_RTN_64', + 50: 'TC_OP_ATOMIC_UMIN_RTN_64', + 51: 'TC_OP_ATOMIC_SMAX_RTN_64', + 52: 'TC_OP_ATOMIC_UMAX_RTN_64', + 53: 'TC_OP_ATOMIC_AND_RTN_64', + 54: 'TC_OP_ATOMIC_OR_RTN_64', + 55: 'TC_OP_ATOMIC_XOR_RTN_64', + 56: 'TC_OP_ATOMIC_INC_RTN_64', + 57: 'TC_OP_ATOMIC_DEC_RTN_64', + 58: 'TC_OP_WBL2_NC', + 59: 'TC_OP_WBL2_WC', + 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', + 64: 'TC_OP_WBINVL1', + 65: 'TC_OP_ATOMIC_FCMPSWAP_32', + 66: 'TC_OP_ATOMIC_FMIN_32', + 67: 'TC_OP_ATOMIC_FMAX_32', + 68: 'TC_OP_RESERVED_FOP_32_0', + 69: 'TC_OP_RESERVED_FADD_32', + 70: 'TC_OP_RESERVED_FOP_32_2', + 71: 'TC_OP_ATOMIC_SWAP_32', + 72: 'TC_OP_ATOMIC_CMPSWAP_32', + 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'TC_OP_INV_METADATA', + 77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 79: 'TC_OP_ATOMIC_ADD_32', + 80: 'TC_OP_ATOMIC_SUB_32', + 81: 'TC_OP_ATOMIC_SMIN_32', + 82: 'TC_OP_ATOMIC_UMIN_32', + 83: 'TC_OP_ATOMIC_SMAX_32', + 84: 'TC_OP_ATOMIC_UMAX_32', + 85: 'TC_OP_ATOMIC_AND_32', + 86: 'TC_OP_ATOMIC_OR_32', + 87: 'TC_OP_ATOMIC_XOR_32', + 88: 'TC_OP_ATOMIC_INC_32', + 89: 'TC_OP_ATOMIC_DEC_32', + 90: 'TC_OP_INVL2_NC', + 91: 'TC_OP_NOP_RTN0', + 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', + 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', + 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', + 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', + 96: 'TC_OP_WBINVL2', + 97: 'TC_OP_ATOMIC_FCMPSWAP_64', + 98: 'TC_OP_ATOMIC_FMIN_64', + 99: 'TC_OP_ATOMIC_FMAX_64', + 100: 'TC_OP_RESERVED_FOP_64_0', + 101: 'TC_OP_RESERVED_FOP_64_1', + 102: 'TC_OP_RESERVED_FOP_64_2', + 103: 'TC_OP_ATOMIC_SWAP_64', + 104: 'TC_OP_ATOMIC_CMPSWAP_64', + 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 111: 'TC_OP_ATOMIC_ADD_64', + 112: 'TC_OP_ATOMIC_SUB_64', + 113: 'TC_OP_ATOMIC_SMIN_64', + 114: 'TC_OP_ATOMIC_UMIN_64', + 115: 'TC_OP_ATOMIC_SMAX_64', + 116: 'TC_OP_ATOMIC_UMAX_64', + 117: 'TC_OP_ATOMIC_AND_64', + 118: 'TC_OP_ATOMIC_OR_64', + 119: 'TC_OP_ATOMIC_XOR_64', + 120: 'TC_OP_ATOMIC_INC_64', + 121: 'TC_OP_ATOMIC_DEC_64', + 122: 'TC_OP_WBINVL2_NC', + 123: 'TC_OP_NOP_ACK', + 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', + 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', + 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', + 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', +} +TC_OP_READ = 0 +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +TC_OP_ATOMIC_FMIN_RTN_32 = 2 +TC_OP_ATOMIC_FMAX_RTN_32 = 3 +TC_OP_RESERVED_FOP_RTN_32_0 = 4 +TC_OP_RESERVED_FADD_RTN_32 = 5 +TC_OP_RESERVED_FOP_RTN_32_2 = 6 +TC_OP_ATOMIC_SWAP_RTN_32 = 7 +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +TC_OP_PROBE_FILTER = 12 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +TC_OP_ATOMIC_ADD_RTN_32 = 15 +TC_OP_ATOMIC_SUB_RTN_32 = 16 +TC_OP_ATOMIC_SMIN_RTN_32 = 17 +TC_OP_ATOMIC_UMIN_RTN_32 = 18 +TC_OP_ATOMIC_SMAX_RTN_32 = 19 +TC_OP_ATOMIC_UMAX_RTN_32 = 20 +TC_OP_ATOMIC_AND_RTN_32 = 21 +TC_OP_ATOMIC_OR_RTN_32 = 22 +TC_OP_ATOMIC_XOR_RTN_32 = 23 +TC_OP_ATOMIC_INC_RTN_32 = 24 +TC_OP_ATOMIC_DEC_RTN_32 = 25 +TC_OP_WBINVL1_VOL = 26 +TC_OP_WBINVL1_SD = 27 +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 +TC_OP_WRITE = 32 +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +TC_OP_ATOMIC_FMIN_RTN_64 = 34 +TC_OP_ATOMIC_FMAX_RTN_64 = 35 +TC_OP_RESERVED_FOP_RTN_64_0 = 36 +TC_OP_RESERVED_FOP_RTN_64_1 = 37 +TC_OP_RESERVED_FOP_RTN_64_2 = 38 +TC_OP_ATOMIC_SWAP_RTN_64 = 39 +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +TC_OP_WBINVL2_SD = 44 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 +TC_OP_ATOMIC_ADD_RTN_64 = 47 +TC_OP_ATOMIC_SUB_RTN_64 = 48 +TC_OP_ATOMIC_SMIN_RTN_64 = 49 +TC_OP_ATOMIC_UMIN_RTN_64 = 50 +TC_OP_ATOMIC_SMAX_RTN_64 = 51 +TC_OP_ATOMIC_UMAX_RTN_64 = 52 +TC_OP_ATOMIC_AND_RTN_64 = 53 +TC_OP_ATOMIC_OR_RTN_64 = 54 +TC_OP_ATOMIC_XOR_RTN_64 = 55 +TC_OP_ATOMIC_INC_RTN_64 = 56 +TC_OP_ATOMIC_DEC_RTN_64 = 57 +TC_OP_WBL2_NC = 58 +TC_OP_WBL2_WC = 59 +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 +TC_OP_WBINVL1 = 64 +TC_OP_ATOMIC_FCMPSWAP_32 = 65 +TC_OP_ATOMIC_FMIN_32 = 66 +TC_OP_ATOMIC_FMAX_32 = 67 +TC_OP_RESERVED_FOP_32_0 = 68 +TC_OP_RESERVED_FADD_32 = 69 +TC_OP_RESERVED_FOP_32_2 = 70 +TC_OP_ATOMIC_SWAP_32 = 71 +TC_OP_ATOMIC_CMPSWAP_32 = 72 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +TC_OP_INV_METADATA = 76 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 +TC_OP_ATOMIC_ADD_32 = 79 +TC_OP_ATOMIC_SUB_32 = 80 +TC_OP_ATOMIC_SMIN_32 = 81 +TC_OP_ATOMIC_UMIN_32 = 82 +TC_OP_ATOMIC_SMAX_32 = 83 +TC_OP_ATOMIC_UMAX_32 = 84 +TC_OP_ATOMIC_AND_32 = 85 +TC_OP_ATOMIC_OR_32 = 86 +TC_OP_ATOMIC_XOR_32 = 87 +TC_OP_ATOMIC_INC_32 = 88 +TC_OP_ATOMIC_DEC_32 = 89 +TC_OP_INVL2_NC = 90 +TC_OP_NOP_RTN0 = 91 +TC_OP_RESERVED_NON_FLOAT_32_1 = 92 +TC_OP_RESERVED_NON_FLOAT_32_2 = 93 +TC_OP_RESERVED_NON_FLOAT_32_3 = 94 +TC_OP_RESERVED_NON_FLOAT_32_4 = 95 +TC_OP_WBINVL2 = 96 +TC_OP_ATOMIC_FCMPSWAP_64 = 97 +TC_OP_ATOMIC_FMIN_64 = 98 +TC_OP_ATOMIC_FMAX_64 = 99 +TC_OP_RESERVED_FOP_64_0 = 100 +TC_OP_RESERVED_FOP_64_1 = 101 +TC_OP_RESERVED_FOP_64_2 = 102 +TC_OP_ATOMIC_SWAP_64 = 103 +TC_OP_ATOMIC_CMPSWAP_64 = 104 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 +TC_OP_ATOMIC_ADD_64 = 111 +TC_OP_ATOMIC_SUB_64 = 112 +TC_OP_ATOMIC_SMIN_64 = 113 +TC_OP_ATOMIC_UMIN_64 = 114 +TC_OP_ATOMIC_SMAX_64 = 115 +TC_OP_ATOMIC_UMAX_64 = 116 +TC_OP_ATOMIC_AND_64 = 117 +TC_OP_ATOMIC_OR_64 = 118 +TC_OP_ATOMIC_XOR_64 = 119 +TC_OP_ATOMIC_INC_64 = 120 +TC_OP_ATOMIC_DEC_64 = 121 +TC_OP_WBINVL2_NC = 122 +TC_OP_NOP_ACK = 123 +TC_OP_RESERVED_NON_FLOAT_64_1 = 124 +TC_OP_RESERVED_NON_FLOAT_64_2 = 125 +TC_OP_RESERVED_NON_FLOAT_64_3 = 126 +TC_OP_RESERVED_NON_FLOAT_64_4 = 127 +TC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP_MASKS' +TC_OP_MASKS__enumvalues = { + 8: 'TC_OP_MASK_FLUSH_DENROM', + 32: 'TC_OP_MASK_64', + 64: 'TC_OP_MASK_NO_RTN', +} +TC_OP_MASK_FLUSH_DENROM = 8 +TC_OP_MASK_64 = 32 +TC_OP_MASK_NO_RTN = 64 +TC_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_EA_CID' +GL2_EA_CID__enumvalues = { + 0: 'GL2_EA_CID_CLIENT', + 1: 'GL2_EA_CID_SDMA', + 2: 'GL2_EA_CID_RLC', + 3: 'GL2_EA_CID_SQC', + 4: 'GL2_EA_CID_CP', + 5: 'GL2_EA_CID_CPDMA', + 6: 'GL2_EA_CID_UTCL2', + 7: 'GL2_EA_CID_RT', + 8: 'GL2_EA_CID_FMASK', + 9: 'GL2_EA_CID_DCC', + 10: 'GL2_EA_CID_Z_STENCIL', + 11: 'GL2_EA_CID_ZPCPSD', + 12: 'GL2_EA_CID_HTILE', + 13: 'GL2_EA_CID_MES', + 15: 'GL2_EA_CID_TCPMETA', +} +GL2_EA_CID_CLIENT = 0 +GL2_EA_CID_SDMA = 1 +GL2_EA_CID_RLC = 2 +GL2_EA_CID_SQC = 3 +GL2_EA_CID_CP = 4 +GL2_EA_CID_CPDMA = 5 +GL2_EA_CID_UTCL2 = 6 +GL2_EA_CID_RT = 7 +GL2_EA_CID_FMASK = 8 +GL2_EA_CID_DCC = 9 +GL2_EA_CID_Z_STENCIL = 10 +GL2_EA_CID_ZPCPSD = 11 +GL2_EA_CID_HTILE = 12 +GL2_EA_CID_MES = 13 +GL2_EA_CID_TCPMETA = 15 +GL2_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_NACKS' +GL2_NACKS__enumvalues = { + 0: 'GL2_NACK_NO_FAULT', + 1: 'GL2_NACK_PAGE_FAULT', + 2: 'GL2_NACK_PROTECTION_FAULT', + 3: 'GL2_NACK_DATA_ERROR', +} +GL2_NACK_NO_FAULT = 0 +GL2_NACK_PAGE_FAULT = 1 +GL2_NACK_PROTECTION_FAULT = 2 +GL2_NACK_DATA_ERROR = 3 +GL2_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP' +GL2_OP__enumvalues = { + 0: 'GL2_OP_READ', + 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', + 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', + 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', + 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'GL2_OP_PROBE_FILTER', + 13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'GL2_OP_ATOMIC_ADD_RTN_32', + 16: 'GL2_OP_ATOMIC_SUB_RTN_32', + 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', + 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', + 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', + 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', + 21: 'GL2_OP_ATOMIC_AND_RTN_32', + 22: 'GL2_OP_ATOMIC_OR_RTN_32', + 23: 'GL2_OP_ATOMIC_XOR_RTN_32', + 24: 'GL2_OP_ATOMIC_INC_RTN_32', + 25: 'GL2_OP_ATOMIC_DEC_RTN_32', + 26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 32: 'GL2_OP_WRITE', + 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', + 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', + 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', + 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 47: 'GL2_OP_ATOMIC_ADD_RTN_64', + 48: 'GL2_OP_ATOMIC_SUB_RTN_64', + 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', + 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', + 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', + 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', + 53: 'GL2_OP_ATOMIC_AND_RTN_64', + 54: 'GL2_OP_ATOMIC_OR_RTN_64', + 55: 'GL2_OP_ATOMIC_XOR_RTN_64', + 56: 'GL2_OP_ATOMIC_INC_RTN_64', + 57: 'GL2_OP_ATOMIC_DEC_RTN_64', + 64: 'GL2_OP_GL1_INV', + 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', + 66: 'GL2_OP_ATOMIC_FMIN_32', + 67: 'GL2_OP_ATOMIC_FMAX_32', + 71: 'GL2_OP_ATOMIC_SWAP_32', + 72: 'GL2_OP_ATOMIC_CMPSWAP_32', + 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'GL2_OP_ATOMIC_UMIN_8', + 77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 79: 'GL2_OP_ATOMIC_ADD_32', + 80: 'GL2_OP_ATOMIC_SUB_32', + 81: 'GL2_OP_ATOMIC_SMIN_32', + 82: 'GL2_OP_ATOMIC_UMIN_32', + 83: 'GL2_OP_ATOMIC_SMAX_32', + 84: 'GL2_OP_ATOMIC_UMAX_32', + 85: 'GL2_OP_ATOMIC_AND_32', + 86: 'GL2_OP_ATOMIC_OR_32', + 87: 'GL2_OP_ATOMIC_XOR_32', + 88: 'GL2_OP_ATOMIC_INC_32', + 89: 'GL2_OP_ATOMIC_DEC_32', + 91: 'GL2_OP_NOP_RTN0', + 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', + 98: 'GL2_OP_ATOMIC_FMIN_64', + 99: 'GL2_OP_ATOMIC_FMAX_64', + 103: 'GL2_OP_ATOMIC_SWAP_64', + 104: 'GL2_OP_ATOMIC_CMPSWAP_64', + 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 111: 'GL2_OP_ATOMIC_ADD_64', + 112: 'GL2_OP_ATOMIC_SUB_64', + 113: 'GL2_OP_ATOMIC_SMIN_64', + 114: 'GL2_OP_ATOMIC_UMIN_64', + 115: 'GL2_OP_ATOMIC_SMAX_64', + 116: 'GL2_OP_ATOMIC_UMAX_64', + 117: 'GL2_OP_ATOMIC_AND_64', + 118: 'GL2_OP_ATOMIC_OR_64', + 119: 'GL2_OP_ATOMIC_XOR_64', + 120: 'GL2_OP_ATOMIC_INC_64', + 121: 'GL2_OP_ATOMIC_DEC_64', + 122: 'GL2_OP_ATOMIC_UMAX_8', + 123: 'GL2_OP_NOP_ACK', +} +GL2_OP_READ = 0 +GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +GL2_OP_ATOMIC_FMIN_RTN_32 = 2 +GL2_OP_ATOMIC_FMAX_RTN_32 = 3 +GL2_OP_ATOMIC_SWAP_RTN_32 = 7 +GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +GL2_OP_PROBE_FILTER = 12 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +GL2_OP_ATOMIC_ADD_RTN_32 = 15 +GL2_OP_ATOMIC_SUB_RTN_32 = 16 +GL2_OP_ATOMIC_SMIN_RTN_32 = 17 +GL2_OP_ATOMIC_UMIN_RTN_32 = 18 +GL2_OP_ATOMIC_SMAX_RTN_32 = 19 +GL2_OP_ATOMIC_UMAX_RTN_32 = 20 +GL2_OP_ATOMIC_AND_RTN_32 = 21 +GL2_OP_ATOMIC_OR_RTN_32 = 22 +GL2_OP_ATOMIC_XOR_RTN_32 = 23 +GL2_OP_ATOMIC_INC_RTN_32 = 24 +GL2_OP_ATOMIC_DEC_RTN_32 = 25 +GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26 +GL2_OP_WRITE = 32 +GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +GL2_OP_ATOMIC_FMIN_RTN_64 = 34 +GL2_OP_ATOMIC_FMAX_RTN_64 = 35 +GL2_OP_ATOMIC_SWAP_RTN_64 = 39 +GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +GL2_OP_ATOMIC_ADD_RTN_64 = 47 +GL2_OP_ATOMIC_SUB_RTN_64 = 48 +GL2_OP_ATOMIC_SMIN_RTN_64 = 49 +GL2_OP_ATOMIC_UMIN_RTN_64 = 50 +GL2_OP_ATOMIC_SMAX_RTN_64 = 51 +GL2_OP_ATOMIC_UMAX_RTN_64 = 52 +GL2_OP_ATOMIC_AND_RTN_64 = 53 +GL2_OP_ATOMIC_OR_RTN_64 = 54 +GL2_OP_ATOMIC_XOR_RTN_64 = 55 +GL2_OP_ATOMIC_INC_RTN_64 = 56 +GL2_OP_ATOMIC_DEC_RTN_64 = 57 +GL2_OP_GL1_INV = 64 +GL2_OP_ATOMIC_FCMPSWAP_32 = 65 +GL2_OP_ATOMIC_FMIN_32 = 66 +GL2_OP_ATOMIC_FMAX_32 = 67 +GL2_OP_ATOMIC_SWAP_32 = 71 +GL2_OP_ATOMIC_CMPSWAP_32 = 72 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +GL2_OP_ATOMIC_UMIN_8 = 76 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +GL2_OP_ATOMIC_ADD_32 = 79 +GL2_OP_ATOMIC_SUB_32 = 80 +GL2_OP_ATOMIC_SMIN_32 = 81 +GL2_OP_ATOMIC_UMIN_32 = 82 +GL2_OP_ATOMIC_SMAX_32 = 83 +GL2_OP_ATOMIC_UMAX_32 = 84 +GL2_OP_ATOMIC_AND_32 = 85 +GL2_OP_ATOMIC_OR_32 = 86 +GL2_OP_ATOMIC_XOR_32 = 87 +GL2_OP_ATOMIC_INC_32 = 88 +GL2_OP_ATOMIC_DEC_32 = 89 +GL2_OP_NOP_RTN0 = 91 +GL2_OP_ATOMIC_FCMPSWAP_64 = 97 +GL2_OP_ATOMIC_FMIN_64 = 98 +GL2_OP_ATOMIC_FMAX_64 = 99 +GL2_OP_ATOMIC_SWAP_64 = 103 +GL2_OP_ATOMIC_CMPSWAP_64 = 104 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +GL2_OP_ATOMIC_ADD_64 = 111 +GL2_OP_ATOMIC_SUB_64 = 112 +GL2_OP_ATOMIC_SMIN_64 = 113 +GL2_OP_ATOMIC_UMIN_64 = 114 +GL2_OP_ATOMIC_SMAX_64 = 115 +GL2_OP_ATOMIC_UMAX_64 = 116 +GL2_OP_ATOMIC_AND_64 = 117 +GL2_OP_ATOMIC_OR_64 = 118 +GL2_OP_ATOMIC_XOR_64 = 119 +GL2_OP_ATOMIC_INC_64 = 120 +GL2_OP_ATOMIC_DEC_64 = 121 +GL2_OP_ATOMIC_UMAX_8 = 122 +GL2_OP_NOP_ACK = 123 +GL2_OP = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP_MASKS' +GL2_OP_MASKS__enumvalues = { + 8: 'GL2_OP_MASK_FLUSH_DENROM', + 32: 'GL2_OP_MASK_64', + 64: 'GL2_OP_MASK_NO_RTN', +} +GL2_OP_MASK_FLUSH_DENROM = 8 +GL2_OP_MASK_64 = 32 +GL2_OP_MASK_NO_RTN = 64 +GL2_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_DOORBELL_MODE' +RLC_DOORBELL_MODE__enumvalues = { + 0: 'RLC_DOORBELL_MODE_DISABLE', + 1: 'RLC_DOORBELL_MODE_ENABLE', + 2: 'RLC_DOORBELL_MODE_ENABLE_PF', + 3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF', +} +RLC_DOORBELL_MODE_DISABLE = 0 +RLC_DOORBELL_MODE_ENABLE = 1 +RLC_DOORBELL_MODE_ENABLE_PF = 2 +RLC_DOORBELL_MODE_ENABLE_PF_VF = 3 +RLC_DOORBELL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFCOUNTER_SEL' +RLC_PERFCOUNTER_SEL__enumvalues = { + 0: 'RLC_PERF_SEL_POWER_FEATURE_0', + 1: 'RLC_PERF_SEL_POWER_FEATURE_1', + 2: 'RLC_PERF_SEL_CP_INTERRUPT', + 3: 'RLC_PERF_SEL_GRBM_INTERRUPT', + 4: 'RLC_PERF_SEL_SPM_INTERRUPT', + 5: 'RLC_PERF_SEL_IH_INTERRUPT', + 6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', +} +RLC_PERF_SEL_POWER_FEATURE_0 = 0 +RLC_PERF_SEL_POWER_FEATURE_1 = 1 +RLC_PERF_SEL_CP_INTERRUPT = 2 +RLC_PERF_SEL_GRBM_INTERRUPT = 3 +RLC_PERF_SEL_SPM_INTERRUPT = 4 +RLC_PERF_SEL_IH_INTERRUPT = 5 +RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6 +RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFMON_STATE' +RLC_PERFMON_STATE__enumvalues = { + 0: 'RLC_PERFMON_STATE_RESET', + 1: 'RLC_PERFMON_STATE_ENABLE', + 2: 'RLC_PERFMON_STATE_DISABLE', + 3: 'RLC_PERFMON_STATE_RESERVED_3', + 4: 'RLC_PERFMON_STATE_RESERVED_4', + 5: 'RLC_PERFMON_STATE_RESERVED_5', + 6: 'RLC_PERFMON_STATE_RESERVED_6', + 7: 'RLC_PERFMON_STATE_ROLLOVER', +} +RLC_PERFMON_STATE_RESET = 0 +RLC_PERFMON_STATE_ENABLE = 1 +RLC_PERFMON_STATE_DISABLE = 2 +RLC_PERFMON_STATE_RESERVED_3 = 3 +RLC_PERFMON_STATE_RESERVED_4 = 4 +RLC_PERFMON_STATE_RESERVED_5 = 5 +RLC_PERFMON_STATE_RESERVED_6 = 6 +RLC_PERFMON_STATE_ROLLOVER = 7 +RLC_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RSPM_CMD' +RSPM_CMD__enumvalues = { + 0: 'RSPM_CMD_INVALID', + 1: 'RSPM_CMD_IDLE', + 2: 'RSPM_CMD_CALIBRATE', + 3: 'RSPM_CMD_SPM_RESET', + 4: 'RSPM_CMD_SPM_START', + 5: 'RSPM_CMD_SPM_STOP', + 6: 'RSPM_CMD_PERF_RESET', + 7: 'RSPM_CMD_PERF_SAMPLE', + 8: 'RSPM_CMD_PROF_START', + 9: 'RSPM_CMD_PROF_STOP', + 10: 'RSPM_CMD_FORCE_SAMPLE', +} +RSPM_CMD_INVALID = 0 +RSPM_CMD_IDLE = 1 +RSPM_CMD_CALIBRATE = 2 +RSPM_CMD_SPM_RESET = 3 +RSPM_CMD_SPM_START = 4 +RSPM_CMD_SPM_STOP = 5 +RSPM_CMD_PERF_RESET = 6 +RSPM_CMD_PERF_SAMPLE = 7 +RSPM_CMD_PROF_START = 8 +RSPM_CMD_PROF_STOP = 9 +RSPM_CMD_FORCE_SAMPLE = 10 +RSPM_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_BASE_MODE' +CLKGATE_BASE_MODE__enumvalues = { + 0: 'MULT_8', + 1: 'MULT_16', +} +MULT_8 = 0 +MULT_16 = 1 +CLKGATE_BASE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_SM_MODE' +CLKGATE_SM_MODE__enumvalues = { + 0: 'ON_SEQ', + 1: 'OFF_SEQ', + 2: 'PROG_SEQ', + 3: 'READ_SEQ', + 4: 'SM_MODE_RESERVED', +} +ON_SEQ = 0 +OFF_SEQ = 1 +PROG_SEQ = 2 +READ_SEQ = 3 +SM_MODE_RESERVED = 4 +CLKGATE_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_FOG_MODE' +SPI_FOG_MODE__enumvalues = { + 0: 'SPI_FOG_NONE', + 1: 'SPI_FOG_EXP', + 2: 'SPI_FOG_EXP2', + 3: 'SPI_FOG_LINEAR', +} +SPI_FOG_NONE = 0 +SPI_FOG_EXP = 1 +SPI_FOG_EXP2 = 2 +SPI_FOG_LINEAR = 3 +SPI_FOG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_LB_WAVES_SELECT' +SPI_LB_WAVES_SELECT__enumvalues = { + 0: 'HS_GS', + 1: 'PS', + 2: 'CS_NA', + 3: 'SPI_LB_WAVES_RSVD', +} +HS_GS = 0 +PS = 1 +CS_NA = 2 +SPI_LB_WAVES_RSVD = 3 +SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PERFCNT_SEL' +SPI_PERFCNT_SEL__enumvalues = { + 1: 'SPI_PERF_GS_WINDOW_VALID', + 2: 'SPI_PERF_GS_BUSY', + 3: 'SPI_PERF_GS_CRAWLER_STALL', + 4: 'SPI_PERF_GS_EVENT_WAVE', + 5: 'SPI_PERF_GS_WAVE', + 6: 'SPI_PERF_GS_PERS_UPD_FULL0', + 7: 'SPI_PERF_GS_PERS_UPD_FULL1', + 8: 'SPI_PERF_GS_FIRST_SUBGRP', + 9: 'SPI_PERF_GS_HS_DEALLOC', + 10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 11: 'SPI_PERF_GS_POS0_STALL', + 12: 'SPI_PERF_GS_POS1_STALL', + 13: 'SPI_PERF_GS_INDX0_STALL', + 14: 'SPI_PERF_GS_INDX1_STALL', + 15: 'SPI_PERF_GS_PWS_STALL', + 21: 'SPI_PERF_HS_WINDOW_VALID', + 22: 'SPI_PERF_HS_BUSY', + 23: 'SPI_PERF_HS_CRAWLER_STALL', + 24: 'SPI_PERF_HS_FIRST_WAVE', + 25: 'SPI_PERF_HS_OFFCHIP_LDS_STALL', + 26: 'SPI_PERF_HS_EVENT_WAVE', + 27: 'SPI_PERF_HS_WAVE', + 28: 'SPI_PERF_HS_PERS_UPD_FULL0', + 29: 'SPI_PERF_HS_PERS_UPD_FULL1', + 30: 'SPI_PERF_HS_PWS_STALL', + 37: 'SPI_PERF_CSGN_WINDOW_VALID', + 38: 'SPI_PERF_CSGN_BUSY', + 39: 'SPI_PERF_CSGN_NUM_THREADGROUPS', + 40: 'SPI_PERF_CSGN_CRAWLER_STALL', + 41: 'SPI_PERF_CSGN_EVENT_WAVE', + 42: 'SPI_PERF_CSGN_WAVE', + 43: 'SPI_PERF_CSGN_PWS_STALL', + 44: 'SPI_PERF_CSN_WINDOW_VALID', + 45: 'SPI_PERF_CSN_BUSY', + 46: 'SPI_PERF_CSN_NUM_THREADGROUPS', + 47: 'SPI_PERF_CSN_CRAWLER_STALL', + 48: 'SPI_PERF_CSN_EVENT_WAVE', + 49: 'SPI_PERF_CSN_WAVE', + 53: 'SPI_PERF_PS0_WINDOW_VALID', + 54: 'SPI_PERF_PS1_WINDOW_VALID', + 55: 'SPI_PERF_PS2_WINDOW_VALID', + 56: 'SPI_PERF_PS3_WINDOW_VALID', + 57: 'SPI_PERF_PS0_BUSY', + 58: 'SPI_PERF_PS1_BUSY', + 59: 'SPI_PERF_PS2_BUSY', + 60: 'SPI_PERF_PS3_BUSY', + 61: 'SPI_PERF_PS0_ACTIVE', + 62: 'SPI_PERF_PS1_ACTIVE', + 63: 'SPI_PERF_PS2_ACTIVE', + 64: 'SPI_PERF_PS3_ACTIVE', + 65: 'SPI_PERF_PS0_DEALLOC', + 66: 'SPI_PERF_PS1_DEALLOC', + 67: 'SPI_PERF_PS2_DEALLOC', + 68: 'SPI_PERF_PS3_DEALLOC', + 69: 'SPI_PERF_PS0_EVENT_WAVE', + 70: 'SPI_PERF_PS1_EVENT_WAVE', + 71: 'SPI_PERF_PS2_EVENT_WAVE', + 72: 'SPI_PERF_PS3_EVENT_WAVE', + 73: 'SPI_PERF_PS0_WAVE', + 74: 'SPI_PERF_PS1_WAVE', + 75: 'SPI_PERF_PS2_WAVE', + 76: 'SPI_PERF_PS3_WAVE', + 77: 'SPI_PERF_PS0_OPT_WAVE', + 78: 'SPI_PERF_PS1_OPT_WAVE', + 79: 'SPI_PERF_PS2_OPT_WAVE', + 80: 'SPI_PERF_PS3_OPT_WAVE', + 81: 'SPI_PERF_PS0_PRIM_BIN0', + 82: 'SPI_PERF_PS1_PRIM_BIN0', + 83: 'SPI_PERF_PS2_PRIM_BIN0', + 84: 'SPI_PERF_PS3_PRIM_BIN0', + 85: 'SPI_PERF_PS0_PRIM_BIN1', + 86: 'SPI_PERF_PS1_PRIM_BIN1', + 87: 'SPI_PERF_PS2_PRIM_BIN1', + 88: 'SPI_PERF_PS3_PRIM_BIN1', + 89: 'SPI_PERF_PS0_CRAWLER_STALL', + 90: 'SPI_PERF_PS1_CRAWLER_STALL', + 91: 'SPI_PERF_PS2_CRAWLER_STALL', + 92: 'SPI_PERF_PS3_CRAWLER_STALL', + 93: 'SPI_PERF_PS_PERS_UPD_FULL0', + 94: 'SPI_PERF_PS_PERS_UPD_FULL1', + 95: 'SPI_PERF_PS0_2_WAVE_GROUPS', + 96: 'SPI_PERF_PS1_2_WAVE_GROUPS', + 97: 'SPI_PERF_PS2_2_WAVE_GROUPS', + 98: 'SPI_PERF_PS3_2_WAVE_GROUPS', + 99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', + 104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', + 105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', + 106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', + 107: 'SPI_PERF_PS_PWS_STALL', + 141: 'SPI_PERF_RA_PIPE_REQ_BIN2', + 142: 'SPI_PERF_RA_TASK_REQ_BIN3', + 143: 'SPI_PERF_RA_WR_CTL_FULL', + 144: 'SPI_PERF_RA_REQ_NO_ALLOC', + 145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 150: 'SPI_PERF_RA_RES_STALL_PS', + 151: 'SPI_PERF_RA_RES_STALL_GS', + 152: 'SPI_PERF_RA_RES_STALL_HS', + 153: 'SPI_PERF_RA_RES_STALL_CSG', + 154: 'SPI_PERF_RA_RES_STALL_CSN', + 155: 'SPI_PERF_RA_TMP_STALL_PS', + 156: 'SPI_PERF_RA_TMP_STALL_GS', + 157: 'SPI_PERF_RA_TMP_STALL_HS', + 158: 'SPI_PERF_RA_TMP_STALL_CSG', + 159: 'SPI_PERF_RA_TMP_STALL_CSN', + 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', + 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', + 170: 'SPI_PERF_RA_LDS_CU_FULL_PS', + 171: 'SPI_PERF_RA_LDS_CU_FULL_HS', + 172: 'SPI_PERF_RA_LDS_CU_FULL_GS', + 173: 'SPI_PERF_RA_LDS_CU_FULL_CSG', + 174: 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 175: 'SPI_PERF_RA_BAR_CU_FULL_HS', + 176: 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 177: 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 178: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 179: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 180: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', + 181: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 182: 'SPI_PERF_RA_WVLIM_STALL_PS', + 183: 'SPI_PERF_RA_WVLIM_STALL_GS', + 184: 'SPI_PERF_RA_WVLIM_STALL_HS', + 185: 'SPI_PERF_RA_WVLIM_STALL_CSG', + 186: 'SPI_PERF_RA_WVLIM_STALL_CSN', + 187: 'SPI_PERF_RA_GS_LOCK', + 188: 'SPI_PERF_RA_HS_LOCK', + 189: 'SPI_PERF_RA_CSG_LOCK', + 190: 'SPI_PERF_RA_CSN_LOCK', + 191: 'SPI_PERF_RA_RSV_UPD', + 192: 'SPI_PERF_RA_PRE_ALLOC_STALL', + 193: 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 194: 'SPI_PERF_RA_CSC_UNDER_TUNNEL', + 195: 'SPI_PERF_RA_WVALLOC_STALL', + 196: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 197: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 198: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 199: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', + 200: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 201: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 202: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 203: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 204: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 205: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 206: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 207: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 208: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 209: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 210: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 211: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 212: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 213: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 214: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 215: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 216: 'SPI_PERF_EXP_ARB_COL_CNT', + 217: 'SPI_PERF_EXP_ARB_POS_CNT', + 218: 'SPI_PERF_EXP_ARB_GDS_CNT', + 219: 'SPI_PERF_EXP_ARB_IDX_CNT', + 220: 'SPI_PERF_EXP_WITH_CONFLICT', + 221: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 222: 'SPI_PERF_GS_EXP_DONE', + 223: 'SPI_PERF_PS_EXP_DONE', + 224: 'SPI_PERF_PS_EXP_ARB_CONFLICT', + 225: 'SPI_PERF_PS_EXP_ALLOC', + 226: 'SPI_PERF_PS0_WAVEID_STARVED', + 227: 'SPI_PERF_PS1_WAVEID_STARVED', + 228: 'SPI_PERF_PS2_WAVEID_STARVED', + 229: 'SPI_PERF_PS3_WAVEID_STARVED', + 230: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 231: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', + 232: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', + 233: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', + 234: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 235: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 236: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 237: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 238: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 239: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 240: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 241: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 242: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 243: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 244: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 245: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 246: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 253: 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 254: 'SPI_PERF_EXPORT_SCB0_STALL', + 255: 'SPI_PERF_EXPORT_SCB1_STALL', + 256: 'SPI_PERF_EXPORT_SCB2_STALL', + 257: 'SPI_PERF_EXPORT_SCB3_STALL', + 258: 'SPI_PERF_EXPORT_DB0_STALL', + 259: 'SPI_PERF_EXPORT_DB1_STALL', + 260: 'SPI_PERF_EXPORT_DB2_STALL', + 261: 'SPI_PERF_EXPORT_DB3_STALL', + 262: 'SPI_PERF_EXPORT_DB4_STALL', + 263: 'SPI_PERF_EXPORT_DB5_STALL', + 264: 'SPI_PERF_EXPORT_DB6_STALL', + 265: 'SPI_PERF_EXPORT_DB7_STALL', + 266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL', + 268: 'SPI_PERF_SWC_PS_WR', + 269: 'SPI_PERF_SWC_GS_WR', + 270: 'SPI_PERF_SWC_HS_WR', + 271: 'SPI_PERF_SWC_CSGN_WR', + 272: 'SPI_PERF_SWC_CSN_WR', + 273: 'SPI_PERF_VWC_PS_WR', + 274: 'SPI_PERF_VWC_ES_WR', + 275: 'SPI_PERF_VWC_GS_WR', + 276: 'SPI_PERF_VWC_LS_WR', + 277: 'SPI_PERF_VWC_HS_WR', + 278: 'SPI_PERF_VWC_CSGN_WR', + 279: 'SPI_PERF_VWC_CSN_WR', + 280: 'SPI_PERF_EXP_THROT_UPSTEP', + 281: 'SPI_PERF_EXP_THROT_DOWNSTEP', + 282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 283: 'SPI_PERF_BUSY', +} +SPI_PERF_GS_WINDOW_VALID = 1 +SPI_PERF_GS_BUSY = 2 +SPI_PERF_GS_CRAWLER_STALL = 3 +SPI_PERF_GS_EVENT_WAVE = 4 +SPI_PERF_GS_WAVE = 5 +SPI_PERF_GS_PERS_UPD_FULL0 = 6 +SPI_PERF_GS_PERS_UPD_FULL1 = 7 +SPI_PERF_GS_FIRST_SUBGRP = 8 +SPI_PERF_GS_HS_DEALLOC = 9 +SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10 +SPI_PERF_GS_POS0_STALL = 11 +SPI_PERF_GS_POS1_STALL = 12 +SPI_PERF_GS_INDX0_STALL = 13 +SPI_PERF_GS_INDX1_STALL = 14 +SPI_PERF_GS_PWS_STALL = 15 +SPI_PERF_HS_WINDOW_VALID = 21 +SPI_PERF_HS_BUSY = 22 +SPI_PERF_HS_CRAWLER_STALL = 23 +SPI_PERF_HS_FIRST_WAVE = 24 +SPI_PERF_HS_OFFCHIP_LDS_STALL = 25 +SPI_PERF_HS_EVENT_WAVE = 26 +SPI_PERF_HS_WAVE = 27 +SPI_PERF_HS_PERS_UPD_FULL0 = 28 +SPI_PERF_HS_PERS_UPD_FULL1 = 29 +SPI_PERF_HS_PWS_STALL = 30 +SPI_PERF_CSGN_WINDOW_VALID = 37 +SPI_PERF_CSGN_BUSY = 38 +SPI_PERF_CSGN_NUM_THREADGROUPS = 39 +SPI_PERF_CSGN_CRAWLER_STALL = 40 +SPI_PERF_CSGN_EVENT_WAVE = 41 +SPI_PERF_CSGN_WAVE = 42 +SPI_PERF_CSGN_PWS_STALL = 43 +SPI_PERF_CSN_WINDOW_VALID = 44 +SPI_PERF_CSN_BUSY = 45 +SPI_PERF_CSN_NUM_THREADGROUPS = 46 +SPI_PERF_CSN_CRAWLER_STALL = 47 +SPI_PERF_CSN_EVENT_WAVE = 48 +SPI_PERF_CSN_WAVE = 49 +SPI_PERF_PS0_WINDOW_VALID = 53 +SPI_PERF_PS1_WINDOW_VALID = 54 +SPI_PERF_PS2_WINDOW_VALID = 55 +SPI_PERF_PS3_WINDOW_VALID = 56 +SPI_PERF_PS0_BUSY = 57 +SPI_PERF_PS1_BUSY = 58 +SPI_PERF_PS2_BUSY = 59 +SPI_PERF_PS3_BUSY = 60 +SPI_PERF_PS0_ACTIVE = 61 +SPI_PERF_PS1_ACTIVE = 62 +SPI_PERF_PS2_ACTIVE = 63 +SPI_PERF_PS3_ACTIVE = 64 +SPI_PERF_PS0_DEALLOC = 65 +SPI_PERF_PS1_DEALLOC = 66 +SPI_PERF_PS2_DEALLOC = 67 +SPI_PERF_PS3_DEALLOC = 68 +SPI_PERF_PS0_EVENT_WAVE = 69 +SPI_PERF_PS1_EVENT_WAVE = 70 +SPI_PERF_PS2_EVENT_WAVE = 71 +SPI_PERF_PS3_EVENT_WAVE = 72 +SPI_PERF_PS0_WAVE = 73 +SPI_PERF_PS1_WAVE = 74 +SPI_PERF_PS2_WAVE = 75 +SPI_PERF_PS3_WAVE = 76 +SPI_PERF_PS0_OPT_WAVE = 77 +SPI_PERF_PS1_OPT_WAVE = 78 +SPI_PERF_PS2_OPT_WAVE = 79 +SPI_PERF_PS3_OPT_WAVE = 80 +SPI_PERF_PS0_PRIM_BIN0 = 81 +SPI_PERF_PS1_PRIM_BIN0 = 82 +SPI_PERF_PS2_PRIM_BIN0 = 83 +SPI_PERF_PS3_PRIM_BIN0 = 84 +SPI_PERF_PS0_PRIM_BIN1 = 85 +SPI_PERF_PS1_PRIM_BIN1 = 86 +SPI_PERF_PS2_PRIM_BIN1 = 87 +SPI_PERF_PS3_PRIM_BIN1 = 88 +SPI_PERF_PS0_CRAWLER_STALL = 89 +SPI_PERF_PS1_CRAWLER_STALL = 90 +SPI_PERF_PS2_CRAWLER_STALL = 91 +SPI_PERF_PS3_CRAWLER_STALL = 92 +SPI_PERF_PS_PERS_UPD_FULL0 = 93 +SPI_PERF_PS_PERS_UPD_FULL1 = 94 +SPI_PERF_PS0_2_WAVE_GROUPS = 95 +SPI_PERF_PS1_2_WAVE_GROUPS = 96 +SPI_PERF_PS2_2_WAVE_GROUPS = 97 +SPI_PERF_PS3_2_WAVE_GROUPS = 98 +SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99 +SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100 +SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101 +SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102 +SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103 +SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104 +SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105 +SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106 +SPI_PERF_PS_PWS_STALL = 107 +SPI_PERF_RA_PIPE_REQ_BIN2 = 141 +SPI_PERF_RA_TASK_REQ_BIN3 = 142 +SPI_PERF_RA_WR_CTL_FULL = 143 +SPI_PERF_RA_REQ_NO_ALLOC = 144 +SPI_PERF_RA_REQ_NO_ALLOC_PS = 145 +SPI_PERF_RA_REQ_NO_ALLOC_GS = 146 +SPI_PERF_RA_REQ_NO_ALLOC_HS = 147 +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148 +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149 +SPI_PERF_RA_RES_STALL_PS = 150 +SPI_PERF_RA_RES_STALL_GS = 151 +SPI_PERF_RA_RES_STALL_HS = 152 +SPI_PERF_RA_RES_STALL_CSG = 153 +SPI_PERF_RA_RES_STALL_CSN = 154 +SPI_PERF_RA_TMP_STALL_PS = 155 +SPI_PERF_RA_TMP_STALL_GS = 156 +SPI_PERF_RA_TMP_STALL_HS = 157 +SPI_PERF_RA_TMP_STALL_CSG = 158 +SPI_PERF_RA_TMP_STALL_CSN = 159 +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160 +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161 +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162 +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163 +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164 +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165 +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166 +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167 +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168 +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169 +SPI_PERF_RA_LDS_CU_FULL_PS = 170 +SPI_PERF_RA_LDS_CU_FULL_HS = 171 +SPI_PERF_RA_LDS_CU_FULL_GS = 172 +SPI_PERF_RA_LDS_CU_FULL_CSG = 173 +SPI_PERF_RA_LDS_CU_FULL_CSN = 174 +SPI_PERF_RA_BAR_CU_FULL_HS = 175 +SPI_PERF_RA_BAR_CU_FULL_CSG = 176 +SPI_PERF_RA_BAR_CU_FULL_CSN = 177 +SPI_PERF_RA_BULKY_CU_FULL_CSG = 178 +SPI_PERF_RA_BULKY_CU_FULL_CSN = 179 +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 180 +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 181 +SPI_PERF_RA_WVLIM_STALL_PS = 182 +SPI_PERF_RA_WVLIM_STALL_GS = 183 +SPI_PERF_RA_WVLIM_STALL_HS = 184 +SPI_PERF_RA_WVLIM_STALL_CSG = 185 +SPI_PERF_RA_WVLIM_STALL_CSN = 186 +SPI_PERF_RA_GS_LOCK = 187 +SPI_PERF_RA_HS_LOCK = 188 +SPI_PERF_RA_CSG_LOCK = 189 +SPI_PERF_RA_CSN_LOCK = 190 +SPI_PERF_RA_RSV_UPD = 191 +SPI_PERF_RA_PRE_ALLOC_STALL = 192 +SPI_PERF_RA_GFX_UNDER_TUNNEL = 193 +SPI_PERF_RA_CSC_UNDER_TUNNEL = 194 +SPI_PERF_RA_WVALLOC_STALL = 195 +SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 196 +SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 197 +SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 198 +SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 199 +SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 200 +SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 201 +SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 202 +SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 203 +SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 204 +SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 205 +SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 206 +SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 207 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 208 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 209 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 210 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 211 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 212 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 213 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 214 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 215 +SPI_PERF_EXP_ARB_COL_CNT = 216 +SPI_PERF_EXP_ARB_POS_CNT = 217 +SPI_PERF_EXP_ARB_GDS_CNT = 218 +SPI_PERF_EXP_ARB_IDX_CNT = 219 +SPI_PERF_EXP_WITH_CONFLICT = 220 +SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 221 +SPI_PERF_GS_EXP_DONE = 222 +SPI_PERF_PS_EXP_DONE = 223 +SPI_PERF_PS_EXP_ARB_CONFLICT = 224 +SPI_PERF_PS_EXP_ALLOC = 225 +SPI_PERF_PS0_WAVEID_STARVED = 226 +SPI_PERF_PS1_WAVEID_STARVED = 227 +SPI_PERF_PS2_WAVEID_STARVED = 228 +SPI_PERF_PS3_WAVEID_STARVED = 229 +SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 230 +SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 231 +SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 232 +SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 233 +SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 234 +SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 235 +SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 236 +SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 237 +SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 238 +SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 239 +SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 240 +SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 241 +SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 242 +SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 243 +SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 244 +SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 245 +SPI_PERF_NUM_EXPGRANT_EXPORTS = 246 +SPI_PERF_PIX_ALLOC_PEND_CNT = 253 +SPI_PERF_EXPORT_SCB0_STALL = 254 +SPI_PERF_EXPORT_SCB1_STALL = 255 +SPI_PERF_EXPORT_SCB2_STALL = 256 +SPI_PERF_EXPORT_SCB3_STALL = 257 +SPI_PERF_EXPORT_DB0_STALL = 258 +SPI_PERF_EXPORT_DB1_STALL = 259 +SPI_PERF_EXPORT_DB2_STALL = 260 +SPI_PERF_EXPORT_DB3_STALL = 261 +SPI_PERF_EXPORT_DB4_STALL = 262 +SPI_PERF_EXPORT_DB5_STALL = 263 +SPI_PERF_EXPORT_DB6_STALL = 264 +SPI_PERF_EXPORT_DB7_STALL = 265 +SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266 +SPI_PERF_GS_NGG_STALL_MSG_VAL = 267 +SPI_PERF_SWC_PS_WR = 268 +SPI_PERF_SWC_GS_WR = 269 +SPI_PERF_SWC_HS_WR = 270 +SPI_PERF_SWC_CSGN_WR = 271 +SPI_PERF_SWC_CSN_WR = 272 +SPI_PERF_VWC_PS_WR = 273 +SPI_PERF_VWC_ES_WR = 274 +SPI_PERF_VWC_GS_WR = 275 +SPI_PERF_VWC_LS_WR = 276 +SPI_PERF_VWC_HS_WR = 277 +SPI_PERF_VWC_CSGN_WR = 278 +SPI_PERF_VWC_CSN_WR = 279 +SPI_PERF_EXP_THROT_UPSTEP = 280 +SPI_PERF_EXP_THROT_DOWNSTEP = 281 +SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282 +SPI_PERF_BUSY = 283 +SPI_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' +SPI_PNT_SPRITE_OVERRIDE__enumvalues = { + 0: 'SPI_PNT_SPRITE_SEL_0', + 1: 'SPI_PNT_SPRITE_SEL_1', + 2: 'SPI_PNT_SPRITE_SEL_S', + 3: 'SPI_PNT_SPRITE_SEL_T', + 4: 'SPI_PNT_SPRITE_SEL_NONE', +} +SPI_PNT_SPRITE_SEL_0 = 0 +SPI_PNT_SPRITE_SEL_1 = 1 +SPI_PNT_SPRITE_SEL_S = 2 +SPI_PNT_SPRITE_SEL_T = 3 +SPI_PNT_SPRITE_SEL_NONE = 4 +SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PS_LDS_GROUP_SIZE' +SPI_PS_LDS_GROUP_SIZE__enumvalues = { + 0: 'SPI_PS_LDS_GROUP_1', + 1: 'SPI_PS_LDS_GROUP_2', + 2: 'SPI_PS_LDS_GROUP_4', +} +SPI_PS_LDS_GROUP_1 = 0 +SPI_PS_LDS_GROUP_2 = 1 +SPI_PS_LDS_GROUP_4 = 2 +SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SAMPLE_CNTL' +SPI_SAMPLE_CNTL__enumvalues = { + 0: 'CENTROIDS_ONLY', + 1: 'CENTERS_ONLY', + 2: 'CENTROIDS_AND_CENTERS', + 3: 'UNDEF', +} +CENTROIDS_ONLY = 0 +CENTERS_ONLY = 1 +CENTROIDS_AND_CENTERS = 2 +UNDEF = 3 +SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_EX_FORMAT' +SPI_SHADER_EX_FORMAT__enumvalues = { + 0: 'SPI_SHADER_ZERO', + 1: 'SPI_SHADER_32_R', + 2: 'SPI_SHADER_32_GR', + 3: 'SPI_SHADER_32_AR', + 4: 'SPI_SHADER_FP16_ABGR', + 5: 'SPI_SHADER_UNORM16_ABGR', + 6: 'SPI_SHADER_SNORM16_ABGR', + 7: 'SPI_SHADER_UINT16_ABGR', + 8: 'SPI_SHADER_SINT16_ABGR', + 9: 'SPI_SHADER_32_ABGR', +} +SPI_SHADER_ZERO = 0 +SPI_SHADER_32_R = 1 +SPI_SHADER_32_GR = 2 +SPI_SHADER_32_AR = 3 +SPI_SHADER_FP16_ABGR = 4 +SPI_SHADER_UNORM16_ABGR = 5 +SPI_SHADER_SNORM16_ABGR = 6 +SPI_SHADER_UINT16_ABGR = 7 +SPI_SHADER_SINT16_ABGR = 8 +SPI_SHADER_32_ABGR = 9 +SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_FORMAT' +SPI_SHADER_FORMAT__enumvalues = { + 0: 'SPI_SHADER_NONE', + 1: 'SPI_SHADER_1COMP', + 2: 'SPI_SHADER_2COMP', + 3: 'SPI_SHADER_4COMPRESS', + 4: 'SPI_SHADER_4COMP', +} +SPI_SHADER_NONE = 0 +SPI_SHADER_1COMP = 1 +SPI_SHADER_2COMP = 2 +SPI_SHADER_4COMPRESS = 3 +SPI_SHADER_4COMP = 4 +SPI_SHADER_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ADDRESS_MODE' +SH_MEM_ADDRESS_MODE__enumvalues = { + 0: 'SH_MEM_ADDRESS_MODE_64', + 1: 'SH_MEM_ADDRESS_MODE_32', +} +SH_MEM_ADDRESS_MODE_64 = 0 +SH_MEM_ADDRESS_MODE_32 = 1 +SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ALIGNMENT_MODE' +SH_MEM_ALIGNMENT_MODE__enumvalues = { + 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', + 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', + 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', +} +SH_MEM_ALIGNMENT_MODE_DWORD = 0 +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 +SH_MEM_ALIGNMENT_MODE_STRICT = 2 +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 +SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQG_PERF_SEL' +SQG_PERF_SEL__enumvalues = { + 0: 'SQG_PERF_SEL_NONE', + 1: 'SQG_PERF_SEL_MSG_BUS_BUSY', + 2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', + 4: 'SQG_PERF_SEL_EXP_BUS0_BUSY', + 5: 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 6: 'SQG_PERF_SEL_TTRACE_REQS', + 7: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 8: 'SQG_PERF_SEL_TTRACE_STALL', + 9: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', + 10: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', + 11: 'SQG_PERF_SEL_EVENTS', + 12: 'SQG_PERF_SEL_WAVES_RESTORED', + 13: 'SQG_PERF_SEL_WAVES_SAVED', + 14: 'SQG_PERF_SEL_ACCUM_PREV', + 15: 'SQG_PERF_SEL_CYCLES', + 16: 'SQG_PERF_SEL_BUSY_CYCLES', + 17: 'SQG_PERF_SEL_WAVE_CYCLES', + 18: 'SQG_PERF_SEL_MSG', + 19: 'SQG_PERF_SEL_MSG_INTERRUPT', + 20: 'SQG_PERF_SEL_WAVES', + 21: 'SQG_PERF_SEL_WAVES_32', + 22: 'SQG_PERF_SEL_WAVES_64', + 23: 'SQG_PERF_SEL_LEVEL_WAVES', + 24: 'SQG_PERF_SEL_ITEMS', + 25: 'SQG_PERF_SEL_WAVE32_ITEMS', + 26: 'SQG_PERF_SEL_WAVE64_ITEMS', + 27: 'SQG_PERF_SEL_PS_QUADS', + 28: 'SQG_PERF_SEL_WAVES_EQ_64', + 29: 'SQG_PERF_SEL_WAVES_EQ_32', + 30: 'SQG_PERF_SEL_WAVES_LT_64', + 31: 'SQG_PERF_SEL_WAVES_LT_48', + 32: 'SQG_PERF_SEL_WAVES_LT_32', + 33: 'SQG_PERF_SEL_WAVES_LT_16', + 34: 'SQG_PERF_SEL_DUMMY_LAST', +} +SQG_PERF_SEL_NONE = 0 +SQG_PERF_SEL_MSG_BUS_BUSY = 1 +SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2 +SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3 +SQG_PERF_SEL_EXP_BUS0_BUSY = 4 +SQG_PERF_SEL_EXP_BUS1_BUSY = 5 +SQG_PERF_SEL_TTRACE_REQS = 6 +SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 7 +SQG_PERF_SEL_TTRACE_STALL = 8 +SQG_PERF_SEL_TTRACE_LOST_PACKETS = 9 +SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 10 +SQG_PERF_SEL_EVENTS = 11 +SQG_PERF_SEL_WAVES_RESTORED = 12 +SQG_PERF_SEL_WAVES_SAVED = 13 +SQG_PERF_SEL_ACCUM_PREV = 14 +SQG_PERF_SEL_CYCLES = 15 +SQG_PERF_SEL_BUSY_CYCLES = 16 +SQG_PERF_SEL_WAVE_CYCLES = 17 +SQG_PERF_SEL_MSG = 18 +SQG_PERF_SEL_MSG_INTERRUPT = 19 +SQG_PERF_SEL_WAVES = 20 +SQG_PERF_SEL_WAVES_32 = 21 +SQG_PERF_SEL_WAVES_64 = 22 +SQG_PERF_SEL_LEVEL_WAVES = 23 +SQG_PERF_SEL_ITEMS = 24 +SQG_PERF_SEL_WAVE32_ITEMS = 25 +SQG_PERF_SEL_WAVE64_ITEMS = 26 +SQG_PERF_SEL_PS_QUADS = 27 +SQG_PERF_SEL_WAVES_EQ_64 = 28 +SQG_PERF_SEL_WAVES_EQ_32 = 29 +SQG_PERF_SEL_WAVES_LT_64 = 30 +SQG_PERF_SEL_WAVES_LT_48 = 31 +SQG_PERF_SEL_WAVES_LT_32 = 32 +SQG_PERF_SEL_WAVES_LT_16 = 33 +SQG_PERF_SEL_DUMMY_LAST = 34 +SQG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_CAC_POWER_SEL' +SQ_CAC_POWER_SEL__enumvalues = { + 0: 'SQ_CAC_POWER_VALU', + 1: 'SQ_CAC_POWER_VALU0', + 2: 'SQ_CAC_POWER_VALU1', + 3: 'SQ_CAC_POWER_VALU2', + 4: 'SQ_CAC_POWER_GPR_RD', + 5: 'SQ_CAC_POWER_GPR_WR', + 6: 'SQ_CAC_POWER_LDS_BUSY', + 7: 'SQ_CAC_POWER_ALU_BUSY', + 8: 'SQ_CAC_POWER_TEX_BUSY', +} +SQ_CAC_POWER_VALU = 0 +SQ_CAC_POWER_VALU0 = 1 +SQ_CAC_POWER_VALU1 = 2 +SQ_CAC_POWER_VALU2 = 3 +SQ_CAC_POWER_GPR_RD = 4 +SQ_CAC_POWER_GPR_WR = 5 +SQ_CAC_POWER_LDS_BUSY = 6 +SQ_CAC_POWER_ALU_BUSY = 7 +SQ_CAC_POWER_TEX_BUSY = 8 +SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_EDC_INFO_SOURCE' +SQ_EDC_INFO_SOURCE__enumvalues = { + 0: 'SQ_EDC_INFO_SOURCE_INVALID', + 1: 'SQ_EDC_INFO_SOURCE_INST', + 2: 'SQ_EDC_INFO_SOURCE_SGPR', + 3: 'SQ_EDC_INFO_SOURCE_VGPR', + 4: 'SQ_EDC_INFO_SOURCE_LDS', + 5: 'SQ_EDC_INFO_SOURCE_GDS', + 6: 'SQ_EDC_INFO_SOURCE_TA', +} +SQ_EDC_INFO_SOURCE_INVALID = 0 +SQ_EDC_INFO_SOURCE_INST = 1 +SQ_EDC_INFO_SOURCE_SGPR = 2 +SQ_EDC_INFO_SOURCE_VGPR = 3 +SQ_EDC_INFO_SOURCE_LDS = 4 +SQ_EDC_INFO_SOURCE_GDS = 5 +SQ_EDC_INFO_SOURCE_TA = 6 +SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IBUF_ST' +SQ_IBUF_ST__enumvalues = { + 0: 'SQ_IBUF_IB_IDLE', + 1: 'SQ_IBUF_IB_INI_WAIT_GNT', + 2: 'SQ_IBUF_IB_INI_WAIT_DRET', + 3: 'SQ_IBUF_IB_LE_4DW', + 4: 'SQ_IBUF_IB_WAIT_DRET', + 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 6: 'SQ_IBUF_IB_DRET', + 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', +} +SQ_IBUF_IB_IDLE = 0 +SQ_IBUF_IB_INI_WAIT_GNT = 1 +SQ_IBUF_IB_INI_WAIT_DRET = 2 +SQ_IBUF_IB_LE_4DW = 3 +SQ_IBUF_IB_WAIT_DRET = 4 +SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 +SQ_IBUF_IB_DRET = 6 +SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 +SQ_IBUF_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IMG_FILTER_TYPE' +SQ_IMG_FILTER_TYPE__enumvalues = { + 0: 'SQ_IMG_FILTER_MODE_BLEND', + 1: 'SQ_IMG_FILTER_MODE_MIN', + 2: 'SQ_IMG_FILTER_MODE_MAX', +} +SQ_IMG_FILTER_MODE_BLEND = 0 +SQ_IMG_FILTER_MODE_MIN = 1 +SQ_IMG_FILTER_MODE_MAX = 2 +SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_CMD' +SQ_IND_CMD_CMD__enumvalues = { + 0: 'SQ_IND_CMD_CMD_NULL', + 1: 'SQ_IND_CMD_CMD_SETHALT', + 2: 'SQ_IND_CMD_CMD_SAVECTX', + 3: 'SQ_IND_CMD_CMD_KILL', + 4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', + 5: 'SQ_IND_CMD_CMD_TRAP', + 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 7: 'SQ_IND_CMD_CMD_SETFATALHALT', + 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', +} +SQ_IND_CMD_CMD_NULL = 0 +SQ_IND_CMD_CMD_SETHALT = 1 +SQ_IND_CMD_CMD_SAVECTX = 2 +SQ_IND_CMD_CMD_KILL = 3 +SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4 +SQ_IND_CMD_CMD_TRAP = 5 +SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 +SQ_IND_CMD_CMD_SETFATALHALT = 7 +SQ_IND_CMD_CMD_SINGLE_STEP = 8 +SQ_IND_CMD_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_MODE' +SQ_IND_CMD_MODE__enumvalues = { + 0: 'SQ_IND_CMD_MODE_SINGLE', + 1: 'SQ_IND_CMD_MODE_BROADCAST', + 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', + 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', +} +SQ_IND_CMD_MODE_SINGLE = 0 +SQ_IND_CMD_MODE_BROADCAST = 1 +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 +SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 +SQ_IND_CMD_MODE_BROADCAST_ME = 4 +SQ_IND_CMD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_STR_ST' +SQ_INST_STR_ST__enumvalues = { + 0: 'SQ_INST_STR_IB_WAVE_NORML', + 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', + 5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', +} +SQ_INST_STR_IB_WAVE_NORML = 0 +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4 +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5 +SQ_INST_STR_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_TYPE' +SQ_INST_TYPE__enumvalues = { + 0: 'SQ_INST_TYPE_VALU', + 1: 'SQ_INST_TYPE_SCALAR', + 2: 'SQ_INST_TYPE_TEX', + 3: 'SQ_INST_TYPE_LDS', + 4: 'SQ_INST_TYPE_LDS_DIRECT', + 5: 'SQ_INST_TYPE_EXP', + 6: 'SQ_INST_TYPE_MSG', + 7: 'SQ_INST_TYPE_BARRIER', + 8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', + 9: 'SQ_INST_TYPE_BRANCH_TAKEN', + 10: 'SQ_INST_TYPE_JUMP', + 11: 'SQ_INST_TYPE_OTHER', + 12: 'SQ_INST_TYPE_NONE', +} +SQ_INST_TYPE_VALU = 0 +SQ_INST_TYPE_SCALAR = 1 +SQ_INST_TYPE_TEX = 2 +SQ_INST_TYPE_LDS = 3 +SQ_INST_TYPE_LDS_DIRECT = 4 +SQ_INST_TYPE_EXP = 5 +SQ_INST_TYPE_MSG = 6 +SQ_INST_TYPE_BARRIER = 7 +SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8 +SQ_INST_TYPE_BRANCH_TAKEN = 9 +SQ_INST_TYPE_JUMP = 10 +SQ_INST_TYPE_OTHER = 11 +SQ_INST_TYPE_NONE = 12 +SQ_INST_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_LLC_CTL' +SQ_LLC_CTL__enumvalues = { + 0: 'SQ_LLC_0', + 1: 'SQ_LLC_1', + 2: 'SQ_LLC_RSVD_2', + 3: 'SQ_LLC_BYPASS', +} +SQ_LLC_0 = 0 +SQ_LLC_1 = 1 +SQ_LLC_RSVD_2 = 2 +SQ_LLC_BYPASS = 3 +SQ_LLC_CTL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_NO_INST_ISSUE' +SQ_NO_INST_ISSUE__enumvalues = { + 0: 'SQ_NO_INST_ISSUE_NO_INSTS', + 1: 'SQ_NO_INST_ISSUE_ALU_DEP', + 2: 'SQ_NO_INST_ISSUE_S_WAITCNT', + 3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN', + 4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT', + 5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT', + 6: 'SQ_NO_INST_ISSUE_OTHER', +} +SQ_NO_INST_ISSUE_NO_INSTS = 0 +SQ_NO_INST_ISSUE_ALU_DEP = 1 +SQ_NO_INST_ISSUE_S_WAITCNT = 2 +SQ_NO_INST_ISSUE_NO_ARB_WIN = 3 +SQ_NO_INST_ISSUE_SLEEP_WAIT = 4 +SQ_NO_INST_ISSUE_BARRIER_WAIT = 5 +SQ_NO_INST_ISSUE_OTHER = 6 +SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_OOB_SELECT' +SQ_OOB_SELECT__enumvalues = { + 0: 'SQ_OOB_INDEX_AND_OFFSET', + 1: 'SQ_OOB_INDEX_ONLY', + 2: 'SQ_OOB_NUM_RECORDS_0', + 3: 'SQ_OOB_COMPLETE', +} +SQ_OOB_INDEX_AND_OFFSET = 0 +SQ_OOB_INDEX_ONLY = 1 +SQ_OOB_NUM_RECORDS_0 = 2 +SQ_OOB_COMPLETE = 3 +SQ_OOB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_PERF_SEL' +SQ_PERF_SEL__enumvalues = { + 0: 'SQ_PERF_SEL_NONE', + 1: 'SQ_PERF_SEL_ACCUM_PREV', + 2: 'SQ_PERF_SEL_CYCLES', + 3: 'SQ_PERF_SEL_BUSY_CYCLES', + 4: 'SQ_PERF_SEL_WAVES', + 5: 'SQ_PERF_SEL_WAVES_32', + 6: 'SQ_PERF_SEL_WAVES_64', + 7: 'SQ_PERF_SEL_LEVEL_WAVES', + 8: 'SQ_PERF_SEL_ITEMS', + 9: 'SQ_PERF_SEL_WAVE32_ITEMS', + 10: 'SQ_PERF_SEL_WAVE64_ITEMS', + 11: 'SQ_PERF_SEL_PS_QUADS', + 12: 'SQ_PERF_SEL_EVENTS', + 13: 'SQ_PERF_SEL_WAVES_EQ_32', + 14: 'SQ_PERF_SEL_WAVES_EQ_64', + 15: 'SQ_PERF_SEL_WAVES_LT_64', + 16: 'SQ_PERF_SEL_WAVES_LT_48', + 17: 'SQ_PERF_SEL_WAVES_LT_32', + 18: 'SQ_PERF_SEL_WAVES_LT_16', + 19: 'SQ_PERF_SEL_WAVES_RESTORED', + 20: 'SQ_PERF_SEL_WAVES_SAVED', + 21: 'SQ_PERF_SEL_MSG', + 22: 'SQ_PERF_SEL_MSG_INTERRUPT', + 23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 24: 'SQ_PERF_SEL_WAVE_CYCLES', + 25: 'SQ_PERF_SEL_WAVE_READY', + 26: 'SQ_PERF_SEL_WAIT_INST_ANY', + 27: 'SQ_PERF_SEL_WAIT_INST_VALU', + 28: 'SQ_PERF_SEL_WAIT_INST_SCA', + 29: 'SQ_PERF_SEL_WAIT_INST_LDS', + 30: 'SQ_PERF_SEL_WAIT_INST_TEX', + 31: 'SQ_PERF_SEL_WAIT_INST_FLAT', + 32: 'SQ_PERF_SEL_WAIT_INST_VMEM', + 33: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', + 34: 'SQ_PERF_SEL_WAIT_INST_BR_MSG', + 35: 'SQ_PERF_SEL_WAIT_ANY', + 36: 'SQ_PERF_SEL_WAIT_CNT_ANY', + 37: 'SQ_PERF_SEL_WAIT_CNT_VMVS', + 38: 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 39: 'SQ_PERF_SEL_WAIT_CNT_EXP', + 40: 'SQ_PERF_SEL_WAIT_TTRACE', + 41: 'SQ_PERF_SEL_WAIT_IFETCH', + 42: 'SQ_PERF_SEL_WAIT_BARRIER', + 43: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 44: 'SQ_PERF_SEL_WAIT_SLEEP', + 45: 'SQ_PERF_SEL_WAIT_DELAY_ALU', + 46: 'SQ_PERF_SEL_WAIT_DEPCTR', + 47: 'SQ_PERF_SEL_WAIT_OTHER', + 48: 'SQ_PERF_SEL_INSTS_ALL', + 49: 'SQ_PERF_SEL_INSTS_BRANCH', + 50: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 51: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', + 53: 'SQ_PERF_SEL_INSTS_EXP_GDS', + 54: 'SQ_PERF_SEL_INSTS_GDS', + 55: 'SQ_PERF_SEL_INSTS_EXP', + 56: 'SQ_PERF_SEL_INSTS_FLAT', + 57: 'SQ_PERF_SEL_INSTS_LDS', + 58: 'SQ_PERF_SEL_INSTS_SALU', + 59: 'SQ_PERF_SEL_INSTS_SMEM', + 60: 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 61: 'SQ_PERF_SEL_INSTS_SENDMSG', + 62: 'SQ_PERF_SEL_INSTS_VALU', + 63: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 64: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 65: 'SQ_PERF_SEL_INSTS_TEX', + 66: 'SQ_PERF_SEL_INSTS_TEX_LOAD', + 67: 'SQ_PERF_SEL_INSTS_TEX_STORE', + 68: 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 69: 'SQ_PERF_SEL_INSTS_INTERNAL', + 70: 'SQ_PERF_SEL_INSTS_WAVE32', + 71: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', + 72: 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 73: 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 74: 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', + 75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 76: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 77: 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 78: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 80: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', + 81: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 82: 'SQ_PERF_SEL_WAVE32_INSTS', + 83: 'SQ_PERF_SEL_WAVE64_INSTS', + 84: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 85: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 86: 'SQ_PERF_SEL_INST_LEVEL_EXP', + 87: 'SQ_PERF_SEL_INST_LEVEL_GDS', + 88: 'SQ_PERF_SEL_INST_LEVEL_LDS', + 89: 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 90: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 91: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', + 92: 'SQ_PERF_SEL_IFETCH_REQS', + 93: 'SQ_PERF_SEL_IFETCH_LEVEL', + 94: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 95: 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 96: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 97: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 98: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 99: 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 100: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 101: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 102: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 103: 'SQ_PERF_SEL_INST_CYCLES_VALU', + 104: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 105: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 106: 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 107: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 108: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 109: 'SQ_PERF_SEL_INST_CYCLES_LDS', + 110: 'SQ_PERF_SEL_INST_CYCLES_TEX', + 111: 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 112: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', + 113: 'SQ_PERF_SEL_INST_CYCLES_EXP', + 114: 'SQ_PERF_SEL_INST_CYCLES_GDS', + 115: 'SQ_PERF_SEL_VALU_STARVE', + 116: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 117: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 118: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 119: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', + 120: 'SQ_PERF_SEL_VMEM_BUS_STALL', + 121: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 122: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 123: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 124: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 125: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 126: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 127: 'SQ_PERF_SEL_SALU_PIPE_STALL', + 128: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 129: 'SQ_PERF_SEL_MSG_BUS_BUSY', + 130: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', + 131: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', + 132: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 133: 'SQ_PERF_SEL_EXP_BUS0_BUSY', + 134: 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 135: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', + 136: 'SQ_PERF_SEL_USER0', + 137: 'SQ_PERF_SEL_USER1', + 138: 'SQ_PERF_SEL_USER2', + 139: 'SQ_PERF_SEL_USER3', + 140: 'SQ_PERF_SEL_USER4', + 141: 'SQ_PERF_SEL_USER5', + 142: 'SQ_PERF_SEL_USER6', + 143: 'SQ_PERF_SEL_USER7', + 144: 'SQ_PERF_SEL_USER8', + 145: 'SQ_PERF_SEL_USER9', + 146: 'SQ_PERF_SEL_USER10', + 147: 'SQ_PERF_SEL_USER11', + 148: 'SQ_PERF_SEL_USER12', + 149: 'SQ_PERF_SEL_USER13', + 150: 'SQ_PERF_SEL_USER14', + 151: 'SQ_PERF_SEL_USER15', + 152: 'SQ_PERF_SEL_USER_LEVEL0', + 153: 'SQ_PERF_SEL_USER_LEVEL1', + 154: 'SQ_PERF_SEL_USER_LEVEL2', + 155: 'SQ_PERF_SEL_USER_LEVEL3', + 156: 'SQ_PERF_SEL_USER_LEVEL4', + 157: 'SQ_PERF_SEL_USER_LEVEL5', + 158: 'SQ_PERF_SEL_USER_LEVEL6', + 159: 'SQ_PERF_SEL_USER_LEVEL7', + 160: 'SQ_PERF_SEL_USER_LEVEL8', + 161: 'SQ_PERF_SEL_USER_LEVEL9', + 162: 'SQ_PERF_SEL_USER_LEVEL10', + 163: 'SQ_PERF_SEL_USER_LEVEL11', + 164: 'SQ_PERF_SEL_USER_LEVEL12', + 165: 'SQ_PERF_SEL_USER_LEVEL13', + 166: 'SQ_PERF_SEL_USER_LEVEL14', + 167: 'SQ_PERF_SEL_USER_LEVEL15', + 168: 'SQ_PERF_SEL_VALU_RETURN_SDST', + 169: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 170: 'SQ_PERF_SEL_INSTS_VALU_TRANS', + 171: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 172: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', + 173: 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', + 174: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 175: 'SQ_PERF_SEL_INSTS_VALU_VINTERP', + 176: 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', + 177: 'SQ_PERF_SEL_OVERFLOW_PREV', + 178: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', + 179: 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 180: 'SQ_PERF_SEL_INSTS_VALU_2_PASS', + 181: 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 182: 'SQ_PERF_SEL_INSTS_VALU_DP', + 183: 'SQ_PERF_SEL_SP_CONST_CYCLES', + 184: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', + 185: 'SQ_PERF_SEL_ITEMS_VALU', + 186: 'SQ_PERF_SEL_ITEMS_MAX_VALU', + 187: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 188: 'SQ_PERF_SEL_DUMMY_END', + 255: 'SQ_PERF_SEL_DUMMY_LAST', + 256: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 257: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 258: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', + 259: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 260: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 261: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 262: 'SQC_PERF_SEL_LDS_ADDR_STALL', + 263: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', + 264: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 265: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 266: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 267: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', + 268: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 269: 'SQC_PERF_SEL_ICACHE_REQ', + 270: 'SQC_PERF_SEL_ICACHE_HITS', + 271: 'SQC_PERF_SEL_ICACHE_MISSES', + 272: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 273: 'SQC_PERF_SEL_ICACHE_INVAL_INST', + 274: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 275: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 276: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 277: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', + 278: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 279: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 280: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 281: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 282: 'SQC_PERF_SEL_TC_REQ', + 283: 'SQC_PERF_SEL_TC_INST_REQ', + 284: 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 285: 'SQC_PERF_SEL_TC_STALL', + 286: 'SQC_PERF_SEL_TC_STARVE', + 287: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 288: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 289: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 290: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 291: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 292: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 293: 'SQC_PERF_SEL_DCACHE_REQ', + 294: 'SQC_PERF_SEL_DCACHE_HITS', + 295: 'SQC_PERF_SEL_DCACHE_MISSES', + 296: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 297: 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 298: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 299: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 300: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 301: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 302: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 303: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 304: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 305: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 306: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 307: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 308: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 309: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 310: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 311: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 312: 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 313: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 314: 'SQC_PERF_SEL_TD_VGPR_BUSY', + 315: 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 316: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 317: 'SQC_PERF_SEL_ICACHE_GCR', + 318: 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 319: 'SQC_PERF_SEL_DCACHE_GCR', + 320: 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 321: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', + 322: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', + 323: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 324: 'SQC_PERF_SEL_DUMMY_LAST', + 448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', + 450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', + 452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0', + 454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2', + 456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 474: 'SP_PERF_SEL_VALU_OPERAND', + 475: 'SP_PERF_SEL_VALU_VGPR_OPERAND', + 476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', + 480: 'SP_PERF_SEL_VALU_STALL', + 481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 485: 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 487: 'SP_PERF_SEL_VGPR_VMEM_RD', + 488: 'SP_PERF_SEL_VGPR_EXP_RD', + 489: 'SP_PERF_SEL_VGPR_SPI_WR', + 490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', + 491: 'SP_PERF_SEL_VGPR_WR', + 492: 'SP_PERF_SEL_VGPR_RD', + 493: 'SP_PERF_SEL_DUMMY_LAST', + 511: 'SQ_PERF_SEL_NONE2', +} +SQ_PERF_SEL_NONE = 0 +SQ_PERF_SEL_ACCUM_PREV = 1 +SQ_PERF_SEL_CYCLES = 2 +SQ_PERF_SEL_BUSY_CYCLES = 3 +SQ_PERF_SEL_WAVES = 4 +SQ_PERF_SEL_WAVES_32 = 5 +SQ_PERF_SEL_WAVES_64 = 6 +SQ_PERF_SEL_LEVEL_WAVES = 7 +SQ_PERF_SEL_ITEMS = 8 +SQ_PERF_SEL_WAVE32_ITEMS = 9 +SQ_PERF_SEL_WAVE64_ITEMS = 10 +SQ_PERF_SEL_PS_QUADS = 11 +SQ_PERF_SEL_EVENTS = 12 +SQ_PERF_SEL_WAVES_EQ_32 = 13 +SQ_PERF_SEL_WAVES_EQ_64 = 14 +SQ_PERF_SEL_WAVES_LT_64 = 15 +SQ_PERF_SEL_WAVES_LT_48 = 16 +SQ_PERF_SEL_WAVES_LT_32 = 17 +SQ_PERF_SEL_WAVES_LT_16 = 18 +SQ_PERF_SEL_WAVES_RESTORED = 19 +SQ_PERF_SEL_WAVES_SAVED = 20 +SQ_PERF_SEL_MSG = 21 +SQ_PERF_SEL_MSG_INTERRUPT = 22 +SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23 +SQ_PERF_SEL_WAVE_CYCLES = 24 +SQ_PERF_SEL_WAVE_READY = 25 +SQ_PERF_SEL_WAIT_INST_ANY = 26 +SQ_PERF_SEL_WAIT_INST_VALU = 27 +SQ_PERF_SEL_WAIT_INST_SCA = 28 +SQ_PERF_SEL_WAIT_INST_LDS = 29 +SQ_PERF_SEL_WAIT_INST_TEX = 30 +SQ_PERF_SEL_WAIT_INST_FLAT = 31 +SQ_PERF_SEL_WAIT_INST_VMEM = 32 +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 33 +SQ_PERF_SEL_WAIT_INST_BR_MSG = 34 +SQ_PERF_SEL_WAIT_ANY = 35 +SQ_PERF_SEL_WAIT_CNT_ANY = 36 +SQ_PERF_SEL_WAIT_CNT_VMVS = 37 +SQ_PERF_SEL_WAIT_CNT_LGKM = 38 +SQ_PERF_SEL_WAIT_CNT_EXP = 39 +SQ_PERF_SEL_WAIT_TTRACE = 40 +SQ_PERF_SEL_WAIT_IFETCH = 41 +SQ_PERF_SEL_WAIT_BARRIER = 42 +SQ_PERF_SEL_WAIT_EXP_ALLOC = 43 +SQ_PERF_SEL_WAIT_SLEEP = 44 +SQ_PERF_SEL_WAIT_DELAY_ALU = 45 +SQ_PERF_SEL_WAIT_DEPCTR = 46 +SQ_PERF_SEL_WAIT_OTHER = 47 +SQ_PERF_SEL_INSTS_ALL = 48 +SQ_PERF_SEL_INSTS_BRANCH = 49 +SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 50 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 51 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 52 +SQ_PERF_SEL_INSTS_EXP_GDS = 53 +SQ_PERF_SEL_INSTS_GDS = 54 +SQ_PERF_SEL_INSTS_EXP = 55 +SQ_PERF_SEL_INSTS_FLAT = 56 +SQ_PERF_SEL_INSTS_LDS = 57 +SQ_PERF_SEL_INSTS_SALU = 58 +SQ_PERF_SEL_INSTS_SMEM = 59 +SQ_PERF_SEL_INSTS_SMEM_NORM = 60 +SQ_PERF_SEL_INSTS_SENDMSG = 61 +SQ_PERF_SEL_INSTS_VALU = 62 +SQ_PERF_SEL_INSTS_VALU_TRANS32 = 63 +SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 64 +SQ_PERF_SEL_INSTS_TEX = 65 +SQ_PERF_SEL_INSTS_TEX_LOAD = 66 +SQ_PERF_SEL_INSTS_TEX_STORE = 67 +SQ_PERF_SEL_INSTS_DELAY_ALU = 68 +SQ_PERF_SEL_INSTS_INTERNAL = 69 +SQ_PERF_SEL_INSTS_WAVE32 = 70 +SQ_PERF_SEL_INSTS_WAVE32_FLAT = 71 +SQ_PERF_SEL_INSTS_WAVE32_LDS = 72 +SQ_PERF_SEL_INSTS_WAVE32_VALU = 73 +SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 74 +SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 75 +SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 76 +SQ_PERF_SEL_INSTS_WAVE32_TEX = 77 +SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 78 +SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 79 +SQ_PERF_SEL_ITEM_CYCLES_VALU = 80 +SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 81 +SQ_PERF_SEL_WAVE32_INSTS = 82 +SQ_PERF_SEL_WAVE64_INSTS = 83 +SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 84 +SQ_PERF_SEL_WAVE64_HALF_SKIP = 85 +SQ_PERF_SEL_INST_LEVEL_EXP = 86 +SQ_PERF_SEL_INST_LEVEL_GDS = 87 +SQ_PERF_SEL_INST_LEVEL_LDS = 88 +SQ_PERF_SEL_INST_LEVEL_SMEM = 89 +SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 90 +SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 91 +SQ_PERF_SEL_IFETCH_REQS = 92 +SQ_PERF_SEL_IFETCH_LEVEL = 93 +SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 94 +SQ_PERF_SEL_VALU_SGATHER_STALL = 95 +SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 96 +SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 97 +SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 98 +SQ_PERF_SEL_SALU_SGATHER_STALL = 99 +SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 100 +SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 101 +SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 102 +SQ_PERF_SEL_INST_CYCLES_VALU = 103 +SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 104 +SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 105 +SQ_PERF_SEL_INST_CYCLES_VMEM = 106 +SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 107 +SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 108 +SQ_PERF_SEL_INST_CYCLES_LDS = 109 +SQ_PERF_SEL_INST_CYCLES_TEX = 110 +SQ_PERF_SEL_INST_CYCLES_FLAT = 111 +SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 112 +SQ_PERF_SEL_INST_CYCLES_EXP = 113 +SQ_PERF_SEL_INST_CYCLES_GDS = 114 +SQ_PERF_SEL_VALU_STARVE = 115 +SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 116 +SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 117 +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 118 +SQ_PERF_SEL_VMEM_BUS_ACTIVE = 119 +SQ_PERF_SEL_VMEM_BUS_STALL = 120 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 121 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 122 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 123 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 124 +SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 125 +SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 126 +SQ_PERF_SEL_SALU_PIPE_STALL = 127 +SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 128 +SQ_PERF_SEL_MSG_BUS_BUSY = 129 +SQ_PERF_SEL_EXP_REQ_BUS_STALL = 130 +SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 131 +SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 132 +SQ_PERF_SEL_EXP_BUS0_BUSY = 133 +SQ_PERF_SEL_EXP_BUS1_BUSY = 134 +SQ_PERF_SEL_INST_CACHE_REQ_STALL = 135 +SQ_PERF_SEL_USER0 = 136 +SQ_PERF_SEL_USER1 = 137 +SQ_PERF_SEL_USER2 = 138 +SQ_PERF_SEL_USER3 = 139 +SQ_PERF_SEL_USER4 = 140 +SQ_PERF_SEL_USER5 = 141 +SQ_PERF_SEL_USER6 = 142 +SQ_PERF_SEL_USER7 = 143 +SQ_PERF_SEL_USER8 = 144 +SQ_PERF_SEL_USER9 = 145 +SQ_PERF_SEL_USER10 = 146 +SQ_PERF_SEL_USER11 = 147 +SQ_PERF_SEL_USER12 = 148 +SQ_PERF_SEL_USER13 = 149 +SQ_PERF_SEL_USER14 = 150 +SQ_PERF_SEL_USER15 = 151 +SQ_PERF_SEL_USER_LEVEL0 = 152 +SQ_PERF_SEL_USER_LEVEL1 = 153 +SQ_PERF_SEL_USER_LEVEL2 = 154 +SQ_PERF_SEL_USER_LEVEL3 = 155 +SQ_PERF_SEL_USER_LEVEL4 = 156 +SQ_PERF_SEL_USER_LEVEL5 = 157 +SQ_PERF_SEL_USER_LEVEL6 = 158 +SQ_PERF_SEL_USER_LEVEL7 = 159 +SQ_PERF_SEL_USER_LEVEL8 = 160 +SQ_PERF_SEL_USER_LEVEL9 = 161 +SQ_PERF_SEL_USER_LEVEL10 = 162 +SQ_PERF_SEL_USER_LEVEL11 = 163 +SQ_PERF_SEL_USER_LEVEL12 = 164 +SQ_PERF_SEL_USER_LEVEL13 = 165 +SQ_PERF_SEL_USER_LEVEL14 = 166 +SQ_PERF_SEL_USER_LEVEL15 = 167 +SQ_PERF_SEL_VALU_RETURN_SDST = 168 +SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 169 +SQ_PERF_SEL_INSTS_VALU_TRANS = 170 +SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 171 +SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 172 +SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 173 +SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 174 +SQ_PERF_SEL_INSTS_VALU_VINTERP = 175 +SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 176 +SQ_PERF_SEL_OVERFLOW_PREV = 177 +SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 178 +SQ_PERF_SEL_INSTS_VALU_1_PASS = 179 +SQ_PERF_SEL_INSTS_VALU_2_PASS = 180 +SQ_PERF_SEL_INSTS_VALU_4_PASS = 181 +SQ_PERF_SEL_INSTS_VALU_DP = 182 +SQ_PERF_SEL_SP_CONST_CYCLES = 183 +SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 184 +SQ_PERF_SEL_ITEMS_VALU = 185 +SQ_PERF_SEL_ITEMS_MAX_VALU = 186 +SQ_PERF_SEL_ITEM_CYCLES_VMEM = 187 +SQ_PERF_SEL_DUMMY_END = 188 +SQ_PERF_SEL_DUMMY_LAST = 255 +SQC_PERF_SEL_LDS_BANK_CONFLICT = 256 +SQC_PERF_SEL_LDS_ADDR_CONFLICT = 257 +SQC_PERF_SEL_LDS_UNALIGNED_STALL = 258 +SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 259 +SQC_PERF_SEL_LDS_ATOMIC_RETURN = 260 +SQC_PERF_SEL_LDS_IDX_ACTIVE = 261 +SQC_PERF_SEL_LDS_ADDR_STALL = 262 +SQC_PERF_SEL_LDS_ADDR_ACTIVE = 263 +SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 264 +SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 265 +SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 266 +SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 267 +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 268 +SQC_PERF_SEL_ICACHE_REQ = 269 +SQC_PERF_SEL_ICACHE_HITS = 270 +SQC_PERF_SEL_ICACHE_MISSES = 271 +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 272 +SQC_PERF_SEL_ICACHE_INVAL_INST = 273 +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 274 +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 275 +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 276 +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 277 +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 278 +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 279 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 280 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 281 +SQC_PERF_SEL_TC_REQ = 282 +SQC_PERF_SEL_TC_INST_REQ = 283 +SQC_PERF_SEL_TC_DATA_READ_REQ = 284 +SQC_PERF_SEL_TC_STALL = 285 +SQC_PERF_SEL_TC_STARVE = 286 +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 287 +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 288 +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 289 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 290 +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 291 +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 292 +SQC_PERF_SEL_DCACHE_REQ = 293 +SQC_PERF_SEL_DCACHE_HITS = 294 +SQC_PERF_SEL_DCACHE_MISSES = 295 +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 296 +SQC_PERF_SEL_DCACHE_INVAL_INST = 297 +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 298 +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 299 +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 300 +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 301 +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 302 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 303 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 304 +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 305 +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 306 +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 307 +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 308 +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 309 +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 310 +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 311 +SQC_PERF_SEL_SQ_DCACHE_REQS = 312 +SQC_PERF_SEL_DCACHE_FLAT_REQ = 313 +SQC_PERF_SEL_TD_VGPR_BUSY = 314 +SQC_PERF_SEL_LDS_VGPR_BUSY = 315 +SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 316 +SQC_PERF_SEL_ICACHE_GCR = 317 +SQC_PERF_SEL_ICACHE_GCR_HITS = 318 +SQC_PERF_SEL_DCACHE_GCR = 319 +SQC_PERF_SEL_DCACHE_GCR_HITS = 320 +SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 321 +SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 322 +SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 323 +SQC_PERF_SEL_DUMMY_LAST = 324 +SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448 +SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449 +SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450 +SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451 +SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452 +SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453 +SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454 +SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455 +SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456 +SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457 +SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458 +SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459 +SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472 +SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473 +SP_PERF_SEL_VALU_OPERAND = 474 +SP_PERF_SEL_VALU_VGPR_OPERAND = 475 +SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476 +SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477 +SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478 +SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479 +SP_PERF_SEL_VALU_STALL = 480 +SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481 +SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482 +SP_PERF_SEL_VALU_STALL_VDST_FWD = 483 +SP_PERF_SEL_VALU_STALL_SDST_FWD = 484 +SP_PERF_SEL_VALU_STALL_DST_STALL = 485 +SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486 +SP_PERF_SEL_VGPR_VMEM_RD = 487 +SP_PERF_SEL_VGPR_EXP_RD = 488 +SP_PERF_SEL_VGPR_SPI_WR = 489 +SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490 +SP_PERF_SEL_VGPR_WR = 491 +SP_PERF_SEL_VGPR_RD = 492 +SP_PERF_SEL_DUMMY_LAST = 493 +SQ_PERF_SEL_NONE2 = 511 +SQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_ROUND_MODE' +SQ_ROUND_MODE__enumvalues = { + 0: 'SQ_ROUND_NEAREST_EVEN', + 1: 'SQ_ROUND_PLUS_INFINITY', + 2: 'SQ_ROUND_MINUS_INFINITY', + 3: 'SQ_ROUND_TO_ZERO', +} +SQ_ROUND_NEAREST_EVEN = 0 +SQ_ROUND_PLUS_INFINITY = 1 +SQ_ROUND_MINUS_INFINITY = 2 +SQ_ROUND_TO_ZERO = 3 +SQ_ROUND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_BUF_TYPE' +SQ_RSRC_BUF_TYPE__enumvalues = { + 0: 'SQ_RSRC_BUF', + 1: 'SQ_RSRC_BUF_RSVD_1', + 2: 'SQ_RSRC_BUF_RSVD_2', + 3: 'SQ_RSRC_BUF_RSVD_3', +} +SQ_RSRC_BUF = 0 +SQ_RSRC_BUF_RSVD_1 = 1 +SQ_RSRC_BUF_RSVD_2 = 2 +SQ_RSRC_BUF_RSVD_3 = 3 +SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_FLAT_TYPE' +SQ_RSRC_FLAT_TYPE__enumvalues = { + 0: 'SQ_RSRC_FLAT_RSVD_0', + 1: 'SQ_RSRC_FLAT', + 2: 'SQ_RSRC_FLAT_RSVD_2', + 3: 'SQ_RSRC_FLAT_RSVD_3', +} +SQ_RSRC_FLAT_RSVD_0 = 0 +SQ_RSRC_FLAT = 1 +SQ_RSRC_FLAT_RSVD_2 = 2 +SQ_RSRC_FLAT_RSVD_3 = 3 +SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_IMG_TYPE' +SQ_RSRC_IMG_TYPE__enumvalues = { + 0: 'SQ_RSRC_IMG_RSVD_0', + 1: 'SQ_RSRC_IMG_RSVD_1', + 2: 'SQ_RSRC_IMG_RSVD_2', + 3: 'SQ_RSRC_IMG_RSVD_3', + 4: 'SQ_RSRC_IMG_RSVD_4', + 5: 'SQ_RSRC_IMG_RSVD_5', + 6: 'SQ_RSRC_IMG_RSVD_6', + 7: 'SQ_RSRC_IMG_RSVD_7', + 8: 'SQ_RSRC_IMG_1D', + 9: 'SQ_RSRC_IMG_2D', + 10: 'SQ_RSRC_IMG_3D', + 11: 'SQ_RSRC_IMG_CUBE', + 12: 'SQ_RSRC_IMG_1D_ARRAY', + 13: 'SQ_RSRC_IMG_2D_ARRAY', + 14: 'SQ_RSRC_IMG_2D_MSAA', + 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', +} +SQ_RSRC_IMG_RSVD_0 = 0 +SQ_RSRC_IMG_RSVD_1 = 1 +SQ_RSRC_IMG_RSVD_2 = 2 +SQ_RSRC_IMG_RSVD_3 = 3 +SQ_RSRC_IMG_RSVD_4 = 4 +SQ_RSRC_IMG_RSVD_5 = 5 +SQ_RSRC_IMG_RSVD_6 = 6 +SQ_RSRC_IMG_RSVD_7 = 7 +SQ_RSRC_IMG_1D = 8 +SQ_RSRC_IMG_2D = 9 +SQ_RSRC_IMG_3D = 10 +SQ_RSRC_IMG_CUBE = 11 +SQ_RSRC_IMG_1D_ARRAY = 12 +SQ_RSRC_IMG_2D_ARRAY = 13 +SQ_RSRC_IMG_2D_MSAA = 14 +SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 +SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_SEL_XYZW01' +SQ_SEL_XYZW01__enumvalues = { + 0: 'SQ_SEL_0', + 1: 'SQ_SEL_1', + 2: 'SQ_SEL_N_BC_1', + 3: 'SQ_SEL_RESERVED_1', + 4: 'SQ_SEL_X', + 5: 'SQ_SEL_Y', + 6: 'SQ_SEL_Z', + 7: 'SQ_SEL_W', +} +SQ_SEL_0 = 0 +SQ_SEL_1 = 1 +SQ_SEL_N_BC_1 = 2 +SQ_SEL_RESERVED_1 = 3 +SQ_SEL_X = 4 +SQ_SEL_Y = 5 +SQ_SEL_Z = 6 +SQ_SEL_W = 7 +SQ_SEL_XYZW01 = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_ANISO_RATIO' +SQ_TEX_ANISO_RATIO__enumvalues = { + 0: 'SQ_TEX_ANISO_RATIO_1', + 1: 'SQ_TEX_ANISO_RATIO_2', + 2: 'SQ_TEX_ANISO_RATIO_4', + 3: 'SQ_TEX_ANISO_RATIO_8', + 4: 'SQ_TEX_ANISO_RATIO_16', +} +SQ_TEX_ANISO_RATIO_1 = 0 +SQ_TEX_ANISO_RATIO_2 = 1 +SQ_TEX_ANISO_RATIO_4 = 2 +SQ_TEX_ANISO_RATIO_8 = 3 +SQ_TEX_ANISO_RATIO_16 = 4 +SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_BORDER_COLOR' +SQ_TEX_BORDER_COLOR__enumvalues = { + 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 3: 'SQ_TEX_BORDER_COLOR_REGISTER', +} +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 +SQ_TEX_BORDER_COLOR_REGISTER = 3 +SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_CLAMP' +SQ_TEX_CLAMP__enumvalues = { + 0: 'SQ_TEX_WRAP', + 1: 'SQ_TEX_MIRROR', + 2: 'SQ_TEX_CLAMP_LAST_TEXEL', + 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 4: 'SQ_TEX_CLAMP_HALF_BORDER', + 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', + 6: 'SQ_TEX_CLAMP_BORDER', + 7: 'SQ_TEX_MIRROR_ONCE_BORDER', +} +SQ_TEX_WRAP = 0 +SQ_TEX_MIRROR = 1 +SQ_TEX_CLAMP_LAST_TEXEL = 2 +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 +SQ_TEX_CLAMP_HALF_BORDER = 4 +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 +SQ_TEX_CLAMP_BORDER = 6 +SQ_TEX_MIRROR_ONCE_BORDER = 7 +SQ_TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_DEPTH_COMPARE' +SQ_TEX_DEPTH_COMPARE__enumvalues = { + 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', + 1: 'SQ_TEX_DEPTH_COMPARE_LESS', + 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', + 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', + 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', + 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', + 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', +} +SQ_TEX_DEPTH_COMPARE_NEVER = 0 +SQ_TEX_DEPTH_COMPARE_LESS = 1 +SQ_TEX_DEPTH_COMPARE_EQUAL = 2 +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 +SQ_TEX_DEPTH_COMPARE_GREATER = 4 +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 +SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 +SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_MIP_FILTER' +SQ_TEX_MIP_FILTER__enumvalues = { + 0: 'SQ_TEX_MIP_FILTER_NONE', + 1: 'SQ_TEX_MIP_FILTER_POINT', + 2: 'SQ_TEX_MIP_FILTER_LINEAR', + 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', +} +SQ_TEX_MIP_FILTER_NONE = 0 +SQ_TEX_MIP_FILTER_POINT = 1 +SQ_TEX_MIP_FILTER_LINEAR = 2 +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 +SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_XY_FILTER' +SQ_TEX_XY_FILTER__enumvalues = { + 0: 'SQ_TEX_XY_FILTER_POINT', + 1: 'SQ_TEX_XY_FILTER_BILINEAR', + 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', + 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', +} +SQ_TEX_XY_FILTER_POINT = 0 +SQ_TEX_XY_FILTER_BILINEAR = 1 +SQ_TEX_XY_FILTER_ANISO_POINT = 2 +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 +SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_Z_FILTER' +SQ_TEX_Z_FILTER__enumvalues = { + 0: 'SQ_TEX_Z_FILTER_NONE', + 1: 'SQ_TEX_Z_FILTER_POINT', + 2: 'SQ_TEX_Z_FILTER_LINEAR', +} +SQ_TEX_Z_FILTER_NONE = 0 +SQ_TEX_Z_FILTER_POINT = 1 +SQ_TEX_Z_FILTER_LINEAR = 2 +SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_MODE' +SQ_TT_MODE__enumvalues = { + 0: 'SQ_TT_MODE_OFF', + 1: 'SQ_TT_MODE_ON', + 2: 'SQ_TT_MODE_GLOBAL', + 3: 'SQ_TT_MODE_DETAIL', +} +SQ_TT_MODE_OFF = 0 +SQ_TT_MODE_ON = 1 +SQ_TT_MODE_GLOBAL = 2 +SQ_TT_MODE_DETAIL = 3 +SQ_TT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_RT_FREQ' +SQ_TT_RT_FREQ__enumvalues = { + 0: 'SQ_TT_RT_FREQ_NEVER', + 1: 'SQ_TT_RT_FREQ_1024_CLK', + 2: 'SQ_TT_RT_FREQ_4096_CLK', +} +SQ_TT_RT_FREQ_NEVER = 0 +SQ_TT_RT_FREQ_1024_CLK = 1 +SQ_TT_RT_FREQ_4096_CLK = 2 +SQ_TT_RT_FREQ = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE' +SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = { + 1: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', + 2: 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', +} +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 1 +SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 2 +SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', + 1: 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', +} +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0 +SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 1 +SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE' +SQ_TT_TOKEN_MASK_REG_EXCLUDE__enumvalues = { + 1: 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', + 2: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', + 4: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', +} +SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 1 +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 2 +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 4 +SQ_TT_TOKEN_MASK_REG_EXCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', + 1: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', + 2: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', +} +SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0 +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 1 +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 2 +SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE' +SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = { + 1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT', + 2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT', + 4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', + 8: 'SQ_TT_TOKEN_MASK_COMP_BIT', + 16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', + 32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT', + 64: 'SQ_TT_TOKEN_MASK_ALL_BIT', + 128: 'SQ_TT_TOKEN_MASK_RSVD_BIT', +} +SQ_TT_TOKEN_MASK_SQDEC_BIT = 1 +SQ_TT_TOKEN_MASK_SHDEC_BIT = 2 +SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4 +SQ_TT_TOKEN_MASK_COMP_BIT = 8 +SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16 +SQ_TT_TOKEN_MASK_CONFIG_BIT = 32 +SQ_TT_TOKEN_MASK_ALL_BIT = 64 +SQ_TT_TOKEN_MASK_RSVD_BIT = 128 +SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', + 2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', + 3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT', + 4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', + 5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', + 6: 'SQ_TT_TOKEN_MASK_ALL_SHIFT', + 7: 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', +} +SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0 +SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1 +SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2 +SQ_TT_TOKEN_MASK_COMP_SHIFT = 3 +SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4 +SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5 +SQ_TT_TOKEN_MASK_ALL_SHIFT = 6 +SQ_TT_TOKEN_MASK_RSVD_SHIFT = 7 +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', + 4: 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', + 5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', +} +SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0 +SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1 +SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2 +SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3 +SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 4 +SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5 +SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6 +SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7 +SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8 +SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9 +SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10 +SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11 +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_UTIL_TIMER' +SQ_TT_UTIL_TIMER__enumvalues = { + 0: 'SQ_TT_UTIL_TIMER_100_CLK', + 1: 'SQ_TT_UTIL_TIMER_250_CLK', +} +SQ_TT_UTIL_TIMER_100_CLK = 0 +SQ_TT_UTIL_TIMER_250_CLK = 1 +SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WAVESTART_MODE' +SQ_TT_WAVESTART_MODE__enumvalues = { + 0: 'SQ_TT_WAVESTART_MODE_SHORT', + 1: 'SQ_TT_WAVESTART_MODE_ALLOC', + 2: 'SQ_TT_WAVESTART_MODE_PBB_ID', +} +SQ_TT_WAVESTART_MODE_SHORT = 0 +SQ_TT_WAVESTART_MODE_ALLOC = 1 +SQ_TT_WAVESTART_MODE_PBB_ID = 2 +SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE' +SQ_TT_WTYPE_INCLUDE__enumvalues = { + 1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 2: 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', + 4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 8: 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', + 16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 32: 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', + 64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT', +} +SQ_TT_WTYPE_INCLUDE_PS_BIT = 1 +SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 2 +SQ_TT_WTYPE_INCLUDE_GS_BIT = 4 +SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 8 +SQ_TT_WTYPE_INCLUDE_HS_BIT = 16 +SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 32 +SQ_TT_WTYPE_INCLUDE_CS_BIT = 64 +SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT' +SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', + 1: 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', + 2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', + 3: 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', + 4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', + 5: 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', + 6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', +} +SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0 +SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 1 +SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2 +SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 3 +SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4 +SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 5 +SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6 +SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WATCH_MODES' +SQ_WATCH_MODES__enumvalues = { + 0: 'SQ_WATCH_MODE_READ', + 1: 'SQ_WATCH_MODE_NONREAD', + 2: 'SQ_WATCH_MODE_ATOMIC', + 3: 'SQ_WATCH_MODE_ALL', +} +SQ_WATCH_MODE_READ = 0 +SQ_WATCH_MODE_NONREAD = 1 +SQ_WATCH_MODE_ATOMIC = 2 +SQ_WATCH_MODE_ALL = 3 +SQ_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL' +SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = { + 0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', + 1: 'SQ_WAVE_FWD_PROG_INTERVAL_256', + 2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096', +} +SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0 +SQ_WAVE_FWD_PROG_INTERVAL_256 = 1 +SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2 +SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3 +SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_IB_ECC_ST' +SQ_WAVE_IB_ECC_ST__enumvalues = { + 0: 'SQ_WAVE_IB_ECC_CLEAN', + 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 2: 'SQ_WAVE_IB_ECC_ERR_HALT', + 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', +} +SQ_WAVE_IB_ECC_CLEAN = 0 +SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 +SQ_WAVE_IB_ECC_ERR_HALT = 2 +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 +SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_SCHED_MODES' +SQ_WAVE_SCHED_MODES__enumvalues = { + 0: 'SQ_WAVE_SCHED_MODE_NORMAL', + 1: 'SQ_WAVE_SCHED_MODE_EXPERT', + 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', +} +SQ_WAVE_SCHED_MODE_NORMAL = 0 +SQ_WAVE_SCHED_MODE_EXPERT = 1 +SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2 +SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_TYPE' +SQ_WAVE_TYPE__enumvalues = { + 0: 'SQ_WAVE_TYPE_PS', + 1: 'SQ_WAVE_TYPE_RSVD0', + 2: 'SQ_WAVE_TYPE_GS', + 3: 'SQ_WAVE_TYPE_RSVD1', + 4: 'SQ_WAVE_TYPE_HS', + 5: 'SQ_WAVE_TYPE_RSVD2', + 6: 'SQ_WAVE_TYPE_CS', + 7: 'SQ_WAVE_TYPE_PS1', + 8: 'SQ_WAVE_TYPE_PS2', + 9: 'SQ_WAVE_TYPE_PS3', +} +SQ_WAVE_TYPE_PS = 0 +SQ_WAVE_TYPE_RSVD0 = 1 +SQ_WAVE_TYPE_GS = 2 +SQ_WAVE_TYPE_RSVD1 = 3 +SQ_WAVE_TYPE_HS = 4 +SQ_WAVE_TYPE_RSVD2 = 5 +SQ_WAVE_TYPE_CS = 6 +SQ_WAVE_TYPE_PS1 = 7 +SQ_WAVE_TYPE_PS2 = 8 +SQ_WAVE_TYPE_PS3 = 9 +SQ_WAVE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSCNTL_TYPE' +CSCNTL_TYPE__enumvalues = { + 0: 'CSCNTL_TYPE_TG', + 1: 'CSCNTL_TYPE_STATE', + 2: 'CSCNTL_TYPE_EVENT', + 3: 'CSCNTL_TYPE_PRIVATE', +} +CSCNTL_TYPE_TG = 0 +CSCNTL_TYPE_STATE = 1 +CSCNTL_TYPE_EVENT = 2 +CSCNTL_TYPE_PRIVATE = 3 +CSCNTL_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSDATA_TYPE' +CSDATA_TYPE__enumvalues = { + 0: 'CSDATA_TYPE_TG', + 1: 'CSDATA_TYPE_STATE', + 2: 'CSDATA_TYPE_EVENT', + 3: 'CSDATA_TYPE_PRIVATE', +} +CSDATA_TYPE_TG = 0 +CSDATA_TYPE_STATE = 1 +CSDATA_TYPE_EVENT = 2 +CSDATA_TYPE_PRIVATE = 3 +CSDATA_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GE1_PERFCOUNT_SELECT' +GE1_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge1_assembler_busy', + 1: 'ge1_assembler_stalled', + 2: 'ge1_dma_busy', + 3: 'ge1_dma_lat_bin_0', + 4: 'ge1_dma_lat_bin_1', + 5: 'ge1_dma_lat_bin_2', + 6: 'ge1_dma_lat_bin_3', + 7: 'ge1_dma_lat_bin_4', + 8: 'ge1_dma_lat_bin_5', + 9: 'ge1_dma_lat_bin_6', + 10: 'ge1_dma_lat_bin_7', + 11: 'ge1_dma_return_cl0', + 12: 'ge1_dma_return_cl1', + 13: 'ge1_dma_utcl1_consecutive_retry_event', + 14: 'ge1_dma_utcl1_request_event', + 15: 'ge1_dma_utcl1_retry_event', + 16: 'ge1_dma_utcl1_stall_event', + 17: 'ge1_dma_utcl1_stall_utcl2_event', + 18: 'ge1_dma_utcl1_translation_hit_event', + 19: 'ge1_dma_utcl1_translation_miss_event', + 20: 'ge1_assembler_dma_starved', + 21: 'ge1_rbiu_di_fifo_stalled_p0', + 22: 'ge1_rbiu_di_fifo_starved_p0', + 23: 'ge1_rbiu_dr_fifo_stalled_p0', + 24: 'ge1_rbiu_dr_fifo_starved_p0', + 25: 'ge1_sclk_reg_vld', + 26: 'ge1_stat_busy', + 27: 'ge1_stat_no_dma_busy', + 28: 'ge1_pipe0_to_pipe1', + 29: 'ge1_pipe1_to_pipe0', + 30: 'ge1_dma_return_size_cl0', + 31: 'ge1_dma_return_size_cl1', + 32: 'ge1_small_draws_one_instance', + 33: 'ge1_sclk_input_vld', + 34: 'ge1_prim_group_limit_hit', + 35: 'ge1_unopt_multi_instance_draws', + 36: 'ge1_rbiu_di_fifo_stalled_p1', + 37: 'ge1_rbiu_di_fifo_starved_p1', + 38: 'ge1_rbiu_dr_fifo_stalled_p1', + 39: 'ge1_rbiu_dr_fifo_starved_p1', +} +ge1_assembler_busy = 0 +ge1_assembler_stalled = 1 +ge1_dma_busy = 2 +ge1_dma_lat_bin_0 = 3 +ge1_dma_lat_bin_1 = 4 +ge1_dma_lat_bin_2 = 5 +ge1_dma_lat_bin_3 = 6 +ge1_dma_lat_bin_4 = 7 +ge1_dma_lat_bin_5 = 8 +ge1_dma_lat_bin_6 = 9 +ge1_dma_lat_bin_7 = 10 +ge1_dma_return_cl0 = 11 +ge1_dma_return_cl1 = 12 +ge1_dma_utcl1_consecutive_retry_event = 13 +ge1_dma_utcl1_request_event = 14 +ge1_dma_utcl1_retry_event = 15 +ge1_dma_utcl1_stall_event = 16 +ge1_dma_utcl1_stall_utcl2_event = 17 +ge1_dma_utcl1_translation_hit_event = 18 +ge1_dma_utcl1_translation_miss_event = 19 +ge1_assembler_dma_starved = 20 +ge1_rbiu_di_fifo_stalled_p0 = 21 +ge1_rbiu_di_fifo_starved_p0 = 22 +ge1_rbiu_dr_fifo_stalled_p0 = 23 +ge1_rbiu_dr_fifo_starved_p0 = 24 +ge1_sclk_reg_vld = 25 +ge1_stat_busy = 26 +ge1_stat_no_dma_busy = 27 +ge1_pipe0_to_pipe1 = 28 +ge1_pipe1_to_pipe0 = 29 +ge1_dma_return_size_cl0 = 30 +ge1_dma_return_size_cl1 = 31 +ge1_small_draws_one_instance = 32 +ge1_sclk_input_vld = 33 +ge1_prim_group_limit_hit = 34 +ge1_unopt_multi_instance_draws = 35 +ge1_rbiu_di_fifo_stalled_p1 = 36 +ge1_rbiu_di_fifo_starved_p1 = 37 +ge1_rbiu_dr_fifo_stalled_p1 = 38 +ge1_rbiu_dr_fifo_starved_p1 = 39 +GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT' +GE2_DIST_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_dist_hs_done', + 1: 'ge_dist_hs_done_latency_se0', + 2: 'ge_dist_hs_done_latency_se1', + 3: 'ge_dist_hs_done_latency_se2', + 4: 'ge_dist_hs_done_latency_se3', + 5: 'ge_dist_hs_done_latency_se4', + 6: 'ge_dist_hs_done_latency_se5', + 7: 'ge_dist_hs_done_latency_se6', + 8: 'ge_dist_hs_done_latency_se7', + 9: 'ge_dist_inside_tf_bin_0', + 10: 'ge_dist_inside_tf_bin_1', + 11: 'ge_dist_inside_tf_bin_2', + 12: 'ge_dist_inside_tf_bin_3', + 13: 'ge_dist_inside_tf_bin_4', + 14: 'ge_dist_inside_tf_bin_5', + 15: 'ge_dist_inside_tf_bin_6', + 16: 'ge_dist_inside_tf_bin_7', + 17: 'ge_dist_inside_tf_bin_8', + 18: 'ge_dist_null_patch', + 19: 'ge_dist_sclk_core_vld', + 20: 'ge_dist_sclk_wd_te11_vld', + 21: 'ge_dist_tfreq_lat_bin_0', + 22: 'ge_dist_tfreq_lat_bin_1', + 23: 'ge_dist_tfreq_lat_bin_2', + 24: 'ge_dist_tfreq_lat_bin_3', + 25: 'ge_dist_tfreq_lat_bin_4', + 26: 'ge_dist_tfreq_lat_bin_5', + 27: 'ge_dist_tfreq_lat_bin_6', + 28: 'ge_dist_tfreq_lat_bin_7', + 29: 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 30: 'ge_dist_tfreq_utcl1_request_event', + 31: 'ge_dist_tfreq_utcl1_retry_event', + 32: 'ge_dist_tfreq_utcl1_stall_event', + 33: 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 34: 'ge_dist_tfreq_utcl1_translation_hit_event', + 35: 'ge_dist_tfreq_utcl1_translation_miss_event', + 36: 'ge_dist_vs_pc_stall', + 37: 'ge_dist_pc_feorder_fifo_full', + 38: 'ge_dist_pc_ge_manager_busy', + 39: 'ge_dist_pc_req_stall_se0', + 40: 'ge_dist_pc_req_stall_se1', + 41: 'ge_dist_pc_req_stall_se2', + 42: 'ge_dist_pc_req_stall_se3', + 43: 'ge_dist_pc_req_stall_se4', + 44: 'ge_dist_pc_req_stall_se5', + 45: 'ge_dist_pc_req_stall_se6', + 46: 'ge_dist_pc_req_stall_se7', + 47: 'ge_dist_pc_space_zero', + 48: 'ge_dist_sclk_input_vld', + 49: 'ge_dist_reserved', + 50: 'ge_dist_wd_te11_busy', + 51: 'ge_dist_te11_starved', + 52: 'ge_dist_switch_mode_stall', + 53: 'ge_all_tf_eq', + 54: 'ge_all_tf2', + 55: 'ge_all_tf3', + 56: 'ge_all_tf4', + 57: 'ge_all_tf5', + 58: 'ge_all_tf6', + 59: 'ge_se0_te11_starved_on_hs_done', + 60: 'ge_se1_te11_starved_on_hs_done', + 61: 'ge_se2_te11_starved_on_hs_done', + 62: 'ge_se3_te11_starved_on_hs_done', + 63: 'ge_se4_te11_starved_on_hs_done', + 64: 'ge_se5_te11_starved_on_hs_done', + 65: 'ge_se6_te11_starved_on_hs_done', + 66: 'ge_se7_te11_starved_on_hs_done', + 67: 'ge_dist_op_fifo_full_starve', + 68: 'ge_dist_hs_done_se0', + 69: 'ge_dist_hs_done_se1', + 70: 'ge_dist_hs_done_se2', + 71: 'ge_dist_hs_done_se3', + 72: 'ge_dist_hs_done_se4', + 73: 'ge_dist_hs_done_se5', + 74: 'ge_dist_hs_done_se6', + 75: 'ge_dist_hs_done_se7', + 76: 'ge_dist_hs_done_latency', + 77: 'ge_dist_distributer_busy', + 78: 'ge_tf_ret_data_stalling_hs_done', + 79: 'ge_num_of_no_dist_patches', + 80: 'ge_num_of_donut_dist_patches', + 81: 'ge_num_of_patch_dist_patches', + 82: 'ge_num_of_se_switches_due_to_patch_accum', + 83: 'ge_num_of_se_switches_due_to_donut', + 84: 'ge_num_of_se_switches_due_to_trap', + 85: 'ge_num_of_hs_alloc_events', + 86: 'ge_agm_gcr_req', + 87: 'ge_agm_gcr_tag_stall', + 88: 'ge_agm_gcr_crd_stall', + 89: 'ge_agm_gcr_stall', + 90: 'ge_agm_gcr_latency', + 91: 'ge_distclk_vld', +} +ge_dist_hs_done = 0 +ge_dist_hs_done_latency_se0 = 1 +ge_dist_hs_done_latency_se1 = 2 +ge_dist_hs_done_latency_se2 = 3 +ge_dist_hs_done_latency_se3 = 4 +ge_dist_hs_done_latency_se4 = 5 +ge_dist_hs_done_latency_se5 = 6 +ge_dist_hs_done_latency_se6 = 7 +ge_dist_hs_done_latency_se7 = 8 +ge_dist_inside_tf_bin_0 = 9 +ge_dist_inside_tf_bin_1 = 10 +ge_dist_inside_tf_bin_2 = 11 +ge_dist_inside_tf_bin_3 = 12 +ge_dist_inside_tf_bin_4 = 13 +ge_dist_inside_tf_bin_5 = 14 +ge_dist_inside_tf_bin_6 = 15 +ge_dist_inside_tf_bin_7 = 16 +ge_dist_inside_tf_bin_8 = 17 +ge_dist_null_patch = 18 +ge_dist_sclk_core_vld = 19 +ge_dist_sclk_wd_te11_vld = 20 +ge_dist_tfreq_lat_bin_0 = 21 +ge_dist_tfreq_lat_bin_1 = 22 +ge_dist_tfreq_lat_bin_2 = 23 +ge_dist_tfreq_lat_bin_3 = 24 +ge_dist_tfreq_lat_bin_4 = 25 +ge_dist_tfreq_lat_bin_5 = 26 +ge_dist_tfreq_lat_bin_6 = 27 +ge_dist_tfreq_lat_bin_7 = 28 +ge_dist_tfreq_utcl1_consecutive_retry_event = 29 +ge_dist_tfreq_utcl1_request_event = 30 +ge_dist_tfreq_utcl1_retry_event = 31 +ge_dist_tfreq_utcl1_stall_event = 32 +ge_dist_tfreq_utcl1_stall_utcl2_event = 33 +ge_dist_tfreq_utcl1_translation_hit_event = 34 +ge_dist_tfreq_utcl1_translation_miss_event = 35 +ge_dist_vs_pc_stall = 36 +ge_dist_pc_feorder_fifo_full = 37 +ge_dist_pc_ge_manager_busy = 38 +ge_dist_pc_req_stall_se0 = 39 +ge_dist_pc_req_stall_se1 = 40 +ge_dist_pc_req_stall_se2 = 41 +ge_dist_pc_req_stall_se3 = 42 +ge_dist_pc_req_stall_se4 = 43 +ge_dist_pc_req_stall_se5 = 44 +ge_dist_pc_req_stall_se6 = 45 +ge_dist_pc_req_stall_se7 = 46 +ge_dist_pc_space_zero = 47 +ge_dist_sclk_input_vld = 48 +ge_dist_reserved = 49 +ge_dist_wd_te11_busy = 50 +ge_dist_te11_starved = 51 +ge_dist_switch_mode_stall = 52 +ge_all_tf_eq = 53 +ge_all_tf2 = 54 +ge_all_tf3 = 55 +ge_all_tf4 = 56 +ge_all_tf5 = 57 +ge_all_tf6 = 58 +ge_se0_te11_starved_on_hs_done = 59 +ge_se1_te11_starved_on_hs_done = 60 +ge_se2_te11_starved_on_hs_done = 61 +ge_se3_te11_starved_on_hs_done = 62 +ge_se4_te11_starved_on_hs_done = 63 +ge_se5_te11_starved_on_hs_done = 64 +ge_se6_te11_starved_on_hs_done = 65 +ge_se7_te11_starved_on_hs_done = 66 +ge_dist_op_fifo_full_starve = 67 +ge_dist_hs_done_se0 = 68 +ge_dist_hs_done_se1 = 69 +ge_dist_hs_done_se2 = 70 +ge_dist_hs_done_se3 = 71 +ge_dist_hs_done_se4 = 72 +ge_dist_hs_done_se5 = 73 +ge_dist_hs_done_se6 = 74 +ge_dist_hs_done_se7 = 75 +ge_dist_hs_done_latency = 76 +ge_dist_distributer_busy = 77 +ge_tf_ret_data_stalling_hs_done = 78 +ge_num_of_no_dist_patches = 79 +ge_num_of_donut_dist_patches = 80 +ge_num_of_patch_dist_patches = 81 +ge_num_of_se_switches_due_to_patch_accum = 82 +ge_num_of_se_switches_due_to_donut = 83 +ge_num_of_se_switches_due_to_trap = 84 +ge_num_of_hs_alloc_events = 85 +ge_agm_gcr_req = 86 +ge_agm_gcr_tag_stall = 87 +ge_agm_gcr_crd_stall = 88 +ge_agm_gcr_stall = 89 +ge_agm_gcr_latency = 90 +ge_distclk_vld = 91 +GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_SE_PERFCOUNT_SELECT' +GE2_SE_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_se_ds_prims', + 1: 'ge_se_es_thread_groups', + 2: 'ge_se_esvert_stalled_gsprim', + 3: 'ge_se_hs_tfm_stall', + 4: 'ge_se_hs_tgs_active_high_water_mark', + 5: 'ge_se_hs_thread_groups', + 6: 'ge_se_reused_es_indices', + 7: 'ge_se_sclk_ngg_vld', + 8: 'ge_se_sclk_te11_vld', + 9: 'ge_se_spi_esvert_eov', + 10: 'ge_se_spi_esvert_stalled', + 11: 'ge_se_spi_esvert_starved_busy', + 12: 'ge_se_spi_esvert_valid', + 13: 'ge_se_spi_gsprim_cont', + 14: 'ge_se_spi_gsprim_eov', + 15: 'ge_se_spi_gsprim_stalled', + 16: 'ge_se_spi_gsprim_starved_busy', + 17: 'ge_se_spi_gsprim_valid', + 18: 'ge_se_spi_gssubgrp_is_event', + 19: 'ge_se_spi_gssubgrp_send', + 20: 'ge_se_spi_hsvert_eov', + 21: 'ge_se_spi_hsvert_stalled', + 22: 'ge_se_spi_hsvert_starved_busy', + 23: 'ge_se_spi_hsvert_valid', + 24: 'ge_se_spi_hswave_is_event', + 25: 'ge_se_spi_hswave_send', + 26: 'ge_se_spi_lsvert_eov', + 27: 'ge_se_spi_lsvert_stalled', + 28: 'ge_se_spi_lsvert_starved_busy', + 29: 'ge_se_spi_lsvert_valid', + 30: 'ge_se_spi_hsvert_fifo_full_stall', + 31: 'ge_se_spi_tgrp_fifo_stall', + 32: 'ge_spi_hsgrp_spi_stall', + 33: 'ge_se_spi_gssubgrp_event_window_active', + 34: 'ge_se_hs_input_stall', + 35: 'ge_se_sending_vert_or_prim', + 36: 'ge_se_sclk_input_vld', + 37: 'ge_spi_lswave_fifo_full_stall', + 38: 'ge_spi_hswave_fifo_full_stall', + 39: 'ge_hs_tif_stall', + 40: 'ge_csb_spi_bp', + 41: 'ge_ngg_starving_for_pc_grant', + 42: 'ge_pa0_csb_eop', + 43: 'ge_pa1_csb_eop', + 44: 'ge_ngg_starved_idle', + 45: 'ge_gsprim_send', + 46: 'ge_esvert_send', + 47: 'ge_ngg_starved_after_work', + 48: 'ge_ngg_subgrp_fifo_stall', + 49: 'ge_ngg_ord_id_req_stall', + 50: 'ge_ngg_indx_bus_stall', + 51: 'ge_hs_stall_tfmm_fifo_full', + 52: 'ge_gs_issue_rtr_stalled', + 53: 'ge_gsprim_stalled_esvert', + 54: 'ge_gsthread_stalled', + 55: 'ge_te11_stall_prim_funnel', + 56: 'ge_te11_stall_vert_funnel', + 57: 'ge_ngg_attr_grp_alloc', + 58: 'ge_ngg_attr_discard_alloc', + 59: 'ge_ngg_pc_space_not_avail', + 60: 'ge_ngg_agm_req_stall', + 61: 'ge_ngg_spi_esvert_partial_eov', + 62: 'ge_ngg_spi_gsprim_partial_eov', + 63: 'ge_spi_gsgrp_valid', + 64: 'ge_ngg_attr_grp_latency', + 65: 'ge_ngg_reuse_prim_limit_hit', + 66: 'ge_ngg_reuse_vert_limit_hit', + 67: 'ge_te11_con_stall', + 68: 'ge_te11_compactor_starved', + 69: 'ge_ngg_stall_tess_off_tess_on', + 70: 'ge_ngg_stall_tess_on_tess_off', +} +ge_se_ds_prims = 0 +ge_se_es_thread_groups = 1 +ge_se_esvert_stalled_gsprim = 2 +ge_se_hs_tfm_stall = 3 +ge_se_hs_tgs_active_high_water_mark = 4 +ge_se_hs_thread_groups = 5 +ge_se_reused_es_indices = 6 +ge_se_sclk_ngg_vld = 7 +ge_se_sclk_te11_vld = 8 +ge_se_spi_esvert_eov = 9 +ge_se_spi_esvert_stalled = 10 +ge_se_spi_esvert_starved_busy = 11 +ge_se_spi_esvert_valid = 12 +ge_se_spi_gsprim_cont = 13 +ge_se_spi_gsprim_eov = 14 +ge_se_spi_gsprim_stalled = 15 +ge_se_spi_gsprim_starved_busy = 16 +ge_se_spi_gsprim_valid = 17 +ge_se_spi_gssubgrp_is_event = 18 +ge_se_spi_gssubgrp_send = 19 +ge_se_spi_hsvert_eov = 20 +ge_se_spi_hsvert_stalled = 21 +ge_se_spi_hsvert_starved_busy = 22 +ge_se_spi_hsvert_valid = 23 +ge_se_spi_hswave_is_event = 24 +ge_se_spi_hswave_send = 25 +ge_se_spi_lsvert_eov = 26 +ge_se_spi_lsvert_stalled = 27 +ge_se_spi_lsvert_starved_busy = 28 +ge_se_spi_lsvert_valid = 29 +ge_se_spi_hsvert_fifo_full_stall = 30 +ge_se_spi_tgrp_fifo_stall = 31 +ge_spi_hsgrp_spi_stall = 32 +ge_se_spi_gssubgrp_event_window_active = 33 +ge_se_hs_input_stall = 34 +ge_se_sending_vert_or_prim = 35 +ge_se_sclk_input_vld = 36 +ge_spi_lswave_fifo_full_stall = 37 +ge_spi_hswave_fifo_full_stall = 38 +ge_hs_tif_stall = 39 +ge_csb_spi_bp = 40 +ge_ngg_starving_for_pc_grant = 41 +ge_pa0_csb_eop = 42 +ge_pa1_csb_eop = 43 +ge_ngg_starved_idle = 44 +ge_gsprim_send = 45 +ge_esvert_send = 46 +ge_ngg_starved_after_work = 47 +ge_ngg_subgrp_fifo_stall = 48 +ge_ngg_ord_id_req_stall = 49 +ge_ngg_indx_bus_stall = 50 +ge_hs_stall_tfmm_fifo_full = 51 +ge_gs_issue_rtr_stalled = 52 +ge_gsprim_stalled_esvert = 53 +ge_gsthread_stalled = 54 +ge_te11_stall_prim_funnel = 55 +ge_te11_stall_vert_funnel = 56 +ge_ngg_attr_grp_alloc = 57 +ge_ngg_attr_discard_alloc = 58 +ge_ngg_pc_space_not_avail = 59 +ge_ngg_agm_req_stall = 60 +ge_ngg_spi_esvert_partial_eov = 61 +ge_ngg_spi_gsprim_partial_eov = 62 +ge_spi_gsgrp_valid = 63 +ge_ngg_attr_grp_latency = 64 +ge_ngg_reuse_prim_limit_hit = 65 +ge_ngg_reuse_vert_limit_hit = 66 +ge_te11_con_stall = 67 +ge_te11_compactor_starved = 68 +ge_ngg_stall_tess_off_tess_on = 69 +ge_ngg_stall_tess_on_tess_off = 70 +GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ONE' +VGT_DETECT_ONE__enumvalues = { + 0: 'ENABLE_TF1_OPT', + 1: 'DISABLE_TF1_OPT', +} +ENABLE_TF1_OPT = 0 +DISABLE_TF1_OPT = 1 +VGT_DETECT_ONE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ZERO' +VGT_DETECT_ZERO__enumvalues = { + 0: 'ENABLE_TF0_OPT', + 1: 'DISABLE_TF0_OPT', +} +ENABLE_TF0_OPT = 0 +DISABLE_TF0_OPT = 1 +VGT_DETECT_ZERO = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DIST_MODE' +VGT_DIST_MODE__enumvalues = { + 0: 'NO_DIST', + 1: 'PATCHES', + 2: 'DONUTS', + 3: 'TRAPEZOIDS', +} +NO_DIST = 0 +PATCHES = 1 +DONUTS = 2 +TRAPEZOIDS = 3 +VGT_DIST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_INDEX_SIZE' +VGT_DI_INDEX_SIZE__enumvalues = { + 0: 'DI_INDEX_SIZE_16_BIT', + 1: 'DI_INDEX_SIZE_32_BIT', + 2: 'DI_INDEX_SIZE_8_BIT', +} +DI_INDEX_SIZE_16_BIT = 0 +DI_INDEX_SIZE_32_BIT = 1 +DI_INDEX_SIZE_8_BIT = 2 +VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' +VGT_DI_MAJOR_MODE_SELECT__enumvalues = { + 0: 'DI_MAJOR_MODE_0', + 1: 'DI_MAJOR_MODE_1', +} +DI_MAJOR_MODE_0 = 0 +DI_MAJOR_MODE_1 = 1 +VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_PRIM_TYPE' +VGT_DI_PRIM_TYPE__enumvalues = { + 0: 'DI_PT_NONE', + 1: 'DI_PT_POINTLIST', + 2: 'DI_PT_LINELIST', + 3: 'DI_PT_LINESTRIP', + 4: 'DI_PT_TRILIST', + 5: 'DI_PT_TRIFAN', + 6: 'DI_PT_TRISTRIP', + 7: 'DI_PT_2D_RECTANGLE', + 8: 'DI_PT_UNUSED_1', + 9: 'DI_PT_PATCH', + 10: 'DI_PT_LINELIST_ADJ', + 11: 'DI_PT_LINESTRIP_ADJ', + 12: 'DI_PT_TRILIST_ADJ', + 13: 'DI_PT_TRISTRIP_ADJ', + 14: 'DI_PT_UNUSED_3', + 15: 'DI_PT_UNUSED_4', + 16: 'DI_PT_UNUSED_5', + 17: 'DI_PT_RECTLIST', + 18: 'DI_PT_LINELOOP', + 19: 'DI_PT_QUADLIST', + 20: 'DI_PT_QUADSTRIP', + 21: 'DI_PT_POLYGON', +} +DI_PT_NONE = 0 +DI_PT_POINTLIST = 1 +DI_PT_LINELIST = 2 +DI_PT_LINESTRIP = 3 +DI_PT_TRILIST = 4 +DI_PT_TRIFAN = 5 +DI_PT_TRISTRIP = 6 +DI_PT_2D_RECTANGLE = 7 +DI_PT_UNUSED_1 = 8 +DI_PT_PATCH = 9 +DI_PT_LINELIST_ADJ = 10 +DI_PT_LINESTRIP_ADJ = 11 +DI_PT_TRILIST_ADJ = 12 +DI_PT_TRISTRIP_ADJ = 13 +DI_PT_UNUSED_3 = 14 +DI_PT_UNUSED_4 = 15 +DI_PT_UNUSED_5 = 16 +DI_PT_RECTLIST = 17 +DI_PT_LINELOOP = 18 +DI_PT_QUADLIST = 19 +DI_PT_QUADSTRIP = 20 +DI_PT_POLYGON = 21 +VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_SOURCE_SELECT' +VGT_DI_SOURCE_SELECT__enumvalues = { + 0: 'DI_SRC_SEL_DMA', + 1: 'DI_SRC_SEL_IMMEDIATE', + 2: 'DI_SRC_SEL_AUTO_INDEX', + 3: 'DI_SRC_SEL_RESERVED', +} +DI_SRC_SEL_DMA = 0 +DI_SRC_SEL_IMMEDIATE = 1 +DI_SRC_SEL_AUTO_INDEX = 2 +DI_SRC_SEL_RESERVED = 3 +VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_BUF_TYPE' +VGT_DMA_BUF_TYPE__enumvalues = { + 0: 'VGT_DMA_BUF_MEM', + 1: 'VGT_DMA_BUF_RING', + 2: 'VGT_DMA_BUF_SETUP', + 3: 'VGT_DMA_PTR_UPDATE', +} +VGT_DMA_BUF_MEM = 0 +VGT_DMA_BUF_RING = 1 +VGT_DMA_BUF_SETUP = 2 +VGT_DMA_PTR_UPDATE = 3 +VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_SWAP_MODE' +VGT_DMA_SWAP_MODE__enumvalues = { + 0: 'VGT_DMA_SWAP_NONE', + 1: 'VGT_DMA_SWAP_16_BIT', + 2: 'VGT_DMA_SWAP_32_BIT', + 3: 'VGT_DMA_SWAP_WORD', +} +VGT_DMA_SWAP_NONE = 0 +VGT_DMA_SWAP_16_BIT = 1 +VGT_DMA_SWAP_32_BIT = 2 +VGT_DMA_SWAP_WORD = 3 +VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_EVENT_TYPE' +VGT_EVENT_TYPE__enumvalues = { + 0: 'Reserved_0x00', + 1: 'SAMPLE_STREAMOUTSTATS1', + 2: 'SAMPLE_STREAMOUTSTATS2', + 3: 'SAMPLE_STREAMOUTSTATS3', + 4: 'CACHE_FLUSH_TS', + 5: 'CONTEXT_DONE', + 6: 'CACHE_FLUSH', + 7: 'CS_PARTIAL_FLUSH', + 8: 'VGT_STREAMOUT_SYNC', + 9: 'Reserved_0x09', + 10: 'VGT_STREAMOUT_RESET', + 11: 'END_OF_PIPE_INCR_DE', + 12: 'END_OF_PIPE_IB_END', + 13: 'RST_PIX_CNT', + 14: 'BREAK_BATCH', + 15: 'VS_PARTIAL_FLUSH', + 16: 'PS_PARTIAL_FLUSH', + 17: 'FLUSH_HS_OUTPUT', + 18: 'FLUSH_DFSM', + 19: 'RESET_TO_LOWEST_VGT', + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', + 21: 'WAIT_SYNC', + 22: 'CACHE_FLUSH_AND_INV_EVENT', + 23: 'PERFCOUNTER_START', + 24: 'PERFCOUNTER_STOP', + 25: 'PIPELINESTAT_START', + 26: 'PIPELINESTAT_STOP', + 27: 'PERFCOUNTER_SAMPLE', + 28: 'FLUSH_ES_OUTPUT', + 29: 'BIN_CONF_OVERRIDE_CHECK', + 30: 'SAMPLE_PIPELINESTAT', + 31: 'SO_VGTSTREAMOUT_FLUSH', + 32: 'SAMPLE_STREAMOUTSTATS', + 33: 'RESET_VTX_CNT', + 34: 'BLOCK_CONTEXT_DONE', + 35: 'CS_CONTEXT_DONE', + 36: 'VGT_FLUSH', + 37: 'TGID_ROLLOVER', + 38: 'SQ_NON_EVENT', + 39: 'SC_SEND_DB_VPZ', + 40: 'BOTTOM_OF_PIPE_TS', + 41: 'FLUSH_SX_TS', + 42: 'DB_CACHE_FLUSH_AND_INV', + 43: 'FLUSH_AND_INV_DB_DATA_TS', + 44: 'FLUSH_AND_INV_DB_META', + 45: 'FLUSH_AND_INV_CB_DATA_TS', + 46: 'FLUSH_AND_INV_CB_META', + 47: 'CS_DONE', + 48: 'PS_DONE', + 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', + 50: 'SX_CB_RAT_ACK_REQUEST', + 51: 'THREAD_TRACE_START', + 52: 'THREAD_TRACE_STOP', + 53: 'THREAD_TRACE_MARKER', + 54: 'THREAD_TRACE_DRAW', + 55: 'THREAD_TRACE_FINISH', + 56: 'PIXEL_PIPE_STAT_CONTROL', + 57: 'PIXEL_PIPE_STAT_DUMP', + 58: 'PIXEL_PIPE_STAT_RESET', + 59: 'CONTEXT_SUSPEND', + 60: 'OFFCHIP_HS_DEALLOC', + 61: 'ENABLE_NGG_PIPELINE', + 62: 'ENABLE_LEGACY_PIPELINE', + 63: 'DRAW_DONE', +} +Reserved_0x00 = 0 +SAMPLE_STREAMOUTSTATS1 = 1 +SAMPLE_STREAMOUTSTATS2 = 2 +SAMPLE_STREAMOUTSTATS3 = 3 +CACHE_FLUSH_TS = 4 +CONTEXT_DONE = 5 +CACHE_FLUSH = 6 +CS_PARTIAL_FLUSH = 7 +VGT_STREAMOUT_SYNC = 8 +Reserved_0x09 = 9 +VGT_STREAMOUT_RESET = 10 +END_OF_PIPE_INCR_DE = 11 +END_OF_PIPE_IB_END = 12 +RST_PIX_CNT = 13 +BREAK_BATCH = 14 +VS_PARTIAL_FLUSH = 15 +PS_PARTIAL_FLUSH = 16 +FLUSH_HS_OUTPUT = 17 +FLUSH_DFSM = 18 +RESET_TO_LOWEST_VGT = 19 +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +WAIT_SYNC = 21 +CACHE_FLUSH_AND_INV_EVENT = 22 +PERFCOUNTER_START = 23 +PERFCOUNTER_STOP = 24 +PIPELINESTAT_START = 25 +PIPELINESTAT_STOP = 26 +PERFCOUNTER_SAMPLE = 27 +FLUSH_ES_OUTPUT = 28 +BIN_CONF_OVERRIDE_CHECK = 29 +SAMPLE_PIPELINESTAT = 30 +SO_VGTSTREAMOUT_FLUSH = 31 +SAMPLE_STREAMOUTSTATS = 32 +RESET_VTX_CNT = 33 +BLOCK_CONTEXT_DONE = 34 +CS_CONTEXT_DONE = 35 +VGT_FLUSH = 36 +TGID_ROLLOVER = 37 +SQ_NON_EVENT = 38 +SC_SEND_DB_VPZ = 39 +BOTTOM_OF_PIPE_TS = 40 +FLUSH_SX_TS = 41 +DB_CACHE_FLUSH_AND_INV = 42 +FLUSH_AND_INV_DB_DATA_TS = 43 +FLUSH_AND_INV_DB_META = 44 +FLUSH_AND_INV_CB_DATA_TS = 45 +FLUSH_AND_INV_CB_META = 46 +CS_DONE = 47 +PS_DONE = 48 +FLUSH_AND_INV_CB_PIXEL_DATA = 49 +SX_CB_RAT_ACK_REQUEST = 50 +THREAD_TRACE_START = 51 +THREAD_TRACE_STOP = 52 +THREAD_TRACE_MARKER = 53 +THREAD_TRACE_DRAW = 54 +THREAD_TRACE_FINISH = 55 +PIXEL_PIPE_STAT_CONTROL = 56 +PIXEL_PIPE_STAT_DUMP = 57 +PIXEL_PIPE_STAT_RESET = 58 +CONTEXT_SUSPEND = 59 +OFFCHIP_HS_DEALLOC = 60 +ENABLE_NGG_PIPELINE = 61 +ENABLE_LEGACY_PIPELINE = 62 +DRAW_DONE = 63 +VGT_EVENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GROUP_CONV_SEL' +VGT_GROUP_CONV_SEL__enumvalues = { + 0: 'VGT_GRP_INDEX_16', + 1: 'VGT_GRP_INDEX_32', + 2: 'VGT_GRP_UINT_16', + 3: 'VGT_GRP_UINT_32', + 4: 'VGT_GRP_SINT_16', + 5: 'VGT_GRP_SINT_32', + 6: 'VGT_GRP_FLOAT_32', + 7: 'VGT_GRP_AUTO_PRIM', + 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', +} +VGT_GRP_INDEX_16 = 0 +VGT_GRP_INDEX_32 = 1 +VGT_GRP_UINT_16 = 2 +VGT_GRP_UINT_32 = 3 +VGT_GRP_SINT_16 = 4 +VGT_GRP_SINT_32 = 5 +VGT_GRP_FLOAT_32 = 6 +VGT_GRP_AUTO_PRIM = 7 +VGT_GRP_FIX_1_23_TO_FLOAT = 8 +VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_MODE_TYPE' +VGT_GS_MODE_TYPE__enumvalues = { + 0: 'GS_OFF', + 1: 'GS_SCENARIO_A', + 2: 'GS_SCENARIO_B', + 3: 'GS_SCENARIO_G', + 4: 'GS_SCENARIO_C', + 5: 'SPRITE_EN', +} +GS_OFF = 0 +GS_SCENARIO_A = 1 +GS_SCENARIO_B = 2 +GS_SCENARIO_G = 3 +GS_SCENARIO_C = 4 +SPRITE_EN = 5 +VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_OUTPRIM_TYPE' +VGT_GS_OUTPRIM_TYPE__enumvalues = { + 0: 'POINTLIST', + 1: 'LINESTRIP', + 2: 'TRISTRIP', + 3: 'RECT_2D', + 4: 'RECTLIST', +} +POINTLIST = 0 +LINESTRIP = 1 +TRISTRIP = 2 +RECT_2D = 3 +RECTLIST = 4 +VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_INDEX_TYPE_MODE' +VGT_INDEX_TYPE_MODE__enumvalues = { + 0: 'VGT_INDEX_16', + 1: 'VGT_INDEX_32', + 2: 'VGT_INDEX_8', +} +VGT_INDEX_16 = 0 +VGT_INDEX_32 = 1 +VGT_INDEX_8 = 2 +VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUTPATH_SELECT' +VGT_OUTPATH_SELECT__enumvalues = { + 0: 'VGT_OUTPATH_VTX_REUSE', + 1: 'VGT_OUTPATH_GS_BLOCK', + 2: 'VGT_OUTPATH_HS_BLOCK', + 3: 'VGT_OUTPATH_PRIM_GEN', + 4: 'VGT_OUTPATH_TE_PRIM_GEN', + 5: 'VGT_OUTPATH_TE_GS_BLOCK', + 6: 'VGT_OUTPATH_TE_OUTPUT', +} +VGT_OUTPATH_VTX_REUSE = 0 +VGT_OUTPATH_GS_BLOCK = 1 +VGT_OUTPATH_HS_BLOCK = 2 +VGT_OUTPATH_PRIM_GEN = 3 +VGT_OUTPATH_TE_PRIM_GEN = 4 +VGT_OUTPATH_TE_GS_BLOCK = 5 +VGT_OUTPATH_TE_OUTPUT = 6 +VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUT_PRIM_TYPE' +VGT_OUT_PRIM_TYPE__enumvalues = { + 0: 'VGT_OUT_POINT', + 1: 'VGT_OUT_LINE', + 2: 'VGT_OUT_TRI', + 3: 'VGT_OUT_RECT_V0', + 4: 'VGT_OUT_RECT_V1', + 5: 'VGT_OUT_RECT_V2', + 6: 'VGT_OUT_RECT_V3', + 7: 'VGT_OUT_2D_RECT', + 8: 'VGT_TE_QUAD', + 9: 'VGT_TE_PRIM_INDEX_LINE', + 10: 'VGT_TE_PRIM_INDEX_TRI', + 11: 'VGT_TE_PRIM_INDEX_QUAD', + 12: 'VGT_OUT_LINE_ADJ', + 13: 'VGT_OUT_TRI_ADJ', + 14: 'VGT_OUT_PATCH', +} +VGT_OUT_POINT = 0 +VGT_OUT_LINE = 1 +VGT_OUT_TRI = 2 +VGT_OUT_RECT_V0 = 3 +VGT_OUT_RECT_V1 = 4 +VGT_OUT_RECT_V2 = 5 +VGT_OUT_RECT_V3 = 6 +VGT_OUT_2D_RECT = 7 +VGT_TE_QUAD = 8 +VGT_TE_PRIM_INDEX_LINE = 9 +VGT_TE_PRIM_INDEX_TRI = 10 +VGT_TE_PRIM_INDEX_QUAD = 11 +VGT_OUT_LINE_ADJ = 12 +VGT_OUT_TRI_ADJ = 13 +VGT_OUT_PATCH = 14 +VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_RDREQ_POLICY' +VGT_RDREQ_POLICY__enumvalues = { + 0: 'VGT_POLICY_LRU', + 1: 'VGT_POLICY_STREAM', + 2: 'VGT_POLICY_BYPASS', +} +VGT_POLICY_LRU = 0 +VGT_POLICY_STREAM = 1 +VGT_POLICY_BYPASS = 2 +VGT_RDREQ_POLICY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_ES_EN' +VGT_STAGES_ES_EN__enumvalues = { + 0: 'ES_STAGE_OFF', + 1: 'ES_STAGE_DS', + 2: 'ES_STAGE_REAL', + 3: 'RESERVED_ES', +} +ES_STAGE_OFF = 0 +ES_STAGE_DS = 1 +ES_STAGE_REAL = 2 +RESERVED_ES = 3 +VGT_STAGES_ES_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_GS_EN' +VGT_STAGES_GS_EN__enumvalues = { + 0: 'GS_STAGE_OFF', + 1: 'GS_STAGE_ON', +} +GS_STAGE_OFF = 0 +GS_STAGE_ON = 1 +VGT_STAGES_GS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_HS_EN' +VGT_STAGES_HS_EN__enumvalues = { + 0: 'HS_STAGE_OFF', + 1: 'HS_STAGE_ON', +} +HS_STAGE_OFF = 0 +HS_STAGE_ON = 1 +VGT_STAGES_HS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_LS_EN' +VGT_STAGES_LS_EN__enumvalues = { + 0: 'LS_STAGE_OFF', + 1: 'LS_STAGE_ON', + 2: 'CS_STAGE_ON', + 3: 'RESERVED_LS', +} +LS_STAGE_OFF = 0 +LS_STAGE_ON = 1 +CS_STAGE_ON = 2 +RESERVED_LS = 3 +VGT_STAGES_LS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_VS_EN' +VGT_STAGES_VS_EN__enumvalues = { + 0: 'VS_STAGE_REAL', + 1: 'VS_STAGE_DS', + 2: 'VS_STAGE_COPY_SHADER', + 3: 'RESERVED_VS', +} +VS_STAGE_REAL = 0 +VS_STAGE_DS = 1 +VS_STAGE_COPY_SHADER = 2 +RESERVED_VS = 3 +VGT_STAGES_VS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_PARTITION' +VGT_TESS_PARTITION__enumvalues = { + 0: 'PART_INTEGER', + 1: 'PART_POW2', + 2: 'PART_FRAC_ODD', + 3: 'PART_FRAC_EVEN', +} +PART_INTEGER = 0 +PART_POW2 = 1 +PART_FRAC_ODD = 2 +PART_FRAC_EVEN = 3 +VGT_TESS_PARTITION = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TOPOLOGY' +VGT_TESS_TOPOLOGY__enumvalues = { + 0: 'OUTPUT_POINT', + 1: 'OUTPUT_LINE', + 2: 'OUTPUT_TRIANGLE_CW', + 3: 'OUTPUT_TRIANGLE_CCW', +} +OUTPUT_POINT = 0 +OUTPUT_LINE = 1 +OUTPUT_TRIANGLE_CW = 2 +OUTPUT_TRIANGLE_CCW = 3 +VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TYPE' +VGT_TESS_TYPE__enumvalues = { + 0: 'TESS_ISOLINE', + 1: 'TESS_TRIANGLE', + 2: 'TESS_QUAD', +} +TESS_ISOLINE = 0 +TESS_TRIANGLE = 1 +TESS_QUAD = 2 +VGT_TESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_REG_XFER' +WD_IA_DRAW_REG_XFER__enumvalues = { + 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 4: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 5: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 6: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 7: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 8: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', +} +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 +WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2 +WD_IA_DRAW_REG_XFER_GE_CNTL = 3 +WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 4 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 5 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 6 +WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 7 +WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 8 +WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_SOURCE' +WD_IA_DRAW_SOURCE__enumvalues = { + 0: 'WD_IA_DRAW_SOURCE_DMA', + 1: 'WD_IA_DRAW_SOURCE_IMMD', + 2: 'WD_IA_DRAW_SOURCE_AUTO', + 3: 'WD_IA_DRAW_SOURCE_OPAQ', +} +WD_IA_DRAW_SOURCE_DMA = 0 +WD_IA_DRAW_SOURCE_IMMD = 1 +WD_IA_DRAW_SOURCE_AUTO = 2 +WD_IA_DRAW_SOURCE_OPAQ = 3 +WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_TYPE' +WD_IA_DRAW_TYPE__enumvalues = { + 0: 'WD_IA_DRAW_TYPE_DI_MM0', + 1: 'WD_IA_DRAW_TYPE_REG_XFER', + 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', + 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 4: 'WD_IA_DRAW_TYPE_MIN_INDX', + 5: 'WD_IA_DRAW_TYPE_MAX_INDX', + 6: 'WD_IA_DRAW_TYPE_INDX_OFF', + 7: 'WD_IA_DRAW_TYPE_IMM_DATA', +} +WD_IA_DRAW_TYPE_DI_MM0 = 0 +WD_IA_DRAW_TYPE_REG_XFER = 1 +WD_IA_DRAW_TYPE_EVENT_INIT = 2 +WD_IA_DRAW_TYPE_EVENT_ADDR = 3 +WD_IA_DRAW_TYPE_MIN_INDX = 4 +WD_IA_DRAW_TYPE_MAX_INDX = 5 +WD_IA_DRAW_TYPE_INDX_OFF = 6 +WD_IA_DRAW_TYPE_IMM_DATA = 7 +WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GB_EDC_DED_MODE' +GB_EDC_DED_MODE__enumvalues = { + 0: 'GB_EDC_DED_MODE_LOG', + 1: 'GB_EDC_DED_MODE_HALT', + 2: 'GB_EDC_DED_MODE_INT_HALT', +} +GB_EDC_DED_MODE_LOG = 0 +GB_EDC_DED_MODE_HALT = 1 +GB_EDC_DED_MODE_INT_HALT = 2 +GB_EDC_DED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CHA_PERF_SEL' +CHA_PERF_SEL__enumvalues = { + 0: 'CHA_PERF_SEL_BUSY', + 1: 'CHA_PERF_SEL_STALL_CHC0', + 2: 'CHA_PERF_SEL_STALL_CHC1', + 3: 'CHA_PERF_SEL_STALL_CHC2', + 4: 'CHA_PERF_SEL_STALL_CHC3', + 5: 'CHA_PERF_SEL_STALL_CHC4', + 6: 'CHA_PERF_SEL_STALL_CHC5', + 7: 'CHA_PERF_SEL_REQUEST_CHC0', + 8: 'CHA_PERF_SEL_REQUEST_CHC1', + 9: 'CHA_PERF_SEL_REQUEST_CHC2', + 10: 'CHA_PERF_SEL_REQUEST_CHC3', + 11: 'CHA_PERF_SEL_REQUEST_CHC4', + 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', + 13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', + 15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', + 19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', + 21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', + 27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 32: 'CHA_PERF_SEL_ARB_REQUESTS', + 33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', + 39: 'CHA_PERF_SEL_CYCLE', +} +CHA_PERF_SEL_BUSY = 0 +CHA_PERF_SEL_STALL_CHC0 = 1 +CHA_PERF_SEL_STALL_CHC1 = 2 +CHA_PERF_SEL_STALL_CHC2 = 3 +CHA_PERF_SEL_STALL_CHC3 = 4 +CHA_PERF_SEL_STALL_CHC4 = 5 +CHA_PERF_SEL_STALL_CHC5 = 6 +CHA_PERF_SEL_REQUEST_CHC0 = 7 +CHA_PERF_SEL_REQUEST_CHC1 = 8 +CHA_PERF_SEL_REQUEST_CHC2 = 9 +CHA_PERF_SEL_REQUEST_CHC3 = 10 +CHA_PERF_SEL_REQUEST_CHC4 = 11 +CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12 +CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13 +CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14 +CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15 +CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16 +CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17 +CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18 +CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19 +CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20 +CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26 +CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27 +CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28 +CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29 +CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30 +CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31 +CHA_PERF_SEL_ARB_REQUESTS = 32 +CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38 +CHA_PERF_SEL_CYCLE = 39 +CHA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHCG_PERF_SEL' +CHCG_PERF_SEL__enumvalues = { + 0: 'CHCG_PERF_SEL_CYCLE', + 1: 'CHCG_PERF_SEL_BUSY', + 2: 'CHCG_PERF_SEL_STARVE', + 3: 'CHCG_PERF_SEL_ARB_RET_LEVEL', + 4: 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'CHCG_PERF_SEL_REQ', + 7: 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'CHCG_PERF_SEL_REQ_NOP_ACK', + 10: 'CHCG_PERF_SEL_REQ_NOP_RTN0', + 11: 'CHCG_PERF_SEL_REQ_READ', + 12: 'CHCG_PERF_SEL_REQ_READ_128B', + 13: 'CHCG_PERF_SEL_REQ_READ_32B', + 14: 'CHCG_PERF_SEL_REQ_READ_64B', + 15: 'CHCG_PERF_SEL_REQ_WRITE', + 16: 'CHCG_PERF_SEL_REQ_WRITE_32B', + 17: 'CHCG_PERF_SEL_REQ_WRITE_64B', + 18: 'CHCG_PERF_SEL_STALL_GUS_GL1', + 19: 'CHCG_PERF_SEL_STALL_BUFFER_FULL', + 20: 'CHCG_PERF_SEL_REQ_CLIENT0', + 21: 'CHCG_PERF_SEL_REQ_CLIENT1', + 22: 'CHCG_PERF_SEL_REQ_CLIENT2', + 23: 'CHCG_PERF_SEL_REQ_CLIENT3', + 24: 'CHCG_PERF_SEL_REQ_CLIENT4', + 25: 'CHCG_PERF_SEL_REQ_CLIENT5', + 26: 'CHCG_PERF_SEL_REQ_CLIENT6', + 27: 'CHCG_PERF_SEL_REQ_CLIENT7', + 28: 'CHCG_PERF_SEL_REQ_CLIENT8', + 29: 'CHCG_PERF_SEL_REQ_CLIENT9', + 30: 'CHCG_PERF_SEL_REQ_CLIENT10', + 31: 'CHCG_PERF_SEL_REQ_CLIENT11', + 32: 'CHCG_PERF_SEL_REQ_CLIENT12', + 33: 'CHCG_PERF_SEL_REQ_CLIENT13', + 34: 'CHCG_PERF_SEL_REQ_CLIENT14', + 35: 'CHCG_PERF_SEL_REQ_CLIENT15', + 36: 'CHCG_PERF_SEL_REQ_CLIENT16', + 37: 'CHCG_PERF_SEL_REQ_CLIENT17', + 38: 'CHCG_PERF_SEL_REQ_CLIENT18', + 39: 'CHCG_PERF_SEL_REQ_CLIENT19', + 40: 'CHCG_PERF_SEL_REQ_CLIENT20', + 41: 'CHCG_PERF_SEL_REQ_CLIENT21', + 42: 'CHCG_PERF_SEL_REQ_CLIENT22', + 43: 'CHCG_PERF_SEL_REQ_CLIENT23', +} +CHCG_PERF_SEL_CYCLE = 0 +CHCG_PERF_SEL_BUSY = 1 +CHCG_PERF_SEL_STARVE = 2 +CHCG_PERF_SEL_ARB_RET_LEVEL = 3 +CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +CHCG_PERF_SEL_REQ = 6 +CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +CHCG_PERF_SEL_REQ_NOP_ACK = 9 +CHCG_PERF_SEL_REQ_NOP_RTN0 = 10 +CHCG_PERF_SEL_REQ_READ = 11 +CHCG_PERF_SEL_REQ_READ_128B = 12 +CHCG_PERF_SEL_REQ_READ_32B = 13 +CHCG_PERF_SEL_REQ_READ_64B = 14 +CHCG_PERF_SEL_REQ_WRITE = 15 +CHCG_PERF_SEL_REQ_WRITE_32B = 16 +CHCG_PERF_SEL_REQ_WRITE_64B = 17 +CHCG_PERF_SEL_STALL_GUS_GL1 = 18 +CHCG_PERF_SEL_STALL_BUFFER_FULL = 19 +CHCG_PERF_SEL_REQ_CLIENT0 = 20 +CHCG_PERF_SEL_REQ_CLIENT1 = 21 +CHCG_PERF_SEL_REQ_CLIENT2 = 22 +CHCG_PERF_SEL_REQ_CLIENT3 = 23 +CHCG_PERF_SEL_REQ_CLIENT4 = 24 +CHCG_PERF_SEL_REQ_CLIENT5 = 25 +CHCG_PERF_SEL_REQ_CLIENT6 = 26 +CHCG_PERF_SEL_REQ_CLIENT7 = 27 +CHCG_PERF_SEL_REQ_CLIENT8 = 28 +CHCG_PERF_SEL_REQ_CLIENT9 = 29 +CHCG_PERF_SEL_REQ_CLIENT10 = 30 +CHCG_PERF_SEL_REQ_CLIENT11 = 31 +CHCG_PERF_SEL_REQ_CLIENT12 = 32 +CHCG_PERF_SEL_REQ_CLIENT13 = 33 +CHCG_PERF_SEL_REQ_CLIENT14 = 34 +CHCG_PERF_SEL_REQ_CLIENT15 = 35 +CHCG_PERF_SEL_REQ_CLIENT16 = 36 +CHCG_PERF_SEL_REQ_CLIENT17 = 37 +CHCG_PERF_SEL_REQ_CLIENT18 = 38 +CHCG_PERF_SEL_REQ_CLIENT19 = 39 +CHCG_PERF_SEL_REQ_CLIENT20 = 40 +CHCG_PERF_SEL_REQ_CLIENT21 = 41 +CHCG_PERF_SEL_REQ_CLIENT22 = 42 +CHCG_PERF_SEL_REQ_CLIENT23 = 43 +CHCG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHC_PERF_SEL' +CHC_PERF_SEL__enumvalues = { + 0: 'CHC_PERF_SEL_CYCLE', + 1: 'CHC_PERF_SEL_BUSY', + 2: 'CHC_PERF_SEL_STARVE', + 3: 'CHC_PERF_SEL_ARB_RET_LEVEL', + 4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'CHC_PERF_SEL_REQ', + 7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'CHC_PERF_SEL_REQ_NOP_ACK', + 10: 'CHC_PERF_SEL_REQ_NOP_RTN0', + 11: 'CHC_PERF_SEL_REQ_READ', + 12: 'CHC_PERF_SEL_REQ_READ_128B', + 13: 'CHC_PERF_SEL_REQ_READ_32B', + 14: 'CHC_PERF_SEL_REQ_READ_64B', + 15: 'CHC_PERF_SEL_REQ_WRITE', + 16: 'CHC_PERF_SEL_REQ_WRITE_32B', + 17: 'CHC_PERF_SEL_REQ_WRITE_64B', + 18: 'CHC_PERF_SEL_STALL_GL2_GL1', + 19: 'CHC_PERF_SEL_STALL_BUFFER_FULL', + 20: 'CHC_PERF_SEL_REQ_CLIENT0', + 21: 'CHC_PERF_SEL_REQ_CLIENT1', + 22: 'CHC_PERF_SEL_REQ_CLIENT2', + 23: 'CHC_PERF_SEL_REQ_CLIENT3', + 24: 'CHC_PERF_SEL_REQ_CLIENT4', + 25: 'CHC_PERF_SEL_REQ_CLIENT5', + 26: 'CHC_PERF_SEL_REQ_CLIENT6', + 27: 'CHC_PERF_SEL_REQ_CLIENT7', + 28: 'CHC_PERF_SEL_REQ_CLIENT8', + 29: 'CHC_PERF_SEL_REQ_CLIENT9', + 30: 'CHC_PERF_SEL_REQ_CLIENT10', + 31: 'CHC_PERF_SEL_REQ_CLIENT11', + 32: 'CHC_PERF_SEL_REQ_CLIENT12', + 33: 'CHC_PERF_SEL_REQ_CLIENT13', + 34: 'CHC_PERF_SEL_REQ_CLIENT14', + 35: 'CHC_PERF_SEL_REQ_CLIENT15', + 36: 'CHC_PERF_SEL_REQ_CLIENT16', + 37: 'CHC_PERF_SEL_REQ_CLIENT17', + 38: 'CHC_PERF_SEL_REQ_CLIENT18', + 39: 'CHC_PERF_SEL_REQ_CLIENT19', + 40: 'CHC_PERF_SEL_REQ_CLIENT20', + 41: 'CHC_PERF_SEL_REQ_CLIENT21', + 42: 'CHC_PERF_SEL_REQ_CLIENT22', + 43: 'CHC_PERF_SEL_REQ_CLIENT23', +} +CHC_PERF_SEL_CYCLE = 0 +CHC_PERF_SEL_BUSY = 1 +CHC_PERF_SEL_STARVE = 2 +CHC_PERF_SEL_ARB_RET_LEVEL = 3 +CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +CHC_PERF_SEL_REQ = 6 +CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +CHC_PERF_SEL_REQ_NOP_ACK = 9 +CHC_PERF_SEL_REQ_NOP_RTN0 = 10 +CHC_PERF_SEL_REQ_READ = 11 +CHC_PERF_SEL_REQ_READ_128B = 12 +CHC_PERF_SEL_REQ_READ_32B = 13 +CHC_PERF_SEL_REQ_READ_64B = 14 +CHC_PERF_SEL_REQ_WRITE = 15 +CHC_PERF_SEL_REQ_WRITE_32B = 16 +CHC_PERF_SEL_REQ_WRITE_64B = 17 +CHC_PERF_SEL_STALL_GL2_GL1 = 18 +CHC_PERF_SEL_STALL_BUFFER_FULL = 19 +CHC_PERF_SEL_REQ_CLIENT0 = 20 +CHC_PERF_SEL_REQ_CLIENT1 = 21 +CHC_PERF_SEL_REQ_CLIENT2 = 22 +CHC_PERF_SEL_REQ_CLIENT3 = 23 +CHC_PERF_SEL_REQ_CLIENT4 = 24 +CHC_PERF_SEL_REQ_CLIENT5 = 25 +CHC_PERF_SEL_REQ_CLIENT6 = 26 +CHC_PERF_SEL_REQ_CLIENT7 = 27 +CHC_PERF_SEL_REQ_CLIENT8 = 28 +CHC_PERF_SEL_REQ_CLIENT9 = 29 +CHC_PERF_SEL_REQ_CLIENT10 = 30 +CHC_PERF_SEL_REQ_CLIENT11 = 31 +CHC_PERF_SEL_REQ_CLIENT12 = 32 +CHC_PERF_SEL_REQ_CLIENT13 = 33 +CHC_PERF_SEL_REQ_CLIENT14 = 34 +CHC_PERF_SEL_REQ_CLIENT15 = 35 +CHC_PERF_SEL_REQ_CLIENT16 = 36 +CHC_PERF_SEL_REQ_CLIENT17 = 37 +CHC_PERF_SEL_REQ_CLIENT18 = 38 +CHC_PERF_SEL_REQ_CLIENT19 = 39 +CHC_PERF_SEL_REQ_CLIENT20 = 40 +CHC_PERF_SEL_REQ_CLIENT21 = 41 +CHC_PERF_SEL_REQ_CLIENT22 = 42 +CHC_PERF_SEL_REQ_CLIENT23 = 43 +CHC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1A_PERF_SEL' +GL1A_PERF_SEL__enumvalues = { + 0: 'GL1A_PERF_SEL_BUSY', + 1: 'GL1A_PERF_SEL_STALL_GL1C0', + 2: 'GL1A_PERF_SEL_STALL_GL1C1', + 3: 'GL1A_PERF_SEL_STALL_GL1C2', + 4: 'GL1A_PERF_SEL_STALL_GL1C3', + 5: 'GL1A_PERF_SEL_REQUEST_GL1C0', + 6: 'GL1A_PERF_SEL_REQUEST_GL1C1', + 7: 'GL1A_PERF_SEL_REQUEST_GL1C2', + 8: 'GL1A_PERF_SEL_REQUEST_GL1C3', + 9: 'GL1A_PERF_SEL_WDS_32B_GL1C0', + 10: 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 11: 'GL1A_PERF_SEL_WDS_32B_GL1C2', + 12: 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', + 17: 'GL1A_PERF_SEL_ARB_REQUESTS', + 18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 23: 'GL1A_PERF_SEL_CYCLE', +} +GL1A_PERF_SEL_BUSY = 0 +GL1A_PERF_SEL_STALL_GL1C0 = 1 +GL1A_PERF_SEL_STALL_GL1C1 = 2 +GL1A_PERF_SEL_STALL_GL1C2 = 3 +GL1A_PERF_SEL_STALL_GL1C3 = 4 +GL1A_PERF_SEL_REQUEST_GL1C0 = 5 +GL1A_PERF_SEL_REQUEST_GL1C1 = 6 +GL1A_PERF_SEL_REQUEST_GL1C2 = 7 +GL1A_PERF_SEL_REQUEST_GL1C3 = 8 +GL1A_PERF_SEL_WDS_32B_GL1C0 = 9 +GL1A_PERF_SEL_WDS_32B_GL1C1 = 10 +GL1A_PERF_SEL_WDS_32B_GL1C2 = 11 +GL1A_PERF_SEL_WDS_32B_GL1C3 = 12 +GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13 +GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14 +GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15 +GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16 +GL1A_PERF_SEL_ARB_REQUESTS = 17 +GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22 +GL1A_PERF_SEL_CYCLE = 23 +GL1A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1C_PERF_SEL' +GL1C_PERF_SEL__enumvalues = { + 0: 'GL1C_PERF_SEL_CYCLE', + 1: 'GL1C_PERF_SEL_BUSY', + 2: 'GL1C_PERF_SEL_STARVE', + 3: 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 4: 'GL1C_PERF_SEL_GL2_REQ_READ', + 5: 'GL1C_PERF_SEL_GL2_REQ_READ_128B', + 6: 'GL1C_PERF_SEL_GL2_REQ_READ_32B', + 7: 'GL1C_PERF_SEL_GL2_REQ_READ_64B', + 8: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 9: 'GL1C_PERF_SEL_GL2_REQ_WRITE', + 10: 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', + 11: 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', + 12: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 13: 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', + 14: 'GL1C_PERF_SEL_REQ', + 15: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', + 16: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 17: 'GL1C_PERF_SEL_REQ_SHADER_INV', + 18: 'GL1C_PERF_SEL_REQ_MISS', + 19: 'GL1C_PERF_SEL_REQ_NOP_ACK', + 20: 'GL1C_PERF_SEL_REQ_NOP_RTN0', + 21: 'GL1C_PERF_SEL_REQ_READ', + 22: 'GL1C_PERF_SEL_REQ_READ_128B', + 23: 'GL1C_PERF_SEL_REQ_READ_32B', + 24: 'GL1C_PERF_SEL_REQ_READ_64B', + 25: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', + 26: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', + 27: 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', + 28: 'GL1C_PERF_SEL_REQ_WRITE', + 29: 'GL1C_PERF_SEL_REQ_WRITE_32B', + 30: 'GL1C_PERF_SEL_REQ_WRITE_64B', + 31: 'GL1C_PERF_SEL_STALL_GL2_GL1', + 32: 'GL1C_PERF_SEL_STALL_LFIFO_FULL', + 33: 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', + 34: 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', + 35: 'GL1C_PERF_SEL_STALL_GCR_INV', + 36: 'GL1C_PERF_SEL_STALL_VM', + 37: 'GL1C_PERF_SEL_REQ_CLIENT0', + 38: 'GL1C_PERF_SEL_REQ_CLIENT1', + 39: 'GL1C_PERF_SEL_REQ_CLIENT2', + 40: 'GL1C_PERF_SEL_REQ_CLIENT3', + 41: 'GL1C_PERF_SEL_REQ_CLIENT4', + 42: 'GL1C_PERF_SEL_REQ_CLIENT5', + 43: 'GL1C_PERF_SEL_REQ_CLIENT6', + 44: 'GL1C_PERF_SEL_REQ_CLIENT7', + 45: 'GL1C_PERF_SEL_REQ_CLIENT8', + 46: 'GL1C_PERF_SEL_REQ_CLIENT9', + 47: 'GL1C_PERF_SEL_REQ_CLIENT10', + 48: 'GL1C_PERF_SEL_REQ_CLIENT11', + 49: 'GL1C_PERF_SEL_REQ_CLIENT12', + 50: 'GL1C_PERF_SEL_REQ_CLIENT13', + 51: 'GL1C_PERF_SEL_REQ_CLIENT14', + 52: 'GL1C_PERF_SEL_REQ_CLIENT15', + 53: 'GL1C_PERF_SEL_REQ_CLIENT16', + 54: 'GL1C_PERF_SEL_REQ_CLIENT17', + 55: 'GL1C_PERF_SEL_REQ_CLIENT18', + 56: 'GL1C_PERF_SEL_REQ_CLIENT19', + 57: 'GL1C_PERF_SEL_REQ_CLIENT20', + 58: 'GL1C_PERF_SEL_REQ_CLIENT21', + 59: 'GL1C_PERF_SEL_REQ_CLIENT22', + 60: 'GL1C_PERF_SEL_REQ_CLIENT23', + 61: 'GL1C_PERF_SEL_REQ_CLIENT24', + 62: 'GL1C_PERF_SEL_REQ_CLIENT25', + 63: 'GL1C_PERF_SEL_REQ_CLIENT26', + 64: 'GL1C_PERF_SEL_REQ_CLIENT27', + 65: 'GL1C_PERF_SEL_UTCL0_REQUEST', + 66: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 67: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 68: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 69: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 70: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 71: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 72: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 73: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 74: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 75: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 76: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 77: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 78: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 79: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 80: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 81: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 82: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 83: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', +} +GL1C_PERF_SEL_CYCLE = 0 +GL1C_PERF_SEL_BUSY = 1 +GL1C_PERF_SEL_STARVE = 2 +GL1C_PERF_SEL_ARB_RET_LEVEL = 3 +GL1C_PERF_SEL_GL2_REQ_READ = 4 +GL1C_PERF_SEL_GL2_REQ_READ_128B = 5 +GL1C_PERF_SEL_GL2_REQ_READ_32B = 6 +GL1C_PERF_SEL_GL2_REQ_READ_64B = 7 +GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 8 +GL1C_PERF_SEL_GL2_REQ_WRITE = 9 +GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 10 +GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 11 +GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 12 +GL1C_PERF_SEL_GL2_REQ_PREFETCH = 13 +GL1C_PERF_SEL_REQ = 14 +GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 15 +GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 16 +GL1C_PERF_SEL_REQ_SHADER_INV = 17 +GL1C_PERF_SEL_REQ_MISS = 18 +GL1C_PERF_SEL_REQ_NOP_ACK = 19 +GL1C_PERF_SEL_REQ_NOP_RTN0 = 20 +GL1C_PERF_SEL_REQ_READ = 21 +GL1C_PERF_SEL_REQ_READ_128B = 22 +GL1C_PERF_SEL_REQ_READ_32B = 23 +GL1C_PERF_SEL_REQ_READ_64B = 24 +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 25 +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 26 +GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 27 +GL1C_PERF_SEL_REQ_WRITE = 28 +GL1C_PERF_SEL_REQ_WRITE_32B = 29 +GL1C_PERF_SEL_REQ_WRITE_64B = 30 +GL1C_PERF_SEL_STALL_GL2_GL1 = 31 +GL1C_PERF_SEL_STALL_LFIFO_FULL = 32 +GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 33 +GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 34 +GL1C_PERF_SEL_STALL_GCR_INV = 35 +GL1C_PERF_SEL_STALL_VM = 36 +GL1C_PERF_SEL_REQ_CLIENT0 = 37 +GL1C_PERF_SEL_REQ_CLIENT1 = 38 +GL1C_PERF_SEL_REQ_CLIENT2 = 39 +GL1C_PERF_SEL_REQ_CLIENT3 = 40 +GL1C_PERF_SEL_REQ_CLIENT4 = 41 +GL1C_PERF_SEL_REQ_CLIENT5 = 42 +GL1C_PERF_SEL_REQ_CLIENT6 = 43 +GL1C_PERF_SEL_REQ_CLIENT7 = 44 +GL1C_PERF_SEL_REQ_CLIENT8 = 45 +GL1C_PERF_SEL_REQ_CLIENT9 = 46 +GL1C_PERF_SEL_REQ_CLIENT10 = 47 +GL1C_PERF_SEL_REQ_CLIENT11 = 48 +GL1C_PERF_SEL_REQ_CLIENT12 = 49 +GL1C_PERF_SEL_REQ_CLIENT13 = 50 +GL1C_PERF_SEL_REQ_CLIENT14 = 51 +GL1C_PERF_SEL_REQ_CLIENT15 = 52 +GL1C_PERF_SEL_REQ_CLIENT16 = 53 +GL1C_PERF_SEL_REQ_CLIENT17 = 54 +GL1C_PERF_SEL_REQ_CLIENT18 = 55 +GL1C_PERF_SEL_REQ_CLIENT19 = 56 +GL1C_PERF_SEL_REQ_CLIENT20 = 57 +GL1C_PERF_SEL_REQ_CLIENT21 = 58 +GL1C_PERF_SEL_REQ_CLIENT22 = 59 +GL1C_PERF_SEL_REQ_CLIENT23 = 60 +GL1C_PERF_SEL_REQ_CLIENT24 = 61 +GL1C_PERF_SEL_REQ_CLIENT25 = 62 +GL1C_PERF_SEL_REQ_CLIENT26 = 63 +GL1C_PERF_SEL_REQ_CLIENT27 = 64 +GL1C_PERF_SEL_UTCL0_REQUEST = 65 +GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 66 +GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 67 +GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 68 +GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 69 +GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 70 +GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 71 +GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 72 +GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 73 +GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 74 +GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 75 +GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 76 +GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 77 +GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 78 +GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 79 +GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 80 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 81 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 82 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 83 +GL1C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1H_REQ_PERF_SEL' +GL1H_REQ_PERF_SEL__enumvalues = { + 0: 'GL1H_REQ_PERF_SEL_BUSY', + 1: 'GL1H_REQ_PERF_SEL_STALL_GL1_0', + 2: 'GL1H_REQ_PERF_SEL_STALL_GL1_1', + 3: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', + 4: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', + 5: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', + 6: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', + 7: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', + 8: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', + 9: 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', + 10: 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', + 11: 'GL1H_REQ_PERF_SEL_CYCLE', +} +GL1H_REQ_PERF_SEL_BUSY = 0 +GL1H_REQ_PERF_SEL_STALL_GL1_0 = 1 +GL1H_REQ_PERF_SEL_STALL_GL1_1 = 2 +GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 3 +GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 4 +GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 5 +GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 6 +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 7 +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 8 +GL1H_REQ_PERF_SEL_ARB_REQUESTS = 9 +GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 10 +GL1H_REQ_PERF_SEL_CYCLE = 11 +GL1H_REQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TA_PERFCOUNT_SEL' +TA_PERFCOUNT_SEL__enumvalues = { + 0: 'TA_PERF_SEL_NULL', + 1: 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 2: 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 3: 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 4: 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 5: 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 6: 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 7: 'TA_PERF_SEL_gradient_busy', + 8: 'TA_PERF_SEL_gradient_fifo_busy', + 9: 'TA_PERF_SEL_lod_busy', + 10: 'TA_PERF_SEL_lod_fifo_busy', + 11: 'TA_PERF_SEL_addresser_busy', + 12: 'TA_PERF_SEL_addresser_fifo_busy', + 13: 'TA_PERF_SEL_aligner_busy', + 14: 'TA_PERF_SEL_write_path_busy', + 15: 'TA_PERF_SEL_ta_busy', + 16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 28: 'TA_PERF_SEL_image_sampler_has_t_instructions', + 29: 'TA_PERF_SEL_image_sampler_has_r_instructions', + 30: 'TA_PERF_SEL_image_sampler_has_q_instructions', + 32: 'TA_PERF_SEL_total_wavefronts', + 33: 'TA_PERF_SEL_gradient_cycles', + 34: 'TA_PERF_SEL_walker_cycles', + 35: 'TA_PERF_SEL_aligner_cycles', + 36: 'TA_PERF_SEL_image_wavefronts', + 37: 'TA_PERF_SEL_image_read_wavefronts', + 38: 'TA_PERF_SEL_image_store_wavefronts', + 39: 'TA_PERF_SEL_image_atomic_wavefronts', + 40: 'TA_PERF_SEL_image_sampler_total_cycles', + 41: 'TA_PERF_SEL_image_nosampler_total_cycles', + 42: 'TA_PERF_SEL_flat_total_cycles', + 43: 'TA_PERF_SEL_bvh_total_cycles', + 44: 'TA_PERF_SEL_buffer_wavefronts', + 45: 'TA_PERF_SEL_buffer_load_wavefronts', + 46: 'TA_PERF_SEL_buffer_store_wavefronts', + 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', + 49: 'TA_PERF_SEL_buffer_total_cycles', + 50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 52: 'TA_PERF_SEL_buffer_has_index_instructions', + 53: 'TA_PERF_SEL_buffer_has_offset_instructions', + 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 56: 'TA_PERF_SEL_image_sampler_wavefronts', + 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 58: 'TA_PERF_SEL_addresser_stalled_cycles', + 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 60: 'TA_PERF_SEL_aniso_stalled_cycles', + 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 62: 'TA_PERF_SEL_deriv_stalled_cycles', + 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 64: 'TA_PERF_SEL_color_1_cycle_quads', + 65: 'TA_PERF_SEL_color_2_cycle_quads', + 66: 'TA_PERF_SEL_color_3_cycle_quads', + 68: 'TA_PERF_SEL_mip_1_cycle_quads', + 69: 'TA_PERF_SEL_mip_2_cycle_quads', + 70: 'TA_PERF_SEL_vol_1_cycle_quads', + 71: 'TA_PERF_SEL_vol_2_cycle_quads', + 72: 'TA_PERF_SEL_sampler_op_quads', + 73: 'TA_PERF_SEL_mipmap_lod_0_samples', + 74: 'TA_PERF_SEL_mipmap_lod_1_samples', + 75: 'TA_PERF_SEL_mipmap_lod_2_samples', + 76: 'TA_PERF_SEL_mipmap_lod_3_samples', + 77: 'TA_PERF_SEL_mipmap_lod_4_samples', + 78: 'TA_PERF_SEL_mipmap_lod_5_samples', + 79: 'TA_PERF_SEL_mipmap_lod_6_samples', + 80: 'TA_PERF_SEL_mipmap_lod_7_samples', + 81: 'TA_PERF_SEL_mipmap_lod_8_samples', + 82: 'TA_PERF_SEL_mipmap_lod_9_samples', + 83: 'TA_PERF_SEL_mipmap_lod_10_samples', + 84: 'TA_PERF_SEL_mipmap_lod_11_samples', + 85: 'TA_PERF_SEL_mipmap_lod_12_samples', + 86: 'TA_PERF_SEL_mipmap_lod_13_samples', + 87: 'TA_PERF_SEL_mipmap_lod_14_samples', + 88: 'TA_PERF_SEL_mipmap_invalid_samples', + 89: 'TA_PERF_SEL_aniso_1_cycle_quads', + 90: 'TA_PERF_SEL_aniso_2_cycle_quads', + 91: 'TA_PERF_SEL_aniso_4_cycle_quads', + 92: 'TA_PERF_SEL_aniso_6_cycle_quads', + 93: 'TA_PERF_SEL_aniso_8_cycle_quads', + 94: 'TA_PERF_SEL_aniso_10_cycle_quads', + 95: 'TA_PERF_SEL_aniso_12_cycle_quads', + 96: 'TA_PERF_SEL_aniso_14_cycle_quads', + 97: 'TA_PERF_SEL_aniso_16_cycle_quads', + 98: 'TA_PERF_SEL_store_write_data_input_cycles', + 99: 'TA_PERF_SEL_store_write_data_output_cycles', + 100: 'TA_PERF_SEL_flat_wavefronts', + 101: 'TA_PERF_SEL_flat_load_wavefronts', + 102: 'TA_PERF_SEL_flat_store_wavefronts', + 103: 'TA_PERF_SEL_flat_atomic_wavefronts', + 104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 105: 'TA_PERF_SEL_register_clk_valid_cycles', + 106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 108: 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', + 109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 117: 'TA_PERF_SEL_store_has_x_instructions', + 118: 'TA_PERF_SEL_store_has_y_instructions', + 119: 'TA_PERF_SEL_store_has_z_instructions', + 120: 'TA_PERF_SEL_store_has_w_instructions', + 121: 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 122: 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 123: 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 128: 'TA_PERF_SEL_in_busy', + 129: 'TA_PERF_SEL_in_fifos_busy', + 130: 'TA_PERF_SEL_in_cfifo_busy', + 131: 'TA_PERF_SEL_in_qfifo_busy', + 132: 'TA_PERF_SEL_in_wfifo_busy', + 133: 'TA_PERF_SEL_in_rfifo_busy', + 134: 'TA_PERF_SEL_bf_busy', + 135: 'TA_PERF_SEL_ns_busy', + 136: 'TA_PERF_SEL_smp_busy_ns_idle', + 137: 'TA_PERF_SEL_smp_idle_ns_busy', + 144: 'TA_PERF_SEL_vmemcmd_cycles', + 145: 'TA_PERF_SEL_vmemreq_cycles', + 146: 'TA_PERF_SEL_in_waiting_on_req_cycles', + 150: 'TA_PERF_SEL_in_addr_cycles', + 151: 'TA_PERF_SEL_in_data_cycles', + 154: 'TA_PERF_SEL_latency_ram_weights_written_cycles', + 155: 'TA_PERF_SEL_latency_ram_ws_required_quads', + 156: 'TA_PERF_SEL_latency_ram_whv_required_quads', + 157: 'TA_PERF_SEL_latency_ram_ws_required_instructions', + 158: 'TA_PERF_SEL_latency_ram_whv_required_instructions', + 159: 'TA_PERF_SEL_latency_ram_ref_required_instructions', + 160: 'TA_PERF_SEL_point_sampled_quads', + 162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 164: 'TA_PERF_SEL_atomic_write_data_input_cycles', + 165: 'TA_PERF_SEL_atomic_write_data_output_cycles', + 173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 176: 'TA_PERF_SEL_num_of_bvh_valid_first_tri', + 177: 'TA_PERF_SEL_num_of_bvh_valid_second_tri', + 178: 'TA_PERF_SEL_num_of_bvh_valid_third_tri', + 179: 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', + 180: 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', + 181: 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', + 182: 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', + 183: 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', + 184: 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', + 185: 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', + 186: 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', + 187: 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', + 188: 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', + 189: 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', + 190: 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', + 191: 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', + 192: 'TA_PERF_SEL_image_sampler_1_op_burst', + 193: 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 194: 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 195: 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 196: 'TA_PERF_SEL_image_linked_1_op_burst', + 197: 'TA_PERF_SEL_image_linked_2to3_op_burst', + 198: 'TA_PERF_SEL_image_linked_4to7_op_burst', + 199: 'TA_PERF_SEL_image_linked_ge8_op_burst', + 200: 'TA_PERF_SEL_image_bvh_1_op_burst', + 201: 'TA_PERF_SEL_image_bvh_2to3_op_burst', + 202: 'TA_PERF_SEL_image_bvh_4to7_op_burst', + 203: 'TA_PERF_SEL_image_bvh_ge8_op_burst', + 204: 'TA_PERF_SEL_image_nosampler_1_op_burst', + 205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 208: 'TA_PERF_SEL_buffer_flat_1_op_burst', + 209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 212: 'TA_PERF_SEL_write_1_op_burst', + 213: 'TA_PERF_SEL_write_2to3_op_burst', + 214: 'TA_PERF_SEL_write_4to31_op_burst', + 215: 'TA_PERF_SEL_write_ge32_op_burst', + 216: 'TA_PERF_SEL_ibubble_1_cycle_burst', + 217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 224: 'TA_PERF_SEL_sampler_clk_valid_cycles', + 225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles', + 226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 227: 'TA_PERF_SEL_write_data_clk_valid_cycles', + 228: 'TA_PERF_SEL_gradient_clk_valid_cycles', + 229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', + 230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 234: 'TA_PERF_SEL_aligner_clk_valid_cycles', + 235: 'TA_PERF_SEL_tcreq_clk_valid_cycles', +} +TA_PERF_SEL_NULL = 0 +TA_PERF_SEL_image_sampler_has_offset_instructions = 1 +TA_PERF_SEL_image_sampler_has_bias_instructions = 2 +TA_PERF_SEL_image_sampler_has_reference_instructions = 3 +TA_PERF_SEL_image_sampler_has_ds_instructions = 4 +TA_PERF_SEL_image_sampler_has_dt_instructions = 5 +TA_PERF_SEL_image_sampler_has_dr_instructions = 6 +TA_PERF_SEL_gradient_busy = 7 +TA_PERF_SEL_gradient_fifo_busy = 8 +TA_PERF_SEL_lod_busy = 9 +TA_PERF_SEL_lod_fifo_busy = 10 +TA_PERF_SEL_addresser_busy = 11 +TA_PERF_SEL_addresser_fifo_busy = 12 +TA_PERF_SEL_aligner_busy = 13 +TA_PERF_SEL_write_path_busy = 14 +TA_PERF_SEL_ta_busy = 15 +TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16 +TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17 +TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18 +TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19 +TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20 +TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21 +TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22 +TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23 +TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24 +TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25 +TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26 +TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27 +TA_PERF_SEL_image_sampler_has_t_instructions = 28 +TA_PERF_SEL_image_sampler_has_r_instructions = 29 +TA_PERF_SEL_image_sampler_has_q_instructions = 30 +TA_PERF_SEL_total_wavefronts = 32 +TA_PERF_SEL_gradient_cycles = 33 +TA_PERF_SEL_walker_cycles = 34 +TA_PERF_SEL_aligner_cycles = 35 +TA_PERF_SEL_image_wavefronts = 36 +TA_PERF_SEL_image_read_wavefronts = 37 +TA_PERF_SEL_image_store_wavefronts = 38 +TA_PERF_SEL_image_atomic_wavefronts = 39 +TA_PERF_SEL_image_sampler_total_cycles = 40 +TA_PERF_SEL_image_nosampler_total_cycles = 41 +TA_PERF_SEL_flat_total_cycles = 42 +TA_PERF_SEL_bvh_total_cycles = 43 +TA_PERF_SEL_buffer_wavefronts = 44 +TA_PERF_SEL_buffer_load_wavefronts = 45 +TA_PERF_SEL_buffer_store_wavefronts = 46 +TA_PERF_SEL_buffer_atomic_wavefronts = 47 +TA_PERF_SEL_buffer_total_cycles = 49 +TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50 +TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51 +TA_PERF_SEL_buffer_has_index_instructions = 52 +TA_PERF_SEL_buffer_has_offset_instructions = 53 +TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 +TA_PERF_SEL_addr_stalled_by_td_cycles = 55 +TA_PERF_SEL_image_sampler_wavefronts = 56 +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 +TA_PERF_SEL_addresser_stalled_cycles = 58 +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 +TA_PERF_SEL_aniso_stalled_cycles = 60 +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 +TA_PERF_SEL_deriv_stalled_cycles = 62 +TA_PERF_SEL_aniso_gt1_cycle_quads = 63 +TA_PERF_SEL_color_1_cycle_quads = 64 +TA_PERF_SEL_color_2_cycle_quads = 65 +TA_PERF_SEL_color_3_cycle_quads = 66 +TA_PERF_SEL_mip_1_cycle_quads = 68 +TA_PERF_SEL_mip_2_cycle_quads = 69 +TA_PERF_SEL_vol_1_cycle_quads = 70 +TA_PERF_SEL_vol_2_cycle_quads = 71 +TA_PERF_SEL_sampler_op_quads = 72 +TA_PERF_SEL_mipmap_lod_0_samples = 73 +TA_PERF_SEL_mipmap_lod_1_samples = 74 +TA_PERF_SEL_mipmap_lod_2_samples = 75 +TA_PERF_SEL_mipmap_lod_3_samples = 76 +TA_PERF_SEL_mipmap_lod_4_samples = 77 +TA_PERF_SEL_mipmap_lod_5_samples = 78 +TA_PERF_SEL_mipmap_lod_6_samples = 79 +TA_PERF_SEL_mipmap_lod_7_samples = 80 +TA_PERF_SEL_mipmap_lod_8_samples = 81 +TA_PERF_SEL_mipmap_lod_9_samples = 82 +TA_PERF_SEL_mipmap_lod_10_samples = 83 +TA_PERF_SEL_mipmap_lod_11_samples = 84 +TA_PERF_SEL_mipmap_lod_12_samples = 85 +TA_PERF_SEL_mipmap_lod_13_samples = 86 +TA_PERF_SEL_mipmap_lod_14_samples = 87 +TA_PERF_SEL_mipmap_invalid_samples = 88 +TA_PERF_SEL_aniso_1_cycle_quads = 89 +TA_PERF_SEL_aniso_2_cycle_quads = 90 +TA_PERF_SEL_aniso_4_cycle_quads = 91 +TA_PERF_SEL_aniso_6_cycle_quads = 92 +TA_PERF_SEL_aniso_8_cycle_quads = 93 +TA_PERF_SEL_aniso_10_cycle_quads = 94 +TA_PERF_SEL_aniso_12_cycle_quads = 95 +TA_PERF_SEL_aniso_14_cycle_quads = 96 +TA_PERF_SEL_aniso_16_cycle_quads = 97 +TA_PERF_SEL_store_write_data_input_cycles = 98 +TA_PERF_SEL_store_write_data_output_cycles = 99 +TA_PERF_SEL_flat_wavefronts = 100 +TA_PERF_SEL_flat_load_wavefronts = 101 +TA_PERF_SEL_flat_store_wavefronts = 102 +TA_PERF_SEL_flat_atomic_wavefronts = 103 +TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104 +TA_PERF_SEL_register_clk_valid_cycles = 105 +TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106 +TA_PERF_SEL_harvestable_clk_enabled_cycles = 107 +TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 108 +TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109 +TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110 +TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114 +TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115 +TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116 +TA_PERF_SEL_store_has_x_instructions = 117 +TA_PERF_SEL_store_has_y_instructions = 118 +TA_PERF_SEL_store_has_z_instructions = 119 +TA_PERF_SEL_store_has_w_instructions = 120 +TA_PERF_SEL_image_nosampler_has_t_instructions = 121 +TA_PERF_SEL_image_nosampler_has_r_instructions = 122 +TA_PERF_SEL_image_nosampler_has_q_instructions = 123 +TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124 +TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125 +TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126 +TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127 +TA_PERF_SEL_in_busy = 128 +TA_PERF_SEL_in_fifos_busy = 129 +TA_PERF_SEL_in_cfifo_busy = 130 +TA_PERF_SEL_in_qfifo_busy = 131 +TA_PERF_SEL_in_wfifo_busy = 132 +TA_PERF_SEL_in_rfifo_busy = 133 +TA_PERF_SEL_bf_busy = 134 +TA_PERF_SEL_ns_busy = 135 +TA_PERF_SEL_smp_busy_ns_idle = 136 +TA_PERF_SEL_smp_idle_ns_busy = 137 +TA_PERF_SEL_vmemcmd_cycles = 144 +TA_PERF_SEL_vmemreq_cycles = 145 +TA_PERF_SEL_in_waiting_on_req_cycles = 146 +TA_PERF_SEL_in_addr_cycles = 150 +TA_PERF_SEL_in_data_cycles = 151 +TA_PERF_SEL_latency_ram_weights_written_cycles = 154 +TA_PERF_SEL_latency_ram_ws_required_quads = 155 +TA_PERF_SEL_latency_ram_whv_required_quads = 156 +TA_PERF_SEL_latency_ram_ws_required_instructions = 157 +TA_PERF_SEL_latency_ram_whv_required_instructions = 158 +TA_PERF_SEL_latency_ram_ref_required_instructions = 159 +TA_PERF_SEL_point_sampled_quads = 160 +TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162 +TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163 +TA_PERF_SEL_atomic_write_data_input_cycles = 164 +TA_PERF_SEL_atomic_write_data_output_cycles = 165 +TA_PERF_SEL_num_unlit_nodes_ta_opt = 173 +TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174 +TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175 +TA_PERF_SEL_num_of_bvh_valid_first_tri = 176 +TA_PERF_SEL_num_of_bvh_valid_second_tri = 177 +TA_PERF_SEL_num_of_bvh_valid_third_tri = 178 +TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 179 +TA_PERF_SEL_num_of_bvh_valid_fp16_box = 180 +TA_PERF_SEL_num_of_bvh_valid_fp32_box = 181 +TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 182 +TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 183 +TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 184 +TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 185 +TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 186 +TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 187 +TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 188 +TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 189 +TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 190 +TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 191 +TA_PERF_SEL_image_sampler_1_op_burst = 192 +TA_PERF_SEL_image_sampler_2to3_op_burst = 193 +TA_PERF_SEL_image_sampler_4to7_op_burst = 194 +TA_PERF_SEL_image_sampler_ge8_op_burst = 195 +TA_PERF_SEL_image_linked_1_op_burst = 196 +TA_PERF_SEL_image_linked_2to3_op_burst = 197 +TA_PERF_SEL_image_linked_4to7_op_burst = 198 +TA_PERF_SEL_image_linked_ge8_op_burst = 199 +TA_PERF_SEL_image_bvh_1_op_burst = 200 +TA_PERF_SEL_image_bvh_2to3_op_burst = 201 +TA_PERF_SEL_image_bvh_4to7_op_burst = 202 +TA_PERF_SEL_image_bvh_ge8_op_burst = 203 +TA_PERF_SEL_image_nosampler_1_op_burst = 204 +TA_PERF_SEL_image_nosampler_2to3_op_burst = 205 +TA_PERF_SEL_image_nosampler_4to31_op_burst = 206 +TA_PERF_SEL_image_nosampler_ge32_op_burst = 207 +TA_PERF_SEL_buffer_flat_1_op_burst = 208 +TA_PERF_SEL_buffer_flat_2to3_op_burst = 209 +TA_PERF_SEL_buffer_flat_4to31_op_burst = 210 +TA_PERF_SEL_buffer_flat_ge32_op_burst = 211 +TA_PERF_SEL_write_1_op_burst = 212 +TA_PERF_SEL_write_2to3_op_burst = 213 +TA_PERF_SEL_write_4to31_op_burst = 214 +TA_PERF_SEL_write_ge32_op_burst = 215 +TA_PERF_SEL_ibubble_1_cycle_burst = 216 +TA_PERF_SEL_ibubble_2to3_cycle_burst = 217 +TA_PERF_SEL_ibubble_4to15_cycle_burst = 218 +TA_PERF_SEL_ibubble_16to31_cycle_burst = 219 +TA_PERF_SEL_ibubble_32to63_cycle_burst = 220 +TA_PERF_SEL_ibubble_ge64_cycle_burst = 221 +TA_PERF_SEL_sampler_clk_valid_cycles = 224 +TA_PERF_SEL_nonsampler_clk_valid_cycles = 225 +TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226 +TA_PERF_SEL_write_data_clk_valid_cycles = 227 +TA_PERF_SEL_gradient_clk_valid_cycles = 228 +TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229 +TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230 +TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231 +TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232 +TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233 +TA_PERF_SEL_aligner_clk_valid_cycles = 234 +TA_PERF_SEL_tcreq_clk_valid_cycles = 235 +TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BC_SWIZZLE' +TEX_BC_SWIZZLE__enumvalues = { + 0: 'TEX_BC_Swizzle_XYZW', + 1: 'TEX_BC_Swizzle_XWYZ', + 2: 'TEX_BC_Swizzle_WZYX', + 3: 'TEX_BC_Swizzle_WXYZ', + 4: 'TEX_BC_Swizzle_ZYXW', + 5: 'TEX_BC_Swizzle_YXWZ', +} +TEX_BC_Swizzle_XYZW = 0 +TEX_BC_Swizzle_XWYZ = 1 +TEX_BC_Swizzle_WZYX = 2 +TEX_BC_Swizzle_WXYZ = 3 +TEX_BC_Swizzle_ZYXW = 4 +TEX_BC_Swizzle_YXWZ = 5 +TEX_BC_SWIZZLE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BORDER_COLOR_TYPE' +TEX_BORDER_COLOR_TYPE__enumvalues = { + 0: 'TEX_BorderColor_TransparentBlack', + 1: 'TEX_BorderColor_OpaqueBlack', + 2: 'TEX_BorderColor_OpaqueWhite', + 3: 'TEX_BorderColor_Register', +} +TEX_BorderColor_TransparentBlack = 0 +TEX_BorderColor_OpaqueBlack = 1 +TEX_BorderColor_OpaqueWhite = 2 +TEX_BorderColor_Register = 3 +TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CHROMA_KEY' +TEX_CHROMA_KEY__enumvalues = { + 0: 'TEX_ChromaKey_Disabled', + 1: 'TEX_ChromaKey_Kill', + 2: 'TEX_ChromaKey_Blend', + 3: 'TEX_ChromaKey_RESERVED_3', +} +TEX_ChromaKey_Disabled = 0 +TEX_ChromaKey_Kill = 1 +TEX_ChromaKey_Blend = 2 +TEX_ChromaKey_RESERVED_3 = 3 +TEX_CHROMA_KEY = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CLAMP' +TEX_CLAMP__enumvalues = { + 0: 'TEX_Clamp_Repeat', + 1: 'TEX_Clamp_Mirror', + 2: 'TEX_Clamp_ClampToLast', + 3: 'TEX_Clamp_MirrorOnceToLast', + 4: 'TEX_Clamp_ClampHalfToBorder', + 5: 'TEX_Clamp_MirrorOnceHalfToBorder', + 6: 'TEX_Clamp_ClampToBorder', + 7: 'TEX_Clamp_MirrorOnceToBorder', +} +TEX_Clamp_Repeat = 0 +TEX_Clamp_Mirror = 1 +TEX_Clamp_ClampToLast = 2 +TEX_Clamp_MirrorOnceToLast = 3 +TEX_Clamp_ClampHalfToBorder = 4 +TEX_Clamp_MirrorOnceHalfToBorder = 5 +TEX_Clamp_ClampToBorder = 6 +TEX_Clamp_MirrorOnceToBorder = 7 +TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_COORD_TYPE' +TEX_COORD_TYPE__enumvalues = { + 0: 'TEX_CoordType_Unnormalized', + 1: 'TEX_CoordType_Normalized', +} +TEX_CoordType_Unnormalized = 0 +TEX_CoordType_Normalized = 1 +TEX_COORD_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' +TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { + 0: 'TEX_DepthCompareFunction_Never', + 1: 'TEX_DepthCompareFunction_Less', + 2: 'TEX_DepthCompareFunction_Equal', + 3: 'TEX_DepthCompareFunction_LessEqual', + 4: 'TEX_DepthCompareFunction_Greater', + 5: 'TEX_DepthCompareFunction_NotEqual', + 6: 'TEX_DepthCompareFunction_GreaterEqual', + 7: 'TEX_DepthCompareFunction_Always', +} +TEX_DepthCompareFunction_Never = 0 +TEX_DepthCompareFunction_Less = 1 +TEX_DepthCompareFunction_Equal = 2 +TEX_DepthCompareFunction_LessEqual = 3 +TEX_DepthCompareFunction_Greater = 4 +TEX_DepthCompareFunction_NotEqual = 5 +TEX_DepthCompareFunction_GreaterEqual = 6 +TEX_DepthCompareFunction_Always = 7 +TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_FORMAT_COMP' +TEX_FORMAT_COMP__enumvalues = { + 0: 'TEX_FormatComp_Unsigned', + 1: 'TEX_FormatComp_Signed', + 2: 'TEX_FormatComp_UnsignedBiased', + 3: 'TEX_FormatComp_RESERVED_3', +} +TEX_FormatComp_Unsigned = 0 +TEX_FormatComp_Signed = 1 +TEX_FormatComp_UnsignedBiased = 2 +TEX_FormatComp_RESERVED_3 = 3 +TEX_FORMAT_COMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MAX_ANISO_RATIO' +TEX_MAX_ANISO_RATIO__enumvalues = { + 0: 'TEX_MaxAnisoRatio_1to1', + 1: 'TEX_MaxAnisoRatio_2to1', + 2: 'TEX_MaxAnisoRatio_4to1', + 3: 'TEX_MaxAnisoRatio_8to1', + 4: 'TEX_MaxAnisoRatio_16to1', + 5: 'TEX_MaxAnisoRatio_RESERVED_5', + 6: 'TEX_MaxAnisoRatio_RESERVED_6', + 7: 'TEX_MaxAnisoRatio_RESERVED_7', +} +TEX_MaxAnisoRatio_1to1 = 0 +TEX_MaxAnisoRatio_2to1 = 1 +TEX_MaxAnisoRatio_4to1 = 2 +TEX_MaxAnisoRatio_8to1 = 3 +TEX_MaxAnisoRatio_16to1 = 4 +TEX_MaxAnisoRatio_RESERVED_5 = 5 +TEX_MaxAnisoRatio_RESERVED_6 = 6 +TEX_MaxAnisoRatio_RESERVED_7 = 7 +TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MIP_FILTER' +TEX_MIP_FILTER__enumvalues = { + 0: 'TEX_MipFilter_None', + 1: 'TEX_MipFilter_Point', + 2: 'TEX_MipFilter_Linear', + 3: 'TEX_MipFilter_Point_Aniso_Adj', +} +TEX_MipFilter_None = 0 +TEX_MipFilter_Point = 1 +TEX_MipFilter_Linear = 2 +TEX_MipFilter_Point_Aniso_Adj = 3 +TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_REQUEST_SIZE' +TEX_REQUEST_SIZE__enumvalues = { + 0: 'TEX_RequestSize_32B', + 1: 'TEX_RequestSize_64B', + 2: 'TEX_RequestSize_128B', + 3: 'TEX_RequestSize_2X64B', +} +TEX_RequestSize_32B = 0 +TEX_RequestSize_64B = 1 +TEX_RequestSize_128B = 2 +TEX_RequestSize_2X64B = 3 +TEX_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_SAMPLER_TYPE' +TEX_SAMPLER_TYPE__enumvalues = { + 0: 'TEX_SamplerType_Invalid', + 1: 'TEX_SamplerType_Valid', +} +TEX_SamplerType_Invalid = 0 +TEX_SamplerType_Valid = 1 +TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_XY_FILTER' +TEX_XY_FILTER__enumvalues = { + 0: 'TEX_XYFilter_Point', + 1: 'TEX_XYFilter_Linear', + 2: 'TEX_XYFilter_AnisoPoint', + 3: 'TEX_XYFilter_AnisoLinear', +} +TEX_XYFilter_Point = 0 +TEX_XYFilter_Linear = 1 +TEX_XYFilter_AnisoPoint = 2 +TEX_XYFilter_AnisoLinear = 3 +TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_Z_FILTER' +TEX_Z_FILTER__enumvalues = { + 0: 'TEX_ZFilter_None', + 1: 'TEX_ZFilter_Point', + 2: 'TEX_ZFilter_Linear', + 3: 'TEX_ZFilter_RESERVED_3', +} +TEX_ZFilter_None = 0 +TEX_ZFilter_Point = 1 +TEX_ZFilter_Linear = 2 +TEX_ZFilter_RESERVED_3 = 3 +TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_TYPE' +TVX_TYPE__enumvalues = { + 0: 'TVX_Type_InvalidTextureResource', + 1: 'TVX_Type_InvalidVertexBuffer', + 2: 'TVX_Type_ValidTextureResource', + 3: 'TVX_Type_ValidVertexBuffer', +} +TVX_Type_InvalidTextureResource = 0 +TVX_Type_InvalidVertexBuffer = 1 +TVX_Type_ValidTextureResource = 2 +TVX_Type_ValidVertexBuffer = 3 +TVX_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_ADDR_MODES' +TA_TC_ADDR_MODES__enumvalues = { + 0: 'TA_TC_ADDR_MODE_DEFAULT', + 1: 'TA_TC_ADDR_MODE_COMP0', + 2: 'TA_TC_ADDR_MODE_COMP1', + 3: 'TA_TC_ADDR_MODE_COMP2', + 4: 'TA_TC_ADDR_MODE_COMP3', + 5: 'TA_TC_ADDR_MODE_UNALIGNED', + 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', +} +TA_TC_ADDR_MODE_DEFAULT = 0 +TA_TC_ADDR_MODE_COMP0 = 1 +TA_TC_ADDR_MODE_COMP1 = 2 +TA_TC_ADDR_MODE_COMP2 = 3 +TA_TC_ADDR_MODE_COMP3 = 4 +TA_TC_ADDR_MODE_UNALIGNED = 5 +TA_TC_ADDR_MODE_BORDER_COLOR = 6 +TA_TC_ADDR_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_REQ_MODES' +TA_TC_REQ_MODES__enumvalues = { + 0: 'TA_TC_REQ_MODE_BORDER', + 1: 'TA_TC_REQ_MODE_TEX2', + 2: 'TA_TC_REQ_MODE_TEX1', + 3: 'TA_TC_REQ_MODE_TEX0', + 4: 'TA_TC_REQ_MODE_NORMAL', + 5: 'TA_TC_REQ_MODE_DWORD', + 6: 'TA_TC_REQ_MODE_BYTE', + 7: 'TA_TC_REQ_MODE_BYTE_NV', +} +TA_TC_REQ_MODE_BORDER = 0 +TA_TC_REQ_MODE_TEX2 = 1 +TA_TC_REQ_MODE_TEX1 = 2 +TA_TC_REQ_MODE_TEX0 = 3 +TA_TC_REQ_MODE_NORMAL = 4 +TA_TC_REQ_MODE_DWORD = 5 +TA_TC_REQ_MODE_BYTE = 6 +TA_TC_REQ_MODE_BYTE_NV = 7 +TA_TC_REQ_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_POLICIES' +TCP_CACHE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_POLICY_MISS_LRU', + 1: 'TCP_CACHE_POLICY_MISS_EVICT', + 2: 'TCP_CACHE_POLICY_HIT_LRU', + 3: 'TCP_CACHE_POLICY_HIT_EVICT', +} +TCP_CACHE_POLICY_MISS_LRU = 0 +TCP_CACHE_POLICY_MISS_EVICT = 1 +TCP_CACHE_POLICY_HIT_LRU = 2 +TCP_CACHE_POLICY_HIT_EVICT = 3 +TCP_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_STORE_POLICIES' +TCP_CACHE_STORE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', + 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', +} +TCP_CACHE_STORE_POLICY_WT_LRU = 0 +TCP_CACHE_STORE_POLICY_WT_EVICT = 1 +TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_DATA_SEL' +TCP_DSM_DATA_SEL__enumvalues = { + 0: 'TCP_DSM_DISABLE', + 1: 'TCP_DSM_SEL0', + 2: 'TCP_DSM_SEL1', + 3: 'TCP_DSM_SEL_BOTH', +} +TCP_DSM_DISABLE = 0 +TCP_DSM_SEL0 = 1 +TCP_DSM_SEL1 = 2 +TCP_DSM_SEL_BOTH = 3 +TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_INJECT_SEL' +TCP_DSM_INJECT_SEL__enumvalues = { + 0: 'TCP_DSM_INJECT_SEL0', + 1: 'TCP_DSM_INJECT_SEL1', + 2: 'TCP_DSM_INJECT_SEL2', + 3: 'TCP_DSM_INJECT_SEL3', +} +TCP_DSM_INJECT_SEL0 = 0 +TCP_DSM_INJECT_SEL1 = 1 +TCP_DSM_INJECT_SEL2 = 2 +TCP_DSM_INJECT_SEL3 = 3 +TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_SINGLE_WRITE' +TCP_DSM_SINGLE_WRITE__enumvalues = { + 0: 'TCP_DSM_SINGLE_WRITE_DIS', + 1: 'TCP_DSM_SINGLE_WRITE_EN', +} +TCP_DSM_SINGLE_WRITE_DIS = 0 +TCP_DSM_SINGLE_WRITE_EN = 1 +TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_OPCODE_TYPE' +TCP_OPCODE_TYPE__enumvalues = { + 0: 'TCP_OPCODE_READ', + 1: 'TCP_OPCODE_WRITE', + 2: 'TCP_OPCODE_ATOMIC', + 3: 'TCP_OPCODE_INV', + 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', + 5: 'TCP_OPCODE_SAMPLER', + 6: 'TCP_OPCODE_LOAD', + 7: 'TCP_OPCODE_GATHERH', +} +TCP_OPCODE_READ = 0 +TCP_OPCODE_WRITE = 1 +TCP_OPCODE_ATOMIC = 2 +TCP_OPCODE_INV = 3 +TCP_OPCODE_ATOMIC_CMPSWAP = 4 +TCP_OPCODE_SAMPLER = 5 +TCP_OPCODE_LOAD = 6 +TCP_OPCODE_GATHERH = 7 +TCP_OPCODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_PERFCOUNT_SELECT' +TCP_PERFCOUNT_SELECT__enumvalues = { + 0: 'TCP_PERF_SEL_GATE_EN1', + 1: 'TCP_PERF_SEL_GATE_EN2', + 2: 'TCP_PERF_SEL_TA_REQ', + 3: 'TCP_PERF_SEL_TA_REQ_STATE_READ', + 4: 'TCP_PERF_SEL_TA_REQ_READ', + 5: 'TCP_PERF_SEL_TA_REQ_WRITE', + 6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 8: 'TCP_PERF_SEL_TA_REQ_GL0_INV', + 9: 'TCP_PERF_SEL_REQ', + 10: 'TCP_PERF_SEL_REQ_READ', + 11: 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', + 12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 14: 'TCP_PERF_SEL_REQ_WRITE', + 15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 16: 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', + 17: 'TCP_PERF_SEL_REQ_NON_READ', + 18: 'TCP_PERF_SEL_REQ_MISS', + 19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 20: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 22: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 24: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 26: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', + 27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 30: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', + 31: 'TCP_PERF_SEL_GL1_REQ_READ', + 32: 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 33: 'TCP_PERF_SEL_GL1_REQ_READ_64B', + 34: 'TCP_PERF_SEL_GL1_REQ_WRITE', + 35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 36: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 37: 'TCP_PERF_SEL_GL1_READ_LATENCY', + 38: 'TCP_PERF_SEL_GL1_WRITE_LATENCY', + 39: 'TCP_PERF_SEL_TCP_LATENCY', + 40: 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 41: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', + 42: 'TCP_PERF_SEL_DATA_FIFO_STALL', + 43: 'TCP_PERF_SEL_LOD_STALL', + 44: 'TCP_PERF_SEL_POWER_STALL', + 45: 'TCP_PERF_SEL_ALLOC_STALL', + 46: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 47: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', + 48: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', + 49: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 50: 'TCP_PERF_SEL_LFIFO_STALL', + 51: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 52: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 53: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 54: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 55: 'TCP_PERF_SEL_GL1_PENDING_STALL', + 56: 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', + 57: 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', + 58: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', + 59: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 60: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 61: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 62: 'TCP_PERF_SEL_TD_TCP_STALL', +} +TCP_PERF_SEL_GATE_EN1 = 0 +TCP_PERF_SEL_GATE_EN2 = 1 +TCP_PERF_SEL_TA_REQ = 2 +TCP_PERF_SEL_TA_REQ_STATE_READ = 3 +TCP_PERF_SEL_TA_REQ_READ = 4 +TCP_PERF_SEL_TA_REQ_WRITE = 5 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7 +TCP_PERF_SEL_TA_REQ_GL0_INV = 8 +TCP_PERF_SEL_REQ = 9 +TCP_PERF_SEL_REQ_READ = 10 +TCP_PERF_SEL_REQ_READ_HIT_EVICT = 11 +TCP_PERF_SEL_REQ_READ_HIT_LRU = 12 +TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13 +TCP_PERF_SEL_REQ_WRITE = 14 +TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15 +TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 16 +TCP_PERF_SEL_REQ_NON_READ = 17 +TCP_PERF_SEL_REQ_MISS = 18 +TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 19 +TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 20 +TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 21 +TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 22 +TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 23 +TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 24 +TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 25 +TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 26 +TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 27 +TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 28 +TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 29 +TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 30 +TCP_PERF_SEL_GL1_REQ_READ = 31 +TCP_PERF_SEL_GL1_REQ_READ_128B = 32 +TCP_PERF_SEL_GL1_REQ_READ_64B = 33 +TCP_PERF_SEL_GL1_REQ_WRITE = 34 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 35 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 36 +TCP_PERF_SEL_GL1_READ_LATENCY = 37 +TCP_PERF_SEL_GL1_WRITE_LATENCY = 38 +TCP_PERF_SEL_TCP_LATENCY = 39 +TCP_PERF_SEL_TCP_TA_REQ_STALL = 40 +TCP_PERF_SEL_TA_TCP_REQ_STARVE = 41 +TCP_PERF_SEL_DATA_FIFO_STALL = 42 +TCP_PERF_SEL_LOD_STALL = 43 +TCP_PERF_SEL_POWER_STALL = 44 +TCP_PERF_SEL_ALLOC_STALL = 45 +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 46 +TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 47 +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 48 +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 49 +TCP_PERF_SEL_LFIFO_STALL = 50 +TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 51 +TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 52 +TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 53 +TCP_PERF_SEL_GL1_GRANT_READ_STALL = 54 +TCP_PERF_SEL_GL1_PENDING_STALL = 55 +TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 56 +TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 57 +TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 58 +TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 59 +TCP_PERF_SEL_READ_DATACONFLICT_STALL = 60 +TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 61 +TCP_PERF_SEL_TD_TCP_STALL = 62 +TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WATCH_MODES' +TCP_WATCH_MODES__enumvalues = { + 0: 'TCP_WATCH_MODE_READ', + 1: 'TCP_WATCH_MODE_NONREAD', + 2: 'TCP_WATCH_MODE_ATOMIC', + 3: 'TCP_WATCH_MODE_ALL', +} +TCP_WATCH_MODE_READ = 0 +TCP_WATCH_MODE_NONREAD = 1 +TCP_WATCH_MODE_ATOMIC = 2 +TCP_WATCH_MODE_ALL = 3 +TCP_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TD_PERFCOUNT_SEL' +TD_PERFCOUNT_SEL__enumvalues = { + 0: 'TD_PERF_SEL_none', + 1: 'TD_PERF_SEL_td_busy', + 2: 'TD_PERF_SEL_input_busy', + 3: 'TD_PERF_SEL_sampler_lerp_busy', + 4: 'TD_PERF_SEL_sampler_out_busy', + 5: 'TD_PERF_SEL_nofilter_busy', + 6: 'TD_PERF_SEL_ray_tracing_bvh4_busy', + 7: 'TD_PERF_SEL_sampler_core_sclk_en', + 8: 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 9: 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 10: 'TD_PERF_SEL_sampler_bypass_sclk_en', + 11: 'TD_PERF_SEL_sampler_minmax_sclk_en', + 12: 'TD_PERF_SEL_sampler_accum_sclk_en', + 13: 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 15: 'TD_PERF_SEL_sampler_out_sclk_en', + 16: 'TD_PERF_SEL_nofilter_sclk_en', + 17: 'TD_PERF_SEL_nofilter_d32_sclk_en', + 18: 'TD_PERF_SEL_nofilter_d16_sclk_en', + 22: 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', + 23: 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', + 24: 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', + 25: 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', + 26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 29: 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', + 30: 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', + 31: 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', + 32: 'TD_PERF_SEL_core_state_ram_max_cnt', + 33: 'TD_PERF_SEL_core_state_rams_read', + 34: 'TD_PERF_SEL_weight_data_rams_read', + 35: 'TD_PERF_SEL_reference_data_rams_read', + 36: 'TD_PERF_SEL_tc_td_ram_fifo_full', + 37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', + 38: 'TD_PERF_SEL_tc_td_data_fifo_full', + 39: 'TD_PERF_SEL_input_state_fifo_full', + 40: 'TD_PERF_SEL_ta_data_stall', + 41: 'TD_PERF_SEL_tc_data_stall', + 42: 'TD_PERF_SEL_tc_ram_stall', + 43: 'TD_PERF_SEL_lds_stall', + 44: 'TD_PERF_SEL_sampler_pkr_full', + 45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 46: 'TD_PERF_SEL_nofilter_pkr_full', + 47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 48: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', + 49: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', + 50: 'TD_PERF_SEL_gather4_instr', + 51: 'TD_PERF_SEL_gather4h_instr', + 54: 'TD_PERF_SEL_sample_instr', + 55: 'TD_PERF_SEL_sample_c_instr', + 56: 'TD_PERF_SEL_load_instr', + 57: 'TD_PERF_SEL_ldfptr_instr', + 58: 'TD_PERF_SEL_write_ack_instr', + 59: 'TD_PERF_SEL_d16_en_instr', + 60: 'TD_PERF_SEL_bypassLerp_instr', + 61: 'TD_PERF_SEL_min_max_filter_instr', + 62: 'TD_PERF_SEL_one_comp_return_instr', + 63: 'TD_PERF_SEL_two_comp_return_instr', + 64: 'TD_PERF_SEL_three_comp_return_instr', + 65: 'TD_PERF_SEL_four_comp_return_instr', + 66: 'TD_PERF_SEL_user_defined_border', + 67: 'TD_PERF_SEL_white_border', + 68: 'TD_PERF_SEL_opaque_black_border', + 69: 'TD_PERF_SEL_lod_warn_from_ta', + 70: 'TD_PERF_SEL_instruction_dest_is_lds', + 71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 75: 'TD_PERF_SEL_out_of_order_instr', + 76: 'TD_PERF_SEL_total_num_instr', + 77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 78: 'TD_PERF_SEL_total_num_sampler_instr', + 79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 80: 'TD_PERF_SEL_total_num_nofilter_instr', + 81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 82: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', + 83: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', + 84: 'TD_PERF_SEL_mixmode_instr', + 85: 'TD_PERF_SEL_mixmode_resource', + 86: 'TD_PERF_SEL_status_packet', + 87: 'TD_PERF_SEL_address_cmd_poison', + 88: 'TD_PERF_SEL_data_poison', + 89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 91: 'TD_PERF_SEL_done_scoreboard_not_empty', + 92: 'TD_PERF_SEL_done_scoreboard_is_full', + 93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 95: 'TD_PERF_SEL_nofilter_formatters_turned_on', + 96: 'TD_PERF_SEL_nofilter_insert_extra_comps', + 97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 99: 'TD_PERF_SEL_msaa_load_instr', + 100: 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 101: 'TD_PERF_SEL_blend_prt_with_prt_default_1', + 102: 'TD_PERF_SEL_resmap_instr', + 103: 'TD_PERF_SEL_prt_ack_instr', + 104: 'TD_PERF_SEL_resmap_with_volume_filtering', + 105: 'TD_PERF_SEL_resmap_with_aniso_filtering', + 106: 'TD_PERF_SEL_resmap_with_no_more_filtering', + 107: 'TD_PERF_SEL_resmap_with_cubemap_corner', + 108: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', + 109: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', + 110: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', + 111: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', + 112: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', + 113: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', + 114: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', + 115: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', + 116: 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', + 117: 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', + 118: 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', + 119: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', + 120: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', + 121: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', + 122: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', + 123: 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', + 124: 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', + 125: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', + 126: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', + 127: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', + 128: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', + 129: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', + 130: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', + 131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 136: 'TD_PERF_SEL_burst_bin_sampler_1', + 137: 'TD_PERF_SEL_burst_bin_sampler_2to8', + 138: 'TD_PERF_SEL_burst_bin_sampler_9to16', + 139: 'TD_PERF_SEL_burst_bin_sampler_gt16', + 140: 'TD_PERF_SEL_burst_bin_gather_1', + 141: 'TD_PERF_SEL_burst_bin_gather_2to8', + 142: 'TD_PERF_SEL_burst_bin_gather_9to16', + 143: 'TD_PERF_SEL_burst_bin_gather_gt16', + 144: 'TD_PERF_SEL_burst_bin_nofilter_1', + 145: 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 146: 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 147: 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 148: 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 149: 'TD_PERF_SEL_burst_bin_bvh4_1', + 150: 'TD_PERF_SEL_burst_bin_bvh4_2to8', + 151: 'TD_PERF_SEL_burst_bin_bvh4_9to16', + 152: 'TD_PERF_SEL_burst_bin_bvh4_gt16', + 153: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', + 154: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', + 155: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', + 156: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', + 157: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', + 158: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', + 159: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', + 160: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', + 161: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', + 162: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', + 163: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', + 164: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', + 165: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', + 166: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', + 167: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', + 168: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', + 169: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', + 170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 180: 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 181: 'TD_PERF_SEL_sampler_lerp0_active', + 182: 'TD_PERF_SEL_sampler_lerp1_active', + 183: 'TD_PERF_SEL_sampler_lerp2_active', + 184: 'TD_PERF_SEL_sampler_lerp3_active', + 185: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', + 186: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 187: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 188: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 189: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 190: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 191: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 192: 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', +} +TD_PERF_SEL_none = 0 +TD_PERF_SEL_td_busy = 1 +TD_PERF_SEL_input_busy = 2 +TD_PERF_SEL_sampler_lerp_busy = 3 +TD_PERF_SEL_sampler_out_busy = 4 +TD_PERF_SEL_nofilter_busy = 5 +TD_PERF_SEL_ray_tracing_bvh4_busy = 6 +TD_PERF_SEL_sampler_core_sclk_en = 7 +TD_PERF_SEL_sampler_preformatter_sclk_en = 8 +TD_PERF_SEL_sampler_bilerp_sclk_en = 9 +TD_PERF_SEL_sampler_bypass_sclk_en = 10 +TD_PERF_SEL_sampler_minmax_sclk_en = 11 +TD_PERF_SEL_sampler_accum_sclk_en = 12 +TD_PERF_SEL_sampler_format_flt_sclk_en = 13 +TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14 +TD_PERF_SEL_sampler_out_sclk_en = 15 +TD_PERF_SEL_nofilter_sclk_en = 16 +TD_PERF_SEL_nofilter_d32_sclk_en = 17 +TD_PERF_SEL_nofilter_d16_sclk_en = 18 +TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 22 +TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 23 +TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 24 +TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 25 +TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26 +TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27 +TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28 +TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 29 +TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 30 +TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 31 +TD_PERF_SEL_core_state_ram_max_cnt = 32 +TD_PERF_SEL_core_state_rams_read = 33 +TD_PERF_SEL_weight_data_rams_read = 34 +TD_PERF_SEL_reference_data_rams_read = 35 +TD_PERF_SEL_tc_td_ram_fifo_full = 36 +TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37 +TD_PERF_SEL_tc_td_data_fifo_full = 38 +TD_PERF_SEL_input_state_fifo_full = 39 +TD_PERF_SEL_ta_data_stall = 40 +TD_PERF_SEL_tc_data_stall = 41 +TD_PERF_SEL_tc_ram_stall = 42 +TD_PERF_SEL_lds_stall = 43 +TD_PERF_SEL_sampler_pkr_full = 44 +TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45 +TD_PERF_SEL_nofilter_pkr_full = 46 +TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47 +TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 48 +TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 49 +TD_PERF_SEL_gather4_instr = 50 +TD_PERF_SEL_gather4h_instr = 51 +TD_PERF_SEL_sample_instr = 54 +TD_PERF_SEL_sample_c_instr = 55 +TD_PERF_SEL_load_instr = 56 +TD_PERF_SEL_ldfptr_instr = 57 +TD_PERF_SEL_write_ack_instr = 58 +TD_PERF_SEL_d16_en_instr = 59 +TD_PERF_SEL_bypassLerp_instr = 60 +TD_PERF_SEL_min_max_filter_instr = 61 +TD_PERF_SEL_one_comp_return_instr = 62 +TD_PERF_SEL_two_comp_return_instr = 63 +TD_PERF_SEL_three_comp_return_instr = 64 +TD_PERF_SEL_four_comp_return_instr = 65 +TD_PERF_SEL_user_defined_border = 66 +TD_PERF_SEL_white_border = 67 +TD_PERF_SEL_opaque_black_border = 68 +TD_PERF_SEL_lod_warn_from_ta = 69 +TD_PERF_SEL_instruction_dest_is_lds = 70 +TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71 +TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74 +TD_PERF_SEL_out_of_order_instr = 75 +TD_PERF_SEL_total_num_instr = 76 +TD_PERF_SEL_total_num_instr_with_perf_wdw = 77 +TD_PERF_SEL_total_num_sampler_instr = 78 +TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79 +TD_PERF_SEL_total_num_nofilter_instr = 80 +TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81 +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 82 +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 83 +TD_PERF_SEL_mixmode_instr = 84 +TD_PERF_SEL_mixmode_resource = 85 +TD_PERF_SEL_status_packet = 86 +TD_PERF_SEL_address_cmd_poison = 87 +TD_PERF_SEL_data_poison = 88 +TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89 +TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90 +TD_PERF_SEL_done_scoreboard_not_empty = 91 +TD_PERF_SEL_done_scoreboard_is_full = 92 +TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93 +TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94 +TD_PERF_SEL_nofilter_formatters_turned_on = 95 +TD_PERF_SEL_nofilter_insert_extra_comps = 96 +TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97 +TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98 +TD_PERF_SEL_msaa_load_instr = 99 +TD_PERF_SEL_blend_prt_with_prt_default_0 = 100 +TD_PERF_SEL_blend_prt_with_prt_default_1 = 101 +TD_PERF_SEL_resmap_instr = 102 +TD_PERF_SEL_prt_ack_instr = 103 +TD_PERF_SEL_resmap_with_volume_filtering = 104 +TD_PERF_SEL_resmap_with_aniso_filtering = 105 +TD_PERF_SEL_resmap_with_no_more_filtering = 106 +TD_PERF_SEL_resmap_with_cubemap_corner = 107 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 108 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 109 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 110 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 111 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 112 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 113 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 114 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 115 +TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 116 +TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 117 +TD_PERF_SEL_ray_tracing_bvh4_tri_node = 118 +TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 119 +TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 120 +TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 121 +TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 122 +TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 123 +TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 124 +TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 125 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 126 +TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 127 +TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 128 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 129 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 130 +TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131 +TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132 +TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133 +TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134 +TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135 +TD_PERF_SEL_burst_bin_sampler_1 = 136 +TD_PERF_SEL_burst_bin_sampler_2to8 = 137 +TD_PERF_SEL_burst_bin_sampler_9to16 = 138 +TD_PERF_SEL_burst_bin_sampler_gt16 = 139 +TD_PERF_SEL_burst_bin_gather_1 = 140 +TD_PERF_SEL_burst_bin_gather_2to8 = 141 +TD_PERF_SEL_burst_bin_gather_9to16 = 142 +TD_PERF_SEL_burst_bin_gather_gt16 = 143 +TD_PERF_SEL_burst_bin_nofilter_1 = 144 +TD_PERF_SEL_burst_bin_nofilter_2to4 = 145 +TD_PERF_SEL_burst_bin_nofilter_5to7 = 146 +TD_PERF_SEL_burst_bin_nofilter_8to16 = 147 +TD_PERF_SEL_burst_bin_nofilter_gt16 = 148 +TD_PERF_SEL_burst_bin_bvh4_1 = 149 +TD_PERF_SEL_burst_bin_bvh4_2to8 = 150 +TD_PERF_SEL_burst_bin_bvh4_9to16 = 151 +TD_PERF_SEL_burst_bin_bvh4_gt16 = 152 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 153 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 154 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 155 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 156 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 157 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 158 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 159 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 160 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 161 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 162 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 163 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 164 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 165 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 166 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 167 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 168 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 169 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175 +TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176 +TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177 +TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178 +TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179 +TD_PERF_SEL_preempting_nofilter_max_cnt = 180 +TD_PERF_SEL_sampler_lerp0_active = 181 +TD_PERF_SEL_sampler_lerp1_active = 182 +TD_PERF_SEL_sampler_lerp2_active = 183 +TD_PERF_SEL_sampler_lerp3_active = 184 +TD_PERF_SEL_nofilter_total_num_comps_to_lds = 185 +TD_PERF_SEL_nofilter_byte_cycling_4cycles = 186 +TD_PERF_SEL_nofilter_byte_cycling_8cycles = 187 +TD_PERF_SEL_nofilter_byte_cycling_16cycles = 188 +TD_PERF_SEL_nofilter_dword_cycling_2cycles = 189 +TD_PERF_SEL_nofilter_dword_cycling_4cycles = 190 +TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 191 +TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 192 +TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2A_PERF_SEL' +GL2A_PERF_SEL__enumvalues = { + 0: 'GL2A_PERF_SEL_NONE', + 1: 'GL2A_PERF_SEL_CYCLE', + 2: 'GL2A_PERF_SEL_BUSY', + 3: 'GL2A_PERF_SEL_REQ_GL2C0', + 4: 'GL2A_PERF_SEL_REQ_GL2C1', + 5: 'GL2A_PERF_SEL_REQ_GL2C2', + 6: 'GL2A_PERF_SEL_REQ_GL2C3', + 7: 'GL2A_PERF_SEL_REQ_GL2C4', + 8: 'GL2A_PERF_SEL_REQ_GL2C5', + 9: 'GL2A_PERF_SEL_REQ_GL2C6', + 10: 'GL2A_PERF_SEL_REQ_GL2C7', + 11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', + 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', + 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', + 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', + 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', + 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', + 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', + 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', + 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', + 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', + 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', + 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', + 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 43: 'GL2A_PERF_SEL_RTN_CLIENT0', + 44: 'GL2A_PERF_SEL_RTN_CLIENT1', + 45: 'GL2A_PERF_SEL_RTN_CLIENT2', + 46: 'GL2A_PERF_SEL_RTN_CLIENT3', + 47: 'GL2A_PERF_SEL_RTN_CLIENT4', + 48: 'GL2A_PERF_SEL_RTN_CLIENT5', + 49: 'GL2A_PERF_SEL_RTN_CLIENT6', + 50: 'GL2A_PERF_SEL_RTN_CLIENT7', + 51: 'GL2A_PERF_SEL_RTN_CLIENT8', + 52: 'GL2A_PERF_SEL_RTN_CLIENT9', + 53: 'GL2A_PERF_SEL_RTN_CLIENT10', + 54: 'GL2A_PERF_SEL_RTN_CLIENT11', + 55: 'GL2A_PERF_SEL_RTN_CLIENT12', + 56: 'GL2A_PERF_SEL_RTN_CLIENT13', + 57: 'GL2A_PERF_SEL_RTN_CLIENT14', + 58: 'GL2A_PERF_SEL_RTN_CLIENT15', + 59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', +} +GL2A_PERF_SEL_NONE = 0 +GL2A_PERF_SEL_CYCLE = 1 +GL2A_PERF_SEL_BUSY = 2 +GL2A_PERF_SEL_REQ_GL2C0 = 3 +GL2A_PERF_SEL_REQ_GL2C1 = 4 +GL2A_PERF_SEL_REQ_GL2C2 = 5 +GL2A_PERF_SEL_REQ_GL2C3 = 6 +GL2A_PERF_SEL_REQ_GL2C4 = 7 +GL2A_PERF_SEL_REQ_GL2C5 = 8 +GL2A_PERF_SEL_REQ_GL2C6 = 9 +GL2A_PERF_SEL_REQ_GL2C7 = 10 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18 +GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 +GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 +GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 +GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 +GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 +GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 +GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 +GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 +GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 +GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 +GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 +GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 +GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 +GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 +GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 +GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 +GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 +GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 +GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 +GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 +GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 +GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 +GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 +GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 +GL2A_PERF_SEL_RTN_CLIENT0 = 43 +GL2A_PERF_SEL_RTN_CLIENT1 = 44 +GL2A_PERF_SEL_RTN_CLIENT2 = 45 +GL2A_PERF_SEL_RTN_CLIENT3 = 46 +GL2A_PERF_SEL_RTN_CLIENT4 = 47 +GL2A_PERF_SEL_RTN_CLIENT5 = 48 +GL2A_PERF_SEL_RTN_CLIENT6 = 49 +GL2A_PERF_SEL_RTN_CLIENT7 = 50 +GL2A_PERF_SEL_RTN_CLIENT8 = 51 +GL2A_PERF_SEL_RTN_CLIENT9 = 52 +GL2A_PERF_SEL_RTN_CLIENT10 = 53 +GL2A_PERF_SEL_RTN_CLIENT11 = 54 +GL2A_PERF_SEL_RTN_CLIENT12 = 55 +GL2A_PERF_SEL_RTN_CLIENT13 = 56 +GL2A_PERF_SEL_RTN_CLIENT14 = 57 +GL2A_PERF_SEL_RTN_CLIENT15 = 58 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74 +GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75 +GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76 +GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77 +GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78 +GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79 +GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80 +GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81 +GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82 +GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83 +GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84 +GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85 +GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86 +GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87 +GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88 +GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89 +GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107 +GL2A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2C_PERF_SEL' +GL2C_PERF_SEL__enumvalues = { + 0: 'GL2C_PERF_SEL_NONE', + 1: 'GL2C_PERF_SEL_CYCLE', + 2: 'GL2C_PERF_SEL_BUSY', + 3: 'GL2C_PERF_SEL_REQ', + 4: 'GL2C_PERF_SEL_VOL_REQ', + 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', + 6: 'GL2C_PERF_SEL_READ', + 7: 'GL2C_PERF_SEL_WRITE', + 8: 'GL2C_PERF_SEL_ATOMIC', + 9: 'GL2C_PERF_SEL_NOP_ACK', + 10: 'GL2C_PERF_SEL_NOP_RTN0', + 11: 'GL2C_PERF_SEL_PROBE', + 12: 'GL2C_PERF_SEL_PROBE_ALL', + 13: 'GL2C_PERF_SEL_INTERNAL_PROBE', + 14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', + 15: 'GL2C_PERF_SEL_METADATA_READ_REQ', + 16: 'GL2C_PERF_SEL_CLIENT0_REQ', + 17: 'GL2C_PERF_SEL_CLIENT1_REQ', + 18: 'GL2C_PERF_SEL_CLIENT2_REQ', + 19: 'GL2C_PERF_SEL_CLIENT3_REQ', + 20: 'GL2C_PERF_SEL_CLIENT4_REQ', + 21: 'GL2C_PERF_SEL_CLIENT5_REQ', + 22: 'GL2C_PERF_SEL_CLIENT6_REQ', + 23: 'GL2C_PERF_SEL_CLIENT7_REQ', + 24: 'GL2C_PERF_SEL_CLIENT8_REQ', + 25: 'GL2C_PERF_SEL_CLIENT9_REQ', + 26: 'GL2C_PERF_SEL_CLIENT10_REQ', + 27: 'GL2C_PERF_SEL_CLIENT11_REQ', + 28: 'GL2C_PERF_SEL_CLIENT12_REQ', + 29: 'GL2C_PERF_SEL_CLIENT13_REQ', + 30: 'GL2C_PERF_SEL_CLIENT14_REQ', + 31: 'GL2C_PERF_SEL_CLIENT15_REQ', + 32: 'GL2C_PERF_SEL_C_RW_S_REQ', + 33: 'GL2C_PERF_SEL_C_RW_US_REQ', + 34: 'GL2C_PERF_SEL_C_RO_S_REQ', + 35: 'GL2C_PERF_SEL_C_RO_US_REQ', + 36: 'GL2C_PERF_SEL_UC_REQ', + 37: 'GL2C_PERF_SEL_LRU_REQ', + 38: 'GL2C_PERF_SEL_STREAM_REQ', + 39: 'GL2C_PERF_SEL_BYPASS_REQ', + 40: 'GL2C_PERF_SEL_NOA_REQ', + 41: 'GL2C_PERF_SEL_SHARED_REQ', + 42: 'GL2C_PERF_SEL_HIT', + 43: 'GL2C_PERF_SEL_MISS', + 44: 'GL2C_PERF_SEL_FULL_HIT', + 45: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', + 46: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 47: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', + 48: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', + 49: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', + 50: 'GL2C_PERF_SEL_UNCACHED_WRITE', + 51: 'GL2C_PERF_SEL_WRITEBACK', + 52: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 53: 'GL2C_PERF_SEL_EVICT', + 54: 'GL2C_PERF_SEL_NORMAL_EVICT', + 55: 'GL2C_PERF_SEL_PROBE_EVICT', + 56: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', + 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', + 67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 69: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 70: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 71: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 72: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 73: 'GL2C_PERF_SEL_READ_32_REQ', + 74: 'GL2C_PERF_SEL_READ_64_REQ', + 75: 'GL2C_PERF_SEL_READ_128_REQ', + 76: 'GL2C_PERF_SEL_WRITE_32_REQ', + 77: 'GL2C_PERF_SEL_WRITE_64_REQ', + 78: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 79: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 80: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 81: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 82: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 83: 'GL2C_PERF_SEL_MC_WRREQ', + 84: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', + 85: 'GL2C_PERF_SEL_EA_WRREQ_64B', + 86: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 87: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', + 88: 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 89: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 90: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 91: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 92: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 93: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', + 94: 'GL2C_PERF_SEL_EA_ATOMIC', + 95: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', + 96: 'GL2C_PERF_SEL_MC_RDREQ', + 97: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', + 98: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 99: 'GL2C_PERF_SEL_EA_RDREQ_32B', + 100: 'GL2C_PERF_SEL_EA_RDREQ_64B', + 101: 'GL2C_PERF_SEL_EA_RDREQ_96B', + 102: 'GL2C_PERF_SEL_EA_RDREQ_128B', + 103: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 104: 'GL2C_PERF_SEL_EA_RD_MDC_32B', + 105: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 106: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 107: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 108: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 109: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', + 110: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', + 111: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 112: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 113: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 114: 'GL2C_PERF_SEL_ONION_READ', + 115: 'GL2C_PERF_SEL_ONION_WRITE', + 116: 'GL2C_PERF_SEL_IO_READ', + 117: 'GL2C_PERF_SEL_IO_WRITE', + 118: 'GL2C_PERF_SEL_GARLIC_READ', + 119: 'GL2C_PERF_SEL_GARLIC_WRITE', + 120: 'GL2C_PERF_SEL_EA_OUTSTANDING', + 121: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 122: 'GL2C_PERF_SEL_SRC_FIFO_FULL', + 123: 'GL2C_PERF_SEL_TAG_STALL', + 124: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 125: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 126: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 127: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 128: 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 129: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 130: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 131: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', + 132: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', + 133: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 134: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 135: 'GL2C_PERF_SEL_BUBBLE', + 136: 'GL2C_PERF_SEL_IB_REQ', + 137: 'GL2C_PERF_SEL_IB_STALL', + 138: 'GL2C_PERF_SEL_IB_TAG_STALL', + 139: 'GL2C_PERF_SEL_IB_CM_STALL', + 140: 'GL2C_PERF_SEL_RETURN_ACK', + 141: 'GL2C_PERF_SEL_RETURN_DATA', + 142: 'GL2C_PERF_SEL_EA_RDRET_NACK', + 143: 'GL2C_PERF_SEL_EA_WRRET_NACK', + 144: 'GL2C_PERF_SEL_GL2A_LEVEL', + 145: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 146: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 147: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 148: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 149: 'GL2C_PERF_SEL_GCR_INV', + 150: 'GL2C_PERF_SEL_GCR_WB', + 151: 'GL2C_PERF_SEL_GCR_DISCARD', + 152: 'GL2C_PERF_SEL_GCR_RANGE', + 153: 'GL2C_PERF_SEL_GCR_ALL', + 154: 'GL2C_PERF_SEL_GCR_VOL', + 155: 'GL2C_PERF_SEL_GCR_UNSHARED', + 156: 'GL2C_PERF_SEL_GCR_MDC_INV', + 157: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 158: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 159: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 160: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', + 161: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', + 162: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 163: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', + 164: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 165: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 166: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 167: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 168: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 169: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 170: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 171: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', + 172: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 173: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', + 174: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 175: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 176: 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 177: 'GL2C_PERF_SEL_MDC_INV_METADATA', + 178: 'GL2C_PERF_SEL_MDC_REQ', + 179: 'GL2C_PERF_SEL_MDC_LEVEL', + 180: 'GL2C_PERF_SEL_MDC_TAG_HIT', + 181: 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 182: 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 183: 'GL2C_PERF_SEL_MDC_TAG_STALL', + 184: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 185: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 186: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 187: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', + 188: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 189: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 190: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 191: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', + 192: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 193: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', + 194: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 195: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', + 196: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 197: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 198: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 199: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 200: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 201: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 202: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 203: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 204: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 205: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 206: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', + 207: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 208: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 209: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 210: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 211: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 212: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 213: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 214: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 215: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 216: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', + 217: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 218: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', + 219: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 220: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 221: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 222: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', + 223: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 224: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 225: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 226: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 227: 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 228: 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 229: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', + 230: 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 231: 'GL2C_PERF_SEL_CM_NO_ACK_REQ', + 232: 'GL2C_PERF_SEL_CM_NOOP_REQ', + 233: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 234: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 235: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 236: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 237: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 238: 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', + 239: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 240: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 241: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 242: 'GL2C_PERF_SEL_CM_RVF_FULL', + 243: 'GL2C_PERF_SEL_CM_SDR_FULL', + 244: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 245: 'GL2C_PERF_SEL_CM_DCC_STALL', + 246: 'GL2C_PERF_SEL_CM_DCC_IN_XFC', + 247: 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', + 248: 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', + 249: 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', + 250: 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', + 251: 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', + 252: 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', + 253: 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', + 254: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 255: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 256: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 257: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', +} +GL2C_PERF_SEL_NONE = 0 +GL2C_PERF_SEL_CYCLE = 1 +GL2C_PERF_SEL_BUSY = 2 +GL2C_PERF_SEL_REQ = 3 +GL2C_PERF_SEL_VOL_REQ = 4 +GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 +GL2C_PERF_SEL_READ = 6 +GL2C_PERF_SEL_WRITE = 7 +GL2C_PERF_SEL_ATOMIC = 8 +GL2C_PERF_SEL_NOP_ACK = 9 +GL2C_PERF_SEL_NOP_RTN0 = 10 +GL2C_PERF_SEL_PROBE = 11 +GL2C_PERF_SEL_PROBE_ALL = 12 +GL2C_PERF_SEL_INTERNAL_PROBE = 13 +GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14 +GL2C_PERF_SEL_METADATA_READ_REQ = 15 +GL2C_PERF_SEL_CLIENT0_REQ = 16 +GL2C_PERF_SEL_CLIENT1_REQ = 17 +GL2C_PERF_SEL_CLIENT2_REQ = 18 +GL2C_PERF_SEL_CLIENT3_REQ = 19 +GL2C_PERF_SEL_CLIENT4_REQ = 20 +GL2C_PERF_SEL_CLIENT5_REQ = 21 +GL2C_PERF_SEL_CLIENT6_REQ = 22 +GL2C_PERF_SEL_CLIENT7_REQ = 23 +GL2C_PERF_SEL_CLIENT8_REQ = 24 +GL2C_PERF_SEL_CLIENT9_REQ = 25 +GL2C_PERF_SEL_CLIENT10_REQ = 26 +GL2C_PERF_SEL_CLIENT11_REQ = 27 +GL2C_PERF_SEL_CLIENT12_REQ = 28 +GL2C_PERF_SEL_CLIENT13_REQ = 29 +GL2C_PERF_SEL_CLIENT14_REQ = 30 +GL2C_PERF_SEL_CLIENT15_REQ = 31 +GL2C_PERF_SEL_C_RW_S_REQ = 32 +GL2C_PERF_SEL_C_RW_US_REQ = 33 +GL2C_PERF_SEL_C_RO_S_REQ = 34 +GL2C_PERF_SEL_C_RO_US_REQ = 35 +GL2C_PERF_SEL_UC_REQ = 36 +GL2C_PERF_SEL_LRU_REQ = 37 +GL2C_PERF_SEL_STREAM_REQ = 38 +GL2C_PERF_SEL_BYPASS_REQ = 39 +GL2C_PERF_SEL_NOA_REQ = 40 +GL2C_PERF_SEL_SHARED_REQ = 41 +GL2C_PERF_SEL_HIT = 42 +GL2C_PERF_SEL_MISS = 43 +GL2C_PERF_SEL_FULL_HIT = 44 +GL2C_PERF_SEL_PARTIAL_32B_HIT = 45 +GL2C_PERF_SEL_PARTIAL_64B_HIT = 46 +GL2C_PERF_SEL_PARTIAL_96B_HIT = 47 +GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 48 +GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 49 +GL2C_PERF_SEL_UNCACHED_WRITE = 50 +GL2C_PERF_SEL_WRITEBACK = 51 +GL2C_PERF_SEL_NORMAL_WRITEBACK = 52 +GL2C_PERF_SEL_EVICT = 53 +GL2C_PERF_SEL_NORMAL_EVICT = 54 +GL2C_PERF_SEL_PROBE_EVICT = 55 +GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 56 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 57 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 58 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 59 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 60 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 61 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 62 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 63 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 64 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 65 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 66 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 67 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 68 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 69 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 70 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 71 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 72 +GL2C_PERF_SEL_READ_32_REQ = 73 +GL2C_PERF_SEL_READ_64_REQ = 74 +GL2C_PERF_SEL_READ_128_REQ = 75 +GL2C_PERF_SEL_WRITE_32_REQ = 76 +GL2C_PERF_SEL_WRITE_64_REQ = 77 +GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 78 +GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 79 +GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 80 +GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 81 +GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 82 +GL2C_PERF_SEL_MC_WRREQ = 83 +GL2C_PERF_SEL_EA_WRREQ_SNOOP = 84 +GL2C_PERF_SEL_EA_WRREQ_64B = 85 +GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 86 +GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 87 +GL2C_PERF_SEL_MC_WRREQ_STALL = 88 +GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 89 +GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 90 +GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 91 +GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 92 +GL2C_PERF_SEL_MC_WRREQ_LEVEL = 93 +GL2C_PERF_SEL_EA_ATOMIC = 94 +GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 95 +GL2C_PERF_SEL_MC_RDREQ = 96 +GL2C_PERF_SEL_EA_RDREQ_SNOOP = 97 +GL2C_PERF_SEL_EA_RDREQ_SPLIT = 98 +GL2C_PERF_SEL_EA_RDREQ_32B = 99 +GL2C_PERF_SEL_EA_RDREQ_64B = 100 +GL2C_PERF_SEL_EA_RDREQ_96B = 101 +GL2C_PERF_SEL_EA_RDREQ_128B = 102 +GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 103 +GL2C_PERF_SEL_EA_RD_MDC_32B = 104 +GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 105 +GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 106 +GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 107 +GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 108 +GL2C_PERF_SEL_MC_RDREQ_LEVEL = 109 +GL2C_PERF_SEL_EA_RDREQ_DRAM = 110 +GL2C_PERF_SEL_EA_WRREQ_DRAM = 111 +GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 112 +GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 113 +GL2C_PERF_SEL_ONION_READ = 114 +GL2C_PERF_SEL_ONION_WRITE = 115 +GL2C_PERF_SEL_IO_READ = 116 +GL2C_PERF_SEL_IO_WRITE = 117 +GL2C_PERF_SEL_GARLIC_READ = 118 +GL2C_PERF_SEL_GARLIC_WRITE = 119 +GL2C_PERF_SEL_EA_OUTSTANDING = 120 +GL2C_PERF_SEL_LATENCY_FIFO_FULL = 121 +GL2C_PERF_SEL_SRC_FIFO_FULL = 122 +GL2C_PERF_SEL_TAG_STALL = 123 +GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 124 +GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 125 +GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 126 +GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 127 +GL2C_PERF_SEL_TAG_PROBE_STALL = 128 +GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 129 +GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 130 +GL2C_PERF_SEL_TAG_READ_DST_STALL = 131 +GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 132 +GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 133 +GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 134 +GL2C_PERF_SEL_BUBBLE = 135 +GL2C_PERF_SEL_IB_REQ = 136 +GL2C_PERF_SEL_IB_STALL = 137 +GL2C_PERF_SEL_IB_TAG_STALL = 138 +GL2C_PERF_SEL_IB_CM_STALL = 139 +GL2C_PERF_SEL_RETURN_ACK = 140 +GL2C_PERF_SEL_RETURN_DATA = 141 +GL2C_PERF_SEL_EA_RDRET_NACK = 142 +GL2C_PERF_SEL_EA_WRRET_NACK = 143 +GL2C_PERF_SEL_GL2A_LEVEL = 144 +GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 145 +GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 146 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 147 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 148 +GL2C_PERF_SEL_GCR_INV = 149 +GL2C_PERF_SEL_GCR_WB = 150 +GL2C_PERF_SEL_GCR_DISCARD = 151 +GL2C_PERF_SEL_GCR_RANGE = 152 +GL2C_PERF_SEL_GCR_ALL = 153 +GL2C_PERF_SEL_GCR_VOL = 154 +GL2C_PERF_SEL_GCR_UNSHARED = 155 +GL2C_PERF_SEL_GCR_MDC_INV = 156 +GL2C_PERF_SEL_GCR_GL2_INV_ALL = 157 +GL2C_PERF_SEL_GCR_GL2_WB_ALL = 158 +GL2C_PERF_SEL_GCR_MDC_INV_ALL = 159 +GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 160 +GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 161 +GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 162 +GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 163 +GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 164 +GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 165 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 166 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 167 +GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 168 +GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 169 +GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 170 +GL2C_PERF_SEL_GCR_INVL2_VOL_START = 171 +GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 172 +GL2C_PERF_SEL_GCR_WBL2_VOL_START = 173 +GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 174 +GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 175 +GL2C_PERF_SEL_GCR_WBINVL2_START = 176 +GL2C_PERF_SEL_MDC_INV_METADATA = 177 +GL2C_PERF_SEL_MDC_REQ = 178 +GL2C_PERF_SEL_MDC_LEVEL = 179 +GL2C_PERF_SEL_MDC_TAG_HIT = 180 +GL2C_PERF_SEL_MDC_SECTOR_HIT = 181 +GL2C_PERF_SEL_MDC_SECTOR_MISS = 182 +GL2C_PERF_SEL_MDC_TAG_STALL = 183 +GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 184 +GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 185 +GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 186 +GL2C_PERF_SEL_CM_CHANNEL0_REQ = 187 +GL2C_PERF_SEL_CM_CHANNEL1_REQ = 188 +GL2C_PERF_SEL_CM_CHANNEL2_REQ = 189 +GL2C_PERF_SEL_CM_CHANNEL3_REQ = 190 +GL2C_PERF_SEL_CM_CHANNEL4_REQ = 191 +GL2C_PERF_SEL_CM_CHANNEL5_REQ = 192 +GL2C_PERF_SEL_CM_CHANNEL6_REQ = 193 +GL2C_PERF_SEL_CM_CHANNEL7_REQ = 194 +GL2C_PERF_SEL_CM_CHANNEL8_REQ = 195 +GL2C_PERF_SEL_CM_CHANNEL9_REQ = 196 +GL2C_PERF_SEL_CM_CHANNEL10_REQ = 197 +GL2C_PERF_SEL_CM_CHANNEL11_REQ = 198 +GL2C_PERF_SEL_CM_CHANNEL12_REQ = 199 +GL2C_PERF_SEL_CM_CHANNEL13_REQ = 200 +GL2C_PERF_SEL_CM_CHANNEL14_REQ = 201 +GL2C_PERF_SEL_CM_CHANNEL15_REQ = 202 +GL2C_PERF_SEL_CM_CHANNEL16_REQ = 203 +GL2C_PERF_SEL_CM_CHANNEL17_REQ = 204 +GL2C_PERF_SEL_CM_CHANNEL18_REQ = 205 +GL2C_PERF_SEL_CM_CHANNEL19_REQ = 206 +GL2C_PERF_SEL_CM_CHANNEL20_REQ = 207 +GL2C_PERF_SEL_CM_CHANNEL21_REQ = 208 +GL2C_PERF_SEL_CM_CHANNEL22_REQ = 209 +GL2C_PERF_SEL_CM_CHANNEL23_REQ = 210 +GL2C_PERF_SEL_CM_CHANNEL24_REQ = 211 +GL2C_PERF_SEL_CM_CHANNEL25_REQ = 212 +GL2C_PERF_SEL_CM_CHANNEL26_REQ = 213 +GL2C_PERF_SEL_CM_CHANNEL27_REQ = 214 +GL2C_PERF_SEL_CM_CHANNEL28_REQ = 215 +GL2C_PERF_SEL_CM_CHANNEL29_REQ = 216 +GL2C_PERF_SEL_CM_CHANNEL30_REQ = 217 +GL2C_PERF_SEL_CM_CHANNEL31_REQ = 218 +GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 219 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 220 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 221 +GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 222 +GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 223 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 224 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 225 +GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 226 +GL2C_PERF_SEL_CM_COMP_READ_REQ = 227 +GL2C_PERF_SEL_CM_READ_BACK_REQ = 228 +GL2C_PERF_SEL_CM_METADATA_WR_REQ = 229 +GL2C_PERF_SEL_CM_WR_ACK_REQ = 230 +GL2C_PERF_SEL_CM_NO_ACK_REQ = 231 +GL2C_PERF_SEL_CM_NOOP_REQ = 232 +GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 233 +GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 234 +GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 235 +GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 236 +GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 237 +GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 238 +GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 239 +GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 240 +GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 241 +GL2C_PERF_SEL_CM_RVF_FULL = 242 +GL2C_PERF_SEL_CM_SDR_FULL = 243 +GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 244 +GL2C_PERF_SEL_CM_DCC_STALL = 245 +GL2C_PERF_SEL_CM_DCC_IN_XFC = 246 +GL2C_PERF_SEL_CM_DCC_OUT_XFC = 247 +GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 248 +GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 249 +GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 250 +GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 251 +GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 252 +GL2C_PERF_SEL_CM_DCC_OUT_CONST = 253 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 254 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 255 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 256 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 257 +GL2C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_PERF_SEL' +GRBM_PERF_SEL__enumvalues = { + 0: 'GRBM_PERF_SEL_COUNT', + 1: 'GRBM_PERF_SEL_USER_DEFINED', + 2: 'GRBM_PERF_SEL_GUI_ACTIVE', + 3: 'GRBM_PERF_SEL_CP_BUSY', + 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', + 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', + 6: 'GRBM_PERF_SEL_CB_BUSY', + 7: 'GRBM_PERF_SEL_DB_BUSY', + 8: 'GRBM_PERF_SEL_PA_BUSY', + 9: 'GRBM_PERF_SEL_SC_BUSY', + 11: 'GRBM_PERF_SEL_SPI_BUSY', + 12: 'GRBM_PERF_SEL_SX_BUSY', + 13: 'GRBM_PERF_SEL_TA_BUSY', + 14: 'GRBM_PERF_SEL_CB_CLEAN', + 15: 'GRBM_PERF_SEL_DB_CLEAN', + 25: 'GRBM_PERF_SEL_GDS_BUSY', + 26: 'GRBM_PERF_SEL_BCI_BUSY', + 27: 'GRBM_PERF_SEL_RLC_BUSY', + 28: 'GRBM_PERF_SEL_TCP_BUSY', + 29: 'GRBM_PERF_SEL_CPG_BUSY', + 30: 'GRBM_PERF_SEL_CPC_BUSY', + 31: 'GRBM_PERF_SEL_CPF_BUSY', + 32: 'GRBM_PERF_SEL_GE_BUSY', + 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 34: 'GRBM_PERF_SEL_UTCL2_BUSY', + 35: 'GRBM_PERF_SEL_EA_BUSY', + 36: 'GRBM_PERF_SEL_RMI_BUSY', + 37: 'GRBM_PERF_SEL_CPAXI_BUSY', + 39: 'GRBM_PERF_SEL_UTCL1_BUSY', + 40: 'GRBM_PERF_SEL_GL2CC_BUSY', + 41: 'GRBM_PERF_SEL_SDMA_BUSY', + 42: 'GRBM_PERF_SEL_CH_BUSY', + 43: 'GRBM_PERF_SEL_PH_BUSY', + 44: 'GRBM_PERF_SEL_PMM_BUSY', + 45: 'GRBM_PERF_SEL_GUS_BUSY', + 46: 'GRBM_PERF_SEL_GL1CC_BUSY', + 47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 48: 'GRBM_PERF_SEL_GL1H_BUSY', + 49: 'GRBM_PERF_SEL_PC_BUSY', +} +GRBM_PERF_SEL_COUNT = 0 +GRBM_PERF_SEL_USER_DEFINED = 1 +GRBM_PERF_SEL_GUI_ACTIVE = 2 +GRBM_PERF_SEL_CP_BUSY = 3 +GRBM_PERF_SEL_CP_COHER_BUSY = 4 +GRBM_PERF_SEL_CP_DMA_BUSY = 5 +GRBM_PERF_SEL_CB_BUSY = 6 +GRBM_PERF_SEL_DB_BUSY = 7 +GRBM_PERF_SEL_PA_BUSY = 8 +GRBM_PERF_SEL_SC_BUSY = 9 +GRBM_PERF_SEL_SPI_BUSY = 11 +GRBM_PERF_SEL_SX_BUSY = 12 +GRBM_PERF_SEL_TA_BUSY = 13 +GRBM_PERF_SEL_CB_CLEAN = 14 +GRBM_PERF_SEL_DB_CLEAN = 15 +GRBM_PERF_SEL_GDS_BUSY = 25 +GRBM_PERF_SEL_BCI_BUSY = 26 +GRBM_PERF_SEL_RLC_BUSY = 27 +GRBM_PERF_SEL_TCP_BUSY = 28 +GRBM_PERF_SEL_CPG_BUSY = 29 +GRBM_PERF_SEL_CPC_BUSY = 30 +GRBM_PERF_SEL_CPF_BUSY = 31 +GRBM_PERF_SEL_GE_BUSY = 32 +GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 +GRBM_PERF_SEL_UTCL2_BUSY = 34 +GRBM_PERF_SEL_EA_BUSY = 35 +GRBM_PERF_SEL_RMI_BUSY = 36 +GRBM_PERF_SEL_CPAXI_BUSY = 37 +GRBM_PERF_SEL_UTCL1_BUSY = 39 +GRBM_PERF_SEL_GL2CC_BUSY = 40 +GRBM_PERF_SEL_SDMA_BUSY = 41 +GRBM_PERF_SEL_CH_BUSY = 42 +GRBM_PERF_SEL_PH_BUSY = 43 +GRBM_PERF_SEL_PMM_BUSY = 44 +GRBM_PERF_SEL_GUS_BUSY = 45 +GRBM_PERF_SEL_GL1CC_BUSY = 46 +GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47 +GRBM_PERF_SEL_GL1H_BUSY = 48 +GRBM_PERF_SEL_PC_BUSY = 49 +GRBM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE0_PERF_SEL' +GRBM_SE0_PERF_SEL__enumvalues = { + 0: 'GRBM_SE0_PERF_SEL_COUNT', + 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE0_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE0_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE0_PERF_SEL_PC_BUSY', +} +GRBM_SE0_PERF_SEL_COUNT = 0 +GRBM_SE0_PERF_SEL_USER_DEFINED = 1 +GRBM_SE0_PERF_SEL_CB_BUSY = 2 +GRBM_SE0_PERF_SEL_DB_BUSY = 3 +GRBM_SE0_PERF_SEL_SC_BUSY = 4 +GRBM_SE0_PERF_SEL_SPI_BUSY = 6 +GRBM_SE0_PERF_SEL_SX_BUSY = 7 +GRBM_SE0_PERF_SEL_TA_BUSY = 8 +GRBM_SE0_PERF_SEL_CB_CLEAN = 9 +GRBM_SE0_PERF_SEL_DB_CLEAN = 10 +GRBM_SE0_PERF_SEL_PA_BUSY = 12 +GRBM_SE0_PERF_SEL_BCI_BUSY = 14 +GRBM_SE0_PERF_SEL_RMI_BUSY = 15 +GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE0_PERF_SEL_TCP_BUSY = 17 +GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE0_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE0_PERF_SEL_PC_BUSY = 20 +GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE1_PERF_SEL' +GRBM_SE1_PERF_SEL__enumvalues = { + 0: 'GRBM_SE1_PERF_SEL_COUNT', + 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE1_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE1_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE1_PERF_SEL_PC_BUSY', +} +GRBM_SE1_PERF_SEL_COUNT = 0 +GRBM_SE1_PERF_SEL_USER_DEFINED = 1 +GRBM_SE1_PERF_SEL_CB_BUSY = 2 +GRBM_SE1_PERF_SEL_DB_BUSY = 3 +GRBM_SE1_PERF_SEL_SC_BUSY = 4 +GRBM_SE1_PERF_SEL_SPI_BUSY = 6 +GRBM_SE1_PERF_SEL_SX_BUSY = 7 +GRBM_SE1_PERF_SEL_TA_BUSY = 8 +GRBM_SE1_PERF_SEL_CB_CLEAN = 9 +GRBM_SE1_PERF_SEL_DB_CLEAN = 10 +GRBM_SE1_PERF_SEL_PA_BUSY = 12 +GRBM_SE1_PERF_SEL_BCI_BUSY = 14 +GRBM_SE1_PERF_SEL_RMI_BUSY = 15 +GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE1_PERF_SEL_TCP_BUSY = 17 +GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE1_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE1_PERF_SEL_PC_BUSY = 20 +GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE2_PERF_SEL' +GRBM_SE2_PERF_SEL__enumvalues = { + 0: 'GRBM_SE2_PERF_SEL_COUNT', + 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE2_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE2_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE2_PERF_SEL_PC_BUSY', +} +GRBM_SE2_PERF_SEL_COUNT = 0 +GRBM_SE2_PERF_SEL_USER_DEFINED = 1 +GRBM_SE2_PERF_SEL_CB_BUSY = 2 +GRBM_SE2_PERF_SEL_DB_BUSY = 3 +GRBM_SE2_PERF_SEL_SC_BUSY = 4 +GRBM_SE2_PERF_SEL_SPI_BUSY = 6 +GRBM_SE2_PERF_SEL_SX_BUSY = 7 +GRBM_SE2_PERF_SEL_TA_BUSY = 8 +GRBM_SE2_PERF_SEL_CB_CLEAN = 9 +GRBM_SE2_PERF_SEL_DB_CLEAN = 10 +GRBM_SE2_PERF_SEL_PA_BUSY = 12 +GRBM_SE2_PERF_SEL_BCI_BUSY = 14 +GRBM_SE2_PERF_SEL_RMI_BUSY = 15 +GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE2_PERF_SEL_TCP_BUSY = 17 +GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE2_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE2_PERF_SEL_PC_BUSY = 20 +GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE3_PERF_SEL' +GRBM_SE3_PERF_SEL__enumvalues = { + 0: 'GRBM_SE3_PERF_SEL_COUNT', + 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE3_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE3_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE3_PERF_SEL_PC_BUSY', +} +GRBM_SE3_PERF_SEL_COUNT = 0 +GRBM_SE3_PERF_SEL_USER_DEFINED = 1 +GRBM_SE3_PERF_SEL_CB_BUSY = 2 +GRBM_SE3_PERF_SEL_DB_BUSY = 3 +GRBM_SE3_PERF_SEL_SC_BUSY = 4 +GRBM_SE3_PERF_SEL_SPI_BUSY = 6 +GRBM_SE3_PERF_SEL_SX_BUSY = 7 +GRBM_SE3_PERF_SEL_TA_BUSY = 8 +GRBM_SE3_PERF_SEL_CB_CLEAN = 9 +GRBM_SE3_PERF_SEL_DB_CLEAN = 10 +GRBM_SE3_PERF_SEL_PA_BUSY = 12 +GRBM_SE3_PERF_SEL_BCI_BUSY = 14 +GRBM_SE3_PERF_SEL_RMI_BUSY = 15 +GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE3_PERF_SEL_TCP_BUSY = 17 +GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE3_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE3_PERF_SEL_PC_BUSY = 20 +GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE4_PERF_SEL' +GRBM_SE4_PERF_SEL__enumvalues = { + 0: 'GRBM_SE4_PERF_SEL_COUNT', + 1: 'GRBM_SE4_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE4_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE4_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE4_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE4_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE4_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE4_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE4_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE4_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE4_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE4_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE4_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE4_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE4_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE4_PERF_SEL_PC_BUSY', +} +GRBM_SE4_PERF_SEL_COUNT = 0 +GRBM_SE4_PERF_SEL_USER_DEFINED = 1 +GRBM_SE4_PERF_SEL_CB_BUSY = 2 +GRBM_SE4_PERF_SEL_DB_BUSY = 3 +GRBM_SE4_PERF_SEL_SC_BUSY = 4 +GRBM_SE4_PERF_SEL_SPI_BUSY = 6 +GRBM_SE4_PERF_SEL_SX_BUSY = 7 +GRBM_SE4_PERF_SEL_TA_BUSY = 8 +GRBM_SE4_PERF_SEL_CB_CLEAN = 9 +GRBM_SE4_PERF_SEL_DB_CLEAN = 10 +GRBM_SE4_PERF_SEL_PA_BUSY = 12 +GRBM_SE4_PERF_SEL_BCI_BUSY = 14 +GRBM_SE4_PERF_SEL_RMI_BUSY = 15 +GRBM_SE4_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE4_PERF_SEL_TCP_BUSY = 17 +GRBM_SE4_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE4_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE4_PERF_SEL_PC_BUSY = 20 +GRBM_SE4_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE5_PERF_SEL' +GRBM_SE5_PERF_SEL__enumvalues = { + 0: 'GRBM_SE5_PERF_SEL_COUNT', + 1: 'GRBM_SE5_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE5_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE5_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE5_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE5_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE5_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE5_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE5_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE5_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE5_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE5_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE5_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE5_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE5_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE5_PERF_SEL_PC_BUSY', +} +GRBM_SE5_PERF_SEL_COUNT = 0 +GRBM_SE5_PERF_SEL_USER_DEFINED = 1 +GRBM_SE5_PERF_SEL_CB_BUSY = 2 +GRBM_SE5_PERF_SEL_DB_BUSY = 3 +GRBM_SE5_PERF_SEL_SC_BUSY = 4 +GRBM_SE5_PERF_SEL_SPI_BUSY = 6 +GRBM_SE5_PERF_SEL_SX_BUSY = 7 +GRBM_SE5_PERF_SEL_TA_BUSY = 8 +GRBM_SE5_PERF_SEL_CB_CLEAN = 9 +GRBM_SE5_PERF_SEL_DB_CLEAN = 10 +GRBM_SE5_PERF_SEL_PA_BUSY = 12 +GRBM_SE5_PERF_SEL_BCI_BUSY = 14 +GRBM_SE5_PERF_SEL_RMI_BUSY = 15 +GRBM_SE5_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE5_PERF_SEL_TCP_BUSY = 17 +GRBM_SE5_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE5_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE5_PERF_SEL_PC_BUSY = 20 +GRBM_SE5_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE6_PERF_SEL' +GRBM_SE6_PERF_SEL__enumvalues = { + 0: 'GRBM_SE6_PERF_SEL_COUNT', + 1: 'GRBM_SE6_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE6_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE6_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE6_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE6_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE6_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE6_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE6_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE6_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE6_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE6_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE6_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE6_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE6_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE6_PERF_SEL_PC_BUSY', +} +GRBM_SE6_PERF_SEL_COUNT = 0 +GRBM_SE6_PERF_SEL_USER_DEFINED = 1 +GRBM_SE6_PERF_SEL_CB_BUSY = 2 +GRBM_SE6_PERF_SEL_DB_BUSY = 3 +GRBM_SE6_PERF_SEL_SC_BUSY = 4 +GRBM_SE6_PERF_SEL_SPI_BUSY = 6 +GRBM_SE6_PERF_SEL_SX_BUSY = 7 +GRBM_SE6_PERF_SEL_TA_BUSY = 8 +GRBM_SE6_PERF_SEL_CB_CLEAN = 9 +GRBM_SE6_PERF_SEL_DB_CLEAN = 10 +GRBM_SE6_PERF_SEL_PA_BUSY = 12 +GRBM_SE6_PERF_SEL_BCI_BUSY = 14 +GRBM_SE6_PERF_SEL_RMI_BUSY = 15 +GRBM_SE6_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE6_PERF_SEL_TCP_BUSY = 17 +GRBM_SE6_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE6_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE6_PERF_SEL_PC_BUSY = 20 +GRBM_SE6_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE7_PERF_SEL' +GRBM_SE7_PERF_SEL__enumvalues = { + 0: 'GRBM_SE7_PERF_SEL_COUNT', + 1: 'GRBM_SE7_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE7_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE7_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE7_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE7_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE7_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE7_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE7_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE7_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE7_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE7_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE7_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE7_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE7_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE7_PERF_SEL_PC_BUSY', +} +GRBM_SE7_PERF_SEL_COUNT = 0 +GRBM_SE7_PERF_SEL_USER_DEFINED = 1 +GRBM_SE7_PERF_SEL_CB_BUSY = 2 +GRBM_SE7_PERF_SEL_DB_BUSY = 3 +GRBM_SE7_PERF_SEL_SC_BUSY = 4 +GRBM_SE7_PERF_SEL_SPI_BUSY = 6 +GRBM_SE7_PERF_SEL_SX_BUSY = 7 +GRBM_SE7_PERF_SEL_TA_BUSY = 8 +GRBM_SE7_PERF_SEL_CB_CLEAN = 9 +GRBM_SE7_PERF_SEL_DB_CLEAN = 10 +GRBM_SE7_PERF_SEL_PA_BUSY = 12 +GRBM_SE7_PERF_SEL_BCI_BUSY = 14 +GRBM_SE7_PERF_SEL_RMI_BUSY = 15 +GRBM_SE7_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE7_PERF_SEL_TCP_BUSY = 17 +GRBM_SE7_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE7_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE7_PERF_SEL_PC_BUSY = 20 +GRBM_SE7_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_COMPAT_LEVEL' +PIPE_COMPAT_LEVEL__enumvalues = { + 0: 'GEN_ZERO', + 1: 'GEN_ONE', + 2: 'GEN_TWO', + 3: 'GEN_RESERVED', +} +GEN_ZERO = 0 +GEN_ONE = 1 +GEN_TWO = 2 +GEN_RESERVED = 3 +PIPE_COMPAT_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_LATENCY_STATS_SEL' +CPC_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', +} +CPC_LATENCY_STATS_SEL_XACK_MAX = 0 +CPC_LATENCY_STATS_SEL_XACK_MIN = 1 +CPC_LATENCY_STATS_SEL_XACK_LAST = 2 +CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 +CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 +CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 +CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_PERFCOUNT_SEL' +CPC_PERFCOUNT_SEL__enumvalues = { + 0: 'CPC_PERF_SEL_ALWAYS_COUNT', + 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', + 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', + 27: 'CPC_PERF_SEL_CPC_STAT_STALL', + 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', + 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', + 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', + 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', + 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', + 45: 'CPC_PERF_SEL_MES_THREAD0', + 46: 'CPC_PERF_SEL_MES_THREAD1', +} +CPC_PERF_SEL_ALWAYS_COUNT = 0 +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 +CPC_PERF_SEL_CPC_STAT_BUSY = 25 +CPC_PERF_SEL_CPC_STAT_IDLE = 26 +CPC_PERF_SEL_CPC_STAT_STALL = 27 +CPC_PERF_SEL_CPC_TCIU_BUSY = 28 +CPC_PERF_SEL_CPC_TCIU_IDLE = 29 +CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 +CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 +CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 +CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 +CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 +CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 +CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 +CPC_PERF_SEL_CPC_GCRIU_STALL = 37 +CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 +CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 +CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 +CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 +CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 +CPC_PERF_SEL_MES_THREAD0 = 45 +CPC_PERF_SEL_MES_THREAD1 = 46 +CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_LATENCY_STATS_SEL' +CPF_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', + 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', + 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', + 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', +} +CPF_LATENCY_STATS_SEL_XACK_MAX = 0 +CPF_LATENCY_STATS_SEL_XACK_MIN = 1 +CPF_LATENCY_STATS_SEL_XACK_LAST = 2 +CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPF_LATENCY_STATS_SEL_READ_MAX = 6 +CPF_LATENCY_STATS_SEL_READ_MIN = 7 +CPF_LATENCY_STATS_SEL_READ_LAST = 8 +CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 +CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 +CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 +CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' +CPF_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPF_PERFWINDOW_SEL_CSF', + 1: 'CPF_PERFWINDOW_SEL_HQD1', + 2: 'CPF_PERFWINDOW_SEL_HQD2', + 3: 'CPF_PERFWINDOW_SEL_RDMA', + 4: 'CPF_PERFWINDOW_SEL_RWPP', +} +CPF_PERFWINDOW_SEL_CSF = 0 +CPF_PERFWINDOW_SEL_HQD1 = 1 +CPF_PERFWINDOW_SEL_HQD2 = 2 +CPF_PERFWINDOW_SEL_RDMA = 3 +CPF_PERFWINDOW_SEL_RWPP = 4 +CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNT_SEL' +CPF_PERFCOUNT_SEL__enumvalues = { + 0: 'CPF_PERF_SEL_ALWAYS_COUNT', + 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', + 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', + 26: 'CPF_PERF_SEL_CPF_STAT_STALL', + 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', + 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', + 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', + 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', + 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', + 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', + 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', +} +CPF_PERF_SEL_ALWAYS_COUNT = 0 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7 +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 +CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 +CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15 +CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 +CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 +CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 +CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 +CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 +CPF_PERF_SEL_CPF_STAT_BUSY = 24 +CPF_PERF_SEL_CPF_STAT_IDLE = 25 +CPF_PERF_SEL_CPF_STAT_STALL = 26 +CPF_PERF_SEL_CPF_TCIU_BUSY = 27 +CPF_PERF_SEL_CPF_TCIU_IDLE = 28 +CPF_PERF_SEL_CPF_TCIU_STALL = 29 +CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 +CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 +CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 +CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 +CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 +CPF_PERF_SEL_CPF_GCRIU_STALL = 35 +CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 +CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 +CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41 +CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42 +CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43 +CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP' +CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = { + 0: 'CPF_SCRATCH_REG_ATOMIC_ADD', + 1: 'CPF_SCRATCH_REG_ATOMIC_SUB', + 2: 'CPF_SCRATCH_REG_ATOMIC_OR', + 3: 'CPF_SCRATCH_REG_ATOMIC_AND', + 4: 'CPF_SCRATCH_REG_ATOMIC_NOT', + 5: 'CPF_SCRATCH_REG_ATOMIC_MIN', + 6: 'CPF_SCRATCH_REG_ATOMIC_MAX', + 7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', +} +CPF_SCRATCH_REG_ATOMIC_ADD = 0 +CPF_SCRATCH_REG_ATOMIC_SUB = 1 +CPF_SCRATCH_REG_ATOMIC_OR = 2 +CPF_SCRATCH_REG_ATOMIC_AND = 3 +CPF_SCRATCH_REG_ATOMIC_NOT = 4 +CPF_SCRATCH_REG_ATOMIC_MIN = 5 +CPF_SCRATCH_REG_ATOMIC_MAX = 6 +CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7 +CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_LATENCY_STATS_SEL' +CPG_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', + 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', + 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', + 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', +} +CPG_LATENCY_STATS_SEL_XACK_MAX = 0 +CPG_LATENCY_STATS_SEL_XACK_MIN = 1 +CPG_LATENCY_STATS_SEL_XACK_LAST = 2 +CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 +CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 +CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 +CPG_LATENCY_STATS_SEL_READ_MAX = 9 +CPG_LATENCY_STATS_SEL_READ_MIN = 10 +CPG_LATENCY_STATS_SEL_READ_LAST = 11 +CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 +CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 +CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 +CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 +CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 +CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 +CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' +CPG_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPG_PERFWINDOW_SEL_PFP', + 1: 'CPG_PERFWINDOW_SEL_ME', + 2: 'CPG_PERFWINDOW_SEL_CE', + 3: 'CPG_PERFWINDOW_SEL_MES', + 4: 'CPG_PERFWINDOW_SEL_MEC1', + 5: 'CPG_PERFWINDOW_SEL_MEC2', + 6: 'CPG_PERFWINDOW_SEL_DFY', + 7: 'CPG_PERFWINDOW_SEL_DMA', + 8: 'CPG_PERFWINDOW_SEL_SHADOW', + 9: 'CPG_PERFWINDOW_SEL_RB', + 10: 'CPG_PERFWINDOW_SEL_CEDMA', + 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', + 13: 'CPG_PERFWINDOW_SEL_PQ1', + 14: 'CPG_PERFWINDOW_SEL_PQ2', + 15: 'CPG_PERFWINDOW_SEL_PQ3', + 16: 'CPG_PERFWINDOW_SEL_MEMWR', + 17: 'CPG_PERFWINDOW_SEL_MEMRD', + 18: 'CPG_PERFWINDOW_SEL_VGT0', + 19: 'CPG_PERFWINDOW_SEL_VGT1', + 20: 'CPG_PERFWINDOW_SEL_APPEND', + 21: 'CPG_PERFWINDOW_SEL_QURD', + 22: 'CPG_PERFWINDOW_SEL_DDID', + 23: 'CPG_PERFWINDOW_SEL_SR', + 24: 'CPG_PERFWINDOW_SEL_QU_EOP', + 25: 'CPG_PERFWINDOW_SEL_QU_STRM', + 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', + 27: 'CPG_PERFWINDOW_SEL_RESERVED1', + 28: 'CPG_PERFWINDOW_SEL_CPC_IC', + 29: 'CPG_PERFWINDOW_SEL_RESERVED2', + 30: 'CPG_PERFWINDOW_SEL_CPG_IC', +} +CPG_PERFWINDOW_SEL_PFP = 0 +CPG_PERFWINDOW_SEL_ME = 1 +CPG_PERFWINDOW_SEL_CE = 2 +CPG_PERFWINDOW_SEL_MES = 3 +CPG_PERFWINDOW_SEL_MEC1 = 4 +CPG_PERFWINDOW_SEL_MEC2 = 5 +CPG_PERFWINDOW_SEL_DFY = 6 +CPG_PERFWINDOW_SEL_DMA = 7 +CPG_PERFWINDOW_SEL_SHADOW = 8 +CPG_PERFWINDOW_SEL_RB = 9 +CPG_PERFWINDOW_SEL_CEDMA = 10 +CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 +CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 +CPG_PERFWINDOW_SEL_PQ1 = 13 +CPG_PERFWINDOW_SEL_PQ2 = 14 +CPG_PERFWINDOW_SEL_PQ3 = 15 +CPG_PERFWINDOW_SEL_MEMWR = 16 +CPG_PERFWINDOW_SEL_MEMRD = 17 +CPG_PERFWINDOW_SEL_VGT0 = 18 +CPG_PERFWINDOW_SEL_VGT1 = 19 +CPG_PERFWINDOW_SEL_APPEND = 20 +CPG_PERFWINDOW_SEL_QURD = 21 +CPG_PERFWINDOW_SEL_DDID = 22 +CPG_PERFWINDOW_SEL_SR = 23 +CPG_PERFWINDOW_SEL_QU_EOP = 24 +CPG_PERFWINDOW_SEL_QU_STRM = 25 +CPG_PERFWINDOW_SEL_QU_PIPE = 26 +CPG_PERFWINDOW_SEL_RESERVED1 = 27 +CPG_PERFWINDOW_SEL_CPC_IC = 28 +CPG_PERFWINDOW_SEL_RESERVED2 = 29 +CPG_PERFWINDOW_SEL_CPG_IC = 30 +CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNT_SEL' +CPG_PERFCOUNT_SEL__enumvalues = { + 0: 'CPG_PERF_SEL_ALWAYS_COUNT', + 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', + 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', + 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', + 53: 'CPG_PERF_SEL_CPG_STAT_STALL', + 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', + 56: 'CPG_PERF_SEL_CPG_TCIU_STALL', + 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', + 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', + 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', + 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', + 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', + 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 78: 'CPG_PERF_SEL_DMA_BUSY', + 79: 'CPG_PERF_SEL_DMA_STARVED', + 80: 'CPG_PERF_SEL_DMA_STALLED', + 81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 82: 'CPG_PERF_SEL_PFP_PWS_STALLED0', + 83: 'CPG_PERF_SEL_ME_PWS_STALLED0', + 84: 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 85: 'CPG_PERF_SEL_ME_PWS_STALLED1', +} +CPG_PERF_SEL_ALWAYS_COUNT = 0 +CPG_PERF_SEL_RBIU_FIFO_FULL = 1 +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 +CPG_PERF_SEL_ME_PARSER_BUSY = 5 +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 +CPG_PERF_SEL_REGISTER_CLK_VALID = 33 +CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 +CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 +CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 +CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 +CPG_PERF_SEL_CPG_STAT_BUSY = 51 +CPG_PERF_SEL_CPG_STAT_IDLE = 52 +CPG_PERF_SEL_CPG_STAT_STALL = 53 +CPG_PERF_SEL_CPG_TCIU_BUSY = 54 +CPG_PERF_SEL_CPG_TCIU_IDLE = 55 +CPG_PERF_SEL_CPG_TCIU_STALL = 56 +CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 +CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 +CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 +CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 +CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 +CPG_PERF_SEL_CPG_GCRIU_STALL = 62 +CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 +CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 +CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 +CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 +CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 +CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 +CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 +CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 +CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 +CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 +CPG_PERF_SEL_DMA_BUSY = 78 +CPG_PERF_SEL_DMA_STARVED = 79 +CPG_PERF_SEL_DMA_STALLED = 80 +CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81 +CPG_PERF_SEL_PFP_PWS_STALLED0 = 82 +CPG_PERF_SEL_ME_PWS_STALLED0 = 83 +CPG_PERF_SEL_PFP_PWS_STALLED1 = 84 +CPG_PERF_SEL_ME_PWS_STALLED1 = 85 +CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' +CP_ALPHA_TAG_RAM_SEL__enumvalues = { + 0: 'CPG_TAG_RAM', + 1: 'CPC_TAG_RAM', + 2: 'CPF_TAG_RAM', + 3: 'RSV_TAG_RAM', +} +CPG_TAG_RAM = 0 +CPC_TAG_RAM = 1 +CPF_TAG_RAM = 2 +RSV_TAG_RAM = 3 +CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_MODE' +CP_DDID_CNTL_MODE__enumvalues = { + 0: 'STALL', + 1: 'OVERRUN', +} +STALL = 0 +OVERRUN = 1 +CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_SIZE' +CP_DDID_CNTL_SIZE__enumvalues = { + 0: 'SIZE_8K', + 1: 'SIZE_16K', +} +SIZE_8K = 0 +SIZE_16K = 1 +CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_VMID_SEL' +CP_DDID_CNTL_VMID_SEL__enumvalues = { + 0: 'DDID_VMID_PIPE', + 1: 'DDID_VMID_CNTL', +} +DDID_VMID_PIPE = 0 +DDID_VMID_CNTL = 1 +CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ME_ID' +CP_ME_ID__enumvalues = { + 0: 'ME_ID0', + 1: 'ME_ID1', + 2: 'ME_ID2', + 3: 'ME_ID3', +} +ME_ID0 = 0 +ME_ID1 = 1 +ME_ID2 = 2 +ME_ID3 = 3 +CP_ME_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_ENABLE_MODE' +CP_PERFMON_ENABLE_MODE__enumvalues = { + 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', + 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', +} +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 +CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_STATE' +CP_PERFMON_STATE__enumvalues = { + 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'CP_PERFMON_STATE_START_COUNTING', + 2: 'CP_PERFMON_STATE_STOP_COUNTING', + 3: 'CP_PERFMON_STATE_RESERVED_3', + 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +CP_PERFMON_STATE_DISABLE_AND_RESET = 0 +CP_PERFMON_STATE_START_COUNTING = 1 +CP_PERFMON_STATE_STOP_COUNTING = 2 +CP_PERFMON_STATE_RESERVED_3 = 3 +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +CP_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PIPE_ID' +CP_PIPE_ID__enumvalues = { + 0: 'PIPE_ID0', + 1: 'PIPE_ID1', + 2: 'PIPE_ID2', + 3: 'PIPE_ID3', +} +PIPE_ID0 = 0 +PIPE_ID1 = 1 +PIPE_ID2 = 2 +PIPE_ID3 = 3 +CP_PIPE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_RING_ID' +CP_RING_ID__enumvalues = { + 0: 'RINGID0', + 1: 'RINGID1', + 2: 'RINGID2', + 3: 'RINGID3', +} +RINGID0 = 0 +RINGID1 = 1 +RINGID2 = 2 +RINGID3 = 3 +CP_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'SPM_PERFMON_STATE' +SPM_PERFMON_STATE__enumvalues = { + 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'STRM_PERFMON_STATE_START_COUNTING', + 2: 'STRM_PERFMON_STATE_STOP_COUNTING', + 3: 'STRM_PERFMON_STATE_RESERVED_3', + 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 +STRM_PERFMON_STATE_START_COUNTING = 1 +STRM_PERFMON_STATE_STOP_COUNTING = 2 +STRM_PERFMON_STATE_RESERVED_3 = 3 +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +SPM_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'SX_BLEND_OPT' +SX_BLEND_OPT__enumvalues = { + 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', +} +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 +SX_BLEND_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_DOWNCONVERT_FORMAT' +SX_DOWNCONVERT_FORMAT__enumvalues = { + 0: 'SX_RT_EXPORT_NO_CONVERSION', + 1: 'SX_RT_EXPORT_32_R', + 2: 'SX_RT_EXPORT_32_A', + 3: 'SX_RT_EXPORT_10_11_11', + 4: 'SX_RT_EXPORT_2_10_10_10', + 5: 'SX_RT_EXPORT_8_8_8_8', + 6: 'SX_RT_EXPORT_5_6_5', + 7: 'SX_RT_EXPORT_1_5_5_5', + 8: 'SX_RT_EXPORT_4_4_4_4', + 9: 'SX_RT_EXPORT_16_16_GR', + 10: 'SX_RT_EXPORT_16_16_AR', + 11: 'SX_RT_EXPORT_9_9_9_E5', + 12: 'SX_RT_EXPORT_2_10_10_10_7E3', + 13: 'SX_RT_EXPORT_2_10_10_10_6E4', +} +SX_RT_EXPORT_NO_CONVERSION = 0 +SX_RT_EXPORT_32_R = 1 +SX_RT_EXPORT_32_A = 2 +SX_RT_EXPORT_10_11_11 = 3 +SX_RT_EXPORT_2_10_10_10 = 4 +SX_RT_EXPORT_8_8_8_8 = 5 +SX_RT_EXPORT_5_6_5 = 6 +SX_RT_EXPORT_1_5_5_5 = 7 +SX_RT_EXPORT_4_4_4_4 = 8 +SX_RT_EXPORT_16_16_GR = 9 +SX_RT_EXPORT_16_16_AR = 10 +SX_RT_EXPORT_9_9_9_E5 = 11 +SX_RT_EXPORT_2_10_10_10_7E3 = 12 +SX_RT_EXPORT_2_10_10_10_6E4 = 13 +SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_OPT_COMB_FCN' +SX_OPT_COMB_FCN__enumvalues = { + 0: 'OPT_COMB_NONE', + 1: 'OPT_COMB_ADD', + 2: 'OPT_COMB_SUBTRACT', + 3: 'OPT_COMB_MIN', + 4: 'OPT_COMB_MAX', + 5: 'OPT_COMB_REVSUBTRACT', + 6: 'OPT_COMB_BLEND_DISABLED', + 7: 'OPT_COMB_SAFE_ADD', +} +OPT_COMB_NONE = 0 +OPT_COMB_ADD = 1 +OPT_COMB_SUBTRACT = 2 +OPT_COMB_MIN = 3 +OPT_COMB_MAX = 4 +OPT_COMB_REVSUBTRACT = 5 +OPT_COMB_BLEND_DISABLED = 6 +OPT_COMB_SAFE_ADD = 7 +SX_OPT_COMB_FCN = ctypes.c_uint32 # enum + +# values for enumeration 'SX_PERFCOUNTER_VALS' +SX_PERFCOUNTER_VALS__enumvalues = { + 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', + 1: 'SX_PERF_SEL_PA_REQ', + 2: 'SX_PERF_SEL_PA_POS', + 3: 'SX_PERF_SEL_CLOCK', + 4: 'SX_PERF_SEL_GATE_EN1', + 5: 'SX_PERF_SEL_GATE_EN2', + 6: 'SX_PERF_SEL_GATE_EN3', + 7: 'SX_PERF_SEL_GATE_EN4', + 8: 'SX_PERF_SEL_SH_POS_STARVE', + 9: 'SX_PERF_SEL_SH_COLOR_STARVE', + 10: 'SX_PERF_SEL_SH_POS_STALL', + 11: 'SX_PERF_SEL_SH_COLOR_STALL', + 12: 'SX_PERF_SEL_DB0_PIXELS', + 13: 'SX_PERF_SEL_DB0_HALF_QUADS', + 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', + 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', + 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', + 17: 'SX_PERF_SEL_DB1_PIXELS', + 18: 'SX_PERF_SEL_DB1_HALF_QUADS', + 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', + 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', + 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', + 22: 'SX_PERF_SEL_DB2_PIXELS', + 23: 'SX_PERF_SEL_DB2_HALF_QUADS', + 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', + 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', + 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', + 27: 'SX_PERF_SEL_DB3_PIXELS', + 28: 'SX_PERF_SEL_DB3_HALF_QUADS', + 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', + 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', + 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', + 32: 'SX_PERF_SEL_COL_BUSY', + 33: 'SX_PERF_SEL_POS_BUSY', + 34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', + 38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', + 43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', + 48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', + 53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 54: 'SX_PERF_SEL_PA_REQ_LATENCY', + 55: 'SX_PERF_SEL_POS_SCBD_STALL', + 56: 'SX_PERF_SEL_CLOCK_DROP_STALL', + 57: 'SX_PERF_SEL_GATE_EN5', + 58: 'SX_PERF_SEL_GATE_EN6', + 59: 'SX_PERF_SEL_DB0_SIZE', + 60: 'SX_PERF_SEL_DB1_SIZE', + 61: 'SX_PERF_SEL_DB2_SIZE', + 62: 'SX_PERF_SEL_DB3_SIZE', + 63: 'SX_PERF_SEL_IDX_STALL_CYCLES', + 64: 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 65: 'SX_PERF_SEL_IDX_REQ', + 66: 'SX_PERF_SEL_IDX_RET', + 67: 'SX_PERF_SEL_IDX_REQ_LATENCY', + 68: 'SX_PERF_SEL_IDX_SCBD_STALL', + 69: 'SX_PERF_SEL_GATE_EN7', + 70: 'SX_PERF_SEL_GATE_EN8', + 71: 'SX_PERF_SEL_SH_IDX_STARVE', + 72: 'SX_PERF_SEL_IDX_BUSY', + 73: 'SX_PERF_SEL_PA_POS_BANK_CONF', + 74: 'SX_PERF_SEL_DB0_END_OF_WAVE', + 75: 'SX_PERF_SEL_DB0_4X2_DISCARD', + 76: 'SX_PERF_SEL_DB1_END_OF_WAVE', + 77: 'SX_PERF_SEL_DB1_4X2_DISCARD', + 78: 'SX_PERF_SEL_DB2_END_OF_WAVE', + 79: 'SX_PERF_SEL_DB2_4X2_DISCARD', + 80: 'SX_PERF_SEL_DB3_END_OF_WAVE', + 81: 'SX_PERF_SEL_DB3_4X2_DISCARD', +} +SX_PERF_SEL_PA_IDLE_CYCLES = 0 +SX_PERF_SEL_PA_REQ = 1 +SX_PERF_SEL_PA_POS = 2 +SX_PERF_SEL_CLOCK = 3 +SX_PERF_SEL_GATE_EN1 = 4 +SX_PERF_SEL_GATE_EN2 = 5 +SX_PERF_SEL_GATE_EN3 = 6 +SX_PERF_SEL_GATE_EN4 = 7 +SX_PERF_SEL_SH_POS_STARVE = 8 +SX_PERF_SEL_SH_COLOR_STARVE = 9 +SX_PERF_SEL_SH_POS_STALL = 10 +SX_PERF_SEL_SH_COLOR_STALL = 11 +SX_PERF_SEL_DB0_PIXELS = 12 +SX_PERF_SEL_DB0_HALF_QUADS = 13 +SX_PERF_SEL_DB0_PIXEL_STALL = 14 +SX_PERF_SEL_DB0_PIXEL_IDLE = 15 +SX_PERF_SEL_DB0_PRED_PIXELS = 16 +SX_PERF_SEL_DB1_PIXELS = 17 +SX_PERF_SEL_DB1_HALF_QUADS = 18 +SX_PERF_SEL_DB1_PIXEL_STALL = 19 +SX_PERF_SEL_DB1_PIXEL_IDLE = 20 +SX_PERF_SEL_DB1_PRED_PIXELS = 21 +SX_PERF_SEL_DB2_PIXELS = 22 +SX_PERF_SEL_DB2_HALF_QUADS = 23 +SX_PERF_SEL_DB2_PIXEL_STALL = 24 +SX_PERF_SEL_DB2_PIXEL_IDLE = 25 +SX_PERF_SEL_DB2_PRED_PIXELS = 26 +SX_PERF_SEL_DB3_PIXELS = 27 +SX_PERF_SEL_DB3_HALF_QUADS = 28 +SX_PERF_SEL_DB3_PIXEL_STALL = 29 +SX_PERF_SEL_DB3_PIXEL_IDLE = 30 +SX_PERF_SEL_DB3_PRED_PIXELS = 31 +SX_PERF_SEL_COL_BUSY = 32 +SX_PERF_SEL_POS_BUSY = 33 +SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34 +SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35 +SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36 +SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37 +SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38 +SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39 +SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40 +SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41 +SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42 +SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43 +SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44 +SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45 +SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46 +SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47 +SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48 +SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49 +SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50 +SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51 +SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52 +SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53 +SX_PERF_SEL_PA_REQ_LATENCY = 54 +SX_PERF_SEL_POS_SCBD_STALL = 55 +SX_PERF_SEL_CLOCK_DROP_STALL = 56 +SX_PERF_SEL_GATE_EN5 = 57 +SX_PERF_SEL_GATE_EN6 = 58 +SX_PERF_SEL_DB0_SIZE = 59 +SX_PERF_SEL_DB1_SIZE = 60 +SX_PERF_SEL_DB2_SIZE = 61 +SX_PERF_SEL_DB3_SIZE = 62 +SX_PERF_SEL_IDX_STALL_CYCLES = 63 +SX_PERF_SEL_IDX_IDLE_CYCLES = 64 +SX_PERF_SEL_IDX_REQ = 65 +SX_PERF_SEL_IDX_RET = 66 +SX_PERF_SEL_IDX_REQ_LATENCY = 67 +SX_PERF_SEL_IDX_SCBD_STALL = 68 +SX_PERF_SEL_GATE_EN7 = 69 +SX_PERF_SEL_GATE_EN8 = 70 +SX_PERF_SEL_SH_IDX_STARVE = 71 +SX_PERF_SEL_IDX_BUSY = 72 +SX_PERF_SEL_PA_POS_BANK_CONF = 73 +SX_PERF_SEL_DB0_END_OF_WAVE = 74 +SX_PERF_SEL_DB0_4X2_DISCARD = 75 +SX_PERF_SEL_DB1_END_OF_WAVE = 76 +SX_PERF_SEL_DB1_4X2_DISCARD = 77 +SX_PERF_SEL_DB2_END_OF_WAVE = 78 +SX_PERF_SEL_DB2_4X2_DISCARD = 79 +SX_PERF_SEL_DB3_END_OF_WAVE = 80 +SX_PERF_SEL_DB3_4X2_DISCARD = 81 +SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum + +# values for enumeration 'CompareFrag' +CompareFrag__enumvalues = { + 0: 'FRAG_NEVER', + 1: 'FRAG_LESS', + 2: 'FRAG_EQUAL', + 3: 'FRAG_LEQUAL', + 4: 'FRAG_GREATER', + 5: 'FRAG_NOTEQUAL', + 6: 'FRAG_GEQUAL', + 7: 'FRAG_ALWAYS', +} +FRAG_NEVER = 0 +FRAG_LESS = 1 +FRAG_EQUAL = 2 +FRAG_LEQUAL = 3 +FRAG_GREATER = 4 +FRAG_NOTEQUAL = 5 +FRAG_GEQUAL = 6 +FRAG_ALWAYS = 7 +CompareFrag = ctypes.c_uint32 # enum + +# values for enumeration 'ConservativeZExport' +ConservativeZExport__enumvalues = { + 0: 'EXPORT_ANY_Z', + 1: 'EXPORT_LESS_THAN_Z', + 2: 'EXPORT_GREATER_THAN_Z', + 3: 'EXPORT_RESERVED', +} +EXPORT_ANY_Z = 0 +EXPORT_LESS_THAN_Z = 1 +EXPORT_GREATER_THAN_Z = 2 +EXPORT_RESERVED = 3 +ConservativeZExport = ctypes.c_uint32 # enum + +# values for enumeration 'DFSMFlushEvents' +DFSMFlushEvents__enumvalues = { + 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', + 1: 'DB_FLUSH_AND_INV_DB_META', + 2: 'DB_CACHE_FLUSH', + 3: 'DB_CACHE_FLUSH_TS', + 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', + 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', + 6: 'DB_VPORT_CHANGED_EVENT', + 7: 'DB_CONTEXT_DONE_EVENT', + 8: 'DB_BREAK_BATCH_EVENT', + 9: 'DB_INVOKE_CHANGE_EVENT', + 10: 'DB_CONTEXT_SUSPEND_EVENT', +} +DB_FLUSH_AND_INV_DB_DATA_TS = 0 +DB_FLUSH_AND_INV_DB_META = 1 +DB_CACHE_FLUSH = 2 +DB_CACHE_FLUSH_TS = 3 +DB_CACHE_FLUSH_AND_INV_EVENT = 4 +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 +DB_VPORT_CHANGED_EVENT = 6 +DB_CONTEXT_DONE_EVENT = 7 +DB_BREAK_BATCH_EVENT = 8 +DB_INVOKE_CHANGE_EVENT = 9 +DB_CONTEXT_SUSPEND_EVENT = 10 +DFSMFlushEvents = ctypes.c_uint32 # enum + +# values for enumeration 'DbMemArbWatermarks' +DbMemArbWatermarks__enumvalues = { + 0: 'TRANSFERRED_64_BYTES', + 1: 'TRANSFERRED_128_BYTES', + 2: 'TRANSFERRED_256_BYTES', + 3: 'TRANSFERRED_512_BYTES', + 4: 'TRANSFERRED_1024_BYTES', + 5: 'TRANSFERRED_2048_BYTES', + 6: 'TRANSFERRED_4096_BYTES', + 7: 'TRANSFERRED_8192_BYTES', +} +TRANSFERRED_64_BYTES = 0 +TRANSFERRED_128_BYTES = 1 +TRANSFERRED_256_BYTES = 2 +TRANSFERRED_512_BYTES = 3 +TRANSFERRED_1024_BYTES = 4 +TRANSFERRED_2048_BYTES = 5 +TRANSFERRED_4096_BYTES = 6 +TRANSFERRED_8192_BYTES = 7 +DbMemArbWatermarks = ctypes.c_uint32 # enum + +# values for enumeration 'DbPRTFaultBehavior' +DbPRTFaultBehavior__enumvalues = { + 0: 'FAULT_ZERO', + 1: 'FAULT_ONE', + 2: 'FAULT_FAIL', + 3: 'FAULT_PASS', +} +FAULT_ZERO = 0 +FAULT_ONE = 1 +FAULT_FAIL = 2 +FAULT_PASS = 3 +DbPRTFaultBehavior = ctypes.c_uint32 # enum + +# values for enumeration 'DbPSLControl' +DbPSLControl__enumvalues = { + 0: 'PSLC_AUTO', + 1: 'PSLC_ON_HANG_ONLY', + 2: 'PSLC_ASAP', + 3: 'PSLC_COUNTDOWN', +} +PSLC_AUTO = 0 +PSLC_ON_HANG_ONLY = 1 +PSLC_ASAP = 2 +PSLC_COUNTDOWN = 3 +DbPSLControl = ctypes.c_uint32 # enum + +# values for enumeration 'ForceControl' +ForceControl__enumvalues = { + 0: 'FORCE_OFF', + 1: 'FORCE_ENABLE', + 2: 'FORCE_DISABLE', + 3: 'FORCE_RESERVED', +} +FORCE_OFF = 0 +FORCE_ENABLE = 1 +FORCE_DISABLE = 2 +FORCE_RESERVED = 3 +ForceControl = ctypes.c_uint32 # enum + +# values for enumeration 'OreoMode' +OreoMode__enumvalues = { + 0: 'OMODE_BLEND', + 1: 'OMODE_O_THEN_B', + 2: 'OMODE_P_THEN_O_THEN_B', + 3: 'OMODE_RESERVED_3', +} +OMODE_BLEND = 0 +OMODE_O_THEN_B = 1 +OMODE_P_THEN_O_THEN_B = 2 +OMODE_RESERVED_3 = 3 +OreoMode = ctypes.c_uint32 # enum + +# values for enumeration 'PerfCounter_Vals' +PerfCounter_Vals__enumvalues = { + 0: 'DB_PERF_SEL_SC_DB_tile_sends', + 1: 'DB_PERF_SEL_SC_DB_tile_busy', + 2: 'DB_PERF_SEL_SC_DB_tile_stalls', + 3: 'DB_PERF_SEL_SC_DB_tile_events', + 4: 'DB_PERF_SEL_SC_DB_tile_tiles', + 5: 'DB_PERF_SEL_SC_DB_tile_covered', + 6: 'DB_PERF_SEL_hiz_tc_read_starved', + 7: 'DB_PERF_SEL_hiz_tc_write_stall', + 8: 'DB_PERF_SEL_hiz_tile_culled', + 9: 'DB_PERF_SEL_his_tile_culled', + 10: 'DB_PERF_SEL_DB_SC_tile_sends', + 11: 'DB_PERF_SEL_DB_SC_tile_busy', + 12: 'DB_PERF_SEL_DB_SC_tile_stalls', + 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 14: 'DB_PERF_SEL_DB_SC_tile_tiles', + 15: 'DB_PERF_SEL_DB_SC_tile_culled', + 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', + 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 23: 'DB_PERF_SEL_SC_DB_quad_sends', + 24: 'DB_PERF_SEL_SC_DB_quad_busy', + 25: 'DB_PERF_SEL_SC_DB_quad_squads', + 26: 'DB_PERF_SEL_SC_DB_quad_tiles', + 27: 'DB_PERF_SEL_SC_DB_quad_pixels', + 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 29: 'DB_PERF_SEL_DB_SC_quad_sends', + 30: 'DB_PERF_SEL_DB_SC_quad_busy', + 31: 'DB_PERF_SEL_DB_SC_quad_stalls', + 32: 'DB_PERF_SEL_DB_SC_quad_tiles', + 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 34: 'DB_PERF_SEL_DB_CB_tile_sends', + 35: 'DB_PERF_SEL_DB_CB_tile_busy', + 36: 'DB_PERF_SEL_DB_CB_tile_stalls', + 37: 'DB_PERF_SEL_SX_DB_quad_sends', + 38: 'DB_PERF_SEL_SX_DB_quad_busy', + 39: 'DB_PERF_SEL_SX_DB_quad_stalls', + 40: 'DB_PERF_SEL_SX_DB_quad_quads', + 41: 'DB_PERF_SEL_SX_DB_quad_pixels', + 42: 'DB_PERF_SEL_SX_DB_quad_exports', + 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', + 44: 'DB_PERF_SEL_DB_CB_lquad_sends', + 45: 'DB_PERF_SEL_DB_CB_lquad_busy', + 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', + 47: 'DB_PERF_SEL_DB_CB_lquad_quads', + 48: 'DB_PERF_SEL_tile_rd_sends', + 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 50: 'DB_PERF_SEL_quad_rd_sends', + 51: 'DB_PERF_SEL_quad_rd_busy', + 52: 'DB_PERF_SEL_quad_rd_mi_stall', + 53: 'DB_PERF_SEL_quad_rd_rw_collision', + 54: 'DB_PERF_SEL_quad_rd_tag_stall', + 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', + 56: 'DB_PERF_SEL_quad_rd_panic', + 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 58: 'DB_PERF_SEL_quad_rdret_sends', + 59: 'DB_PERF_SEL_quad_rdret_busy', + 60: 'DB_PERF_SEL_tile_wr_sends', + 61: 'DB_PERF_SEL_tile_wr_acks', + 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 63: 'DB_PERF_SEL_quad_wr_sends', + 64: 'DB_PERF_SEL_quad_wr_busy', + 65: 'DB_PERF_SEL_quad_wr_mi_stall', + 66: 'DB_PERF_SEL_quad_wr_coherency_stall', + 67: 'DB_PERF_SEL_quad_wr_acks', + 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 69: 'DB_PERF_SEL_Tile_Cache_misses', + 70: 'DB_PERF_SEL_Tile_Cache_hits', + 71: 'DB_PERF_SEL_Tile_Cache_flushes', + 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', + 73: 'DB_PERF_SEL_Tile_Cache_starves', + 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 75: 'DB_PERF_SEL_tcp_dispatcher_reads', + 76: 'DB_PERF_SEL_tcp_prefetcher_reads', + 77: 'DB_PERF_SEL_tcp_preloader_reads', + 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', + 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', + 80: 'DB_PERF_SEL_tcp_preloader_flushes', + 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', + 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 95: 'DB_PERF_SEL_Stencil_Cache_misses', + 96: 'DB_PERF_SEL_Stencil_Cache_hits', + 97: 'DB_PERF_SEL_Stencil_Cache_flushes', + 98: 'DB_PERF_SEL_Stencil_Cache_starves', + 99: 'DB_PERF_SEL_Stencil_Cache_frees', + 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', + 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', + 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', + 108: 'DB_PERF_SEL_Z_Cache_frees', + 109: 'DB_PERF_SEL_Plane_Cache_misses', + 110: 'DB_PERF_SEL_Plane_Cache_hits', + 111: 'DB_PERF_SEL_Plane_Cache_flushes', + 112: 'DB_PERF_SEL_Plane_Cache_starves', + 113: 'DB_PERF_SEL_Plane_Cache_frees', + 114: 'DB_PERF_SEL_flush_expanded_stencil', + 115: 'DB_PERF_SEL_flush_compressed_stencil', + 116: 'DB_PERF_SEL_flush_single_stencil', + 117: 'DB_PERF_SEL_planes_flushed', + 118: 'DB_PERF_SEL_flush_1plane', + 119: 'DB_PERF_SEL_flush_2plane', + 120: 'DB_PERF_SEL_flush_3plane', + 121: 'DB_PERF_SEL_flush_4plane', + 122: 'DB_PERF_SEL_flush_5plane', + 123: 'DB_PERF_SEL_flush_6plane', + 124: 'DB_PERF_SEL_flush_7plane', + 125: 'DB_PERF_SEL_flush_8plane', + 126: 'DB_PERF_SEL_flush_9plane', + 127: 'DB_PERF_SEL_flush_10plane', + 128: 'DB_PERF_SEL_flush_11plane', + 129: 'DB_PERF_SEL_flush_12plane', + 130: 'DB_PERF_SEL_flush_13plane', + 131: 'DB_PERF_SEL_flush_14plane', + 132: 'DB_PERF_SEL_flush_15plane', + 133: 'DB_PERF_SEL_flush_16plane', + 134: 'DB_PERF_SEL_flush_expanded_z', + 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 137: 'DB_PERF_SEL_dk_tile_sends', + 138: 'DB_PERF_SEL_dk_tile_busy', + 139: 'DB_PERF_SEL_dk_tile_quad_starves', + 140: 'DB_PERF_SEL_dk_tile_stalls', + 141: 'DB_PERF_SEL_dk_squad_sends', + 142: 'DB_PERF_SEL_dk_squad_busy', + 143: 'DB_PERF_SEL_dk_squad_stalls', + 144: 'DB_PERF_SEL_Op_Pipe_Busy', + 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 146: 'DB_PERF_SEL_qc_busy', + 147: 'DB_PERF_SEL_qc_xfc', + 148: 'DB_PERF_SEL_qc_conflicts', + 149: 'DB_PERF_SEL_qc_full_stall', + 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', + 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', + 153: 'DB_PERF_SEL_tl_busy', + 154: 'DB_PERF_SEL_tl_dtc_read_starved', + 155: 'DB_PERF_SEL_tl_z_fetch_stall', + 156: 'DB_PERF_SEL_tl_stencil_stall', + 157: 'DB_PERF_SEL_tl_z_decompress_stall', + 158: 'DB_PERF_SEL_tl_stencil_locked_stall', + 159: 'DB_PERF_SEL_tl_events', + 160: 'DB_PERF_SEL_tl_summarize_squads', + 161: 'DB_PERF_SEL_tl_flush_expand_squads', + 162: 'DB_PERF_SEL_tl_expand_squads', + 163: 'DB_PERF_SEL_tl_preZ_squads', + 164: 'DB_PERF_SEL_tl_postZ_squads', + 165: 'DB_PERF_SEL_tl_preZ_noop_squads', + 166: 'DB_PERF_SEL_tl_postZ_noop_squads', + 167: 'DB_PERF_SEL_tl_tile_ops', + 168: 'DB_PERF_SEL_tl_in_xfc', + 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 170: 'DB_PERF_SEL_tl_in_fast_z_stall', + 171: 'DB_PERF_SEL_tl_out_xfc', + 172: 'DB_PERF_SEL_tl_out_squads', + 173: 'DB_PERF_SEL_zf_plane_multicycle', + 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', + 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', + 180: 'DB_PERF_SEL_ts_tc_update_stall', + 181: 'DB_PERF_SEL_sc_kick_start', + 182: 'DB_PERF_SEL_sc_kick_end', + 183: 'DB_PERF_SEL_clock_reg_active', + 184: 'DB_PERF_SEL_clock_main_active', + 185: 'DB_PERF_SEL_clock_mem_export_active', + 186: 'DB_PERF_SEL_esr_ps_out_busy', + 187: 'DB_PERF_SEL_esr_ps_lqf_busy', + 188: 'DB_PERF_SEL_esr_ps_lqf_stall', + 189: 'DB_PERF_SEL_etr_out_send', + 190: 'DB_PERF_SEL_etr_out_busy', + 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', + 193: 'DB_PERF_SEL_etr_out_esr_stall', + 194: 'DB_PERF_SEL_esr_ps_vic_busy', + 195: 'DB_PERF_SEL_esr_ps_vic_stall', + 196: 'DB_PERF_SEL_esr_eot_fwd_busy', + 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 198: 'DB_PERF_SEL_esr_eot_fwd_forward', + 199: 'DB_PERF_SEL_esr_sqq_zi_busy', + 200: 'DB_PERF_SEL_esr_sqq_zi_stall', + 201: 'DB_PERF_SEL_postzl_sq_pt_busy', + 202: 'DB_PERF_SEL_postzl_sq_pt_stall', + 203: 'DB_PERF_SEL_postzl_se_busy', + 204: 'DB_PERF_SEL_postzl_se_stall', + 205: 'DB_PERF_SEL_postzl_partial_launch', + 206: 'DB_PERF_SEL_postzl_full_launch', + 207: 'DB_PERF_SEL_postzl_partial_waiting', + 208: 'DB_PERF_SEL_postzl_tile_mem_stall', + 209: 'DB_PERF_SEL_postzl_tile_init_stall', + 210: 'DB_PERF_SEL_prezl_tile_mem_stall', + 211: 'DB_PERF_SEL_prezl_tile_init_stall', + 212: 'DB_PERF_SEL_dtt_sm_clash_stall', + 213: 'DB_PERF_SEL_dtt_sm_slot_stall', + 214: 'DB_PERF_SEL_dtt_sm_miss_stall', + 215: 'DB_PERF_SEL_mi_rdreq_busy', + 216: 'DB_PERF_SEL_mi_rdreq_stall', + 217: 'DB_PERF_SEL_mi_wrreq_busy', + 218: 'DB_PERF_SEL_mi_wrreq_stall', + 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 220: 'DB_PERF_SEL_dkg_tile_rate_tile', + 221: 'DB_PERF_SEL_prezl_src_in_sends', + 222: 'DB_PERF_SEL_prezl_src_in_stall', + 223: 'DB_PERF_SEL_prezl_src_in_squads', + 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', + 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 227: 'DB_PERF_SEL_prezl_src_out_stall', + 228: 'DB_PERF_SEL_postzl_src_in_sends', + 229: 'DB_PERF_SEL_postzl_src_in_stall', + 230: 'DB_PERF_SEL_postzl_src_in_squads', + 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', + 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 234: 'DB_PERF_SEL_postzl_src_out_stall', + 235: 'DB_PERF_SEL_esr_ps_src_in_sends', + 236: 'DB_PERF_SEL_esr_ps_src_in_stall', + 237: 'DB_PERF_SEL_esr_ps_src_in_squads', + 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 242: 'DB_PERF_SEL_esr_ps_src_out_stall', + 243: 'DB_PERF_SEL_depth_bounds_tile_culled', + 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 246: 'DB_PERF_SEL_flush_compressed', + 247: 'DB_PERF_SEL_flush_plane_le4', + 248: 'DB_PERF_SEL_tiles_z_fully_summarized', + 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', + 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', + 256: 'DB_PERF_SEL_di_dt_stall', + 257: 'Spare_257', + 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', + 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', + 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', + 261: 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 262: 'DB_PERF_SEL_DB_CB_lquad_double_format', + 263: 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 264: 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 265: 'DB_PERF_SEL_CB_DB_rdreq_sends', + 266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 267: 'DB_PERF_SEL_CB_DB_wrreq_sends', + 268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 269: 'DB_PERF_SEL_DB_CB_rdret_ack', + 270: 'DB_PERF_SEL_DB_CB_rdret_nack', + 271: 'DB_PERF_SEL_DB_CB_wrret_ack', + 272: 'DB_PERF_SEL_DB_CB_wrret_nack', + 273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 277: 'DB_PERF_SEL_unmapped_z_tile_culled', + 278: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 279: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 280: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 281: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 282: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 283: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 284: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 285: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 286: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 287: 'DB_PERF_SEL_DB_CB_context_dones', + 288: 'DB_PERF_SEL_DB_CB_eop_dones', + 289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 292: 'DB_PERF_SEL_SC_DB_tile_backface', + 293: 'DB_PERF_SEL_SC_DB_quad_quads', + 294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 298: 'DB_PERF_SEL_DB_SC_quad_double_quad', + 299: 'DB_PERF_SEL_SX_DB_quad_export_quads', + 300: 'DB_PERF_SEL_SX_DB_quad_double_format', + 301: 'DB_PERF_SEL_SX_DB_quad_fast_format', + 302: 'DB_PERF_SEL_SX_DB_quad_slow_format', + 303: 'DB_PERF_SEL_quad_rd_sends_unc', + 304: 'DB_PERF_SEL_quad_rd_mi_stall_unc', + 305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 310: 'DB_PERF_SEL_noz_waiting_for_postz_done', + 311: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', + 312: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', + 313: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', + 314: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', + 315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 316: 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 317: 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 319: 'DB_PERF_SEL_RMI_wr_z_32byte_req', + 320: 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 329: 'DB_PERF_SEL_esr_vic_sqq_busy', + 330: 'DB_PERF_SEL_esr_vic_sqq_stall', + 331: 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 344: 'DB_PERF_SEL_ts_events_pws_enable', + 345: 'DB_PERF_SEL_ps_events_pws_enable', + 346: 'DB_PERF_SEL_cs_events_pws_enable', + 347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', +} +DB_PERF_SEL_SC_DB_tile_sends = 0 +DB_PERF_SEL_SC_DB_tile_busy = 1 +DB_PERF_SEL_SC_DB_tile_stalls = 2 +DB_PERF_SEL_SC_DB_tile_events = 3 +DB_PERF_SEL_SC_DB_tile_tiles = 4 +DB_PERF_SEL_SC_DB_tile_covered = 5 +DB_PERF_SEL_hiz_tc_read_starved = 6 +DB_PERF_SEL_hiz_tc_write_stall = 7 +DB_PERF_SEL_hiz_tile_culled = 8 +DB_PERF_SEL_his_tile_culled = 9 +DB_PERF_SEL_DB_SC_tile_sends = 10 +DB_PERF_SEL_DB_SC_tile_busy = 11 +DB_PERF_SEL_DB_SC_tile_stalls = 12 +DB_PERF_SEL_DB_SC_tile_df_stalls = 13 +DB_PERF_SEL_DB_SC_tile_tiles = 14 +DB_PERF_SEL_DB_SC_tile_culled = 15 +DB_PERF_SEL_DB_SC_tile_hier_kill = 16 +DB_PERF_SEL_DB_SC_tile_fast_ops = 17 +DB_PERF_SEL_DB_SC_tile_no_ops = 18 +DB_PERF_SEL_DB_SC_tile_tile_rate = 19 +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 +DB_PERF_SEL_SC_DB_quad_sends = 23 +DB_PERF_SEL_SC_DB_quad_busy = 24 +DB_PERF_SEL_SC_DB_quad_squads = 25 +DB_PERF_SEL_SC_DB_quad_tiles = 26 +DB_PERF_SEL_SC_DB_quad_pixels = 27 +DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 +DB_PERF_SEL_DB_SC_quad_sends = 29 +DB_PERF_SEL_DB_SC_quad_busy = 30 +DB_PERF_SEL_DB_SC_quad_stalls = 31 +DB_PERF_SEL_DB_SC_quad_tiles = 32 +DB_PERF_SEL_DB_SC_quad_lit_quad = 33 +DB_PERF_SEL_DB_CB_tile_sends = 34 +DB_PERF_SEL_DB_CB_tile_busy = 35 +DB_PERF_SEL_DB_CB_tile_stalls = 36 +DB_PERF_SEL_SX_DB_quad_sends = 37 +DB_PERF_SEL_SX_DB_quad_busy = 38 +DB_PERF_SEL_SX_DB_quad_stalls = 39 +DB_PERF_SEL_SX_DB_quad_quads = 40 +DB_PERF_SEL_SX_DB_quad_pixels = 41 +DB_PERF_SEL_SX_DB_quad_exports = 42 +DB_PERF_SEL_SH_quads_outstanding_sum = 43 +DB_PERF_SEL_DB_CB_lquad_sends = 44 +DB_PERF_SEL_DB_CB_lquad_busy = 45 +DB_PERF_SEL_DB_CB_lquad_stalls = 46 +DB_PERF_SEL_DB_CB_lquad_quads = 47 +DB_PERF_SEL_tile_rd_sends = 48 +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 +DB_PERF_SEL_quad_rd_sends = 50 +DB_PERF_SEL_quad_rd_busy = 51 +DB_PERF_SEL_quad_rd_mi_stall = 52 +DB_PERF_SEL_quad_rd_rw_collision = 53 +DB_PERF_SEL_quad_rd_tag_stall = 54 +DB_PERF_SEL_quad_rd_32byte_reqs = 55 +DB_PERF_SEL_quad_rd_panic = 56 +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 +DB_PERF_SEL_quad_rdret_sends = 58 +DB_PERF_SEL_quad_rdret_busy = 59 +DB_PERF_SEL_tile_wr_sends = 60 +DB_PERF_SEL_tile_wr_acks = 61 +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 +DB_PERF_SEL_quad_wr_sends = 63 +DB_PERF_SEL_quad_wr_busy = 64 +DB_PERF_SEL_quad_wr_mi_stall = 65 +DB_PERF_SEL_quad_wr_coherency_stall = 66 +DB_PERF_SEL_quad_wr_acks = 67 +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 +DB_PERF_SEL_Tile_Cache_misses = 69 +DB_PERF_SEL_Tile_Cache_hits = 70 +DB_PERF_SEL_Tile_Cache_flushes = 71 +DB_PERF_SEL_Tile_Cache_surface_stall = 72 +DB_PERF_SEL_Tile_Cache_starves = 73 +DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 +DB_PERF_SEL_tcp_dispatcher_reads = 75 +DB_PERF_SEL_tcp_prefetcher_reads = 76 +DB_PERF_SEL_tcp_preloader_reads = 77 +DB_PERF_SEL_tcp_dispatcher_flushes = 78 +DB_PERF_SEL_tcp_prefetcher_flushes = 79 +DB_PERF_SEL_tcp_preloader_flushes = 80 +DB_PERF_SEL_Depth_Tile_Cache_sends = 81 +DB_PERF_SEL_Depth_Tile_Cache_busy = 82 +DB_PERF_SEL_Depth_Tile_Cache_starves = 83 +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 +DB_PERF_SEL_Depth_Tile_Cache_misses = 86 +DB_PERF_SEL_Depth_Tile_Cache_hits = 87 +DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 +DB_PERF_SEL_Depth_Tile_Cache_event = 91 +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 +DB_PERF_SEL_Stencil_Cache_misses = 95 +DB_PERF_SEL_Stencil_Cache_hits = 96 +DB_PERF_SEL_Stencil_Cache_flushes = 97 +DB_PERF_SEL_Stencil_Cache_starves = 98 +DB_PERF_SEL_Stencil_Cache_frees = 99 +DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 +DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 +DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 +DB_PERF_SEL_Z_Cache_pmask_misses = 104 +DB_PERF_SEL_Z_Cache_pmask_hits = 105 +DB_PERF_SEL_Z_Cache_pmask_flushes = 106 +DB_PERF_SEL_Z_Cache_pmask_starves = 107 +DB_PERF_SEL_Z_Cache_frees = 108 +DB_PERF_SEL_Plane_Cache_misses = 109 +DB_PERF_SEL_Plane_Cache_hits = 110 +DB_PERF_SEL_Plane_Cache_flushes = 111 +DB_PERF_SEL_Plane_Cache_starves = 112 +DB_PERF_SEL_Plane_Cache_frees = 113 +DB_PERF_SEL_flush_expanded_stencil = 114 +DB_PERF_SEL_flush_compressed_stencil = 115 +DB_PERF_SEL_flush_single_stencil = 116 +DB_PERF_SEL_planes_flushed = 117 +DB_PERF_SEL_flush_1plane = 118 +DB_PERF_SEL_flush_2plane = 119 +DB_PERF_SEL_flush_3plane = 120 +DB_PERF_SEL_flush_4plane = 121 +DB_PERF_SEL_flush_5plane = 122 +DB_PERF_SEL_flush_6plane = 123 +DB_PERF_SEL_flush_7plane = 124 +DB_PERF_SEL_flush_8plane = 125 +DB_PERF_SEL_flush_9plane = 126 +DB_PERF_SEL_flush_10plane = 127 +DB_PERF_SEL_flush_11plane = 128 +DB_PERF_SEL_flush_12plane = 129 +DB_PERF_SEL_flush_13plane = 130 +DB_PERF_SEL_flush_14plane = 131 +DB_PERF_SEL_flush_15plane = 132 +DB_PERF_SEL_flush_16plane = 133 +DB_PERF_SEL_flush_expanded_z = 134 +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 +DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 +DB_PERF_SEL_dk_tile_sends = 137 +DB_PERF_SEL_dk_tile_busy = 138 +DB_PERF_SEL_dk_tile_quad_starves = 139 +DB_PERF_SEL_dk_tile_stalls = 140 +DB_PERF_SEL_dk_squad_sends = 141 +DB_PERF_SEL_dk_squad_busy = 142 +DB_PERF_SEL_dk_squad_stalls = 143 +DB_PERF_SEL_Op_Pipe_Busy = 144 +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 +DB_PERF_SEL_qc_busy = 146 +DB_PERF_SEL_qc_xfc = 147 +DB_PERF_SEL_qc_conflicts = 148 +DB_PERF_SEL_qc_full_stall = 149 +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 +DB_PERF_SEL_tsc_insert_summarize_stall = 152 +DB_PERF_SEL_tl_busy = 153 +DB_PERF_SEL_tl_dtc_read_starved = 154 +DB_PERF_SEL_tl_z_fetch_stall = 155 +DB_PERF_SEL_tl_stencil_stall = 156 +DB_PERF_SEL_tl_z_decompress_stall = 157 +DB_PERF_SEL_tl_stencil_locked_stall = 158 +DB_PERF_SEL_tl_events = 159 +DB_PERF_SEL_tl_summarize_squads = 160 +DB_PERF_SEL_tl_flush_expand_squads = 161 +DB_PERF_SEL_tl_expand_squads = 162 +DB_PERF_SEL_tl_preZ_squads = 163 +DB_PERF_SEL_tl_postZ_squads = 164 +DB_PERF_SEL_tl_preZ_noop_squads = 165 +DB_PERF_SEL_tl_postZ_noop_squads = 166 +DB_PERF_SEL_tl_tile_ops = 167 +DB_PERF_SEL_tl_in_xfc = 168 +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 +DB_PERF_SEL_tl_in_fast_z_stall = 170 +DB_PERF_SEL_tl_out_xfc = 171 +DB_PERF_SEL_tl_out_squads = 172 +DB_PERF_SEL_zf_plane_multicycle = 173 +DB_PERF_SEL_PostZ_Samples_passing_Z = 174 +DB_PERF_SEL_PostZ_Samples_failing_Z = 175 +DB_PERF_SEL_PostZ_Samples_failing_S = 176 +DB_PERF_SEL_PreZ_Samples_passing_Z = 177 +DB_PERF_SEL_PreZ_Samples_failing_Z = 178 +DB_PERF_SEL_PreZ_Samples_failing_S = 179 +DB_PERF_SEL_ts_tc_update_stall = 180 +DB_PERF_SEL_sc_kick_start = 181 +DB_PERF_SEL_sc_kick_end = 182 +DB_PERF_SEL_clock_reg_active = 183 +DB_PERF_SEL_clock_main_active = 184 +DB_PERF_SEL_clock_mem_export_active = 185 +DB_PERF_SEL_esr_ps_out_busy = 186 +DB_PERF_SEL_esr_ps_lqf_busy = 187 +DB_PERF_SEL_esr_ps_lqf_stall = 188 +DB_PERF_SEL_etr_out_send = 189 +DB_PERF_SEL_etr_out_busy = 190 +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 +DB_PERF_SEL_etr_out_cb_tile_stall = 192 +DB_PERF_SEL_etr_out_esr_stall = 193 +DB_PERF_SEL_esr_ps_vic_busy = 194 +DB_PERF_SEL_esr_ps_vic_stall = 195 +DB_PERF_SEL_esr_eot_fwd_busy = 196 +DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 +DB_PERF_SEL_esr_eot_fwd_forward = 198 +DB_PERF_SEL_esr_sqq_zi_busy = 199 +DB_PERF_SEL_esr_sqq_zi_stall = 200 +DB_PERF_SEL_postzl_sq_pt_busy = 201 +DB_PERF_SEL_postzl_sq_pt_stall = 202 +DB_PERF_SEL_postzl_se_busy = 203 +DB_PERF_SEL_postzl_se_stall = 204 +DB_PERF_SEL_postzl_partial_launch = 205 +DB_PERF_SEL_postzl_full_launch = 206 +DB_PERF_SEL_postzl_partial_waiting = 207 +DB_PERF_SEL_postzl_tile_mem_stall = 208 +DB_PERF_SEL_postzl_tile_init_stall = 209 +DB_PERF_SEL_prezl_tile_mem_stall = 210 +DB_PERF_SEL_prezl_tile_init_stall = 211 +DB_PERF_SEL_dtt_sm_clash_stall = 212 +DB_PERF_SEL_dtt_sm_slot_stall = 213 +DB_PERF_SEL_dtt_sm_miss_stall = 214 +DB_PERF_SEL_mi_rdreq_busy = 215 +DB_PERF_SEL_mi_rdreq_stall = 216 +DB_PERF_SEL_mi_wrreq_busy = 217 +DB_PERF_SEL_mi_wrreq_stall = 218 +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 +DB_PERF_SEL_dkg_tile_rate_tile = 220 +DB_PERF_SEL_prezl_src_in_sends = 221 +DB_PERF_SEL_prezl_src_in_stall = 222 +DB_PERF_SEL_prezl_src_in_squads = 223 +DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 +DB_PERF_SEL_prezl_src_in_tile_rate = 225 +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 +DB_PERF_SEL_prezl_src_out_stall = 227 +DB_PERF_SEL_postzl_src_in_sends = 228 +DB_PERF_SEL_postzl_src_in_stall = 229 +DB_PERF_SEL_postzl_src_in_squads = 230 +DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 +DB_PERF_SEL_postzl_src_in_tile_rate = 232 +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 +DB_PERF_SEL_postzl_src_out_stall = 234 +DB_PERF_SEL_esr_ps_src_in_sends = 235 +DB_PERF_SEL_esr_ps_src_in_stall = 236 +DB_PERF_SEL_esr_ps_src_in_squads = 237 +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 +DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 +DB_PERF_SEL_esr_ps_src_out_stall = 242 +DB_PERF_SEL_depth_bounds_tile_culled = 243 +DB_PERF_SEL_PreZ_Samples_failing_DB = 244 +DB_PERF_SEL_PostZ_Samples_failing_DB = 245 +DB_PERF_SEL_flush_compressed = 246 +DB_PERF_SEL_flush_plane_le4 = 247 +DB_PERF_SEL_tiles_z_fully_summarized = 248 +DB_PERF_SEL_tiles_stencil_fully_summarized = 249 +DB_PERF_SEL_tiles_z_clear_on_expclear = 250 +DB_PERF_SEL_tiles_s_clear_on_expclear = 251 +DB_PERF_SEL_tiles_decomp_on_expclear = 252 +DB_PERF_SEL_tiles_compressed_to_decompressed = 253 +DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 +DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 +DB_PERF_SEL_di_dt_stall = 256 +Spare_257 = 257 +DB_PERF_SEL_DB_SC_s_tile_rate = 258 +DB_PERF_SEL_DB_SC_c_tile_rate = 259 +DB_PERF_SEL_DB_SC_z_tile_rate = 260 +DB_PERF_SEL_DB_CB_lquad_export_quads = 261 +DB_PERF_SEL_DB_CB_lquad_double_format = 262 +DB_PERF_SEL_DB_CB_lquad_fast_format = 263 +DB_PERF_SEL_DB_CB_lquad_slow_format = 264 +DB_PERF_SEL_CB_DB_rdreq_sends = 265 +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266 +DB_PERF_SEL_CB_DB_wrreq_sends = 267 +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268 +DB_PERF_SEL_DB_CB_rdret_ack = 269 +DB_PERF_SEL_DB_CB_rdret_nack = 270 +DB_PERF_SEL_DB_CB_wrret_ack = 271 +DB_PERF_SEL_DB_CB_wrret_nack = 272 +DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273 +DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274 +DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275 +DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276 +DB_PERF_SEL_unmapped_z_tile_culled = 277 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 278 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279 +DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 280 +DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 281 +DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 282 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 283 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 284 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 285 +DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 286 +DB_PERF_SEL_DB_CB_context_dones = 287 +DB_PERF_SEL_DB_CB_eop_dones = 288 +DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289 +DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290 +DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291 +DB_PERF_SEL_SC_DB_tile_backface = 292 +DB_PERF_SEL_SC_DB_quad_quads = 293 +DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294 +DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295 +DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296 +DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297 +DB_PERF_SEL_DB_SC_quad_double_quad = 298 +DB_PERF_SEL_SX_DB_quad_export_quads = 299 +DB_PERF_SEL_SX_DB_quad_double_format = 300 +DB_PERF_SEL_SX_DB_quad_fast_format = 301 +DB_PERF_SEL_SX_DB_quad_slow_format = 302 +DB_PERF_SEL_quad_rd_sends_unc = 303 +DB_PERF_SEL_quad_rd_mi_stall_unc = 304 +DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305 +DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306 +DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307 +DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308 +DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309 +DB_PERF_SEL_noz_waiting_for_postz_done = 310 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 311 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 312 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 313 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 314 +DB_PERF_SEL_RMI_rd_tile_32byte_req = 315 +DB_PERF_SEL_RMI_rd_z_32byte_req = 316 +DB_PERF_SEL_RMI_rd_s_32byte_req = 317 +DB_PERF_SEL_RMI_wr_tile_32byte_req = 318 +DB_PERF_SEL_RMI_wr_z_32byte_req = 319 +DB_PERF_SEL_RMI_wr_s_32byte_req = 320 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321 +DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322 +DB_PERF_SEL_RMI_rd_z_32byte_ret = 323 +DB_PERF_SEL_RMI_rd_s_32byte_ret = 324 +DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325 +DB_PERF_SEL_RMI_wr_z_32byte_ack = 326 +DB_PERF_SEL_RMI_wr_s_32byte_ack = 327 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328 +DB_PERF_SEL_esr_vic_sqq_busy = 329 +DB_PERF_SEL_esr_vic_sqq_stall = 330 +DB_PERF_SEL_esr_psi_vic_tile_rate = 331 +DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332 +DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333 +DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334 +DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335 +DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336 +DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337 +DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338 +DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339 +DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340 +DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341 +DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342 +DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343 +DB_PERF_SEL_ts_events_pws_enable = 344 +DB_PERF_SEL_ps_events_pws_enable = 345 +DB_PERF_SEL_cs_events_pws_enable = 346 +DB_PERF_SEL_DB_SC_quad_noz_tiles = 347 +DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348 +PerfCounter_Vals = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeCounterId' +PixelPipeCounterId__enumvalues = { + 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', + 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', +} +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 +PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 +PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 +PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 +PixelPipeCounterId = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeStride' +PixelPipeStride__enumvalues = { + 0: 'PIXEL_PIPE_STRIDE_32_BITS', + 1: 'PIXEL_PIPE_STRIDE_64_BITS', + 2: 'PIXEL_PIPE_STRIDE_128_BITS', + 3: 'PIXEL_PIPE_STRIDE_256_BITS', +} +PIXEL_PIPE_STRIDE_32_BITS = 0 +PIXEL_PIPE_STRIDE_64_BITS = 1 +PIXEL_PIPE_STRIDE_128_BITS = 2 +PIXEL_PIPE_STRIDE_256_BITS = 3 +PixelPipeStride = ctypes.c_uint32 # enum + +# values for enumeration 'RingCounterControl' +RingCounterControl__enumvalues = { + 0: 'COUNTER_RING_SPLIT', + 1: 'COUNTER_RING_0', + 2: 'COUNTER_RING_1', +} +COUNTER_RING_SPLIT = 0 +COUNTER_RING_0 = 1 +COUNTER_RING_1 = 2 +RingCounterControl = ctypes.c_uint32 # enum + +# values for enumeration 'StencilOp' +StencilOp__enumvalues = { + 0: 'STENCIL_KEEP', + 1: 'STENCIL_ZERO', + 2: 'STENCIL_ONES', + 3: 'STENCIL_REPLACE_TEST', + 4: 'STENCIL_REPLACE_OP', + 5: 'STENCIL_ADD_CLAMP', + 6: 'STENCIL_SUB_CLAMP', + 7: 'STENCIL_INVERT', + 8: 'STENCIL_ADD_WRAP', + 9: 'STENCIL_SUB_WRAP', + 10: 'STENCIL_AND', + 11: 'STENCIL_OR', + 12: 'STENCIL_XOR', + 13: 'STENCIL_NAND', + 14: 'STENCIL_NOR', + 15: 'STENCIL_XNOR', +} +STENCIL_KEEP = 0 +STENCIL_ZERO = 1 +STENCIL_ONES = 2 +STENCIL_REPLACE_TEST = 3 +STENCIL_REPLACE_OP = 4 +STENCIL_ADD_CLAMP = 5 +STENCIL_SUB_CLAMP = 6 +STENCIL_INVERT = 7 +STENCIL_ADD_WRAP = 8 +STENCIL_SUB_WRAP = 9 +STENCIL_AND = 10 +STENCIL_OR = 11 +STENCIL_XOR = 12 +STENCIL_NAND = 13 +STENCIL_NOR = 14 +STENCIL_XNOR = 15 +StencilOp = ctypes.c_uint32 # enum + +# values for enumeration 'ZLimitSumm' +ZLimitSumm__enumvalues = { + 0: 'FORCE_SUMM_OFF', + 1: 'FORCE_SUMM_MINZ', + 2: 'FORCE_SUMM_MAXZ', + 3: 'FORCE_SUMM_BOTH', +} +FORCE_SUMM_OFF = 0 +FORCE_SUMM_MINZ = 1 +FORCE_SUMM_MAXZ = 2 +FORCE_SUMM_BOTH = 3 +ZLimitSumm = ctypes.c_uint32 # enum + +# values for enumeration 'ZModeForce' +ZModeForce__enumvalues = { + 0: 'NO_FORCE', + 1: 'FORCE_EARLY_Z', + 2: 'FORCE_LATE_Z', + 3: 'FORCE_RE_Z', +} +NO_FORCE = 0 +FORCE_EARLY_Z = 1 +FORCE_LATE_Z = 2 +FORCE_RE_Z = 3 +ZModeForce = ctypes.c_uint32 # enum + +# values for enumeration 'ZOrder' +ZOrder__enumvalues = { + 0: 'LATE_Z', + 1: 'EARLY_Z_THEN_LATE_Z', + 2: 'RE_Z', + 3: 'EARLY_Z_THEN_RE_Z', +} +LATE_Z = 0 +EARLY_Z_THEN_LATE_Z = 1 +RE_Z = 2 +EARLY_Z_THEN_RE_Z = 3 +ZOrder = ctypes.c_uint32 # enum + +# values for enumeration 'ZSamplePosition' +ZSamplePosition__enumvalues = { + 0: 'Z_SAMPLE_CENTER', + 1: 'Z_SAMPLE_CENTROID', +} +Z_SAMPLE_CENTER = 0 +Z_SAMPLE_CENTROID = 1 +ZSamplePosition = ctypes.c_uint32 # enum + +# values for enumeration 'ZpassControl' +ZpassControl__enumvalues = { + 0: 'ZPASS_DISABLE', + 1: 'ZPASS_SAMPLES', + 2: 'ZPASS_PIXELS', +} +ZPASS_DISABLE = 0 +ZPASS_SAMPLES = 1 +ZPASS_PIXELS = 2 +ZpassControl = ctypes.c_uint32 # enum + +# values for enumeration 'SU_PERFCNT_SEL' +SU_PERFCNT_SEL__enumvalues = { + 0: 'PERF_PAPC_PASX_REQ', + 1: 'PERF_PAPC_PASX_DISABLE_PIPE', + 2: 'PERF_PAPC_PASX_FIRST_VECTOR', + 3: 'PERF_PAPC_PASX_SECOND_VECTOR', + 4: 'PERF_PAPC_PASX_FIRST_DEAD', + 5: 'PERF_PAPC_PASX_SECOND_DEAD', + 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 8: 'PERF_PAPC_PA_INPUT_PRIM', + 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', + 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 14: 'PERF_PAPC_CLPR_CULL_PRIM', + 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', + 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', + 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', + 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', + 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', + 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 39: 'PERF_PAPC_CLSM_NULL_PRIM', + 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', + 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', + 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', + 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', + 49: 'PERF_PAPC_SU_INPUT_PRIM', + 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', + 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 61: 'PERF_PAPC_SU_OUTPUT_PRIM', + 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', + 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', + 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 77: 'PERF_PAPC_PASX_REQ_IDLE', + 78: 'PERF_PAPC_PASX_REQ_BUSY', + 79: 'PERF_PAPC_PASX_REQ_STALLED', + 80: 'PERF_PAPC_PASX_REC_IDLE', + 81: 'PERF_PAPC_PASX_REC_BUSY', + 82: 'PERF_PAPC_PASX_REC_STARVED_SX', + 83: 'PERF_PAPC_PASX_REC_STALLED', + 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 86: 'PERF_PAPC_CCGSM_IDLE', + 87: 'PERF_PAPC_CCGSM_BUSY', + 88: 'PERF_PAPC_CCGSM_STALLED', + 89: 'PERF_PAPC_CLPRIM_IDLE', + 90: 'PERF_PAPC_CLPRIM_BUSY', + 91: 'PERF_PAPC_CLPRIM_STALLED', + 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 93: 'PERF_PAPC_CLIPSM_IDLE', + 94: 'PERF_PAPC_CLIPSM_BUSY', + 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', + 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 100: 'PERF_PAPC_CLIPGA_IDLE', + 101: 'PERF_PAPC_CLIPGA_BUSY', + 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 103: 'PERF_PAPC_CLIPGA_STALLED', + 104: 'PERF_PAPC_CLIP_IDLE', + 105: 'PERF_PAPC_CLIP_BUSY', + 106: 'PERF_PAPC_SU_IDLE', + 107: 'PERF_PAPC_SU_BUSY', + 108: 'PERF_PAPC_SU_STARVED_CLIP', + 109: 'PERF_PAPC_SU_STALLED_SC', + 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', + 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', + 112: 'PERF_PAPC_PA_REG_SCLK_VLD', + 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 114: 'PERF_PAPC_PASX_SE0_REQ', + 115: 'PERF_PAPC_PASX_SE1_REQ', + 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', + 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', + 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 131: 'PERF_PAPC_SU_SE0_STALLED_SC', + 132: 'PERF_PAPC_SU_SE1_STALLED_SC', + 133: 'PERF_PAPC_SU_SE01_STALLED_SC', + 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 135: 'PERF_PAPC_SU_CULLED_PRIM', + 136: 'PERF_PAPC_SU_OUTPUT_EOPG', + 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 151: 'PERF_PAPC_SU_SE2_STALLED_SC', + 152: 'PERF_PAPC_SU_SE3_STALLED_SC', + 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', + 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', + 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', + 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', + 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', + 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', + 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', + 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 170: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 171: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 172: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 173: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 174: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 175: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 176: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 177: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 179: 'PERF_PA_VERTEX_FIFO_FULL', + 180: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', + 182: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 183: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', + 185: 'PERF_PA_PIPE0_SWITCHED_GEN', + 186: 'PERF_PA_PIPE1_SWITCHED_GEN', + 188: 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 189: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 190: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 191: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 192: 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', + 193: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 194: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 195: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', + 196: 'PERF_ENGG_CSB_NULL_SUBGROUP', + 197: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 198: 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 199: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', + 200: 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 201: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', + 202: 'PERF_ENGG_CSB_DELAY_BIN00', + 203: 'PERF_ENGG_CSB_DELAY_BIN01', + 204: 'PERF_ENGG_CSB_DELAY_BIN02', + 205: 'PERF_ENGG_CSB_DELAY_BIN03', + 206: 'PERF_ENGG_CSB_DELAY_BIN04', + 207: 'PERF_ENGG_CSB_DELAY_BIN05', + 208: 'PERF_ENGG_CSB_DELAY_BIN06', + 209: 'PERF_ENGG_CSB_DELAY_BIN07', + 210: 'PERF_ENGG_CSB_DELAY_BIN08', + 211: 'PERF_ENGG_CSB_DELAY_BIN09', + 212: 'PERF_ENGG_CSB_DELAY_BIN10', + 213: 'PERF_ENGG_CSB_DELAY_BIN11', + 214: 'PERF_ENGG_CSB_DELAY_BIN12', + 215: 'PERF_ENGG_CSB_DELAY_BIN13', + 216: 'PERF_ENGG_CSB_DELAY_BIN14', + 217: 'PERF_ENGG_CSB_DELAY_BIN15', + 218: 'PERF_ENGG_CSB_SPI_DELAY_BIN00', + 219: 'PERF_ENGG_CSB_SPI_DELAY_BIN01', + 220: 'PERF_ENGG_CSB_SPI_DELAY_BIN02', + 221: 'PERF_ENGG_CSB_SPI_DELAY_BIN03', + 222: 'PERF_ENGG_CSB_SPI_DELAY_BIN04', + 223: 'PERF_ENGG_CSB_SPI_DELAY_BIN05', + 224: 'PERF_ENGG_CSB_SPI_DELAY_BIN06', + 225: 'PERF_ENGG_CSB_SPI_DELAY_BIN07', + 226: 'PERF_ENGG_CSB_SPI_DELAY_BIN08', + 227: 'PERF_ENGG_CSB_SPI_DELAY_BIN09', + 228: 'PERF_ENGG_CSB_SPI_DELAY_BIN10', + 229: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 230: 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', + 231: 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', + 232: 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', + 233: 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', + 234: 'PERF_ENGG_INDEX_REQ_STARVED', + 235: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 236: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 237: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 238: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 239: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 240: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 241: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 242: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 243: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 244: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 245: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 246: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 247: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 253: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 254: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 255: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 256: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 257: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 258: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', + 259: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', + 260: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', + 261: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', + 262: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', + 263: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 264: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 265: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 266: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 267: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 268: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 269: 'PERF_ENGG_POS_REQ_STARVED', + 270: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 271: 'PERF_ENGG_BUSY', + 272: 'PERF_CLIPSM_CULL_PRIMS_CNT', + 273: 'PERF_PH_SEND_1_SC', + 274: 'PERF_PH_SEND_2_SC', + 275: 'PERF_PH_SEND_3_SC', + 276: 'PERF_PH_SEND_4_SC', + 277: 'PERF_OUTPUT_PRIM_1_SC', + 278: 'PERF_OUTPUT_PRIM_2_SC', + 279: 'PERF_OUTPUT_PRIM_3_SC', + 280: 'PERF_OUTPUT_PRIM_4_SC', +} +PERF_PAPC_PASX_REQ = 0 +PERF_PAPC_PASX_DISABLE_PIPE = 1 +PERF_PAPC_PASX_FIRST_VECTOR = 2 +PERF_PAPC_PASX_SECOND_VECTOR = 3 +PERF_PAPC_PASX_FIRST_DEAD = 4 +PERF_PAPC_PASX_SECOND_DEAD = 5 +PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 +PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 +PERF_PAPC_PA_INPUT_PRIM = 8 +PERF_PAPC_PA_INPUT_NULL_PRIM = 9 +PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 +PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 +PERF_PAPC_CLPR_CULL_PRIM = 14 +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 +PERF_PAPC_CLPR_VV_CULL_PRIM = 16 +PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 +PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 +PERF_PAPC_CLSM_NULL_PRIM = 39 +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 +PERF_PAPC_SU_INPUT_PRIM = 49 +PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 +PERF_PAPC_SU_INPUT_NULL_PRIM = 51 +PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 +PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 +PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 +PERF_PAPC_SU_OUTPUT_PRIM = 61 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 +PERF_PAPC_PASX_REQ_IDLE = 77 +PERF_PAPC_PASX_REQ_BUSY = 78 +PERF_PAPC_PASX_REQ_STALLED = 79 +PERF_PAPC_PASX_REC_IDLE = 80 +PERF_PAPC_PASX_REC_BUSY = 81 +PERF_PAPC_PASX_REC_STARVED_SX = 82 +PERF_PAPC_PASX_REC_STALLED = 83 +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 +PERF_PAPC_CCGSM_IDLE = 86 +PERF_PAPC_CCGSM_BUSY = 87 +PERF_PAPC_CCGSM_STALLED = 88 +PERF_PAPC_CLPRIM_IDLE = 89 +PERF_PAPC_CLPRIM_BUSY = 90 +PERF_PAPC_CLPRIM_STALLED = 91 +PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 +PERF_PAPC_CLIPSM_IDLE = 93 +PERF_PAPC_CLIPSM_BUSY = 94 +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 +PERF_PAPC_CLIPGA_IDLE = 100 +PERF_PAPC_CLIPGA_BUSY = 101 +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 +PERF_PAPC_CLIPGA_STALLED = 103 +PERF_PAPC_CLIP_IDLE = 104 +PERF_PAPC_CLIP_BUSY = 105 +PERF_PAPC_SU_IDLE = 106 +PERF_PAPC_SU_BUSY = 107 +PERF_PAPC_SU_STARVED_CLIP = 108 +PERF_PAPC_SU_STALLED_SC = 109 +PERF_PAPC_CL_DYN_SCLK_VLD = 110 +PERF_PAPC_SU_DYN_SCLK_VLD = 111 +PERF_PAPC_PA_REG_SCLK_VLD = 112 +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 +PERF_PAPC_PASX_SE0_REQ = 114 +PERF_PAPC_PASX_SE1_REQ = 115 +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 +PERF_PAPC_SU_SE0_STALLED_SC = 131 +PERF_PAPC_SU_SE1_STALLED_SC = 132 +PERF_PAPC_SU_SE01_STALLED_SC = 133 +PERF_PAPC_CLSM_CLIPPING_PRIM = 134 +PERF_PAPC_SU_CULLED_PRIM = 135 +PERF_PAPC_SU_OUTPUT_EOPG = 136 +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 +PERF_PAPC_SU_SE2_STALLED_SC = 151 +PERF_PAPC_SU_SE3_STALLED_SC = 152 +PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 +PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 +PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 +PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 +PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 +PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 +PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 +PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 +PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 +PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 +PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 +PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 +PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 +PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166 +PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167 +PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168 +PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 170 +PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 171 +PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 172 +PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 173 +PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 174 +PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 175 +PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 176 +PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 177 +PERF_PA_VERTEX_FIFO_FULL = 179 +PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 180 +PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 182 +PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 183 +PERF_PA_PIPE0_SWITCHED_GEN = 185 +PERF_PA_PIPE1_SWITCHED_GEN = 186 +PERF_ENGG_CSB_MACHINE_IS_STARVED = 188 +PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 189 +PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 190 +PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 191 +PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 192 +PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 193 +PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 194 +PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 195 +PERF_ENGG_CSB_NULL_SUBGROUP = 196 +PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 197 +PERF_ENGG_CSB_GE_MEMORY_FULL = 198 +PERF_ENGG_CSB_GE_MEMORY_EMPTY = 199 +PERF_ENGG_CSB_SPI_MEMORY_FULL = 200 +PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 201 +PERF_ENGG_CSB_DELAY_BIN00 = 202 +PERF_ENGG_CSB_DELAY_BIN01 = 203 +PERF_ENGG_CSB_DELAY_BIN02 = 204 +PERF_ENGG_CSB_DELAY_BIN03 = 205 +PERF_ENGG_CSB_DELAY_BIN04 = 206 +PERF_ENGG_CSB_DELAY_BIN05 = 207 +PERF_ENGG_CSB_DELAY_BIN06 = 208 +PERF_ENGG_CSB_DELAY_BIN07 = 209 +PERF_ENGG_CSB_DELAY_BIN08 = 210 +PERF_ENGG_CSB_DELAY_BIN09 = 211 +PERF_ENGG_CSB_DELAY_BIN10 = 212 +PERF_ENGG_CSB_DELAY_BIN11 = 213 +PERF_ENGG_CSB_DELAY_BIN12 = 214 +PERF_ENGG_CSB_DELAY_BIN13 = 215 +PERF_ENGG_CSB_DELAY_BIN14 = 216 +PERF_ENGG_CSB_DELAY_BIN15 = 217 +PERF_ENGG_CSB_SPI_DELAY_BIN00 = 218 +PERF_ENGG_CSB_SPI_DELAY_BIN01 = 219 +PERF_ENGG_CSB_SPI_DELAY_BIN02 = 220 +PERF_ENGG_CSB_SPI_DELAY_BIN03 = 221 +PERF_ENGG_CSB_SPI_DELAY_BIN04 = 222 +PERF_ENGG_CSB_SPI_DELAY_BIN05 = 223 +PERF_ENGG_CSB_SPI_DELAY_BIN06 = 224 +PERF_ENGG_CSB_SPI_DELAY_BIN07 = 225 +PERF_ENGG_CSB_SPI_DELAY_BIN08 = 226 +PERF_ENGG_CSB_SPI_DELAY_BIN09 = 227 +PERF_ENGG_CSB_SPI_DELAY_BIN10 = 228 +PERF_ENGG_INDEX_REQ_NULL_REQUEST = 229 +PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 230 +PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 231 +PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 232 +PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 233 +PERF_ENGG_INDEX_REQ_STARVED = 234 +PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 235 +PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 236 +PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 237 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 238 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 239 +PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 240 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 241 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 242 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 243 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 244 +PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 245 +PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 246 +PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 247 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 248 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 249 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 250 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 251 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 252 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 253 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 254 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 255 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 256 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 257 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 258 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 259 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 260 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 261 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 262 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 263 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 264 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 265 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 266 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 267 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 268 +PERF_ENGG_POS_REQ_STARVED = 269 +PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 270 +PERF_ENGG_BUSY = 271 +PERF_CLIPSM_CULL_PRIMS_CNT = 272 +PERF_PH_SEND_1_SC = 273 +PERF_PH_SEND_2_SC = 274 +PERF_PH_SEND_3_SC = 275 +PERF_PH_SEND_4_SC = 276 +PERF_OUTPUT_PRIM_1_SC = 277 +PERF_OUTPUT_PRIM_2_SC = 278 +PERF_OUTPUT_PRIM_3_SC = 279 +PERF_OUTPUT_PRIM_4_SC = 280 +SU_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PH_PERFCNT_SEL' +PH_PERFCNT_SEL__enumvalues = { + 0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 8: 'PH_PERF_SEL_SC0_ARB_BUSY', + 9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 16: 'PH_PERF_SEL_SC0_SEND', + 17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', + 27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', + 28: 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE', + 30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 31: 'PH_PERF_SEL_SC0_PA0_LPOV_WE', + 32: 'PH_PERF_SEL_SC0_PA0_EOP_WE', + 33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE', + 35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', + 36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', + 39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', + 40: 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE', + 42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 43: 'PH_PERF_SEL_SC0_PA1_LPOV_WE', + 44: 'PH_PERF_SEL_SC0_PA1_EOP_WE', + 45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE', + 47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', + 48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', + 51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', + 52: 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE', + 54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 55: 'PH_PERF_SEL_SC0_PA2_LPOV_WE', + 56: 'PH_PERF_SEL_SC0_PA2_EOP_WE', + 57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE', + 59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', + 60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', + 63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', + 64: 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE', + 66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 67: 'PH_PERF_SEL_SC0_PA3_LPOV_WE', + 68: 'PH_PERF_SEL_SC0_PA3_EOP_WE', + 69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE', + 71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', + 72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', + 75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', + 76: 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE', + 78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 79: 'PH_PERF_SEL_SC0_PA4_LPOV_WE', + 80: 'PH_PERF_SEL_SC0_PA4_EOP_WE', + 81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE', + 83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', + 84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', + 87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', + 88: 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE', + 90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 91: 'PH_PERF_SEL_SC0_PA5_LPOV_WE', + 92: 'PH_PERF_SEL_SC0_PA5_EOP_WE', + 93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE', + 95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', + 96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', + 99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', + 100: 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE', + 102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 103: 'PH_PERF_SEL_SC0_PA6_LPOV_WE', + 104: 'PH_PERF_SEL_SC0_PA6_EOP_WE', + 105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE', + 107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', + 108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', + 111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', + 112: 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE', + 114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 115: 'PH_PERF_SEL_SC0_PA7_LPOV_WE', + 116: 'PH_PERF_SEL_SC0_PA7_EOP_WE', + 117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE', + 119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', + 120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 128: 'PH_PERF_SEL_SC1_ARB_BUSY', + 129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 136: 'PH_PERF_SEL_SC1_SEND', + 137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', + 147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', + 148: 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE', + 150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 151: 'PH_PERF_SEL_SC1_PA0_LPOV_WE', + 152: 'PH_PERF_SEL_SC1_PA0_EOP_WE', + 153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE', + 155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', + 156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', + 159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', + 160: 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE', + 162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 163: 'PH_PERF_SEL_SC1_PA1_LPOV_WE', + 164: 'PH_PERF_SEL_SC1_PA1_EOP_WE', + 165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE', + 167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', + 168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', + 171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', + 172: 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE', + 174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 175: 'PH_PERF_SEL_SC1_PA2_LPOV_WE', + 176: 'PH_PERF_SEL_SC1_PA2_EOP_WE', + 177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE', + 179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', + 180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', + 183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', + 184: 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE', + 186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 187: 'PH_PERF_SEL_SC1_PA3_LPOV_WE', + 188: 'PH_PERF_SEL_SC1_PA3_EOP_WE', + 189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE', + 191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', + 192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', + 195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', + 196: 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE', + 198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 199: 'PH_PERF_SEL_SC1_PA4_LPOV_WE', + 200: 'PH_PERF_SEL_SC1_PA4_EOP_WE', + 201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE', + 203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', + 204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', + 207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', + 208: 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE', + 210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 211: 'PH_PERF_SEL_SC1_PA5_LPOV_WE', + 212: 'PH_PERF_SEL_SC1_PA5_EOP_WE', + 213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE', + 215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', + 216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', + 219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', + 220: 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE', + 222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 223: 'PH_PERF_SEL_SC1_PA6_LPOV_WE', + 224: 'PH_PERF_SEL_SC1_PA6_EOP_WE', + 225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE', + 227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', + 228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', + 231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', + 232: 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE', + 234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 235: 'PH_PERF_SEL_SC1_PA7_LPOV_WE', + 236: 'PH_PERF_SEL_SC1_PA7_EOP_WE', + 237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE', + 239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', + 240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 248: 'PH_PERF_SEL_SC2_ARB_BUSY', + 249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 256: 'PH_PERF_SEL_SC2_SEND', + 257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', + 267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', + 268: 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE', + 270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 271: 'PH_PERF_SEL_SC2_PA0_LPOV_WE', + 272: 'PH_PERF_SEL_SC2_PA0_EOP_WE', + 273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE', + 275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', + 276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', + 279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', + 280: 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE', + 282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 283: 'PH_PERF_SEL_SC2_PA1_LPOV_WE', + 284: 'PH_PERF_SEL_SC2_PA1_EOP_WE', + 285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE', + 287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', + 288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', + 291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', + 292: 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE', + 294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 295: 'PH_PERF_SEL_SC2_PA2_LPOV_WE', + 296: 'PH_PERF_SEL_SC2_PA2_EOP_WE', + 297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE', + 299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', + 300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', + 303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', + 304: 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE', + 306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 307: 'PH_PERF_SEL_SC2_PA3_LPOV_WE', + 308: 'PH_PERF_SEL_SC2_PA3_EOP_WE', + 309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE', + 311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', + 312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', + 315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', + 316: 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE', + 318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 319: 'PH_PERF_SEL_SC2_PA4_LPOV_WE', + 320: 'PH_PERF_SEL_SC2_PA4_EOP_WE', + 321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE', + 323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', + 324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', + 327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', + 328: 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE', + 330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 331: 'PH_PERF_SEL_SC2_PA5_LPOV_WE', + 332: 'PH_PERF_SEL_SC2_PA5_EOP_WE', + 333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE', + 335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', + 336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', + 339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', + 340: 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE', + 342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 343: 'PH_PERF_SEL_SC2_PA6_LPOV_WE', + 344: 'PH_PERF_SEL_SC2_PA6_EOP_WE', + 345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE', + 347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', + 348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', + 351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', + 352: 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE', + 354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 355: 'PH_PERF_SEL_SC2_PA7_LPOV_WE', + 356: 'PH_PERF_SEL_SC2_PA7_EOP_WE', + 357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE', + 359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', + 360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 368: 'PH_PERF_SEL_SC3_ARB_BUSY', + 369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 376: 'PH_PERF_SEL_SC3_SEND', + 377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', + 387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', + 388: 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE', + 390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 391: 'PH_PERF_SEL_SC3_PA0_LPOV_WE', + 392: 'PH_PERF_SEL_SC3_PA0_EOP_WE', + 393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE', + 395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', + 396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', + 399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', + 400: 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE', + 402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 403: 'PH_PERF_SEL_SC3_PA1_LPOV_WE', + 404: 'PH_PERF_SEL_SC3_PA1_EOP_WE', + 405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE', + 407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', + 408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', + 411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', + 412: 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE', + 414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 415: 'PH_PERF_SEL_SC3_PA2_LPOV_WE', + 416: 'PH_PERF_SEL_SC3_PA2_EOP_WE', + 417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE', + 419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', + 420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', + 423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', + 424: 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE', + 426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 427: 'PH_PERF_SEL_SC3_PA3_LPOV_WE', + 428: 'PH_PERF_SEL_SC3_PA3_EOP_WE', + 429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE', + 431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', + 432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', + 435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', + 436: 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE', + 438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 439: 'PH_PERF_SEL_SC3_PA4_LPOV_WE', + 440: 'PH_PERF_SEL_SC3_PA4_EOP_WE', + 441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE', + 443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', + 444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', + 447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', + 448: 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE', + 450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 451: 'PH_PERF_SEL_SC3_PA5_LPOV_WE', + 452: 'PH_PERF_SEL_SC3_PA5_EOP_WE', + 453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE', + 455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', + 456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', + 459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', + 460: 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE', + 462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 463: 'PH_PERF_SEL_SC3_PA6_LPOV_WE', + 464: 'PH_PERF_SEL_SC3_PA6_EOP_WE', + 465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE', + 467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', + 468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', + 471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', + 472: 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE', + 474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 475: 'PH_PERF_SEL_SC3_PA7_LPOV_WE', + 476: 'PH_PERF_SEL_SC3_PA7_EOP_WE', + 477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE', + 479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', + 480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 488: 'PH_PERF_SEL_SC4_ARB_BUSY', + 489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 496: 'PH_PERF_SEL_SC4_SEND', + 497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', + 507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', + 508: 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE', + 510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 511: 'PH_PERF_SEL_SC4_PA0_LPOV_WE', + 512: 'PH_PERF_SEL_SC4_PA0_EOP_WE', + 513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE', + 515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', + 516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', + 519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', + 520: 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE', + 522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 523: 'PH_PERF_SEL_SC4_PA1_LPOV_WE', + 524: 'PH_PERF_SEL_SC4_PA1_EOP_WE', + 525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE', + 527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', + 528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', + 531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', + 532: 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE', + 534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 535: 'PH_PERF_SEL_SC4_PA2_LPOV_WE', + 536: 'PH_PERF_SEL_SC4_PA2_EOP_WE', + 537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE', + 539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', + 540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', + 543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', + 544: 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE', + 546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 547: 'PH_PERF_SEL_SC4_PA3_LPOV_WE', + 548: 'PH_PERF_SEL_SC4_PA3_EOP_WE', + 549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE', + 551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', + 552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', + 555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', + 556: 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE', + 558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 559: 'PH_PERF_SEL_SC4_PA4_LPOV_WE', + 560: 'PH_PERF_SEL_SC4_PA4_EOP_WE', + 561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE', + 563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', + 564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', + 567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', + 568: 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE', + 570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 571: 'PH_PERF_SEL_SC4_PA5_LPOV_WE', + 572: 'PH_PERF_SEL_SC4_PA5_EOP_WE', + 573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE', + 575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', + 576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', + 579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', + 580: 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE', + 582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 583: 'PH_PERF_SEL_SC4_PA6_LPOV_WE', + 584: 'PH_PERF_SEL_SC4_PA6_EOP_WE', + 585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE', + 587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', + 588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', + 591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', + 592: 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE', + 594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 595: 'PH_PERF_SEL_SC4_PA7_LPOV_WE', + 596: 'PH_PERF_SEL_SC4_PA7_EOP_WE', + 597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE', + 599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', + 600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 608: 'PH_PERF_SEL_SC5_ARB_BUSY', + 609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 616: 'PH_PERF_SEL_SC5_SEND', + 617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', + 627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', + 628: 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE', + 630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 631: 'PH_PERF_SEL_SC5_PA0_LPOV_WE', + 632: 'PH_PERF_SEL_SC5_PA0_EOP_WE', + 633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE', + 635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', + 636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', + 639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', + 640: 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE', + 642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 643: 'PH_PERF_SEL_SC5_PA1_LPOV_WE', + 644: 'PH_PERF_SEL_SC5_PA1_EOP_WE', + 645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE', + 647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', + 648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', + 651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', + 652: 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE', + 654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 655: 'PH_PERF_SEL_SC5_PA2_LPOV_WE', + 656: 'PH_PERF_SEL_SC5_PA2_EOP_WE', + 657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE', + 659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', + 660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', + 663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', + 664: 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE', + 666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 667: 'PH_PERF_SEL_SC5_PA3_LPOV_WE', + 668: 'PH_PERF_SEL_SC5_PA3_EOP_WE', + 669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE', + 671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', + 672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', + 675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', + 676: 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE', + 678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 679: 'PH_PERF_SEL_SC5_PA4_LPOV_WE', + 680: 'PH_PERF_SEL_SC5_PA4_EOP_WE', + 681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE', + 683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', + 684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', + 687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', + 688: 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE', + 690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 691: 'PH_PERF_SEL_SC5_PA5_LPOV_WE', + 692: 'PH_PERF_SEL_SC5_PA5_EOP_WE', + 693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE', + 695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', + 696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', + 699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', + 700: 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE', + 702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 703: 'PH_PERF_SEL_SC5_PA6_LPOV_WE', + 704: 'PH_PERF_SEL_SC5_PA6_EOP_WE', + 705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE', + 707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', + 708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', + 711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', + 712: 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE', + 714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 715: 'PH_PERF_SEL_SC5_PA7_LPOV_WE', + 716: 'PH_PERF_SEL_SC5_PA7_EOP_WE', + 717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE', + 719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', + 720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 728: 'PH_PERF_SEL_SC6_ARB_BUSY', + 729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 736: 'PH_PERF_SEL_SC6_SEND', + 737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', + 747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', + 748: 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE', + 750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 751: 'PH_PERF_SEL_SC6_PA0_LPOV_WE', + 752: 'PH_PERF_SEL_SC6_PA0_EOP_WE', + 753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE', + 755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', + 756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', + 759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', + 760: 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE', + 762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 763: 'PH_PERF_SEL_SC6_PA1_LPOV_WE', + 764: 'PH_PERF_SEL_SC6_PA1_EOP_WE', + 765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE', + 767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', + 768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', + 771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', + 772: 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE', + 774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 775: 'PH_PERF_SEL_SC6_PA2_LPOV_WE', + 776: 'PH_PERF_SEL_SC6_PA2_EOP_WE', + 777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE', + 779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', + 780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', + 783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', + 784: 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE', + 786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 787: 'PH_PERF_SEL_SC6_PA3_LPOV_WE', + 788: 'PH_PERF_SEL_SC6_PA3_EOP_WE', + 789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE', + 791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', + 792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', + 795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', + 796: 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE', + 798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 799: 'PH_PERF_SEL_SC6_PA4_LPOV_WE', + 800: 'PH_PERF_SEL_SC6_PA4_EOP_WE', + 801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE', + 803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', + 804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', + 807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', + 808: 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE', + 810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 811: 'PH_PERF_SEL_SC6_PA5_LPOV_WE', + 812: 'PH_PERF_SEL_SC6_PA5_EOP_WE', + 813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE', + 815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', + 816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', + 819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', + 820: 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE', + 822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 823: 'PH_PERF_SEL_SC6_PA6_LPOV_WE', + 824: 'PH_PERF_SEL_SC6_PA6_EOP_WE', + 825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE', + 827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', + 828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', + 831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', + 832: 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE', + 834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 835: 'PH_PERF_SEL_SC6_PA7_LPOV_WE', + 836: 'PH_PERF_SEL_SC6_PA7_EOP_WE', + 837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE', + 839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', + 840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 848: 'PH_PERF_SEL_SC7_ARB_BUSY', + 849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 856: 'PH_PERF_SEL_SC7_SEND', + 857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', + 867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', + 868: 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE', + 870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 871: 'PH_PERF_SEL_SC7_PA0_LPOV_WE', + 872: 'PH_PERF_SEL_SC7_PA0_EOP_WE', + 873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE', + 875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', + 876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', + 879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', + 880: 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE', + 882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 883: 'PH_PERF_SEL_SC7_PA1_LPOV_WE', + 884: 'PH_PERF_SEL_SC7_PA1_EOP_WE', + 885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE', + 887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', + 888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', + 891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', + 892: 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE', + 894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 895: 'PH_PERF_SEL_SC7_PA2_LPOV_WE', + 896: 'PH_PERF_SEL_SC7_PA2_EOP_WE', + 897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE', + 899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', + 900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', + 903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', + 904: 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE', + 906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 907: 'PH_PERF_SEL_SC7_PA3_LPOV_WE', + 908: 'PH_PERF_SEL_SC7_PA3_EOP_WE', + 909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE', + 911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', + 912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', + 915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', + 916: 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE', + 918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 919: 'PH_PERF_SEL_SC7_PA4_LPOV_WE', + 920: 'PH_PERF_SEL_SC7_PA4_EOP_WE', + 921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE', + 923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', + 924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', + 927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', + 928: 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE', + 930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 931: 'PH_PERF_SEL_SC7_PA5_LPOV_WE', + 932: 'PH_PERF_SEL_SC7_PA5_EOP_WE', + 933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE', + 935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', + 936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', + 939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', + 940: 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE', + 942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 943: 'PH_PERF_SEL_SC7_PA6_LPOV_WE', + 944: 'PH_PERF_SEL_SC7_PA6_EOP_WE', + 945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE', + 947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', + 948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', + 951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', + 952: 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE', + 954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 955: 'PH_PERF_SEL_SC7_PA7_LPOV_WE', + 956: 'PH_PERF_SEL_SC7_PA7_EOP_WE', + 957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE', + 959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', + 960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 992: 'PH_PERF_SC0_FIFO_STATUS_0', + 993: 'PH_PERF_SC0_FIFO_STATUS_1', + 994: 'PH_PERF_SC0_FIFO_STATUS_2', + 995: 'PH_PERF_SC0_FIFO_STATUS_3', + 996: 'PH_PERF_SC1_FIFO_STATUS_0', + 997: 'PH_PERF_SC1_FIFO_STATUS_1', + 998: 'PH_PERF_SC1_FIFO_STATUS_2', + 999: 'PH_PERF_SC1_FIFO_STATUS_3', + 1000: 'PH_PERF_SC2_FIFO_STATUS_0', + 1001: 'PH_PERF_SC2_FIFO_STATUS_1', + 1002: 'PH_PERF_SC2_FIFO_STATUS_2', + 1003: 'PH_PERF_SC2_FIFO_STATUS_3', + 1004: 'PH_PERF_SC3_FIFO_STATUS_0', + 1005: 'PH_PERF_SC3_FIFO_STATUS_1', + 1006: 'PH_PERF_SC3_FIFO_STATUS_2', + 1007: 'PH_PERF_SC3_FIFO_STATUS_3', + 1008: 'PH_PERF_SC4_FIFO_STATUS_0', + 1009: 'PH_PERF_SC4_FIFO_STATUS_1', + 1010: 'PH_PERF_SC4_FIFO_STATUS_2', + 1011: 'PH_PERF_SC4_FIFO_STATUS_3', + 1012: 'PH_PERF_SC5_FIFO_STATUS_0', + 1013: 'PH_PERF_SC5_FIFO_STATUS_1', + 1014: 'PH_PERF_SC5_FIFO_STATUS_2', + 1015: 'PH_PERF_SC5_FIFO_STATUS_3', + 1016: 'PH_PERF_SC6_FIFO_STATUS_0', + 1017: 'PH_PERF_SC6_FIFO_STATUS_1', + 1018: 'PH_PERF_SC6_FIFO_STATUS_2', + 1019: 'PH_PERF_SC6_FIFO_STATUS_3', + 1020: 'PH_PERF_SC7_FIFO_STATUS_0', + 1021: 'PH_PERF_SC7_FIFO_STATUS_1', + 1022: 'PH_PERF_SC7_FIFO_STATUS_2', + 1023: 'PH_PERF_SC7_FIFO_STATUS_3', +} +PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0 +PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 +PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 +PH_PERF_SEL_SC0_ARB_BUSY = 8 +PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9 +PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10 +PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11 +PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 +PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13 +PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 +PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15 +PH_PERF_SEL_SC0_SEND = 16 +PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 +PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18 +PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 +PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20 +PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21 +PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22 +PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25 +PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26 +PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27 +PH_PERF_SEL_SC0_PA0_NULL_WE = 28 +PH_PERF_SEL_SC0_PA0_EVENT_WE = 29 +PH_PERF_SEL_SC0_PA0_FPOV_WE = 30 +PH_PERF_SEL_SC0_PA0_LPOV_WE = 31 +PH_PERF_SEL_SC0_PA0_EOP_WE = 32 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33 +PH_PERF_SEL_SC0_PA0_EOPG_WE = 34 +PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 35 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37 +PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38 +PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39 +PH_PERF_SEL_SC0_PA1_NULL_WE = 40 +PH_PERF_SEL_SC0_PA1_EVENT_WE = 41 +PH_PERF_SEL_SC0_PA1_FPOV_WE = 42 +PH_PERF_SEL_SC0_PA1_LPOV_WE = 43 +PH_PERF_SEL_SC0_PA1_EOP_WE = 44 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45 +PH_PERF_SEL_SC0_PA1_EOPG_WE = 46 +PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 47 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49 +PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50 +PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51 +PH_PERF_SEL_SC0_PA2_NULL_WE = 52 +PH_PERF_SEL_SC0_PA2_EVENT_WE = 53 +PH_PERF_SEL_SC0_PA2_FPOV_WE = 54 +PH_PERF_SEL_SC0_PA2_LPOV_WE = 55 +PH_PERF_SEL_SC0_PA2_EOP_WE = 56 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57 +PH_PERF_SEL_SC0_PA2_EOPG_WE = 58 +PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 59 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61 +PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62 +PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63 +PH_PERF_SEL_SC0_PA3_NULL_WE = 64 +PH_PERF_SEL_SC0_PA3_EVENT_WE = 65 +PH_PERF_SEL_SC0_PA3_FPOV_WE = 66 +PH_PERF_SEL_SC0_PA3_LPOV_WE = 67 +PH_PERF_SEL_SC0_PA3_EOP_WE = 68 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69 +PH_PERF_SEL_SC0_PA3_EOPG_WE = 70 +PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 71 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73 +PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74 +PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75 +PH_PERF_SEL_SC0_PA4_NULL_WE = 76 +PH_PERF_SEL_SC0_PA4_EVENT_WE = 77 +PH_PERF_SEL_SC0_PA4_FPOV_WE = 78 +PH_PERF_SEL_SC0_PA4_LPOV_WE = 79 +PH_PERF_SEL_SC0_PA4_EOP_WE = 80 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81 +PH_PERF_SEL_SC0_PA4_EOPG_WE = 82 +PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 83 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85 +PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86 +PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87 +PH_PERF_SEL_SC0_PA5_NULL_WE = 88 +PH_PERF_SEL_SC0_PA5_EVENT_WE = 89 +PH_PERF_SEL_SC0_PA5_FPOV_WE = 90 +PH_PERF_SEL_SC0_PA5_LPOV_WE = 91 +PH_PERF_SEL_SC0_PA5_EOP_WE = 92 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93 +PH_PERF_SEL_SC0_PA5_EOPG_WE = 94 +PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 95 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97 +PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98 +PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99 +PH_PERF_SEL_SC0_PA6_NULL_WE = 100 +PH_PERF_SEL_SC0_PA6_EVENT_WE = 101 +PH_PERF_SEL_SC0_PA6_FPOV_WE = 102 +PH_PERF_SEL_SC0_PA6_LPOV_WE = 103 +PH_PERF_SEL_SC0_PA6_EOP_WE = 104 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105 +PH_PERF_SEL_SC0_PA6_EOPG_WE = 106 +PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 107 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109 +PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110 +PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111 +PH_PERF_SEL_SC0_PA7_NULL_WE = 112 +PH_PERF_SEL_SC0_PA7_EVENT_WE = 113 +PH_PERF_SEL_SC0_PA7_FPOV_WE = 114 +PH_PERF_SEL_SC0_PA7_LPOV_WE = 115 +PH_PERF_SEL_SC0_PA7_EOP_WE = 116 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117 +PH_PERF_SEL_SC0_PA7_EOPG_WE = 118 +PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 119 +PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120 +PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 +PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 +PH_PERF_SEL_SC1_ARB_BUSY = 128 +PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129 +PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130 +PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131 +PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 +PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133 +PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 +PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135 +PH_PERF_SEL_SC1_SEND = 136 +PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 +PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138 +PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 +PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140 +PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141 +PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142 +PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145 +PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146 +PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147 +PH_PERF_SEL_SC1_PA0_NULL_WE = 148 +PH_PERF_SEL_SC1_PA0_EVENT_WE = 149 +PH_PERF_SEL_SC1_PA0_FPOV_WE = 150 +PH_PERF_SEL_SC1_PA0_LPOV_WE = 151 +PH_PERF_SEL_SC1_PA0_EOP_WE = 152 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153 +PH_PERF_SEL_SC1_PA0_EOPG_WE = 154 +PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 155 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157 +PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158 +PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159 +PH_PERF_SEL_SC1_PA1_NULL_WE = 160 +PH_PERF_SEL_SC1_PA1_EVENT_WE = 161 +PH_PERF_SEL_SC1_PA1_FPOV_WE = 162 +PH_PERF_SEL_SC1_PA1_LPOV_WE = 163 +PH_PERF_SEL_SC1_PA1_EOP_WE = 164 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165 +PH_PERF_SEL_SC1_PA1_EOPG_WE = 166 +PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 167 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169 +PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170 +PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171 +PH_PERF_SEL_SC1_PA2_NULL_WE = 172 +PH_PERF_SEL_SC1_PA2_EVENT_WE = 173 +PH_PERF_SEL_SC1_PA2_FPOV_WE = 174 +PH_PERF_SEL_SC1_PA2_LPOV_WE = 175 +PH_PERF_SEL_SC1_PA2_EOP_WE = 176 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177 +PH_PERF_SEL_SC1_PA2_EOPG_WE = 178 +PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 179 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181 +PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182 +PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183 +PH_PERF_SEL_SC1_PA3_NULL_WE = 184 +PH_PERF_SEL_SC1_PA3_EVENT_WE = 185 +PH_PERF_SEL_SC1_PA3_FPOV_WE = 186 +PH_PERF_SEL_SC1_PA3_LPOV_WE = 187 +PH_PERF_SEL_SC1_PA3_EOP_WE = 188 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189 +PH_PERF_SEL_SC1_PA3_EOPG_WE = 190 +PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 191 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193 +PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194 +PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195 +PH_PERF_SEL_SC1_PA4_NULL_WE = 196 +PH_PERF_SEL_SC1_PA4_EVENT_WE = 197 +PH_PERF_SEL_SC1_PA4_FPOV_WE = 198 +PH_PERF_SEL_SC1_PA4_LPOV_WE = 199 +PH_PERF_SEL_SC1_PA4_EOP_WE = 200 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201 +PH_PERF_SEL_SC1_PA4_EOPG_WE = 202 +PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 203 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205 +PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206 +PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207 +PH_PERF_SEL_SC1_PA5_NULL_WE = 208 +PH_PERF_SEL_SC1_PA5_EVENT_WE = 209 +PH_PERF_SEL_SC1_PA5_FPOV_WE = 210 +PH_PERF_SEL_SC1_PA5_LPOV_WE = 211 +PH_PERF_SEL_SC1_PA5_EOP_WE = 212 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213 +PH_PERF_SEL_SC1_PA5_EOPG_WE = 214 +PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 215 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217 +PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218 +PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219 +PH_PERF_SEL_SC1_PA6_NULL_WE = 220 +PH_PERF_SEL_SC1_PA6_EVENT_WE = 221 +PH_PERF_SEL_SC1_PA6_FPOV_WE = 222 +PH_PERF_SEL_SC1_PA6_LPOV_WE = 223 +PH_PERF_SEL_SC1_PA6_EOP_WE = 224 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225 +PH_PERF_SEL_SC1_PA6_EOPG_WE = 226 +PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 227 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229 +PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230 +PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231 +PH_PERF_SEL_SC1_PA7_NULL_WE = 232 +PH_PERF_SEL_SC1_PA7_EVENT_WE = 233 +PH_PERF_SEL_SC1_PA7_FPOV_WE = 234 +PH_PERF_SEL_SC1_PA7_LPOV_WE = 235 +PH_PERF_SEL_SC1_PA7_EOP_WE = 236 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237 +PH_PERF_SEL_SC1_PA7_EOPG_WE = 238 +PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 239 +PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240 +PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 +PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 +PH_PERF_SEL_SC2_ARB_BUSY = 248 +PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249 +PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250 +PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251 +PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 +PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253 +PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 +PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255 +PH_PERF_SEL_SC2_SEND = 256 +PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 +PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258 +PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 +PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260 +PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261 +PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262 +PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265 +PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266 +PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267 +PH_PERF_SEL_SC2_PA0_NULL_WE = 268 +PH_PERF_SEL_SC2_PA0_EVENT_WE = 269 +PH_PERF_SEL_SC2_PA0_FPOV_WE = 270 +PH_PERF_SEL_SC2_PA0_LPOV_WE = 271 +PH_PERF_SEL_SC2_PA0_EOP_WE = 272 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273 +PH_PERF_SEL_SC2_PA0_EOPG_WE = 274 +PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 275 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277 +PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278 +PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279 +PH_PERF_SEL_SC2_PA1_NULL_WE = 280 +PH_PERF_SEL_SC2_PA1_EVENT_WE = 281 +PH_PERF_SEL_SC2_PA1_FPOV_WE = 282 +PH_PERF_SEL_SC2_PA1_LPOV_WE = 283 +PH_PERF_SEL_SC2_PA1_EOP_WE = 284 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285 +PH_PERF_SEL_SC2_PA1_EOPG_WE = 286 +PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 287 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289 +PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290 +PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291 +PH_PERF_SEL_SC2_PA2_NULL_WE = 292 +PH_PERF_SEL_SC2_PA2_EVENT_WE = 293 +PH_PERF_SEL_SC2_PA2_FPOV_WE = 294 +PH_PERF_SEL_SC2_PA2_LPOV_WE = 295 +PH_PERF_SEL_SC2_PA2_EOP_WE = 296 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297 +PH_PERF_SEL_SC2_PA2_EOPG_WE = 298 +PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 299 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301 +PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302 +PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303 +PH_PERF_SEL_SC2_PA3_NULL_WE = 304 +PH_PERF_SEL_SC2_PA3_EVENT_WE = 305 +PH_PERF_SEL_SC2_PA3_FPOV_WE = 306 +PH_PERF_SEL_SC2_PA3_LPOV_WE = 307 +PH_PERF_SEL_SC2_PA3_EOP_WE = 308 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309 +PH_PERF_SEL_SC2_PA3_EOPG_WE = 310 +PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 311 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313 +PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314 +PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315 +PH_PERF_SEL_SC2_PA4_NULL_WE = 316 +PH_PERF_SEL_SC2_PA4_EVENT_WE = 317 +PH_PERF_SEL_SC2_PA4_FPOV_WE = 318 +PH_PERF_SEL_SC2_PA4_LPOV_WE = 319 +PH_PERF_SEL_SC2_PA4_EOP_WE = 320 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321 +PH_PERF_SEL_SC2_PA4_EOPG_WE = 322 +PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 323 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325 +PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326 +PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327 +PH_PERF_SEL_SC2_PA5_NULL_WE = 328 +PH_PERF_SEL_SC2_PA5_EVENT_WE = 329 +PH_PERF_SEL_SC2_PA5_FPOV_WE = 330 +PH_PERF_SEL_SC2_PA5_LPOV_WE = 331 +PH_PERF_SEL_SC2_PA5_EOP_WE = 332 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333 +PH_PERF_SEL_SC2_PA5_EOPG_WE = 334 +PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 335 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337 +PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338 +PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339 +PH_PERF_SEL_SC2_PA6_NULL_WE = 340 +PH_PERF_SEL_SC2_PA6_EVENT_WE = 341 +PH_PERF_SEL_SC2_PA6_FPOV_WE = 342 +PH_PERF_SEL_SC2_PA6_LPOV_WE = 343 +PH_PERF_SEL_SC2_PA6_EOP_WE = 344 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345 +PH_PERF_SEL_SC2_PA6_EOPG_WE = 346 +PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 347 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349 +PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350 +PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351 +PH_PERF_SEL_SC2_PA7_NULL_WE = 352 +PH_PERF_SEL_SC2_PA7_EVENT_WE = 353 +PH_PERF_SEL_SC2_PA7_FPOV_WE = 354 +PH_PERF_SEL_SC2_PA7_LPOV_WE = 355 +PH_PERF_SEL_SC2_PA7_EOP_WE = 356 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357 +PH_PERF_SEL_SC2_PA7_EOPG_WE = 358 +PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 359 +PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360 +PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 +PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 +PH_PERF_SEL_SC3_ARB_BUSY = 368 +PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369 +PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370 +PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371 +PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 +PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373 +PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 +PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375 +PH_PERF_SEL_SC3_SEND = 376 +PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 +PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378 +PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 +PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380 +PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381 +PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382 +PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385 +PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386 +PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387 +PH_PERF_SEL_SC3_PA0_NULL_WE = 388 +PH_PERF_SEL_SC3_PA0_EVENT_WE = 389 +PH_PERF_SEL_SC3_PA0_FPOV_WE = 390 +PH_PERF_SEL_SC3_PA0_LPOV_WE = 391 +PH_PERF_SEL_SC3_PA0_EOP_WE = 392 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393 +PH_PERF_SEL_SC3_PA0_EOPG_WE = 394 +PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 395 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397 +PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398 +PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399 +PH_PERF_SEL_SC3_PA1_NULL_WE = 400 +PH_PERF_SEL_SC3_PA1_EVENT_WE = 401 +PH_PERF_SEL_SC3_PA1_FPOV_WE = 402 +PH_PERF_SEL_SC3_PA1_LPOV_WE = 403 +PH_PERF_SEL_SC3_PA1_EOP_WE = 404 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405 +PH_PERF_SEL_SC3_PA1_EOPG_WE = 406 +PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 407 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409 +PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410 +PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411 +PH_PERF_SEL_SC3_PA2_NULL_WE = 412 +PH_PERF_SEL_SC3_PA2_EVENT_WE = 413 +PH_PERF_SEL_SC3_PA2_FPOV_WE = 414 +PH_PERF_SEL_SC3_PA2_LPOV_WE = 415 +PH_PERF_SEL_SC3_PA2_EOP_WE = 416 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417 +PH_PERF_SEL_SC3_PA2_EOPG_WE = 418 +PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 419 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421 +PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422 +PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423 +PH_PERF_SEL_SC3_PA3_NULL_WE = 424 +PH_PERF_SEL_SC3_PA3_EVENT_WE = 425 +PH_PERF_SEL_SC3_PA3_FPOV_WE = 426 +PH_PERF_SEL_SC3_PA3_LPOV_WE = 427 +PH_PERF_SEL_SC3_PA3_EOP_WE = 428 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429 +PH_PERF_SEL_SC3_PA3_EOPG_WE = 430 +PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 431 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433 +PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434 +PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435 +PH_PERF_SEL_SC3_PA4_NULL_WE = 436 +PH_PERF_SEL_SC3_PA4_EVENT_WE = 437 +PH_PERF_SEL_SC3_PA4_FPOV_WE = 438 +PH_PERF_SEL_SC3_PA4_LPOV_WE = 439 +PH_PERF_SEL_SC3_PA4_EOP_WE = 440 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441 +PH_PERF_SEL_SC3_PA4_EOPG_WE = 442 +PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 443 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445 +PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446 +PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447 +PH_PERF_SEL_SC3_PA5_NULL_WE = 448 +PH_PERF_SEL_SC3_PA5_EVENT_WE = 449 +PH_PERF_SEL_SC3_PA5_FPOV_WE = 450 +PH_PERF_SEL_SC3_PA5_LPOV_WE = 451 +PH_PERF_SEL_SC3_PA5_EOP_WE = 452 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453 +PH_PERF_SEL_SC3_PA5_EOPG_WE = 454 +PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 455 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457 +PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458 +PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459 +PH_PERF_SEL_SC3_PA6_NULL_WE = 460 +PH_PERF_SEL_SC3_PA6_EVENT_WE = 461 +PH_PERF_SEL_SC3_PA6_FPOV_WE = 462 +PH_PERF_SEL_SC3_PA6_LPOV_WE = 463 +PH_PERF_SEL_SC3_PA6_EOP_WE = 464 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465 +PH_PERF_SEL_SC3_PA6_EOPG_WE = 466 +PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 467 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469 +PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470 +PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471 +PH_PERF_SEL_SC3_PA7_NULL_WE = 472 +PH_PERF_SEL_SC3_PA7_EVENT_WE = 473 +PH_PERF_SEL_SC3_PA7_FPOV_WE = 474 +PH_PERF_SEL_SC3_PA7_LPOV_WE = 475 +PH_PERF_SEL_SC3_PA7_EOP_WE = 476 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477 +PH_PERF_SEL_SC3_PA7_EOPG_WE = 478 +PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 479 +PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480 +PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 +PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 +PH_PERF_SEL_SC4_ARB_BUSY = 488 +PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489 +PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490 +PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491 +PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 +PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493 +PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 +PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495 +PH_PERF_SEL_SC4_SEND = 496 +PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 +PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498 +PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 +PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500 +PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501 +PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502 +PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505 +PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506 +PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507 +PH_PERF_SEL_SC4_PA0_NULL_WE = 508 +PH_PERF_SEL_SC4_PA0_EVENT_WE = 509 +PH_PERF_SEL_SC4_PA0_FPOV_WE = 510 +PH_PERF_SEL_SC4_PA0_LPOV_WE = 511 +PH_PERF_SEL_SC4_PA0_EOP_WE = 512 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513 +PH_PERF_SEL_SC4_PA0_EOPG_WE = 514 +PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 515 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517 +PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518 +PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519 +PH_PERF_SEL_SC4_PA1_NULL_WE = 520 +PH_PERF_SEL_SC4_PA1_EVENT_WE = 521 +PH_PERF_SEL_SC4_PA1_FPOV_WE = 522 +PH_PERF_SEL_SC4_PA1_LPOV_WE = 523 +PH_PERF_SEL_SC4_PA1_EOP_WE = 524 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525 +PH_PERF_SEL_SC4_PA1_EOPG_WE = 526 +PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 527 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529 +PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530 +PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531 +PH_PERF_SEL_SC4_PA2_NULL_WE = 532 +PH_PERF_SEL_SC4_PA2_EVENT_WE = 533 +PH_PERF_SEL_SC4_PA2_FPOV_WE = 534 +PH_PERF_SEL_SC4_PA2_LPOV_WE = 535 +PH_PERF_SEL_SC4_PA2_EOP_WE = 536 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537 +PH_PERF_SEL_SC4_PA2_EOPG_WE = 538 +PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 539 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541 +PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542 +PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543 +PH_PERF_SEL_SC4_PA3_NULL_WE = 544 +PH_PERF_SEL_SC4_PA3_EVENT_WE = 545 +PH_PERF_SEL_SC4_PA3_FPOV_WE = 546 +PH_PERF_SEL_SC4_PA3_LPOV_WE = 547 +PH_PERF_SEL_SC4_PA3_EOP_WE = 548 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549 +PH_PERF_SEL_SC4_PA3_EOPG_WE = 550 +PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 551 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553 +PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554 +PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555 +PH_PERF_SEL_SC4_PA4_NULL_WE = 556 +PH_PERF_SEL_SC4_PA4_EVENT_WE = 557 +PH_PERF_SEL_SC4_PA4_FPOV_WE = 558 +PH_PERF_SEL_SC4_PA4_LPOV_WE = 559 +PH_PERF_SEL_SC4_PA4_EOP_WE = 560 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561 +PH_PERF_SEL_SC4_PA4_EOPG_WE = 562 +PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 563 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565 +PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566 +PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567 +PH_PERF_SEL_SC4_PA5_NULL_WE = 568 +PH_PERF_SEL_SC4_PA5_EVENT_WE = 569 +PH_PERF_SEL_SC4_PA5_FPOV_WE = 570 +PH_PERF_SEL_SC4_PA5_LPOV_WE = 571 +PH_PERF_SEL_SC4_PA5_EOP_WE = 572 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573 +PH_PERF_SEL_SC4_PA5_EOPG_WE = 574 +PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 575 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577 +PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578 +PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579 +PH_PERF_SEL_SC4_PA6_NULL_WE = 580 +PH_PERF_SEL_SC4_PA6_EVENT_WE = 581 +PH_PERF_SEL_SC4_PA6_FPOV_WE = 582 +PH_PERF_SEL_SC4_PA6_LPOV_WE = 583 +PH_PERF_SEL_SC4_PA6_EOP_WE = 584 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585 +PH_PERF_SEL_SC4_PA6_EOPG_WE = 586 +PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 587 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589 +PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590 +PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591 +PH_PERF_SEL_SC4_PA7_NULL_WE = 592 +PH_PERF_SEL_SC4_PA7_EVENT_WE = 593 +PH_PERF_SEL_SC4_PA7_FPOV_WE = 594 +PH_PERF_SEL_SC4_PA7_LPOV_WE = 595 +PH_PERF_SEL_SC4_PA7_EOP_WE = 596 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597 +PH_PERF_SEL_SC4_PA7_EOPG_WE = 598 +PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 599 +PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600 +PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 +PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 +PH_PERF_SEL_SC5_ARB_BUSY = 608 +PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609 +PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610 +PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611 +PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 +PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613 +PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 +PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615 +PH_PERF_SEL_SC5_SEND = 616 +PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 +PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618 +PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 +PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620 +PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621 +PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622 +PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625 +PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626 +PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627 +PH_PERF_SEL_SC5_PA0_NULL_WE = 628 +PH_PERF_SEL_SC5_PA0_EVENT_WE = 629 +PH_PERF_SEL_SC5_PA0_FPOV_WE = 630 +PH_PERF_SEL_SC5_PA0_LPOV_WE = 631 +PH_PERF_SEL_SC5_PA0_EOP_WE = 632 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633 +PH_PERF_SEL_SC5_PA0_EOPG_WE = 634 +PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 635 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637 +PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638 +PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639 +PH_PERF_SEL_SC5_PA1_NULL_WE = 640 +PH_PERF_SEL_SC5_PA1_EVENT_WE = 641 +PH_PERF_SEL_SC5_PA1_FPOV_WE = 642 +PH_PERF_SEL_SC5_PA1_LPOV_WE = 643 +PH_PERF_SEL_SC5_PA1_EOP_WE = 644 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645 +PH_PERF_SEL_SC5_PA1_EOPG_WE = 646 +PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 647 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649 +PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650 +PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651 +PH_PERF_SEL_SC5_PA2_NULL_WE = 652 +PH_PERF_SEL_SC5_PA2_EVENT_WE = 653 +PH_PERF_SEL_SC5_PA2_FPOV_WE = 654 +PH_PERF_SEL_SC5_PA2_LPOV_WE = 655 +PH_PERF_SEL_SC5_PA2_EOP_WE = 656 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657 +PH_PERF_SEL_SC5_PA2_EOPG_WE = 658 +PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 659 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661 +PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662 +PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663 +PH_PERF_SEL_SC5_PA3_NULL_WE = 664 +PH_PERF_SEL_SC5_PA3_EVENT_WE = 665 +PH_PERF_SEL_SC5_PA3_FPOV_WE = 666 +PH_PERF_SEL_SC5_PA3_LPOV_WE = 667 +PH_PERF_SEL_SC5_PA3_EOP_WE = 668 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669 +PH_PERF_SEL_SC5_PA3_EOPG_WE = 670 +PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 671 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673 +PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674 +PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675 +PH_PERF_SEL_SC5_PA4_NULL_WE = 676 +PH_PERF_SEL_SC5_PA4_EVENT_WE = 677 +PH_PERF_SEL_SC5_PA4_FPOV_WE = 678 +PH_PERF_SEL_SC5_PA4_LPOV_WE = 679 +PH_PERF_SEL_SC5_PA4_EOP_WE = 680 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681 +PH_PERF_SEL_SC5_PA4_EOPG_WE = 682 +PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 683 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685 +PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686 +PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687 +PH_PERF_SEL_SC5_PA5_NULL_WE = 688 +PH_PERF_SEL_SC5_PA5_EVENT_WE = 689 +PH_PERF_SEL_SC5_PA5_FPOV_WE = 690 +PH_PERF_SEL_SC5_PA5_LPOV_WE = 691 +PH_PERF_SEL_SC5_PA5_EOP_WE = 692 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693 +PH_PERF_SEL_SC5_PA5_EOPG_WE = 694 +PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 695 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697 +PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698 +PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699 +PH_PERF_SEL_SC5_PA6_NULL_WE = 700 +PH_PERF_SEL_SC5_PA6_EVENT_WE = 701 +PH_PERF_SEL_SC5_PA6_FPOV_WE = 702 +PH_PERF_SEL_SC5_PA6_LPOV_WE = 703 +PH_PERF_SEL_SC5_PA6_EOP_WE = 704 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705 +PH_PERF_SEL_SC5_PA6_EOPG_WE = 706 +PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 707 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709 +PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710 +PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711 +PH_PERF_SEL_SC5_PA7_NULL_WE = 712 +PH_PERF_SEL_SC5_PA7_EVENT_WE = 713 +PH_PERF_SEL_SC5_PA7_FPOV_WE = 714 +PH_PERF_SEL_SC5_PA7_LPOV_WE = 715 +PH_PERF_SEL_SC5_PA7_EOP_WE = 716 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717 +PH_PERF_SEL_SC5_PA7_EOPG_WE = 718 +PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 719 +PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720 +PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 +PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 +PH_PERF_SEL_SC6_ARB_BUSY = 728 +PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729 +PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730 +PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731 +PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 +PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733 +PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 +PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735 +PH_PERF_SEL_SC6_SEND = 736 +PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 +PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738 +PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 +PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740 +PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741 +PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742 +PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745 +PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746 +PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747 +PH_PERF_SEL_SC6_PA0_NULL_WE = 748 +PH_PERF_SEL_SC6_PA0_EVENT_WE = 749 +PH_PERF_SEL_SC6_PA0_FPOV_WE = 750 +PH_PERF_SEL_SC6_PA0_LPOV_WE = 751 +PH_PERF_SEL_SC6_PA0_EOP_WE = 752 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753 +PH_PERF_SEL_SC6_PA0_EOPG_WE = 754 +PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 755 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757 +PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758 +PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759 +PH_PERF_SEL_SC6_PA1_NULL_WE = 760 +PH_PERF_SEL_SC6_PA1_EVENT_WE = 761 +PH_PERF_SEL_SC6_PA1_FPOV_WE = 762 +PH_PERF_SEL_SC6_PA1_LPOV_WE = 763 +PH_PERF_SEL_SC6_PA1_EOP_WE = 764 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765 +PH_PERF_SEL_SC6_PA1_EOPG_WE = 766 +PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 767 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769 +PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770 +PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771 +PH_PERF_SEL_SC6_PA2_NULL_WE = 772 +PH_PERF_SEL_SC6_PA2_EVENT_WE = 773 +PH_PERF_SEL_SC6_PA2_FPOV_WE = 774 +PH_PERF_SEL_SC6_PA2_LPOV_WE = 775 +PH_PERF_SEL_SC6_PA2_EOP_WE = 776 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777 +PH_PERF_SEL_SC6_PA2_EOPG_WE = 778 +PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 779 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781 +PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782 +PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783 +PH_PERF_SEL_SC6_PA3_NULL_WE = 784 +PH_PERF_SEL_SC6_PA3_EVENT_WE = 785 +PH_PERF_SEL_SC6_PA3_FPOV_WE = 786 +PH_PERF_SEL_SC6_PA3_LPOV_WE = 787 +PH_PERF_SEL_SC6_PA3_EOP_WE = 788 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789 +PH_PERF_SEL_SC6_PA3_EOPG_WE = 790 +PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 791 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793 +PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794 +PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795 +PH_PERF_SEL_SC6_PA4_NULL_WE = 796 +PH_PERF_SEL_SC6_PA4_EVENT_WE = 797 +PH_PERF_SEL_SC6_PA4_FPOV_WE = 798 +PH_PERF_SEL_SC6_PA4_LPOV_WE = 799 +PH_PERF_SEL_SC6_PA4_EOP_WE = 800 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801 +PH_PERF_SEL_SC6_PA4_EOPG_WE = 802 +PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 803 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805 +PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806 +PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807 +PH_PERF_SEL_SC6_PA5_NULL_WE = 808 +PH_PERF_SEL_SC6_PA5_EVENT_WE = 809 +PH_PERF_SEL_SC6_PA5_FPOV_WE = 810 +PH_PERF_SEL_SC6_PA5_LPOV_WE = 811 +PH_PERF_SEL_SC6_PA5_EOP_WE = 812 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813 +PH_PERF_SEL_SC6_PA5_EOPG_WE = 814 +PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 815 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817 +PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818 +PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819 +PH_PERF_SEL_SC6_PA6_NULL_WE = 820 +PH_PERF_SEL_SC6_PA6_EVENT_WE = 821 +PH_PERF_SEL_SC6_PA6_FPOV_WE = 822 +PH_PERF_SEL_SC6_PA6_LPOV_WE = 823 +PH_PERF_SEL_SC6_PA6_EOP_WE = 824 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825 +PH_PERF_SEL_SC6_PA6_EOPG_WE = 826 +PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 827 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829 +PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830 +PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831 +PH_PERF_SEL_SC6_PA7_NULL_WE = 832 +PH_PERF_SEL_SC6_PA7_EVENT_WE = 833 +PH_PERF_SEL_SC6_PA7_FPOV_WE = 834 +PH_PERF_SEL_SC6_PA7_LPOV_WE = 835 +PH_PERF_SEL_SC6_PA7_EOP_WE = 836 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837 +PH_PERF_SEL_SC6_PA7_EOPG_WE = 838 +PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 839 +PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840 +PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 +PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 +PH_PERF_SEL_SC7_ARB_BUSY = 848 +PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849 +PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850 +PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851 +PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 +PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853 +PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 +PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855 +PH_PERF_SEL_SC7_SEND = 856 +PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 +PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858 +PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 +PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860 +PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861 +PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862 +PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865 +PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866 +PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867 +PH_PERF_SEL_SC7_PA0_NULL_WE = 868 +PH_PERF_SEL_SC7_PA0_EVENT_WE = 869 +PH_PERF_SEL_SC7_PA0_FPOV_WE = 870 +PH_PERF_SEL_SC7_PA0_LPOV_WE = 871 +PH_PERF_SEL_SC7_PA0_EOP_WE = 872 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873 +PH_PERF_SEL_SC7_PA0_EOPG_WE = 874 +PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 875 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877 +PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878 +PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879 +PH_PERF_SEL_SC7_PA1_NULL_WE = 880 +PH_PERF_SEL_SC7_PA1_EVENT_WE = 881 +PH_PERF_SEL_SC7_PA1_FPOV_WE = 882 +PH_PERF_SEL_SC7_PA1_LPOV_WE = 883 +PH_PERF_SEL_SC7_PA1_EOP_WE = 884 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885 +PH_PERF_SEL_SC7_PA1_EOPG_WE = 886 +PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 887 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889 +PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890 +PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891 +PH_PERF_SEL_SC7_PA2_NULL_WE = 892 +PH_PERF_SEL_SC7_PA2_EVENT_WE = 893 +PH_PERF_SEL_SC7_PA2_FPOV_WE = 894 +PH_PERF_SEL_SC7_PA2_LPOV_WE = 895 +PH_PERF_SEL_SC7_PA2_EOP_WE = 896 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897 +PH_PERF_SEL_SC7_PA2_EOPG_WE = 898 +PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 899 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901 +PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902 +PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903 +PH_PERF_SEL_SC7_PA3_NULL_WE = 904 +PH_PERF_SEL_SC7_PA3_EVENT_WE = 905 +PH_PERF_SEL_SC7_PA3_FPOV_WE = 906 +PH_PERF_SEL_SC7_PA3_LPOV_WE = 907 +PH_PERF_SEL_SC7_PA3_EOP_WE = 908 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909 +PH_PERF_SEL_SC7_PA3_EOPG_WE = 910 +PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 911 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913 +PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914 +PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915 +PH_PERF_SEL_SC7_PA4_NULL_WE = 916 +PH_PERF_SEL_SC7_PA4_EVENT_WE = 917 +PH_PERF_SEL_SC7_PA4_FPOV_WE = 918 +PH_PERF_SEL_SC7_PA4_LPOV_WE = 919 +PH_PERF_SEL_SC7_PA4_EOP_WE = 920 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921 +PH_PERF_SEL_SC7_PA4_EOPG_WE = 922 +PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 923 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925 +PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926 +PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927 +PH_PERF_SEL_SC7_PA5_NULL_WE = 928 +PH_PERF_SEL_SC7_PA5_EVENT_WE = 929 +PH_PERF_SEL_SC7_PA5_FPOV_WE = 930 +PH_PERF_SEL_SC7_PA5_LPOV_WE = 931 +PH_PERF_SEL_SC7_PA5_EOP_WE = 932 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933 +PH_PERF_SEL_SC7_PA5_EOPG_WE = 934 +PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 935 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937 +PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938 +PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939 +PH_PERF_SEL_SC7_PA6_NULL_WE = 940 +PH_PERF_SEL_SC7_PA6_EVENT_WE = 941 +PH_PERF_SEL_SC7_PA6_FPOV_WE = 942 +PH_PERF_SEL_SC7_PA6_LPOV_WE = 943 +PH_PERF_SEL_SC7_PA6_EOP_WE = 944 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945 +PH_PERF_SEL_SC7_PA6_EOPG_WE = 946 +PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 947 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949 +PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950 +PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951 +PH_PERF_SEL_SC7_PA7_NULL_WE = 952 +PH_PERF_SEL_SC7_PA7_EVENT_WE = 953 +PH_PERF_SEL_SC7_PA7_FPOV_WE = 954 +PH_PERF_SEL_SC7_PA7_LPOV_WE = 955 +PH_PERF_SEL_SC7_PA7_EOP_WE = 956 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957 +PH_PERF_SEL_SC7_PA7_EOPG_WE = 958 +PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 959 +PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960 +PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961 +PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962 +PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963 +PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964 +PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965 +PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966 +PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991 +PH_PERF_SC0_FIFO_STATUS_0 = 992 +PH_PERF_SC0_FIFO_STATUS_1 = 993 +PH_PERF_SC0_FIFO_STATUS_2 = 994 +PH_PERF_SC0_FIFO_STATUS_3 = 995 +PH_PERF_SC1_FIFO_STATUS_0 = 996 +PH_PERF_SC1_FIFO_STATUS_1 = 997 +PH_PERF_SC1_FIFO_STATUS_2 = 998 +PH_PERF_SC1_FIFO_STATUS_3 = 999 +PH_PERF_SC2_FIFO_STATUS_0 = 1000 +PH_PERF_SC2_FIFO_STATUS_1 = 1001 +PH_PERF_SC2_FIFO_STATUS_2 = 1002 +PH_PERF_SC2_FIFO_STATUS_3 = 1003 +PH_PERF_SC3_FIFO_STATUS_0 = 1004 +PH_PERF_SC3_FIFO_STATUS_1 = 1005 +PH_PERF_SC3_FIFO_STATUS_2 = 1006 +PH_PERF_SC3_FIFO_STATUS_3 = 1007 +PH_PERF_SC4_FIFO_STATUS_0 = 1008 +PH_PERF_SC4_FIFO_STATUS_1 = 1009 +PH_PERF_SC4_FIFO_STATUS_2 = 1010 +PH_PERF_SC4_FIFO_STATUS_3 = 1011 +PH_PERF_SC5_FIFO_STATUS_0 = 1012 +PH_PERF_SC5_FIFO_STATUS_1 = 1013 +PH_PERF_SC5_FIFO_STATUS_2 = 1014 +PH_PERF_SC5_FIFO_STATUS_3 = 1015 +PH_PERF_SC6_FIFO_STATUS_0 = 1016 +PH_PERF_SC6_FIFO_STATUS_1 = 1017 +PH_PERF_SC6_FIFO_STATUS_2 = 1018 +PH_PERF_SC6_FIFO_STATUS_3 = 1019 +PH_PERF_SC7_FIFO_STATUS_0 = 1020 +PH_PERF_SC7_FIFO_STATUS_1 = 1021 +PH_PERF_SC7_FIFO_STATUS_2 = 1022 +PH_PERF_SC7_FIFO_STATUS_3 = 1023 +PH_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PhSPIstatusMode' +PhSPIstatusMode__enumvalues = { + 0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 2: 'PH_SPI_MODE_DISABLED', +} +PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0 +PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1 +PH_SPI_MODE_DISABLED = 2 +PhSPIstatusMode = ctypes.c_uint32 # enum + +# values for enumeration 'RMIPerfSel' +RMIPerfSel__enumvalues = { + 0: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 1: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', +} +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0 +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 1 +RMIPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'GCRPerfSel' +GCRPerfSel__enumvalues = { + 0: 'GCR_PERF_SEL_NONE', + 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', + 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', + 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', + 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', + 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 33: 'GCR_PERF_SEL_CPC_ALL_REQ', + 34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', + 35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', + 40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 44: 'GCR_PERF_SEL_CPC_METADATA_REQ', + 45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', + 46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 47: 'GCR_PERF_SEL_CPC_TCP_REQ', + 48: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 49: 'GCR_PERF_SEL_CPG_ALL_REQ', + 50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', + 51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', + 56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 60: 'GCR_PERF_SEL_CPG_METADATA_REQ', + 61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', + 62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 63: 'GCR_PERF_SEL_CPG_TCP_REQ', + 64: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', + 65: 'GCR_PERF_SEL_CPF_ALL_REQ', + 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', + 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', + 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', + 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', + 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 79: 'GCR_PERF_SEL_CPF_TCP_REQ', + 80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 81: 'GCR_PERF_SEL_VIRT_REQ', + 82: 'GCR_PERF_SEL_PHY_REQ', + 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 85: 'GCR_PERF_SEL_ALL_REQ', + 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 89: 'GCR_PERF_SEL_UTCL2_REQ', + 90: 'GCR_PERF_SEL_UTCL2_RET', + 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 94: 'GCR_PERF_SEL_RLC_ALL_REQ', + 95: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', + 96: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 97: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 98: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 99: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 100: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', + 101: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 102: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 103: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 104: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 105: 'GCR_PERF_SEL_RLC_METADATA_REQ', + 106: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', + 107: 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 108: 'GCR_PERF_SEL_RLC_TCP_REQ', + 109: 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', + 110: 'GCR_PERF_SEL_PM_ALL_REQ', + 111: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', + 112: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 113: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 114: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 115: 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 116: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', + 117: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 118: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 119: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 120: 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 121: 'GCR_PERF_SEL_PM_METADATA_REQ', + 122: 'GCR_PERF_SEL_PM_SQC_DATA_REQ', + 123: 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 124: 'GCR_PERF_SEL_PM_TCP_REQ', + 125: 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', + 126: 'GCR_PERF_SEL_PIO_ALL_REQ', + 127: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', + 128: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 129: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 130: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 131: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 132: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', + 133: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 134: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 135: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 136: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 137: 'GCR_PERF_SEL_PIO_METADATA_REQ', + 138: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', + 139: 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 140: 'GCR_PERF_SEL_PIO_TCP_REQ', + 141: 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', +} +GCR_PERF_SEL_NONE = 0 +GCR_PERF_SEL_SDMA0_ALL_REQ = 1 +GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 +GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 +GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 +GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 +GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 +GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 +GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 +GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 +GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 +GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 +GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 +GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 +GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 +GCR_PERF_SEL_SDMA0_TCP_REQ = 15 +GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16 +GCR_PERF_SEL_SDMA1_ALL_REQ = 17 +GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 +GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 +GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 +GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 +GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 +GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 +GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 +GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 +GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 +GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 +GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 +GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 +GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 +GCR_PERF_SEL_SDMA1_TCP_REQ = 31 +GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32 +GCR_PERF_SEL_CPC_ALL_REQ = 33 +GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34 +GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35 +GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36 +GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37 +GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38 +GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39 +GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40 +GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41 +GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42 +GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43 +GCR_PERF_SEL_CPC_METADATA_REQ = 44 +GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45 +GCR_PERF_SEL_CPC_SQC_INST_REQ = 46 +GCR_PERF_SEL_CPC_TCP_REQ = 47 +GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 48 +GCR_PERF_SEL_CPG_ALL_REQ = 49 +GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50 +GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51 +GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52 +GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53 +GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54 +GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55 +GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56 +GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57 +GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58 +GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59 +GCR_PERF_SEL_CPG_METADATA_REQ = 60 +GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61 +GCR_PERF_SEL_CPG_SQC_INST_REQ = 62 +GCR_PERF_SEL_CPG_TCP_REQ = 63 +GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 64 +GCR_PERF_SEL_CPF_ALL_REQ = 65 +GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 +GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 +GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 +GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 +GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 +GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 +GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 +GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 +GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 +GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 +GCR_PERF_SEL_CPF_METADATA_REQ = 76 +GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 +GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 +GCR_PERF_SEL_CPF_TCP_REQ = 79 +GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80 +GCR_PERF_SEL_VIRT_REQ = 81 +GCR_PERF_SEL_PHY_REQ = 82 +GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 +GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 +GCR_PERF_SEL_ALL_REQ = 85 +GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 +GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 +GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 +GCR_PERF_SEL_UTCL2_REQ = 89 +GCR_PERF_SEL_UTCL2_RET = 90 +GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 +GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 +GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 +GCR_PERF_SEL_RLC_ALL_REQ = 94 +GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 95 +GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 96 +GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 97 +GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 98 +GCR_PERF_SEL_RLC_GL2_ALL_REQ = 99 +GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 100 +GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 101 +GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 102 +GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 103 +GCR_PERF_SEL_RLC_GL1_ALL_REQ = 104 +GCR_PERF_SEL_RLC_METADATA_REQ = 105 +GCR_PERF_SEL_RLC_SQC_DATA_REQ = 106 +GCR_PERF_SEL_RLC_SQC_INST_REQ = 107 +GCR_PERF_SEL_RLC_TCP_REQ = 108 +GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 109 +GCR_PERF_SEL_PM_ALL_REQ = 110 +GCR_PERF_SEL_PM_GL2_RANGE_REQ = 111 +GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 112 +GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 113 +GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 114 +GCR_PERF_SEL_PM_GL2_ALL_REQ = 115 +GCR_PERF_SEL_PM_GL1_RANGE_REQ = 116 +GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 117 +GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 118 +GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 119 +GCR_PERF_SEL_PM_GL1_ALL_REQ = 120 +GCR_PERF_SEL_PM_METADATA_REQ = 121 +GCR_PERF_SEL_PM_SQC_DATA_REQ = 122 +GCR_PERF_SEL_PM_SQC_INST_REQ = 123 +GCR_PERF_SEL_PM_TCP_REQ = 124 +GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 125 +GCR_PERF_SEL_PIO_ALL_REQ = 126 +GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 127 +GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 128 +GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 129 +GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 130 +GCR_PERF_SEL_PIO_GL2_ALL_REQ = 131 +GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 132 +GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 133 +GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 134 +GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 135 +GCR_PERF_SEL_PIO_GL1_ALL_REQ = 136 +GCR_PERF_SEL_PIO_METADATA_REQ = 137 +GCR_PERF_SEL_PIO_SQC_DATA_REQ = 138 +GCR_PERF_SEL_PIO_SQC_INST_REQ = 139 +GCR_PERF_SEL_PIO_TCP_REQ = 140 +GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 141 +GCRPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1PerfSel' +UTCL1PerfSel__enumvalues = { + 0: 'UTCL1_PERF_SEL_NONE', + 1: 'UTCL1_PERF_SEL_REQS', + 2: 'UTCL1_PERF_SEL_HITS', + 3: 'UTCL1_PERF_SEL_MISSES', + 4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', + 5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 6: 'UTCL1_PERF_SEL_UTCL2_REQS', + 7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', + 10: 'UTCL1_PERF_SEL_STALL_MH_FULL', + 11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT', + 13: 'UTCL1_PERF_SEL_RTNS', + 14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', + 15: 'UTCL1_PERF_SEL_BYPASS_REQS', + 16: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 17: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 18: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 19: 'UTCL1_PERF_SEL_CP_INVREQS', + 20: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 21: 'UTCL1_PERF_SEL_RANGE_INVREQS', + 22: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', +} +UTCL1_PERF_SEL_NONE = 0 +UTCL1_PERF_SEL_REQS = 1 +UTCL1_PERF_SEL_HITS = 2 +UTCL1_PERF_SEL_MISSES = 3 +UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4 +UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5 +UTCL1_PERF_SEL_UTCL2_REQS = 6 +UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7 +UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8 +UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9 +UTCL1_PERF_SEL_STALL_MH_FULL = 10 +UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11 +UTCL1_PERF_SEL_UTCL2_RET_CNT = 12 +UTCL1_PERF_SEL_RTNS = 13 +UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14 +UTCL1_PERF_SEL_BYPASS_REQS = 15 +UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 16 +UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 17 +UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 18 +UTCL1_PERF_SEL_CP_INVREQS = 19 +UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 20 +UTCL1_PERF_SEL_RANGE_INVREQS = 21 +UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 22 +UTCL1PerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'IH_CLIENT_TYPE' +IH_CLIENT_TYPE__enumvalues = { + 0: 'IH_GFX_VMID_CLIENT', + 1: 'IH_MM_VMID_CLIENT', + 2: 'IH_MULTI_VMID_CLIENT', + 3: 'IH_CLIENT_TYPE_RESERVED', +} +IH_GFX_VMID_CLIENT = 0 +IH_MM_VMID_CLIENT = 1 +IH_MULTI_VMID_CLIENT = 2 +IH_CLIENT_TYPE_RESERVED = 3 +IH_CLIENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'IH_INTERFACE_TYPE' +IH_INTERFACE_TYPE__enumvalues = { + 0: 'IH_LEGACY_INTERFACE', + 1: 'IH_REGISTER_WRITE_INTERFACE', +} +IH_LEGACY_INTERFACE = 0 +IH_REGISTER_WRITE_INTERFACE = 1 +IH_INTERFACE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'IH_PERF_SEL' +IH_PERF_SEL__enumvalues = { + 0: 'IH_PERF_SEL_CYCLE', + 1: 'IH_PERF_SEL_IDLE', + 2: 'IH_PERF_SEL_INPUT_IDLE', + 3: 'IH_PERF_SEL_BUFFER_IDLE', + 4: 'IH_PERF_SEL_RB0_FULL', + 5: 'IH_PERF_SEL_RB0_OVERFLOW', + 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', + 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', + 9: 'IH_PERF_SEL_MC_WR_IDLE', + 10: 'IH_PERF_SEL_MC_WR_COUNT', + 11: 'IH_PERF_SEL_MC_WR_STALL', + 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', + 14: 'IH_PERF_SEL_BIF_LINE0_RISING', + 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', + 16: 'IH_PERF_SEL_RB1_FULL', + 17: 'IH_PERF_SEL_RB1_OVERFLOW', + 18: 'IH_PERF_SEL_COOKIE_REC_ERROR', + 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', + 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', + 21: 'IH_PERF_SEL_RB2_FULL', + 22: 'IH_PERF_SEL_RB2_OVERFLOW', + 23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', + 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', + 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', + 26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 27: 'IH_PERF_SEL_SELF_IV_VALID', + 28: 'IH_PERF_SEL_BUFFER_FIFO_FULL', + 29: 'IH_PERF_SEL_RB0_FULL_VF0', + 30: 'IH_PERF_SEL_RB0_FULL_VF1', + 31: 'IH_PERF_SEL_RB0_FULL_VF2', + 32: 'IH_PERF_SEL_RB0_FULL_VF3', + 33: 'IH_PERF_SEL_RB0_FULL_VF4', + 34: 'IH_PERF_SEL_RB0_FULL_VF5', + 35: 'IH_PERF_SEL_RB0_FULL_VF6', + 36: 'IH_PERF_SEL_RB0_FULL_VF7', + 37: 'IH_PERF_SEL_RB0_FULL_VF8', + 38: 'IH_PERF_SEL_RB0_FULL_VF9', + 39: 'IH_PERF_SEL_RB0_FULL_VF10', + 40: 'IH_PERF_SEL_RB0_FULL_VF11', + 41: 'IH_PERF_SEL_RB0_FULL_VF12', + 42: 'IH_PERF_SEL_RB0_FULL_VF13', + 43: 'IH_PERF_SEL_RB0_FULL_VF14', + 44: 'IH_PERF_SEL_RB0_FULL_VF15', + 45: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', + 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', + 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', + 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', + 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', + 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', + 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', + 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', + 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 61: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', + 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 77: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', + 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', + 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', + 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', + 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', + 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', + 93: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', + 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', + 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', + 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', + 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', + 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', + 109: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 125: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 141: 'IH_PERF_SEL_CLIENT0_INT', + 142: 'IH_PERF_SEL_CLIENT1_INT', + 143: 'IH_PERF_SEL_CLIENT2_INT', + 144: 'IH_PERF_SEL_CLIENT3_INT', + 145: 'IH_PERF_SEL_CLIENT4_INT', + 146: 'IH_PERF_SEL_CLIENT5_INT', + 147: 'IH_PERF_SEL_CLIENT6_INT', + 148: 'IH_PERF_SEL_CLIENT7_INT', + 149: 'IH_PERF_SEL_CLIENT8_INT', + 150: 'IH_PERF_SEL_CLIENT9_INT', + 151: 'IH_PERF_SEL_CLIENT10_INT', + 152: 'IH_PERF_SEL_CLIENT11_INT', + 153: 'IH_PERF_SEL_CLIENT12_INT', + 154: 'IH_PERF_SEL_CLIENT13_INT', + 155: 'IH_PERF_SEL_CLIENT14_INT', + 156: 'IH_PERF_SEL_CLIENT15_INT', + 157: 'IH_PERF_SEL_CLIENT16_INT', + 158: 'IH_PERF_SEL_CLIENT17_INT', + 159: 'IH_PERF_SEL_CLIENT18_INT', + 160: 'IH_PERF_SEL_CLIENT19_INT', + 161: 'IH_PERF_SEL_CLIENT20_INT', + 162: 'IH_PERF_SEL_CLIENT21_INT', + 163: 'IH_PERF_SEL_CLIENT22_INT', + 164: 'IH_PERF_SEL_CLIENT23_INT', + 165: 'IH_PERF_SEL_CLIENT24_INT', + 166: 'IH_PERF_SEL_CLIENT25_INT', + 167: 'IH_PERF_SEL_CLIENT26_INT', + 168: 'IH_PERF_SEL_CLIENT27_INT', + 169: 'IH_PERF_SEL_CLIENT28_INT', + 170: 'IH_PERF_SEL_CLIENT29_INT', + 171: 'IH_PERF_SEL_CLIENT30_INT', + 172: 'IH_PERF_SEL_CLIENT31_INT', + 173: 'IH_PERF_SEL_RB1_FULL_VF0', + 174: 'IH_PERF_SEL_RB1_FULL_VF1', + 175: 'IH_PERF_SEL_RB1_FULL_VF2', + 176: 'IH_PERF_SEL_RB1_FULL_VF3', + 177: 'IH_PERF_SEL_RB1_FULL_VF4', + 178: 'IH_PERF_SEL_RB1_FULL_VF5', + 179: 'IH_PERF_SEL_RB1_FULL_VF6', + 180: 'IH_PERF_SEL_RB1_FULL_VF7', + 181: 'IH_PERF_SEL_RB1_FULL_VF8', + 182: 'IH_PERF_SEL_RB1_FULL_VF9', + 183: 'IH_PERF_SEL_RB1_FULL_VF10', + 184: 'IH_PERF_SEL_RB1_FULL_VF11', + 185: 'IH_PERF_SEL_RB1_FULL_VF12', + 186: 'IH_PERF_SEL_RB1_FULL_VF13', + 187: 'IH_PERF_SEL_RB1_FULL_VF14', + 188: 'IH_PERF_SEL_RB1_FULL_VF15', + 189: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 190: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 191: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 192: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 193: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 194: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 195: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 196: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 197: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 198: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 199: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 200: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 201: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 202: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 203: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 204: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 205: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', + 206: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 207: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 208: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', + 209: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 210: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', + 211: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 212: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', + 213: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 214: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', + 215: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 216: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 217: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 218: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 219: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 220: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', + 221: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 222: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 223: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 224: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', + 225: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 226: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', + 227: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 228: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', + 229: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 230: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', + 231: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 232: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 233: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 234: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 235: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 236: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', + 237: 'IH_PERF_SEL_RB2_FULL_VF0', + 238: 'IH_PERF_SEL_RB2_FULL_VF1', + 239: 'IH_PERF_SEL_RB2_FULL_VF2', + 240: 'IH_PERF_SEL_RB2_FULL_VF3', + 241: 'IH_PERF_SEL_RB2_FULL_VF4', + 242: 'IH_PERF_SEL_RB2_FULL_VF5', + 243: 'IH_PERF_SEL_RB2_FULL_VF6', + 244: 'IH_PERF_SEL_RB2_FULL_VF7', + 245: 'IH_PERF_SEL_RB2_FULL_VF8', + 246: 'IH_PERF_SEL_RB2_FULL_VF9', + 247: 'IH_PERF_SEL_RB2_FULL_VF10', + 248: 'IH_PERF_SEL_RB2_FULL_VF11', + 249: 'IH_PERF_SEL_RB2_FULL_VF12', + 250: 'IH_PERF_SEL_RB2_FULL_VF13', + 251: 'IH_PERF_SEL_RB2_FULL_VF14', + 252: 'IH_PERF_SEL_RB2_FULL_VF15', + 253: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 254: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 255: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 256: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 257: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 258: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 259: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 260: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 261: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 262: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 263: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 264: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 265: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 266: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 267: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 268: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 269: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', + 270: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 271: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 272: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', + 273: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 274: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', + 275: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 276: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', + 277: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 278: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', + 279: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 280: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 281: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 282: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 283: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 284: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', + 285: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 286: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 287: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 288: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', + 289: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 290: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', + 291: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 292: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', + 293: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 294: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', + 295: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 296: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 297: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 298: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 299: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 300: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', + 301: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 302: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 303: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 304: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 305: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 306: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 307: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 308: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 309: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 310: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 311: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', + 312: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 313: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 314: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 315: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 316: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 317: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 318: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 319: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 320: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 321: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 322: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 323: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 324: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 325: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 326: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 327: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 328: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', + 329: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 330: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 331: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 332: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 333: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 334: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 335: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 336: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 337: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 338: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 339: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 340: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 341: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 342: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 343: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 344: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 345: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', + 346: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 347: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 348: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 349: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 350: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 351: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 352: 'IH_PERF_SEL_RB0_LOAD_RPTR', + 353: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', + 354: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', + 355: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 356: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', + 357: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 358: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', + 359: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 360: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', + 361: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 362: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', + 363: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 364: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 365: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 366: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 367: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 368: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', + 369: 'IH_PERF_SEL_RB1_LOAD_RPTR', + 370: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', + 371: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', + 372: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 373: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', + 374: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 375: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', + 376: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 377: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', + 378: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 379: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', + 380: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 381: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 382: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 383: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 384: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 385: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', + 386: 'IH_PERF_SEL_RB2_LOAD_RPTR', + 387: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', + 388: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', + 389: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 390: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', + 391: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 392: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', + 393: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 394: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', + 395: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 396: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', + 397: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 398: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 399: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 400: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 401: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 402: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', +} +IH_PERF_SEL_CYCLE = 0 +IH_PERF_SEL_IDLE = 1 +IH_PERF_SEL_INPUT_IDLE = 2 +IH_PERF_SEL_BUFFER_IDLE = 3 +IH_PERF_SEL_RB0_FULL = 4 +IH_PERF_SEL_RB0_OVERFLOW = 5 +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 +IH_PERF_SEL_RB0_WPTR_WRAP = 7 +IH_PERF_SEL_RB0_RPTR_WRAP = 8 +IH_PERF_SEL_MC_WR_IDLE = 9 +IH_PERF_SEL_MC_WR_COUNT = 10 +IH_PERF_SEL_MC_WR_STALL = 11 +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 +IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 +IH_PERF_SEL_BIF_LINE0_RISING = 14 +IH_PERF_SEL_BIF_LINE0_FALLING = 15 +IH_PERF_SEL_RB1_FULL = 16 +IH_PERF_SEL_RB1_OVERFLOW = 17 +IH_PERF_SEL_COOKIE_REC_ERROR = 18 +IH_PERF_SEL_RB1_WPTR_WRAP = 19 +IH_PERF_SEL_RB1_RPTR_WRAP = 20 +IH_PERF_SEL_RB2_FULL = 21 +IH_PERF_SEL_RB2_OVERFLOW = 22 +IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23 +IH_PERF_SEL_RB2_WPTR_WRAP = 24 +IH_PERF_SEL_RB2_RPTR_WRAP = 25 +IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26 +IH_PERF_SEL_SELF_IV_VALID = 27 +IH_PERF_SEL_BUFFER_FIFO_FULL = 28 +IH_PERF_SEL_RB0_FULL_VF0 = 29 +IH_PERF_SEL_RB0_FULL_VF1 = 30 +IH_PERF_SEL_RB0_FULL_VF2 = 31 +IH_PERF_SEL_RB0_FULL_VF3 = 32 +IH_PERF_SEL_RB0_FULL_VF4 = 33 +IH_PERF_SEL_RB0_FULL_VF5 = 34 +IH_PERF_SEL_RB0_FULL_VF6 = 35 +IH_PERF_SEL_RB0_FULL_VF7 = 36 +IH_PERF_SEL_RB0_FULL_VF8 = 37 +IH_PERF_SEL_RB0_FULL_VF9 = 38 +IH_PERF_SEL_RB0_FULL_VF10 = 39 +IH_PERF_SEL_RB0_FULL_VF11 = 40 +IH_PERF_SEL_RB0_FULL_VF12 = 41 +IH_PERF_SEL_RB0_FULL_VF13 = 42 +IH_PERF_SEL_RB0_FULL_VF14 = 43 +IH_PERF_SEL_RB0_FULL_VF15 = 44 +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 45 +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 46 +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 47 +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 48 +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 49 +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 50 +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 51 +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 52 +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 53 +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 54 +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 55 +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 56 +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 57 +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 58 +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 59 +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 60 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 61 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 62 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 63 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 64 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 65 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 66 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 67 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 68 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 69 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 70 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 71 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 72 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 73 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 74 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 75 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 76 +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 77 +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 78 +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 79 +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 80 +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 81 +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 82 +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 83 +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 84 +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 85 +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 86 +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 87 +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 88 +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 89 +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 90 +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 91 +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 92 +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 93 +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 94 +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 95 +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 96 +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 97 +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 98 +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 99 +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 100 +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 101 +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 102 +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 103 +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 104 +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 105 +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 106 +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 107 +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 108 +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 109 +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 110 +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 111 +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 112 +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 113 +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 114 +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 115 +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 116 +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 117 +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 118 +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 119 +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 120 +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 121 +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 122 +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 123 +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 124 +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 125 +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 126 +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 127 +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 128 +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 129 +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 130 +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 131 +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 132 +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 133 +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 134 +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 135 +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 136 +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 137 +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 138 +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 139 +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 140 +IH_PERF_SEL_CLIENT0_INT = 141 +IH_PERF_SEL_CLIENT1_INT = 142 +IH_PERF_SEL_CLIENT2_INT = 143 +IH_PERF_SEL_CLIENT3_INT = 144 +IH_PERF_SEL_CLIENT4_INT = 145 +IH_PERF_SEL_CLIENT5_INT = 146 +IH_PERF_SEL_CLIENT6_INT = 147 +IH_PERF_SEL_CLIENT7_INT = 148 +IH_PERF_SEL_CLIENT8_INT = 149 +IH_PERF_SEL_CLIENT9_INT = 150 +IH_PERF_SEL_CLIENT10_INT = 151 +IH_PERF_SEL_CLIENT11_INT = 152 +IH_PERF_SEL_CLIENT12_INT = 153 +IH_PERF_SEL_CLIENT13_INT = 154 +IH_PERF_SEL_CLIENT14_INT = 155 +IH_PERF_SEL_CLIENT15_INT = 156 +IH_PERF_SEL_CLIENT16_INT = 157 +IH_PERF_SEL_CLIENT17_INT = 158 +IH_PERF_SEL_CLIENT18_INT = 159 +IH_PERF_SEL_CLIENT19_INT = 160 +IH_PERF_SEL_CLIENT20_INT = 161 +IH_PERF_SEL_CLIENT21_INT = 162 +IH_PERF_SEL_CLIENT22_INT = 163 +IH_PERF_SEL_CLIENT23_INT = 164 +IH_PERF_SEL_CLIENT24_INT = 165 +IH_PERF_SEL_CLIENT25_INT = 166 +IH_PERF_SEL_CLIENT26_INT = 167 +IH_PERF_SEL_CLIENT27_INT = 168 +IH_PERF_SEL_CLIENT28_INT = 169 +IH_PERF_SEL_CLIENT29_INT = 170 +IH_PERF_SEL_CLIENT30_INT = 171 +IH_PERF_SEL_CLIENT31_INT = 172 +IH_PERF_SEL_RB1_FULL_VF0 = 173 +IH_PERF_SEL_RB1_FULL_VF1 = 174 +IH_PERF_SEL_RB1_FULL_VF2 = 175 +IH_PERF_SEL_RB1_FULL_VF3 = 176 +IH_PERF_SEL_RB1_FULL_VF4 = 177 +IH_PERF_SEL_RB1_FULL_VF5 = 178 +IH_PERF_SEL_RB1_FULL_VF6 = 179 +IH_PERF_SEL_RB1_FULL_VF7 = 180 +IH_PERF_SEL_RB1_FULL_VF8 = 181 +IH_PERF_SEL_RB1_FULL_VF9 = 182 +IH_PERF_SEL_RB1_FULL_VF10 = 183 +IH_PERF_SEL_RB1_FULL_VF11 = 184 +IH_PERF_SEL_RB1_FULL_VF12 = 185 +IH_PERF_SEL_RB1_FULL_VF13 = 186 +IH_PERF_SEL_RB1_FULL_VF14 = 187 +IH_PERF_SEL_RB1_FULL_VF15 = 188 +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 189 +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 190 +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 191 +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 192 +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 193 +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 194 +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 195 +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 196 +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 197 +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 198 +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 199 +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 200 +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 201 +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 202 +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 203 +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 204 +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 205 +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 206 +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 207 +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 208 +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 209 +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 210 +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 211 +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 212 +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 213 +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 214 +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 215 +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 216 +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 217 +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 218 +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 219 +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 220 +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 221 +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 222 +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 223 +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 224 +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 225 +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 226 +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 227 +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 228 +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 229 +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 230 +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 231 +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 232 +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 233 +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 234 +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 235 +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 236 +IH_PERF_SEL_RB2_FULL_VF0 = 237 +IH_PERF_SEL_RB2_FULL_VF1 = 238 +IH_PERF_SEL_RB2_FULL_VF2 = 239 +IH_PERF_SEL_RB2_FULL_VF3 = 240 +IH_PERF_SEL_RB2_FULL_VF4 = 241 +IH_PERF_SEL_RB2_FULL_VF5 = 242 +IH_PERF_SEL_RB2_FULL_VF6 = 243 +IH_PERF_SEL_RB2_FULL_VF7 = 244 +IH_PERF_SEL_RB2_FULL_VF8 = 245 +IH_PERF_SEL_RB2_FULL_VF9 = 246 +IH_PERF_SEL_RB2_FULL_VF10 = 247 +IH_PERF_SEL_RB2_FULL_VF11 = 248 +IH_PERF_SEL_RB2_FULL_VF12 = 249 +IH_PERF_SEL_RB2_FULL_VF13 = 250 +IH_PERF_SEL_RB2_FULL_VF14 = 251 +IH_PERF_SEL_RB2_FULL_VF15 = 252 +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 253 +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 254 +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 255 +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 256 +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 257 +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 258 +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 259 +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 260 +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 261 +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 262 +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 263 +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 264 +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 265 +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 266 +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 267 +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 268 +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 269 +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 270 +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 271 +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 272 +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 273 +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 274 +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 275 +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 276 +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 277 +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 278 +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 279 +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 280 +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 281 +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 282 +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 283 +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 284 +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 285 +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 286 +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 287 +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 288 +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 289 +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 290 +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 291 +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 292 +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 293 +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 294 +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 295 +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 296 +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 297 +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 298 +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 299 +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 300 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 301 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 302 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 303 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 304 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 305 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 306 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 307 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 308 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 309 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 310 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 311 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 312 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 313 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 314 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 315 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 316 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 317 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 318 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 319 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 320 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 321 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 322 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 323 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 324 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 325 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 326 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 327 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 328 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 329 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 330 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 331 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 332 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 333 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 334 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 335 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 336 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 337 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 338 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 339 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 340 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 341 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 342 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 343 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 344 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 345 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 346 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 347 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 348 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 349 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 350 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 351 +IH_PERF_SEL_RB0_LOAD_RPTR = 352 +IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 353 +IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 354 +IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 355 +IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 356 +IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 357 +IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 358 +IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 359 +IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 360 +IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 361 +IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 362 +IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 363 +IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 364 +IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 365 +IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 366 +IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 367 +IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 368 +IH_PERF_SEL_RB1_LOAD_RPTR = 369 +IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 370 +IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 371 +IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 372 +IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 373 +IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 374 +IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 375 +IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 376 +IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 377 +IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 378 +IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 379 +IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 380 +IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 381 +IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 382 +IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 383 +IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 384 +IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 385 +IH_PERF_SEL_RB2_LOAD_RPTR = 386 +IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 387 +IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 388 +IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 389 +IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 390 +IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 391 +IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 392 +IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 393 +IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 394 +IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 395 +IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 396 +IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 397 +IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 398 +IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 399 +IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 400 +IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 401 +IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 402 +IH_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'IH_RING_ID' +IH_RING_ID__enumvalues = { + 0: 'IH_RING_ID_INTERRUPT', + 1: 'IH_RING_ID_REQUEST', + 2: 'IH_RING_ID_TRANSLATION', + 3: 'IH_RING_ID_RESERVED', +} +IH_RING_ID_INTERRUPT = 0 +IH_RING_ID_REQUEST = 1 +IH_RING_ID_TRANSLATION = 2 +IH_RING_ID_RESERVED = 3 +IH_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'IH_VF_RB_SELECT' +IH_VF_RB_SELECT__enumvalues = { + 0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 1: 'IH_VF_RB_SELECT_IH_FCN_ID', + 2: 'IH_VF_RB_SELECT_PF', + 3: 'IH_VF_RB_SELECT_RESERVED', +} +IH_VF_RB_SELECT_CLIENT_FCN_ID = 0 +IH_VF_RB_SELECT_IH_FCN_ID = 1 +IH_VF_RB_SELECT_PF = 2 +IH_VF_RB_SELECT_RESERVED = 3 +IH_VF_RB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SEM_PERF_SEL' +SEM_PERF_SEL__enumvalues = { + 0: 'SEM_PERF_SEL_CYCLE', + 1: 'SEM_PERF_SEL_IDLE', + 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', + 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', + 4: 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', + 5: 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', + 6: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', + 7: 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', + 8: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', + 9: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 10: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', + 11: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', + 12: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', + 13: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', + 14: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', + 15: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 16: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 17: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 18: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 19: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 20: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 21: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 22: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 23: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 24: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 25: 'SEM_PERF_SEL_SDMA2_REQ_WAIT', + 26: 'SEM_PERF_SEL_SDMA3_REQ_WAIT', + 27: 'SEM_PERF_SEL_UVD_REQ_WAIT', + 28: 'SEM_PERF_SEL_UVD1_REQ_WAIT', + 29: 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 30: 'SEM_PERF_SEL_ACP_REQ_WAIT', + 31: 'SEM_PERF_SEL_ISP_REQ_WAIT', + 32: 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 33: 'SEM_PERF_SEL_VP8_REQ_WAIT', + 34: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 35: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 36: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 37: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 38: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 39: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 40: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 41: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 42: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 43: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 44: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 45: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 46: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 47: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 48: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 49: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 50: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 51: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 52: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 53: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 54: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 55: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 56: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 57: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 58: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 59: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 60: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 61: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 62: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 63: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 64: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 65: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 66: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 67: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 68: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 69: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 70: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 71: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 72: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 73: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 74: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 75: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 76: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 77: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 78: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 79: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 80: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 81: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 82: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 83: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 84: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 85: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 86: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 87: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 88: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 89: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 90: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 91: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 92: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 93: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 94: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 95: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 96: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 97: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 98: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 99: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 100: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 101: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 102: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 103: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 104: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 105: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 106: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 107: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 108: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 109: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 110: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 111: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 112: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 113: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 114: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 115: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 116: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 117: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 118: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 119: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 120: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 121: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 122: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 123: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 124: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 125: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 126: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 127: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 128: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 129: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 130: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 131: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 132: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 133: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 134: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 135: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 136: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 137: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 138: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 139: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 140: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 141: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 142: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 143: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 144: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 145: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 146: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 147: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 148: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 149: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 150: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 151: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 152: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 153: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 154: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 155: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 156: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 157: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 158: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 159: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 160: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 161: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 162: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 163: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 164: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 165: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 166: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 167: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 168: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 169: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 170: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 171: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 172: 'SEM_PERF_SEL_MC_RD_REQ', + 173: 'SEM_PERF_SEL_MC_RD_RET', + 174: 'SEM_PERF_SEL_MC_WR_REQ', + 175: 'SEM_PERF_SEL_MC_WR_RET', + 176: 'SEM_PERF_SEL_ATC_REQ', + 177: 'SEM_PERF_SEL_ATC_RET', + 178: 'SEM_PERF_SEL_ATC_XNACK', + 179: 'SEM_PERF_SEL_ATC_INVALIDATION', + 180: 'SEM_PERF_SEL_ATC_VM_INVALIDATION', +} +SEM_PERF_SEL_CYCLE = 0 +SEM_PERF_SEL_IDLE = 1 +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 +SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 4 +SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 5 +SEM_PERF_SEL_UVD_REQ_SIGNAL = 6 +SEM_PERF_SEL_UVD1_REQ_SIGNAL = 7 +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 8 +SEM_PERF_SEL_ACP_REQ_SIGNAL = 9 +SEM_PERF_SEL_ISP_REQ_SIGNAL = 10 +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 11 +SEM_PERF_SEL_VP8_REQ_SIGNAL = 12 +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 13 +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 14 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 15 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 16 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 17 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 18 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 19 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 20 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 21 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 22 +SEM_PERF_SEL_SDMA0_REQ_WAIT = 23 +SEM_PERF_SEL_SDMA1_REQ_WAIT = 24 +SEM_PERF_SEL_SDMA2_REQ_WAIT = 25 +SEM_PERF_SEL_SDMA3_REQ_WAIT = 26 +SEM_PERF_SEL_UVD_REQ_WAIT = 27 +SEM_PERF_SEL_UVD1_REQ_WAIT = 28 +SEM_PERF_SEL_VCE0_REQ_WAIT = 29 +SEM_PERF_SEL_ACP_REQ_WAIT = 30 +SEM_PERF_SEL_ISP_REQ_WAIT = 31 +SEM_PERF_SEL_VCE1_REQ_WAIT = 32 +SEM_PERF_SEL_VP8_REQ_WAIT = 33 +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 34 +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 35 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 36 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 37 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 38 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 39 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 40 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 41 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 42 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 43 +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 44 +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 45 +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 46 +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 47 +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 48 +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 49 +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 50 +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 51 +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 52 +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 53 +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 54 +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 55 +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 56 +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 57 +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 58 +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 59 +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 60 +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 61 +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 62 +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 63 +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 64 +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 65 +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 66 +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 67 +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 68 +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 69 +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 70 +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 71 +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 72 +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 73 +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 74 +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 75 +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 76 +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 77 +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 78 +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 79 +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 80 +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 81 +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 82 +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 83 +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 84 +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 85 +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 86 +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 87 +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 88 +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 89 +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 90 +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 91 +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 92 +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 93 +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 94 +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 95 +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 96 +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 97 +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 98 +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 99 +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 100 +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 101 +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 102 +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 103 +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 104 +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 105 +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 106 +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 107 +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 108 +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 109 +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 110 +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 111 +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 112 +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 113 +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 114 +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 115 +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 116 +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 117 +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 118 +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 119 +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 120 +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 121 +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 122 +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 123 +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 124 +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 125 +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 126 +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 127 +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 128 +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 129 +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 130 +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 131 +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 132 +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 133 +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 134 +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 135 +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 136 +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 137 +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 138 +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 139 +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 140 +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 141 +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 142 +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 143 +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 144 +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 145 +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 146 +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 147 +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 148 +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 149 +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 150 +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 151 +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 152 +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 153 +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 154 +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 155 +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 156 +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 157 +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 158 +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 159 +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 160 +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 161 +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 162 +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 163 +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 164 +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 165 +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 166 +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 167 +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 168 +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 169 +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 170 +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 171 +SEM_PERF_SEL_MC_RD_REQ = 172 +SEM_PERF_SEL_MC_RD_RET = 173 +SEM_PERF_SEL_MC_WR_REQ = 174 +SEM_PERF_SEL_MC_WR_RET = 175 +SEM_PERF_SEL_ATC_REQ = 176 +SEM_PERF_SEL_ATC_RET = 177 +SEM_PERF_SEL_ATC_XNACK = 178 +SEM_PERF_SEL_ATC_INVALIDATION = 179 +SEM_PERF_SEL_ATC_VM_INVALIDATION = 180 +SEM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LSDMA_PERF_SEL' +LSDMA_PERF_SEL__enumvalues = { + 0: 'LSDMA_PERF_SEL_CYCLE', + 1: 'LSDMA_PERF_SEL_IDLE', + 2: 'LSDMA_PERF_SEL_REG_IDLE', + 3: 'LSDMA_PERF_SEL_RB_EMPTY', + 4: 'LSDMA_PERF_SEL_RB_FULL', + 5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'LSDMA_PERF_SEL_RB_RPTR_WB', + 9: 'LSDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'LSDMA_PERF_SEL_RB_CMD_FULL', + 11: 'LSDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'LSDMA_PERF_SEL_IB_CMD_FULL', + 13: 'LSDMA_PERF_SEL_EX_IDLE', + 14: 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'LSDMA_PERF_SEL_MC_WR_IDLE', + 17: 'LSDMA_PERF_SEL_MC_WR_COUNT', + 18: 'LSDMA_PERF_SEL_MC_RD_IDLE', + 19: 'LSDMA_PERF_SEL_MC_RD_COUNT', + 20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'LSDMA_PERF_SEL_SEM_IDLE', + 25: 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'LSDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'LSDMA_PERF_SEL_INT_IDLE', + 31: 'LSDMA_PERF_SEL_INT_REQ_STALL', + 32: 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'LSDMA_PERF_SEL_NUM_PACKET', + 37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'LSDMA_PERF_SEL_CE_WR_IDLE', + 39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'LSDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'LSDMA_PERF_SEL_CE_IN_IDLE', + 43: 'LSDMA_PERF_SEL_CE_DST_IDLE', + 46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'LSDMA_PERF_SEL_CE_INFO_FULL', + 50: 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'LSDMA_PERF_SEL_CE_RD_STALL', + 52: 'LSDMA_PERF_SEL_CE_WR_STALL', + 53: 'LSDMA_PERF_SEL_GFX_SELECT', + 54: 'LSDMA_PERF_SEL_RLC0_SELECT', + 55: 'LSDMA_PERF_SEL_RLC1_SELECT', + 56: 'LSDMA_PERF_SEL_PAGE_SELECT', + 57: 'LSDMA_PERF_SEL_CTX_CHANGE', + 58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'LSDMA_PERF_SEL_DOORBELL', + 61: 'LSDMA_PERF_SEL_RD_BA_RTR', + 62: 'LSDMA_PERF_SEL_WR_BA_RTR', + 63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'LSDMA_PERF_SEL_CE_L1_STALL', + 66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', + 67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK', + 72: 'LSDMA_PERF_SEL_ATCL2_FREE', + 73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', + 76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', + 78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE', + 81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE', + 84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 86: 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 87: 'LSDMA_PERF_SEL_L1_RD_INV_EN', + 88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE', + 95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', + 103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', + 105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', + 107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 109: 'LSDMA_PERF_SEL_CMD_OP_MATCH', + 110: 'LSDMA_PERF_SEL_CMD_OP_START', + 111: 'LSDMA_PERF_SEL_CMD_OP_END', + 112: 'LSDMA_PERF_SEL_CE_BUSY', + 113: 'LSDMA_PERF_SEL_CE_BUSY_START', + 114: 'LSDMA_PERF_SEL_CE_BUSY_END', + 115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 122: 'LSDMA_PERF_SEL_DRAM_ECC', + 123: 'LSDMA_PERF_SEL_NACK_GEN_ERR', +} +LSDMA_PERF_SEL_CYCLE = 0 +LSDMA_PERF_SEL_IDLE = 1 +LSDMA_PERF_SEL_REG_IDLE = 2 +LSDMA_PERF_SEL_RB_EMPTY = 3 +LSDMA_PERF_SEL_RB_FULL = 4 +LSDMA_PERF_SEL_RB_WPTR_WRAP = 5 +LSDMA_PERF_SEL_RB_RPTR_WRAP = 6 +LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +LSDMA_PERF_SEL_RB_RPTR_WB = 8 +LSDMA_PERF_SEL_RB_CMD_IDLE = 9 +LSDMA_PERF_SEL_RB_CMD_FULL = 10 +LSDMA_PERF_SEL_IB_CMD_IDLE = 11 +LSDMA_PERF_SEL_IB_CMD_FULL = 12 +LSDMA_PERF_SEL_EX_IDLE = 13 +LSDMA_PERF_SEL_SRBM_REG_SEND = 14 +LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +LSDMA_PERF_SEL_MC_WR_IDLE = 16 +LSDMA_PERF_SEL_MC_WR_COUNT = 17 +LSDMA_PERF_SEL_MC_RD_IDLE = 18 +LSDMA_PERF_SEL_MC_RD_COUNT = 19 +LSDMA_PERF_SEL_MC_RD_RET_STALL = 20 +LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +LSDMA_PERF_SEL_SEM_IDLE = 24 +LSDMA_PERF_SEL_SEM_REQ_STALL = 25 +LSDMA_PERF_SEL_SEM_REQ_COUNT = 26 +LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +LSDMA_PERF_SEL_SEM_RESP_FAIL = 28 +LSDMA_PERF_SEL_SEM_RESP_PASS = 29 +LSDMA_PERF_SEL_INT_IDLE = 30 +LSDMA_PERF_SEL_INT_REQ_STALL = 31 +LSDMA_PERF_SEL_INT_REQ_COUNT = 32 +LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +LSDMA_PERF_SEL_INT_RESP_RETRY = 34 +LSDMA_PERF_SEL_NUM_PACKET = 35 +LSDMA_PERF_SEL_CE_WREQ_IDLE = 37 +LSDMA_PERF_SEL_CE_WR_IDLE = 38 +LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +LSDMA_PERF_SEL_CE_RREQ_IDLE = 40 +LSDMA_PERF_SEL_CE_OUT_IDLE = 41 +LSDMA_PERF_SEL_CE_IN_IDLE = 42 +LSDMA_PERF_SEL_CE_DST_IDLE = 43 +LSDMA_PERF_SEL_CE_AFIFO_FULL = 46 +LSDMA_PERF_SEL_CE_INFO_FULL = 49 +LSDMA_PERF_SEL_CE_INFO1_FULL = 50 +LSDMA_PERF_SEL_CE_RD_STALL = 51 +LSDMA_PERF_SEL_CE_WR_STALL = 52 +LSDMA_PERF_SEL_GFX_SELECT = 53 +LSDMA_PERF_SEL_RLC0_SELECT = 54 +LSDMA_PERF_SEL_RLC1_SELECT = 55 +LSDMA_PERF_SEL_PAGE_SELECT = 56 +LSDMA_PERF_SEL_CTX_CHANGE = 57 +LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +LSDMA_PERF_SEL_DOORBELL = 60 +LSDMA_PERF_SEL_RD_BA_RTR = 61 +LSDMA_PERF_SEL_WR_BA_RTR = 62 +LSDMA_PERF_SEL_F32_L1_WR_VLD = 63 +LSDMA_PERF_SEL_CE_L1_WR_VLD = 64 +LSDMA_PERF_SEL_CE_L1_STALL = 65 +LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 +LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 +LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 +LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 +LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70 +LSDMA_PERF_SEL_ATCL2_RET_ACK = 71 +LSDMA_PERF_SEL_ATCL2_FREE = 72 +LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 +LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74 +LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75 +LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76 +LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77 +LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 +LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 +LSDMA_PERF_SEL_L1_WRL2_IDLE = 80 +LSDMA_PERF_SEL_L1_RDL2_IDLE = 81 +LSDMA_PERF_SEL_L1_WRMC_IDLE = 82 +LSDMA_PERF_SEL_L1_RDMC_IDLE = 83 +LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84 +LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85 +LSDMA_PERF_SEL_L1_WR_INV_EN = 86 +LSDMA_PERF_SEL_L1_RD_INV_EN = 87 +LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 +LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 +LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 +LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 +LSDMA_PERF_SEL_L1_INV_MIDDLE = 94 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100 +LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101 +LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102 +LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103 +LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106 +LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107 +LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108 +LSDMA_PERF_SEL_CMD_OP_MATCH = 109 +LSDMA_PERF_SEL_CMD_OP_START = 110 +LSDMA_PERF_SEL_CMD_OP_END = 111 +LSDMA_PERF_SEL_CE_BUSY = 112 +LSDMA_PERF_SEL_CE_BUSY_START = 113 +LSDMA_PERF_SEL_CE_BUSY_END = 114 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117 +LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118 +LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119 +LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120 +LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121 +LSDMA_PERF_SEL_DRAM_ECC = 122 +LSDMA_PERF_SEL_NACK_GEN_ERR = 123 +LSDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' +EFC_SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'EFC_ARGB1555', + 2: 'EFC_RGBA5551', + 3: 'EFC_RGB565', + 4: 'EFC_BGR565', + 5: 'EFC_ARGB4444', + 6: 'EFC_RGBA4444', + 8: 'EFC_ARGB8888', + 9: 'EFC_RGBA8888', + 10: 'EFC_ARGB2101010', + 11: 'EFC_RGBA1010102', + 12: 'EFC_AYCrCb8888', + 13: 'EFC_YCrCbA8888', + 14: 'EFC_ACrYCb8888', + 15: 'EFC_CrYCbA8888', + 16: 'EFC_ARGB16161616_10MSB', + 17: 'EFC_RGBA16161616_10MSB', + 18: 'EFC_ARGB16161616_10LSB', + 19: 'EFC_RGBA16161616_10LSB', + 20: 'EFC_ARGB16161616_12MSB', + 21: 'EFC_RGBA16161616_12MSB', + 22: 'EFC_ARGB16161616_12LSB', + 23: 'EFC_RGBA16161616_12LSB', + 24: 'EFC_ARGB16161616_FLOAT', + 25: 'EFC_RGBA16161616_FLOAT', + 26: 'EFC_ARGB16161616_UNORM', + 27: 'EFC_RGBA16161616_UNORM', + 28: 'EFC_ARGB16161616_SNORM', + 29: 'EFC_RGBA16161616_SNORM', + 32: 'EFC_AYCrCb16161616_10MSB', + 33: 'EFC_AYCrCb16161616_10LSB', + 34: 'EFC_YCrCbA16161616_10MSB', + 35: 'EFC_YCrCbA16161616_10LSB', + 36: 'EFC_ACrYCb16161616_10MSB', + 37: 'EFC_ACrYCb16161616_10LSB', + 38: 'EFC_CrYCbA16161616_10MSB', + 39: 'EFC_CrYCbA16161616_10LSB', + 40: 'EFC_AYCrCb16161616_12MSB', + 41: 'EFC_AYCrCb16161616_12LSB', + 42: 'EFC_YCrCbA16161616_12MSB', + 43: 'EFC_YCrCbA16161616_12LSB', + 44: 'EFC_ACrYCb16161616_12MSB', + 45: 'EFC_ACrYCb16161616_12LSB', + 46: 'EFC_CrYCbA16161616_12MSB', + 47: 'EFC_CrYCbA16161616_12LSB', + 64: 'EFC_Y8_CrCb88_420_PLANAR', + 65: 'EFC_Y8_CbCr88_420_PLANAR', + 66: 'EFC_Y10_CrCb1010_420_PLANAR', + 67: 'EFC_Y10_CbCr1010_420_PLANAR', + 68: 'EFC_Y12_CrCb1212_420_PLANAR', + 69: 'EFC_Y12_CbCr1212_420_PLANAR', + 72: 'EFC_YCrYCb8888_422_PACKED', + 73: 'EFC_YCbYCr8888_422_PACKED', + 74: 'EFC_CrYCbY8888_422_PACKED', + 75: 'EFC_CbYCrY8888_422_PACKED', + 76: 'EFC_YCrYCb10101010_422_PACKED', + 77: 'EFC_YCbYCr10101010_422_PACKED', + 78: 'EFC_CrYCbY10101010_422_PACKED', + 79: 'EFC_CbYCrY10101010_422_PACKED', + 80: 'EFC_YCrYCb12121212_422_PACKED', + 81: 'EFC_YCbYCr12121212_422_PACKED', + 82: 'EFC_CrYCbY12121212_422_PACKED', + 83: 'EFC_CbYCrY12121212_422_PACKED', + 112: 'EFC_RGB111110_FIX', + 113: 'EFC_BGR101111_FIX', + 114: 'EFC_ACrYCb2101010', + 115: 'EFC_CrYCbA1010102', + 118: 'EFC_RGB111110_FLOAT', + 119: 'EFC_BGR101111_FLOAT', + 120: 'EFC_MONO_8', + 121: 'EFC_MONO_10MSB', + 122: 'EFC_MONO_10LSB', + 123: 'EFC_MONO_12MSB', + 124: 'EFC_MONO_12LSB', + 125: 'EFC_MONO_16', +} +EFC_ARGB1555 = 1 +EFC_RGBA5551 = 2 +EFC_RGB565 = 3 +EFC_BGR565 = 4 +EFC_ARGB4444 = 5 +EFC_RGBA4444 = 6 +EFC_ARGB8888 = 8 +EFC_RGBA8888 = 9 +EFC_ARGB2101010 = 10 +EFC_RGBA1010102 = 11 +EFC_AYCrCb8888 = 12 +EFC_YCrCbA8888 = 13 +EFC_ACrYCb8888 = 14 +EFC_CrYCbA8888 = 15 +EFC_ARGB16161616_10MSB = 16 +EFC_RGBA16161616_10MSB = 17 +EFC_ARGB16161616_10LSB = 18 +EFC_RGBA16161616_10LSB = 19 +EFC_ARGB16161616_12MSB = 20 +EFC_RGBA16161616_12MSB = 21 +EFC_ARGB16161616_12LSB = 22 +EFC_RGBA16161616_12LSB = 23 +EFC_ARGB16161616_FLOAT = 24 +EFC_RGBA16161616_FLOAT = 25 +EFC_ARGB16161616_UNORM = 26 +EFC_RGBA16161616_UNORM = 27 +EFC_ARGB16161616_SNORM = 28 +EFC_RGBA16161616_SNORM = 29 +EFC_AYCrCb16161616_10MSB = 32 +EFC_AYCrCb16161616_10LSB = 33 +EFC_YCrCbA16161616_10MSB = 34 +EFC_YCrCbA16161616_10LSB = 35 +EFC_ACrYCb16161616_10MSB = 36 +EFC_ACrYCb16161616_10LSB = 37 +EFC_CrYCbA16161616_10MSB = 38 +EFC_CrYCbA16161616_10LSB = 39 +EFC_AYCrCb16161616_12MSB = 40 +EFC_AYCrCb16161616_12LSB = 41 +EFC_YCrCbA16161616_12MSB = 42 +EFC_YCrCbA16161616_12LSB = 43 +EFC_ACrYCb16161616_12MSB = 44 +EFC_ACrYCb16161616_12LSB = 45 +EFC_CrYCbA16161616_12MSB = 46 +EFC_CrYCbA16161616_12LSB = 47 +EFC_Y8_CrCb88_420_PLANAR = 64 +EFC_Y8_CbCr88_420_PLANAR = 65 +EFC_Y10_CrCb1010_420_PLANAR = 66 +EFC_Y10_CbCr1010_420_PLANAR = 67 +EFC_Y12_CrCb1212_420_PLANAR = 68 +EFC_Y12_CbCr1212_420_PLANAR = 69 +EFC_YCrYCb8888_422_PACKED = 72 +EFC_YCbYCr8888_422_PACKED = 73 +EFC_CrYCbY8888_422_PACKED = 74 +EFC_CbYCrY8888_422_PACKED = 75 +EFC_YCrYCb10101010_422_PACKED = 76 +EFC_YCbYCr10101010_422_PACKED = 77 +EFC_CrYCbY10101010_422_PACKED = 78 +EFC_CbYCrY10101010_422_PACKED = 79 +EFC_YCrYCb12121212_422_PACKED = 80 +EFC_YCbYCr12121212_422_PACKED = 81 +EFC_CrYCbY12121212_422_PACKED = 82 +EFC_CbYCrY12121212_422_PACKED = 83 +EFC_RGB111110_FIX = 112 +EFC_BGR101111_FIX = 113 +EFC_ACrYCb2101010 = 114 +EFC_CrYCbA1010102 = 115 +EFC_RGB111110_FLOAT = 118 +EFC_BGR101111_FLOAT = 119 +EFC_MONO_8 = 120 +EFC_MONO_10MSB = 121 +EFC_MONO_10LSB = 122 +EFC_MONO_12MSB = 123 +EFC_MONO_12LSB = 124 +EFC_MONO_16 = 125 +EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum +_PSP_TEE_GFX_IF_H_ = True # macro +PSP_GFX_CMD_BUF_VERSION = 0x00000001 # macro +GFX_CMD_STATUS_MASK = 0x0000FFFF # macro +GFX_CMD_ID_MASK = 0x000F0000 # macro +GFX_CMD_RESERVED_MASK = 0x7FF00000 # macro +GFX_CMD_RESPONSE_MASK = 0x80000000 # macro +C2PMSG_CMD_GFX_USB_PD_FW_VER = 0x2000000 # macro +GFX_FLAG_RESPONSE = 0x80000000 # macro +GFX_BUF_MAX_DESC = 64 # macro +FRAME_TYPE_DESTROY = 1 # macro +PSP_ERR_UNKNOWN_COMMAND = 0x00000100 # macro + +# values for enumeration 'psp_gfx_crtl_cmd_id' +psp_gfx_crtl_cmd_id__enumvalues = { + 65536: 'GFX_CTRL_CMD_ID_INIT_RBI_RING', + 131072: 'GFX_CTRL_CMD_ID_INIT_GPCOM_RING', + 196608: 'GFX_CTRL_CMD_ID_DESTROY_RINGS', + 262144: 'GFX_CTRL_CMD_ID_CAN_INIT_RINGS', + 327680: 'GFX_CTRL_CMD_ID_ENABLE_INT', + 393216: 'GFX_CTRL_CMD_ID_DISABLE_INT', + 458752: 'GFX_CTRL_CMD_ID_MODE1_RST', + 524288: 'GFX_CTRL_CMD_ID_GBR_IH_SET', + 589824: 'GFX_CTRL_CMD_ID_CONSUME_CMD', + 786432: 'GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING', + 983040: 'GFX_CTRL_CMD_ID_MAX', +} +GFX_CTRL_CMD_ID_INIT_RBI_RING = 65536 +GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 131072 +GFX_CTRL_CMD_ID_DESTROY_RINGS = 196608 +GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 262144 +GFX_CTRL_CMD_ID_ENABLE_INT = 327680 +GFX_CTRL_CMD_ID_DISABLE_INT = 393216 +GFX_CTRL_CMD_ID_MODE1_RST = 458752 +GFX_CTRL_CMD_ID_GBR_IH_SET = 524288 +GFX_CTRL_CMD_ID_CONSUME_CMD = 589824 +GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 786432 +GFX_CTRL_CMD_ID_MAX = 983040 +psp_gfx_crtl_cmd_id = ctypes.c_uint32 # enum +class struct_psp_gfx_ctrl(Structure): + pass + +struct_psp_gfx_ctrl._pack_ = 1 # source:False +struct_psp_gfx_ctrl._fields_ = [ + ('cmd_resp', ctypes.c_uint32), + ('rbi_wptr', ctypes.c_uint32), + ('rbi_rptr', ctypes.c_uint32), + ('gpcom_wptr', ctypes.c_uint32), + ('gpcom_rptr', ctypes.c_uint32), + ('ring_addr_lo', ctypes.c_uint32), + ('ring_addr_hi', ctypes.c_uint32), + ('ring_buf_size', ctypes.c_uint32), +] + + +# values for enumeration 'psp_gfx_cmd_id' +psp_gfx_cmd_id__enumvalues = { + 1: 'GFX_CMD_ID_LOAD_TA', + 2: 'GFX_CMD_ID_UNLOAD_TA', + 3: 'GFX_CMD_ID_INVOKE_CMD', + 4: 'GFX_CMD_ID_LOAD_ASD', + 5: 'GFX_CMD_ID_SETUP_TMR', + 6: 'GFX_CMD_ID_LOAD_IP_FW', + 7: 'GFX_CMD_ID_DESTROY_TMR', + 8: 'GFX_CMD_ID_SAVE_RESTORE', + 9: 'GFX_CMD_ID_SETUP_VMR', + 10: 'GFX_CMD_ID_DESTROY_VMR', + 11: 'GFX_CMD_ID_PROG_REG', + 15: 'GFX_CMD_ID_GET_FW_ATTESTATION', + 32: 'GFX_CMD_ID_LOAD_TOC', + 33: 'GFX_CMD_ID_AUTOLOAD_RLC', + 34: 'GFX_CMD_ID_BOOT_CFG', + 39: 'GFX_CMD_ID_SRIOV_SPATIAL_PART', +} +GFX_CMD_ID_LOAD_TA = 1 +GFX_CMD_ID_UNLOAD_TA = 2 +GFX_CMD_ID_INVOKE_CMD = 3 +GFX_CMD_ID_LOAD_ASD = 4 +GFX_CMD_ID_SETUP_TMR = 5 +GFX_CMD_ID_LOAD_IP_FW = 6 +GFX_CMD_ID_DESTROY_TMR = 7 +GFX_CMD_ID_SAVE_RESTORE = 8 +GFX_CMD_ID_SETUP_VMR = 9 +GFX_CMD_ID_DESTROY_VMR = 10 +GFX_CMD_ID_PROG_REG = 11 +GFX_CMD_ID_GET_FW_ATTESTATION = 15 +GFX_CMD_ID_LOAD_TOC = 32 +GFX_CMD_ID_AUTOLOAD_RLC = 33 +GFX_CMD_ID_BOOT_CFG = 34 +GFX_CMD_ID_SRIOV_SPATIAL_PART = 39 +psp_gfx_cmd_id = ctypes.c_uint32 # enum + +# values for enumeration 'psp_gfx_boot_config_cmd' +psp_gfx_boot_config_cmd__enumvalues = { + 1: 'BOOTCFG_CMD_SET', + 2: 'BOOTCFG_CMD_GET', + 3: 'BOOTCFG_CMD_INVALIDATE', +} +BOOTCFG_CMD_SET = 1 +BOOTCFG_CMD_GET = 2 +BOOTCFG_CMD_INVALIDATE = 3 +psp_gfx_boot_config_cmd = ctypes.c_uint32 # enum + +# values for enumeration 'psp_gfx_boot_config' +psp_gfx_boot_config__enumvalues = { + 1: 'BOOT_CONFIG_GECC', +} +BOOT_CONFIG_GECC = 1 +psp_gfx_boot_config = ctypes.c_uint32 # enum +class struct_psp_gfx_cmd_load_ta(Structure): + pass + +struct_psp_gfx_cmd_load_ta._pack_ = 1 # source:False +struct_psp_gfx_cmd_load_ta._fields_ = [ + ('app_phy_addr_lo', ctypes.c_uint32), + ('app_phy_addr_hi', ctypes.c_uint32), + ('app_len', ctypes.c_uint32), + ('cmd_buf_phy_addr_lo', ctypes.c_uint32), + ('cmd_buf_phy_addr_hi', ctypes.c_uint32), + ('cmd_buf_len', ctypes.c_uint32), +] + +class struct_psp_gfx_cmd_unload_ta(Structure): + pass + +struct_psp_gfx_cmd_unload_ta._pack_ = 1 # source:False +struct_psp_gfx_cmd_unload_ta._fields_ = [ + ('session_id', ctypes.c_uint32), +] + +class struct_psp_gfx_buf_desc(Structure): + pass + +struct_psp_gfx_buf_desc._pack_ = 1 # source:False +struct_psp_gfx_buf_desc._fields_ = [ + ('buf_phy_addr_lo', ctypes.c_uint32), + ('buf_phy_addr_hi', ctypes.c_uint32), + ('buf_size', ctypes.c_uint32), +] + +class struct_psp_gfx_buf_list(Structure): + pass + +struct_psp_gfx_buf_list._pack_ = 1 # source:False +struct_psp_gfx_buf_list._fields_ = [ + ('num_desc', ctypes.c_uint32), + ('total_size', ctypes.c_uint32), + ('buf_desc', struct_psp_gfx_buf_desc * 64), +] + +class struct_psp_gfx_cmd_invoke_cmd(Structure): + pass + +struct_psp_gfx_cmd_invoke_cmd._pack_ = 1 # source:False +struct_psp_gfx_cmd_invoke_cmd._fields_ = [ + ('session_id', ctypes.c_uint32), + ('ta_cmd_id', ctypes.c_uint32), + ('buf', struct_psp_gfx_buf_list), +] + +class struct_psp_gfx_cmd_setup_tmr(Structure): + pass + +class union_psp_gfx_cmd_setup_tmr_0(Union): + pass + +class struct_psp_gfx_cmd_setup_tmr_0_bitfield(Structure): + pass + +struct_psp_gfx_cmd_setup_tmr_0_bitfield._pack_ = 1 # source:False +struct_psp_gfx_cmd_setup_tmr_0_bitfield._fields_ = [ + ('sriov_enabled', ctypes.c_uint32, 1), + ('virt_phy_addr', ctypes.c_uint32, 1), + ('reserved', ctypes.c_uint32, 30), +] + +union_psp_gfx_cmd_setup_tmr_0._pack_ = 1 # source:False +union_psp_gfx_cmd_setup_tmr_0._fields_ = [ + ('bitfield', struct_psp_gfx_cmd_setup_tmr_0_bitfield), + ('tmr_flags', ctypes.c_uint32), +] + +struct_psp_gfx_cmd_setup_tmr._pack_ = 1 # source:False +struct_psp_gfx_cmd_setup_tmr._anonymous_ = ('_0',) +struct_psp_gfx_cmd_setup_tmr._fields_ = [ + ('buf_phy_addr_lo', ctypes.c_uint32), + ('buf_phy_addr_hi', ctypes.c_uint32), + ('buf_size', ctypes.c_uint32), + ('_0', union_psp_gfx_cmd_setup_tmr_0), + ('system_phy_addr_lo', ctypes.c_uint32), + ('system_phy_addr_hi', ctypes.c_uint32), +] + + +# values for enumeration 'psp_gfx_fw_type' +psp_gfx_fw_type__enumvalues = { + 0: 'GFX_FW_TYPE_NONE', + 1: 'GFX_FW_TYPE_CP_ME', + 2: 'GFX_FW_TYPE_CP_PFP', + 3: 'GFX_FW_TYPE_CP_CE', + 4: 'GFX_FW_TYPE_CP_MEC', + 5: 'GFX_FW_TYPE_CP_MEC_ME1', + 6: 'GFX_FW_TYPE_CP_MEC_ME2', + 7: 'GFX_FW_TYPE_RLC_V', + 8: 'GFX_FW_TYPE_RLC_G', + 9: 'GFX_FW_TYPE_SDMA0', + 10: 'GFX_FW_TYPE_SDMA1', + 11: 'GFX_FW_TYPE_DMCU_ERAM', + 12: 'GFX_FW_TYPE_DMCU_ISR', + 13: 'GFX_FW_TYPE_VCN', + 14: 'GFX_FW_TYPE_UVD', + 15: 'GFX_FW_TYPE_VCE', + 16: 'GFX_FW_TYPE_ISP', + 17: 'GFX_FW_TYPE_ACP', + 18: 'GFX_FW_TYPE_SMU', + 19: 'GFX_FW_TYPE_MMSCH', + 20: 'GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM', + 21: 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM', + 22: 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL', + 23: 'GFX_FW_TYPE_UVD1', + 24: 'GFX_FW_TYPE_TOC', + 25: 'GFX_FW_TYPE_RLC_P', + 26: 'GFX_FW_TYPE_RLC_IRAM', + 27: 'GFX_FW_TYPE_GLOBAL_TAP_DELAYS', + 28: 'GFX_FW_TYPE_SE0_TAP_DELAYS', + 29: 'GFX_FW_TYPE_SE1_TAP_DELAYS', + 30: 'GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS', + 31: 'GFX_FW_TYPE_SDMA0_JT', + 32: 'GFX_FW_TYPE_SDMA1_JT', + 33: 'GFX_FW_TYPE_CP_MES', + 34: 'GFX_FW_TYPE_MES_STACK', + 35: 'GFX_FW_TYPE_RLC_SRM_DRAM_SR', + 36: 'GFX_FW_TYPE_RLCG_SCRATCH_SR', + 37: 'GFX_FW_TYPE_RLCP_SCRATCH_SR', + 38: 'GFX_FW_TYPE_RLCV_SCRATCH_SR', + 39: 'GFX_FW_TYPE_RLX6_DRAM_SR', + 40: 'GFX_FW_TYPE_SDMA0_PG_CONTEXT', + 41: 'GFX_FW_TYPE_SDMA1_PG_CONTEXT', + 42: 'GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM', + 43: 'GFX_FW_TYPE_SE0_MUX_SELECT_RAM', + 44: 'GFX_FW_TYPE_SE1_MUX_SELECT_RAM', + 45: 'GFX_FW_TYPE_ACCUM_CTRL_RAM', + 46: 'GFX_FW_TYPE_RLCP_CAM', + 47: 'GFX_FW_TYPE_RLC_SPP_CAM_EXT', + 48: 'GFX_FW_TYPE_RLC_DRAM_BOOT', + 49: 'GFX_FW_TYPE_VCN0_RAM', + 50: 'GFX_FW_TYPE_VCN1_RAM', + 51: 'GFX_FW_TYPE_DMUB', + 52: 'GFX_FW_TYPE_SDMA2', + 53: 'GFX_FW_TYPE_SDMA3', + 54: 'GFX_FW_TYPE_SDMA4', + 55: 'GFX_FW_TYPE_SDMA5', + 56: 'GFX_FW_TYPE_SDMA6', + 57: 'GFX_FW_TYPE_SDMA7', + 58: 'GFX_FW_TYPE_VCN1', + 62: 'GFX_FW_TYPE_CAP', + 65: 'GFX_FW_TYPE_SE2_TAP_DELAYS', + 66: 'GFX_FW_TYPE_SE3_TAP_DELAYS', + 67: 'GFX_FW_TYPE_REG_LIST', + 68: 'GFX_FW_TYPE_IMU_I', + 69: 'GFX_FW_TYPE_IMU_D', + 70: 'GFX_FW_TYPE_LSDMA', + 71: 'GFX_FW_TYPE_SDMA_UCODE_TH0', + 72: 'GFX_FW_TYPE_SDMA_UCODE_TH1', + 73: 'GFX_FW_TYPE_PPTABLE', + 74: 'GFX_FW_TYPE_DISCRETE_USB4', + 75: 'GFX_FW_TYPE_TA', + 76: 'GFX_FW_TYPE_RS64_MES', + 77: 'GFX_FW_TYPE_RS64_MES_STACK', + 78: 'GFX_FW_TYPE_RS64_KIQ', + 79: 'GFX_FW_TYPE_RS64_KIQ_STACK', + 80: 'GFX_FW_TYPE_ISP_DATA', + 81: 'GFX_FW_TYPE_CP_MES_KIQ', + 82: 'GFX_FW_TYPE_MES_KIQ_STACK', + 83: 'GFX_FW_TYPE_UMSCH_DATA', + 84: 'GFX_FW_TYPE_UMSCH_UCODE', + 85: 'GFX_FW_TYPE_UMSCH_CMD_BUFFER', + 86: 'GFX_FW_TYPE_USB_DP_COMBO_PHY', + 87: 'GFX_FW_TYPE_RS64_PFP', + 88: 'GFX_FW_TYPE_RS64_ME', + 89: 'GFX_FW_TYPE_RS64_MEC', + 90: 'GFX_FW_TYPE_RS64_PFP_P0_STACK', + 91: 'GFX_FW_TYPE_RS64_PFP_P1_STACK', + 92: 'GFX_FW_TYPE_RS64_ME_P0_STACK', + 93: 'GFX_FW_TYPE_RS64_ME_P1_STACK', + 94: 'GFX_FW_TYPE_RS64_MEC_P0_STACK', + 95: 'GFX_FW_TYPE_RS64_MEC_P1_STACK', + 96: 'GFX_FW_TYPE_RS64_MEC_P2_STACK', + 97: 'GFX_FW_TYPE_RS64_MEC_P3_STACK', + 100: 'GFX_FW_TYPE_VPEC_FW1', + 101: 'GFX_FW_TYPE_VPEC_FW2', + 102: 'GFX_FW_TYPE_VPE', + 128: 'GFX_FW_TYPE_JPEG_RAM', + 129: 'GFX_FW_TYPE_P2S_TABLE', + 130: 'GFX_FW_TYPE_MAX', +} +GFX_FW_TYPE_NONE = 0 +GFX_FW_TYPE_CP_ME = 1 +GFX_FW_TYPE_CP_PFP = 2 +GFX_FW_TYPE_CP_CE = 3 +GFX_FW_TYPE_CP_MEC = 4 +GFX_FW_TYPE_CP_MEC_ME1 = 5 +GFX_FW_TYPE_CP_MEC_ME2 = 6 +GFX_FW_TYPE_RLC_V = 7 +GFX_FW_TYPE_RLC_G = 8 +GFX_FW_TYPE_SDMA0 = 9 +GFX_FW_TYPE_SDMA1 = 10 +GFX_FW_TYPE_DMCU_ERAM = 11 +GFX_FW_TYPE_DMCU_ISR = 12 +GFX_FW_TYPE_VCN = 13 +GFX_FW_TYPE_UVD = 14 +GFX_FW_TYPE_VCE = 15 +GFX_FW_TYPE_ISP = 16 +GFX_FW_TYPE_ACP = 17 +GFX_FW_TYPE_SMU = 18 +GFX_FW_TYPE_MMSCH = 19 +GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20 +GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21 +GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22 +GFX_FW_TYPE_UVD1 = 23 +GFX_FW_TYPE_TOC = 24 +GFX_FW_TYPE_RLC_P = 25 +GFX_FW_TYPE_RLC_IRAM = 26 +GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27 +GFX_FW_TYPE_SE0_TAP_DELAYS = 28 +GFX_FW_TYPE_SE1_TAP_DELAYS = 29 +GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30 +GFX_FW_TYPE_SDMA0_JT = 31 +GFX_FW_TYPE_SDMA1_JT = 32 +GFX_FW_TYPE_CP_MES = 33 +GFX_FW_TYPE_MES_STACK = 34 +GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35 +GFX_FW_TYPE_RLCG_SCRATCH_SR = 36 +GFX_FW_TYPE_RLCP_SCRATCH_SR = 37 +GFX_FW_TYPE_RLCV_SCRATCH_SR = 38 +GFX_FW_TYPE_RLX6_DRAM_SR = 39 +GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40 +GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41 +GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42 +GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43 +GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44 +GFX_FW_TYPE_ACCUM_CTRL_RAM = 45 +GFX_FW_TYPE_RLCP_CAM = 46 +GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47 +GFX_FW_TYPE_RLC_DRAM_BOOT = 48 +GFX_FW_TYPE_VCN0_RAM = 49 +GFX_FW_TYPE_VCN1_RAM = 50 +GFX_FW_TYPE_DMUB = 51 +GFX_FW_TYPE_SDMA2 = 52 +GFX_FW_TYPE_SDMA3 = 53 +GFX_FW_TYPE_SDMA4 = 54 +GFX_FW_TYPE_SDMA5 = 55 +GFX_FW_TYPE_SDMA6 = 56 +GFX_FW_TYPE_SDMA7 = 57 +GFX_FW_TYPE_VCN1 = 58 +GFX_FW_TYPE_CAP = 62 +GFX_FW_TYPE_SE2_TAP_DELAYS = 65 +GFX_FW_TYPE_SE3_TAP_DELAYS = 66 +GFX_FW_TYPE_REG_LIST = 67 +GFX_FW_TYPE_IMU_I = 68 +GFX_FW_TYPE_IMU_D = 69 +GFX_FW_TYPE_LSDMA = 70 +GFX_FW_TYPE_SDMA_UCODE_TH0 = 71 +GFX_FW_TYPE_SDMA_UCODE_TH1 = 72 +GFX_FW_TYPE_PPTABLE = 73 +GFX_FW_TYPE_DISCRETE_USB4 = 74 +GFX_FW_TYPE_TA = 75 +GFX_FW_TYPE_RS64_MES = 76 +GFX_FW_TYPE_RS64_MES_STACK = 77 +GFX_FW_TYPE_RS64_KIQ = 78 +GFX_FW_TYPE_RS64_KIQ_STACK = 79 +GFX_FW_TYPE_ISP_DATA = 80 +GFX_FW_TYPE_CP_MES_KIQ = 81 +GFX_FW_TYPE_MES_KIQ_STACK = 82 +GFX_FW_TYPE_UMSCH_DATA = 83 +GFX_FW_TYPE_UMSCH_UCODE = 84 +GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85 +GFX_FW_TYPE_USB_DP_COMBO_PHY = 86 +GFX_FW_TYPE_RS64_PFP = 87 +GFX_FW_TYPE_RS64_ME = 88 +GFX_FW_TYPE_RS64_MEC = 89 +GFX_FW_TYPE_RS64_PFP_P0_STACK = 90 +GFX_FW_TYPE_RS64_PFP_P1_STACK = 91 +GFX_FW_TYPE_RS64_ME_P0_STACK = 92 +GFX_FW_TYPE_RS64_ME_P1_STACK = 93 +GFX_FW_TYPE_RS64_MEC_P0_STACK = 94 +GFX_FW_TYPE_RS64_MEC_P1_STACK = 95 +GFX_FW_TYPE_RS64_MEC_P2_STACK = 96 +GFX_FW_TYPE_RS64_MEC_P3_STACK = 97 +GFX_FW_TYPE_VPEC_FW1 = 100 +GFX_FW_TYPE_VPEC_FW2 = 101 +GFX_FW_TYPE_VPE = 102 +GFX_FW_TYPE_JPEG_RAM = 128 +GFX_FW_TYPE_P2S_TABLE = 129 +GFX_FW_TYPE_MAX = 130 +psp_gfx_fw_type = ctypes.c_uint32 # enum +class struct_psp_gfx_cmd_load_ip_fw(Structure): + pass + +struct_psp_gfx_cmd_load_ip_fw._pack_ = 1 # source:False +struct_psp_gfx_cmd_load_ip_fw._fields_ = [ + ('fw_phy_addr_lo', ctypes.c_uint32), + ('fw_phy_addr_hi', ctypes.c_uint32), + ('fw_size', ctypes.c_uint32), + ('fw_type', psp_gfx_fw_type), +] + +class struct_psp_gfx_cmd_save_restore_ip_fw(Structure): + pass + +struct_psp_gfx_cmd_save_restore_ip_fw._pack_ = 1 # source:False +struct_psp_gfx_cmd_save_restore_ip_fw._fields_ = [ + ('save_fw', ctypes.c_uint32), + ('save_restore_addr_lo', ctypes.c_uint32), + ('save_restore_addr_hi', ctypes.c_uint32), + ('buf_size', ctypes.c_uint32), + ('fw_type', psp_gfx_fw_type), +] + +class struct_psp_gfx_cmd_reg_prog(Structure): + pass + +struct_psp_gfx_cmd_reg_prog._pack_ = 1 # source:False +struct_psp_gfx_cmd_reg_prog._fields_ = [ + ('reg_value', ctypes.c_uint32), + ('reg_id', ctypes.c_uint32), +] + +class struct_psp_gfx_cmd_load_toc(Structure): + pass + +struct_psp_gfx_cmd_load_toc._pack_ = 1 # source:False +struct_psp_gfx_cmd_load_toc._fields_ = [ + ('toc_phy_addr_lo', ctypes.c_uint32), + ('toc_phy_addr_hi', ctypes.c_uint32), + ('toc_size', ctypes.c_uint32), +] + +class struct_psp_gfx_cmd_boot_cfg(Structure): + pass + +struct_psp_gfx_cmd_boot_cfg._pack_ = 1 # source:False +struct_psp_gfx_cmd_boot_cfg._fields_ = [ + ('timestamp', ctypes.c_uint32), + ('sub_cmd', psp_gfx_boot_config_cmd), + ('boot_config', ctypes.c_uint32), + ('boot_config_valid', ctypes.c_uint32), +] + +class struct_psp_gfx_cmd_sriov_spatial_part(Structure): + pass + +struct_psp_gfx_cmd_sriov_spatial_part._pack_ = 1 # source:False +struct_psp_gfx_cmd_sriov_spatial_part._fields_ = [ + ('mode', ctypes.c_uint32), + ('override_ips', ctypes.c_uint32), + ('override_xcds_avail', ctypes.c_uint32), + ('override_this_aid', ctypes.c_uint32), +] + +class union_psp_gfx_commands(Union): + pass + +union_psp_gfx_commands._pack_ = 1 # source:False +union_psp_gfx_commands._fields_ = [ + ('cmd_load_ta', struct_psp_gfx_cmd_load_ta), + ('cmd_unload_ta', struct_psp_gfx_cmd_unload_ta), + ('cmd_invoke_cmd', struct_psp_gfx_cmd_invoke_cmd), + ('cmd_setup_tmr', struct_psp_gfx_cmd_setup_tmr), + ('cmd_load_ip_fw', struct_psp_gfx_cmd_load_ip_fw), + ('cmd_save_restore_ip_fw', struct_psp_gfx_cmd_save_restore_ip_fw), + ('cmd_setup_reg_prog', struct_psp_gfx_cmd_reg_prog), + ('cmd_setup_vmr', struct_psp_gfx_cmd_setup_tmr), + ('cmd_load_toc', struct_psp_gfx_cmd_load_toc), + ('boot_cfg', struct_psp_gfx_cmd_boot_cfg), + ('cmd_spatial_part', struct_psp_gfx_cmd_sriov_spatial_part), + ('PADDING_0', ctypes.c_ubyte * 768), +] + +class struct_psp_gfx_uresp_reserved(Structure): + pass + +struct_psp_gfx_uresp_reserved._pack_ = 1 # source:False +struct_psp_gfx_uresp_reserved._fields_ = [ + ('reserved', ctypes.c_uint32 * 8), +] + +class struct_psp_gfx_uresp_fwar_db_info(Structure): + pass + +struct_psp_gfx_uresp_fwar_db_info._pack_ = 1 # source:False +struct_psp_gfx_uresp_fwar_db_info._fields_ = [ + ('fwar_db_addr_lo', ctypes.c_uint32), + ('fwar_db_addr_hi', ctypes.c_uint32), +] + +class struct_psp_gfx_uresp_bootcfg(Structure): + pass + +struct_psp_gfx_uresp_bootcfg._pack_ = 1 # source:False +struct_psp_gfx_uresp_bootcfg._fields_ = [ + ('boot_cfg', ctypes.c_uint32), +] + +class union_psp_gfx_uresp(Union): + pass + +union_psp_gfx_uresp._pack_ = 1 # source:False +union_psp_gfx_uresp._fields_ = [ + ('reserved', struct_psp_gfx_uresp_reserved), + ('boot_cfg', struct_psp_gfx_uresp_bootcfg), + ('fwar_db_info', struct_psp_gfx_uresp_fwar_db_info), + ('PADDING_0', ctypes.c_ubyte * 24), +] + +class struct_psp_gfx_resp(Structure): + pass + +struct_psp_gfx_resp._pack_ = 1 # source:False +struct_psp_gfx_resp._fields_ = [ + ('status', ctypes.c_uint32), + ('session_id', ctypes.c_uint32), + ('fw_addr_lo', ctypes.c_uint32), + ('fw_addr_hi', ctypes.c_uint32), + ('tmr_size', ctypes.c_uint32), + ('reserved', ctypes.c_uint32 * 11), + ('uresp', union_psp_gfx_uresp), +] + +class struct_psp_gfx_cmd_resp(Structure): + pass + +struct_psp_gfx_cmd_resp._pack_ = 1 # source:False +struct_psp_gfx_cmd_resp._fields_ = [ + ('buf_size', ctypes.c_uint32), + ('buf_version', ctypes.c_uint32), + ('cmd_id', ctypes.c_uint32), + ('resp_buf_addr_lo', ctypes.c_uint32), + ('resp_buf_addr_hi', ctypes.c_uint32), + ('resp_offset', ctypes.c_uint32), + ('resp_buf_size', ctypes.c_uint32), + ('cmd', union_psp_gfx_commands), + ('reserved_1', ctypes.c_ubyte * 52), + ('resp', struct_psp_gfx_resp), + ('reserved_2', ctypes.c_ubyte * 64), +] + +class struct_psp_gfx_rb_frame(Structure): + pass + +struct_psp_gfx_rb_frame._pack_ = 1 # source:False +struct_psp_gfx_rb_frame._fields_ = [ + ('cmd_buf_addr_lo', ctypes.c_uint32), + ('cmd_buf_addr_hi', ctypes.c_uint32), + ('cmd_buf_size', ctypes.c_uint32), + ('fence_addr_lo', ctypes.c_uint32), + ('fence_addr_hi', ctypes.c_uint32), + ('fence_value', ctypes.c_uint32), + ('sid_lo', ctypes.c_uint32), + ('sid_hi', ctypes.c_uint32), + ('vmid', ctypes.c_ubyte), + ('frame_type', ctypes.c_ubyte), + ('reserved1', ctypes.c_ubyte * 2), + ('reserved2', ctypes.c_uint32 * 7), +] + + +# values for enumeration 'tee_error_code' +tee_error_code__enumvalues = { + 0: 'TEE_SUCCESS', + 4294901770: 'TEE_ERROR_NOT_SUPPORTED', +} +TEE_SUCCESS = 0 +TEE_ERROR_NOT_SUPPORTED = 4294901770 +tee_error_code = ctypes.c_uint32 # enum +__AMDGPU_PSP_H__ = True # macro +PSP_FENCE_BUFFER_SIZE = 0x1000 # macro +PSP_CMD_BUFFER_SIZE = 0x1000 # macro +PSP_1_MEG = 0x100000 # macro +# def PSP_TMR_SIZE(adev): # macro +# return ((adev)->asic_type==CHIP_ALDEBARAN?0x800000:0x400000) +PSP_TMR_ALIGNMENT = 0x100000 # macro +PSP_FW_NAME_LEN = 0x24 # macro +AMDGPU_XGMI_MAX_CONNECTED_NODES = 64 # macro +MEM_TRAIN_SYSTEM_SIGNATURE = 0x54534942 # macro +GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES = 0x1000 # macro +GDDR6_MEM_TRAINING_OFFSET = 0x8000 # macro +BIST_MEM_TRAINING_ENCROACHED_SIZE = 0x2000000 # macro +PSP_RUNTIME_DB_SIZE_IN_BYTES = 0x10000 # macro +PSP_RUNTIME_DB_OFFSET = 0x100000 # macro +PSP_RUNTIME_DB_COOKIE_ID = 0x0ed5 # macro +PSP_RUNTIME_DB_VER_1 = 0x0100 # macro +PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT = 0x40 # macro + +# values for enumeration 'psp_shared_mem_size' +psp_shared_mem_size__enumvalues = { + 0: 'PSP_ASD_SHARED_MEM_SIZE', + 16384: 'PSP_XGMI_SHARED_MEM_SIZE', + 16384: 'PSP_RAS_SHARED_MEM_SIZE', + 16384: 'PSP_HDCP_SHARED_MEM_SIZE', + 16384: 'PSP_DTM_SHARED_MEM_SIZE', + 16384: 'PSP_RAP_SHARED_MEM_SIZE', + 16384: 'PSP_SECUREDISPLAY_SHARED_MEM_SIZE', +} +PSP_ASD_SHARED_MEM_SIZE = 0 +PSP_XGMI_SHARED_MEM_SIZE = 16384 +PSP_RAS_SHARED_MEM_SIZE = 16384 +PSP_HDCP_SHARED_MEM_SIZE = 16384 +PSP_DTM_SHARED_MEM_SIZE = 16384 +PSP_RAP_SHARED_MEM_SIZE = 16384 +PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 16384 +psp_shared_mem_size = ctypes.c_uint32 # enum + +# values for enumeration 'ta_type_id' +ta_type_id__enumvalues = { + 1: 'TA_TYPE_XGMI', + 2: 'TA_TYPE_RAS', + 3: 'TA_TYPE_HDCP', + 4: 'TA_TYPE_DTM', + 5: 'TA_TYPE_RAP', + 6: 'TA_TYPE_SECUREDISPLAY', + 7: 'TA_TYPE_MAX_INDEX', +} +TA_TYPE_XGMI = 1 +TA_TYPE_RAS = 2 +TA_TYPE_HDCP = 3 +TA_TYPE_DTM = 4 +TA_TYPE_RAP = 5 +TA_TYPE_SECUREDISPLAY = 6 +TA_TYPE_MAX_INDEX = 7 +ta_type_id = ctypes.c_uint32 # enum +class struct_psp_context(Structure): + pass + +class struct_psp_xgmi_node_info(Structure): + pass + +class struct_psp_xgmi_topology_info(Structure): + pass + +class struct_psp_bin_desc(Structure): + pass + + +# values for enumeration 'psp_bootloader_cmd' +psp_bootloader_cmd__enumvalues = { + 65536: 'PSP_BL__LOAD_SYSDRV', + 131072: 'PSP_BL__LOAD_SOSDRV', + 524288: 'PSP_BL__LOAD_KEY_DATABASE', + 720896: 'PSP_BL__LOAD_SOCDRV', + 786432: 'PSP_BL__LOAD_DBGDRV', + 786432: 'PSP_BL__LOAD_HADDRV', + 851968: 'PSP_BL__LOAD_INTFDRV', + 917504: 'PSP_BL__LOAD_RASDRV', + 983040: 'PSP_BL__LOAD_IPKEYMGRDRV', + 1048576: 'PSP_BL__DRAM_LONG_TRAIN', + 2097152: 'PSP_BL__DRAM_SHORT_TRAIN', + 268435456: 'PSP_BL__LOAD_TOS_SPL_TABLE', +} +PSP_BL__LOAD_SYSDRV = 65536 +PSP_BL__LOAD_SOSDRV = 131072 +PSP_BL__LOAD_KEY_DATABASE = 524288 +PSP_BL__LOAD_SOCDRV = 720896 +PSP_BL__LOAD_DBGDRV = 786432 +PSP_BL__LOAD_HADDRV = 786432 +PSP_BL__LOAD_INTFDRV = 851968 +PSP_BL__LOAD_RASDRV = 917504 +PSP_BL__LOAD_IPKEYMGRDRV = 983040 +PSP_BL__DRAM_LONG_TRAIN = 1048576 +PSP_BL__DRAM_SHORT_TRAIN = 2097152 +PSP_BL__LOAD_TOS_SPL_TABLE = 268435456 +psp_bootloader_cmd = ctypes.c_uint32 # enum + +# values for enumeration 'psp_ring_type' +psp_ring_type__enumvalues = { + 0: 'PSP_RING_TYPE__INVALID', + 1: 'PSP_RING_TYPE__UM', + 2: 'PSP_RING_TYPE__KM', +} +PSP_RING_TYPE__INVALID = 0 +PSP_RING_TYPE__UM = 1 +PSP_RING_TYPE__KM = 2 +psp_ring_type = ctypes.c_uint32 # enum + +# values for enumeration 'psp_reg_prog_id' +psp_reg_prog_id__enumvalues = { + 0: 'PSP_REG_IH_RB_CNTL', + 1: 'PSP_REG_IH_RB_CNTL_RING1', + 2: 'PSP_REG_IH_RB_CNTL_RING2', + 3: 'PSP_REG_LAST', +} +PSP_REG_IH_RB_CNTL = 0 +PSP_REG_IH_RB_CNTL_RING1 = 1 +PSP_REG_IH_RB_CNTL_RING2 = 2 +PSP_REG_LAST = 3 +psp_reg_prog_id = ctypes.c_uint32 # enum + +# values for enumeration 'psp_memory_training_init_flag' +psp_memory_training_init_flag__enumvalues = { + 0: 'PSP_MEM_TRAIN_NOT_SUPPORT', + 1: 'PSP_MEM_TRAIN_SUPPORT', + 2: 'PSP_MEM_TRAIN_INIT_FAILED', + 4: 'PSP_MEM_TRAIN_RESERVE_SUCCESS', + 8: 'PSP_MEM_TRAIN_INIT_SUCCESS', +} +PSP_MEM_TRAIN_NOT_SUPPORT = 0 +PSP_MEM_TRAIN_SUPPORT = 1 +PSP_MEM_TRAIN_INIT_FAILED = 2 +PSP_MEM_TRAIN_RESERVE_SUCCESS = 4 +PSP_MEM_TRAIN_INIT_SUCCESS = 8 +psp_memory_training_init_flag = ctypes.c_uint32 # enum + +# values for enumeration 'psp_memory_training_ops' +psp_memory_training_ops__enumvalues = { + 1: 'PSP_MEM_TRAIN_SEND_LONG_MSG', + 2: 'PSP_MEM_TRAIN_SAVE', + 4: 'PSP_MEM_TRAIN_RESTORE', + 8: 'PSP_MEM_TRAIN_SEND_SHORT_MSG', + 1: 'PSP_MEM_TRAIN_COLD_BOOT', + 8: 'PSP_MEM_TRAIN_RESUME', +} +PSP_MEM_TRAIN_SEND_LONG_MSG = 1 +PSP_MEM_TRAIN_SAVE = 2 +PSP_MEM_TRAIN_RESTORE = 4 +PSP_MEM_TRAIN_SEND_SHORT_MSG = 8 +PSP_MEM_TRAIN_COLD_BOOT = 1 +PSP_MEM_TRAIN_RESUME = 8 +psp_memory_training_ops = ctypes.c_uint32 # enum + +# values for enumeration 'psp_runtime_entry_type' +psp_runtime_entry_type__enumvalues = { + 0: 'PSP_RUNTIME_ENTRY_TYPE_INVALID', + 1: 'PSP_RUNTIME_ENTRY_TYPE_TEST', + 2: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON', + 3: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL', + 4: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI', + 5: 'PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG', + 6: 'PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS', +} +PSP_RUNTIME_ENTRY_TYPE_INVALID = 0 +PSP_RUNTIME_ENTRY_TYPE_TEST = 1 +PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 2 +PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 3 +PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 4 +PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 5 +PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 6 +psp_runtime_entry_type = ctypes.c_uint32 # enum + +# values for enumeration 'psp_runtime_boot_cfg_feature' +psp_runtime_boot_cfg_feature__enumvalues = { + 1: 'BOOT_CFG_FEATURE_GECC', + 2: 'BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING', +} +BOOT_CFG_FEATURE_GECC = 1 +BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 2 +psp_runtime_boot_cfg_feature = ctypes.c_uint32 # enum + +# values for enumeration 'psp_runtime_scpm_authentication' +psp_runtime_scpm_authentication__enumvalues = { + 0: 'SCPM_DISABLE', + 1: 'SCPM_ENABLE', + 2: 'SCPM_ENABLE_WITH_SCPM_ERR', +} +SCPM_DISABLE = 0 +SCPM_ENABLE = 1 +SCPM_ENABLE_WITH_SCPM_ERR = 2 +psp_runtime_scpm_authentication = ctypes.c_uint32 # enum +__AMDGPU_IRQ_H__ = True # macro +AMDGPU_MAX_IRQ_SRC_ID = 0x100 # macro +AMDGPU_MAX_IRQ_CLIENT_ID = 0x100 # macro +AMDGPU_IRQ_CLIENTID_LEGACY = 0 # macro +AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW = 4 # macro +class struct_amdgpu_device(Structure): + pass + + +# values for enumeration 'amdgpu_interrupt_state' +amdgpu_interrupt_state__enumvalues = { + 0: 'AMDGPU_IRQ_STATE_DISABLE', + 1: 'AMDGPU_IRQ_STATE_ENABLE', +} +AMDGPU_IRQ_STATE_DISABLE = 0 +AMDGPU_IRQ_STATE_ENABLE = 1 +amdgpu_interrupt_state = ctypes.c_uint32 # enum +class struct_amdgpu_iv_entry(Structure): + pass + +struct_amdgpu_iv_entry._pack_ = 1 # source:False +struct_amdgpu_iv_entry._fields_ = [ + ('client_id', ctypes.c_uint32), + ('src_id', ctypes.c_uint32), + ('ring_id', ctypes.c_uint32), + ('vmid', ctypes.c_uint32), + ('vmid_src', ctypes.c_uint32), + ('PADDING_0', ctypes.c_ubyte * 4), + ('timestamp', ctypes.c_uint64), + ('timestamp_src', ctypes.c_uint32), + ('pasid', ctypes.c_uint32), + ('node_id', ctypes.c_uint32), + ('src_data', ctypes.c_uint32 * 4), + ('PADDING_1', ctypes.c_ubyte * 4), + ('iv_entry', ctypes.POINTER(ctypes.c_uint32)), +] + + +# values for enumeration 'interrupt_node_id_per_aid' +interrupt_node_id_per_aid__enumvalues = { + 0: 'AID0_NODEID', + 1: 'XCD0_NODEID', + 2: 'XCD1_NODEID', + 4: 'AID1_NODEID', + 5: 'XCD2_NODEID', + 6: 'XCD3_NODEID', + 8: 'AID2_NODEID', + 9: 'XCD4_NODEID', + 10: 'XCD5_NODEID', + 12: 'AID3_NODEID', + 13: 'XCD6_NODEID', + 14: 'XCD7_NODEID', + 15: 'NODEID_MAX', +} +AID0_NODEID = 0 +XCD0_NODEID = 1 +XCD1_NODEID = 2 +AID1_NODEID = 4 +XCD2_NODEID = 5 +XCD3_NODEID = 6 +AID2_NODEID = 8 +XCD4_NODEID = 9 +XCD5_NODEID = 10 +AID3_NODEID = 12 +XCD6_NODEID = 13 +XCD7_NODEID = 14 +NODEID_MAX = 15 +interrupt_node_id_per_aid = ctypes.c_uint32 # enum +AMDGPU_DOORBELL_H = True # macro + +# values for enumeration 'AMDGPU_DOORBELL_ASSIGNMENT' +AMDGPU_DOORBELL_ASSIGNMENT__enumvalues = { + 0: 'AMDGPU_DOORBELL_KIQ', + 1: 'AMDGPU_DOORBELL_HIQ', + 2: 'AMDGPU_DOORBELL_DIQ', + 16: 'AMDGPU_DOORBELL_MEC_RING0', + 17: 'AMDGPU_DOORBELL_MEC_RING1', + 18: 'AMDGPU_DOORBELL_MEC_RING2', + 19: 'AMDGPU_DOORBELL_MEC_RING3', + 20: 'AMDGPU_DOORBELL_MEC_RING4', + 21: 'AMDGPU_DOORBELL_MEC_RING5', + 22: 'AMDGPU_DOORBELL_MEC_RING6', + 23: 'AMDGPU_DOORBELL_MEC_RING7', + 32: 'AMDGPU_DOORBELL_GFX_RING0', + 480: 'AMDGPU_DOORBELL_sDMA_ENGINE0', + 481: 'AMDGPU_DOORBELL_sDMA_ENGINE1', + 488: 'AMDGPU_DOORBELL_IH', + 1023: 'AMDGPU_DOORBELL_MAX_ASSIGNMENT', + 65535: 'AMDGPU_DOORBELL_INVALID', +} +AMDGPU_DOORBELL_KIQ = 0 +AMDGPU_DOORBELL_HIQ = 1 +AMDGPU_DOORBELL_DIQ = 2 +AMDGPU_DOORBELL_MEC_RING0 = 16 +AMDGPU_DOORBELL_MEC_RING1 = 17 +AMDGPU_DOORBELL_MEC_RING2 = 18 +AMDGPU_DOORBELL_MEC_RING3 = 19 +AMDGPU_DOORBELL_MEC_RING4 = 20 +AMDGPU_DOORBELL_MEC_RING5 = 21 +AMDGPU_DOORBELL_MEC_RING6 = 22 +AMDGPU_DOORBELL_MEC_RING7 = 23 +AMDGPU_DOORBELL_GFX_RING0 = 32 +AMDGPU_DOORBELL_sDMA_ENGINE0 = 480 +AMDGPU_DOORBELL_sDMA_ENGINE1 = 481 +AMDGPU_DOORBELL_IH = 488 +AMDGPU_DOORBELL_MAX_ASSIGNMENT = 1023 +AMDGPU_DOORBELL_INVALID = 65535 +AMDGPU_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'AMDGPU_VEGA20_DOORBELL_ASSIGNMENT' +AMDGPU_VEGA20_DOORBELL_ASSIGNMENT__enumvalues = { + 0: 'AMDGPU_VEGA20_DOORBELL_KIQ', + 1: 'AMDGPU_VEGA20_DOORBELL_HIQ', + 2: 'AMDGPU_VEGA20_DOORBELL_DIQ', + 3: 'AMDGPU_VEGA20_DOORBELL_MEC_RING0', + 4: 'AMDGPU_VEGA20_DOORBELL_MEC_RING1', + 5: 'AMDGPU_VEGA20_DOORBELL_MEC_RING2', + 6: 'AMDGPU_VEGA20_DOORBELL_MEC_RING3', + 7: 'AMDGPU_VEGA20_DOORBELL_MEC_RING4', + 8: 'AMDGPU_VEGA20_DOORBELL_MEC_RING5', + 9: 'AMDGPU_VEGA20_DOORBELL_MEC_RING6', + 10: 'AMDGPU_VEGA20_DOORBELL_MEC_RING7', + 11: 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_START', + 138: 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_END', + 139: 'AMDGPU_VEGA20_DOORBELL_GFX_RING0', + 256: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0', + 266: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1', + 276: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2', + 286: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3', + 296: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4', + 306: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5', + 316: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6', + 326: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7', + 376: 'AMDGPU_VEGA20_DOORBELL_IH', + 392: 'AMDGPU_VEGA20_DOORBELL64_VCN0_1', + 393: 'AMDGPU_VEGA20_DOORBELL64_VCN2_3', + 394: 'AMDGPU_VEGA20_DOORBELL64_VCN4_5', + 395: 'AMDGPU_VEGA20_DOORBELL64_VCN6_7', + 396: 'AMDGPU_VEGA20_DOORBELL64_VCN8_9', + 397: 'AMDGPU_VEGA20_DOORBELL64_VCNa_b', + 398: 'AMDGPU_VEGA20_DOORBELL64_VCNc_d', + 399: 'AMDGPU_VEGA20_DOORBELL64_VCNe_f', + 392: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1', + 393: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3', + 394: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5', + 395: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7', + 396: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1', + 397: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3', + 398: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5', + 399: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7', + 256: 'AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP', + 399: 'AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP', + 400: 'AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START', + 407: 'AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START', + 464: 'AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START', + 503: 'AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT', + 65535: 'AMDGPU_VEGA20_DOORBELL_INVALID', +} +AMDGPU_VEGA20_DOORBELL_KIQ = 0 +AMDGPU_VEGA20_DOORBELL_HIQ = 1 +AMDGPU_VEGA20_DOORBELL_DIQ = 2 +AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 3 +AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 4 +AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 5 +AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 6 +AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 7 +AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 8 +AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 9 +AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 10 +AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 11 +AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 138 +AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 139 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 256 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 266 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 276 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 286 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 296 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 306 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 316 +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 326 +AMDGPU_VEGA20_DOORBELL_IH = 376 +AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 392 +AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 393 +AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 394 +AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 395 +AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 396 +AMDGPU_VEGA20_DOORBELL64_VCNa_b = 397 +AMDGPU_VEGA20_DOORBELL64_VCNc_d = 398 +AMDGPU_VEGA20_DOORBELL64_VCNe_f = 399 +AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 392 +AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 393 +AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 394 +AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 395 +AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 396 +AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 397 +AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 398 +AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 399 +AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = 256 +AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = 399 +AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 400 +AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 407 +AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 464 +AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 503 +AMDGPU_VEGA20_DOORBELL_INVALID = 65535 +AMDGPU_VEGA20_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'AMDGPU_NAVI10_DOORBELL_ASSIGNMENT' +AMDGPU_NAVI10_DOORBELL_ASSIGNMENT__enumvalues = { + 0: 'AMDGPU_NAVI10_DOORBELL_KIQ', + 1: 'AMDGPU_NAVI10_DOORBELL_HIQ', + 2: 'AMDGPU_NAVI10_DOORBELL_DIQ', + 3: 'AMDGPU_NAVI10_DOORBELL_MEC_RING0', + 4: 'AMDGPU_NAVI10_DOORBELL_MEC_RING1', + 5: 'AMDGPU_NAVI10_DOORBELL_MEC_RING2', + 6: 'AMDGPU_NAVI10_DOORBELL_MEC_RING3', + 7: 'AMDGPU_NAVI10_DOORBELL_MEC_RING4', + 8: 'AMDGPU_NAVI10_DOORBELL_MEC_RING5', + 9: 'AMDGPU_NAVI10_DOORBELL_MEC_RING6', + 10: 'AMDGPU_NAVI10_DOORBELL_MEC_RING7', + 11: 'AMDGPU_NAVI10_DOORBELL_MES_RING0', + 12: 'AMDGPU_NAVI10_DOORBELL_MES_RING1', + 13: 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_START', + 138: 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_END', + 139: 'AMDGPU_NAVI10_DOORBELL_GFX_RING0', + 140: 'AMDGPU_NAVI10_DOORBELL_GFX_RING1', + 141: 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START', + 255: 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END', + 256: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0', + 266: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1', + 276: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2', + 286: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3', + 376: 'AMDGPU_NAVI10_DOORBELL_IH', + 392: 'AMDGPU_NAVI10_DOORBELL64_VCN0_1', + 393: 'AMDGPU_NAVI10_DOORBELL64_VCN2_3', + 394: 'AMDGPU_NAVI10_DOORBELL64_VCN4_5', + 395: 'AMDGPU_NAVI10_DOORBELL64_VCN6_7', + 396: 'AMDGPU_NAVI10_DOORBELL64_VCN8_9', + 397: 'AMDGPU_NAVI10_DOORBELL64_VCNa_b', + 398: 'AMDGPU_NAVI10_DOORBELL64_VCNc_d', + 399: 'AMDGPU_NAVI10_DOORBELL64_VCNe_f', + 400: 'AMDGPU_NAVI10_DOORBELL64_VPE', + 256: 'AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP', + 400: 'AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP', + 400: 'AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT', + 65535: 'AMDGPU_NAVI10_DOORBELL_INVALID', +} +AMDGPU_NAVI10_DOORBELL_KIQ = 0 +AMDGPU_NAVI10_DOORBELL_HIQ = 1 +AMDGPU_NAVI10_DOORBELL_DIQ = 2 +AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 3 +AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 4 +AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 5 +AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 6 +AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 7 +AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 8 +AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 9 +AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 10 +AMDGPU_NAVI10_DOORBELL_MES_RING0 = 11 +AMDGPU_NAVI10_DOORBELL_MES_RING1 = 12 +AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 13 +AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 138 +AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 139 +AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 140 +AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 141 +AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 255 +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 256 +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 266 +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 276 +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 286 +AMDGPU_NAVI10_DOORBELL_IH = 376 +AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 392 +AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 393 +AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 394 +AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 395 +AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 396 +AMDGPU_NAVI10_DOORBELL64_VCNa_b = 397 +AMDGPU_NAVI10_DOORBELL64_VCNc_d = 398 +AMDGPU_NAVI10_DOORBELL64_VCNe_f = 399 +AMDGPU_NAVI10_DOORBELL64_VPE = 400 +AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = 256 +AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = 400 +AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 400 +AMDGPU_NAVI10_DOORBELL_INVALID = 65535 +AMDGPU_NAVI10_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'AMDGPU_DOORBELL64_ASSIGNMENT' +AMDGPU_DOORBELL64_ASSIGNMENT__enumvalues = { + 0: 'AMDGPU_DOORBELL64_KIQ', + 1: 'AMDGPU_DOORBELL64_HIQ', + 2: 'AMDGPU_DOORBELL64_DIQ', + 3: 'AMDGPU_DOORBELL64_MEC_RING0', + 4: 'AMDGPU_DOORBELL64_MEC_RING1', + 5: 'AMDGPU_DOORBELL64_MEC_RING2', + 6: 'AMDGPU_DOORBELL64_MEC_RING3', + 7: 'AMDGPU_DOORBELL64_MEC_RING4', + 8: 'AMDGPU_DOORBELL64_MEC_RING5', + 9: 'AMDGPU_DOORBELL64_MEC_RING6', + 10: 'AMDGPU_DOORBELL64_MEC_RING7', + 11: 'AMDGPU_DOORBELL64_USERQUEUE_START', + 138: 'AMDGPU_DOORBELL64_USERQUEUE_END', + 139: 'AMDGPU_DOORBELL64_GFX_RING0', + 240: 'AMDGPU_DOORBELL64_sDMA_ENGINE0', + 241: 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0', + 242: 'AMDGPU_DOORBELL64_sDMA_ENGINE1', + 243: 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1', + 244: 'AMDGPU_DOORBELL64_IH', + 245: 'AMDGPU_DOORBELL64_IH_RING1', + 246: 'AMDGPU_DOORBELL64_IH_RING2', + 248: 'AMDGPU_DOORBELL64_VCN0_1', + 249: 'AMDGPU_DOORBELL64_VCN2_3', + 250: 'AMDGPU_DOORBELL64_VCN4_5', + 251: 'AMDGPU_DOORBELL64_VCN6_7', + 248: 'AMDGPU_DOORBELL64_UVD_RING0_1', + 249: 'AMDGPU_DOORBELL64_UVD_RING2_3', + 250: 'AMDGPU_DOORBELL64_UVD_RING4_5', + 251: 'AMDGPU_DOORBELL64_UVD_RING6_7', + 252: 'AMDGPU_DOORBELL64_VCE_RING0_1', + 253: 'AMDGPU_DOORBELL64_VCE_RING2_3', + 254: 'AMDGPU_DOORBELL64_VCE_RING4_5', + 255: 'AMDGPU_DOORBELL64_VCE_RING6_7', + 240: 'AMDGPU_DOORBELL64_FIRST_NON_CP', + 255: 'AMDGPU_DOORBELL64_LAST_NON_CP', + 255: 'AMDGPU_DOORBELL64_MAX_ASSIGNMENT', + 65535: 'AMDGPU_DOORBELL64_INVALID', +} +AMDGPU_DOORBELL64_KIQ = 0 +AMDGPU_DOORBELL64_HIQ = 1 +AMDGPU_DOORBELL64_DIQ = 2 +AMDGPU_DOORBELL64_MEC_RING0 = 3 +AMDGPU_DOORBELL64_MEC_RING1 = 4 +AMDGPU_DOORBELL64_MEC_RING2 = 5 +AMDGPU_DOORBELL64_MEC_RING3 = 6 +AMDGPU_DOORBELL64_MEC_RING4 = 7 +AMDGPU_DOORBELL64_MEC_RING5 = 8 +AMDGPU_DOORBELL64_MEC_RING6 = 9 +AMDGPU_DOORBELL64_MEC_RING7 = 10 +AMDGPU_DOORBELL64_USERQUEUE_START = 11 +AMDGPU_DOORBELL64_USERQUEUE_END = 138 +AMDGPU_DOORBELL64_GFX_RING0 = 139 +AMDGPU_DOORBELL64_sDMA_ENGINE0 = 240 +AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 241 +AMDGPU_DOORBELL64_sDMA_ENGINE1 = 242 +AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 243 +AMDGPU_DOORBELL64_IH = 244 +AMDGPU_DOORBELL64_IH_RING1 = 245 +AMDGPU_DOORBELL64_IH_RING2 = 246 +AMDGPU_DOORBELL64_VCN0_1 = 248 +AMDGPU_DOORBELL64_VCN2_3 = 249 +AMDGPU_DOORBELL64_VCN4_5 = 250 +AMDGPU_DOORBELL64_VCN6_7 = 251 +AMDGPU_DOORBELL64_UVD_RING0_1 = 248 +AMDGPU_DOORBELL64_UVD_RING2_3 = 249 +AMDGPU_DOORBELL64_UVD_RING4_5 = 250 +AMDGPU_DOORBELL64_UVD_RING6_7 = 251 +AMDGPU_DOORBELL64_VCE_RING0_1 = 252 +AMDGPU_DOORBELL64_VCE_RING2_3 = 253 +AMDGPU_DOORBELL64_VCE_RING4_5 = 254 +AMDGPU_DOORBELL64_VCE_RING6_7 = 255 +AMDGPU_DOORBELL64_FIRST_NON_CP = 240 +AMDGPU_DOORBELL64_LAST_NON_CP = 255 +AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 255 +AMDGPU_DOORBELL64_INVALID = 65535 +AMDGPU_DOORBELL64_ASSIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1' +AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1__enumvalues = { + 0: 'AMDGPU_DOORBELL_LAYOUT1_KIQ_START', + 1: 'AMDGPU_DOORBELL_LAYOUT1_HIQ', + 2: 'AMDGPU_DOORBELL_LAYOUT1_DIQ', + 8: 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START', + 15: 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END', + 16: 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START', + 31: 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END', + 32: 'AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE', + 256: 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START', + 415: 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END', + 416: 'AMDGPU_DOORBELL_LAYOUT1_IH', + 432: 'AMDGPU_DOORBELL_LAYOUT1_VCN_START', + 488: 'AMDGPU_DOORBELL_LAYOUT1_VCN_END', + 256: 'AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP', + 488: 'AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP', + 488: 'AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT', + 65535: 'AMDGPU_DOORBELL_LAYOUT1_INVALID', +} +AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0 +AMDGPU_DOORBELL_LAYOUT1_HIQ = 1 +AMDGPU_DOORBELL_LAYOUT1_DIQ = 2 +AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 8 +AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 15 +AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 16 +AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 31 +AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 32 +AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 256 +AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 415 +AMDGPU_DOORBELL_LAYOUT1_IH = 416 +AMDGPU_DOORBELL_LAYOUT1_VCN_START = 432 +AMDGPU_DOORBELL_LAYOUT1_VCN_END = 488 +AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = 256 +AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = 488 +AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 488 +AMDGPU_DOORBELL_LAYOUT1_INVALID = 65535 +AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 = ctypes.c_uint32 # enum +__SOC15_IH_CLIENTID_H__ = True # macro + +# values for enumeration 'soc15_ih_clientid' +soc15_ih_clientid__enumvalues = { + 0: 'SOC15_IH_CLIENTID_IH', + 1: 'SOC15_IH_CLIENTID_ACP', + 2: 'SOC15_IH_CLIENTID_ATHUB', + 3: 'SOC15_IH_CLIENTID_BIF', + 4: 'SOC15_IH_CLIENTID_DCE', + 5: 'SOC15_IH_CLIENTID_ISP', + 6: 'SOC15_IH_CLIENTID_PCIE0', + 7: 'SOC15_IH_CLIENTID_RLC', + 8: 'SOC15_IH_CLIENTID_SDMA0', + 9: 'SOC15_IH_CLIENTID_SDMA1', + 10: 'SOC15_IH_CLIENTID_SE0SH', + 11: 'SOC15_IH_CLIENTID_SE1SH', + 12: 'SOC15_IH_CLIENTID_SE2SH', + 13: 'SOC15_IH_CLIENTID_SE3SH', + 14: 'SOC15_IH_CLIENTID_UVD1', + 15: 'SOC15_IH_CLIENTID_THM', + 16: 'SOC15_IH_CLIENTID_UVD', + 17: 'SOC15_IH_CLIENTID_VCE0', + 18: 'SOC15_IH_CLIENTID_VMC', + 19: 'SOC15_IH_CLIENTID_XDMA', + 20: 'SOC15_IH_CLIENTID_GRBM_CP', + 21: 'SOC15_IH_CLIENTID_ATS', + 22: 'SOC15_IH_CLIENTID_ROM_SMUIO', + 23: 'SOC15_IH_CLIENTID_DF', + 24: 'SOC15_IH_CLIENTID_VCE1', + 25: 'SOC15_IH_CLIENTID_PWR', + 26: 'SOC15_IH_CLIENTID_RESERVED', + 27: 'SOC15_IH_CLIENTID_UTCL2', + 28: 'SOC15_IH_CLIENTID_EA', + 29: 'SOC15_IH_CLIENTID_UTCL2LOG', + 30: 'SOC15_IH_CLIENTID_MP0', + 31: 'SOC15_IH_CLIENTID_MP1', + 32: 'SOC15_IH_CLIENTID_MAX', + 16: 'SOC15_IH_CLIENTID_VCN', + 14: 'SOC15_IH_CLIENTID_VCN1', + 1: 'SOC15_IH_CLIENTID_SDMA2', + 4: 'SOC15_IH_CLIENTID_SDMA3', + 5: 'SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid', + 5: 'SOC15_IH_CLIENTID_SDMA4', + 17: 'SOC15_IH_CLIENTID_SDMA5', + 19: 'SOC15_IH_CLIENTID_SDMA6', + 24: 'SOC15_IH_CLIENTID_SDMA7', + 6: 'SOC15_IH_CLIENTID_VMC1', +} +SOC15_IH_CLIENTID_IH = 0 +SOC15_IH_CLIENTID_ACP = 1 +SOC15_IH_CLIENTID_ATHUB = 2 +SOC15_IH_CLIENTID_BIF = 3 +SOC15_IH_CLIENTID_DCE = 4 +SOC15_IH_CLIENTID_ISP = 5 +SOC15_IH_CLIENTID_PCIE0 = 6 +SOC15_IH_CLIENTID_RLC = 7 +SOC15_IH_CLIENTID_SDMA0 = 8 +SOC15_IH_CLIENTID_SDMA1 = 9 +SOC15_IH_CLIENTID_SE0SH = 10 +SOC15_IH_CLIENTID_SE1SH = 11 +SOC15_IH_CLIENTID_SE2SH = 12 +SOC15_IH_CLIENTID_SE3SH = 13 +SOC15_IH_CLIENTID_UVD1 = 14 +SOC15_IH_CLIENTID_THM = 15 +SOC15_IH_CLIENTID_UVD = 16 +SOC15_IH_CLIENTID_VCE0 = 17 +SOC15_IH_CLIENTID_VMC = 18 +SOC15_IH_CLIENTID_XDMA = 19 +SOC15_IH_CLIENTID_GRBM_CP = 20 +SOC15_IH_CLIENTID_ATS = 21 +SOC15_IH_CLIENTID_ROM_SMUIO = 22 +SOC15_IH_CLIENTID_DF = 23 +SOC15_IH_CLIENTID_VCE1 = 24 +SOC15_IH_CLIENTID_PWR = 25 +SOC15_IH_CLIENTID_RESERVED = 26 +SOC15_IH_CLIENTID_UTCL2 = 27 +SOC15_IH_CLIENTID_EA = 28 +SOC15_IH_CLIENTID_UTCL2LOG = 29 +SOC15_IH_CLIENTID_MP0 = 30 +SOC15_IH_CLIENTID_MP1 = 31 +SOC15_IH_CLIENTID_MAX = 32 +SOC15_IH_CLIENTID_VCN = 16 +SOC15_IH_CLIENTID_VCN1 = 14 +SOC15_IH_CLIENTID_SDMA2 = 1 +SOC15_IH_CLIENTID_SDMA3 = 4 +SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = 5 +SOC15_IH_CLIENTID_SDMA4 = 5 +SOC15_IH_CLIENTID_SDMA5 = 17 +SOC15_IH_CLIENTID_SDMA6 = 19 +SOC15_IH_CLIENTID_SDMA7 = 24 +SOC15_IH_CLIENTID_VMC1 = 6 +soc15_ih_clientid = ctypes.c_uint32 # enum +AMDGPU_IRQ_CLIENTID_MAX = SOC15_IH_CLIENTID_MAX # macro +soc15_ih_clientid_name = [] # Variable ctypes.POINTER(ctypes.c_char) * 0 + +# values for enumeration 'soc21_ih_clientid' +soc21_ih_clientid__enumvalues = { + 0: 'SOC21_IH_CLIENTID_IH', + 2: 'SOC21_IH_CLIENTID_ATHUB', + 3: 'SOC21_IH_CLIENTID_BIF', + 4: 'SOC21_IH_CLIENTID_DCN', + 5: 'SOC21_IH_CLIENTID_ISP', + 6: 'SOC21_IH_CLIENTID_MP3', + 7: 'SOC21_IH_CLIENTID_RLC', + 10: 'SOC21_IH_CLIENTID_GFX', + 11: 'SOC21_IH_CLIENTID_IMU', + 14: 'SOC21_IH_CLIENTID_VCN1', + 15: 'SOC21_IH_CLIENTID_THM', + 16: 'SOC21_IH_CLIENTID_VCN', + 17: 'SOC21_IH_CLIENTID_VPE1', + 18: 'SOC21_IH_CLIENTID_VMC', + 20: 'SOC21_IH_CLIENTID_GRBM_CP', + 22: 'SOC21_IH_CLIENTID_ROM_SMUIO', + 23: 'SOC21_IH_CLIENTID_DF', + 24: 'SOC21_IH_CLIENTID_VPE', + 25: 'SOC21_IH_CLIENTID_PWR', + 26: 'SOC21_IH_CLIENTID_LSDMA', + 30: 'SOC21_IH_CLIENTID_MP0', + 31: 'SOC21_IH_CLIENTID_MP1', + 32: 'SOC21_IH_CLIENTID_MAX', +} +SOC21_IH_CLIENTID_IH = 0 +SOC21_IH_CLIENTID_ATHUB = 2 +SOC21_IH_CLIENTID_BIF = 3 +SOC21_IH_CLIENTID_DCN = 4 +SOC21_IH_CLIENTID_ISP = 5 +SOC21_IH_CLIENTID_MP3 = 6 +SOC21_IH_CLIENTID_RLC = 7 +SOC21_IH_CLIENTID_GFX = 10 +SOC21_IH_CLIENTID_IMU = 11 +SOC21_IH_CLIENTID_VCN1 = 14 +SOC21_IH_CLIENTID_THM = 15 +SOC21_IH_CLIENTID_VCN = 16 +SOC21_IH_CLIENTID_VPE1 = 17 +SOC21_IH_CLIENTID_VMC = 18 +SOC21_IH_CLIENTID_GRBM_CP = 20 +SOC21_IH_CLIENTID_ROM_SMUIO = 22 +SOC21_IH_CLIENTID_DF = 23 +SOC21_IH_CLIENTID_VPE = 24 +SOC21_IH_CLIENTID_PWR = 25 +SOC21_IH_CLIENTID_LSDMA = 26 +SOC21_IH_CLIENTID_MP0 = 30 +SOC21_IH_CLIENTID_MP1 = 31 +SOC21_IH_CLIENTID_MAX = 32 +soc21_ih_clientid = ctypes.c_uint32 # enum +__all__ = \ + ['ACCEPT_UNSOLICITED_RESPONSE_ENABLE', + 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_HWID', + 'ACP_TYPE_DVD_AUDIO', 'ACP_TYPE_GENERIC_AUDIO', + 'ACP_TYPE_ICE60958_AUDIO', 'ACP_TYPE_SUPER_AUDIO_CD', + 'ACrYCb16161616_10LSB', 'ACrYCb16161616_10MSB', + 'ACrYCb16161616_12LSB', 'ACrYCb16161616_12MSB', 'ACrYCb2101010', + 'ACrYCb8888', 'ADDR_GEN_ONE', 'ADDR_GEN_TWO', 'ADDR_GEN_ZERO', + 'ADDR_RESERVED', 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE', + 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', + 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', + 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', + 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', + 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', + 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', + 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', + 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', + 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', + 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', + 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', + 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', + 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', + 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', + 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', + 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', + 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS', + 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', + 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', + 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', + 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST', + 'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL', + 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', + 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', + 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'AID0_NODEID', + 'AID1_NODEID', 'AID2_NODEID', 'AID3_NODEID', + 'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE', + 'ALLOW_SR_ON_TRANS_REQ_ENABLE', 'ALL_USE_R', + 'ALPHA_DATA_ONTO_ALPHA_PORT', 'ALPHA_DATA_ONTO_CB_B_PORT', + 'ALPHA_DATA_ONTO_CR_R_PORT', 'ALPHA_DATA_ONTO_Y_G_PORT', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE', + 'AMDGPU_CPCE_UCODE_LOADED', 'AMDGPU_CPMEC1_UCODE_LOADED', + 'AMDGPU_CPMEC2_UCODE_LOADED', 'AMDGPU_CPME_UCODE_LOADED', + 'AMDGPU_CPPFP_UCODE_LOADED', 'AMDGPU_CPRLC_UCODE_LOADED', + 'AMDGPU_DOORBELL64_ASSIGNMENT', 'AMDGPU_DOORBELL64_DIQ', + 'AMDGPU_DOORBELL64_FIRST_NON_CP', 'AMDGPU_DOORBELL64_GFX_RING0', + 'AMDGPU_DOORBELL64_HIQ', 'AMDGPU_DOORBELL64_IH', + 'AMDGPU_DOORBELL64_IH_RING1', 'AMDGPU_DOORBELL64_IH_RING2', + 'AMDGPU_DOORBELL64_INVALID', 'AMDGPU_DOORBELL64_KIQ', + 'AMDGPU_DOORBELL64_LAST_NON_CP', + 'AMDGPU_DOORBELL64_MAX_ASSIGNMENT', 'AMDGPU_DOORBELL64_MEC_RING0', + 'AMDGPU_DOORBELL64_MEC_RING1', 'AMDGPU_DOORBELL64_MEC_RING2', + 'AMDGPU_DOORBELL64_MEC_RING3', 'AMDGPU_DOORBELL64_MEC_RING4', + 'AMDGPU_DOORBELL64_MEC_RING5', 'AMDGPU_DOORBELL64_MEC_RING6', + 'AMDGPU_DOORBELL64_MEC_RING7', 'AMDGPU_DOORBELL64_USERQUEUE_END', + 'AMDGPU_DOORBELL64_USERQUEUE_START', + 'AMDGPU_DOORBELL64_UVD_RING0_1', 'AMDGPU_DOORBELL64_UVD_RING2_3', + 'AMDGPU_DOORBELL64_UVD_RING4_5', 'AMDGPU_DOORBELL64_UVD_RING6_7', + 'AMDGPU_DOORBELL64_VCE_RING0_1', 'AMDGPU_DOORBELL64_VCE_RING2_3', + 'AMDGPU_DOORBELL64_VCE_RING4_5', 'AMDGPU_DOORBELL64_VCE_RING6_7', + 'AMDGPU_DOORBELL64_VCN0_1', 'AMDGPU_DOORBELL64_VCN2_3', + 'AMDGPU_DOORBELL64_VCN4_5', 'AMDGPU_DOORBELL64_VCN6_7', + 'AMDGPU_DOORBELL64_sDMA_ENGINE0', + 'AMDGPU_DOORBELL64_sDMA_ENGINE1', + 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0', + 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1', + 'AMDGPU_DOORBELL_ASSIGNMENT', + 'AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1', 'AMDGPU_DOORBELL_DIQ', + 'AMDGPU_DOORBELL_GFX_RING0', 'AMDGPU_DOORBELL_H', + 'AMDGPU_DOORBELL_HIQ', 'AMDGPU_DOORBELL_IH', + 'AMDGPU_DOORBELL_INVALID', 'AMDGPU_DOORBELL_KIQ', + 'AMDGPU_DOORBELL_LAYOUT1_DIQ', + 'AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP', + 'AMDGPU_DOORBELL_LAYOUT1_HIQ', 'AMDGPU_DOORBELL_LAYOUT1_IH', + 'AMDGPU_DOORBELL_LAYOUT1_INVALID', + 'AMDGPU_DOORBELL_LAYOUT1_KIQ_START', + 'AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP', + 'AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT', + 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END', + 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START', + 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END', + 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START', + 'AMDGPU_DOORBELL_LAYOUT1_VCN_END', + 'AMDGPU_DOORBELL_LAYOUT1_VCN_START', + 'AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE', + 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END', + 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START', + 'AMDGPU_DOORBELL_MAX_ASSIGNMENT', 'AMDGPU_DOORBELL_MEC_RING0', + 'AMDGPU_DOORBELL_MEC_RING1', 'AMDGPU_DOORBELL_MEC_RING2', + 'AMDGPU_DOORBELL_MEC_RING3', 'AMDGPU_DOORBELL_MEC_RING4', + 'AMDGPU_DOORBELL_MEC_RING5', 'AMDGPU_DOORBELL_MEC_RING6', + 'AMDGPU_DOORBELL_MEC_RING7', 'AMDGPU_DOORBELL_sDMA_ENGINE0', + 'AMDGPU_DOORBELL_sDMA_ENGINE1', 'AMDGPU_FW_LOAD_DIRECT', + 'AMDGPU_FW_LOAD_PSP', 'AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO', + 'AMDGPU_FW_LOAD_SMU', 'AMDGPU_GFXHUB_START', + 'AMDGPU_IRQ_CLIENTID_LEGACY', 'AMDGPU_IRQ_CLIENTID_MAX', + 'AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW', 'AMDGPU_IRQ_STATE_DISABLE', + 'AMDGPU_IRQ_STATE_ENABLE', 'AMDGPU_MAX_IRQ_CLIENT_ID', + 'AMDGPU_MAX_IRQ_SRC_ID', 'AMDGPU_MAX_VMHUBS', + 'AMDGPU_MMHUB0_START', 'AMDGPU_MMHUB1_START', 'AMDGPU_MTYPE_CC', + 'AMDGPU_MTYPE_NC', 'AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP', + 'AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP', + 'AMDGPU_NAVI10_DOORBELL64_VCN0_1', + 'AMDGPU_NAVI10_DOORBELL64_VCN2_3', + 'AMDGPU_NAVI10_DOORBELL64_VCN4_5', + 'AMDGPU_NAVI10_DOORBELL64_VCN6_7', + 'AMDGPU_NAVI10_DOORBELL64_VCN8_9', + 'AMDGPU_NAVI10_DOORBELL64_VCNa_b', + 'AMDGPU_NAVI10_DOORBELL64_VCNc_d', + 'AMDGPU_NAVI10_DOORBELL64_VCNe_f', 'AMDGPU_NAVI10_DOORBELL64_VPE', + 'AMDGPU_NAVI10_DOORBELL_ASSIGNMENT', 'AMDGPU_NAVI10_DOORBELL_DIQ', + 'AMDGPU_NAVI10_DOORBELL_GFX_RING0', + 'AMDGPU_NAVI10_DOORBELL_GFX_RING1', + 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END', + 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START', + 'AMDGPU_NAVI10_DOORBELL_HIQ', 'AMDGPU_NAVI10_DOORBELL_IH', + 'AMDGPU_NAVI10_DOORBELL_INVALID', 'AMDGPU_NAVI10_DOORBELL_KIQ', + 'AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING0', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING1', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING2', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING3', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING4', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING5', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING6', + 'AMDGPU_NAVI10_DOORBELL_MEC_RING7', + 'AMDGPU_NAVI10_DOORBELL_MES_RING0', + 'AMDGPU_NAVI10_DOORBELL_MES_RING1', + 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_END', + 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_START', + 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0', + 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1', + 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2', + 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3', 'AMDGPU_PDE_PTE', + 'AMDGPU_PDE_PTE_GFX12', 'AMDGPU_PTE_DEFAULT_ATC', + 'AMDGPU_PTE_EXECUTABLE', 'AMDGPU_PTE_IS_PTE', 'AMDGPU_PTE_LOG', + 'AMDGPU_PTE_MTYPE_GFX12_MASK', 'AMDGPU_PTE_MTYPE_NV10_MASK', + 'AMDGPU_PTE_MTYPE_VG10_MASK', 'AMDGPU_PTE_NOALLOC', + 'AMDGPU_PTE_PRT', 'AMDGPU_PTE_PRT_GFX12', 'AMDGPU_PTE_READABLE', + 'AMDGPU_PTE_SNOOPED', 'AMDGPU_PTE_SYSTEM', 'AMDGPU_PTE_TF', + 'AMDGPU_PTE_TMZ', 'AMDGPU_PTE_VALID', 'AMDGPU_PTE_WRITEABLE', + 'AMDGPU_SDMA0_UCODE_LOADED', 'AMDGPU_SDMA1_UCODE_LOADED', + 'AMDGPU_UCODE_ID', 'AMDGPU_UCODE_ID_CAP', 'AMDGPU_UCODE_ID_CP_CE', + 'AMDGPU_UCODE_ID_CP_ME', 'AMDGPU_UCODE_ID_CP_MEC1', + 'AMDGPU_UCODE_ID_CP_MEC1_JT', 'AMDGPU_UCODE_ID_CP_MEC2', + 'AMDGPU_UCODE_ID_CP_MEC2_JT', 'AMDGPU_UCODE_ID_CP_MES', + 'AMDGPU_UCODE_ID_CP_MES1', 'AMDGPU_UCODE_ID_CP_MES1_DATA', + 'AMDGPU_UCODE_ID_CP_MES_DATA', 'AMDGPU_UCODE_ID_CP_PFP', + 'AMDGPU_UCODE_ID_CP_RS64_ME', 'AMDGPU_UCODE_ID_CP_RS64_MEC', + 'AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK', + 'AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK', + 'AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK', + 'AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK', + 'AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK', + 'AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK', + 'AMDGPU_UCODE_ID_CP_RS64_PFP', + 'AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK', + 'AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK', 'AMDGPU_UCODE_ID_DMCUB', + 'AMDGPU_UCODE_ID_DMCU_ERAM', 'AMDGPU_UCODE_ID_DMCU_INTV', + 'AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS', 'AMDGPU_UCODE_ID_IMU_D', + 'AMDGPU_UCODE_ID_IMU_I', 'AMDGPU_UCODE_ID_ISP', + 'AMDGPU_UCODE_ID_JPEG_RAM', 'AMDGPU_UCODE_ID_MAXIMUM', + 'AMDGPU_UCODE_ID_P2S_TABLE', 'AMDGPU_UCODE_ID_PPTABLE', + 'AMDGPU_UCODE_ID_RLC_DRAM', 'AMDGPU_UCODE_ID_RLC_G', + 'AMDGPU_UCODE_ID_RLC_IRAM', 'AMDGPU_UCODE_ID_RLC_P', + 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL', + 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM', + 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM', + 'AMDGPU_UCODE_ID_RLC_V', 'AMDGPU_UCODE_ID_SDMA0', + 'AMDGPU_UCODE_ID_SDMA1', 'AMDGPU_UCODE_ID_SDMA2', + 'AMDGPU_UCODE_ID_SDMA3', 'AMDGPU_UCODE_ID_SDMA4', + 'AMDGPU_UCODE_ID_SDMA5', 'AMDGPU_UCODE_ID_SDMA6', + 'AMDGPU_UCODE_ID_SDMA7', 'AMDGPU_UCODE_ID_SDMA_RS64', + 'AMDGPU_UCODE_ID_SDMA_UCODE_TH0', + 'AMDGPU_UCODE_ID_SDMA_UCODE_TH1', + 'AMDGPU_UCODE_ID_SE0_TAP_DELAYS', + 'AMDGPU_UCODE_ID_SE1_TAP_DELAYS', + 'AMDGPU_UCODE_ID_SE2_TAP_DELAYS', + 'AMDGPU_UCODE_ID_SE3_TAP_DELAYS', 'AMDGPU_UCODE_ID_SMC', + 'AMDGPU_UCODE_ID_STORAGE', 'AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER', + 'AMDGPU_UCODE_ID_UMSCH_MM_DATA', 'AMDGPU_UCODE_ID_UMSCH_MM_UCODE', + 'AMDGPU_UCODE_ID_UVD', 'AMDGPU_UCODE_ID_UVD1', + 'AMDGPU_UCODE_ID_VCE', 'AMDGPU_UCODE_ID_VCN', + 'AMDGPU_UCODE_ID_VCN0_RAM', 'AMDGPU_UCODE_ID_VCN1', + 'AMDGPU_UCODE_ID_VCN1_RAM', 'AMDGPU_UCODE_ID_VPE', + 'AMDGPU_UCODE_ID_VPE_CTL', 'AMDGPU_UCODE_ID_VPE_CTX', + 'AMDGPU_UCODE_STATUS', 'AMDGPU_UCODE_STATUS_INVALID', + 'AMDGPU_UCODE_STATUS_LOADED', 'AMDGPU_UCODE_STATUS_NOT_LOADED', + 'AMDGPU_VA_RESERVED_BOTTOM', 'AMDGPU_VA_RESERVED_CSA_SIZE', + 'AMDGPU_VA_RESERVED_SEQ64_SIZE', 'AMDGPU_VA_RESERVED_TOP', + 'AMDGPU_VA_RESERVED_TRAP_SIZE', + 'AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP', + 'AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP', + 'AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1', + 'AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3', + 'AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5', + 'AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7', + 'AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1', + 'AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3', + 'AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5', + 'AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7', + 'AMDGPU_VEGA20_DOORBELL64_VCN0_1', + 'AMDGPU_VEGA20_DOORBELL64_VCN2_3', + 'AMDGPU_VEGA20_DOORBELL64_VCN4_5', + 'AMDGPU_VEGA20_DOORBELL64_VCN6_7', + 'AMDGPU_VEGA20_DOORBELL64_VCN8_9', + 'AMDGPU_VEGA20_DOORBELL64_VCNa_b', + 'AMDGPU_VEGA20_DOORBELL64_VCNc_d', + 'AMDGPU_VEGA20_DOORBELL64_VCNe_f', + 'AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START', + 'AMDGPU_VEGA20_DOORBELL_ASSIGNMENT', 'AMDGPU_VEGA20_DOORBELL_DIQ', + 'AMDGPU_VEGA20_DOORBELL_GFX_RING0', 'AMDGPU_VEGA20_DOORBELL_HIQ', + 'AMDGPU_VEGA20_DOORBELL_IH', 'AMDGPU_VEGA20_DOORBELL_INVALID', + 'AMDGPU_VEGA20_DOORBELL_KIQ', + 'AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING0', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING1', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING2', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING3', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING4', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING5', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING6', + 'AMDGPU_VEGA20_DOORBELL_MEC_RING7', + 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_END', + 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_START', + 'AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START', + 'AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6', + 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7', + 'AMDGPU_VM_FAULT_STOP_ALWAYS', 'AMDGPU_VM_FAULT_STOP_FIRST', + 'AMDGPU_VM_FAULT_STOP_NEVER', 'AMDGPU_VM_MAX_UPDATE_SIZE', + 'AMDGPU_VM_NORETRY_FLAGS', 'AMDGPU_VM_NORETRY_FLAGS_TF', + 'AMDGPU_VM_PDB0', 'AMDGPU_VM_PDB1', 'AMDGPU_VM_PDB2', + 'AMDGPU_VM_PTB', 'AMDGPU_VM_RESERVED_VRAM', + 'AMDGPU_VM_USE_CPU_FOR_COMPUTE', 'AMDGPU_VM_USE_CPU_FOR_GFX', + 'AMDGPU_XGMI_MAX_CONNECTED_NODES', 'APG_ACP_OVERRIDE', + 'APG_ACP_SOURCE_NO_OVERRIDE', 'APG_ACP_TYPE_DVD_AUDIO', + 'APG_ACP_TYPE_GENERIC_AUDIO', 'APG_ACP_TYPE_ICE60958_AUDIO', + 'APG_ACP_TYPE_SUPER_AUDIO_CD', 'APG_AUDIO_CRC_CH0_SIG', + 'APG_AUDIO_CRC_CH1_SIG', 'APG_AUDIO_CRC_CH2_SIG', + 'APG_AUDIO_CRC_CH3_SIG', 'APG_AUDIO_CRC_CH4_SIG', + 'APG_AUDIO_CRC_CH5_SIG', 'APG_AUDIO_CRC_CH6_SIG', + 'APG_AUDIO_CRC_CH7_SIG', 'APG_AUDIO_CRC_CONTINUOUS', + 'APG_AUDIO_CRC_CONTROL_CH_SEL', 'APG_AUDIO_CRC_CONTROL_CONT', + 'APG_AUDIO_CRC_ONESHOT', 'APG_AUDIO_CRC_RESERVED_10', + 'APG_AUDIO_CRC_RESERVED_11', 'APG_AUDIO_CRC_RESERVED_12', + 'APG_AUDIO_CRC_RESERVED_13', 'APG_AUDIO_CRC_RESERVED_14', + 'APG_AUDIO_CRC_RESERVED_15', 'APG_AUDIO_CRC_RESERVED_8', + 'APG_AUDIO_CRC_RESERVED_9', 'APG_DBG_ACP_TYPE', + 'APG_DBG_AUDIO_DTO_BASE', 'APG_DBG_AUDIO_DTO_DIV', + 'APG_DBG_AUDIO_DTO_MULTI', 'APG_DBG_MUX_SEL', + 'APG_DEBUG_AUDIO_MODE', 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', + 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST', + 'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS', + 'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON', + 'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL', + 'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE', + 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN', + 'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555', + 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', + 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', + 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', + 'ATHUB_HWID', 'ATHUB_HWIP', 'AUDIO_AZ_HWID', 'AUDIO_LAYOUT_0', + 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', + 'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE', + 'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF', + 'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB', + 'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', + 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'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', + 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', + 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', + 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', + 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', + 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', + 'AZ_RIRB_WRITE_POINTER_DO_RESET', + 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', + 'AZ_STATE_CHANGE_STATUS', + 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ', + 'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565', + 'BIGK_FRAGMENT_SIZE', 'BINARY_SIGNATURE', 'BINNER_BREAK_BATCH', + 'BINNER_DROP', 'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', + 'BINNING_ALLOWED', 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', + 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', + 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', + 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', + 'BIST_MEM_TRAINING_ENCROACHED_SIZE', 'BITS_31_0', 'BITS_32_1', + 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', 'BITS_36_5', 'BITS_37_6', + 'BITS_38_7', 'BLEND_CONSTANT_ALPHA', 'BLEND_CONSTANT_COLOR', + 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', 'BLEND_INV_SRC1_ALPHA', + 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', + 'BLEND_ONE_MINUS_CONSTANT_ALPHA', + 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', + 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', + 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', + 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', + 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT', + 'BOOTCFG_CMD_GET', 'BOOTCFG_CMD_INVALIDATE', 'BOOTCFG_CMD_SET', + 'BOOT_CFG_FEATURE_GECC', + 'BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING', 'BOOT_CONFIG_GECC', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', 'BOTTOM_OF_PIPE_TS', + 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', 'BYPASS_GAMUT', + 'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', + 'BinningMode', 'BlendOp', 'BlendOpt', + 'C2PMSG_CMD_GFX_USB_PD_FW_VER', 'CACHE_BYPASS', 'CACHE_FLUSH', + 'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', + 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', 'CACHE_LRU_WR', 'CACHE_NOA', + 'CACHE_NOA_WR', 'CACHE_STREAM', 'CACHE_STREAM_RD', 'CBMode', + 'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel', + 'CBRamList', 'CB_B_DATA_ONTO_ALPHA_PORT', + 'CB_B_DATA_ONTO_CB_B_PORT', 'CB_B_DATA_ONTO_CR_R_PORT', + 'CB_B_DATA_ONTO_Y_G_PORT', 'CB_DCC_DECOMPRESS', + 'CB_DCG_BACKEND_RDLAT_FIFO', 'CB_DCG_CCC_CAS_COLOR_PTR', + 'CB_DCG_CCC_CAS_FRAG_PTR', 'CB_DCG_CCC_CAS_KEYID', + 'CB_DCG_CCC_CAS_SURF_PARAM', 'CB_DCG_CCC_CAS_TAG_ARRAY', + 'CB_DCG_COLOR_STORE', 'CB_DCG_COLOR_STORE_DIRTY_BYTE', + 'CB_DCG_DCC_CACHE', 'CB_DCG_DCC_DIRTY_BITS', + 'CB_DCG_FMASK_CACHE_STORE', 'CB_DCG_FRONTEND_RDLAT_FIFO', + 'CB_DCG_OUTPUT_FIFO', 'CB_DCG_QBLOCK_ALLOC', + 'CB_DCG_QUAD_PTR_FIFO', 'CB_DCG_READ_SKID_FIFO', + 'CB_DCG_SRC_FIFO', 'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR', + 'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', + 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', + 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 'CB_PERF_SEL_BLEND_CLOCK_EN', + 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', + 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CC_CACHE_FLUSH', + 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', + 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', + 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CC_TAG_HIT', + 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', + 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_DCC_CACHE_FLUSH', + 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', + 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', + 'CB_PERF_SEL_DCC_CACHE_STALL', + 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', + 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', + 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', + 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', 'CB_PERF_SEL_FILTER_DRAWN_QUAD', + 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', + 'CB_PERF_SEL_FILTER_DRAWN_TILE', + 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE', + 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 'CB_PERF_SEL_RESERVED_118', 'CB_PERF_SEL_RESERVED_119', + 'CB_PERF_SEL_RESERVED_120', 'CB_PERF_SEL_RESERVED_121', + 'CB_PERF_SEL_RESERVED_122', 'CB_PERF_SEL_RESERVED_123', + 'CB_PERF_SEL_RESERVED_124', 'CB_PERF_SEL_RESERVED_125', + 'CB_PERF_SEL_RESERVED_126', 'CB_PERF_SEL_RESERVED_127', + 'CB_PERF_SEL_RESERVED_128', 'CB_PERF_SEL_RESERVED_129', + 'CB_PERF_SEL_RESERVED_130', 'CB_PERF_SEL_RESERVED_131', + 'CB_PERF_SEL_RESERVED_132', 'CB_PERF_SEL_RESERVED_133', + 'CB_PERF_SEL_RESERVED_134', 'CB_PERF_SEL_RESERVED_135', + 'CB_PERF_SEL_RESERVED_136', 'CB_PERF_SEL_RESERVED_137', + 'CB_PERF_SEL_RESERVED_138', 'CB_PERF_SEL_RESERVED_139', + 'CB_PERF_SEL_RESERVED_140', 'CB_PERF_SEL_RESERVED_141', + 'CB_PERF_SEL_RESERVED_142', 'CB_PERF_SEL_RESERVED_143', + 'CB_PERF_SEL_RESERVED_144', 'CB_PERF_SEL_RESERVED_145', + 'CB_PERF_SEL_RESERVED_146', 'CB_PERF_SEL_RESERVED_147', + 'CB_PERF_SEL_RESERVED_148', 'CB_PERF_SEL_RESERVED_149', + 'CB_PERF_SEL_RESERVED_165', 'CB_PERF_SEL_RESERVED_166', + 'CB_PERF_SEL_RESERVED_167', 'CB_PERF_SEL_RESERVED_168', + 'CB_PERF_SEL_RESERVED_169', 'CB_PERF_SEL_RESERVED_170', + 'CB_PERF_SEL_RESERVED_171', 'CB_PERF_SEL_RESERVED_172', + 'CB_PERF_SEL_RESERVED_173', 'CB_PERF_SEL_RESERVED_174', + 'CB_PERF_SEL_RESERVED_175', 'CB_PERF_SEL_RESERVED_176', + 'CB_PERF_SEL_RESERVED_177', 'CB_PERF_SEL_RESERVED_178', + 'CB_PERF_SEL_RESERVED_179', 'CB_PERF_SEL_RESERVED_180', + 'CB_PERF_SEL_RESERVED_181', 'CB_PERF_SEL_RESERVED_182', + 'CB_PERF_SEL_RESERVED_183', 'CB_PERF_SEL_RESERVED_184', + 'CB_PERF_SEL_RESERVED_185', 'CB_PERF_SEL_RESERVED_186', + 'CB_PERF_SEL_RESERVED_187', 'CB_PERF_SEL_RESERVED_188', + 'CB_PERF_SEL_RESERVED_189', 'CB_PERF_SEL_RESERVED_190', + 'CB_PERF_SEL_RESERVED_191', 'CB_PERF_SEL_RESERVED_192', + 'CB_PERF_SEL_RESERVED_193', 'CB_PERF_SEL_RESERVED_194', + 'CB_PERF_SEL_RESERVED_195', 'CB_PERF_SEL_RESERVED_196', + 'CB_PERF_SEL_RESERVED_197', 'CB_PERF_SEL_RESERVED_198', + 'CB_PERF_SEL_RESERVED_199', 'CB_PERF_SEL_RESERVED_205', + 'CB_PERF_SEL_RESERVED_206', 'CB_PERF_SEL_RESERVED_207', + 'CB_PERF_SEL_RESERVED_208', 'CB_PERF_SEL_RESERVED_209', + 'CB_PERF_SEL_RESERVED_21', 'CB_PERF_SEL_RESERVED_210', + 'CB_PERF_SEL_RESERVED_211', 'CB_PERF_SEL_RESERVED_212', + 'CB_PERF_SEL_RESERVED_213', 'CB_PERF_SEL_RESERVED_214', + 'CB_PERF_SEL_RESERVED_215', 'CB_PERF_SEL_RESERVED_216', + 'CB_PERF_SEL_RESERVED_217', 'CB_PERF_SEL_RESERVED_218', + 'CB_PERF_SEL_RESERVED_219', 'CB_PERF_SEL_RESERVED_22', + 'CB_PERF_SEL_RESERVED_220', 'CB_PERF_SEL_RESERVED_221', + 'CB_PERF_SEL_RESERVED_222', 'CB_PERF_SEL_RESERVED_223', + 'CB_PERF_SEL_RESERVED_224', 'CB_PERF_SEL_RESERVED_225', + 'CB_PERF_SEL_RESERVED_226', 'CB_PERF_SEL_RESERVED_227', + 'CB_PERF_SEL_RESERVED_228', 'CB_PERF_SEL_RESERVED_229', + 'CB_PERF_SEL_RESERVED_23', 'CB_PERF_SEL_RESERVED_230', + 'CB_PERF_SEL_RESERVED_231', 'CB_PERF_SEL_RESERVED_232', + 'CB_PERF_SEL_RESERVED_233', 'CB_PERF_SEL_RESERVED_234', + 'CB_PERF_SEL_RESERVED_235', 'CB_PERF_SEL_RESERVED_236', + 'CB_PERF_SEL_RESERVED_237', 'CB_PERF_SEL_RESERVED_238', + 'CB_PERF_SEL_RESERVED_239', 'CB_PERF_SEL_RESERVED_24', + 'CB_PERF_SEL_RESERVED_240', 'CB_PERF_SEL_RESERVED_241', + 'CB_PERF_SEL_RESERVED_242', 'CB_PERF_SEL_RESERVED_243', + 'CB_PERF_SEL_RESERVED_244', 'CB_PERF_SEL_RESERVED_245', + 'CB_PERF_SEL_RESERVED_246', 'CB_PERF_SEL_RESERVED_247', + 'CB_PERF_SEL_RESERVED_248', 'CB_PERF_SEL_RESERVED_249', + 'CB_PERF_SEL_RESERVED_25', 'CB_PERF_SEL_RESERVED_259', + 'CB_PERF_SEL_RESERVED_26', 'CB_PERF_SEL_RESERVED_260', + 'CB_PERF_SEL_RESERVED_261', 'CB_PERF_SEL_RESERVED_262', + 'CB_PERF_SEL_RESERVED_263', 'CB_PERF_SEL_RESERVED_264', + 'CB_PERF_SEL_RESERVED_265', 'CB_PERF_SEL_RESERVED_266', + 'CB_PERF_SEL_RESERVED_267', 'CB_PERF_SEL_RESERVED_268', + 'CB_PERF_SEL_RESERVED_269', 'CB_PERF_SEL_RESERVED_27', + 'CB_PERF_SEL_RESERVED_270', 'CB_PERF_SEL_RESERVED_271', + 'CB_PERF_SEL_RESERVED_272', 'CB_PERF_SEL_RESERVED_273', + 'CB_PERF_SEL_RESERVED_274', 'CB_PERF_SEL_RESERVED_275', + 'CB_PERF_SEL_RESERVED_276', 'CB_PERF_SEL_RESERVED_277', + 'CB_PERF_SEL_RESERVED_278', 'CB_PERF_SEL_RESERVED_279', + 'CB_PERF_SEL_RESERVED_28', 'CB_PERF_SEL_RESERVED_280', + 'CB_PERF_SEL_RESERVED_281', 'CB_PERF_SEL_RESERVED_282', + 'CB_PERF_SEL_RESERVED_283', 'CB_PERF_SEL_RESERVED_284', + 'CB_PERF_SEL_RESERVED_285', 'CB_PERF_SEL_RESERVED_286', + 'CB_PERF_SEL_RESERVED_287', 'CB_PERF_SEL_RESERVED_288', + 'CB_PERF_SEL_RESERVED_289', 'CB_PERF_SEL_RESERVED_29', + 'CB_PERF_SEL_RESERVED_290', 'CB_PERF_SEL_RESERVED_291', + 'CB_PERF_SEL_RESERVED_292', 'CB_PERF_SEL_RESERVED_293', + 'CB_PERF_SEL_RESERVED_294', 'CB_PERF_SEL_RESERVED_295', + 'CB_PERF_SEL_RESERVED_296', 'CB_PERF_SEL_RESERVED_297', + 'CB_PERF_SEL_RESERVED_298', 'CB_PERF_SEL_RESERVED_299', + 'CB_PERF_SEL_RESERVED_303', 'CB_PERF_SEL_RESERVED_304', + 'CB_PERF_SEL_RESERVED_305', 'CB_PERF_SEL_RESERVED_306', + 'CB_PERF_SEL_RESERVED_307', 'CB_PERF_SEL_RESERVED_308', + 'CB_PERF_SEL_RESERVED_309', 'CB_PERF_SEL_RESERVED_310', + 'CB_PERF_SEL_RESERVED_311', 'CB_PERF_SEL_RESERVED_312', + 'CB_PERF_SEL_RESERVED_313', 'CB_PERF_SEL_RESERVED_314', + 'CB_PERF_SEL_RESERVED_315', 'CB_PERF_SEL_RESERVED_316', + 'CB_PERF_SEL_RESERVED_317', 'CB_PERF_SEL_RESERVED_318', + 'CB_PERF_SEL_RESERVED_319', 'CB_PERF_SEL_RESERVED_320', + 'CB_PERF_SEL_RESERVED_321', 'CB_PERF_SEL_RESERVED_322', + 'CB_PERF_SEL_RESERVED_323', 'CB_PERF_SEL_RESERVED_324', + 'CB_PERF_SEL_RESERVED_325', 'CB_PERF_SEL_RESERVED_326', + 'CB_PERF_SEL_RESERVED_327', 'CB_PERF_SEL_RESERVED_328', + 'CB_PERF_SEL_RESERVED_329', 'CB_PERF_SEL_RESERVED_330', + 'CB_PERF_SEL_RESERVED_331', 'CB_PERF_SEL_RESERVED_332', + 'CB_PERF_SEL_RESERVED_333', 'CB_PERF_SEL_RESERVED_334', + 'CB_PERF_SEL_RESERVED_335', 'CB_PERF_SEL_RESERVED_336', + 'CB_PERF_SEL_RESERVED_337', 'CB_PERF_SEL_RESERVED_338', + 'CB_PERF_SEL_RESERVED_339', 'CB_PERF_SEL_RESERVED_340', + 'CB_PERF_SEL_RESERVED_341', 'CB_PERF_SEL_RESERVED_342', + 'CB_PERF_SEL_RESERVED_343', 'CB_PERF_SEL_RESERVED_344', + 'CB_PERF_SEL_RESERVED_345', 'CB_PERF_SEL_RESERVED_346', + 'CB_PERF_SEL_RESERVED_347', 'CB_PERF_SEL_RESERVED_348', + 'CB_PERF_SEL_RESERVED_349', 'CB_PERF_SEL_RESERVED_350', + 'CB_PERF_SEL_RESERVED_351', 'CB_PERF_SEL_RESERVED_352', + 'CB_PERF_SEL_RESERVED_353', 'CB_PERF_SEL_RESERVED_354', + 'CB_PERF_SEL_RESERVED_355', 'CB_PERF_SEL_RESERVED_356', + 'CB_PERF_SEL_RESERVED_357', 'CB_PERF_SEL_RESERVED_358', + 'CB_PERF_SEL_RESERVED_359', 'CB_PERF_SEL_RESERVED_360', + 'CB_PERF_SEL_RESERVED_361', 'CB_PERF_SEL_RESERVED_362', + 'CB_PERF_SEL_RESERVED_363', 'CB_PERF_SEL_RESERVED_364', + 'CB_PERF_SEL_RESERVED_365', 'CB_PERF_SEL_RESERVED_366', + 'CB_PERF_SEL_RESERVED_367', 'CB_PERF_SEL_RESERVED_368', + 'CB_PERF_SEL_RESERVED_369', 'CB_PERF_SEL_RESERVED_370', + 'CB_PERF_SEL_RESERVED_371', 'CB_PERF_SEL_RESERVED_372', + 'CB_PERF_SEL_RESERVED_373', 'CB_PERF_SEL_RESERVED_374', + 'CB_PERF_SEL_RESERVED_375', 'CB_PERF_SEL_RESERVED_376', + 'CB_PERF_SEL_RESERVED_377', 'CB_PERF_SEL_RESERVED_378', + 'CB_PERF_SEL_RESERVED_379', 'CB_PERF_SEL_RESERVED_38', + 'CB_PERF_SEL_RESERVED_380', 'CB_PERF_SEL_RESERVED_381', + 'CB_PERF_SEL_RESERVED_382', 'CB_PERF_SEL_RESERVED_383', + 'CB_PERF_SEL_RESERVED_384', 'CB_PERF_SEL_RESERVED_385', + 'CB_PERF_SEL_RESERVED_386', 'CB_PERF_SEL_RESERVED_387', + 'CB_PERF_SEL_RESERVED_388', 'CB_PERF_SEL_RESERVED_389', + 'CB_PERF_SEL_RESERVED_39', 'CB_PERF_SEL_RESERVED_390', + 'CB_PERF_SEL_RESERVED_391', 'CB_PERF_SEL_RESERVED_392', + 'CB_PERF_SEL_RESERVED_393', 'CB_PERF_SEL_RESERVED_394', + 'CB_PERF_SEL_RESERVED_395', 'CB_PERF_SEL_RESERVED_396', + 'CB_PERF_SEL_RESERVED_397', 'CB_PERF_SEL_RESERVED_398', + 'CB_PERF_SEL_RESERVED_399', 'CB_PERF_SEL_RESERVED_40', + 'CB_PERF_SEL_RESERVED_400', 'CB_PERF_SEL_RESERVED_401', + 'CB_PERF_SEL_RESERVED_402', 'CB_PERF_SEL_RESERVED_403', + 'CB_PERF_SEL_RESERVED_404', 'CB_PERF_SEL_RESERVED_405', + 'CB_PERF_SEL_RESERVED_406', 'CB_PERF_SEL_RESERVED_407', + 'CB_PERF_SEL_RESERVED_408', 'CB_PERF_SEL_RESERVED_409', + 'CB_PERF_SEL_RESERVED_41', 'CB_PERF_SEL_RESERVED_410', + 'CB_PERF_SEL_RESERVED_411', 'CB_PERF_SEL_RESERVED_412', + 'CB_PERF_SEL_RESERVED_413', 'CB_PERF_SEL_RESERVED_414', + 'CB_PERF_SEL_RESERVED_415', 'CB_PERF_SEL_RESERVED_416', + 'CB_PERF_SEL_RESERVED_417', 'CB_PERF_SEL_RESERVED_418', + 'CB_PERF_SEL_RESERVED_419', 'CB_PERF_SEL_RESERVED_42', + 'CB_PERF_SEL_RESERVED_420', 'CB_PERF_SEL_RESERVED_421', + 'CB_PERF_SEL_RESERVED_422', 'CB_PERF_SEL_RESERVED_423', + 'CB_PERF_SEL_RESERVED_424', 'CB_PERF_SEL_RESERVED_425', + 'CB_PERF_SEL_RESERVED_426', 'CB_PERF_SEL_RESERVED_427', + 'CB_PERF_SEL_RESERVED_428', 'CB_PERF_SEL_RESERVED_429', + 'CB_PERF_SEL_RESERVED_43', 'CB_PERF_SEL_RESERVED_430', + 'CB_PERF_SEL_RESERVED_431', 'CB_PERF_SEL_RESERVED_432', + 'CB_PERF_SEL_RESERVED_433', 'CB_PERF_SEL_RESERVED_434', + 'CB_PERF_SEL_RESERVED_435', 'CB_PERF_SEL_RESERVED_436', + 'CB_PERF_SEL_RESERVED_437', 'CB_PERF_SEL_RESERVED_438', + 'CB_PERF_SEL_RESERVED_439', 'CB_PERF_SEL_RESERVED_44', + 'CB_PERF_SEL_RESERVED_440', 'CB_PERF_SEL_RESERVED_441', + 'CB_PERF_SEL_RESERVED_442', 'CB_PERF_SEL_RESERVED_443', + 'CB_PERF_SEL_RESERVED_444', 'CB_PERF_SEL_RESERVED_445', + 'CB_PERF_SEL_RESERVED_446', 'CB_PERF_SEL_RESERVED_447', + 'CB_PERF_SEL_RESERVED_448', 'CB_PERF_SEL_RESERVED_449', + 'CB_PERF_SEL_RESERVED_45', 'CB_PERF_SEL_RESERVED_450', + 'CB_PERF_SEL_RESERVED_451', 'CB_PERF_SEL_RESERVED_452', + 'CB_PERF_SEL_RESERVED_453', 'CB_PERF_SEL_RESERVED_454', + 'CB_PERF_SEL_RESERVED_455', 'CB_PERF_SEL_RESERVED_456', + 'CB_PERF_SEL_RESERVED_457', 'CB_PERF_SEL_RESERVED_458', + 'CB_PERF_SEL_RESERVED_459', 'CB_PERF_SEL_RESERVED_46', + 'CB_PERF_SEL_RESERVED_460', 'CB_PERF_SEL_RESERVED_461', + 'CB_PERF_SEL_RESERVED_462', 'CB_PERF_SEL_RESERVED_463', + 'CB_PERF_SEL_RESERVED_464', 'CB_PERF_SEL_RESERVED_465', + 'CB_PERF_SEL_RESERVED_47', 'CB_PERF_SEL_RESERVED_48', + 'CB_PERF_SEL_RESERVED_49', 'CB_PERF_SEL_RESERVED_65', + 'CB_PERF_SEL_RESERVED_66', 'CB_PERF_SEL_RESERVED_67', + 'CB_PERF_SEL_RESERVED_68', 'CB_PERF_SEL_RESERVED_69', + 'CB_PERF_SEL_RESERVED_70', 'CB_PERF_SEL_RESERVED_71', + 'CB_PERF_SEL_RESERVED_72', 'CB_PERF_SEL_RESERVED_73', + 'CB_PERF_SEL_RESERVED_74', 'CB_PERF_SEL_RESERVED_75', + 'CB_PERF_SEL_RESERVED_76', 'CB_PERF_SEL_RESERVED_77', + 'CB_PERF_SEL_RESERVED_78', 'CB_PERF_SEL_RESERVED_79', + 'CB_PERF_SEL_RESERVED_80', 'CB_PERF_SEL_RESERVED_81', + 'CB_PERF_SEL_RESERVED_82', 'CB_PERF_SEL_RESERVED_83', + 'CB_PERF_SEL_RESERVED_84', 'CB_PERF_SEL_RESERVED_85', + 'CB_PERF_SEL_RESERVED_86', 'CB_PERF_SEL_RESERVED_87', + 'CB_PERF_SEL_RESERVED_88', 'CB_PERF_SEL_RESERVED_89', + 'CB_PERF_SEL_RESERVED_90', 'CB_PERF_SEL_RESERVED_91', + 'CB_PERF_SEL_RESERVED_92', 'CB_PERF_SEL_RESERVED_93', + 'CB_PERF_SEL_RESERVED_94', 'CB_PERF_SEL_RESERVED_95', + 'CB_PERF_SEL_RESERVED_96', 'CB_PERF_SEL_RESERVED_97', + 'CB_PERF_SEL_RESERVED_98', 'CB_PERF_SEL_RESERVED_99', + 'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED', 'CCXSEC_HWID', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', + 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY', + 'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 'CHA_PERF_SEL_IO_32B_WDS_CHC3', 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0', + 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', + 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4', + 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', 'CHA_PERF_SEL_STALL_CHC0', + 'CHA_PERF_SEL_STALL_CHC1', 'CHA_PERF_SEL_STALL_CHC2', + 'CHA_PERF_SEL_STALL_CHC3', 'CHA_PERF_SEL_STALL_CHC4', + 'CHA_PERF_SEL_STALL_CHC5', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL', + 'CHCG_PERF_SEL_ARB_RET_LEVEL', 'CHCG_PERF_SEL_BUSY', + 'CHCG_PERF_SEL_CYCLE', 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', + 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHCG_PERF_SEL_REQ', + 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHCG_PERF_SEL_REQ_CLIENT0', + 'CHCG_PERF_SEL_REQ_CLIENT1', 'CHCG_PERF_SEL_REQ_CLIENT10', + 'CHCG_PERF_SEL_REQ_CLIENT11', 'CHCG_PERF_SEL_REQ_CLIENT12', + 'CHCG_PERF_SEL_REQ_CLIENT13', 'CHCG_PERF_SEL_REQ_CLIENT14', + 'CHCG_PERF_SEL_REQ_CLIENT15', 'CHCG_PERF_SEL_REQ_CLIENT16', + 'CHCG_PERF_SEL_REQ_CLIENT17', 'CHCG_PERF_SEL_REQ_CLIENT18', + 'CHCG_PERF_SEL_REQ_CLIENT19', 'CHCG_PERF_SEL_REQ_CLIENT2', + 'CHCG_PERF_SEL_REQ_CLIENT20', 'CHCG_PERF_SEL_REQ_CLIENT21', + 'CHCG_PERF_SEL_REQ_CLIENT22', 'CHCG_PERF_SEL_REQ_CLIENT23', + 'CHCG_PERF_SEL_REQ_CLIENT3', 'CHCG_PERF_SEL_REQ_CLIENT4', + 'CHCG_PERF_SEL_REQ_CLIENT5', 'CHCG_PERF_SEL_REQ_CLIENT6', + 'CHCG_PERF_SEL_REQ_CLIENT7', 'CHCG_PERF_SEL_REQ_CLIENT8', + 'CHCG_PERF_SEL_REQ_CLIENT9', 'CHCG_PERF_SEL_REQ_NOP_ACK', + 'CHCG_PERF_SEL_REQ_NOP_RTN0', 'CHCG_PERF_SEL_REQ_READ', + 'CHCG_PERF_SEL_REQ_READ_128B', 'CHCG_PERF_SEL_REQ_READ_32B', + 'CHCG_PERF_SEL_REQ_READ_64B', 'CHCG_PERF_SEL_REQ_WRITE', + 'CHCG_PERF_SEL_REQ_WRITE_32B', 'CHCG_PERF_SEL_REQ_WRITE_64B', + 'CHCG_PERF_SEL_STALL_BUFFER_FULL', 'CHCG_PERF_SEL_STALL_GUS_GL1', + 'CHCG_PERF_SEL_STARVE', 'CHC_PERF_SEL', + 'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY', + 'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ', + 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0', + 'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10', + 'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12', + 'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14', + 'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16', + 'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18', + 'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2', + 'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21', + 'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23', + 'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4', + 'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6', + 'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8', + 'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK', + 'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ', + 'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B', + 'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE', + 'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B', + 'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1', + 'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB', + 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB', + 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB', + 'CLEAR_SMU_INTR', 'CLKA_HWID', 'CLKB_HWID', 'CLKGATE_BASE_MODE', + 'CLKGATE_SM_MODE', 'CLK_HWIP', 'CLOCK_BRANCH_SOFT_RESET', + 'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 'CLOCK_GATING_DISABLE', 'CLOCK_GATING_DISABLED', + 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_DISABLE_ENUM', + 'CLOCK_GATING_DISABLE_ENUM_DISABLED', + 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', + 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', + 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', + 'CMASK_CLR00_F2', 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', + 'CMASK_CLR01_F1', 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', + 'CMASK_CLR10_F0', 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', + 'CMASK_CLR10_FX', 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', + 'CMASK_CLR11_F2', 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', + 'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', + 'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', + 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', + 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', + 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', + 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', + 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', + 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', + 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', + 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', + 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', + 'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', + 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', + 'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM', + 'CM_GAMMA_LUT_SEL_ENUM', 'CM_GAMUT_REMAP_MODE_ENUM', + 'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM', + 'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', + 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', 'CM_LUT_RAM_SEL', + 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', 'CM_NOT_PENDING', + 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', 'CM_WRITE_BASE_ONLY', + 'CM_YES_PENDING', 'CNVC_BYPASS', 'CNVC_BYPASS_DISABLE', + 'CNVC_BYPASS_EN', 'CNVC_COEF_FORMAT_ENUM', 'CNVC_DIS', 'CNVC_EN', + 'CNVC_ENABLE', 'CNVC_FIX_S2_13', 'CNVC_FIX_S3_12', + 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', 'CNVC_TRUNCATE', + 'CNVC_YES_PENDING', 'COEF_POST_CSC', 'COEF_POST_CSC_B', + 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', + 'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND', + 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT', + 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_MODE', + 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', + 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPAT_LEVEL', + 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', + 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', + 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', + 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', + 'CORB_READ_POINTER_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', + 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', + 'CPC_LATENCY_STATS_SEL_INVAL_LAST', + 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', + 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', + 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MES_THREAD0', + 'CPC_PERF_SEL_MES_THREAD1', + 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', + 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', + 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 'CPF_LATENCY_STATS_SEL_READ_LAST', + 'CPF_LATENCY_STATS_SEL_READ_MAX', + 'CPF_LATENCY_STATS_SEL_READ_MIN', + 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', + 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', + 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', + 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', + 'CPF_PERF_SEL_ALWAYS_COUNT', + 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', + 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', + 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND', + 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX', + 'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT', + 'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR', + 'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM', + 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 'CPG_LATENCY_STATS_SEL_INVAL_LAST', + 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 'CPG_LATENCY_STATS_SEL_READ_LAST', + 'CPG_LATENCY_STATS_SEL_READ_MAX', + 'CPG_LATENCY_STATS_SEL_READ_MIN', + 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', + 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', + 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', + 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', + 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', + 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', + 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', + 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', + 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', + 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', + 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', + 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', + 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', + 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', + 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', + 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', + 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', + 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL', + 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_DMA_BUSY', + 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED', + 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', + 'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', + 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', + 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', + 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', + 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', + 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', + 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', + 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', + 'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1', + 'CRC_IN_CUR_2', 'CRC_IN_CUR_3', 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', + 'CRC_IN_PIX_1', 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', + 'CRC_IN_PIX_5', 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', + 'CRC_SRC_0', 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', + 'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', + 'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', + 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', + 'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT', + 'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT', + 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', + 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', + 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', + 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', + 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', + 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', + 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY', + 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', + 'CURSOR_COLOR_24BIT_1BIT_AND', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 'CURSOR_COLOR_64BIT_FP_PREMULT', + 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', + 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', + 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', + 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', + 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', + 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', + 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', + 'CURSOR_MODE', 'CURSOR_MONO_2BIT', + 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_EN', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', + 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', + 'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY', + 'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP', + 'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED', + 'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ', + 'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', + 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', + 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', + 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', + 'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING', + 'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION', + 'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED', + 'CbYCrY8888_422_PACKED', 'CmaskCode', 'CombFunc', 'CompareFrag', + 'ConservativeZExport', 'CovToShaderSel', 'CrYCbA1010102', + 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB', + 'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888', + 'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED', + 'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', + 'DAC_MUX_SELECT_DACB', 'DAZ_HWID', 'DBGU0_HWID', 'DBGU1_HWID', + 'DBGU_IO_HWID', 'DBGU_NBIO_HWID', 'DB_BREAK_BATCH_EVENT', + 'DB_CACHE_FLUSH', 'DB_CACHE_FLUSH_AND_INV', + 'DB_CACHE_FLUSH_AND_INV_EVENT', 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', + 'DB_CACHE_FLUSH_TS', 'DB_CONTEXT_DONE_EVENT', + 'DB_CONTEXT_SUSPEND_EVENT', 'DB_FLUSH_AND_INV_DB_DATA_TS', + 'DB_FLUSH_AND_INV_DB_META', 'DB_INVOKE_CHANGE_EVENT', + 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 'DB_PERF_SEL_CB_DB_rdreq_sends', + 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 'DB_PERF_SEL_CB_DB_wrreq_sends', + 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', + 'DB_PERF_SEL_DB_CB_lquad_busy', + 'DB_PERF_SEL_DB_CB_lquad_double_format', + 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 'DB_PERF_SEL_DB_CB_lquad_quads', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', + 'DB_PERF_SEL_DB_CB_lquad_sends', + 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', + 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', + 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', + 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', + 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', + 'DB_PERF_SEL_DB_SC_quad_double_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', + 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', + 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', + 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 'DB_PERF_SEL_DB_SC_tile_stalls', + 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate', + 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 'DB_PERF_SEL_Depth_Tile_Cache_event', + 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 'DB_PERF_SEL_Plane_Cache_flushes', + 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', + 'DB_PERF_SEL_Plane_Cache_misses', + 'DB_PERF_SEL_Plane_Cache_starves', + 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 'DB_PERF_SEL_PostZ_Samples_failing_S', + 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 'DB_PERF_SEL_PreZ_Samples_failing_S', + 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy', + 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', + 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface', + 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', + 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', + 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 'DB_PERF_SEL_SH_quads_outstanding_sum', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 'DB_PERF_SEL_SX_DB_quad_busy', + 'DB_PERF_SEL_SX_DB_quad_double_format', + 'DB_PERF_SEL_SX_DB_quad_export_quads', + 'DB_PERF_SEL_SX_DB_quad_exports', + 'DB_PERF_SEL_SX_DB_quad_fast_format', + 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', + 'DB_PERF_SEL_SX_DB_quad_sends', + 'DB_PERF_SEL_SX_DB_quad_slow_format', + 'DB_PERF_SEL_SX_DB_quad_stalls', + 'DB_PERF_SEL_Stencil_Cache_flushes', + 'DB_PERF_SEL_Stencil_Cache_frees', + 'DB_PERF_SEL_Stencil_Cache_hits', + 'DB_PERF_SEL_Stencil_Cache_misses', + 'DB_PERF_SEL_Stencil_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', + 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_surface_stall', + 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 'DB_PERF_SEL_Z_Cache_pmask_hits', + 'DB_PERF_SEL_Z_Cache_pmask_misses', + 'DB_PERF_SEL_Z_Cache_pmask_starves', + 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 'DB_PERF_SEL_clock_main_active', + 'DB_PERF_SEL_clock_mem_export_active', + 'DB_PERF_SEL_clock_reg_active', + 'DB_PERF_SEL_cs_events_pws_enable', + 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', + 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', + 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', + 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', + 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', + 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', + 'DB_PERF_SEL_dtt_sm_slot_stall', + 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', + 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', + 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends', + 'DB_PERF_SEL_esr_ps_src_in_squads', + 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_stall', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy', + 'DB_PERF_SEL_esr_ps_vic_stall', + 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', + 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall', + 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_cb_tile_stall', + 'DB_PERF_SEL_etr_out_esr_stall', + 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', + 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', + 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', + 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', + 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', + 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', + 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', + 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', + 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', + 'DB_PERF_SEL_flush_compressed_stencil', + 'DB_PERF_SEL_flush_expanded_stencil', + 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', + 'DB_PERF_SEL_flush_single_stencil', + 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved', + 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', + 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', + 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', + 'DB_PERF_SEL_noz_waiting_for_postz_done', + 'DB_PERF_SEL_planes_flushed', + 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_postzl_full_launch', + 'DB_PERF_SEL_postzl_partial_launch', + 'DB_PERF_SEL_postzl_partial_waiting', + 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', + 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', + 'DB_PERF_SEL_postzl_src_in_sends', + 'DB_PERF_SEL_postzl_src_in_squads', + 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 'DB_PERF_SEL_postzl_src_in_stall', + 'DB_PERF_SEL_postzl_src_in_tile_rate', + 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_postzl_src_out_stall', + 'DB_PERF_SEL_postzl_tile_init_stall', + 'DB_PERF_SEL_postzl_tile_mem_stall', + 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_prezl_src_in_sends', + 'DB_PERF_SEL_prezl_src_in_squads', + 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 'DB_PERF_SEL_prezl_src_in_stall', + 'DB_PERF_SEL_prezl_src_in_tile_rate', + 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_prezl_src_out_stall', + 'DB_PERF_SEL_prezl_tile_init_stall', + 'DB_PERF_SEL_prezl_tile_mem_stall', + 'DB_PERF_SEL_ps_events_pws_enable', 'DB_PERF_SEL_qc_busy', + 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', + 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', + 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', + 'DB_PERF_SEL_quad_rd_mi_stall', + 'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic', + 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', + 'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall', + 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', + 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', + 'DB_PERF_SEL_quad_wr_coherency_stall', + 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', + 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', + 'DB_PERF_SEL_tcp_dispatcher_flushes', + 'DB_PERF_SEL_tcp_dispatcher_reads', + 'DB_PERF_SEL_tcp_prefetcher_flushes', + 'DB_PERF_SEL_tcp_prefetcher_reads', + 'DB_PERF_SEL_tcp_preloader_flushes', + 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', + 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', + 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 'DB_PERF_SEL_tiles_decomp_on_expclear', + 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', + 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', + 'DB_PERF_SEL_tl_expand_squads', + 'DB_PERF_SEL_tl_flush_expand_squads', + 'DB_PERF_SEL_tl_in_fast_z_stall', + 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', + 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', + 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', + 'DB_PERF_SEL_tl_preZ_squads', + 'DB_PERF_SEL_tl_stencil_locked_stall', + 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', + 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', + 'DB_PERF_SEL_tl_z_fetch_stall', + 'DB_PERF_SEL_ts_events_pws_enable', + 'DB_PERF_SEL_ts_tc_update_stall', + 'DB_PERF_SEL_tsc_insert_summarize_stall', + 'DB_PERF_SEL_unmapped_z_tile_culled', + 'DB_PERF_SEL_zf_plane_multicycle', 'DB_VPORT_CHANGED_EVENT', + 'DCCG_AUDIO_DTO0_SOURCE_SEL', 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', + 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', + 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 'DCCG_AUDIO_DTO_USE_512FBR_DTO', + 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', + 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', + 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', + 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', + 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', + 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', + 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', + 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', + 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', + 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', + 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', + 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', + 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', + 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', + 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED', 'DCEAZ_HWID', + 'DCE_HWIP', 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_OFF', + 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE', + 'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK', + 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', + 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', + 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', + 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', + 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', + 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', + 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', + 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', + 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', + 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', + 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', + 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', + 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', + 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', + 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN', + 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', + 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', + 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', + 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', + 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', + 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', + 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', + 'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE', + 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', + 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', + 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', + 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', + 'DCIOCHIP_REF_27_SRC_SEL', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', + 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', + 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', + 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET', + 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', + 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL', + 'DCIO_DC_GENERICB_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', + 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', + 'DCIO_DC_GPU_TIMER_READ_SELECT', + 'DCIO_DC_GPU_TIMER_START_POSITION', + 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', + 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', + 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', + 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', + 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', + 'DCIO_DPCS_INTERRUPT_TYPE', + 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', + 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', + 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', + 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 'DCIO_EXT_VSYNC_MASK_NONE', 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', + 'DCIO_EXT_VSYNC_MASK_PIPE0', 'DCIO_EXT_VSYNC_MASK_PIPE1', + 'DCIO_EXT_VSYNC_MASK_PIPE2', 'DCIO_EXT_VSYNC_MASK_PIPE3', + 'DCIO_EXT_VSYNC_MASK_PIPE4', 'DCIO_EXT_VSYNC_MASK_PIPE5', + 'DCIO_EXT_VSYNC_MUX_GENERICB', 'DCIO_EXT_VSYNC_MUX_OTG0', + 'DCIO_EXT_VSYNC_MUX_OTG1', 'DCIO_EXT_VSYNC_MUX_OTG2', + 'DCIO_EXT_VSYNC_MUX_OTG3', 'DCIO_EXT_VSYNC_MUX_OTG4', + 'DCIO_EXT_VSYNC_MUX_OTG5', 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 'DCIO_GENERICA_SEL_GENERICA_DCCG', 'DCIO_GENERICA_SEL_STEREOSYNC', + 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 'DCIO_GENERICB_SEL_STEREOSYNC', 'DCIO_GENERICB_SEL_SYNCEN', + 'DCIO_GENLK_CLK_GSL_MASK', 'DCIO_GENLK_CLK_GSL_MASK_NO', + 'DCIO_GENLK_CLK_GSL_MASK_STEREO', + 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', + 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', + 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', + 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', + 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', + 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', + 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', + 'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_PHY_HPO_ENC_SRC_SEL', + 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', + 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', + 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', + 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', + 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', + 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', + 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', + 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', + 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', + 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', + 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', + 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', + 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', + 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 'DCI_HWID', + 'DCI_HWIP', 'DCO_HWID', 'DC_DMCUB_INT_TYPE', + 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', + 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 'DC_SMU_INTERRUPT_ENABLE', 'DDCL_HWID', 'DDID_VMID_CNTL', + 'DDID_VMID_PIPE', 'DEBUG_BUS_SELECT_ABM0', + 'DEBUG_BUS_SELECT_ABM1', 'DEBUG_BUS_SELECT_ABM2', + 'DEBUG_BUS_SELECT_ABM3', 'DEBUG_BUS_SELECT_ABM_RESERVED0', + 'DEBUG_BUS_SELECT_ABM_RESERVED1', 'DEBUG_BUS_SELECT_DPG0', + 'DEBUG_BUS_SELECT_DPG1', 'DEBUG_BUS_SELECT_DPG2', + 'DEBUG_BUS_SELECT_DPG3', 'DEBUG_BUS_SELECT_DPG_RESERVED0', + 'DEBUG_BUS_SELECT_DPG_RESERVED1', 'DEBUG_BUS_SELECT_FMT0', + 'DEBUG_BUS_SELECT_FMT1', 'DEBUG_BUS_SELECT_FMT2', + 'DEBUG_BUS_SELECT_FMT3', 'DEBUG_BUS_SELECT_FMT_RESERVED0', + 'DEBUG_BUS_SELECT_FMT_RESERVED1', 'DEBUG_BUS_SELECT_OPPBUF0', + 'DEBUG_BUS_SELECT_OPPBUF1', 'DEBUG_BUS_SELECT_OPPBUF2', + 'DEBUG_BUS_SELECT_OPPBUF3', 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', + 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', 'DEBUG_BUS_SELECT_OPP_PIPE0', + 'DEBUG_BUS_SELECT_OPP_PIPE1', 'DEBUG_BUS_SELECT_OPP_PIPE2', + 'DEBUG_BUS_SELECT_OPP_PIPE3', + 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', + 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', 'DECERR', + 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE', + 'DETILE_BUFFER_PACKER_IS_DISABLE', + 'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES', + 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', + 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', + 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', + 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', + 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', + 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', + 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', + 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', + 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', + 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', 'DFX_DAP_HWID', + 'DFX_HWID', 'DF_HWID', 'DF_HWIP', 'DIFFERENT_RGB', + 'DIG_10BIT_TEST_PATTERN', 'DIG_ALL_PIXEL', + 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', + 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', + 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD_SELECT', 'DIG_BE_CNTL_MODE', + 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', + 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', + 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', + 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE', + 'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON', + 'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT', + 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0', + 'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2', + 'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_RESERVED', + 'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1', + 'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3', + 'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_1_PIX_PER_CYCLE', + 'DIG_FIFO_2_PIX_PER_CYCLE', 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL', + 'DIG_FIFO_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', + 'DIG_FIFO_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED', + 'DIG_FIFO_OUTPUT_PROCESSING_MODE', 'DIG_FIFO_OVERFLOW_OCCURRED', + 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', + 'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', + 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_INPUT_PIXEL_SEL', + 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', + 'DIG_ODD_PIXEL_ONLY', 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', + 'DIG_OUTPUT_CRC_DATA_SEL', 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 'DIG_OUTPUT_CRC_FOR_AUDIO', 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 'DIG_OUTPUT_CRC_FOR_VBI', 'DIG_OUTPUT_CRC_ON_LINK0', + 'DIG_OUTPUT_CRC_ON_LINK1', 'DIG_PAIR_PIXELS', + 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', 'DIG_SINGLETON_PIXELS', + 'DIG_SL_PIXEL_GROUPING', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', + 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', + 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH', + 'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT', + 'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP', + 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', + 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', + 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', + 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', + 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', + 'DIO_DBG_BLOCK_SEL', 'DIO_DBG_BLOCK_SEL_AUX0', + 'DIO_DBG_BLOCK_SEL_AUX1', 'DIO_DBG_BLOCK_SEL_AUX2', + 'DIO_DBG_BLOCK_SEL_AUX3', 'DIO_DBG_BLOCK_SEL_AUX4', + 'DIO_DBG_BLOCK_SEL_DIGA', 'DIO_DBG_BLOCK_SEL_DIGB', + 'DIO_DBG_BLOCK_SEL_DIGC', 'DIO_DBG_BLOCK_SEL_DIGD', + 'DIO_DBG_BLOCK_SEL_DIGE', 'DIO_DBG_BLOCK_SEL_DIGFE_A', + 'DIO_DBG_BLOCK_SEL_DIGFE_B', 'DIO_DBG_BLOCK_SEL_DIGFE_C', + 'DIO_DBG_BLOCK_SEL_DIGFE_D', 'DIO_DBG_BLOCK_SEL_DIGFE_E', + 'DIO_DBG_BLOCK_SEL_DIO', 'DIO_DBG_BLOCK_SEL_DPA', + 'DIO_DBG_BLOCK_SEL_DPB', 'DIO_DBG_BLOCK_SEL_DPC', + 'DIO_DBG_BLOCK_SEL_DPD', 'DIO_DBG_BLOCK_SEL_DPE', + 'DIO_DBG_BLOCK_SEL_DPFE_A', 'DIO_DBG_BLOCK_SEL_DPFE_B', + 'DIO_DBG_BLOCK_SEL_DPFE_C', 'DIO_DBG_BLOCK_SEL_DPFE_D', + 'DIO_DBG_BLOCK_SEL_DPFE_E', 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', + 'DIO_DBG_BLOCK_SEL_RESERVED', 'DIO_FIFO_ERROR', + 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10', + 'DIO_FIFO_ERROR_11', + 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', 'DIO_HWID', + 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', + 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', + 'DISABLE_DEBUG', 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', + 'DISABLE_PWL', 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', + 'DISABLE_THE_FEATURE', 'DISABLE_THE_INTERRUPT', + 'DISCOVERY_TABLE_SIGNATURE', 'DISPCLK_CHG_FWD_CORR_DISABLE', + 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', + 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', + 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1', + 'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED', + 'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED', + 'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4', + 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', + 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', + 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', + 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', + 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', + 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', + 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', + 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', + 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', + 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', + 'DI_SRC_SEL_RESERVED', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', + 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', + 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', + 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', + 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', + 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', + 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', + 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', + 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', + 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', + 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE', + 'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE', + 'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL', + 'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST', + 'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS', + 'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON', + 'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL', + 'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF', + 'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT', + 'DMU_DC_GPU_TIMER_START_POSITION', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', + 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', + 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', + 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', + 'DMU_HWID', 'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE', + 'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK', + 'DOUT_I2C_ACK_TO_CLEAN', + 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_ABORT_XFER', + 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', + 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', + 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', + 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', + 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', + 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDCVGA', + 'DOUT_I2C_CONTROL_SEND_RESET', + 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', + 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', + 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', + 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', + 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', + 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', + 'DOUT_I2C_DDC_SPEED_THRESHOLD', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', + 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', + 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', + 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPHY_8B10B_CUR_DISP', + 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', + 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', + 'DPHY_8B10B_RESETET', + 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', + 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', + 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', + 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', + 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', + 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', + 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', + 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', + 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', + 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', + 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', + 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', + 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', + 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', + 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', + 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', + 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', + 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', + 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', + 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', + 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', + 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', + 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', + 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', + 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', + 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', + 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', + 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', + 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', + 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', + 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', + 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', + 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', + 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', + 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', + 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', + 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', + 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B', + 'DPTE_GROUP_SIZE_64B', 'DP_128B132B', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS', + 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', + 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', + 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD_SEL', + 'DP_AUX_CONTROL_NO_HPD_SELECTED', 'DP_AUX_CONTROL_TEST_MODE', + 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 'DP_AUX_CONTROL_TEST_MODE_ENABLE', + 'DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', + 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', + 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', + 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', + 'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS', + 'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW', + 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY', + 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', + 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', + 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', + 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 'DP_AUX_SW_CONTROL_LS_READ_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', + 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', + 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH', + 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', + 'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC', + 'DP_COMPONENT_DEPTH_8BPC', 'DP_CP_ENCRYPTION_TYPE', + 'DP_CP_ENCRYPTION_TYPE_0', 'DP_CP_ENCRYPTION_TYPE_1', + 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', + 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', + 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', + 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', + 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', + 'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE', + 'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE', + 'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY', + 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_LLCP', + 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 'DP_DPHY_SYM32_CRC_START_TP_START', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', + 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE', + 'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_ENCRYPT_TYPE0', + 'DP_DPHY_SYM32_ENCRYPT_TYPE1', 'DP_DPHY_SYM32_LT_TPS1', + 'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET', + 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED', + 'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', + 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_STATUS_ENABLED', 'DP_DPHY_SYM32_STATUS_IDLE', + 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', + 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_SIMPLE_422', + 'DP_DSC_DISABLE', 'DP_DSC_MODE', 'DP_DSC_NATIVE_422_420', + 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', + 'DP_DTO_DS_DISABLE', 'DP_EMBEDDED_PANEL', + 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', + 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', + 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE', + 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', + 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', + 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', + 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', + 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', + 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', + 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', + 'DP_MSE_SAT_ENCRYPT0', 'DP_MSE_SAT_ENCRYPT0_DISABLED', + 'DP_MSE_SAT_ENCRYPT0_ENABLED', 'DP_MSE_SAT_ENCRYPT1', + 'DP_MSE_SAT_ENCRYPT1_DISABLED', 'DP_MSE_SAT_ENCRYPT1_ENABLED', + 'DP_MSE_SAT_ENCRYPT2', 'DP_MSE_SAT_ENCRYPT2_DISABLED', + 'DP_MSE_SAT_ENCRYPT2_ENABLED', 'DP_MSE_SAT_ENCRYPT3', + 'DP_MSE_SAT_ENCRYPT3_DISABLED', 'DP_MSE_SAT_ENCRYPT3_ENABLED', + 'DP_MSE_SAT_ENCRYPT4', 'DP_MSE_SAT_ENCRYPT4_DISABLED', + 'DP_MSE_SAT_ENCRYPT4_ENABLED', 'DP_MSE_SAT_ENCRYPT5', + 'DP_MSE_SAT_ENCRYPT5_DISABLED', 'DP_MSE_SAT_ENCRYPT5_ENABLED', + 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', + 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', + 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', + 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', + 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', + 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', + 'DP_ONE_PIXEL_PER_CYCLE', 'DP_PIXEL_ENCODING', + 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', + 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', + 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM', + 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', + 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', + 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', + 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', + 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', + 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', + 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', + 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', + 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', + 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', + 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', + 'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE', + 'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET', + 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', + 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT', + 'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL', + 'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL', + 'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', + 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET', + 'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1', + 'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE', + 'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID', + 'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF', + 'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', + 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET', + 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE', + 'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED', + 'DP_SYM32_ENC_PENDING', + 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', + 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', + 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY', + 'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW', + 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_TWO_PIXEL_PER_CYCLE', + 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', 'DP_UDI_4_LANES', + 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', + 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', + 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', + 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', + 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL', + 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', + 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', + 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', + 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', + 'DSCCIF_BITS_PER_COMPONENT_ENUM', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', + 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 'DSCC_BITS_PER_COMPONENT_ENUM', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCC_DSC_VERSION_MAJOR_ENUM', + 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', + 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', + 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', + 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', + 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', + 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', + 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL', + 'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH', + 'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT', + 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', + 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', + 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE', + 'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS', + 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL', + 'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1', + 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', + 'DS_REF_SRC', 'DTO_FORCE_BYPASS', 'DTO_FORCE_NO_BYPASS', + 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', + 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', + 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', + 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', + 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', + 'DWB_CRC_CONT_EN_CONT', 'DWB_CRC_CONT_EN_ENUM', + 'DWB_CRC_CONT_EN_ONE_SHOT', 'DWB_CRC_SRC_SEL_DWB_IN', + 'DWB_CRC_SRC_SEL_DWB_OUT', 'DWB_CRC_SRC_SEL_ENUM', + 'DWB_CRC_SRC_SEL_OGAM_OUT', 'DWB_DATA_OVERFLOW_INT_TYPE_0', + 'DWB_DATA_OVERFLOW_INT_TYPE_1', 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC', + 'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED', + 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', + 'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A', + 'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM', + 'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG', + 'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS', + 'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS', + 'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS', + 'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS', + 'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD', + 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM', + 'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM', + 'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB', + 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM', + 'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', + 'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE', + 'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS', + 'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED', + 'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM', + 'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE', + 'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM', + 'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16', + 'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4', + 'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM', + 'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', + 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', + 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', + 'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY', + 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', + 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', + 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', + 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', + 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', + 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', + 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', + 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', + 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', + 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', + 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', + 'EFC_BGR101111_FLOAT', 'EFC_BGR565', + 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', + 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', + 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', + 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', + 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', + 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', + 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', + 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', + 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', + 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', + 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', + 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', + 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', + 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', + 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', + 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', + 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', + 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', + 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', + 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', + 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', + 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', + 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', + 'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK', + 'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED', + 'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL', + 'ENABLE_LEGACY_PIPELINE', 'ENABLE_MEM_PWR_CTRL', + 'ENABLE_NGG_PIPELINE', 'ENABLE_PWL', 'ENABLE_TF0_OPT', + 'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK', + 'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END', + 'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE', + 'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS', + 'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC', + 'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC', + 'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE', + 'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA', + 'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', + 'ENUM_DPG_FIELD_POLARITY', + 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', + 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', + 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE', + 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', + 'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE', + 'ENUM_DP_DPHY_SYM32_MODE', 'ENUM_DP_DPHY_SYM32_NUM_LANES', + 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_STATUS', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE', + 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT', + 'ENUM_DP_SYM32_ENC_AUDIO_MUTE', + 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE', + 'ENUM_DP_SYM32_ENC_CRC_VALID', + 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH', + 'ENUM_DP_SYM32_ENC_ENABLE', + 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION', + 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE', + 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM', + 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE', + 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET', + 'ENUM_DP_SYM32_ENC_SDP_PRIORITY', + 'ENUM_DP_SYM32_ENC_SOF_REFERENCE', + 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_DSCRM_DISABLE', + 'ENUM_DSCRM_EN', 'ENUM_DSCRM_ENABLE', 'ENUM_NUM_SIMD_PER_CU', + 'ES_STAGE_DS', 'ES_STAGE_OFF', 'ES_STAGE_REAL', 'EXOKAY', + 'EXPANSION_MODE', 'EXPANSION_MODE_CONSERVATIVE', + 'EXPANSION_MODE_OPTIMAL', 'EXPANSION_MODE_ZERO', + 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', 'EXPORT_4C_16BPC', + 'EXPORT_4C_32BPC', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z', + 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'FAULT_FAIL', + 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FCH_HWID', + 'FCH_USB_PD_HWID', 'FC_EYE_SELECTION_ENUM', + 'FC_EYE_SELECTION_LEFT_EYE', 'FC_EYE_SELECTION_RIGHT_EYE', + 'FC_EYE_SELECTION_STEREO_DIS', 'FC_FRAME_CAPTURE_RATE_ENUM', + 'FC_FRAME_CAPTURE_RATE_FULL', 'FC_FRAME_CAPTURE_RATE_HALF', + 'FC_FRAME_CAPTURE_RATE_QUARTER', 'FC_FRAME_CAPTURE_RATE_THIRD', + 'FC_STEREO_EYE_POLARITY_ENUM', 'FC_STEREO_EYE_POLARITY_LEFT', + 'FC_STEREO_EYE_POLARITY_RIGHT', 'FEC_ACTIVE_STATUS', 'FIX_S2_13', + 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', 'FLIP_RATE', + 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', 'FLIP_RATE_3', + 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', 'FLIP_RATE_7', + 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS', + 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', + 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', + 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', + 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', + 'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', + 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 'FMT_CLAMP_CNTL_COLOR_FORMAT', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', + 'FMT_CONTROL_PIXEL_ENCODING', + 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', + 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 'FMT_CONTROL_SUBSAMPLING_MODE', + 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', + 'FMT_CONTROL_SUBSAMPLING_ORDER', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', + 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', + 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', + 'FMT_FRAME_RANDOM_ENABLE_CONTROL', + 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM', + 'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS', + 'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD', + 'FMT_RGB_RANDOM_ENABLE_CONTROL', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', + 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', + 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', + 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00', + 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', + 'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE', + 'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', + 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', + 'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0', + 'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO', + 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', + 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', + 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', + 'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR', + 'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R', + 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', + 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', + 'FRAME_TYPE_DESTROY', 'FUSE_HWID', 'ForceControl', 'GAMUT_COEF', + 'GAMUT_COEF_B', 'GATCL1RequestType', 'GATCL1_TYPE_BYPASS', + 'GATCL1_TYPE_NORMAL', 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', + 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', + 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', + 'GB_TILING_CONFIG_TABLE_SIZE', 'GC', 'GCRPerfSel', + 'GCR_PERF_SEL_ALL_REQ', + 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', + 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 'GCR_PERF_SEL_CPC_TCP_REQ', + 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', + 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 'GCR_PERF_SEL_CPF_TCP_REQ', + 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', + 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 'GCR_PERF_SEL_CPG_TCP_REQ', + 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE', + 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ', + 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 'GCR_PERF_SEL_PIO_TCP_REQ', + 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ', + 'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 'GCR_PERF_SEL_PM_TCP_REQ', + 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_RLC_ALL_REQ', 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ', + 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 'GCR_PERF_SEL_RLC_TCP_REQ', + 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA0_ALL_REQ', 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', + 'GCR_PERF_SEL_VIRT_REQ', 'GC_HWID', 'GC_HWIP', 'GC_TABLE_ID', + 'GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES', + 'GDDR6_MEM_TRAINING_OFFSET', 'GDS_PERFCOUNT_SELECT', + 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', + 'GDS_PERF_SEL_SE0_2COMP_REQ', 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_GDS_RD_OP', 'GDS_PERF_SEL_SE0_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_GDS_WR_OP', + 'GDS_PERF_SEL_SE0_NORET', 'GDS_PERF_SEL_SE0_ORD_CNT', + 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_RET', + 'GDS_PERF_SEL_SE1_2COMP_REQ', 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_GDS_RD_OP', 'GDS_PERF_SEL_SE1_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_GDS_WR_OP', + 'GDS_PERF_SEL_SE1_NORET', 'GDS_PERF_SEL_SE1_ORD_CNT', + 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_RET', + 'GDS_PERF_SEL_SE2_2COMP_REQ', 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_GDS_RD_OP', 'GDS_PERF_SEL_SE2_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_GDS_WR_OP', + 'GDS_PERF_SEL_SE2_NORET', 'GDS_PERF_SEL_SE2_ORD_CNT', + 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_RET', + 'GDS_PERF_SEL_SE3_2COMP_REQ', 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_GDS_RD_OP', 'GDS_PERF_SEL_SE3_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_GDS_WR_OP', + 'GDS_PERF_SEL_SE3_NORET', 'GDS_PERF_SEL_SE3_ORD_CNT', + 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_RET', + 'GDS_PERF_SEL_SE4_2COMP_REQ', 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE4_GDS_RD_OP', 'GDS_PERF_SEL_SE4_GDS_REL_OP', + 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE4_GDS_WR_OP', + 'GDS_PERF_SEL_SE4_NORET', 'GDS_PERF_SEL_SE4_ORD_CNT', + 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE4_RET', + 'GDS_PERF_SEL_SE5_2COMP_REQ', 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE5_GDS_RD_OP', 'GDS_PERF_SEL_SE5_GDS_REL_OP', + 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE5_GDS_WR_OP', + 'GDS_PERF_SEL_SE5_NORET', 'GDS_PERF_SEL_SE5_ORD_CNT', + 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE5_RET', + 'GDS_PERF_SEL_SE6_2COMP_REQ', 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE6_GDS_RD_OP', 'GDS_PERF_SEL_SE6_GDS_REL_OP', + 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE6_GDS_WR_OP', + 'GDS_PERF_SEL_SE6_NORET', 'GDS_PERF_SEL_SE6_ORD_CNT', + 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE6_RET', + 'GDS_PERF_SEL_SE7_2COMP_REQ', 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE7_GDS_RD_OP', 'GDS_PERF_SEL_SE7_GDS_REL_OP', + 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE7_GDS_WR_OP', + 'GDS_PERF_SEL_SE7_NORET', 'GDS_PERF_SEL_SE7_ORD_CNT', + 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE7_RET', + 'GDS_PERF_SEL_WBUF_WR', 'GDS_PERF_SEL_WR_COMP', + 'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT', + 'GE2_SE_PERFCOUNT_SELECT', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', + 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', + 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', + 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED', + 'GEN_ONE', 'GEN_RESERVED', 'GEN_TWO', 'GEN_ZERO', + 'GFX_BUF_MAX_DESC', 'GFX_CMD_ID_AUTOLOAD_RLC', + 'GFX_CMD_ID_BOOT_CFG', 'GFX_CMD_ID_DESTROY_TMR', + 'GFX_CMD_ID_DESTROY_VMR', 'GFX_CMD_ID_GET_FW_ATTESTATION', + 'GFX_CMD_ID_INVOKE_CMD', 'GFX_CMD_ID_LOAD_ASD', + 'GFX_CMD_ID_LOAD_IP_FW', 'GFX_CMD_ID_LOAD_TA', + 'GFX_CMD_ID_LOAD_TOC', 'GFX_CMD_ID_MASK', 'GFX_CMD_ID_PROG_REG', + 'GFX_CMD_ID_SAVE_RESTORE', 'GFX_CMD_ID_SETUP_TMR', + 'GFX_CMD_ID_SETUP_VMR', 'GFX_CMD_ID_SRIOV_SPATIAL_PART', + 'GFX_CMD_ID_UNLOAD_TA', 'GFX_CMD_RESERVED_MASK', + 'GFX_CMD_RESPONSE_MASK', 'GFX_CMD_STATUS_MASK', + 'GFX_CTRL_CMD_ID_CAN_INIT_RINGS', 'GFX_CTRL_CMD_ID_CONSUME_CMD', + 'GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING', + 'GFX_CTRL_CMD_ID_DESTROY_RINGS', 'GFX_CTRL_CMD_ID_DISABLE_INT', + 'GFX_CTRL_CMD_ID_ENABLE_INT', 'GFX_CTRL_CMD_ID_GBR_IH_SET', + 'GFX_CTRL_CMD_ID_INIT_GPCOM_RING', + 'GFX_CTRL_CMD_ID_INIT_RBI_RING', 'GFX_CTRL_CMD_ID_MAX', + 'GFX_CTRL_CMD_ID_MODE1_RST', 'GFX_FLAG_RESPONSE', + 'GFX_FW_TYPE_ACCUM_CTRL_RAM', 'GFX_FW_TYPE_ACP', + 'GFX_FW_TYPE_CAP', 'GFX_FW_TYPE_CP_CE', 'GFX_FW_TYPE_CP_ME', + 'GFX_FW_TYPE_CP_MEC', 'GFX_FW_TYPE_CP_MEC_ME1', + 'GFX_FW_TYPE_CP_MEC_ME2', 'GFX_FW_TYPE_CP_MES', + 'GFX_FW_TYPE_CP_MES_KIQ', 'GFX_FW_TYPE_CP_PFP', + 'GFX_FW_TYPE_DISCRETE_USB4', 'GFX_FW_TYPE_DMCU_ERAM', + 'GFX_FW_TYPE_DMCU_ISR', 'GFX_FW_TYPE_DMUB', + 'GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM', + 'GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS', + 'GFX_FW_TYPE_GLOBAL_TAP_DELAYS', 'GFX_FW_TYPE_IMU_D', + 'GFX_FW_TYPE_IMU_I', 'GFX_FW_TYPE_ISP', 'GFX_FW_TYPE_ISP_DATA', + 'GFX_FW_TYPE_JPEG_RAM', 'GFX_FW_TYPE_LSDMA', 'GFX_FW_TYPE_MAX', + 'GFX_FW_TYPE_MES_KIQ_STACK', 'GFX_FW_TYPE_MES_STACK', + 'GFX_FW_TYPE_MMSCH', 'GFX_FW_TYPE_NONE', 'GFX_FW_TYPE_P2S_TABLE', + 'GFX_FW_TYPE_PPTABLE', 'GFX_FW_TYPE_REG_LIST', + 'GFX_FW_TYPE_RLCG_SCRATCH_SR', 'GFX_FW_TYPE_RLCP_CAM', + 'GFX_FW_TYPE_RLCP_SCRATCH_SR', 'GFX_FW_TYPE_RLCV_SCRATCH_SR', + 'GFX_FW_TYPE_RLC_DRAM_BOOT', 'GFX_FW_TYPE_RLC_G', + 'GFX_FW_TYPE_RLC_IRAM', 'GFX_FW_TYPE_RLC_P', + 'GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM', + 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL', + 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM', + 'GFX_FW_TYPE_RLC_SPP_CAM_EXT', 'GFX_FW_TYPE_RLC_SRM_DRAM_SR', + 'GFX_FW_TYPE_RLC_V', 'GFX_FW_TYPE_RLX6_DRAM_SR', + 'GFX_FW_TYPE_RS64_KIQ', 'GFX_FW_TYPE_RS64_KIQ_STACK', + 'GFX_FW_TYPE_RS64_ME', 'GFX_FW_TYPE_RS64_MEC', + 'GFX_FW_TYPE_RS64_MEC_P0_STACK', 'GFX_FW_TYPE_RS64_MEC_P1_STACK', + 'GFX_FW_TYPE_RS64_MEC_P2_STACK', 'GFX_FW_TYPE_RS64_MEC_P3_STACK', + 'GFX_FW_TYPE_RS64_MES', 'GFX_FW_TYPE_RS64_MES_STACK', + 'GFX_FW_TYPE_RS64_ME_P0_STACK', 'GFX_FW_TYPE_RS64_ME_P1_STACK', + 'GFX_FW_TYPE_RS64_PFP', 'GFX_FW_TYPE_RS64_PFP_P0_STACK', + 'GFX_FW_TYPE_RS64_PFP_P1_STACK', 'GFX_FW_TYPE_SDMA0', + 'GFX_FW_TYPE_SDMA0_JT', 'GFX_FW_TYPE_SDMA0_PG_CONTEXT', + 'GFX_FW_TYPE_SDMA1', 'GFX_FW_TYPE_SDMA1_JT', + 'GFX_FW_TYPE_SDMA1_PG_CONTEXT', 'GFX_FW_TYPE_SDMA2', + 'GFX_FW_TYPE_SDMA3', 'GFX_FW_TYPE_SDMA4', 'GFX_FW_TYPE_SDMA5', + 'GFX_FW_TYPE_SDMA6', 'GFX_FW_TYPE_SDMA7', + 'GFX_FW_TYPE_SDMA_UCODE_TH0', 'GFX_FW_TYPE_SDMA_UCODE_TH1', + 'GFX_FW_TYPE_SE0_MUX_SELECT_RAM', 'GFX_FW_TYPE_SE0_TAP_DELAYS', + 'GFX_FW_TYPE_SE1_MUX_SELECT_RAM', 'GFX_FW_TYPE_SE1_TAP_DELAYS', + 'GFX_FW_TYPE_SE2_TAP_DELAYS', 'GFX_FW_TYPE_SE3_TAP_DELAYS', + 'GFX_FW_TYPE_SMU', 'GFX_FW_TYPE_TA', 'GFX_FW_TYPE_TOC', + 'GFX_FW_TYPE_UMSCH_CMD_BUFFER', 'GFX_FW_TYPE_UMSCH_DATA', + 'GFX_FW_TYPE_UMSCH_UCODE', 'GFX_FW_TYPE_USB_DP_COMBO_PHY', + 'GFX_FW_TYPE_UVD', 'GFX_FW_TYPE_UVD1', 'GFX_FW_TYPE_VCE', + 'GFX_FW_TYPE_VCN', 'GFX_FW_TYPE_VCN0_RAM', 'GFX_FW_TYPE_VCN1', + 'GFX_FW_TYPE_VCN1_RAM', 'GFX_FW_TYPE_VPE', 'GFX_FW_TYPE_VPEC_FW1', + 'GFX_FW_TYPE_VPEC_FW2', 'GL0V_CACHE_POLICIES', + 'GL0V_CACHE_POLICY_HIT_EVICT', 'GL0V_CACHE_POLICY_HIT_LRU', + 'GL0V_CACHE_POLICY_MISS_EVICT', 'GL0V_CACHE_POLICY_MISS_LRU', + 'GL1A_PERF_SEL', 'GL1A_PERF_SEL_ARB_REQUESTS', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY', + 'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0', + 'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2', + 'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', + 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', + 'GL1C_PERF_SEL_GL2_REQ_READ', 'GL1C_PERF_SEL_GL2_REQ_READ_128B', + 'GL1C_PERF_SEL_GL2_REQ_READ_32B', + 'GL1C_PERF_SEL_GL2_REQ_READ_64B', + 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 'GL1C_PERF_SEL_GL2_REQ_WRITE', 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', + 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', + 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0', + 'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10', + 'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12', + 'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14', + 'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16', + 'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18', + 'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2', + 'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21', + 'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23', + 'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25', + 'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27', + 'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4', + 'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6', + 'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8', + 'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_MISS', + 'GL1C_PERF_SEL_REQ_NOP_ACK', 'GL1C_PERF_SEL_REQ_NOP_RTN0', + 'GL1C_PERF_SEL_REQ_READ', 'GL1C_PERF_SEL_REQ_READ_128B', + 'GL1C_PERF_SEL_REQ_READ_32B', 'GL1C_PERF_SEL_REQ_READ_64B', + 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', + 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', + 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', + 'GL1C_PERF_SEL_REQ_SHADER_INV', 'GL1C_PERF_SEL_REQ_WRITE', + 'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B', + 'GL1C_PERF_SEL_STALL_GCR_INV', 'GL1C_PERF_SEL_STALL_GL2_GL1', + 'GL1C_PERF_SEL_STALL_LFIFO_FULL', + 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', + 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', + 'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE', + 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 'GL1C_PERF_SEL_UTCL0_REQUEST', + 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 'GL1H_REQ_PERF_SEL', 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', + 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', + 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', 'GL1H_REQ_PERF_SEL_BUSY', + 'GL1H_REQ_PERF_SEL_CYCLE', 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', + 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', + 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1H_REQ_PERF_SEL_STALL_GL1_0', 'GL1H_REQ_PERF_SEL_STALL_GL1_1', + 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', + 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', 'GL1_CACHE_POLICIES', + 'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU', + 'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU', + 'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS', + 'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', + 'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1', + 'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3', + 'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5', + 'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', + 'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11', + 'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13', + 'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15', + 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', + 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', + 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', + 'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', + 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', + 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ', + 'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ', + 'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ', + 'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', + 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', + 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', + 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', + 'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', + 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_DCC_IN_XFC', 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', + 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', + 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', + 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', + 'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ', + 'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL', + 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', + 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', + 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', + 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', + 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING', + 'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B', + 'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 'GL2C_PERF_SEL_EA_RDRET_NACK', + 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK', + 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT', + 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT', + 'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE', + 'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD', + 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV', + 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE', + 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', + 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', + 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', + 'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ', + 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', + 'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ', + 'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ', + 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ', + 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL', + 'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_MDC_TAG_HIT', + 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 'GL2C_PERF_SEL_MDC_TAG_STALL', + 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS', + 'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE', + 'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0', + 'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE', + 'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE', + 'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', + 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', + 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', + 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', + 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', + 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', + 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', + 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', + 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', + 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', + 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', + 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', + 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', + 'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT', + 'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC', + 'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_MES', + 'GL2_EA_CID_RLC', 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', + 'GL2_EA_CID_SQC', 'GL2_EA_CID_TCPMETA', 'GL2_EA_CID_UTCL2', + 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', 'GL2_NACKS', + 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT', + 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32', + 'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32', + 'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32', + 'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32', + 'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', + 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64', + 'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', + 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', + 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', + 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', + 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', + 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', + 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', + 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', + 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', + 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', + 'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64', + 'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64', + 'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64', + 'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64', + 'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64', + 'GL2_OP_ATOMIC_UMAX_8', 'GL2_OP_ATOMIC_UMAX_RTN_32', + 'GL2_OP_ATOMIC_UMAX_RTN_64', 'GL2_OP_ATOMIC_UMIN_32', + 'GL2_OP_ATOMIC_UMIN_64', 'GL2_OP_ATOMIC_UMIN_8', + 'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64', + 'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64', + 'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64', + 'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', + 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', + 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', + 'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'GL2_OP_WRITE', 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', + 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', + 'GLOBAL_STATUS_FLUSH_STATUS', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', + 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', + 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', + 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', + 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', + 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', + 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', + 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY', + 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', + 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', + 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', + 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', + 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', + 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', + 'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1H_BUSY', + 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', + 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', + 'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PH_BUSY', + 'GRBM_PERF_SEL_PMM_BUSY', 'GRBM_PERF_SEL_RLC_BUSY', + 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', + 'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', + 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', + 'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', + 'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY', + 'GRBM_SE0_PERF_SEL', 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 'GRBM_SE0_PERF_SEL_CB_BUSY', 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 'GRBM_SE0_PERF_SEL_COUNT', 'GRBM_SE0_PERF_SEL_DB_BUSY', + 'GRBM_SE0_PERF_SEL_DB_CLEAN', 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE0_PERF_SEL_GL1H_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY', + 'GRBM_SE0_PERF_SEL_PC_BUSY', 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', + 'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL', + 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', + 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', + 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_GL1H_BUSY', + 'GRBM_SE1_PERF_SEL_PA_BUSY', 'GRBM_SE1_PERF_SEL_PC_BUSY', + 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', + 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', + 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_TCP_BUSY', + 'GRBM_SE1_PERF_SEL_USER_DEFINED', 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE2_PERF_SEL', 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 'GRBM_SE2_PERF_SEL_CB_BUSY', 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 'GRBM_SE2_PERF_SEL_COUNT', 'GRBM_SE2_PERF_SEL_DB_BUSY', + 'GRBM_SE2_PERF_SEL_DB_CLEAN', 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE2_PERF_SEL_GL1H_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY', + 'GRBM_SE2_PERF_SEL_PC_BUSY', 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', + 'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL', + 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', + 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', + 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_GL1H_BUSY', + 'GRBM_SE3_PERF_SEL_PA_BUSY', 'GRBM_SE3_PERF_SEL_PC_BUSY', + 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', + 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', + 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_TCP_BUSY', + 'GRBM_SE3_PERF_SEL_USER_DEFINED', 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE4_PERF_SEL', 'GRBM_SE4_PERF_SEL_BCI_BUSY', + 'GRBM_SE4_PERF_SEL_CB_BUSY', 'GRBM_SE4_PERF_SEL_CB_CLEAN', + 'GRBM_SE4_PERF_SEL_COUNT', 'GRBM_SE4_PERF_SEL_DB_BUSY', + 'GRBM_SE4_PERF_SEL_DB_CLEAN', 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE4_PERF_SEL_GL1H_BUSY', 'GRBM_SE4_PERF_SEL_PA_BUSY', + 'GRBM_SE4_PERF_SEL_PC_BUSY', 'GRBM_SE4_PERF_SEL_RMI_BUSY', + 'GRBM_SE4_PERF_SEL_SC_BUSY', 'GRBM_SE4_PERF_SEL_SPI_BUSY', + 'GRBM_SE4_PERF_SEL_SX_BUSY', 'GRBM_SE4_PERF_SEL_TA_BUSY', + 'GRBM_SE4_PERF_SEL_TCP_BUSY', 'GRBM_SE4_PERF_SEL_USER_DEFINED', + 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', 'GRBM_SE5_PERF_SEL', + 'GRBM_SE5_PERF_SEL_BCI_BUSY', 'GRBM_SE5_PERF_SEL_CB_BUSY', + 'GRBM_SE5_PERF_SEL_CB_CLEAN', 'GRBM_SE5_PERF_SEL_COUNT', + 'GRBM_SE5_PERF_SEL_DB_BUSY', 'GRBM_SE5_PERF_SEL_DB_CLEAN', + 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', 'GRBM_SE5_PERF_SEL_GL1H_BUSY', + 'GRBM_SE5_PERF_SEL_PA_BUSY', 'GRBM_SE5_PERF_SEL_PC_BUSY', + 'GRBM_SE5_PERF_SEL_RMI_BUSY', 'GRBM_SE5_PERF_SEL_SC_BUSY', + 'GRBM_SE5_PERF_SEL_SPI_BUSY', 'GRBM_SE5_PERF_SEL_SX_BUSY', + 'GRBM_SE5_PERF_SEL_TA_BUSY', 'GRBM_SE5_PERF_SEL_TCP_BUSY', + 'GRBM_SE5_PERF_SEL_USER_DEFINED', 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE6_PERF_SEL', 'GRBM_SE6_PERF_SEL_BCI_BUSY', + 'GRBM_SE6_PERF_SEL_CB_BUSY', 'GRBM_SE6_PERF_SEL_CB_CLEAN', + 'GRBM_SE6_PERF_SEL_COUNT', 'GRBM_SE6_PERF_SEL_DB_BUSY', + 'GRBM_SE6_PERF_SEL_DB_CLEAN', 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE6_PERF_SEL_GL1H_BUSY', 'GRBM_SE6_PERF_SEL_PA_BUSY', + 'GRBM_SE6_PERF_SEL_PC_BUSY', 'GRBM_SE6_PERF_SEL_RMI_BUSY', + 'GRBM_SE6_PERF_SEL_SC_BUSY', 'GRBM_SE6_PERF_SEL_SPI_BUSY', + 'GRBM_SE6_PERF_SEL_SX_BUSY', 'GRBM_SE6_PERF_SEL_TA_BUSY', + 'GRBM_SE6_PERF_SEL_TCP_BUSY', 'GRBM_SE6_PERF_SEL_USER_DEFINED', + 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', 'GRBM_SE7_PERF_SEL', + 'GRBM_SE7_PERF_SEL_BCI_BUSY', 'GRBM_SE7_PERF_SEL_CB_BUSY', + 'GRBM_SE7_PERF_SEL_CB_CLEAN', 'GRBM_SE7_PERF_SEL_COUNT', + 'GRBM_SE7_PERF_SEL_DB_BUSY', 'GRBM_SE7_PERF_SEL_DB_CLEAN', + 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', 'GRBM_SE7_PERF_SEL_GL1H_BUSY', + 'GRBM_SE7_PERF_SEL_PA_BUSY', 'GRBM_SE7_PERF_SEL_PC_BUSY', + 'GRBM_SE7_PERF_SEL_RMI_BUSY', 'GRBM_SE7_PERF_SEL_SC_BUSY', + 'GRBM_SE7_PERF_SEL_SPI_BUSY', 'GRBM_SE7_PERF_SEL_SX_BUSY', + 'GRBM_SE7_PERF_SEL_TA_BUSY', 'GRBM_SE7_PERF_SEL_TCP_BUSY', + 'GRBM_SE7_PERF_SEL_USER_DEFINED', 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', + 'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A', + 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', + 'GS_STAGE_ON', 'HARVEST_INFO', 'HARVEST_TABLE_SIGNATURE', + 'HDMICHARCLK_SRC_SEL', 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', + 'HDMICHARCLK_SRC_SEL_UNIPHYA', 'HDMICHARCLK_SRC_SEL_UNIPHYB', + 'HDMICHARCLK_SRC_SEL_UNIPHYC', 'HDMICHARCLK_SRC_SEL_UNIPHYD', + 'HDMICHARCLK_SRC_SEL_UNIPHYE', 'HDMISTREAMCLK_DTO_FORCE_DIS', + 'HDMISTREAMCLK_SRC_SEL', 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', + 'HDMI_ACP_SEND', 'HDMI_ACR_0_MULTIPLE_RESERVED', + 'HDMI_ACR_1_MULTIPLE', 'HDMI_ACR_2_MULTIPLE', + 'HDMI_ACR_3_MULTIPLE_RESERVED', 'HDMI_ACR_4_MULTIPLE', + 'HDMI_ACR_5_MULTIPLE_RESERVED', 'HDMI_ACR_6_MULTIPLE_RESERVED', + 'HDMI_ACR_7_MULTIPLE_RESERVED', 'HDMI_ACR_AUDIO_PRIORITY', + 'HDMI_ACR_CONT', 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', + 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', + 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', + 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', + 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', + 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', + 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', + 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', + 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', + 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', + 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', + 'HDMI_AUDIO_INFO_SEND', + 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'HDMI_BORROW_MODE', 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', + 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', + 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE', + 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', + 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', + 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', + 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', + 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_FRL', + 'HDMI_GC_AVMUTE', 'HDMI_GC_AVMUTE_CONT', + 'HDMI_GC_AVMUTE_CONT_DISABLE', 'HDMI_GC_AVMUTE_CONT_ENABLE', + 'HDMI_GC_AVMUTE_SET', 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', + 'HDMI_GC_CONT_DISABLE', 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', + 'HDMI_GC_PKT_SEND', 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', + 'HDMI_GENERIC_CONT_DISABLE', 'HDMI_GENERIC_CONT_ENABLE', + 'HDMI_GENERIC_NOT_SEND', 'HDMI_GENERIC_PKT_SEND', + 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', + 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', + 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', + 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', + 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', + 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', + 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', + 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', + 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', + 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', + 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', + 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', + 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', + 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', + 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDMI_STREAM_ENC_DB_DISABLE', + 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL', 'HDMI_STREAM_ENC_DB_ENABLE', + 'HDMI_STREAM_ENC_DCCG', 'HDMI_STREAM_ENC_DISABLE', + 'HDMI_STREAM_ENC_DISPLAY_PIPE', 'HDMI_STREAM_ENC_DSC_MODE', + 'HDMI_STREAM_ENC_ENABLE', 'HDMI_STREAM_ENC_ENABLE_CONTROL', + 'HDMI_STREAM_ENC_HARDWARE', 'HDMI_STREAM_ENC_NOT_RESET', + 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', + 'HDMI_STREAM_ENC_ODM_COMBINE_MODE', + 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', + 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', + 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT', + 'HDMI_STREAM_ENC_PIXEL_ENCODING', 'HDMI_STREAM_ENC_PROGRAMMABLE', + 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL', 'HDMI_STREAM_ENC_RESET', + 'HDMI_STREAM_ENC_RESET_CONTROL', 'HDMI_STREAM_ENC_STREAM_ACTIVE', + 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', + 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', + 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', 'HDMI_TB_ENC_ACP_SEND', + 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY', 'HDMI_TB_ENC_ACR_CONT', + 'HDMI_TB_ENC_ACR_N_MULTIPLE', 'HDMI_TB_ENC_ACR_SELECT', + 'HDMI_TB_ENC_ACR_SEND', 'HDMI_TB_ENC_ACR_SOURCE', + 'HDMI_TB_ENC_AUDIO_INFO_CONT', 'HDMI_TB_ENC_AUDIO_INFO_SEND', + 'HDMI_TB_ENC_CRC_SRC_SEL', 'HDMI_TB_ENC_CRC_TYPE', + 'HDMI_TB_ENC_DEEP_COLOR_DEPTH', 'HDMI_TB_ENC_DEFAULT_PAHSE', + 'HDMI_TB_ENC_DSC_MODE', 'HDMI_TB_ENC_ENABLE', + 'HDMI_TB_ENC_GC_AVMUTE', 'HDMI_TB_ENC_GC_AVMUTE_CONT', + 'HDMI_TB_ENC_GC_CONT', 'HDMI_TB_ENC_GC_SEND', + 'HDMI_TB_ENC_GENERIC_CONT', 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', + 'HDMI_TB_ENC_GENERIC_LOCK_EN', 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', + 'HDMI_TB_ENC_GENERIC_SEND', 'HDMI_TB_ENC_ISRC_CONT', + 'HDMI_TB_ENC_ISRC_SEND', 'HDMI_TB_ENC_METADATA_ENABLE', + 'HDMI_TB_ENC_PACKET_LINE_REFERENCE', 'HDMI_TB_ENC_PIXEL_ENCODING', + 'HDMI_TB_ENC_RESET', 'HDMI_TB_ENC_SYNC_PHASE', + 'HDMI_TMDS_OR_DP_8B10B', 'HDP_ENDIAN_8IN16', 'HDP_ENDIAN_8IN32', + 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE', 'HDP_HWID', 'HDP_HWIP', + 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', + 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', + 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', + 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', + 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED', + 'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE', + 'HPO_TOP_CLOCK_GATING_EN', + 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK', + 'HPO_TOP_REGISTER_GATED_DISPCLK', + 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', + 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL', + 'HPO_TOP_TEST_CLOCK_RESERVED', 'HS_GS', 'HS_STAGE_OFF', + 'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', + 'HUBP_BLANK_SW_DEASSERT', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', + 'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', + 'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON', + 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', + 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', + 'HWIP_MAX_INSTANCE', 'HW_ID_MAX', 'HW_MIRRORING_DISABLE', + 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', 'Hdp_SurfaceEndian', + 'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK', + 'IHC_INTERRUPT_DEST', 'IHC_INTERRUPT_LINE_STATUS', + 'IH_CLIENT_TYPE', 'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT', + 'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT', + 'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL', + 'IH_PERF_SEL_BIF_LINE0_FALLING', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 'IH_PERF_SEL_BIF_LINE0_RISING', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE', + 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', + 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', + 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', + 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', + 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', + 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', + 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', + 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', + 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', + 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', + 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', + 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', + 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', + 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', + 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', + 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', + 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR', + 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', + 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', + 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', + 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0', + 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', + 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', + 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', + 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', + 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', + 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', + 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', + 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_LOAD_RPTR', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', + 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0', + 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', + 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', + 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', + 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF2', + 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF4', + 'IH_PERF_SEL_RB1_FULL_VF5', 'IH_PERF_SEL_RB1_FULL_VF6', + 'IH_PERF_SEL_RB1_FULL_VF7', 'IH_PERF_SEL_RB1_FULL_VF8', + 'IH_PERF_SEL_RB1_FULL_VF9', 'IH_PERF_SEL_RB1_LOAD_RPTR', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', + 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 'IH_PERF_SEL_RB1_OVERFLOW_VF4', 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 'IH_PERF_SEL_RB1_OVERFLOW_VF6', 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 'IH_PERF_SEL_RB1_OVERFLOW_VF8', 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 'IH_PERF_SEL_RB1_RPTR_WRAP', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0', + 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', + 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', + 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', + 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF2', + 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF4', + 'IH_PERF_SEL_RB2_FULL_VF5', 'IH_PERF_SEL_RB2_FULL_VF6', + 'IH_PERF_SEL_RB2_FULL_VF7', 'IH_PERF_SEL_RB2_FULL_VF8', + 'IH_PERF_SEL_RB2_FULL_VF9', 'IH_PERF_SEL_RB2_LOAD_RPTR', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', + 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 'IH_PERF_SEL_RB2_OVERFLOW_VF4', 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 'IH_PERF_SEL_RB2_OVERFLOW_VF6', 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 'IH_PERF_SEL_RB2_OVERFLOW_VF8', 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 'IH_PERF_SEL_RB2_RPTR_WRAP', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID', + 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID', + 'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST', + 'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION', + 'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF', + 'IH_VF_RB_SELECT_RESERVED', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_FIFO_ERROR_TYPE', + 'INPUT_INNER_COVERAGE', 'INST_ID_ECC_INTERRUPT_MSG', + 'INST_ID_HOST_REG_TRAP_MSG', 'INST_ID_HW_TRAP', + 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ', + 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', + 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED', + 'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB', + 'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED', + 'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', + 'IOAGR_HWID', 'IOAPIC_HWID', 'IOHC_HWID', 'IP_DISCOVERY', + 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', + 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', + 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'ISP_HWID', 'ISP_HWIP', + 'JITTER_REMOVE_DISABLE', 'JPEG_HWIP', 'L1IMU10_HWID', + 'L1IMU11_HWID', 'L1IMU12_HWID', 'L1IMU13_HWID', 'L1IMU14_HWID', + 'L1IMU15_HWID', 'L1IMU3_HWID', 'L1IMU4_HWID', 'L1IMU5_HWID', + 'L1IMU6_HWID', 'L1IMU7_HWID', 'L1IMU8_HWID', 'L1IMU9_HWID', + 'L1IMU_IOAGR_HWID', 'L1IMU_NBIF_HWID', 'L1IMU_PCIE_HWID', + 'L2IMU_HWID', 'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', + 'LB_ALPHA_ENABLE', 'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN', + 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', 'LB_MEMORY_CONFIG_0', + 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', 'LB_MEMORY_CONFIG_3', + 'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B', + 'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LOOSE_PACK', + 'LSDMA_HWID', 'LSDMA_HWIP', 'LSDMA_PERF_SEL', + 'LSDMA_PERF_SEL_ATCL2_FREE', 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY', + 'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START', + 'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE', + 'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL', + 'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE', + 'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END', + 'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START', + 'LSDMA_PERF_SEL_CTX_CHANGE', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE', + 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC', + 'LSDMA_PERF_SEL_EX_IDLE', + 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL', + 'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE', + 'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 'LSDMA_PERF_SEL_INT_REQ_STALL', + 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE', + 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT', + 'LSDMA_PERF_SEL_MC_WR_IDLE', + 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET', + 'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL', + 'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY', + 'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB', + 'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR', + 'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT', + 'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE', + 'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR', + 'LS_STAGE_OFF', 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', + 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', + 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', + 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', + 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', + 'LUT_4_MODE_RAMB_LUT', 'LUT_4_MODE_ROMA_LUT', + 'LUT_4_MODE_ROMB_LUT', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', + 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'MALL_INFO', + 'MALL_INFO_TABLE_ID', 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', + 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', + 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', + 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 'MASTER_UPDATE_LOCK_SEL_RESERVED5', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 'MAX_HWIP', 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', + 'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT', + 'MEM_POWER_DIS_MODE_DISABLE', 'MEM_POWER_DIS_MODE_ENABLE', + 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF', + 'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP', + 'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON', + 'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL', + 'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', + 'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', + 'MEM_PWR_STATUS', 'MEM_TRAIN_SYSTEM_SIGNATURE', + 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', 'METADATA_HUBP_SEL_1', + 'METADATA_HUBP_SEL_2', 'METADATA_HUBP_SEL_3', + 'METADATA_HUBP_SEL_RESERVED', 'METADATA_STREAM_DP', + 'METADATA_STREAM_DVE', 'METADATA_STREAM_TYPE_SEL', + 'META_CHUNK_SIZE', 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', + 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', + 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', + 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', + 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', + 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', + 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', + 'MIN_META_CHUNK_SIZE_64B', 'MMHUB_HWID', 'MMHUB_HWIP', + 'MONO_10LSB', 'MONO_10MSB', 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', + 'MONO_2BIT', 'MONO_8', 'MP0_HWID', 'MP0_HWIP', 'MP1_HWID', + 'MP1_HWIP', 'MP2_HWID', 'MPCC_BG_COLOR_BPC', + 'MPCC_BG_COLOR_BPC_10bit', 'MPCC_BG_COLOR_BPC_11bit', + 'MPCC_BG_COLOR_BPC_12bit', 'MPCC_BG_COLOR_BPC_8bit', + 'MPCC_BG_COLOR_BPC_9bit', 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', + 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0', + 'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2', + 'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV', + 'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT', + 'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT', + 'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL', + 'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS', + 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 'MPCC_MCM_GAMMA_LUT_MODE_ENUM', + 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA', + 'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3', + 'MPCC_MCM_GAMMA_LUT_SEL_ENUM', 'MPCC_MCM_LUT_2_MODE_BYPASS', + 'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R', + 'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE', + 'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG', + 'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT', + 'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS', + 'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL', + 'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG', + 'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1', + 'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16', + 'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32', + 'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64', + 'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM', + 'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD', + 'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM', + 'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON', + 'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS', + 'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS', + 'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R', + 'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB', + 'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL', + 'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL', + 'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE', + 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', + 'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL', + 'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM', + 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2', + 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV', + 'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA', + 'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB', + 'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT', + 'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128', + 'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2', + 'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4', + 'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', + 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', + 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', + 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', + 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', + 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', + 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', + 'MPC_DEBUG_BUS1_DATA_SELECT', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', + 'MPC_DEBUG_BUS2_DATA_SELECT', 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', + 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', + 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', + 'MPC_DEBUG_BUS2_DATA_SELECT_RES', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', + 'MPC_DEBUG_BUS_MPCC_BYTE0', 'MPC_DEBUG_BUS_MPCC_BYTE1', + 'MPC_DEBUG_BUS_MPCC_BYTE2', 'MPC_DEBUG_BUS_MPCC_BYTE3', + 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT', 'MPC_OCSC_COEF_FORMAT', + 'MPC_OCSC_COEF_FORMAT_S2_13', 'MPC_OCSC_COEF_FORMAT_S3_12', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', + 'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', + 'MPC_OUT_RATE_CONTROL_DISABLE_SET', + 'MPC_OUT_RATE_CONTROL_SET_DISABLE', + 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', + 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', + 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', + 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', + 'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED', + 'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8', + 'MemArbMode', 'NBIF_HWID', 'NBIF_HWIP', 'NBIO_HWIP', 'NODEID_MAX', + 'NON_BYPASS', 'NOT_FORCE_THE_CLOCK_DISABLED', 'NOT_SENT', + 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ', + 'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', + 'NO_OUTSTANDING_REQ', 'NPS_INFO', 'NPS_INFO_TABLE_ID', + 'NPS_INFO_TABLE_MAX_NUM_INSTANCES', 'NTBCCP_HWID', 'NTB_HWID', + 'NUM_SIMD_PER_CU', 'OBUF_BYPASS_DIS', 'OBUF_BYPASS_EN', + 'OBUF_BYPASS_SEL', 'OBUF_FULL', 'OBUF_FULL_RECOUT', + 'OBUF_HALF_RECOUT', 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', + 'OBUF_RECOUT', 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', + 'OFF_SEQ', 'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B', + 'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ', + 'OPPBUF_DISPLAY_SEGMENTATION', + 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', + 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL', + 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL', + 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL', + 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL', + 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL', 'OPP_PIPE_CLOCK_DISABLE', + 'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL', + 'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', + 'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 'OPP_PIPE_CRC_INTERLACE_MODE', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', + 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', + 'OPP_PIPE_CRC_PIXEL_SELECT', + 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', + 'OPP_PIPE_CRC_STEREO_MODE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', + 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R', + 'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1', + 'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3', + 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', + 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', + 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', + 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', + 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', + 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', 'OSSSYS_HWID', + 'OSSSYS_HWIP', 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', + 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', + 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX', + 'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1', + 'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL', + 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', + 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN', + 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1', + 'OTG_DIG_UPDATE_VCOUNT_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', + 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', + 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN', + 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE', + 'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1', + 'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3', + 'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0', + 'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10', + 'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12', + 'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14', + 'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2', + 'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4', + 'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6', + 'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8', + 'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL', + 'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW', + 'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO', + 'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4', + 'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO', + 'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', + 'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', + 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', + 'OTG_TRIGA_FREQUENCY_SELECT_3', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', + 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', + 'OTG_TRIGB_FREQUENCY_SELECT_3', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', + 'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL', + 'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW', + 'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK', + 'OTG_V_SYNC_MODE_HSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', + 'OUTPUT_LINE', 'OUTPUT_POINT', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', + 'OVERRUN', 'OreoMode', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', + 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PCIE_HWID', 'PCIE_HWIP', + 'PCS_HWID', 'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE', + 'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW', + 'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START', + 'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE', + 'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET', + 'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE', + 'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW', + 'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START', + 'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE', + 'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET', + 'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE', + 'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW', + 'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START', + 'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE', + 'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET', + 'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE', + 'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW', + 'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START', + 'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE', + 'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET', + 'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL', + 'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1', + 'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3', + 'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5', + 'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7', + 'PERFCOUNTER_CNTOFF_START_DIS', + 'PERFCOUNTER_CNTOFF_START_DISABLE', + 'PERFCOUNTER_CNTOFF_START_ENABLE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', + 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', + 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', + 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', + 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', + 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', + 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', + 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', + 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', + 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', + 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', + 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', + 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', + 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', + 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', + 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', + 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', + 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', + 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', + 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', + 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', + 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', + 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', + 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', + 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', + 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', + 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', + 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', + 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', + 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', + 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', + 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', + 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', + 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', + 'PERFMON_COUNTER_MODE_ACCUM', + 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 'PERFMON_COUNTER_MODE_DIRTY', + 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', + 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', + 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', + 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', + 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', + 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', + 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', + 'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT', + 'PERF_ENGG_BUSY', 'PERF_ENGG_CSB_DELAY_BIN00', + 'PERF_ENGG_CSB_DELAY_BIN01', 'PERF_ENGG_CSB_DELAY_BIN02', + 'PERF_ENGG_CSB_DELAY_BIN03', 'PERF_ENGG_CSB_DELAY_BIN04', + 'PERF_ENGG_CSB_DELAY_BIN05', 'PERF_ENGG_CSB_DELAY_BIN06', + 'PERF_ENGG_CSB_DELAY_BIN07', 'PERF_ENGG_CSB_DELAY_BIN08', + 'PERF_ENGG_CSB_DELAY_BIN09', 'PERF_ENGG_CSB_DELAY_BIN10', + 'PERF_ENGG_CSB_DELAY_BIN11', 'PERF_ENGG_CSB_DELAY_BIN12', + 'PERF_ENGG_CSB_DELAY_BIN13', 'PERF_ENGG_CSB_DELAY_BIN14', + 'PERF_ENGG_CSB_DELAY_BIN15', 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 'PERF_ENGG_CSB_NULL_SUBGROUP', + 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_DELAY_BIN00', + 'PERF_ENGG_CSB_SPI_DELAY_BIN01', 'PERF_ENGG_CSB_SPI_DELAY_BIN02', + 'PERF_ENGG_CSB_SPI_DELAY_BIN03', 'PERF_ENGG_CSB_SPI_DELAY_BIN04', + 'PERF_ENGG_CSB_SPI_DELAY_BIN05', 'PERF_ENGG_CSB_SPI_DELAY_BIN06', + 'PERF_ENGG_CSB_SPI_DELAY_BIN07', 'PERF_ENGG_CSB_SPI_DELAY_BIN08', + 'PERF_ENGG_CSB_SPI_DELAY_BIN09', 'PERF_ENGG_CSB_SPI_DELAY_BIN10', + 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 'PERF_ENGG_INDEX_REQ_STARVED', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC', + 'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC', + 'PERF_OUTPUT_PRIM_4_SC', 'PERF_PAPC_CCGSM_BUSY', + 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', + 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', + 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', + 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', + 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', + 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', + 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', + 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', + 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', + 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', + 'PERF_PAPC_PASX_REC_STALLED', + 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', + 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', + 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', + 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', + 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', + 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', + 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', + 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', + 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', + 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE01_STALLED_SC', + 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE0_STALLED_SC', + 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE1_STALLED_SC', + 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE2_STALLED_SC', + 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', + 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', 'PERF_PA_PIPE0_SWITCHED_GEN', + 'PERF_PA_PIPE1_SWITCHED_GEN', + 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL', + 'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC', + 'PERF_PH_SEND_4_SC', 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END', + 'PERSISTENT_SPACE_START', 'PHYSYMCLK_FORCE_EN', + 'PHYSYMCLK_FORCE_EN_DISABLE', 'PHYSYMCLK_FORCE_EN_ENABLE', + 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', + 'PHYSYMCLK_FORCE_SRC_SEL', 'PHYSYMCLK_FORCE_SRC_SYMCLK', + 'PHY_CUSTOM_RATE', 'PHY_DP_RATE_10P', 'PHY_DP_RATE_13P5', + 'PHY_DP_RATE_1P62', 'PHY_DP_RATE_20P', 'PHY_DP_RATE_2P16', + 'PHY_DP_RATE_2P43', 'PHY_DP_RATE_2P7', 'PHY_DP_RATE_3P24', + 'PHY_DP_RATE_4P32', 'PHY_DP_RATE_5P4', 'PHY_DP_RATE_8P1', + 'PHY_IF_WIDTH_10BIT', 'PHY_IF_WIDTH_20BIT', 'PHY_IF_WIDTH_40BIT', + 'PHY_IF_WIDTH_80BIT', 'PH_PERFCNT_SEL', + 'PH_PERF_SC0_FIFO_STATUS_0', 'PH_PERF_SC0_FIFO_STATUS_1', + 'PH_PERF_SC0_FIFO_STATUS_2', 'PH_PERF_SC0_FIFO_STATUS_3', + 'PH_PERF_SC1_FIFO_STATUS_0', 'PH_PERF_SC1_FIFO_STATUS_1', + 'PH_PERF_SC1_FIFO_STATUS_2', 'PH_PERF_SC1_FIFO_STATUS_3', + 'PH_PERF_SC2_FIFO_STATUS_0', 'PH_PERF_SC2_FIFO_STATUS_1', + 'PH_PERF_SC2_FIFO_STATUS_2', 'PH_PERF_SC2_FIFO_STATUS_3', + 'PH_PERF_SC3_FIFO_STATUS_0', 'PH_PERF_SC3_FIFO_STATUS_1', + 'PH_PERF_SC3_FIFO_STATUS_2', 'PH_PERF_SC3_FIFO_STATUS_3', + 'PH_PERF_SC4_FIFO_STATUS_0', 'PH_PERF_SC4_FIFO_STATUS_1', + 'PH_PERF_SC4_FIFO_STATUS_2', 'PH_PERF_SC4_FIFO_STATUS_3', + 'PH_PERF_SC5_FIFO_STATUS_0', 'PH_PERF_SC5_FIFO_STATUS_1', + 'PH_PERF_SC5_FIFO_STATUS_2', 'PH_PERF_SC5_FIFO_STATUS_3', + 'PH_PERF_SC6_FIFO_STATUS_0', 'PH_PERF_SC6_FIFO_STATUS_1', + 'PH_PERF_SC6_FIFO_STATUS_2', 'PH_PERF_SC6_FIFO_STATUS_3', + 'PH_PERF_SC7_FIFO_STATUS_0', 'PH_PERF_SC7_FIFO_STATUS_1', + 'PH_PERF_SC7_FIFO_STATUS_2', 'PH_PERF_SC7_FIFO_STATUS_3', + 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_BUSY', + 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA0_EOPG_WE', 'PH_PERF_SEL_SC0_PA0_EOP_WE', + 'PH_PERF_SEL_SC0_PA0_EVENT_WE', 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 'PH_PERF_SEL_SC0_PA0_LPOV_WE', 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA1_EOPG_WE', 'PH_PERF_SEL_SC0_PA1_EOP_WE', + 'PH_PERF_SEL_SC0_PA1_EVENT_WE', 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 'PH_PERF_SEL_SC0_PA1_LPOV_WE', 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA2_EOPG_WE', 'PH_PERF_SEL_SC0_PA2_EOP_WE', + 'PH_PERF_SEL_SC0_PA2_EVENT_WE', 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 'PH_PERF_SEL_SC0_PA2_LPOV_WE', 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA3_EOPG_WE', 'PH_PERF_SEL_SC0_PA3_EOP_WE', + 'PH_PERF_SEL_SC0_PA3_EVENT_WE', 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 'PH_PERF_SEL_SC0_PA3_LPOV_WE', 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA4_EOPG_WE', 'PH_PERF_SEL_SC0_PA4_EOP_WE', + 'PH_PERF_SEL_SC0_PA4_EVENT_WE', 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 'PH_PERF_SEL_SC0_PA4_LPOV_WE', 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA5_EOPG_WE', 'PH_PERF_SEL_SC0_PA5_EOP_WE', + 'PH_PERF_SEL_SC0_PA5_EVENT_WE', 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 'PH_PERF_SEL_SC0_PA5_LPOV_WE', 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA6_EOPG_WE', 'PH_PERF_SEL_SC0_PA6_EOP_WE', + 'PH_PERF_SEL_SC0_PA6_EVENT_WE', 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 'PH_PERF_SEL_SC0_PA6_LPOV_WE', 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA7_EOPG_WE', 'PH_PERF_SEL_SC0_PA7_EOP_WE', + 'PH_PERF_SEL_SC0_PA7_EVENT_WE', 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 'PH_PERF_SEL_SC0_PA7_LPOV_WE', 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC1_ARB_BUSY', + 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA0_EOPG_WE', 'PH_PERF_SEL_SC1_PA0_EOP_WE', + 'PH_PERF_SEL_SC1_PA0_EVENT_WE', 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 'PH_PERF_SEL_SC1_PA0_LPOV_WE', 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA1_EOPG_WE', 'PH_PERF_SEL_SC1_PA1_EOP_WE', + 'PH_PERF_SEL_SC1_PA1_EVENT_WE', 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 'PH_PERF_SEL_SC1_PA1_LPOV_WE', 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA2_EOPG_WE', 'PH_PERF_SEL_SC1_PA2_EOP_WE', + 'PH_PERF_SEL_SC1_PA2_EVENT_WE', 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 'PH_PERF_SEL_SC1_PA2_LPOV_WE', 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA3_EOPG_WE', 'PH_PERF_SEL_SC1_PA3_EOP_WE', + 'PH_PERF_SEL_SC1_PA3_EVENT_WE', 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 'PH_PERF_SEL_SC1_PA3_LPOV_WE', 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA4_EOPG_WE', 'PH_PERF_SEL_SC1_PA4_EOP_WE', + 'PH_PERF_SEL_SC1_PA4_EVENT_WE', 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 'PH_PERF_SEL_SC1_PA4_LPOV_WE', 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA5_EOPG_WE', 'PH_PERF_SEL_SC1_PA5_EOP_WE', + 'PH_PERF_SEL_SC1_PA5_EVENT_WE', 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 'PH_PERF_SEL_SC1_PA5_LPOV_WE', 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA6_EOPG_WE', 'PH_PERF_SEL_SC1_PA6_EOP_WE', + 'PH_PERF_SEL_SC1_PA6_EVENT_WE', 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 'PH_PERF_SEL_SC1_PA6_LPOV_WE', 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA7_EOPG_WE', 'PH_PERF_SEL_SC1_PA7_EOP_WE', + 'PH_PERF_SEL_SC1_PA7_EVENT_WE', 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 'PH_PERF_SEL_SC1_PA7_LPOV_WE', 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC2_ARB_BUSY', + 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA0_EOPG_WE', 'PH_PERF_SEL_SC2_PA0_EOP_WE', + 'PH_PERF_SEL_SC2_PA0_EVENT_WE', 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 'PH_PERF_SEL_SC2_PA0_LPOV_WE', 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA1_EOPG_WE', 'PH_PERF_SEL_SC2_PA1_EOP_WE', + 'PH_PERF_SEL_SC2_PA1_EVENT_WE', 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 'PH_PERF_SEL_SC2_PA1_LPOV_WE', 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA2_EOPG_WE', 'PH_PERF_SEL_SC2_PA2_EOP_WE', + 'PH_PERF_SEL_SC2_PA2_EVENT_WE', 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 'PH_PERF_SEL_SC2_PA2_LPOV_WE', 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA3_EOPG_WE', 'PH_PERF_SEL_SC2_PA3_EOP_WE', + 'PH_PERF_SEL_SC2_PA3_EVENT_WE', 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 'PH_PERF_SEL_SC2_PA3_LPOV_WE', 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA4_EOPG_WE', 'PH_PERF_SEL_SC2_PA4_EOP_WE', + 'PH_PERF_SEL_SC2_PA4_EVENT_WE', 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 'PH_PERF_SEL_SC2_PA4_LPOV_WE', 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA5_EOPG_WE', 'PH_PERF_SEL_SC2_PA5_EOP_WE', + 'PH_PERF_SEL_SC2_PA5_EVENT_WE', 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 'PH_PERF_SEL_SC2_PA5_LPOV_WE', 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA6_EOPG_WE', 'PH_PERF_SEL_SC2_PA6_EOP_WE', + 'PH_PERF_SEL_SC2_PA6_EVENT_WE', 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 'PH_PERF_SEL_SC2_PA6_LPOV_WE', 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA7_EOPG_WE', 'PH_PERF_SEL_SC2_PA7_EOP_WE', + 'PH_PERF_SEL_SC2_PA7_EVENT_WE', 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 'PH_PERF_SEL_SC2_PA7_LPOV_WE', 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC3_ARB_BUSY', + 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA0_EOPG_WE', 'PH_PERF_SEL_SC3_PA0_EOP_WE', + 'PH_PERF_SEL_SC3_PA0_EVENT_WE', 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 'PH_PERF_SEL_SC3_PA0_LPOV_WE', 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA1_EOPG_WE', 'PH_PERF_SEL_SC3_PA1_EOP_WE', + 'PH_PERF_SEL_SC3_PA1_EVENT_WE', 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 'PH_PERF_SEL_SC3_PA1_LPOV_WE', 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA2_EOPG_WE', 'PH_PERF_SEL_SC3_PA2_EOP_WE', + 'PH_PERF_SEL_SC3_PA2_EVENT_WE', 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 'PH_PERF_SEL_SC3_PA2_LPOV_WE', 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA3_EOPG_WE', 'PH_PERF_SEL_SC3_PA3_EOP_WE', + 'PH_PERF_SEL_SC3_PA3_EVENT_WE', 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 'PH_PERF_SEL_SC3_PA3_LPOV_WE', 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA4_EOPG_WE', 'PH_PERF_SEL_SC3_PA4_EOP_WE', + 'PH_PERF_SEL_SC3_PA4_EVENT_WE', 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 'PH_PERF_SEL_SC3_PA4_LPOV_WE', 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA5_EOPG_WE', 'PH_PERF_SEL_SC3_PA5_EOP_WE', + 'PH_PERF_SEL_SC3_PA5_EVENT_WE', 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 'PH_PERF_SEL_SC3_PA5_LPOV_WE', 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA6_EOPG_WE', 'PH_PERF_SEL_SC3_PA6_EOP_WE', + 'PH_PERF_SEL_SC3_PA6_EVENT_WE', 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 'PH_PERF_SEL_SC3_PA6_LPOV_WE', 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA7_EOPG_WE', 'PH_PERF_SEL_SC3_PA7_EOP_WE', + 'PH_PERF_SEL_SC3_PA7_EVENT_WE', 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 'PH_PERF_SEL_SC3_PA7_LPOV_WE', 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC4_ARB_BUSY', + 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA0_EOPG_WE', 'PH_PERF_SEL_SC4_PA0_EOP_WE', + 'PH_PERF_SEL_SC4_PA0_EVENT_WE', 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 'PH_PERF_SEL_SC4_PA0_LPOV_WE', 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA1_EOPG_WE', 'PH_PERF_SEL_SC4_PA1_EOP_WE', + 'PH_PERF_SEL_SC4_PA1_EVENT_WE', 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 'PH_PERF_SEL_SC4_PA1_LPOV_WE', 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA2_EOPG_WE', 'PH_PERF_SEL_SC4_PA2_EOP_WE', + 'PH_PERF_SEL_SC4_PA2_EVENT_WE', 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 'PH_PERF_SEL_SC4_PA2_LPOV_WE', 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA3_EOPG_WE', 'PH_PERF_SEL_SC4_PA3_EOP_WE', + 'PH_PERF_SEL_SC4_PA3_EVENT_WE', 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 'PH_PERF_SEL_SC4_PA3_LPOV_WE', 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA4_EOPG_WE', 'PH_PERF_SEL_SC4_PA4_EOP_WE', + 'PH_PERF_SEL_SC4_PA4_EVENT_WE', 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 'PH_PERF_SEL_SC4_PA4_LPOV_WE', 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA5_EOPG_WE', 'PH_PERF_SEL_SC4_PA5_EOP_WE', + 'PH_PERF_SEL_SC4_PA5_EVENT_WE', 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 'PH_PERF_SEL_SC4_PA5_LPOV_WE', 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA6_EOPG_WE', 'PH_PERF_SEL_SC4_PA6_EOP_WE', + 'PH_PERF_SEL_SC4_PA6_EVENT_WE', 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 'PH_PERF_SEL_SC4_PA6_LPOV_WE', 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA7_EOPG_WE', 'PH_PERF_SEL_SC4_PA7_EOP_WE', + 'PH_PERF_SEL_SC4_PA7_EVENT_WE', 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 'PH_PERF_SEL_SC4_PA7_LPOV_WE', 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC5_ARB_BUSY', + 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA0_EOPG_WE', 'PH_PERF_SEL_SC5_PA0_EOP_WE', + 'PH_PERF_SEL_SC5_PA0_EVENT_WE', 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 'PH_PERF_SEL_SC5_PA0_LPOV_WE', 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA1_EOPG_WE', 'PH_PERF_SEL_SC5_PA1_EOP_WE', + 'PH_PERF_SEL_SC5_PA1_EVENT_WE', 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 'PH_PERF_SEL_SC5_PA1_LPOV_WE', 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA2_EOPG_WE', 'PH_PERF_SEL_SC5_PA2_EOP_WE', + 'PH_PERF_SEL_SC5_PA2_EVENT_WE', 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 'PH_PERF_SEL_SC5_PA2_LPOV_WE', 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA3_EOPG_WE', 'PH_PERF_SEL_SC5_PA3_EOP_WE', + 'PH_PERF_SEL_SC5_PA3_EVENT_WE', 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 'PH_PERF_SEL_SC5_PA3_LPOV_WE', 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA4_EOPG_WE', 'PH_PERF_SEL_SC5_PA4_EOP_WE', + 'PH_PERF_SEL_SC5_PA4_EVENT_WE', 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 'PH_PERF_SEL_SC5_PA4_LPOV_WE', 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA5_EOPG_WE', 'PH_PERF_SEL_SC5_PA5_EOP_WE', + 'PH_PERF_SEL_SC5_PA5_EVENT_WE', 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 'PH_PERF_SEL_SC5_PA5_LPOV_WE', 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA6_EOPG_WE', 'PH_PERF_SEL_SC5_PA6_EOP_WE', + 'PH_PERF_SEL_SC5_PA6_EVENT_WE', 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 'PH_PERF_SEL_SC5_PA6_LPOV_WE', 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA7_EOPG_WE', 'PH_PERF_SEL_SC5_PA7_EOP_WE', + 'PH_PERF_SEL_SC5_PA7_EVENT_WE', 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 'PH_PERF_SEL_SC5_PA7_LPOV_WE', 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC6_ARB_BUSY', + 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA0_EOPG_WE', 'PH_PERF_SEL_SC6_PA0_EOP_WE', + 'PH_PERF_SEL_SC6_PA0_EVENT_WE', 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 'PH_PERF_SEL_SC6_PA0_LPOV_WE', 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA1_EOPG_WE', 'PH_PERF_SEL_SC6_PA1_EOP_WE', + 'PH_PERF_SEL_SC6_PA1_EVENT_WE', 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 'PH_PERF_SEL_SC6_PA1_LPOV_WE', 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA2_EOPG_WE', 'PH_PERF_SEL_SC6_PA2_EOP_WE', + 'PH_PERF_SEL_SC6_PA2_EVENT_WE', 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 'PH_PERF_SEL_SC6_PA2_LPOV_WE', 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA3_EOPG_WE', 'PH_PERF_SEL_SC6_PA3_EOP_WE', + 'PH_PERF_SEL_SC6_PA3_EVENT_WE', 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 'PH_PERF_SEL_SC6_PA3_LPOV_WE', 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA4_EOPG_WE', 'PH_PERF_SEL_SC6_PA4_EOP_WE', + 'PH_PERF_SEL_SC6_PA4_EVENT_WE', 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 'PH_PERF_SEL_SC6_PA4_LPOV_WE', 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA5_EOPG_WE', 'PH_PERF_SEL_SC6_PA5_EOP_WE', + 'PH_PERF_SEL_SC6_PA5_EVENT_WE', 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 'PH_PERF_SEL_SC6_PA5_LPOV_WE', 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA6_EOPG_WE', 'PH_PERF_SEL_SC6_PA6_EOP_WE', + 'PH_PERF_SEL_SC6_PA6_EVENT_WE', 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 'PH_PERF_SEL_SC6_PA6_LPOV_WE', 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA7_EOPG_WE', 'PH_PERF_SEL_SC6_PA7_EOP_WE', + 'PH_PERF_SEL_SC6_PA7_EVENT_WE', 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 'PH_PERF_SEL_SC6_PA7_LPOV_WE', 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC7_ARB_BUSY', + 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA0_EOPG_WE', 'PH_PERF_SEL_SC7_PA0_EOP_WE', + 'PH_PERF_SEL_SC7_PA0_EVENT_WE', 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 'PH_PERF_SEL_SC7_PA0_LPOV_WE', 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA1_EOPG_WE', 'PH_PERF_SEL_SC7_PA1_EOP_WE', + 'PH_PERF_SEL_SC7_PA1_EVENT_WE', 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 'PH_PERF_SEL_SC7_PA1_LPOV_WE', 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA2_EOPG_WE', 'PH_PERF_SEL_SC7_PA2_EOP_WE', + 'PH_PERF_SEL_SC7_PA2_EVENT_WE', 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 'PH_PERF_SEL_SC7_PA2_LPOV_WE', 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA3_EOPG_WE', 'PH_PERF_SEL_SC7_PA3_EOP_WE', + 'PH_PERF_SEL_SC7_PA3_EVENT_WE', 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 'PH_PERF_SEL_SC7_PA3_LPOV_WE', 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA4_EOPG_WE', 'PH_PERF_SEL_SC7_PA4_EOP_WE', + 'PH_PERF_SEL_SC7_PA4_EVENT_WE', 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 'PH_PERF_SEL_SC7_PA4_LPOV_WE', 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA5_EOPG_WE', 'PH_PERF_SEL_SC7_PA5_EOP_WE', + 'PH_PERF_SEL_SC7_PA5_EVENT_WE', 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 'PH_PERF_SEL_SC7_PA5_LPOV_WE', 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA6_EOPG_WE', 'PH_PERF_SEL_SC7_PA6_EOP_WE', + 'PH_PERF_SEL_SC7_PA6_EVENT_WE', 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 'PH_PERF_SEL_SC7_PA6_LPOV_WE', 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA7_EOPG_WE', 'PH_PERF_SEL_SC7_PA7_EOP_WE', + 'PH_PERF_SEL_SC7_PA7_EVENT_WE', 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 'PH_PERF_SEL_SC7_PA7_LPOV_WE', 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', + 'PIPE_ALIGNED_SURF', 'PIPE_COMPAT_LEVEL', 'PIPE_ID0', 'PIPE_ID1', + 'PIPE_ID2', 'PIPE_ID3', 'PIPE_INT_MASK_MODE', + 'PIPE_INT_MASK_MODE_DISABLE', 'PIPE_INT_MASK_MODE_ENABLE', + 'PIPE_INT_TYPE_MODE', 'PIPE_INT_TYPE_MODE_DISABLE', + 'PIPE_INT_TYPE_MODE_ENABLE', 'PIPE_IN_FLUSH_URGENT', + 'PIPE_IN_FLUSH_URGENT_DISABLE', 'PIPE_IN_FLUSH_URGENT_ENABLE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 'PIPE_PIXEL_RATE_PLL_SOURCE', + 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', + 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', + 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', + 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', + 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', + 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', + 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', + 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', + 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', + 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', + 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS', + 'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', + 'PRE_CSC_MODE_ENUM', 'PRE_CSC_SET_A', 'PRE_CSC_SET_B', + 'PRE_DEGAM_BT2020', 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', + 'PRE_DEGAM_BYPASS', 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', + 'PRE_DEGAM_GAMMA_24', 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', + 'PRE_DEGAM_SELECT', 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', + 'PRQ_MRQ_FLUSH_URGENT', 'PRQ_MRQ_FLUSH_URGENT_DISABLE', + 'PRQ_MRQ_FLUSH_URGENT_ENABLE', 'PS', 'PSLC_ASAP', 'PSLC_AUTO', + 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PSP_1_MEG', + 'PSP_ASD_SHARED_MEM_SIZE', 'PSP_BL__DRAM_LONG_TRAIN', + 'PSP_BL__DRAM_SHORT_TRAIN', 'PSP_BL__LOAD_DBGDRV', + 'PSP_BL__LOAD_HADDRV', 'PSP_BL__LOAD_INTFDRV', + 'PSP_BL__LOAD_IPKEYMGRDRV', 'PSP_BL__LOAD_KEY_DATABASE', + 'PSP_BL__LOAD_RASDRV', 'PSP_BL__LOAD_SOCDRV', + 'PSP_BL__LOAD_SOSDRV', 'PSP_BL__LOAD_SYSDRV', + 'PSP_BL__LOAD_TOS_SPL_TABLE', 'PSP_CMD_BUFFER_SIZE', + 'PSP_DTM_SHARED_MEM_SIZE', 'PSP_ERR_UNKNOWN_COMMAND', + 'PSP_FENCE_BUFFER_SIZE', 'PSP_FW_NAME_LEN', + 'PSP_FW_TYPE_MAX_INDEX', 'PSP_FW_TYPE_PSP_DBG_DRV', + 'PSP_FW_TYPE_PSP_INTF_DRV', 'PSP_FW_TYPE_PSP_IPKEYMGR_DRV', + 'PSP_FW_TYPE_PSP_KDB', 'PSP_FW_TYPE_PSP_RAS_DRV', + 'PSP_FW_TYPE_PSP_RL', 'PSP_FW_TYPE_PSP_SOC_DRV', + 'PSP_FW_TYPE_PSP_SOS', 'PSP_FW_TYPE_PSP_SPL', + 'PSP_FW_TYPE_PSP_SYS_DRV', 'PSP_FW_TYPE_PSP_TOC', + 'PSP_FW_TYPE_UNKOWN', 'PSP_GFX_CMD_BUF_VERSION', + 'PSP_HDCP_SHARED_MEM_SIZE', 'PSP_HEADER_SIZE', + 'PSP_MEM_TRAIN_COLD_BOOT', 'PSP_MEM_TRAIN_INIT_FAILED', + 'PSP_MEM_TRAIN_INIT_SUCCESS', 'PSP_MEM_TRAIN_NOT_SUPPORT', + 'PSP_MEM_TRAIN_RESERVE_SUCCESS', 'PSP_MEM_TRAIN_RESTORE', + 'PSP_MEM_TRAIN_RESUME', 'PSP_MEM_TRAIN_SAVE', + 'PSP_MEM_TRAIN_SEND_LONG_MSG', 'PSP_MEM_TRAIN_SEND_SHORT_MSG', + 'PSP_MEM_TRAIN_SUPPORT', 'PSP_RAP_SHARED_MEM_SIZE', + 'PSP_RAS_SHARED_MEM_SIZE', 'PSP_REG_IH_RB_CNTL', + 'PSP_REG_IH_RB_CNTL_RING1', 'PSP_REG_IH_RB_CNTL_RING2', + 'PSP_REG_LAST', 'PSP_RING_TYPE__INVALID', 'PSP_RING_TYPE__KM', + 'PSP_RING_TYPE__UM', 'PSP_RUNTIME_DB_COOKIE_ID', + 'PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT', 'PSP_RUNTIME_DB_OFFSET', + 'PSP_RUNTIME_DB_SIZE_IN_BYTES', 'PSP_RUNTIME_DB_VER_1', + 'PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG', + 'PSP_RUNTIME_ENTRY_TYPE_INVALID', + 'PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON', + 'PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL', + 'PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI', + 'PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS', + 'PSP_RUNTIME_ENTRY_TYPE_TEST', + 'PSP_SECUREDISPLAY_SHARED_MEM_SIZE', 'PSP_TMR_ALIGNMENT', + 'PSP_XGMI_SHARED_MEM_SIZE', 'PS_DONE', 'PS_PARTIAL_FLUSH', + 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', 'PTE_BUFFER_MODE_1', + 'PTE_ROW_HEIGHT_LINEAR', 'PTE_ROW_HEIGHT_LINEAR_1024L', + 'PTE_ROW_HEIGHT_LINEAR_128L', 'PTE_ROW_HEIGHT_LINEAR_16L', + 'PTE_ROW_HEIGHT_LINEAR_256L', 'PTE_ROW_HEIGHT_LINEAR_32L', + 'PTE_ROW_HEIGHT_LINEAR_512L', 'PTE_ROW_HEIGHT_LINEAR_64L', + 'PTE_ROW_HEIGHT_LINEAR_8L', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN', + 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', + 'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF', + 'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT', + 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF', + 'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT', + 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE', + 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', + 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', + 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PWR_HWID', + 'PWR_HWIP', 'PerfCounter_Vals', 'PhSPIstatusMode', + 'PixelPipeCounterId', 'PixelPipeStride', 'PkrMap', 'PkrXsel', + 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS', 'RAMB', + 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF', + 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', + 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', + 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', + 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', + 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', + 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', + 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', + 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', + 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', + 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', + 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', + 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', + 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', + 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', + 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', + 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', + 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', + 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', + 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', + 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', + 'RASTER_CONFIG_SE_PAIR_MAP_3', + 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', + 'RDPCSPIPE_APBCLK_DISABLE', 'RDPCSPIPE_APBCLK_ENABLE', + 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', + 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', + 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET', + 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', + 'RDPCSPIPE_DBG_OCLA_SEL', 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', + 'RDPCSPIPE_ENC_TYPE', 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', + 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', 'RDPCSPIPE_FIFO_EMPTY', + 'RDPCSPIPE_FIFO_FULL', 'RDPCSPIPE_FIFO_IS_EMPTY', + 'RDPCSPIPE_FIFO_IS_FULL', 'RDPCSPIPE_FIFO_NOT_EMPTY', + 'RDPCSPIPE_FIFO_NOT_FULL', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', + 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', + 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', + 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', + 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', + 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', + 'RDPCSPIPE_MEM_PWR_NO_FORCE', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', + 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', + 'RDPCSPIPE_PACK_MODE', 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', + 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', + 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', + 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', + 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', + 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', + 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', + 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', + 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', + 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 'RDPCSPIPE_PHY_DP_TX_RATE', 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', + 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', + 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', + 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', + 'RDPCSPIPE_PHY_IF_WIDTH', 'RDPCSPIPE_PHY_RATE', + 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', + 'RDPCSPIPE_PHY_REF_ALT_CLK_EN', + 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', 'RDPCSPIPE_PHY_REF_RANGE_0', + 'RDPCSPIPE_PHY_REF_RANGE_1', 'RDPCSPIPE_PHY_REF_RANGE_2', + 'RDPCSPIPE_PHY_REF_RANGE_3', 'RDPCSPIPE_PHY_REF_RANGE_4', + 'RDPCSPIPE_PHY_REF_RANGE_5', 'RDPCSPIPE_PHY_REF_RANGE_6', + 'RDPCSPIPE_PHY_REF_RANGE_7', + 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', + 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', + 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', + 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', + 'RDPCSPIPE_SRAMCLK_DISABLE', 'RDPCSPIPE_SRAMCLK_ENABLE', + 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', + 'RDPCSPIPE_SRAMCLK_NOT_PASS', 'RDPCSPIPE_SRAMCLK_PASS', + 'RDPCSPIPE_SRAM_EXT_LD_DONE', 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', + 'RDPCSPIPE_SRAM_INIT_DONE', 'RDPCSPIPE_SRAM_INIT_NOT_DONE', + 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', + 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', + 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', + 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCSPIPE_TEST_CLK_SEL', + 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_NONE', + 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', + 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', + 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', 'RDPCS_PIPE_CLK_CLOCK_OFF', + 'RDPCS_PIPE_CLK_CLOCK_ON', 'RDPCS_PIPE_CLK_DISABLE', + 'RDPCS_PIPE_CLK_ENABLE', 'RDPCS_PIPE_CLK_GATE_DISABLE', + 'RDPCS_PIPE_CLK_GATE_ENABLE', + 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB', + 'RDPCS_PIPE_FIFO_DISABLE', 'RDPCS_PIPE_FIFO_ENABLE', + 'RDPCS_PIPE_FIFO_LANE_DISABLE', 'RDPCS_PIPE_FIFO_LANE_ENABLE', + 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', + 'RDPCS_PIPE_SOFT_RESET_DISABLE', 'RDPCS_PIPE_SOFT_RESET_ENABLE', + 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', + 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_SEQ', + 'RECTLIST', 'RECT_2D', 'RED_LUT', 'REFER_TO_DP_SOF', + 'REFER_TO_OTG_SOF', 'REG_SECURE_VIOLATE_READ', + 'REG_SECURE_VIOLATE_WRITE', 'REG_UNALLOCATED_ADDR_READ', + 'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ', + 'REG_VIRTUAL_WRITE', 'RESERVED_1', 'RESERVED_10', 'RESERVED_11', + 'RESERVED_20', 'RESERVED_21', 'RESERVED_22', 'RESERVED_23', + 'RESERVED_3', 'RESERVED_32', 'RESERVED_33', 'RESERVED_34', + 'RESERVED_35', 'RESERVED_44', 'RESERVED_45', 'RESERVED_46', + 'RESERVED_47', 'RESERVED_56', 'RESERVED_57', 'RESERVED_58', + 'RESERVED_59', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62', + 'RESERVED_63', 'RESERVED_72', 'RESERVED_73', 'RESERVED_74', + 'RESERVED_75', 'RESERVED_8', 'RESERVED_84', 'RESERVED_85', + 'RESERVED_86', 'RESERVED_87', 'RESERVED_88', 'RESERVED_89', + 'RESERVED_9', 'RESERVED_90', 'RESERVED_91', 'RESERVED_ES', + 'RESERVED_LS', 'RESERVED_RDPOLICY', 'RESERVED_VS', + 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RESPONSE_STATUS', 'RE_Z', + 'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102', + 'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', + 'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', + 'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', + 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE', + 'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF', + 'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL', + 'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE', + 'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3', + 'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5', + 'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET', + 'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT', + 'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT', + 'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1', + 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT', + 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', + 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', + 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 'ROM_SIGNATURE', + 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES', + 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE', + 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', 'RSMU_HWIP', 'RSPM_CMD', + 'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE', + 'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE', + 'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET', + 'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT', + 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', + 'ReadPolicy', 'Reserved_0x00', 'Reserved_0x09', + 'RingCounterControl', 'SAMPLE_PIPELINESTAT', + 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', + 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', 'SATA_HWID', + 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', 'SCL_ALPHA_COEF_FIRST', + 'SCL_ALPHA_COEF_SECOND', 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', + 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', + 'SCL_CHROMA_COEF_FIRST', 'SCL_CHROMA_COEF_SECOND', + 'SCL_COEF_2TAP_HARDCODE_OFF', 'SCL_COEF_2TAP_HARDCODE_ON', + 'SCL_COEF_CHROMA_HORZ_FILTER', 'SCL_COEF_CHROMA_VERT_FILTER', + 'SCL_COEF_FILTER_TYPE_SEL', 'SCL_COEF_LUMA_HORZ_FILTER', + 'SCL_COEF_LUMA_VERT_FILTER', 'SCL_COEF_RAM_SEL', + 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', 'SCL_SHARP_DISABLE', + 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SCPM_DISABLE', 'SCPM_ENABLE', + 'SCPM_ENABLE_WITH_SCPM_ERR', 'SC_BACKEND_BUSY', + 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', + 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', + 'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED', + 'SC_BM_BE3_STALLED', 'SC_BM_BUSY', + 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO', + 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_DB0_QUAD_INTF_BUSY', + 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', 'SC_DB0_QUAD_INTF_IDLE', + 'SC_DB0_QUAD_INTF_SEND', 'SC_DB0_QUAD_INTF_STALLED_BY_DB', + 'SC_DB0_TILE_INTERFACE_BUSY', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_DB0_TILE_MASK_FIFO_FULL', + 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 'SC_DB1_QUAD_INTF_BUSY', 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', + 'SC_DB1_QUAD_INTF_IDLE', 'SC_DB1_QUAD_INTF_SEND', + 'SC_DB1_QUAD_INTF_STALLED_BY_DB', 'SC_DB1_TILE_INTERFACE_BUSY', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_DB1_TILE_MASK_FIFO_FULL', + 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', + 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', + 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', + 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', + 'SC_FSR_WALKED', 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', + 'SC_FULL_QTR_QUAD', 'SC_GRP0_DYN_SCLK_BUSY', + 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', + 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', + 'SC_GRP5_DYN_SCLK_BUSY', 'SC_GRP6_DYN_SCLK_BUSY', + 'SC_GRP7_DYN_SCLK_BUSY', 'SC_GRP8_DYN_SCLK_BUSY', + 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', + 'SC_HALF_LSB', 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', + 'SC_LSB_TWO_SIDED', 'SC_MULTICYCLE_BUBBLE_FREEZE', + 'SC_P0_DETAIL_QUAD_COUNT', 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 'SC_P0_DETAIL_QUAD_WITH_2_PIX', 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 'SC_P0_DETAIL_QUAD_WITH_4_PIX', 'SC_P0_HIZ_QUAD_COUNT', + 'SC_P0_HIZ_QUAD_PER_TILE_H0', 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 'SC_P0_HIZ_QUAD_PER_TILE_H10', 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 'SC_P0_HIZ_QUAD_PER_TILE_H12', 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 'SC_P0_HIZ_QUAD_PER_TILE_H14', 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 'SC_P0_HIZ_QUAD_PER_TILE_H16', 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 'SC_P0_HIZ_QUAD_PER_TILE_H3', 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 'SC_P0_HIZ_QUAD_PER_TILE_H5', 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 'SC_P0_HIZ_QUAD_PER_TILE_H7', 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 'SC_P0_HIZ_QUAD_PER_TILE_H9', 'SC_P0_HIZ_TILE_COUNT', + 'SC_P1_DETAIL_QUAD_COUNT', 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 'SC_P1_DETAIL_QUAD_WITH_2_PIX', 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 'SC_P1_DETAIL_QUAD_WITH_4_PIX', 'SC_P1_HIZ_QUAD_COUNT', + 'SC_P1_HIZ_QUAD_PER_TILE_H0', 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 'SC_P1_HIZ_QUAD_PER_TILE_H10', 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 'SC_P1_HIZ_QUAD_PER_TILE_H12', 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 'SC_P1_HIZ_QUAD_PER_TILE_H14', 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 'SC_P1_HIZ_QUAD_PER_TILE_H16', 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 'SC_P1_HIZ_QUAD_PER_TILE_H3', 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 'SC_P1_HIZ_QUAD_PER_TILE_H5', 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 'SC_P1_HIZ_QUAD_PER_TILE_H7', 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 'SC_P1_HIZ_QUAD_PER_TILE_H9', 'SC_P1_HIZ_TILE_COUNT', + 'SC_P2_DETAIL_QUAD_COUNT', 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 'SC_P2_DETAIL_QUAD_WITH_2_PIX', 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 'SC_P2_DETAIL_QUAD_WITH_4_PIX', 'SC_P2_HIZ_QUAD_COUNT', + 'SC_P2_HIZ_QUAD_PER_TILE_H0', 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 'SC_P2_HIZ_QUAD_PER_TILE_H10', 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 'SC_P2_HIZ_QUAD_PER_TILE_H12', 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 'SC_P2_HIZ_QUAD_PER_TILE_H14', 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 'SC_P2_HIZ_QUAD_PER_TILE_H16', 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 'SC_P2_HIZ_QUAD_PER_TILE_H3', 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 'SC_P2_HIZ_QUAD_PER_TILE_H5', 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 'SC_P2_HIZ_QUAD_PER_TILE_H7', 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 'SC_P2_HIZ_QUAD_PER_TILE_H9', 'SC_P2_HIZ_TILE_COUNT', + 'SC_P3_DETAIL_QUAD_COUNT', 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 'SC_P3_DETAIL_QUAD_WITH_2_PIX', 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 'SC_P3_DETAIL_QUAD_WITH_4_PIX', 'SC_P3_HIZ_QUAD_COUNT', + 'SC_P3_HIZ_QUAD_PER_TILE_H0', 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 'SC_P3_HIZ_QUAD_PER_TILE_H10', 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 'SC_P3_HIZ_QUAD_PER_TILE_H12', 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 'SC_P3_HIZ_QUAD_PER_TILE_H14', 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 'SC_P3_HIZ_QUAD_PER_TILE_H16', 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 'SC_P3_HIZ_QUAD_PER_TILE_H3', 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 'SC_P3_HIZ_QUAD_PER_TILE_H5', 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 'SC_P3_HIZ_QUAD_PER_TILE_H7', 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 'SC_P3_HIZ_QUAD_PER_TILE_H9', 'SC_P3_HIZ_TILE_COUNT', + 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', + 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', + 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', + 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', + 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', + 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', + 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', + 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', + 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', + 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', + 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', + 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', + 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', + 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', + 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', + 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', + 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', + 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', + 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', + 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', + 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', + 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', + 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', + 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', + 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', + 'SC_PBB_BUSY_AND_NO_SENDS', + 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH', + 'SC_PBB_END_OF_BIN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', + 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', + 'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', + 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', + 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', + 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', + 'SC_PKR_WAVE_BREAK_FULL_TILE', 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', + 'SC_PK_BUSY', 'SC_PK_DEALLOC_WAVE_BREAK', + 'SC_PK_MAX_DEALLOC_FORCE_EOV', 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', + 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', + 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', + 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', + 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', + 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', + 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_ENG_MULTICYCLE_BUBBLE', + 'SC_PS_PA0_SC_FIFO_EMPTY', 'SC_PS_PA0_SC_FIFO_FULL', + 'SC_PS_PA1_SC_FIFO_EMPTY', 'SC_PS_PA1_SC_FIFO_FULL', + 'SC_PS_PA2_SC_FIFO_EMPTY', 'SC_PS_PA2_SC_FIFO_FULL', + 'SC_PS_PA3_SC_FIFO_EMPTY', 'SC_PS_PA3_SC_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL', + 'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP', + 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PW_BM_PASS_EMPTY_PRIM', + 'SC_QTR_FULL_QUAD', 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', + 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', + 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', + 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', + 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', + 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', + 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', + 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', + 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', + 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', + 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', + 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_QUAD_COUNT', + 'SC_QZ1_QUAD_PER_TILE_H0', 'SC_QZ1_QUAD_PER_TILE_H1', + 'SC_QZ1_QUAD_PER_TILE_H10', 'SC_QZ1_QUAD_PER_TILE_H11', + 'SC_QZ1_QUAD_PER_TILE_H12', 'SC_QZ1_QUAD_PER_TILE_H13', + 'SC_QZ1_QUAD_PER_TILE_H14', 'SC_QZ1_QUAD_PER_TILE_H15', + 'SC_QZ1_QUAD_PER_TILE_H16', 'SC_QZ1_QUAD_PER_TILE_H2', + 'SC_QZ1_QUAD_PER_TILE_H3', 'SC_QZ1_QUAD_PER_TILE_H4', + 'SC_QZ1_QUAD_PER_TILE_H5', 'SC_QZ1_QUAD_PER_TILE_H6', + 'SC_QZ1_QUAD_PER_TILE_H7', 'SC_QZ1_QUAD_PER_TILE_H8', + 'SC_QZ1_QUAD_PER_TILE_H9', 'SC_QZ1_TILE_COUNT', + 'SC_QZ1_TILE_COVERED_COUNT', 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', + 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', + 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', + 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', + 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', + 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', + 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', + 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', + 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', + 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', + 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_QUAD_COUNT', + 'SC_QZ3_QUAD_PER_TILE_H0', 'SC_QZ3_QUAD_PER_TILE_H1', + 'SC_QZ3_QUAD_PER_TILE_H10', 'SC_QZ3_QUAD_PER_TILE_H11', + 'SC_QZ3_QUAD_PER_TILE_H12', 'SC_QZ3_QUAD_PER_TILE_H13', + 'SC_QZ3_QUAD_PER_TILE_H14', 'SC_QZ3_QUAD_PER_TILE_H15', + 'SC_QZ3_QUAD_PER_TILE_H16', 'SC_QZ3_QUAD_PER_TILE_H2', + 'SC_QZ3_QUAD_PER_TILE_H3', 'SC_QZ3_QUAD_PER_TILE_H4', + 'SC_QZ3_QUAD_PER_TILE_H5', 'SC_QZ3_QUAD_PER_TILE_H6', + 'SC_QZ3_QUAD_PER_TILE_H7', 'SC_QZ3_QUAD_PER_TILE_H8', + 'SC_QZ3_QUAD_PER_TILE_H9', 'SC_QZ3_TILE_COUNT', + 'SC_QZ3_TILE_COVERED_COUNT', 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 'SC_QZQP_WINDOW_VALID', 'SC_QZQP_WINDOW_VALID_BUSY', + 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', 'SC_RESERVED_1', + 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY', + 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', + 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', + 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_0_0', + 'SC_SPI_DEALLOC_0_1', 'SC_SPI_DEALLOC_0_2', 'SC_SPI_DEALLOC_1_0', + 'SC_SPI_DEALLOC_1_1', 'SC_SPI_DEALLOC_1_2', 'SC_SPI_DEALLOC_2_0', + 'SC_SPI_DEALLOC_2_1', 'SC_SPI_DEALLOC_2_2', 'SC_SPI_DEALLOC_3_0', + 'SC_SPI_DEALLOC_3_1', 'SC_SPI_DEALLOC_3_2', 'SC_SPI_EVENT', + 'SC_SPI_FPOV_0', 'SC_SPI_FPOV_1', 'SC_SPI_FPOV_2', + 'SC_SPI_FPOV_3', 'SC_SPI_SEND', 'SC_SRPS_WINDOW_VALID', + 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', + 'SC_STALLED_BY_DB0_TILEFIFO', 'SC_STALLED_BY_DB1_TILEFIFO', + 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', + 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', + 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', + 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', + 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 'SC_SUPERTILE_COUNT', + 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', + 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', + 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', + 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', + 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', + 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', + 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', + 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', + 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', + 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', + 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', + 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', + 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', + 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', + 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', + 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', + 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', + 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', + 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', + 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', + 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X', + 'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRS_COMB_MODE_MAX', + 'SC_VRS_COMB_MODE_MIN', 'SC_VRS_COMB_MODE_OVERRIDE', + 'SC_VRS_COMB_MODE_PASSTHRU', 'SC_VRS_COMB_MODE_SATURATE', + 'SDMA0_HWID', 'SDMA0_HWIP', 'SDMA1_HWID', 'SDMA1_HWIP', + 'SDMA2_HWID', 'SDMA2_HWIP', 'SDMA3_HWID', 'SDMA3_HWIP', + 'SDMA4_HWIP', 'SDMA5_HWIP', 'SDMA6_HWIP', 'SDMA7_HWIP', + 'SDMA_PERFMON_SEL', 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', + 'SDMA_PERFMON_SEL_CE_DST_IDLE', 'SDMA_PERFMON_SEL_CE_INFO1_FULL', + 'SDMA_PERFMON_SEL_CE_INFO_FULL', 'SDMA_PERFMON_SEL_CE_IN_IDLE', + 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', 'SDMA_PERFMON_SEL_CE_OUT_IDLE', + 'SDMA_PERFMON_SEL_CE_RD_STALL', 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', + 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', + 'SDMA_PERFMON_SEL_CE_WR_IDLE', 'SDMA_PERFMON_SEL_CE_WR_STALL', + 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE', + 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL', + 'SDMA_PERFMON_SEL_EX_IDLE', + 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', 'SDMA_PERFMON_SEL_GCR_RTN', + 'SDMA_PERFMON_SEL_GCR_SEND', 'SDMA_PERFMON_SEL_GFX_SELECT', + 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE', + 'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 'SDMA_PERFMON_SEL_MC_RD_COUNT', 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD', + 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_PAGE_SELECT', + 'SDMA_PERFMON_SEL_RB_CMD_FULL', 'SDMA_PERFMON_SEL_RB_CMD_IDLE', + 'SDMA_PERFMON_SEL_RB_EMPTY', 'SDMA_PERFMON_SEL_RB_FULL', + 'SDMA_PERFMON_SEL_RB_RPTR_WB', 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR', + 'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_RLC0_SELECT', + 'SDMA_PERFMON_SEL_RLC1_SELECT', + 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN', + 'SDMA_PERFMON_SEL_TLBI_SEND', + 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL', + 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY', + 'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START', + 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE', + 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', + 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', + 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE', + 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', + 'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', + 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END', + 'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START', + 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', + 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', + 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', + 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERF_SEL_F32_CH_WR_REQ', 'SDMA_PERF_SEL_F32_CH_WR_RET', + 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND', + 'SDMA_PERF_SEL_GFX_SELECT', 'SDMA_PERF_SEL_GPUVM_INV_HIGH', + 'SDMA_PERF_SEL_GPUVM_INV_LOW', 'SDMA_PERF_SEL_IB_CH_RD_REQ', + 'SDMA_PERF_SEL_IB_CH_RD_RET', 'SDMA_PERF_SEL_IB_CMD_FULL', + 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', + 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', + 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD', + 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', + 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', + 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', + 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', + 'SDMA_PERF_SEL_RB_CH_RD_REQ', 'SDMA_PERF_SEL_RB_CH_RD_RET', + 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', + 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', + 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', + 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', + 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', + 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', + 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', + 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', + 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR', + 'SDPMUX_HWID', 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', + 'SEGMENTS_1', 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', + 'SEGMENTS_32', 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', + 'SEL_DTBCLK0', 'SEL_DTBCLK1', 'SEL_REFCLK0', 'SEM_ECC_ERROR', + 'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION', + 'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET', + 'SEM_PERF_SEL_ATC_VM_INVALIDATION', 'SEM_PERF_SEL_ATC_XNACK', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', + 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', + 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', + 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', + 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA2_REQ_WAIT', + 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA3_REQ_WAIT', + 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', 'SEM_PERF_SEL_UVD1_REQ_WAIT', + 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', + 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', + 'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR', + 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', + 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR', + 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', + 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', + 'SH_MEM_ALIGNMENT_MODE_DWORD', + 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', + 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE', + 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', + 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', + 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', + 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', + 'SIMM16_WAIT_EVENT_EXP_RDY_SIZE', + 'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K', + 'SLVERR', 'SMUIO_HWID', 'SMUIO_HWIP', 'SMU_INTR', + 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', + 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', 'SOC15_IH_CLIENTID_ACP', + 'SOC15_IH_CLIENTID_ATHUB', 'SOC15_IH_CLIENTID_ATS', + 'SOC15_IH_CLIENTID_BIF', 'SOC15_IH_CLIENTID_DCE', + 'SOC15_IH_CLIENTID_DF', 'SOC15_IH_CLIENTID_EA', + 'SOC15_IH_CLIENTID_GRBM_CP', 'SOC15_IH_CLIENTID_IH', + 'SOC15_IH_CLIENTID_ISP', 'SOC15_IH_CLIENTID_MAX', + 'SOC15_IH_CLIENTID_MP0', 'SOC15_IH_CLIENTID_MP1', + 'SOC15_IH_CLIENTID_PCIE0', 'SOC15_IH_CLIENTID_PWR', + 'SOC15_IH_CLIENTID_RESERVED', 'SOC15_IH_CLIENTID_RLC', + 'SOC15_IH_CLIENTID_ROM_SMUIO', 'SOC15_IH_CLIENTID_SDMA0', + 'SOC15_IH_CLIENTID_SDMA1', 'SOC15_IH_CLIENTID_SDMA2', + 'SOC15_IH_CLIENTID_SDMA3', + 'SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid', + 'SOC15_IH_CLIENTID_SDMA4', 'SOC15_IH_CLIENTID_SDMA5', + 'SOC15_IH_CLIENTID_SDMA6', 'SOC15_IH_CLIENTID_SDMA7', + 'SOC15_IH_CLIENTID_SE0SH', 'SOC15_IH_CLIENTID_SE1SH', + 'SOC15_IH_CLIENTID_SE2SH', 'SOC15_IH_CLIENTID_SE3SH', + 'SOC15_IH_CLIENTID_THM', 'SOC15_IH_CLIENTID_UTCL2', + 'SOC15_IH_CLIENTID_UTCL2LOG', 'SOC15_IH_CLIENTID_UVD', + 'SOC15_IH_CLIENTID_UVD1', 'SOC15_IH_CLIENTID_VCE0', + 'SOC15_IH_CLIENTID_VCE1', 'SOC15_IH_CLIENTID_VCN', + 'SOC15_IH_CLIENTID_VCN1', 'SOC15_IH_CLIENTID_VMC', + 'SOC15_IH_CLIENTID_VMC1', 'SOC15_IH_CLIENTID_XDMA', + 'SOC21_IH_CLIENTID_ATHUB', 'SOC21_IH_CLIENTID_BIF', + 'SOC21_IH_CLIENTID_DCN', 'SOC21_IH_CLIENTID_DF', + 'SOC21_IH_CLIENTID_GFX', 'SOC21_IH_CLIENTID_GRBM_CP', + 'SOC21_IH_CLIENTID_IH', 'SOC21_IH_CLIENTID_IMU', + 'SOC21_IH_CLIENTID_ISP', 'SOC21_IH_CLIENTID_LSDMA', + 'SOC21_IH_CLIENTID_MAX', 'SOC21_IH_CLIENTID_MP0', + 'SOC21_IH_CLIENTID_MP1', 'SOC21_IH_CLIENTID_MP3', + 'SOC21_IH_CLIENTID_PWR', 'SOC21_IH_CLIENTID_RLC', + 'SOC21_IH_CLIENTID_ROM_SMUIO', 'SOC21_IH_CLIENTID_THM', + 'SOC21_IH_CLIENTID_VCN', 'SOC21_IH_CLIENTID_VCN1', + 'SOC21_IH_CLIENTID_VMC', 'SOC21_IH_CLIENTID_VPE', + 'SOC21_IH_CLIENTID_VPE1', 'SOFT_RESET', 'SOFT_RESET_0', + 'SOFT_RESET_1', 'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', + 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', + 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL', + 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY', + 'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE', + 'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL', + 'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WINDOW_VALID', + 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', + 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', + 'SPI_PERF_CSN_WAVE', 'SPI_PERF_CSN_WINDOW_VALID', + 'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL', + 'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL', + 'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL', + 'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL', + 'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL', + 'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL', + 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', + 'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', + 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP', + 'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', + 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_EXP_DONE', + 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_HS_DEALLOC', + 'SPI_PERF_GS_INDX0_STALL', 'SPI_PERF_GS_INDX1_STALL', + 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0', + 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL', + 'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL', + 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', + 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', + 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', + 'SPI_PERF_HS_OFFCHIP_LDS_STALL', 'SPI_PERF_HS_PERS_UPD_FULL0', + 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL', + 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', + 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS', + 'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY', + 'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC', + 'SPI_PERF_PS0_EVENT_WAVE', 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 'SPI_PERF_PS0_OPT_WAVE', 'SPI_PERF_PS0_PRIM_BIN0', + 'SPI_PERF_PS0_PRIM_BIN1', 'SPI_PERF_PS0_WAVE', + 'SPI_PERF_PS0_WAVEID_STARVED', + 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WINDOW_VALID', + 'SPI_PERF_PS1_2_WAVE_GROUPS', 'SPI_PERF_PS1_ACTIVE', + 'SPI_PERF_PS1_BUSY', 'SPI_PERF_PS1_CRAWLER_STALL', + 'SPI_PERF_PS1_DEALLOC', 'SPI_PERF_PS1_EVENT_WAVE', + 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS1_OPT_WAVE', + 'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1', + 'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED', + 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WINDOW_VALID', + 'SPI_PERF_PS2_2_WAVE_GROUPS', 'SPI_PERF_PS2_ACTIVE', + 'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CRAWLER_STALL', + 'SPI_PERF_PS2_DEALLOC', 'SPI_PERF_PS2_EVENT_WAVE', + 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS2_OPT_WAVE', + 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', + 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED', + 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WINDOW_VALID', + 'SPI_PERF_PS3_2_WAVE_GROUPS', 'SPI_PERF_PS3_ACTIVE', + 'SPI_PERF_PS3_BUSY', 'SPI_PERF_PS3_CRAWLER_STALL', + 'SPI_PERF_PS3_DEALLOC', 'SPI_PERF_PS3_EVENT_WAVE', + 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS3_OPT_WAVE', + 'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1', + 'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED', + 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WINDOW_VALID', + 'SPI_PERF_PS_EXP_ALLOC', 'SPI_PERF_PS_EXP_ARB_CONFLICT', + 'SPI_PERF_PS_EXP_DONE', 'SPI_PERF_PS_PERS_UPD_FULL0', + 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_PS_PWS_STALL', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', + 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK', + 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', + 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS', + 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2', + 'SPI_PERF_RA_PRE_ALLOC_STALL', 'SPI_PERF_RA_REQ_NO_ALLOC', + 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 'SPI_PERF_RA_REQ_NO_ALLOC_PS', 'SPI_PERF_RA_RES_STALL_CSG', + 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS', + 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS', + 'SPI_PERF_RA_RSV_UPD', 'SPI_PERF_RA_TASK_REQ_BIN3', + 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', + 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', + 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL', + 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', + 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', + 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SWC_CSGN_WR', + 'SPI_PERF_SWC_CSN_WR', 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', + 'SPI_PERF_SWC_PS_WR', 'SPI_PERF_VWC_CSGN_WR', + 'SPI_PERF_VWC_CSN_WR', 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', + 'SPI_PERF_VWC_HS_WR', 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR', + 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', + 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', + 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', + 'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4', + 'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', + 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', + 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', + 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', + 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', + 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', + 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', + 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', + 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST', + 'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_OPERAND', + 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL', + 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_VGPR_OPERAND', 'SP_PERF_SEL_VGPR_EXP_RD', + 'SP_PERF_SEL_VGPR_RD', 'SP_PERF_SEL_VGPR_SPI_WR', + 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', 'SP_PERF_SEL_VGPR_VMEM_RD', + 'SP_PERF_SEL_VGPR_WR', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', + 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS', + 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', + 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_DCACHE_REQ', + 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', + 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', + 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ', + 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', + 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', + 'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY', + 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', + 'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV', + 'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES', + 'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS', + 'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS', + 'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_MSG', + 'SQG_PERF_SEL_MSG_BUS_BUSY', 'SQG_PERF_SEL_MSG_INTERRUPT', + 'SQG_PERF_SEL_NONE', 'SQG_PERF_SEL_PS_QUADS', + 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS', + 'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_WAVE32_ITEMS', + 'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES', + 'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64', + 'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64', + 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16', + 'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48', + 'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_RESTORED', + 'SQG_PERF_SEL_WAVES_SAVED', 'SQG_PERF_SEL_WAVE_CYCLES', + 'SQIND_GLOBAL_REGS_OFFSET', 'SQIND_GLOBAL_REGS_SIZE', + 'SQIND_LOCAL_REGS_OFFSET', 'SQIND_LOCAL_REGS_SIZE', + 'SQIND_WAVE_HWREGS_OFFSET', 'SQIND_WAVE_HWREGS_SIZE', + 'SQIND_WAVE_SGPRS_OFFSET', 'SQIND_WAVE_SGPRS_SIZE', + 'SQIND_WAVE_VGPRS_OFFSET', 'SQIND_WAVE_VGPRS_SIZE', + 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', 'SQPERFSDEC_BEGIN', + 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', 'SQPWRDEC_END', + 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', + 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', + 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', + 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', + 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', + 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', + 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', + 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', + 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', + 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', + 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', + 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', + 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', + 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', + 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', + 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', + 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', + 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', + 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', + 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', + 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', + 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', + 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', + 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', + 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', + 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', + 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP', + 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE', + 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', + 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', + 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', + 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST', + 'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER', + 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN', + 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS', + 'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG', + 'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR', + 'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', 'SQ_LLC_0', 'SQ_LLC_1', + 'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2', + 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', + 'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP', + 'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_NO_ARB_WIN', + 'SQ_NO_INST_ISSUE_NO_INSTS', 'SQ_NO_INST_ISSUE_OTHER', + 'SQ_NO_INST_ISSUE_SLEEP_WAIT', 'SQ_NO_INST_ISSUE_S_WAITCNT', + 'SQ_OOB_COMPLETE', 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', + 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', + 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', + 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', + 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', + 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', + 'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BRANCH', + 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', + 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP', + 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', + 'SQ_PERF_SEL_INSTS_GDS', 'SQ_PERF_SEL_INSTS_INTERNAL', + 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_SALU', + 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM', 'SQ_PERF_SEL_INSTS_TEX', + 'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_STORE', + 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 'SQ_PERF_SEL_INSTS_VALU_DP', + 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 'SQ_PERF_SEL_INSTS_VALU_VINTERP', + 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', + 'SQ_PERF_SEL_INSTS_WAVE32', 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', + 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP', + 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 'SQ_PERF_SEL_INST_CYCLES_GDS', 'SQ_PERF_SEL_INST_CYCLES_LDS', + 'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU', + 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', + 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS', + 'SQ_PERF_SEL_ITEMS_MAX_VALU', 'SQ_PERF_SEL_ITEMS_VALU', + 'SQ_PERF_SEL_ITEM_CYCLES_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG', + 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE', + 'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV', + 'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 'SQ_PERF_SEL_SP_CONST_CYCLES', + 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0', + 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', + 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', + 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', + 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', + 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', + 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', + 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', + 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', + 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', + 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', + 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', + 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', + 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', + 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 'SQ_PERF_SEL_VALU_RETURN_SDST', + 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', 'SQ_PERF_SEL_VMEM_BUS_STALL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', + 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_EXP', + 'SQ_PERF_SEL_WAIT_CNT_LGKM', 'SQ_PERF_SEL_WAIT_CNT_VMVS', + 'SQ_PERF_SEL_WAIT_DELAY_ALU', 'SQ_PERF_SEL_WAIT_DEPCTR', + 'SQ_PERF_SEL_WAIT_EXP_ALLOC', 'SQ_PERF_SEL_WAIT_IFETCH', + 'SQ_PERF_SEL_WAIT_INST_ANY', 'SQ_PERF_SEL_WAIT_INST_BR_MSG', + 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', + 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_SCA', + 'SQ_PERF_SEL_WAIT_INST_TEX', 'SQ_PERF_SEL_WAIT_INST_VALU', + 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', + 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_TTRACE', + 'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', + 'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS', + 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32', + 'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32', + 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', + 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', + 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', + 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', + 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', + 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', + 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', + 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', + 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', + 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', + 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', + 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', + 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', + 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', + 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', + 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SEL_0', 'SQ_SEL_1', + 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', + 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_TEX_ANISO_RATIO', + 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', + 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', + 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', + 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', + 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', + 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 'SQ_TEX_DEPTH_COMPARE_GREATER', + 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', + 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', + 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', + 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', + 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', + 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', + 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', + 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', + 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', + 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', + 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', + 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', + 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', + 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', + 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', 'SQ_TT_MODE', + 'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF', + 'SQ_TT_MODE_ON', 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', + 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', + 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', + 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', + 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', + 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', 'SQ_TT_RT_FREQ', + 'SQ_TT_RT_FREQ_1024_CLK', 'SQ_TT_RT_FREQ_4096_CLK', + 'SQ_TT_RT_FREQ_NEVER', 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', + 'SQ_TT_TOKEN_MASK_ALL_BIT', 'SQ_TT_TOKEN_MASK_ALL_SHIFT', + 'SQ_TT_TOKEN_MASK_COMP_BIT', 'SQ_TT_TOKEN_MASK_COMP_SHIFT', + 'SQ_TT_TOKEN_MASK_CONFIG_BIT', 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', + 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', + 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_INST_EXCLUDE', + 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT', + 'SQ_TT_TOKEN_MASK_REG_EXCLUDE', + 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', 'SQ_TT_TOKEN_MASK_RSVD_BIT', + 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', 'SQ_TT_TOKEN_MASK_SHDEC_BIT', + 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', 'SQ_TT_TOKEN_MASK_SQDEC_BIT', + 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER', + 'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK', + 'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC', + 'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT', + 'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT', + 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', + 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', + 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT', + 'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', + 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', + 'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096', + 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE', + 'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE', + 'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE', + 'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE', + 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', + 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES', + 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT', + 'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', + 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', + 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', + 'SQ_WAVE_TYPE_PS3', 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', + 'SQ_WAVE_TYPE_RSVD2', 'SRCID_NONSECURE_CP', + 'SRCID_NONSECURE_CP_RCIU', 'SRCID_RLC', 'SRCID_RLCV', + 'SRCID_SECURE_CP', 'SRCID_SECURE_CP_RCIU', 'SST_HWID', 'STALL', + 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', + 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', + 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', + 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', + 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', + 'STREAM_0_SYNCHRONIZATION', + 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_10_SYNCHRONIZATION', + 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION', + 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION', + 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION', + 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION', + 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION', + 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_1_SYNCHRONIZATION', + 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_2_SYNCHRONIZATION', + 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_3_SYNCHRONIZATION', + 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_4_SYNCHRONIZATION', + 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION', + 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION', + 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION', + 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION', + 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION', + 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_DSC_444_RGB', 'STREAM_DSC_DISABLE', + 'STREAM_DSC_NATIVE_422_420', 'STREAM_ODM_COMBINE_1_SEGMENT', + 'STREAM_ODM_COMBINE_2_SEGMENT', 'STREAM_ODM_COMBINE_4_SEGMENT', + 'STREAM_ODM_COMBINE_RESERVED', 'STREAM_PIXEL_ENCODING_420', + 'STREAM_PIXEL_ENCODING_422', 'STREAM_PIXEL_ENCODING_444_RGB', + 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'STRM_PERFMON_STATE_RESERVED_3', + 'STRM_PERFMON_STATE_START_COUNTING', + 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', + 'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B', + 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', + 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B', + 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK', + 'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B', + 'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B', + 'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE', + 'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE', + 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', + 'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL', + 'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE', + 'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', + 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLED', + 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', + 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', + 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', + 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', + 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', + 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', + 'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT', + 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', + 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT', + 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', + 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', + 'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY', + 'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE', + 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', + 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', + 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', + 'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE', + 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', + 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', + 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', + 'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE', + 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', + 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', + 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', + 'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE', + 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', + 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', + 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', + 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', + 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', + 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', + 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', + 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', + 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', + 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', + 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF', + 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY', + 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL', + 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', + 'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL', + 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', + 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', + 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', + 'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3', + 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', + 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', + 'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION', + 'SYMCLK_FE_FORCE_EN', 'SYMCLK_FE_FORCE_EN_DISABLE', + 'SYMCLK_FE_FORCE_EN_ENABLE', 'SYMCLK_FE_FORCE_SRC', + 'SYMCLK_FE_FORCE_SRC_RESERVED', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'SYSTEMHUB_HWID', 'ScMap', + 'ScUncertaintyRegionMode', 'ScUncertaintyRegionMult', 'ScXsel', + 'ScYsel', 'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel', + 'SeXsel', 'SeYsel', 'SourceFormat', 'Spare_257', 'StencilOp', + 'TA_FW_TYPE_MAX_INDEX', 'TA_FW_TYPE_PSP_ASD', + 'TA_FW_TYPE_PSP_DTM', 'TA_FW_TYPE_PSP_HDCP', 'TA_FW_TYPE_PSP_RAP', + 'TA_FW_TYPE_PSP_RAS', 'TA_FW_TYPE_PSP_SECUREDISPLAY', + 'TA_FW_TYPE_PSP_XGMI', 'TA_FW_TYPE_UNKOWN', 'TA_PERFCOUNT_SEL', + 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', + 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 'TA_PERF_SEL_addresser_stalled_cycles', + 'TA_PERF_SEL_aligner_busy', + 'TA_PERF_SEL_aligner_clk_valid_cycles', + 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', + 'TA_PERF_SEL_aniso_12_cycle_quads', + 'TA_PERF_SEL_aniso_14_cycle_quads', + 'TA_PERF_SEL_aniso_16_cycle_quads', + 'TA_PERF_SEL_aniso_1_cycle_quads', + 'TA_PERF_SEL_aniso_2_cycle_quads', + 'TA_PERF_SEL_aniso_4_cycle_quads', + 'TA_PERF_SEL_aniso_6_cycle_quads', + 'TA_PERF_SEL_aniso_8_cycle_quads', + 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 'TA_PERF_SEL_aniso_stalled_cycles', + 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_write_data_input_cycles', + 'TA_PERF_SEL_atomic_write_data_output_cycles', + 'TA_PERF_SEL_bf_busy', + 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_atomic_wavefronts', + 'TA_PERF_SEL_buffer_flat_1_op_burst', + 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 'TA_PERF_SEL_buffer_has_index_instructions', + 'TA_PERF_SEL_buffer_has_offset_instructions', + 'TA_PERF_SEL_buffer_load_wavefronts', + 'TA_PERF_SEL_buffer_store_wavefronts', + 'TA_PERF_SEL_buffer_total_cycles', + 'TA_PERF_SEL_buffer_wavefronts', 'TA_PERF_SEL_bvh_total_cycles', + 'TA_PERF_SEL_color_1_cycle_quads', + 'TA_PERF_SEL_color_2_cycle_quads', + 'TA_PERF_SEL_color_3_cycle_quads', + 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 'TA_PERF_SEL_deriv_stalled_cycles', + 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_flat_atomic_wavefronts', + 'TA_PERF_SEL_flat_load_wavefronts', + 'TA_PERF_SEL_flat_store_wavefronts', + 'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts', + 'TA_PERF_SEL_gradient_busy', + 'TA_PERF_SEL_gradient_clk_valid_cycles', + 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', + 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', + 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 'TA_PERF_SEL_ibubble_1_cycle_burst', + 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 'TA_PERF_SEL_image_atomic_wavefronts', + 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_1_op_burst', + 'TA_PERF_SEL_image_bvh_2to3_op_burst', + 'TA_PERF_SEL_image_bvh_4to7_op_burst', + 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_ge8_op_burst', + 'TA_PERF_SEL_image_linked_1_op_burst', + 'TA_PERF_SEL_image_linked_2to3_op_burst', + 'TA_PERF_SEL_image_linked_4to7_op_burst', + 'TA_PERF_SEL_image_linked_ge8_op_burst', + 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_1_op_burst', + 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 'TA_PERF_SEL_image_nosampler_total_cycles', + 'TA_PERF_SEL_image_read_wavefronts', + 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_op_burst', + 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 'TA_PERF_SEL_image_sampler_has_q_instructions', + 'TA_PERF_SEL_image_sampler_has_r_instructions', + 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 'TA_PERF_SEL_image_sampler_has_t_instructions', + 'TA_PERF_SEL_image_sampler_total_cycles', + 'TA_PERF_SEL_image_sampler_wavefronts', + 'TA_PERF_SEL_image_store_wavefronts', + 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles', + 'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy', + 'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy', + 'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy', + 'TA_PERF_SEL_in_waiting_on_req_cycles', + 'TA_PERF_SEL_in_wfifo_busy', + 'TA_PERF_SEL_latency_ram_ref_required_instructions', + 'TA_PERF_SEL_latency_ram_weights_written_cycles', + 'TA_PERF_SEL_latency_ram_whv_required_instructions', + 'TA_PERF_SEL_latency_ram_whv_required_quads', + 'TA_PERF_SEL_latency_ram_ws_required_instructions', + 'TA_PERF_SEL_latency_ram_ws_required_quads', + 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy', + 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads', + 'TA_PERF_SEL_mip_2_cycle_quads', + 'TA_PERF_SEL_mipmap_invalid_samples', + 'TA_PERF_SEL_mipmap_lod_0_samples', + 'TA_PERF_SEL_mipmap_lod_10_samples', + 'TA_PERF_SEL_mipmap_lod_11_samples', + 'TA_PERF_SEL_mipmap_lod_12_samples', + 'TA_PERF_SEL_mipmap_lod_13_samples', + 'TA_PERF_SEL_mipmap_lod_14_samples', + 'TA_PERF_SEL_mipmap_lod_1_samples', + 'TA_PERF_SEL_mipmap_lod_2_samples', + 'TA_PERF_SEL_mipmap_lod_3_samples', + 'TA_PERF_SEL_mipmap_lod_4_samples', + 'TA_PERF_SEL_mipmap_lod_5_samples', + 'TA_PERF_SEL_mipmap_lod_6_samples', + 'TA_PERF_SEL_mipmap_lod_7_samples', + 'TA_PERF_SEL_mipmap_lod_8_samples', + 'TA_PERF_SEL_mipmap_lod_9_samples', + 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', + 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', + 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', + 'TA_PERF_SEL_num_of_bvh_valid_first_tri', + 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', + 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', + 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', + 'TA_PERF_SEL_num_of_bvh_valid_second_tri', + 'TA_PERF_SEL_num_of_bvh_valid_third_tri', + 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 'TA_PERF_SEL_point_sampled_quads', + 'TA_PERF_SEL_register_clk_valid_cycles', + 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 'TA_PERF_SEL_sampler_clk_valid_cycles', + 'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle', + 'TA_PERF_SEL_smp_idle_ns_busy', + 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_has_w_instructions', + 'TA_PERF_SEL_store_has_x_instructions', + 'TA_PERF_SEL_store_has_y_instructions', + 'TA_PERF_SEL_store_has_z_instructions', + 'TA_PERF_SEL_store_write_data_input_cycles', + 'TA_PERF_SEL_store_write_data_output_cycles', + 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles', + 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles', + 'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads', + 'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles', + 'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst', + 'TA_PERF_SEL_write_4to31_op_burst', + 'TA_PERF_SEL_write_data_clk_valid_cycles', + 'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy', + 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', + 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', + 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', + 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', + 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', + 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', + 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', + 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TA_TYPE_DTM', + 'TA_TYPE_HDCP', 'TA_TYPE_MAX_INDEX', 'TA_TYPE_RAP', 'TA_TYPE_RAS', + 'TA_TYPE_SECUREDISPLAY', 'TA_TYPE_XGMI', 'TB_ACP_NOT_SEND', + 'TB_ACP_PKT_SEND', 'TB_ACR_0_MULTIPLE_RESERVED', + 'TB_ACR_1_MULTIPLE', 'TB_ACR_2_MULTIPLE', + 'TB_ACR_3_MULTIPLE_RESERVED', 'TB_ACR_4_MULTIPLE', + 'TB_ACR_5_MULTIPLE_RESERVED', 'TB_ACR_6_MULTIPLE_RESERVED', + 'TB_ACR_7_MULTIPLE_RESERVED', 'TB_ACR_CONT_DISABLE', + 'TB_ACR_CONT_ENABLE', 'TB_ACR_NOT_SEND', + 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 'TB_ACR_PKT_SEND', + 'TB_ACR_SELECT_32K', 'TB_ACR_SELECT_44K', 'TB_ACR_SELECT_48K', + 'TB_ACR_SELECT_HW', 'TB_ACR_SOURCE_HW', 'TB_ACR_SOURCE_SW', + 'TB_AUDIO_INFO_CONT_DISABLE', 'TB_AUDIO_INFO_CONT_ENABLE', + 'TB_AUDIO_INFO_NOT_SEND', 'TB_AUDIO_INFO_PKT_SEND', + 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'TB_BORROW_MODE_ACTIVE', 'TB_BORROW_MODE_BLANK', + 'TB_BORROW_MODE_NONE', 'TB_BORROW_MODE_RESERVED', + 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', 'TB_CRC_ACTIVE_TRIBYTES', + 'TB_CRC_ALL_TRIBYTES', 'TB_CRC_DATAISLAND_TRIBYTES', + 'TB_CRC_DEEP_COLOR_PACKER', 'TB_CRC_DSC_PACKER', + 'TB_CRC_ENCRYPTOR_INPUT', 'TB_CRC_TB_ENC_INPUT', + 'TB_DEEP_COLOR_DEPTH_24BPP', 'TB_DEEP_COLOR_DEPTH_30BPP', + 'TB_DEEP_COLOR_DEPTH_36BPP', 'TB_DEEP_COLOR_DEPTH_RESERVED', + 'TB_DEFAULT_PHASE_IS_0', 'TB_DEFAULT_PHASE_IS_1', 'TB_DISABLE', + 'TB_DSC_444_RGB', 'TB_DSC_DISABLE', 'TB_DSC_NATIVE_422_420', + 'TB_ENABLE', 'TB_GC_AVMUTE_CONT_DISABLE', + 'TB_GC_AVMUTE_CONT_ENABLE', 'TB_GC_AVMUTE_SET', + 'TB_GC_AVMUTE_UNSET', 'TB_GC_CONT_DISABLE', 'TB_GC_CONT_ENABLE', + 'TB_GC_NOT_SEND', 'TB_GC_PKT_SEND', 'TB_GENERIC_CONT_DISABLE', + 'TB_GENERIC_CONT_ENABLE', 'TB_GENERIC_NOT_SEND', + 'TB_GENERIC_PKT_SEND', 'TB_ISRC_CONT_DISABLE', + 'TB_ISRC_CONT_ENABLE', 'TB_ISRC_NOT_SEND', 'TB_ISRC_PKT_SEND', + 'TB_METADATA_NOT_SEND', 'TB_METADATA_PKT_SEND', 'TB_NOT_RESET', + 'TB_NOT_SYNC_PHASE_ON_FRAME_START', 'TB_NO_ERROR_OCCURRED', + 'TB_OVERFLOW_OCCURRED', 'TB_PIXEL_ENCODING_420', + 'TB_PIXEL_ENCODING_422', 'TB_PIXEL_ENCODING_444_RGB', + 'TB_PKT_LINE_REF_END_OF_ACTIVE', 'TB_PKT_LINE_REF_OTGSOF', + 'TB_RESET', 'TB_SYNC_PHASE_ON_FRAME_START', 'TCC_CACHE_POLICIES', + 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', + 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', + 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', + 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', + 'TCP_CACHE_STORE_POLICY_WT_EVICT', + 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', + 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', + 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', + 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', + 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', + 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', + 'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP', + 'TCP_OPCODE_GATHERH', 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', + 'TCP_OPCODE_READ', 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', + 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT', + 'TCP_PERF_SEL_ALLOC_STALL', + 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1', + 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE', + 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL', + 'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', + 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', 'TCP_PERF_SEL_POWER_STALL', + 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ', + 'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ', + 'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', + 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', 'TCP_PERF_SEL_REQ_WRITE', + 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', 'TCP_PERF_SEL_TA_REQ', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_TA_REQ_GL0_INV', 'TCP_PERF_SEL_TA_REQ_READ', + 'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE', + 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', 'TCP_PERF_SEL_TCP_LATENCY', + 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL', + 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES', + 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', + 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID', + 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', + 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', + 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', + 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', + 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS', + 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', + 'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', + 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', + 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', + 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', + 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', + 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', + 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', + 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', + 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', + 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', + 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', + 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', + 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', + 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', + 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', + 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', + 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', + 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', + 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', + 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', + 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', + 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', + 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', + 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', + 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', + 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', + 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', + 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', + 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', + 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', + 'TC_OP_READ', 'TC_OP_RESERVED_FADD_32', + 'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0', + 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', + 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2', + 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', + 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', + 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', + 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', + 'TC_OP_RESERVED_NON_FLOAT_64_4', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', + 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', + 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', + 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', + 'TD_PERF_SEL_address_cmd_poison', + 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 'TD_PERF_SEL_blend_prt_with_prt_default_1', + 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 'TD_PERF_SEL_burst_bin_bvh4_1', 'TD_PERF_SEL_burst_bin_bvh4_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', + 'TD_PERF_SEL_burst_bin_gather_1', + 'TD_PERF_SEL_burst_bin_gather_2to8', + 'TD_PERF_SEL_burst_bin_gather_9to16', + 'TD_PERF_SEL_burst_bin_gather_gt16', + 'TD_PERF_SEL_burst_bin_nofilter_1', + 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_sampler_1', + 'TD_PERF_SEL_burst_bin_sampler_2to8', + 'TD_PERF_SEL_burst_bin_sampler_9to16', + 'TD_PERF_SEL_burst_bin_sampler_gt16', + 'TD_PERF_SEL_bypassLerp_instr', + 'TD_PERF_SEL_core_state_ram_max_cnt', + 'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr', + 'TD_PERF_SEL_data_poison', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 'TD_PERF_SEL_done_scoreboard_is_full', + 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 'TD_PERF_SEL_done_scoreboard_not_empty', + 'TD_PERF_SEL_four_comp_return_instr', 'TD_PERF_SEL_gather4_instr', + 'TD_PERF_SEL_gather4h_instr', + 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full', + 'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_ldfptr_instr', + 'TD_PERF_SEL_lds_stall', 'TD_PERF_SEL_load_instr', + 'TD_PERF_SEL_lod_warn_from_ta', + 'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr', + 'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr', + 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_nofilter_busy', + 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 'TD_PERF_SEL_nofilter_d16_sclk_en', + 'TD_PERF_SEL_nofilter_d32_sclk_en', + 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 'TD_PERF_SEL_nofilter_formatters_turned_on', + 'TD_PERF_SEL_nofilter_insert_extra_comps', + 'TD_PERF_SEL_nofilter_pkr_full', + 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_sclk_en', + 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none', + 'TD_PERF_SEL_one_comp_return_instr', + 'TD_PERF_SEL_opaque_black_border', + 'TD_PERF_SEL_out_of_order_instr', + 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 'TD_PERF_SEL_prt_ack_instr', + 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', + 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', + 'TD_PERF_SEL_ray_tracing_bvh4_busy', + 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', + 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', + 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', + 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', + 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', + 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', + 'TD_PERF_SEL_reference_data_rams_read', + 'TD_PERF_SEL_resmap_instr', + 'TD_PERF_SEL_resmap_with_aniso_filtering', + 'TD_PERF_SEL_resmap_with_cubemap_corner', + 'TD_PERF_SEL_resmap_with_no_more_filtering', + 'TD_PERF_SEL_resmap_with_volume_filtering', + 'TD_PERF_SEL_sample_c_instr', 'TD_PERF_SEL_sample_instr', + 'TD_PERF_SEL_sampler_accum_sclk_en', + 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', + 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 'TD_PERF_SEL_sampler_bypass_sclk_en', + 'TD_PERF_SEL_sampler_core_sclk_en', + 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 'TD_PERF_SEL_sampler_lerp0_active', + 'TD_PERF_SEL_sampler_lerp1_active', + 'TD_PERF_SEL_sampler_lerp2_active', + 'TD_PERF_SEL_sampler_lerp3_active', + 'TD_PERF_SEL_sampler_lerp_busy', + 'TD_PERF_SEL_sampler_minmax_sclk_en', + 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en', + 'TD_PERF_SEL_sampler_pkr_full', + 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_ta_data_stall', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', + 'TD_PERF_SEL_tc_td_data_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_three_comp_return_instr', + 'TD_PERF_SEL_total_num_instr', + 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_nofilter_instr', + 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', + 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_sampler_instr', + 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 'TD_PERF_SEL_two_comp_return_instr', + 'TD_PERF_SEL_user_defined_border', + 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', + 'TD_PERF_SEL_write_ack_instr', 'TEE_ERROR_NOT_SUPPORTED', + 'TEE_SUCCESS', 'TESS_ISOLINE', 'TESS_QUAD', 'TESS_TRIANGLE', + 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', 'TEST_CLK_SEL_0', + 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', 'TEST_CLK_SEL_3', + 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', 'TEST_CLK_SEL_6', + 'TEST_CLK_SEL_7', 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', + 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', + 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', + 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', + 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', + 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', + 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', + 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', + 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', + 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', + 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', + 'TEX_Clamp_MirrorOnceHalfToBorder', + 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', + 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', + 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', + 'TEX_DepthCompareFunction_Always', + 'TEX_DepthCompareFunction_Equal', + 'TEX_DepthCompareFunction_Greater', + 'TEX_DepthCompareFunction_GreaterEqual', + 'TEX_DepthCompareFunction_Less', + 'TEX_DepthCompareFunction_LessEqual', + 'TEX_DepthCompareFunction_Never', + 'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP', + 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', + 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', + 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', + 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', + 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', + 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', + 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', + 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', + 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', + 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', + 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', + 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', + 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', + 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', + 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', + 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', + 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', + 'THM_HWID', 'THM_HWIP', 'THREAD_TRACE_DRAW', + 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', + 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TIGHT_PACK', + 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', + 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', + 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', + 'TMDS_CTL0_DATA_MODULATION_BIT1', + 'TMDS_CTL0_DATA_MODULATION_BIT2', + 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', + 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', + 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', + 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', + 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', + 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', + 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', + 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', + 'TMDS_CTL1_DATA_MODULATION_BIT0', + 'TMDS_CTL1_DATA_MODULATION_BIT1', + 'TMDS_CTL1_DATA_MODULATION_BIT2', + 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', + 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', + 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', + 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', + 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', + 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', + 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', + 'TMDS_CTL2_DATA_MODULATION_BIT0', + 'TMDS_CTL2_DATA_MODULATION_BIT1', + 'TMDS_CTL2_DATA_MODULATION_BIT2', + 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', + 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', + 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', + 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', + 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', + 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', + 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', + 'TMDS_CTL3_DATA_MODULATION_BIT0', + 'TMDS_CTL3_DATA_MODULATION_BIT1', + 'TMDS_CTL3_DATA_MODULATION_BIT2', + 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', + 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', + 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', + 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', + 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', + 'TMDS_CTL3_PATTERN_OUT_ENABLE', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT', + 'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', + 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', + 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', + 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', + 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', + 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', + 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', + 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', + 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', + 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', + 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', + 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TOTAL_TABLES', + 'TRANSERR', 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', + 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', + 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', + 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', + 'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', + 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', + 'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END', + 'UCONFIG_SPACE_START', 'UMC_HWID', 'UMC_HWIP', 'UNDEF', + 'UNSIGNED', 'USB_HWID', 'USE_MALL_FOR_CURSOR', + 'USE_MALL_FOR_CURSOR_0', 'USE_MALL_FOR_CURSOR_1', + 'USE_MALL_FOR_PSTATE_CHANGE', 'USE_MALL_FOR_PSTATE_CHANGE_0', + 'USE_MALL_FOR_PSTATE_CHANGE_1', 'USE_MALL_FOR_STATIC_SCREEN', + 'USE_MALL_FOR_STATIC_SCREEN_0', 'USE_MALL_FOR_STATIC_SCREEN_1', + 'UTCL0FaultType', 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', + 'UTCL0_TYPE_NORMAL', 'UTCL0_TYPE_SHOOTDOWN', + 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', 'UTCL0_XNACK_RETRY', + 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', 'UTCL1PerfSel', + 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS', + 'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_HITS', + 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', + 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES', + 'UTCL1_PERF_SEL_NONE', 'UTCL1_PERF_SEL_RANGE_INVREQS', + 'UTCL1_PERF_SEL_REQS', 'UTCL1_PERF_SEL_RTNS', + 'UTCL1_PERF_SEL_STALL_MH_FULL', + 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', 'UTCL1_PERF_SEL_UTCL2_REQS', + 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS', + 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', + 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', + 'UTCL1_XNACK_SUCCESS', 'UVD_HWID', 'UVD_HWIP', 'V11_STRUCTS_H_', + 'VCE_HWID', 'VCE_HWIP', 'VCN1_HWIP', 'VCN_HWID', 'VCN_HWIP', + 'VCN_INFO', 'VCN_INFO_TABLE_ID', + 'VCN_INFO_TABLE_MAX_NUM_INSTANCES', 'VGT_DETECT_ONE', + 'VGT_DETECT_ZERO', 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', + 'VGT_DI_MAJOR_MODE_SELECT', 'VGT_DI_PRIM_TYPE', + 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING', + 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE', + 'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', + 'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', + 'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM', + 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', + 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16', + 'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', + 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', + 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', + 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', + 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', + 'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT', + 'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE', + 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', + 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', + 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', + 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', + 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', + 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', + 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', + 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', + 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', + 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', + 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', + 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', + 'VMEMCMD_RETURN_IN_ORDER', 'VMEMCMD_RETURN_IN_ORDER_READ', + 'VMEMCMD_RETURN_ORDER', 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', + 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VM_GROUP_SIZE', + 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B', + 'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B', + 'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_1024KB', 'VM_PG_SIZE_128KB', + 'VM_PG_SIZE_16KB', 'VM_PG_SIZE_2048KB', 'VM_PG_SIZE_256KB', + 'VM_PG_SIZE_32KB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_512KB', + 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_8KB', 'VPE_HWID', 'VPE_HWIP', + 'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ', + 'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL', + 'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC', + 'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA', + 'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2', + 'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2', + 'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA', + 'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4', + 'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA', + 'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1', + 'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3', + 'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK', + 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', + 'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0', + 'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', + 'VS_STAGE_COPY_SHADER', 'VS_STAGE_DS', 'VS_STAGE_REAL', + 'VTG_SEL_0', 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', + 'VTG_SEL_5', 'WAFLC_HWID', 'WAIT_SYNC', 'WATERMARK_MODE', + 'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', + 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', + 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', + 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', + 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', + 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', + 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', + 'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WritePolicy', 'XCD0_NODEID', + 'XCD1_NODEID', 'XCD2_NODEID', 'XCD3_NODEID', 'XCD4_NODEID', + 'XCD5_NODEID', 'XCD6_NODEID', 'XCD7_NODEID', 'XDMA_HWID', + 'XGBE_HWID', 'XGMI_HWID', 'XGMI_HWIP', 'XNORM', 'XNORM_A', + 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL', + 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', + 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', + 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', + 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', + 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', + 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', + 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', + 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', + 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', + 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', + 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT', + 'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT', + 'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder', + 'ZPASS_DISABLE', 'ZPASS_PIXELS', 'ZPASS_SAMPLES', + 'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', + 'ZpassControl', '_DISCOVERY_H_', '_PSP_TEE_GFX_IF_H_', + '__AMDGPU_IRQ_H__', '__AMDGPU_PSP_H__', '__AMDGPU_UCODE_H__', + '__AMDGPU_VM_H__', '__SOC15_IH_CLIENTID_H__', + '_soc21_ENUM_HEADER', 'amd_hw_ip_block_type', + 'amdgpu_firmware_load_type', 'amdgpu_interrupt_state', + 'amdgpu_vm_level', 'binary_header', 'bool', 'c__EA_table', + 'die_header', 'die_info', 'ge1_assembler_busy', + 'ge1_assembler_dma_starved', 'ge1_assembler_stalled', + 'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1', + 'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4', + 'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7', + 'ge1_dma_return_cl0', 'ge1_dma_return_cl1', + 'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1', + 'ge1_dma_utcl1_consecutive_retry_event', + 'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event', + 'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event', + 'ge1_dma_utcl1_translation_hit_event', + 'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1', + 'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit', + 'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1', + 'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1', + 'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1', + 'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1', + 'ge1_sclk_input_vld', 'ge1_sclk_reg_vld', + 'ge1_small_draws_one_instance', 'ge1_stat_busy', + 'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws', + 'ge_agm_gcr_crd_stall', 'ge_agm_gcr_latency', 'ge_agm_gcr_req', + 'ge_agm_gcr_stall', 'ge_agm_gcr_tag_stall', 'ge_all_tf2', + 'ge_all_tf3', 'ge_all_tf4', 'ge_all_tf5', 'ge_all_tf6', + 'ge_all_tf_eq', 'ge_csb_spi_bp', 'ge_dist_distributer_busy', + 'ge_dist_hs_done', 'ge_dist_hs_done_latency', + 'ge_dist_hs_done_latency_se0', 'ge_dist_hs_done_latency_se1', + 'ge_dist_hs_done_latency_se2', 'ge_dist_hs_done_latency_se3', + 'ge_dist_hs_done_latency_se4', 'ge_dist_hs_done_latency_se5', + 'ge_dist_hs_done_latency_se6', 'ge_dist_hs_done_latency_se7', + 'ge_dist_hs_done_se0', 'ge_dist_hs_done_se1', + 'ge_dist_hs_done_se2', 'ge_dist_hs_done_se3', + 'ge_dist_hs_done_se4', 'ge_dist_hs_done_se5', + 'ge_dist_hs_done_se6', 'ge_dist_hs_done_se7', + 'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1', + 'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3', + 'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5', + 'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7', + 'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch', + 'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full', + 'ge_dist_pc_ge_manager_busy', 'ge_dist_pc_req_stall_se0', + 'ge_dist_pc_req_stall_se1', 'ge_dist_pc_req_stall_se2', + 'ge_dist_pc_req_stall_se3', 'ge_dist_pc_req_stall_se4', + 'ge_dist_pc_req_stall_se5', 'ge_dist_pc_req_stall_se6', + 'ge_dist_pc_req_stall_se7', 'ge_dist_pc_space_zero', + 'ge_dist_reserved', 'ge_dist_sclk_core_vld', + 'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld', + 'ge_dist_switch_mode_stall', 'ge_dist_te11_starved', + 'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1', + 'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3', + 'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5', + 'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7', + 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 'ge_dist_tfreq_utcl1_request_event', + 'ge_dist_tfreq_utcl1_retry_event', + 'ge_dist_tfreq_utcl1_stall_event', + 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 'ge_dist_tfreq_utcl1_translation_hit_event', + 'ge_dist_tfreq_utcl1_translation_miss_event', + 'ge_dist_vs_pc_stall', 'ge_dist_wd_te11_busy', 'ge_distclk_vld', + 'ge_esvert_send', 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send', + 'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled', + 'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall', + 'ge_ngg_agm_req_stall', 'ge_ngg_attr_discard_alloc', + 'ge_ngg_attr_grp_alloc', 'ge_ngg_attr_grp_latency', + 'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall', + 'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit', + 'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov', + 'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on', + 'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work', + 'ge_ngg_starved_idle', 'ge_ngg_starving_for_pc_grant', + 'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches', + 'ge_num_of_hs_alloc_events', 'ge_num_of_no_dist_patches', + 'ge_num_of_patch_dist_patches', + 'ge_num_of_se_switches_due_to_donut', + 'ge_num_of_se_switches_due_to_patch_accum', + 'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop', + 'ge_pa1_csb_eop', 'ge_se0_te11_starved_on_hs_done', + 'ge_se1_te11_starved_on_hs_done', + 'ge_se2_te11_starved_on_hs_done', + 'ge_se3_te11_starved_on_hs_done', + 'ge_se4_te11_starved_on_hs_done', + 'ge_se5_te11_starved_on_hs_done', + 'ge_se6_te11_starved_on_hs_done', + 'ge_se7_te11_starved_on_hs_done', 'ge_se_ds_prims', + 'ge_se_es_thread_groups', 'ge_se_esvert_stalled_gsprim', + 'ge_se_hs_input_stall', 'ge_se_hs_tfm_stall', + 'ge_se_hs_tgs_active_high_water_mark', 'ge_se_hs_thread_groups', + 'ge_se_reused_es_indices', 'ge_se_sclk_input_vld', + 'ge_se_sclk_ngg_vld', 'ge_se_sclk_te11_vld', + 'ge_se_sending_vert_or_prim', 'ge_se_spi_esvert_eov', + 'ge_se_spi_esvert_stalled', 'ge_se_spi_esvert_starved_busy', + 'ge_se_spi_esvert_valid', 'ge_se_spi_gsprim_cont', + 'ge_se_spi_gsprim_eov', 'ge_se_spi_gsprim_stalled', + 'ge_se_spi_gsprim_starved_busy', 'ge_se_spi_gsprim_valid', + 'ge_se_spi_gssubgrp_event_window_active', + 'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send', + 'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall', + 'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy', + 'ge_se_spi_hsvert_valid', 'ge_se_spi_hswave_is_event', + 'ge_se_spi_hswave_send', 'ge_se_spi_lsvert_eov', + 'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy', + 'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall', + 'ge_spi_gsgrp_valid', 'ge_spi_hsgrp_spi_stall', + 'ge_spi_hswave_fifo_full_stall', 'ge_spi_lswave_fifo_full_stall', + 'ge_te11_compactor_starved', 'ge_te11_con_stall', + 'ge_te11_stall_prim_funnel', 'ge_te11_stall_vert_funnel', + 'ge_tf_ret_data_stalling_hs_done', 'harvest_info', + 'harvest_info_header', 'harvest_table', 'hw_id_map', 'int16_t', + 'int32_t', 'int8_t', 'interrupt_node_id_per_aid', 'ip', + 'ip_discovery_header', 'ip_structure', 'ip_v3', 'ip_v4', + 'psp_bootloader_cmd', 'psp_fw_type', 'psp_gfx_boot_config', + 'psp_gfx_boot_config_cmd', 'psp_gfx_cmd_id', + 'psp_gfx_crtl_cmd_id', 'psp_gfx_fw_type', + 'psp_memory_training_init_flag', 'psp_memory_training_ops', + 'psp_reg_prog_id', 'psp_ring_type', + 'psp_runtime_boot_cfg_feature', 'psp_runtime_entry_type', + 'psp_runtime_scpm_authentication', 'psp_shared_mem_size', + 'soc15_ih_clientid', 'soc15_ih_clientid_name', + 'soc21_ih_clientid', 'struct__fuse_data_bits', + 'struct_amdgpu_device', 'struct_amdgpu_firmware_info', + 'struct_amdgpu_iv_entry', 'struct_binary_header', + 'struct_common_firmware_header', 'struct_die', + 'struct_die_header', 'struct_die_info', + 'struct_dmcu_firmware_header_v1_0', + 'struct_dmcub_firmware_header_v1_0', 'struct_firmware', + 'struct_gc_info_v1_0', 'struct_gc_info_v1_1', + 'struct_gc_info_v1_2', 'struct_gc_info_v2_0', + 'struct_gc_info_v2_1', 'struct_gfx_firmware_header_v1_0', + 'struct_gfx_firmware_header_v2_0', + 'struct_gpu_info_firmware_header_v1_0', + 'struct_gpu_info_firmware_v1_0', 'struct_gpu_info_firmware_v1_1', + 'struct_gpu_info_header', 'struct_harvest_info', + 'struct_harvest_info_header', 'struct_harvest_table', + 'struct_imu_firmware_header_v1_0', 'struct_ip', + 'struct_ip_discovery_header', 'struct_ip_discovery_header_0_0', + 'struct_ip_structure', 'struct_ip_v3', 'struct_ip_v4', + 'struct_mall_info_header', 'struct_mall_info_v1_0', + 'struct_mall_info_v2_0', 'struct_mc_firmware_header_v1_0', + 'struct_mes_firmware_header_v1_0', 'struct_nps_info_header', + 'struct_nps_info_v1_0', 'struct_nps_instance_info_v1_0', + 'struct_psp_bin_desc', 'struct_psp_context', + 'struct_psp_firmware_header_v1_0', + 'struct_psp_firmware_header_v1_1', + 'struct_psp_firmware_header_v1_2', + 'struct_psp_firmware_header_v1_3', + 'struct_psp_firmware_header_v2_0', + 'struct_psp_firmware_header_v2_1', 'struct_psp_fw_bin_desc', + 'struct_psp_fw_legacy_bin_desc', 'struct_psp_gfx_buf_desc', + 'struct_psp_gfx_buf_list', 'struct_psp_gfx_cmd_boot_cfg', + 'struct_psp_gfx_cmd_invoke_cmd', 'struct_psp_gfx_cmd_load_ip_fw', + 'struct_psp_gfx_cmd_load_ta', 'struct_psp_gfx_cmd_load_toc', + 'struct_psp_gfx_cmd_reg_prog', 'struct_psp_gfx_cmd_resp', + 'struct_psp_gfx_cmd_save_restore_ip_fw', + 'struct_psp_gfx_cmd_setup_tmr', + 'struct_psp_gfx_cmd_setup_tmr_0_bitfield', + 'struct_psp_gfx_cmd_sriov_spatial_part', + 'struct_psp_gfx_cmd_unload_ta', 'struct_psp_gfx_ctrl', + 'struct_psp_gfx_rb_frame', 'struct_psp_gfx_resp', + 'struct_psp_gfx_uresp_bootcfg', + 'struct_psp_gfx_uresp_fwar_db_info', + 'struct_psp_gfx_uresp_reserved', 'struct_psp_xgmi_node_info', + 'struct_psp_xgmi_topology_info', + 'struct_rlc_firmware_header_v1_0', + 'struct_rlc_firmware_header_v2_0', + 'struct_rlc_firmware_header_v2_1', + 'struct_rlc_firmware_header_v2_2', + 'struct_rlc_firmware_header_v2_3', + 'struct_rlc_firmware_header_v2_4', + 'struct_sdma_firmware_header_v1_0', + 'struct_sdma_firmware_header_v1_1', + 'struct_sdma_firmware_header_v2_0', + 'struct_sdma_firmware_header_v3_0', + 'struct_smc_firmware_header_v1_0', + 'struct_smc_firmware_header_v2_0', + 'struct_smc_firmware_header_v2_1', + 'struct_smc_soft_pptable_entry', 'struct_ta_firmware_header_v1_0', + 'struct_ta_firmware_header_v2_0', 'struct_table_info', + 'struct_umsch_mm_firmware_header_v1_0', 'struct_v11_compute_mqd', + 'struct_v11_gfx_mqd', 'struct_v11_sdma_mqd', + 'struct_vcn_info_header', 'struct_vcn_info_v1_0', + 'struct_vcn_instance_info_v1_0', + 'struct_vpe_firmware_header_v1_0', 'ta_fw_type', 'ta_type_id', + 'table', 'table__enumvalues', 'table_info', 'tee_error_code', + 'u16', 'u32', 'u64', 'u8', 'uint16_t', 'uint32_t', 'uint64_t', + 'uint8_t', 'union__fuse_data', 'union_amdgpu_firmware_header', + 'union_die_0', 'union_ip_discovery_header_0', + 'union_psp_gfx_cmd_setup_tmr_0', 'union_psp_gfx_commands', + 'union_psp_gfx_uresp'] diff --git a/tinygrad/runtime/autogen/am/gc_11_0_0.py b/tinygrad/runtime/autogen/am/gc_11_0_0.py new file mode 100644 index 0000000000..5c8273df5a --- /dev/null +++ b/tinygrad/runtime/autogen/am/gc_11_0_0.py @@ -0,0 +1,88935 @@ +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_gc_11_0_0_OFFSET_HEADER = True # macro +regSDMA0_DEC_START = 0x0000 # macro +regSDMA0_DEC_START_BASE_IDX = 0 # macro +regSDMA0_F32_MISC_CNTL = 0x000b # macro +regSDMA0_F32_MISC_CNTL_BASE_IDX = 0 # macro +regSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro +regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro +regSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro +regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro +regSDMA0_POWER_CNTL = 0x001a # macro +regSDMA0_POWER_CNTL_BASE_IDX = 0 # macro +regSDMA0_CNTL = 0x001c # macro +regSDMA0_CNTL_BASE_IDX = 0 # macro +regSDMA0_CHICKEN_BITS = 0x001d # macro +regSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro +regSDMA0_GB_ADDR_CONFIG = 0x001e # macro +regSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro +regSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro +regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro +regSDMA0_RB_RPTR_FETCH = 0x0020 # macro +regSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro +regSDMA0_RB_RPTR_FETCH_HI = 0x0021 # macro +regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro +regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0022 # macro +regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro +regSDMA0_IB_OFFSET_FETCH = 0x0023 # macro +regSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro +regSDMA0_PROGRAM = 0x0024 # macro +regSDMA0_PROGRAM_BASE_IDX = 0 # macro +regSDMA0_STATUS_REG = 0x0025 # macro +regSDMA0_STATUS_REG_BASE_IDX = 0 # macro +regSDMA0_STATUS1_REG = 0x0026 # macro +regSDMA0_STATUS1_REG_BASE_IDX = 0 # macro +regSDMA0_CNTL1 = 0x0027 # macro +regSDMA0_CNTL1_BASE_IDX = 0 # macro +regSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro +regSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro +regSDMA0_UCODE_CHECKSUM = 0x0029 # macro +regSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro +regSDMA0_FREEZE = 0x002b # macro +regSDMA0_FREEZE_BASE_IDX = 0 # macro +regSDMA0_PROCESS_QUANTUM0 = 0x002c # macro +regSDMA0_PROCESS_QUANTUM0_BASE_IDX = 0 # macro +regSDMA0_PROCESS_QUANTUM1 = 0x002d # macro +regSDMA0_PROCESS_QUANTUM1_BASE_IDX = 0 # macro +regSDMA0_WATCHDOG_CNTL = 0x002e # macro +regSDMA0_WATCHDOG_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE_STATUS0 = 0x002f # macro +regSDMA0_QUEUE_STATUS0_BASE_IDX = 0 # macro +regSDMA0_EDC_CONFIG = 0x0032 # macro +regSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro +regSDMA0_BA_THRESHOLD = 0x0033 # macro +regSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro +regSDMA0_ID = 0x0034 # macro +regSDMA0_ID_BASE_IDX = 0 # macro +regSDMA0_VERSION = 0x0035 # macro +regSDMA0_VERSION_BASE_IDX = 0 # macro +regSDMA0_EDC_COUNTER = 0x0036 # macro +regSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro +regSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro +regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro +regSDMA0_STATUS2_REG = 0x0038 # macro +regSDMA0_STATUS2_REG_BASE_IDX = 0 # macro +regSDMA0_ATOMIC_CNTL = 0x0039 # macro +regSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro +regSDMA0_ATOMIC_PREOP_LO = 0x003a # macro +regSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro +regSDMA0_ATOMIC_PREOP_HI = 0x003b # macro +regSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro +regSDMA0_UTCL1_CNTL = 0x003c # macro +regSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro +regSDMA0_UTCL1_WATERMK = 0x003d # macro +regSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro +regSDMA0_UTCL1_TIMEOUT = 0x003e # macro +regSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro +regSDMA0_UTCL1_PAGE = 0x003f # macro +regSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro +regSDMA0_UTCL1_RD_STATUS = 0x0040 # macro +regSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro +regSDMA0_UTCL1_WR_STATUS = 0x0041 # macro +regSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro +regSDMA0_UTCL1_INV0 = 0x0042 # macro +regSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro +regSDMA0_UTCL1_INV1 = 0x0043 # macro +regSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro +regSDMA0_UTCL1_INV2 = 0x0044 # macro +regSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro +regSDMA0_UTCL1_RD_XNACK0 = 0x0045 # macro +regSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro +regSDMA0_UTCL1_RD_XNACK1 = 0x0046 # macro +regSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro +regSDMA0_UTCL1_WR_XNACK0 = 0x0047 # macro +regSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro +regSDMA0_UTCL1_WR_XNACK1 = 0x0048 # macro +regSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro +regSDMA0_RELAX_ORDERING_LUT = 0x004a # macro +regSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro +regSDMA0_CHICKEN_BITS_2 = 0x004b # macro +regSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro +regSDMA0_STATUS3_REG = 0x004c # macro +regSDMA0_STATUS3_REG_BASE_IDX = 0 # macro +regSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro +regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro +regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_GLOBAL_QUANTUM = 0x004f # macro +regSDMA0_GLOBAL_QUANTUM_BASE_IDX = 0 # macro +regSDMA0_ERROR_LOG = 0x0050 # macro +regSDMA0_ERROR_LOG_BASE_IDX = 0 # macro +regSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro +regSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro +regSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro +regSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro +regSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro +regSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro +regSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro +regSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro +regSDMA0_F32_COUNTER = 0x0055 # macro +regSDMA0_F32_COUNTER_BASE_IDX = 0 # macro +regSDMA0_CRD_CNTL = 0x005b # macro +regSDMA0_CRD_CNTL_BASE_IDX = 0 # macro +regSDMA0_RLC_CGCG_CTRL = 0x005c # macro +regSDMA0_RLC_CGCG_CTRL_BASE_IDX = 0 # macro +regSDMA0_AQL_STATUS = 0x005f # macro +regSDMA0_AQL_STATUS_BASE_IDX = 0 # macro +regSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro +regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro +regSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro +regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro +regSDMA0_TLBI_GCR_CNTL = 0x0062 # macro +regSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro +regSDMA0_TILING_CONFIG = 0x0063 # macro +regSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro +regSDMA0_INT_STATUS = 0x0070 # macro +regSDMA0_INT_STATUS_BASE_IDX = 0 # macro +regSDMA0_HOLE_ADDR_LO = 0x0072 # macro +regSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_HOLE_ADDR_HI = 0x0073 # macro +regSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_CLOCK_GATING_STATUS = 0x0075 # macro +regSDMA0_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro +regSDMA0_STATUS4_REG = 0x0076 # macro +regSDMA0_STATUS4_REG_BASE_IDX = 0 # macro +regSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro +regSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro +regSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro +regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro +regSDMA0_TIMESTAMP_CNTL = 0x0079 # macro +regSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro +regSDMA0_STATUS5_REG = 0x007a # macro +regSDMA0_STATUS5_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE_RESET_REQ = 0x007b # macro +regSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro +regSDMA0_STATUS6_REG = 0x007c # macro +regSDMA0_STATUS6_REG_BASE_IDX = 0 # macro +regSDMA0_UCODE1_CHECKSUM = 0x007d # macro +regSDMA0_UCODE1_CHECKSUM_BASE_IDX = 0 # macro +regSDMA0_CE_CTRL = 0x007e # macro +regSDMA0_CE_CTRL_BASE_IDX = 0 # macro +regSDMA0_FED_STATUS = 0x007f # macro +regSDMA0_FED_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_CNTL = 0x0080 # macro +regSDMA0_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_BASE = 0x0081 # macro +regSDMA0_QUEUE0_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_BASE_HI = 0x0082 # macro +regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_RPTR = 0x0083 # macro +regSDMA0_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_RPTR_HI = 0x0084 # macro +regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_WPTR = 0x0085 # macro +regSDMA0_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_WPTR_HI = 0x0086 # macro +regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_RPTR_ADDR_HI = 0x0088 # macro +regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_RPTR_ADDR_LO = 0x0089 # macro +regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_IB_CNTL = 0x008a # macro +regSDMA0_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_IB_RPTR = 0x008b # macro +regSDMA0_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_IB_OFFSET = 0x008c # macro +regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_IB_BASE_LO = 0x008d # macro +regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_IB_BASE_HI = 0x008e # macro +regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_IB_SIZE = 0x008f # macro +regSDMA0_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_SKIP_CNTL = 0x0090 # macro +regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_CONTEXT_STATUS = 0x0091 # macro +regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_DOORBELL = 0x0092 # macro +regSDMA0_QUEUE0_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_DOORBELL_LOG = 0x00a9 # macro +regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_DOORBELL_OFFSET = 0x00ab # macro +regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_CSA_ADDR_LO = 0x00ac # macro +regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_CSA_ADDR_HI = 0x00ad # macro +regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_SCHEDULE_CNTL = 0x00ae # macro +regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_IB_SUB_REMAIN = 0x00af # macro +regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_PREEMPT = 0x00b0 # macro +regSDMA0_QUEUE0_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_DUMMY_REG = 0x00b1 # macro +regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_AQL_CNTL = 0x00b4 # macro +regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MINOR_PTR_UPDATE = 0x00b5 # macro +regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_RB_PREEMPT = 0x00b6 # macro +regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA0 = 0x00c0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA1 = 0x00c1 # macro +regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA2 = 0x00c2 # macro +regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA3 = 0x00c3 # macro +regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA4 = 0x00c4 # macro +regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA5 = 0x00c5 # macro +regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA6 = 0x00c6 # macro +regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA7 = 0x00c7 # macro +regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA8 = 0x00c8 # macro +regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA9 = 0x00c9 # macro +regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_DATA10 = 0x00ca # macro +regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE0_MIDCMD_CNTL = 0x00cb # macro +regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_CNTL = 0x00d8 # macro +regSDMA0_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_BASE = 0x00d9 # macro +regSDMA0_QUEUE1_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_BASE_HI = 0x00da # macro +regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_RPTR = 0x00db # macro +regSDMA0_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_RPTR_HI = 0x00dc # macro +regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_WPTR = 0x00dd # macro +regSDMA0_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_WPTR_HI = 0x00de # macro +regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_RPTR_ADDR_HI = 0x00e0 # macro +regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_RPTR_ADDR_LO = 0x00e1 # macro +regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_IB_CNTL = 0x00e2 # macro +regSDMA0_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_IB_RPTR = 0x00e3 # macro +regSDMA0_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_IB_OFFSET = 0x00e4 # macro +regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_IB_BASE_LO = 0x00e5 # macro +regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_IB_BASE_HI = 0x00e6 # macro +regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_IB_SIZE = 0x00e7 # macro +regSDMA0_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_SKIP_CNTL = 0x00e8 # macro +regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_CONTEXT_STATUS = 0x00e9 # macro +regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_DOORBELL = 0x00ea # macro +regSDMA0_QUEUE1_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_DOORBELL_LOG = 0x0101 # macro +regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_DOORBELL_OFFSET = 0x0103 # macro +regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_CSA_ADDR_LO = 0x0104 # macro +regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_CSA_ADDR_HI = 0x0105 # macro +regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_SCHEDULE_CNTL = 0x0106 # macro +regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_IB_SUB_REMAIN = 0x0107 # macro +regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_PREEMPT = 0x0108 # macro +regSDMA0_QUEUE1_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_DUMMY_REG = 0x0109 # macro +regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x010a # macro +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x010b # macro +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_AQL_CNTL = 0x010c # macro +regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MINOR_PTR_UPDATE = 0x010d # macro +regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_RB_PREEMPT = 0x010e # macro +regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA0 = 0x0118 # macro +regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA1 = 0x0119 # macro +regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA2 = 0x011a # macro +regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA3 = 0x011b # macro +regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA4 = 0x011c # macro +regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA5 = 0x011d # macro +regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA6 = 0x011e # macro +regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA7 = 0x011f # macro +regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA8 = 0x0120 # macro +regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA9 = 0x0121 # macro +regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_DATA10 = 0x0122 # macro +regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE1_MIDCMD_CNTL = 0x0123 # macro +regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_CNTL = 0x0130 # macro +regSDMA0_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_BASE = 0x0131 # macro +regSDMA0_QUEUE2_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_BASE_HI = 0x0132 # macro +regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_RPTR = 0x0133 # macro +regSDMA0_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_RPTR_HI = 0x0134 # macro +regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_WPTR = 0x0135 # macro +regSDMA0_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_WPTR_HI = 0x0136 # macro +regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_RPTR_ADDR_HI = 0x0138 # macro +regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_RPTR_ADDR_LO = 0x0139 # macro +regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_IB_CNTL = 0x013a # macro +regSDMA0_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_IB_RPTR = 0x013b # macro +regSDMA0_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_IB_OFFSET = 0x013c # macro +regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_IB_BASE_LO = 0x013d # macro +regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_IB_BASE_HI = 0x013e # macro +regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_IB_SIZE = 0x013f # macro +regSDMA0_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_SKIP_CNTL = 0x0140 # macro +regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_CONTEXT_STATUS = 0x0141 # macro +regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_DOORBELL = 0x0142 # macro +regSDMA0_QUEUE2_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_DOORBELL_LOG = 0x0159 # macro +regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_DOORBELL_OFFSET = 0x015b # macro +regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_CSA_ADDR_LO = 0x015c # macro +regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_CSA_ADDR_HI = 0x015d # macro +regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_SCHEDULE_CNTL = 0x015e # macro +regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_IB_SUB_REMAIN = 0x015f # macro +regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_PREEMPT = 0x0160 # macro +regSDMA0_QUEUE2_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_DUMMY_REG = 0x0161 # macro +regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_AQL_CNTL = 0x0164 # macro +regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MINOR_PTR_UPDATE = 0x0165 # macro +regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_RB_PREEMPT = 0x0166 # macro +regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA0 = 0x0170 # macro +regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA1 = 0x0171 # macro +regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA2 = 0x0172 # macro +regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA3 = 0x0173 # macro +regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA4 = 0x0174 # macro +regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA5 = 0x0175 # macro +regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA6 = 0x0176 # macro +regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA7 = 0x0177 # macro +regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA8 = 0x0178 # macro +regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA9 = 0x0179 # macro +regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_DATA10 = 0x017a # macro +regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE2_MIDCMD_CNTL = 0x017b # macro +regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_CNTL = 0x0188 # macro +regSDMA0_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_BASE = 0x0189 # macro +regSDMA0_QUEUE3_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_BASE_HI = 0x018a # macro +regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_RPTR = 0x018b # macro +regSDMA0_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_RPTR_HI = 0x018c # macro +regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_WPTR = 0x018d # macro +regSDMA0_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_WPTR_HI = 0x018e # macro +regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_RPTR_ADDR_HI = 0x0190 # macro +regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_RPTR_ADDR_LO = 0x0191 # macro +regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_IB_CNTL = 0x0192 # macro +regSDMA0_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_IB_RPTR = 0x0193 # macro +regSDMA0_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_IB_OFFSET = 0x0194 # macro +regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_IB_BASE_LO = 0x0195 # macro +regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_IB_BASE_HI = 0x0196 # macro +regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_IB_SIZE = 0x0197 # macro +regSDMA0_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_SKIP_CNTL = 0x0198 # macro +regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_CONTEXT_STATUS = 0x0199 # macro +regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_DOORBELL = 0x019a # macro +regSDMA0_QUEUE3_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_DOORBELL_LOG = 0x01b1 # macro +regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_DOORBELL_OFFSET = 0x01b3 # macro +regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_CSA_ADDR_LO = 0x01b4 # macro +regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_CSA_ADDR_HI = 0x01b5 # macro +regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_SCHEDULE_CNTL = 0x01b6 # macro +regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_IB_SUB_REMAIN = 0x01b7 # macro +regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_PREEMPT = 0x01b8 # macro +regSDMA0_QUEUE3_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_DUMMY_REG = 0x01b9 # macro +regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_AQL_CNTL = 0x01bc # macro +regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MINOR_PTR_UPDATE = 0x01bd # macro +regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_RB_PREEMPT = 0x01be # macro +regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA0 = 0x01c8 # macro +regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA1 = 0x01c9 # macro +regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA2 = 0x01ca # macro +regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA3 = 0x01cb # macro +regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA4 = 0x01cc # macro +regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA5 = 0x01cd # macro +regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA6 = 0x01ce # macro +regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA7 = 0x01cf # macro +regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA8 = 0x01d0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA9 = 0x01d1 # macro +regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_DATA10 = 0x01d2 # macro +regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE3_MIDCMD_CNTL = 0x01d3 # macro +regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_CNTL = 0x01e0 # macro +regSDMA0_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_BASE = 0x01e1 # macro +regSDMA0_QUEUE4_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_BASE_HI = 0x01e2 # macro +regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_RPTR = 0x01e3 # macro +regSDMA0_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_RPTR_HI = 0x01e4 # macro +regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_WPTR = 0x01e5 # macro +regSDMA0_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_WPTR_HI = 0x01e6 # macro +regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_RPTR_ADDR_HI = 0x01e8 # macro +regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_RPTR_ADDR_LO = 0x01e9 # macro +regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_IB_CNTL = 0x01ea # macro +regSDMA0_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_IB_RPTR = 0x01eb # macro +regSDMA0_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_IB_OFFSET = 0x01ec # macro +regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_IB_BASE_LO = 0x01ed # macro +regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_IB_BASE_HI = 0x01ee # macro +regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_IB_SIZE = 0x01ef # macro +regSDMA0_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_SKIP_CNTL = 0x01f0 # macro +regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_CONTEXT_STATUS = 0x01f1 # macro +regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_DOORBELL = 0x01f2 # macro +regSDMA0_QUEUE4_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_DOORBELL_LOG = 0x0209 # macro +regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_DOORBELL_OFFSET = 0x020b # macro +regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_CSA_ADDR_LO = 0x020c # macro +regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_CSA_ADDR_HI = 0x020d # macro +regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_SCHEDULE_CNTL = 0x020e # macro +regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_IB_SUB_REMAIN = 0x020f # macro +regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_PREEMPT = 0x0210 # macro +regSDMA0_QUEUE4_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_DUMMY_REG = 0x0211 # macro +regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_AQL_CNTL = 0x0214 # macro +regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MINOR_PTR_UPDATE = 0x0215 # macro +regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_RB_PREEMPT = 0x0216 # macro +regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA0 = 0x0220 # macro +regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA1 = 0x0221 # macro +regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA2 = 0x0222 # macro +regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA3 = 0x0223 # macro +regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA4 = 0x0224 # macro +regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA5 = 0x0225 # macro +regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA6 = 0x0226 # macro +regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA7 = 0x0227 # macro +regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA8 = 0x0228 # macro +regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA9 = 0x0229 # macro +regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_DATA10 = 0x022a # macro +regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE4_MIDCMD_CNTL = 0x022b # macro +regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_CNTL = 0x0238 # macro +regSDMA0_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_BASE = 0x0239 # macro +regSDMA0_QUEUE5_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_BASE_HI = 0x023a # macro +regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_RPTR = 0x023b # macro +regSDMA0_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_RPTR_HI = 0x023c # macro +regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_WPTR = 0x023d # macro +regSDMA0_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_WPTR_HI = 0x023e # macro +regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_RPTR_ADDR_HI = 0x0240 # macro +regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_RPTR_ADDR_LO = 0x0241 # macro +regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_IB_CNTL = 0x0242 # macro +regSDMA0_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_IB_RPTR = 0x0243 # macro +regSDMA0_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_IB_OFFSET = 0x0244 # macro +regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_IB_BASE_LO = 0x0245 # macro +regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_IB_BASE_HI = 0x0246 # macro +regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_IB_SIZE = 0x0247 # macro +regSDMA0_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_SKIP_CNTL = 0x0248 # macro +regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_CONTEXT_STATUS = 0x0249 # macro +regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_DOORBELL = 0x024a # macro +regSDMA0_QUEUE5_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_DOORBELL_LOG = 0x0261 # macro +regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_DOORBELL_OFFSET = 0x0263 # macro +regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_CSA_ADDR_LO = 0x0264 # macro +regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_CSA_ADDR_HI = 0x0265 # macro +regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_SCHEDULE_CNTL = 0x0266 # macro +regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_IB_SUB_REMAIN = 0x0267 # macro +regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_PREEMPT = 0x0268 # macro +regSDMA0_QUEUE5_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_DUMMY_REG = 0x0269 # macro +regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x026a # macro +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x026b # macro +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_AQL_CNTL = 0x026c # macro +regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MINOR_PTR_UPDATE = 0x026d # macro +regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_RB_PREEMPT = 0x026e # macro +regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA0 = 0x0278 # macro +regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA1 = 0x0279 # macro +regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA2 = 0x027a # macro +regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA3 = 0x027b # macro +regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA4 = 0x027c # macro +regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA5 = 0x027d # macro +regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA6 = 0x027e # macro +regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA7 = 0x027f # macro +regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA8 = 0x0280 # macro +regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA9 = 0x0281 # macro +regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_DATA10 = 0x0282 # macro +regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE5_MIDCMD_CNTL = 0x0283 # macro +regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_CNTL = 0x0290 # macro +regSDMA0_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_BASE = 0x0291 # macro +regSDMA0_QUEUE6_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_BASE_HI = 0x0292 # macro +regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_RPTR = 0x0293 # macro +regSDMA0_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_RPTR_HI = 0x0294 # macro +regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_WPTR = 0x0295 # macro +regSDMA0_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_WPTR_HI = 0x0296 # macro +regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_RPTR_ADDR_HI = 0x0298 # macro +regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_RPTR_ADDR_LO = 0x0299 # macro +regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_IB_CNTL = 0x029a # macro +regSDMA0_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_IB_RPTR = 0x029b # macro +regSDMA0_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_IB_OFFSET = 0x029c # macro +regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_IB_BASE_LO = 0x029d # macro +regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_IB_BASE_HI = 0x029e # macro +regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_IB_SIZE = 0x029f # macro +regSDMA0_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_SKIP_CNTL = 0x02a0 # macro +regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_CONTEXT_STATUS = 0x02a1 # macro +regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_DOORBELL = 0x02a2 # macro +regSDMA0_QUEUE6_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_DOORBELL_LOG = 0x02b9 # macro +regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_DOORBELL_OFFSET = 0x02bb # macro +regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_CSA_ADDR_LO = 0x02bc # macro +regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_CSA_ADDR_HI = 0x02bd # macro +regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_SCHEDULE_CNTL = 0x02be # macro +regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_IB_SUB_REMAIN = 0x02bf # macro +regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_PREEMPT = 0x02c0 # macro +regSDMA0_QUEUE6_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_DUMMY_REG = 0x02c1 # macro +regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_AQL_CNTL = 0x02c4 # macro +regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MINOR_PTR_UPDATE = 0x02c5 # macro +regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_RB_PREEMPT = 0x02c6 # macro +regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA0 = 0x02d0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA1 = 0x02d1 # macro +regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA2 = 0x02d2 # macro +regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA3 = 0x02d3 # macro +regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA4 = 0x02d4 # macro +regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA5 = 0x02d5 # macro +regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA6 = 0x02d6 # macro +regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA7 = 0x02d7 # macro +regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA8 = 0x02d8 # macro +regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA9 = 0x02d9 # macro +regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_DATA10 = 0x02da # macro +regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE6_MIDCMD_CNTL = 0x02db # macro +regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_CNTL = 0x02e8 # macro +regSDMA0_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_BASE = 0x02e9 # macro +regSDMA0_QUEUE7_RB_BASE_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_BASE_HI = 0x02ea # macro +regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_RPTR = 0x02eb # macro +regSDMA0_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_RPTR_HI = 0x02ec # macro +regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_WPTR = 0x02ed # macro +regSDMA0_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_WPTR_HI = 0x02ee # macro +regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_RPTR_ADDR_HI = 0x02f0 # macro +regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_RPTR_ADDR_LO = 0x02f1 # macro +regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_IB_CNTL = 0x02f2 # macro +regSDMA0_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_IB_RPTR = 0x02f3 # macro +regSDMA0_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_IB_OFFSET = 0x02f4 # macro +regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_IB_BASE_LO = 0x02f5 # macro +regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_IB_BASE_HI = 0x02f6 # macro +regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_IB_SIZE = 0x02f7 # macro +regSDMA0_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_SKIP_CNTL = 0x02f8 # macro +regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_CONTEXT_STATUS = 0x02f9 # macro +regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_DOORBELL = 0x02fa # macro +regSDMA0_QUEUE7_DOORBELL_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_DOORBELL_LOG = 0x0311 # macro +regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_DOORBELL_OFFSET = 0x0313 # macro +regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_CSA_ADDR_LO = 0x0314 # macro +regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_CSA_ADDR_HI = 0x0315 # macro +regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_SCHEDULE_CNTL = 0x0316 # macro +regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_IB_SUB_REMAIN = 0x0317 # macro +regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_PREEMPT = 0x0318 # macro +regSDMA0_QUEUE7_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_DUMMY_REG = 0x0319 # macro +regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x031a # macro +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x031b # macro +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_AQL_CNTL = 0x031c # macro +regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MINOR_PTR_UPDATE = 0x031d # macro +regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_RB_PREEMPT = 0x031e # macro +regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA0 = 0x0328 # macro +regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA1 = 0x0329 # macro +regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA2 = 0x032a # macro +regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA3 = 0x032b # macro +regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA4 = 0x032c # macro +regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA5 = 0x032d # macro +regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA6 = 0x032e # macro +regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA7 = 0x032f # macro +regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA8 = 0x0330 # macro +regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA9 = 0x0331 # macro +regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_DATA10 = 0x0332 # macro +regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA0_QUEUE7_MIDCMD_CNTL = 0x0333 # macro +regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_DEC_START = 0x0600 # macro +regSDMA1_DEC_START_BASE_IDX = 0 # macro +regSDMA1_F32_MISC_CNTL = 0x060b # macro +regSDMA1_F32_MISC_CNTL_BASE_IDX = 0 # macro +regSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro +regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro +regSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro +regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro +regSDMA1_POWER_CNTL = 0x061a # macro +regSDMA1_POWER_CNTL_BASE_IDX = 0 # macro +regSDMA1_CNTL = 0x061c # macro +regSDMA1_CNTL_BASE_IDX = 0 # macro +regSDMA1_CHICKEN_BITS = 0x061d # macro +regSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro +regSDMA1_GB_ADDR_CONFIG = 0x061e # macro +regSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro +regSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro +regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro +regSDMA1_RB_RPTR_FETCH = 0x0620 # macro +regSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro +regSDMA1_RB_RPTR_FETCH_HI = 0x0621 # macro +regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro +regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0622 # macro +regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro +regSDMA1_IB_OFFSET_FETCH = 0x0623 # macro +regSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro +regSDMA1_PROGRAM = 0x0624 # macro +regSDMA1_PROGRAM_BASE_IDX = 0 # macro +regSDMA1_STATUS_REG = 0x0625 # macro +regSDMA1_STATUS_REG_BASE_IDX = 0 # macro +regSDMA1_STATUS1_REG = 0x0626 # macro +regSDMA1_STATUS1_REG_BASE_IDX = 0 # macro +regSDMA1_CNTL1 = 0x0627 # macro +regSDMA1_CNTL1_BASE_IDX = 0 # macro +regSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro +regSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro +regSDMA1_UCODE_CHECKSUM = 0x0629 # macro +regSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro +regSDMA1_FREEZE = 0x062b # macro +regSDMA1_FREEZE_BASE_IDX = 0 # macro +regSDMA1_PROCESS_QUANTUM0 = 0x062c # macro +regSDMA1_PROCESS_QUANTUM0_BASE_IDX = 0 # macro +regSDMA1_PROCESS_QUANTUM1 = 0x062d # macro +regSDMA1_PROCESS_QUANTUM1_BASE_IDX = 0 # macro +regSDMA1_WATCHDOG_CNTL = 0x062e # macro +regSDMA1_WATCHDOG_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE_STATUS0 = 0x062f # macro +regSDMA1_QUEUE_STATUS0_BASE_IDX = 0 # macro +regSDMA1_EDC_CONFIG = 0x0632 # macro +regSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro +regSDMA1_BA_THRESHOLD = 0x0633 # macro +regSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro +regSDMA1_ID = 0x0634 # macro +regSDMA1_ID_BASE_IDX = 0 # macro +regSDMA1_VERSION = 0x0635 # macro +regSDMA1_VERSION_BASE_IDX = 0 # macro +regSDMA1_EDC_COUNTER = 0x0636 # macro +regSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro +regSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro +regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro +regSDMA1_STATUS2_REG = 0x0638 # macro +regSDMA1_STATUS2_REG_BASE_IDX = 0 # macro +regSDMA1_ATOMIC_CNTL = 0x0639 # macro +regSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro +regSDMA1_ATOMIC_PREOP_LO = 0x063a # macro +regSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro +regSDMA1_ATOMIC_PREOP_HI = 0x063b # macro +regSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro +regSDMA1_UTCL1_CNTL = 0x063c # macro +regSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro +regSDMA1_UTCL1_WATERMK = 0x063d # macro +regSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro +regSDMA1_UTCL1_TIMEOUT = 0x063e # macro +regSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro +regSDMA1_UTCL1_PAGE = 0x063f # macro +regSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro +regSDMA1_UTCL1_RD_STATUS = 0x0640 # macro +regSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro +regSDMA1_UTCL1_WR_STATUS = 0x0641 # macro +regSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro +regSDMA1_UTCL1_INV0 = 0x0642 # macro +regSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro +regSDMA1_UTCL1_INV1 = 0x0643 # macro +regSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro +regSDMA1_UTCL1_INV2 = 0x0644 # macro +regSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro +regSDMA1_UTCL1_RD_XNACK0 = 0x0645 # macro +regSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro +regSDMA1_UTCL1_RD_XNACK1 = 0x0646 # macro +regSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro +regSDMA1_UTCL1_WR_XNACK0 = 0x0647 # macro +regSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro +regSDMA1_UTCL1_WR_XNACK1 = 0x0648 # macro +regSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro +regSDMA1_RELAX_ORDERING_LUT = 0x064a # macro +regSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro +regSDMA1_CHICKEN_BITS_2 = 0x064b # macro +regSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro +regSDMA1_STATUS3_REG = 0x064c # macro +regSDMA1_STATUS3_REG_BASE_IDX = 0 # macro +regSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro +regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro +regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_GLOBAL_QUANTUM = 0x064f # macro +regSDMA1_GLOBAL_QUANTUM_BASE_IDX = 0 # macro +regSDMA1_ERROR_LOG = 0x0650 # macro +regSDMA1_ERROR_LOG_BASE_IDX = 0 # macro +regSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro +regSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro +regSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro +regSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro +regSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro +regSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro +regSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro +regSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro +regSDMA1_F32_COUNTER = 0x0655 # macro +regSDMA1_F32_COUNTER_BASE_IDX = 0 # macro +regSDMA1_CRD_CNTL = 0x065b # macro +regSDMA1_CRD_CNTL_BASE_IDX = 0 # macro +regSDMA1_RLC_CGCG_CTRL = 0x065c # macro +regSDMA1_RLC_CGCG_CTRL_BASE_IDX = 0 # macro +regSDMA1_AQL_STATUS = 0x065f # macro +regSDMA1_AQL_STATUS_BASE_IDX = 0 # macro +regSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro +regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro +regSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro +regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro +regSDMA1_TLBI_GCR_CNTL = 0x0662 # macro +regSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro +regSDMA1_TILING_CONFIG = 0x0663 # macro +regSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro +regSDMA1_INT_STATUS = 0x0670 # macro +regSDMA1_INT_STATUS_BASE_IDX = 0 # macro +regSDMA1_HOLE_ADDR_LO = 0x0672 # macro +regSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_HOLE_ADDR_HI = 0x0673 # macro +regSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_CLOCK_GATING_STATUS = 0x0675 # macro +regSDMA1_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro +regSDMA1_STATUS4_REG = 0x0676 # macro +regSDMA1_STATUS4_REG_BASE_IDX = 0 # macro +regSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro +regSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro +regSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro +regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro +regSDMA1_TIMESTAMP_CNTL = 0x0679 # macro +regSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro +regSDMA1_STATUS5_REG = 0x067a # macro +regSDMA1_STATUS5_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE_RESET_REQ = 0x067b # macro +regSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro +regSDMA1_STATUS6_REG = 0x067c # macro +regSDMA1_STATUS6_REG_BASE_IDX = 0 # macro +regSDMA1_UCODE1_CHECKSUM = 0x067d # macro +regSDMA1_UCODE1_CHECKSUM_BASE_IDX = 0 # macro +regSDMA1_CE_CTRL = 0x067e # macro +regSDMA1_CE_CTRL_BASE_IDX = 0 # macro +regSDMA1_FED_STATUS = 0x067f # macro +regSDMA1_FED_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_CNTL = 0x0680 # macro +regSDMA1_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_BASE = 0x0681 # macro +regSDMA1_QUEUE0_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_BASE_HI = 0x0682 # macro +regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_RPTR = 0x0683 # macro +regSDMA1_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_RPTR_HI = 0x0684 # macro +regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_WPTR = 0x0685 # macro +regSDMA1_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_WPTR_HI = 0x0686 # macro +regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_RPTR_ADDR_HI = 0x0688 # macro +regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_RPTR_ADDR_LO = 0x0689 # macro +regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_IB_CNTL = 0x068a # macro +regSDMA1_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_IB_RPTR = 0x068b # macro +regSDMA1_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_IB_OFFSET = 0x068c # macro +regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_IB_BASE_LO = 0x068d # macro +regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_IB_BASE_HI = 0x068e # macro +regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_IB_SIZE = 0x068f # macro +regSDMA1_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_SKIP_CNTL = 0x0690 # macro +regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_CONTEXT_STATUS = 0x0691 # macro +regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_DOORBELL = 0x0692 # macro +regSDMA1_QUEUE0_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_DOORBELL_LOG = 0x06a9 # macro +regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_DOORBELL_OFFSET = 0x06ab # macro +regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_CSA_ADDR_LO = 0x06ac # macro +regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_CSA_ADDR_HI = 0x06ad # macro +regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_SCHEDULE_CNTL = 0x06ae # macro +regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_IB_SUB_REMAIN = 0x06af # macro +regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_PREEMPT = 0x06b0 # macro +regSDMA1_QUEUE0_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_DUMMY_REG = 0x06b1 # macro +regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_AQL_CNTL = 0x06b4 # macro +regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MINOR_PTR_UPDATE = 0x06b5 # macro +regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_RB_PREEMPT = 0x06b6 # macro +regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA0 = 0x06c0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA1 = 0x06c1 # macro +regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA2 = 0x06c2 # macro +regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA3 = 0x06c3 # macro +regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA4 = 0x06c4 # macro +regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA5 = 0x06c5 # macro +regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA6 = 0x06c6 # macro +regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA7 = 0x06c7 # macro +regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA8 = 0x06c8 # macro +regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA9 = 0x06c9 # macro +regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_DATA10 = 0x06ca # macro +regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE0_MIDCMD_CNTL = 0x06cb # macro +regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_CNTL = 0x06d8 # macro +regSDMA1_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_BASE = 0x06d9 # macro +regSDMA1_QUEUE1_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_BASE_HI = 0x06da # macro +regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_RPTR = 0x06db # macro +regSDMA1_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_RPTR_HI = 0x06dc # macro +regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_WPTR = 0x06dd # macro +regSDMA1_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_WPTR_HI = 0x06de # macro +regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_RPTR_ADDR_HI = 0x06e0 # macro +regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_RPTR_ADDR_LO = 0x06e1 # macro +regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_IB_CNTL = 0x06e2 # macro +regSDMA1_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_IB_RPTR = 0x06e3 # macro +regSDMA1_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_IB_OFFSET = 0x06e4 # macro +regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_IB_BASE_LO = 0x06e5 # macro +regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_IB_BASE_HI = 0x06e6 # macro +regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_IB_SIZE = 0x06e7 # macro +regSDMA1_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_SKIP_CNTL = 0x06e8 # macro +regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_CONTEXT_STATUS = 0x06e9 # macro +regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_DOORBELL = 0x06ea # macro +regSDMA1_QUEUE1_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_DOORBELL_LOG = 0x0701 # macro +regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_DOORBELL_OFFSET = 0x0703 # macro +regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_CSA_ADDR_LO = 0x0704 # macro +regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_CSA_ADDR_HI = 0x0705 # macro +regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_SCHEDULE_CNTL = 0x0706 # macro +regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_IB_SUB_REMAIN = 0x0707 # macro +regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_PREEMPT = 0x0708 # macro +regSDMA1_QUEUE1_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_DUMMY_REG = 0x0709 # macro +regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x070a # macro +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x070b # macro +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_AQL_CNTL = 0x070c # macro +regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MINOR_PTR_UPDATE = 0x070d # macro +regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_RB_PREEMPT = 0x070e # macro +regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA0 = 0x0718 # macro +regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA1 = 0x0719 # macro +regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA2 = 0x071a # macro +regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA3 = 0x071b # macro +regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA4 = 0x071c # macro +regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA5 = 0x071d # macro +regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA6 = 0x071e # macro +regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA7 = 0x071f # macro +regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA8 = 0x0720 # macro +regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA9 = 0x0721 # macro +regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_DATA10 = 0x0722 # macro +regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE1_MIDCMD_CNTL = 0x0723 # macro +regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_CNTL = 0x0730 # macro +regSDMA1_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_BASE = 0x0731 # macro +regSDMA1_QUEUE2_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_BASE_HI = 0x0732 # macro +regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_RPTR = 0x0733 # macro +regSDMA1_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_RPTR_HI = 0x0734 # macro +regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_WPTR = 0x0735 # macro +regSDMA1_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_WPTR_HI = 0x0736 # macro +regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_RPTR_ADDR_HI = 0x0738 # macro +regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_RPTR_ADDR_LO = 0x0739 # macro +regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_IB_CNTL = 0x073a # macro +regSDMA1_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_IB_RPTR = 0x073b # macro +regSDMA1_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_IB_OFFSET = 0x073c # macro +regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_IB_BASE_LO = 0x073d # macro +regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_IB_BASE_HI = 0x073e # macro +regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_IB_SIZE = 0x073f # macro +regSDMA1_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_SKIP_CNTL = 0x0740 # macro +regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_CONTEXT_STATUS = 0x0741 # macro +regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_DOORBELL = 0x0742 # macro +regSDMA1_QUEUE2_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_DOORBELL_LOG = 0x0759 # macro +regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_DOORBELL_OFFSET = 0x075b # macro +regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_CSA_ADDR_LO = 0x075c # macro +regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_CSA_ADDR_HI = 0x075d # macro +regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_SCHEDULE_CNTL = 0x075e # macro +regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_IB_SUB_REMAIN = 0x075f # macro +regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_PREEMPT = 0x0760 # macro +regSDMA1_QUEUE2_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_DUMMY_REG = 0x0761 # macro +regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_AQL_CNTL = 0x0764 # macro +regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MINOR_PTR_UPDATE = 0x0765 # macro +regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_RB_PREEMPT = 0x0766 # macro +regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA0 = 0x0770 # macro +regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA1 = 0x0771 # macro +regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA2 = 0x0772 # macro +regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA3 = 0x0773 # macro +regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA4 = 0x0774 # macro +regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA5 = 0x0775 # macro +regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA6 = 0x0776 # macro +regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA7 = 0x0777 # macro +regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA8 = 0x0778 # macro +regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA9 = 0x0779 # macro +regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_DATA10 = 0x077a # macro +regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE2_MIDCMD_CNTL = 0x077b # macro +regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_CNTL = 0x0788 # macro +regSDMA1_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_BASE = 0x0789 # macro +regSDMA1_QUEUE3_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_BASE_HI = 0x078a # macro +regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_RPTR = 0x078b # macro +regSDMA1_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_RPTR_HI = 0x078c # macro +regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_WPTR = 0x078d # macro +regSDMA1_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_WPTR_HI = 0x078e # macro +regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_RPTR_ADDR_HI = 0x0790 # macro +regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_RPTR_ADDR_LO = 0x0791 # macro +regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_IB_CNTL = 0x0792 # macro +regSDMA1_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_IB_RPTR = 0x0793 # macro +regSDMA1_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_IB_OFFSET = 0x0794 # macro +regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_IB_BASE_LO = 0x0795 # macro +regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_IB_BASE_HI = 0x0796 # macro +regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_IB_SIZE = 0x0797 # macro +regSDMA1_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_SKIP_CNTL = 0x0798 # macro +regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_CONTEXT_STATUS = 0x0799 # macro +regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_DOORBELL = 0x079a # macro +regSDMA1_QUEUE3_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_DOORBELL_LOG = 0x07b1 # macro +regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_DOORBELL_OFFSET = 0x07b3 # macro +regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_CSA_ADDR_LO = 0x07b4 # macro +regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_CSA_ADDR_HI = 0x07b5 # macro +regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_SCHEDULE_CNTL = 0x07b6 # macro +regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_IB_SUB_REMAIN = 0x07b7 # macro +regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_PREEMPT = 0x07b8 # macro +regSDMA1_QUEUE3_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_DUMMY_REG = 0x07b9 # macro +regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_AQL_CNTL = 0x07bc # macro +regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MINOR_PTR_UPDATE = 0x07bd # macro +regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_RB_PREEMPT = 0x07be # macro +regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA0 = 0x07c8 # macro +regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA1 = 0x07c9 # macro +regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA2 = 0x07ca # macro +regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA3 = 0x07cb # macro +regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA4 = 0x07cc # macro +regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA5 = 0x07cd # macro +regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA6 = 0x07ce # macro +regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA7 = 0x07cf # macro +regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA8 = 0x07d0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA9 = 0x07d1 # macro +regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_DATA10 = 0x07d2 # macro +regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE3_MIDCMD_CNTL = 0x07d3 # macro +regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_CNTL = 0x07e0 # macro +regSDMA1_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_BASE = 0x07e1 # macro +regSDMA1_QUEUE4_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_BASE_HI = 0x07e2 # macro +regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_RPTR = 0x07e3 # macro +regSDMA1_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_RPTR_HI = 0x07e4 # macro +regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_WPTR = 0x07e5 # macro +regSDMA1_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_WPTR_HI = 0x07e6 # macro +regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_RPTR_ADDR_HI = 0x07e8 # macro +regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_RPTR_ADDR_LO = 0x07e9 # macro +regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_IB_CNTL = 0x07ea # macro +regSDMA1_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_IB_RPTR = 0x07eb # macro +regSDMA1_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_IB_OFFSET = 0x07ec # macro +regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_IB_BASE_LO = 0x07ed # macro +regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_IB_BASE_HI = 0x07ee # macro +regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_IB_SIZE = 0x07ef # macro +regSDMA1_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_SKIP_CNTL = 0x07f0 # macro +regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_CONTEXT_STATUS = 0x07f1 # macro +regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_DOORBELL = 0x07f2 # macro +regSDMA1_QUEUE4_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_DOORBELL_LOG = 0x0809 # macro +regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_DOORBELL_OFFSET = 0x080b # macro +regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_CSA_ADDR_LO = 0x080c # macro +regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_CSA_ADDR_HI = 0x080d # macro +regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_SCHEDULE_CNTL = 0x080e # macro +regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_IB_SUB_REMAIN = 0x080f # macro +regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_PREEMPT = 0x0810 # macro +regSDMA1_QUEUE4_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_DUMMY_REG = 0x0811 # macro +regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_AQL_CNTL = 0x0814 # macro +regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MINOR_PTR_UPDATE = 0x0815 # macro +regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_RB_PREEMPT = 0x0816 # macro +regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA0 = 0x0820 # macro +regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA1 = 0x0821 # macro +regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA2 = 0x0822 # macro +regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA3 = 0x0823 # macro +regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA4 = 0x0824 # macro +regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA5 = 0x0825 # macro +regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA6 = 0x0826 # macro +regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA7 = 0x0827 # macro +regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA8 = 0x0828 # macro +regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA9 = 0x0829 # macro +regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_DATA10 = 0x082a # macro +regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE4_MIDCMD_CNTL = 0x082b # macro +regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_CNTL = 0x0838 # macro +regSDMA1_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_BASE = 0x0839 # macro +regSDMA1_QUEUE5_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_BASE_HI = 0x083a # macro +regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_RPTR = 0x083b # macro +regSDMA1_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_RPTR_HI = 0x083c # macro +regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_WPTR = 0x083d # macro +regSDMA1_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_WPTR_HI = 0x083e # macro +regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_RPTR_ADDR_HI = 0x0840 # macro +regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_RPTR_ADDR_LO = 0x0841 # macro +regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_IB_CNTL = 0x0842 # macro +regSDMA1_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_IB_RPTR = 0x0843 # macro +regSDMA1_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_IB_OFFSET = 0x0844 # macro +regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_IB_BASE_LO = 0x0845 # macro +regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_IB_BASE_HI = 0x0846 # macro +regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_IB_SIZE = 0x0847 # macro +regSDMA1_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_SKIP_CNTL = 0x0848 # macro +regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_CONTEXT_STATUS = 0x0849 # macro +regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_DOORBELL = 0x084a # macro +regSDMA1_QUEUE5_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_DOORBELL_LOG = 0x0861 # macro +regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_DOORBELL_OFFSET = 0x0863 # macro +regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_CSA_ADDR_LO = 0x0864 # macro +regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_CSA_ADDR_HI = 0x0865 # macro +regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_SCHEDULE_CNTL = 0x0866 # macro +regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_IB_SUB_REMAIN = 0x0867 # macro +regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_PREEMPT = 0x0868 # macro +regSDMA1_QUEUE5_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_DUMMY_REG = 0x0869 # macro +regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x086a # macro +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x086b # macro +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_AQL_CNTL = 0x086c # macro +regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MINOR_PTR_UPDATE = 0x086d # macro +regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_RB_PREEMPT = 0x086e # macro +regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA0 = 0x0878 # macro +regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA1 = 0x0879 # macro +regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA2 = 0x087a # macro +regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA3 = 0x087b # macro +regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA4 = 0x087c # macro +regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA5 = 0x087d # macro +regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA6 = 0x087e # macro +regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA7 = 0x087f # macro +regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA8 = 0x0880 # macro +regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA9 = 0x0881 # macro +regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_DATA10 = 0x0882 # macro +regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE5_MIDCMD_CNTL = 0x0883 # macro +regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_CNTL = 0x0890 # macro +regSDMA1_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_BASE = 0x0891 # macro +regSDMA1_QUEUE6_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_BASE_HI = 0x0892 # macro +regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_RPTR = 0x0893 # macro +regSDMA1_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_RPTR_HI = 0x0894 # macro +regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_WPTR = 0x0895 # macro +regSDMA1_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_WPTR_HI = 0x0896 # macro +regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_RPTR_ADDR_HI = 0x0898 # macro +regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_RPTR_ADDR_LO = 0x0899 # macro +regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_IB_CNTL = 0x089a # macro +regSDMA1_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_IB_RPTR = 0x089b # macro +regSDMA1_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_IB_OFFSET = 0x089c # macro +regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_IB_BASE_LO = 0x089d # macro +regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_IB_BASE_HI = 0x089e # macro +regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_IB_SIZE = 0x089f # macro +regSDMA1_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_SKIP_CNTL = 0x08a0 # macro +regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_CONTEXT_STATUS = 0x08a1 # macro +regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_DOORBELL = 0x08a2 # macro +regSDMA1_QUEUE6_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_DOORBELL_LOG = 0x08b9 # macro +regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_DOORBELL_OFFSET = 0x08bb # macro +regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_CSA_ADDR_LO = 0x08bc # macro +regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_CSA_ADDR_HI = 0x08bd # macro +regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_SCHEDULE_CNTL = 0x08be # macro +regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_IB_SUB_REMAIN = 0x08bf # macro +regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_PREEMPT = 0x08c0 # macro +regSDMA1_QUEUE6_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_DUMMY_REG = 0x08c1 # macro +regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_AQL_CNTL = 0x08c4 # macro +regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MINOR_PTR_UPDATE = 0x08c5 # macro +regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_RB_PREEMPT = 0x08c6 # macro +regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA0 = 0x08d0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA1 = 0x08d1 # macro +regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA2 = 0x08d2 # macro +regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA3 = 0x08d3 # macro +regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA4 = 0x08d4 # macro +regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA5 = 0x08d5 # macro +regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA6 = 0x08d6 # macro +regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA7 = 0x08d7 # macro +regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA8 = 0x08d8 # macro +regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA9 = 0x08d9 # macro +regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_DATA10 = 0x08da # macro +regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE6_MIDCMD_CNTL = 0x08db # macro +regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_CNTL = 0x08e8 # macro +regSDMA1_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_BASE = 0x08e9 # macro +regSDMA1_QUEUE7_RB_BASE_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_BASE_HI = 0x08ea # macro +regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_RPTR = 0x08eb # macro +regSDMA1_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_RPTR_HI = 0x08ec # macro +regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_WPTR = 0x08ed # macro +regSDMA1_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_WPTR_HI = 0x08ee # macro +regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_RPTR_ADDR_HI = 0x08f0 # macro +regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_RPTR_ADDR_LO = 0x08f1 # macro +regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_IB_CNTL = 0x08f2 # macro +regSDMA1_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_IB_RPTR = 0x08f3 # macro +regSDMA1_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_IB_OFFSET = 0x08f4 # macro +regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_IB_BASE_LO = 0x08f5 # macro +regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_IB_BASE_HI = 0x08f6 # macro +regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_IB_SIZE = 0x08f7 # macro +regSDMA1_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_SKIP_CNTL = 0x08f8 # macro +regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_CONTEXT_STATUS = 0x08f9 # macro +regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_DOORBELL = 0x08fa # macro +regSDMA1_QUEUE7_DOORBELL_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_DOORBELL_LOG = 0x0911 # macro +regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_DOORBELL_OFFSET = 0x0913 # macro +regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_CSA_ADDR_LO = 0x0914 # macro +regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_CSA_ADDR_HI = 0x0915 # macro +regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_SCHEDULE_CNTL = 0x0916 # macro +regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_IB_SUB_REMAIN = 0x0917 # macro +regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_PREEMPT = 0x0918 # macro +regSDMA1_QUEUE7_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_DUMMY_REG = 0x0919 # macro +regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x091a # macro +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x091b # macro +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_AQL_CNTL = 0x091c # macro +regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MINOR_PTR_UPDATE = 0x091d # macro +regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_RB_PREEMPT = 0x091e # macro +regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA0 = 0x0928 # macro +regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA1 = 0x0929 # macro +regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA2 = 0x092a # macro +regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA3 = 0x092b # macro +regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA4 = 0x092c # macro +regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA5 = 0x092d # macro +regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA6 = 0x092e # macro +regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA7 = 0x092f # macro +regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA8 = 0x0930 # macro +regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA9 = 0x0931 # macro +regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_DATA10 = 0x0932 # macro +regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro +regSDMA1_QUEUE7_MIDCMD_CNTL = 0x0933 # macro +regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro +regSDMA0_UCODE_ADDR = 0x5880 # macro +regSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro +regSDMA0_UCODE_DATA = 0x5881 # macro +regSDMA0_UCODE_DATA_BASE_IDX = 1 # macro +regSDMA0_UCODE_SELFLOAD_CONTROL = 0x5882 # macro +regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro +regSDMA0_BROADCAST_UCODE_ADDR = 0x5886 # macro +regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro +regSDMA0_BROADCAST_UCODE_DATA = 0x5887 # macro +regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro +regSDMA0_F32_CNTL = 0x589a # macro +regSDMA0_F32_CNTL_BASE_IDX = 1 # macro +regSDMA1_UCODE_ADDR = 0x58a0 # macro +regSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro +regSDMA1_UCODE_DATA = 0x58a1 # macro +regSDMA1_UCODE_DATA_BASE_IDX = 1 # macro +regSDMA1_UCODE_SELFLOAD_CONTROL = 0x58a2 # macro +regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro +regSDMA1_BROADCAST_UCODE_ADDR = 0x58a6 # macro +regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro +regSDMA1_BROADCAST_UCODE_DATA = 0x58a7 # macro +regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro +regSDMA1_F32_CNTL = 0x58ba # macro +regSDMA1_F32_CNTL_BASE_IDX = 1 # macro +regSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro +regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro +regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro +regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro +regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro +regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro +regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro +regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro +regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro +regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro +regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro +regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro +regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro +regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro +regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro +regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro +regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro +regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro +regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER0_LO = 0x3662 # macro +regSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER0_HI = 0x3663 # macro +regSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER1_LO = 0x3664 # macro +regSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSDMA0_PERFCOUNTER1_HI = 0x3665 # macro +regSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro +regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro +regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER0_LO = 0x366e # macro +regSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER0_HI = 0x366f # macro +regSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER1_LO = 0x3670 # macro +regSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSDMA1_PERFCOUNTER1_HI = 0x3671 # macro +regSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGRBM_CNTL = 0x0da0 # macro +regGRBM_CNTL_BASE_IDX = 0 # macro +regGRBM_SKEW_CNTL = 0x0da1 # macro +regGRBM_SKEW_CNTL_BASE_IDX = 0 # macro +regGRBM_STATUS2 = 0x0da2 # macro +regGRBM_STATUS2_BASE_IDX = 0 # macro +regGRBM_PWR_CNTL = 0x0da3 # macro +regGRBM_PWR_CNTL_BASE_IDX = 0 # macro +regGRBM_STATUS = 0x0da4 # macro +regGRBM_STATUS_BASE_IDX = 0 # macro +regGRBM_STATUS_SE0 = 0x0da5 # macro +regGRBM_STATUS_SE0_BASE_IDX = 0 # macro +regGRBM_STATUS_SE1 = 0x0da6 # macro +regGRBM_STATUS_SE1_BASE_IDX = 0 # macro +regGRBM_STATUS3 = 0x0da7 # macro +regGRBM_STATUS3_BASE_IDX = 0 # macro +regGRBM_SOFT_RESET = 0x0da8 # macro +regGRBM_SOFT_RESET_BASE_IDX = 0 # macro +regGRBM_GFX_CLKEN_CNTL = 0x0dac # macro +regGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro +regGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro +regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro +regGRBM_STATUS_SE2 = 0x0dae # macro +regGRBM_STATUS_SE2_BASE_IDX = 0 # macro +regGRBM_STATUS_SE3 = 0x0daf # macro +regGRBM_STATUS_SE3_BASE_IDX = 0 # macro +regGRBM_STATUS_SE4 = 0x0db0 # macro +regGRBM_STATUS_SE4_BASE_IDX = 0 # macro +regGRBM_STATUS_SE5 = 0x0db1 # macro +regGRBM_STATUS_SE5_BASE_IDX = 0 # macro +regGRBM_READ_ERROR = 0x0db6 # macro +regGRBM_READ_ERROR_BASE_IDX = 0 # macro +regGRBM_READ_ERROR2 = 0x0db7 # macro +regGRBM_READ_ERROR2_BASE_IDX = 0 # macro +regGRBM_INT_CNTL = 0x0db8 # macro +regGRBM_INT_CNTL_BASE_IDX = 0 # macro +regGRBM_TRAP_OP = 0x0db9 # macro +regGRBM_TRAP_OP_BASE_IDX = 0 # macro +regGRBM_TRAP_ADDR = 0x0dba # macro +regGRBM_TRAP_ADDR_BASE_IDX = 0 # macro +regGRBM_TRAP_ADDR_MSK = 0x0dbb # macro +regGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro +regGRBM_TRAP_WD = 0x0dbc # macro +regGRBM_TRAP_WD_BASE_IDX = 0 # macro +regGRBM_TRAP_WD_MSK = 0x0dbd # macro +regGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro +regGRBM_DSM_BYPASS = 0x0dbe # macro +regGRBM_DSM_BYPASS_BASE_IDX = 0 # macro +regGRBM_WRITE_ERROR = 0x0dbf # macro +regGRBM_WRITE_ERROR_BASE_IDX = 0 # macro +regGRBM_CHIP_REVISION = 0x0dc1 # macro +regGRBM_CHIP_REVISION_BASE_IDX = 0 # macro +regGRBM_IH_CREDIT = 0x0dc4 # macro +regGRBM_IH_CREDIT_BASE_IDX = 0 # macro +regGRBM_PWR_CNTL2 = 0x0dc5 # macro +regGRBM_PWR_CNTL2_BASE_IDX = 0 # macro +regGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro +regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro +regGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro +regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro +regGRBM_INVALID_PIPE = 0x0dc9 # macro +regGRBM_INVALID_PIPE_BASE_IDX = 0 # macro +regGRBM_FENCE_RANGE0 = 0x0dca # macro +regGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro +regGRBM_FENCE_RANGE1 = 0x0dcb # macro +regGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG0 = 0x0de0 # macro +regGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG1 = 0x0de1 # macro +regGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG2 = 0x0de2 # macro +regGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG3 = 0x0de3 # macro +regGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG4 = 0x0de4 # macro +regGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG5 = 0x0de5 # macro +regGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG6 = 0x0de6 # macro +regGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG7 = 0x0de7 # macro +regGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro +regVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro +regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro +regCP_CPC_DEBUG_CNTL = 0x0e20 # macro +regCP_CPC_DEBUG_CNTL_BASE_IDX = 0 # macro +regCP_CPC_DEBUG_DATA = 0x0e21 # macro +regCP_CPC_DEBUG_DATA_BASE_IDX = 0 # macro +regCP_CPC_STATUS = 0x0e24 # macro +regCP_CPC_STATUS_BASE_IDX = 0 # macro +regCP_CPC_BUSY_STAT = 0x0e25 # macro +regCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro +regCP_CPC_STALLED_STAT1 = 0x0e26 # macro +regCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro +regCP_CPF_STATUS = 0x0e27 # macro +regCP_CPF_STATUS_BASE_IDX = 0 # macro +regCP_CPF_BUSY_STAT = 0x0e28 # macro +regCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro +regCP_CPF_STALLED_STAT1 = 0x0e29 # macro +regCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro +regCP_CPC_BUSY_STAT2 = 0x0e2a # macro +regCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro +regCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro +regCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +regCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro +regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro +regCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro +regCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro +regCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_CPC_SCRATCH_INDEX = 0x0e30 # macro +regCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro +regCP_CPC_SCRATCH_DATA = 0x0e31 # macro +regCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro +regCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro +regCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +regCP_CPF_BUSY_STAT2 = 0x0e33 # macro +regCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro +regCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro +regCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro +regCP_STALLED_STAT3 = 0x0f3c # macro +regCP_STALLED_STAT3_BASE_IDX = 0 # macro +regCP_STALLED_STAT1 = 0x0f3d # macro +regCP_STALLED_STAT1_BASE_IDX = 0 # macro +regCP_STALLED_STAT2 = 0x0f3e # macro +regCP_STALLED_STAT2_BASE_IDX = 0 # macro +regCP_BUSY_STAT = 0x0f3f # macro +regCP_BUSY_STAT_BASE_IDX = 0 # macro +regCP_STAT = 0x0f40 # macro +regCP_STAT_BASE_IDX = 0 # macro +regCP_ME_HEADER_DUMP = 0x0f41 # macro +regCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_PFP_HEADER_DUMP = 0x0f42 # macro +regCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_GRBM_FREE_COUNT = 0x0f43 # macro +regCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +regCP_PFP_INSTR_PNTR = 0x0f45 # macro +regCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_ME_INSTR_PNTR = 0x0f46 # macro +regCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_MEC1_INSTR_PNTR = 0x0f48 # macro +regCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_MEC2_INSTR_PNTR = 0x0f49 # macro +regCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_CSF_STAT = 0x0f54 # macro +regCP_CSF_STAT_BASE_IDX = 0 # macro +regCP_CNTX_STAT = 0x0f58 # macro +regCP_CNTX_STAT_BASE_IDX = 0 # macro +regCP_ME_PREEMPTION = 0x0f59 # macro +regCP_ME_PREEMPTION_BASE_IDX = 0 # macro +regCP_RB1_RPTR = 0x0f5f # macro +regCP_RB1_RPTR_BASE_IDX = 0 # macro +regCP_RB0_RPTR = 0x0f60 # macro +regCP_RB0_RPTR_BASE_IDX = 0 # macro +regCP_RB_RPTR = 0x0f60 # macro +regCP_RB_RPTR_BASE_IDX = 0 # macro +regCP_RB_WPTR_DELAY = 0x0f61 # macro +regCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro +regCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro +regCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +regCP_ROQ1_THRESHOLDS = 0x0f75 # macro +regCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro +regCP_ROQ2_THRESHOLDS = 0x0f76 # macro +regCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro +regCP_STQ_THRESHOLDS = 0x0f77 # macro +regCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro +regCP_MEQ_THRESHOLDS = 0x0f79 # macro +regCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro +regCP_ROQ_AVAIL = 0x0f7a # macro +regCP_ROQ_AVAIL_BASE_IDX = 0 # macro +regCP_STQ_AVAIL = 0x0f7b # macro +regCP_STQ_AVAIL_BASE_IDX = 0 # macro +regCP_ROQ2_AVAIL = 0x0f7c # macro +regCP_ROQ2_AVAIL_BASE_IDX = 0 # macro +regCP_MEQ_AVAIL = 0x0f7d # macro +regCP_MEQ_AVAIL_BASE_IDX = 0 # macro +regCP_CMD_INDEX = 0x0f7e # macro +regCP_CMD_INDEX_BASE_IDX = 0 # macro +regCP_CMD_DATA = 0x0f7f # macro +regCP_CMD_DATA_BASE_IDX = 0 # macro +regCP_ROQ_RB_STAT = 0x0f80 # macro +regCP_ROQ_RB_STAT_BASE_IDX = 0 # macro +regCP_ROQ_IB1_STAT = 0x0f81 # macro +regCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro +regCP_ROQ_IB2_STAT = 0x0f82 # macro +regCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro +regCP_STQ_STAT = 0x0f83 # macro +regCP_STQ_STAT_BASE_IDX = 0 # macro +regCP_STQ_WR_STAT = 0x0f84 # macro +regCP_STQ_WR_STAT_BASE_IDX = 0 # macro +regCP_MEQ_STAT = 0x0f85 # macro +regCP_MEQ_STAT_BASE_IDX = 0 # macro +regCP_ROQ3_THRESHOLDS = 0x0f8c # macro +regCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro +regCP_ROQ_DB_STAT = 0x0f8d # macro +regCP_ROQ_DB_STAT_BASE_IDX = 0 # macro +regCP_DEBUG_CNTL = 0x0f98 # macro +regCP_DEBUG_CNTL_BASE_IDX = 0 # macro +regCP_DEBUG_DATA = 0x0f99 # macro +regCP_DEBUG_DATA_BASE_IDX = 0 # macro +regCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro +regCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro +regVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro +regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro +regVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro +regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro +regVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro +regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro +regVGT_MC_LAT_CNTL = 0x0fd6 # macro +regVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro +regIA_UTCL1_STATUS_2 = 0x0fd7 # macro +regIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro +regWD_CNTL_STATUS = 0x0fdf # macro +regWD_CNTL_STATUS_BASE_IDX = 0 # macro +regCC_GC_PRIM_CONFIG = 0x0fe0 # macro +regCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro +regWD_QOS = 0x0fe2 # macro +regWD_QOS_BASE_IDX = 0 # macro +regWD_UTCL1_CNTL = 0x0fe3 # macro +regWD_UTCL1_CNTL_BASE_IDX = 0 # macro +regWD_UTCL1_STATUS = 0x0fe4 # macro +regWD_UTCL1_STATUS_BASE_IDX = 0 # macro +regIA_UTCL1_CNTL = 0x0fe6 # macro +regIA_UTCL1_CNTL_BASE_IDX = 0 # macro +regIA_UTCL1_STATUS = 0x0fe7 # macro +regIA_UTCL1_STATUS_BASE_IDX = 0 # macro +regCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro +regCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro +regGE_RATE_CNTL_1 = 0x0ff4 # macro +regGE_RATE_CNTL_1_BASE_IDX = 0 # macro +regGE_RATE_CNTL_2 = 0x0ff5 # macro +regGE_RATE_CNTL_2_BASE_IDX = 0 # macro +regVGT_SYS_CONFIG = 0x1003 # macro +regVGT_SYS_CONFIG_BASE_IDX = 0 # macro +regGE_PRIV_CONTROL = 0x1004 # macro +regGE_PRIV_CONTROL_BASE_IDX = 0 # macro +regGE_STATUS = 0x1005 # macro +regGE_STATUS_BASE_IDX = 0 # macro +regVGT_GS_MAX_WAVE_ID = 0x1009 # macro +regVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro +regGFX_PIPE_CONTROL = 0x100d # macro +regGFX_PIPE_CONTROL_BASE_IDX = 0 # macro +regCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro +regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro +regGE2_SE_CNTL_STATUS = 0x1011 # macro +regGE2_SE_CNTL_STATUS_BASE_IDX = 0 # macro +regGE_SPI_IF_SAFE_REG = 0x1018 # macro +regGE_SPI_IF_SAFE_REG_BASE_IDX = 0 # macro +regGE_PA_IF_SAFE_REG = 0x1019 # macro +regGE_PA_IF_SAFE_REG_BASE_IDX = 0 # macro +regPA_CL_CNTL_STATUS = 0x1024 # macro +regPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro +regPA_CL_ENHANCE = 0x1025 # macro +regPA_CL_ENHANCE_BASE_IDX = 0 # macro +regPA_SU_CNTL_STATUS = 0x1034 # macro +regPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro +regPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro +regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro +regSQ_CONFIG = 0x10a0 # macro +regSQ_CONFIG_BASE_IDX = 0 # macro +regSQC_CONFIG = 0x10a1 # macro +regSQC_CONFIG_BASE_IDX = 0 # macro +regLDS_CONFIG = 0x10a2 # macro +regLDS_CONFIG_BASE_IDX = 0 # macro +regSQ_RANDOM_WAVE_PRI = 0x10a3 # macro +regSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro +regSQG_STATUS = 0x10a4 # macro +regSQG_STATUS_BASE_IDX = 0 # macro +regSQ_FIFO_SIZES = 0x10a5 # macro +regSQ_FIFO_SIZES_BASE_IDX = 0 # macro +regSQ_DSM_CNTL = 0x10a6 # macro +regSQ_DSM_CNTL_BASE_IDX = 0 # macro +regSQ_DSM_CNTL2 = 0x10a7 # macro +regSQ_DSM_CNTL2_BASE_IDX = 0 # macro +regSP_CONFIG = 0x10ab # macro +regSP_CONFIG_BASE_IDX = 0 # macro +regSQ_ARB_CONFIG = 0x10ac # macro +regSQ_ARB_CONFIG_BASE_IDX = 0 # macro +regSQ_DEBUG_HOST_TRAP_STATUS = 0x10b6 # macro +regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX = 0 # macro +regSQG_GL1H_STATUS = 0x10b9 # macro +regSQG_GL1H_STATUS_BASE_IDX = 0 # macro +regSQG_CONFIG = 0x10ba # macro +regSQG_CONFIG_BASE_IDX = 0 # macro +regSQ_PERF_SNAPSHOT_CTRL = 0x10bb # macro +regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX = 0 # macro +regCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro +regCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro +regSQ_INTERRUPT_AUTO_MASK = 0x10be # macro +regSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro +regSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro +regSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro +regSQ_WATCH0_ADDR_H = 0x10d0 # macro +regSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro +regSQ_WATCH0_ADDR_L = 0x10d1 # macro +regSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro +regSQ_WATCH0_CNTL = 0x10d2 # macro +regSQ_WATCH0_CNTL_BASE_IDX = 0 # macro +regSQ_WATCH1_ADDR_H = 0x10d3 # macro +regSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro +regSQ_WATCH1_ADDR_L = 0x10d4 # macro +regSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro +regSQ_WATCH1_CNTL = 0x10d5 # macro +regSQ_WATCH1_CNTL_BASE_IDX = 0 # macro +regSQ_WATCH2_ADDR_H = 0x10d6 # macro +regSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro +regSQ_WATCH2_ADDR_L = 0x10d7 # macro +regSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro +regSQ_WATCH2_CNTL = 0x10d8 # macro +regSQ_WATCH2_CNTL_BASE_IDX = 0 # macro +regSQ_WATCH3_ADDR_H = 0x10d9 # macro +regSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro +regSQ_WATCH3_ADDR_L = 0x10da # macro +regSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro +regSQ_WATCH3_CNTL = 0x10db # macro +regSQ_WATCH3_CNTL_BASE_IDX = 0 # macro +regSQ_IND_INDEX = 0x1118 # macro +regSQ_IND_INDEX_BASE_IDX = 0 # macro +regSQ_IND_DATA = 0x1119 # macro +regSQ_IND_DATA_BASE_IDX = 0 # macro +regSQ_CMD = 0x111b # macro +regSQ_CMD_BASE_IDX = 0 # macro +regSX_DEBUG_1 = 0x11b8 # macro +regSX_DEBUG_1_BASE_IDX = 0 # macro +regSPI_PS_MAX_WAVE_ID = 0x11da # macro +regSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro +regSPI_GFX_CNTL = 0x11dc # macro +regSPI_GFX_CNTL_BASE_IDX = 0 # macro +regSPI_DSM_CNTL = 0x11e3 # macro +regSPI_DSM_CNTL_BASE_IDX = 0 # macro +regSPI_DSM_CNTL2 = 0x11e4 # macro +regSPI_DSM_CNTL2_BASE_IDX = 0 # macro +regSPI_EDC_CNT = 0x11e5 # macro +regSPI_EDC_CNT_BASE_IDX = 0 # macro +regSPI_CONFIG_PS_CU_EN = 0x11f2 # macro +regSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_CNTL = 0x124a # macro +regSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro +regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro +regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro +regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro +regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro +regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro +regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro +regSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro +regSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro +regSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro +regSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro +regSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro +regSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro +regSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro +regSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro +regSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro +regSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro +regSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro +regSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro +regSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro +regSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro +regSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro +regSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro +regSPI_LB_CTR_CTRL = 0x1274 # macro +regSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro +regSPI_LB_WGP_MASK = 0x1275 # macro +regSPI_LB_WGP_MASK_BASE_IDX = 0 # macro +regSPI_LB_DATA_REG = 0x1276 # macro +regSPI_LB_DATA_REG_BASE_IDX = 0 # macro +regSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro +regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro +regSPI_GDS_CREDITS = 0x1278 # macro +regSPI_GDS_CREDITS_BASE_IDX = 0 # macro +regSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro +regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro +regSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro +regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro +regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro +regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro +regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro +regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro +regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro +regSPI_LB_DATA_WAVES = 0x1284 # macro +regSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro +regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro +regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro +regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro +regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro +regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro +regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro +regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro +regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro +regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro +regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro +regTD_STATUS = 0x12c6 # macro +regTD_STATUS_BASE_IDX = 0 # macro +regTD_DSM_CNTL = 0x12cf # macro +regTD_DSM_CNTL_BASE_IDX = 0 # macro +regTD_DSM_CNTL2 = 0x12d0 # macro +regTD_DSM_CNTL2_BASE_IDX = 0 # macro +regTD_SCRATCH = 0x12d3 # macro +regTD_SCRATCH_BASE_IDX = 0 # macro +regTA_CNTL = 0x12e1 # macro +regTA_CNTL_BASE_IDX = 0 # macro +regTA_CNTL_AUX = 0x12e2 # macro +regTA_CNTL_AUX_BASE_IDX = 0 # macro +regTA_CNTL2 = 0x12e5 # macro +regTA_CNTL2_BASE_IDX = 0 # macro +regTA_STATUS = 0x12e8 # macro +regTA_STATUS_BASE_IDX = 0 # macro +regTA_SCRATCH = 0x1304 # macro +regTA_SCRATCH_BASE_IDX = 0 # macro +regGDS_CONFIG = 0x1360 # macro +regGDS_CONFIG_BASE_IDX = 0 # macro +regGDS_CNTL_STATUS = 0x1361 # macro +regGDS_CNTL_STATUS_BASE_IDX = 0 # macro +regGDS_ENHANCE = 0x1362 # macro +regGDS_ENHANCE_BASE_IDX = 0 # macro +regGDS_PROTECTION_FAULT = 0x1363 # macro +regGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro +regGDS_VM_PROTECTION_FAULT = 0x1364 # macro +regGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro +regGDS_EDC_CNT = 0x1365 # macro +regGDS_EDC_CNT_BASE_IDX = 0 # macro +regGDS_EDC_GRBM_CNT = 0x1366 # macro +regGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro +regGDS_EDC_OA_DED = 0x1367 # macro +regGDS_EDC_OA_DED_BASE_IDX = 0 # macro +regGDS_DSM_CNTL = 0x136a # macro +regGDS_DSM_CNTL_BASE_IDX = 0 # macro +regGDS_EDC_OA_PHY_CNT = 0x136b # macro +regGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro +regGDS_EDC_OA_PIPE_CNT = 0x136c # macro +regGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro +regGDS_DSM_CNTL2 = 0x136d # macro +regGDS_DSM_CNTL2_BASE_IDX = 0 # macro +regDB_DEBUG = 0x13ac # macro +regDB_DEBUG_BASE_IDX = 0 # macro +regDB_DEBUG2 = 0x13ad # macro +regDB_DEBUG2_BASE_IDX = 0 # macro +regDB_DEBUG3 = 0x13ae # macro +regDB_DEBUG3_BASE_IDX = 0 # macro +regDB_DEBUG4 = 0x13af # macro +regDB_DEBUG4_BASE_IDX = 0 # macro +regDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro +regDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro +regDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro +regDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro +regDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro +regDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro +regDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro +regDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro +regDB_CREDIT_LIMIT = 0x13b4 # macro +regDB_CREDIT_LIMIT_BASE_IDX = 0 # macro +regDB_WATERMARKS = 0x13b5 # macro +regDB_WATERMARKS_BASE_IDX = 0 # macro +regDB_SUBTILE_CONTROL = 0x13b6 # macro +regDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro +regDB_FREE_CACHELINES = 0x13b7 # macro +regDB_FREE_CACHELINES_BASE_IDX = 0 # macro +regDB_FIFO_DEPTH1 = 0x13b8 # macro +regDB_FIFO_DEPTH1_BASE_IDX = 0 # macro +regDB_FIFO_DEPTH2 = 0x13b9 # macro +regDB_FIFO_DEPTH2_BASE_IDX = 0 # macro +regDB_LAST_OF_BURST_CONFIG = 0x13ba # macro +regDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro +regDB_RING_CONTROL = 0x13bb # macro +regDB_RING_CONTROL_BASE_IDX = 0 # macro +regDB_MEM_ARB_WATERMARKS = 0x13bc # macro +regDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro +regDB_FIFO_DEPTH3 = 0x13bd # macro +regDB_FIFO_DEPTH3_BASE_IDX = 0 # macro +regDB_DEBUG6 = 0x13be # macro +regDB_DEBUG6_BASE_IDX = 0 # macro +regDB_EXCEPTION_CONTROL = 0x13bf # macro +regDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro +regDB_DEBUG7 = 0x13d0 # macro +regDB_DEBUG7_BASE_IDX = 0 # macro +regDB_DEBUG5 = 0x13d1 # macro +regDB_DEBUG5_BASE_IDX = 0 # macro +regDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro +regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro +regDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro +regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro +regDB_FIFO_DEPTH4 = 0x13d9 # macro +regDB_FIFO_DEPTH4_BASE_IDX = 0 # macro +regCC_RB_REDUNDANCY = 0x13dc # macro +regCC_RB_REDUNDANCY_BASE_IDX = 0 # macro +regCC_RB_BACKEND_DISABLE = 0x13dd # macro +regCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro +regGB_ADDR_CONFIG = 0x13de # macro +regGB_ADDR_CONFIG_BASE_IDX = 0 # macro +regGB_BACKEND_MAP = 0x13df # macro +regGB_BACKEND_MAP_BASE_IDX = 0 # macro +regGB_GPU_ID = 0x13e0 # macro +regGB_GPU_ID_BASE_IDX = 0 # macro +regCC_RB_DAISY_CHAIN = 0x13e1 # macro +regCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro +regGB_ADDR_CONFIG_READ = 0x13e2 # macro +regGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro +regCB_HW_CONTROL_4 = 0x1422 # macro +regCB_HW_CONTROL_4_BASE_IDX = 0 # macro +regCB_HW_CONTROL_3 = 0x1423 # macro +regCB_HW_CONTROL_3_BASE_IDX = 0 # macro +regCB_HW_CONTROL = 0x1424 # macro +regCB_HW_CONTROL_BASE_IDX = 0 # macro +regCB_HW_CONTROL_1 = 0x1425 # macro +regCB_HW_CONTROL_1_BASE_IDX = 0 # macro +regCB_HW_CONTROL_2 = 0x1426 # macro +regCB_HW_CONTROL_2_BASE_IDX = 0 # macro +regCB_DCC_CONFIG = 0x1427 # macro +regCB_DCC_CONFIG_BASE_IDX = 0 # macro +regCB_HW_MEM_ARBITER_RD = 0x1428 # macro +regCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro +regCB_HW_MEM_ARBITER_WR = 0x1429 # macro +regCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro +regCB_FGCG_SRAM_OVERRIDE = 0x142a # macro +regCB_FGCG_SRAM_OVERRIDE_BASE_IDX = 0 # macro +regCB_DCC_CONFIG2 = 0x142b # macro +regCB_DCC_CONFIG2_BASE_IDX = 0 # macro +regCHICKEN_BITS = 0x142d # macro +regCHICKEN_BITS_BASE_IDX = 0 # macro +regCB_CACHE_EVICT_POINTS = 0x142e # macro +regCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro +regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro +regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_LAZY = 0x17a6 # macro +regGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_LAZY = 0x17a7 # macro +regGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro +regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro +regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro +regGCEA_DRAM_PAGE_BURST = 0x17aa # macro +regGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro +regGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro +regGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro +regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro +regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro +regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro +regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro +regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro +regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro +regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro +regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro +regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro +regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro +regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro +regGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro +regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro +regGCEA_IO_GROUP_BURST = 0x1883 # macro +regGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_AGE = 0x1884 # macro +regGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_AGE = 0x1885 # macro +regGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro +regGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro +regGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_FIXED = 0x1888 # macro +regGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_FIXED = 0x1889 # macro +regGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_URGENCY = 0x188a # macro +regGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_URGENCY = 0x188b # macro +regGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro +regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro +regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro +regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro +regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro +regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro +regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro +regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro +regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_SDP_ARB_FINAL = 0x1896 # macro +regGCEA_SDP_ARB_FINAL_BASE_IDX = 0 # macro +regGCEA_SDP_IO_PRIORITY = 0x1899 # macro +regGCEA_SDP_IO_PRIORITY_BASE_IDX = 0 # macro +regGCEA_SDP_CREDITS = 0x189a # macro +regGCEA_SDP_CREDITS_BASE_IDX = 0 # macro +regGCEA_SDP_TAG_RESERVE0 = 0x189b # macro +regGCEA_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro +regGCEA_SDP_TAG_RESERVE1 = 0x189c # macro +regGCEA_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro +regGCEA_SDP_VCC_RESERVE0 = 0x189d # macro +regGCEA_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro +regGCEA_SDP_VCC_RESERVE1 = 0x189e # macro +regGCEA_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro +regGCEA_MISC = 0x14a2 # macro +regGCEA_MISC_BASE_IDX = 0 # macro +regGCEA_LATENCY_SAMPLING = 0x14a3 # macro +regGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro +regGCEA_MAM_CTRL2 = 0x14a9 # macro +regGCEA_MAM_CTRL2_BASE_IDX = 0 # macro +regGCEA_MAM_CTRL = 0x14ab # macro +regGCEA_MAM_CTRL_BASE_IDX = 0 # macro +regGCEA_EDC_CNT = 0x14b2 # macro +regGCEA_EDC_CNT_BASE_IDX = 0 # macro +regGCEA_EDC_CNT2 = 0x14b3 # macro +regGCEA_EDC_CNT2_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL = 0x14b4 # macro +regGCEA_DSM_CNTL_BASE_IDX = 0 # macro +regGCEA_DSM_CNTLA = 0x14b5 # macro +regGCEA_DSM_CNTLA_BASE_IDX = 0 # macro +regGCEA_DSM_CNTLB = 0x14b6 # macro +regGCEA_DSM_CNTLB_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL2 = 0x14b7 # macro +regGCEA_DSM_CNTL2_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL2A = 0x14b8 # macro +regGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL2B = 0x14b9 # macro +regGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro +regGCEA_GL2C_XBR_CREDITS = 0x14ba # macro +regGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro +regGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro +regGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro +regGCEA_PROBE_CNTL = 0x14bc # macro +regGCEA_PROBE_CNTL_BASE_IDX = 0 # macro +regGCEA_PROBE_MAP = 0x14bd # macro +regGCEA_PROBE_MAP_BASE_IDX = 0 # macro +regGCEA_ERR_STATUS = 0x14be # macro +regGCEA_ERR_STATUS_BASE_IDX = 0 # macro +regGCEA_MISC2 = 0x14bf # macro +regGCEA_MISC2_BASE_IDX = 0 # macro +regGCEA_RRET_MEM_RESERVE = 0x1518 # macro +regGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro +regGCEA_EDC_CNT3 = 0x151a # macro +regGCEA_EDC_CNT3_BASE_IDX = 0 # macro +regGCEA_SDP_ENABLE = 0x151e # macro +regGCEA_SDP_ENABLE_BASE_IDX = 0 # macro +regSPI_PQEV_CTRL = 0x14c0 # macro +regSPI_PQEV_CTRL_BASE_IDX = 0 # macro +regSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro +regSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro +regRMI_GENERAL_CNTL = 0x1880 # macro +regRMI_GENERAL_CNTL_BASE_IDX = 1 # macro +regRMI_GENERAL_CNTL1 = 0x1881 # macro +regRMI_GENERAL_CNTL1_BASE_IDX = 1 # macro +regRMI_GENERAL_STATUS = 0x1882 # macro +regRMI_GENERAL_STATUS_BASE_IDX = 1 # macro +regRMI_SUBBLOCK_STATUS0 = 0x1883 # macro +regRMI_SUBBLOCK_STATUS0_BASE_IDX = 1 # macro +regRMI_SUBBLOCK_STATUS1 = 0x1884 # macro +regRMI_SUBBLOCK_STATUS1_BASE_IDX = 1 # macro +regRMI_SUBBLOCK_STATUS2 = 0x1885 # macro +regRMI_SUBBLOCK_STATUS2_BASE_IDX = 1 # macro +regRMI_SUBBLOCK_STATUS3 = 0x1886 # macro +regRMI_SUBBLOCK_STATUS3_BASE_IDX = 1 # macro +regRMI_XBAR_CONFIG = 0x1887 # macro +regRMI_XBAR_CONFIG_BASE_IDX = 1 # macro +regRMI_PROBE_POP_LOGIC_CNTL = 0x1888 # macro +regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 1 # macro +regRMI_UTC_XNACK_N_MISC_CNTL = 0x1889 # macro +regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 1 # macro +regRMI_DEMUX_CNTL = 0x188a # macro +regRMI_DEMUX_CNTL_BASE_IDX = 1 # macro +regRMI_UTCL1_CNTL1 = 0x188b # macro +regRMI_UTCL1_CNTL1_BASE_IDX = 1 # macro +regRMI_UTCL1_CNTL2 = 0x188c # macro +regRMI_UTCL1_CNTL2_BASE_IDX = 1 # macro +regRMI_UTC_UNIT_CONFIG = 0x188d # macro +regRMI_UTC_UNIT_CONFIG_BASE_IDX = 1 # macro +regRMI_TCIW_FORMATTER0_CNTL = 0x188e # macro +regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 1 # macro +regRMI_TCIW_FORMATTER1_CNTL = 0x188f # macro +regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 1 # macro +regRMI_SCOREBOARD_CNTL = 0x1890 # macro +regRMI_SCOREBOARD_CNTL_BASE_IDX = 1 # macro +regRMI_SCOREBOARD_STATUS0 = 0x1891 # macro +regRMI_SCOREBOARD_STATUS0_BASE_IDX = 1 # macro +regRMI_SCOREBOARD_STATUS1 = 0x1892 # macro +regRMI_SCOREBOARD_STATUS1_BASE_IDX = 1 # macro +regRMI_SCOREBOARD_STATUS2 = 0x1893 # macro +regRMI_SCOREBOARD_STATUS2_BASE_IDX = 1 # macro +regRMI_XBAR_ARBITER_CONFIG = 0x1894 # macro +regRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 1 # macro +regRMI_XBAR_ARBITER_CONFIG_1 = 0x1895 # macro +regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 1 # macro +regRMI_CLOCK_CNTRL = 0x1896 # macro +regRMI_CLOCK_CNTRL_BASE_IDX = 1 # macro +regRMI_UTCL1_STATUS = 0x1897 # macro +regRMI_UTCL1_STATUS_BASE_IDX = 1 # macro +regRMI_RB_GLX_CID_MAP = 0x1898 # macro +regRMI_RB_GLX_CID_MAP_BASE_IDX = 1 # macro +regRMI_SPARE = 0x189f # macro +regRMI_SPARE_BASE_IDX = 1 # macro +regRMI_SPARE_1 = 0x18a0 # macro +regRMI_SPARE_1_BASE_IDX = 1 # macro +regRMI_SPARE_2 = 0x18a1 # macro +regRMI_SPARE_2_BASE_IDX = 1 # macro +regCC_RMI_REDUNDANCY = 0x18a2 # macro +regCC_RMI_REDUNDANCY_BASE_IDX = 1 # macro +regGCR_PIO_CNTL = 0x1580 # macro +regGCR_PIO_CNTL_BASE_IDX = 0 # macro +regGCR_PIO_DATA = 0x1581 # macro +regGCR_PIO_DATA_BASE_IDX = 0 # macro +regPMM_CNTL = 0x1582 # macro +regPMM_CNTL_BASE_IDX = 0 # macro +regPMM_STATUS = 0x1583 # macro +regPMM_STATUS_BASE_IDX = 0 # macro +regUTCL1_CTRL_1 = 0x158c # macro +regUTCL1_CTRL_1_BASE_IDX = 0 # macro +regUTCL1_ALOG = 0x158f # macro +regUTCL1_ALOG_BASE_IDX = 0 # macro +regUTCL1_STATUS = 0x1594 # macro +regUTCL1_STATUS_BASE_IDX = 0 # macro +regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x15a4 # macro +regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro +regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x15a5 # macro +regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro +regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x15a6 # macro +regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro +regGCMC_VM_FB_OFFSET = 0x15a7 # macro +regGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x15a8 # macro +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x15a9 # macro +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro +regGCMC_VM_STEERING = 0x15aa # macro +regGCMC_VM_STEERING_BASE_IDX = 0 # macro +regGCMC_MEM_POWER_LS = 0x15ac # macro +regGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x15ad # macro +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x15ae # macro +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x15af # macro +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 # macro +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x15b0 # macro +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 # macro +regGCMC_VM_APT_CNTL = 0x15b1 # macro +regGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro +regGCMC_VM_LOCAL_FB_ADDRESS_START = 0x15b2 # macro +regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 # macro +regGCMC_VM_LOCAL_FB_ADDRESS_END = 0x15b3 # macro +regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 # macro +regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x15b4 # macro +regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro +regGCUTCL2_ICG_CTRL = 0x15b5 # macro +regGCUTCL2_ICG_CTRL_BASE_IDX = 0 # macro +regGCUTCL2_CGTT_BUSY_CTRL = 0x15b7 # macro +regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro +regGCMC_VM_FB_NOALLOC_CNTL = 0x15b8 # macro +regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro +regGCUTCL2_HARVEST_BYPASS_GROUPS = 0x15b9 # macro +regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro +regGCUTCL2_GROUP_RET_FAULT_STATUS = 0x15bb # macro +regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 # macro +regGCVM_L2_CNTL = 0x15bc # macro +regGCVM_L2_CNTL_BASE_IDX = 0 # macro +regGCVM_L2_CNTL2 = 0x15bd # macro +regGCVM_L2_CNTL2_BASE_IDX = 0 # macro +regGCVM_L2_CNTL3 = 0x15be # macro +regGCVM_L2_CNTL3_BASE_IDX = 0 # macro +regGCVM_L2_STATUS = 0x15bf # macro +regGCVM_L2_STATUS_BASE_IDX = 0 # macro +regGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro +regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro +regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro +regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro +regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_CNTL = 0x15c3 # macro +regGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro +regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro +regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro +regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro +regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro +regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro +regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro +regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro +regGCVM_L2_CNTL4 = 0x15d4 # macro +regGCVM_L2_CNTL4_BASE_IDX = 0 # macro +regGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro +regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro +regGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro +regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro +regGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro +regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro +regGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro +regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro +regGCVM_L2_ICG_CTRL = 0x15d9 # macro +regGCVM_L2_ICG_CTRL_BASE_IDX = 0 # macro +regGCVM_L2_CNTL5 = 0x15da # macro +regGCVM_L2_CNTL5_BASE_IDX = 0 # macro +regGCVM_L2_GCR_CNTL = 0x15db # macro +regGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro +regGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15dc # macro +regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro +regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15dd # macro +regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro +regGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15de # macro +regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro +regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15df # macro +regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro +regGCVM_L2_CGTT_BUSY_CTRL = 0x15e0 # macro +regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro +regGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e1 # macro +regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro +regGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e2 # macro +regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x15e5 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x15e6 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x15e7 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x15e8 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro +regGCVM_L2_BANK_SELECT_MASKS = 0x15e9 # macro +regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 # macro +regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x15ea # macro +regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 # macro +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x15eb # macro +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 # macro +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x15ec # macro +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 # macro +regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x15ed # macro +regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 # macro +regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x15ee # macro +regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro +regGCMC_VM_FB_LOCATION_BASE = 0x1678 # macro +regGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro +regGCMC_VM_FB_LOCATION_TOP = 0x1679 # macro +regGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro +regGCMC_VM_AGP_TOP = 0x167a # macro +regGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro +regGCMC_VM_AGP_BOT = 0x167b # macro +regGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro +regGCMC_VM_AGP_BASE = 0x167c # macro +regGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro +regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x167d # macro +regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro +regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x167e # macro +regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro +regGCMC_VM_MX_L1_TLB_CNTL = 0x167f # macro +regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT0_CNTL = 0x1688 # macro +regGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT1_CNTL = 0x1689 # macro +regGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT2_CNTL = 0x168a # macro +regGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT3_CNTL = 0x168b # macro +regGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT4_CNTL = 0x168c # macro +regGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT5_CNTL = 0x168d # macro +regGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT6_CNTL = 0x168e # macro +regGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT7_CNTL = 0x168f # macro +regGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT8_CNTL = 0x1690 # macro +regGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT9_CNTL = 0x1691 # macro +regGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT10_CNTL = 0x1692 # macro +regGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT11_CNTL = 0x1693 # macro +regGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT12_CNTL = 0x1694 # macro +regGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT13_CNTL = 0x1695 # macro +regGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT14_CNTL = 0x1696 # macro +regGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXT15_CNTL = 0x1697 # macro +regGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro +regGCVM_CONTEXTS_DISABLE = 0x1698 # macro +regGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG0_SEM = 0x1699 # macro +regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG1_SEM = 0x169a # macro +regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG2_SEM = 0x169b # macro +regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG3_SEM = 0x169c # macro +regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG4_SEM = 0x169d # macro +regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG5_SEM = 0x169e # macro +regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG6_SEM = 0x169f # macro +regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG7_SEM = 0x16a0 # macro +regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG8_SEM = 0x16a1 # macro +regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG9_SEM = 0x16a2 # macro +regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG10_SEM = 0x16a3 # macro +regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG11_SEM = 0x16a4 # macro +regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG12_SEM = 0x16a5 # macro +regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG13_SEM = 0x16a6 # macro +regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG14_SEM = 0x16a7 # macro +regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG15_SEM = 0x16a8 # macro +regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG16_SEM = 0x16a9 # macro +regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG17_SEM = 0x16aa # macro +regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG0_REQ = 0x16ab # macro +regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG1_REQ = 0x16ac # macro +regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG2_REQ = 0x16ad # macro +regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG3_REQ = 0x16ae # macro +regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG4_REQ = 0x16af # macro +regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG5_REQ = 0x16b0 # macro +regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG6_REQ = 0x16b1 # macro +regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG7_REQ = 0x16b2 # macro +regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG8_REQ = 0x16b3 # macro +regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG9_REQ = 0x16b4 # macro +regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG10_REQ = 0x16b5 # macro +regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG11_REQ = 0x16b6 # macro +regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG12_REQ = 0x16b7 # macro +regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG13_REQ = 0x16b8 # macro +regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG14_REQ = 0x16b9 # macro +regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG15_REQ = 0x16ba # macro +regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG16_REQ = 0x16bb # macro +regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG17_REQ = 0x16bc # macro +regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG0_ACK = 0x16bd # macro +regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG1_ACK = 0x16be # macro +regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG2_ACK = 0x16bf # macro +regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG3_ACK = 0x16c0 # macro +regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG4_ACK = 0x16c1 # macro +regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG5_ACK = 0x16c2 # macro +regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG6_ACK = 0x16c3 # macro +regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG7_ACK = 0x16c4 # macro +regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG8_ACK = 0x16c5 # macro +regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG9_ACK = 0x16c6 # macro +regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG10_ACK = 0x16c7 # macro +regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG11_ACK = 0x16c8 # macro +regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG12_ACK = 0x16c9 # macro +regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG13_ACK = 0x16ca # macro +regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG14_ACK = 0x16cb # macro +regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG15_ACK = 0x16cc # macro +regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG16_ACK = 0x16cd # macro +regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG17_ACK = 0x16ce # macro +regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x16cf # macro +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x16d0 # macro +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x16d1 # macro +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x16d2 # macro +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x16d3 # macro +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x16d4 # macro +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x16d5 # macro +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x16d6 # macro +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x16d7 # macro +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x16d8 # macro +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x16d9 # macro +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x16da # macro +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x16db # macro +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x16dc # macro +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x16dd # macro +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x16de # macro +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x16df # macro +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x16e0 # macro +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x16e1 # macro +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x16e2 # macro +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x16e3 # macro +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x16e4 # macro +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x16e5 # macro +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x16e6 # macro +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x16e7 # macro +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x16e8 # macro +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x16e9 # macro +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x16ea # macro +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x16eb # macro +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x16ec # macro +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x16ed # macro +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x16ee # macro +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x16ef # macro +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x16f0 # macro +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x16f1 # macro +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x16f2 # macro +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f3 # macro +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f4 # macro +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f5 # macro +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f6 # macro +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f7 # macro +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f8 # macro +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f9 # macro +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fa # macro +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fb # macro +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fc # macro +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fd # macro +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fe # macro +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x16ff # macro +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1700 # macro +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1701 # macro +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1702 # macro +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1703 # macro +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1704 # macro +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1705 # macro +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x1706 # macro +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x1707 # macro +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x1708 # macro +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x1709 # macro +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x170a # macro +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x170b # macro +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x170c # macro +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x170d # macro +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x170e # macro +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x170f # macro +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1710 # macro +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1711 # macro +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1712 # macro +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1713 # macro +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1714 # macro +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1715 # macro +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x1716 # macro +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x1717 # macro +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x1718 # macro +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x1719 # macro +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x171a # macro +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x171b # macro +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x171c # macro +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x171d # macro +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x171e # macro +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x171f # macro +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1720 # macro +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1721 # macro +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1722 # macro +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1723 # macro +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1724 # macro +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1725 # macro +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x1726 # macro +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x1727 # macro +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x1728 # macro +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x1729 # macro +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x172a # macro +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x172b # macro +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x172c # macro +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x172d # macro +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x172e # macro +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x172f # macro +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x1730 # macro +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x1731 # macro +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x1732 # macro +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x1733 # macro +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x1734 # macro +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x1735 # macro +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x1736 # macro +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x1737 # macro +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x1738 # macro +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x1739 # macro +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x173a # macro +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x173b # macro +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x173c # macro +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x173d # macro +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x173e # macro +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x173f # macro +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x1740 # macro +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x1741 # macro +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x1742 # macro +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x1743 # macro +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x1744 # macro +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x1745 # macro +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x1746 # macro +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x1747 # macro +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x1748 # macro +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x1749 # macro +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x174a # macro +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x174b # macro +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x174c # macro +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x174d # macro +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x174e # macro +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x174f # macro +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x1750 # macro +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x1751 # macro +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x1752 # macro +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1753 # macro +regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1754 # macro +regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1755 # macro +regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1756 # macro +regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1757 # macro +regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1758 # macro +regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1759 # macro +regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175a # macro +regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175b # macro +regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175c # macro +regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175d # macro +regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175e # macro +regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175f # macro +regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1760 # macro +regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1761 # macro +regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1762 # macro +regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1763 # macro +regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regGCVML2_PERFCOUNTER2_0_LO = 0x34e0 # macro +regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_1_LO = 0x34e1 # macro +regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_0_HI = 0x34e2 # macro +regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_1_HI = 0x34e3 # macro +regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER_LO = 0x34e4 # macro +regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER_HI = 0x34e5 # macro +regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGCUTCL2_PERFCOUNTER_LO = 0x34e6 # macro +regGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGCUTCL2_PERFCOUNTER_HI = 0x34e7 # macro +regGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_0_SELECT = 0x3d20 # macro +regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_1_SELECT = 0x3d21 # macro +regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d22 # macro +regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d23 # macro +regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_0_MODE = 0x3d24 # macro +regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro +regGCVML2_PERFCOUNTER2_1_MODE = 0x3d25 # macro +regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d30 # macro +regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d31 # macro +regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d32 # macro +regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d33 # macro +regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d34 # macro +regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d35 # macro +regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d36 # macro +regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d37 # macro +regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro +regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d38 # macro +regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regGCUTCL2_PERFCOUNTER0_CFG = 0x3d39 # macro +regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regGCUTCL2_PERFCOUNTER1_CFG = 0x3d3a # macro +regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regGCUTCL2_PERFCOUNTER2_CFG = 0x3d3b # macro +regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro +regGCUTCL2_PERFCOUNTER3_CFG = 0x3d3c # macro +regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro +regGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d3d # macro +regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro +regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro +regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro +regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro +regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro +regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro +regGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro +regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro +regGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5e41 # macro +regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x5e44 # macro +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_0 = 0x5e48 # macro +regGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_1 = 0x5e49 # macro +regGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_2 = 0x5e4a # macro +regGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_3 = 0x5e4b # macro +regGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_4 = 0x5e4c # macro +regGCMC_VM_MARC_BASE_LO_4_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_5 = 0x5e4d # macro +regGCMC_VM_MARC_BASE_LO_5_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_6 = 0x5e4e # macro +regGCMC_VM_MARC_BASE_LO_6_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_7 = 0x5e4f # macro +regGCMC_VM_MARC_BASE_LO_7_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_8 = 0x5e50 # macro +regGCMC_VM_MARC_BASE_LO_8_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_9 = 0x5e51 # macro +regGCMC_VM_MARC_BASE_LO_9_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_10 = 0x5e52 # macro +regGCMC_VM_MARC_BASE_LO_10_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_11 = 0x5e53 # macro +regGCMC_VM_MARC_BASE_LO_11_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_12 = 0x5e54 # macro +regGCMC_VM_MARC_BASE_LO_12_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_13 = 0x5e55 # macro +regGCMC_VM_MARC_BASE_LO_13_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_14 = 0x5e56 # macro +regGCMC_VM_MARC_BASE_LO_14_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_LO_15 = 0x5e57 # macro +regGCMC_VM_MARC_BASE_LO_15_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_0 = 0x5e58 # macro +regGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_1 = 0x5e59 # macro +regGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_2 = 0x5e5a # macro +regGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_3 = 0x5e5b # macro +regGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_4 = 0x5e5c # macro +regGCMC_VM_MARC_BASE_HI_4_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_5 = 0x5e5d # macro +regGCMC_VM_MARC_BASE_HI_5_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_6 = 0x5e5e # macro +regGCMC_VM_MARC_BASE_HI_6_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_7 = 0x5e5f # macro +regGCMC_VM_MARC_BASE_HI_7_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_8 = 0x5e60 # macro +regGCMC_VM_MARC_BASE_HI_8_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_9 = 0x5e61 # macro +regGCMC_VM_MARC_BASE_HI_9_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_10 = 0x5e62 # macro +regGCMC_VM_MARC_BASE_HI_10_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_11 = 0x5e63 # macro +regGCMC_VM_MARC_BASE_HI_11_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_12 = 0x5e64 # macro +regGCMC_VM_MARC_BASE_HI_12_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_13 = 0x5e65 # macro +regGCMC_VM_MARC_BASE_HI_13_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_14 = 0x5e66 # macro +regGCMC_VM_MARC_BASE_HI_14_BASE_IDX = 1 # macro +regGCMC_VM_MARC_BASE_HI_15 = 0x5e67 # macro +regGCMC_VM_MARC_BASE_HI_15_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_0 = 0x5e68 # macro +regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_1 = 0x5e69 # macro +regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_2 = 0x5e6a # macro +regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_3 = 0x5e6b # macro +regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_4 = 0x5e6c # macro +regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_5 = 0x5e6d # macro +regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_6 = 0x5e6e # macro +regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_7 = 0x5e6f # macro +regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_8 = 0x5e70 # macro +regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_9 = 0x5e71 # macro +regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_10 = 0x5e72 # macro +regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_11 = 0x5e73 # macro +regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_12 = 0x5e74 # macro +regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_13 = 0x5e75 # macro +regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_14 = 0x5e76 # macro +regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_LO_15 = 0x5e77 # macro +regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_0 = 0x5e78 # macro +regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_1 = 0x5e79 # macro +regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_2 = 0x5e7a # macro +regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_3 = 0x5e7b # macro +regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_4 = 0x5e7c # macro +regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_5 = 0x5e7d # macro +regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_6 = 0x5e7e # macro +regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_7 = 0x5e7f # macro +regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_8 = 0x5e80 # macro +regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_9 = 0x5e81 # macro +regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_10 = 0x5e82 # macro +regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_11 = 0x5e83 # macro +regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_12 = 0x5e84 # macro +regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_13 = 0x5e85 # macro +regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_14 = 0x5e86 # macro +regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX = 1 # macro +regGCMC_VM_MARC_RELOC_HI_15 = 0x5e87 # macro +regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_0 = 0x5e88 # macro +regGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_1 = 0x5e89 # macro +regGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_2 = 0x5e8a # macro +regGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_3 = 0x5e8b # macro +regGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_4 = 0x5e8c # macro +regGCMC_VM_MARC_LEN_LO_4_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_5 = 0x5e8d # macro +regGCMC_VM_MARC_LEN_LO_5_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_6 = 0x5e8e # macro +regGCMC_VM_MARC_LEN_LO_6_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_7 = 0x5e8f # macro +regGCMC_VM_MARC_LEN_LO_7_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_8 = 0x5e90 # macro +regGCMC_VM_MARC_LEN_LO_8_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_9 = 0x5e91 # macro +regGCMC_VM_MARC_LEN_LO_9_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_10 = 0x5e92 # macro +regGCMC_VM_MARC_LEN_LO_10_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_11 = 0x5e93 # macro +regGCMC_VM_MARC_LEN_LO_11_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_12 = 0x5e94 # macro +regGCMC_VM_MARC_LEN_LO_12_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_13 = 0x5e95 # macro +regGCMC_VM_MARC_LEN_LO_13_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_14 = 0x5e96 # macro +regGCMC_VM_MARC_LEN_LO_14_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_LO_15 = 0x5e97 # macro +regGCMC_VM_MARC_LEN_LO_15_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_0 = 0x5e98 # macro +regGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_1 = 0x5e99 # macro +regGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_2 = 0x5e9a # macro +regGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_3 = 0x5e9b # macro +regGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_4 = 0x5e9c # macro +regGCMC_VM_MARC_LEN_HI_4_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_5 = 0x5e9d # macro +regGCMC_VM_MARC_LEN_HI_5_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_6 = 0x5e9e # macro +regGCMC_VM_MARC_LEN_HI_6_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_7 = 0x5e9f # macro +regGCMC_VM_MARC_LEN_HI_7_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_8 = 0x5ea0 # macro +regGCMC_VM_MARC_LEN_HI_8_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_9 = 0x5ea1 # macro +regGCMC_VM_MARC_LEN_HI_9_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_10 = 0x5ea2 # macro +regGCMC_VM_MARC_LEN_HI_10_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_11 = 0x5ea3 # macro +regGCMC_VM_MARC_LEN_HI_11_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_12 = 0x5ea4 # macro +regGCMC_VM_MARC_LEN_HI_12_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_13 = 0x5ea5 # macro +regGCMC_VM_MARC_LEN_HI_13_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_14 = 0x5ea6 # macro +regGCMC_VM_MARC_LEN_HI_14_BASE_IDX = 1 # macro +regGCMC_VM_MARC_LEN_HI_15 = 0x5ea7 # macro +regGCMC_VM_MARC_LEN_HI_15_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_0 = 0x5ea8 # macro +regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_1 = 0x5ea9 # macro +regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_2 = 0x5eaa # macro +regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_3 = 0x5eab # macro +regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_4 = 0x5eac # macro +regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_5 = 0x5ead # macro +regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_6 = 0x5eae # macro +regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_7 = 0x5eaf # macro +regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_8 = 0x5eb0 # macro +regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_9 = 0x5eb1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_10 = 0x5eb2 # macro +regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_11 = 0x5eb3 # macro +regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_12 = 0x5eb4 # macro +regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_13 = 0x5eb5 # macro +regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_14 = 0x5eb6 # macro +regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX = 1 # macro +regGCMC_VM_MARC_PFVF_MAPPING_15 = 0x5eb7 # macro +regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX = 1 # macro +regGCUTC_TRANSLATION_FAULT_CNTL0 = 0x5eb8 # macro +regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 1 # macro +regGCUTC_TRANSLATION_FAULT_CNTL1 = 0x5eb9 # macro +regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 1 # macro +regSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro +regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro +regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro +regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_PS = 0x19a8 # macro +regSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_PS = 0x19a9 # macro +regSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro +regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro +regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro +regSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro +regSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro +regSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro +regSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro +regSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro +regSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro +regSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro +regSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro +regSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro +regSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro +regSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro +regSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro +regSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro +regSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro +regSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro +regSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro +regSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro +regSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro +regSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro +regSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro +regSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro +regSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro +regSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro +regSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro +regSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro +regSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro +regSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro +regSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro +regSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro +regSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro +regSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro +regSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro +regSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro +regSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro +regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro +regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro +regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro +regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro +regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro +regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro +regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro +regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro +regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_GS = 0x1a28 # macro +regSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_GS = 0x1a29 # macro +regSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro +regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro +regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro +regSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro +regSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro +regSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro +regSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro +regSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro +regSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro +regSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro +regSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro +regSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro +regSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro +regSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro +regSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro +regSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro +regSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro +regSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro +regSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro +regSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro +regSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro +regSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro +regSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro +regSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro +regSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro +regSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro +regSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro +regSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro +regSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro +regSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro +regSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro +regSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro +regSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro +regSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro +regSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro +regSPI_SHADER_GS_MESHLET_DIM = 0x1a4c # macro +regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX = 0 # macro +regSPI_SHADER_GS_MESHLET_EXP_ALLOC = 0x1a4d # macro +regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX = 0 # macro +regSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro +regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro +regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro +regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro +regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro +regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_ES = 0x1a68 # macro +regSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_ES = 0x1a69 # macro +regSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro +regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro +regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro +regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro +regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro +regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro +regSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro +regSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro +regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro +regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro +regSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro +regSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro +regSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro +regSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro +regSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro +regSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro +regSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro +regSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro +regSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro +regSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro +regSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro +regSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro +regSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro +regSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro +regSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro +regSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro +regSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro +regSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro +regSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro +regSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro +regSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro +regSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro +regSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro +regSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro +regSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro +regSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro +regSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro +regSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro +regSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro +regSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro +regSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro +regSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro +regSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro +regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro +regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro +regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro +regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro +regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro +regSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro +regSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro +regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro +regCOMPUTE_DIM_X = 0x1ba1 # macro +regCOMPUTE_DIM_X_BASE_IDX = 0 # macro +regCOMPUTE_DIM_Y = 0x1ba2 # macro +regCOMPUTE_DIM_Y_BASE_IDX = 0 # macro +regCOMPUTE_DIM_Z = 0x1ba3 # macro +regCOMPUTE_DIM_Z_BASE_IDX = 0 # macro +regCOMPUTE_START_X = 0x1ba4 # macro +regCOMPUTE_START_X_BASE_IDX = 0 # macro +regCOMPUTE_START_Y = 0x1ba5 # macro +regCOMPUTE_START_Y_BASE_IDX = 0 # macro +regCOMPUTE_START_Z = 0x1ba6 # macro +regCOMPUTE_START_Z_BASE_IDX = 0 # macro +regCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro +regCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro +regCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro +regCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro +regCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro +regCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro +regCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro +regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro +regCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro +regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro +regCOMPUTE_PGM_LO = 0x1bac # macro +regCOMPUTE_PGM_LO_BASE_IDX = 0 # macro +regCOMPUTE_PGM_HI = 0x1bad # macro +regCOMPUTE_PGM_HI_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro +regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro +regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro +regCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro +regCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro +regCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro +regCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro +regCOMPUTE_VMID = 0x1bb4 # macro +regCOMPUTE_VMID_BASE_IDX = 0 # macro +regCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro +regCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro +regCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro +regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro +regCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro +regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro +regCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro +regCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro +regCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro +regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro +regCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro +regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro +regCOMPUTE_RESTART_X = 0x1bbb # macro +regCOMPUTE_RESTART_X_BASE_IDX = 0 # macro +regCOMPUTE_RESTART_Y = 0x1bbc # macro +regCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro +regCOMPUTE_RESTART_Z = 0x1bbd # macro +regCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro +regCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro +regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro +regCOMPUTE_MISC_RESERVED = 0x1bbf # macro +regCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_ID = 0x1bc0 # macro +regCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro +regCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro +regCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro +regCOMPUTE_REQ_CTRL = 0x1bc2 # macro +regCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro +regCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro +regCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro +regCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro +regCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro +regCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro +regCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro +regCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro +regCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro +regCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro +regCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro +regCOMPUTE_DDID_INDEX = 0x1bc9 # macro +regCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro +regCOMPUTE_SHADER_CHKSUM = 0x1bca # macro +regCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE4 = 0x1bcb # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE5 = 0x1bcc # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE6 = 0x1bcd # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE7 = 0x1bce # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_INTERLEAVE = 0x1bcf # macro +regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX = 0 # macro +regCOMPUTE_RELAUNCH = 0x1bd0 # macro +regCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bd1 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bd2 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro +regCOMPUTE_RELAUNCH2 = 0x1bd3 # macro +regCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_0 = 0x1be0 # macro +regCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_1 = 0x1be1 # macro +regCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_2 = 0x1be2 # macro +regCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_3 = 0x1be3 # macro +regCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_4 = 0x1be4 # macro +regCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_5 = 0x1be5 # macro +regCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_6 = 0x1be6 # macro +regCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_7 = 0x1be7 # macro +regCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_8 = 0x1be8 # macro +regCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_9 = 0x1be9 # macro +regCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_10 = 0x1bea # macro +regCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_11 = 0x1beb # macro +regCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_12 = 0x1bec # macro +regCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_13 = 0x1bed # macro +regCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_14 = 0x1bee # macro +regCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_15 = 0x1bef # macro +regCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro +regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_END = 0x1c1e # macro +regCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro +regCOMPUTE_NOWHERE = 0x1c1f # macro +regCOMPUTE_NOWHERE_BASE_IDX = 0 # macro +regSH_RESERVED_REG0 = 0x1c20 # macro +regSH_RESERVED_REG0_BASE_IDX = 0 # macro +regSH_RESERVED_REG1 = 0x1c21 # macro +regSH_RESERVED_REG1_BASE_IDX = 0 # macro +regCP_CU_MASK_ADDR_LO = 0x1dd2 # macro +regCP_CU_MASK_ADDR_LO_BASE_IDX = 0 # macro +regCP_CU_MASK_ADDR_HI = 0x1dd3 # macro +regCP_CU_MASK_ADDR_HI_BASE_IDX = 0 # macro +regCP_CU_MASK_CNTL = 0x1dd4 # macro +regCP_CU_MASK_CNTL_BASE_IDX = 0 # macro +regCP_EOPQ_WAIT_TIME = 0x1dd5 # macro +regCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro +regCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro +regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro +regCPC_INT_INFO = 0x1dd7 # macro +regCPC_INT_INFO_BASE_IDX = 0 # macro +regCP_VIRT_STATUS = 0x1dd8 # macro +regCP_VIRT_STATUS_BASE_IDX = 0 # macro +regCPC_INT_ADDR = 0x1dd9 # macro +regCPC_INT_ADDR_BASE_IDX = 0 # macro +regCPC_INT_PASID = 0x1dda # macro +regCPC_INT_PASID_BASE_IDX = 0 # macro +regCP_GFX_ERROR = 0x1ddb # macro +regCP_GFX_ERROR_BASE_IDX = 0 # macro +regCPG_UTCL1_CNTL = 0x1ddc # macro +regCPG_UTCL1_CNTL_BASE_IDX = 0 # macro +regCPC_UTCL1_CNTL = 0x1ddd # macro +regCPC_UTCL1_CNTL_BASE_IDX = 0 # macro +regCPF_UTCL1_CNTL = 0x1dde # macro +regCPF_UTCL1_CNTL_BASE_IDX = 0 # macro +regCP_AQL_SMM_STATUS = 0x1ddf # macro +regCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro +regCP_RB0_BASE = 0x1de0 # macro +regCP_RB0_BASE_BASE_IDX = 0 # macro +regCP_RB_BASE = 0x1de0 # macro +regCP_RB_BASE_BASE_IDX = 0 # macro +regCP_RB0_CNTL = 0x1de1 # macro +regCP_RB0_CNTL_BASE_IDX = 0 # macro +regCP_RB_CNTL = 0x1de1 # macro +regCP_RB_CNTL_BASE_IDX = 0 # macro +regCP_RB_RPTR_WR = 0x1de2 # macro +regCP_RB_RPTR_WR_BASE_IDX = 0 # macro +regCP_RB0_RPTR_ADDR = 0x1de3 # macro +regCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_RB_RPTR_ADDR = 0x1de3 # macro +regCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro +regCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB_RPTR_ADDR_HI = 0x1de4 # macro +regCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB0_BUFSZ_MASK = 0x1de5 # macro +regCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro +regCP_RB_BUFSZ_MASK = 0x1de5 # macro +regCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro +regCP_INT_CNTL = 0x1de9 # macro +regCP_INT_CNTL_BASE_IDX = 0 # macro +regCP_INT_STATUS = 0x1dea # macro +regCP_INT_STATUS_BASE_IDX = 0 # macro +regCP_DEVICE_ID = 0x1deb # macro +regCP_DEVICE_ID_BASE_IDX = 0 # macro +regCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro +regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_RING_PRIORITY_CNTS = 0x1dec # macro +regCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_ME0_PIPE0_PRIORITY = 0x1ded # macro +regCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro +regCP_RING0_PRIORITY = 0x1ded # macro +regCP_RING0_PRIORITY_BASE_IDX = 0 # macro +regCP_ME0_PIPE1_PRIORITY = 0x1dee # macro +regCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro +regCP_RING1_PRIORITY = 0x1dee # macro +regCP_RING1_PRIORITY_BASE_IDX = 0 # macro +regCP_FATAL_ERROR = 0x1df0 # macro +regCP_FATAL_ERROR_BASE_IDX = 0 # macro +regCP_RB_VMID = 0x1df1 # macro +regCP_RB_VMID_BASE_IDX = 0 # macro +regCP_ME0_PIPE0_VMID = 0x1df2 # macro +regCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro +regCP_ME0_PIPE1_VMID = 0x1df3 # macro +regCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro +regCP_RB0_WPTR = 0x1df4 # macro +regCP_RB0_WPTR_BASE_IDX = 0 # macro +regCP_RB_WPTR = 0x1df4 # macro +regCP_RB_WPTR_BASE_IDX = 0 # macro +regCP_RB0_WPTR_HI = 0x1df5 # macro +regCP_RB0_WPTR_HI_BASE_IDX = 0 # macro +regCP_RB_WPTR_HI = 0x1df5 # macro +regCP_RB_WPTR_HI_BASE_IDX = 0 # macro +regCP_RB1_WPTR = 0x1df6 # macro +regCP_RB1_WPTR_BASE_IDX = 0 # macro +regCP_RB1_WPTR_HI = 0x1df7 # macro +regCP_RB1_WPTR_HI_BASE_IDX = 0 # macro +regCP_PROCESS_QUANTUM = 0x1df9 # macro +regCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro +regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro +regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro +regCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro +regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro +regCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro +regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro +regCPG_UTCL1_ERROR = 0x1dfe # macro +regCPG_UTCL1_ERROR_BASE_IDX = 0 # macro +regCPC_UTCL1_ERROR = 0x1dff # macro +regCPC_UTCL1_ERROR_BASE_IDX = 0 # macro +regCP_RB1_BASE = 0x1e00 # macro +regCP_RB1_BASE_BASE_IDX = 0 # macro +regCP_RB1_CNTL = 0x1e01 # macro +regCP_RB1_CNTL_BASE_IDX = 0 # macro +regCP_RB1_RPTR_ADDR = 0x1e02 # macro +regCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro +regCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB1_BUFSZ_MASK = 0x1e04 # macro +regCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro +regCP_INT_CNTL_RING0 = 0x1e0a # macro +regCP_INT_CNTL_RING0_BASE_IDX = 0 # macro +regCP_INT_CNTL_RING1 = 0x1e0b # macro +regCP_INT_CNTL_RING1_BASE_IDX = 0 # macro +regCP_INT_STATUS_RING0 = 0x1e0d # macro +regCP_INT_STATUS_RING0_BASE_IDX = 0 # macro +regCP_INT_STATUS_RING1 = 0x1e0e # macro +regCP_INT_STATUS_RING1_BASE_IDX = 0 # macro +regCP_ME_F32_INTERRUPT = 0x1e13 # macro +regCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_PFP_F32_INTERRUPT = 0x1e14 # macro +regCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_MEC1_F32_INTERRUPT = 0x1e16 # macro +regCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_MEC2_F32_INTERRUPT = 0x1e17 # macro +regCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_PWR_CNTL = 0x1e18 # macro +regCP_PWR_CNTL_BASE_IDX = 0 # macro +regCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro +regCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro +regCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro +regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro +regCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro +regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro +regGB_EDC_MODE = 0x1e1e # macro +regGB_EDC_MODE_BASE_IDX = 0 # macro +regCP_DEBUG = 0x1e1f # macro +regCP_DEBUG_BASE_IDX = 0 # macro +regCP_CPC_DEBUG = 0x1e21 # macro +regCP_CPC_DEBUG_BASE_IDX = 0 # macro +regCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro +regCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +regCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro +regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro +regCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro +regCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro +regCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro +regCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro +regCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro +regCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro +regCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro +regCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro +regCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro +regCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro +regCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro +regCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro +regCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro +regCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro +regCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro +regCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro +regCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro +regCP_GFX_QUEUE_INDEX = 0x1e37 # macro +regCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro +regCC_GC_EDC_CONFIG = 0x1e38 # macro +regCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro +regCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro +regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro +regCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro +regCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro +regCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro +regCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro +regCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro +regCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro +regCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro +regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro +regCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro +regCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro +regCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro +regCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro +regCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro +regCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_ME_PRGRM_CNTR_START = 0x1e45 # macro +regCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro +regCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro +regCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro +regCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_ME_INTR_ROUTINE_START = 0x1e4a # macro +regCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro +regCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro +regCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_CONTEXT_CNTL = 0x1e4d # macro +regCP_CONTEXT_CNTL_BASE_IDX = 0 # macro +regCP_MAX_CONTEXT = 0x1e4e # macro +regCP_MAX_CONTEXT_BASE_IDX = 0 # macro +regCP_IQ_WAIT_TIME1 = 0x1e4f # macro +regCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro +regCP_IQ_WAIT_TIME2 = 0x1e50 # macro +regCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro +regCP_RB0_BASE_HI = 0x1e51 # macro +regCP_RB0_BASE_HI_BASE_IDX = 0 # macro +regCP_RB1_BASE_HI = 0x1e52 # macro +regCP_RB1_BASE_HI_BASE_IDX = 0 # macro +regCP_VMID_RESET = 0x1e53 # macro +regCP_VMID_RESET_BASE_IDX = 0 # macro +regCPC_INT_CNTL = 0x1e54 # macro +regCPC_INT_CNTL_BASE_IDX = 0 # macro +regCPC_INT_STATUS = 0x1e55 # macro +regCPC_INT_STATUS_BASE_IDX = 0 # macro +regCP_VMID_PREEMPT = 0x1e56 # macro +regCP_VMID_PREEMPT_BASE_IDX = 0 # macro +regCPC_INT_CNTX_ID = 0x1e57 # macro +regCPC_INT_CNTX_ID_BASE_IDX = 0 # macro +regCP_PQ_STATUS = 0x1e58 # macro +regCP_PQ_STATUS_BASE_IDX = 0 # macro +regCP_PFP_PRGRM_CNTR_START_HI = 0x1e59 # macro +regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro +regCP_MAX_DRAW_COUNT = 0x1e5c # macro +regCP_MAX_DRAW_COUNT_BASE_IDX = 0 # macro +regCP_MEC1_F32_INT_DIS = 0x1e5d # macro +regCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro +regCP_MEC2_F32_INT_DIS = 0x1e5e # macro +regCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro +regCP_VMID_STATUS = 0x1e5f # macro +regCP_VMID_STATUS_BASE_IDX = 0 # macro +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro +regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro +regCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro +regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro +regCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro +regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro +regCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro +regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro +regCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro +regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro +regCPC_OS_PIPES = 0x1e67 # macro +regCPC_OS_PIPES_BASE_IDX = 0 # macro +regCP_SUSPEND_RESUME_REQ = 0x1e68 # macro +regCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro +regCP_SUSPEND_CNTL = 0x1e69 # macro +regCP_SUSPEND_CNTL_BASE_IDX = 0 # macro +regCP_IQ_WAIT_TIME3 = 0x1e6a # macro +regCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro +regCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro +regCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro +regCP_DDID_BASE_ADDR_LO = 0x1e6b # macro +regCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro +regCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro +regCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_DDID_BASE_ADDR_HI = 0x1e6c # macro +regCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCPC_DDID_CNTL = 0x1e6d # macro +regCPC_DDID_CNTL_BASE_IDX = 0 # macro +regCP_DDID_CNTL = 0x1e6d # macro +regCP_DDID_CNTL_BASE_IDX = 0 # macro +regCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro +regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro +regCP_GFX_DDID_WPTR = 0x1e6f # macro +regCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro +regCP_GFX_DDID_RPTR = 0x1e70 # macro +regCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro +regCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro +regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro +regCP_GFX_HPD_STATUS0 = 0x1e72 # macro +regCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro +regCP_GFX_HPD_CONTROL0 = 0x1e73 # macro +regCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro +regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro +regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro +regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro +regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro +regCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro +regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro +regCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro +regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro +regCP_GFX_INDEX_MUTEX = 0x1e78 # macro +regCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro +regCP_ME_PRGRM_CNTR_START_HI = 0x1e79 # macro +regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro +regCP_PFP_INTR_ROUTINE_START_HI = 0x1e7a # macro +regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro +regCP_ME_INTR_ROUTINE_START_HI = 0x1e7b # macro +regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro +regCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro +regCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro +regCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro +regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_GFX_HQD_ACTIVE = 0x1e80 # macro +regCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro +regCP_GFX_HQD_VMID = 0x1e81 # macro +regCP_GFX_HQD_VMID_BASE_IDX = 0 # macro +regCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro +regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro +regCP_GFX_HQD_QUANTUM = 0x1e85 # macro +regCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro +regCP_GFX_HQD_BASE = 0x1e86 # macro +regCP_GFX_HQD_BASE_BASE_IDX = 0 # macro +regCP_GFX_HQD_BASE_HI = 0x1e87 # macro +regCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro +regCP_GFX_HQD_RPTR = 0x1e88 # macro +regCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro +regCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro +regCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro +regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro +regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro +regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL = 0x1e8d # macro +regCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro +regCP_GFX_HQD_OFFSET = 0x1e8e # macro +regCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro +regCP_GFX_HQD_CNTL = 0x1e8f # macro +regCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro +regCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro +regCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro +regCP_GFX_HQD_WPTR = 0x1e91 # macro +regCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro +regCP_GFX_HQD_WPTR_HI = 0x1e92 # macro +regCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro +regCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro +regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro +regCP_GFX_HQD_MAPPED = 0x1e94 # macro +regCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro +regCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro +regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro +regCP_GFX_HQD_IQ_TIMER = 0x1e96 # macro +regCP_GFX_HQD_IQ_TIMER_BASE_IDX = 0 # macro +regCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro +regCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro +regCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro +regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro +regCP_GFX_MQD_CONTROL = 0x1e9a # macro +regCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_GFX_CONTROL = 0x1e9f # macro +regCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_GFX_STATUS = 0x1ea0 # macro +regCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro +regCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro +regCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro +regCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro +regCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro +regCP_DMA_WATCH0_MASK = 0x1ec2 # macro +regCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro +regCP_DMA_WATCH0_CNTL = 0x1ec3 # macro +regCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro +regCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro +regCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro +regCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro +regCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro +regCP_DMA_WATCH1_MASK = 0x1ec6 # macro +regCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro +regCP_DMA_WATCH1_CNTL = 0x1ec7 # macro +regCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro +regCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro +regCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro +regCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro +regCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro +regCP_DMA_WATCH2_MASK = 0x1eca # macro +regCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro +regCP_DMA_WATCH2_CNTL = 0x1ecb # macro +regCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro +regCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro +regCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro +regCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro +regCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro +regCP_DMA_WATCH3_MASK = 0x1ece # macro +regCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro +regCP_DMA_WATCH3_CNTL = 0x1ecf # macro +regCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro +regCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro +regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro +regCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro +regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro +regCP_DMA_WATCH_STAT = 0x1ed2 # macro +regCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro +regCP_PFP_JT_STAT = 0x1ed3 # macro +regCP_PFP_JT_STAT_BASE_IDX = 0 # macro +regCP_MEC_JT_STAT = 0x1ed5 # macro +regCP_MEC_JT_STAT_BASE_IDX = 0 # macro +regCP_CPC_BUSY_HYSTERESIS = 0x1edb # macro +regCP_CPC_BUSY_HYSTERESIS_BASE_IDX = 0 # macro +regCP_CPF_BUSY_HYSTERESIS1 = 0x1edc # macro +regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro +regCP_CPF_BUSY_HYSTERESIS2 = 0x1edd # macro +regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro +regCP_CPG_BUSY_HYSTERESIS1 = 0x1ede # macro +regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro +regCP_CPG_BUSY_HYSTERESIS2 = 0x1edf # macro +regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CLEAR = 0x1f28 # macro +regCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro +regCP_RB0_ACTIVE = 0x1f40 # macro +regCP_RB0_ACTIVE_BASE_IDX = 0 # macro +regCP_RB_ACTIVE = 0x1f40 # macro +regCP_RB_ACTIVE_BASE_IDX = 0 # macro +regCP_RB1_ACTIVE = 0x1f41 # macro +regCP_RB1_ACTIVE_BASE_IDX = 0 # macro +regCP_RB_STATUS = 0x1f43 # macro +regCP_RB_STATUS_BASE_IDX = 0 # macro +regCPG_RCIU_CAM_INDEX = 0x1f44 # macro +regCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro +regCPG_RCIU_CAM_DATA = 0x1f45 # macro +regCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro +regCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro +regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro +regCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro +regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro +regCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro +regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro +regCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro +regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro +regCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro +regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro +regCP_SDMA_DMA_DONE = 0x1f4e # macro +regCP_SDMA_DMA_DONE_BASE_IDX = 0 # macro +regCP_PFP_SDMA_CS = 0x1f4f # macro +regCP_PFP_SDMA_CS_BASE_IDX = 0 # macro +regCP_ME_SDMA_CS = 0x1f50 # macro +regCP_ME_SDMA_CS_BASE_IDX = 0 # macro +regCPF_GCR_CNTL = 0x1f53 # macro +regCPF_GCR_CNTL_BASE_IDX = 0 # macro +regCPG_UTCL1_STATUS = 0x1f54 # macro +regCPG_UTCL1_STATUS_BASE_IDX = 0 # macro +regCPC_UTCL1_STATUS = 0x1f55 # macro +regCPC_UTCL1_STATUS_BASE_IDX = 0 # macro +regCPF_UTCL1_STATUS = 0x1f56 # macro +regCPF_UTCL1_STATUS_BASE_IDX = 0 # macro +regCP_SD_CNTL = 0x1f57 # macro +regCP_SD_CNTL_BASE_IDX = 0 # macro +regCP_SOFT_RESET_CNTL = 0x1f59 # macro +regCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro +regCP_CPC_GFX_CNTL = 0x1f5a # macro +regCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro +regSPI_ARB_PRIORITY = 0x1f60 # macro +regSPI_ARB_PRIORITY_BASE_IDX = 0 # macro +regSPI_ARB_CYCLES_0 = 0x1f61 # macro +regSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro +regSPI_ARB_CYCLES_1 = 0x1f62 # macro +regSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro +regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro +regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro +regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro +regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro +regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro +regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS4 = 0x1f6d # macro +regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS5 = 0x1f6e # macro +regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS6 = 0x1f6f # macro +regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS7 = 0x1f70 # macro +regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX = 0 # macro +regSPI_USER_ACCUM_VMID_CNTL = 0x1f71 # macro +regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro +regSPI_GDBG_PER_VMID_CNTL = 0x1f72 # macro +regSPI_GDBG_PER_VMID_CNTL_BASE_IDX = 0 # macro +regSPI_COMPUTE_QUEUE_RESET = 0x1f73 # macro +regSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro +regSPI_COMPUTE_WF_CTX_SAVE = 0x1f74 # macro +regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro +regCP_HPD_UTCL1_CNTL = 0x1fa3 # macro +regCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro +regCP_HPD_UTCL1_ERROR = 0x1fa7 # macro +regCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro +regCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro +regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro +regCP_MQD_BASE_ADDR = 0x1fa9 # macro +regCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro +regCP_MQD_BASE_ADDR_HI = 0x1faa # macro +regCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_ACTIVE = 0x1fab # macro +regCP_HQD_ACTIVE_BASE_IDX = 0 # macro +regCP_HQD_VMID = 0x1fac # macro +regCP_HQD_VMID_BASE_IDX = 0 # macro +regCP_HQD_PERSISTENT_STATE = 0x1fad # macro +regCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro +regCP_HQD_PIPE_PRIORITY = 0x1fae # macro +regCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro +regCP_HQD_QUEUE_PRIORITY = 0x1faf # macro +regCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro +regCP_HQD_QUANTUM = 0x1fb0 # macro +regCP_HQD_QUANTUM_BASE_IDX = 0 # macro +regCP_HQD_PQ_BASE = 0x1fb1 # macro +regCP_HQD_PQ_BASE_BASE_IDX = 0 # macro +regCP_HQD_PQ_BASE_HI = 0x1fb2 # macro +regCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro +regCP_HQD_PQ_RPTR = 0x1fb3 # macro +regCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro +regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_PQ_CONTROL = 0x1fba # macro +regCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_IB_BASE_ADDR = 0x1fbb # macro +regCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro +regCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro +regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_IB_RPTR = 0x1fbd # macro +regCP_HQD_IB_RPTR_BASE_IDX = 0 # macro +regCP_HQD_IB_CONTROL = 0x1fbe # macro +regCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_IQ_TIMER = 0x1fbf # macro +regCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro +regCP_HQD_IQ_RPTR = 0x1fc0 # macro +regCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro +regCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro +regCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro +regCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro +regCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro +regCP_HQD_OFFLOAD = 0x1fc2 # macro +regCP_HQD_OFFLOAD_BASE_IDX = 0 # macro +regCP_HQD_SEMA_CMD = 0x1fc3 # macro +regCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro +regCP_HQD_MSG_TYPE = 0x1fc4 # macro +regCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro +regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro +regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro +regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro +regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro +regCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro +regCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro +regCP_HQD_HQ_STATUS0 = 0x1fc9 # macro +regCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro +regCP_HQD_HQ_CONTROL0 = 0x1fca # macro +regCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro +regCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro +regCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro +regCP_MQD_CONTROL = 0x1fcb # macro +regCP_MQD_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_HQ_STATUS1 = 0x1fcc # macro +regCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro +regCP_HQD_HQ_CONTROL1 = 0x1fcd # macro +regCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro +regCP_HQD_EOP_BASE_ADDR = 0x1fce # macro +regCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro +regCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro +regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_EOP_CONTROL = 0x1fd0 # macro +regCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_EOP_RPTR = 0x1fd1 # macro +regCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro +regCP_HQD_EOP_WPTR = 0x1fd2 # macro +regCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro +regCP_HQD_EOP_EVENTS = 0x1fd3 # macro +regCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro +regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro +regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro +regCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro +regCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro +regCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro +regCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro +regCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro +regCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro +regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro +regCP_HQD_ERROR = 0x1fdc # macro +regCP_HQD_ERROR_BASE_IDX = 0 # macro +regCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro +regCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro +regCP_HQD_AQL_CONTROL = 0x1fde # macro +regCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_LO = 0x1fdf # macro +regCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro +regCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro +regCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro +regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro +regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro +regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro +regCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro +regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro +regCP_HQD_DDID_RPTR = 0x1fe4 # macro +regCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro +regCP_HQD_DDID_WPTR = 0x1fe5 # macro +regCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro +regCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro +regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro +regCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro +regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro +regCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro +regCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro +regTCP_WATCH0_ADDR_H = 0x2048 # macro +regTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH0_ADDR_L = 0x2049 # macro +regTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH0_CNTL = 0x204a # macro +regTCP_WATCH0_CNTL_BASE_IDX = 0 # macro +regTCP_WATCH1_ADDR_H = 0x204b # macro +regTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH1_ADDR_L = 0x204c # macro +regTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH1_CNTL = 0x204d # macro +regTCP_WATCH1_CNTL_BASE_IDX = 0 # macro +regTCP_WATCH2_ADDR_H = 0x204e # macro +regTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH2_ADDR_L = 0x204f # macro +regTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH2_CNTL = 0x2050 # macro +regTCP_WATCH2_CNTL_BASE_IDX = 0 # macro +regTCP_WATCH3_ADDR_H = 0x2051 # macro +regTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH3_ADDR_L = 0x2052 # macro +regTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH3_CNTL = 0x2053 # macro +regTCP_WATCH3_CNTL_BASE_IDX = 0 # macro +regGDS_VMID0_BASE = 0x20a0 # macro +regGDS_VMID0_BASE_BASE_IDX = 0 # macro +regGDS_VMID0_SIZE = 0x20a1 # macro +regGDS_VMID0_SIZE_BASE_IDX = 0 # macro +regGDS_VMID1_BASE = 0x20a2 # macro +regGDS_VMID1_BASE_BASE_IDX = 0 # macro +regGDS_VMID1_SIZE = 0x20a3 # macro +regGDS_VMID1_SIZE_BASE_IDX = 0 # macro +regGDS_VMID2_BASE = 0x20a4 # macro +regGDS_VMID2_BASE_BASE_IDX = 0 # macro +regGDS_VMID2_SIZE = 0x20a5 # macro +regGDS_VMID2_SIZE_BASE_IDX = 0 # macro +regGDS_VMID3_BASE = 0x20a6 # macro +regGDS_VMID3_BASE_BASE_IDX = 0 # macro +regGDS_VMID3_SIZE = 0x20a7 # macro +regGDS_VMID3_SIZE_BASE_IDX = 0 # macro +regGDS_VMID4_BASE = 0x20a8 # macro +regGDS_VMID4_BASE_BASE_IDX = 0 # macro +regGDS_VMID4_SIZE = 0x20a9 # macro +regGDS_VMID4_SIZE_BASE_IDX = 0 # macro +regGDS_VMID5_BASE = 0x20aa # macro +regGDS_VMID5_BASE_BASE_IDX = 0 # macro +regGDS_VMID5_SIZE = 0x20ab # macro +regGDS_VMID5_SIZE_BASE_IDX = 0 # macro +regGDS_VMID6_BASE = 0x20ac # macro +regGDS_VMID6_BASE_BASE_IDX = 0 # macro +regGDS_VMID6_SIZE = 0x20ad # macro +regGDS_VMID6_SIZE_BASE_IDX = 0 # macro +regGDS_VMID7_BASE = 0x20ae # macro +regGDS_VMID7_BASE_BASE_IDX = 0 # macro +regGDS_VMID7_SIZE = 0x20af # macro +regGDS_VMID7_SIZE_BASE_IDX = 0 # macro +regGDS_VMID8_BASE = 0x20b0 # macro +regGDS_VMID8_BASE_BASE_IDX = 0 # macro +regGDS_VMID8_SIZE = 0x20b1 # macro +regGDS_VMID8_SIZE_BASE_IDX = 0 # macro +regGDS_VMID9_BASE = 0x20b2 # macro +regGDS_VMID9_BASE_BASE_IDX = 0 # macro +regGDS_VMID9_SIZE = 0x20b3 # macro +regGDS_VMID9_SIZE_BASE_IDX = 0 # macro +regGDS_VMID10_BASE = 0x20b4 # macro +regGDS_VMID10_BASE_BASE_IDX = 0 # macro +regGDS_VMID10_SIZE = 0x20b5 # macro +regGDS_VMID10_SIZE_BASE_IDX = 0 # macro +regGDS_VMID11_BASE = 0x20b6 # macro +regGDS_VMID11_BASE_BASE_IDX = 0 # macro +regGDS_VMID11_SIZE = 0x20b7 # macro +regGDS_VMID11_SIZE_BASE_IDX = 0 # macro +regGDS_VMID12_BASE = 0x20b8 # macro +regGDS_VMID12_BASE_BASE_IDX = 0 # macro +regGDS_VMID12_SIZE = 0x20b9 # macro +regGDS_VMID12_SIZE_BASE_IDX = 0 # macro +regGDS_VMID13_BASE = 0x20ba # macro +regGDS_VMID13_BASE_BASE_IDX = 0 # macro +regGDS_VMID13_SIZE = 0x20bb # macro +regGDS_VMID13_SIZE_BASE_IDX = 0 # macro +regGDS_VMID14_BASE = 0x20bc # macro +regGDS_VMID14_BASE_BASE_IDX = 0 # macro +regGDS_VMID14_SIZE = 0x20bd # macro +regGDS_VMID14_SIZE_BASE_IDX = 0 # macro +regGDS_VMID15_BASE = 0x20be # macro +regGDS_VMID15_BASE_BASE_IDX = 0 # macro +regGDS_VMID15_SIZE = 0x20bf # macro +regGDS_VMID15_SIZE_BASE_IDX = 0 # macro +regGDS_GWS_VMID0 = 0x20c0 # macro +regGDS_GWS_VMID0_BASE_IDX = 0 # macro +regGDS_GWS_VMID1 = 0x20c1 # macro +regGDS_GWS_VMID1_BASE_IDX = 0 # macro +regGDS_GWS_VMID2 = 0x20c2 # macro +regGDS_GWS_VMID2_BASE_IDX = 0 # macro +regGDS_GWS_VMID3 = 0x20c3 # macro +regGDS_GWS_VMID3_BASE_IDX = 0 # macro +regGDS_GWS_VMID4 = 0x20c4 # macro +regGDS_GWS_VMID4_BASE_IDX = 0 # macro +regGDS_GWS_VMID5 = 0x20c5 # macro +regGDS_GWS_VMID5_BASE_IDX = 0 # macro +regGDS_GWS_VMID6 = 0x20c6 # macro +regGDS_GWS_VMID6_BASE_IDX = 0 # macro +regGDS_GWS_VMID7 = 0x20c7 # macro +regGDS_GWS_VMID7_BASE_IDX = 0 # macro +regGDS_GWS_VMID8 = 0x20c8 # macro +regGDS_GWS_VMID8_BASE_IDX = 0 # macro +regGDS_GWS_VMID9 = 0x20c9 # macro +regGDS_GWS_VMID9_BASE_IDX = 0 # macro +regGDS_GWS_VMID10 = 0x20ca # macro +regGDS_GWS_VMID10_BASE_IDX = 0 # macro +regGDS_GWS_VMID11 = 0x20cb # macro +regGDS_GWS_VMID11_BASE_IDX = 0 # macro +regGDS_GWS_VMID12 = 0x20cc # macro +regGDS_GWS_VMID12_BASE_IDX = 0 # macro +regGDS_GWS_VMID13 = 0x20cd # macro +regGDS_GWS_VMID13_BASE_IDX = 0 # macro +regGDS_GWS_VMID14 = 0x20ce # macro +regGDS_GWS_VMID14_BASE_IDX = 0 # macro +regGDS_GWS_VMID15 = 0x20cf # macro +regGDS_GWS_VMID15_BASE_IDX = 0 # macro +regGDS_OA_VMID0 = 0x20d0 # macro +regGDS_OA_VMID0_BASE_IDX = 0 # macro +regGDS_OA_VMID1 = 0x20d1 # macro +regGDS_OA_VMID1_BASE_IDX = 0 # macro +regGDS_OA_VMID2 = 0x20d2 # macro +regGDS_OA_VMID2_BASE_IDX = 0 # macro +regGDS_OA_VMID3 = 0x20d3 # macro +regGDS_OA_VMID3_BASE_IDX = 0 # macro +regGDS_OA_VMID4 = 0x20d4 # macro +regGDS_OA_VMID4_BASE_IDX = 0 # macro +regGDS_OA_VMID5 = 0x20d5 # macro +regGDS_OA_VMID5_BASE_IDX = 0 # macro +regGDS_OA_VMID6 = 0x20d6 # macro +regGDS_OA_VMID6_BASE_IDX = 0 # macro +regGDS_OA_VMID7 = 0x20d7 # macro +regGDS_OA_VMID7_BASE_IDX = 0 # macro +regGDS_OA_VMID8 = 0x20d8 # macro +regGDS_OA_VMID8_BASE_IDX = 0 # macro +regGDS_OA_VMID9 = 0x20d9 # macro +regGDS_OA_VMID9_BASE_IDX = 0 # macro +regGDS_OA_VMID10 = 0x20da # macro +regGDS_OA_VMID10_BASE_IDX = 0 # macro +regGDS_OA_VMID11 = 0x20db # macro +regGDS_OA_VMID11_BASE_IDX = 0 # macro +regGDS_OA_VMID12 = 0x20dc # macro +regGDS_OA_VMID12_BASE_IDX = 0 # macro +regGDS_OA_VMID13 = 0x20dd # macro +regGDS_OA_VMID13_BASE_IDX = 0 # macro +regGDS_OA_VMID14 = 0x20de # macro +regGDS_OA_VMID14_BASE_IDX = 0 # macro +regGDS_OA_VMID15 = 0x20df # macro +regGDS_OA_VMID15_BASE_IDX = 0 # macro +regGDS_GWS_RESET0 = 0x20e4 # macro +regGDS_GWS_RESET0_BASE_IDX = 0 # macro +regGDS_GWS_RESET1 = 0x20e5 # macro +regGDS_GWS_RESET1_BASE_IDX = 0 # macro +regGDS_GWS_RESOURCE_RESET = 0x20e6 # macro +regGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro +regGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro +regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro +regGDS_OA_RESET_MASK = 0x20e9 # macro +regGDS_OA_RESET_MASK_BASE_IDX = 0 # macro +regGDS_OA_RESET = 0x20ea # macro +regGDS_OA_RESET_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_STATUS = 0x20ed # macro +regGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT0 = 0x20ee # macro +regGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT1 = 0x20ef # macro +regGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT2 = 0x20f0 # macro +regGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT3 = 0x20f1 # macro +regGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_GFX_CTXSW_STATUS = 0x20f2 # macro +regGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro +regGDS_PS_CTXSW_CNT0 = 0x20f7 # macro +regGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS_CTXSW_CNT1 = 0x20f8 # macro +regGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS_CTXSW_CNT2 = 0x20f9 # macro +regGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS_CTXSW_CNT3 = 0x20fa # macro +regGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS_CTXSW_IDX = 0x20fb # macro +regGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT0 = 0x2117 # macro +regGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT1 = 0x2118 # macro +regGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT2 = 0x2119 # macro +regGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT3 = 0x211a # macro +regGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_MEMORY_CLEAN = 0x211f # macro +regGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro +regGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro +regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro +regGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro +regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro +regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro +regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro +regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro +regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro +regGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro +regGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_FIXED = 0x2c08 # macro +regGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_FIXED = 0x2c09 # macro +regGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro +regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro +regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro +regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro +regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro +regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro +regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro +regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro +regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro +regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro +regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro +regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro +regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro +regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro +regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro +regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro +regGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro +regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro +regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro +regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro +regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro +regGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro +regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro +regGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro +regGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro +regGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro +regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro +regGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro +regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUEUING = 0x2c22 # macro +regGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_FIXED = 0x2c23 # macro +regGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro +regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro +regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro +regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro +regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro +regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro +regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro +regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro +regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro +regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro +regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro +regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro +regGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro +regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro +regGUS_IO_GROUP_BURST = 0x2c30 # macro +regGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro +regGUS_DRAM_GROUP_BURST = 0x2c31 # macro +regGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro +regGUS_SDP_ARB_FINAL = 0x2c32 # macro +regGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro +regGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro +regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro +regGUS_SDP_CREDITS = 0x2c34 # macro +regGUS_SDP_CREDITS_BASE_IDX = 1 # macro +regGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro +regGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro +regGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro +regGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro +regGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro +regGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro +regGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro +regGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro +regGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro +regGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro +regGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro +regGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro +regGUS_SDP_REQ_CNTL = 0x2c3b # macro +regGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro +regGUS_MISC = 0x2c3c # macro +regGUS_MISC_BASE_IDX = 1 # macro +regGUS_LATENCY_SAMPLING = 0x2c3d # macro +regGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro +regGUS_ERR_STATUS = 0x2c3e # macro +regGUS_ERR_STATUS_BASE_IDX = 1 # macro +regGUS_MISC2 = 0x2c3f # macro +regGUS_MISC2_BASE_IDX = 1 # macro +regGUS_SDP_ENABLE = 0x2c45 # macro +regGUS_SDP_ENABLE_BASE_IDX = 1 # macro +regGUS_L1_CH0_CMD_IN = 0x2c46 # macro +regGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro +regGUS_L1_CH0_CMD_OUT = 0x2c47 # macro +regGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro +regGUS_L1_CH0_DATA_IN = 0x2c48 # macro +regGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro +regGUS_L1_CH0_DATA_OUT = 0x2c49 # macro +regGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro +regGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro +regGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro +regGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro +regGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro +regGUS_L1_CH1_CMD_IN = 0x2c4c # macro +regGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro +regGUS_L1_CH1_CMD_OUT = 0x2c4d # macro +regGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro +regGUS_L1_CH1_DATA_IN = 0x2c4e # macro +regGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro +regGUS_L1_CH1_DATA_OUT = 0x2c4f # macro +regGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro +regGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro +regGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro +regGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro +regGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA0_CMD_IN = 0x2c52 # macro +regGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro +regGUS_L1_SA0_CMD_OUT = 0x2c53 # macro +regGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA0_DATA_IN = 0x2c54 # macro +regGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro +regGUS_L1_SA0_DATA_OUT = 0x2c55 # macro +regGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro +regGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro +regGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro +regGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA1_CMD_IN = 0x2c58 # macro +regGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro +regGUS_L1_SA1_CMD_OUT = 0x2c59 # macro +regGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA1_DATA_IN = 0x2c5a # macro +regGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro +regGUS_L1_SA1_DATA_OUT = 0x2c5b # macro +regGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro +regGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro +regGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro +regGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA2_CMD_IN = 0x2c5e # macro +regGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro +regGUS_L1_SA2_CMD_OUT = 0x2c5f # macro +regGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA2_DATA_IN = 0x2c60 # macro +regGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro +regGUS_L1_SA2_DATA_OUT = 0x2c61 # macro +regGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro +regGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro +regGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro +regGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA3_CMD_IN = 0x2c64 # macro +regGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro +regGUS_L1_SA3_CMD_OUT = 0x2c65 # macro +regGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA3_DATA_IN = 0x2c66 # macro +regGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro +regGUS_L1_SA3_DATA_OUT = 0x2c67 # macro +regGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro +regGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro +regGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro +regGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro +regGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro +regGUS_MISC3 = 0x2c6a # macro +regGUS_MISC3_BASE_IDX = 1 # macro +regGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro +regGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro +regDB_RENDER_CONTROL = 0x0000 # macro +regDB_RENDER_CONTROL_BASE_IDX = 1 # macro +regDB_COUNT_CONTROL = 0x0001 # macro +regDB_COUNT_CONTROL_BASE_IDX = 1 # macro +regDB_DEPTH_VIEW = 0x0002 # macro +regDB_DEPTH_VIEW_BASE_IDX = 1 # macro +regDB_RENDER_OVERRIDE = 0x0003 # macro +regDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro +regDB_RENDER_OVERRIDE2 = 0x0004 # macro +regDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro +regDB_HTILE_DATA_BASE = 0x0005 # macro +regDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro +regDB_DEPTH_SIZE_XY = 0x0007 # macro +regDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro +regDB_DEPTH_BOUNDS_MIN = 0x0008 # macro +regDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro +regDB_DEPTH_BOUNDS_MAX = 0x0009 # macro +regDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro +regDB_STENCIL_CLEAR = 0x000a # macro +regDB_STENCIL_CLEAR_BASE_IDX = 1 # macro +regDB_DEPTH_CLEAR = 0x000b # macro +regDB_DEPTH_CLEAR_BASE_IDX = 1 # macro +regPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro +regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro +regPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro +regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro +regDB_RESERVED_REG_2 = 0x000f # macro +regDB_RESERVED_REG_2_BASE_IDX = 1 # macro +regDB_Z_INFO = 0x0010 # macro +regDB_Z_INFO_BASE_IDX = 1 # macro +regDB_STENCIL_INFO = 0x0011 # macro +regDB_STENCIL_INFO_BASE_IDX = 1 # macro +regDB_Z_READ_BASE = 0x0012 # macro +regDB_Z_READ_BASE_BASE_IDX = 1 # macro +regDB_STENCIL_READ_BASE = 0x0013 # macro +regDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro +regDB_Z_WRITE_BASE = 0x0014 # macro +regDB_Z_WRITE_BASE_BASE_IDX = 1 # macro +regDB_STENCIL_WRITE_BASE = 0x0015 # macro +regDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro +regDB_RESERVED_REG_1 = 0x0016 # macro +regDB_RESERVED_REG_1_BASE_IDX = 1 # macro +regDB_RESERVED_REG_3 = 0x0017 # macro +regDB_RESERVED_REG_3_BASE_IDX = 1 # macro +regDB_Z_READ_BASE_HI = 0x001a # macro +regDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro +regDB_STENCIL_READ_BASE_HI = 0x001b # macro +regDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro +regDB_Z_WRITE_BASE_HI = 0x001c # macro +regDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro +regDB_STENCIL_WRITE_BASE_HI = 0x001d # macro +regDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro +regDB_HTILE_DATA_BASE_HI = 0x001e # macro +regDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro +regDB_RMI_L2_CACHE_CONTROL = 0x001f # macro +regDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro +regTA_BC_BASE_ADDR = 0x0020 # macro +regTA_BC_BASE_ADDR_BASE_IDX = 1 # macro +regTA_BC_BASE_ADDR_HI = 0x0021 # macro +regTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_0 = 0x007a # macro +regCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_1 = 0x007b # macro +regCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_2 = 0x007c # macro +regCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_3 = 0x007d # macro +regCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_2 = 0x007e # macro +regCOHER_DEST_BASE_2_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_3 = 0x007f # macro +regCOHER_DEST_BASE_3_BASE_IDX = 1 # macro +regPA_SC_WINDOW_OFFSET = 0x0080 # macro +regPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro +regPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro +regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro +regPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro +regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_RULE = 0x0083 # macro +regPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_0_TL = 0x0084 # macro +regPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_0_BR = 0x0085 # macro +regPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_1_TL = 0x0086 # macro +regPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_1_BR = 0x0087 # macro +regPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_2_TL = 0x0088 # macro +regPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_2_BR = 0x0089 # macro +regPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_3_TL = 0x008a # macro +regPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_3_BR = 0x008b # macro +regPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro +regPA_SC_EDGERULE = 0x008c # macro +regPA_SC_EDGERULE_BASE_IDX = 1 # macro +regPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro +regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro +regCB_TARGET_MASK = 0x008e # macro +regCB_TARGET_MASK_BASE_IDX = 1 # macro +regCB_SHADER_MASK = 0x008f # macro +regCB_SHADER_MASK_BASE_IDX = 1 # macro +regPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro +regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro +regPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro +regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_0 = 0x0092 # macro +regCOHER_DEST_BASE_0_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_1 = 0x0093 # macro +regCOHER_DEST_BASE_1_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro +regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro +regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro +regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro +regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro +regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro +regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro +regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro +regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro +regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro +regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro +regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro +regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro +regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro +regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro +regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro +regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro +regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro +regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro +regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro +regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro +regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro +regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro +regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro +regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro +regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro +regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro +regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro +regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro +regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro +regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro +regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro +regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro +regPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro +regPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro +regPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro +regPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro +regPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro +regPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_3 = 0x00ba # macro +regPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_3 = 0x00bb # macro +regPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_4 = 0x00bc # macro +regPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_4 = 0x00bd # macro +regPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_5 = 0x00be # macro +regPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_5 = 0x00bf # macro +regPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro +regPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro +regPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro +regPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro +regPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro +regPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro +regPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro +regPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro +regPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro +regPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro +regPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_11 = 0x00ca # macro +regPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_11 = 0x00cb # macro +regPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_12 = 0x00cc # macro +regPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_12 = 0x00cd # macro +regPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_13 = 0x00ce # macro +regPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_13 = 0x00cf # macro +regPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro +regPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro +regPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro +regPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro +regPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro +regPA_SC_RASTER_CONFIG = 0x00d4 # macro +regPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro +regPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro +regPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro +regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro +regPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro +regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro +regCP_PERFMON_CNTX_CNTL = 0x00d8 # macro +regCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro +regCP_PIPEID = 0x00d9 # macro +regCP_PIPEID_BASE_IDX = 1 # macro +regCP_RINGID = 0x00d9 # macro +regCP_RINGID_BASE_IDX = 1 # macro +regCP_VMID = 0x00da # macro +regCP_VMID_BASE_IDX = 1 # macro +regCONTEXT_RESERVED_REG0 = 0x00db # macro +regCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro +regCONTEXT_RESERVED_REG1 = 0x00dc # macro +regCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro +regPA_SC_VRS_OVERRIDE_CNTL = 0x00f4 # macro +regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro +regPA_SC_VRS_RATE_FEEDBACK_BASE = 0x00f5 # macro +regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX = 1 # macro +regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT = 0x00f6 # macro +regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX = 1 # macro +regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY = 0x00f7 # macro +regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX = 1 # macro +regPA_SC_VRS_RATE_CACHE_CNTL = 0x00f9 # macro +regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX = 1 # macro +regPA_SC_VRS_RATE_BASE = 0x00fc # macro +regPA_SC_VRS_RATE_BASE_BASE_IDX = 1 # macro +regPA_SC_VRS_RATE_BASE_EXT = 0x00fd # macro +regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX = 1 # macro +regPA_SC_VRS_RATE_SIZE_XY = 0x00fe # macro +regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX = 1 # macro +regVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro +regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro +regCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro +regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND_RED = 0x0105 # macro +regCB_BLEND_RED_BASE_IDX = 1 # macro +regCB_BLEND_GREEN = 0x0106 # macro +regCB_BLEND_GREEN_BASE_IDX = 1 # macro +regCB_BLEND_BLUE = 0x0107 # macro +regCB_BLEND_BLUE_BASE_IDX = 1 # macro +regCB_BLEND_ALPHA = 0x0108 # macro +regCB_BLEND_ALPHA_BASE_IDX = 1 # macro +regCB_FDCC_CONTROL = 0x0109 # macro +regCB_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COVERAGE_OUT_CONTROL = 0x010a # macro +regCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro +regDB_STENCIL_CONTROL = 0x010b # macro +regDB_STENCIL_CONTROL_BASE_IDX = 1 # macro +regDB_STENCILREFMASK = 0x010c # macro +regDB_STENCILREFMASK_BASE_IDX = 1 # macro +regDB_STENCILREFMASK_BF = 0x010d # macro +regDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE = 0x010f # macro +regPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET = 0x0110 # macro +regPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE = 0x0111 # macro +regPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET = 0x0112 # macro +regPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE = 0x0113 # macro +regPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET = 0x0114 # macro +regPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_1 = 0x0115 # macro +regPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro +regPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_1 = 0x0117 # macro +regPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro +regPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro +regPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro +regPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_2 = 0x011b # macro +regPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_2 = 0x011c # macro +regPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_2 = 0x011d # macro +regPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_2 = 0x011e # macro +regPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_2 = 0x011f # macro +regPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro +regPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_3 = 0x0121 # macro +regPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro +regPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_3 = 0x0123 # macro +regPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro +regPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro +regPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro +regPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_4 = 0x0127 # macro +regPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro +regPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_4 = 0x0129 # macro +regPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_4 = 0x012a # macro +regPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_4 = 0x012b # macro +regPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro +regPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_5 = 0x012d # macro +regPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_5 = 0x012e # macro +regPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_5 = 0x012f # macro +regPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro +regPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro +regPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro +regPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_6 = 0x0133 # macro +regPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro +regPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_6 = 0x0135 # macro +regPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro +regPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro +regPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro +regPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_7 = 0x0139 # macro +regPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_7 = 0x013a # macro +regPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_7 = 0x013b # macro +regPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_7 = 0x013c # macro +regPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_7 = 0x013d # macro +regPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro +regPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_8 = 0x013f # macro +regPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro +regPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_8 = 0x0141 # macro +regPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro +regPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro +regPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro +regPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_9 = 0x0145 # macro +regPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro +regPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_9 = 0x0147 # macro +regPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro +regPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro +regPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro +regPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_10 = 0x014b # macro +regPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_10 = 0x014c # macro +regPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_10 = 0x014d # macro +regPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_10 = 0x014e # macro +regPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_10 = 0x014f # macro +regPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro +regPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_11 = 0x0151 # macro +regPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro +regPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_11 = 0x0153 # macro +regPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro +regPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro +regPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro +regPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_12 = 0x0157 # macro +regPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro +regPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_12 = 0x0159 # macro +regPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_12 = 0x015a # macro +regPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_12 = 0x015b # macro +regPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro +regPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_13 = 0x015d # macro +regPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_13 = 0x015e # macro +regPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_13 = 0x015f # macro +regPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro +regPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro +regPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro +regPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_14 = 0x0163 # macro +regPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro +regPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_14 = 0x0165 # macro +regPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro +regPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro +regPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro +regPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_15 = 0x0169 # macro +regPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_15 = 0x016a # macro +regPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_15 = 0x016b # macro +regPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_15 = 0x016c # macro +regPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_15 = 0x016d # macro +regPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro +regPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro +regPA_CL_UCP_0_X = 0x016f # macro +regPA_CL_UCP_0_X_BASE_IDX = 1 # macro +regPA_CL_UCP_0_Y = 0x0170 # macro +regPA_CL_UCP_0_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_0_Z = 0x0171 # macro +regPA_CL_UCP_0_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_0_W = 0x0172 # macro +regPA_CL_UCP_0_W_BASE_IDX = 1 # macro +regPA_CL_UCP_1_X = 0x0173 # macro +regPA_CL_UCP_1_X_BASE_IDX = 1 # macro +regPA_CL_UCP_1_Y = 0x0174 # macro +regPA_CL_UCP_1_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_1_Z = 0x0175 # macro +regPA_CL_UCP_1_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_1_W = 0x0176 # macro +regPA_CL_UCP_1_W_BASE_IDX = 1 # macro +regPA_CL_UCP_2_X = 0x0177 # macro +regPA_CL_UCP_2_X_BASE_IDX = 1 # macro +regPA_CL_UCP_2_Y = 0x0178 # macro +regPA_CL_UCP_2_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_2_Z = 0x0179 # macro +regPA_CL_UCP_2_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_2_W = 0x017a # macro +regPA_CL_UCP_2_W_BASE_IDX = 1 # macro +regPA_CL_UCP_3_X = 0x017b # macro +regPA_CL_UCP_3_X_BASE_IDX = 1 # macro +regPA_CL_UCP_3_Y = 0x017c # macro +regPA_CL_UCP_3_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_3_Z = 0x017d # macro +regPA_CL_UCP_3_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_3_W = 0x017e # macro +regPA_CL_UCP_3_W_BASE_IDX = 1 # macro +regPA_CL_UCP_4_X = 0x017f # macro +regPA_CL_UCP_4_X_BASE_IDX = 1 # macro +regPA_CL_UCP_4_Y = 0x0180 # macro +regPA_CL_UCP_4_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_4_Z = 0x0181 # macro +regPA_CL_UCP_4_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_4_W = 0x0182 # macro +regPA_CL_UCP_4_W_BASE_IDX = 1 # macro +regPA_CL_UCP_5_X = 0x0183 # macro +regPA_CL_UCP_5_X_BASE_IDX = 1 # macro +regPA_CL_UCP_5_Y = 0x0184 # macro +regPA_CL_UCP_5_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_5_Z = 0x0185 # macro +regPA_CL_UCP_5_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_5_W = 0x0186 # macro +regPA_CL_UCP_5_W_BASE_IDX = 1 # macro +regPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro +regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro +regPA_RATE_CNTL = 0x0188 # macro +regPA_RATE_CNTL_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_0 = 0x0191 # macro +regSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_1 = 0x0192 # macro +regSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_2 = 0x0193 # macro +regSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_3 = 0x0194 # macro +regSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_4 = 0x0195 # macro +regSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_5 = 0x0196 # macro +regSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_6 = 0x0197 # macro +regSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_7 = 0x0198 # macro +regSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_8 = 0x0199 # macro +regSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_9 = 0x019a # macro +regSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_10 = 0x019b # macro +regSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_11 = 0x019c # macro +regSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_12 = 0x019d # macro +regSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_13 = 0x019e # macro +regSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_14 = 0x019f # macro +regSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro +regSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro +regSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro +regSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro +regSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro +regSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro +regSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro +regSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro +regSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro +regSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro +regSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_25 = 0x01aa # macro +regSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_26 = 0x01ab # macro +regSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_27 = 0x01ac # macro +regSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_28 = 0x01ad # macro +regSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_29 = 0x01ae # macro +regSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_30 = 0x01af # macro +regSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro +regSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro +regSPI_VS_OUT_CONFIG = 0x01b1 # macro +regSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro +regSPI_PS_INPUT_ENA = 0x01b3 # macro +regSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro +regSPI_PS_INPUT_ADDR = 0x01b4 # macro +regSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro +regSPI_INTERP_CONTROL_0 = 0x01b5 # macro +regSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro +regSPI_PS_IN_CONTROL = 0x01b6 # macro +regSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro +regSPI_BARYC_CNTL = 0x01b8 # macro +regSPI_BARYC_CNTL_BASE_IDX = 1 # macro +regSPI_TMPRING_SIZE = 0x01ba # macro +regSPI_TMPRING_SIZE_BASE_IDX = 1 # macro +regSPI_GFX_SCRATCH_BASE_LO = 0x01bb # macro +regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX = 1 # macro +regSPI_GFX_SCRATCH_BASE_HI = 0x01bc # macro +regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX = 1 # macro +regSPI_SHADER_IDX_FORMAT = 0x01c2 # macro +regSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro +regSPI_SHADER_POS_FORMAT = 0x01c3 # macro +regSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro +regSPI_SHADER_Z_FORMAT = 0x01c4 # macro +regSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro +regSPI_SHADER_COL_FORMAT = 0x01c5 # macro +regSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro +regSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro +regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro +regSX_PS_DOWNCONVERT = 0x01d5 # macro +regSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro +regSX_BLEND_OPT_EPSILON = 0x01d6 # macro +regSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro +regSX_BLEND_OPT_CONTROL = 0x01d7 # macro +regSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro +regSX_MRT0_BLEND_OPT = 0x01d8 # macro +regSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro +regSX_MRT1_BLEND_OPT = 0x01d9 # macro +regSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro +regSX_MRT2_BLEND_OPT = 0x01da # macro +regSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro +regSX_MRT3_BLEND_OPT = 0x01db # macro +regSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro +regSX_MRT4_BLEND_OPT = 0x01dc # macro +regSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro +regSX_MRT5_BLEND_OPT = 0x01dd # macro +regSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro +regSX_MRT6_BLEND_OPT = 0x01de # macro +regSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro +regSX_MRT7_BLEND_OPT = 0x01df # macro +regSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro +regCB_BLEND0_CONTROL = 0x01e0 # macro +regCB_BLEND0_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND1_CONTROL = 0x01e1 # macro +regCB_BLEND1_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND2_CONTROL = 0x01e2 # macro +regCB_BLEND2_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND3_CONTROL = 0x01e3 # macro +regCB_BLEND3_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND4_CONTROL = 0x01e4 # macro +regCB_BLEND4_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND5_CONTROL = 0x01e5 # macro +regCB_BLEND5_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND6_CONTROL = 0x01e6 # macro +regCB_BLEND6_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND7_CONTROL = 0x01e7 # macro +regCB_BLEND7_CONTROL_BASE_IDX = 1 # macro +regGFX_COPY_STATE = 0x01f4 # macro +regGFX_COPY_STATE_BASE_IDX = 1 # macro +regPA_CL_POINT_X_RAD = 0x01f5 # macro +regPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro +regPA_CL_POINT_Y_RAD = 0x01f6 # macro +regPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro +regPA_CL_POINT_SIZE = 0x01f7 # macro +regPA_CL_POINT_SIZE_BASE_IDX = 1 # macro +regPA_CL_POINT_CULL_RAD = 0x01f8 # macro +regPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro +regVGT_DMA_BASE_HI = 0x01f9 # macro +regVGT_DMA_BASE_HI_BASE_IDX = 1 # macro +regVGT_DMA_BASE = 0x01fa # macro +regVGT_DMA_BASE_BASE_IDX = 1 # macro +regVGT_DRAW_INITIATOR = 0x01fc # macro +regVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro +regVGT_EVENT_ADDRESS_REG = 0x01fe # macro +regVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro +regGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro +regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro +regDB_DEPTH_CONTROL = 0x0200 # macro +regDB_DEPTH_CONTROL_BASE_IDX = 1 # macro +regDB_EQAA = 0x0201 # macro +regDB_EQAA_BASE_IDX = 1 # macro +regCB_COLOR_CONTROL = 0x0202 # macro +regCB_COLOR_CONTROL_BASE_IDX = 1 # macro +regDB_SHADER_CONTROL = 0x0203 # macro +regDB_SHADER_CONTROL_BASE_IDX = 1 # macro +regPA_CL_CLIP_CNTL = 0x0204 # macro +regPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro +regPA_SU_SC_MODE_CNTL = 0x0205 # macro +regPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro +regPA_CL_VTE_CNTL = 0x0206 # macro +regPA_CL_VTE_CNTL_BASE_IDX = 1 # macro +regPA_CL_VS_OUT_CNTL = 0x0207 # macro +regPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro +regPA_CL_NANINF_CNTL = 0x0208 # macro +regPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro +regPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro +regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro +regPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro +regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro +regPA_SU_PRIM_FILTER_CNTL = 0x020b # macro +regPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro +regPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro +regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro +regPA_CL_NGG_CNTL = 0x020e # macro +regPA_CL_NGG_CNTL_BASE_IDX = 1 # macro +regPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro +regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro +regPA_STEREO_CNTL = 0x0210 # macro +regPA_STEREO_CNTL_BASE_IDX = 1 # macro +regPA_STATE_STEREO_X = 0x0211 # macro +regPA_STATE_STEREO_X_BASE_IDX = 1 # macro +regPA_CL_VRS_CNTL = 0x0212 # macro +regPA_CL_VRS_CNTL_BASE_IDX = 1 # macro +regPA_SU_POINT_SIZE = 0x0280 # macro +regPA_SU_POINT_SIZE_BASE_IDX = 1 # macro +regPA_SU_POINT_MINMAX = 0x0281 # macro +regPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro +regPA_SU_LINE_CNTL = 0x0282 # macro +regPA_SU_LINE_CNTL_BASE_IDX = 1 # macro +regPA_SC_LINE_STIPPLE = 0x0283 # macro +regPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro +regVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro +regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro +regVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro +regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro +regPA_SC_MODE_CNTL_0 = 0x0292 # macro +regPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro +regPA_SC_MODE_CNTL_1 = 0x0293 # macro +regPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro +regVGT_ENHANCE = 0x0294 # macro +regVGT_ENHANCE_BASE_IDX = 1 # macro +regIA_ENHANCE = 0x029c # macro +regIA_ENHANCE_BASE_IDX = 1 # macro +regVGT_DMA_SIZE = 0x029d # macro +regVGT_DMA_SIZE_BASE_IDX = 1 # macro +regVGT_DMA_MAX_SIZE = 0x029e # macro +regVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro +regVGT_DMA_INDEX_TYPE = 0x029f # macro +regVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro +regWD_ENHANCE = 0x02a0 # macro +regWD_ENHANCE_BASE_IDX = 1 # macro +regVGT_PRIMITIVEID_EN = 0x02a1 # macro +regVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro +regVGT_DMA_NUM_INSTANCES = 0x02a2 # macro +regVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro +regVGT_PRIMITIVEID_RESET = 0x02a3 # macro +regVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro +regVGT_EVENT_INITIATOR = 0x02a4 # macro +regVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro +regVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro +regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro +regVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro +regVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro +regVGT_REUSE_OFF = 0x02ad # macro +regVGT_REUSE_OFF_BASE_IDX = 1 # macro +regDB_HTILE_SURFACE = 0x02af # macro +regDB_HTILE_SURFACE_BASE_IDX = 1 # macro +regDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro +regDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro +regDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro +regDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro +regDB_PRELOAD_CONTROL = 0x02b2 # macro +regDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro +regVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro +regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro +regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro +regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro +regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro +regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro +regVGT_GS_MAX_VERT_OUT = 0x02ce # macro +regVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro +regGE_NGG_SUBGRP_CNTL = 0x02d3 # macro +regGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro +regVGT_TESS_DISTRIBUTION = 0x02d4 # macro +regVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro +regVGT_SHADER_STAGES_EN = 0x02d5 # macro +regVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro +regVGT_LS_HS_CONFIG = 0x02d6 # macro +regVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro +regVGT_TF_PARAM = 0x02db # macro +regVGT_TF_PARAM_BASE_IDX = 1 # macro +regDB_ALPHA_TO_MASK = 0x02dc # macro +regDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro +regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro +regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro +regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro +regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro +regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro +regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro +regVGT_GS_INSTANCE_CNT = 0x02e4 # macro +regVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro +regPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro +regPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro +regPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro +regPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro +regPA_SC_LINE_CNTL = 0x02f7 # macro +regPA_SC_LINE_CNTL_BASE_IDX = 1 # macro +regPA_SC_AA_CONFIG = 0x02f8 # macro +regPA_SC_AA_CONFIG_BASE_IDX = 1 # macro +regPA_SU_VTX_CNTL = 0x02f9 # macro +regPA_SU_VTX_CNTL_BASE_IDX = 1 # macro +regPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro +regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro +regPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro +regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro +regPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro +regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro +regPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro +regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro +regPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro +regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro +regPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro +regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro +regPA_SC_SHADER_CONTROL = 0x0310 # macro +regPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro +regPA_SC_BINNER_CNTL_0 = 0x0311 # macro +regPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro +regPA_SC_BINNER_CNTL_1 = 0x0312 # macro +regPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro +regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro +regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro +regPA_SC_NGG_MODE_CNTL = 0x0314 # macro +regPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro +regPA_SC_BINNER_CNTL_2 = 0x0315 # macro +regPA_SC_BINNER_CNTL_2_BASE_IDX = 1 # macro +regCB_COLOR0_BASE = 0x0318 # macro +regCB_COLOR0_BASE_BASE_IDX = 1 # macro +regCB_COLOR0_VIEW = 0x031b # macro +regCB_COLOR0_VIEW_BASE_IDX = 1 # macro +regCB_COLOR0_INFO = 0x031c # macro +regCB_COLOR0_INFO_BASE_IDX = 1 # macro +regCB_COLOR0_ATTRIB = 0x031d # macro +regCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR0_FDCC_CONTROL = 0x031e # macro +regCB_COLOR0_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR0_DCC_BASE = 0x0325 # macro +regCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR1_BASE = 0x0327 # macro +regCB_COLOR1_BASE_BASE_IDX = 1 # macro +regCB_COLOR1_VIEW = 0x032a # macro +regCB_COLOR1_VIEW_BASE_IDX = 1 # macro +regCB_COLOR1_INFO = 0x032b # macro +regCB_COLOR1_INFO_BASE_IDX = 1 # macro +regCB_COLOR1_ATTRIB = 0x032c # macro +regCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR1_FDCC_CONTROL = 0x032d # macro +regCB_COLOR1_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR1_DCC_BASE = 0x0334 # macro +regCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR2_BASE = 0x0336 # macro +regCB_COLOR2_BASE_BASE_IDX = 1 # macro +regCB_COLOR2_VIEW = 0x0339 # macro +regCB_COLOR2_VIEW_BASE_IDX = 1 # macro +regCB_COLOR2_INFO = 0x033a # macro +regCB_COLOR2_INFO_BASE_IDX = 1 # macro +regCB_COLOR2_ATTRIB = 0x033b # macro +regCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR2_FDCC_CONTROL = 0x033c # macro +regCB_COLOR2_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR2_DCC_BASE = 0x0343 # macro +regCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR3_BASE = 0x0345 # macro +regCB_COLOR3_BASE_BASE_IDX = 1 # macro +regCB_COLOR3_VIEW = 0x0348 # macro +regCB_COLOR3_VIEW_BASE_IDX = 1 # macro +regCB_COLOR3_INFO = 0x0349 # macro +regCB_COLOR3_INFO_BASE_IDX = 1 # macro +regCB_COLOR3_ATTRIB = 0x034a # macro +regCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR3_FDCC_CONTROL = 0x034b # macro +regCB_COLOR3_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR3_DCC_BASE = 0x0352 # macro +regCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR4_BASE = 0x0354 # macro +regCB_COLOR4_BASE_BASE_IDX = 1 # macro +regCB_COLOR4_VIEW = 0x0357 # macro +regCB_COLOR4_VIEW_BASE_IDX = 1 # macro +regCB_COLOR4_INFO = 0x0358 # macro +regCB_COLOR4_INFO_BASE_IDX = 1 # macro +regCB_COLOR4_ATTRIB = 0x0359 # macro +regCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR4_FDCC_CONTROL = 0x035a # macro +regCB_COLOR4_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR4_DCC_BASE = 0x0361 # macro +regCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR5_BASE = 0x0363 # macro +regCB_COLOR5_BASE_BASE_IDX = 1 # macro +regCB_COLOR5_VIEW = 0x0366 # macro +regCB_COLOR5_VIEW_BASE_IDX = 1 # macro +regCB_COLOR5_INFO = 0x0367 # macro +regCB_COLOR5_INFO_BASE_IDX = 1 # macro +regCB_COLOR5_ATTRIB = 0x0368 # macro +regCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR5_FDCC_CONTROL = 0x0369 # macro +regCB_COLOR5_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR5_DCC_BASE = 0x0370 # macro +regCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR6_BASE = 0x0372 # macro +regCB_COLOR6_BASE_BASE_IDX = 1 # macro +regCB_COLOR6_VIEW = 0x0375 # macro +regCB_COLOR6_VIEW_BASE_IDX = 1 # macro +regCB_COLOR6_INFO = 0x0376 # macro +regCB_COLOR6_INFO_BASE_IDX = 1 # macro +regCB_COLOR6_ATTRIB = 0x0377 # macro +regCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR6_FDCC_CONTROL = 0x0378 # macro +regCB_COLOR6_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR6_DCC_BASE = 0x037f # macro +regCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR7_BASE = 0x0381 # macro +regCB_COLOR7_BASE_BASE_IDX = 1 # macro +regCB_COLOR7_VIEW = 0x0384 # macro +regCB_COLOR7_VIEW_BASE_IDX = 1 # macro +regCB_COLOR7_INFO = 0x0385 # macro +regCB_COLOR7_INFO_BASE_IDX = 1 # macro +regCB_COLOR7_ATTRIB = 0x0386 # macro +regCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR7_FDCC_CONTROL = 0x0387 # macro +regCB_COLOR7_FDCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR7_DCC_BASE = 0x038e # macro +regCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR0_BASE_EXT = 0x0390 # macro +regCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR1_BASE_EXT = 0x0391 # macro +regCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR2_BASE_EXT = 0x0392 # macro +regCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR3_BASE_EXT = 0x0393 # macro +regCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR4_BASE_EXT = 0x0394 # macro +regCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR5_BASE_EXT = 0x0395 # macro +regCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR6_BASE_EXT = 0x0396 # macro +regCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR7_BASE_EXT = 0x0397 # macro +regCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro +regCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro +regCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro +regCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro +regCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro +regCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro +regCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro +regCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR7_DCC_BASE_EXT = 0x03af # macro +regCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR0_ATTRIB2 = 0x03b0 # macro +regCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR1_ATTRIB2 = 0x03b1 # macro +regCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR2_ATTRIB2 = 0x03b2 # macro +regCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR3_ATTRIB2 = 0x03b3 # macro +regCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR4_ATTRIB2 = 0x03b4 # macro +regCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR5_ATTRIB2 = 0x03b5 # macro +regCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR6_ATTRIB2 = 0x03b6 # macro +regCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR7_ATTRIB2 = 0x03b7 # macro +regCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR0_ATTRIB3 = 0x03b8 # macro +regCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro +regCB_COLOR1_ATTRIB3 = 0x03b9 # macro +regCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro +regCB_COLOR2_ATTRIB3 = 0x03ba # macro +regCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro +regCB_COLOR3_ATTRIB3 = 0x03bb # macro +regCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro +regCB_COLOR4_ATTRIB3 = 0x03bc # macro +regCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro +regCB_COLOR5_ATTRIB3 = 0x03bd # macro +regCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro +regCB_COLOR6_ATTRIB3 = 0x03be # macro +regCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro +regCB_COLOR7_ATTRIB3 = 0x03bf # macro +regCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro +regCONFIG_RESERVED_REG0 = 0x0800 # macro +regCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro +regCONFIG_RESERVED_REG1 = 0x0801 # macro +regCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro +regCP_MEC_CNTL = 0x0802 # macro +regCP_MEC_CNTL_BASE_IDX = 1 # macro +regCP_ME_CNTL = 0x0803 # macro +regCP_ME_CNTL_BASE_IDX = 1 # macro +regGRBM_GFX_CNTL = 0x0900 # macro +regGRBM_GFX_CNTL_BASE_IDX = 1 # macro +regGRBM_NOWHERE = 0x0901 # macro +regGRBM_NOWHERE_BASE_IDX = 1 # macro +regPA_SC_VRS_SURFACE_CNTL = 0x0940 # macro +regPA_SC_VRS_SURFACE_CNTL_BASE_IDX = 1 # macro +regPA_SC_ENHANCE = 0x0941 # macro +regPA_SC_ENHANCE_BASE_IDX = 1 # macro +regPA_SC_ENHANCE_1 = 0x0942 # macro +regPA_SC_ENHANCE_1_BASE_IDX = 1 # macro +regPA_SC_ENHANCE_2 = 0x0943 # macro +regPA_SC_ENHANCE_2_BASE_IDX = 1 # macro +regPA_SC_ENHANCE_3 = 0x0944 # macro +regPA_SC_ENHANCE_3_BASE_IDX = 1 # macro +regPA_SC_BINNER_CNTL_OVERRIDE = 0x0946 # macro +regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 1 # macro +regPA_SC_PBB_OVERRIDE_FLAG = 0x0947 # macro +regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 1 # macro +regPA_SC_DSM_CNTL = 0x0948 # macro +regPA_SC_DSM_CNTL_BASE_IDX = 1 # macro +regPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x0949 # macro +regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 1 # macro +regPA_SC_FIFO_SIZE = 0x094a # macro +regPA_SC_FIFO_SIZE_BASE_IDX = 1 # macro +regPA_SC_IF_FIFO_SIZE = 0x094b # macro +regPA_SC_IF_FIFO_SIZE_BASE_IDX = 1 # macro +regPA_SC_PACKER_WAVE_ID_CNTL = 0x094c # macro +regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX = 1 # macro +regPA_SC_ATM_CNTL = 0x094d # macro +regPA_SC_ATM_CNTL_BASE_IDX = 1 # macro +regPA_SC_PKR_WAVE_TABLE_CNTL = 0x094e # macro +regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 1 # macro +regPA_SC_FORCE_EOV_MAX_CNTS = 0x094f # macro +regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 1 # macro +regPA_SC_BINNER_EVENT_CNTL_0 = 0x0950 # macro +regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 1 # macro +regPA_SC_BINNER_EVENT_CNTL_1 = 0x0951 # macro +regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 1 # macro +regPA_SC_BINNER_EVENT_CNTL_2 = 0x0952 # macro +regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 1 # macro +regPA_SC_BINNER_EVENT_CNTL_3 = 0x0953 # macro +regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 1 # macro +regPA_SC_BINNER_TIMEOUT_COUNTER = 0x0954 # macro +regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 1 # macro +regPA_SC_BINNER_PERF_CNTL_0 = 0x0955 # macro +regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 1 # macro +regPA_SC_BINNER_PERF_CNTL_1 = 0x0956 # macro +regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 1 # macro +regPA_SC_BINNER_PERF_CNTL_2 = 0x0957 # macro +regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 1 # macro +regPA_SC_BINNER_PERF_CNTL_3 = 0x0958 # macro +regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x095b # macro +regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x095c # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_HV_LOCK = 0x095d # macro +regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro +regPA_PH_INTERFACE_FIFO_SIZE = 0x095e # macro +regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 1 # macro +regPA_PH_ENHANCE = 0x095f # macro +regPA_PH_ENHANCE_BASE_IDX = 1 # macro +regPA_SC_VRS_SURFACE_CNTL_1 = 0x0960 # macro +regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX = 1 # macro +regSQ_RUNTIME_CONFIG = 0x09e0 # macro +regSQ_RUNTIME_CONFIG_BASE_IDX = 1 # macro +regSQ_DEBUG_STS_GLOBAL = 0x09e1 # macro +regSQ_DEBUG_STS_GLOBAL_BASE_IDX = 1 # macro +regSQ_DEBUG_STS_GLOBAL2 = 0x09e2 # macro +regSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 1 # macro +regSH_MEM_BASES = 0x09e3 # macro +regSH_MEM_BASES_BASE_IDX = 1 # macro +regSH_MEM_CONFIG = 0x09e4 # macro +regSH_MEM_CONFIG_BASE_IDX = 1 # macro +regSQ_DEBUG = 0x09e5 # macro +regSQ_DEBUG_BASE_IDX = 1 # macro +regSQ_SHADER_TBA_LO = 0x09e6 # macro +regSQ_SHADER_TBA_LO_BASE_IDX = 1 # macro +regSQ_SHADER_TBA_HI = 0x09e7 # macro +regSQ_SHADER_TBA_HI_BASE_IDX = 1 # macro +regSQ_SHADER_TMA_LO = 0x09e8 # macro +regSQ_SHADER_TMA_LO_BASE_IDX = 1 # macro +regSQ_SHADER_TMA_HI = 0x09e9 # macro +regSQ_SHADER_TMA_HI_BASE_IDX = 1 # macro +regCP_DEBUG_2 = 0x1800 # macro +regCP_DEBUG_2_BASE_IDX = 1 # macro +regCP_FETCHER_SOURCE = 0x1801 # macro +regCP_FETCHER_SOURCE_BASE_IDX = 1 # macro +regCP_HPD_MES_ROQ_OFFSETS = 0x1821 # macro +regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 1 # macro +regCP_HPD_ROQ_OFFSETS = 0x1821 # macro +regCP_HPD_ROQ_OFFSETS_BASE_IDX = 1 # macro +regCP_HPD_STATUS0 = 0x1822 # macro +regCP_HPD_STATUS0_BASE_IDX = 1 # macro +regDIDT_INDEX_AUTO_INCR_EN = 0x1900 # macro +regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 1 # macro +regDIDT_EDC_CTRL = 0x1901 # macro +regDIDT_EDC_CTRL_BASE_IDX = 1 # macro +regDIDT_EDC_THROTTLE_CTRL = 0x1902 # macro +regDIDT_EDC_THROTTLE_CTRL_BASE_IDX = 1 # macro +regDIDT_EDC_THRESHOLD = 0x1903 # macro +regDIDT_EDC_THRESHOLD_BASE_IDX = 1 # macro +regDIDT_EDC_STALL_PATTERN_1_2 = 0x1904 # macro +regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro +regDIDT_EDC_STALL_PATTERN_3_4 = 0x1905 # macro +regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro +regDIDT_EDC_STALL_PATTERN_5_6 = 0x1906 # macro +regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro +regDIDT_EDC_STALL_PATTERN_7 = 0x1907 # macro +regDIDT_EDC_STALL_PATTERN_7_BASE_IDX = 1 # macro +regDIDT_EDC_STATUS = 0x1908 # macro +regDIDT_EDC_STATUS_BASE_IDX = 1 # macro +regDIDT_EDC_DYNAMIC_THRESHOLD_RO = 0x1909 # macro +regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX = 1 # macro +regDIDT_EDC_OVERFLOW = 0x190a # macro +regDIDT_EDC_OVERFLOW_BASE_IDX = 1 # macro +regDIDT_EDC_ROLLING_POWER_DELTA = 0x190b # macro +regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro +regDIDT_IND_INDEX = 0x190c # macro +regDIDT_IND_INDEX_BASE_IDX = 1 # macro +regDIDT_IND_DATA = 0x190d # macro +regDIDT_IND_DATA_BASE_IDX = 1 # macro +regSPI_GDBG_WAVE_CNTL = 0x1943 # macro +regSPI_GDBG_WAVE_CNTL_BASE_IDX = 1 # macro +regSPI_GDBG_TRAP_CONFIG = 0x1944 # macro +regSPI_GDBG_TRAP_CONFIG_BASE_IDX = 1 # macro +regSPI_GDBG_WAVE_CNTL3 = 0x1945 # macro +regSPI_GDBG_WAVE_CNTL3_BASE_IDX = 1 # macro +regSPI_ARB_CNTL_0 = 0x1949 # macro +regSPI_ARB_CNTL_0_BASE_IDX = 1 # macro +regSPI_FEATURE_CTRL = 0x194a # macro +regSPI_FEATURE_CTRL_BASE_IDX = 1 # macro +regSPI_SHADER_RSRC_LIMIT_CTRL = 0x194b # macro +regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 1 # macro +regSPI_COMPUTE_WF_CTX_SAVE_STATUS = 0x194e # macro +regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX = 1 # macro +regTCP_INVALIDATE = 0x19a0 # macro +regTCP_INVALIDATE_BASE_IDX = 1 # macro +regTCP_STATUS = 0x19a1 # macro +regTCP_STATUS_BASE_IDX = 1 # macro +regTCP_CNTL = 0x19a2 # macro +regTCP_CNTL_BASE_IDX = 1 # macro +regTCP_CNTL2 = 0x19a3 # macro +regTCP_CNTL2_BASE_IDX = 1 # macro +regTCP_DEBUG_INDEX = 0x19a5 # macro +regTCP_DEBUG_INDEX_BASE_IDX = 1 # macro +regTCP_DEBUG_DATA = 0x19a6 # macro +regTCP_DEBUG_DATA_BASE_IDX = 1 # macro +regGDS_ENHANCE2 = 0x19b0 # macro +regGDS_ENHANCE2_BASE_IDX = 1 # macro +regGDS_OA_CGPG_RESTORE = 0x19b1 # macro +regGDS_OA_CGPG_RESTORE_BASE_IDX = 1 # macro +regUTCL1_CTRL_0 = 0x1980 # macro +regUTCL1_CTRL_0_BASE_IDX = 1 # macro +regUTCL1_UTCL0_INVREQ_DISABLE = 0x1984 # macro +regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 1 # macro +regUTCL1_CTRL_2 = 0x1985 # macro +regUTCL1_CTRL_2_BASE_IDX = 1 # macro +regUTCL1_FIFO_SIZING = 0x1986 # macro +regUTCL1_FIFO_SIZING_BASE_IDX = 1 # macro +regGCRD_SA0_TARGETS_DISABLE = 0x1987 # macro +regGCRD_SA0_TARGETS_DISABLE_BASE_IDX = 1 # macro +regGCRD_SA1_TARGETS_DISABLE = 0x1989 # macro +regGCRD_SA1_TARGETS_DISABLE_BASE_IDX = 1 # macro +regGCRD_CREDIT_SAFE = 0x198a # macro +regGCRD_CREDIT_SAFE_BASE_IDX = 1 # macro +regGCR_GENERAL_CNTL = 0x1990 # macro +regGCR_GENERAL_CNTL_BASE_IDX = 1 # macro +regGCR_CMD_STATUS = 0x1992 # macro +regGCR_CMD_STATUS_BASE_IDX = 1 # macro +regGCR_SPARE = 0x1993 # macro +regGCR_SPARE_BASE_IDX = 1 # macro +regPMM_CNTL2 = 0x1999 # macro +regPMM_CNTL2_BASE_IDX = 1 # macro +regSEDC_GL1_GL2_OVERRIDES = 0x1ac0 # macro +regSEDC_GL1_GL2_OVERRIDES_BASE_IDX = 1 # macro +regGC_CAC_CTRL_1 = 0x1ad0 # macro +regGC_CAC_CTRL_1_BASE_IDX = 1 # macro +regGC_CAC_CTRL_2 = 0x1ad1 # macro +regGC_CAC_CTRL_2_BASE_IDX = 1 # macro +regGC_CAC_AGGR_LOWER = 0x1ad2 # macro +regGC_CAC_AGGR_LOWER_BASE_IDX = 1 # macro +regGC_CAC_AGGR_UPPER = 0x1ad3 # macro +regGC_CAC_AGGR_UPPER_BASE_IDX = 1 # macro +regSE0_CAC_AGGR_LOWER = 0x1ad4 # macro +regSE0_CAC_AGGR_LOWER_BASE_IDX = 1 # macro +regSE0_CAC_AGGR_UPPER = 0x1ad5 # macro +regSE0_CAC_AGGR_UPPER_BASE_IDX = 1 # macro +regSE1_CAC_AGGR_LOWER = 0x1ad6 # macro +regSE1_CAC_AGGR_LOWER_BASE_IDX = 1 # macro +regSE1_CAC_AGGR_UPPER = 0x1ad7 # macro +regSE1_CAC_AGGR_UPPER_BASE_IDX = 1 # macro +regSE2_CAC_AGGR_LOWER = 0x1ad8 # macro +regSE2_CAC_AGGR_LOWER_BASE_IDX = 1 # macro +regSE2_CAC_AGGR_UPPER = 0x1ad9 # macro +regSE2_CAC_AGGR_UPPER_BASE_IDX = 1 # macro +regSE3_CAC_AGGR_LOWER = 0x1ada # macro +regSE3_CAC_AGGR_LOWER_BASE_IDX = 1 # macro +regSE3_CAC_AGGR_UPPER = 0x1adb # macro +regSE3_CAC_AGGR_UPPER_BASE_IDX = 1 # macro +regSE4_CAC_AGGR_LOWER = 0x1adc # macro +regSE4_CAC_AGGR_LOWER_BASE_IDX = 1 # macro +regSE4_CAC_AGGR_UPPER = 0x1add # macro +regSE4_CAC_AGGR_UPPER_BASE_IDX = 1 # macro +regSE5_CAC_AGGR_LOWER = 0x1ade # macro +regSE5_CAC_AGGR_LOWER_BASE_IDX = 1 # macro +regSE5_CAC_AGGR_UPPER = 0x1adf # macro +regSE5_CAC_AGGR_UPPER_BASE_IDX = 1 # macro +regGC_CAC_AGGR_GFXCLK_CYCLE = 0x1ae4 # macro +regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regSE0_CAC_AGGR_GFXCLK_CYCLE = 0x1ae5 # macro +regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regSE1_CAC_AGGR_GFXCLK_CYCLE = 0x1ae6 # macro +regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regSE2_CAC_AGGR_GFXCLK_CYCLE = 0x1ae7 # macro +regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regSE3_CAC_AGGR_GFXCLK_CYCLE = 0x1ae8 # macro +regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regSE4_CAC_AGGR_GFXCLK_CYCLE = 0x1ae9 # macro +regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regSE5_CAC_AGGR_GFXCLK_CYCLE = 0x1aea # macro +regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regGC_EDC_CTRL = 0x1aed # macro +regGC_EDC_CTRL_BASE_IDX = 1 # macro +regGC_EDC_THRESHOLD = 0x1aee # macro +regGC_EDC_THRESHOLD_BASE_IDX = 1 # macro +regGC_EDC_STRETCH_CTRL = 0x1aef # macro +regGC_EDC_STRETCH_CTRL_BASE_IDX = 1 # macro +regGC_EDC_STRETCH_THRESHOLD = 0x1af0 # macro +regGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 1 # macro +regEDC_HYSTERESIS_CNTL = 0x1af1 # macro +regEDC_HYSTERESIS_CNTL_BASE_IDX = 1 # macro +regGC_THROTTLE_CTRL = 0x1af2 # macro +regGC_THROTTLE_CTRL_BASE_IDX = 1 # macro +regGC_THROTTLE_CTRL1 = 0x1af3 # macro +regGC_THROTTLE_CTRL1_BASE_IDX = 1 # macro +regPCC_STALL_PATTERN_CTRL = 0x1af4 # macro +regPCC_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro +regPWRBRK_STALL_PATTERN_CTRL = 0x1af5 # macro +regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro +regPCC_STALL_PATTERN_1_2 = 0x1af6 # macro +regPCC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro +regPCC_STALL_PATTERN_3_4 = 0x1af7 # macro +regPCC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro +regPCC_STALL_PATTERN_5_6 = 0x1af8 # macro +regPCC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro +regPCC_STALL_PATTERN_7 = 0x1af9 # macro +regPCC_STALL_PATTERN_7_BASE_IDX = 1 # macro +regPWRBRK_STALL_PATTERN_1_2 = 0x1afa # macro +regPWRBRK_STALL_PATTERN_1_2_BASE_IDX = 1 # macro +regPWRBRK_STALL_PATTERN_3_4 = 0x1afb # macro +regPWRBRK_STALL_PATTERN_3_4_BASE_IDX = 1 # macro +regPWRBRK_STALL_PATTERN_5_6 = 0x1afc # macro +regPWRBRK_STALL_PATTERN_5_6_BASE_IDX = 1 # macro +regPWRBRK_STALL_PATTERN_7 = 0x1afd # macro +regPWRBRK_STALL_PATTERN_7_BASE_IDX = 1 # macro +regDIDT_STALL_PATTERN_CTRL = 0x1afe # macro +regDIDT_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro +regDIDT_STALL_PATTERN_1_2 = 0x1aff # macro +regDIDT_STALL_PATTERN_1_2_BASE_IDX = 1 # macro +regDIDT_STALL_PATTERN_3_4 = 0x1b00 # macro +regDIDT_STALL_PATTERN_3_4_BASE_IDX = 1 # macro +regDIDT_STALL_PATTERN_5_6 = 0x1b01 # macro +regDIDT_STALL_PATTERN_5_6_BASE_IDX = 1 # macro +regDIDT_STALL_PATTERN_7 = 0x1b02 # macro +regDIDT_STALL_PATTERN_7_BASE_IDX = 1 # macro +regPCC_PWRBRK_HYSTERESIS_CTRL = 0x1b03 # macro +regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX = 1 # macro +regEDC_STRETCH_PERF_COUNTER = 0x1b04 # macro +regEDC_STRETCH_PERF_COUNTER_BASE_IDX = 1 # macro +regEDC_UNSTRETCH_PERF_COUNTER = 0x1b05 # macro +regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX = 1 # macro +regEDC_STRETCH_NUM_PERF_COUNTER = 0x1b06 # macro +regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX = 1 # macro +regGC_EDC_STATUS = 0x1b07 # macro +regGC_EDC_STATUS_BASE_IDX = 1 # macro +regGC_EDC_OVERFLOW = 0x1b08 # macro +regGC_EDC_OVERFLOW_BASE_IDX = 1 # macro +regGC_EDC_ROLLING_POWER_DELTA = 0x1b09 # macro +regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro +regGC_THROTTLE_STATUS = 0x1b0a # macro +regGC_THROTTLE_STATUS_BASE_IDX = 1 # macro +regEDC_PERF_COUNTER = 0x1b0b # macro +regEDC_PERF_COUNTER_BASE_IDX = 1 # macro +regPCC_PERF_COUNTER = 0x1b0c # macro +regPCC_PERF_COUNTER_BASE_IDX = 1 # macro +regPWRBRK_PERF_COUNTER = 0x1b0d # macro +regPWRBRK_PERF_COUNTER_BASE_IDX = 1 # macro +regEDC_HYSTERESIS_STAT = 0x1b0e # macro +regEDC_HYSTERESIS_STAT_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_CP_0 = 0x1b10 # macro +regGC_CAC_WEIGHT_CP_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_CP_1 = 0x1b11 # macro +regGC_CAC_WEIGHT_CP_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_EA_0 = 0x1b12 # macro +regGC_CAC_WEIGHT_EA_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_EA_1 = 0x1b13 # macro +regGC_CAC_WEIGHT_EA_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_EA_2 = 0x1b14 # macro +regGC_CAC_WEIGHT_EA_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x1b15 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x1b16 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x1b17 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x1b18 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x1b19 # macro +regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x1b1a # macro +regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x1b1b # macro +regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x1b1c # macro +regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x1b1d # macro +regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x1b1e # macro +regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x1b1f # macro +regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GDS_0 = 0x1b20 # macro +regGC_CAC_WEIGHT_GDS_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GDS_1 = 0x1b21 # macro +regGC_CAC_WEIGHT_GDS_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GDS_2 = 0x1b22 # macro +regGC_CAC_WEIGHT_GDS_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GE_0 = 0x1b23 # macro +regGC_CAC_WEIGHT_GE_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GE_1 = 0x1b24 # macro +regGC_CAC_WEIGHT_GE_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GE_2 = 0x1b25 # macro +regGC_CAC_WEIGHT_GE_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GE_3 = 0x1b26 # macro +regGC_CAC_WEIGHT_GE_3_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GE_4 = 0x1b27 # macro +regGC_CAC_WEIGHT_GE_4_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GE_5 = 0x1b28 # macro +regGC_CAC_WEIGHT_GE_5_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GE_6 = 0x1b29 # macro +regGC_CAC_WEIGHT_GE_6_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_PMM_0 = 0x1b2e # macro +regGC_CAC_WEIGHT_PMM_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GL2C_0 = 0x1b2f # macro +regGC_CAC_WEIGHT_GL2C_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GL2C_1 = 0x1b30 # macro +regGC_CAC_WEIGHT_GL2C_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GL2C_2 = 0x1b31 # macro +regGC_CAC_WEIGHT_GL2C_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_PH_0 = 0x1b32 # macro +regGC_CAC_WEIGHT_PH_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_PH_1 = 0x1b33 # macro +regGC_CAC_WEIGHT_PH_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_PH_2 = 0x1b34 # macro +regGC_CAC_WEIGHT_PH_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_PH_3 = 0x1b35 # macro +regGC_CAC_WEIGHT_PH_3_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_SDMA_0 = 0x1b36 # macro +regGC_CAC_WEIGHT_SDMA_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_SDMA_1 = 0x1b37 # macro +regGC_CAC_WEIGHT_SDMA_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_SDMA_2 = 0x1b38 # macro +regGC_CAC_WEIGHT_SDMA_2_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_SDMA_3 = 0x1b39 # macro +regGC_CAC_WEIGHT_SDMA_3_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_SDMA_4 = 0x1b3a # macro +regGC_CAC_WEIGHT_SDMA_4_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_SDMA_5 = 0x1b3b # macro +regGC_CAC_WEIGHT_SDMA_5_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_CHC_0 = 0x1b3c # macro +regGC_CAC_WEIGHT_CHC_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_CHC_1 = 0x1b3d # macro +regGC_CAC_WEIGHT_CHC_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GUS_0 = 0x1b3e # macro +regGC_CAC_WEIGHT_GUS_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GUS_1 = 0x1b3f # macro +regGC_CAC_WEIGHT_GUS_1_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_RLC_0 = 0x1b40 # macro +regGC_CAC_WEIGHT_RLC_0_BASE_IDX = 1 # macro +regGC_CAC_WEIGHT_GRBM_0 = 0x1b44 # macro +regGC_CAC_WEIGHT_GRBM_0_BASE_IDX = 1 # macro +regGC_EDC_CLK_MONITOR_CTRL = 0x1b56 # macro +regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX = 1 # macro +regGC_CAC_IND_INDEX = 0x1b58 # macro +regGC_CAC_IND_INDEX_BASE_IDX = 1 # macro +regGC_CAC_IND_DATA = 0x1b59 # macro +regGC_CAC_IND_DATA_BASE_IDX = 1 # macro +regSE_CAC_CTRL_1 = 0x1b70 # macro +regSE_CAC_CTRL_1_BASE_IDX = 1 # macro +regSE_CAC_CTRL_2 = 0x1b71 # macro +regSE_CAC_CTRL_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TA_0 = 0x1b72 # macro +regSE_CAC_WEIGHT_TA_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TD_0 = 0x1b73 # macro +regSE_CAC_WEIGHT_TD_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TD_1 = 0x1b74 # macro +regSE_CAC_WEIGHT_TD_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TD_2 = 0x1b75 # macro +regSE_CAC_WEIGHT_TD_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TD_3 = 0x1b76 # macro +regSE_CAC_WEIGHT_TD_3_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TD_4 = 0x1b77 # macro +regSE_CAC_WEIGHT_TD_4_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TD_5 = 0x1b78 # macro +regSE_CAC_WEIGHT_TD_5_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TCP_0 = 0x1b79 # macro +regSE_CAC_WEIGHT_TCP_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TCP_1 = 0x1b7a # macro +regSE_CAC_WEIGHT_TCP_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TCP_2 = 0x1b7b # macro +regSE_CAC_WEIGHT_TCP_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_TCP_3 = 0x1b7c # macro +regSE_CAC_WEIGHT_TCP_3_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SQ_0 = 0x1b7d # macro +regSE_CAC_WEIGHT_SQ_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SQ_1 = 0x1b7e # macro +regSE_CAC_WEIGHT_SQ_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SQ_2 = 0x1b7f # macro +regSE_CAC_WEIGHT_SQ_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SP_0 = 0x1b80 # macro +regSE_CAC_WEIGHT_SP_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SP_1 = 0x1b81 # macro +regSE_CAC_WEIGHT_SP_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_LDS_0 = 0x1b82 # macro +regSE_CAC_WEIGHT_LDS_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_LDS_1 = 0x1b83 # macro +regSE_CAC_WEIGHT_LDS_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_LDS_2 = 0x1b84 # macro +regSE_CAC_WEIGHT_LDS_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_LDS_3 = 0x1b85 # macro +regSE_CAC_WEIGHT_LDS_3_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SQC_0 = 0x1b87 # macro +regSE_CAC_WEIGHT_SQC_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SQC_1 = 0x1b88 # macro +regSE_CAC_WEIGHT_SQC_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CU_0 = 0x1b89 # macro +regSE_CAC_WEIGHT_CU_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_BCI_0 = 0x1b8a # macro +regSE_CAC_WEIGHT_BCI_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_0 = 0x1b8b # macro +regSE_CAC_WEIGHT_CB_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_1 = 0x1b8c # macro +regSE_CAC_WEIGHT_CB_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_2 = 0x1b8d # macro +regSE_CAC_WEIGHT_CB_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_3 = 0x1b8e # macro +regSE_CAC_WEIGHT_CB_3_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_4 = 0x1b8f # macro +regSE_CAC_WEIGHT_CB_4_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_5 = 0x1b90 # macro +regSE_CAC_WEIGHT_CB_5_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_6 = 0x1b91 # macro +regSE_CAC_WEIGHT_CB_6_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_7 = 0x1b92 # macro +regSE_CAC_WEIGHT_CB_7_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_8 = 0x1b93 # macro +regSE_CAC_WEIGHT_CB_8_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_9 = 0x1b94 # macro +regSE_CAC_WEIGHT_CB_9_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_10 = 0x1b95 # macro +regSE_CAC_WEIGHT_CB_10_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_CB_11 = 0x1b96 # macro +regSE_CAC_WEIGHT_CB_11_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_DB_0 = 0x1b97 # macro +regSE_CAC_WEIGHT_DB_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_DB_1 = 0x1b98 # macro +regSE_CAC_WEIGHT_DB_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_DB_2 = 0x1b99 # macro +regSE_CAC_WEIGHT_DB_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_DB_3 = 0x1b9a # macro +regSE_CAC_WEIGHT_DB_3_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_DB_4 = 0x1b9b # macro +regSE_CAC_WEIGHT_DB_4_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_RMI_0 = 0x1b9c # macro +regSE_CAC_WEIGHT_RMI_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_RMI_1 = 0x1b9d # macro +regSE_CAC_WEIGHT_RMI_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SX_0 = 0x1b9e # macro +regSE_CAC_WEIGHT_SX_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SXRB_0 = 0x1b9f # macro +regSE_CAC_WEIGHT_SXRB_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_UTCL1_0 = 0x1ba0 # macro +regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_GL1C_0 = 0x1ba1 # macro +regSE_CAC_WEIGHT_GL1C_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_GL1C_1 = 0x1ba2 # macro +regSE_CAC_WEIGHT_GL1C_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_GL1C_2 = 0x1ba3 # macro +regSE_CAC_WEIGHT_GL1C_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SPI_0 = 0x1ba4 # macro +regSE_CAC_WEIGHT_SPI_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SPI_1 = 0x1ba5 # macro +regSE_CAC_WEIGHT_SPI_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SPI_2 = 0x1ba6 # macro +regSE_CAC_WEIGHT_SPI_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_PC_0 = 0x1ba7 # macro +regSE_CAC_WEIGHT_PC_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_PA_0 = 0x1ba8 # macro +regSE_CAC_WEIGHT_PA_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_PA_1 = 0x1ba9 # macro +regSE_CAC_WEIGHT_PA_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_PA_2 = 0x1baa # macro +regSE_CAC_WEIGHT_PA_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_PA_3 = 0x1bab # macro +regSE_CAC_WEIGHT_PA_3_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SC_0 = 0x1bac # macro +regSE_CAC_WEIGHT_SC_0_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SC_1 = 0x1bad # macro +regSE_CAC_WEIGHT_SC_1_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SC_2 = 0x1bae # macro +regSE_CAC_WEIGHT_SC_2_BASE_IDX = 1 # macro +regSE_CAC_WEIGHT_SC_3 = 0x1baf # macro +regSE_CAC_WEIGHT_SC_3_BASE_IDX = 1 # macro +regSE_CAC_WINDOW_AGGR_VALUE = 0x1bb0 # macro +regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX = 1 # macro +regSE_CAC_WINDOW_GFXCLK_CYCLE = 0x1bb1 # macro +regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX = 1 # macro +regSE_CAC_IND_INDEX = 0x1bce # macro +regSE_CAC_IND_INDEX_BASE_IDX = 1 # macro +regSE_CAC_IND_DATA = 0x1bcf # macro +regSE_CAC_IND_DATA_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_0 = 0x1c00 # macro +regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_1 = 0x1c01 # macro +regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_2 = 0x1c02 # macro +regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_3 = 0x1c03 # macro +regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_4 = 0x1c04 # macro +regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_5 = 0x1c05 # macro +regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_6 = 0x1c06 # macro +regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_7 = 0x1c07 # macro +regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_8 = 0x1c08 # macro +regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_9 = 0x1c09 # macro +regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_10 = 0x1c0a # macro +regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_11 = 0x1c0b # macro +regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_12 = 0x1c0c # macro +regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_13 = 0x1c0d # macro +regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_14 = 0x1c0e # macro +regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_CU_15 = 0x1c0f # macro +regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1c10 # macro +regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1c11 # macro +regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1c12 # macro +regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1c13 # macro +regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1c14 # macro +regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1c15 # macro +regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1c16 # macro +regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1c17 # macro +regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1c18 # macro +regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1c19 # macro +regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_10 = 0x1c1a # macro +regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_11 = 0x1c1b # macro +regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_12 = 0x1c1c # macro +regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_13 = 0x1c1d # macro +regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_14 = 0x1c1e # macro +regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX = 1 # macro +regSPI_RESOURCE_RESERVE_EN_CU_15 = 0x1c1f # macro +regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX = 1 # macro +regCP_EOP_DONE_ADDR_LO = 0x2000 # macro +regCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro +regCP_EOP_DONE_ADDR_HI = 0x2001 # macro +regCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro +regCP_EOP_DONE_DATA_LO = 0x2002 # macro +regCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro +regCP_EOP_DONE_DATA_HI = 0x2003 # macro +regCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro +regCP_EOP_LAST_FENCE_LO = 0x2004 # macro +regCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro +regCP_EOP_LAST_FENCE_HI = 0x2005 # macro +regCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro +regCP_PIPE_STATS_ADDR_LO = 0x2018 # macro +regCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro +regCP_PIPE_STATS_ADDR_HI = 0x2019 # macro +regCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro +regCP_VGT_IAVERT_COUNT_LO = 0x201a # macro +regCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_IAVERT_COUNT_HI = 0x201b # macro +regCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro +regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro +regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro +regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro +regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro +regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro +regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro +regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro +regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro +regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro +regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro +regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro +regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_PA_CINVOC_COUNT_LO = 0x2028 # macro +regCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_PA_CINVOC_COUNT_HI = 0x2029 # macro +regCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_PA_CPRIM_COUNT_LO = 0x202a # macro +regCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro +regCP_PA_CPRIM_COUNT_HI = 0x202b # macro +regCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro +regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro +regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro +regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro +regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro +regCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro +regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro +regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_ASINVOC_COUNT_LO = 0x2032 # macro +regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_ASINVOC_COUNT_HI = 0x2033 # macro +regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_PIPE_STATS_CONTROL = 0x203d # macro +regCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro +regSCRATCH_REG0 = 0x2040 # macro +regSCRATCH_REG0_BASE_IDX = 1 # macro +regSCRATCH_REG1 = 0x2041 # macro +regSCRATCH_REG1_BASE_IDX = 1 # macro +regSCRATCH_REG2 = 0x2042 # macro +regSCRATCH_REG2_BASE_IDX = 1 # macro +regSCRATCH_REG3 = 0x2043 # macro +regSCRATCH_REG3_BASE_IDX = 1 # macro +regSCRATCH_REG4 = 0x2044 # macro +regSCRATCH_REG4_BASE_IDX = 1 # macro +regSCRATCH_REG5 = 0x2045 # macro +regSCRATCH_REG5_BASE_IDX = 1 # macro +regSCRATCH_REG6 = 0x2046 # macro +regSCRATCH_REG6_BASE_IDX = 1 # macro +regSCRATCH_REG7 = 0x2047 # macro +regSCRATCH_REG7_BASE_IDX = 1 # macro +regSCRATCH_REG_ATOMIC = 0x2048 # macro +regSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro +regSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro +regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro +regCP_APPEND_DDID_CNT = 0x204b # macro +regCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro +regCP_APPEND_DATA_HI = 0x204c # macro +regCP_APPEND_DATA_HI_BASE_IDX = 1 # macro +regCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro +regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro +regCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro +regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro +regCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro +regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +regCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro +regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +regCP_APPEND_ADDR_LO = 0x2058 # macro +regCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro +regCP_APPEND_ADDR_HI = 0x2059 # macro +regCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro +regCP_APPEND_DATA = 0x205a # macro +regCP_APPEND_DATA_BASE_IDX = 1 # macro +regCP_APPEND_DATA_LO = 0x205a # macro +regCP_APPEND_DATA_LO_BASE_IDX = 1 # macro +regCP_APPEND_LAST_CS_FENCE = 0x205b # macro +regCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro +regCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro +regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro +regCP_APPEND_LAST_PS_FENCE = 0x205c # macro +regCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro +regCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro +regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro +regCP_ATOMIC_PREOP_LO = 0x205d # macro +regCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +regCP_ME_ATOMIC_PREOP_LO = 0x205d # macro +regCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +regCP_ATOMIC_PREOP_HI = 0x205e # macro +regCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_ATOMIC_PREOP_HI = 0x205e # macro +regCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro +regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro +regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro +regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro +regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro +regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro +regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro +regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro +regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_MC_WADDR_LO = 0x2069 # macro +regCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro +regCP_ME_MC_WADDR_HI = 0x206a # macro +regCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro +regCP_ME_MC_WDATA_LO = 0x206b # macro +regCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro +regCP_ME_MC_WDATA_HI = 0x206c # macro +regCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro +regCP_ME_MC_RADDR_LO = 0x206d # macro +regCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro +regCP_ME_MC_RADDR_HI = 0x206e # macro +regCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro +regCP_SEM_WAIT_TIMER = 0x206f # macro +regCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro +regCP_SIG_SEM_ADDR_LO = 0x2070 # macro +regCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro +regCP_SIG_SEM_ADDR_HI = 0x2071 # macro +regCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro +regCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro +regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro +regCP_WAIT_SEM_ADDR_LO = 0x2075 # macro +regCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro +regCP_WAIT_SEM_ADDR_HI = 0x2076 # macro +regCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_PFP_CONTROL = 0x2077 # macro +regCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro +regCP_DMA_ME_CONTROL = 0x2078 # macro +regCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro +regCP_DMA_ME_SRC_ADDR = 0x2080 # macro +regCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro +regCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro +regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_ME_DST_ADDR = 0x2082 # macro +regCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro +regCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro +regCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_ME_COMMAND = 0x2084 # macro +regCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro +regCP_DMA_PFP_SRC_ADDR = 0x2085 # macro +regCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro +regCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro +regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_PFP_DST_ADDR = 0x2087 # macro +regCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro +regCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro +regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_PFP_COMMAND = 0x2089 # macro +regCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro +regCP_DMA_CNTL = 0x208a # macro +regCP_DMA_CNTL_BASE_IDX = 1 # macro +regCP_DMA_READ_TAGS = 0x208b # macro +regCP_DMA_READ_TAGS_BASE_IDX = 1 # macro +regCP_PFP_IB_CONTROL = 0x208d # macro +regCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro +regCP_PFP_LOAD_CONTROL = 0x208e # macro +regCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro +regCP_SCRATCH_INDEX = 0x208f # macro +regCP_SCRATCH_INDEX_BASE_IDX = 1 # macro +regCP_SCRATCH_DATA = 0x2090 # macro +regCP_SCRATCH_DATA_BASE_IDX = 1 # macro +regCP_RB_OFFSET = 0x2091 # macro +regCP_RB_OFFSET_BASE_IDX = 1 # macro +regCP_IB2_OFFSET = 0x2093 # macro +regCP_IB2_OFFSET_BASE_IDX = 1 # macro +regCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro +regCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro +regCP_IB2_PREAMBLE_END = 0x2097 # macro +regCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro +regCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro +regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro +regCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro +regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro +regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro +regCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro +regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro +regCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro +regCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro +regCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro +regCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro +regUCONFIG_RESERVED_REG0 = 0x20a2 # macro +regUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro +regUCONFIG_RESERVED_REG1 = 0x20a3 # macro +regUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro +regCP_PA_MSPRIM_COUNT_LO = 0x20a4 # macro +regCP_PA_MSPRIM_COUNT_LO_BASE_IDX = 1 # macro +regCP_PA_MSPRIM_COUNT_HI = 0x20a5 # macro +regCP_PA_MSPRIM_COUNT_HI_BASE_IDX = 1 # macro +regCP_GE_MSINVOC_COUNT_LO = 0x20a6 # macro +regCP_GE_MSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_GE_MSINVOC_COUNT_HI = 0x20a7 # macro +regCP_GE_MSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_IB1_CMD_BUFSZ = 0x20c0 # macro +regCP_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_IB2_CMD_BUFSZ = 0x20c1 # macro +regCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_ST_CMD_BUFSZ = 0x20c2 # macro +regCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_IB1_BASE_LO = 0x20cc # macro +regCP_IB1_BASE_LO_BASE_IDX = 1 # macro +regCP_IB1_BASE_HI = 0x20cd # macro +regCP_IB1_BASE_HI_BASE_IDX = 1 # macro +regCP_IB1_BUFSZ = 0x20ce # macro +regCP_IB1_BUFSZ_BASE_IDX = 1 # macro +regCP_IB2_BASE_LO = 0x20cf # macro +regCP_IB2_BASE_LO_BASE_IDX = 1 # macro +regCP_IB2_BASE_HI = 0x20d0 # macro +regCP_IB2_BASE_HI_BASE_IDX = 1 # macro +regCP_IB2_BUFSZ = 0x20d1 # macro +regCP_IB2_BUFSZ_BASE_IDX = 1 # macro +regCP_ST_BASE_LO = 0x20d2 # macro +regCP_ST_BASE_LO_BASE_IDX = 1 # macro +regCP_ST_BASE_HI = 0x20d3 # macro +regCP_ST_BASE_HI_BASE_IDX = 1 # macro +regCP_ST_BUFSZ = 0x20d4 # macro +regCP_ST_BUFSZ_BASE_IDX = 1 # macro +regCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro +regCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro +regCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro +regCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro +regCP_EOP_DONE_CNTX_ID = 0x20d7 # macro +regCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro +regCP_DB_BASE_LO = 0x20d8 # macro +regCP_DB_BASE_LO_BASE_IDX = 1 # macro +regCP_DB_BASE_HI = 0x20d9 # macro +regCP_DB_BASE_HI_BASE_IDX = 1 # macro +regCP_DB_BUFSZ = 0x20da # macro +regCP_DB_BUFSZ_BASE_IDX = 1 # macro +regCP_DB_CMD_BUFSZ = 0x20db # macro +regCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_PFP_COMPLETION_STATUS = 0x20ec # macro +regCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro +regCP_PRED_NOT_VISIBLE = 0x20ee # macro +regCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro +regCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro +regCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro +regCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro +regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro +regCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro +regCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro +regCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro +regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro +regCP_DISPATCH_INDR_ADDR = 0x20f6 # macro +regCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro +regCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro +regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro +regCP_INDEX_BASE_ADDR = 0x20f8 # macro +regCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro +regCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro +regCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro +regCP_INDEX_TYPE = 0x20fa # macro +regCP_INDEX_TYPE_BASE_IDX = 1 # macro +regCP_GDS_BKUP_ADDR = 0x20fb # macro +regCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro +regCP_GDS_BKUP_ADDR_HI = 0x20fc # macro +regCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro +regCP_SAMPLE_STATUS = 0x20fd # macro +regCP_SAMPLE_STATUS_BASE_IDX = 1 # macro +regCP_ME_COHER_CNTL = 0x20fe # macro +regCP_ME_COHER_CNTL_BASE_IDX = 1 # macro +regCP_ME_COHER_SIZE = 0x20ff # macro +regCP_ME_COHER_SIZE_BASE_IDX = 1 # macro +regCP_ME_COHER_SIZE_HI = 0x2100 # macro +regCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro +regCP_ME_COHER_BASE = 0x2101 # macro +regCP_ME_COHER_BASE_BASE_IDX = 1 # macro +regCP_ME_COHER_BASE_HI = 0x2102 # macro +regCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro +regCP_ME_COHER_STATUS = 0x2103 # macro +regCP_ME_COHER_STATUS_BASE_IDX = 1 # macro +regRLC_GPM_PERF_COUNT_0 = 0x2140 # macro +regRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro +regRLC_GPM_PERF_COUNT_1 = 0x2141 # macro +regRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro +regGRBM_GFX_INDEX = 0x2200 # macro +regGRBM_GFX_INDEX_BASE_IDX = 1 # macro +regVGT_PRIMITIVE_TYPE = 0x2242 # macro +regVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro +regVGT_INDEX_TYPE = 0x2243 # macro +regVGT_INDEX_TYPE_BASE_IDX = 1 # macro +regGE_MIN_VTX_INDX = 0x2249 # macro +regGE_MIN_VTX_INDX_BASE_IDX = 1 # macro +regGE_INDX_OFFSET = 0x224a # macro +regGE_INDX_OFFSET_BASE_IDX = 1 # macro +regGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro +regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro +regVGT_NUM_INDICES = 0x224c # macro +regVGT_NUM_INDICES_BASE_IDX = 1 # macro +regVGT_NUM_INSTANCES = 0x224d # macro +regVGT_NUM_INSTANCES_BASE_IDX = 1 # macro +regVGT_TF_RING_SIZE = 0x224e # macro +regVGT_TF_RING_SIZE_BASE_IDX = 1 # macro +regVGT_HS_OFFCHIP_PARAM = 0x224f # macro +regVGT_HS_OFFCHIP_PARAM_BASE_IDX = 1 # macro +regVGT_TF_MEMORY_BASE = 0x2250 # macro +regVGT_TF_MEMORY_BASE_BASE_IDX = 1 # macro +regGE_MAX_VTX_INDX = 0x2259 # macro +regGE_MAX_VTX_INDX_BASE_IDX = 1 # macro +regVGT_INSTANCE_BASE_ID = 0x225a # macro +regVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro +regGE_CNTL = 0x225b # macro +regGE_CNTL_BASE_IDX = 1 # macro +regGE_USER_VGPR1 = 0x225c # macro +regGE_USER_VGPR1_BASE_IDX = 1 # macro +regGE_USER_VGPR2 = 0x225d # macro +regGE_USER_VGPR2_BASE_IDX = 1 # macro +regGE_USER_VGPR3 = 0x225e # macro +regGE_USER_VGPR3_BASE_IDX = 1 # macro +regGE_STEREO_CNTL = 0x225f # macro +regGE_STEREO_CNTL_BASE_IDX = 1 # macro +regGE_PC_ALLOC = 0x2260 # macro +regGE_PC_ALLOC_BASE_IDX = 1 # macro +regVGT_TF_MEMORY_BASE_HI = 0x2261 # macro +regVGT_TF_MEMORY_BASE_HI_BASE_IDX = 1 # macro +regGE_USER_VGPR_EN = 0x2262 # macro +regGE_USER_VGPR_EN_BASE_IDX = 1 # macro +regGE_GS_FAST_LAUNCH_WG_DIM = 0x2264 # macro +regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX = 1 # macro +regGE_GS_FAST_LAUNCH_WG_DIM_1 = 0x2265 # macro +regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX = 1 # macro +regVGT_GS_OUT_PRIM_TYPE = 0x2266 # macro +regVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro +regPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro +regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro +regPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro +regPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro +regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro +regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro +regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro +regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro +regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro +regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro +regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro +regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro +regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro +regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro +regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro +regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro +regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro +regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_H = 0x22b1 # macro +regPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_V = 0x22b2 # macro +regPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro +regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro +regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro +regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro +regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro +regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro +regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro +regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro +regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro +regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro +regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro +regSQC_CACHES = 0x2348 # macro +regSQC_CACHES_BASE_IDX = 1 # macro +regTA_CS_BC_BASE_ADDR = 0x2380 # macro +regTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro +regTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro +regTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro +regDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro +regDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro +regDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro +regDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro +regDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro +regDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro +regDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro +regDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro +regGDS_RD_ADDR = 0x2400 # macro +regGDS_RD_ADDR_BASE_IDX = 1 # macro +regGDS_RD_DATA = 0x2401 # macro +regGDS_RD_DATA_BASE_IDX = 1 # macro +regGDS_RD_BURST_ADDR = 0x2402 # macro +regGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro +regGDS_RD_BURST_COUNT = 0x2403 # macro +regGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro +regGDS_RD_BURST_DATA = 0x2404 # macro +regGDS_RD_BURST_DATA_BASE_IDX = 1 # macro +regGDS_WR_ADDR = 0x2405 # macro +regGDS_WR_ADDR_BASE_IDX = 1 # macro +regGDS_WR_DATA = 0x2406 # macro +regGDS_WR_DATA_BASE_IDX = 1 # macro +regGDS_WR_BURST_ADDR = 0x2407 # macro +regGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro +regGDS_WR_BURST_DATA = 0x2408 # macro +regGDS_WR_BURST_DATA_BASE_IDX = 1 # macro +regGDS_WRITE_COMPLETE = 0x2409 # macro +regGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro +regGDS_ATOM_CNTL = 0x240a # macro +regGDS_ATOM_CNTL_BASE_IDX = 1 # macro +regGDS_ATOM_COMPLETE = 0x240b # macro +regGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro +regGDS_ATOM_BASE = 0x240c # macro +regGDS_ATOM_BASE_BASE_IDX = 1 # macro +regGDS_ATOM_SIZE = 0x240d # macro +regGDS_ATOM_SIZE_BASE_IDX = 1 # macro +regGDS_ATOM_OFFSET0 = 0x240e # macro +regGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro +regGDS_ATOM_OFFSET1 = 0x240f # macro +regGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro +regGDS_ATOM_DST = 0x2410 # macro +regGDS_ATOM_DST_BASE_IDX = 1 # macro +regGDS_ATOM_OP = 0x2411 # macro +regGDS_ATOM_OP_BASE_IDX = 1 # macro +regGDS_ATOM_SRC0 = 0x2412 # macro +regGDS_ATOM_SRC0_BASE_IDX = 1 # macro +regGDS_ATOM_SRC0_U = 0x2413 # macro +regGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro +regGDS_ATOM_SRC1 = 0x2414 # macro +regGDS_ATOM_SRC1_BASE_IDX = 1 # macro +regGDS_ATOM_SRC1_U = 0x2415 # macro +regGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro +regGDS_ATOM_READ0 = 0x2416 # macro +regGDS_ATOM_READ0_BASE_IDX = 1 # macro +regGDS_ATOM_READ0_U = 0x2417 # macro +regGDS_ATOM_READ0_U_BASE_IDX = 1 # macro +regGDS_ATOM_READ1 = 0x2418 # macro +regGDS_ATOM_READ1_BASE_IDX = 1 # macro +regGDS_ATOM_READ1_U = 0x2419 # macro +regGDS_ATOM_READ1_U_BASE_IDX = 1 # macro +regGDS_GWS_RESOURCE_CNTL = 0x241a # macro +regGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro +regGDS_GWS_RESOURCE = 0x241b # macro +regGDS_GWS_RESOURCE_BASE_IDX = 1 # macro +regGDS_GWS_RESOURCE_CNT = 0x241c # macro +regGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro +regGDS_OA_CNTL = 0x241d # macro +regGDS_OA_CNTL_BASE_IDX = 1 # macro +regGDS_OA_COUNTER = 0x241e # macro +regGDS_OA_COUNTER_BASE_IDX = 1 # macro +regGDS_OA_ADDRESS = 0x241f # macro +regGDS_OA_ADDRESS_BASE_IDX = 1 # macro +regGDS_OA_INCDEC = 0x2420 # macro +regGDS_OA_INCDEC_BASE_IDX = 1 # macro +regGDS_OA_RING_SIZE = 0x2421 # macro +regGDS_OA_RING_SIZE_BASE_IDX = 1 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_0 = 0x2422 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX = 1 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_1 = 0x2423 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX = 1 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_2 = 0x2424 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX = 1 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_3 = 0x2425 # macro +regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX = 1 # macro +regGDS_GS_0 = 0x2426 # macro +regGDS_GS_0_BASE_IDX = 1 # macro +regGDS_GS_1 = 0x2427 # macro +regGDS_GS_1_BASE_IDX = 1 # macro +regGDS_GS_2 = 0x2428 # macro +regGDS_GS_2_BASE_IDX = 1 # macro +regGDS_GS_3 = 0x2429 # macro +regGDS_GS_3_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_0_LO = 0x242a # macro +regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_0_HI = 0x242b # macro +regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_0_LO = 0x242c # macro +regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_0_HI = 0x242d # macro +regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_1_LO = 0x242e # macro +regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_1_HI = 0x242f # macro +regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_1_LO = 0x2430 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_1_HI = 0x2431 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_2_LO = 0x2432 # macro +regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_2_HI = 0x2433 # macro +regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_2_LO = 0x2434 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_2_HI = 0x2435 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_3_LO = 0x2436 # macro +regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_NEEDED_3_HI = 0x2437 # macro +regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_3_LO = 0x2438 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX = 1 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_3_HI = 0x2439 # macro +regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX = 1 # macro +regSPI_CONFIG_CNTL = 0x2440 # macro +regSPI_CONFIG_CNTL_BASE_IDX = 1 # macro +regSPI_CONFIG_CNTL_1 = 0x2441 # macro +regSPI_CONFIG_CNTL_1_BASE_IDX = 1 # macro +regSPI_CONFIG_CNTL_2 = 0x2442 # macro +regSPI_CONFIG_CNTL_2_BASE_IDX = 1 # macro +regSPI_WAVE_LIMIT_CNTL = 0x2443 # macro +regSPI_WAVE_LIMIT_CNTL_BASE_IDX = 1 # macro +regSPI_GS_THROTTLE_CNTL1 = 0x2444 # macro +regSPI_GS_THROTTLE_CNTL1_BASE_IDX = 1 # macro +regSPI_GS_THROTTLE_CNTL2 = 0x2445 # macro +regSPI_GS_THROTTLE_CNTL2_BASE_IDX = 1 # macro +regSPI_ATTRIBUTE_RING_BASE = 0x2446 # macro +regSPI_ATTRIBUTE_RING_BASE_BASE_IDX = 1 # macro +regSPI_ATTRIBUTE_RING_SIZE = 0x2447 # macro +regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX = 1 # macro +regCP_MES_PRGRM_CNTR_START = 0x2800 # macro +regCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro +regCP_MES_INTR_ROUTINE_START = 0x2801 # macro +regCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro +regCP_MES_MTVEC_LO = 0x2801 # macro +regCP_MES_MTVEC_LO_BASE_IDX = 1 # macro +regCP_MES_INTR_ROUTINE_START_HI = 0x2802 # macro +regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX = 1 # macro +regCP_MES_MTVEC_HI = 0x2802 # macro +regCP_MES_MTVEC_HI_BASE_IDX = 1 # macro +regCP_MES_CNTL = 0x2807 # macro +regCP_MES_CNTL_BASE_IDX = 1 # macro +regCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro +regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro +regCP_MES_PIPE0_PRIORITY = 0x2809 # macro +regCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro +regCP_MES_PIPE1_PRIORITY = 0x280a # macro +regCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro +regCP_MES_PIPE2_PRIORITY = 0x280b # macro +regCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro +regCP_MES_PIPE3_PRIORITY = 0x280c # macro +regCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro +regCP_MES_HEADER_DUMP = 0x280d # macro +regCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro +regCP_MES_MIE_LO = 0x280e # macro +regCP_MES_MIE_LO_BASE_IDX = 1 # macro +regCP_MES_MIE_HI = 0x280f # macro +regCP_MES_MIE_HI_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT = 0x2810 # macro +regCP_MES_INTERRUPT_BASE_IDX = 1 # macro +regCP_MES_SCRATCH_INDEX = 0x2811 # macro +regCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro +regCP_MES_SCRATCH_DATA = 0x2812 # macro +regCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro +regCP_MES_INSTR_PNTR = 0x2813 # macro +regCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro +regCP_MES_MSCRATCH_HI = 0x2814 # macro +regCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro +regCP_MES_MSCRATCH_LO = 0x2815 # macro +regCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro +regCP_MES_MSTATUS_LO = 0x2816 # macro +regCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro +regCP_MES_MSTATUS_HI = 0x2817 # macro +regCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro +regCP_MES_MEPC_LO = 0x2818 # macro +regCP_MES_MEPC_LO_BASE_IDX = 1 # macro +regCP_MES_MEPC_HI = 0x2819 # macro +regCP_MES_MEPC_HI_BASE_IDX = 1 # macro +regCP_MES_MCAUSE_LO = 0x281a # macro +regCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro +regCP_MES_MCAUSE_HI = 0x281b # macro +regCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro +regCP_MES_MBADADDR_LO = 0x281c # macro +regCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro +regCP_MES_MBADADDR_HI = 0x281d # macro +regCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro +regCP_MES_MIP_LO = 0x281e # macro +regCP_MES_MIP_LO_BASE_IDX = 1 # macro +regCP_MES_MIP_HI = 0x281f # macro +regCP_MES_MIP_HI_BASE_IDX = 1 # macro +regCP_MES_IC_OP_CNTL = 0x2820 # macro +regCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro +regCP_MES_MCYCLE_LO = 0x2826 # macro +regCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro +regCP_MES_MCYCLE_HI = 0x2827 # macro +regCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro +regCP_MES_MTIME_LO = 0x2828 # macro +regCP_MES_MTIME_LO_BASE_IDX = 1 # macro +regCP_MES_MTIME_HI = 0x2829 # macro +regCP_MES_MTIME_HI_BASE_IDX = 1 # macro +regCP_MES_MINSTRET_LO = 0x282a # macro +regCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro +regCP_MES_MINSTRET_HI = 0x282b # macro +regCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro +regCP_MES_MISA_LO = 0x282c # macro +regCP_MES_MISA_LO_BASE_IDX = 1 # macro +regCP_MES_MISA_HI = 0x282d # macro +regCP_MES_MISA_HI_BASE_IDX = 1 # macro +regCP_MES_MVENDORID_LO = 0x282e # macro +regCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro +regCP_MES_MVENDORID_HI = 0x282f # macro +regCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro +regCP_MES_MARCHID_LO = 0x2830 # macro +regCP_MES_MARCHID_LO_BASE_IDX = 1 # macro +regCP_MES_MARCHID_HI = 0x2831 # macro +regCP_MES_MARCHID_HI_BASE_IDX = 1 # macro +regCP_MES_MIMPID_LO = 0x2832 # macro +regCP_MES_MIMPID_LO_BASE_IDX = 1 # macro +regCP_MES_MIMPID_HI = 0x2833 # macro +regCP_MES_MIMPID_HI_BASE_IDX = 1 # macro +regCP_MES_MHARTID_LO = 0x2834 # macro +regCP_MES_MHARTID_LO_BASE_IDX = 1 # macro +regCP_MES_MHARTID_HI = 0x2835 # macro +regCP_MES_MHARTID_HI_BASE_IDX = 1 # macro +regCP_MES_DC_BASE_CNTL = 0x2836 # macro +regCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_OP_CNTL = 0x2837 # macro +regCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro +regCP_MES_MTIMECMP_LO = 0x2838 # macro +regCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro +regCP_MES_MTIMECMP_HI = 0x2839 # macro +regCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro +regCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro +regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro +regCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro +regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro +regCP_MES_DOORBELL_CONTROL1 = 0x283c # macro +regCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro +regCP_MES_DOORBELL_CONTROL2 = 0x283d # macro +regCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro +regCP_MES_DOORBELL_CONTROL3 = 0x283e # macro +regCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro +regCP_MES_DOORBELL_CONTROL4 = 0x283f # macro +regCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro +regCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro +regCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro +regCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro +regCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro +regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR = 0x2842 # macro +regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX = 1 # macro +regCP_MES_GP0_LO = 0x2843 # macro +regCP_MES_GP0_LO_BASE_IDX = 1 # macro +regCP_MES_GP0_HI = 0x2844 # macro +regCP_MES_GP0_HI_BASE_IDX = 1 # macro +regCP_MES_GP1_LO = 0x2845 # macro +regCP_MES_GP1_LO_BASE_IDX = 1 # macro +regCP_MES_GP1_HI = 0x2846 # macro +regCP_MES_GP1_HI_BASE_IDX = 1 # macro +regCP_MES_GP2_LO = 0x2847 # macro +regCP_MES_GP2_LO_BASE_IDX = 1 # macro +regCP_MES_GP2_HI = 0x2848 # macro +regCP_MES_GP2_HI_BASE_IDX = 1 # macro +regCP_MES_GP3_LO = 0x2849 # macro +regCP_MES_GP3_LO_BASE_IDX = 1 # macro +regCP_MES_GP3_HI = 0x284a # macro +regCP_MES_GP3_HI_BASE_IDX = 1 # macro +regCP_MES_GP4_LO = 0x284b # macro +regCP_MES_GP4_LO_BASE_IDX = 1 # macro +regCP_MES_GP4_HI = 0x284c # macro +regCP_MES_GP4_HI_BASE_IDX = 1 # macro +regCP_MES_GP5_LO = 0x284d # macro +regCP_MES_GP5_LO_BASE_IDX = 1 # macro +regCP_MES_GP5_HI = 0x284e # macro +regCP_MES_GP5_HI_BASE_IDX = 1 # macro +regCP_MES_GP6_LO = 0x284f # macro +regCP_MES_GP6_LO_BASE_IDX = 1 # macro +regCP_MES_GP6_HI = 0x2850 # macro +regCP_MES_GP6_HI_BASE_IDX = 1 # macro +regCP_MES_GP7_LO = 0x2851 # macro +regCP_MES_GP7_LO_BASE_IDX = 1 # macro +regCP_MES_GP7_HI = 0x2852 # macro +regCP_MES_GP7_HI_BASE_IDX = 1 # macro +regCP_MES_GP8_LO = 0x2853 # macro +regCP_MES_GP8_LO_BASE_IDX = 1 # macro +regCP_MES_GP8_HI = 0x2854 # macro +regCP_MES_GP8_HI_BASE_IDX = 1 # macro +regCP_MES_GP9_LO = 0x2855 # macro +regCP_MES_GP9_LO_BASE_IDX = 1 # macro +regCP_MES_GP9_HI = 0x2856 # macro +regCP_MES_GP9_HI_BASE_IDX = 1 # macro +regCP_MES_LOCAL_BASE0_LO = 0x2883 # macro +regCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro +regCP_MES_LOCAL_BASE0_HI = 0x2884 # macro +regCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro +regCP_MES_LOCAL_MASK0_LO = 0x2885 # macro +regCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro +regCP_MES_LOCAL_MASK0_HI = 0x2886 # macro +regCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro +regCP_MES_LOCAL_APERTURE = 0x2887 # macro +regCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro +regCP_MES_LOCAL_INSTR_BASE_LO = 0x2888 # macro +regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro +regCP_MES_LOCAL_INSTR_BASE_HI = 0x2889 # macro +regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro +regCP_MES_LOCAL_INSTR_MASK_LO = 0x288a # macro +regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro +regCP_MES_LOCAL_INSTR_MASK_HI = 0x288b # macro +regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro +regCP_MES_LOCAL_INSTR_APERTURE = 0x288c # macro +regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro +regCP_MES_LOCAL_SCRATCH_APERTURE = 0x288d # macro +regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro +regCP_MES_LOCAL_SCRATCH_BASE_LO = 0x288e # macro +regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro +regCP_MES_LOCAL_SCRATCH_BASE_HI = 0x288f # macro +regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro +regCP_MES_PERFCOUNT_CNTL = 0x2899 # macro +regCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro +regCP_MES_PENDING_INTERRUPT = 0x289a # macro +regCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro +regCP_MES_PRGRM_CNTR_START_HI = 0x289d # macro +regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_16 = 0x289f # macro +regCP_MES_INTERRUPT_DATA_16_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_17 = 0x28a0 # macro +regCP_MES_INTERRUPT_DATA_17_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_18 = 0x28a1 # macro +regCP_MES_INTERRUPT_DATA_18_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_19 = 0x28a2 # macro +regCP_MES_INTERRUPT_DATA_19_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_20 = 0x28a3 # macro +regCP_MES_INTERRUPT_DATA_20_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_21 = 0x28a4 # macro +regCP_MES_INTERRUPT_DATA_21_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_22 = 0x28a5 # macro +regCP_MES_INTERRUPT_DATA_22_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_23 = 0x28a6 # macro +regCP_MES_INTERRUPT_DATA_23_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_24 = 0x28a7 # macro +regCP_MES_INTERRUPT_DATA_24_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_25 = 0x28a8 # macro +regCP_MES_INTERRUPT_DATA_25_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_26 = 0x28a9 # macro +regCP_MES_INTERRUPT_DATA_26_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_27 = 0x28aa # macro +regCP_MES_INTERRUPT_DATA_27_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_28 = 0x28ab # macro +regCP_MES_INTERRUPT_DATA_28_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_29 = 0x28ac # macro +regCP_MES_INTERRUPT_DATA_29_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_30 = 0x28ad # macro +regCP_MES_INTERRUPT_DATA_30_BASE_IDX = 1 # macro +regCP_MES_INTERRUPT_DATA_31 = 0x28ae # macro +regCP_MES_INTERRUPT_DATA_31_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE0_BASE = 0x28af # macro +regCP_MES_DC_APERTURE0_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE0_MASK = 0x28b0 # macro +regCP_MES_DC_APERTURE0_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE0_CNTL = 0x28b1 # macro +regCP_MES_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE1_BASE = 0x28b2 # macro +regCP_MES_DC_APERTURE1_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE1_MASK = 0x28b3 # macro +regCP_MES_DC_APERTURE1_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE1_CNTL = 0x28b4 # macro +regCP_MES_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE2_BASE = 0x28b5 # macro +regCP_MES_DC_APERTURE2_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE2_MASK = 0x28b6 # macro +regCP_MES_DC_APERTURE2_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE2_CNTL = 0x28b7 # macro +regCP_MES_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE3_BASE = 0x28b8 # macro +regCP_MES_DC_APERTURE3_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE3_MASK = 0x28b9 # macro +regCP_MES_DC_APERTURE3_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE3_CNTL = 0x28ba # macro +regCP_MES_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE4_BASE = 0x28bb # macro +regCP_MES_DC_APERTURE4_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE4_MASK = 0x28bc # macro +regCP_MES_DC_APERTURE4_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE4_CNTL = 0x28bd # macro +regCP_MES_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE5_BASE = 0x28be # macro +regCP_MES_DC_APERTURE5_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE5_MASK = 0x28bf # macro +regCP_MES_DC_APERTURE5_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE5_CNTL = 0x28c0 # macro +regCP_MES_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE6_BASE = 0x28c1 # macro +regCP_MES_DC_APERTURE6_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE6_MASK = 0x28c2 # macro +regCP_MES_DC_APERTURE6_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE6_CNTL = 0x28c3 # macro +regCP_MES_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE7_BASE = 0x28c4 # macro +regCP_MES_DC_APERTURE7_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE7_MASK = 0x28c5 # macro +regCP_MES_DC_APERTURE7_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE7_CNTL = 0x28c6 # macro +regCP_MES_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE8_BASE = 0x28c7 # macro +regCP_MES_DC_APERTURE8_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE8_MASK = 0x28c8 # macro +regCP_MES_DC_APERTURE8_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE8_CNTL = 0x28c9 # macro +regCP_MES_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE9_BASE = 0x28ca # macro +regCP_MES_DC_APERTURE9_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE9_MASK = 0x28cb # macro +regCP_MES_DC_APERTURE9_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE9_CNTL = 0x28cc # macro +regCP_MES_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE10_BASE = 0x28cd # macro +regCP_MES_DC_APERTURE10_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE10_MASK = 0x28ce # macro +regCP_MES_DC_APERTURE10_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE10_CNTL = 0x28cf # macro +regCP_MES_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE11_BASE = 0x28d0 # macro +regCP_MES_DC_APERTURE11_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE11_MASK = 0x28d1 # macro +regCP_MES_DC_APERTURE11_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE11_CNTL = 0x28d2 # macro +regCP_MES_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE12_BASE = 0x28d3 # macro +regCP_MES_DC_APERTURE12_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE12_MASK = 0x28d4 # macro +regCP_MES_DC_APERTURE12_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE12_CNTL = 0x28d5 # macro +regCP_MES_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE13_BASE = 0x28d6 # macro +regCP_MES_DC_APERTURE13_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE13_MASK = 0x28d7 # macro +regCP_MES_DC_APERTURE13_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE13_CNTL = 0x28d8 # macro +regCP_MES_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE14_BASE = 0x28d9 # macro +regCP_MES_DC_APERTURE14_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE14_MASK = 0x28da # macro +regCP_MES_DC_APERTURE14_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE14_CNTL = 0x28db # macro +regCP_MES_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE15_BASE = 0x28dc # macro +regCP_MES_DC_APERTURE15_BASE_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE15_MASK = 0x28dd # macro +regCP_MES_DC_APERTURE15_MASK_BASE_IDX = 1 # macro +regCP_MES_DC_APERTURE15_CNTL = 0x28de # macro +regCP_MES_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro +regCP_MEC_RS64_PRGRM_CNTR_START = 0x2900 # macro +regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX = 1 # macro +regCP_MEC_MTVEC_LO = 0x2901 # macro +regCP_MEC_MTVEC_LO_BASE_IDX = 1 # macro +regCP_MEC_MTVEC_HI = 0x2902 # macro +regCP_MEC_MTVEC_HI_BASE_IDX = 1 # macro +regCP_MEC_ISA_CNTL = 0x2903 # macro +regCP_MEC_ISA_CNTL_BASE_IDX = 1 # macro +regCP_MEC_RS64_CNTL = 0x2904 # macro +regCP_MEC_RS64_CNTL_BASE_IDX = 1 # macro +regCP_MEC_MIE_LO = 0x2905 # macro +regCP_MEC_MIE_LO_BASE_IDX = 1 # macro +regCP_MEC_MIE_HI = 0x2906 # macro +regCP_MEC_MIE_HI_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT = 0x2907 # macro +regCP_MEC_RS64_INTERRUPT_BASE_IDX = 1 # macro +regCP_MEC_RS64_INSTR_PNTR = 0x2908 # macro +regCP_MEC_RS64_INSTR_PNTR_BASE_IDX = 1 # macro +regCP_MEC_MIP_LO = 0x2909 # macro +regCP_MEC_MIP_LO_BASE_IDX = 1 # macro +regCP_MEC_MIP_HI = 0x290a # macro +regCP_MEC_MIP_HI_BASE_IDX = 1 # macro +regCP_MEC_DC_BASE_CNTL = 0x290b # macro +regCP_MEC_DC_BASE_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_OP_CNTL = 0x290c # macro +regCP_MEC_DC_OP_CNTL_BASE_IDX = 1 # macro +regCP_MEC_MTIMECMP_LO = 0x290d # macro +regCP_MEC_MTIMECMP_LO_BASE_IDX = 1 # macro +regCP_MEC_MTIMECMP_HI = 0x290e # macro +regCP_MEC_MTIMECMP_HI_BASE_IDX = 1 # macro +regCP_MEC_GP0_LO = 0x2910 # macro +regCP_MEC_GP0_LO_BASE_IDX = 1 # macro +regCP_MEC_GP0_HI = 0x2911 # macro +regCP_MEC_GP0_HI_BASE_IDX = 1 # macro +regCP_MEC_GP1_LO = 0x2912 # macro +regCP_MEC_GP1_LO_BASE_IDX = 1 # macro +regCP_MEC_GP1_HI = 0x2913 # macro +regCP_MEC_GP1_HI_BASE_IDX = 1 # macro +regCP_MEC_GP2_LO = 0x2914 # macro +regCP_MEC_GP2_LO_BASE_IDX = 1 # macro +regCP_MEC_GP2_HI = 0x2915 # macro +regCP_MEC_GP2_HI_BASE_IDX = 1 # macro +regCP_MEC_GP3_LO = 0x2916 # macro +regCP_MEC_GP3_LO_BASE_IDX = 1 # macro +regCP_MEC_GP3_HI = 0x2917 # macro +regCP_MEC_GP3_HI_BASE_IDX = 1 # macro +regCP_MEC_GP4_LO = 0x2918 # macro +regCP_MEC_GP4_LO_BASE_IDX = 1 # macro +regCP_MEC_GP4_HI = 0x2919 # macro +regCP_MEC_GP4_HI_BASE_IDX = 1 # macro +regCP_MEC_GP5_LO = 0x291a # macro +regCP_MEC_GP5_LO_BASE_IDX = 1 # macro +regCP_MEC_GP5_HI = 0x291b # macro +regCP_MEC_GP5_HI_BASE_IDX = 1 # macro +regCP_MEC_GP6_LO = 0x291c # macro +regCP_MEC_GP6_LO_BASE_IDX = 1 # macro +regCP_MEC_GP6_HI = 0x291d # macro +regCP_MEC_GP6_HI_BASE_IDX = 1 # macro +regCP_MEC_GP7_LO = 0x291e # macro +regCP_MEC_GP7_LO_BASE_IDX = 1 # macro +regCP_MEC_GP7_HI = 0x291f # macro +regCP_MEC_GP7_HI_BASE_IDX = 1 # macro +regCP_MEC_GP8_LO = 0x2920 # macro +regCP_MEC_GP8_LO_BASE_IDX = 1 # macro +regCP_MEC_GP8_HI = 0x2921 # macro +regCP_MEC_GP8_HI_BASE_IDX = 1 # macro +regCP_MEC_GP9_LO = 0x2922 # macro +regCP_MEC_GP9_LO_BASE_IDX = 1 # macro +regCP_MEC_GP9_HI = 0x2923 # macro +regCP_MEC_GP9_HI_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_BASE0_LO = 0x2927 # macro +regCP_MEC_LOCAL_BASE0_LO_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_BASE0_HI = 0x2928 # macro +regCP_MEC_LOCAL_BASE0_HI_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_MASK0_LO = 0x2929 # macro +regCP_MEC_LOCAL_MASK0_LO_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_MASK0_HI = 0x292a # macro +regCP_MEC_LOCAL_MASK0_HI_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_APERTURE = 0x292b # macro +regCP_MEC_LOCAL_APERTURE_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_INSTR_BASE_LO = 0x292c # macro +regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_INSTR_BASE_HI = 0x292d # macro +regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_INSTR_MASK_LO = 0x292e # macro +regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_INSTR_MASK_HI = 0x292f # macro +regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_INSTR_APERTURE = 0x2930 # macro +regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_SCRATCH_APERTURE = 0x2931 # macro +regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_SCRATCH_BASE_LO = 0x2932 # macro +regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro +regCP_MEC_LOCAL_SCRATCH_BASE_HI = 0x2933 # macro +regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro +regCP_MEC_RS64_PERFCOUNT_CNTL = 0x2934 # macro +regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX = 1 # macro +regCP_MEC_RS64_PENDING_INTERRUPT = 0x2935 # macro +regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX = 1 # macro +regCP_MEC_RS64_PRGRM_CNTR_START_HI = 0x2938 # macro +regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_16 = 0x293a # macro +regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_17 = 0x293b # macro +regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_18 = 0x293c # macro +regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_19 = 0x293d # macro +regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_20 = 0x293e # macro +regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_21 = 0x293f # macro +regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_22 = 0x2940 # macro +regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_23 = 0x2941 # macro +regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_24 = 0x2942 # macro +regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_25 = 0x2943 # macro +regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_26 = 0x2944 # macro +regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_27 = 0x2945 # macro +regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_28 = 0x2946 # macro +regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_29 = 0x2947 # macro +regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_30 = 0x2948 # macro +regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX = 1 # macro +regCP_MEC_RS64_INTERRUPT_DATA_31 = 0x2949 # macro +regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE0_BASE = 0x294a # macro +regCP_MEC_DC_APERTURE0_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE0_MASK = 0x294b # macro +regCP_MEC_DC_APERTURE0_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE0_CNTL = 0x294c # macro +regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE1_BASE = 0x294d # macro +regCP_MEC_DC_APERTURE1_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE1_MASK = 0x294e # macro +regCP_MEC_DC_APERTURE1_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE1_CNTL = 0x294f # macro +regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE2_BASE = 0x2950 # macro +regCP_MEC_DC_APERTURE2_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE2_MASK = 0x2951 # macro +regCP_MEC_DC_APERTURE2_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE2_CNTL = 0x2952 # macro +regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE3_BASE = 0x2953 # macro +regCP_MEC_DC_APERTURE3_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE3_MASK = 0x2954 # macro +regCP_MEC_DC_APERTURE3_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE3_CNTL = 0x2955 # macro +regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE4_BASE = 0x2956 # macro +regCP_MEC_DC_APERTURE4_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE4_MASK = 0x2957 # macro +regCP_MEC_DC_APERTURE4_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE4_CNTL = 0x2958 # macro +regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE5_BASE = 0x2959 # macro +regCP_MEC_DC_APERTURE5_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE5_MASK = 0x295a # macro +regCP_MEC_DC_APERTURE5_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE5_CNTL = 0x295b # macro +regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE6_BASE = 0x295c # macro +regCP_MEC_DC_APERTURE6_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE6_MASK = 0x295d # macro +regCP_MEC_DC_APERTURE6_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE6_CNTL = 0x295e # macro +regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE7_BASE = 0x295f # macro +regCP_MEC_DC_APERTURE7_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE7_MASK = 0x2960 # macro +regCP_MEC_DC_APERTURE7_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE7_CNTL = 0x2961 # macro +regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE8_BASE = 0x2962 # macro +regCP_MEC_DC_APERTURE8_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE8_MASK = 0x2963 # macro +regCP_MEC_DC_APERTURE8_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE8_CNTL = 0x2964 # macro +regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE9_BASE = 0x2965 # macro +regCP_MEC_DC_APERTURE9_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE9_MASK = 0x2966 # macro +regCP_MEC_DC_APERTURE9_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE9_CNTL = 0x2967 # macro +regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE10_BASE = 0x2968 # macro +regCP_MEC_DC_APERTURE10_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE10_MASK = 0x2969 # macro +regCP_MEC_DC_APERTURE10_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE10_CNTL = 0x296a # macro +regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE11_BASE = 0x296b # macro +regCP_MEC_DC_APERTURE11_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE11_MASK = 0x296c # macro +regCP_MEC_DC_APERTURE11_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE11_CNTL = 0x296d # macro +regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE12_BASE = 0x296e # macro +regCP_MEC_DC_APERTURE12_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE12_MASK = 0x296f # macro +regCP_MEC_DC_APERTURE12_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE12_CNTL = 0x2970 # macro +regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE13_BASE = 0x2971 # macro +regCP_MEC_DC_APERTURE13_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE13_MASK = 0x2972 # macro +regCP_MEC_DC_APERTURE13_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE13_CNTL = 0x2973 # macro +regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE14_BASE = 0x2974 # macro +regCP_MEC_DC_APERTURE14_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE14_MASK = 0x2975 # macro +regCP_MEC_DC_APERTURE14_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE14_CNTL = 0x2976 # macro +regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE15_BASE = 0x2977 # macro +regCP_MEC_DC_APERTURE15_BASE_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE15_MASK = 0x2978 # macro +regCP_MEC_DC_APERTURE15_MASK_BASE_IDX = 1 # macro +regCP_MEC_DC_APERTURE15_CNTL = 0x2979 # macro +regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro +regCP_CPC_IC_OP_CNTL = 0x297a # macro +regCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro +regCP_GFX_CNTL = 0x2a00 # macro +regCP_GFX_CNTL_BASE_IDX = 1 # macro +regCP_GFX_RS64_INTERRUPT0 = 0x2a01 # macro +regCP_GFX_RS64_INTERRUPT0_BASE_IDX = 1 # macro +regCP_GFX_RS64_INTR_EN0 = 0x2a02 # macro +regCP_GFX_RS64_INTR_EN0_BASE_IDX = 1 # macro +regCP_GFX_RS64_INTR_EN1 = 0x2a03 # macro +regCP_GFX_RS64_INTR_EN1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_BASE_CNTL = 0x2a08 # macro +regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_OP_CNTL = 0x2a09 # macro +regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_BASE0_LO = 0x2a0a # macro +regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_BASE0_HI = 0x2a0b # macro +regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_MASK0_LO = 0x2a0c # macro +regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_MASK0_HI = 0x2a0d # macro +regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_APERTURE = 0x2a0e # macro +regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_INSTR_BASE_LO = 0x2a0f # macro +regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_INSTR_BASE_HI = 0x2a10 # macro +regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_INSTR_MASK_LO = 0x2a11 # macro +regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_INSTR_MASK_HI = 0x2a12 # macro +regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_INSTR_APERTURE = 0x2a13 # macro +regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE = 0x2a14 # macro +regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO = 0x2a15 # macro +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI = 0x2a16 # macro +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_PERFCOUNT_CNTL0 = 0x2a1a # macro +regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_PERFCOUNT_CNTL1 = 0x2a1b # macro +regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_MIP_LO0 = 0x2a1c # macro +regCP_GFX_RS64_MIP_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_MIP_LO1 = 0x2a1d # macro +regCP_GFX_RS64_MIP_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_MIP_HI0 = 0x2a1e # macro +regCP_GFX_RS64_MIP_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_MIP_HI1 = 0x2a1f # macro +regCP_GFX_RS64_MIP_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_MTIMECMP_LO0 = 0x2a20 # macro +regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_MTIMECMP_LO1 = 0x2a21 # macro +regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_MTIMECMP_HI0 = 0x2a22 # macro +regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_MTIMECMP_HI1 = 0x2a23 # macro +regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP0_LO0 = 0x2a24 # macro +regCP_GFX_RS64_GP0_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP0_LO1 = 0x2a25 # macro +regCP_GFX_RS64_GP0_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP0_HI0 = 0x2a26 # macro +regCP_GFX_RS64_GP0_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP0_HI1 = 0x2a27 # macro +regCP_GFX_RS64_GP0_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP1_LO0 = 0x2a28 # macro +regCP_GFX_RS64_GP1_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP1_LO1 = 0x2a29 # macro +regCP_GFX_RS64_GP1_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP1_HI0 = 0x2a2a # macro +regCP_GFX_RS64_GP1_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP1_HI1 = 0x2a2b # macro +regCP_GFX_RS64_GP1_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP2_LO0 = 0x2a2c # macro +regCP_GFX_RS64_GP2_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP2_LO1 = 0x2a2d # macro +regCP_GFX_RS64_GP2_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP2_HI0 = 0x2a2e # macro +regCP_GFX_RS64_GP2_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP2_HI1 = 0x2a2f # macro +regCP_GFX_RS64_GP2_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP3_LO0 = 0x2a30 # macro +regCP_GFX_RS64_GP3_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP3_LO1 = 0x2a31 # macro +regCP_GFX_RS64_GP3_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP3_HI0 = 0x2a32 # macro +regCP_GFX_RS64_GP3_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP3_HI1 = 0x2a33 # macro +regCP_GFX_RS64_GP3_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP4_LO0 = 0x2a34 # macro +regCP_GFX_RS64_GP4_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP4_LO1 = 0x2a35 # macro +regCP_GFX_RS64_GP4_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP4_HI0 = 0x2a36 # macro +regCP_GFX_RS64_GP4_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP4_HI1 = 0x2a37 # macro +regCP_GFX_RS64_GP4_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP5_LO0 = 0x2a38 # macro +regCP_GFX_RS64_GP5_LO0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP5_LO1 = 0x2a39 # macro +regCP_GFX_RS64_GP5_LO1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP5_HI0 = 0x2a3a # macro +regCP_GFX_RS64_GP5_HI0_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP5_HI1 = 0x2a3b # macro +regCP_GFX_RS64_GP5_HI1_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP6_LO = 0x2a3c # macro +regCP_GFX_RS64_GP6_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP6_HI = 0x2a3d # macro +regCP_GFX_RS64_GP6_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP7_LO = 0x2a3e # macro +regCP_GFX_RS64_GP7_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP7_HI = 0x2a3f # macro +regCP_GFX_RS64_GP7_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP8_LO = 0x2a40 # macro +regCP_GFX_RS64_GP8_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP8_HI = 0x2a41 # macro +regCP_GFX_RS64_GP8_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP9_LO = 0x2a42 # macro +regCP_GFX_RS64_GP9_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_GP9_HI = 0x2a43 # macro +regCP_GFX_RS64_GP9_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_INSTR_PNTR0 = 0x2a44 # macro +regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX = 1 # macro +regCP_GFX_RS64_INSTR_PNTR1 = 0x2a45 # macro +regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX = 1 # macro +regCP_GFX_RS64_PENDING_INTERRUPT0 = 0x2a46 # macro +regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX = 1 # macro +regCP_GFX_RS64_PENDING_INTERRUPT1 = 0x2a47 # macro +regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE0_BASE0 = 0x2a49 # macro +regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE0_MASK0 = 0x2a4a # macro +regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE0_CNTL0 = 0x2a4b # macro +regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE1_BASE0 = 0x2a4c # macro +regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE1_MASK0 = 0x2a4d # macro +regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE1_CNTL0 = 0x2a4e # macro +regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE2_BASE0 = 0x2a4f # macro +regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE2_MASK0 = 0x2a50 # macro +regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE2_CNTL0 = 0x2a51 # macro +regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE3_BASE0 = 0x2a52 # macro +regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE3_MASK0 = 0x2a53 # macro +regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE3_CNTL0 = 0x2a54 # macro +regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE4_BASE0 = 0x2a55 # macro +regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE4_MASK0 = 0x2a56 # macro +regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE4_CNTL0 = 0x2a57 # macro +regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE5_BASE0 = 0x2a58 # macro +regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE5_MASK0 = 0x2a59 # macro +regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE5_CNTL0 = 0x2a5a # macro +regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE6_BASE0 = 0x2a5b # macro +regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE6_MASK0 = 0x2a5c # macro +regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE6_CNTL0 = 0x2a5d # macro +regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE7_BASE0 = 0x2a5e # macro +regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE7_MASK0 = 0x2a5f # macro +regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE7_CNTL0 = 0x2a60 # macro +regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE8_BASE0 = 0x2a61 # macro +regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE8_MASK0 = 0x2a62 # macro +regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE8_CNTL0 = 0x2a63 # macro +regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE9_BASE0 = 0x2a64 # macro +regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE9_MASK0 = 0x2a65 # macro +regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE9_CNTL0 = 0x2a66 # macro +regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE10_BASE0 = 0x2a67 # macro +regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE10_MASK0 = 0x2a68 # macro +regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE10_CNTL0 = 0x2a69 # macro +regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE11_BASE0 = 0x2a6a # macro +regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE11_MASK0 = 0x2a6b # macro +regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE11_CNTL0 = 0x2a6c # macro +regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE12_BASE0 = 0x2a6d # macro +regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE12_MASK0 = 0x2a6e # macro +regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE12_CNTL0 = 0x2a6f # macro +regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE13_BASE0 = 0x2a70 # macro +regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE13_MASK0 = 0x2a71 # macro +regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE13_CNTL0 = 0x2a72 # macro +regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE14_BASE0 = 0x2a73 # macro +regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE14_MASK0 = 0x2a74 # macro +regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE14_CNTL0 = 0x2a75 # macro +regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE15_BASE0 = 0x2a76 # macro +regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE15_MASK0 = 0x2a77 # macro +regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE15_CNTL0 = 0x2a78 # macro +regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE0_BASE1 = 0x2a79 # macro +regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE0_MASK1 = 0x2a7a # macro +regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE0_CNTL1 = 0x2a7b # macro +regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE1_BASE1 = 0x2a7c # macro +regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE1_MASK1 = 0x2a7d # macro +regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE1_CNTL1 = 0x2a7e # macro +regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE2_BASE1 = 0x2a7f # macro +regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE2_MASK1 = 0x2a80 # macro +regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE2_CNTL1 = 0x2a81 # macro +regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE3_BASE1 = 0x2a82 # macro +regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE3_MASK1 = 0x2a83 # macro +regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE3_CNTL1 = 0x2a84 # macro +regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE4_BASE1 = 0x2a85 # macro +regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE4_MASK1 = 0x2a86 # macro +regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE4_CNTL1 = 0x2a87 # macro +regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE5_BASE1 = 0x2a88 # macro +regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE5_MASK1 = 0x2a89 # macro +regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE5_CNTL1 = 0x2a8a # macro +regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE6_BASE1 = 0x2a8b # macro +regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE6_MASK1 = 0x2a8c # macro +regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE6_CNTL1 = 0x2a8d # macro +regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE7_BASE1 = 0x2a8e # macro +regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE7_MASK1 = 0x2a8f # macro +regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE7_CNTL1 = 0x2a90 # macro +regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE8_BASE1 = 0x2a91 # macro +regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE8_MASK1 = 0x2a92 # macro +regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE8_CNTL1 = 0x2a93 # macro +regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE9_BASE1 = 0x2a94 # macro +regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE9_MASK1 = 0x2a95 # macro +regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE9_CNTL1 = 0x2a96 # macro +regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE10_BASE1 = 0x2a97 # macro +regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE10_MASK1 = 0x2a98 # macro +regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE10_CNTL1 = 0x2a99 # macro +regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE11_BASE1 = 0x2a9a # macro +regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE11_MASK1 = 0x2a9b # macro +regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE11_CNTL1 = 0x2a9c # macro +regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE12_BASE1 = 0x2a9d # macro +regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE12_MASK1 = 0x2a9e # macro +regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE12_CNTL1 = 0x2a9f # macro +regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE13_BASE1 = 0x2aa0 # macro +regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE13_MASK1 = 0x2aa1 # macro +regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE13_CNTL1 = 0x2aa2 # macro +regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE14_BASE1 = 0x2aa3 # macro +regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE14_MASK1 = 0x2aa4 # macro +regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE14_CNTL1 = 0x2aa5 # macro +regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE15_BASE1 = 0x2aa6 # macro +regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE15_MASK1 = 0x2aa7 # macro +regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_APERTURE15_CNTL1 = 0x2aa8 # macro +regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX = 1 # macro +regCP_GFX_RS64_INTERRUPT1 = 0x2aac # macro +regCP_GFX_RS64_INTERRUPT1_BASE_IDX = 1 # macro +regGL1_DRAM_BURST_MASK = 0x2d02 # macro +regGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro +regGL1_ARB_STATUS = 0x2d03 # macro +regGL1_ARB_STATUS_BASE_IDX = 1 # macro +regGL1I_GL1R_REP_FGCG_OVERRIDE = 0x2d05 # macro +regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro +regGL1C_STATUS = 0x2d41 # macro +regGL1C_STATUS_BASE_IDX = 1 # macro +regGL1C_UTCL0_CNTL1 = 0x2d42 # macro +regGL1C_UTCL0_CNTL1_BASE_IDX = 1 # macro +regGL1C_UTCL0_CNTL2 = 0x2d43 # macro +regGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro +regGL1C_UTCL0_STATUS = 0x2d44 # macro +regGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro +regGL1C_UTCL0_RETRY = 0x2d45 # macro +regGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro +regCH_ARB_CTRL = 0x2d80 # macro +regCH_ARB_CTRL_BASE_IDX = 1 # macro +regCH_DRAM_BURST_MASK = 0x2d82 # macro +regCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro +regCH_ARB_STATUS = 0x2d83 # macro +regCH_ARB_STATUS_BASE_IDX = 1 # macro +regCH_DRAM_BURST_CTRL = 0x2d84 # macro +regCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro +regCHA_CHC_CREDITS = 0x2d88 # macro +regCHA_CHC_CREDITS_BASE_IDX = 1 # macro +regCHA_CLIENT_FREE_DELAY = 0x2d89 # macro +regCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro +regCHI_CHR_REP_FGCG_OVERRIDE = 0x2d8c # macro +regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro +regCH_VC5_ENABLE = 0x2d94 # macro +regCH_VC5_ENABLE_BASE_IDX = 1 # macro +regCHC_CTRL = 0x2dc0 # macro +regCHC_CTRL_BASE_IDX = 1 # macro +regCHC_STATUS = 0x2dc1 # macro +regCHC_STATUS_BASE_IDX = 1 # macro +regCHCG_CTRL = 0x2dc2 # macro +regCHCG_CTRL_BASE_IDX = 1 # macro +regCHCG_STATUS = 0x2dc3 # macro +regCHCG_STATUS_BASE_IDX = 1 # macro +regGL2C_CTRL = 0x2e00 # macro +regGL2C_CTRL_BASE_IDX = 1 # macro +regGL2C_CTRL2 = 0x2e01 # macro +regGL2C_CTRL2_BASE_IDX = 1 # macro +regGL2C_ADDR_MATCH_MASK = 0x2e03 # macro +regGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro +regGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro +regGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro +regGL2C_WBINVL2 = 0x2e05 # macro +regGL2C_WBINVL2_BASE_IDX = 1 # macro +regGL2C_SOFT_RESET = 0x2e06 # macro +regGL2C_SOFT_RESET_BASE_IDX = 1 # macro +regGL2C_CM_CTRL0 = 0x2e07 # macro +regGL2C_CM_CTRL0_BASE_IDX = 1 # macro +regGL2C_CM_CTRL1 = 0x2e08 # macro +regGL2C_CM_CTRL1_BASE_IDX = 1 # macro +regGL2C_CM_STALL = 0x2e09 # macro +regGL2C_CM_STALL_BASE_IDX = 1 # macro +regGL2C_CTRL3 = 0x2e0c # macro +regGL2C_CTRL3_BASE_IDX = 1 # macro +regGL2C_LB_CTR_CTRL = 0x2e0d # macro +regGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro +regGL2C_LB_DATA0 = 0x2e0e # macro +regGL2C_LB_DATA0_BASE_IDX = 1 # macro +regGL2C_LB_DATA1 = 0x2e0f # macro +regGL2C_LB_DATA1_BASE_IDX = 1 # macro +regGL2C_LB_DATA2 = 0x2e10 # macro +regGL2C_LB_DATA2_BASE_IDX = 1 # macro +regGL2C_LB_DATA3 = 0x2e11 # macro +regGL2C_LB_DATA3_BASE_IDX = 1 # macro +regGL2C_LB_CTR_SEL0 = 0x2e12 # macro +regGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro +regGL2C_LB_CTR_SEL1 = 0x2e13 # macro +regGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro +regGL2C_CTRL4 = 0x2e17 # macro +regGL2C_CTRL4_BASE_IDX = 1 # macro +regGL2C_DISCARD_STALL_CTRL = 0x2e18 # macro +regGL2C_DISCARD_STALL_CTRL_BASE_IDX = 1 # macro +regGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro +regGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro +regGL2A_ADDR_MATCH_MASK = 0x2e21 # macro +regGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro +regGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro +regGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro +regGL2A_PRIORITY_CTRL = 0x2e23 # macro +regGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro +regGL2A_RESP_THROTTLE_CTRL = 0x2e2a # macro +regGL2A_RESP_THROTTLE_CTRL_BASE_IDX = 1 # macro +regGL1H_ARB_CTRL = 0x2e40 # macro +regGL1H_ARB_CTRL_BASE_IDX = 1 # macro +regGL1H_GL1_CREDITS = 0x2e41 # macro +regGL1H_GL1_CREDITS_BASE_IDX = 1 # macro +regGL1H_BURST_MASK = 0x2e42 # macro +regGL1H_BURST_MASK_BASE_IDX = 1 # macro +regGL1H_BURST_CTRL = 0x2e43 # macro +regGL1H_BURST_CTRL_BASE_IDX = 1 # macro +regGL1H_ARB_STATUS = 0x2e44 # macro +regGL1H_ARB_STATUS_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER1_LO = 0x3000 # macro +regCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER1_HI = 0x3001 # macro +regCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_LO = 0x3002 # macro +regCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_HI = 0x3003 # macro +regCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER1_LO = 0x3004 # macro +regCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER1_HI = 0x3005 # macro +regCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_LO = 0x3006 # macro +regCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_HI = 0x3007 # macro +regCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER1_LO = 0x3008 # macro +regCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER1_HI = 0x3009 # macro +regCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_LO = 0x300a # macro +regCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_HI = 0x300b # macro +regCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCPF_LATENCY_STATS_DATA = 0x300c # macro +regCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +regCPG_LATENCY_STATS_DATA = 0x300d # macro +regCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +regCPC_LATENCY_STATS_DATA = 0x300e # macro +regCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER0_LO = 0x3040 # macro +regGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER0_HI = 0x3041 # macro +regGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER1_LO = 0x3043 # macro +regGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER1_HI = 0x3044 # macro +regGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro +regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro +regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro +regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro +regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro +regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro +regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro +regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro +regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE4_PERFCOUNTER_LO = 0x304d # macro +regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE4_PERFCOUNTER_HI = 0x304e # macro +regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE5_PERFCOUNTER_LO = 0x304f # macro +regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE5_PERFCOUNTER_HI = 0x3050 # macro +regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE6_PERFCOUNTER_LO = 0x3051 # macro +regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE6_PERFCOUNTER_HI = 0x3052 # macro +regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER0_LO = 0x30a4 # macro +regGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER0_HI = 0x30a5 # macro +regGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER1_LO = 0x30a6 # macro +regGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER1_HI = 0x30a7 # macro +regGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER2_LO = 0x30a8 # macro +regGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER2_HI = 0x30a9 # macro +regGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER3_LO = 0x30aa # macro +regGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER3_HI = 0x30ab # macro +regGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro +regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro +regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro +regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro +regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro +regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro +regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro +regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro +regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro +regGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro +regGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro +regGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro +regGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro +regGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro +regGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro +regGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro +regGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_LO = 0x3100 # macro +regPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_HI = 0x3101 # macro +regPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_LO = 0x3102 # macro +regPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_HI = 0x3103 # macro +regPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER2_LO = 0x3104 # macro +regPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER2_HI = 0x3105 # macro +regPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER3_LO = 0x3106 # macro +regPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER3_HI = 0x3107 # macro +regPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_LO = 0x3140 # macro +regPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_HI = 0x3141 # macro +regPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER1_LO = 0x3142 # macro +regPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER1_HI = 0x3143 # macro +regPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER2_LO = 0x3144 # macro +regPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER2_HI = 0x3145 # macro +regPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER3_LO = 0x3146 # macro +regPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER3_HI = 0x3147 # macro +regPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER4_LO = 0x3148 # macro +regPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER4_HI = 0x3149 # macro +regPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER5_LO = 0x314a # macro +regPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER5_HI = 0x314b # macro +regPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER6_LO = 0x314c # macro +regPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER6_HI = 0x314d # macro +regPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER7_LO = 0x314e # macro +regPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER7_HI = 0x314f # macro +regPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_HI = 0x3180 # macro +regSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_LO = 0x3181 # macro +regSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_HI = 0x3182 # macro +regSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_LO = 0x3183 # macro +regSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_HI = 0x3184 # macro +regSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_LO = 0x3185 # macro +regSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_HI = 0x3186 # macro +regSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_LO = 0x3187 # macro +regSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER4_HI = 0x3188 # macro +regSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER4_LO = 0x3189 # macro +regSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER5_HI = 0x318a # macro +regSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER5_LO = 0x318b # macro +regSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regPC_PERFCOUNTER0_HI = 0x318c # macro +regPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regPC_PERFCOUNTER0_LO = 0x318d # macro +regPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regPC_PERFCOUNTER1_HI = 0x318e # macro +regPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regPC_PERFCOUNTER1_LO = 0x318f # macro +regPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regPC_PERFCOUNTER2_HI = 0x3190 # macro +regPC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regPC_PERFCOUNTER2_LO = 0x3191 # macro +regPC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regPC_PERFCOUNTER3_HI = 0x3192 # macro +regPC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPC_PERFCOUNTER3_LO = 0x3193 # macro +regPC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER0_LO = 0x31c0 # macro +regSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER1_LO = 0x31c2 # macro +regSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER2_LO = 0x31c4 # macro +regSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER3_LO = 0x31c6 # macro +regSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER4_LO = 0x31c8 # macro +regSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER5_LO = 0x31ca # macro +regSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER6_LO = 0x31cc # macro +regSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER7_LO = 0x31ce # macro +regSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER0_LO = 0x31e4 # macro +regSQG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER0_HI = 0x31e5 # macro +regSQG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER1_LO = 0x31e6 # macro +regSQG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER1_HI = 0x31e7 # macro +regSQG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER2_LO = 0x31e8 # macro +regSQG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER2_HI = 0x31e9 # macro +regSQG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER3_LO = 0x31ea # macro +regSQG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER3_HI = 0x31eb # macro +regSQG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER4_LO = 0x31ec # macro +regSQG_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER4_HI = 0x31ed # macro +regSQG_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER5_LO = 0x31ee # macro +regSQG_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER5_HI = 0x31ef # macro +regSQG_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER6_LO = 0x31f0 # macro +regSQG_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER6_HI = 0x31f1 # macro +regSQG_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER7_LO = 0x31f2 # macro +regSQG_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER7_HI = 0x31f3 # macro +regSQG_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_LO = 0x3240 # macro +regSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_HI = 0x3241 # macro +regSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_LO = 0x3242 # macro +regSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_HI = 0x3243 # macro +regSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER2_LO = 0x3244 # macro +regSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER2_HI = 0x3245 # macro +regSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER3_LO = 0x3246 # macro +regSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER3_HI = 0x3247 # macro +regSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER2_LO = 0x3260 # macro +regGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER2_HI = 0x3261 # macro +regGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER_LO = 0x3262 # macro +regGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER_HI = 0x3263 # macro +regGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_LO = 0x3280 # macro +regGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_HI = 0x3281 # macro +regGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER1_LO = 0x3282 # macro +regGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER1_HI = 0x3283 # macro +regGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER2_LO = 0x3284 # macro +regGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER2_HI = 0x3285 # macro +regGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER3_LO = 0x3286 # macro +regGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER3_HI = 0x3287 # macro +regGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_LO = 0x32c0 # macro +regTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_HI = 0x32c1 # macro +regTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTA_PERFCOUNTER1_LO = 0x32c2 # macro +regTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTA_PERFCOUNTER1_HI = 0x32c3 # macro +regTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_LO = 0x3300 # macro +regTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_HI = 0x3301 # macro +regTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTD_PERFCOUNTER1_LO = 0x3302 # macro +regTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTD_PERFCOUNTER1_HI = 0x3303 # macro +regTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_LO = 0x3340 # macro +regTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_HI = 0x3341 # macro +regTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_LO = 0x3342 # macro +regTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_HI = 0x3343 # macro +regTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER2_LO = 0x3344 # macro +regTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER2_HI = 0x3345 # macro +regTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER3_LO = 0x3346 # macro +regTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER3_HI = 0x3347 # macro +regTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER_FILTER = 0x3348 # macro +regTCP_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER_FILTER2 = 0x3349 # macro +regTCP_PERFCOUNTER_FILTER2_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER_FILTER_EN = 0x334a # macro +regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER0_LO = 0x3380 # macro +regGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER0_HI = 0x3381 # macro +regGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER1_LO = 0x3382 # macro +regGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER1_HI = 0x3383 # macro +regGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER2_LO = 0x3384 # macro +regGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER2_HI = 0x3385 # macro +regGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER3_LO = 0x3386 # macro +regGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER3_HI = 0x3387 # macro +regGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER0_LO = 0x3390 # macro +regGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER0_HI = 0x3391 # macro +regGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER1_LO = 0x3392 # macro +regGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER1_HI = 0x3393 # macro +regGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER2_LO = 0x3394 # macro +regGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER2_HI = 0x3395 # macro +regGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER3_LO = 0x3396 # macro +regGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER3_HI = 0x3397 # macro +regGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER0_LO = 0x33a0 # macro +regGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER0_HI = 0x33a1 # macro +regGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER1_LO = 0x33a2 # macro +regGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER1_HI = 0x33a3 # macro +regGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER2_LO = 0x33a4 # macro +regGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER2_HI = 0x33a5 # macro +regGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER3_LO = 0x33a6 # macro +regGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER3_HI = 0x33a7 # macro +regGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER0_LO = 0x33c0 # macro +regCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER0_HI = 0x33c1 # macro +regCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER1_LO = 0x33c2 # macro +regCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER1_HI = 0x33c3 # macro +regCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER2_LO = 0x33c4 # macro +regCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER2_HI = 0x33c5 # macro +regCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER3_LO = 0x33c6 # macro +regCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER3_HI = 0x33c7 # macro +regCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER0_LO = 0x33c8 # macro +regCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER0_HI = 0x33c9 # macro +regCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER1_LO = 0x33ca # macro +regCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER1_HI = 0x33cb # macro +regCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER2_LO = 0x33cc # macro +regCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER2_HI = 0x33cd # macro +regCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER3_LO = 0x33ce # macro +regCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER3_HI = 0x33cf # macro +regCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_LO = 0x3406 # macro +regCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_HI = 0x3407 # macro +regCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER1_LO = 0x3408 # macro +regCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER1_HI = 0x3409 # macro +regCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER2_LO = 0x340a # macro +regCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER2_HI = 0x340b # macro +regCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER3_LO = 0x340c # macro +regCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER3_HI = 0x340d # macro +regCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_LO = 0x3440 # macro +regDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_HI = 0x3441 # macro +regDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_LO = 0x3442 # macro +regDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_HI = 0x3443 # macro +regDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER2_LO = 0x3444 # macro +regDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER2_HI = 0x3445 # macro +regDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER3_LO = 0x3446 # macro +regDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER3_HI = 0x3447 # macro +regDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER0_LO = 0x3480 # macro +regRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER0_HI = 0x3481 # macro +regRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER1_LO = 0x3482 # macro +regRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER1_HI = 0x3483 # macro +regRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_LO = 0x34c0 # macro +regRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_HI = 0x34c1 # macro +regRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER1_LO = 0x34c2 # macro +regRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER1_HI = 0x34c3 # macro +regRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_LO = 0x34c4 # macro +regRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_HI = 0x34c5 # macro +regRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER3_LO = 0x34c6 # macro +regRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER3_HI = 0x34c7 # macro +regRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGCR_PERFCOUNTER0_LO = 0x3520 # macro +regGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGCR_PERFCOUNTER0_HI = 0x3521 # macro +regGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGCR_PERFCOUNTER1_LO = 0x3522 # macro +regGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGCR_PERFCOUNTER1_HI = 0x3523 # macro +regGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER0_LO = 0x3580 # macro +regPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER0_HI = 0x3581 # macro +regPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER1_LO = 0x3582 # macro +regPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER1_HI = 0x3583 # macro +regPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER2_LO = 0x3584 # macro +regPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER2_HI = 0x3585 # macro +regPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER3_LO = 0x3586 # macro +regPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER3_HI = 0x3587 # macro +regPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER4_LO = 0x3588 # macro +regPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER4_HI = 0x3589 # macro +regPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER5_LO = 0x358a # macro +regPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER5_HI = 0x358b # macro +regPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER6_LO = 0x358c # macro +regPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER6_HI = 0x358d # macro +regPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER7_LO = 0x358e # macro +regPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER7_HI = 0x358f # macro +regPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER0_LO = 0x35a0 # macro +regUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER0_HI = 0x35a1 # macro +regUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER1_LO = 0x35a2 # macro +regUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER1_HI = 0x35a3 # macro +regUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER2_LO = 0x35a4 # macro +regUTCL1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER2_HI = 0x35a5 # macro +regUTCL1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER3_LO = 0x35a6 # macro +regUTCL1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER3_HI = 0x35a7 # macro +regUTCL1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER0_LO = 0x35c0 # macro +regGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER0_HI = 0x35c1 # macro +regGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER1_LO = 0x35c2 # macro +regGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER1_HI = 0x35c3 # macro +regGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER2_LO = 0x35c4 # macro +regGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER2_HI = 0x35c5 # macro +regGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER3_LO = 0x35c6 # macro +regGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER3_HI = 0x35c7 # macro +regGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER0_LO = 0x35d0 # macro +regGL1H_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER0_HI = 0x35d1 # macro +regGL1H_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER1_LO = 0x35d2 # macro +regGL1H_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER1_HI = 0x35d3 # macro +regGL1H_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER2_LO = 0x35d4 # macro +regGL1H_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER2_HI = 0x35d5 # macro +regGL1H_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER3_LO = 0x35d6 # macro +regGL1H_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER3_HI = 0x35d7 # macro +regGL1H_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER0_LO = 0x3600 # macro +regCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER0_HI = 0x3601 # macro +regCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER1_LO = 0x3602 # macro +regCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER1_HI = 0x3603 # macro +regCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER2_LO = 0x3604 # macro +regCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER2_HI = 0x3605 # macro +regCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER3_LO = 0x3606 # macro +regCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER3_HI = 0x3607 # macro +regCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER2_LO = 0x3640 # macro +regGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER2_HI = 0x3641 # macro +regGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER_LO = 0x3642 # macro +regGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER_HI = 0x3643 # macro +regGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER1_SELECT = 0x3800 # macro +regCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro +regCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_SELECT = 0x3802 # macro +regCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER1_SELECT = 0x3803 # macro +regCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro +regCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER1_SELECT = 0x3805 # macro +regCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro +regCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_SELECT = 0x3807 # macro +regCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCP_PERFMON_CNTL = 0x3808 # macro +regCP_PERFMON_CNTL_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_SELECT = 0x3809 # macro +regCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro +regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro +regCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro +regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro +regCPF_LATENCY_STATS_SELECT = 0x380c # macro +regCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +regCPG_LATENCY_STATS_SELECT = 0x380d # macro +regCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +regCPC_LATENCY_STATS_SELECT = 0x380e # macro +regCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +regCPC_TC_PERF_COUNTER_WINDOW_SELECT = 0x380f # macro +regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro +regCP_DRAW_OBJECT = 0x3810 # macro +regCP_DRAW_OBJECT_BASE_IDX = 1 # macro +regCP_DRAW_OBJECT_COUNTER = 0x3811 # macro +regCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro +regCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_HI = 0x3813 # macro +regCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_LO = 0x3814 # macro +regCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_CNTL = 0x3815 # macro +regCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro +regGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro +regGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro +regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro +regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro +regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro +regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE4_PERFCOUNTER_SELECT = 0x3846 # macro +regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE5_PERFCOUNTER_SELECT = 0x3847 # macro +regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE6_PERFCOUNTER_SELECT = 0x3848 # macro +regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro +regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro +regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro +regGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro +regGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro +regGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro +regGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro +regGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro +regGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER3_SELECT = 0x38aa # macro +regGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro +regGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro +regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro +regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro +regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro +regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro +regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro +regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro +regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro +regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro +regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro +regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro +regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro +regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro +regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro +regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro +regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro +regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro +regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro +regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro +regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro +regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro +regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro +regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro +regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro +regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro +regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro +regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro +regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro +regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro +regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro +regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro +regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro +regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro +regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_SELECT = 0x3980 # macro +regSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_SELECT = 0x3981 # macro +regSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_SELECT = 0x3982 # macro +regSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_SELECT = 0x3983 # macro +regSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro +regSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro +regSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro +regSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro +regSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER4_SELECT = 0x3988 # macro +regSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER5_SELECT = 0x3989 # macro +regSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER_BINS = 0x398a # macro +regSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro +regPC_PERFCOUNTER0_SELECT = 0x398c # macro +regPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regPC_PERFCOUNTER1_SELECT = 0x398d # macro +regPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regPC_PERFCOUNTER2_SELECT = 0x398e # macro +regPC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regPC_PERFCOUNTER3_SELECT = 0x398f # macro +regPC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regPC_PERFCOUNTER0_SELECT1 = 0x3990 # macro +regPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regPC_PERFCOUNTER1_SELECT1 = 0x3991 # macro +regPC_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regPC_PERFCOUNTER2_SELECT1 = 0x3992 # macro +regPC_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regPC_PERFCOUNTER3_SELECT1 = 0x3993 # macro +regPC_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro +regSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro +regSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro +regSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro +regSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro +regSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro +regSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro +regSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro +regSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro +regSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro +regSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER10_SELECT = 0x39ca # macro +regSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER11_SELECT = 0x39cb # macro +regSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER12_SELECT = 0x39cc # macro +regSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER13_SELECT = 0x39cd # macro +regSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER14_SELECT = 0x39ce # macro +regSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER15_SELECT = 0x39cf # macro +regSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER0_SELECT = 0x39d0 # macro +regSQG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER1_SELECT = 0x39d1 # macro +regSQG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER2_SELECT = 0x39d2 # macro +regSQG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER3_SELECT = 0x39d3 # macro +regSQG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER4_SELECT = 0x39d4 # macro +regSQG_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER5_SELECT = 0x39d5 # macro +regSQG_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER6_SELECT = 0x39d6 # macro +regSQG_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER7_SELECT = 0x39d7 # macro +regSQG_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER_CTRL = 0x39d8 # macro +regSQG_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro +regSQG_PERFCOUNTER_CTRL2 = 0x39da # macro +regSQG_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro +regSQG_PERF_SAMPLE_FINISH = 0x39db # macro +regSQG_PERF_SAMPLE_FINISH_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER_CTRL = 0x39e0 # macro +regSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro +regSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 # macro +regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 # macro +regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_BUF1_BASE = 0x39ea # macro +regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_BUF1_SIZE = 0x39eb # macro +regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_CTRL = 0x39ec # macro +regSQ_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_MASK = 0x39ed # macro +regSQ_THREAD_TRACE_MASK_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_TOKEN_MASK = 0x39ee # macro +regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_WPTR = 0x39ef # macro +regSQ_THREAD_TRACE_WPTR_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_STATUS = 0x39f4 # macro +regSQ_THREAD_TRACE_STATUS_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_STATUS2 = 0x39f5 # macro +regSQ_THREAD_TRACE_STATUS2_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x39f6 # macro +regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x39f7 # macro +regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x39f8 # macro +regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x39f9 # macro +regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_DROPPED_CNTR = 0x39fa # macro +regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro +regGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro +regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro +regGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro +regGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro +regGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro +regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_SELECT = 0x3a40 # macro +regSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_SELECT = 0x3a41 # macro +regSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER2_SELECT = 0x3a42 # macro +regSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER3_SELECT = 0x3a43 # macro +regSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro +regSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro +regSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro +regGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro +regGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro +regGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro +regGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro +regGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro +regGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro +regGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro +regGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro +regTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro +regTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro +regTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_SELECT = 0x3b00 # macro +regTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro +regTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTD_PERFCOUNTER1_SELECT = 0x3b02 # macro +regTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro +regTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro +regTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro +regTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro +regTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro +regTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro +regTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro +regGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro +regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro +regGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro +regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro +regGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro +regGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro +regGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro +regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro +regGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro +regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro +regGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro +regGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro +regGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro +regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro +regGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro +regGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro +regGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro +regCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro +regCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro +regCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro +regCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro +regCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro +regCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro +regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro +regCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro +regCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro +regCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER_FILTER = 0x3c00 # macro +regCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_SELECT = 0x3c01 # macro +regCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro +regCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCB_PERFCOUNTER1_SELECT = 0x3c03 # macro +regCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER2_SELECT = 0x3c04 # macro +regCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER3_SELECT = 0x3c05 # macro +regCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_SELECT = 0x3c40 # macro +regDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro +regDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_SELECT = 0x3c42 # macro +regDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro +regDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regDB_PERFCOUNTER2_SELECT = 0x3c44 # macro +regDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER3_SELECT = 0x3c46 # macro +regDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_CNTL = 0x3c80 # macro +regRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro +regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro +regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro +regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro +regRLC_SPM_RING_WRPTR = 0x3c84 # macro +regRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro +regRLC_SPM_RING_RDPTR = 0x3c85 # macro +regRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro +regRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro +regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c87 # macro +regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro +regRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c88 # macro +regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c89 # macro +regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro +regRLC_SPM_SE_MUXSEL_ADDR = 0x3c8a # macro +regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_SE_MUXSEL_DATA = 0x3c8b # macro +regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c92 # macro +regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_DATARAM_DATA = 0x3c93 # macro +regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3c94 # macro +regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3c95 # macro +regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c96 # macro +regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c97 # macro +regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3c98 # macro +regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_STATUS = 0x3c99 # macro +regRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_CTRL = 0x3c9a # macro +regRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_MODE = 0x3c9b # macro +regRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro +regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro +regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro +regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro +regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3c9f # macro +regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro +regRLC_SPM_PAUSE = 0x3ca2 # macro +regRLC_SPM_PAUSE_BASE_IDX = 1 # macro +regRLC_SPM_STATUS = 0x3ca3 # macro +regRLC_SPM_STATUS_BASE_IDX = 1 # macro +regRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca4 # macro +regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro +regRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca5 # macro +regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro +regRLC_SPM_MODE = 0x3cad # macro +regRLC_SPM_MODE_BASE_IDX = 1 # macro +regRLC_SPM_RSPM_REQ_DATA_LO = 0x3cae # macro +regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro +regRLC_SPM_RSPM_REQ_DATA_HI = 0x3caf # macro +regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro +regRLC_SPM_RSPM_REQ_OP = 0x3cb0 # macro +regRLC_SPM_RSPM_REQ_OP_BASE_IDX = 1 # macro +regRLC_SPM_RSPM_RET_DATA = 0x3cb1 # macro +regRLC_SPM_RSPM_RET_DATA_BASE_IDX = 1 # macro +regRLC_SPM_RSPM_RET_OP = 0x3cb2 # macro +regRLC_SPM_RSPM_RET_OP_BASE_IDX = 1 # macro +regRLC_SPM_SE_RSPM_REQ_DATA_LO = 0x3cb3 # macro +regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro +regRLC_SPM_SE_RSPM_REQ_DATA_HI = 0x3cb4 # macro +regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro +regRLC_SPM_SE_RSPM_REQ_OP = 0x3cb5 # macro +regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX = 1 # macro +regRLC_SPM_SE_RSPM_RET_DATA = 0x3cb6 # macro +regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX = 1 # macro +regRLC_SPM_SE_RSPM_RET_OP = 0x3cb7 # macro +regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX = 1 # macro +regRLC_SPM_RSPM_CMD = 0x3cb8 # macro +regRLC_SPM_RSPM_CMD_BASE_IDX = 1 # macro +regRLC_SPM_RSPM_CMD_ACK = 0x3cb9 # macro +regRLC_SPM_RSPM_CMD_ACK_BASE_IDX = 1 # macro +regRLC_SPM_SPARE = 0x3cbf # macro +regRLC_SPM_SPARE_BASE_IDX = 1 # macro +regRLC_PERFMON_CNTL = 0x3cc0 # macro +regRLC_PERFMON_CNTL_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro +regRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro +regRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro +regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro +regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro +regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro +regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro +regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro +regRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro +regRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro +regRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro +regRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro +regRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro +regRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regRMI_PERF_COUNTER_CNTL = 0x3d06 # macro +regRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro +regGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro +regGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro +regGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro +regGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro +regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro +regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro +regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro +regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro +regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro +regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro +regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro +regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro +regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro +regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro +regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro +regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER0_SELECT = 0x3da0 # macro +regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER1_SELECT = 0x3da1 # macro +regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER2_SELECT = 0x3da2 # macro +regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regUTCL1_PERFCOUNTER3_SELECT = 0x3da3 # macro +regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro +regGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro +regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro +regGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro +regGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro +regGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER0_SELECT = 0x3dd0 # macro +regGL1H_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER0_SELECT1 = 0x3dd1 # macro +regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER1_SELECT = 0x3dd2 # macro +regGL1H_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER2_SELECT = 0x3dd3 # macro +regGL1H_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGL1H_PERFCOUNTER3_SELECT = 0x3dd4 # macro +regGL1H_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro +regCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro +regCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro +regCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro +regCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro +regCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro +regGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro +regGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER2_MODE = 0x3e02 # macro +regGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER0_CFG = 0x3e03 # macro +regGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER1_CFG = 0x3e04 # macro +regGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro +regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro +regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro +regGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro +regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro +regGRTAVFS_GENERAL_0 = 0x4b02 # macro +regGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro +regGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro +regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro +regGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro +regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro +regGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro +regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro +regGRTAVFS_TARG_FREQ = 0x4b06 # macro +regGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro +regGRTAVFS_TARG_VOLT = 0x4b07 # macro +regGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro +regGRTAVFS_SOFT_RESET = 0x4b0c # macro +regGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro +regGRTAVFS_PSM_CNTL = 0x4b0d # macro +regGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro +regGRTAVFS_CLK_CNTL = 0x4b0e # macro +regGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro +regGRTAVFS_SE_RTAVFS_REG_ADDR = 0x4b40 # macro +regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro +regGRTAVFS_SE_RTAVFS_WR_DATA = 0x4b41 # macro +regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX = 1 # macro +regGRTAVFS_SE_GENERAL_0 = 0x4b42 # macro +regGRTAVFS_SE_GENERAL_0_BASE_IDX = 1 # macro +regGRTAVFS_SE_RTAVFS_RD_DATA = 0x4b43 # macro +regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX = 1 # macro +regGRTAVFS_SE_RTAVFS_REG_CTRL = 0x4b44 # macro +regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro +regGRTAVFS_SE_RTAVFS_REG_STATUS = 0x4b45 # macro +regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro +regGRTAVFS_SE_TARG_FREQ = 0x4b46 # macro +regGRTAVFS_SE_TARG_FREQ_BASE_IDX = 1 # macro +regGRTAVFS_SE_TARG_VOLT = 0x4b47 # macro +regGRTAVFS_SE_TARG_VOLT_BASE_IDX = 1 # macro +regGRTAVFS_SE_SOFT_RESET = 0x4b4c # macro +regGRTAVFS_SE_SOFT_RESET_BASE_IDX = 1 # macro +regGRTAVFS_SE_PSM_CNTL = 0x4b4d # macro +regGRTAVFS_SE_PSM_CNTL_BASE_IDX = 1 # macro +regGRTAVFS_SE_CLK_CNTL = 0x4b4e # macro +regGRTAVFS_SE_CLK_CNTL_BASE_IDX = 1 # macro +regRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro +regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro +regRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro +regRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro +regCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro +regCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_PFP_UCODE_ADDR = 0x5814 # macro +regCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_HYP_PFP_UCODE_DATA = 0x5815 # macro +regCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro +regCP_PFP_UCODE_DATA = 0x5815 # macro +regCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro +regCP_HYP_ME_UCODE_ADDR = 0x5816 # macro +regCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_ME_RAM_RADDR = 0x5816 # macro +regCP_ME_RAM_RADDR_BASE_IDX = 1 # macro +regCP_ME_RAM_WADDR = 0x5816 # macro +regCP_ME_RAM_WADDR_BASE_IDX = 1 # macro +regCP_HYP_ME_UCODE_DATA = 0x5817 # macro +regCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro +regCP_ME_RAM_DATA = 0x5817 # macro +regCP_ME_RAM_DATA_BASE_IDX = 1 # macro +regCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro +regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_MEC_ME1_UCODE_ADDR = 0x581a # macro +regCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_HYP_MEC1_UCODE_DATA = 0x581b # macro +regCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro +regCP_MEC_ME1_UCODE_DATA = 0x581b # macro +regCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro +regCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro +regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_MEC_ME2_UCODE_ADDR = 0x581c # macro +regCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_HYP_MEC2_UCODE_DATA = 0x581d # macro +regCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro +regCP_MEC_ME2_UCODE_DATA = 0x581d # macro +regCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro +regCP_PFP_IC_BASE_LO = 0x5840 # macro +regCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro +regCP_PFP_IC_BASE_HI = 0x5841 # macro +regCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro +regCP_PFP_IC_BASE_CNTL = 0x5842 # macro +regCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro +regCP_PFP_IC_OP_CNTL = 0x5843 # macro +regCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro +regCP_ME_IC_BASE_LO = 0x5844 # macro +regCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro +regCP_ME_IC_BASE_HI = 0x5845 # macro +regCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro +regCP_ME_IC_BASE_CNTL = 0x5846 # macro +regCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro +regCP_ME_IC_OP_CNTL = 0x5847 # macro +regCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro +regCP_CPC_IC_BASE_LO = 0x584c # macro +regCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro +regCP_CPC_IC_BASE_HI = 0x584d # macro +regCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro +regCP_CPC_IC_BASE_CNTL = 0x584e # macro +regCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro +regCP_MES_IC_BASE_LO = 0x5850 # macro +regCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro +regCP_MES_MIBASE_LO = 0x5850 # macro +regCP_MES_MIBASE_LO_BASE_IDX = 1 # macro +regCP_MES_IC_BASE_HI = 0x5851 # macro +regCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro +regCP_MES_MIBASE_HI = 0x5851 # macro +regCP_MES_MIBASE_HI_BASE_IDX = 1 # macro +regCP_MES_IC_BASE_CNTL = 0x5852 # macro +regCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro +regCP_MES_DC_BASE_LO = 0x5854 # macro +regCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro +regCP_MES_MDBASE_LO = 0x5854 # macro +regCP_MES_MDBASE_LO_BASE_IDX = 1 # macro +regCP_MES_DC_BASE_HI = 0x5855 # macro +regCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro +regCP_MES_MDBASE_HI = 0x5855 # macro +regCP_MES_MDBASE_HI_BASE_IDX = 1 # macro +regCP_MES_MIBOUND_LO = 0x585b # macro +regCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro +regCP_MES_MIBOUND_HI = 0x585c # macro +regCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro +regCP_MES_MDBOUND_LO = 0x585d # macro +regCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro +regCP_MES_MDBOUND_HI = 0x585e # macro +regCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_BASE0_LO = 0x5863 # macro +regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_BASE1_LO = 0x5864 # macro +regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_BASE0_HI = 0x5865 # macro +regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_DC_BASE1_HI = 0x5866 # macro +regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX = 1 # macro +regCP_GFX_RS64_MIBOUND_LO = 0x586c # macro +regCP_GFX_RS64_MIBOUND_LO_BASE_IDX = 1 # macro +regCP_GFX_RS64_MIBOUND_HI = 0x586d # macro +regCP_GFX_RS64_MIBOUND_HI_BASE_IDX = 1 # macro +regCP_MEC_DC_BASE_LO = 0x5870 # macro +regCP_MEC_DC_BASE_LO_BASE_IDX = 1 # macro +regCP_MEC_MDBASE_LO = 0x5870 # macro +regCP_MEC_MDBASE_LO_BASE_IDX = 1 # macro +regCP_MEC_DC_BASE_HI = 0x5871 # macro +regCP_MEC_DC_BASE_HI_BASE_IDX = 1 # macro +regCP_MEC_MDBASE_HI = 0x5871 # macro +regCP_MEC_MDBASE_HI_BASE_IDX = 1 # macro +regCP_MEC_MIBOUND_LO = 0x5872 # macro +regCP_MEC_MIBOUND_LO_BASE_IDX = 1 # macro +regCP_MEC_MIBOUND_HI = 0x5873 # macro +regCP_MEC_MIBOUND_HI_BASE_IDX = 1 # macro +regCP_MEC_MDBOUND_LO = 0x5874 # macro +regCP_MEC_MDBOUND_LO_BASE_IDX = 1 # macro +regCP_MEC_MDBOUND_HI = 0x5875 # macro +regCP_MEC_MDBOUND_HI_BASE_IDX = 1 # macro +regRLC_CNTL = 0x4c00 # macro +regRLC_CNTL_BASE_IDX = 1 # macro +regRLC_F32_UCODE_VERSION = 0x4c03 # macro +regRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro +regRLC_STAT = 0x4c04 # macro +regRLC_STAT_BASE_IDX = 1 # macro +regRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro +regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro +regRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro +regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_0 = 0x4c0e # macro +regRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_1 = 0x4c0f # macro +regRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_2 = 0x4c10 # macro +regRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_3 = 0x4c11 # macro +regRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_4 = 0x4c12 # macro +regRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_CTRL = 0x4c13 # macro +regRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_STAT = 0x4c14 # macro +regRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro +regRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro +regRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro +regRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro +regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro +regRLC_INT_STAT = 0x4c18 # macro +regRLC_INT_STAT_BASE_IDX = 1 # macro +regRLC_MGCG_CTRL = 0x4c1a # macro +regRLC_MGCG_CTRL_BASE_IDX = 1 # macro +regRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro +regRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro +regRLC_PG_DELAY_2 = 0x4c1f # macro +regRLC_PG_DELAY_2_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro +regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro +regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro +regRLC_UCODE_CNTL = 0x4c27 # macro +regRLC_UCODE_CNTL_BASE_IDX = 1 # macro +regRLC_GPM_THREAD_RESET = 0x4c28 # macro +regRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro +regRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro +regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro +regRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro +regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro +regRLC_GPM_THREAD_INVALIDATE_CACHE = 0x4c2b # macro +regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro +regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro +regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro +regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro +regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_CTRL = 0x4c34 # macro +regRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_STAT = 0x4c35 # macro +regRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro +regRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro +regRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro +regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro +regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro +regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro +regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro +regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro +regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro +regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro +regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro +regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_32 = 0x4c42 # macro +regRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro +regRLC_PG_CNTL = 0x4c43 # macro +regRLC_PG_CNTL_BASE_IDX = 1 # macro +regRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro +regRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro +regRLC_GPM_THREAD_ENABLE = 0x4c45 # macro +regRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro +regRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro +regRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro +regRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro +regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro +regRLC_CGCG_CGLS_CTRL = 0x4c49 # macro +regRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro +regRLC_CGCG_RAMP_CTRL = 0x4c4a # macro +regRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro +regRLC_DYN_PG_STATUS = 0x4c4b # macro +regRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro +regRLC_DYN_PG_REQUEST = 0x4c4c # macro +regRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro +regRLC_PG_DELAY = 0x4c4d # macro +regRLC_PG_DELAY_BASE_IDX = 1 # macro +regRLC_WGP_STATUS = 0x4c4e # macro +regRLC_WGP_STATUS_BASE_IDX = 1 # macro +regRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro +regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro +regRLC_MAX_PG_WGP = 0x4c54 # macro +regRLC_MAX_PG_WGP_BASE_IDX = 1 # macro +regRLC_AUTO_PG_CTRL = 0x4c55 # macro +regRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro +regRLC_SERDES_RD_INDEX = 0x4c59 # macro +regRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro +regRLC_SERDES_RD_DATA_0 = 0x4c5a # macro +regRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro +regRLC_SERDES_RD_DATA_1 = 0x4c5b # macro +regRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro +regRLC_SERDES_RD_DATA_2 = 0x4c5c # macro +regRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro +regRLC_SERDES_RD_DATA_3 = 0x4c5d # macro +regRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro +regRLC_SERDES_MASK = 0x4c5e # macro +regRLC_SERDES_MASK_BASE_IDX = 1 # macro +regRLC_SERDES_CTRL = 0x4c5f # macro +regRLC_SERDES_CTRL_BASE_IDX = 1 # macro +regRLC_SERDES_DATA = 0x4c60 # macro +regRLC_SERDES_DATA_BASE_IDX = 1 # macro +regRLC_SERDES_BUSY = 0x4c61 # macro +regRLC_SERDES_BUSY_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_0 = 0x4c63 # macro +regRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_1 = 0x4c64 # macro +regRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_2 = 0x4c65 # macro +regRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_3 = 0x4c66 # macro +regRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_4 = 0x4c67 # macro +regRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_5 = 0x4c68 # macro +regRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_6 = 0x4c69 # macro +regRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_7 = 0x4c6a # macro +regRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro +regRLC_STATIC_PG_STATUS = 0x4c6e # macro +regRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_16 = 0x4c76 # macro +regRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro +regRLC_PG_DELAY_3 = 0x4c78 # macro +regRLC_PG_DELAY_3_BASE_IDX = 1 # macro +regRLC_GPR_REG1 = 0x4c79 # macro +regRLC_GPR_REG1_BASE_IDX = 1 # macro +regRLC_GPR_REG2 = 0x4c7a # macro +regRLC_GPR_REG2_BASE_IDX = 1 # macro +regRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro +regRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro +regRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro +regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro +regRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro +regRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro +regRLC_SRM_CNTL = 0x4c80 # macro +regRLC_SRM_CNTL_BASE_IDX = 1 # macro +regRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro +regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro +regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro +regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro +regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro +regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro +regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro +regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro +regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro +regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro +regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro +regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro +regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro +regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro +regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro +regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro +regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro +regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro +regRLC_SRM_STAT = 0x4c9b # macro +regRLC_SRM_STAT_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_8 = 0x4cad # macro +regRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_9 = 0x4cae # macro +regRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_10 = 0x4caf # macro +regRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_11 = 0x4cb0 # macro +regRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_12 = 0x4cb1 # macro +regRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro +regRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro +regRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro +regRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro +regRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro +regRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro +regRLC_UTCL1_STATUS_2 = 0x4cb6 # macro +regRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro +regRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro +regRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro +regRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro +regRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro +regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro +regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro +regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro +regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro +regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro +regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro +regRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro +regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro +regRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro +regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_0 = 0x4cc7 # macro +regRLC_SEMAPHORE_0_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_1 = 0x4cc8 # macro +regRLC_SEMAPHORE_1_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_2 = 0x4cc9 # macro +regRLC_SEMAPHORE_2_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_3 = 0x4cca # macro +regRLC_SEMAPHORE_3_BASE_IDX = 1 # macro +regRLC_PACE_INT_STAT = 0x4ccc # macro +regRLC_PACE_INT_STAT_BASE_IDX = 1 # macro +regRLC_UTCL1_STATUS = 0x4cd4 # macro +regRLC_UTCL1_STATUS_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_0 = 0x4cd5 # macro +regRLC_R2I_CNTL_0_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_1 = 0x4cd6 # macro +regRLC_R2I_CNTL_1_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_2 = 0x4cd7 # macro +regRLC_R2I_CNTL_2_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_3 = 0x4cd8 # macro +regRLC_R2I_CNTL_3_BASE_IDX = 1 # macro +regRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro +regRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_13 = 0x4cdd # macro +regRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_14 = 0x4cde # macro +regRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_15 = 0x4cdf # macro +regRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro +regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro +regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro +regRLC_PACE_INT_DISABLE = 0x4ced # macro +regRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro +regRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro +regRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro +regRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro +regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro +regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro +regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro +regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro +regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro +regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro +regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro +regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4cfb # macro +regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4cfc # macro +regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro +regRLC_RLCV_SPARE_INT = 0x4d00 # macro +regRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro +regRLC_PACE_TIMER_INT_0 = 0x4d04 # macro +regRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro +regRLC_PACE_TIMER_INT_1 = 0x4d05 # macro +regRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro +regRLC_PACE_TIMER_CTRL = 0x4d06 # macro +regRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro +regRLC_SMU_CLK_REQ = 0x4d08 # macro +regRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro +regRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro +regRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro +regRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro +regRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro +regRLC_SPARE = 0x4d0b # macro +regRLC_SPARE_BASE_IDX = 1 # macro +regRLC_SPP_CTRL = 0x4d0c # macro +regRLC_SPP_CTRL_BASE_IDX = 1 # macro +regRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro +regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro +regRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro +regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro +regRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro +regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro +regRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro +regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro +regRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro +regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro +regRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro +regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro +regRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro +regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro +regRLC_SPP_PROF_INFO_1 = 0x4d18 # macro +regRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro +regRLC_SPP_PROF_INFO_2 = 0x4d19 # macro +regRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro +regRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro +regRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro +regRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro +regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro +regRLC_SPP_STATUS = 0x4d1c # macro +regRLC_SPP_STATUS_BASE_IDX = 1 # macro +regRLC_SPP_PVT_STAT_0 = 0x4d1d # macro +regRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro +regRLC_SPP_PVT_STAT_1 = 0x4d1e # macro +regRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro +regRLC_SPP_PVT_STAT_2 = 0x4d1f # macro +regRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro +regRLC_SPP_PVT_STAT_3 = 0x4d20 # macro +regRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro +regRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro +regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro +regRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro +regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro +regRLC_SPP_PBB_INFO = 0x4d23 # macro +regRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro +regRLC_SPP_RESET = 0x4d24 # macro +regRLC_SPP_RESET_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro +regRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro +regRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro +regRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro +regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro +regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro +regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro +regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro +regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro +regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro +regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +regRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro +regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +regRLC_CAC_MASK_CNTL = 0x4d45 # macro +regRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro +regRLC_POWER_RESIDENCY_CNTR_CTRL = 0x4d48 # macro +regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro +regRLC_CLK_RESIDENCY_CNTR_CTRL = 0x4d49 # macro +regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro +regRLC_DS_RESIDENCY_CNTR_CTRL = 0x4d4a # macro +regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro +regRLC_ULV_RESIDENCY_CNTR_CTRL = 0x4d4b # macro +regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro +regRLC_PCC_RESIDENCY_CNTR_CTRL = 0x4d4c # macro +regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro +regRLC_GENERAL_RESIDENCY_CNTR_CTRL = 0x4d4d # macro +regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro +regRLC_POWER_RESIDENCY_EVENT_CNTR = 0x4d50 # macro +regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro +regRLC_CLK_RESIDENCY_EVENT_CNTR = 0x4d51 # macro +regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro +regRLC_DS_RESIDENCY_EVENT_CNTR = 0x4d52 # macro +regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro +regRLC_ULV_RESIDENCY_EVENT_CNTR = 0x4d53 # macro +regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro +regRLC_PCC_RESIDENCY_EVENT_CNTR = 0x4d54 # macro +regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro +regRLC_GENERAL_RESIDENCY_EVENT_CNTR = 0x4d55 # macro +regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro +regRLC_POWER_RESIDENCY_REF_CNTR = 0x4d58 # macro +regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro +regRLC_CLK_RESIDENCY_REF_CNTR = 0x4d59 # macro +regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro +regRLC_DS_RESIDENCY_REF_CNTR = 0x4d5a # macro +regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro +regRLC_ULV_RESIDENCY_REF_CNTR = 0x4d5b # macro +regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro +regRLC_PCC_RESIDENCY_REF_CNTR = 0x4d5c # macro +regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro +regRLC_GENERAL_RESIDENCY_REF_CNTR = 0x4d5d # macro +regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro +regRLC_GFX_IH_CLIENT_CTRL = 0x4d5e # macro +regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX = 1 # macro +regRLC_GFX_IH_ARBITER_STAT = 0x4d5f # macro +regRLC_GFX_IH_ARBITER_STAT_BASE_IDX = 1 # macro +regRLC_GFX_IH_CLIENT_SE_STAT_L = 0x4d60 # macro +regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX = 1 # macro +regRLC_GFX_IH_CLIENT_SE_STAT_H = 0x4d61 # macro +regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX = 1 # macro +regRLC_GFX_IH_CLIENT_SDMA_STAT = 0x4d62 # macro +regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX = 1 # macro +regRLC_GFX_IH_CLIENT_OTHER_STAT = 0x4d63 # macro +regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX = 1 # macro +regRLC_SPM_GLOBAL_DELAY_IND_ADDR = 0x4d64 # macro +regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_GLOBAL_DELAY_IND_DATA = 0x4d65 # macro +regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX = 1 # macro +regRLC_SPM_SE_DELAY_IND_ADDR = 0x4d66 # macro +regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_SE_DELAY_IND_DATA = 0x4d67 # macro +regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX = 1 # macro +regRLC_LX6_CNTL = 0x4d80 # macro +regRLC_LX6_CNTL_BASE_IDX = 1 # macro +regRLC_XT_CORE_STATUS = 0x4dd4 # macro +regRLC_XT_CORE_STATUS_BASE_IDX = 1 # macro +regRLC_XT_CORE_INTERRUPT = 0x4dd5 # macro +regRLC_XT_CORE_INTERRUPT_BASE_IDX = 1 # macro +regRLC_XT_CORE_FAULT_INFO = 0x4dd6 # macro +regRLC_XT_CORE_FAULT_INFO_BASE_IDX = 1 # macro +regRLC_XT_CORE_ALT_RESET_VEC = 0x4dd7 # macro +regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX = 1 # macro +regRLC_XT_CORE_RESERVED = 0x4dd8 # macro +regRLC_XT_CORE_RESERVED_BASE_IDX = 1 # macro +regRLC_XT_INT_VEC_FORCE = 0x4dd9 # macro +regRLC_XT_INT_VEC_FORCE_BASE_IDX = 1 # macro +regRLC_XT_INT_VEC_CLEAR = 0x4dda # macro +regRLC_XT_INT_VEC_CLEAR_BASE_IDX = 1 # macro +regRLC_XT_INT_VEC_MUX_SEL = 0x4ddb # macro +regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX = 1 # macro +regRLC_XT_INT_VEC_MUX_INT_SEL = 0x4ddc # macro +regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro +regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro +regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro +regRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro +regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro +regRLC_SPP_CAM_ADDR = 0x4de8 # macro +regRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro +regRLC_SPP_CAM_DATA = 0x4de9 # macro +regRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro +regRLC_SPP_CAM_EXT_ADDR = 0x4dea # macro +regRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro +regRLC_SPP_CAM_EXT_DATA = 0x4deb # macro +regRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_RANGE = 0x4df5 # macro +regRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_CNTL = 0x4df6 # macro +regRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_STAT = 0x4df7 # macro +regRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro +regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro +regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro +regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro +regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro +regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro +regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro +regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +regRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro +regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +regRLC_MEM_SLP_CNTL = 0x4e00 # macro +regRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro +regSMU_RLC_RESPONSE = 0x4e01 # macro +regSMU_RLC_RESPONSE_BASE_IDX = 1 # macro +regRLC_RLCV_SAFE_MODE = 0x4e02 # macro +regRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro +regRLC_SMU_SAFE_MODE = 0x4e03 # macro +regRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro +regRLC_RLCV_COMMAND = 0x4e04 # macro +regRLC_RLCV_COMMAND_BASE_IDX = 1 # macro +regRLC_SMU_MESSAGE = 0x4e05 # macro +regRLC_SMU_MESSAGE_BASE_IDX = 1 # macro +regRLC_SMU_MESSAGE_1 = 0x4e06 # macro +regRLC_SMU_MESSAGE_1_BASE_IDX = 1 # macro +regRLC_SMU_MESSAGE_2 = 0x4e07 # macro +regRLC_SMU_MESSAGE_2_BASE_IDX = 1 # macro +regRLC_SRM_GPM_COMMAND = 0x4e08 # macro +regRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro +regRLC_SRM_GPM_ABORT = 0x4e09 # macro +regRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro +regRLC_SMU_COMMAND = 0x4e0a # macro +regRLC_SMU_COMMAND_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_1 = 0x4e0b # macro +regRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_2 = 0x4e0c # macro +regRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_3 = 0x4e0d # macro +regRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_4 = 0x4e0e # macro +regRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_5 = 0x4e0f # macro +regRLC_SMU_ARGUMENT_5_BASE_IDX = 1 # macro +regRLC_IMU_BOOTLOAD_ADDR_HI = 0x4e10 # macro +regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro +regRLC_IMU_BOOTLOAD_ADDR_LO = 0x4e11 # macro +regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro +regRLC_IMU_BOOTLOAD_SIZE = 0x4e12 # macro +regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX = 1 # macro +regRLC_IMU_MISC = 0x4e16 # macro +regRLC_IMU_MISC_BASE_IDX = 1 # macro +regRLC_IMU_RESET_VECTOR = 0x4e17 # macro +regRLC_IMU_RESET_VECTOR_BASE_IDX = 1 # macro +regRLC_RLCS_DEC_START = 0x4e60 # macro +regRLC_RLCS_DEC_START_BASE_IDX = 1 # macro +regRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro +regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro +regRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro +regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro +regRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro +regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro +regRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro +regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro +regRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro +regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro +regRLC_RLCS_CGCG_REQUEST = 0x4e66 # macro +regRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro +regRLC_RLCS_CGCG_STATUS = 0x4e67 # macro +regRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_SOC_DS_CNTL = 0x4e68 # macro +regRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_GFX_DS_CNTL = 0x4e69 # macro +regRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL = 0x4e6a # macro +regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX = 1 # macro +regRLC_GPM_STAT = 0x4e6b # macro +regRLC_GPM_STAT_BASE_IDX = 1 # macro +regRLC_RLCS_GPM_STAT = 0x4e6b # macro +regRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro +regRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6c # macro +regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro +regRLC_RLCS_DIDT_FORCE_STALL = 0x4e6d # macro +regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro +regRLC_RLCS_IOV_CMD_STATUS = 0x4e6e # macro +regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e6f # macro +regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro +regRLC_RLCS_IOV_SCH_BLOCK = 0x4e70 # macro +regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro +regRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e71 # macro +regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_GPM_STAT_2 = 0x4e72 # macro +regRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro +regRLC_RLCS_GRBM_SOFT_RESET = 0x4e73 # macro +regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro +regRLC_RLCS_PG_CHANGE_STATUS = 0x4e74 # macro +regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_PG_CHANGE_READ = 0x4e75 # macro +regRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro +regRLC_RLCS_IH_SEMAPHORE = 0x4e76 # macro +regRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro +regRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e77 # macro +regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro +regRLC_RLCS_WGP_STATUS = 0x4e78 # macro +regRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_WGP_READ = 0x4e79 # macro +regRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro +regRLC_RLCS_CP_INT_CTRL_1 = 0x4e7a # macro +regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro +regRLC_RLCS_CP_INT_CTRL_2 = 0x4e7b # macro +regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro +regRLC_RLCS_CP_INT_INFO_1 = 0x4e7c # macro +regRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro +regRLC_RLCS_CP_INT_INFO_2 = 0x4e7d # macro +regRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro +regRLC_RLCS_SPM_INT_CTRL = 0x4e7e # macro +regRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro +regRLC_RLCS_SPM_INT_INFO_1 = 0x4e7f # macro +regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro +regRLC_RLCS_SPM_INT_INFO_2 = 0x4e80 # macro +regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro +regRLC_RLCS_DSM_TRIG = 0x4e81 # macro +regRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro +regRLC_RLCS_BOOTLOAD_STATUS = 0x4e82 # macro +regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_POWER_BRAKE_CNTL = 0x4e83 # macro +regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4e84 # macro +regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro +regRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4e85 # macro +regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro +regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4e86 # macro +regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_CMP_IDLE_CNTL = 0x4e87 # macro +regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_0 = 0x4e88 # macro +regRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_1 = 0x4e89 # macro +regRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_2 = 0x4e8a # macro +regRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_3 = 0x4e8b # macro +regRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_4 = 0x4e8c # macro +regRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_5 = 0x4e8d # macro +regRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_6 = 0x4e8e # macro +regRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_7 = 0x4e8f # macro +regRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_8 = 0x4e90 # macro +regRLC_RLCS_GENERAL_8_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_9 = 0x4e91 # macro +regRLC_RLCS_GENERAL_9_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_10 = 0x4e92 # macro +regRLC_RLCS_GENERAL_10_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_11 = 0x4e93 # macro +regRLC_RLCS_GENERAL_11_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_12 = 0x4e94 # macro +regRLC_RLCS_GENERAL_12_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_13 = 0x4e95 # macro +regRLC_RLCS_GENERAL_13_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_14 = 0x4e96 # macro +regRLC_RLCS_GENERAL_14_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_15 = 0x4e97 # macro +regRLC_RLCS_GENERAL_15_BASE_IDX = 1 # macro +regRLC_RLCS_GENERAL_16 = 0x4e98 # macro +regRLC_RLCS_GENERAL_16_BASE_IDX = 1 # macro +regRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro +regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro +regRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro +regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro +regRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro +regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro +regRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro +regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro +regRLC_RLCS_SPM_SQTT_MODE = 0x4ec9 # macro +regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro +regRLC_RLCS_CP_DMA_SRCID_OVER = 0x4eca # macro +regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro +regRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4ecb # macro +regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro +regRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4ecc # macro +regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_VIDCHG_CNTL = 0x4ecd # macro +regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_EDC_INT_CNTL = 0x4ece # macro +regRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_KMD_LOG_CNTL1 = 0x4ecf # macro +regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro +regRLC_RLCS_KMD_LOG_CNTL2 = 0x4ed0 # macro +regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro +regRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ed1 # macro +regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro +regRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ed2 # macro +regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro +regRLC_RLCS_SRM_SRCID_CNTL = 0x4ed3 # macro +regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_GCR_DATA_0 = 0x4ed4 # macro +regRLC_RLCS_GCR_DATA_0_BASE_IDX = 1 # macro +regRLC_RLCS_GCR_DATA_1 = 0x4ed5 # macro +regRLC_RLCS_GCR_DATA_1_BASE_IDX = 1 # macro +regRLC_RLCS_GCR_DATA_2 = 0x4ed6 # macro +regRLC_RLCS_GCR_DATA_2_BASE_IDX = 1 # macro +regRLC_RLCS_GCR_DATA_3 = 0x4ed7 # macro +regRLC_RLCS_GCR_DATA_3_BASE_IDX = 1 # macro +regRLC_RLCS_GCR_STATUS = 0x4ed8 # macro +regRLC_RLCS_GCR_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4ed9 # macro +regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro +regRLC_RLCS_UTCL2_CNTL = 0x4eda # macro +regRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MSG_DATA0 = 0x4edb # macro +regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MSG_DATA1 = 0x4edc # macro +regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MSG_DATA2 = 0x4edd # macro +regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MSG_DATA3 = 0x4ede # macro +regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MSG_DATA4 = 0x4edf # macro +regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MSG_CONTROL = 0x4ee0 # macro +regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MSG_CNTL = 0x4ee1 # macro +regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_RLC_IMU_MSG_DATA0 = 0x4ee2 # macro +regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX = 1 # macro +regRLC_RLCS_RLC_IMU_MSG_CONTROL = 0x4ee3 # macro +regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX = 1 # macro +regRLC_RLCS_RLC_IMU_MSG_CNTL = 0x4ee4 # macro +regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 = 0x4ee5 # macro +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 = 0x4ee6 # macro +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_MUTEX_CNTL = 0x4ee7 # macro +regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RLC_STATUS = 0x4ee8 # macro +regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_RLC_IMU_STATUS = 0x4ee9 # macro +regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RAM_DATA_1 = 0x4eea # macro +regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RAM_ADDR_1_LSB = 0x4eeb # macro +regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RAM_ADDR_1_MSB = 0x4eec # macro +regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RAM_DATA_0 = 0x4eed # macro +regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RAM_ADDR_0_LSB = 0x4eee # macro +regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RAM_ADDR_0_MSB = 0x4eef # macro +regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_RAM_CNTL = 0x4ef0 # macro +regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_IMU_GFX_DOORBELL_FENCE = 0x4ef1 # macro +regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX = 1 # macro +regRLC_RLCS_SDMA_INT_CNTL_1 = 0x4ef3 # macro +regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX = 1 # macro +regRLC_RLCS_SDMA_INT_CNTL_2 = 0x4ef4 # macro +regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX = 1 # macro +regRLC_RLCS_SDMA_INT_STAT = 0x4ef5 # macro +regRLC_RLCS_SDMA_INT_STAT_BASE_IDX = 1 # macro +regRLC_RLCS_SDMA_INT_INFO = 0x4ef6 # macro +regRLC_RLCS_SDMA_INT_INFO_BASE_IDX = 1 # macro +regRLC_RLCS_PMM_CGCG_CNTL = 0x4ef7 # macro +regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_GFX_MEM_POWER_CTRL_LO = 0x4ef8 # macro +regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX = 1 # macro +regRLC_RLCS_GFX_RM_CNTL = 0x4efa # macro +regRLC_RLCS_GFX_RM_CNTL_BASE_IDX = 1 # macro +regRLC_RLCS_DEC_END = 0x4fff # macro +regRLC_RLCS_DEC_END_BASE_IDX = 1 # macro +regRLC_SAFE_MODE = 0x0980 # macro +regRLC_SAFE_MODE_BASE_IDX = 1 # macro +regRLC_SPM_SAMPLE_CNT = 0x0981 # macro +regRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro +regRLC_SPM_MC_CNTL = 0x0982 # macro +regRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro +regRLC_SPM_INT_CNTL = 0x0983 # macro +regRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro +regRLC_SPM_INT_STATUS = 0x0984 # macro +regRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro +regRLC_SPM_INT_INFO_1 = 0x0985 # macro +regRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro +regRLC_SPM_INT_INFO_2 = 0x0986 # macro +regRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro +regRLC_CSIB_ADDR_LO = 0x0987 # macro +regRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro +regRLC_CSIB_ADDR_HI = 0x0988 # macro +regRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro +regRLC_CSIB_LENGTH = 0x0989 # macro +regRLC_CSIB_LENGTH_BASE_IDX = 1 # macro +regRLC_CP_SCHEDULERS = 0x098a # macro +regRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro +regRLC_CP_EOF_INT = 0x098b # macro +regRLC_CP_EOF_INT_BASE_IDX = 1 # macro +regRLC_CP_EOF_INT_CNT = 0x098c # macro +regRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro +regRLC_SPARE_INT_0 = 0x098d # macro +regRLC_SPARE_INT_0_BASE_IDX = 1 # macro +regRLC_SPARE_INT_1 = 0x098e # macro +regRLC_SPARE_INT_1_BASE_IDX = 1 # macro +regRLC_SPARE_INT_2 = 0x098f # macro +regRLC_SPARE_INT_2_BASE_IDX = 1 # macro +regRLC_PACE_SPARE_INT = 0x0990 # macro +regRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro +regRLC_PACE_SPARE_INT_1 = 0x0991 # macro +regRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro +regRLC_RLCV_SPARE_INT_1 = 0x0992 # macro +regRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro +regCGTS_TCC_DISABLE = 0x5006 # macro +regCGTS_TCC_DISABLE_BASE_IDX = 1 # macro +regCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro +regCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_PA_CLK_CTRL = 0x5088 # macro +regCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL0 = 0x5089 # macro +regCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL1 = 0x508a # macro +regCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL2 = 0x508b # macro +regCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro +regCGTT_SQG_CLK_CTRL = 0x508d # macro +regCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro +regSQ_ALU_CLK_CTRL = 0x508e # macro +regSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro +regSQ_TEX_CLK_CTRL = 0x508f # macro +regSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro +regSQ_LDS_CLK_CTRL = 0x5090 # macro +regSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro +regICG_SP_CLK_CTRL = 0x5093 # macro +regICG_SP_CLK_CTRL_BASE_IDX = 1 # macro +regTA_CGTT_CTRL = 0x509d # macro +regTA_CGTT_CTRL_BASE_IDX = 1 # macro +regDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro +regDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro +regCB_CGTT_SCLK_CTRL = 0x50a8 # macro +regCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +regCGTT_CP_CLK_CTRL = 0x50b0 # macro +regCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_CPF_CLK_CTRL = 0x50b1 # macro +regCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_CPC_CLK_CTRL = 0x50b2 # macro +regCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_RLC_CLK_CTRL = 0x50b5 # macro +regCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL3 = 0x50bc # macro +regCGTT_SC_CLK_CTRL3_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL4 = 0x50bd # macro +regCGTT_SC_CLK_CTRL4_BASE_IDX = 1 # macro +regGCEA_ICG_CTRL = 0x50c4 # macro +regGCEA_ICG_CTRL_BASE_IDX = 1 # macro +regGL1I_GL1R_MGCG_OVERRIDE = 0x50e4 # macro +regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX = 1 # macro +regGL1H_ICG_CTRL = 0x50e8 # macro +regGL1H_ICG_CTRL_BASE_IDX = 1 # macro +regCHI_CHR_MGCG_OVERRIDE = 0x50e9 # macro +regCHI_CHR_MGCG_OVERRIDE_BASE_IDX = 1 # macro +regICG_GL1C_CLK_CTRL = 0x50ec # macro +regICG_GL1C_CLK_CTRL_BASE_IDX = 1 # macro +regICG_GL1A_CTRL = 0x50f0 # macro +regICG_GL1A_CTRL_BASE_IDX = 1 # macro +regICG_CHA_CTRL = 0x50f1 # macro +regICG_CHA_CTRL_BASE_IDX = 1 # macro +regGUS_ICG_CTRL = 0x50f4 # macro +regGUS_ICG_CTRL_BASE_IDX = 1 # macro +regCGTT_PH_CLK_CTRL0 = 0x50f8 # macro +regCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro +regCGTT_PH_CLK_CTRL1 = 0x50f9 # macro +regCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro +regCGTT_PH_CLK_CTRL2 = 0x50fa # macro +regCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro +regCGTT_PH_CLK_CTRL3 = 0x50fb # macro +regCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro +regGFX_ICG_GL2C_CTRL = 0x50fc # macro +regGFX_ICG_GL2C_CTRL_BASE_IDX = 1 # macro +regGFX_ICG_GL2C_CTRL1 = 0x50fd # macro +regGFX_ICG_GL2C_CTRL1_BASE_IDX = 1 # macro +regICG_LDS_CLK_CTRL = 0x5114 # macro +regICG_LDS_CLK_CTRL_BASE_IDX = 1 # macro +regICG_CHC_CLK_CTRL = 0x5140 # macro +regICG_CHC_CLK_CTRL_BASE_IDX = 1 # macro +regICG_CHCG_CLK_CTRL = 0x5144 # macro +regICG_CHCG_CLK_CTRL_BASE_IDX = 1 # macro +regGFX_PIPE_PRIORITY = 0x587f # macro +regGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro +regGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro +regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro +regGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro +regGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro +regGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro +regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro +regGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro +regGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro +regGC_IH_COOKIE_0_PTR = 0x5a07 # macro +regGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro +regGRBM_SE_REMAP_CNTL = 0x5a08 # macro +regGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro +regRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro +regRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro +regRLC_SDMA0_STATUS = 0x5b18 # macro +regRLC_SDMA0_STATUS_BASE_IDX = 1 # macro +regRLC_SDMA1_STATUS = 0x5b19 # macro +regRLC_SDMA1_STATUS_BASE_IDX = 1 # macro +regRLC_SDMA2_STATUS = 0x5b1a # macro +regRLC_SDMA2_STATUS_BASE_IDX = 1 # macro +regRLC_SDMA3_STATUS = 0x5b1b # macro +regRLC_SDMA3_STATUS_BASE_IDX = 1 # macro +regRLC_SDMA0_BUSY_STATUS = 0x5b1c # macro +regRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_SDMA1_BUSY_STATUS = 0x5b1d # macro +regRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_SDMA2_BUSY_STATUS = 0x5b1e # macro +regRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_SDMA3_BUSY_STATUS = 0x5b1f # macro +regRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro +regRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro +regRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_INT_1 = 0x5b26 # macro +regRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_CTRL = 0x5b27 # macro +regRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_STAT = 0x5b28 # macro +regRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_MASK = 0x5b2d # macro +regRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro +regRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro +regRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro +regRLC_BUSY_CLK_CNTL = 0x5b30 # macro +regRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro +regRLC_CLK_CNTL = 0x5b31 # macro +regRLC_CLK_CNTL_BASE_IDX = 1 # macro +regRLC_PACE_TIMER_STAT = 0x5b33 # macro +regRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro +regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro +regRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro +regRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro +regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_0 = 0x5b38 # macro +regRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_3 = 0x5b3a # macro +regRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_1 = 0x5b3b # macro +regRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_2 = 0x5b3c # macro +regRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro +regRLC_PACE_INT_FORCE = 0x5b3d # macro +regRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro +regRLC_PACE_INT_CLEAR = 0x5b3e # macro +regRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_INT_STAT = 0x5b3f # macro +regRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro +regRLC_IH_COOKIE = 0x5b41 # macro +regRLC_IH_COOKIE_BASE_IDX = 1 # macro +regRLC_IH_COOKIE_CNTL = 0x5b42 # macro +regRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro +regRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro +regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro +regRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro +regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro +regRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro +regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro +regRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro +regRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro +regRLC_GPU_IOV_F32_RESET = 0x5b47 # macro +regRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro +regRLC_GPU_IOV_UCODE_ADDR = 0x5b48 # macro +regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_UCODE_DATA = 0x5b49 # macro +regRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro +regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_F32_INVALIDATE_CACHE = 0x5b4b # macro +regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro +regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro +regRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro +regRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCRATCH_ADDR = 0x5b50 # macro +regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCRATCH_DATA = 0x5b51 # macro +regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro +regRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro +regRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro +regRLC_GPM_UCODE_ADDR = 0x5b60 # macro +regRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro +regRLC_GPM_UCODE_DATA = 0x5b61 # macro +regRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro +regRLC_GPM_IRAM_ADDR = 0x5b62 # macro +regRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro +regRLC_GPM_IRAM_DATA = 0x5b63 # macro +regRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro +regRLC_RLCP_IRAM_ADDR = 0x5b64 # macro +regRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro +regRLC_RLCP_IRAM_DATA = 0x5b65 # macro +regRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro +regRLC_RLCV_IRAM_ADDR = 0x5b66 # macro +regRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro +regRLC_RLCV_IRAM_DATA = 0x5b67 # macro +regRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro +regRLC_LX6_DRAM_ADDR = 0x5b68 # macro +regRLC_LX6_DRAM_ADDR_BASE_IDX = 1 # macro +regRLC_LX6_DRAM_DATA = 0x5b69 # macro +regRLC_LX6_DRAM_DATA_BASE_IDX = 1 # macro +regRLC_LX6_IRAM_ADDR = 0x5b6a # macro +regRLC_LX6_IRAM_ADDR_BASE_IDX = 1 # macro +regRLC_LX6_IRAM_DATA = 0x5b6b # macro +regRLC_LX6_IRAM_DATA_BASE_IDX = 1 # macro +regRLC_PACE_UCODE_ADDR = 0x5b6c # macro +regRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro +regRLC_PACE_UCODE_DATA = 0x5b6d # macro +regRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro +regRLC_GPM_SCRATCH_ADDR = 0x5b6e # macro +regRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro +regRLC_GPM_SCRATCH_DATA = 0x5b6f # macro +regRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro +regRLC_SRM_DRAM_ADDR = 0x5b71 # macro +regRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro +regRLC_SRM_DRAM_DATA = 0x5b72 # macro +regRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro +regRLC_SRM_ARAM_ADDR = 0x5b73 # macro +regRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro +regRLC_SRM_ARAM_DATA = 0x5b74 # macro +regRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro +regRLC_PACE_SCRATCH_ADDR = 0x5b77 # macro +regRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro +regRLC_PACE_SCRATCH_DATA = 0x5b78 # macro +regRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro +regRLC_GTS_OFFSET_LSB = 0x5b79 # macro +regRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro +regRLC_GTS_OFFSET_MSB = 0x5b7a # macro +regRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro +regGL2_PIPE_STEER_0 = 0x5b80 # macro +regGL2_PIPE_STEER_0_BASE_IDX = 1 # macro +regGL2_PIPE_STEER_1 = 0x5b81 # macro +regGL2_PIPE_STEER_1_BASE_IDX = 1 # macro +regGL2_PIPE_STEER_2 = 0x5b82 # macro +regGL2_PIPE_STEER_2_BASE_IDX = 1 # macro +regGL2_PIPE_STEER_3 = 0x5b83 # macro +regGL2_PIPE_STEER_3_BASE_IDX = 1 # macro +regGL1_PIPE_STEER = 0x5b84 # macro +regGL1_PIPE_STEER_BASE_IDX = 1 # macro +regCH_PIPE_STEER = 0x5b88 # macro +regCH_PIPE_STEER_BASE_IDX = 1 # macro +regGC_USER_SHADER_ARRAY_CONFIG = 0x5b90 # macro +regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 1 # macro +regGC_USER_PRIM_CONFIG = 0x5b91 # macro +regGC_USER_PRIM_CONFIG_BASE_IDX = 1 # macro +regGC_USER_SA_UNIT_DISABLE = 0x5b92 # macro +regGC_USER_SA_UNIT_DISABLE_BASE_IDX = 1 # macro +regGC_USER_RB_REDUNDANCY = 0x5b93 # macro +regGC_USER_RB_REDUNDANCY_BASE_IDX = 1 # macro +regGC_USER_RB_BACKEND_DISABLE = 0x5b94 # macro +regGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 1 # macro +regGC_USER_RMI_REDUNDANCY = 0x5b95 # macro +regGC_USER_RMI_REDUNDANCY_BASE_IDX = 1 # macro +regCGTS_USER_TCC_DISABLE = 0x5b96 # macro +regCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro +regGC_USER_SHADER_RATE_CONFIG = 0x5b97 # macro +regGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro +regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro +regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro +regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro +regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro +regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro +regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro +regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro +regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro +regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro +regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro +regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro +regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro +regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro +regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro +regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro +regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro +regCP_MES_DM_INDEX_ADDR = 0x5c00 # macro +regCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro +regCP_MES_DM_INDEX_DATA = 0x5c01 # macro +regCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro +regCP_MEC_DM_INDEX_ADDR = 0x5c02 # macro +regCP_MEC_DM_INDEX_ADDR_BASE_IDX = 1 # macro +regCP_MEC_DM_INDEX_DATA = 0x5c03 # macro +regCP_MEC_DM_INDEX_DATA_BASE_IDX = 1 # macro +regCP_GFX_RS64_DM_INDEX_ADDR = 0x5c04 # macro +regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX = 1 # macro +regCP_GFX_RS64_DM_INDEX_DATA = 0x5c05 # macro +regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX = 1 # macro +regCPG_PSP_DEBUG = 0x5c10 # macro +regCPG_PSP_DEBUG_BASE_IDX = 1 # macro +regCPC_PSP_DEBUG = 0x5c11 # macro +regCPC_PSP_DEBUG_BASE_IDX = 1 # macro +regGRBM_SEC_CNTL = 0x5e0d # macro +regGRBM_SEC_CNTL_BASE_IDX = 1 # macro +regGRBM_CAM_INDEX = 0x5e10 # macro +regGRBM_CAM_INDEX_BASE_IDX = 1 # macro +regGRBM_HYP_CAM_INDEX = 0x5e10 # macro +regGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro +regGRBM_CAM_DATA = 0x5e11 # macro +regGRBM_CAM_DATA_BASE_IDX = 1 # macro +regGRBM_HYP_CAM_DATA = 0x5e11 # macro +regGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro +regGRBM_CAM_DATA_UPPER = 0x5e12 # macro +regGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro +regGRBM_HYP_CAM_DATA_UPPER = 0x5e12 # macro +regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro +regRLC_FWL_FIRST_VIOL_ADDR = 0x5f26 # macro +regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_0 = 0x4000 # macro +regGFX_IMU_C2PMSG_0_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_1 = 0x4001 # macro +regGFX_IMU_C2PMSG_1_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_2 = 0x4002 # macro +regGFX_IMU_C2PMSG_2_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_3 = 0x4003 # macro +regGFX_IMU_C2PMSG_3_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_4 = 0x4004 # macro +regGFX_IMU_C2PMSG_4_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_5 = 0x4005 # macro +regGFX_IMU_C2PMSG_5_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_6 = 0x4006 # macro +regGFX_IMU_C2PMSG_6_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_7 = 0x4007 # macro +regGFX_IMU_C2PMSG_7_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_8 = 0x4008 # macro +regGFX_IMU_C2PMSG_8_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_9 = 0x4009 # macro +regGFX_IMU_C2PMSG_9_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_10 = 0x400a # macro +regGFX_IMU_C2PMSG_10_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_11 = 0x400b # macro +regGFX_IMU_C2PMSG_11_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_12 = 0x400c # macro +regGFX_IMU_C2PMSG_12_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_13 = 0x400d # macro +regGFX_IMU_C2PMSG_13_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_14 = 0x400e # macro +regGFX_IMU_C2PMSG_14_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_15 = 0x400f # macro +regGFX_IMU_C2PMSG_15_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_16 = 0x4010 # macro +regGFX_IMU_C2PMSG_16_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_17 = 0x4011 # macro +regGFX_IMU_C2PMSG_17_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_18 = 0x4012 # macro +regGFX_IMU_C2PMSG_18_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_19 = 0x4013 # macro +regGFX_IMU_C2PMSG_19_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_20 = 0x4014 # macro +regGFX_IMU_C2PMSG_20_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_21 = 0x4015 # macro +regGFX_IMU_C2PMSG_21_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_22 = 0x4016 # macro +regGFX_IMU_C2PMSG_22_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_23 = 0x4017 # macro +regGFX_IMU_C2PMSG_23_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_24 = 0x4018 # macro +regGFX_IMU_C2PMSG_24_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_25 = 0x4019 # macro +regGFX_IMU_C2PMSG_25_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_26 = 0x401a # macro +regGFX_IMU_C2PMSG_26_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_27 = 0x401b # macro +regGFX_IMU_C2PMSG_27_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_28 = 0x401c # macro +regGFX_IMU_C2PMSG_28_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_29 = 0x401d # macro +regGFX_IMU_C2PMSG_29_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_30 = 0x401e # macro +regGFX_IMU_C2PMSG_30_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_31 = 0x401f # macro +regGFX_IMU_C2PMSG_31_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_32 = 0x4020 # macro +regGFX_IMU_C2PMSG_32_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_33 = 0x4021 # macro +regGFX_IMU_C2PMSG_33_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_34 = 0x4022 # macro +regGFX_IMU_C2PMSG_34_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_35 = 0x4023 # macro +regGFX_IMU_C2PMSG_35_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_36 = 0x4024 # macro +regGFX_IMU_C2PMSG_36_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_37 = 0x4025 # macro +regGFX_IMU_C2PMSG_37_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_38 = 0x4026 # macro +regGFX_IMU_C2PMSG_38_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_39 = 0x4027 # macro +regGFX_IMU_C2PMSG_39_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_40 = 0x4028 # macro +regGFX_IMU_C2PMSG_40_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_41 = 0x4029 # macro +regGFX_IMU_C2PMSG_41_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_42 = 0x402a # macro +regGFX_IMU_C2PMSG_42_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_43 = 0x402b # macro +regGFX_IMU_C2PMSG_43_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_44 = 0x402c # macro +regGFX_IMU_C2PMSG_44_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_45 = 0x402d # macro +regGFX_IMU_C2PMSG_45_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_46 = 0x402e # macro +regGFX_IMU_C2PMSG_46_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_47 = 0x402f # macro +regGFX_IMU_C2PMSG_47_BASE_IDX = 1 # macro +regGFX_IMU_MSG_FLAGS = 0x403f # macro +regGFX_IMU_MSG_FLAGS_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_ACCESS_CTRL0 = 0x4040 # macro +regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX = 1 # macro +regGFX_IMU_C2PMSG_ACCESS_CTRL1 = 0x4041 # macro +regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX = 1 # macro +regGFX_IMU_PWRMGT_IRQ_CTRL = 0x4042 # macro +regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_MP1_MUTEX = 0x4043 # macro +regGFX_IMU_MP1_MUTEX_BASE_IDX = 1 # macro +regGFX_IMU_RLC_DATA_4 = 0x4046 # macro +regGFX_IMU_RLC_DATA_4_BASE_IDX = 1 # macro +regGFX_IMU_RLC_DATA_3 = 0x4047 # macro +regGFX_IMU_RLC_DATA_3_BASE_IDX = 1 # macro +regGFX_IMU_RLC_DATA_2 = 0x4048 # macro +regGFX_IMU_RLC_DATA_2_BASE_IDX = 1 # macro +regGFX_IMU_RLC_DATA_1 = 0x4049 # macro +regGFX_IMU_RLC_DATA_1_BASE_IDX = 1 # macro +regGFX_IMU_RLC_DATA_0 = 0x404a # macro +regGFX_IMU_RLC_DATA_0_BASE_IDX = 1 # macro +regGFX_IMU_RLC_CMD = 0x404b # macro +regGFX_IMU_RLC_CMD_BASE_IDX = 1 # macro +regGFX_IMU_RLC_MUTEX = 0x404c # macro +regGFX_IMU_RLC_MUTEX_BASE_IDX = 1 # macro +regGFX_IMU_RLC_MSG_STATUS = 0x404f # macro +regGFX_IMU_RLC_MSG_STATUS_BASE_IDX = 1 # macro +regRLC_GFX_IMU_DATA_0 = 0x4052 # macro +regRLC_GFX_IMU_DATA_0_BASE_IDX = 1 # macro +regRLC_GFX_IMU_CMD = 0x4053 # macro +regRLC_GFX_IMU_CMD_BASE_IDX = 1 # macro +regGFX_IMU_RLC_STATUS = 0x4054 # macro +regGFX_IMU_RLC_STATUS_BASE_IDX = 1 # macro +regGFX_IMU_STATUS = 0x4055 # macro +regGFX_IMU_STATUS_BASE_IDX = 1 # macro +regGFX_IMU_SOC_DATA = 0x4059 # macro +regGFX_IMU_SOC_DATA_BASE_IDX = 1 # macro +regGFX_IMU_SOC_ADDR = 0x405a # macro +regGFX_IMU_SOC_ADDR_BASE_IDX = 1 # macro +regGFX_IMU_SOC_REQ = 0x405b # macro +regGFX_IMU_SOC_REQ_BASE_IDX = 1 # macro +regGFX_IMU_VF_CTRL = 0x405c # macro +regGFX_IMU_VF_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_TELEMETRY = 0x4060 # macro +regGFX_IMU_TELEMETRY_BASE_IDX = 1 # macro +regGFX_IMU_TELEMETRY_DATA = 0x4061 # macro +regGFX_IMU_TELEMETRY_DATA_BASE_IDX = 1 # macro +regGFX_IMU_TELEMETRY_TEMPERATURE = 0x4062 # macro +regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_0 = 0x4068 # macro +regGFX_IMU_SCRATCH_0_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_1 = 0x4069 # macro +regGFX_IMU_SCRATCH_1_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_2 = 0x406a # macro +regGFX_IMU_SCRATCH_2_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_3 = 0x406b # macro +regGFX_IMU_SCRATCH_3_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_4 = 0x406c # macro +regGFX_IMU_SCRATCH_4_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_5 = 0x406d # macro +regGFX_IMU_SCRATCH_5_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_6 = 0x406e # macro +regGFX_IMU_SCRATCH_6_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_7 = 0x406f # macro +regGFX_IMU_SCRATCH_7_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_8 = 0x4070 # macro +regGFX_IMU_SCRATCH_8_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_9 = 0x4071 # macro +regGFX_IMU_SCRATCH_9_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_10 = 0x4072 # macro +regGFX_IMU_SCRATCH_10_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_11 = 0x4073 # macro +regGFX_IMU_SCRATCH_11_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_12 = 0x4074 # macro +regGFX_IMU_SCRATCH_12_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_13 = 0x4075 # macro +regGFX_IMU_SCRATCH_13_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_14 = 0x4076 # macro +regGFX_IMU_SCRATCH_14_BASE_IDX = 1 # macro +regGFX_IMU_SCRATCH_15 = 0x4077 # macro +regGFX_IMU_SCRATCH_15_BASE_IDX = 1 # macro +regGFX_IMU_FW_GTS_LO = 0x4078 # macro +regGFX_IMU_FW_GTS_LO_BASE_IDX = 1 # macro +regGFX_IMU_FW_GTS_HI = 0x4079 # macro +regGFX_IMU_FW_GTS_HI_BASE_IDX = 1 # macro +regGFX_IMU_GTS_OFFSET_LO = 0x407a # macro +regGFX_IMU_GTS_OFFSET_LO_BASE_IDX = 1 # macro +regGFX_IMU_GTS_OFFSET_HI = 0x407b # macro +regGFX_IMU_GTS_OFFSET_HI_BASE_IDX = 1 # macro +regGFX_IMU_RLC_GTS_OFFSET_LO = 0x407c # macro +regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX = 1 # macro +regGFX_IMU_RLC_GTS_OFFSET_HI = 0x407d # macro +regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX = 1 # macro +regGFX_IMU_CORE_INT_STATUS = 0x407f # macro +regGFX_IMU_CORE_INT_STATUS_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_MASK = 0x4080 # macro +regGFX_IMU_PIC_INT_MASK_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_LVL = 0x4081 # macro +regGFX_IMU_PIC_INT_LVL_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_EDGE = 0x4082 # macro +regGFX_IMU_PIC_INT_EDGE_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_0 = 0x4083 # macro +regGFX_IMU_PIC_INT_PRI_0_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_1 = 0x4084 # macro +regGFX_IMU_PIC_INT_PRI_1_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_2 = 0x4085 # macro +regGFX_IMU_PIC_INT_PRI_2_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_3 = 0x4086 # macro +regGFX_IMU_PIC_INT_PRI_3_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_4 = 0x4087 # macro +regGFX_IMU_PIC_INT_PRI_4_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_5 = 0x4088 # macro +regGFX_IMU_PIC_INT_PRI_5_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_6 = 0x4089 # macro +regGFX_IMU_PIC_INT_PRI_6_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_PRI_7 = 0x408a # macro +regGFX_IMU_PIC_INT_PRI_7_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INT_STATUS = 0x408b # macro +regGFX_IMU_PIC_INT_STATUS_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INTR = 0x408c # macro +regGFX_IMU_PIC_INTR_BASE_IDX = 1 # macro +regGFX_IMU_PIC_INTR_ID = 0x408d # macro +regGFX_IMU_PIC_INTR_ID_BASE_IDX = 1 # macro +regGFX_IMU_IH_CTRL_1 = 0x4090 # macro +regGFX_IMU_IH_CTRL_1_BASE_IDX = 1 # macro +regGFX_IMU_IH_CTRL_2 = 0x4091 # macro +regGFX_IMU_IH_CTRL_2_BASE_IDX = 1 # macro +regGFX_IMU_IH_CTRL_3 = 0x4092 # macro +regGFX_IMU_IH_CTRL_3_BASE_IDX = 1 # macro +regGFX_IMU_IH_STATUS = 0x4093 # macro +regGFX_IMU_IH_STATUS_BASE_IDX = 1 # macro +regGFX_IMU_FUSESTRAP = 0x4094 # macro +regGFX_IMU_SMUIO_VIDCHG_CTRL = 0x4098 # macro +regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_GFXCLK_BYPASS_CTRL = 0x409c # macro +regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_CLK_CTRL = 0x409d # macro +regGFX_IMU_CLK_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_DOORBELL_CONTROL = 0x409e # macro +regGFX_IMU_DOORBELL_CONTROL_BASE_IDX = 1 # macro +regGFX_IMU_RLC_CG_CTRL = 0x40a0 # macro +regGFX_IMU_RLC_CG_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_RLC_THROTTLE_GFX = 0x40a1 # macro +regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX = 1 # macro +regGFX_IMU_RLC_RESET_VECTOR = 0x40a2 # macro +regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX = 1 # macro +regGFX_IMU_RLC_OVERRIDE = 0x40a3 # macro +regGFX_IMU_RLC_OVERRIDE_BASE_IDX = 1 # macro +regGFX_IMU_DPM_CONTROL = 0x40a8 # macro +regGFX_IMU_DPM_CONTROL_BASE_IDX = 1 # macro +regGFX_IMU_DPM_ACC = 0x40a9 # macro +regGFX_IMU_DPM_ACC_BASE_IDX = 1 # macro +regGFX_IMU_DPM_REF_COUNTER = 0x40aa # macro +regGFX_IMU_DPM_REF_COUNTER_BASE_IDX = 1 # macro +regGFX_IMU_RLC_RAM_INDEX = 0x40ac # macro +regGFX_IMU_RLC_RAM_INDEX_BASE_IDX = 1 # macro +regGFX_IMU_RLC_RAM_ADDR_HIGH = 0x40ad # macro +regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX = 1 # macro +regGFX_IMU_RLC_RAM_ADDR_LOW = 0x40ae # macro +regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX = 1 # macro +regGFX_IMU_RLC_RAM_DATA = 0x40af # macro +regGFX_IMU_RLC_RAM_DATA_BASE_IDX = 1 # macro +regGFX_IMU_FENCE_CTRL = 0x40b0 # macro +regGFX_IMU_FENCE_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_FENCE_LOG_INIT = 0x40b1 # macro +regGFX_IMU_FENCE_LOG_INIT_BASE_IDX = 1 # macro +regGFX_IMU_FENCE_LOG_ADDR = 0x40b2 # macro +regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX = 1 # macro +regGFX_IMU_PROGRAM_CTR = 0x40b5 # macro +regGFX_IMU_PROGRAM_CTR_BASE_IDX = 1 # macro +regGFX_IMU_CORE_CTRL = 0x40b6 # macro +regGFX_IMU_CORE_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_CORE_STATUS = 0x40b7 # macro +regGFX_IMU_CORE_STATUS_BASE_IDX = 1 # macro +regGFX_IMU_PWROKRAW = 0x40b8 # macro +regGFX_IMU_PWROKRAW_BASE_IDX = 1 # macro +regGFX_IMU_PWROK = 0x40b9 # macro +regGFX_IMU_PWROK_BASE_IDX = 1 # macro +regGFX_IMU_GAP_PWROK = 0x40ba # macro +regGFX_IMU_GAP_PWROK_BASE_IDX = 1 # macro +regGFX_IMU_RESETn = 0x40bb # macro +regGFX_IMU_RESETn_BASE_IDX = 1 # macro +regGFX_IMU_GFX_RESET_CTRL = 0x40bc # macro +regGFX_IMU_GFX_RESET_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_AEB_OVERRIDE = 0x40bd # macro +regGFX_IMU_AEB_OVERRIDE_BASE_IDX = 1 # macro +regGFX_IMU_VDCI_RESET_CTRL = 0x40be # macro +regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_GFX_ISO_CTRL = 0x40bf # macro +regGFX_IMU_GFX_ISO_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_CTRL0 = 0x40c0 # macro +regGFX_IMU_TIMER0_CTRL0_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_CTRL1 = 0x40c1 # macro +regGFX_IMU_TIMER0_CTRL1_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_CMP_AUTOINC = 0x40c2 # macro +regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_CMP_INTEN = 0x40c3 # macro +regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_CMP0 = 0x40c4 # macro +regGFX_IMU_TIMER0_CMP0_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_CMP1 = 0x40c5 # macro +regGFX_IMU_TIMER0_CMP1_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_CMP3 = 0x40c7 # macro +regGFX_IMU_TIMER0_CMP3_BASE_IDX = 1 # macro +regGFX_IMU_TIMER0_VALUE = 0x40c8 # macro +regGFX_IMU_TIMER0_VALUE_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_CTRL0 = 0x40c9 # macro +regGFX_IMU_TIMER1_CTRL0_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_CTRL1 = 0x40ca # macro +regGFX_IMU_TIMER1_CTRL1_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_CMP_AUTOINC = 0x40cb # macro +regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_CMP_INTEN = 0x40cc # macro +regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_CMP0 = 0x40cd # macro +regGFX_IMU_TIMER1_CMP0_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_CMP1 = 0x40ce # macro +regGFX_IMU_TIMER1_CMP1_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_CMP3 = 0x40d0 # macro +regGFX_IMU_TIMER1_CMP3_BASE_IDX = 1 # macro +regGFX_IMU_TIMER1_VALUE = 0x40d1 # macro +regGFX_IMU_TIMER1_VALUE_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_CTRL0 = 0x40d2 # macro +regGFX_IMU_TIMER2_CTRL0_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_CTRL1 = 0x40d3 # macro +regGFX_IMU_TIMER2_CTRL1_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_CMP_AUTOINC = 0x40d4 # macro +regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_CMP_INTEN = 0x40d5 # macro +regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_CMP0 = 0x40d6 # macro +regGFX_IMU_TIMER2_CMP0_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_CMP1 = 0x40d7 # macro +regGFX_IMU_TIMER2_CMP1_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_CMP3 = 0x40d9 # macro +regGFX_IMU_TIMER2_CMP3_BASE_IDX = 1 # macro +regGFX_IMU_TIMER2_VALUE = 0x40da # macro +regGFX_IMU_TIMER2_VALUE_BASE_IDX = 1 # macro +regGFX_IMU_FUSE_CTRL = 0x40e0 # macro +regGFX_IMU_FUSE_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_D_RAM_ADDR = 0x40fc # macro +regGFX_IMU_D_RAM_ADDR_BASE_IDX = 1 # macro +regGFX_IMU_D_RAM_DATA = 0x40fd # macro +regGFX_IMU_D_RAM_DATA_BASE_IDX = 1 # macro +regGFX_IMU_GFX_IH_GASKET_CTRL = 0x40ff # macro +regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX = 1 # macro +regGFX_IMU_RLC_BOOTLOADER_ADDR_HI = 0x5f81 # macro +regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX = 1 # macro +regGFX_IMU_RLC_BOOTLOADER_ADDR_LO = 0x5f82 # macro +regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX = 1 # macro +regGFX_IMU_RLC_BOOTLOADER_SIZE = 0x5f83 # macro +regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX = 1 # macro +regGFX_IMU_I_RAM_ADDR = 0x5f90 # macro +regGFX_IMU_I_RAM_ADDR_BASE_IDX = 1 # macro +regGFX_IMU_I_RAM_DATA = 0x5f91 # macro +regGFX_IMU_I_RAM_DATA_BASE_IDX = 1 # macro +ixGC_CAC_ID = 0x0000 # macro +ixGC_CAC_CNTL = 0x0001 # macro +ixGC_CAC_ACC_CP0 = 0x0010 # macro +ixGC_CAC_ACC_CP1 = 0x0011 # macro +ixGC_CAC_ACC_CP2 = 0x0012 # macro +ixGC_CAC_ACC_EA0 = 0x0013 # macro +ixGC_CAC_ACC_EA1 = 0x0014 # macro +ixGC_CAC_ACC_EA2 = 0x0015 # macro +ixGC_CAC_ACC_EA3 = 0x0016 # macro +ixGC_CAC_ACC_EA4 = 0x0017 # macro +ixGC_CAC_ACC_EA5 = 0x0018 # macro +ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0019 # macro +ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x001a # macro +ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x001b # macro +ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x001c # macro +ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x001d # macro +ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x001e # macro +ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x001f # macro +ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x0020 # macro +ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x0021 # macro +ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0022 # macro +ixGC_CAC_ACC_UTCL2_VML20 = 0x0023 # macro +ixGC_CAC_ACC_UTCL2_VML21 = 0x0024 # macro +ixGC_CAC_ACC_UTCL2_VML22 = 0x0025 # macro +ixGC_CAC_ACC_UTCL2_VML23 = 0x0026 # macro +ixGC_CAC_ACC_UTCL2_VML24 = 0x0027 # macro +ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0028 # macro +ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0029 # macro +ixGC_CAC_ACC_UTCL2_WALKER2 = 0x002a # macro +ixGC_CAC_ACC_UTCL2_WALKER3 = 0x002b # macro +ixGC_CAC_ACC_UTCL2_WALKER4 = 0x002c # macro +ixGC_CAC_ACC_GDS0 = 0x002d # macro +ixGC_CAC_ACC_GDS1 = 0x002e # macro +ixGC_CAC_ACC_GDS2 = 0x002f # macro +ixGC_CAC_ACC_GDS3 = 0x0030 # macro +ixGC_CAC_ACC_GDS4 = 0x0031 # macro +ixGC_CAC_ACC_GE0 = 0x0032 # macro +ixGC_CAC_ACC_GE1 = 0x0033 # macro +ixGC_CAC_ACC_GE2 = 0x0034 # macro +ixGC_CAC_ACC_GE3 = 0x0035 # macro +ixGC_CAC_ACC_GE4 = 0x0036 # macro +ixGC_CAC_ACC_GE5 = 0x0037 # macro +ixGC_CAC_ACC_GE6 = 0x0038 # macro +ixGC_CAC_ACC_GE7 = 0x0039 # macro +ixGC_CAC_ACC_GE8 = 0x003a # macro +ixGC_CAC_ACC_GE9 = 0x003b # macro +ixGC_CAC_ACC_GE10 = 0x003c # macro +ixGC_CAC_ACC_GE11 = 0x003d # macro +ixGC_CAC_ACC_GE12 = 0x003e # macro +ixGC_CAC_ACC_GE13 = 0x003f # macro +ixGC_CAC_ACC_GE14 = 0x0040 # macro +ixGC_CAC_ACC_GE15 = 0x0041 # macro +ixGC_CAC_ACC_GE16 = 0x0042 # macro +ixGC_CAC_ACC_GE17 = 0x0043 # macro +ixGC_CAC_ACC_GE18 = 0x0044 # macro +ixGC_CAC_ACC_GE19 = 0x0045 # macro +ixGC_CAC_ACC_GE20 = 0x0046 # macro +ixGC_CAC_ACC_PMM0 = 0x0047 # macro +ixGC_CAC_ACC_GL2C0 = 0x0048 # macro +ixGC_CAC_ACC_GL2C1 = 0x0049 # macro +ixGC_CAC_ACC_GL2C2 = 0x004a # macro +ixGC_CAC_ACC_GL2C3 = 0x004b # macro +ixGC_CAC_ACC_GL2C4 = 0x004c # macro +ixGC_CAC_ACC_PH0 = 0x004d # macro +ixGC_CAC_ACC_PH1 = 0x004e # macro +ixGC_CAC_ACC_PH2 = 0x004f # macro +ixGC_CAC_ACC_PH3 = 0x0050 # macro +ixGC_CAC_ACC_PH4 = 0x0051 # macro +ixGC_CAC_ACC_PH5 = 0x0052 # macro +ixGC_CAC_ACC_PH6 = 0x0053 # macro +ixGC_CAC_ACC_PH7 = 0x0054 # macro +ixGC_CAC_ACC_SDMA0 = 0x0055 # macro +ixGC_CAC_ACC_SDMA1 = 0x0056 # macro +ixGC_CAC_ACC_SDMA2 = 0x0057 # macro +ixGC_CAC_ACC_SDMA3 = 0x0058 # macro +ixGC_CAC_ACC_SDMA4 = 0x0059 # macro +ixGC_CAC_ACC_SDMA5 = 0x005a # macro +ixGC_CAC_ACC_SDMA6 = 0x005b # macro +ixGC_CAC_ACC_SDMA7 = 0x005c # macro +ixGC_CAC_ACC_SDMA8 = 0x005d # macro +ixGC_CAC_ACC_SDMA9 = 0x005e # macro +ixGC_CAC_ACC_SDMA10 = 0x005f # macro +ixGC_CAC_ACC_SDMA11 = 0x0060 # macro +ixGC_CAC_ACC_CHC0 = 0x0061 # macro +ixGC_CAC_ACC_CHC1 = 0x0062 # macro +ixGC_CAC_ACC_CHC2 = 0x0063 # macro +ixGC_CAC_ACC_GUS0 = 0x0064 # macro +ixGC_CAC_ACC_GUS1 = 0x0065 # macro +ixGC_CAC_ACC_GUS2 = 0x0066 # macro +ixGC_CAC_ACC_RLC0 = 0x0067 # macro +ixRELEASE_TO_STALL_LUT_1_8 = 0x0100 # macro +ixRELEASE_TO_STALL_LUT_9_16 = 0x0101 # macro +ixRELEASE_TO_STALL_LUT_17_20 = 0x0102 # macro +ixSTALL_TO_RELEASE_LUT_1_4 = 0x0103 # macro +ixSTALL_TO_RELEASE_LUT_5_7 = 0x0104 # macro +ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0105 # macro +ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0106 # macro +ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0107 # macro +ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0108 # macro +ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0109 # macro +ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x010a # macro +ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x010b # macro +ixFIXED_PATTERN_PERF_COUNTER_1 = 0x010c # macro +ixFIXED_PATTERN_PERF_COUNTER_2 = 0x010d # macro +ixFIXED_PATTERN_PERF_COUNTER_3 = 0x010e # macro +ixFIXED_PATTERN_PERF_COUNTER_4 = 0x010f # macro +ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0110 # macro +ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0111 # macro +ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0112 # macro +ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0113 # macro +ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0114 # macro +ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0115 # macro +ixHW_LUT_UPDATE_STATUS = 0x0116 # macro +ixSE_CAC_ID = 0x0000 # macro +ixSE_CAC_CNTL = 0x0001 # macro +ixRTAVFS_REG0 = 0x0000 # macro +ixRTAVFS_REG1 = 0x0001 # macro +ixRTAVFS_REG2 = 0x0002 # macro +ixRTAVFS_REG3 = 0x0003 # macro +ixRTAVFS_REG4 = 0x0004 # macro +ixRTAVFS_REG5 = 0x0005 # macro +ixRTAVFS_REG6 = 0x0006 # macro +ixRTAVFS_REG7 = 0x0007 # macro +ixRTAVFS_REG8 = 0x0008 # macro +ixRTAVFS_REG9 = 0x0009 # macro +ixRTAVFS_REG10 = 0x000a # macro +ixRTAVFS_REG11 = 0x000b # macro +ixRTAVFS_REG12 = 0x000c # macro +ixRTAVFS_REG13 = 0x000d # macro +ixRTAVFS_REG14 = 0x000e # macro +ixRTAVFS_REG15 = 0x000f # macro +ixRTAVFS_REG16 = 0x0010 # macro +ixRTAVFS_REG17 = 0x0011 # macro +ixRTAVFS_REG18 = 0x0012 # macro +ixRTAVFS_REG19 = 0x0013 # macro +ixRTAVFS_REG20 = 0x0014 # macro +ixRTAVFS_REG21 = 0x0015 # macro +ixRTAVFS_REG22 = 0x0016 # macro +ixRTAVFS_REG23 = 0x0017 # macro +ixRTAVFS_REG24 = 0x0018 # macro +ixRTAVFS_REG25 = 0x0019 # macro +ixRTAVFS_REG26 = 0x001a # macro +ixRTAVFS_REG27 = 0x001b # macro +ixRTAVFS_REG28 = 0x001c # macro +ixRTAVFS_REG29 = 0x001d # macro +ixRTAVFS_REG30 = 0x001e # macro +ixRTAVFS_REG31 = 0x001f # macro +ixRTAVFS_REG32 = 0x0020 # macro +ixRTAVFS_REG33 = 0x0021 # macro +ixRTAVFS_REG34 = 0x0022 # macro +ixRTAVFS_REG35 = 0x0023 # macro +ixRTAVFS_REG36 = 0x0024 # macro +ixRTAVFS_REG37 = 0x0025 # macro +ixRTAVFS_REG38 = 0x0026 # macro +ixRTAVFS_REG39 = 0x0027 # macro +ixRTAVFS_REG40 = 0x0028 # macro +ixRTAVFS_REG41 = 0x0029 # macro +ixRTAVFS_REG42 = 0x002a # macro +ixRTAVFS_REG43 = 0x002b # macro +ixRTAVFS_REG44 = 0x002c # macro +ixRTAVFS_REG45 = 0x002d # macro +ixRTAVFS_REG46 = 0x002e # macro +ixRTAVFS_REG47 = 0x002f # macro +ixRTAVFS_REG48 = 0x0030 # macro +ixRTAVFS_REG49 = 0x0031 # macro +ixRTAVFS_REG50 = 0x0032 # macro +ixRTAVFS_REG51 = 0x0033 # macro +ixRTAVFS_REG52 = 0x0034 # macro +ixRTAVFS_REG53 = 0x0035 # macro +ixRTAVFS_REG54 = 0x0036 # macro +ixRTAVFS_REG55 = 0x0037 # macro +ixRTAVFS_REG56 = 0x0038 # macro +ixRTAVFS_REG57 = 0x0039 # macro +ixRTAVFS_REG58 = 0x003a # macro +ixRTAVFS_REG59 = 0x003b # macro +ixRTAVFS_REG60 = 0x003c # macro +ixRTAVFS_REG61 = 0x003d # macro +ixRTAVFS_REG62 = 0x003e # macro +ixRTAVFS_REG63 = 0x003f # macro +ixRTAVFS_REG64 = 0x0040 # macro +ixRTAVFS_REG65 = 0x0041 # macro +ixRTAVFS_REG66 = 0x0042 # macro +ixRTAVFS_REG67 = 0x0043 # macro +ixRTAVFS_REG68 = 0x0044 # macro +ixRTAVFS_REG69 = 0x0045 # macro +ixRTAVFS_REG70 = 0x0046 # macro +ixRTAVFS_REG71 = 0x0047 # macro +ixRTAVFS_REG72 = 0x0048 # macro +ixRTAVFS_REG73 = 0x0049 # macro +ixRTAVFS_REG74 = 0x004a # macro +ixRTAVFS_REG75 = 0x004b # macro +ixRTAVFS_REG76 = 0x004c # macro +ixRTAVFS_REG77 = 0x004d # macro +ixRTAVFS_REG78 = 0x004e # macro +ixRTAVFS_REG79 = 0x004f # macro +ixRTAVFS_REG80 = 0x0050 # macro +ixRTAVFS_REG81 = 0x0051 # macro +ixRTAVFS_REG82 = 0x0052 # macro +ixRTAVFS_REG83 = 0x0053 # macro +ixRTAVFS_REG84 = 0x0054 # macro +ixRTAVFS_REG85 = 0x0055 # macro +ixRTAVFS_REG86 = 0x0056 # macro +ixRTAVFS_REG87 = 0x0057 # macro +ixRTAVFS_REG88 = 0x0058 # macro +ixRTAVFS_REG89 = 0x0059 # macro +ixRTAVFS_REG90 = 0x005a # macro +ixRTAVFS_REG91 = 0x005b # macro +ixRTAVFS_REG92 = 0x005c # macro +ixRTAVFS_REG93 = 0x005d # macro +ixRTAVFS_REG94 = 0x005e # macro +ixRTAVFS_REG95 = 0x005f # macro +ixRTAVFS_REG96 = 0x0060 # macro +ixRTAVFS_REG97 = 0x0061 # macro +ixRTAVFS_REG98 = 0x0062 # macro +ixRTAVFS_REG99 = 0x0063 # macro +ixRTAVFS_REG100 = 0x0064 # macro +ixRTAVFS_REG101 = 0x0065 # macro +ixRTAVFS_REG102 = 0x0066 # macro +ixRTAVFS_REG103 = 0x0067 # macro +ixRTAVFS_REG104 = 0x0068 # macro +ixRTAVFS_REG105 = 0x0069 # macro +ixRTAVFS_REG106 = 0x006a # macro +ixRTAVFS_REG107 = 0x006b # macro +ixRTAVFS_REG108 = 0x006c # macro +ixRTAVFS_REG109 = 0x006d # macro +ixRTAVFS_REG110 = 0x006e # macro +ixRTAVFS_REG111 = 0x006f # macro +ixRTAVFS_REG112 = 0x0070 # macro +ixRTAVFS_REG113 = 0x0071 # macro +ixRTAVFS_REG114 = 0x0072 # macro +ixRTAVFS_REG115 = 0x0073 # macro +ixRTAVFS_REG116 = 0x0074 # macro +ixRTAVFS_REG117 = 0x0075 # macro +ixRTAVFS_REG118 = 0x0076 # macro +ixRTAVFS_REG119 = 0x0077 # macro +ixRTAVFS_REG120 = 0x0078 # macro +ixRTAVFS_REG121 = 0x0079 # macro +ixRTAVFS_REG122 = 0x007a # macro +ixRTAVFS_REG123 = 0x007b # macro +ixRTAVFS_REG124 = 0x007c # macro +ixRTAVFS_REG125 = 0x007d # macro +ixRTAVFS_REG126 = 0x007e # macro +ixRTAVFS_REG127 = 0x007f # macro +ixRTAVFS_REG128 = 0x0080 # macro +ixRTAVFS_REG129 = 0x0081 # macro +ixRTAVFS_REG130 = 0x0082 # macro +ixRTAVFS_REG131 = 0x0083 # macro +ixRTAVFS_REG132 = 0x0084 # macro +ixRTAVFS_REG133 = 0x0085 # macro +ixRTAVFS_REG134 = 0x0086 # macro +ixRTAVFS_REG135 = 0x0087 # macro +ixRTAVFS_REG136 = 0x0088 # macro +ixRTAVFS_REG137 = 0x0089 # macro +ixRTAVFS_REG138 = 0x008a # macro +ixRTAVFS_REG139 = 0x008b # macro +ixRTAVFS_REG140 = 0x008c # macro +ixRTAVFS_REG141 = 0x008d # macro +ixRTAVFS_REG142 = 0x008e # macro +ixRTAVFS_REG143 = 0x008f # macro +ixRTAVFS_REG144 = 0x0090 # macro +ixRTAVFS_REG145 = 0x0091 # macro +ixRTAVFS_REG146 = 0x0092 # macro +ixRTAVFS_REG147 = 0x0093 # macro +ixRTAVFS_REG148 = 0x0094 # macro +ixRTAVFS_REG149 = 0x0095 # macro +ixRTAVFS_REG150 = 0x0096 # macro +ixRTAVFS_REG151 = 0x0097 # macro +ixRTAVFS_REG152 = 0x0098 # macro +ixRTAVFS_REG153 = 0x0099 # macro +ixRTAVFS_REG154 = 0x009a # macro +ixRTAVFS_REG155 = 0x009b # macro +ixRTAVFS_REG156 = 0x009c # macro +ixRTAVFS_REG157 = 0x009d # macro +ixRTAVFS_REG158 = 0x009e # macro +ixRTAVFS_REG159 = 0x009f # macro +ixRTAVFS_REG160 = 0x00a0 # macro +ixRTAVFS_REG161 = 0x00a1 # macro +ixRTAVFS_REG162 = 0x00a2 # macro +ixRTAVFS_REG163 = 0x00a3 # macro +ixRTAVFS_REG164 = 0x00a4 # macro +ixRTAVFS_REG165 = 0x00a5 # macro +ixRTAVFS_REG166 = 0x00a6 # macro +ixRTAVFS_REG167 = 0x00a7 # macro +ixRTAVFS_REG168 = 0x00a8 # macro +ixRTAVFS_REG169 = 0x00a9 # macro +ixRTAVFS_REG170 = 0x00aa # macro +ixRTAVFS_REG171 = 0x00ab # macro +ixRTAVFS_REG172 = 0x00ac # macro +ixRTAVFS_REG173 = 0x00ad # macro +ixRTAVFS_REG174 = 0x00ae # macro +ixRTAVFS_REG175 = 0x00af # macro +ixRTAVFS_REG176 = 0x00b0 # macro +ixRTAVFS_REG177 = 0x00b1 # macro +ixRTAVFS_REG178 = 0x00b2 # macro +ixRTAVFS_REG179 = 0x00b3 # macro +ixRTAVFS_REG180 = 0x00b4 # macro +ixRTAVFS_REG181 = 0x00b5 # macro +ixRTAVFS_REG182 = 0x00b6 # macro +ixRTAVFS_REG183 = 0x00b7 # macro +ixRTAVFS_REG184 = 0x00b8 # macro +ixRTAVFS_REG185 = 0x00b9 # macro +ixRTAVFS_REG186 = 0x00ba # macro +ixRTAVFS_REG187 = 0x00bb # macro +ixRTAVFS_REG188 = 0x00bc # macro +ixRTAVFS_REG189 = 0x00bd # macro +ixRTAVFS_REG190 = 0x00be # macro +ixRTAVFS_REG191 = 0x00bf # macro +ixRTAVFS_REG192 = 0x00c0 # macro +ixRTAVFS_REG193 = 0x00c1 # macro +ixRTAVFS_REG194 = 0x00c2 # macro +ixSQ_DEBUG_STS_LOCAL = 0x0008 # macro +ixSQ_DEBUG_CTRL_LOCAL = 0x0009 # macro +ixSQ_WAVE_ACTIVE = 0x000a # macro +ixSQ_WAVE_VALID_AND_IDLE = 0x000b # macro +ixSQ_WAVE_MODE = 0x0101 # macro +ixSQ_WAVE_STATUS = 0x0102 # macro +ixSQ_WAVE_TRAPSTS = 0x0103 # macro +ixSQ_WAVE_GPR_ALLOC = 0x0105 # macro +ixSQ_WAVE_LDS_ALLOC = 0x0106 # macro +ixSQ_WAVE_IB_STS = 0x0107 # macro +ixSQ_WAVE_PC_LO = 0x0108 # macro +ixSQ_WAVE_PC_HI = 0x0109 # macro +ixSQ_WAVE_IB_DBG1 = 0x010d # macro +ixSQ_WAVE_FLUSH_IB = 0x010e # macro +ixSQ_WAVE_FLAT_SCRATCH_LO = 0x0114 # macro +ixSQ_WAVE_FLAT_SCRATCH_HI = 0x0115 # macro +ixSQ_WAVE_HW_ID1 = 0x0117 # macro +ixSQ_WAVE_HW_ID2 = 0x0118 # macro +ixSQ_WAVE_POPS_PACKER = 0x0119 # macro +ixSQ_WAVE_SCHED_MODE = 0x011a # macro +ixSQ_WAVE_IB_STS2 = 0x011c # macro +ixSQ_WAVE_SHADER_CYCLES = 0x011d # macro +ixSQ_WAVE_TTMP0 = 0x026c # macro +ixSQ_WAVE_TTMP1 = 0x026d # macro +ixSQ_WAVE_TTMP3 = 0x026f # macro +ixSQ_WAVE_TTMP4 = 0x0270 # macro +ixSQ_WAVE_TTMP5 = 0x0271 # macro +ixSQ_WAVE_TTMP6 = 0x0272 # macro +ixSQ_WAVE_TTMP7 = 0x0273 # macro +ixSQ_WAVE_TTMP8 = 0x0274 # macro +ixSQ_WAVE_TTMP9 = 0x0275 # macro +ixSQ_WAVE_TTMP10 = 0x0276 # macro +ixSQ_WAVE_TTMP11 = 0x0277 # macro +ixSQ_WAVE_TTMP12 = 0x0278 # macro +ixSQ_WAVE_TTMP13 = 0x0279 # macro +ixSQ_WAVE_TTMP14 = 0x027a # macro +ixSQ_WAVE_TTMP15 = 0x027b # macro +ixSQ_WAVE_M0 = 0x027d # macro +ixSQ_WAVE_EXEC_LO = 0x027e # macro +ixSQ_WAVE_EXEC_HI = 0x027f # macro +_gc_11_0_0_SH_MASK_HEADER = True # macro +SDMA0_DEC_START__START__SHIFT = 0x0 # macro +SDMA0_DEC_START__START_MASK = 0xFFFFFFFF # macro +SDMA0_F32_MISC_CNTL__F32_WAKEUP__SHIFT = 0x0 # macro +SDMA0_F32_MISC_CNTL__F32_WAKEUP_MASK = 0x00000001 # macro +SDMA0_GLOBAL_TIMESTAMP_LO__DATA__SHIFT = 0x0 # macro +SDMA0_GLOBAL_TIMESTAMP_LO__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_GLOBAL_TIMESTAMP_HI__DATA__SHIFT = 0x0 # macro +SDMA0_GLOBAL_TIMESTAMP_HI__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_POWER_CNTL__LS_ENABLE__SHIFT = 0x8 # macro +SDMA0_POWER_CNTL__LS_ENABLE_MASK = 0x00000100 # macro +SDMA0_CNTL__TRAP_ENABLE__SHIFT = 0x0 # macro +SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT = 0x2 # macro +SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT = 0x3 # macro +SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x5 # macro +SDMA0_CNTL__PIO_DONE_ACK_ENABLE__SHIFT = 0x6 # macro +SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT = 0x8 # macro +SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT = 0x9 # macro +SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT = 0xa # macro +SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT = 0xb # macro +SDMA0_CNTL__PAGE_NULL_INT_ENABLE__SHIFT = 0xc # macro +SDMA0_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT = 0xd # macro +SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT = 0x10 # macro +SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT = 0x11 # macro +SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT = 0x1c # macro +SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT = 0x1d # macro +SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT = 0x1e # macro +SDMA0_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT = 0x1f # macro +SDMA0_CNTL__TRAP_ENABLE_MASK = 0x00000001 # macro +SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK = 0x00000004 # macro +SDMA0_CNTL__DATA_SWAP_ENABLE_MASK = 0x00000008 # macro +SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00000020 # macro +SDMA0_CNTL__PIO_DONE_ACK_ENABLE_MASK = 0x00000040 # macro +SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK = 0x00000100 # macro +SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK = 0x00000200 # macro +SDMA0_CNTL__CP_MES_INT_ENABLE_MASK = 0x00000400 # macro +SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK = 0x00000800 # macro +SDMA0_CNTL__PAGE_NULL_INT_ENABLE_MASK = 0x00001000 # macro +SDMA0_CNTL__PAGE_FAULT_INT_ENABLE_MASK = 0x00002000 # macro +SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK = 0x00010000 # macro +SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK = 0x00020000 # macro +SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK = 0x10000000 # macro +SDMA0_CNTL__FROZEN_INT_ENABLE_MASK = 0x20000000 # macro +SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK = 0x40000000 # macro +SDMA0_CNTL__RB_PREEMPT_INT_ENABLE_MASK = 0x80000000 # macro +SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT = 0x1 # macro +SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT = 0x2 # macro +SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT = 0x5 # macro +SDMA0_CHICKEN_BITS__RD_BURST__SHIFT = 0x6 # macro +SDMA0_CHICKEN_BITS__WR_BURST__SHIFT = 0x8 # macro +SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT = 0xa # macro +SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT = 0xe # macro +SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT = 0xf # macro +SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT = 0x10 # macro +SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT = 0x11 # macro +SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT = 0x12 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT = 0x13 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT = 0x14 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT = 0x15 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT = 0x16 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT = 0x17 # macro +SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT = 0x18 # macro +SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT = 0x19 # macro +SDMA0_CHICKEN_BITS__RESERVED__SHIFT = 0x1a # macro +SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK = 0x00000002 # macro +SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK = 0x00000004 # macro +SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK = 0x00000020 # macro +SDMA0_CHICKEN_BITS__RD_BURST_MASK = 0x000000C0 # macro +SDMA0_CHICKEN_BITS__WR_BURST_MASK = 0x00000300 # macro +SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK = 0x00003C00 # macro +SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK = 0x00004000 # macro +SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK = 0x00008000 # macro +SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK = 0x00010000 # macro +SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK = 0x00020000 # macro +SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK = 0x00040000 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK = 0x00080000 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK = 0x00100000 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK = 0x00200000 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK = 0x00400000 # macro +SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK = 0x00800000 # macro +SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK = 0x01000000 # macro +SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK = 0x02000000 # macro +SDMA0_CHICKEN_BITS__RESERVED_MASK = 0xFC000000 # macro +SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT = 0x0 # macro +SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +SDMA0_GB_ADDR_CONFIG__NUM_PKRS__SHIFT = 0x8 # macro +SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT = 0x1a # macro +SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK = 0x00000007 # macro +SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +SDMA0_GB_ADDR_CONFIG__NUM_PKRS_MASK = 0x00000700 # macro +SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT = 0x0 # macro +SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT = 0x8 # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT = 0x1a # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK = 0x00000007 # macro +SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK = 0x00000700 # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT = 0x2 # macro +SDMA0_RB_RPTR_FETCH__OFFSET_MASK = 0xFFFFFFFC # macro +SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT = 0x0 # macro +SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK = 0xFFFFFFFF # macro +SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT = 0x2 # macro +SDMA0_IB_OFFSET_FETCH__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_PROGRAM__STREAM__SHIFT = 0x0 # macro +SDMA0_PROGRAM__STREAM_MASK = 0xFFFFFFFF # macro +SDMA0_STATUS_REG__IDLE__SHIFT = 0x0 # macro +SDMA0_STATUS_REG__REG_IDLE__SHIFT = 0x1 # macro +SDMA0_STATUS_REG__RB_EMPTY__SHIFT = 0x2 # macro +SDMA0_STATUS_REG__RB_FULL__SHIFT = 0x3 # macro +SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT = 0x4 # macro +SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT = 0x5 # macro +SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT = 0x6 # macro +SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT = 0x7 # macro +SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT = 0x8 # macro +SDMA0_STATUS_REG__INSIDE_IB__SHIFT = 0x9 # macro +SDMA0_STATUS_REG__EX_IDLE__SHIFT = 0xa # macro +SDMA0_STATUS_REG__CGCG_FENCE__SHIFT = 0xb # macro +SDMA0_STATUS_REG__PACKET_READY__SHIFT = 0xc # macro +SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT = 0xd # macro +SDMA0_STATUS_REG__SRBM_IDLE__SHIFT = 0xe # macro +SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT = 0xf # macro +SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT = 0x10 # macro +SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT = 0x11 # macro +SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT = 0x12 # macro +SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT = 0x13 # macro +SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT = 0x14 # macro +SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT = 0x15 # macro +SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT = 0x16 # macro +SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT = 0x19 # macro +SDMA0_STATUS_REG__SEM_IDLE__SHIFT = 0x1a # macro +SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT = 0x1b # macro +SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT = 0x1c # macro +SDMA0_STATUS_REG__INT_IDLE__SHIFT = 0x1e # macro +SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT = 0x1f # macro +SDMA0_STATUS_REG__IDLE_MASK = 0x00000001 # macro +SDMA0_STATUS_REG__REG_IDLE_MASK = 0x00000002 # macro +SDMA0_STATUS_REG__RB_EMPTY_MASK = 0x00000004 # macro +SDMA0_STATUS_REG__RB_FULL_MASK = 0x00000008 # macro +SDMA0_STATUS_REG__RB_CMD_IDLE_MASK = 0x00000010 # macro +SDMA0_STATUS_REG__RB_CMD_FULL_MASK = 0x00000020 # macro +SDMA0_STATUS_REG__IB_CMD_IDLE_MASK = 0x00000040 # macro +SDMA0_STATUS_REG__IB_CMD_FULL_MASK = 0x00000080 # macro +SDMA0_STATUS_REG__BLOCK_IDLE_MASK = 0x00000100 # macro +SDMA0_STATUS_REG__INSIDE_IB_MASK = 0x00000200 # macro +SDMA0_STATUS_REG__EX_IDLE_MASK = 0x00000400 # macro +SDMA0_STATUS_REG__CGCG_FENCE_MASK = 0x00000800 # macro +SDMA0_STATUS_REG__PACKET_READY_MASK = 0x00001000 # macro +SDMA0_STATUS_REG__MC_WR_IDLE_MASK = 0x00002000 # macro +SDMA0_STATUS_REG__SRBM_IDLE_MASK = 0x00004000 # macro +SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK = 0x00008000 # macro +SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK = 0x00010000 # macro +SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK = 0x00020000 # macro +SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK = 0x00040000 # macro +SDMA0_STATUS_REG__MC_RD_IDLE_MASK = 0x00080000 # macro +SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK = 0x00100000 # macro +SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK = 0x00200000 # macro +SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK = 0x00400000 # macro +SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK = 0x02000000 # macro +SDMA0_STATUS_REG__SEM_IDLE_MASK = 0x04000000 # macro +SDMA0_STATUS_REG__SEM_REQ_STALL_MASK = 0x08000000 # macro +SDMA0_STATUS_REG__SEM_RESP_STATE_MASK = 0x30000000 # macro +SDMA0_STATUS_REG__INT_IDLE_MASK = 0x40000000 # macro +SDMA0_STATUS_REG__INT_REQ_STALL_MASK = 0x80000000 # macro +SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT = 0x0 # macro +SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT = 0x1 # macro +SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT = 0x2 # macro +SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT = 0x3 # macro +SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT = 0x4 # macro +SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT = 0x5 # macro +SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT = 0x6 # macro +SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT = 0x9 # macro +SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT = 0xa # macro +SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT = 0xb # macro +SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT = 0xc # macro +SDMA0_STATUS1_REG__EX_START__SHIFT = 0xd # macro +SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT = 0xf # macro +SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT = 0x10 # macro +SDMA0_STATUS1_REG__SEC_INTR_STATUS__SHIFT = 0x11 # macro +SDMA0_STATUS1_REG__WPTR_POLL_IDLE__SHIFT = 0x12 # macro +SDMA0_STATUS1_REG__SDMA_IDLE__SHIFT = 0x13 # macro +SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK = 0x00000001 # macro +SDMA0_STATUS1_REG__CE_WR_IDLE_MASK = 0x00000002 # macro +SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK = 0x00000004 # macro +SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK = 0x00000008 # macro +SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK = 0x00000010 # macro +SDMA0_STATUS1_REG__CE_IN_IDLE_MASK = 0x00000020 # macro +SDMA0_STATUS1_REG__CE_DST_IDLE_MASK = 0x00000040 # macro +SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK = 0x00000200 # macro +SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK = 0x00000400 # macro +SDMA0_STATUS1_REG__CE_INFO_FULL_MASK = 0x00000800 # macro +SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK = 0x00001000 # macro +SDMA0_STATUS1_REG__EX_START_MASK = 0x00002000 # macro +SDMA0_STATUS1_REG__CE_RD_STALL_MASK = 0x00008000 # macro +SDMA0_STATUS1_REG__CE_WR_STALL_MASK = 0x00010000 # macro +SDMA0_STATUS1_REG__SEC_INTR_STATUS_MASK = 0x00020000 # macro +SDMA0_STATUS1_REG__WPTR_POLL_IDLE_MASK = 0x00040000 # macro +SDMA0_STATUS1_REG__SDMA_IDLE_MASK = 0x00080000 # macro +SDMA0_CNTL1__WPTR_POLL_FREQUENCY__SHIFT = 0x2 # macro +SDMA0_CNTL1__WPTR_POLL_FREQUENCY_MASK = 0x0000FFFC # macro +SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT = 0x0 # macro +SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK = 0x00000003 # macro +SDMA0_UCODE_CHECKSUM__DATA__SHIFT = 0x0 # macro +SDMA0_UCODE_CHECKSUM__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_FREEZE__PREEMPT__SHIFT = 0x0 # macro +SDMA0_FREEZE__FREEZE__SHIFT = 0x4 # macro +SDMA0_FREEZE__FROZEN__SHIFT = 0x5 # macro +SDMA0_FREEZE__F32_FREEZE__SHIFT = 0x6 # macro +SDMA0_FREEZE__PREEMPT_MASK = 0x00000001 # macro +SDMA0_FREEZE__FREEZE_MASK = 0x00000010 # macro +SDMA0_FREEZE__FROZEN_MASK = 0x00000020 # macro +SDMA0_FREEZE__F32_FREEZE_MASK = 0x00000040 # macro +SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT = 0x0 # macro +SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT = 0x8 # macro +SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT = 0x10 # macro +SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT = 0x18 # macro +SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK = 0x000000FF # macro +SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK = 0x00FF0000 # macro +SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK = 0xFF000000 # macro +SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT = 0x0 # macro +SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT = 0x8 # macro +SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT = 0x10 # macro +SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT = 0x18 # macro +SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK = 0x000000FF # macro +SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK = 0x00FF0000 # macro +SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK = 0xFF000000 # macro +SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT = 0x0 # macro +SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT = 0x8 # macro +SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK = 0x000000FF # macro +SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK = 0x0000FF00 # macro +SDMA0_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT = 0x0 # macro +SDMA0_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT = 0x4 # macro +SDMA0_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT = 0x8 # macro +SDMA0_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT = 0xc # macro +SDMA0_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT = 0x10 # macro +SDMA0_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT = 0x14 # macro +SDMA0_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT = 0x18 # macro +SDMA0_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT = 0x1c # macro +SDMA0_QUEUE_STATUS0__QUEUE0_STATUS_MASK = 0x0000000F # macro +SDMA0_QUEUE_STATUS0__QUEUE1_STATUS_MASK = 0x000000F0 # macro +SDMA0_QUEUE_STATUS0__QUEUE2_STATUS_MASK = 0x00000F00 # macro +SDMA0_QUEUE_STATUS0__QUEUE3_STATUS_MASK = 0x0000F000 # macro +SDMA0_QUEUE_STATUS0__QUEUE4_STATUS_MASK = 0x000F0000 # macro +SDMA0_QUEUE_STATUS0__QUEUE5_STATUS_MASK = 0x00F00000 # macro +SDMA0_QUEUE_STATUS0__QUEUE6_STATUS_MASK = 0x0F000000 # macro +SDMA0_QUEUE_STATUS0__QUEUE7_STATUS_MASK = 0xF0000000 # macro +SDMA0_EDC_CONFIG__DIS_EDC__SHIFT = 0x1 # macro +SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT = 0x2 # macro +SDMA0_EDC_CONFIG__DIS_EDC_MASK = 0x00000002 # macro +SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK = 0x00000004 # macro +SDMA0_BA_THRESHOLD__READ_THRES__SHIFT = 0x0 # macro +SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT = 0x10 # macro +SDMA0_BA_THRESHOLD__READ_THRES_MASK = 0x000003FF # macro +SDMA0_BA_THRESHOLD__WRITE_THRES_MASK = 0x03FF0000 # macro +SDMA0_ID__DEVICE_ID__SHIFT = 0x0 # macro +SDMA0_ID__DEVICE_ID_MASK = 0x000000FF # macro +SDMA0_VERSION__MINVER__SHIFT = 0x0 # macro +SDMA0_VERSION__MAJVER__SHIFT = 0x8 # macro +SDMA0_VERSION__REV__SHIFT = 0x10 # macro +SDMA0_VERSION__MINVER_MASK = 0x0000007F # macro +SDMA0_VERSION__MAJVER_MASK = 0x00007F00 # macro +SDMA0_VERSION__REV_MASK = 0x003F0000 # macro +SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT = 0x0 # macro +SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT = 0x1 # macro +SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT = 0x2 # macro +SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT = 0x3 # macro +SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT = 0x4 # macro +SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT = 0x5 # macro +SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT = 0x6 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT = 0x7 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT = 0x8 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT = 0x9 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT = 0xa # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT = 0xb # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT = 0xc # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT = 0xd # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT = 0xe # macro +SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT = 0xf # macro +SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT = 0x10 # macro +SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK = 0x00000001 # macro +SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK = 0x00000002 # macro +SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK = 0x00000004 # macro +SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK = 0x00000008 # macro +SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK = 0x00000010 # macro +SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK = 0x00000020 # macro +SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK = 0x00000040 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK = 0x00000080 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK = 0x00000100 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK = 0x00000200 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK = 0x00000400 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK = 0x00000800 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK = 0x00001000 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK = 0x00002000 # macro +SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK = 0x00004000 # macro +SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK = 0x00008000 # macro +SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK = 0x00010000 # macro +SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT = 0x0 # macro +SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK = 0x00000001 # macro +SDMA0_STATUS2_REG__ID__SHIFT = 0x0 # macro +SDMA0_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT = 0x2 # macro +SDMA0_STATUS2_REG__CMD_OP__SHIFT = 0x10 # macro +SDMA0_STATUS2_REG__ID_MASK = 0x00000003 # macro +SDMA0_STATUS2_REG__TH0F32_INSTR_PTR_MASK = 0x0000FFFC # macro +SDMA0_STATUS2_REG__CMD_OP_MASK = 0xFFFF0000 # macro +SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT = 0x0 # macro +SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT = 0x1f # macro +SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK = 0x7FFFFFFF # macro +SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK = 0x80000000 # macro +SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT = 0x0 # macro +SDMA0_ATOMIC_PREOP_LO__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT = 0x0 # macro +SDMA0_ATOMIC_PREOP_HI__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT = 0x0 # macro +SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT = 0x5 # macro +SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT = 0x9 # macro +SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT = 0xe # macro +SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT = 0xf # macro +SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT = 0x10 # macro +SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT = 0x11 # macro +SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT = 0x12 # macro +SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT = 0x18 # macro +SDMA0_UTCL1_CNTL__REDO_DELAY_MASK = 0x0000001F # macro +SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK = 0x000001E0 # macro +SDMA0_UTCL1_CNTL__RESP_MODE_MASK = 0x00000600 # macro +SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK = 0x00004000 # macro +SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK = 0x00008000 # macro +SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK = 0x00010000 # macro +SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK = 0x00020000 # macro +SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK = 0x003C0000 # macro +SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK = 0x3F000000 # macro +SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT = 0x0 # macro +SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT = 0x4 # macro +SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT = 0x6 # macro +SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT = 0xa # macro +SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT = 0xc # macro +SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT = 0x10 # macro +SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT = 0x12 # macro +SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT = 0x16 # macro +SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK = 0x0000000F # macro +SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK = 0x00000030 # macro +SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK = 0x000003C0 # macro +SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK = 0x00000C00 # macro +SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK = 0x0000F000 # macro +SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK = 0x00030000 # macro +SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK = 0x003C0000 # macro +SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK = 0x00C00000 # macro +SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT = 0x0 # macro +SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT_MASK = 0x0000FFFF # macro +SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT = 0x0 # macro +SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT = 0x1 # macro +SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT = 0x6 # macro +SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT = 0xa # macro +SDMA0_UTCL1_PAGE__USE_IO__SHIFT = 0xb # macro +SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT = 0xc # macro +SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT = 0xe # macro +SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT = 0x10 # macro +SDMA0_UTCL1_PAGE__USE_BC__SHIFT = 0x16 # macro +SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT = 0x17 # macro +SDMA0_UTCL1_PAGE__LLC_NOALLOC__SHIFT = 0x18 # macro +SDMA0_UTCL1_PAGE__VM_HOLE_MASK = 0x00000001 # macro +SDMA0_UTCL1_PAGE__REQ_TYPE_MASK = 0x0000001E # macro +SDMA0_UTCL1_PAGE__USE_MTYPE_MASK = 0x000003C0 # macro +SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK = 0x00000400 # macro +SDMA0_UTCL1_PAGE__USE_IO_MASK = 0x00000800 # macro +SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK = 0x00003000 # macro +SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK = 0x0000C000 # macro +SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK = 0x003F0000 # macro +SDMA0_UTCL1_PAGE__USE_BC_MASK = 0x00400000 # macro +SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK = 0x00800000 # macro +SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK = 0x01000000 # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT = 0x0 # macro +SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT = 0x1 # macro +SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT = 0x2 # macro +SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT = 0x3 # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT = 0x4 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED0__SHIFT = 0x5 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED1__SHIFT = 0x6 # macro +SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT = 0x7 # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT = 0x8 # macro +SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT = 0x9 # macro +SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT = 0xa # macro +SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT = 0xb # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT = 0xc # macro +SDMA0_UTCL1_RD_STATUS__RESERVED2__SHIFT = 0xd # macro +SDMA0_UTCL1_RD_STATUS__RESERVED3__SHIFT = 0xe # macro +SDMA0_UTCL1_RD_STATUS__META_Q_FULL__SHIFT = 0xf # macro +SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT = 0x10 # macro +SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT = 0x11 # macro +SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT = 0x12 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT = 0x13 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT = 0x15 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT = 0x16 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT = 0x17 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT = 0x18 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT = 0x19 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED4__SHIFT = 0x1a # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT = 0x1b # macro +SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT = 0x1c # macro +SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT = 0x1d # macro +SDMA0_UTCL1_RD_STATUS__INV_BUSY__SHIFT = 0x1e # macro +SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT = 0x1f # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK = 0x00000001 # macro +SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK = 0x00000002 # macro +SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK = 0x00000004 # macro +SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK = 0x00000008 # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK = 0x00000010 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED0_MASK = 0x00000020 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED1_MASK = 0x00000040 # macro +SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY_MASK = 0x00000080 # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK = 0x00000100 # macro +SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK = 0x00000200 # macro +SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK = 0x00000400 # macro +SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK = 0x00000800 # macro +SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK = 0x00001000 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED2_MASK = 0x00002000 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED3_MASK = 0x00004000 # macro +SDMA0_UTCL1_RD_STATUS__META_Q_FULL_MASK = 0x00008000 # macro +SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK = 0x00010000 # macro +SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK = 0x00020000 # macro +SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK = 0x00040000 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK = 0x00180000 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK = 0x00200000 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK = 0x00400000 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK = 0x00800000 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK = 0x01000000 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK = 0x02000000 # macro +SDMA0_UTCL1_RD_STATUS__RESERVED4_MASK = 0x04000000 # macro +SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK = 0x08000000 # macro +SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK = 0x10000000 # macro +SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK = 0x20000000 # macro +SDMA0_UTCL1_RD_STATUS__INV_BUSY_MASK = 0x40000000 # macro +SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK = 0x80000000 # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT = 0x0 # macro +SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT = 0x1 # macro +SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT = 0x2 # macro +SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT = 0x3 # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT = 0x4 # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT = 0x5 # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT = 0x6 # macro +SDMA0_UTCL1_WR_STATUS__RESERVED0__SHIFT = 0x7 # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT = 0x8 # macro +SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT = 0x9 # macro +SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT = 0xa # macro +SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT = 0xb # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT = 0xc # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT = 0xd # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT = 0xe # macro +SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT = 0xf # macro +SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT = 0x10 # macro +SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT = 0x11 # macro +SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT = 0x12 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT = 0x13 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT = 0x15 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT = 0x16 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT = 0x17 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT = 0x18 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT = 0x19 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT = 0x1a # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT = 0x1b # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT = 0x1c # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT = 0x1d # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT = 0x1e # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT = 0x1f # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK = 0x00000001 # macro +SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK = 0x00000002 # macro +SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK = 0x00000004 # macro +SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK = 0x00000008 # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK = 0x00000010 # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK = 0x00000020 # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK = 0x00000040 # macro +SDMA0_UTCL1_WR_STATUS__RESERVED0_MASK = 0x00000080 # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK = 0x00000100 # macro +SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK = 0x00000200 # macro +SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK = 0x00000400 # macro +SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK = 0x00000800 # macro +SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK = 0x00001000 # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK = 0x00002000 # macro +SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK = 0x00004000 # macro +SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK = 0x00008000 # macro +SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK = 0x00010000 # macro +SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK = 0x00020000 # macro +SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK = 0x00040000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK = 0x00180000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK = 0x00200000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK = 0x00400000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK = 0x00800000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK = 0x01000000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK = 0x02000000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK = 0x04000000 # macro +SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK = 0x08000000 # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK = 0x10000000 # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK = 0x20000000 # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK = 0x40000000 # macro +SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK = 0x80000000 # macro +SDMA0_UTCL1_INV0__INV_PROC_BUSY__SHIFT = 0x0 # macro +SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT = 0x1 # macro +SDMA0_UTCL1_INV0__GPUVM_VMID__SHIFT = 0x7 # macro +SDMA0_UTCL1_INV0__GPUVM_MODE__SHIFT = 0xb # macro +SDMA0_UTCL1_INV0__GPUVM_HIGH__SHIFT = 0xd # macro +SDMA0_UTCL1_INV0__GPUVM_TAG__SHIFT = 0xe # macro +SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT = 0x12 # macro +SDMA0_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT = 0x16 # macro +SDMA0_UTCL1_INV0__INV_TYPE__SHIFT = 0x1a # macro +SDMA0_UTCL1_INV0__INV_PROC_BUSY_MASK = 0x00000001 # macro +SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK = 0x0000007E # macro +SDMA0_UTCL1_INV0__GPUVM_VMID_MASK = 0x00000780 # macro +SDMA0_UTCL1_INV0__GPUVM_MODE_MASK = 0x00001800 # macro +SDMA0_UTCL1_INV0__GPUVM_HIGH_MASK = 0x00002000 # macro +SDMA0_UTCL1_INV0__GPUVM_TAG_MASK = 0x0003C000 # macro +SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH_MASK = 0x003C0000 # macro +SDMA0_UTCL1_INV0__GPUVM_VMID_LOW_MASK = 0x03C00000 # macro +SDMA0_UTCL1_INV0__INV_TYPE_MASK = 0x0C000000 # macro +SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT = 0x0 # macro +SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK = 0xFFFFFFFF # macro +SDMA0_UTCL1_INV2__CPF_VMID__SHIFT = 0x0 # macro +SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT = 0x10 # macro +SDMA0_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT = 0x11 # macro +SDMA0_UTCL1_INV2__CPF_VMID_MASK = 0x0000FFFF # macro +SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE_MASK = 0x00010000 # macro +SDMA0_UTCL1_INV2__CPF_FRAG_SIZE_MASK = 0x007E0000 # macro +SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT = 0x0 # macro +SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK = 0xFFFFFFFF # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT = 0x0 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT = 0x4 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT = 0x8 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT = 0xa # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT = 0xc # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT = 0xe # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT = 0xf # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT = 0x10 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK = 0x0000000F # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK = 0x000000F0 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK = 0x00000300 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK = 0x00000C00 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK = 0x00003000 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK = 0x00004000 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK = 0x00008000 # macro +SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK = 0x00010000 # macro +SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT = 0x0 # macro +SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK = 0xFFFFFFFF # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT = 0x0 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT = 0x4 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT = 0x8 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT = 0xa # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT = 0xc # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT = 0xe # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT = 0xf # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT = 0x10 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK = 0x0000000F # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK = 0x000000F0 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK = 0x00000300 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK = 0x00000C00 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK = 0x00003000 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK = 0x00004000 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK = 0x00008000 # macro +SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK = 0x00010000 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT = 0x0 # macro +SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT = 0x1 # macro +SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT = 0x2 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT = 0x3 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT = 0x4 # macro +SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT = 0x5 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT = 0x6 # macro +SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT = 0x8 # macro +SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT = 0x9 # macro +SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT = 0xa # macro +SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT = 0xb # macro +SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT = 0xc # macro +SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT = 0xd # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT = 0xe # macro +SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT = 0x1b # macro +SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT = 0x1c # macro +SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT = 0x1d # macro +SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT = 0x1e # macro +SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT = 0x1f # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK = 0x00000001 # macro +SDMA0_RELAX_ORDERING_LUT__COPY_MASK = 0x00000002 # macro +SDMA0_RELAX_ORDERING_LUT__WRITE_MASK = 0x00000004 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK = 0x00000008 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK = 0x00000010 # macro +SDMA0_RELAX_ORDERING_LUT__FENCE_MASK = 0x00000020 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK = 0x000000C0 # macro +SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK = 0x00000100 # macro +SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK = 0x00000200 # macro +SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK = 0x00000400 # macro +SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK = 0x00000800 # macro +SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK = 0x00001000 # macro +SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK = 0x00002000 # macro +SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK = 0x07FFC000 # macro +SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK = 0x08000000 # macro +SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK = 0x10000000 # macro +SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK = 0x20000000 # macro +SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK = 0x40000000 # macro +SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK = 0x80000000 # macro +SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT = 0x0 # macro +SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT = 0x4 # macro +SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT = 0x6 # macro +SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT = 0x7 # macro +SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT = 0x8 # macro +SDMA0_CHICKEN_BITS_2__RESERVED_14_12__SHIFT = 0xc # macro +SDMA0_CHICKEN_BITS_2__RESERVED_15__SHIFT = 0xf # macro +SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT = 0x10 # macro +SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT = 0x12 # macro +SDMA0_CHICKEN_BITS_2__RESERVED_22_20__SHIFT = 0x14 # macro +SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT = 0x17 # macro +SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT = 0x19 # macro +SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT = 0x1e # macro +SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT = 0x1f # macro +SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK = 0x0000000F # macro +SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK = 0x00000010 # macro +SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK = 0x00000040 # macro +SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK = 0x00000080 # macro +SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK = 0x00000F00 # macro +SDMA0_CHICKEN_BITS_2__RESERVED_14_12_MASK = 0x00007000 # macro +SDMA0_CHICKEN_BITS_2__RESERVED_15_MASK = 0x00008000 # macro +SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK = 0x00030000 # macro +SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK = 0x000C0000 # macro +SDMA0_CHICKEN_BITS_2__RESERVED_22_20_MASK = 0x00700000 # macro +SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK = 0x01800000 # macro +SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK = 0x3E000000 # macro +SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK = 0x40000000 # macro +SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK = 0x80000000 # macro +SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT = 0x0 # macro +SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT = 0x10 # macro +SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT = 0x14 # macro +SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT = 0x15 # macro +SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT = 0x16 # macro +SDMA0_STATUS3_REG__GCR_IDLE__SHIFT = 0x17 # macro +SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT = 0x18 # macro +SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT = 0x19 # macro +SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT = 0x1a # macro +SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT = 0x1e # macro +SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK = 0x0000FFFF # macro +SDMA0_STATUS3_REG__PREV_VM_CMD_MASK = 0x000F0000 # macro +SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK = 0x00100000 # macro +SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK = 0x00200000 # macro +SDMA0_STATUS3_REG__TLBI_IDLE_MASK = 0x00400000 # macro +SDMA0_STATUS3_REG__GCR_IDLE_MASK = 0x00800000 # macro +SDMA0_STATUS3_REG__INVREQ_IDLE_MASK = 0x01000000 # macro +SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK = 0x02000000 # macro +SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK = 0x3C000000 # macro +SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS_MASK = 0xC0000000 # macro +SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT = 0x0 # macro +SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT = 0x1 # macro +SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT = 0x2 # macro +SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT = 0xc # macro +SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK = 0x00000001 # macro +SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK = 0x00000002 # macro +SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK = 0x00000004 # macro +SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK = 0xFFFFF000 # macro +SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK = 0x0000FFFF # macro +SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT = 0x0 # macro +SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT = 0x8 # macro +SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK = 0x000000FF # macro +SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_ERROR_LOG__OVERRIDE__SHIFT = 0x0 # macro +SDMA0_ERROR_LOG__STATUS__SHIFT = 0x10 # macro +SDMA0_ERROR_LOG__OVERRIDE_MASK = 0x0000FFFF # macro +SDMA0_ERROR_LOG__STATUS_MASK = 0xFFFF0000 # macro +SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT = 0x0 # macro +SDMA0_PUB_DUMMY_REG0__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT = 0x0 # macro +SDMA0_PUB_DUMMY_REG1__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT = 0x0 # macro +SDMA0_PUB_DUMMY_REG2__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT = 0x0 # macro +SDMA0_PUB_DUMMY_REG3__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_F32_COUNTER__VALUE__SHIFT = 0x0 # macro +SDMA0_F32_COUNTER__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT = 0x7 # macro +SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT = 0xd # macro +SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT = 0x13 # macro +SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT = 0x19 # macro +SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK = 0x00001F80 # macro +SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK = 0x0007E000 # macro +SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK = 0x01F80000 # macro +SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK = 0x7E000000 # macro +SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT = 0x1 # macro +SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT = 0x10 # macro +SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK = 0x00000002 # macro +SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK = 0xFFFF0000 # macro +SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT = 0x0 # macro +SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT = 0x1 # macro +SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK = 0x00000001 # macro +SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK = 0x00000002 # macro +SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT = 0x0 # macro +SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT = 0x0 # macro +SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK = 0x00000007 # macro +SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT = 0x0 # macro +SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT = 0x4 # macro +SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT = 0x8 # macro +SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT = 0x10 # macro +SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT = 0x18 # macro +SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK = 0x0000000F # macro +SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK = 0x000000F0 # macro +SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK = 0x00000F00 # macro +SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK = 0x00FF0000 # macro +SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK = 0xFF000000 # macro +SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT = 0x4 # macro +SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK = 0x00000070 # macro +SDMA0_INT_STATUS__DATA__SHIFT = 0x0 # macro +SDMA0_INT_STATUS__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_HOLE_ADDR_LO__VALUE__SHIFT = 0x0 # macro +SDMA0_HOLE_ADDR_LO__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_HOLE_ADDR_HI__VALUE__SHIFT = 0x0 # macro +SDMA0_HOLE_ADDR_HI__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT = 0x0 # macro +SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT = 0x2 # macro +SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT = 0x3 # macro +SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT = 0x4 # macro +SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT = 0x5 # macro +SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT = 0x6 # macro +SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK = 0x00000001 # macro +SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK = 0x00000004 # macro +SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK = 0x00000008 # macro +SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK = 0x00000010 # macro +SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK = 0x00000020 # macro +SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK = 0x00000040 # macro +SDMA0_STATUS4_REG__IDLE__SHIFT = 0x0 # macro +SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT = 0x2 # macro +SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT = 0x3 # macro +SDMA0_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT = 0x4 # macro +SDMA0_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT = 0x5 # macro +SDMA0_STATUS4_REG__GCR_OUTSTANDING__SHIFT = 0x6 # macro +SDMA0_STATUS4_REG__TLBI_OUTSTANDING__SHIFT = 0x7 # macro +SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT = 0x8 # macro +SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT = 0x9 # macro +SDMA0_STATUS4_REG__REG_POLLING__SHIFT = 0xa # macro +SDMA0_STATUS4_REG__MEM_POLLING__SHIFT = 0xb # macro +SDMA0_STATUS4_REG__RESERVED_13_12__SHIFT = 0xc # macro +SDMA0_STATUS4_REG__RESERVED_15_14__SHIFT = 0xe # macro +SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT = 0x10 # macro +SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT = 0x14 # macro +SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT = 0x15 # macro +SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT = 0x16 # macro +SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT = 0x17 # macro +SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT = 0x18 # macro +SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT = 0x19 # macro +SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT = 0x1a # macro +SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT = 0x1b # macro +SDMA0_STATUS4_REG__IDLE_MASK = 0x00000001 # macro +SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK = 0x00000004 # macro +SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK = 0x00000008 # macro +SDMA0_STATUS4_REG__CH_RD_OUTSTANDING_MASK = 0x00000010 # macro +SDMA0_STATUS4_REG__CH_WR_OUTSTANDING_MASK = 0x00000020 # macro +SDMA0_STATUS4_REG__GCR_OUTSTANDING_MASK = 0x00000040 # macro +SDMA0_STATUS4_REG__TLBI_OUTSTANDING_MASK = 0x00000080 # macro +SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK = 0x00000100 # macro +SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK = 0x00000200 # macro +SDMA0_STATUS4_REG__REG_POLLING_MASK = 0x00000400 # macro +SDMA0_STATUS4_REG__MEM_POLLING_MASK = 0x00000800 # macro +SDMA0_STATUS4_REG__RESERVED_13_12_MASK = 0x00003000 # macro +SDMA0_STATUS4_REG__RESERVED_15_14_MASK = 0x0000C000 # macro +SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK = 0x000F0000 # macro +SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK = 0x00100000 # macro +SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK = 0x00200000 # macro +SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK = 0x00400000 # macro +SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK = 0x00800000 # macro +SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK = 0x01000000 # macro +SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK = 0x02000000 # macro +SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK = 0x04000000 # macro +SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK = 0x08000000 # macro +SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT = 0x0 # macro +SDMA0_SCRATCH_RAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT = 0x0 # macro +SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK = 0x0000007F # macro +SDMA0_TIMESTAMP_CNTL__CAPTURE__SHIFT = 0x0 # macro +SDMA0_TIMESTAMP_CNTL__CAPTURE_MASK = 0x00000001 # macro +SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT = 0x0 # macro +SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT = 0x1 # macro +SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT = 0x2 # macro +SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT = 0x3 # macro +SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT = 0x4 # macro +SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT = 0x5 # macro +SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT = 0x6 # macro +SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT = 0x7 # macro +SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT = 0x10 # macro +SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x14 # macro +SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x15 # macro +SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x16 # macro +SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x17 # macro +SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x18 # macro +SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x19 # macro +SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x1a # macro +SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x1b # macro +SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK = 0x00000001 # macro +SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK = 0x00000002 # macro +SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK = 0x00000004 # macro +SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK = 0x00000008 # macro +SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK = 0x00000010 # macro +SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK = 0x00000020 # macro +SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK = 0x00000040 # macro +SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK = 0x00000080 # macro +SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID_MASK = 0x000F0000 # macro +SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00100000 # macro +SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00200000 # macro +SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00400000 # macro +SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00800000 # macro +SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x01000000 # macro +SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x02000000 # macro +SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x04000000 # macro +SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x08000000 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT = 0x0 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT = 0x1 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT = 0x2 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT = 0x3 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT = 0x4 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT = 0x5 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT = 0x6 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT = 0x7 # macro +SDMA0_QUEUE_RESET_REQ__RESERVED__SHIFT = 0x8 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET_MASK = 0x00000001 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET_MASK = 0x00000002 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET_MASK = 0x00000004 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET_MASK = 0x00000008 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET_MASK = 0x00000010 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET_MASK = 0x00000020 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET_MASK = 0x00000040 # macro +SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET_MASK = 0x00000080 # macro +SDMA0_QUEUE_RESET_REQ__RESERVED_MASK = 0xFFFFFF00 # macro +SDMA0_STATUS6_REG__ID__SHIFT = 0x0 # macro +SDMA0_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT = 0x2 # macro +SDMA0_STATUS6_REG__TH1_EXCEPTION__SHIFT = 0x10 # macro +SDMA0_STATUS6_REG__ID_MASK = 0x00000003 # macro +SDMA0_STATUS6_REG__TH1F32_INSTR_PTR_MASK = 0x0000FFFC # macro +SDMA0_STATUS6_REG__TH1_EXCEPTION_MASK = 0xFFFF0000 # macro +SDMA0_UCODE1_CHECKSUM__DATA__SHIFT = 0x0 # macro +SDMA0_UCODE1_CHECKSUM__DATA_MASK = 0xFFFFFFFF # macro +SDMA0_CE_CTRL__RD_LUT_WATERMARK__SHIFT = 0x0 # macro +SDMA0_CE_CTRL__RD_LUT_DEPTH__SHIFT = 0x3 # macro +SDMA0_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT = 0x5 # macro +SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT = 0x8 # macro +SDMA0_CE_CTRL__RESERVED__SHIFT = 0x9 # macro +SDMA0_CE_CTRL__RD_LUT_WATERMARK_MASK = 0x00000007 # macro +SDMA0_CE_CTRL__RD_LUT_DEPTH_MASK = 0x00000018 # macro +SDMA0_CE_CTRL__WR_AFIFO_WATERMARK_MASK = 0x000000E0 # macro +SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK = 0x00000100 # macro +SDMA0_CE_CTRL__RESERVED_MASK = 0xFFFFFE00 # macro +SDMA0_FED_STATUS__RB_FETCH_ECC__SHIFT = 0x0 # macro +SDMA0_FED_STATUS__IB_FETCH_ECC__SHIFT = 0x1 # macro +SDMA0_FED_STATUS__F32_DATA_ECC__SHIFT = 0x2 # macro +SDMA0_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT = 0x3 # macro +SDMA0_FED_STATUS__COPY_DATA_ECC__SHIFT = 0x4 # macro +SDMA0_FED_STATUS__COPY_METADATA_ECC__SHIFT = 0x5 # macro +SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT = 0x6 # macro +SDMA0_FED_STATUS__RB_FETCH_ECC_MASK = 0x00000001 # macro +SDMA0_FED_STATUS__IB_FETCH_ECC_MASK = 0x00000002 # macro +SDMA0_FED_STATUS__F32_DATA_ECC_MASK = 0x00000004 # macro +SDMA0_FED_STATUS__WPTR_ATOMIC_ECC_MASK = 0x00000008 # macro +SDMA0_FED_STATUS__COPY_DATA_ECC_MASK = 0x00000010 # macro +SDMA0_FED_STATUS__COPY_METADATA_ECC_MASK = 0x00000020 # macro +SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC_MASK = 0x00000040 # macro +SDMA0_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE0_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE0_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE0_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE0_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE0_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE0_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE0_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE0_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE0_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE0_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE0_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE0_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE0_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE0_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE0_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE0_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE0_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE0_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE0_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT = 0x1 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB_MASK = 0x00000002 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE0_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE0_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE0_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE0_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE0_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE0_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE0_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE0_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE0_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE0_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE0_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE1_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE1_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE1_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE1_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE1_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE1_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE1_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE1_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE1_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE1_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE1_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE1_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE1_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE1_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE1_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE1_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE1_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE1_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE1_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE1_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE1_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE1_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE1_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE1_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE1_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE1_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE1_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE1_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE1_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE1_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE1_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE2_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE2_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE2_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE2_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE2_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE2_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE2_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE2_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE2_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE2_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE2_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE2_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE2_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE2_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE2_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE2_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE2_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE2_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE2_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE2_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE2_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE2_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE2_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE2_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE2_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE2_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE2_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE2_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE2_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE2_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE2_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE3_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE3_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE3_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE3_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE3_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE3_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE3_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE3_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE3_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE3_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE3_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE3_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE3_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE3_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE3_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE3_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE3_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE3_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE3_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE3_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE3_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE3_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE3_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE3_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE3_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE3_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE3_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE3_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE3_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE3_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE3_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE4_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE4_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE4_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE4_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE4_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE4_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE4_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE4_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE4_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE4_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE4_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE4_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE4_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE4_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE4_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE4_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE4_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE4_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE4_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE4_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE4_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE4_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE4_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE4_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE4_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE4_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE4_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE4_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE4_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE4_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE4_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE5_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE5_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE5_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE5_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE5_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE5_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE5_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE5_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE5_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE5_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE5_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE5_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE5_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE5_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE5_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE5_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE5_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE5_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE5_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE5_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE5_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE5_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE5_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE5_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE5_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE5_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE5_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE5_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE5_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE5_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE5_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE6_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE6_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE6_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE6_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE6_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE6_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE6_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE6_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE6_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE6_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE6_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE6_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE6_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE6_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE6_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE6_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE6_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE6_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE6_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE6_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE6_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE6_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE6_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE6_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE6_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE6_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE6_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE6_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE6_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE6_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE6_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA0_QUEUE7_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA0_QUEUE7_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA0_QUEUE7_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE7_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA0_QUEUE7_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA0_QUEUE7_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA0_QUEUE7_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA0_QUEUE7_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA0_QUEUE7_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA0_QUEUE7_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA0_QUEUE7_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA0_QUEUE7_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE7_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE7_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE7_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA0_QUEUE7_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA0_QUEUE7_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA0_QUEUE7_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE7_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE7_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA0_QUEUE7_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA0_QUEUE7_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA0_QUEUE7_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA0_QUEUE7_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA0_QUEUE7_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA0_QUEUE7_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA0_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE7_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE7_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA0_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA0_QUEUE7_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA0_QUEUE7_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA0_QUEUE7_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA0_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_DEC_START__START__SHIFT = 0x0 # macro +SDMA1_DEC_START__START_MASK = 0xFFFFFFFF # macro +SDMA1_F32_MISC_CNTL__F32_WAKEUP__SHIFT = 0x0 # macro +SDMA1_F32_MISC_CNTL__F32_WAKEUP_MASK = 0x00000001 # macro +SDMA1_GLOBAL_TIMESTAMP_LO__DATA__SHIFT = 0x0 # macro +SDMA1_GLOBAL_TIMESTAMP_LO__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_GLOBAL_TIMESTAMP_HI__DATA__SHIFT = 0x0 # macro +SDMA1_GLOBAL_TIMESTAMP_HI__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_POWER_CNTL__LS_ENABLE__SHIFT = 0x8 # macro +SDMA1_POWER_CNTL__LS_ENABLE_MASK = 0x00000100 # macro +SDMA1_CNTL__TRAP_ENABLE__SHIFT = 0x0 # macro +SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT = 0x2 # macro +SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT = 0x3 # macro +SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x5 # macro +SDMA1_CNTL__PIO_DONE_ACK_ENABLE__SHIFT = 0x6 # macro +SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT = 0x8 # macro +SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT = 0x9 # macro +SDMA1_CNTL__CP_MES_INT_ENABLE__SHIFT = 0xa # macro +SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT = 0xb # macro +SDMA1_CNTL__PAGE_NULL_INT_ENABLE__SHIFT = 0xc # macro +SDMA1_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT = 0xd # macro +SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT = 0x10 # macro +SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT = 0x11 # macro +SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT = 0x1c # macro +SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT = 0x1d # macro +SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT = 0x1e # macro +SDMA1_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT = 0x1f # macro +SDMA1_CNTL__TRAP_ENABLE_MASK = 0x00000001 # macro +SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK = 0x00000004 # macro +SDMA1_CNTL__DATA_SWAP_ENABLE_MASK = 0x00000008 # macro +SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00000020 # macro +SDMA1_CNTL__PIO_DONE_ACK_ENABLE_MASK = 0x00000040 # macro +SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK = 0x00000100 # macro +SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE_MASK = 0x00000200 # macro +SDMA1_CNTL__CP_MES_INT_ENABLE_MASK = 0x00000400 # macro +SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK = 0x00000800 # macro +SDMA1_CNTL__PAGE_NULL_INT_ENABLE_MASK = 0x00001000 # macro +SDMA1_CNTL__PAGE_FAULT_INT_ENABLE_MASK = 0x00002000 # macro +SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK = 0x00010000 # macro +SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK = 0x00020000 # macro +SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK = 0x10000000 # macro +SDMA1_CNTL__FROZEN_INT_ENABLE_MASK = 0x20000000 # macro +SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK = 0x40000000 # macro +SDMA1_CNTL__RB_PREEMPT_INT_ENABLE_MASK = 0x80000000 # macro +SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT = 0x1 # macro +SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT = 0x2 # macro +SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT = 0x5 # macro +SDMA1_CHICKEN_BITS__RD_BURST__SHIFT = 0x6 # macro +SDMA1_CHICKEN_BITS__WR_BURST__SHIFT = 0x8 # macro +SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT = 0xa # macro +SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT = 0xe # macro +SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT = 0xf # macro +SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT = 0x10 # macro +SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT = 0x11 # macro +SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT = 0x12 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT = 0x13 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT = 0x14 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT = 0x15 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT = 0x16 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT = 0x17 # macro +SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT = 0x18 # macro +SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT = 0x19 # macro +SDMA1_CHICKEN_BITS__RESERVED__SHIFT = 0x1a # macro +SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK = 0x00000002 # macro +SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK = 0x00000004 # macro +SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK = 0x00000020 # macro +SDMA1_CHICKEN_BITS__RD_BURST_MASK = 0x000000C0 # macro +SDMA1_CHICKEN_BITS__WR_BURST_MASK = 0x00000300 # macro +SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK = 0x00003C00 # macro +SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK = 0x00004000 # macro +SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK = 0x00008000 # macro +SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK = 0x00010000 # macro +SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK = 0x00020000 # macro +SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK = 0x00040000 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK = 0x00080000 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK = 0x00100000 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK = 0x00200000 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK = 0x00400000 # macro +SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK = 0x00800000 # macro +SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK = 0x01000000 # macro +SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK = 0x02000000 # macro +SDMA1_CHICKEN_BITS__RESERVED_MASK = 0xFC000000 # macro +SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT = 0x0 # macro +SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +SDMA1_GB_ADDR_CONFIG__NUM_PKRS__SHIFT = 0x8 # macro +SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT = 0x1a # macro +SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK = 0x00000007 # macro +SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +SDMA1_GB_ADDR_CONFIG__NUM_PKRS_MASK = 0x00000700 # macro +SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT = 0x0 # macro +SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT = 0x8 # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT = 0x1a # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK = 0x00000007 # macro +SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK = 0x00000700 # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT = 0x2 # macro +SDMA1_RB_RPTR_FETCH__OFFSET_MASK = 0xFFFFFFFC # macro +SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT = 0x0 # macro +SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK = 0xFFFFFFFF # macro +SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT = 0x2 # macro +SDMA1_IB_OFFSET_FETCH__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_PROGRAM__STREAM__SHIFT = 0x0 # macro +SDMA1_PROGRAM__STREAM_MASK = 0xFFFFFFFF # macro +SDMA1_STATUS_REG__IDLE__SHIFT = 0x0 # macro +SDMA1_STATUS_REG__REG_IDLE__SHIFT = 0x1 # macro +SDMA1_STATUS_REG__RB_EMPTY__SHIFT = 0x2 # macro +SDMA1_STATUS_REG__RB_FULL__SHIFT = 0x3 # macro +SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT = 0x4 # macro +SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT = 0x5 # macro +SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT = 0x6 # macro +SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT = 0x7 # macro +SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT = 0x8 # macro +SDMA1_STATUS_REG__INSIDE_IB__SHIFT = 0x9 # macro +SDMA1_STATUS_REG__EX_IDLE__SHIFT = 0xa # macro +SDMA1_STATUS_REG__CGCG_FENCE__SHIFT = 0xb # macro +SDMA1_STATUS_REG__PACKET_READY__SHIFT = 0xc # macro +SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT = 0xd # macro +SDMA1_STATUS_REG__SRBM_IDLE__SHIFT = 0xe # macro +SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT = 0xf # macro +SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT = 0x10 # macro +SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT = 0x11 # macro +SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT = 0x12 # macro +SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT = 0x13 # macro +SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT = 0x14 # macro +SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT = 0x15 # macro +SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT = 0x16 # macro +SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT = 0x19 # macro +SDMA1_STATUS_REG__SEM_IDLE__SHIFT = 0x1a # macro +SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT = 0x1b # macro +SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT = 0x1c # macro +SDMA1_STATUS_REG__INT_IDLE__SHIFT = 0x1e # macro +SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT = 0x1f # macro +SDMA1_STATUS_REG__IDLE_MASK = 0x00000001 # macro +SDMA1_STATUS_REG__REG_IDLE_MASK = 0x00000002 # macro +SDMA1_STATUS_REG__RB_EMPTY_MASK = 0x00000004 # macro +SDMA1_STATUS_REG__RB_FULL_MASK = 0x00000008 # macro +SDMA1_STATUS_REG__RB_CMD_IDLE_MASK = 0x00000010 # macro +SDMA1_STATUS_REG__RB_CMD_FULL_MASK = 0x00000020 # macro +SDMA1_STATUS_REG__IB_CMD_IDLE_MASK = 0x00000040 # macro +SDMA1_STATUS_REG__IB_CMD_FULL_MASK = 0x00000080 # macro +SDMA1_STATUS_REG__BLOCK_IDLE_MASK = 0x00000100 # macro +SDMA1_STATUS_REG__INSIDE_IB_MASK = 0x00000200 # macro +SDMA1_STATUS_REG__EX_IDLE_MASK = 0x00000400 # macro +SDMA1_STATUS_REG__CGCG_FENCE_MASK = 0x00000800 # macro +SDMA1_STATUS_REG__PACKET_READY_MASK = 0x00001000 # macro +SDMA1_STATUS_REG__MC_WR_IDLE_MASK = 0x00002000 # macro +SDMA1_STATUS_REG__SRBM_IDLE_MASK = 0x00004000 # macro +SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK = 0x00008000 # macro +SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK = 0x00010000 # macro +SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK = 0x00020000 # macro +SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK = 0x00040000 # macro +SDMA1_STATUS_REG__MC_RD_IDLE_MASK = 0x00080000 # macro +SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK = 0x00100000 # macro +SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK = 0x00200000 # macro +SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK = 0x00400000 # macro +SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK = 0x02000000 # macro +SDMA1_STATUS_REG__SEM_IDLE_MASK = 0x04000000 # macro +SDMA1_STATUS_REG__SEM_REQ_STALL_MASK = 0x08000000 # macro +SDMA1_STATUS_REG__SEM_RESP_STATE_MASK = 0x30000000 # macro +SDMA1_STATUS_REG__INT_IDLE_MASK = 0x40000000 # macro +SDMA1_STATUS_REG__INT_REQ_STALL_MASK = 0x80000000 # macro +SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT = 0x0 # macro +SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT = 0x1 # macro +SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT = 0x2 # macro +SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT = 0x3 # macro +SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT = 0x4 # macro +SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT = 0x5 # macro +SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT = 0x6 # macro +SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT = 0x9 # macro +SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT = 0xa # macro +SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT = 0xb # macro +SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT = 0xc # macro +SDMA1_STATUS1_REG__EX_START__SHIFT = 0xd # macro +SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT = 0xf # macro +SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT = 0x10 # macro +SDMA1_STATUS1_REG__SEC_INTR_STATUS__SHIFT = 0x11 # macro +SDMA1_STATUS1_REG__WPTR_POLL_IDLE__SHIFT = 0x12 # macro +SDMA1_STATUS1_REG__SDMA_IDLE__SHIFT = 0x13 # macro +SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK = 0x00000001 # macro +SDMA1_STATUS1_REG__CE_WR_IDLE_MASK = 0x00000002 # macro +SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK = 0x00000004 # macro +SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK = 0x00000008 # macro +SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK = 0x00000010 # macro +SDMA1_STATUS1_REG__CE_IN_IDLE_MASK = 0x00000020 # macro +SDMA1_STATUS1_REG__CE_DST_IDLE_MASK = 0x00000040 # macro +SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK = 0x00000200 # macro +SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK = 0x00000400 # macro +SDMA1_STATUS1_REG__CE_INFO_FULL_MASK = 0x00000800 # macro +SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK = 0x00001000 # macro +SDMA1_STATUS1_REG__EX_START_MASK = 0x00002000 # macro +SDMA1_STATUS1_REG__CE_RD_STALL_MASK = 0x00008000 # macro +SDMA1_STATUS1_REG__CE_WR_STALL_MASK = 0x00010000 # macro +SDMA1_STATUS1_REG__SEC_INTR_STATUS_MASK = 0x00020000 # macro +SDMA1_STATUS1_REG__WPTR_POLL_IDLE_MASK = 0x00040000 # macro +SDMA1_STATUS1_REG__SDMA_IDLE_MASK = 0x00080000 # macro +SDMA1_CNTL1__WPTR_POLL_FREQUENCY__SHIFT = 0x2 # macro +SDMA1_CNTL1__WPTR_POLL_FREQUENCY_MASK = 0x0000FFFC # macro +SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT = 0x0 # macro +SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK = 0x00000003 # macro +SDMA1_UCODE_CHECKSUM__DATA__SHIFT = 0x0 # macro +SDMA1_UCODE_CHECKSUM__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_FREEZE__PREEMPT__SHIFT = 0x0 # macro +SDMA1_FREEZE__FREEZE__SHIFT = 0x4 # macro +SDMA1_FREEZE__FROZEN__SHIFT = 0x5 # macro +SDMA1_FREEZE__F32_FREEZE__SHIFT = 0x6 # macro +SDMA1_FREEZE__PREEMPT_MASK = 0x00000001 # macro +SDMA1_FREEZE__FREEZE_MASK = 0x00000010 # macro +SDMA1_FREEZE__FROZEN_MASK = 0x00000020 # macro +SDMA1_FREEZE__F32_FREEZE_MASK = 0x00000040 # macro +SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT = 0x0 # macro +SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT = 0x8 # macro +SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT = 0x10 # macro +SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT = 0x18 # macro +SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK = 0x000000FF # macro +SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK = 0x00FF0000 # macro +SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK = 0xFF000000 # macro +SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT = 0x0 # macro +SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT = 0x8 # macro +SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT = 0x10 # macro +SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT = 0x18 # macro +SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK = 0x000000FF # macro +SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK = 0x00FF0000 # macro +SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK = 0xFF000000 # macro +SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT = 0x0 # macro +SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT = 0x8 # macro +SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK = 0x000000FF # macro +SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK = 0x0000FF00 # macro +SDMA1_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT = 0x0 # macro +SDMA1_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT = 0x4 # macro +SDMA1_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT = 0x8 # macro +SDMA1_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT = 0xc # macro +SDMA1_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT = 0x10 # macro +SDMA1_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT = 0x14 # macro +SDMA1_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT = 0x18 # macro +SDMA1_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT = 0x1c # macro +SDMA1_QUEUE_STATUS0__QUEUE0_STATUS_MASK = 0x0000000F # macro +SDMA1_QUEUE_STATUS0__QUEUE1_STATUS_MASK = 0x000000F0 # macro +SDMA1_QUEUE_STATUS0__QUEUE2_STATUS_MASK = 0x00000F00 # macro +SDMA1_QUEUE_STATUS0__QUEUE3_STATUS_MASK = 0x0000F000 # macro +SDMA1_QUEUE_STATUS0__QUEUE4_STATUS_MASK = 0x000F0000 # macro +SDMA1_QUEUE_STATUS0__QUEUE5_STATUS_MASK = 0x00F00000 # macro +SDMA1_QUEUE_STATUS0__QUEUE6_STATUS_MASK = 0x0F000000 # macro +SDMA1_QUEUE_STATUS0__QUEUE7_STATUS_MASK = 0xF0000000 # macro +SDMA1_EDC_CONFIG__DIS_EDC__SHIFT = 0x1 # macro +SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT = 0x2 # macro +SDMA1_EDC_CONFIG__DIS_EDC_MASK = 0x00000002 # macro +SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK = 0x00000004 # macro +SDMA1_BA_THRESHOLD__READ_THRES__SHIFT = 0x0 # macro +SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT = 0x10 # macro +SDMA1_BA_THRESHOLD__READ_THRES_MASK = 0x000003FF # macro +SDMA1_BA_THRESHOLD__WRITE_THRES_MASK = 0x03FF0000 # macro +SDMA1_ID__DEVICE_ID__SHIFT = 0x0 # macro +SDMA1_ID__DEVICE_ID_MASK = 0x000000FF # macro +SDMA1_VERSION__MINVER__SHIFT = 0x0 # macro +SDMA1_VERSION__MAJVER__SHIFT = 0x8 # macro +SDMA1_VERSION__REV__SHIFT = 0x10 # macro +SDMA1_VERSION__MINVER_MASK = 0x0000007F # macro +SDMA1_VERSION__MAJVER_MASK = 0x00007F00 # macro +SDMA1_VERSION__REV_MASK = 0x003F0000 # macro +SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT = 0x0 # macro +SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT = 0x1 # macro +SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT = 0x2 # macro +SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT = 0x3 # macro +SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT = 0x4 # macro +SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT = 0x5 # macro +SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT = 0x6 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT = 0x7 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT = 0x8 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT = 0x9 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT = 0xa # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT = 0xb # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT = 0xc # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT = 0xd # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT = 0xe # macro +SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT = 0xf # macro +SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT = 0x10 # macro +SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK = 0x00000001 # macro +SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK = 0x00000002 # macro +SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK = 0x00000004 # macro +SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK = 0x00000008 # macro +SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK = 0x00000010 # macro +SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK = 0x00000020 # macro +SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK = 0x00000040 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK = 0x00000080 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK = 0x00000100 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK = 0x00000200 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK = 0x00000400 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK = 0x00000800 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK = 0x00001000 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK = 0x00002000 # macro +SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK = 0x00004000 # macro +SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK = 0x00008000 # macro +SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK = 0x00010000 # macro +SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT = 0x0 # macro +SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK = 0x00000001 # macro +SDMA1_STATUS2_REG__ID__SHIFT = 0x0 # macro +SDMA1_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT = 0x2 # macro +SDMA1_STATUS2_REG__CMD_OP__SHIFT = 0x10 # macro +SDMA1_STATUS2_REG__ID_MASK = 0x00000003 # macro +SDMA1_STATUS2_REG__TH0F32_INSTR_PTR_MASK = 0x0000FFFC # macro +SDMA1_STATUS2_REG__CMD_OP_MASK = 0xFFFF0000 # macro +SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT = 0x0 # macro +SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT = 0x1f # macro +SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK = 0x7FFFFFFF # macro +SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK = 0x80000000 # macro +SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT = 0x0 # macro +SDMA1_ATOMIC_PREOP_LO__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT = 0x0 # macro +SDMA1_ATOMIC_PREOP_HI__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT = 0x0 # macro +SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT = 0x5 # macro +SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT = 0x9 # macro +SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT = 0xe # macro +SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT = 0xf # macro +SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT = 0x10 # macro +SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT = 0x11 # macro +SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT = 0x12 # macro +SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT = 0x18 # macro +SDMA1_UTCL1_CNTL__REDO_DELAY_MASK = 0x0000001F # macro +SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK = 0x000001E0 # macro +SDMA1_UTCL1_CNTL__RESP_MODE_MASK = 0x00000600 # macro +SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK = 0x00004000 # macro +SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK = 0x00008000 # macro +SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK = 0x00010000 # macro +SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK = 0x00020000 # macro +SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK = 0x003C0000 # macro +SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK = 0x3F000000 # macro +SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT = 0x0 # macro +SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT = 0x4 # macro +SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT = 0x6 # macro +SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT = 0xa # macro +SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT = 0xc # macro +SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT = 0x10 # macro +SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT = 0x12 # macro +SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT = 0x16 # macro +SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK = 0x0000000F # macro +SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK = 0x00000030 # macro +SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK = 0x000003C0 # macro +SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK = 0x00000C00 # macro +SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK = 0x0000F000 # macro +SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK = 0x00030000 # macro +SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK = 0x003C0000 # macro +SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK = 0x00C00000 # macro +SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT = 0x0 # macro +SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT_MASK = 0x0000FFFF # macro +SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT = 0x0 # macro +SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT = 0x1 # macro +SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT = 0x6 # macro +SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT = 0xa # macro +SDMA1_UTCL1_PAGE__USE_IO__SHIFT = 0xb # macro +SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT = 0xc # macro +SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT = 0xe # macro +SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT = 0x10 # macro +SDMA1_UTCL1_PAGE__USE_BC__SHIFT = 0x16 # macro +SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT = 0x17 # macro +SDMA1_UTCL1_PAGE__LLC_NOALLOC__SHIFT = 0x18 # macro +SDMA1_UTCL1_PAGE__VM_HOLE_MASK = 0x00000001 # macro +SDMA1_UTCL1_PAGE__REQ_TYPE_MASK = 0x0000001E # macro +SDMA1_UTCL1_PAGE__USE_MTYPE_MASK = 0x000003C0 # macro +SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK = 0x00000400 # macro +SDMA1_UTCL1_PAGE__USE_IO_MASK = 0x00000800 # macro +SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK = 0x00003000 # macro +SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK = 0x0000C000 # macro +SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK = 0x003F0000 # macro +SDMA1_UTCL1_PAGE__USE_BC_MASK = 0x00400000 # macro +SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK = 0x00800000 # macro +SDMA1_UTCL1_PAGE__LLC_NOALLOC_MASK = 0x01000000 # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT = 0x0 # macro +SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT = 0x1 # macro +SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT = 0x2 # macro +SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT = 0x3 # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT = 0x4 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED0__SHIFT = 0x5 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED1__SHIFT = 0x6 # macro +SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT = 0x7 # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT = 0x8 # macro +SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT = 0x9 # macro +SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT = 0xa # macro +SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT = 0xb # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT = 0xc # macro +SDMA1_UTCL1_RD_STATUS__RESERVED2__SHIFT = 0xd # macro +SDMA1_UTCL1_RD_STATUS__RESERVED3__SHIFT = 0xe # macro +SDMA1_UTCL1_RD_STATUS__META_Q_FULL__SHIFT = 0xf # macro +SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT = 0x10 # macro +SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT = 0x11 # macro +SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT = 0x12 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT = 0x13 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT = 0x15 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT = 0x16 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT = 0x17 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT = 0x18 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT = 0x19 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED4__SHIFT = 0x1a # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT = 0x1b # macro +SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT = 0x1c # macro +SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT = 0x1d # macro +SDMA1_UTCL1_RD_STATUS__INV_BUSY__SHIFT = 0x1e # macro +SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT = 0x1f # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK = 0x00000001 # macro +SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK = 0x00000002 # macro +SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK = 0x00000004 # macro +SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK = 0x00000008 # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK = 0x00000010 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED0_MASK = 0x00000020 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED1_MASK = 0x00000040 # macro +SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY_MASK = 0x00000080 # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK = 0x00000100 # macro +SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK = 0x00000200 # macro +SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK = 0x00000400 # macro +SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK = 0x00000800 # macro +SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK = 0x00001000 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED2_MASK = 0x00002000 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED3_MASK = 0x00004000 # macro +SDMA1_UTCL1_RD_STATUS__META_Q_FULL_MASK = 0x00008000 # macro +SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK = 0x00010000 # macro +SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK = 0x00020000 # macro +SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK = 0x00040000 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK = 0x00180000 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK = 0x00200000 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK = 0x00400000 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK = 0x00800000 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK = 0x01000000 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK = 0x02000000 # macro +SDMA1_UTCL1_RD_STATUS__RESERVED4_MASK = 0x04000000 # macro +SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK = 0x08000000 # macro +SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK = 0x10000000 # macro +SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK = 0x20000000 # macro +SDMA1_UTCL1_RD_STATUS__INV_BUSY_MASK = 0x40000000 # macro +SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK = 0x80000000 # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT = 0x0 # macro +SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT = 0x1 # macro +SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT = 0x2 # macro +SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT = 0x3 # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT = 0x4 # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT = 0x5 # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT = 0x6 # macro +SDMA1_UTCL1_WR_STATUS__RESERVED0__SHIFT = 0x7 # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT = 0x8 # macro +SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT = 0x9 # macro +SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT = 0xa # macro +SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT = 0xb # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT = 0xc # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT = 0xd # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT = 0xe # macro +SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT = 0xf # macro +SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT = 0x10 # macro +SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT = 0x11 # macro +SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT = 0x12 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT = 0x13 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT = 0x15 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT = 0x16 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT = 0x17 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT = 0x18 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT = 0x19 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT = 0x1a # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT = 0x1b # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT = 0x1c # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT = 0x1d # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT = 0x1e # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT = 0x1f # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK = 0x00000001 # macro +SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK = 0x00000002 # macro +SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK = 0x00000004 # macro +SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK = 0x00000008 # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK = 0x00000010 # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK = 0x00000020 # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK = 0x00000040 # macro +SDMA1_UTCL1_WR_STATUS__RESERVED0_MASK = 0x00000080 # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK = 0x00000100 # macro +SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK = 0x00000200 # macro +SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK = 0x00000400 # macro +SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK = 0x00000800 # macro +SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK = 0x00001000 # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK = 0x00002000 # macro +SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK = 0x00004000 # macro +SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK = 0x00008000 # macro +SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK = 0x00010000 # macro +SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK = 0x00020000 # macro +SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK = 0x00040000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK = 0x00180000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK = 0x00200000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK = 0x00400000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK = 0x00800000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK = 0x01000000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK = 0x02000000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK = 0x04000000 # macro +SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK = 0x08000000 # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK = 0x10000000 # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK = 0x20000000 # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK = 0x40000000 # macro +SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK = 0x80000000 # macro +SDMA1_UTCL1_INV0__INV_PROC_BUSY__SHIFT = 0x0 # macro +SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT = 0x1 # macro +SDMA1_UTCL1_INV0__GPUVM_VMID__SHIFT = 0x7 # macro +SDMA1_UTCL1_INV0__GPUVM_MODE__SHIFT = 0xb # macro +SDMA1_UTCL1_INV0__GPUVM_HIGH__SHIFT = 0xd # macro +SDMA1_UTCL1_INV0__GPUVM_TAG__SHIFT = 0xe # macro +SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT = 0x12 # macro +SDMA1_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT = 0x16 # macro +SDMA1_UTCL1_INV0__INV_TYPE__SHIFT = 0x1a # macro +SDMA1_UTCL1_INV0__INV_PROC_BUSY_MASK = 0x00000001 # macro +SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK = 0x0000007E # macro +SDMA1_UTCL1_INV0__GPUVM_VMID_MASK = 0x00000780 # macro +SDMA1_UTCL1_INV0__GPUVM_MODE_MASK = 0x00001800 # macro +SDMA1_UTCL1_INV0__GPUVM_HIGH_MASK = 0x00002000 # macro +SDMA1_UTCL1_INV0__GPUVM_TAG_MASK = 0x0003C000 # macro +SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH_MASK = 0x003C0000 # macro +SDMA1_UTCL1_INV0__GPUVM_VMID_LOW_MASK = 0x03C00000 # macro +SDMA1_UTCL1_INV0__INV_TYPE_MASK = 0x0C000000 # macro +SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT = 0x0 # macro +SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK = 0xFFFFFFFF # macro +SDMA1_UTCL1_INV2__CPF_VMID__SHIFT = 0x0 # macro +SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT = 0x10 # macro +SDMA1_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT = 0x11 # macro +SDMA1_UTCL1_INV2__CPF_VMID_MASK = 0x0000FFFF # macro +SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE_MASK = 0x00010000 # macro +SDMA1_UTCL1_INV2__CPF_FRAG_SIZE_MASK = 0x007E0000 # macro +SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT = 0x0 # macro +SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK = 0xFFFFFFFF # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT = 0x0 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT = 0x4 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT = 0x8 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT = 0xa # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT = 0xc # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT = 0xe # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT = 0xf # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT = 0x10 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK = 0x0000000F # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK = 0x000000F0 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK = 0x00000300 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK = 0x00000C00 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK = 0x00003000 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK = 0x00004000 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK = 0x00008000 # macro +SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK = 0x00010000 # macro +SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT = 0x0 # macro +SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK = 0xFFFFFFFF # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT = 0x0 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT = 0x4 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT = 0x8 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT = 0xa # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT = 0xc # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT = 0xe # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT = 0xf # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT = 0x10 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK = 0x0000000F # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK = 0x000000F0 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK = 0x00000300 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK = 0x00000C00 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK = 0x00003000 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK = 0x00004000 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK = 0x00008000 # macro +SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK = 0x00010000 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT = 0x0 # macro +SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT = 0x1 # macro +SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT = 0x2 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT = 0x3 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT = 0x4 # macro +SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT = 0x5 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT = 0x6 # macro +SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT = 0x8 # macro +SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT = 0x9 # macro +SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT = 0xa # macro +SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT = 0xb # macro +SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT = 0xc # macro +SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT = 0xd # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT = 0xe # macro +SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT = 0x1b # macro +SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT = 0x1c # macro +SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT = 0x1d # macro +SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT = 0x1e # macro +SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT = 0x1f # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK = 0x00000001 # macro +SDMA1_RELAX_ORDERING_LUT__COPY_MASK = 0x00000002 # macro +SDMA1_RELAX_ORDERING_LUT__WRITE_MASK = 0x00000004 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK = 0x00000008 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK = 0x00000010 # macro +SDMA1_RELAX_ORDERING_LUT__FENCE_MASK = 0x00000020 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK = 0x000000C0 # macro +SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK = 0x00000100 # macro +SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK = 0x00000200 # macro +SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK = 0x00000400 # macro +SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK = 0x00000800 # macro +SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK = 0x00001000 # macro +SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK = 0x00002000 # macro +SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK = 0x07FFC000 # macro +SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK = 0x08000000 # macro +SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK = 0x10000000 # macro +SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK = 0x20000000 # macro +SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK = 0x40000000 # macro +SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK = 0x80000000 # macro +SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT = 0x0 # macro +SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT = 0x4 # macro +SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT = 0x6 # macro +SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT = 0x7 # macro +SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT = 0x8 # macro +SDMA1_CHICKEN_BITS_2__RESERVED_14_12__SHIFT = 0xc # macro +SDMA1_CHICKEN_BITS_2__RESERVED_15__SHIFT = 0xf # macro +SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT = 0x10 # macro +SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT = 0x12 # macro +SDMA1_CHICKEN_BITS_2__RESERVED_22_20__SHIFT = 0x14 # macro +SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT = 0x17 # macro +SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT = 0x19 # macro +SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT = 0x1e # macro +SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT = 0x1f # macro +SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK = 0x0000000F # macro +SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK = 0x00000010 # macro +SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK = 0x00000040 # macro +SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK = 0x00000080 # macro +SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK = 0x00000F00 # macro +SDMA1_CHICKEN_BITS_2__RESERVED_14_12_MASK = 0x00007000 # macro +SDMA1_CHICKEN_BITS_2__RESERVED_15_MASK = 0x00008000 # macro +SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK = 0x00030000 # macro +SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK = 0x000C0000 # macro +SDMA1_CHICKEN_BITS_2__RESERVED_22_20_MASK = 0x00700000 # macro +SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK = 0x01800000 # macro +SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK = 0x3E000000 # macro +SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK = 0x40000000 # macro +SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK = 0x80000000 # macro +SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT = 0x0 # macro +SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT = 0x10 # macro +SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT = 0x14 # macro +SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT = 0x15 # macro +SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT = 0x16 # macro +SDMA1_STATUS3_REG__GCR_IDLE__SHIFT = 0x17 # macro +SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT = 0x18 # macro +SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT = 0x19 # macro +SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT = 0x1a # macro +SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT = 0x1e # macro +SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK = 0x0000FFFF # macro +SDMA1_STATUS3_REG__PREV_VM_CMD_MASK = 0x000F0000 # macro +SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK = 0x00100000 # macro +SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK = 0x00200000 # macro +SDMA1_STATUS3_REG__TLBI_IDLE_MASK = 0x00400000 # macro +SDMA1_STATUS3_REG__GCR_IDLE_MASK = 0x00800000 # macro +SDMA1_STATUS3_REG__INVREQ_IDLE_MASK = 0x01000000 # macro +SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK = 0x02000000 # macro +SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK = 0x3C000000 # macro +SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS_MASK = 0xC0000000 # macro +SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT = 0x0 # macro +SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT = 0x1 # macro +SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT = 0x2 # macro +SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT = 0xc # macro +SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK = 0x00000001 # macro +SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK = 0x00000002 # macro +SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK = 0x00000004 # macro +SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK = 0xFFFFF000 # macro +SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK = 0x0000FFFF # macro +SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT = 0x0 # macro +SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT = 0x8 # macro +SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK = 0x000000FF # macro +SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_ERROR_LOG__OVERRIDE__SHIFT = 0x0 # macro +SDMA1_ERROR_LOG__STATUS__SHIFT = 0x10 # macro +SDMA1_ERROR_LOG__OVERRIDE_MASK = 0x0000FFFF # macro +SDMA1_ERROR_LOG__STATUS_MASK = 0xFFFF0000 # macro +SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT = 0x0 # macro +SDMA1_PUB_DUMMY_REG0__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT = 0x0 # macro +SDMA1_PUB_DUMMY_REG1__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT = 0x0 # macro +SDMA1_PUB_DUMMY_REG2__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT = 0x0 # macro +SDMA1_PUB_DUMMY_REG3__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_F32_COUNTER__VALUE__SHIFT = 0x0 # macro +SDMA1_F32_COUNTER__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT = 0x7 # macro +SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT = 0xd # macro +SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT = 0x13 # macro +SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT = 0x19 # macro +SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK = 0x00001F80 # macro +SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK = 0x0007E000 # macro +SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK = 0x01F80000 # macro +SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK = 0x7E000000 # macro +SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT = 0x1 # macro +SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT = 0x10 # macro +SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK = 0x00000002 # macro +SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK = 0xFFFF0000 # macro +SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT = 0x0 # macro +SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT = 0x1 # macro +SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK = 0x00000001 # macro +SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK = 0x00000002 # macro +SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT = 0x0 # macro +SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT = 0x0 # macro +SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK = 0x00000007 # macro +SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT = 0x0 # macro +SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT = 0x4 # macro +SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT = 0x8 # macro +SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT = 0x10 # macro +SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT = 0x18 # macro +SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK = 0x0000000F # macro +SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK = 0x000000F0 # macro +SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK = 0x00000F00 # macro +SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK = 0x00FF0000 # macro +SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK = 0xFF000000 # macro +SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT = 0x4 # macro +SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK = 0x00000070 # macro +SDMA1_INT_STATUS__DATA__SHIFT = 0x0 # macro +SDMA1_INT_STATUS__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_HOLE_ADDR_LO__VALUE__SHIFT = 0x0 # macro +SDMA1_HOLE_ADDR_LO__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_HOLE_ADDR_HI__VALUE__SHIFT = 0x0 # macro +SDMA1_HOLE_ADDR_HI__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT = 0x0 # macro +SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT = 0x2 # macro +SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT = 0x3 # macro +SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT = 0x4 # macro +SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT = 0x5 # macro +SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT = 0x6 # macro +SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK = 0x00000001 # macro +SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK = 0x00000004 # macro +SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK = 0x00000008 # macro +SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK = 0x00000010 # macro +SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK = 0x00000020 # macro +SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK = 0x00000040 # macro +SDMA1_STATUS4_REG__IDLE__SHIFT = 0x0 # macro +SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT = 0x2 # macro +SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT = 0x3 # macro +SDMA1_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT = 0x4 # macro +SDMA1_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT = 0x5 # macro +SDMA1_STATUS4_REG__GCR_OUTSTANDING__SHIFT = 0x6 # macro +SDMA1_STATUS4_REG__TLBI_OUTSTANDING__SHIFT = 0x7 # macro +SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT = 0x8 # macro +SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT = 0x9 # macro +SDMA1_STATUS4_REG__REG_POLLING__SHIFT = 0xa # macro +SDMA1_STATUS4_REG__MEM_POLLING__SHIFT = 0xb # macro +SDMA1_STATUS4_REG__RESERVED_13_12__SHIFT = 0xc # macro +SDMA1_STATUS4_REG__RESERVED_15_14__SHIFT = 0xe # macro +SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT = 0x10 # macro +SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT = 0x14 # macro +SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT = 0x15 # macro +SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT = 0x16 # macro +SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT = 0x17 # macro +SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT = 0x18 # macro +SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT = 0x19 # macro +SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT = 0x1a # macro +SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT = 0x1b # macro +SDMA1_STATUS4_REG__IDLE_MASK = 0x00000001 # macro +SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK = 0x00000004 # macro +SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK = 0x00000008 # macro +SDMA1_STATUS4_REG__CH_RD_OUTSTANDING_MASK = 0x00000010 # macro +SDMA1_STATUS4_REG__CH_WR_OUTSTANDING_MASK = 0x00000020 # macro +SDMA1_STATUS4_REG__GCR_OUTSTANDING_MASK = 0x00000040 # macro +SDMA1_STATUS4_REG__TLBI_OUTSTANDING_MASK = 0x00000080 # macro +SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK = 0x00000100 # macro +SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK = 0x00000200 # macro +SDMA1_STATUS4_REG__REG_POLLING_MASK = 0x00000400 # macro +SDMA1_STATUS4_REG__MEM_POLLING_MASK = 0x00000800 # macro +SDMA1_STATUS4_REG__RESERVED_13_12_MASK = 0x00003000 # macro +SDMA1_STATUS4_REG__RESERVED_15_14_MASK = 0x0000C000 # macro +SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK = 0x000F0000 # macro +SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK = 0x00100000 # macro +SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK = 0x00200000 # macro +SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK = 0x00400000 # macro +SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK = 0x00800000 # macro +SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK = 0x01000000 # macro +SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK = 0x02000000 # macro +SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK = 0x04000000 # macro +SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK = 0x08000000 # macro +SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT = 0x0 # macro +SDMA1_SCRATCH_RAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT = 0x0 # macro +SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK = 0x0000007F # macro +SDMA1_TIMESTAMP_CNTL__CAPTURE__SHIFT = 0x0 # macro +SDMA1_TIMESTAMP_CNTL__CAPTURE_MASK = 0x00000001 # macro +SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT = 0x0 # macro +SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT = 0x1 # macro +SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT = 0x2 # macro +SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT = 0x3 # macro +SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT = 0x4 # macro +SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT = 0x5 # macro +SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT = 0x6 # macro +SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT = 0x7 # macro +SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT = 0x10 # macro +SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x14 # macro +SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x15 # macro +SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x16 # macro +SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x17 # macro +SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x18 # macro +SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x19 # macro +SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x1a # macro +SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT = 0x1b # macro +SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK = 0x00000001 # macro +SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK = 0x00000002 # macro +SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK = 0x00000004 # macro +SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK = 0x00000008 # macro +SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK = 0x00000010 # macro +SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK = 0x00000020 # macro +SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK = 0x00000040 # macro +SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK = 0x00000080 # macro +SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID_MASK = 0x000F0000 # macro +SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00100000 # macro +SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00200000 # macro +SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00400000 # macro +SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x00800000 # macro +SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x01000000 # macro +SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x02000000 # macro +SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x04000000 # macro +SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK = 0x08000000 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT = 0x0 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT = 0x1 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT = 0x2 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT = 0x3 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT = 0x4 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT = 0x5 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT = 0x6 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT = 0x7 # macro +SDMA1_QUEUE_RESET_REQ__RESERVED__SHIFT = 0x8 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET_MASK = 0x00000001 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET_MASK = 0x00000002 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET_MASK = 0x00000004 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET_MASK = 0x00000008 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET_MASK = 0x00000010 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET_MASK = 0x00000020 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET_MASK = 0x00000040 # macro +SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET_MASK = 0x00000080 # macro +SDMA1_QUEUE_RESET_REQ__RESERVED_MASK = 0xFFFFFF00 # macro +SDMA1_STATUS6_REG__ID__SHIFT = 0x0 # macro +SDMA1_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT = 0x2 # macro +SDMA1_STATUS6_REG__TH1_EXCEPTION__SHIFT = 0x10 # macro +SDMA1_STATUS6_REG__ID_MASK = 0x00000003 # macro +SDMA1_STATUS6_REG__TH1F32_INSTR_PTR_MASK = 0x0000FFFC # macro +SDMA1_STATUS6_REG__TH1_EXCEPTION_MASK = 0xFFFF0000 # macro +SDMA1_UCODE1_CHECKSUM__DATA__SHIFT = 0x0 # macro +SDMA1_UCODE1_CHECKSUM__DATA_MASK = 0xFFFFFFFF # macro +SDMA1_CE_CTRL__RD_LUT_WATERMARK__SHIFT = 0x0 # macro +SDMA1_CE_CTRL__RD_LUT_DEPTH__SHIFT = 0x3 # macro +SDMA1_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT = 0x5 # macro +SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT = 0x8 # macro +SDMA1_CE_CTRL__RESERVED__SHIFT = 0x9 # macro +SDMA1_CE_CTRL__RD_LUT_WATERMARK_MASK = 0x00000007 # macro +SDMA1_CE_CTRL__RD_LUT_DEPTH_MASK = 0x00000018 # macro +SDMA1_CE_CTRL__WR_AFIFO_WATERMARK_MASK = 0x000000E0 # macro +SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK = 0x00000100 # macro +SDMA1_CE_CTRL__RESERVED_MASK = 0xFFFFFE00 # macro +SDMA1_FED_STATUS__RB_FETCH_ECC__SHIFT = 0x0 # macro +SDMA1_FED_STATUS__IB_FETCH_ECC__SHIFT = 0x1 # macro +SDMA1_FED_STATUS__F32_DATA_ECC__SHIFT = 0x2 # macro +SDMA1_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT = 0x3 # macro +SDMA1_FED_STATUS__COPY_DATA_ECC__SHIFT = 0x4 # macro +SDMA1_FED_STATUS__COPY_METADATA_ECC__SHIFT = 0x5 # macro +SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT = 0x6 # macro +SDMA1_FED_STATUS__RB_FETCH_ECC_MASK = 0x00000001 # macro +SDMA1_FED_STATUS__IB_FETCH_ECC_MASK = 0x00000002 # macro +SDMA1_FED_STATUS__F32_DATA_ECC_MASK = 0x00000004 # macro +SDMA1_FED_STATUS__WPTR_ATOMIC_ECC_MASK = 0x00000008 # macro +SDMA1_FED_STATUS__COPY_DATA_ECC_MASK = 0x00000010 # macro +SDMA1_FED_STATUS__COPY_METADATA_ECC_MASK = 0x00000020 # macro +SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC_MASK = 0x00000040 # macro +SDMA1_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE0_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE0_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE0_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE0_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE0_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE0_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE0_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE0_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE0_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE0_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE0_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE0_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE0_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE0_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE0_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE0_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE0_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE0_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE0_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE0_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT = 0x1 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB_MASK = 0x00000002 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE0_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE0_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE0_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE0_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE0_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE0_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE0_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE0_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE0_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE0_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE0_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE1_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE1_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE1_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE1_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE1_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE1_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE1_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE1_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE1_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE1_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE1_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE1_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE1_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE1_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE1_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE1_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE1_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE1_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE1_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE1_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE1_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE1_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE1_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE1_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE1_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE1_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE1_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE1_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE1_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE1_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE1_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE2_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE2_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE2_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE2_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE2_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE2_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE2_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE2_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE2_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE2_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE2_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE2_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE2_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE2_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE2_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE2_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE2_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE2_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE2_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE2_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE2_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE2_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE2_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE2_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE2_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE2_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE2_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE2_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE2_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE2_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE2_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE3_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE3_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE3_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE3_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE3_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE3_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE3_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE3_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE3_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE3_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE3_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE3_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE3_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE3_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE3_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE3_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE3_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE3_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE3_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE3_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE3_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE3_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE3_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE3_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE3_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE3_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE3_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE3_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE3_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE3_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE3_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE4_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE4_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE4_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE4_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE4_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE4_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE4_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE4_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE4_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE4_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE4_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE4_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE4_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE4_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE4_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE4_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE4_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE4_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE4_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE4_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE4_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE4_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE4_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE4_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE4_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE4_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE4_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE4_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE4_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE4_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE4_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE5_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE5_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE5_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE5_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE5_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE5_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE5_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE5_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE5_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE5_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE5_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE5_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE5_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE5_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE5_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE5_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE5_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE5_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE5_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE5_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE5_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE5_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE5_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE5_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE5_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE5_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE5_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE5_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE5_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE5_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE5_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE6_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE6_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE6_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE6_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE6_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE6_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE6_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE6_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE6_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE6_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE6_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE6_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE6_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE6_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE6_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE6_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE6_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE6_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE6_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE6_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE6_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE6_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE6_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE6_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE6_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE6_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE6_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE6_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE6_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE6_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE6_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA1_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT = 0x8 # macro +SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT = 0x9 # macro +SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT = 0xa # macro +SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT = 0xb # macro +SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT = 0xc # macro +SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT = 0xd # macro +SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT = 0x10 # macro +SDMA1_QUEUE7_RB_CNTL__RB_PRIV__SHIFT = 0x17 # macro +SDMA1_QUEUE7_RB_CNTL__RB_VMID__SHIFT = 0x18 # macro +SDMA1_QUEUE7_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE7_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK = 0x00000100 # macro +SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK = 0x00000200 # macro +SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK = 0x00000800 # macro +SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK = 0x00001000 # macro +SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK = 0x00002000 # macro +SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK = 0x001F0000 # macro +SDMA1_QUEUE7_RB_CNTL__RB_PRIV_MASK = 0x00800000 # macro +SDMA1_QUEUE7_RB_CNTL__RB_VMID_MASK = 0x0F000000 # macro +SDMA1_QUEUE7_RB_BASE__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_BASE_HI__ADDR_MASK = 0x00FFFFFF # macro +SDMA1_QUEUE7_RB_RPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_RPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_RPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_WPTR__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_WPTR__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_WPTR_HI__OFFSET_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT = 0x4 # macro +SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT = 0x8 # macro +SDMA1_QUEUE7_IB_CNTL__CMD_VMID__SHIFT = 0x10 # macro +SDMA1_QUEUE7_IB_CNTL__IB_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK = 0x00000010 # macro +SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK = 0x00000100 # macro +SDMA1_QUEUE7_IB_CNTL__CMD_VMID_MASK = 0x000F0000 # macro +SDMA1_QUEUE7_IB_RPTR__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE7_IB_RPTR__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE7_IB_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE7_IB_OFFSET__OFFSET_MASK = 0x003FFFFC # macro +SDMA1_QUEUE7_IB_BASE_LO__ADDR__SHIFT = 0x5 # macro +SDMA1_QUEUE7_IB_BASE_LO__ADDR_MASK = 0xFFFFFFE0 # macro +SDMA1_QUEUE7_IB_BASE_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE7_IB_BASE_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_IB_SIZE__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE7_IB_SIZE__SIZE_MASK = 0x000FFFFF # macro +SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT = 0x0 # macro +SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK = 0x000FFFFF # macro +SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT = 0x0 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT = 0x2 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT = 0x3 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT = 0x4 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT = 0x7 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT = 0xa # macro +SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT = 0xb # macro +SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT = 0xc # macro +SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT = 0x10 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED_MASK = 0x00000001 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__IDLE_MASK = 0x00000004 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK = 0x00000008 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK = 0x00000070 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK = 0x00000080 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK = 0x00000400 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK = 0x00000800 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK = 0x00001000 # macro +SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK = 0x00FF0000 # macro +SDMA1_QUEUE7_DOORBELL__ENABLE__SHIFT = 0x1c # macro +SDMA1_QUEUE7_DOORBELL__CAPTURED__SHIFT = 0x1e # macro +SDMA1_QUEUE7_DOORBELL__ENABLE_MASK = 0x10000000 # macro +SDMA1_QUEUE7_DOORBELL__CAPTURED_MASK = 0x40000000 # macro +SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT = 0x0 # macro +SDMA1_QUEUE7_DOORBELL_LOG__DATA__SHIFT = 0x2 # macro +SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK = 0x00000001 # macro +SDMA1_QUEUE7_DOORBELL_LOG__DATA_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT = 0x2 # macro +SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK = 0x0FFFFFFC # macro +SDMA1_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE7_CSA_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE7_CSA_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT = 0x0 # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT = 0x2 # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT = 0x6 # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT = 0x8 # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK = 0x00000003 # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK = 0x0000001C # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK = 0x000000C0 # macro +SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK = 0x0000FF00 # macro +SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT = 0x0 # macro +SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE_MASK = 0x00003FFF # macro +SDMA1_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT = 0x0 # macro +SDMA1_QUEUE7_PREEMPT__IB_PREEMPT_MASK = 0x00000001 # macro +SDMA1_QUEUE7_DUMMY_REG__DUMMY__SHIFT = 0x0 # macro +SDMA1_QUEUE7_DUMMY_REG__DUMMY_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT = 0x2 # macro +SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT = 0x1 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT = 0x8 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT = 0x10 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT = 0x11 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT = 0x12 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK = 0x000000FE # macro +SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK = 0x0000FF00 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK = 0x00010000 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK = 0x00020000 # macro +SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK = 0x00040000 # macro +SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK = 0x00000001 # macro +SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT = 0x0 # macro +SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK = 0x00000001 # macro +SDMA1_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA0__DATA0_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA1__DATA1_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA2__DATA2_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA3__DATA3_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA4__DATA4_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA5__DATA5_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA6__DATA6_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA7__DATA7_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA8__DATA8_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA9__DATA9_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_DATA10__DATA10_MASK = 0xFFFFFFFF # macro +SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT = 0x0 # macro +SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT = 0x1 # macro +SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT = 0x4 # macro +SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT = 0x8 # macro +SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK = 0x00000001 # macro +SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK = 0x00000002 # macro +SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK = 0x000000F0 # macro +SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK = 0x00000100 # macro +SDMA0_UCODE_ADDR__VALUE__SHIFT = 0x0 # macro +SDMA0_UCODE_ADDR__THID__SHIFT = 0xf # macro +SDMA0_UCODE_ADDR__VALUE_MASK = 0x00001FFF # macro +SDMA0_UCODE_ADDR__THID_MASK = 0x00008000 # macro +SDMA0_UCODE_DATA__VALUE__SHIFT = 0x0 # macro +SDMA0_UCODE_DATA__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_BROADCAST_UCODE_ADDR__VALUE__SHIFT = 0x0 # macro +SDMA0_BROADCAST_UCODE_ADDR__THID__SHIFT = 0xf # macro +SDMA0_BROADCAST_UCODE_ADDR__VALUE_MASK = 0x00001FFF # macro +SDMA0_BROADCAST_UCODE_ADDR__THID_MASK = 0x00008000 # macro +SDMA0_BROADCAST_UCODE_DATA__VALUE__SHIFT = 0x0 # macro +SDMA0_BROADCAST_UCODE_DATA__VALUE_MASK = 0xFFFFFFFF # macro +SDMA0_F32_CNTL__HALT__SHIFT = 0x0 # macro +SDMA0_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT = 0x8 # macro +SDMA0_F32_CNTL__TH0_RESET__SHIFT = 0x9 # macro +SDMA0_F32_CNTL__TH0_ENABLE__SHIFT = 0xa # macro +SDMA0_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT = 0xc # macro +SDMA0_F32_CNTL__TH1_RESET__SHIFT = 0xd # macro +SDMA0_F32_CNTL__TH1_ENABLE__SHIFT = 0xe # macro +SDMA0_F32_CNTL__TH0_PRIORITY__SHIFT = 0x10 # macro +SDMA0_F32_CNTL__TH1_PRIORITY__SHIFT = 0x18 # macro +SDMA0_F32_CNTL__HALT_MASK = 0x00000001 # macro +SDMA0_F32_CNTL__TH0_CHECKSUM_CLR_MASK = 0x00000100 # macro +SDMA0_F32_CNTL__TH0_RESET_MASK = 0x00000200 # macro +SDMA0_F32_CNTL__TH0_ENABLE_MASK = 0x00000400 # macro +SDMA0_F32_CNTL__TH1_CHECKSUM_CLR_MASK = 0x00001000 # macro +SDMA0_F32_CNTL__TH1_RESET_MASK = 0x00002000 # macro +SDMA0_F32_CNTL__TH1_ENABLE_MASK = 0x00004000 # macro +SDMA0_F32_CNTL__TH0_PRIORITY_MASK = 0x00FF0000 # macro +SDMA0_F32_CNTL__TH1_PRIORITY_MASK = 0xFF000000 # macro +SDMA1_UCODE_ADDR__VALUE__SHIFT = 0x0 # macro +SDMA1_UCODE_ADDR__THID__SHIFT = 0xf # macro +SDMA1_UCODE_ADDR__VALUE_MASK = 0x00001FFF # macro +SDMA1_UCODE_ADDR__THID_MASK = 0x00008000 # macro +SDMA1_UCODE_DATA__VALUE__SHIFT = 0x0 # macro +SDMA1_UCODE_DATA__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_BROADCAST_UCODE_ADDR__VALUE__SHIFT = 0x0 # macro +SDMA1_BROADCAST_UCODE_ADDR__THID__SHIFT = 0xf # macro +SDMA1_BROADCAST_UCODE_ADDR__VALUE_MASK = 0x00001FFF # macro +SDMA1_BROADCAST_UCODE_ADDR__THID_MASK = 0x00008000 # macro +SDMA1_BROADCAST_UCODE_DATA__VALUE__SHIFT = 0x0 # macro +SDMA1_BROADCAST_UCODE_DATA__VALUE_MASK = 0xFFFFFFFF # macro +SDMA1_F32_CNTL__HALT__SHIFT = 0x0 # macro +SDMA1_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT = 0x8 # macro +SDMA1_F32_CNTL__TH0_RESET__SHIFT = 0x9 # macro +SDMA1_F32_CNTL__TH0_ENABLE__SHIFT = 0xa # macro +SDMA1_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT = 0xc # macro +SDMA1_F32_CNTL__TH1_RESET__SHIFT = 0xd # macro +SDMA1_F32_CNTL__TH1_ENABLE__SHIFT = 0xe # macro +SDMA1_F32_CNTL__TH0_PRIORITY__SHIFT = 0x10 # macro +SDMA1_F32_CNTL__TH1_PRIORITY__SHIFT = 0x18 # macro +SDMA1_F32_CNTL__HALT_MASK = 0x00000001 # macro +SDMA1_F32_CNTL__TH0_CHECKSUM_CLR_MASK = 0x00000100 # macro +SDMA1_F32_CNTL__TH0_RESET_MASK = 0x00000200 # macro +SDMA1_F32_CNTL__TH0_ENABLE_MASK = 0x00000400 # macro +SDMA1_F32_CNTL__TH1_CHECKSUM_CLR_MASK = 0x00001000 # macro +SDMA1_F32_CNTL__TH1_RESET_MASK = 0x00002000 # macro +SDMA1_F32_CNTL__TH1_ENABLE_MASK = 0x00004000 # macro +SDMA1_F32_CNTL__TH0_PRIORITY_MASK = 0x00FF0000 # macro +SDMA1_F32_CNTL__TH1_PRIORITY_MASK = 0xFF000000 # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT = 0x0 # macro +SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK = 0x0000FFFF # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT = 0x0 # macro +SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK = 0x0000FFFF # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_CNTL__READ_TIMEOUT__SHIFT = 0x0 # macro +GRBM_CNTL__REPORT_LAST_RDERR__SHIFT = 0x1f # macro +GRBM_CNTL__READ_TIMEOUT_MASK = 0x000000FF # macro +GRBM_CNTL__REPORT_LAST_RDERR_MASK = 0x80000000 # macro +GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT = 0x0 # macro +GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT = 0x6 # macro +GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK = 0x0000003F # macro +GRBM_SKEW_CNTL__SKEW_COUNT_MASK = 0x00000FC0 # macro +GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT = 0x0 # macro +GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT = 0x4 # macro +GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT = 0x5 # macro +GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT = 0x6 # macro +GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT = 0x7 # macro +GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT = 0x8 # macro +GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT = 0x9 # macro +GRBM_STATUS2__RLC_RQ_PENDING__SHIFT = 0xe # macro +GRBM_STATUS2__UTCL2_BUSY__SHIFT = 0xf # macro +GRBM_STATUS2__EA_BUSY__SHIFT = 0x10 # macro +GRBM_STATUS2__RMI_BUSY__SHIFT = 0x11 # macro +GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT = 0x12 # macro +GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT = 0x13 # macro +GRBM_STATUS2__EA_LINK_BUSY__SHIFT = 0x14 # macro +GRBM_STATUS2__SDMA_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT = 0x16 # macro +GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT = 0x17 # macro +GRBM_STATUS2__RLC_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS2__TCP_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS2__CPF_BUSY__SHIFT = 0x1c # macro +GRBM_STATUS2__CPC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS2__CPG_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK = 0x0000000F # macro +GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK = 0x00000010 # macro +GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK = 0x00000020 # macro +GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK = 0x00000040 # macro +GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK = 0x00000080 # macro +GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK = 0x00000100 # macro +GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK = 0x00000200 # macro +GRBM_STATUS2__RLC_RQ_PENDING_MASK = 0x00004000 # macro +GRBM_STATUS2__UTCL2_BUSY_MASK = 0x00008000 # macro +GRBM_STATUS2__EA_BUSY_MASK = 0x00010000 # macro +GRBM_STATUS2__RMI_BUSY_MASK = 0x00020000 # macro +GRBM_STATUS2__UTCL2_RQ_PENDING_MASK = 0x00040000 # macro +GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK = 0x00080000 # macro +GRBM_STATUS2__EA_LINK_BUSY_MASK = 0x00100000 # macro +GRBM_STATUS2__SDMA_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS2__SDMA0_RQ_PENDING_MASK = 0x00400000 # macro +GRBM_STATUS2__SDMA1_RQ_PENDING_MASK = 0x00800000 # macro +GRBM_STATUS2__RLC_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS2__TCP_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS2__CPF_BUSY_MASK = 0x10000000 # macro +GRBM_STATUS2__CPC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS2__CPG_BUSY_MASK = 0x40000000 # macro +GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT = 0x0 # macro +GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT = 0x2 # macro +GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT = 0x4 # macro +GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT = 0x6 # macro +GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT = 0xe # macro +GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT = 0xf # macro +GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK = 0x00000003 # macro +GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK = 0x0000000C # macro +GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK = 0x00000030 # macro +GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK = 0x000000C0 # macro +GRBM_PWR_CNTL__GFX_REQ_EN_MASK = 0x00004000 # macro +GRBM_PWR_CNTL__ALL_REQ_EN_MASK = 0x00008000 # macro +GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT = 0x0 # macro +GRBM_STATUS__SDMA_RQ_PENDING__SHIFT = 0x6 # macro +GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT = 0x7 # macro +GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT = 0x8 # macro +GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT = 0x9 # macro +GRBM_STATUS__DB_CLEAN__SHIFT = 0xc # macro +GRBM_STATUS__CB_CLEAN__SHIFT = 0xd # macro +GRBM_STATUS__TA_BUSY__SHIFT = 0xe # macro +GRBM_STATUS__GDS_BUSY__SHIFT = 0xf # macro +GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT = 0x10 # macro +GRBM_STATUS__SX_BUSY__SHIFT = 0x14 # macro +GRBM_STATUS__GE_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS__SPI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS__BCI_BUSY__SHIFT = 0x17 # macro +GRBM_STATUS__SC_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS__PA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS__DB_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS__ANY_ACTIVE__SHIFT = 0x1b # macro +GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT = 0x1c # macro +GRBM_STATUS__CP_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS__CB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS__GUI_ACTIVE__SHIFT = 0x1f # macro +GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK = 0x0000000F # macro +GRBM_STATUS__SDMA_RQ_PENDING_MASK = 0x00000040 # macro +GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK = 0x00000080 # macro +GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK = 0x00000100 # macro +GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK = 0x00000200 # macro +GRBM_STATUS__DB_CLEAN_MASK = 0x00001000 # macro +GRBM_STATUS__CB_CLEAN_MASK = 0x00002000 # macro +GRBM_STATUS__TA_BUSY_MASK = 0x00004000 # macro +GRBM_STATUS__GDS_BUSY_MASK = 0x00008000 # macro +GRBM_STATUS__GE_BUSY_NO_DMA_MASK = 0x00010000 # macro +GRBM_STATUS__SX_BUSY_MASK = 0x00100000 # macro +GRBM_STATUS__GE_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS__SPI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS__BCI_BUSY_MASK = 0x00800000 # macro +GRBM_STATUS__SC_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS__PA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS__DB_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS__ANY_ACTIVE_MASK = 0x08000000 # macro +GRBM_STATUS__CP_COHERENCY_BUSY_MASK = 0x10000000 # macro +GRBM_STATUS__CP_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS__CB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS__GUI_ACTIVE_MASK = 0x80000000 # macro +GRBM_STATUS_SE0__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE0__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT = 0x3 # macro +GRBM_STATUS_SE0__TCP_BUSY__SHIFT = 0x4 # macro +GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT = 0x5 # macro +GRBM_STATUS_SE0__GL1H_BUSY__SHIFT = 0x6 # macro +GRBM_STATUS_SE0__PC_BUSY__SHIFT = 0x7 # macro +GRBM_STATUS_SE0__SEDC_BUSY__SHIFT = 0x8 # macro +GRBM_STATUS_SE0__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE0__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE0__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE0__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE0__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE0__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE0__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE0__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE0__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE0__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE0__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE0__UTCL1_BUSY_MASK = 0x00000008 # macro +GRBM_STATUS_SE0__TCP_BUSY_MASK = 0x00000010 # macro +GRBM_STATUS_SE0__GL1CC_BUSY_MASK = 0x00000020 # macro +GRBM_STATUS_SE0__GL1H_BUSY_MASK = 0x00000040 # macro +GRBM_STATUS_SE0__PC_BUSY_MASK = 0x00000080 # macro +GRBM_STATUS_SE0__SEDC_BUSY_MASK = 0x00000100 # macro +GRBM_STATUS_SE0__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE0__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE0__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE0__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE0__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE0__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE0__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE0__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE0__CB_BUSY_MASK = 0x80000000 # macro +GRBM_STATUS_SE1__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE1__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT = 0x3 # macro +GRBM_STATUS_SE1__TCP_BUSY__SHIFT = 0x4 # macro +GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT = 0x5 # macro +GRBM_STATUS_SE1__GL1H_BUSY__SHIFT = 0x6 # macro +GRBM_STATUS_SE1__PC_BUSY__SHIFT = 0x7 # macro +GRBM_STATUS_SE1__SEDC_BUSY__SHIFT = 0x8 # macro +GRBM_STATUS_SE1__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE1__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE1__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE1__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE1__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE1__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE1__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE1__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE1__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE1__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE1__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE1__UTCL1_BUSY_MASK = 0x00000008 # macro +GRBM_STATUS_SE1__TCP_BUSY_MASK = 0x00000010 # macro +GRBM_STATUS_SE1__GL1CC_BUSY_MASK = 0x00000020 # macro +GRBM_STATUS_SE1__GL1H_BUSY_MASK = 0x00000040 # macro +GRBM_STATUS_SE1__PC_BUSY_MASK = 0x00000080 # macro +GRBM_STATUS_SE1__SEDC_BUSY_MASK = 0x00000100 # macro +GRBM_STATUS_SE1__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE1__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE1__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE1__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE1__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE1__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE1__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE1__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE1__CB_BUSY_MASK = 0x80000000 # macro +GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT = 0x5 # macro +GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT = 0x7 # macro +GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT = 0x8 # macro +GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT = 0x9 # macro +GRBM_STATUS3__PH_BUSY__SHIFT = 0xd # macro +GRBM_STATUS3__CH_BUSY__SHIFT = 0xe # macro +GRBM_STATUS3__GL2CC_BUSY__SHIFT = 0xf # macro +GRBM_STATUS3__GL1CC_BUSY__SHIFT = 0x10 # macro +GRBM_STATUS3__SEDC_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS3__PC_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS3__GL1H_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS3__GUS_LINK_BUSY__SHIFT = 0x1c # macro +GRBM_STATUS3__GUS_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS3__UTCL1_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS3__PMM_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK = 0x00000020 # macro +GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK = 0x00000080 # macro +GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK = 0x00000100 # macro +GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK = 0x00000200 # macro +GRBM_STATUS3__PH_BUSY_MASK = 0x00002000 # macro +GRBM_STATUS3__CH_BUSY_MASK = 0x00004000 # macro +GRBM_STATUS3__GL2CC_BUSY_MASK = 0x00008000 # macro +GRBM_STATUS3__GL1CC_BUSY_MASK = 0x00010000 # macro +GRBM_STATUS3__SEDC_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS3__PC_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS3__GL1H_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS3__GUS_LINK_BUSY_MASK = 0x10000000 # macro +GRBM_STATUS3__GUS_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS3__UTCL1_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS3__PMM_BUSY_MASK = 0x80000000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT = 0x0 # macro +GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT = 0x2 # macro +GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT = 0xf # macro +GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT = 0x10 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT = 0x11 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT = 0x12 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT = 0x13 # macro +GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT = 0x14 # macro +GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT = 0x16 # macro +GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT = 0x17 # macro +GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT = 0x18 # macro +GRBM_SOFT_RESET__SOFT_RESET_CP_MASK = 0x00000001 # macro +GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK = 0x00000004 # macro +GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK = 0x00008000 # macro +GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK = 0x00010000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK = 0x00020000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK = 0x00040000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK = 0x00080000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK = 0x00100000 # macro +GRBM_SOFT_RESET__SOFT_RESET_EA_MASK = 0x00400000 # macro +GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK = 0x00800000 # macro +GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK = 0x01000000 # macro +GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT = 0x0 # macro +GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT = 0x8 # macro +GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK = 0x0000000F # macro +GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK = 0x00001F00 # macro +GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT = 0x0 # macro +GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK = 0x000000FF # macro +GRBM_STATUS_SE2__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE2__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT = 0x3 # macro +GRBM_STATUS_SE2__TCP_BUSY__SHIFT = 0x4 # macro +GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT = 0x5 # macro +GRBM_STATUS_SE2__GL1H_BUSY__SHIFT = 0x6 # macro +GRBM_STATUS_SE2__PC_BUSY__SHIFT = 0x7 # macro +GRBM_STATUS_SE2__SEDC_BUSY__SHIFT = 0x8 # macro +GRBM_STATUS_SE2__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE2__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE2__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE2__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE2__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE2__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE2__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE2__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE2__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE2__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE2__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE2__UTCL1_BUSY_MASK = 0x00000008 # macro +GRBM_STATUS_SE2__TCP_BUSY_MASK = 0x00000010 # macro +GRBM_STATUS_SE2__GL1CC_BUSY_MASK = 0x00000020 # macro +GRBM_STATUS_SE2__GL1H_BUSY_MASK = 0x00000040 # macro +GRBM_STATUS_SE2__PC_BUSY_MASK = 0x00000080 # macro +GRBM_STATUS_SE2__SEDC_BUSY_MASK = 0x00000100 # macro +GRBM_STATUS_SE2__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE2__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE2__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE2__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE2__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE2__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE2__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE2__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE2__CB_BUSY_MASK = 0x80000000 # macro +GRBM_STATUS_SE3__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE3__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT = 0x3 # macro +GRBM_STATUS_SE3__TCP_BUSY__SHIFT = 0x4 # macro +GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT = 0x5 # macro +GRBM_STATUS_SE3__GL1H_BUSY__SHIFT = 0x6 # macro +GRBM_STATUS_SE3__PC_BUSY__SHIFT = 0x7 # macro +GRBM_STATUS_SE3__SEDC_BUSY__SHIFT = 0x8 # macro +GRBM_STATUS_SE3__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE3__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE3__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE3__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE3__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE3__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE3__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE3__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE3__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE3__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE3__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE3__UTCL1_BUSY_MASK = 0x00000008 # macro +GRBM_STATUS_SE3__TCP_BUSY_MASK = 0x00000010 # macro +GRBM_STATUS_SE3__GL1CC_BUSY_MASK = 0x00000020 # macro +GRBM_STATUS_SE3__GL1H_BUSY_MASK = 0x00000040 # macro +GRBM_STATUS_SE3__PC_BUSY_MASK = 0x00000080 # macro +GRBM_STATUS_SE3__SEDC_BUSY_MASK = 0x00000100 # macro +GRBM_STATUS_SE3__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE3__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE3__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE3__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE3__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE3__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE3__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE3__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE3__CB_BUSY_MASK = 0x80000000 # macro +GRBM_STATUS_SE4__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE4__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE4__UTCL1_BUSY__SHIFT = 0x3 # macro +GRBM_STATUS_SE4__TCP_BUSY__SHIFT = 0x4 # macro +GRBM_STATUS_SE4__GL1CC_BUSY__SHIFT = 0x5 # macro +GRBM_STATUS_SE4__GL1H_BUSY__SHIFT = 0x6 # macro +GRBM_STATUS_SE4__PC_BUSY__SHIFT = 0x7 # macro +GRBM_STATUS_SE4__SEDC_BUSY__SHIFT = 0x8 # macro +GRBM_STATUS_SE4__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE4__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE4__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE4__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE4__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE4__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE4__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE4__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE4__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE4__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE4__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE4__UTCL1_BUSY_MASK = 0x00000008 # macro +GRBM_STATUS_SE4__TCP_BUSY_MASK = 0x00000010 # macro +GRBM_STATUS_SE4__GL1CC_BUSY_MASK = 0x00000020 # macro +GRBM_STATUS_SE4__GL1H_BUSY_MASK = 0x00000040 # macro +GRBM_STATUS_SE4__PC_BUSY_MASK = 0x00000080 # macro +GRBM_STATUS_SE4__SEDC_BUSY_MASK = 0x00000100 # macro +GRBM_STATUS_SE4__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE4__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE4__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE4__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE4__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE4__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE4__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE4__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE4__CB_BUSY_MASK = 0x80000000 # macro +GRBM_STATUS_SE5__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE5__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE5__UTCL1_BUSY__SHIFT = 0x3 # macro +GRBM_STATUS_SE5__TCP_BUSY__SHIFT = 0x4 # macro +GRBM_STATUS_SE5__GL1CC_BUSY__SHIFT = 0x5 # macro +GRBM_STATUS_SE5__GL1H_BUSY__SHIFT = 0x6 # macro +GRBM_STATUS_SE5__PC_BUSY__SHIFT = 0x7 # macro +GRBM_STATUS_SE5__SEDC_BUSY__SHIFT = 0x8 # macro +GRBM_STATUS_SE5__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE5__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE5__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE5__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE5__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE5__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE5__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE5__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE5__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE5__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE5__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE5__UTCL1_BUSY_MASK = 0x00000008 # macro +GRBM_STATUS_SE5__TCP_BUSY_MASK = 0x00000010 # macro +GRBM_STATUS_SE5__GL1CC_BUSY_MASK = 0x00000020 # macro +GRBM_STATUS_SE5__GL1H_BUSY_MASK = 0x00000040 # macro +GRBM_STATUS_SE5__PC_BUSY_MASK = 0x00000080 # macro +GRBM_STATUS_SE5__SEDC_BUSY_MASK = 0x00000100 # macro +GRBM_STATUS_SE5__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE5__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE5__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE5__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE5__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE5__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE5__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE5__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE5__CB_BUSY_MASK = 0x80000000 # macro +GRBM_READ_ERROR__READ_ADDRESS__SHIFT = 0x2 # macro +GRBM_READ_ERROR__READ_PIPEID__SHIFT = 0x14 # macro +GRBM_READ_ERROR__READ_MEID__SHIFT = 0x16 # macro +GRBM_READ_ERROR__READ_ERROR__SHIFT = 0x1f # macro +GRBM_READ_ERROR__READ_ADDRESS_MASK = 0x000FFFFC # macro +GRBM_READ_ERROR__READ_PIPEID_MASK = 0x00300000 # macro +GRBM_READ_ERROR__READ_MEID_MASK = 0x00C00000 # macro +GRBM_READ_ERROR__READ_ERROR_MASK = 0x80000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT = 0x9 # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT = 0xa # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT = 0xb # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT = 0xc # macro +GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT = 0xd # macro +GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT = 0xe # macro +GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT = 0x12 # macro +GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT = 0x13 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT = 0x14 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT = 0x15 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT = 0x16 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT = 0x17 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT = 0x18 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT = 0x19 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT = 0x1a # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT = 0x1b # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT = 0x1c # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT = 0x1d # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT = 0x1e # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT = 0x1f # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK = 0x00000200 # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK = 0x00000400 # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK = 0x00000800 # macro +GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK = 0x00001000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK = 0x00002000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK = 0x00004000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK = 0x00040000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK = 0x00080000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK = 0x00100000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK = 0x00200000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK = 0x00400000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK = 0x00800000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK = 0x01000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK = 0x02000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK = 0x04000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK = 0x08000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK = 0x10000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK = 0x20000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK = 0x40000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK = 0x80000000 # macro +GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT = 0x0 # macro +GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT = 0x13 # macro +GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK = 0x00000001 # macro +GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK = 0x00080000 # macro +GRBM_TRAP_OP__RW__SHIFT = 0x0 # macro +GRBM_TRAP_OP__RW_MASK = 0x00000001 # macro +GRBM_TRAP_ADDR__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_ADDR__DATA_MASK = 0x0003FFFF # macro +GRBM_TRAP_ADDR_MSK__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_ADDR_MSK__DATA_MASK = 0x0003FFFF # macro +GRBM_TRAP_WD__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_WD__DATA_MASK = 0xFFFFFFFF # macro +GRBM_TRAP_WD_MSK__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_WD_MSK__DATA_MASK = 0xFFFFFFFF # macro +GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT = 0x0 # macro +GRBM_DSM_BYPASS__BYPASS_EN__SHIFT = 0x2 # macro +GRBM_DSM_BYPASS__BYPASS_BITS_MASK = 0x00000003 # macro +GRBM_DSM_BYPASS__BYPASS_EN_MASK = 0x00000004 # macro +GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT = 0x0 # macro +GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT = 0x2 # macro +GRBM_WRITE_ERROR__WRITE_VFID__SHIFT = 0x8 # macro +GRBM_WRITE_ERROR__WRITE_VF__SHIFT = 0xc # macro +GRBM_WRITE_ERROR__WRITE_VMID__SHIFT = 0xd # macro +GRBM_WRITE_ERROR__TMZ__SHIFT = 0x11 # macro +GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT = 0x14 # macro +GRBM_WRITE_ERROR__WRITE_MEID__SHIFT = 0x16 # macro +GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT = 0x1f # macro +GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK = 0x00000001 # macro +GRBM_WRITE_ERROR__WRITE_SSRCID_MASK = 0x0000003C # macro +GRBM_WRITE_ERROR__WRITE_VFID_MASK = 0x00000F00 # macro +GRBM_WRITE_ERROR__WRITE_VF_MASK = 0x00001000 # macro +GRBM_WRITE_ERROR__WRITE_VMID_MASK = 0x0001E000 # macro +GRBM_WRITE_ERROR__TMZ_MASK = 0x00020000 # macro +GRBM_WRITE_ERROR__WRITE_PIPEID_MASK = 0x00300000 # macro +GRBM_WRITE_ERROR__WRITE_MEID_MASK = 0x00C00000 # macro +GRBM_WRITE_ERROR__WRITE_ERROR_MASK = 0x80000000 # macro +GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT = 0x0 # macro +GRBM_CHIP_REVISION__CHIP_REVISION_MASK = 0x000000FF # macro +GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro +GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT = 0x10 # macro +GRBM_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro +GRBM_IH_CREDIT__IH_CLIENT_ID_MASK = 0x00FF0000 # macro +GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT = 0x10 # macro +GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT = 0x14 # macro +GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK = 0x00010000 # macro +GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK = 0x00100000 # macro +GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT = 0x0 # macro +GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK = 0x0003FFFF # macro +GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT = 0x0 # macro +GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK = 0x0003FFFF # macro +GRBM_INVALID_PIPE__ADDR__SHIFT = 0x2 # macro +GRBM_INVALID_PIPE__PIPEID__SHIFT = 0x14 # macro +GRBM_INVALID_PIPE__MEID__SHIFT = 0x16 # macro +GRBM_INVALID_PIPE__QUEUEID__SHIFT = 0x18 # macro +GRBM_INVALID_PIPE__SSRCID__SHIFT = 0x1b # macro +GRBM_INVALID_PIPE__INVALID_PIPE__SHIFT = 0x1f # macro +GRBM_INVALID_PIPE__ADDR_MASK = 0x000FFFFC # macro +GRBM_INVALID_PIPE__PIPEID_MASK = 0x00300000 # macro +GRBM_INVALID_PIPE__MEID_MASK = 0x00C00000 # macro +GRBM_INVALID_PIPE__QUEUEID_MASK = 0x07000000 # macro +GRBM_INVALID_PIPE__SSRCID_MASK = 0x78000000 # macro +GRBM_INVALID_PIPE__INVALID_PIPE_MASK = 0x80000000 # macro +GRBM_FENCE_RANGE0__START__SHIFT = 0x0 # macro +GRBM_FENCE_RANGE0__END__SHIFT = 0x10 # macro +GRBM_FENCE_RANGE0__START_MASK = 0x0000FFFF # macro +GRBM_FENCE_RANGE0__END_MASK = 0xFFFF0000 # macro +GRBM_FENCE_RANGE1__START__SHIFT = 0x0 # macro +GRBM_FENCE_RANGE1__END__SHIFT = 0x10 # macro +GRBM_FENCE_RANGE1__START_MASK = 0x0000FFFF # macro +GRBM_FENCE_RANGE1__END_MASK = 0xFFFF0000 # macro +GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK = 0xFFFFFFFF # macro +VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT = 0x0 # macro +VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT = 0x4 # macro +VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT = 0x1f # macro +VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK = 0x0000000F # macro +VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK = 0x000003F0 # macro +VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK = 0x80000000 # macro +CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT = 0x0 # macro +CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK = 0x0000007F # macro +CP_CPC_DEBUG_DATA__DEBUG_DATA__SHIFT = 0x0 # macro +CP_CPC_DEBUG_DATA__DEBUG_DATA_MASK = 0xFFFFFFFF # macro +CP_CPC_STATUS__MEC1_BUSY__SHIFT = 0x0 # macro +CP_CPC_STATUS__MEC2_BUSY__SHIFT = 0x1 # macro +CP_CPC_STATUS__DC0_BUSY__SHIFT = 0x2 # macro +CP_CPC_STATUS__DC1_BUSY__SHIFT = 0x3 # macro +CP_CPC_STATUS__RCIU1_BUSY__SHIFT = 0x4 # macro +CP_CPC_STATUS__RCIU2_BUSY__SHIFT = 0x5 # macro +CP_CPC_STATUS__ROQ1_BUSY__SHIFT = 0x6 # macro +CP_CPC_STATUS__ROQ2_BUSY__SHIFT = 0x7 # macro +CP_CPC_STATUS__TCIU_BUSY__SHIFT = 0xa # macro +CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT = 0xb # macro +CP_CPC_STATUS__QU_BUSY__SHIFT = 0xc # macro +CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT = 0xd # macro +CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT = 0xe # macro +CP_CPC_STATUS__GCRIU_BUSY__SHIFT = 0xf # macro +CP_CPC_STATUS__MES_BUSY__SHIFT = 0x10 # macro +CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT = 0x11 # macro +CP_CPC_STATUS__RCIU3_BUSY__SHIFT = 0x12 # macro +CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT = 0x13 # macro +CP_CPC_STATUS__MES_DATA_CACHE_BUSY__SHIFT = 0x14 # macro +CP_CPC_STATUS__MEC_DATA_CACHE_BUSY__SHIFT = 0x15 # macro +CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT = 0x1d # macro +CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT = 0x1e # macro +CP_CPC_STATUS__CPC_BUSY__SHIFT = 0x1f # macro +CP_CPC_STATUS__MEC1_BUSY_MASK = 0x00000001 # macro +CP_CPC_STATUS__MEC2_BUSY_MASK = 0x00000002 # macro +CP_CPC_STATUS__DC0_BUSY_MASK = 0x00000004 # macro +CP_CPC_STATUS__DC1_BUSY_MASK = 0x00000008 # macro +CP_CPC_STATUS__RCIU1_BUSY_MASK = 0x00000010 # macro +CP_CPC_STATUS__RCIU2_BUSY_MASK = 0x00000020 # macro +CP_CPC_STATUS__ROQ1_BUSY_MASK = 0x00000040 # macro +CP_CPC_STATUS__ROQ2_BUSY_MASK = 0x00000080 # macro +CP_CPC_STATUS__TCIU_BUSY_MASK = 0x00000400 # macro +CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK = 0x00000800 # macro +CP_CPC_STATUS__QU_BUSY_MASK = 0x00001000 # macro +CP_CPC_STATUS__UTCL2IU_BUSY_MASK = 0x00002000 # macro +CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK = 0x00004000 # macro +CP_CPC_STATUS__GCRIU_BUSY_MASK = 0x00008000 # macro +CP_CPC_STATUS__MES_BUSY_MASK = 0x00010000 # macro +CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK = 0x00020000 # macro +CP_CPC_STATUS__RCIU3_BUSY_MASK = 0x00040000 # macro +CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK = 0x00080000 # macro +CP_CPC_STATUS__MES_DATA_CACHE_BUSY_MASK = 0x00100000 # macro +CP_CPC_STATUS__MEC_DATA_CACHE_BUSY_MASK = 0x00200000 # macro +CP_CPC_STATUS__CPG_CPC_BUSY_MASK = 0x20000000 # macro +CP_CPC_STATUS__CPF_CPC_BUSY_MASK = 0x40000000 # macro +CP_CPC_STATUS__CPC_BUSY_MASK = 0x80000000 # macro +CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT = 0x0 # macro +CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY__SHIFT = 0x1 # macro +CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT = 0x2 # macro +CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT = 0x3 # macro +CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT = 0x4 # macro +CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT = 0x5 # macro +CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT = 0x6 # macro +CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT = 0x7 # macro +CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT = 0x8 # macro +CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT = 0x9 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT = 0xa # macro +CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT = 0xb # macro +CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT = 0xc # macro +CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT = 0xd # macro +CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT = 0x10 # macro +CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY__SHIFT = 0x11 # macro +CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT = 0x12 # macro +CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT = 0x13 # macro +CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT = 0x14 # macro +CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT = 0x15 # macro +CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT = 0x16 # macro +CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT = 0x17 # macro +CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT = 0x18 # macro +CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT = 0x19 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT = 0x1a # macro +CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT = 0x1b # macro +CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT = 0x1c # macro +CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT = 0x1d # macro +CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK = 0x00000001 # macro +CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY_MASK = 0x00000002 # macro +CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK = 0x00000004 # macro +CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK = 0x00000008 # macro +CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK = 0x00000010 # macro +CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK = 0x00000020 # macro +CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK = 0x00000040 # macro +CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK = 0x00000080 # macro +CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK = 0x00000100 # macro +CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK = 0x00000200 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK = 0x00000400 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK = 0x00000800 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK = 0x00001000 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK = 0x00002000 # macro +CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK = 0x00010000 # macro +CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY_MASK = 0x00020000 # macro +CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK = 0x00040000 # macro +CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK = 0x00080000 # macro +CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK = 0x00100000 # macro +CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK = 0x00200000 # macro +CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK = 0x00400000 # macro +CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK = 0x00800000 # macro +CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK = 0x01000000 # macro +CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK = 0x02000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK = 0x04000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK = 0x08000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK = 0x10000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK = 0x20000000 # macro +CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT = 0x3 # macro +CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT = 0x4 # macro +CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT = 0x6 # macro +CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT = 0x7 # macro +CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT = 0x8 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT = 0x9 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT = 0xa # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT = 0xd # macro +CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT = 0x10 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT = 0x11 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT = 0x12 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT = 0x15 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT = 0x16 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT = 0x17 # macro +CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT = 0x18 # macro +CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT = 0x19 # macro +CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK = 0x00000008 # macro +CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK = 0x00000010 # macro +CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK = 0x00000040 # macro +CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK = 0x00000080 # macro +CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK = 0x00000100 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK = 0x00000200 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK = 0x00000400 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK = 0x00002000 # macro +CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK = 0x00010000 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK = 0x00020000 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK = 0x00040000 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK = 0x00200000 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK = 0x00400000 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK = 0x00800000 # macro +CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK = 0x01000000 # macro +CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK = 0x02000000 # macro +CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT = 0x0 # macro +CP_CPF_STATUS__CSF_BUSY__SHIFT = 0x1 # macro +CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT = 0x4 # macro +CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT = 0x5 # macro +CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT = 0x6 # macro +CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT = 0x7 # macro +CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT = 0x8 # macro +CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT = 0x9 # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT = 0xa # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT = 0xb # macro +CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT = 0xc # macro +CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT = 0xd # macro +CP_CPF_STATUS__TCIU_BUSY__SHIFT = 0xe # macro +CP_CPF_STATUS__HQD_BUSY__SHIFT = 0xf # macro +CP_CPF_STATUS__PRT_BUSY__SHIFT = 0x10 # macro +CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT = 0x11 # macro +CP_CPF_STATUS__RCIU_BUSY__SHIFT = 0x12 # macro +CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT = 0x13 # macro +CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT = 0x14 # macro +CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT = 0x15 # macro +CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT = 0x16 # macro +CP_CPF_STATUS__GCRIU_BUSY__SHIFT = 0x17 # macro +CP_CPF_STATUS__MES_HQD_BUSY__SHIFT = 0x18 # macro +CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT = 0x1a # macro +CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT = 0x1b # macro +CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT = 0x1c # macro +CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT = 0x1e # macro +CP_CPF_STATUS__CPF_BUSY__SHIFT = 0x1f # macro +CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK = 0x00000001 # macro +CP_CPF_STATUS__CSF_BUSY_MASK = 0x00000002 # macro +CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK = 0x00000010 # macro +CP_CPF_STATUS__ROQ_RING_BUSY_MASK = 0x00000020 # macro +CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK = 0x00000040 # macro +CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK = 0x00000080 # macro +CP_CPF_STATUS__ROQ_STATE_BUSY_MASK = 0x00000100 # macro +CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK = 0x00000200 # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK = 0x00000400 # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK = 0x00000800 # macro +CP_CPF_STATUS__SEMAPHORE_BUSY_MASK = 0x00001000 # macro +CP_CPF_STATUS__INTERRUPT_BUSY_MASK = 0x00002000 # macro +CP_CPF_STATUS__TCIU_BUSY_MASK = 0x00004000 # macro +CP_CPF_STATUS__HQD_BUSY_MASK = 0x00008000 # macro +CP_CPF_STATUS__PRT_BUSY_MASK = 0x00010000 # macro +CP_CPF_STATUS__UTCL2IU_BUSY_MASK = 0x00020000 # macro +CP_CPF_STATUS__RCIU_BUSY_MASK = 0x00040000 # macro +CP_CPF_STATUS__RCIU_GFX_BUSY_MASK = 0x00080000 # macro +CP_CPF_STATUS__RCIU_CMP_BUSY_MASK = 0x00100000 # macro +CP_CPF_STATUS__ROQ_DATA_BUSY_MASK = 0x00200000 # macro +CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK = 0x00400000 # macro +CP_CPF_STATUS__GCRIU_BUSY_MASK = 0x00800000 # macro +CP_CPF_STATUS__MES_HQD_BUSY_MASK = 0x01000000 # macro +CP_CPF_STATUS__CPF_GFX_BUSY_MASK = 0x04000000 # macro +CP_CPF_STATUS__CPF_CMP_BUSY_MASK = 0x08000000 # macro +CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK = 0x30000000 # macro +CP_CPF_STATUS__CPC_CPF_BUSY_MASK = 0x40000000 # macro +CP_CPF_STATUS__CPF_BUSY_MASK = 0x80000000 # macro +CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT = 0x0 # macro +CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT = 0x1 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT = 0x2 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT = 0x3 # macro +CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT = 0x4 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT = 0x5 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT = 0x6 # macro +CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT = 0x7 # macro +CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT = 0x8 # macro +CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT = 0x9 # macro +CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT = 0xa # macro +CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT = 0xb # macro +CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT = 0xc # macro +CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT = 0xd # macro +CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT = 0xe # macro +CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT = 0xf # macro +CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT = 0x10 # macro +CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT = 0x11 # macro +CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT = 0x12 # macro +CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT = 0x13 # macro +CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT = 0x14 # macro +CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT = 0x15 # macro +CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT = 0x16 # macro +CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT = 0x17 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT = 0x18 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT = 0x19 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT = 0x1a # macro +CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT = 0x1b # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT = 0x1c # macro +CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT = 0x1d # macro +CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT = 0x1e # macro +CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT = 0x1f # macro +CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK = 0x00000001 # macro +CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK = 0x00000002 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK = 0x00000004 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK = 0x00000008 # macro +CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK = 0x00000010 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK = 0x00000020 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK = 0x00000040 # macro +CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK = 0x00000080 # macro +CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK = 0x00000100 # macro +CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK = 0x00000200 # macro +CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK = 0x00000400 # macro +CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK = 0x00000800 # macro +CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK = 0x00001000 # macro +CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK = 0x00002000 # macro +CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK = 0x00004000 # macro +CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK = 0x00008000 # macro +CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK = 0x00010000 # macro +CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK = 0x00020000 # macro +CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK = 0x00040000 # macro +CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK = 0x00080000 # macro +CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK = 0x00100000 # macro +CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK = 0x00200000 # macro +CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK = 0x00400000 # macro +CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK = 0x00800000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK = 0x01000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK = 0x02000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK = 0x04000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK = 0x08000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK = 0x10000000 # macro +CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK = 0x20000000 # macro +CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK = 0x40000000 # macro +CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK = 0x80000000 # macro +CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT = 0x0 # macro +CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT = 0x1 # macro +CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT = 0x2 # macro +CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT = 0x3 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT = 0x5 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT = 0x6 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT = 0x7 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT = 0x8 # macro +CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT = 0x9 # macro +CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT = 0xa # macro +CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT = 0xb # macro +CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT = 0xc # macro +CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT = 0xd # macro +CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK = 0x00000001 # macro +CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK = 0x00000002 # macro +CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK = 0x00000004 # macro +CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK = 0x00000008 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK = 0x00000020 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK = 0x00000040 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK = 0x00000080 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK = 0x00000100 # macro +CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK = 0x00000200 # macro +CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK = 0x00000400 # macro +CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK = 0x00000800 # macro +CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK = 0x00001000 # macro +CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK = 0x00002000 # macro +CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT = 0x0 # macro +CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT = 0x2 # macro +CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT = 0x3 # macro +CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT = 0x7 # macro +CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT = 0x8 # macro +CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT = 0xa # macro +CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT = 0xb # macro +CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT = 0xc # macro +CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT = 0xd # macro +CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK = 0x00000001 # macro +CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK = 0x00000004 # macro +CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK = 0x00000008 # macro +CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK = 0x00000080 # macro +CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK = 0x00000100 # macro +CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK = 0x00000400 # macro +CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK = 0x00000800 # macro +CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK = 0x00001000 # macro +CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK = 0x00002000 # macro +CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT = 0x0 # macro +CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK = 0x0000003F # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT = 0x0 # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK = 0x0003FFFF # macro +CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT = 0x0 # macro +CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT = 0x0 # macro +CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT = 0x0 # macro +CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT = 0x1f # macro +CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK = 0x000001FF # macro +CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK = 0x80000000 # macro +CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT = 0x0 # macro +CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK = 0xFFFFFFFF # macro +CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT = 0x0 # macro +CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK = 0x00000007 # macro +CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY__SHIFT = 0x0 # macro +CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY__SHIFT = 0x1 # macro +CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT = 0xc # macro +CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT = 0xe # macro +CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT = 0x11 # macro +CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT = 0x12 # macro +CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT = 0x16 # macro +CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT = 0x17 # macro +CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT = 0x18 # macro +CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT = 0x1b # macro +CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT = 0x1e # macro +CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY_MASK = 0x00000001 # macro +CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY_MASK = 0x00000002 # macro +CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK = 0x00001000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK = 0x00004000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK = 0x00020000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK = 0x00040000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK = 0x00400000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK = 0x00800000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK = 0x01000000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK = 0x08000000 # macro +CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK = 0x40000000 # macro +CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT = 0x0 # macro +CP_CPC_HALT_HYST_COUNT__COUNT_MASK = 0x0000000F # macro +CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT = 0x0 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT = 0x1 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT = 0x2 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT = 0x3 # macro +CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT = 0x4 # macro +CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT = 0x5 # macro +CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT = 0x6 # macro +CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT = 0x7 # macro +CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT = 0xa # macro +CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT = 0xb # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT = 0xc # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT = 0xd # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT = 0xe # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT = 0xf # macro +CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT = 0x10 # macro +CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT = 0x11 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT = 0x12 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT = 0x13 # macro +CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT = 0x14 # macro +CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT = 0x15 # macro +CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK = 0x00000001 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK = 0x00000002 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK = 0x00000004 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK = 0x00000008 # macro +CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK = 0x00000010 # macro +CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK = 0x00000020 # macro +CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK = 0x00000040 # macro +CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK = 0x00000080 # macro +CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK = 0x00000400 # macro +CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK = 0x00000800 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK = 0x00001000 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK = 0x00002000 # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK = 0x00004000 # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK = 0x00008000 # macro +CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK = 0x00010000 # macro +CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK = 0x00020000 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK = 0x00040000 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK = 0x00080000 # macro +CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK = 0x00100000 # macro +CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK = 0x00200000 # macro +CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT = 0x0 # macro +CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0__SHIFT = 0x2 # macro +CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1__SHIFT = 0x3 # macro +CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT = 0x4 # macro +CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT = 0x5 # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT = 0xa # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT = 0xb # macro +CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT = 0xc # macro +CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT = 0xd # macro +CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT = 0xe # macro +CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT = 0xf # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT = 0x17 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT = 0x18 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT = 0x19 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT = 0x1a # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT = 0x1b # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT = 0x1c # macro +CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT = 0x1d # macro +CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK = 0x00000001 # macro +CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0_MASK = 0x00000004 # macro +CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1_MASK = 0x00000008 # macro +CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK = 0x00000010 # macro +CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK = 0x00000020 # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK = 0x00000400 # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK = 0x00000800 # macro +CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK = 0x00001000 # macro +CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK = 0x00002000 # macro +CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK = 0x00004000 # macro +CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK = 0x00008000 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK = 0x00800000 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK = 0x01000000 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK = 0x02000000 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK = 0x04000000 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK = 0x08000000 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK = 0x10000000 # macro +CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK = 0x20000000 # macro +CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT = 0x0 # macro +CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT = 0x1 # macro +CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT = 0x2 # macro +CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT = 0x4 # macro +CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT = 0x5 # macro +CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT = 0x6 # macro +CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT = 0x8 # macro +CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT = 0x9 # macro +CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT = 0xa # macro +CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT = 0xb # macro +CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT = 0xc # macro +CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT = 0xd # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT = 0xe # macro +CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT = 0xf # macro +CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT = 0x10 # macro +CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT = 0x11 # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT = 0x12 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT = 0x13 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT = 0x14 # macro +CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT = 0x15 # macro +CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT = 0x16 # macro +CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT = 0x17 # macro +CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT = 0x18 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT = 0x19 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT = 0x1a # macro +CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT = 0x1b # macro +CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT = 0x1c # macro +CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT = 0x1d # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT = 0x1e # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT = 0x1f # macro +CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK = 0x00000001 # macro +CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK = 0x00000002 # macro +CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK = 0x00000004 # macro +CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK = 0x00000010 # macro +CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK = 0x00000020 # macro +CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK = 0x00000040 # macro +CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK = 0x00000100 # macro +CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK = 0x00000200 # macro +CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK = 0x00000400 # macro +CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK = 0x00000800 # macro +CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK = 0x00001000 # macro +CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK = 0x00002000 # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK = 0x00004000 # macro +CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK = 0x00008000 # macro +CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK = 0x00010000 # macro +CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK = 0x00020000 # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK = 0x00040000 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK = 0x00080000 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK = 0x00100000 # macro +CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK = 0x00200000 # macro +CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK = 0x00400000 # macro +CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK = 0x00800000 # macro +CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK = 0x01000000 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK = 0x02000000 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK = 0x04000000 # macro +CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK = 0x08000000 # macro +CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK = 0x10000000 # macro +CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK = 0x20000000 # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK = 0x40000000 # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK = 0x80000000 # macro +CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT = 0x0 # macro +CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT = 0x6 # macro +CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT = 0x7 # macro +CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT = 0x8 # macro +CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT = 0x9 # macro +CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT = 0xa # macro +CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT = 0xc # macro +CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT = 0xd # macro +CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT = 0xe # macro +CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT = 0xf # macro +CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT = 0x11 # macro +CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT = 0x12 # macro +CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT = 0x13 # macro +CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT = 0x14 # macro +CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT = 0x15 # macro +CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT = 0x16 # macro +CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK = 0x00000001 # macro +CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK = 0x00000040 # macro +CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK = 0x00000080 # macro +CP_BUSY_STAT__ME_PARSING_PACKETS_MASK = 0x00000100 # macro +CP_BUSY_STAT__RCIU_PFP_BUSY_MASK = 0x00000200 # macro +CP_BUSY_STAT__RCIU_ME_BUSY_MASK = 0x00000400 # macro +CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK = 0x00001000 # macro +CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK = 0x00002000 # macro +CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK = 0x00004000 # macro +CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK = 0x00008000 # macro +CP_BUSY_STAT__ME_PARSER_BUSY_MASK = 0x00020000 # macro +CP_BUSY_STAT__EOP_DONE_BUSY_MASK = 0x00040000 # macro +CP_BUSY_STAT__STRM_OUT_BUSY_MASK = 0x00080000 # macro +CP_BUSY_STAT__PIPE_STATS_BUSY_MASK = 0x00100000 # macro +CP_BUSY_STAT__RCIU_CE_BUSY_MASK = 0x00200000 # macro +CP_BUSY_STAT__CE_PARSING_PACKETS_MASK = 0x00400000 # macro +CP_STAT__ROQ_DB_BUSY__SHIFT = 0x5 # macro +CP_STAT__ROQ_CE_DB_BUSY__SHIFT = 0x6 # macro +CP_STAT__ROQ_RING_BUSY__SHIFT = 0x9 # macro +CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT = 0xa # macro +CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT = 0xb # macro +CP_STAT__ROQ_STATE_BUSY__SHIFT = 0xc # macro +CP_STAT__DC_BUSY__SHIFT = 0xd # macro +CP_STAT__UTCL2IU_BUSY__SHIFT = 0xe # macro +CP_STAT__PFP_BUSY__SHIFT = 0xf # macro +CP_STAT__MEQ_BUSY__SHIFT = 0x10 # macro +CP_STAT__ME_BUSY__SHIFT = 0x11 # macro +CP_STAT__QUERY_BUSY__SHIFT = 0x12 # macro +CP_STAT__SEMAPHORE_BUSY__SHIFT = 0x13 # macro +CP_STAT__INTERRUPT_BUSY__SHIFT = 0x14 # macro +CP_STAT__SURFACE_SYNC_BUSY__SHIFT = 0x15 # macro +CP_STAT__DMA_BUSY__SHIFT = 0x16 # macro +CP_STAT__RCIU_BUSY__SHIFT = 0x17 # macro +CP_STAT__SCRATCH_RAM_BUSY__SHIFT = 0x18 # macro +CP_STAT__GCRIU_BUSY__SHIFT = 0x19 # macro +CP_STAT__CE_BUSY__SHIFT = 0x1a # macro +CP_STAT__TCIU_BUSY__SHIFT = 0x1b # macro +CP_STAT__ROQ_CE_RING_BUSY__SHIFT = 0x1c # macro +CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT = 0x1d # macro +CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT = 0x1e # macro +CP_STAT__CP_BUSY__SHIFT = 0x1f # macro +CP_STAT__ROQ_DB_BUSY_MASK = 0x00000020 # macro +CP_STAT__ROQ_CE_DB_BUSY_MASK = 0x00000040 # macro +CP_STAT__ROQ_RING_BUSY_MASK = 0x00000200 # macro +CP_STAT__ROQ_INDIRECT1_BUSY_MASK = 0x00000400 # macro +CP_STAT__ROQ_INDIRECT2_BUSY_MASK = 0x00000800 # macro +CP_STAT__ROQ_STATE_BUSY_MASK = 0x00001000 # macro +CP_STAT__DC_BUSY_MASK = 0x00002000 # macro +CP_STAT__UTCL2IU_BUSY_MASK = 0x00004000 # macro +CP_STAT__PFP_BUSY_MASK = 0x00008000 # macro +CP_STAT__MEQ_BUSY_MASK = 0x00010000 # macro +CP_STAT__ME_BUSY_MASK = 0x00020000 # macro +CP_STAT__QUERY_BUSY_MASK = 0x00040000 # macro +CP_STAT__SEMAPHORE_BUSY_MASK = 0x00080000 # macro +CP_STAT__INTERRUPT_BUSY_MASK = 0x00100000 # macro +CP_STAT__SURFACE_SYNC_BUSY_MASK = 0x00200000 # macro +CP_STAT__DMA_BUSY_MASK = 0x00400000 # macro +CP_STAT__RCIU_BUSY_MASK = 0x00800000 # macro +CP_STAT__SCRATCH_RAM_BUSY_MASK = 0x01000000 # macro +CP_STAT__GCRIU_BUSY_MASK = 0x02000000 # macro +CP_STAT__CE_BUSY_MASK = 0x04000000 # macro +CP_STAT__TCIU_BUSY_MASK = 0x08000000 # macro +CP_STAT__ROQ_CE_RING_BUSY_MASK = 0x10000000 # macro +CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK = 0x20000000 # macro +CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK = 0x40000000 # macro +CP_STAT__CP_BUSY_MASK = 0x80000000 # macro +CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT = 0x0 # macro +CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT = 0x0 # macro +CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT = 0x0 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT = 0x8 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT = 0x10 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_MASK = 0x0000003F # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK = 0x00003F00 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK = 0x003F0000 # macro +CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_ME_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT = 0x8 # macro +CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK = 0x0001FF00 # macro +CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT = 0x0 # macro +CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT = 0x8 # macro +CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT = 0x14 # macro +CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT = 0x1c # macro +CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK = 0x000000FF # macro +CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK = 0x00000700 # macro +CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK = 0x0FF00000 # macro +CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK = 0x70000000 # macro +CP_ME_PREEMPTION__OBSOLETE__SHIFT = 0x0 # macro +CP_ME_PREEMPTION__OBSOLETE_MASK = 0x00000001 # macro +CP_RB1_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_RB1_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_RB0_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_RB0_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_RB_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_RB_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT = 0x0 # macro +CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT = 0x1c # macro +CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK = 0x0FFFFFFF # macro +CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK = 0xF0000000 # macro +CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT = 0x0 # macro +CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT = 0x10 # macro +CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK = 0x0000FFFF # macro +CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK = 0xFFFF0000 # macro +CP_ROQ1_THRESHOLDS__RB1_START__SHIFT = 0x0 # macro +CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT = 0xa # macro +CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT = 0x14 # macro +CP_ROQ1_THRESHOLDS__RB1_START_MASK = 0x000003FF # macro +CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK = 0x000FFC00 # macro +CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK = 0x3FF00000 # macro +CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT = 0x0 # macro +CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT = 0xa # macro +CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK = 0x000003FF # macro +CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK = 0x000FFC00 # macro +CP_STQ_THRESHOLDS__STQ0_START__SHIFT = 0x0 # macro +CP_STQ_THRESHOLDS__STQ1_START__SHIFT = 0x8 # macro +CP_STQ_THRESHOLDS__STQ2_START__SHIFT = 0x10 # macro +CP_STQ_THRESHOLDS__STQ0_START_MASK = 0x000000FF # macro +CP_STQ_THRESHOLDS__STQ1_START_MASK = 0x0000FF00 # macro +CP_STQ_THRESHOLDS__STQ2_START_MASK = 0x00FF0000 # macro +CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT = 0x0 # macro +CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT = 0x8 # macro +CP_MEQ_THRESHOLDS__MEQ1_START_MASK = 0x000000FF # macro +CP_MEQ_THRESHOLDS__MEQ2_START_MASK = 0x0000FF00 # macro +CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT = 0x0 # macro +CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT = 0x10 # macro +CP_ROQ_AVAIL__ROQ_CNT_RING_MASK = 0x00000FFF # macro +CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK = 0x0FFF0000 # macro +CP_STQ_AVAIL__STQ_CNT__SHIFT = 0x0 # macro +CP_STQ_AVAIL__STQ_CNT_MASK = 0x000001FF # macro +CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT = 0x0 # macro +CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT = 0x10 # macro +CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK = 0x00000FFF # macro +CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK = 0x0FFF0000 # macro +CP_MEQ_AVAIL__MEQ_CNT__SHIFT = 0x0 # macro +CP_MEQ_AVAIL__MEQ_CNT_MASK = 0x000003FF # macro +CP_CMD_INDEX__CMD_INDEX__SHIFT = 0x0 # macro +CP_CMD_INDEX__CMD_ME_SEL__SHIFT = 0xc # macro +CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT = 0x10 # macro +CP_CMD_INDEX__CMD_INDEX_MASK = 0x000007FF # macro +CP_CMD_INDEX__CMD_ME_SEL_MASK = 0x00003000 # macro +CP_CMD_INDEX__CMD_QUEUE_SEL_MASK = 0x00070000 # macro +CP_CMD_DATA__CMD_DATA__SHIFT = 0x0 # macro +CP_CMD_DATA__CMD_DATA_MASK = 0xFFFFFFFF # macro +CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT = 0x0 # macro +CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT = 0x10 # macro +CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK = 0x00000FFF # macro +CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK = 0x0FFF0000 # macro +CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT = 0x0 # macro +CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT = 0x10 # macro +CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK = 0x00000FFF # macro +CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK = 0x0FFF0000 # macro +CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT = 0x0 # macro +CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT = 0x10 # macro +CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK = 0x00000FFF # macro +CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK = 0x0FFF0000 # macro +CP_STQ_STAT__STQ_RPTR__SHIFT = 0x0 # macro +CP_STQ_STAT__STQ_RPTR_MASK = 0x000003FF # macro +CP_STQ_WR_STAT__STQ_WPTR__SHIFT = 0x0 # macro +CP_STQ_WR_STAT__STQ_WPTR_MASK = 0x000003FF # macro +CP_MEQ_STAT__MEQ_RPTR__SHIFT = 0x0 # macro +CP_MEQ_STAT__MEQ_WPTR__SHIFT = 0x10 # macro +CP_MEQ_STAT__MEQ_RPTR_MASK = 0x000003FF # macro +CP_MEQ_STAT__MEQ_WPTR_MASK = 0x03FF0000 # macro +CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT = 0x0 # macro +CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT = 0xa # macro +CP_ROQ3_THRESHOLDS__R0_DB_START_MASK = 0x000003FF # macro +CP_ROQ3_THRESHOLDS__R1_DB_START_MASK = 0x000FFC00 # macro +CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT = 0x0 # macro +CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT = 0x10 # macro +CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK = 0x00000FFF # macro +CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK = 0x0FFF0000 # macro +CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT = 0x16 # macro +CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT = 0x17 # macro +CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK = 0x00400000 # macro +CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK = 0x00800000 # macro +CP_DEBUG_CNTL__DEBUG_INDX__SHIFT = 0x0 # macro +CP_DEBUG_CNTL__DEBUG_INDX_MASK = 0x0000007F # macro +CP_DEBUG_DATA__DEBUG_DATA__SHIFT = 0x0 # macro +CP_DEBUG_DATA__DEBUG_DATA_MASK = 0xFFFFFFFF # macro +CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT = 0x0 # macro +CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK = 0x0003FFFF # macro +VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT = 0x0 # macro +VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK = 0x000003FF # macro +VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT = 0x0 # macro +VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK = 0x0000003F # macro +VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT = 0x0 # macro +VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK = 0x0000003F # macro +VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT = 0x0 # macro +VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK = 0x0000000F # macro +IA_UTCL1_STATUS_2__IA_BUSY__SHIFT = 0x0 # macro +IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT = 0x1 # macro +IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT = 0x2 # macro +IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT = 0x3 # macro +IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT = 0x4 # macro +IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT = 0x5 # macro +IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT = 0x6 # macro +IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT = 0x7 # macro +IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT = 0x8 # macro +IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT = 0x10 # macro +IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT = 0x18 # macro +IA_UTCL1_STATUS_2__IA_BUSY_MASK = 0x00000001 # macro +IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK = 0x00000002 # macro +IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK = 0x00000004 # macro +IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK = 0x00000008 # macro +IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK = 0x00000010 # macro +IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK = 0x00000020 # macro +IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK = 0x00000040 # macro +IA_UTCL1_STATUS_2__PRT_DETECTED_MASK = 0x00000080 # macro +IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK = 0x3F000000 # macro +WD_CNTL_STATUS__DIST_BUSY__SHIFT = 0x0 # macro +WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT = 0x1 # macro +WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT = 0x2 # macro +WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT = 0x3 # macro +WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT = 0x4 # macro +WD_CNTL_STATUS__WLC_BUSY__SHIFT = 0x5 # macro +WD_CNTL_STATUS__DIST_BUSY_MASK = 0x00000001 # macro +WD_CNTL_STATUS__DIST_BE_BUSY_MASK = 0x00000002 # macro +WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK = 0x00000004 # macro +WD_CNTL_STATUS__WD_TE11_BUSY_MASK = 0x00000008 # macro +WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK = 0x00000010 # macro +WD_CNTL_STATUS__WLC_BUSY_MASK = 0x00000020 # macro +CC_GC_PRIM_CONFIG__INACTIVE_PA__SHIFT = 0x4 # macro +CC_GC_PRIM_CONFIG__INACTIVE_PA_MASK = 0x000FFFF0 # macro +WD_QOS__DRAW_STALL__SHIFT = 0x0 # macro +WD_QOS__DRAW_STALL_MASK = 0x00000001 # macro +WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +WD_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +WD_UTCL1_CNTL__BYPASS__SHIFT = 0x19 # macro +WD_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT = 0x1d # macro +WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT = 0x1e # macro +WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +WD_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +WD_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +WD_UTCL1_CNTL__BYPASS_MASK = 0x02000000 # macro +WD_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +WD_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK = 0x20000000 # macro +WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK = 0x40000000 # macro +WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +WD_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +WD_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +WD_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +WD_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +WD_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +IA_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +IA_UTCL1_CNTL__BYPASS__SHIFT = 0x19 # macro +IA_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT = 0x1d # macro +IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT = 0x1e # macro +IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +IA_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +IA_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +IA_UTCL1_CNTL__BYPASS_MASK = 0x02000000 # macro +IA_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +IA_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK = 0x20000000 # macro +IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK = 0x40000000 # macro +IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +IA_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +IA_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +IA_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +IA_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +IA_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT = 0x8 # macro +CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK = 0x00FFFF00 # macro +GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT__SHIFT = 0x0 # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT__SHIFT = 0x4 # macro +GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT__SHIFT = 0x8 # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT__SHIFT = 0xc # macro +GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT__SHIFT = 0x10 # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT__SHIFT = 0x14 # macro +GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM__SHIFT = 0x18 # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM__SHIFT = 0x1c # macro +GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT_MASK = 0x0000000F # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT_MASK = 0x000000F0 # macro +GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT_MASK = 0x00000F00 # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT_MASK = 0x0000F000 # macro +GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT_MASK = 0x000F0000 # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT_MASK = 0x00F00000 # macro +GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM_MASK = 0x0F000000 # macro +GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM_MASK = 0xF0000000 # macro +GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT__SHIFT = 0x0 # macro +GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT__SHIFT = 0x4 # macro +GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM__SHIFT = 0x8 # macro +GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM__SHIFT = 0xc # macro +GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS__SHIFT = 0x10 # macro +GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES__SHIFT = 0x14 # macro +GE_RATE_CNTL_2__MERGED_HS_GS_MODE__SHIFT = 0x18 # macro +GE_RATE_CNTL_2__MERGED_LS_ES_MODE__SHIFT = 0x19 # macro +GE_RATE_CNTL_2__ENABLE_RATE_CNTL__SHIFT = 0x1a # macro +GE_RATE_CNTL_2__SWAP_PRIORITY__SHIFT = 0x1b # macro +GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT_MASK = 0x0000000F # macro +GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT_MASK = 0x000000F0 # macro +GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM_MASK = 0x00000F00 # macro +GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM_MASK = 0x0000F000 # macro +GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS_MASK = 0x000F0000 # macro +GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES_MASK = 0x00F00000 # macro +GE_RATE_CNTL_2__MERGED_HS_GS_MODE_MASK = 0x01000000 # macro +GE_RATE_CNTL_2__MERGED_LS_ES_MODE_MASK = 0x02000000 # macro +GE_RATE_CNTL_2__ENABLE_RATE_CNTL_MASK = 0x04000000 # macro +GE_RATE_CNTL_2__SWAP_PRIORITY_MASK = 0x08000000 # macro +VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT = 0x0 # macro +VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT = 0x1 # macro +VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT = 0x7 # macro +VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT__SHIFT = 0x8 # macro +VGT_SYS_CONFIG__DUAL_CORE_EN_MASK = 0x00000001 # macro +VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK = 0x0000007E # macro +VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK = 0x00000080 # macro +VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT_MASK = 0x0007FF00 # macro +GE_PRIV_CONTROL__RESERVED__SHIFT = 0x0 # macro +GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT = 0x1 # macro +GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT = 0xa # macro +GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT = 0xf # macro +GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT = 0x10 # macro +GE_PRIV_CONTROL__DISABLE_ACCUM_AGM__SHIFT = 0x11 # macro +GE_PRIV_CONTROL__RESERVED_MASK = 0x00000001 # macro +GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK = 0x000003FE # macro +GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK = 0x00000400 # macro +GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK = 0x00008000 # macro +GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK = 0x00010000 # macro +GE_PRIV_CONTROL__DISABLE_ACCUM_AGM_MASK = 0x00020000 # macro +GE_STATUS__PERFCOUNTER_STATUS__SHIFT = 0x0 # macro +GE_STATUS__THREAD_TRACE_STATUS__SHIFT = 0x1 # macro +GE_STATUS__PERFCOUNTER_STATUS_MASK = 0x00000001 # macro +GE_STATUS__THREAD_TRACE_STATUS_MASK = 0x00000002 # macro +VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT = 0x0 # macro +VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK = 0x00000FFF # macro +GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT = 0x0 # macro +GFX_PIPE_CONTROL__RESERVED__SHIFT = 0xd # macro +GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT = 0x10 # macro +GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT = 0x11 # macro +GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK = 0x00001FFF # macro +GFX_PIPE_CONTROL__RESERVED_MASK = 0x0000E000 # macro +GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK = 0x00010000 # macro +GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK = 0x00020000 # macro +CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT = 0x10 # macro +CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK = 0xFFFF0000 # macro +GE2_SE_CNTL_STATUS__TE_BUSY__SHIFT = 0x0 # macro +GE2_SE_CNTL_STATUS__NGG_BUSY__SHIFT = 0x1 # macro +GE2_SE_CNTL_STATUS__HS_BUSY__SHIFT = 0x2 # macro +GE2_SE_CNTL_STATUS__TE_BUSY_MASK = 0x00000001 # macro +GE2_SE_CNTL_STATUS__NGG_BUSY_MASK = 0x00000002 # macro +GE2_SE_CNTL_STATUS__HS_BUSY_MASK = 0x00000004 # macro +GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA__SHIFT = 0x0 # macro +GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA__SHIFT = 0x6 # macro +GE_SPI_IF_SAFE_REG__GE_SPI_GRP__SHIFT = 0xc # macro +GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA_MASK = 0x0000003F # macro +GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA_MASK = 0x00000FC0 # macro +GE_SPI_IF_SAFE_REG__GE_SPI_GRP_MASK = 0x0003F000 # macro +GE_PA_IF_SAFE_REG__GE_PA_CSB__SHIFT = 0x0 # macro +GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD__SHIFT = 0xa # macro +GE_PA_IF_SAFE_REG__GE_PA_CSB_MASK = 0x000003FF # macro +GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD_MASK = 0x000FFC00 # macro +PA_CL_CNTL_STATUS__CL_BUSY__SHIFT = 0x1f # macro +PA_CL_CNTL_STATUS__CL_BUSY_MASK = 0x80000000 # macro +PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT = 0x0 # macro +PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT = 0x1 # macro +PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT = 0x3 # macro +PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT = 0x4 # macro +PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT = 0x6 # macro +PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT = 0x7 # macro +PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT = 0x8 # macro +PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT = 0x9 # macro +PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT = 0xb # macro +PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT = 0xc # macro +PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT = 0xe # macro +PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT = 0x11 # macro +PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT = 0x12 # macro +PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT = 0x13 # macro +PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT = 0x14 # macro +PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE__SHIFT = 0x15 # macro +PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL__SHIFT = 0x16 # macro +PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT = 0x17 # macro +PA_CL_ENHANCE__ECO_SPARE3__SHIFT = 0x1c # macro +PA_CL_ENHANCE__ECO_SPARE2__SHIFT = 0x1d # macro +PA_CL_ENHANCE__ECO_SPARE1__SHIFT = 0x1e # macro +PA_CL_ENHANCE__ECO_SPARE0__SHIFT = 0x1f # macro +PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK = 0x00000001 # macro +PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK = 0x00000006 # macro +PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK = 0x00000008 # macro +PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK = 0x00000010 # macro +PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK = 0x00000040 # macro +PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK = 0x00000080 # macro +PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK = 0x00000100 # macro +PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK = 0x00000600 # macro +PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK = 0x00000800 # macro +PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK = 0x00003000 # macro +PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK = 0x0001C000 # macro +PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK = 0x00020000 # macro +PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK = 0x00040000 # macro +PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK = 0x00080000 # macro +PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK = 0x00100000 # macro +PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE_MASK = 0x00200000 # macro +PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL_MASK = 0x00400000 # macro +PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK = 0x00800000 # macro +PA_CL_ENHANCE__ECO_SPARE3_MASK = 0x10000000 # macro +PA_CL_ENHANCE__ECO_SPARE2_MASK = 0x20000000 # macro +PA_CL_ENHANCE__ECO_SPARE1_MASK = 0x40000000 # macro +PA_CL_ENHANCE__ECO_SPARE0_MASK = 0x80000000 # macro +PA_SU_CNTL_STATUS__SU_BUSY__SHIFT = 0x1f # macro +PA_SU_CNTL_STATUS__SU_BUSY_MASK = 0x80000000 # macro +PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT = 0x0 # macro +PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK = 0x000003FF # macro +SQ_CONFIG__ECO_SPARE__SHIFT = 0x0 # macro +SQ_CONFIG__NEW_TRANS_ARB_SCHEME__SHIFT = 0x8 # macro +SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP__SHIFT = 0x9 # macro +SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT = 0xa # macro +SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS__SHIFT = 0x12 # macro +SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS__SHIFT = 0x13 # macro +SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT = 0x15 # macro +SQ_CONFIG__DISABLE_END_CLAUSE_TX__SHIFT = 0x1b # macro +SQ_CONFIG__ECO_SPARE_MASK = 0x000000FF # macro +SQ_CONFIG__NEW_TRANS_ARB_SCHEME_MASK = 0x00000100 # macro +SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP_MASK = 0x00000200 # macro +SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS_MASK = 0x00040000 # macro +SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS_MASK = 0x00180000 # macro +SQ_CONFIG__DISABLE_END_CLAUSE_TX_MASK = 0x08000000 # macro +SQC_CONFIG__INST_CACHE_SIZE__SHIFT = 0x0 # macro +SQC_CONFIG__DATA_CACHE_SIZE__SHIFT = 0x2 # macro +SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT = 0x4 # macro +SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT = 0x6 # macro +SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT = 0x7 # macro +SQC_CONFIG__FORCE_IN_ORDER__SHIFT = 0x8 # macro +SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT = 0x9 # macro +SQC_CONFIG__EVICT_LRU__SHIFT = 0xa # macro +SQC_CONFIG__FORCE_2_BANK__SHIFT = 0xc # macro +SQC_CONFIG__FORCE_1_BANK__SHIFT = 0xd # macro +SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT = 0xe # macro +SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE__SHIFT = 0x16 # macro +SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG__SHIFT = 0x17 # macro +SQC_CONFIG__SPARE__SHIFT = 0x1a # macro +SQC_CONFIG__INST_CACHE_SIZE_MASK = 0x00000003 # macro +SQC_CONFIG__DATA_CACHE_SIZE_MASK = 0x0000000C # macro +SQC_CONFIG__MISS_FIFO_DEPTH_MASK = 0x00000030 # macro +SQC_CONFIG__HIT_FIFO_DEPTH_MASK = 0x00000040 # macro +SQC_CONFIG__FORCE_ALWAYS_MISS_MASK = 0x00000080 # macro +SQC_CONFIG__FORCE_IN_ORDER_MASK = 0x00000100 # macro +SQC_CONFIG__PER_VMID_INV_DISABLE_MASK = 0x00000200 # macro +SQC_CONFIG__EVICT_LRU_MASK = 0x00000C00 # macro +SQC_CONFIG__FORCE_2_BANK_MASK = 0x00001000 # macro +SQC_CONFIG__FORCE_1_BANK_MASK = 0x00002000 # macro +SQC_CONFIG__LS_DISABLE_CLOCKS_MASK = 0x003FC000 # macro +SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE_MASK = 0x00400000 # macro +SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG_MASK = 0x03800000 # macro +SQC_CONFIG__SPARE_MASK = 0xFC000000 # macro +LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT = 0x0 # macro +LDS_CONFIG__CONF_BIT_1__SHIFT = 0x1 # macro +LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE__SHIFT = 0x2 # macro +LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT = 0x3 # macro +LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT = 0x4 # macro +LDS_CONFIG__CONF_BIT_5__SHIFT = 0x5 # macro +LDS_CONFIG__CONF_BIT_6__SHIFT = 0x6 # macro +LDS_CONFIG__CONF_BIT_7__SHIFT = 0x7 # macro +LDS_CONFIG__CONF_BIT_8__SHIFT = 0x8 # macro +LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK = 0x00000001 # macro +LDS_CONFIG__CONF_BIT_1_MASK = 0x00000002 # macro +LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE_MASK = 0x00000004 # macro +LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK = 0x00000008 # macro +LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK = 0x00000010 # macro +LDS_CONFIG__CONF_BIT_5_MASK = 0x00000020 # macro +LDS_CONFIG__CONF_BIT_6_MASK = 0x00000040 # macro +LDS_CONFIG__CONF_BIT_7_MASK = 0x00000080 # macro +LDS_CONFIG__CONF_BIT_8_MASK = 0x00000100 # macro +SQ_RANDOM_WAVE_PRI__RET__SHIFT = 0x0 # macro +SQ_RANDOM_WAVE_PRI__RUI__SHIFT = 0x7 # macro +SQ_RANDOM_WAVE_PRI__RNG__SHIFT = 0xa # macro +SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT = 0x1f # macro +SQ_RANDOM_WAVE_PRI__RET_MASK = 0x0000007F # macro +SQ_RANDOM_WAVE_PRI__RUI_MASK = 0x00000380 # macro +SQ_RANDOM_WAVE_PRI__RNG_MASK = 0x00FFFC00 # macro +SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK = 0x80000000 # macro +SQG_STATUS__REG_BUSY__SHIFT = 0x0 # macro +SQG_STATUS__REG_BUSY_MASK = 0x00000001 # macro +SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT = 0x0 # macro +SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT = 0x8 # macro +SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED__SHIFT = 0xc # macro +SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT = 0xe # macro +SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT = 0x10 # macro +SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT = 0x12 # macro +SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT__SHIFT = 0x14 # macro +SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK = 0x0000000F # macro +SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK = 0x00000300 # macro +SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED_MASK = 0x00003000 # macro +SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK = 0x0000C000 # macro +SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK = 0x00030000 # macro +SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK = 0x000C0000 # macro +SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT_MASK = 0x00300000 # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT = 0x0 # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT = 0x1 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT = 0x2 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT = 0x3 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT = 0x8 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT = 0x9 # macro +SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT = 0xa # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT = 0x10 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT = 0x11 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT = 0x12 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT = 0x13 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT = 0x14 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT = 0x15 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT = 0x18 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT = 0x19 # macro +SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT = 0x1a # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK = 0x00000001 # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK = 0x00000002 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK = 0x00000004 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK = 0x00000008 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK = 0x00000100 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK = 0x00000200 # macro +SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK = 0x00000400 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK = 0x00010000 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK = 0x00020000 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK = 0x00040000 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK = 0x00080000 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK = 0x00100000 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK = 0x00200000 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK = 0x01000000 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK = 0x02000000 # macro +SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK = 0x04000000 # macro +SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT = 0xe # macro +SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT = 0x14 # macro +SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT = 0x1a # macro +SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK = 0x000FC000 # macro +SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK = 0x03F00000 # macro +SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK = 0xFC000000 # macro +SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT = 0x0 # macro +SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT = 0x2 # macro +SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT = 0x3 # macro +SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT = 0x4 # macro +SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT = 0x5 # macro +SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK = 0x00000003 # macro +SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK = 0x00000004 # macro +SP_CONFIG__DISABLE_TRANS_COEXEC_MASK = 0x00000008 # macro +SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK = 0x00000010 # macro +SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK = 0x00000020 # macro +SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT = 0x0 # macro +SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT = 0x4 # macro +SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK = 0x00000003 # macro +SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK = 0x00000030 # macro +SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT__SHIFT = 0x0 # macro +SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT_MASK = 0x0000007F # macro +SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED__SHIFT = 0x0 # macro +SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED__SHIFT = 0x1 # macro +SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED__SHIFT = 0x2 # macro +SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED__SHIFT = 0x3 # macro +SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED_MASK = 0x00000001 # macro +SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED_MASK = 0x00000002 # macro +SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED_MASK = 0x00000004 # macro +SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED_MASK = 0x00000008 # macro +SQG_CONFIG__GL1H_PREFETCH_PAGE__SHIFT = 0x0 # macro +SQG_CONFIG__SQG_ICPFT_EN__SHIFT = 0xd # macro +SQG_CONFIG__SQG_ICPFT_CLR__SHIFT = 0xe # macro +SQG_CONFIG__XNACK_INTR_MASK__SHIFT = 0x10 # macro +SQG_CONFIG__GL1H_PREFETCH_PAGE_MASK = 0x0000000F # macro +SQG_CONFIG__SQG_ICPFT_EN_MASK = 0x00002000 # macro +SQG_CONFIG__SQG_ICPFT_CLR_MASK = 0x00004000 # macro +SQG_CONFIG__XNACK_INTR_MASK_MASK = 0xFFFF0000 # macro +SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF__SHIFT = 0x0 # macro +SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT = 0x1 # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT = 0x11 # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL__SHIFT = 0x12 # macro +SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF_MASK = 0x00000001 # macro +SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK = 0x0001FFFE # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK = 0x00020000 # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL_MASK = 0x003C0000 # macro +CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT = 0x1 # macro +CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK = 0x00000006 # macro +SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT = 0x0 # macro +SQ_INTERRUPT_AUTO_MASK__MASK_MASK = 0x00FFFFFF # macro +SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT = 0x0 # macro +SQ_INTERRUPT_MSG_CTRL__STALL_MASK = 0x00000001 # macro +SQ_WATCH0_ADDR_H__ADDR__SHIFT = 0x0 # macro +SQ_WATCH0_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +SQ_WATCH0_ADDR_L__ADDR__SHIFT = 0x6 # macro +SQ_WATCH0_ADDR_L__ADDR_MASK = 0xFFFFFFC0 # macro +SQ_WATCH0_CNTL__MASK__SHIFT = 0x0 # macro +SQ_WATCH0_CNTL__VMID__SHIFT = 0x18 # macro +SQ_WATCH0_CNTL__VALID__SHIFT = 0x1f # macro +SQ_WATCH0_CNTL__MASK_MASK = 0x00FFFFFF # macro +SQ_WATCH0_CNTL__VMID_MASK = 0x0F000000 # macro +SQ_WATCH0_CNTL__VALID_MASK = 0x80000000 # macro +SQ_WATCH1_ADDR_H__ADDR__SHIFT = 0x0 # macro +SQ_WATCH1_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +SQ_WATCH1_ADDR_L__ADDR__SHIFT = 0x6 # macro +SQ_WATCH1_ADDR_L__ADDR_MASK = 0xFFFFFFC0 # macro +SQ_WATCH1_CNTL__MASK__SHIFT = 0x0 # macro +SQ_WATCH1_CNTL__VMID__SHIFT = 0x18 # macro +SQ_WATCH1_CNTL__VALID__SHIFT = 0x1f # macro +SQ_WATCH1_CNTL__MASK_MASK = 0x00FFFFFF # macro +SQ_WATCH1_CNTL__VMID_MASK = 0x0F000000 # macro +SQ_WATCH1_CNTL__VALID_MASK = 0x80000000 # macro +SQ_WATCH2_ADDR_H__ADDR__SHIFT = 0x0 # macro +SQ_WATCH2_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +SQ_WATCH2_ADDR_L__ADDR__SHIFT = 0x6 # macro +SQ_WATCH2_ADDR_L__ADDR_MASK = 0xFFFFFFC0 # macro +SQ_WATCH2_CNTL__MASK__SHIFT = 0x0 # macro +SQ_WATCH2_CNTL__VMID__SHIFT = 0x18 # macro +SQ_WATCH2_CNTL__VALID__SHIFT = 0x1f # macro +SQ_WATCH2_CNTL__MASK_MASK = 0x00FFFFFF # macro +SQ_WATCH2_CNTL__VMID_MASK = 0x0F000000 # macro +SQ_WATCH2_CNTL__VALID_MASK = 0x80000000 # macro +SQ_WATCH3_ADDR_H__ADDR__SHIFT = 0x0 # macro +SQ_WATCH3_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +SQ_WATCH3_ADDR_L__ADDR__SHIFT = 0x6 # macro +SQ_WATCH3_ADDR_L__ADDR_MASK = 0xFFFFFFC0 # macro +SQ_WATCH3_CNTL__MASK__SHIFT = 0x0 # macro +SQ_WATCH3_CNTL__VMID__SHIFT = 0x18 # macro +SQ_WATCH3_CNTL__VALID__SHIFT = 0x1f # macro +SQ_WATCH3_CNTL__MASK_MASK = 0x00FFFFFF # macro +SQ_WATCH3_CNTL__VMID_MASK = 0x0F000000 # macro +SQ_WATCH3_CNTL__VALID_MASK = 0x80000000 # macro +SQ_IND_INDEX__WAVE_ID__SHIFT = 0x0 # macro +SQ_IND_INDEX__WORKITEM_ID__SHIFT = 0x5 # macro +SQ_IND_INDEX__AUTO_INCR__SHIFT = 0xb # macro +SQ_IND_INDEX__INDEX__SHIFT = 0x10 # macro +SQ_IND_INDEX__WAVE_ID_MASK = 0x0000001F # macro +SQ_IND_INDEX__WORKITEM_ID_MASK = 0x000007E0 # macro +SQ_IND_INDEX__AUTO_INCR_MASK = 0x00000800 # macro +SQ_IND_INDEX__INDEX_MASK = 0xFFFF0000 # macro +SQ_IND_DATA__DATA__SHIFT = 0x0 # macro +SQ_IND_DATA__DATA_MASK = 0xFFFFFFFF # macro +SQ_CMD__CMD__SHIFT = 0x0 # macro +SQ_CMD__MODE__SHIFT = 0x4 # macro +SQ_CMD__CHECK_VMID__SHIFT = 0x7 # macro +SQ_CMD__DATA__SHIFT = 0x8 # macro +SQ_CMD__WAVE_ID__SHIFT = 0x10 # macro +SQ_CMD__QUEUE_ID__SHIFT = 0x18 # macro +SQ_CMD__VM_ID__SHIFT = 0x1c # macro +SQ_CMD__CMD_MASK = 0x0000000F # macro +SQ_CMD__MODE_MASK = 0x00000070 # macro +SQ_CMD__CHECK_VMID_MASK = 0x00000080 # macro +SQ_CMD__DATA_MASK = 0x00000F00 # macro +SQ_CMD__WAVE_ID_MASK = 0x001F0000 # macro +SQ_CMD__QUEUE_ID_MASK = 0x07000000 # macro +SQ_CMD__VM_ID_MASK = 0xF0000000 # macro +SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT = 0x0 # macro +SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT = 0x7 # macro +SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT = 0x8 # macro +SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT = 0x9 # macro +SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT = 0xa # macro +SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT = 0xb # macro +SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT = 0xc # macro +SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT = 0xd # macro +SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT = 0xe # macro +SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT = 0xf # macro +SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT = 0x10 # macro +SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT = 0x11 # macro +SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT = 0x12 # macro +SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT = 0x13 # macro +SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT = 0x14 # macro +SX_DEBUG_1__DISABLE_GDS_CGTS_OPT__SHIFT = 0x15 # macro +SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT = 0x16 # macro +SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT__SHIFT = 0x17 # macro +SX_DEBUG_1__DEBUG_DATA__SHIFT = 0x18 # macro +SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK = 0x0000007F # macro +SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE_MASK = 0x00000080 # macro +SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK = 0x00000100 # macro +SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK = 0x00000200 # macro +SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK = 0x00000400 # macro +SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK = 0x00000800 # macro +SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK = 0x00001000 # macro +SX_DEBUG_1__DISABLE_REP_FGCG_MASK = 0x00002000 # macro +SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK = 0x00004000 # macro +SX_DEBUG_1__DISABLE_RAM_FGCG_MASK = 0x00008000 # macro +SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK = 0x00010000 # macro +SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK = 0x00020000 # macro +SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK = 0x00040000 # macro +SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK = 0x00080000 # macro +SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK = 0x00100000 # macro +SX_DEBUG_1__DISABLE_GDS_CGTS_OPT_MASK = 0x00200000 # macro +SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK = 0x00400000 # macro +SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT_MASK = 0x00800000 # macro +SX_DEBUG_1__DEBUG_DATA_MASK = 0xFF000000 # macro +SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT = 0x0 # macro +SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT = 0x10 # macro +SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK = 0x00000FFF # macro +SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK = 0x03FF0000 # macro +SPI_GFX_CNTL__RESET_COUNTS__SHIFT = 0x0 # macro +SPI_GFX_CNTL__RESET_COUNTS_MASK = 0x00000001 # macro +SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT = 0x3 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK = 0x000001F8 # macro +SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT = 0x0 # macro +SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK = 0x00000003 # macro +SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT = 0x0 # macro +SPI_CONFIG_PS_CU_EN__PKR2_OFFSET__SHIFT = 0x4 # macro +SPI_CONFIG_PS_CU_EN__PKR3_OFFSET__SHIFT = 0x8 # macro +SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK = 0x0000000F # macro +SPI_CONFIG_PS_CU_EN__PKR2_OFFSET_MASK = 0x000000F0 # macro +SPI_CONFIG_PS_CU_EN__PKR3_OFFSET_MASK = 0x00000F00 # macro +SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_CNTL__EN__SHIFT = 0x4 # macro +SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK = 0x0000000F # macro +SPI_WF_LIFETIME_CNTL__EN_MASK = 0x00000010 # macro +SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK = 0x80000000 # macro +SPI_LB_CTR_CTRL__LOAD__SHIFT = 0x0 # macro +SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT = 0x1 # macro +SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT = 0x3 # macro +SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT = 0x4 # macro +SPI_LB_CTR_CTRL__LOAD_MASK = 0x00000001 # macro +SPI_LB_CTR_CTRL__WAVES_SELECT_MASK = 0x00000006 # macro +SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK = 0x00000008 # macro +SPI_LB_CTR_CTRL__RESET_COUNTS_MASK = 0x00000010 # macro +SPI_LB_WGP_MASK__WGP_MASK__SHIFT = 0x0 # macro +SPI_LB_WGP_MASK__WGP_MASK_MASK = 0xFFFF # macro +SPI_LB_DATA_REG__CNT_DATA__SHIFT = 0x0 # macro +SPI_LB_DATA_REG__CNT_DATA_MASK = 0xFFFFFFFF # macro +SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT = 0x0 # macro +SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK = 0xFFFF # macro +SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT = 0x0 # macro +SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT = 0x8 # macro +SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK = 0x000000FF # macro +SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK = 0x0000FF00 # macro +SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT = 0x0 # macro +SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT = 0x10 # macro +SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK = 0x0000FFFF # macro +SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK = 0xFFFF0000 # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT = 0x0 # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT = 0x10 # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK = 0x0000FFFF # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK = 0xFFFF0000 # macro +SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK = 0xFFFFFFFF # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK = 0x000007FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK = 0x07FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK = 0x000007FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK = 0x07FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK = 0x000007FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK = 0x07FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK = 0x000007FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK = 0x07FF0000 # macro +SPI_LB_DATA_WAVES__COUNT0__SHIFT = 0x0 # macro +SPI_LB_DATA_WAVES__COUNT1__SHIFT = 0x10 # macro +SPI_LB_DATA_WAVES__COUNT0_MASK = 0x0000FFFF # macro +SPI_LB_DATA_WAVES__COUNT1_MASK = 0xFFFF0000 # macro +SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT = 0x6 # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK = 0x003F # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK = 0x03C0 # macro +SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT = 0x6 # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK = 0x003F # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK = 0x03C0 # macro +TD_STATUS__BUSY__SHIFT = 0x1f # macro +TD_STATUS__BUSY_MASK = 0x80000000 # macro +TD_SCRATCH__SCRATCH__SHIFT = 0x0 # macro +TD_SCRATCH__SCRATCH_MASK = 0xFFFFFFFF # macro +TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT = 0x0 # macro +TA_CNTL__ALIGNER_CREDIT__SHIFT = 0x10 # macro +TA_CNTL__TD_FIFO_CREDIT__SHIFT = 0x16 # macro +TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK = 0x00000001 # macro +TA_CNTL__ALIGNER_CREDIT_MASK = 0x001F0000 # macro +TA_CNTL__TD_FIFO_CREDIT_MASK = 0xFFC00000 # macro +TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT = 0x0 # macro +TA_CNTL_AUX__DEPTH_AS_PITCH_DIS__SHIFT = 0x1 # macro +TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM__SHIFT = 0x2 # macro +TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS__SHIFT = 0x3 # macro +TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT = 0x4 # macro +TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT = 0x5 # macro +TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT = 0x6 # macro +TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT = 0x7 # macro +TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT = 0x8 # macro +TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT = 0x9 # macro +TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT = 0xa # macro +TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT = 0xc # macro +TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT = 0xd # macro +TA_CNTL_AUX__ANISO_STEP__SHIFT = 0xe # macro +TA_CNTL_AUX__MINMAG_UNNORM__SHIFT = 0xf # macro +TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT = 0x10 # macro +TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT = 0x11 # macro +TA_CNTL_AUX__ANISO_TAP__SHIFT = 0x12 # macro +TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT = 0x14 # macro +TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT = 0x15 # macro +TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT = 0x16 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT = 0x17 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT = 0x18 # macro +TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT = 0x19 # macro +TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT = 0x1a # macro +TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT = 0x1c # macro +TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT = 0x1d # macro +TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT = 0x1e # macro +TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK = 0x00000001 # macro +TA_CNTL_AUX__DEPTH_AS_PITCH_DIS_MASK = 0x00000002 # macro +TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM_MASK = 0x00000004 # macro +TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS_MASK = 0x00000008 # macro +TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK = 0x00000010 # macro +TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK = 0x00000020 # macro +TA_CNTL_AUX__GATHERH_DST_SEL_MASK = 0x00000040 # macro +TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK = 0x00000080 # macro +TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK = 0x00000100 # macro +TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK = 0x00000200 # macro +TA_CNTL_AUX__ANISO_HALF_THRESH_MASK = 0x00000C00 # macro +TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK = 0x00001000 # macro +TA_CNTL_AUX__ANISO_STEP_ORDER_MASK = 0x00002000 # macro +TA_CNTL_AUX__ANISO_STEP_MASK = 0x00004000 # macro +TA_CNTL_AUX__MINMAG_UNNORM_MASK = 0x00008000 # macro +TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK = 0x00010000 # macro +TA_CNTL_AUX__ANISO_RATIO_LUT_MASK = 0x00020000 # macro +TA_CNTL_AUX__ANISO_TAP_MASK = 0x00040000 # macro +TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK = 0x00100000 # macro +TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK = 0x00200000 # macro +TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK = 0x00400000 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK = 0x00800000 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK = 0x01000000 # macro +TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK = 0x02000000 # macro +TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK = 0x04000000 # macro +TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK = 0x10000000 # macro +TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK = 0x20000000 # macro +TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK = 0xC0000000 # macro +TA_CNTL2__POINT_SAMPLE_ACCEL_DIS__SHIFT = 0x10 # macro +TA_CNTL2__TRUNCATE_COORD_MODE__SHIFT = 0x12 # macro +TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS__SHIFT = 0x13 # macro +TA_CNTL2__POINT_SAMPLE_ACCEL_DIS_MASK = 0x00010000 # macro +TA_CNTL2__TRUNCATE_COORD_MODE_MASK = 0x00040000 # macro +TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS_MASK = 0x00080000 # macro +TA_STATUS__FG_PFIFO_EMPTYB__SHIFT = 0xc # macro +TA_STATUS__FG_LFIFO_EMPTYB__SHIFT = 0xd # macro +TA_STATUS__FG_SFIFO_EMPTYB__SHIFT = 0xe # macro +TA_STATUS__FL_PFIFO_EMPTYB__SHIFT = 0x10 # macro +TA_STATUS__FL_LFIFO_EMPTYB__SHIFT = 0x11 # macro +TA_STATUS__FL_SFIFO_EMPTYB__SHIFT = 0x12 # macro +TA_STATUS__FA_PFIFO_EMPTYB__SHIFT = 0x14 # macro +TA_STATUS__FA_LFIFO_EMPTYB__SHIFT = 0x15 # macro +TA_STATUS__FA_SFIFO_EMPTYB__SHIFT = 0x16 # macro +TA_STATUS__IN_BUSY__SHIFT = 0x18 # macro +TA_STATUS__FG_BUSY__SHIFT = 0x19 # macro +TA_STATUS__LA_BUSY__SHIFT = 0x1a # macro +TA_STATUS__FL_BUSY__SHIFT = 0x1b # macro +TA_STATUS__TA_BUSY__SHIFT = 0x1c # macro +TA_STATUS__FA_BUSY__SHIFT = 0x1d # macro +TA_STATUS__AL_BUSY__SHIFT = 0x1e # macro +TA_STATUS__BUSY__SHIFT = 0x1f # macro +TA_STATUS__FG_PFIFO_EMPTYB_MASK = 0x00001000 # macro +TA_STATUS__FG_LFIFO_EMPTYB_MASK = 0x00002000 # macro +TA_STATUS__FG_SFIFO_EMPTYB_MASK = 0x00004000 # macro +TA_STATUS__FL_PFIFO_EMPTYB_MASK = 0x00010000 # macro +TA_STATUS__FL_LFIFO_EMPTYB_MASK = 0x00020000 # macro +TA_STATUS__FL_SFIFO_EMPTYB_MASK = 0x00040000 # macro +TA_STATUS__FA_PFIFO_EMPTYB_MASK = 0x00100000 # macro +TA_STATUS__FA_LFIFO_EMPTYB_MASK = 0x00200000 # macro +TA_STATUS__FA_SFIFO_EMPTYB_MASK = 0x00400000 # macro +TA_STATUS__IN_BUSY_MASK = 0x01000000 # macro +TA_STATUS__FG_BUSY_MASK = 0x02000000 # macro +TA_STATUS__LA_BUSY_MASK = 0x04000000 # macro +TA_STATUS__FL_BUSY_MASK = 0x08000000 # macro +TA_STATUS__TA_BUSY_MASK = 0x10000000 # macro +TA_STATUS__FA_BUSY_MASK = 0x20000000 # macro +TA_STATUS__AL_BUSY_MASK = 0x40000000 # macro +TA_STATUS__BUSY_MASK = 0x80000000 # macro +TA_SCRATCH__SCRATCH__SHIFT = 0x0 # macro +TA_SCRATCH__SCRATCH_MASK = 0xFFFFFFFF # macro +GDS_CONFIG__UNUSED__SHIFT = 0x1 # macro +GDS_CONFIG__UNUSED_MASK = 0xFFFFFFFE # macro +GDS_CNTL_STATUS__GDS_BUSY__SHIFT = 0x0 # macro +GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT = 0x1 # macro +GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT = 0x2 # macro +GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT = 0x3 # macro +GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT = 0x4 # macro +GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT = 0x5 # macro +GDS_CNTL_STATUS__DS_BUSY__SHIFT = 0x6 # macro +GDS_CNTL_STATUS__GWS_BUSY__SHIFT = 0x7 # macro +GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT = 0x8 # macro +GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT = 0x9 # macro +GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT = 0xa # macro +GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT = 0xb # macro +GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT = 0xc # macro +GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT = 0xd # macro +GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT = 0xe # macro +GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT = 0xf # macro +GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT = 0x10 # macro +GDS_CNTL_STATUS__UNUSED__SHIFT = 0x11 # macro +GDS_CNTL_STATUS__GDS_BUSY_MASK = 0x00000001 # macro +GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK = 0x00000002 # macro +GDS_CNTL_STATUS__ORD_APP_BUSY_MASK = 0x00000004 # macro +GDS_CNTL_STATUS__DS_WR_CLAMP_MASK = 0x00000008 # macro +GDS_CNTL_STATUS__DS_RD_CLAMP_MASK = 0x00000010 # macro +GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK = 0x00000020 # macro +GDS_CNTL_STATUS__DS_BUSY_MASK = 0x00000040 # macro +GDS_CNTL_STATUS__GWS_BUSY_MASK = 0x00000080 # macro +GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK = 0x00000100 # macro +GDS_CNTL_STATUS__CREDIT_BUSY0_MASK = 0x00000200 # macro +GDS_CNTL_STATUS__CREDIT_BUSY1_MASK = 0x00000400 # macro +GDS_CNTL_STATUS__CREDIT_BUSY2_MASK = 0x00000800 # macro +GDS_CNTL_STATUS__CREDIT_BUSY3_MASK = 0x00001000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY4_MASK = 0x00002000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY5_MASK = 0x00004000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY6_MASK = 0x00008000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY7_MASK = 0x00010000 # macro +GDS_CNTL_STATUS__UNUSED_MASK = 0xFFFE0000 # macro +GDS_ENHANCE__MISC__SHIFT = 0x0 # macro +GDS_ENHANCE__AUTO_INC_INDEX__SHIFT = 0x10 # macro +GDS_ENHANCE__CGPG_RESTORE__SHIFT = 0x11 # macro +GDS_ENHANCE__UNUSED__SHIFT = 0x12 # macro +GDS_ENHANCE__MISC_MASK = 0x0000FFFF # macro +GDS_ENHANCE__AUTO_INC_INDEX_MASK = 0x00010000 # macro +GDS_ENHANCE__CGPG_RESTORE_MASK = 0x00020000 # macro +GDS_ENHANCE__UNUSED_MASK = 0xFFFC0000 # macro +GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT = 0x0 # macro +GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT = 0x1 # macro +GDS_PROTECTION_FAULT__GRBM__SHIFT = 0x2 # macro +GDS_PROTECTION_FAULT__SE_ID__SHIFT = 0x3 # macro +GDS_PROTECTION_FAULT__SA_ID__SHIFT = 0x6 # macro +GDS_PROTECTION_FAULT__WGP_ID__SHIFT = 0x7 # macro +GDS_PROTECTION_FAULT__SIMD_ID__SHIFT = 0xb # macro +GDS_PROTECTION_FAULT__WAVE_ID__SHIFT = 0xd # macro +GDS_PROTECTION_FAULT__ADDRESS__SHIFT = 0x12 # macro +GDS_PROTECTION_FAULT__WRITE_DIS_MASK = 0x00000001 # macro +GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK = 0x00000002 # macro +GDS_PROTECTION_FAULT__GRBM_MASK = 0x00000004 # macro +GDS_PROTECTION_FAULT__SE_ID_MASK = 0x00000038 # macro +GDS_PROTECTION_FAULT__SA_ID_MASK = 0x00000040 # macro +GDS_PROTECTION_FAULT__WGP_ID_MASK = 0x00000780 # macro +GDS_PROTECTION_FAULT__SIMD_ID_MASK = 0x00001800 # macro +GDS_PROTECTION_FAULT__WAVE_ID_MASK = 0x0003E000 # macro +GDS_PROTECTION_FAULT__ADDRESS_MASK = 0xFFFC0000 # macro +GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT = 0x0 # macro +GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT = 0x1 # macro +GDS_VM_PROTECTION_FAULT__GWS__SHIFT = 0x2 # macro +GDS_VM_PROTECTION_FAULT__OA__SHIFT = 0x3 # macro +GDS_VM_PROTECTION_FAULT__GRBM__SHIFT = 0x4 # macro +GDS_VM_PROTECTION_FAULT__TMZ__SHIFT = 0x5 # macro +GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT = 0x6 # macro +GDS_VM_PROTECTION_FAULT__VMID__SHIFT = 0x8 # macro +GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT = 0xc # macro +GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT = 0x10 # macro +GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK = 0x00000001 # macro +GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK = 0x00000002 # macro +GDS_VM_PROTECTION_FAULT__GWS_MASK = 0x00000004 # macro +GDS_VM_PROTECTION_FAULT__OA_MASK = 0x00000008 # macro +GDS_VM_PROTECTION_FAULT__GRBM_MASK = 0x00000010 # macro +GDS_VM_PROTECTION_FAULT__TMZ_MASK = 0x00000020 # macro +GDS_VM_PROTECTION_FAULT__UNUSED1_MASK = 0x000000C0 # macro +GDS_VM_PROTECTION_FAULT__VMID_MASK = 0x00000F00 # macro +GDS_VM_PROTECTION_FAULT__UNUSED2_MASK = 0x0000F000 # macro +GDS_VM_PROTECTION_FAULT__ADDRESS_MASK = 0xFFFF0000 # macro +GDS_EDC_CNT__GDS_MEM_DED__SHIFT = 0x0 # macro +GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT = 0x2 # macro +GDS_EDC_CNT__GDS_MEM_SEC__SHIFT = 0x4 # macro +GDS_EDC_CNT__UNUSED__SHIFT = 0x6 # macro +GDS_EDC_CNT__GDS_MEM_DED_MASK = 0x00000003 # macro +GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK = 0x0000000C # macro +GDS_EDC_CNT__GDS_MEM_SEC_MASK = 0x00000030 # macro +GDS_EDC_CNT__UNUSED_MASK = 0xFFFFFFC0 # macro +GDS_EDC_GRBM_CNT__DED__SHIFT = 0x0 # macro +GDS_EDC_GRBM_CNT__SEC__SHIFT = 0x2 # macro +GDS_EDC_GRBM_CNT__UNUSED__SHIFT = 0x4 # macro +GDS_EDC_GRBM_CNT__DED_MASK = 0x00000003 # macro +GDS_EDC_GRBM_CNT__SEC_MASK = 0x0000000C # macro +GDS_EDC_GRBM_CNT__UNUSED_MASK = 0xFFFFFFF0 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT = 0x0 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT = 0x1 # macro +GDS_EDC_OA_DED__ME0_CS_DED__SHIFT = 0x2 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT = 0x3 # macro +GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT = 0x4 # macro +GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT = 0x5 # macro +GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT = 0x6 # macro +GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT = 0x7 # macro +GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT = 0x8 # macro +GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT = 0x9 # macro +GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT = 0xa # macro +GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT = 0xb # macro +GDS_EDC_OA_DED__ME0_PIPE1_CS_DED__SHIFT = 0xc # macro +GDS_EDC_OA_DED__UNUSED1__SHIFT = 0xd # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK = 0x00000001 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK = 0x00000002 # macro +GDS_EDC_OA_DED__ME0_CS_DED_MASK = 0x00000004 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK = 0x00000008 # macro +GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK = 0x00000010 # macro +GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK = 0x00000020 # macro +GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK = 0x00000040 # macro +GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK = 0x00000080 # macro +GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK = 0x00000100 # macro +GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK = 0x00000200 # macro +GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK = 0x00000400 # macro +GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK = 0x00000800 # macro +GDS_EDC_OA_DED__ME0_PIPE1_CS_DED_MASK = 0x00001000 # macro +GDS_EDC_OA_DED__UNUSED1_MASK = 0xFFFFE000 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT = 0x0 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT = 0x1 # macro +GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT = 0x3 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT = 0x4 # macro +GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT = 0x6 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT = 0x7 # macro +GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT = 0x9 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT = 0xa # macro +GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT = 0xc # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT = 0xd # macro +GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +GDS_DSM_CNTL__UNUSED__SHIFT = 0xf # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK = 0x00000001 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK = 0x00000002 # macro +GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK = 0x00000008 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK = 0x00000010 # macro +GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK = 0x00000040 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK = 0x00000080 # macro +GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK = 0x00000200 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK = 0x00000400 # macro +GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK = 0x00001000 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK = 0x00002000 # macro +GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +GDS_DSM_CNTL__UNUSED_MASK = 0xFFFF8000 # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT = 0x0 # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT = 0x2 # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT = 0x4 # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT = 0x6 # macro +GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT = 0x8 # macro +GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT = 0xa # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK = 0x00000003 # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK = 0x0000000C # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK = 0x00000030 # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK = 0x000000C0 # macro +GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK = 0x00000300 # macro +GDS_EDC_OA_PHY_CNT__UNUSED1_MASK = 0xFFFFFC00 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT = 0x0 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT = 0x2 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT = 0x4 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT = 0x6 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT = 0x8 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT = 0xa # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT = 0xc # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT = 0xe # macro +GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT = 0x10 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK = 0x00000003 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK = 0x0000000C # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK = 0x00000030 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK = 0x000000C0 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK = 0x00000300 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK = 0x00000C00 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK = 0x00003000 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK = 0x0000C000 # macro +GDS_EDC_OA_PIPE_CNT__UNUSED_MASK = 0xFFFF0000 # macro +GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +GDS_DSM_CNTL2__UNUSED__SHIFT = 0xf # macro +GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT = 0x1a # macro +GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +GDS_DSM_CNTL2__UNUSED_MASK = 0x03FF8000 # macro +GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK = 0xFC000000 # macro +DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT = 0x0 # macro +DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT = 0x1 # macro +DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT = 0x2 # macro +DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT = 0x3 # macro +DB_DEBUG__FORCE_Z_MODE__SHIFT = 0x4 # macro +DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT = 0x6 # macro +DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT = 0x7 # macro +DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT = 0x8 # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT = 0xa # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT = 0xc # macro +DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT = 0xe # macro +DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT = 0xf # macro +DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT = 0x10 # macro +DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT = 0x11 # macro +DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT = 0x12 # macro +DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT = 0x13 # macro +DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT = 0x15 # macro +DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT = 0x16 # macro +DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT = 0x17 # macro +DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT = 0x18 # macro +DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT = 0x1c # macro +DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT = 0x1d # macro +DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT = 0x1e # macro +DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT = 0x1f # macro +DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK = 0x00000001 # macro +DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK = 0x00000002 # macro +DB_DEBUG__FETCH_FULL_Z_TILE_MASK = 0x00000004 # macro +DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK = 0x00000008 # macro +DB_DEBUG__FORCE_Z_MODE_MASK = 0x00000030 # macro +DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK = 0x00000040 # macro +DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK = 0x00000080 # macro +DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK = 0x00000300 # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK = 0x00000C00 # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK = 0x00003000 # macro +DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK = 0x00004000 # macro +DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK = 0x00008000 # macro +DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK = 0x00010000 # macro +DB_DEBUG__DISABLE_SUMM_SQUADS_MASK = 0x00020000 # macro +DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK = 0x00040000 # macro +DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK = 0x00180000 # macro +DB_DEBUG__NEVER_FREE_Z_ONLY_MASK = 0x00200000 # macro +DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK = 0x00400000 # macro +DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK = 0x00800000 # macro +DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK = 0x0F000000 # macro +DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK = 0x10000000 # macro +DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK = 0x20000000 # macro +DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK = 0x40000000 # macro +DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK = 0x80000000 # macro +DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT = 0x0 # macro +DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT = 0x1 # macro +DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT = 0x2 # macro +DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT = 0x3 # macro +DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT = 0x4 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT = 0x5 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT = 0x6 # macro +DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT = 0x7 # macro +DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT = 0x8 # macro +DB_DEBUG2__CLK_OFF_DELAY__SHIFT = 0x9 # macro +DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT = 0xe # macro +DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT = 0xf # macro +DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT = 0x10 # macro +DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT = 0x11 # macro +DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT = 0x12 # macro +DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT = 0x13 # macro +DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT = 0x14 # macro +DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES__SHIFT = 0x15 # macro +DB_DEBUG2__FORCE_ITERATE_256__SHIFT = 0x18 # macro +DB_DEBUG2__RESERVED1__SHIFT = 0x1a # macro +DB_DEBUG2__DEBUG_BUS_FLOP_EN__SHIFT = 0x1b # macro +DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT = 0x1c # macro +DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT = 0x1d # macro +DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT = 0x1e # macro +DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT = 0x1f # macro +DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK = 0x00000001 # macro +DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK = 0x00000002 # macro +DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK = 0x00000004 # macro +DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK = 0x00000008 # macro +DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK = 0x00000010 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK = 0x00000020 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK = 0x00000040 # macro +DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK = 0x00000080 # macro +DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK = 0x00000100 # macro +DB_DEBUG2__CLK_OFF_DELAY_MASK = 0x00003E00 # macro +DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK = 0x00004000 # macro +DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK = 0x00008000 # macro +DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK = 0x00010000 # macro +DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK = 0x00020000 # macro +DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK = 0x00040000 # macro +DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK = 0x00080000 # macro +DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK_MASK = 0x00100000 # macro +DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES_MASK = 0x00200000 # macro +DB_DEBUG2__FORCE_ITERATE_256_MASK = 0x03000000 # macro +DB_DEBUG2__RESERVED1_MASK = 0x04000000 # macro +DB_DEBUG2__DEBUG_BUS_FLOP_EN_MASK = 0x08000000 # macro +DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK = 0x10000000 # macro +DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK = 0x20000000 # macro +DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK = 0x40000000 # macro +DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK = 0x80000000 # macro +DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT = 0x0 # macro +DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT = 0x1 # macro +DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT = 0x2 # macro +DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT = 0x3 # macro +DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT = 0x4 # macro +DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT = 0x5 # macro +DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT = 0x6 # macro +DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT = 0x8 # macro +DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT = 0xa # macro +DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT = 0xb # macro +DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT = 0xd # macro +DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT = 0xe # macro +DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT = 0xf # macro +DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT = 0x10 # macro +DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT = 0x11 # macro +DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT = 0x13 # macro +DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT = 0x14 # macro +DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT = 0x15 # macro +DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT = 0x16 # macro +DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT = 0x17 # macro +DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT = 0x18 # macro +DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT = 0x19 # macro +DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT = 0x1a # macro +DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT = 0x1b # macro +DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT = 0x1c # macro +DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT = 0x1d # macro +DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT = 0x1e # macro +DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT = 0x1f # macro +DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK = 0x00000001 # macro +DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK = 0x00000002 # macro +DB_DEBUG3__FORCE_DB_IS_GOOD_MASK = 0x00000004 # macro +DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK = 0x00000008 # macro +DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK = 0x00000010 # macro +DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK = 0x00000020 # macro +DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK = 0x00000040 # macro +DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK = 0x00000100 # macro +DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK = 0x00000400 # macro +DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK = 0x00000800 # macro +DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK = 0x00002000 # macro +DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK = 0x00004000 # macro +DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK = 0x00008000 # macro +DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK = 0x00010000 # macro +DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK = 0x00020000 # macro +DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK = 0x00080000 # macro +DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK = 0x00100000 # macro +DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK = 0x00200000 # macro +DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK = 0x00400000 # macro +DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK = 0x00800000 # macro +DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK = 0x01000000 # macro +DB_DEBUG3__DISABLE_DI_DT_STALL_MASK = 0x02000000 # macro +DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK = 0x04000000 # macro +DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK = 0x08000000 # macro +DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK = 0x10000000 # macro +DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK = 0x20000000 # macro +DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK = 0x40000000 # macro +DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK = 0x80000000 # macro +DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT = 0x0 # macro +DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT = 0x1 # macro +DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT = 0x2 # macro +DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT = 0x3 # macro +DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT = 0x4 # macro +DB_DEBUG4__DISABLE_SEPARATE_SX_CLK__SHIFT = 0x5 # macro +DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT = 0x6 # macro +DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT = 0x7 # macro +DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK__SHIFT = 0x8 # macro +DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT = 0x9 # macro +DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT = 0xa # macro +DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT = 0xb # macro +DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT = 0xc # macro +DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT = 0xd # macro +DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT = 0xe # macro +DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT = 0xf # macro +DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT = 0x10 # macro +DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT = 0x12 # macro +DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT = 0x13 # macro +DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT = 0x15 # macro +DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT = 0x16 # macro +DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT = 0x18 # macro +DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT = 0x1b # macro +DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT = 0x1c # macro +DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT = 0x1e # macro +DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD__SHIFT = 0x1f # macro +DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK = 0x00000001 # macro +DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK = 0x00000002 # macro +DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK = 0x00000004 # macro +DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK = 0x00000008 # macro +DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK = 0x00000010 # macro +DB_DEBUG4__DISABLE_SEPARATE_SX_CLK_MASK = 0x00000020 # macro +DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK = 0x00000040 # macro +DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK = 0x00000080 # macro +DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK_MASK = 0x00000100 # macro +DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK = 0x00000200 # macro +DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK = 0x00000400 # macro +DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK = 0x00000800 # macro +DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK = 0x00001000 # macro +DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK = 0x00002000 # macro +DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK = 0x00004000 # macro +DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK = 0x00008000 # macro +DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK = 0x00010000 # macro +DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK = 0x00040000 # macro +DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK = 0x00080000 # macro +DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK = 0x00200000 # macro +DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK = 0x00400000 # macro +DB_DEBUG4__WR_MEM_BURST_CTL_MASK = 0x07000000 # macro +DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK = 0x08000000 # macro +DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK = 0x10000000 # macro +DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK = 0x40000000 # macro +DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD_MASK = 0x80000000 # macro +DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT = 0x0 # macro +DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT = 0x10 # macro +DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK = 0x000000FF # macro +DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK = 0x00FF0000 # macro +DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT = 0x0 # macro +DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT = 0x10 # macro +DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK = 0x000000FF # macro +DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK = 0x00FF0000 # macro +DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT = 0x0 # macro +DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT = 0x10 # macro +DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK = 0x000000FF # macro +DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK = 0x00FF0000 # macro +DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT = 0x0 # macro +DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT = 0x10 # macro +DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK = 0x000000FF # macro +DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK = 0x00FF0000 # macro +DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT = 0x0 # macro +DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT = 0x5 # macro +DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT = 0xa # macro +DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS__SHIFT = 0xd # macro +DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS__SHIFT = 0x12 # macro +DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK = 0x0000001F # macro +DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK = 0x000003E0 # macro +DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK = 0x00001C00 # macro +DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS_MASK = 0x0003E000 # macro +DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS_MASK = 0x007C0000 # macro +DB_WATERMARKS__DEPTH_FREE__SHIFT = 0x0 # macro +DB_WATERMARKS__DEPTH_FLUSH__SHIFT = 0x8 # macro +DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT = 0x10 # macro +DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT = 0x18 # macro +DB_WATERMARKS__DEPTH_FREE_MASK = 0x000000FF # macro +DB_WATERMARKS__DEPTH_FLUSH_MASK = 0x0000FF00 # macro +DB_WATERMARKS__DEPTH_PENDING_FREE_MASK = 0x00FF0000 # macro +DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK = 0xFF000000 # macro +DB_SUBTILE_CONTROL__MSAA1_X__SHIFT = 0x0 # macro +DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT = 0x2 # macro +DB_SUBTILE_CONTROL__MSAA2_X__SHIFT = 0x4 # macro +DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT = 0x6 # macro +DB_SUBTILE_CONTROL__MSAA4_X__SHIFT = 0x8 # macro +DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT = 0xa # macro +DB_SUBTILE_CONTROL__MSAA8_X__SHIFT = 0xc # macro +DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT = 0xe # macro +DB_SUBTILE_CONTROL__MSAA16_X__SHIFT = 0x10 # macro +DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT = 0x12 # macro +DB_SUBTILE_CONTROL__MSAA1_X_MASK = 0x00000003 # macro +DB_SUBTILE_CONTROL__MSAA1_Y_MASK = 0x0000000C # macro +DB_SUBTILE_CONTROL__MSAA2_X_MASK = 0x00000030 # macro +DB_SUBTILE_CONTROL__MSAA2_Y_MASK = 0x000000C0 # macro +DB_SUBTILE_CONTROL__MSAA4_X_MASK = 0x00000300 # macro +DB_SUBTILE_CONTROL__MSAA4_Y_MASK = 0x00000C00 # macro +DB_SUBTILE_CONTROL__MSAA8_X_MASK = 0x00003000 # macro +DB_SUBTILE_CONTROL__MSAA8_Y_MASK = 0x0000C000 # macro +DB_SUBTILE_CONTROL__MSAA16_X_MASK = 0x00030000 # macro +DB_SUBTILE_CONTROL__MSAA16_Y_MASK = 0x000C0000 # macro +DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT = 0x0 # macro +DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT = 0x8 # macro +DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT = 0x10 # macro +DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT = 0x18 # macro +DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK = 0x000000FF # macro +DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK = 0x0000FF00 # macro +DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK = 0x00FF0000 # macro +DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK = 0xFF000000 # macro +DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT = 0x0 # macro +DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT = 0x8 # macro +DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT = 0x10 # macro +DB_FIFO_DEPTH1__QC_DEPTH__SHIFT = 0x18 # macro +DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK = 0x000000FF # macro +DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK = 0x0000FF00 # macro +DB_FIFO_DEPTH1__MCC_DEPTH_MASK = 0x00FF0000 # macro +DB_FIFO_DEPTH1__QC_DEPTH_MASK = 0xFF000000 # macro +DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT = 0x0 # macro +DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT = 0x8 # macro +DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT = 0x10 # macro +DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT = 0x19 # macro +DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK = 0x000000FF # macro +DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK = 0x0000FF00 # macro +DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK = 0x01FF0000 # macro +DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK = 0xFE000000 # macro +DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT = 0x0 # macro +DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT = 0x8 # macro +DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT = 0xb # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT = 0x11 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT = 0x12 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT = 0x13 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT = 0x14 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT = 0x15 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT = 0x16 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT = 0x17 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT = 0x19 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT = 0x1a # macro +DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT = 0x1c # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE__SHIFT = 0x1d # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT = 0x1e # macro +DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT = 0x1f # macro +DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK = 0x000000FF # macro +DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK = 0x00000700 # macro +DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK = 0x0000F800 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK = 0x00020000 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK = 0x00040000 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK = 0x00080000 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK = 0x00100000 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK = 0x00200000 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK = 0x00400000 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK = 0x00800000 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK = 0x02000000 # macro +DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK = 0x04000000 # macro +DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK = 0x10000000 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE_MASK = 0x20000000 # macro +DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK = 0x40000000 # macro +DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK = 0x80000000 # macro +DB_RING_CONTROL__COUNTER_CONTROL__SHIFT = 0x0 # macro +DB_RING_CONTROL__COUNTER_CONTROL_MASK = 0x00000003 # macro +DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT = 0x0 # macro +DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT = 0x8 # macro +DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT = 0x10 # macro +DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT = 0x18 # macro +DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK = 0x00000007 # macro +DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK = 0x00000700 # macro +DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK = 0x00070000 # macro +DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK = 0x07000000 # macro +DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT = 0x0 # macro +DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH__SHIFT = 0x8 # macro +DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH__SHIFT = 0x10 # macro +DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT = 0x18 # macro +DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK = 0x000000FF # macro +DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH_MASK = 0x0000FF00 # macro +DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH_MASK = 0x00FF0000 # macro +DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK = 0xFF000000 # macro +DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT__SHIFT = 0x0 # macro +DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT__SHIFT = 0x1 # macro +DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT__SHIFT = 0x2 # macro +DB_DEBUG6__OREO_TRANSITION_EVENT_ALL__SHIFT = 0x3 # macro +DB_DEBUG6__OREO_TRANSITION_EVENT_ID__SHIFT = 0x4 # macro +DB_DEBUG6__OREO_TRANSITION_EVENT_EN__SHIFT = 0xa # macro +DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL__SHIFT = 0xb # macro +DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL__SHIFT = 0xc # macro +DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID__SHIFT = 0xd # macro +DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL__SHIFT = 0x10 # macro +DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT__SHIFT = 0x18 # macro +DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK__SHIFT = 0x19 # macro +DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX__SHIFT = 0x1a # macro +DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC__SHIFT = 0x1b # macro +DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT_MASK = 0x00000001 # macro +DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT_MASK = 0x00000002 # macro +DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT_MASK = 0x00000004 # macro +DB_DEBUG6__OREO_TRANSITION_EVENT_ALL_MASK = 0x00000008 # macro +DB_DEBUG6__OREO_TRANSITION_EVENT_ID_MASK = 0x000003F0 # macro +DB_DEBUG6__OREO_TRANSITION_EVENT_EN_MASK = 0x00000400 # macro +DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL_MASK = 0x00000800 # macro +DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL_MASK = 0x00001000 # macro +DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID_MASK = 0x00006000 # macro +DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL_MASK = 0x00FF0000 # macro +DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT_MASK = 0x01000000 # macro +DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK_MASK = 0x02000000 # macro +DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX_MASK = 0x04000000 # macro +DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC_MASK = 0x08000000 # macro +DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT = 0x0 # macro +DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT = 0x1 # macro +DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT = 0x2 # macro +DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT = 0x3 # macro +DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT = 0x4 # macro +DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT = 0x8 # macro +DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT = 0x18 # macro +DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK = 0x00000001 # macro +DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK = 0x00000002 # macro +DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK = 0x00000004 # macro +DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK = 0x00000008 # macro +DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK = 0x00000010 # macro +DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK = 0x00000F00 # macro +DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK = 0x7F000000 # macro +DB_DEBUG7__SPARE_BITS__SHIFT = 0x0 # macro +DB_DEBUG7__SPARE_BITS_MASK = 0xFFFFFFFF # macro +DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD__SHIFT = 0x0 # macro +DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION__SHIFT = 0x1 # macro +DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT__SHIFT = 0x2 # macro +DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT__SHIFT = 0x3 # macro +DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT = 0x4 # macro +DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT = 0x5 # macro +DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX__SHIFT = 0x6 # macro +DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT = 0x7 # macro +DB_DEBUG5__DISABLE_VRS_1X2_2XAA__SHIFT = 0x8 # macro +DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT = 0x9 # macro +DB_DEBUG5__DISABLE_HTILE_HARVESTING__SHIFT = 0xa # macro +DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK__SHIFT = 0xb # macro +DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH__SHIFT = 0xc # macro +DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT = 0xd # macro +DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT = 0xe # macro +DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK__SHIFT = 0xf # macro +DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT = 0x10 # macro +DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT = 0x11 # macro +DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT = 0x12 # macro +DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT = 0x13 # macro +DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT = 0x14 # macro +DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT = 0x15 # macro +DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT = 0x16 # macro +DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE__SHIFT = 0x17 # macro +DB_DEBUG5__SPARE_BITS__SHIFT = 0x18 # macro +DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD_MASK = 0x00000001 # macro +DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION_MASK = 0x00000002 # macro +DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT_MASK = 0x00000004 # macro +DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT_MASK = 0x00000008 # macro +DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK = 0x00000010 # macro +DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK = 0x00000020 # macro +DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX_MASK = 0x00000040 # macro +DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK = 0x00000080 # macro +DB_DEBUG5__DISABLE_VRS_1X2_2XAA_MASK = 0x00000100 # macro +DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK = 0x00000200 # macro +DB_DEBUG5__DISABLE_HTILE_HARVESTING_MASK = 0x00000400 # macro +DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK_MASK = 0x00000800 # macro +DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH_MASK = 0x00001000 # macro +DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK = 0x00002000 # macro +DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK = 0x00004000 # macro +DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK_MASK = 0x00008000 # macro +DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK = 0x00010000 # macro +DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK = 0x00020000 # macro +DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK = 0x00040000 # macro +DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK = 0x00080000 # macro +DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK = 0x00100000 # macro +DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK = 0x00200000 # macro +DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK = 0x00400000 # macro +DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE_MASK = 0x00800000 # macro +DB_DEBUG5__SPARE_BITS_MASK = 0xFF000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT = 0x0 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT = 0x1 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT = 0x2 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT = 0x3 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT = 0x4 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT = 0x5 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT = 0x6 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT = 0x7 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT = 0x8 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT = 0x9 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT = 0xa # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT = 0xb # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT = 0xc # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT = 0xd # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT = 0xe # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT = 0xf # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT = 0x10 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT = 0x11 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT = 0x12 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT = 0x13 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT = 0x14 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT = 0x15 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT = 0x16 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT = 0x17 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT = 0x18 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT = 0x19 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT = 0x1a # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27__SHIFT = 0x1b # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28__SHIFT = 0x1c # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29__SHIFT = 0x1d # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30__SHIFT = 0x1e # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31__SHIFT = 0x1f # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK = 0x00000001 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK = 0x00000002 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK = 0x00000004 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK = 0x00000008 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK = 0x00000010 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK = 0x00000020 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK = 0x00000040 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK = 0x00000080 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK = 0x00000100 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK = 0x00000200 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK = 0x00000400 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK = 0x00000800 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK = 0x00001000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK = 0x00002000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK = 0x00004000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK = 0x00008000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK = 0x00010000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK = 0x00020000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK = 0x00040000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK = 0x00080000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK = 0x00100000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK = 0x00200000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK = 0x00400000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK = 0x00800000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK = 0x01000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK = 0x02000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK = 0x04000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27_MASK = 0x08000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28_MASK = 0x10000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29_MASK = 0x20000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30_MASK = 0x40000000 # macro +DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31_MASK = 0x80000000 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT = 0x0 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE__SHIFT = 0x2 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT = 0x3 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT = 0x4 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT = 0x5 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT = 0x6 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE__SHIFT = 0x7 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE__SHIFT = 0x8 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK = 0x00000001 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE_MASK = 0x00000004 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK = 0x00000008 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK = 0x00000010 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK = 0x00000020 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK = 0x00000040 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE_MASK = 0x00000080 # macro +DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE_MASK = 0x00000100 # macro +DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH__SHIFT = 0x0 # macro +DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH__SHIFT = 0x8 # macro +DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH__SHIFT = 0x10 # macro +DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH__SHIFT = 0x18 # macro +DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH_MASK = 0x000000FF # macro +DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH_MASK = 0x0000FF00 # macro +DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH_MASK = 0x00FF0000 # macro +DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH_MASK = 0xFF000000 # macro +CC_RB_REDUNDANCY__FAILED_RB0__SHIFT = 0x8 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT = 0xc # macro +CC_RB_REDUNDANCY__FAILED_RB1__SHIFT = 0x10 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT = 0x14 # macro +CC_RB_REDUNDANCY__FAILED_RB0_MASK = 0x00000F00 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK = 0x00001000 # macro +CC_RB_REDUNDANCY__FAILED_RB1_MASK = 0x000F0000 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK = 0x00100000 # macro +CC_RB_BACKEND_DISABLE__RESERVED__SHIFT = 0x2 # macro +CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT = 0x4 # macro +CC_RB_BACKEND_DISABLE__RESERVED_MASK = 0x0000000C # macro +CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK = 0xFFFFFFF0 # macro +GB_ADDR_CONFIG__NUM_PIPES__SHIFT = 0x0 # macro +GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +GB_ADDR_CONFIG__NUM_PKRS__SHIFT = 0x8 # macro +GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT = 0x1a # macro +GB_ADDR_CONFIG__NUM_PIPES_MASK = 0x00000007 # macro +GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +GB_ADDR_CONFIG__NUM_PKRS_MASK = 0x00000700 # macro +GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +GB_BACKEND_MAP__BACKEND_MAP__SHIFT = 0x0 # macro +GB_BACKEND_MAP__BACKEND_MAP_MASK = 0xFFFFFFFF # macro +GB_GPU_ID__GPU_ID__SHIFT = 0x0 # macro +GB_GPU_ID__GPU_ID_MASK = 0x0000000F # macro +CC_RB_DAISY_CHAIN__RB_0__SHIFT = 0x0 # macro +CC_RB_DAISY_CHAIN__RB_1__SHIFT = 0x4 # macro +CC_RB_DAISY_CHAIN__RB_2__SHIFT = 0x8 # macro +CC_RB_DAISY_CHAIN__RB_3__SHIFT = 0xc # macro +CC_RB_DAISY_CHAIN__RB_4__SHIFT = 0x10 # macro +CC_RB_DAISY_CHAIN__RB_5__SHIFT = 0x14 # macro +CC_RB_DAISY_CHAIN__RB_6__SHIFT = 0x18 # macro +CC_RB_DAISY_CHAIN__RB_7__SHIFT = 0x1c # macro +CC_RB_DAISY_CHAIN__RB_0_MASK = 0x0000000F # macro +CC_RB_DAISY_CHAIN__RB_1_MASK = 0x000000F0 # macro +CC_RB_DAISY_CHAIN__RB_2_MASK = 0x00000F00 # macro +CC_RB_DAISY_CHAIN__RB_3_MASK = 0x0000F000 # macro +CC_RB_DAISY_CHAIN__RB_4_MASK = 0x000F0000 # macro +CC_RB_DAISY_CHAIN__RB_5_MASK = 0x00F00000 # macro +CC_RB_DAISY_CHAIN__RB_6_MASK = 0x0F000000 # macro +CC_RB_DAISY_CHAIN__RB_7_MASK = 0xF0000000 # macro +GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT = 0x0 # macro +GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT = 0x8 # macro +GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT = 0x1a # macro +GB_ADDR_CONFIG_READ__NUM_PIPES_MASK = 0x00000007 # macro +GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +GB_ADDR_CONFIG_READ__NUM_PKRS_MASK = 0x00000700 # macro +GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2__SHIFT = 0x0 # macro +CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM__SHIFT = 0x3 # macro +CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE__SHIFT = 0x5 # macro +CB_HW_CONTROL_4__SPARE_10__SHIFT = 0x6 # macro +CB_HW_CONTROL_4__SPARE_11__SHIFT = 0x7 # macro +CB_HW_CONTROL_4__SPARE_12__SHIFT = 0x8 # macro +CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT = 0x9 # macro +CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD__SHIFT = 0xa # macro +CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD__SHIFT = 0xd # macro +CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD__SHIFT = 0x10 # macro +CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD__SHIFT = 0x11 # macro +CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD__SHIFT = 0x12 # macro +CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2_MASK = 0x00000007 # macro +CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM_MASK = 0x00000018 # macro +CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE_MASK = 0x00000020 # macro +CB_HW_CONTROL_4__SPARE_10_MASK = 0x00000040 # macro +CB_HW_CONTROL_4__SPARE_11_MASK = 0x00000080 # macro +CB_HW_CONTROL_4__SPARE_12_MASK = 0x00000100 # macro +CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK = 0x00000200 # macro +CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD_MASK = 0x00001C00 # macro +CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD_MASK = 0x0000E000 # macro +CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD_MASK = 0x00010000 # macro +CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD_MASK = 0x00020000 # macro +CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD_MASK = 0x00040000 # macro +CB_HW_CONTROL_3__SPARE_5__SHIFT = 0x0 # macro +CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT = 0x1 # macro +CB_HW_CONTROL_3__SPARE_6__SHIFT = 0x2 # macro +CB_HW_CONTROL_3__SPARE_7__SHIFT = 0x3 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT = 0x4 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT = 0x5 # macro +CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT = 0x6 # macro +CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT = 0x7 # macro +CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT = 0xb # macro +CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT = 0xc # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT = 0xd # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT = 0xe # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT = 0xf # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT = 0x10 # macro +CB_HW_CONTROL_3__SPARE_8__SHIFT = 0x11 # macro +CB_HW_CONTROL_3__SPARE_9__SHIFT = 0x12 # macro +CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT__SHIFT = 0x14 # macro +CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x15 # macro +CB_HW_CONTROL_3__SPARE_5_MASK = 0x00000001 # macro +CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK = 0x00000002 # macro +CB_HW_CONTROL_3__SPARE_6_MASK = 0x00000004 # macro +CB_HW_CONTROL_3__SPARE_7_MASK = 0x00000008 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK = 0x00000010 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK = 0x00000020 # macro +CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK = 0x00000040 # macro +CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK = 0x00000080 # macro +CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK = 0x00000800 # macro +CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK = 0x00001000 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK = 0x00002000 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK = 0x00004000 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK = 0x00008000 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK = 0x00010000 # macro +CB_HW_CONTROL_3__SPARE_8_MASK = 0x00020000 # macro +CB_HW_CONTROL_3__SPARE_9_MASK = 0x00040000 # macro +CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT_MASK = 0x00100000 # macro +CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00200000 # macro +CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT = 0x0 # macro +CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT = 0x1 # macro +CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX__SHIFT = 0x2 # macro +CB_HW_CONTROL__RMI_CREDITS__SHIFT = 0x6 # macro +CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES__SHIFT = 0xc # macro +CB_HW_CONTROL__FORCE_FEA_HIGH__SHIFT = 0xf # macro +CB_HW_CONTROL__FORCE_EVICT_ALL_VALID__SHIFT = 0x10 # macro +CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING__SHIFT = 0x11 # macro +CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT = 0x13 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT = 0x15 # macro +CB_HW_CONTROL__SPARE_2__SHIFT = 0x16 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT = 0x18 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT = 0x19 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x1a # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT = 0x1b # macro +CB_HW_CONTROL__SPARE_3__SHIFT = 0x1d # macro +CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT = 0x1e # macro +CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT = 0x1f # macro +CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK = 0x00000001 # macro +CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK = 0x00000002 # macro +CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX_MASK = 0x00000004 # macro +CB_HW_CONTROL__RMI_CREDITS_MASK = 0x00000FC0 # macro +CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES_MASK = 0x00007000 # macro +CB_HW_CONTROL__FORCE_FEA_HIGH_MASK = 0x00008000 # macro +CB_HW_CONTROL__FORCE_EVICT_ALL_VALID_MASK = 0x00010000 # macro +CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING_MASK = 0x00020000 # macro +CB_HW_CONTROL__FORCE_NEEDS_DST_MASK = 0x00080000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK = 0x00200000 # macro +CB_HW_CONTROL__SPARE_2_MASK = 0x00400000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK = 0x01000000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK = 0x02000000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK = 0x04000000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK = 0x08000000 # macro +CB_HW_CONTROL__SPARE_3_MASK = 0x20000000 # macro +CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK = 0x40000000 # macro +CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK = 0x80000000 # macro +CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT = 0x0 # macro +CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK = 0x0000003F # macro +CB_HW_CONTROL_2__SPARE_4__SHIFT = 0x0 # macro +CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT = 0x8 # macro +CB_HW_CONTROL_2__SPARE__SHIFT = 0xe # macro +CB_HW_CONTROL_2__SPARE_4_MASK = 0x000000FF # macro +CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK = 0x00003F00 # macro +CB_HW_CONTROL_2__SPARE_MASK = 0xFFFFC000 # macro +CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH__SHIFT = 0x0 # macro +CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x5 # macro +CB_DCC_CONFIG__SPARE_13__SHIFT = 0x6 # macro +CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT = 0x7 # macro +CB_DCC_CONFIG__SPARE_14__SHIFT = 0x8 # macro +CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT = 0x10 # macro +CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT = 0x19 # macro +CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH_MASK = 0x0000001F # macro +CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000020 # macro +CB_DCC_CONFIG__SPARE_13_MASK = 0x00000040 # macro +CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK = 0x00000080 # macro +CB_DCC_CONFIG__SPARE_14_MASK = 0x0000FF00 # macro +CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK = 0x01FF0000 # macro +CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK = 0xFE000000 # macro +CB_HW_MEM_ARBITER_RD__MODE__SHIFT = 0x0 # macro +CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT = 0x2 # macro +CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT = 0x6 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT = 0xa # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT = 0xc # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT = 0xe # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT = 0x10 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT = 0x12 # macro +CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT = 0x13 # macro +CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT = 0x16 # macro +CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT = 0x19 # macro +CB_HW_MEM_ARBITER_RD__MODE_MASK = 0x00000003 # macro +CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK = 0x0000003C # macro +CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK = 0x000003C0 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK = 0x00000C00 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK = 0x00003000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK = 0x0000C000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK = 0x00030000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK = 0x00040000 # macro +CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK = 0x00380000 # macro +CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK = 0x01C00000 # macro +CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK = 0x02000000 # macro +CB_HW_MEM_ARBITER_WR__MODE__SHIFT = 0x0 # macro +CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT = 0x2 # macro +CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT = 0x6 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT = 0xa # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT = 0xc # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT = 0xe # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT = 0x10 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT = 0x12 # macro +CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT = 0x13 # macro +CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT = 0x16 # macro +CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT = 0x19 # macro +CB_HW_MEM_ARBITER_WR__MODE_MASK = 0x00000003 # macro +CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK = 0x0000003C # macro +CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK = 0x000003C0 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK = 0x00000C00 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK = 0x00003000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK = 0x0000C000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK = 0x00030000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK = 0x00040000 # macro +CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK = 0x00380000 # macro +CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK = 0x01C00000 # macro +CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK = 0x02000000 # macro +CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG__SHIFT = 0x0 # macro +CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG_MASK = 0x000FFFFF # macro +CHICKEN_BITS__SPARE__SHIFT = 0x0 # macro +CHICKEN_BITS__SPARE_MASK = 0xFFFFFFFF # macro +CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT__SHIFT = 0x0 # macro +CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT__SHIFT = 0x8 # macro +CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT = 0x10 # macro +CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT = 0x18 # macro +CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT_MASK = 0x000000FF # macro +CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT_MASK = 0x0000FF00 # macro +CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK = 0x00FF0000 # macro +CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK = 0xFF000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT = 0x0 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT = 0x3 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT = 0x6 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT = 0x9 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK = 0x00000007 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK = 0x00000038 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT = 0x0 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT = 0x3 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT = 0x6 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT = 0x9 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK = 0x00000007 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK = 0x00000038 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT = 0x0 # macro +GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT = 0x3 # macro +GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT = 0x6 # macro +GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT = 0x9 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT = 0xc # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT = 0x14 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT = 0x1b # macro +GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK = 0x00000007 # macro +GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK = 0x00000038 # macro +GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK = 0x0003F000 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK = 0x07F00000 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK = 0x78000000 # macro +GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT = 0x0 # macro +GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT = 0x3 # macro +GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT = 0x6 # macro +GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT = 0x9 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT = 0xc # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT = 0x14 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT = 0x1b # macro +GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK = 0x00000007 # macro +GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK = 0x00000038 # macro +GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK = 0x0003F000 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK = 0x07F00000 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK = 0x78000000 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT = 0x0 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT = 0x4 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT = 0x8 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT = 0xc # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT = 0x10 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT = 0x13 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT = 0x16 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT = 0x19 # macro +GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT = 0x1c # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK = 0x0000000F # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK = 0x000000F0 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK = 0x00000F00 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK = 0x0000F000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK = 0x00070000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK = 0x00380000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK = 0x01C00000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK = 0x0E000000 # macro +GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK = 0x10000000 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT = 0x0 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT = 0x4 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT = 0x8 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT = 0xc # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT = 0x10 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT = 0x13 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT = 0x16 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT = 0x19 # macro +GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT = 0x1c # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK = 0x0000000F # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK = 0x000000F0 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK = 0x00000F00 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK = 0x0000F000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK = 0x00070000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK = 0x00380000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK = 0x01C00000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK = 0x0E000000 # macro +GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK = 0x10000000 # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT = 0x0 # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT = 0x8 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT = 0x10 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT = 0x18 # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK = 0x000000FF # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK = 0x0000FF00 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK = 0x00FF0000 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK = 0xFF000000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT = 0x0 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT = 0x4 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT = 0x8 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT = 0xc # macro +GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT = 0x10 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK = 0x0000000F # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK = 0x000000F0 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK = 0x00000F00 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK = 0x0000F000 # macro +GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK = 0x00030000 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT = 0x0 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT = 0x4 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT = 0x8 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT = 0xc # macro +GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT = 0x10 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK = 0x0000000F # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK = 0x000000F0 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK = 0x00000F00 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK = 0x0000F000 # macro +GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK = 0x00030000 # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT = 0x0 # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT = 0x8 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT = 0x10 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT = 0x18 # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK = 0x000000FF # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK = 0x0000FF00 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK = 0x00FF0000 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK = 0xFF000000 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT = 0x1 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT = 0x2 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT = 0x4 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT = 0x5 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT = 0x7 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT = 0xa # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT = 0xb # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT = 0xc # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT = 0xd # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT = 0xe # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT = 0xf # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT = 0x11 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT = 0x12 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT = 0x13 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT = 0x14 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT = 0x15 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT = 0x16 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT = 0x17 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT = 0x19 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT = 0x1a # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT = 0x1b # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT = 0x1c # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT = 0x1d # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT = 0x1e # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT = 0x1f # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK = 0x00000001 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK = 0x00000002 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK = 0x00000004 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK = 0x00000008 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK = 0x00000010 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK = 0x00000020 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK = 0x00000040 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK = 0x00000080 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK = 0x00000100 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK = 0x00000200 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK = 0x00000400 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK = 0x00000800 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK = 0x00001000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK = 0x00002000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK = 0x00004000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK = 0x00008000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK = 0x00010000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK = 0x00020000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK = 0x00040000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK = 0x00080000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK = 0x00100000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK = 0x00200000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK = 0x00400000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK = 0x00800000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK = 0x01000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK = 0x02000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK = 0x04000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK = 0x08000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK = 0x10000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK = 0x20000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK = 0x40000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK = 0x80000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT = 0x1 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT = 0x2 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT = 0x4 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT = 0x5 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT = 0x7 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT = 0xa # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT = 0xb # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT = 0xc # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT = 0xd # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT = 0xe # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT = 0xf # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT = 0x11 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT = 0x12 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT = 0x13 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT = 0x14 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT = 0x15 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT = 0x16 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT = 0x17 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT = 0x19 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT = 0x1a # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT = 0x1b # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT = 0x1c # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT = 0x1d # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT = 0x1e # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT = 0x1f # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK = 0x00000001 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK = 0x00000002 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK = 0x00000004 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK = 0x00000008 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK = 0x00000010 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK = 0x00000020 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK = 0x00000040 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK = 0x00000080 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK = 0x00000100 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK = 0x00000200 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK = 0x00000400 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK = 0x00000800 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK = 0x00001000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK = 0x00002000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK = 0x00004000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK = 0x00008000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK = 0x00010000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK = 0x00020000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK = 0x00040000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK = 0x00080000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK = 0x00100000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK = 0x00200000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK = 0x00400000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK = 0x00800000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK = 0x01000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK = 0x02000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK = 0x04000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK = 0x08000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK = 0x10000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK = 0x20000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK = 0x40000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK = 0x80000000 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT = 0x0 # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT = 0x5 # macro +GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT = 0xa # macro +GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT = 0xf # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT = 0x11 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT = 0x12 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT = 0x13 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT = 0x14 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT = 0x15 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT = 0x16 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT = 0x17 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT = 0x18 # macro +GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT = 0x19 # macro +GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT = 0x1a # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT = 0x1b # macro +GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT = 0x1c # macro +GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT = 0x1d # macro +GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT = 0x1e # macro +GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT = 0x1f # macro +GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK = 0x0000001F # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK = 0x000003E0 # macro +GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK = 0x00007C00 # macro +GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK = 0x00018000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK = 0x00020000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK = 0x00040000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK = 0x00080000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK = 0x00100000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK = 0x00200000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK = 0x00400000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK = 0x00800000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK = 0x01000000 # macro +GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK = 0x02000000 # macro +GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK = 0x04000000 # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK = 0x08000000 # macro +GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK = 0x10000000 # macro +GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK = 0x20000000 # macro +GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK = 0x40000000 # macro +GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK = 0x80000000 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT = 0x0 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT = 0x4 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT = 0x8 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT = 0xc # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT = 0x10 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT = 0x14 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT = 0x18 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT = 0x1c # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK = 0x0000000F # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK = 0x000000F0 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK = 0x00000F00 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK = 0x0000F000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK = 0x000F0000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK = 0x00F00000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK = 0x0F000000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK = 0xF0000000 # macro +GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT = 0x0 # macro +GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT = 0x8 # macro +GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT = 0x10 # macro +GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT = 0x18 # macro +GCEA_SDP_CREDITS__TAG_LIMIT_MASK = 0x000000FF # macro +GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK = 0x00007F00 # macro +GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK = 0x007F0000 # macro +GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK = 0x3F000000 # macro +GCEA_SDP_TAG_RESERVE0__VC0__SHIFT = 0x0 # macro +GCEA_SDP_TAG_RESERVE0__VC1__SHIFT = 0x8 # macro +GCEA_SDP_TAG_RESERVE0__VC2__SHIFT = 0x10 # macro +GCEA_SDP_TAG_RESERVE0__VC3__SHIFT = 0x18 # macro +GCEA_SDP_TAG_RESERVE0__VC0_MASK = 0x000000FF # macro +GCEA_SDP_TAG_RESERVE0__VC1_MASK = 0x0000FF00 # macro +GCEA_SDP_TAG_RESERVE0__VC2_MASK = 0x00FF0000 # macro +GCEA_SDP_TAG_RESERVE0__VC3_MASK = 0xFF000000 # macro +GCEA_SDP_TAG_RESERVE1__VC4__SHIFT = 0x0 # macro +GCEA_SDP_TAG_RESERVE1__VC5__SHIFT = 0x8 # macro +GCEA_SDP_TAG_RESERVE1__VC6__SHIFT = 0x10 # macro +GCEA_SDP_TAG_RESERVE1__VC7__SHIFT = 0x18 # macro +GCEA_SDP_TAG_RESERVE1__VC4_MASK = 0x000000FF # macro +GCEA_SDP_TAG_RESERVE1__VC5_MASK = 0x0000FF00 # macro +GCEA_SDP_TAG_RESERVE1__VC6_MASK = 0x00FF0000 # macro +GCEA_SDP_TAG_RESERVE1__VC7_MASK = 0xFF000000 # macro +GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT = 0x0 # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT = 0x1 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT = 0x2 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT = 0x3 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT = 0x4 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT = 0x5 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT = 0x6 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT = 0x7 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT = 0x8 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT = 0x9 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT = 0xa # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT = 0xb # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT = 0xc # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT = 0xd # macro +GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT = 0xe # macro +GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT = 0xf # macro +GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT = 0x11 # macro +GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT = 0x13 # macro +GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT = 0x15 # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT = 0x1a # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT = 0x1b # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT = 0x1c # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT = 0x1d # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT = 0x1e # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT = 0x1f # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK = 0x00000001 # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK = 0x00000002 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK = 0x00000004 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK = 0x00000008 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK = 0x00000010 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK = 0x00000020 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK = 0x00000040 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK = 0x00000080 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK = 0x00000100 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK = 0x00000200 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK = 0x00000400 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK = 0x00000800 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK = 0x00001000 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK = 0x00002000 # macro +GCEA_MISC__EARLY_SDP_ORIGDATA_MASK = 0x00004000 # macro +GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK = 0x00018000 # macro +GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK = 0x00060000 # macro +GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK = 0x00180000 # macro +GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK = 0x03E00000 # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK = 0x04000000 # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK = 0x08000000 # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK = 0x10000000 # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK = 0x20000000 # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK = 0x40000000 # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK = 0x80000000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT = 0x0 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT = 0x1 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT = 0x2 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT = 0x3 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT = 0x4 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT = 0x5 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT = 0x6 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT = 0x7 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT = 0x8 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT = 0x9 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT = 0xa # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT = 0xb # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT = 0xc # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT = 0xd # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT = 0xe # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT = 0x16 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK = 0x00000001 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK = 0x00000002 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK = 0x00000004 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK = 0x00000008 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK = 0x00000010 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK = 0x00000020 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK = 0x00000040 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK = 0x00000080 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK = 0x00000100 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK = 0x00000200 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK = 0x00000400 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK = 0x00000800 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK = 0x00001000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK = 0x00002000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK = 0x003FC000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK = 0x3FC00000 # macro +GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE__SHIFT = 0x0 # macro +GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY__SHIFT = 0x1 # macro +GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY__SHIFT = 0x2 # macro +GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT__SHIFT = 0x3 # macro +GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT__SHIFT = 0x6 # macro +GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE__SHIFT = 0x9 # macro +GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE__SHIFT = 0xf # macro +GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP__SHIFT = 0x12 # macro +GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE__SHIFT = 0x13 # macro +GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE__SHIFT = 0x14 # macro +GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER__SHIFT = 0x15 # macro +GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE__SHIFT = 0x16 # macro +GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE__SHIFT = 0x17 # macro +GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT = 0x18 # macro +GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE_MASK = 0x00000001 # macro +GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY_MASK = 0x00000002 # macro +GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY_MASK = 0x00000004 # macro +GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT_MASK = 0x00000038 # macro +GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT_MASK = 0x000001C0 # macro +GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE_MASK = 0x00007E00 # macro +GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE_MASK = 0x00038000 # macro +GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP_MASK = 0x00040000 # macro +GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE_MASK = 0x00080000 # macro +GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE_MASK = 0x00100000 # macro +GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER_MASK = 0x00200000 # macro +GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE_MASK = 0x00400000 # macro +GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE_MASK = 0x00800000 # macro +GCEA_MAM_CTRL2__RESERVED_FIELD_MASK = 0xFF000000 # macro +GCEA_MAM_CTRL__MAM_DISABLE__SHIFT = 0x0 # macro +GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE__SHIFT = 0x1 # macro +GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE__SHIFT = 0x2 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN__SHIFT = 0x3 # macro +GCEA_MAM_CTRL__SDMA_UPDT_ARAM__SHIFT = 0x4 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC__SHIFT = 0x5 # macro +GCEA_MAM_CTRL__FLUSH_TRACKER__SHIFT = 0x6 # macro +GCEA_MAM_CTRL__CLEAR_TRACKER__SHIFT = 0x7 # macro +GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT = 0x8 # macro +GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER__SHIFT = 0xc # macro +GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT__SHIFT = 0xd # macro +GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER__SHIFT = 0xe # macro +GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT__SHIFT = 0xf # macro +GCEA_MAM_CTRL__RESERVED_FIELD__SHIFT = 0x10 # macro +GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES__SHIFT = 0x17 # macro +GCEA_MAM_CTRL__ARAM_RB_ADDR_HI__SHIFT = 0x1c # macro +GCEA_MAM_CTRL__MAM_DISABLE_MASK = 0x00000001 # macro +GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE_MASK = 0x00000002 # macro +GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE_MASK = 0x00000004 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN_MASK = 0x00000008 # macro +GCEA_MAM_CTRL__SDMA_UPDT_ARAM_MASK = 0x00000010 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC_MASK = 0x00000020 # macro +GCEA_MAM_CTRL__FLUSH_TRACKER_MASK = 0x00000040 # macro +GCEA_MAM_CTRL__CLEAR_TRACKER_MASK = 0x00000080 # macro +GCEA_MAM_CTRL__SDP_PRIORITY_MASK = 0x00000F00 # macro +GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER_MASK = 0x00001000 # macro +GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT_MASK = 0x00002000 # macro +GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER_MASK = 0x00004000 # macro +GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT_MASK = 0x00008000 # macro +GCEA_MAM_CTRL__RESERVED_FIELD_MASK = 0x007F0000 # macro +GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES_MASK = 0x0F800000 # macro +GCEA_MAM_CTRL__ARAM_RB_ADDR_HI_MASK = 0xF0000000 # macro +GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT = 0x0 # macro +GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT = 0x2 # macro +GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT = 0x4 # macro +GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT = 0x6 # macro +GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT = 0x8 # macro +GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT = 0xa # macro +GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT = 0xc # macro +GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT = 0xe # macro +GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT = 0x10 # macro +GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT = 0x12 # macro +GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT = 0x14 # macro +GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT = 0x16 # macro +GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT = 0x18 # macro +GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT = 0x1a # macro +GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT = 0x1c # macro +GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT = 0x1e # macro +GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK = 0x00000003 # macro +GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK = 0x0000000C # macro +GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK = 0x00000030 # macro +GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK = 0x000000C0 # macro +GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK = 0x00000300 # macro +GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK = 0x00000C00 # macro +GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK = 0x00003000 # macro +GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK = 0x0000C000 # macro +GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK = 0x00030000 # macro +GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK = 0x000C0000 # macro +GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK = 0x00300000 # macro +GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK = 0x00C00000 # macro +GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK = 0x03000000 # macro +GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK = 0x0C000000 # macro +GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK = 0x30000000 # macro +GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK = 0xC0000000 # macro +GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT = 0x0 # macro +GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT = 0x2 # macro +GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT = 0x4 # macro +GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT = 0x6 # macro +GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT = 0x8 # macro +GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT = 0xa # macro +GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT = 0xc # macro +GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT = 0xe # macro +GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT = 0x10 # macro +GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT = 0x12 # macro +GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT = 0x14 # macro +GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT = 0x16 # macro +GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT = 0x18 # macro +GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT = 0x1a # macro +GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT = 0x1c # macro +GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT = 0x1e # macro +GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK = 0x00000003 # macro +GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK = 0x0000000C # macro +GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK = 0x00000030 # macro +GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK = 0x000000C0 # macro +GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK = 0x00000300 # macro +GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK = 0x00000C00 # macro +GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK = 0x00003000 # macro +GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK = 0x0000C000 # macro +GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK = 0x00030000 # macro +GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK = 0x000C0000 # macro +GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK = 0x00300000 # macro +GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK = 0x00C00000 # macro +GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK = 0x03000000 # macro +GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK = 0x0C000000 # macro +GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK = 0x30000000 # macro +GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK = 0xC0000000 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT = 0x15 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x17 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK = 0x00600000 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK = 0x00800000 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT = 0x1a # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +GCEA_DSM_CNTL2__INJECT_DELAY_MASK = 0xFC000000 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT = 0x0 # macro +GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT = 0x6 # macro +GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT = 0x8 # macro +GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT = 0xe # macro +GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT = 0x10 # macro +GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT = 0x16 # macro +GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT = 0x18 # macro +GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT = 0x1e # macro +GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK = 0x0000003F # macro +GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK = 0x000000C0 # macro +GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK = 0x00003F00 # macro +GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK = 0x0000C000 # macro +GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK = 0x003F0000 # macro +GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK = 0x00C00000 # macro +GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK = 0x3F000000 # macro +GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK = 0xC0000000 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT = 0x0 # macro +GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT = 0x4 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT = 0x8 # macro +GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT = 0xc # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT = 0x10 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT = 0x13 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT = 0x14 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT = 0x17 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK = 0x0000000F # macro +GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK = 0x000000F0 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK = 0x00000F00 # macro +GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK = 0x0000F000 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK = 0x00070000 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK = 0x00080000 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK = 0x00700000 # macro +GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK = 0x00800000 # macro +GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT = 0x0 # macro +GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT = 0x5 # macro +GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK = 0x0000001F # macro +GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK = 0x00000020 # macro +GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT = 0x0 # macro +GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT = 0x1 # macro +GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT = 0x2 # macro +GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT = 0x3 # macro +GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT = 0x4 # macro +GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT = 0x5 # macro +GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT = 0x6 # macro +GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT = 0x7 # macro +GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT = 0x8 # macro +GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT = 0x9 # macro +GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT = 0xa # macro +GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT = 0xb # macro +GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT = 0xc # macro +GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT = 0xd # macro +GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT = 0xe # macro +GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT = 0xf # macro +GCEA_PROBE_MAP__INTLV_SIZE__SHIFT = 0x10 # macro +GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK = 0x00000001 # macro +GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK = 0x00000002 # macro +GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK = 0x00000004 # macro +GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK = 0x00000008 # macro +GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK = 0x00000010 # macro +GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK = 0x00000020 # macro +GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK = 0x00000040 # macro +GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK = 0x00000080 # macro +GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK = 0x00000100 # macro +GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK = 0x00000200 # macro +GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK = 0x00000400 # macro +GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK = 0x00000800 # macro +GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK = 0x00001000 # macro +GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK = 0x00002000 # macro +GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK = 0x00004000 # macro +GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK = 0x00008000 # macro +GCEA_PROBE_MAP__INTLV_SIZE_MASK = 0x00030000 # macro +GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT = 0x0 # macro +GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT = 0x4 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xb # macro +GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xc # macro +GCEA_ERR_STATUS__FUE_FLAG__SHIFT = 0xd # macro +GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT = 0xe # macro +GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT = 0xf # macro +GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT = 0x10 # macro +GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT = 0x11 # macro +GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK = 0x0000000F # macro +GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK = 0x000000F0 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00000800 # macro +GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00001000 # macro +GCEA_ERR_STATUS__FUE_FLAG_MASK = 0x00002000 # macro +GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK = 0x00004000 # macro +GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK = 0x00008000 # macro +GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK = 0x00010000 # macro +GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK = 0x00020000 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT = 0x0 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT = 0x1 # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT = 0x2 # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT = 0x7 # macro +GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT = 0xc # macro +GCEA_MISC2__BLOCK_REQUESTS__SHIFT = 0xd # macro +GCEA_MISC2__REQUESTS_BLOCKED__SHIFT = 0xe # macro +GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT = 0xf # macro +GCEA_MISC2__LINKMGR_CRBUSY_MASK__SHIFT = 0x10 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK = 0x00000001 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK = 0x00000002 # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK = 0x0000007C # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK = 0x00000F80 # macro +GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK = 0x00001000 # macro +GCEA_MISC2__BLOCK_REQUESTS_MASK = 0x00002000 # macro +GCEA_MISC2__REQUESTS_BLOCKED_MASK = 0x00004000 # macro +GCEA_MISC2__FGCLKEN_OVERRIDE_MASK = 0x00008000 # macro +GCEA_MISC2__LINKMGR_CRBUSY_MASK_MASK = 0x00010000 # macro +GCEA_RRET_MEM_RESERVE__VC0__SHIFT = 0x0 # macro +GCEA_RRET_MEM_RESERVE__VC1__SHIFT = 0x4 # macro +GCEA_RRET_MEM_RESERVE__VC2__SHIFT = 0x8 # macro +GCEA_RRET_MEM_RESERVE__VC3__SHIFT = 0xc # macro +GCEA_RRET_MEM_RESERVE__VC4__SHIFT = 0x10 # macro +GCEA_RRET_MEM_RESERVE__VC5__SHIFT = 0x14 # macro +GCEA_RRET_MEM_RESERVE__VC6__SHIFT = 0x18 # macro +GCEA_RRET_MEM_RESERVE__VC7__SHIFT = 0x1c # macro +GCEA_RRET_MEM_RESERVE__VC0_MASK = 0x0000000F # macro +GCEA_RRET_MEM_RESERVE__VC1_MASK = 0x000000F0 # macro +GCEA_RRET_MEM_RESERVE__VC2_MASK = 0x00000F00 # macro +GCEA_RRET_MEM_RESERVE__VC3_MASK = 0x0000F000 # macro +GCEA_RRET_MEM_RESERVE__VC4_MASK = 0x000F0000 # macro +GCEA_RRET_MEM_RESERVE__VC5_MASK = 0x00F00000 # macro +GCEA_RRET_MEM_RESERVE__VC6_MASK = 0x0F000000 # macro +GCEA_RRET_MEM_RESERVE__VC7_MASK = 0xF0000000 # macro +GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT = 0x0 # macro +GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT = 0x2 # macro +GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT = 0x4 # macro +GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT = 0x6 # macro +GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT = 0x8 # macro +GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT = 0xa # macro +GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT = 0xc # macro +GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT = 0xe # macro +GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT = 0x10 # macro +GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT = 0x12 # macro +GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT = 0x14 # macro +GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT = 0x16 # macro +GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT = 0x18 # macro +GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT = 0x1a # macro +GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT__SHIFT = 0x1c # macro +GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT = 0x1e # macro +GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK = 0x00000003 # macro +GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK = 0x0000000C # macro +GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK = 0x00000030 # macro +GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK = 0x000000C0 # macro +GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK = 0x00000300 # macro +GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK = 0x00000C00 # macro +GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK = 0x00003000 # macro +GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK = 0x0000C000 # macro +GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK = 0x00030000 # macro +GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK = 0x000C0000 # macro +GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK = 0x00300000 # macro +GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK = 0x00C00000 # macro +GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK = 0x03000000 # macro +GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK = 0x0C000000 # macro +GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT_MASK = 0x30000000 # macro +GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK = 0xC0000000 # macro +GCEA_SDP_ENABLE__ENABLE__SHIFT = 0x0 # macro +GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST__SHIFT = 0x1 # macro +GCEA_SDP_ENABLE__ENABLE_MASK = 0x00000001 # macro +GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST_MASK = 0x00000002 # macro +SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT = 0x0 # macro +SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT = 0xa # macro +SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT = 0x10 # macro +SPI_PQEV_CTRL__SCAN_PERIOD_MASK = 0x000003FF # macro +SPI_PQEV_CTRL__QUEUE_DURATION_MASK = 0x0000FC00 # macro +SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK = 0x00FF0000 # macro +SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT = 0x0 # macro +SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT = 0x1 # macro +SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT = 0x5 # macro +SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT = 0x9 # macro +SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT = 0xd # macro +SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT = 0x10 # macro +SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT = 0x13 # macro +SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT = 0x1a # macro +SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT = 0x1d # macro +SPI_EXP_THROTTLE_CTRL__ENABLE_MASK = 0x00000001 # macro +SPI_EXP_THROTTLE_CTRL__PERIOD_MASK = 0x0000001E # macro +SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK = 0x000001E0 # macro +SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK = 0x00001E00 # macro +SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK = 0x0000E000 # macro +SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK = 0x00070000 # macro +SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK = 0x03F80000 # macro +SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK = 0x1C000000 # macro +SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK = 0x20000000 # macro +RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT = 0x0 # macro +RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT = 0x1 # macro +RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT = 0x13 # macro +RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT = 0x15 # macro +RMI_GENERAL_CNTL__BURST_DISABLE_MASK = 0x00000001 # macro +RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK = 0x0001FFFE # macro +RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK = 0x00080000 # macro +RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK = 0x01E00000 # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT = 0x0 # macro +RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT = 0x4 # macro +RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT = 0x6 # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT = 0x8 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT = 0x9 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT = 0xb # macro +RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT = 0xe # macro +RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT = 0xf # macro +RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS__SHIFT = 0x10 # macro +RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS__SHIFT = 0x16 # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK = 0x0000000F # macro +RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK = 0x00000030 # macro +RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK = 0x000000C0 # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK = 0x00000100 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK = 0x00000600 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK = 0x00000800 # macro +RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK = 0x00004000 # macro +RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK = 0x00008000 # macro +RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS_MASK = 0x003F0000 # macro +RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS_MASK = 0x0FC00000 # macro +RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT = 0x0 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT = 0x1 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT = 0x2 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT = 0x3 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT = 0x4 # macro +RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT = 0x5 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_6__SHIFT = 0x6 # macro +RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT = 0x7 # macro +RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT = 0x8 # macro +RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT = 0x9 # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT = 0xa # macro +RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT = 0xb # macro +RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT = 0xc # macro +RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT = 0xd # macro +RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT = 0xe # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT = 0xf # macro +RMI_GENERAL_STATUS__RESERVED_BIT_18__SHIFT = 0x12 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_19__SHIFT = 0x13 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_20__SHIFT = 0x14 # macro +RMI_GENERAL_STATUS__RESERVED_BITS_28_21__SHIFT = 0x15 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_29__SHIFT = 0x1d # macro +RMI_GENERAL_STATUS__RESERVED_BIT_30__SHIFT = 0x1e # macro +RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT = 0x1f # macro +RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK = 0x00000001 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK = 0x00000002 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK = 0x00000004 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK = 0x00000008 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK = 0x00000010 # macro +RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK = 0x00000020 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_6_MASK = 0x00000040 # macro +RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK = 0x00000080 # macro +RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK = 0x00000100 # macro +RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK = 0x00000200 # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK = 0x00000400 # macro +RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK = 0x00000800 # macro +RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK = 0x00001000 # macro +RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK = 0x00002000 # macro +RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK = 0x00004000 # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK = 0x00008000 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_18_MASK = 0x00040000 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_19_MASK = 0x00080000 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_20_MASK = 0x00100000 # macro +RMI_GENERAL_STATUS__RESERVED_BITS_28_21_MASK = 0x1FE00000 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_29_MASK = 0x20000000 # macro +RMI_GENERAL_STATUS__RESERVED_BIT_30_MASK = 0x40000000 # macro +RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK = 0x80000000 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT = 0x7 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT = 0x8 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT = 0x9 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT = 0x10 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT = 0x11 # macro +RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT = 0x12 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK = 0x0000007F # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK = 0x00000080 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK = 0x00000100 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK = 0x0000FE00 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK = 0x00010000 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK = 0x00020000 # macro +RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK = 0x0FFC0000 # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT = 0xa # macro +RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT = 0x14 # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK = 0x000003FF # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK = 0x000FFC00 # macro +RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK = 0x3FF00000 # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT = 0x9 # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK = 0x000001FF # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK = 0x0003FE00 # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT = 0xa # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK = 0x000003FF # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK = 0x000FFC00 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT = 0x0 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT = 0x2 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT = 0x6 # macro +RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT = 0x7 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT = 0x8 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT = 0xc # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT = 0xd # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK = 0x00000003 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK = 0x0000003C # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK = 0x00000040 # macro +RMI_XBAR_CONFIG__ARBITER_DIS_MASK = 0x00000080 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK = 0x00000F00 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK = 0x00001000 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK = 0x00002000 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT = 0x0 # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT = 0x7 # macro +RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT = 0x8 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT = 0xa # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT = 0x11 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK = 0x0000007F # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK = 0x00000080 # macro +RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK = 0x00000300 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK = 0x0001FC00 # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK = 0x00020000 # macro +RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT = 0x0 # macro +RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT = 0x8 # macro +RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT = 0xc # macro +RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT = 0xd # macro +RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK = 0x000000FF # macro +RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK = 0x00000F00 # macro +RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK = 0x00001000 # macro +RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK = 0x00002000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT = 0x2 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT = 0x6 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT = 0xe # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT = 0x12 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT = 0x16 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT = 0x1e # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK = 0x00000004 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK = 0x00003FC0 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK = 0x0000C000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK = 0x00040000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK = 0x3FC00000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK = 0xC0000000 # macro +RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT = 0x1 # macro +RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +RMI_UTCL1_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +RMI_UTCL1_CNTL1__CLIENTID__SHIFT = 0x7 # macro +RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT = 0x10 # macro +RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT = 0x11 # macro +RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT = 0x12 # macro +RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT = 0x13 # macro +RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT = 0x17 # macro +RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT = 0x18 # macro +RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT = 0x19 # macro +RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT = 0x1b # macro +RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK = 0x00000002 # macro +RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +RMI_UTCL1_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +RMI_UTCL1_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +RMI_UTCL1_CNTL1__USERVM_DIS_MASK = 0x00010000 # macro +RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK = 0x00020000 # macro +RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK = 0x00040000 # macro +RMI_UTCL1_CNTL1__REG_INV_VMID_MASK = 0x00780000 # macro +RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK = 0x00800000 # macro +RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK = 0x01000000 # macro +RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK = 0x02000000 # macro +RMI_UTCL1_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK = 0x08000000 # macro +RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT = 0x0 # macro +RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +RMI_UTCL1_CNTL2__LINE_VALID__SHIFT = 0xa # macro +RMI_UTCL1_CNTL2__DIS_EDC__SHIFT = 0xb # macro +RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT = 0xc # macro +RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT = 0xd # macro +RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT = 0xf # macro +RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT = 0x10 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT = 0x12 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT = 0x13 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT = 0x14 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT = 0x15 # macro +RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT = 0x19 # macro +RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT = 0x1b # macro +RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT = 0x1c # macro +RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT = 0x1d # macro +RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT = 0x1e # macro +RMI_UTCL1_CNTL2__RESERVED__SHIFT = 0x1f # macro +RMI_UTCL1_CNTL2__UTC_SPARE_MASK = 0x000000FF # macro +RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +RMI_UTCL1_CNTL2__LINE_VALID_MASK = 0x00000400 # macro +RMI_UTCL1_CNTL2__DIS_EDC_MASK = 0x00000800 # macro +RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK = 0x00001000 # macro +RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK = 0x00002000 # macro +RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK = 0x00008000 # macro +RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK = 0x00030000 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK = 0x00040000 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK = 0x00080000 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK = 0x00100000 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK = 0x01E00000 # macro +RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK = 0x02000000 # macro +RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK = 0x08000000 # macro +RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK = 0x10000000 # macro +RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK = 0x20000000 # macro +RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK = 0x40000000 # macro +RMI_UTCL1_CNTL2__RESERVED_MASK = 0x80000000 # macro +RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT = 0x0 # macro +RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK = 0x0000FFFF # macro +RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT = 0x9 # macro +RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT = 0x1d # macro +RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT = 0x1f # macro +RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK = 0x0007FE00 # macro +RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK = 0x20000000 # macro +RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK = 0x80000000 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT = 0x0 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT = 0x1 # macro +RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT = 0x9 # macro +RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT = 0x1d # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT = 0x1e # macro +RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT = 0x1f # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK = 0x00000001 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK = 0x000001FE # macro +RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK = 0x0007FE00 # macro +RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK = 0x20000000 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK = 0x40000000 # macro +RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK = 0x80000000 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT = 0x0 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT = 0x1 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT = 0x2 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT = 0x3 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT = 0x5 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT = 0x6 # macro +RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT = 0x9 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK = 0x00000001 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK = 0x00000002 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK = 0x00000004 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK = 0x00000008 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK = 0x00000020 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK = 0x00000040 # macro +RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK = 0x001FFE00 # macro +RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT = 0x0 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT = 0x1 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT = 0x2 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT = 0x12 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT = 0x13 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT = 0x14 # macro +RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT = 0x15 # macro +RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT = 0x16 # macro +RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK = 0x00000001 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK = 0x00000002 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK = 0x0003FFFC # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK = 0x00040000 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK = 0x00080000 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK = 0x00100000 # macro +RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK = 0x00200000 # macro +RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK = 0x07C00000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT = 0x0 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT = 0xc # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT = 0xd # macro +RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT = 0xe # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT = 0xf # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT = 0x1b # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT = 0x1c # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT = 0x1d # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT = 0x1e # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK = 0x00000FFF # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK = 0x00001000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK = 0x00002000 # macro +RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK = 0x00004000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK = 0x07FF8000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK = 0x08000000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK = 0x10000000 # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK = 0x20000000 # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK = 0x40000000 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT = 0x0 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT = 0xc # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT = 0xd # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT = 0x19 # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT = 0x1a # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT = 0x1b # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT = 0x1c # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT = 0x1d # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT = 0x1e # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT = 0x1f # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK = 0x00000FFF # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK = 0x00001000 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK = 0x01FFE000 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK = 0x02000000 # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK = 0x04000000 # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK = 0x08000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK = 0x10000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK = 0x20000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK = 0x40000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK = 0x80000000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT = 0x0 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT = 0x2 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT = 0x3 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT = 0x4 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT = 0x5 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT = 0x6 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT = 0x8 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT = 0x10 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT = 0x12 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT = 0x13 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT = 0x14 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT = 0x15 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT = 0x16 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT = 0x18 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK = 0x00000003 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK = 0x00000004 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK = 0x00000008 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK = 0x00000010 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK = 0x00000020 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK = 0x000000C0 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK = 0x0000FF00 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK = 0x00030000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK = 0x00040000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK = 0x00080000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK = 0x00100000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK = 0x00200000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK = 0x00C00000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK = 0xFF000000 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT = 0x0 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT = 0x8 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK = 0x000000FF # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK = 0x0000FF00 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT = 0x0 # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT = 0x5 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT = 0xa # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT = 0xf # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK = 0x0000001F # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK = 0x000003E0 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK = 0x00007C00 # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK = 0x000F8000 # macro +RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +RMI_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +RMI_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +RMI_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT = 0x0 # macro +RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT = 0x4 # macro +RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT = 0x8 # macro +RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT = 0xc # macro +RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT = 0x10 # macro +RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT = 0x14 # macro +RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT = 0x18 # macro +RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT = 0x1c # macro +RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK = 0x0000000F # macro +RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK = 0x000000F0 # macro +RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK = 0x00000F00 # macro +RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK = 0x0000F000 # macro +RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK = 0x000F0000 # macro +RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK = 0x00F00000 # macro +RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK = 0x0F000000 # macro +RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK = 0xF0000000 # macro +RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT = 0x1 # macro +RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT = 0x2 # macro +RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT = 0x3 # macro +RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT = 0x4 # macro +RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT = 0x5 # macro +RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT = 0x6 # macro +RMI_SPARE__SPARE_BIT_7__SHIFT = 0x7 # macro +RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT = 0x8 # macro +RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT = 0x9 # macro +RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT = 0xa # macro +RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT = 0xb # macro +RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT = 0xc # macro +RMI_SPARE__NOFILL_RMI_CID_S__SHIFT = 0xd # macro +RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT = 0xe # macro +RMI_SPARE__SPARE_BIT_15_0__SHIFT = 0xf # macro +RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT = 0x10 # macro +RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK = 0x00000002 # macro +RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK = 0x00000004 # macro +RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK = 0x00000008 # macro +RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK = 0x00000010 # macro +RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK = 0x00000020 # macro +RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK = 0x00000040 # macro +RMI_SPARE__SPARE_BIT_7_MASK = 0x00000080 # macro +RMI_SPARE__NOFILL_RMI_CID_CC_MASK = 0x00000100 # macro +RMI_SPARE__NOFILL_RMI_CID_FC_MASK = 0x00000200 # macro +RMI_SPARE__NOFILL_RMI_CID_CM_MASK = 0x00000400 # macro +RMI_SPARE__NOFILL_RMI_CID_DC_MASK = 0x00000800 # macro +RMI_SPARE__NOFILL_RMI_CID_Z_MASK = 0x00001000 # macro +RMI_SPARE__NOFILL_RMI_CID_S_MASK = 0x00002000 # macro +RMI_SPARE__NOFILL_RMI_CID_TILE_MASK = 0x00004000 # macro +RMI_SPARE__SPARE_BIT_15_0_MASK = 0x00008000 # macro +RMI_SPARE__ARBITER_ADDRESS_MASK_MASK = 0xFFFF0000 # macro +RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT = 0x0 # macro +RMI_SPARE_1__SPARE_BIT_9__SHIFT = 0x1 # macro +RMI_SPARE_1__SPARE_BIT_10__SHIFT = 0x2 # macro +RMI_SPARE_1__SPARE_BIT_11__SHIFT = 0x3 # macro +RMI_SPARE_1__SPARE_BIT_12__SHIFT = 0x4 # macro +RMI_SPARE_1__SPARE_BIT_13__SHIFT = 0x5 # macro +RMI_SPARE_1__SPARE_BIT_14__SHIFT = 0x6 # macro +RMI_SPARE_1__SPARE_BIT_15__SHIFT = 0x7 # macro +RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT = 0x8 # macro +RMI_SPARE_1__SPARE_BIT_16_1__SHIFT = 0x10 # macro +RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK = 0x00000001 # macro +RMI_SPARE_1__SPARE_BIT_9_MASK = 0x00000002 # macro +RMI_SPARE_1__SPARE_BIT_10_MASK = 0x00000004 # macro +RMI_SPARE_1__SPARE_BIT_11_MASK = 0x00000008 # macro +RMI_SPARE_1__SPARE_BIT_12_MASK = 0x00000010 # macro +RMI_SPARE_1__SPARE_BIT_13_MASK = 0x00000020 # macro +RMI_SPARE_1__SPARE_BIT_14_MASK = 0x00000040 # macro +RMI_SPARE_1__SPARE_BIT_15_MASK = 0x00000080 # macro +RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK = 0x0000FF00 # macro +RMI_SPARE_1__SPARE_BIT_16_1_MASK = 0xFFFF0000 # macro +RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT = 0x0 # macro +RMI_SPARE_2__SPARE_BIT_8_2__SHIFT = 0x10 # macro +RMI_SPARE_2__SPARE_BIT_8_3__SHIFT = 0x18 # macro +RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK = 0x0000FFFF # macro +RMI_SPARE_2__SPARE_BIT_8_2_MASK = 0x00FF0000 # macro +RMI_SPARE_2__SPARE_BIT_8_3_MASK = 0xFF000000 # macro +CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT = 0x1 # macro +CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT = 0x2 # macro +CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT = 0x3 # macro +CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT = 0x4 # macro +CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK = 0x00000002 # macro +CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK = 0x00000004 # macro +CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK = 0x00000008 # macro +CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK = 0x00000010 # macro +GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT = 0x0 # macro +GCR_PIO_CNTL__GCR_REG_DONE__SHIFT = 0x2 # macro +GCR_PIO_CNTL__GCR_REG_RESET__SHIFT = 0x3 # macro +GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT = 0x10 # macro +GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT = 0x1e # macro +GCR_PIO_CNTL__GCR_READY__SHIFT = 0x1f # macro +GCR_PIO_CNTL__GCR_DATA_INDEX_MASK = 0x00000003 # macro +GCR_PIO_CNTL__GCR_REG_DONE_MASK = 0x00000004 # macro +GCR_PIO_CNTL__GCR_REG_RESET_MASK = 0x00000008 # macro +GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK = 0x00FF0000 # macro +GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK = 0x40000000 # macro +GCR_PIO_CNTL__GCR_READY_MASK = 0x80000000 # macro +GCR_PIO_DATA__GCR_DATA__SHIFT = 0x0 # macro +GCR_PIO_DATA__GCR_DATA_MASK = 0xFFFFFFFF # macro +PMM_CNTL__PMM_DISABLE__SHIFT = 0x0 # macro +PMM_CNTL__ABIT_FORCE_FLUSH__SHIFT = 0x1 # macro +PMM_CNTL__ABIT_TIMER_THRESHOLD__SHIFT = 0x2 # macro +PMM_CNTL__ABIT_TIMER_DISABLE__SHIFT = 0x6 # macro +PMM_CNTL__ABIT_TIMER_RESET__SHIFT = 0x7 # macro +PMM_CNTL__INTERRUPT_PRIORITY__SHIFT = 0x8 # macro +PMM_CNTL__PMM_INTERRUPTS_DISABLE__SHIFT = 0xa # macro +PMM_CNTL__RESERVED__SHIFT = 0xb # macro +PMM_CNTL__PMM_DISABLE_MASK = 0x00000001 # macro +PMM_CNTL__ABIT_FORCE_FLUSH_MASK = 0x00000002 # macro +PMM_CNTL__ABIT_TIMER_THRESHOLD_MASK = 0x0000003C # macro +PMM_CNTL__ABIT_TIMER_DISABLE_MASK = 0x00000040 # macro +PMM_CNTL__ABIT_TIMER_RESET_MASK = 0x00000080 # macro +PMM_CNTL__INTERRUPT_PRIORITY_MASK = 0x00000300 # macro +PMM_CNTL__PMM_INTERRUPTS_DISABLE_MASK = 0x00000400 # macro +PMM_CNTL__RESERVED_MASK = 0xFFFFF800 # macro +PMM_STATUS__PMM_IDLE__SHIFT = 0x0 # macro +PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS__SHIFT = 0x1 # macro +PMM_STATUS__ABIT_FORCE_FLUSH_DONE__SHIFT = 0x2 # macro +PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS__SHIFT = 0x3 # macro +PMM_STATUS__ABIT_TIMER_FLUSH_DONE__SHIFT = 0x4 # macro +PMM_STATUS__ABIT_TIMER_RUNNING__SHIFT = 0x5 # macro +PMM_STATUS__PMM_INTERRUPTS_PENDING__SHIFT = 0x6 # macro +PMM_STATUS__ABIT_FLUSH_ERROR__SHIFT = 0x7 # macro +PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS__SHIFT = 0x8 # macro +PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS__SHIFT = 0x9 # macro +PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS__SHIFT = 0xa # macro +PMM_STATUS__RESERVED__SHIFT = 0xb # macro +PMM_STATUS__PMM_IDLE_MASK = 0x00000001 # macro +PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS_MASK = 0x00000002 # macro +PMM_STATUS__ABIT_FORCE_FLUSH_DONE_MASK = 0x00000004 # macro +PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS_MASK = 0x00000008 # macro +PMM_STATUS__ABIT_TIMER_FLUSH_DONE_MASK = 0x00000010 # macro +PMM_STATUS__ABIT_TIMER_RUNNING_MASK = 0x00000020 # macro +PMM_STATUS__PMM_INTERRUPTS_PENDING_MASK = 0x00000040 # macro +PMM_STATUS__ABIT_FLUSH_ERROR_MASK = 0x00000080 # macro +PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS_MASK = 0x00000100 # macro +PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS_MASK = 0x00000200 # macro +PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS_MASK = 0x00000400 # macro +PMM_STATUS__RESERVED_MASK = 0xFFFFF800 # macro +UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS__SHIFT = 0x0 # macro +UTCL1_CTRL_1__UTCL1_TCP_BYPASS__SHIFT = 0x1 # macro +UTCL1_CTRL_1__UTCL1_SQCI_BYPASS__SHIFT = 0x2 # macro +UTCL1_CTRL_1__UTCL1_SQCD_BYPASS__SHIFT = 0x3 # macro +UTCL1_CTRL_1__UTCL1_RMI_BYPASS__SHIFT = 0x4 # macro +UTCL1_CTRL_1__UTCL1_SQG_BYPASS__SHIFT = 0x5 # macro +UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT = 0x6 # macro +UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL__SHIFT = 0x7 # macro +UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE__SHIFT = 0x8 # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1__SHIFT = 0x9 # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2__SHIFT = 0xb # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3__SHIFT = 0xd # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4__SHIFT = 0xf # macro +UTCL1_CTRL_1__RESERVED__SHIFT = 0x11 # macro +UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS_MASK = 0x00000001 # macro +UTCL1_CTRL_1__UTCL1_TCP_BYPASS_MASK = 0x00000002 # macro +UTCL1_CTRL_1__UTCL1_SQCI_BYPASS_MASK = 0x00000004 # macro +UTCL1_CTRL_1__UTCL1_SQCD_BYPASS_MASK = 0x00000008 # macro +UTCL1_CTRL_1__UTCL1_RMI_BYPASS_MASK = 0x00000010 # macro +UTCL1_CTRL_1__UTCL1_SQG_BYPASS_MASK = 0x00000020 # macro +UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK = 0x00000040 # macro +UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_MASK = 0x00000080 # macro +UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE_MASK = 0x00000100 # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1_MASK = 0x00000600 # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2_MASK = 0x00001800 # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3_MASK = 0x00006000 # macro +UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4_MASK = 0x00018000 # macro +UTCL1_CTRL_1__RESERVED_MASK = 0xFFFE0000 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT = 0x0 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT = 0x3 # macro +UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT = 0x4 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT = 0x5 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT = 0x6 # macro +UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT = 0x9 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT = 0xa # macro +UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT = 0xc # macro +UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT = 0xf # macro +UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT = 0x10 # macro +UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT = 0x11 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT = 0x17 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT = 0x18 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK = 0x00000007 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK = 0x00000008 # macro +UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK = 0x00000010 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE_MASK = 0x00000020 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK = 0x000001C0 # macro +UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK = 0x00000200 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK = 0x00000C00 # macro +UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK = 0x00007000 # macro +UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK = 0x00008000 # macro +UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK = 0x00010000 # macro +UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK = 0x007E0000 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK = 0x00800000 # macro +UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK = 0x01000000 # macro +UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT = 0x0 # macro +UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT = 0x1 # macro +UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT = 0x2 # macro +UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT = 0x3 # macro +UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT = 0x4 # macro +UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT = 0x5 # macro +UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT = 0x7 # macro +UTCL1_STATUS__RESERVED__SHIFT = 0x8 # macro +UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK = 0x00000001 # macro +UTCL1_STATUS__UTCL1_MH_BUSY_MASK = 0x00000002 # macro +UTCL1_STATUS__UTCL1_INV_BUSY_MASK = 0x00000004 # macro +UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK = 0x00000008 # macro +UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK = 0x00000010 # macro +UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK = 0x00000060 # macro +UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK = 0x00000080 # macro +UTCL1_STATUS__RESERVED_MASK = 0x00000100 # macro +GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT = 0x17 # macro +GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK = 0xFF800000 # macro +GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT = 0x0 # macro +GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT = 0x17 # macro +GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK = 0x00000001 # macro +GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK = 0xFF800000 # macro +GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT = 0x0 # macro +GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK = 0x00000FFF # macro +GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT = 0x0 # macro +GCMC_VM_FB_OFFSET__FB_OFFSET_MASK = 0x00FFFFFF # macro +GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT = 0x0 # macro +GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK = 0xFFFFFFFF # macro +GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT = 0x0 # macro +GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK = 0x0000000F # macro +GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT = 0x0 # macro +GCMC_VM_STEERING__DEFAULT_STEERING_MASK = 0x00000003 # macro +GCMC_MEM_POWER_LS__LS_SETUP__SHIFT = 0x0 # macro +GCMC_MEM_POWER_LS__LS_HOLD__SHIFT = 0x6 # macro +GCMC_MEM_POWER_LS__LS_SETUP_MASK = 0x0000003F # macro +GCMC_MEM_POWER_LS__LS_HOLD_MASK = 0x00000FC0 # macro +GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT = 0x0 # macro +GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT = 0x1 # macro +GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT = 0x2 # macro +GCMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT = 0x4 # macro +GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT = 0x5 # macro +GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT = 0x6 # macro +GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK = 0x00000001 # macro +GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK = 0x00000002 # macro +GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK = 0x0000000C # macro +GCMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK = 0x00000010 # macro +GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK = 0x00000020 # macro +GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK = 0x000000C0 # macro +GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT = 0x0 # macro +GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK = 0x00000001 # macro +GCUTCL2_ICG_CTRL__OFF_HYSTERESIS__SHIFT = 0x0 # macro +GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT = 0x4 # macro +GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT = 0x5 # macro +GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT = 0x6 # macro +GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT = 0x7 # macro +GCUTCL2_ICG_CTRL__OFF_HYSTERESIS_MASK = 0x0000000F # macro +GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK = 0x00000010 # macro +GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK = 0x00000020 # macro +GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK = 0x00000040 # macro +GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK = 0x00000080 # macro +GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT = 0x0 # macro +GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT = 0x5 # macro +GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK = 0x0000001F # macro +GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK = 0x00000020 # macro +GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT = 0x0 # macro +GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT = 0x1 # macro +GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH__SHIFT = 0x2 # macro +GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT = 0x3 # macro +GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT = 0x4 # macro +GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT = 0x5 # macro +GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK = 0x00000001 # macro +GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK = 0x00000002 # macro +GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH_MASK = 0x00000004 # macro +GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK = 0x00000008 # macro +GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK = 0x00000010 # macro +GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK = 0x00000020 # macro +GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT = 0x0 # macro +GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK = 0xFFFFFFFF # macro +GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT = 0x0 # macro +GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK = 0xFFFFFFFF # macro +GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT = 0x0 # macro +GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT = 0x1 # macro +GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT = 0x2 # macro +GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT = 0x4 # macro +GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT = 0x8 # macro +GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0x9 # macro +GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0xa # macro +GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT = 0xb # macro +GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT = 0xc # macro +GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT = 0xf # macro +GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT = 0x12 # macro +GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT = 0x13 # macro +GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT = 0x15 # macro +GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT = 0x1a # macro +GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK = 0x00000001 # macro +GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK = 0x00000002 # macro +GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK = 0x0000000C # macro +GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK = 0x00000030 # macro +GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK = 0x00000100 # macro +GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000200 # macro +GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000400 # macro +GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK = 0x00000800 # macro +GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK = 0x00007000 # macro +GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK = 0x00038000 # macro +GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK = 0x00040000 # macro +GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK = 0x00180000 # macro +GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK = 0x03E00000 # macro +GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK = 0x0C000000 # macro +GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT = 0x0 # macro +GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT = 0x1 # macro +GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT = 0x15 # macro +GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT = 0x16 # macro +GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT = 0x17 # macro +GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT = 0x1a # macro +GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT = 0x1c # macro +GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK = 0x00000001 # macro +GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK = 0x00000002 # macro +GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK = 0x00200000 # macro +GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK = 0x00400000 # macro +GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK = 0x03800000 # macro +GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK = 0x0C000000 # macro +GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK = 0x70000000 # macro +GCVM_L2_CNTL3__BANK_SELECT__SHIFT = 0x0 # macro +GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT = 0x6 # macro +GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT = 0x8 # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0xf # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT = 0x14 # macro +GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT = 0x15 # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT = 0x18 # macro +GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT = 0x1c # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT = 0x1d # macro +GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT = 0x1e # macro +GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT = 0x1f # macro +GCVM_L2_CNTL3__BANK_SELECT_MASK = 0x0000003F # macro +GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK = 0x000000C0 # macro +GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK = 0x00001F00 # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000F8000 # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK = 0x00100000 # macro +GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK = 0x00E00000 # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK = 0x0F000000 # macro +GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK = 0x10000000 # macro +GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK = 0x20000000 # macro +GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK = 0x40000000 # macro +GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK = 0x80000000 # macro +GCVM_L2_STATUS__L2_BUSY__SHIFT = 0x0 # macro +GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT = 0x1 # macro +GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x11 # macro +GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x12 # macro +GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT = 0x13 # macro +GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT = 0x14 # macro +GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT = 0x15 # macro +GCVM_L2_STATUS__L2_BUSY_MASK = 0x00000001 # macro +GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK = 0x0001FFFE # macro +GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK = 0x00020000 # macro +GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK = 0x00040000 # macro +GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK = 0x00080000 # macro +GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK = 0x00100000 # macro +GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK = 0x00200000 # macro +GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT = 0x0 # macro +GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT = 0x1 # macro +GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT = 0x2 # macro +GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK = 0x00000001 # macro +GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK = 0x00000002 # macro +GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK = 0x000000FC # macro +GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT = 0x0 # macro +GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT = 0x8 # macro +GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK = 0x000000FF # macro +GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK = 0x0000FF00 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT = 0x1 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x2 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x3 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x4 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x5 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x6 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x7 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x8 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x9 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xb # macro +GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0xd # macro +GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x1d # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT = 0x1e # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT = 0x1f # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00000001 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK = 0x00000002 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000004 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000008 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000010 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000020 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000040 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000080 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000100 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000200 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000800 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x1FFFE000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x20000000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK = 0x40000000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK = 0x80000000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x10 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT = 0x11 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT = 0x12 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT = 0x13 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x0000FFFF # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x00010000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK = 0x00020000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK = 0x00040000 # macro +GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK = 0x00080000 # macro +GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT = 0x1 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT = 0x4 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT = 0x8 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT = 0x9 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT = 0x12 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT = 0x13 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT = 0x14 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT = 0x18 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT = 0x19 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT = 0x1d # macro +GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK = 0x00000001 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK = 0x0000000E # macro +GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK = 0x000000F0 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK = 0x00000100 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK = 0x0003FE00 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK = 0x00040000 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK = 0x00080000 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK = 0x00F00000 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK = 0x01000000 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK = 0x1E000000 # macro +GCVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK = 0x20000000 # macro +GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK = 0xFFFFFFFF # macro +GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK = 0x0000000F # macro +GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT = 0x0 # macro +GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT = 0x6 # macro +GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT = 0x7 # macro +GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x8 # macro +GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x12 # macro +GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT = 0x1c # macro +GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT = 0x1d # macro +GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT = 0x1e # macro +GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT = 0x1f # macro +GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK = 0x0000003F # macro +GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK = 0x00000040 # macro +GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK = 0x00000080 # macro +GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0003FF00 # macro +GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0FFC0000 # macro +GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK = 0x10000000 # macro +GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK = 0x20000000 # macro +GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK = 0x40000000 # macro +GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK = 0x80000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT = 0x0 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT = 0x1 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT = 0x2 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT = 0x3 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT = 0x4 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT = 0x5 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT = 0x6 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT = 0x7 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT = 0x8 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT = 0x9 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT = 0xa # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT = 0xb # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT = 0xc # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT = 0xd # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT = 0xe # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT = 0xf # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT = 0x10 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT = 0x11 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT = 0x12 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT = 0x13 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT = 0x14 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT = 0x15 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT = 0x16 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT = 0x17 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT = 0x18 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT = 0x19 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT = 0x1a # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT = 0x1b # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT = 0x1c # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT = 0x1d # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT = 0x1e # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT = 0x1f # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK = 0x00000001 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK = 0x00000002 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK = 0x00000004 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK = 0x00000008 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK = 0x00000010 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK = 0x00000020 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK = 0x00000040 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK = 0x00000080 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK = 0x00000100 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK = 0x00000200 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK = 0x00000400 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK = 0x00000800 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK = 0x00001000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK = 0x00002000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK = 0x00004000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK = 0x00008000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK = 0x00010000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK = 0x00020000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK = 0x00040000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK = 0x00080000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK = 0x00100000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK = 0x00200000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK = 0x00400000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK = 0x00800000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK = 0x01000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK = 0x02000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK = 0x04000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK = 0x08000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK = 0x10000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK = 0x20000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK = 0x40000000 # macro +GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK = 0x80000000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT = 0x14 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT = 0x1a # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK = 0x00100000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK = 0x7C000000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT = 0x14 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT = 0x1a # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK = 0x00100000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK = 0x7C000000 # macro +GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT = 0x0 # macro +GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT = 0x1 # macro +GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT = 0x2 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT = 0x3 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT = 0x4 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT = 0x5 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT = 0x6 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT = 0x9 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT = 0xc # macro +GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK = 0x00000001 # macro +GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK = 0x00000002 # macro +GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK = 0x00000004 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK = 0x00000008 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK = 0x00000010 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK = 0x00000020 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK = 0x000001C0 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK = 0x00000E00 # macro +GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK = 0x0000F000 # macro +GCVM_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT = 0x0 # macro +GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT = 0x4 # macro +GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT = 0x5 # macro +GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT = 0x6 # macro +GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT = 0x7 # macro +GCVM_L2_ICG_CTRL__OFF_HYSTERESIS_MASK = 0x0000000F # macro +GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK = 0x00000010 # macro +GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK = 0x00000020 # macro +GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK = 0x00000040 # macro +GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK = 0x00000080 # macro +GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT = 0x5 # macro +GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT = 0xe # macro +GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT = 0xf # macro +GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT = 0x10 # macro +GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK = 0x00003FE0 # macro +GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK = 0x00004000 # macro +GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK = 0x00008000 # macro +GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK = 0x00010000 # macro +GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT = 0x0 # macro +GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT = 0x1 # macro +GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK = 0x00000001 # macro +GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK = 0x000003FE # macro +GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT = 0x0 # macro +GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK = 0x00FFFFFF # macro +GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT = 0x1 # macro +GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK = 0x0000FFFE # macro +GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT = 0x0 # macro +GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK = 0x00FFFFFF # macro +GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT = 0x1 # macro +GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK = 0x0000FFFE # macro +GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT = 0x0 # macro +GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT = 0x5 # macro +GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK = 0x0000001F # macro +GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK = 0x00000020 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT = 0x0 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT = 0x1 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT = 0x4 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT = 0x8 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT = 0xc # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT = 0x10 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK = 0x00000001 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK = 0x00000002 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK = 0x000000F0 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK = 0x00000F00 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK = 0x0000F000 # macro +GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK = 0xFFFF0000 # macro +GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT = 0x0 # macro +GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK = 0xFFFFFFFF # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT = 0x0 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK = 0xFFFFFFFF # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT = 0x0 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT = 0x4 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT = 0x8 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT = 0xc # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT = 0xd # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT = 0xf # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT = 0x10 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT = 0x11 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT = 0x12 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT = 0x1e # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK = 0x0000000F # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK = 0x000000F0 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK = 0x00000F00 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK = 0x00001000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK = 0x00006000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK = 0x00008000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK = 0x00010000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK = 0x00020000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK = 0x07FC0000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK = 0x40000000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT = 0x0 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK = 0xFFFFFFFF # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT = 0x0 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT = 0x4 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT = 0x7 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT = 0xd # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT = 0xe # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT = 0xf # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT = 0x10 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT = 0x11 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT = 0x12 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT = 0x15 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT = 0x16 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT = 0x18 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT = 0x1f # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK = 0x0000000F # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK = 0x00000070 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK = 0x00001F80 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK = 0x00002000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK = 0x00004000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK = 0x00008000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK = 0x00010000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK = 0x00020000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK = 0x001C0000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK = 0x00200000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK = 0x00C00000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK = 0x01000000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK = 0x80000000 # macro +GCVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT = 0x0 # macro +GCVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT = 0x4 # macro +GCVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT = 0x8 # macro +GCVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT = 0xc # macro +GCVM_L2_BANK_SELECT_MASKS__MASK0_MASK = 0x0000000F # macro +GCVM_L2_BANK_SELECT_MASKS__MASK1_MASK = 0x000000F0 # macro +GCVM_L2_BANK_SELECT_MASKS__MASK2_MASK = 0x00000F00 # macro +GCVM_L2_BANK_SELECT_MASKS__MASK3_MASK = 0x0000F000 # macro +GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT = 0x0 # macro +GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT = 0xa # macro +GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK = 0x000003FF # macro +GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK = 0x00000400 # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT = 0x0 # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT = 0xa # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK = 0x000003FF # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK = 0x00000400 # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT = 0x0 # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT = 0xa # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK = 0x000003FF # macro +GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK = 0x00000400 # macro +GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT = 0x0 # macro +GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT = 0xa # macro +GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK = 0x000003FF # macro +GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK = 0x00000400 # macro +GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT = 0x0 # macro +GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT = 0xa # macro +GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK = 0x000003FF # macro +GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK = 0x00000400 # macro +GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT = 0x0 # macro +GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK = 0x00FFFFFF # macro +GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT = 0x0 # macro +GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK = 0x00FFFFFF # macro +GCMC_VM_AGP_TOP__AGP_TOP__SHIFT = 0x0 # macro +GCMC_VM_AGP_TOP__AGP_TOP_MASK = 0x00FFFFFF # macro +GCMC_VM_AGP_BOT__AGP_BOT__SHIFT = 0x0 # macro +GCMC_VM_AGP_BOT__AGP_BOT_MASK = 0x00FFFFFF # macro +GCMC_VM_AGP_BASE__AGP_BASE__SHIFT = 0x0 # macro +GCMC_VM_AGP_BASE__AGP_BASE_MASK = 0x00FFFFFF # macro +GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT = 0x0 # macro +GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT = 0x3 # macro +GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT = 0x5 # macro +GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT = 0x6 # macro +GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT = 0x7 # macro +GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT = 0xb # macro +GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK = 0x00000001 # macro +GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK = 0x00000018 # macro +GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK = 0x00000020 # macro +GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK = 0x00000040 # macro +GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK = 0x00000780 # macro +GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK = 0x00003800 # macro +GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT = 0x0 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT = 0x1 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT = 0x2 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT = 0x3 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT = 0x4 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT = 0x5 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT = 0x6 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT = 0x7 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT = 0x8 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT = 0x9 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT = 0xa # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT = 0xb # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT = 0xc # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT = 0xd # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT = 0xe # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT = 0xf # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK = 0x00000001 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK = 0x00000002 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK = 0x00000004 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK = 0x00000008 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK = 0x00000010 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK = 0x00000020 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK = 0x00000040 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK = 0x00000080 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK = 0x00000100 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK = 0x00000200 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK = 0x00000400 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK = 0x00000800 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK = 0x00001000 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK = 0x00002000 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK = 0x00004000 # macro +GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK = 0x00008000 # macro +GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT = 0x10 # macro +GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK = 0x00010000 # macro +GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT = 0x2 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT = 0x4 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT = 0x6 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT = 0x8 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT = 0xc # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT = 0x10 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT = 0x14 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK = 0x00000003 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK = 0x0000000C # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK = 0x00000030 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK = 0x000000C0 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK = 0x00000F00 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK = 0x0000F000 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK = 0x000F0000 # macro +GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK = 0x00F00000 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT = 0x0 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT = 0x2 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT = 0x4 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT = 0x6 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT = 0x8 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT = 0xc # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT = 0x10 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT = 0x14 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK = 0x00000003 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK = 0x0000000C # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK = 0x00000030 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK = 0x000000C0 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK = 0x00000F00 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK = 0x0000F000 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK = 0x000F0000 # macro +GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK = 0x00F00000 # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT = 0x1c # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT = 0x1d # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK = 0x10000000 # macro +GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK = 0x20000000 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT = 0x0 # macro +GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT = 0x10 # macro +GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK = 0x0000FFFF # macro +GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT = 0x0 # macro +GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT = 0x10 # macro +GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK = 0x0000FFFF # macro +GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK = 0xFFFF0000 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT = 0x0 # macro +GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK = 0x00000001 # macro +GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15__SHIFT = 0xc # macro +GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15__SHIFT = 0x0 # macro +GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15__SHIFT = 0x1 # macro +GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15__SHIFT = 0xc # macro +GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15_MASK = 0x00000001 # macro +GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15_MASK = 0x00000002 # macro +GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15__SHIFT = 0x0 # macro +GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15__SHIFT = 0xc # macro +GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15_MASK = 0xFFFFF000 # macro +GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15__SHIFT = 0x0 # macro +GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15_MASK = 0x000FFFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF_MASK = 0x00010000 # macro +GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS__SHIFT = 0x0 # macro +GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF__SHIFT = 0x10 # macro +GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS_MASK = 0x0000FFFF # macro +GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF_MASK = 0x00010000 # macro +GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT = 0x0 # macro +GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK = 0xFFFFFFFF # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT = 0x0 # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT = 0x4 # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT = 0x5 # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT = 0x6 # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK = 0x0000000F # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK = 0x00000010 # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK = 0x00000020 # macro +GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START__SHIFT = 0x1d # macro +SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END__SHIFT = 0x1e # macro +SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP__SHIFT = 0x1f # macro +SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK = 0x0000FFFF # macro +SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE_MASK = 0x003F0000 # macro +SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START_MASK = 0x20000000 # macro +SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END_MASK = 0x40000000 # macro +SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP_MASK = 0x80000000 # macro +SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT = 0x0 # macro +SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK = 0x0000FFFF # macro +SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK = 0x003F0000 # macro +SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE_MASK = 0x00C00000 # macro +SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT = 0x14 # macro +SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT = 0x15 # macro +SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT = 0x18 # macro +SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT = 0x19 # macro +SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT = 0x1d # macro +SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK = 0x00000C00 # macro +SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK = 0x000FF000 # macro +SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK = 0x00100000 # macro +SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK = 0x00200000 # macro +SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK = 0x00800000 # macro +SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK = 0x01000000 # macro +SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK = 0x02000000 # macro +SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK = 0x04000000 # macro +SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK = 0x20000000 # macro +SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT = 0x8 # macro +SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT = 0x19 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK = 0x00000080 # macro +SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK = 0x0000FF00 # macro +SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK = 0x01FF0000 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK = 0x02000000 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK = 0x04000000 # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK = 0xF0000000 # macro +SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_31__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT = 0x0 # macro +SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT = 0x1 # macro +SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT = 0x5 # macro +SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT = 0x9 # macro +SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT = 0xa # macro +SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT = 0xf # macro +SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT = 0x10 # macro +SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT = 0x11 # macro +SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK = 0x00000001 # macro +SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK = 0x0000001E # macro +SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK = 0x000001E0 # macro +SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK = 0x00000200 # macro +SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK = 0x00007C00 # macro +SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK = 0x00008000 # macro +SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK = 0x00010000 # macro +SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK = 0x000E0000 # macro +SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT = 0x0 # macro +SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC4_GS__RESERVED__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN__SHIFT = 0xe # macro +SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN__SHIFT = 0xf # macro +SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START__SHIFT = 0x1d # macro +SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END__SHIFT = 0x1e # macro +SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP__SHIFT = 0x1f # macro +SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC4_GS__RESERVED_MASK = 0x00003FFE # macro +SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN_MASK = 0x00004000 # macro +SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN_MASK = 0x00008000 # macro +SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK = 0x007F0000 # macro +SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE_MASK = 0x1F800000 # macro +SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START_MASK = 0x20000000 # macro +SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END_MASK = 0x40000000 # macro +SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP_MASK = 0x80000000 # macro +SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK = 0x0000FFFF # macro +SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK = 0x003F0000 # macro +SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK = 0x03C00000 # macro +SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK = 0xFC000000 # macro +SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT = 0x14 # macro +SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT = 0x15 # macro +SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT = 0x18 # macro +SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT = 0x19 # macro +SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT = 0x1d # macro +SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT = 0x1f # macro +SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK = 0x00000C00 # macro +SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK = 0x000FF000 # macro +SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK = 0x00100000 # macro +SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK = 0x00200000 # macro +SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK = 0x00800000 # macro +SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK = 0x01000000 # macro +SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK = 0x02000000 # macro +SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK = 0x04000000 # macro +SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK = 0x60000000 # macro +SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK = 0x80000000 # macro +SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT = 0x12 # macro +SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT = 0x13 # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK = 0x0000FF80 # macro +SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK = 0x00030000 # macro +SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK = 0x00040000 # macro +SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK = 0x07F80000 # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK = 0xF0000000 # macro +SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_GS_31__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X__SHIFT = 0x0 # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y__SHIFT = 0x8 # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z__SHIFT = 0x10 # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE__SHIFT = 0x18 # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X_MASK = 0x000000FF # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y_MASK = 0x0000FF00 # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z_MASK = 0x00FF0000 # macro +SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE_MASK = 0xFF000000 # macro +SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS__SHIFT = 0x0 # macro +SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS__SHIFT = 0x9 # macro +SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS_MASK = 0x000001FF # macro +SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS_MASK = 0x0003FE00 # macro +SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT = 0x0 # macro +SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT = 0x1 # macro +SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT = 0x5 # macro +SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT = 0x9 # macro +SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT = 0xa # macro +SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT = 0xf # macro +SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT = 0x10 # macro +SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT = 0x11 # macro +SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK = 0x00000001 # macro +SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK = 0x0000001E # macro +SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK = 0x000001E0 # macro +SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK = 0x00000200 # macro +SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK = 0x00007C00 # macro +SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK = 0x00008000 # macro +SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK = 0x00010000 # macro +SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK = 0x000E0000 # macro +SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT = 0x0 # macro +SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START__SHIFT = 0x1d # macro +SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END__SHIFT = 0x1e # macro +SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP__SHIFT = 0x1f # macro +SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK = 0x0000FFFF # macro +SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE_MASK = 0x003F0000 # macro +SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START_MASK = 0x20000000 # macro +SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END_MASK = 0x40000000 # macro +SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP_MASK = 0x80000000 # macro +SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK = 0x0000FC00 # macro +SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK = 0xFFFF0000 # macro +SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT = 0x14 # macro +SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT = 0x15 # macro +SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT = 0x18 # macro +SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT = 0x19 # macro +SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT = 0x1e # macro +SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK = 0x00000C00 # macro +SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK = 0x000FF000 # macro +SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK = 0x00100000 # macro +SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK = 0x00200000 # macro +SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK = 0x00800000 # macro +SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK = 0x01000000 # macro +SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK = 0x02000000 # macro +SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK = 0x04000000 # macro +SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK = 0x30000000 # macro +SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK = 0x40000000 # macro +SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT = 0x8 # macro +SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT = 0x9 # macro +SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT = 0x12 # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK = 0x00000080 # macro +SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK = 0x00000100 # macro +SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK = 0x0003FE00 # macro +SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK = 0x07FC0000 # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK = 0xF0000000 # macro +SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_HS_31__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT = 0x0 # macro +SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT = 0x1 # macro +SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT = 0x5 # macro +SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT = 0x9 # macro +SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT = 0xa # macro +SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT = 0xf # macro +SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT = 0x10 # macro +SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT = 0x11 # macro +SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK = 0x00000001 # macro +SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK = 0x0000001E # macro +SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK = 0x000001E0 # macro +SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK = 0x00000200 # macro +SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK = 0x00007C00 # macro +SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK = 0x00008000 # macro +SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK = 0x00010000 # macro +SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK = 0x000E0000 # macro +SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT = 0x0 # macro +SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK = 0x0000007F # macro +SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK = 0xFF # macro +COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT = 0x1 # macro +COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT = 0x2 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT = 0x3 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT = 0x4 # macro +COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT = 0x5 # macro +COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT = 0x6 # macro +COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT = 0xa # macro +COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT = 0xb # macro +COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT = 0xc # macro +COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT = 0xd # macro +COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT = 0xe # macro +COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT = 0xf # macro +COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT = 0x10 # macro +COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT = 0x11 # macro +COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK = 0x00000001 # macro +COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK = 0x00000002 # macro +COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK = 0x00000004 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK = 0x00000008 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK = 0x00000010 # macro +COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK = 0x00000020 # macro +COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK = 0x00000040 # macro +COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK = 0x00000400 # macro +COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK = 0x00000800 # macro +COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK = 0x00001000 # macro +COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK = 0x00002000 # macro +COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK = 0x00004000 # macro +COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK = 0x00008000 # macro +COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK = 0x00010000 # macro +COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK = 0x00020000 # macro +COMPUTE_DIM_X__SIZE__SHIFT = 0x0 # macro +COMPUTE_DIM_X__SIZE_MASK = 0xFFFFFFFF # macro +COMPUTE_DIM_Y__SIZE__SHIFT = 0x0 # macro +COMPUTE_DIM_Y__SIZE_MASK = 0xFFFFFFFF # macro +COMPUTE_DIM_Z__SIZE__SHIFT = 0x0 # macro +COMPUTE_DIM_Z__SIZE_MASK = 0xFFFFFFFF # macro +COMPUTE_START_X__START__SHIFT = 0x0 # macro +COMPUTE_START_X__START_MASK = 0xFFFFFFFF # macro +COMPUTE_START_Y__START__SHIFT = 0x0 # macro +COMPUTE_START_Y__START_MASK = 0xFFFFFFFF # macro +COMPUTE_START_Z__START__SHIFT = 0x0 # macro +COMPUTE_START_Z__START_MASK = 0xFFFFFFFF # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT = 0x0 # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT = 0x10 # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK = 0x0000FFFF # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK = 0xFFFF0000 # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT = 0x0 # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT = 0x10 # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK = 0x0000FFFF # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK = 0xFFFF0000 # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT = 0x0 # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT = 0x10 # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK = 0x0000FFFF # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK = 0xFFFF0000 # macro +COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT = 0x0 # macro +COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK = 0x00000001 # macro +COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT = 0x0 # macro +COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK = 0x00000001 # macro +COMPUTE_PGM_LO__DATA__SHIFT = 0x0 # macro +COMPUTE_PGM_LO__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_PGM_HI__DATA__SHIFT = 0x0 # macro +COMPUTE_PGM_HI__DATA_MASK = 0x000000FF # macro +COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK = 0x000000FF # macro +COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK = 0x000000FF # macro +COMPUTE_PGM_RSRC1__VGPRS__SHIFT = 0x0 # macro +COMPUTE_PGM_RSRC1__SGPRS__SHIFT = 0x6 # macro +COMPUTE_PGM_RSRC1__PRIORITY__SHIFT = 0xa # macro +COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT = 0xc # macro +COMPUTE_PGM_RSRC1__PRIV__SHIFT = 0x14 # macro +COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT = 0x15 # macro +COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT = 0x17 # macro +COMPUTE_PGM_RSRC1__BULKY__SHIFT = 0x18 # macro +COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT = 0x1a # macro +COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT = 0x1d # macro +COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT = 0x1e # macro +COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT = 0x1f # macro +COMPUTE_PGM_RSRC1__VGPRS_MASK = 0x0000003F # macro +COMPUTE_PGM_RSRC1__SGPRS_MASK = 0x000003C0 # macro +COMPUTE_PGM_RSRC1__PRIORITY_MASK = 0x00000C00 # macro +COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK = 0x000FF000 # macro +COMPUTE_PGM_RSRC1__PRIV_MASK = 0x00100000 # macro +COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK = 0x00200000 # macro +COMPUTE_PGM_RSRC1__IEEE_MODE_MASK = 0x00800000 # macro +COMPUTE_PGM_RSRC1__BULKY_MASK = 0x01000000 # macro +COMPUTE_PGM_RSRC1__FP16_OVFL_MASK = 0x04000000 # macro +COMPUTE_PGM_RSRC1__WGP_MODE_MASK = 0x20000000 # macro +COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK = 0x40000000 # macro +COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK = 0x80000000 # macro +COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT = 0x0 # macro +COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT = 0x1 # macro +COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT = 0x6 # macro +COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT = 0x7 # macro +COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT = 0x8 # macro +COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT = 0x9 # macro +COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT = 0xa # macro +COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT = 0xb # macro +COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT = 0xd # macro +COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT = 0xf # macro +COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT = 0x18 # macro +COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK = 0x00000001 # macro +COMPUTE_PGM_RSRC2__USER_SGPR_MASK = 0x0000003E # macro +COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK = 0x00000040 # macro +COMPUTE_PGM_RSRC2__TGID_X_EN_MASK = 0x00000080 # macro +COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK = 0x00000100 # macro +COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK = 0x00000200 # macro +COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK = 0x00000400 # macro +COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK = 0x00001800 # macro +COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK = 0x00006000 # macro +COMPUTE_PGM_RSRC2__LDS_SIZE_MASK = 0x00FF8000 # macro +COMPUTE_PGM_RSRC2__EXCP_EN_MASK = 0x7F000000 # macro +COMPUTE_VMID__DATA__SHIFT = 0x0 # macro +COMPUTE_VMID__DATA_MASK = 0x0000000F # macro +COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT = 0x0 # macro +COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT = 0xc # macro +COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT = 0x10 # macro +COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT = 0x16 # macro +COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT = 0x17 # macro +COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT = 0x18 # macro +COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK = 0x000003FF # macro +COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK = 0x0000F000 # macro +COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK = 0x003F0000 # macro +COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK = 0x00400000 # macro +COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK = 0x00800000 # macro +COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK = 0x07000000 # macro +COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT = 0x0 # macro +COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK = 0xFFFFFFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT = 0x0 # macro +COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK = 0xFFFFFFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_TMPRING_SIZE__WAVES__SHIFT = 0x0 # macro +COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT = 0xc # macro +COMPUTE_TMPRING_SIZE__WAVES_MASK = 0x00000FFF # macro +COMPUTE_TMPRING_SIZE__WAVESIZE_MASK = 0x07FFF000 # macro +COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT = 0x0 # macro +COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK = 0xFFFFFFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT = 0x0 # macro +COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK = 0xFFFFFFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_RESTART_X__RESTART__SHIFT = 0x0 # macro +COMPUTE_RESTART_X__RESTART_MASK = 0xFFFFFFFF # macro +COMPUTE_RESTART_Y__RESTART__SHIFT = 0x0 # macro +COMPUTE_RESTART_Y__RESTART_MASK = 0xFFFFFFFF # macro +COMPUTE_RESTART_Z__RESTART__SHIFT = 0x0 # macro +COMPUTE_RESTART_Z__RESTART_MASK = 0xFFFFFFFF # macro +COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT = 0x0 # macro +COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK = 0x00000001 # macro +COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT = 0x0 # macro +COMPUTE_MISC_RESERVED__RESERVED3__SHIFT = 0x3 # macro +COMPUTE_MISC_RESERVED__RESERVED4__SHIFT = 0x4 # macro +COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT = 0x5 # macro +COMPUTE_MISC_RESERVED__SEND_SEID_MASK = 0x00000007 # macro +COMPUTE_MISC_RESERVED__RESERVED3_MASK = 0x00000008 # macro +COMPUTE_MISC_RESERVED__RESERVED4_MASK = 0x00000010 # macro +COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK = 0x0001FFE0 # macro +COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK = 0xFFFFFFFF # macro +COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT = 0x0 # macro +COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK = 0xFFFFFFFF # macro +COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT = 0x0 # macro +COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT = 0x1 # macro +COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT = 0x5 # macro +COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT = 0x9 # macro +COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT = 0xa # macro +COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT = 0xf # macro +COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT = 0x10 # macro +COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT = 0x11 # macro +COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT = 0x14 # macro +COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK = 0x00000001 # macro +COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK = 0x0000001E # macro +COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK = 0x000001E0 # macro +COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK = 0x00000200 # macro +COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK = 0x00007C00 # macro +COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK = 0x00008000 # macro +COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK = 0x00010000 # macro +COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK = 0x000E0000 # macro +COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK = 0x07F00000 # macro +COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT = 0x0 # macro +COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK = 0x0000007F # macro +COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT = 0x0 # macro +COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK = 0x0000007F # macro +COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT = 0x0 # macro +COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK = 0x0000007F # macro +COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT = 0x0 # macro +COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK = 0x0000007F # macro +COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT = 0x0 # macro +COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT = 0x4 # macro +COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT = 0xa # macro +COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT = 0xb # macro +COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT = 0x1f # macro +COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK = 0x0000000F # macro +COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK = 0x000003F0 # macro +COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK = 0x00000400 # macro +COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK = 0x00000800 # macro +COMPUTE_PGM_RSRC3__IMAGE_OP_MASK = 0x80000000 # macro +COMPUTE_DDID_INDEX__INDEX__SHIFT = 0x0 # macro +COMPUTE_DDID_INDEX__INDEX_MASK = 0x000007FF # macro +COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT = 0x0 # macro +COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK = 0xFFFFFFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_MASK = 0x000003FF # macro +COMPUTE_RELAUNCH__PAYLOAD__SHIFT = 0x0 # macro +COMPUTE_RELAUNCH__IS_EVENT__SHIFT = 0x1e # macro +COMPUTE_RELAUNCH__IS_STATE__SHIFT = 0x1f # macro +COMPUTE_RELAUNCH__PAYLOAD_MASK = 0x3FFFFFFF # macro +COMPUTE_RELAUNCH__IS_EVENT_MASK = 0x40000000 # macro +COMPUTE_RELAUNCH__IS_STATE_MASK = 0x80000000 # macro +COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT = 0x0 # macro +COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK = 0xFFFFFFFF # macro +COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT = 0x0 # macro +COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK = 0xFFFF # macro +COMPUTE_RELAUNCH2__PAYLOAD__SHIFT = 0x0 # macro +COMPUTE_RELAUNCH2__IS_EVENT__SHIFT = 0x1e # macro +COMPUTE_RELAUNCH2__IS_STATE__SHIFT = 0x1f # macro +COMPUTE_RELAUNCH2__PAYLOAD_MASK = 0x3FFFFFFF # macro +COMPUTE_RELAUNCH2__IS_EVENT_MASK = 0x40000000 # macro +COMPUTE_RELAUNCH2__IS_STATE_MASK = 0x80000000 # macro +COMPUTE_USER_DATA_0__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_1__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_2__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_3__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_3__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_4__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_4__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_5__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_5__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_6__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_6__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_7__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_7__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_8__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_8__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_9__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_9__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_10__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_10__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_11__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_11__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_12__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_12__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_13__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_13__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_14__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_14__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_15__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_15__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT = 0xa # macro +COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK = 0x000003FF # macro +COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK = 0x00000400 # macro +COMPUTE_DISPATCH_END__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_END__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_NOWHERE__DATA__SHIFT = 0x0 # macro +COMPUTE_NOWHERE__DATA_MASK = 0xFFFFFFFF # macro +SH_RESERVED_REG0__DATA__SHIFT = 0x0 # macro +SH_RESERVED_REG0__DATA_MASK = 0xFFFFFFFF # macro +SH_RESERVED_REG1__DATA__SHIFT = 0x0 # macro +SH_RESERVED_REG1__DATA_MASK = 0xFFFFFFFF # macro +CP_CU_MASK_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_CU_MASK_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_CU_MASK_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_CU_MASK_ADDR_HI__ADDR_HI_MASK = 0xFFFFFFFF # macro +CP_CU_MASK_CNTL__POLICY__SHIFT = 0x0 # macro +CP_CU_MASK_CNTL__POLICY_MASK = 0x00000001 # macro +CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT = 0x0 # macro +CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT = 0xa # macro +CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK = 0x000003FF # macro +CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK = 0x0003FC00 # macro +CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT = 0x0 # macro +CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT = 0x8 # macro +CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK = 0x000000FF # macro +CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK = 0x0000FF00 # macro +CPC_INT_INFO__ADDR_HI__SHIFT = 0x0 # macro +CPC_INT_INFO__TYPE__SHIFT = 0x10 # macro +CPC_INT_INFO__VMID__SHIFT = 0x14 # macro +CPC_INT_INFO__QUEUE_ID__SHIFT = 0x1c # macro +CPC_INT_INFO__ADDR_HI_MASK = 0x0000FFFF # macro +CPC_INT_INFO__TYPE_MASK = 0x00010000 # macro +CPC_INT_INFO__VMID_MASK = 0x00F00000 # macro +CPC_INT_INFO__QUEUE_ID_MASK = 0x70000000 # macro +CP_VIRT_STATUS__VIRT_STATUS__SHIFT = 0x0 # macro +CP_VIRT_STATUS__VIRT_STATUS_MASK = 0xFFFFFFFF # macro +CPC_INT_ADDR__ADDR__SHIFT = 0x0 # macro +CPC_INT_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +CPC_INT_PASID__PASID__SHIFT = 0x0 # macro +CPC_INT_PASID__BYPASS_PASID__SHIFT = 0x10 # macro +CPC_INT_PASID__PASID_MASK = 0x0000FFFF # macro +CPC_INT_PASID__BYPASS_PASID_MASK = 0x00010000 # macro +CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR__SHIFT = 0x0 # macro +CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR__SHIFT = 0x1 # macro +CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR__SHIFT = 0x2 # macro +CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR__SHIFT = 0x3 # macro +CP_GFX_ERROR__SUA_ERROR__SHIFT = 0x4 # macro +CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT = 0x6 # macro +CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT = 0x7 # macro +CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT = 0x9 # macro +CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT = 0xa # macro +CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT = 0xb # macro +CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT = 0xc # macro +CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT = 0xd # macro +CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT = 0xe # macro +CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT = 0xf # macro +CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT = 0x12 # macro +CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT = 0x13 # macro +CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT = 0x14 # macro +CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT = 0x15 # macro +CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT = 0x17 # macro +CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT = 0x18 # macro +CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT = 0x19 # macro +CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT = 0x1a # macro +CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT = 0x1b # macro +CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT = 0x1e # macro +CP_GFX_ERROR__RESERVED__SHIFT = 0x1f # macro +CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR_MASK = 0x00000001 # macro +CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR_MASK = 0x00000002 # macro +CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR_MASK = 0x00000004 # macro +CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR_MASK = 0x00000008 # macro +CP_GFX_ERROR__SUA_ERROR_MASK = 0x00000010 # macro +CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK = 0x00000040 # macro +CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK = 0x00000080 # macro +CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK = 0x00000200 # macro +CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK = 0x00000400 # macro +CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK = 0x00000800 # macro +CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK = 0x00001000 # macro +CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK = 0x00002000 # macro +CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK = 0x00004000 # macro +CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK = 0x00008000 # macro +CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK = 0x00040000 # macro +CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK = 0x00080000 # macro +CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK = 0x00100000 # macro +CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK = 0x00200000 # macro +CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK = 0x00800000 # macro +CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK = 0x01000000 # macro +CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK = 0x02000000 # macro +CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK = 0x04000000 # macro +CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK = 0x08000000 # macro +CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK = 0x40000000 # macro +CP_GFX_ERROR__RESERVED_MASK = 0x80000000 # macro +CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +CPG_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +CPG_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x1d # macro +CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x1e # macro +CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +CPG_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +CPG_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +CPG_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x20000000 # macro +CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x40000000 # macro +CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +CPC_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +CPC_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x1d # macro +CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x1e # macro +CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +CPC_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +CPC_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +CPC_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x20000000 # macro +CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x40000000 # macro +CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +CPF_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +CPF_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x1d # macro +CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x1e # macro +CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT = 0x1f # macro +CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +CPF_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +CPF_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +CPF_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x20000000 # macro +CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x40000000 # macro +CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK = 0x80000000 # macro +CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT = 0x0 # macro +CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK = 0xFFFFFFFF # macro +CP_RB0_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_RB0_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_RB_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_RB_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_RB0_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_RB0_CNTL__TMZ_STATE__SHIFT = 0x6 # macro +CP_RB0_CNTL__TMZ_MATCH__SHIFT = 0x7 # macro +CP_RB0_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_RB0_CNTL__RB_NON_PRIV__SHIFT = 0xf # macro +CP_RB0_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_RB0_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_RB0_CNTL__RB_VOLATILE__SHIFT = 0x1a # macro +CP_RB0_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_RB0_CNTL__RB_EXE__SHIFT = 0x1c # macro +CP_RB0_CNTL__KMD_QUEUE__SHIFT = 0x1d # macro +CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_RB0_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_RB0_CNTL__TMZ_STATE_MASK = 0x00000040 # macro +CP_RB0_CNTL__TMZ_MATCH_MASK = 0x00000080 # macro +CP_RB0_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_RB0_CNTL__RB_NON_PRIV_MASK = 0x00008000 # macro +CP_RB0_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_RB0_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_RB0_CNTL__RB_VOLATILE_MASK = 0x04000000 # macro +CP_RB0_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_RB0_CNTL__RB_EXE_MASK = 0x10000000 # macro +CP_RB0_CNTL__KMD_QUEUE_MASK = 0x20000000 # macro +CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_RB_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_RB_CNTL__TMZ_STATE__SHIFT = 0x6 # macro +CP_RB_CNTL__TMZ_MATCH__SHIFT = 0x7 # macro +CP_RB_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_RB_CNTL__RB_NON_PRIV__SHIFT = 0xf # macro +CP_RB_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_RB_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_RB_CNTL__RB_VOLATILE__SHIFT = 0x1a # macro +CP_RB_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_RB_CNTL__RB_EXE__SHIFT = 0x1c # macro +CP_RB_CNTL__KMD_QUEUE__SHIFT = 0x1d # macro +CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_RB_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_RB_CNTL__TMZ_STATE_MASK = 0x00000040 # macro +CP_RB_CNTL__TMZ_MATCH_MASK = 0x00000080 # macro +CP_RB_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_RB_CNTL__RB_NON_PRIV_MASK = 0x00008000 # macro +CP_RB_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_RB_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_RB_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_RB_CNTL__RB_VOLATILE_MASK = 0x04000000 # macro +CP_RB_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_RB_CNTL__RB_EXE_MASK = 0x10000000 # macro +CP_RB_CNTL__KMD_QUEUE_MASK = 0x20000000 # macro +CP_RB_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT = 0x0 # macro +CP_RB_RPTR_WR__RB_RPTR_WR_MASK = 0x000FFFFF # macro +CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB0_BUFSZ_MASK__DATA__SHIFT = 0x0 # macro +CP_RB0_BUFSZ_MASK__DATA_MASK = 0x000FFFFF # macro +CP_RB_BUFSZ_MASK__DATA__SHIFT = 0x0 # macro +CP_RB_BUFSZ_MASK__DATA_MASK = 0x000FFFFF # macro +CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT = 0x8 # macro +CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT = 0x9 # macro +CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT = 0xa # macro +CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT = 0xb # macro +CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT = 0x12 # macro +CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT = 0x13 # macro +CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT = 0x14 # macro +CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT = 0x15 # macro +CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT = 0x16 # macro +CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_INT_CNTL__RESUME_INT_ENABLE_MASK = 0x00000100 # macro +CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK = 0x00000200 # macro +CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK = 0x00000400 # macro +CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK = 0x00000800 # macro +CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK = 0x00040000 # macro +CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK = 0x00080000 # macro +CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK = 0x00100000 # macro +CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK = 0x00200000 # macro +CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK = 0x00400000 # macro +CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_INT_STATUS__RESUME_INT_STAT__SHIFT = 0x8 # macro +CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT = 0x9 # macro +CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT = 0xa # macro +CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT = 0xb # macro +CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT = 0xe # macro +CP_INT_STATUS__GPF_INT_STAT__SHIFT = 0x10 # macro +CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT = 0x11 # macro +CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT = 0x12 # macro +CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT = 0x13 # macro +CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT = 0x14 # macro +CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT = 0x15 # macro +CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT = 0x16 # macro +CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT = 0x17 # macro +CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT = 0x18 # macro +CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT = 0x1a # macro +CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT = 0x1b # macro +CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT = 0x1d # macro +CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT = 0x1e # macro +CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT = 0x1f # macro +CP_INT_STATUS__RESUME_INT_STAT_MASK = 0x00000100 # macro +CP_INT_STATUS__SUSPEND_INT_STAT_MASK = 0x00000200 # macro +CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK = 0x00000400 # macro +CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK = 0x00000800 # macro +CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK = 0x00004000 # macro +CP_INT_STATUS__GPF_INT_STAT_MASK = 0x00010000 # macro +CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK = 0x00020000 # macro +CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK = 0x00040000 # macro +CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK = 0x00080000 # macro +CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK = 0x00100000 # macro +CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK = 0x00200000 # macro +CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK = 0x00400000 # macro +CP_INT_STATUS__PRIV_REG_INT_STAT_MASK = 0x00800000 # macro +CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK = 0x01000000 # macro +CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK = 0x04000000 # macro +CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK = 0x08000000 # macro +CP_INT_STATUS__GENERIC2_INT_STAT_MASK = 0x20000000 # macro +CP_INT_STATUS__GENERIC1_INT_STAT_MASK = 0x40000000 # macro +CP_INT_STATUS__GENERIC0_INT_STAT_MASK = 0x80000000 # macro +CP_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +CP_DEVICE_ID__DEVICE_ID_MASK = 0x000000FF # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_RING0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_RING0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_RING1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_RING1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT = 0x0 # macro +CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT = 0x1 # macro +CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT = 0x2 # macro +CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT = 0x3 # macro +CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT = 0x4 # macro +CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK = 0x00000001 # macro +CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK = 0x00000002 # macro +CP_FATAL_ERROR__GFX_HALT_PROC_MASK = 0x00000004 # macro +CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK = 0x00000008 # macro +CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK = 0x00000010 # macro +CP_RB_VMID__RB0_VMID__SHIFT = 0x0 # macro +CP_RB_VMID__RB1_VMID__SHIFT = 0x8 # macro +CP_RB_VMID__RB2_VMID__SHIFT = 0x10 # macro +CP_RB_VMID__RB0_VMID_MASK = 0x0000000F # macro +CP_RB_VMID__RB1_VMID_MASK = 0x00000F00 # macro +CP_RB_VMID__RB2_VMID_MASK = 0x000F0000 # macro +CP_ME0_PIPE0_VMID__VMID__SHIFT = 0x0 # macro +CP_ME0_PIPE0_VMID__VMID_MASK = 0x0000000F # macro +CP_ME0_PIPE1_VMID__VMID__SHIFT = 0x0 # macro +CP_ME0_PIPE1_VMID__VMID_MASK = 0x0000000F # macro +CP_RB0_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_RB0_WPTR__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_RB_WPTR__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB0_WPTR_HI__RB_WPTR__SHIFT = 0x0 # macro +CP_RB0_WPTR_HI__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB_WPTR_HI__RB_WPTR__SHIFT = 0x0 # macro +CP_RB_WPTR_HI__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB1_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_RB1_WPTR__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB1_WPTR_HI__RB_WPTR__SHIFT = 0x0 # macro +CP_RB1_WPTR_HI__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT = 0x0 # macro +CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT = 0x1c # macro +CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT = 0x1d # macro +CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT = 0x1f # macro +CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK = 0x0FFFFFFF # macro +CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK = 0x10000000 # macro +CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK = 0x60000000 # macro +CP_PROCESS_QUANTUM__QUANTUM_EN_MASK = 0x80000000 # macro +CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT = 0x2 # macro +CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK = 0x00000FFC # macro +CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT = 0x2 # macro +CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK = 0x00000FFC # macro +CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT = 0x2 # macro +CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK = 0x00000FFC # macro +CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT = 0x2 # macro +CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK = 0x00000FFC # macro +CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT = 0x0 # macro +CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK = 0x00000001 # macro +CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT = 0x0 # macro +CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK = 0x00000001 # macro +CP_RB1_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_RB1_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_RB1_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_RB1_CNTL__TMZ_STATE__SHIFT = 0x6 # macro +CP_RB1_CNTL__TMZ_MATCH__SHIFT = 0x7 # macro +CP_RB1_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_RB1_CNTL__RB_NON_PRIV__SHIFT = 0xf # macro +CP_RB1_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_RB1_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_RB1_CNTL__RB_VOLATILE__SHIFT = 0x1a # macro +CP_RB1_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_RB1_CNTL__RB_EXE__SHIFT = 0x1c # macro +CP_RB1_CNTL__KMD_QUEUE__SHIFT = 0x1d # macro +CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_RB1_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_RB1_CNTL__TMZ_STATE_MASK = 0x00000040 # macro +CP_RB1_CNTL__TMZ_MATCH_MASK = 0x00000080 # macro +CP_RB1_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_RB1_CNTL__RB_NON_PRIV_MASK = 0x00008000 # macro +CP_RB1_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_RB1_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_RB1_CNTL__RB_VOLATILE_MASK = 0x04000000 # macro +CP_RB1_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_RB1_CNTL__RB_EXE_MASK = 0x10000000 # macro +CP_RB1_CNTL__KMD_QUEUE_MASK = 0x20000000 # macro +CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB1_BUFSZ_MASK__DATA__SHIFT = 0x0 # macro +CP_RB1_BUFSZ_MASK__DATA_MASK = 0x000FFFFF # macro +CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT = 0x8 # macro +CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT = 0x9 # macro +CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT = 0xa # macro +CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT = 0xb # macro +CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT = 0x12 # macro +CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT = 0x13 # macro +CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT = 0x14 # macro +CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT = 0x15 # macro +CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT = 0x16 # macro +CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK = 0x00000100 # macro +CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK = 0x00000200 # macro +CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK = 0x00000400 # macro +CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK = 0x00000800 # macro +CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK = 0x00040000 # macro +CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK = 0x00080000 # macro +CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK = 0x00100000 # macro +CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK = 0x00200000 # macro +CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK = 0x00400000 # macro +CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT = 0x16 # macro +CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK = 0x00400000 # macro +CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT = 0x8 # macro +CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT = 0x9 # macro +CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT = 0xa # macro +CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT = 0xb # macro +CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT = 0xe # macro +CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT = 0x10 # macro +CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT = 0x11 # macro +CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT = 0x12 # macro +CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT = 0x13 # macro +CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT = 0x14 # macro +CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT = 0x15 # macro +CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT = 0x16 # macro +CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT = 0x17 # macro +CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT = 0x18 # macro +CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT = 0x1a # macro +CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT = 0x1b # macro +CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT = 0x1d # macro +CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT = 0x1e # macro +CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT = 0x1f # macro +CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK = 0x00000100 # macro +CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK = 0x00000200 # macro +CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK = 0x00000400 # macro +CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK = 0x00000800 # macro +CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK = 0x00004000 # macro +CP_INT_STATUS_RING0__GPF_INT_STAT_MASK = 0x00010000 # macro +CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK = 0x00020000 # macro +CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK = 0x00040000 # macro +CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK = 0x00080000 # macro +CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK = 0x00100000 # macro +CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK = 0x00200000 # macro +CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK = 0x00400000 # macro +CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK = 0x00800000 # macro +CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK = 0x01000000 # macro +CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK = 0x04000000 # macro +CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK = 0x08000000 # macro +CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK = 0x20000000 # macro +CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK = 0x40000000 # macro +CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK = 0x80000000 # macro +CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT = 0xe # macro +CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT = 0x10 # macro +CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT = 0x11 # macro +CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT = 0x16 # macro +CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT = 0x17 # macro +CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT = 0x18 # macro +CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT = 0x1a # macro +CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT = 0x1b # macro +CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT = 0x1d # macro +CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT = 0x1e # macro +CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT = 0x1f # macro +CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK = 0x00004000 # macro +CP_INT_STATUS_RING1__GPF_INT_STAT_MASK = 0x00010000 # macro +CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK = 0x00020000 # macro +CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK = 0x00400000 # macro +CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK = 0x00800000 # macro +CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK = 0x01000000 # macro +CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK = 0x04000000 # macro +CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK = 0x08000000 # macro +CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK = 0x20000000 # macro +CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK = 0x40000000 # macro +CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK = 0x80000000 # macro +CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT = 0x0 # macro +CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT = 0x1 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT = 0x2 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT = 0x3 # macro +CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK = 0x00000001 # macro +CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK = 0x00000002 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK = 0x00000004 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK = 0x00000008 # macro +CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT = 0x0 # macro +CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT = 0x3 # macro +CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK = 0x00000001 # macro +CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK = 0x00000008 # macro +CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT = 0x0 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT = 0x1 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT = 0x8 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT = 0x9 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT = 0xa # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT = 0xb # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT = 0x10 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT = 0x11 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT = 0x12 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT = 0x13 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT = 0x14 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT = 0x15 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT = 0x16 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT = 0x17 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK = 0x00000001 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK = 0x00000002 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK = 0x00000100 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK = 0x00000200 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK = 0x00000400 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK = 0x00000800 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK = 0x00010000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK = 0x00020000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK = 0x00040000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK = 0x00080000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK = 0x00100000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK = 0x00200000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK = 0x00400000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK = 0x00800000 # macro +CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT = 0x0 # macro +CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT = 0x4 # macro +CP_ECC_FIRSTOCCURRENCE__ME__SHIFT = 0x8 # macro +CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT = 0xa # macro +CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT = 0x10 # macro +CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK = 0x00000003 # macro +CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK = 0x000000F0 # macro +CP_ECC_FIRSTOCCURRENCE__ME_MASK = 0x00000300 # macro +CP_ECC_FIRSTOCCURRENCE__PIPE_MASK = 0x00000C00 # macro +CP_ECC_FIRSTOCCURRENCE__VMID_MASK = 0x000F0000 # macro +CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT = 0x0 # macro +CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK = 0xFFFFFFFF # macro +CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT = 0x0 # macro +CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK = 0xFFFFFFFF # macro +GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT = 0xf # macro +GB_EDC_MODE__COUNT_FED_OUT__SHIFT = 0x10 # macro +GB_EDC_MODE__GATE_FUE__SHIFT = 0x11 # macro +GB_EDC_MODE__DED_MODE__SHIFT = 0x14 # macro +GB_EDC_MODE__PROP_FED__SHIFT = 0x1d # macro +GB_EDC_MODE__BYPASS__SHIFT = 0x1f # macro +GB_EDC_MODE__FORCE_SEC_ON_DED_MASK = 0x00008000 # macro +GB_EDC_MODE__COUNT_FED_OUT_MASK = 0x00010000 # macro +GB_EDC_MODE__GATE_FUE_MASK = 0x00020000 # macro +GB_EDC_MODE__DED_MODE_MASK = 0x00300000 # macro +GB_EDC_MODE__PROP_FED_MASK = 0x20000000 # macro +GB_EDC_MODE__BYPASS_MASK = 0x80000000 # macro +CP_DEBUG__PERFMON_RING_SEL__SHIFT = 0x0 # macro +CP_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT = 0x2 # macro +CP_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT = 0x8 # macro +CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT = 0x9 # macro +CP_DEBUG__PACKET_FILTER_DISABLE__SHIFT = 0xa # macro +CP_DEBUG__NOT_EOP_PREEMPT_DISABLE__SHIFT = 0xb # macro +CP_DEBUG__CPG_CHIU_RO_DISABLE__SHIFT = 0xc # macro +CP_DEBUG__CPG_GCR_CNTL_BYPASS__SHIFT = 0xd # macro +CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT = 0xe # macro +CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE__SHIFT = 0xf # macro +CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT = 0x10 # macro +CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT = 0x14 # macro +CP_DEBUG__CPG_CHIU_GUS_DISABLE__SHIFT = 0x15 # macro +CP_DEBUG__INTERRUPT_DISABLE__SHIFT = 0x16 # macro +CP_DEBUG__PREDICATE_DISABLE__SHIFT = 0x17 # macro +CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT = 0x18 # macro +CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT = 0x19 # macro +CP_DEBUG__EVENT_FILT_DISABLE__SHIFT = 0x1a # macro +CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE__SHIFT = 0x1b # macro +CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT = 0x1c # macro +CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT = 0x1d # macro +CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT = 0x1e # macro +CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT = 0x1f # macro +CP_DEBUG__PERFMON_RING_SEL_MASK = 0x00000003 # macro +CP_DEBUG__DEBUG_BUS_SELECT_BITS_MASK = 0x000000FC # macro +CP_DEBUG__DEBUG_BUS_FLOP_EN_MASK = 0x00000100 # macro +CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK = 0x00000200 # macro +CP_DEBUG__PACKET_FILTER_DISABLE_MASK = 0x00000400 # macro +CP_DEBUG__NOT_EOP_PREEMPT_DISABLE_MASK = 0x00000800 # macro +CP_DEBUG__CPG_CHIU_RO_DISABLE_MASK = 0x00001000 # macro +CP_DEBUG__CPG_GCR_CNTL_BYPASS_MASK = 0x00002000 # macro +CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK = 0x00004000 # macro +CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE_MASK = 0x00008000 # macro +CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK = 0x00070000 # macro +CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK = 0x00100000 # macro +CP_DEBUG__CPG_CHIU_GUS_DISABLE_MASK = 0x00200000 # macro +CP_DEBUG__INTERRUPT_DISABLE_MASK = 0x00400000 # macro +CP_DEBUG__PREDICATE_DISABLE_MASK = 0x00800000 # macro +CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK = 0x01000000 # macro +CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK = 0x02000000 # macro +CP_DEBUG__EVENT_FILT_DISABLE_MASK = 0x04000000 # macro +CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE_MASK = 0x08000000 # macro +CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK = 0x10000000 # macro +CP_DEBUG__CS_STATE_FILT_DISABLE_MASK = 0x20000000 # macro +CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK = 0x40000000 # macro +CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK = 0x80000000 # macro +CP_CPC_DEBUG__PIPE_SELECT__SHIFT = 0x0 # macro +CP_CPC_DEBUG__ME_SELECT__SHIFT = 0x2 # macro +CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE__SHIFT = 0x4 # macro +CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT = 0xe # macro +CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT = 0xf # macro +CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE__SHIFT = 0x10 # macro +CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS__SHIFT = 0x11 # macro +CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT = 0x12 # macro +CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT = 0x14 # macro +CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT = 0x15 # macro +CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT = 0x16 # macro +CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE__SHIFT = 0x17 # macro +CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT = 0x18 # macro +CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT = 0x19 # macro +CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT = 0x1a # macro +CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE__SHIFT = 0x1b # macro +CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT = 0x1c # macro +CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT = 0x1d # macro +CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE__SHIFT = 0x1e # macro +CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT = 0x1f # macro +CP_CPC_DEBUG__PIPE_SELECT_MASK = 0x00000003 # macro +CP_CPC_DEBUG__ME_SELECT_MASK = 0x00000004 # macro +CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE_MASK = 0x00000010 # macro +CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN_MASK = 0x00004000 # macro +CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK = 0x00008000 # macro +CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE_MASK = 0x00010000 # macro +CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS_MASK = 0x00020000 # macro +CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK = 0x00040000 # macro +CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK = 0x00100000 # macro +CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK = 0x00200000 # macro +CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK = 0x00400000 # macro +CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE_MASK = 0x00800000 # macro +CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK = 0x01000000 # macro +CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK = 0x02000000 # macro +CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK = 0x04000000 # macro +CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE_MASK = 0x08000000 # macro +CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK = 0x10000000 # macro +CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK = 0x20000000 # macro +CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE_MASK = 0x40000000 # macro +CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK = 0x80000000 # macro +CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT = 0x0 # macro +CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT = 0x1d # macro +CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT = 0x1e # macro +CP_PQ_WPTR_POLL_CNTL__EN__SHIFT = 0x1f # macro +CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK = 0x000000FF # macro +CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK = 0x20000000 # macro +CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK = 0x40000000 # macro +CP_PQ_WPTR_POLL_CNTL__EN_MASK = 0x80000000 # macro +CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT = 0x0 # macro +CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK = 0xFFFFFFFF # macro +CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT = 0x17 # macro +CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK = 0x00800000 # macro +CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT = 0x17 # macro +CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK = 0x00800000 # macro +CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT = 0x0 # macro +CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT = 0x4 # macro +CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT = 0x8 # macro +CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK = 0x00000001 # macro +CP_GFX_QUEUE_INDEX__PIPE_ID_MASK = 0x00000030 # macro +CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK = 0x00000700 # macro +CC_GC_EDC_CONFIG__DIS_EDC__SHIFT = 0x1 # macro +CC_GC_EDC_CONFIG__DIS_EDC_MASK = 0x00000002 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_PFP_PRGRM_CNTR_START__IP_START_MASK = 0xFFFFFFFF # macro +CP_ME_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_ME_PRGRM_CNTR_START__IP_START_MASK = 0xFFFFFFFF # macro +CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_MEC1_PRGRM_CNTR_START__IP_START_MASK = 0x000FFFFF # macro +CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_MEC2_PRGRM_CNTR_START__IP_START_MASK = 0x000FFFFF # macro +CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_PFP_INTR_ROUTINE_START__IR_START_MASK = 0xFFFFFFFF # macro +CP_ME_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_ME_INTR_ROUTINE_START__IR_START_MASK = 0xFFFFFFFF # macro +CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_MEC1_INTR_ROUTINE_START__IR_START_MASK = 0x000FFFFF # macro +CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_MEC2_INTR_ROUTINE_START__IR_START_MASK = 0x000FFFFF # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT = 0x0 # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT = 0x4 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT = 0x10 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT = 0x14 # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK = 0x00000007 # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK = 0x00000070 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK = 0x00070000 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK = 0x00700000 # macro +CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT = 0x0 # macro +CP_MAX_CONTEXT__MAX_CONTEXT_MASK = 0x00000007 # macro +CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT = 0x0 # macro +CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT = 0x8 # macro +CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT = 0x10 # macro +CP_IQ_WAIT_TIME1__GWS__SHIFT = 0x18 # macro +CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK = 0x000000FF # macro +CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK = 0x0000FF00 # macro +CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK = 0x00FF0000 # macro +CP_IQ_WAIT_TIME1__GWS_MASK = 0xFF000000 # macro +CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT = 0x0 # macro +CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT = 0x8 # macro +CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT = 0x10 # macro +CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT = 0x18 # macro +CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK = 0x000000FF # macro +CP_IQ_WAIT_TIME2__SCH_WAVE_MASK = 0x0000FF00 # macro +CP_IQ_WAIT_TIME2__SEM_REARM_MASK = 0x00FF0000 # macro +CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK = 0xFF000000 # macro +CP_RB0_BASE_HI__RB_BASE_HI__SHIFT = 0x0 # macro +CP_RB0_BASE_HI__RB_BASE_HI_MASK = 0x000000FF # macro +CP_RB1_BASE_HI__RB_BASE_HI__SHIFT = 0x0 # macro +CP_RB1_BASE_HI__RB_BASE_HI_MASK = 0x000000FF # macro +CP_VMID_RESET__RESET_REQUEST__SHIFT = 0x0 # macro +CP_VMID_RESET__PIPE0_QUEUES__SHIFT = 0x10 # macro +CP_VMID_RESET__PIPE1_QUEUES__SHIFT = 0x18 # macro +CP_VMID_RESET__RESET_REQUEST_MASK = 0x0000FFFF # macro +CP_VMID_RESET__PIPE0_QUEUES_MASK = 0x00FF0000 # macro +CP_VMID_RESET__PIPE1_QUEUES_MASK = 0xFF000000 # macro +CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CPC_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CPC_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CPC_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT = 0x0 # macro +CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT = 0x10 # macro +CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK = 0x0000FFFF # macro +CP_VMID_PREEMPT__VIRT_COMMAND_MASK = 0x000F0000 # macro +CPC_INT_CNTX_ID__CNTX_ID__SHIFT = 0x0 # macro +CPC_INT_CNTX_ID__CNTX_ID_MASK = 0xFFFFFFFF # macro +CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT = 0x0 # macro +CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT = 0x1 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT = 0x2 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT = 0x3 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_MASK = 0x00000001 # macro +CP_PQ_STATUS__DOORBELL_ENABLE_MASK = 0x00000002 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK = 0x00000004 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK = 0x00000008 # macro +CP_PFP_PRGRM_CNTR_START_HI__IP_START__SHIFT = 0x0 # macro +CP_PFP_PRGRM_CNTR_START_HI__IP_START_MASK = 0x3FFFFFFF # macro +CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT__SHIFT = 0x0 # macro +CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT_MASK = 0xFFFFFFFF # macro +CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT = 0x0 # macro +CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT = 0x10 # macro +CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK = 0x0000FFFF # macro +CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK = 0xFFFF0000 # macro +CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT = 0xc # macro +CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK = 0xFFFFF000 # macro +CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT = 0x3 # macro +CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK = 0x00000018 # macro +CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT = 0x2 # macro +CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK = 0x0000FFFC # macro +CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT = 0xc # macro +CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK = 0x0000F000 # macro +CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT = 0x2 # macro +CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK = 0x03FFFFFC # macro +CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT = 0xc # macro +CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK = 0x03FFF000 # macro +CPC_OS_PIPES__OS_PIPES__SHIFT = 0x0 # macro +CPC_OS_PIPES__OS_PIPES_MASK = 0x000000FF # macro +CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT = 0x0 # macro +CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT = 0x1 # macro +CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK = 0x00000001 # macro +CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK = 0x00000002 # macro +CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT = 0x0 # macro +CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT = 0x1 # macro +CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT = 0x2 # macro +CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT = 0x3 # macro +CP_SUSPEND_CNTL__SUSPEND_MODE_MASK = 0x00000001 # macro +CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK = 0x00000002 # macro +CP_SUSPEND_CNTL__RESUME_LOCK_MASK = 0x00000004 # macro +CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK = 0x00000008 # macro +CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT = 0x0 # macro +CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK = 0x000000FF # macro +CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT = 0x6 # macro +CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK = 0xFFFFFFC0 # macro +CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT = 0x6 # macro +CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK = 0xFFFFFFC0 # macro +CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CPC_DDID_CNTL__THRESHOLD__SHIFT = 0x0 # macro +CPC_DDID_CNTL__SIZE__SHIFT = 0x10 # macro +CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT = 0x13 # macro +CPC_DDID_CNTL__POLICY__SHIFT = 0x1c # macro +CPC_DDID_CNTL__MODE__SHIFT = 0x1e # macro +CPC_DDID_CNTL__ENABLE__SHIFT = 0x1f # macro +CPC_DDID_CNTL__THRESHOLD_MASK = 0x000000FF # macro +CPC_DDID_CNTL__SIZE_MASK = 0x00010000 # macro +CPC_DDID_CNTL__NO_RING_MEMORY_MASK = 0x00080000 # macro +CPC_DDID_CNTL__POLICY_MASK = 0x30000000 # macro +CPC_DDID_CNTL__MODE_MASK = 0x40000000 # macro +CPC_DDID_CNTL__ENABLE_MASK = 0x80000000 # macro +CP_DDID_CNTL__THRESHOLD__SHIFT = 0x0 # macro +CP_DDID_CNTL__SIZE__SHIFT = 0x10 # macro +CP_DDID_CNTL__NO_RING_MEMORY__SHIFT = 0x13 # macro +CP_DDID_CNTL__VMID__SHIFT = 0x14 # macro +CP_DDID_CNTL__VMID_SEL__SHIFT = 0x18 # macro +CP_DDID_CNTL__POLICY__SHIFT = 0x1c # macro +CP_DDID_CNTL__MODE__SHIFT = 0x1e # macro +CP_DDID_CNTL__ENABLE__SHIFT = 0x1f # macro +CP_DDID_CNTL__THRESHOLD_MASK = 0x000000FF # macro +CP_DDID_CNTL__SIZE_MASK = 0x00010000 # macro +CP_DDID_CNTL__NO_RING_MEMORY_MASK = 0x00080000 # macro +CP_DDID_CNTL__VMID_MASK = 0x00F00000 # macro +CP_DDID_CNTL__VMID_SEL_MASK = 0x01000000 # macro +CP_DDID_CNTL__POLICY_MASK = 0x30000000 # macro +CP_DDID_CNTL__MODE_MASK = 0x40000000 # macro +CP_DDID_CNTL__ENABLE_MASK = 0x80000000 # macro +CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT = 0x0 # macro +CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK = 0x0000FFFF # macro +CP_GFX_DDID_WPTR__COUNT__SHIFT = 0x0 # macro +CP_GFX_DDID_WPTR__COUNT_MASK = 0x0000FFFF # macro +CP_GFX_DDID_RPTR__COUNT__SHIFT = 0x0 # macro +CP_GFX_DDID_RPTR__COUNT_MASK = 0x0000FFFF # macro +CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT = 0x0 # macro +CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK = 0x000000FF # macro +CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT = 0x0 # macro +CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT = 0x5 # macro +CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT = 0x8 # macro +CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT = 0x10 # macro +CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT = 0x14 # macro +CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT = 0x1c # macro +CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT = 0x1d # macro +CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT = 0x1e # macro +CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT = 0x1f # macro +CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK = 0x0000001F # macro +CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK = 0x000000E0 # macro +CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK = 0x0000FF00 # macro +CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK = 0x00070000 # macro +CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK = 0x01F00000 # macro +CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK = 0x10000000 # macro +CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK = 0x20000000 # macro +CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK = 0x40000000 # macro +CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK = 0x80000000 # macro +CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT = 0x0 # macro +CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT = 0x4 # macro +CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL__SHIFT = 0x8 # macro +CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK = 0x00000001 # macro +CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK = 0x00000010 # macro +CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL_MASK = 0x00000100 # macro +CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT = 0x0 # macro +CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT = 0x0 # macro +CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_INDEX_MUTEX__REQUEST__SHIFT = 0x0 # macro +CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT = 0x1 # macro +CP_GFX_INDEX_MUTEX__REQUEST_MASK = 0x00000001 # macro +CP_GFX_INDEX_MUTEX__CLIENTID_MASK = 0x0000000E # macro +CP_ME_PRGRM_CNTR_START_HI__IP_START__SHIFT = 0x0 # macro +CP_ME_PRGRM_CNTR_START_HI__IP_START_MASK = 0x3FFFFFFF # macro +CP_PFP_INTR_ROUTINE_START_HI__IR_START__SHIFT = 0x0 # macro +CP_PFP_INTR_ROUTINE_START_HI__IR_START_MASK = 0x3FFFFFFF # macro +CP_ME_INTR_ROUTINE_START_HI__IR_START__SHIFT = 0x0 # macro +CP_ME_INTR_ROUTINE_START_HI__IR_START_MASK = 0x3FFFFFFF # macro +CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT = 0x2 # macro +CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFFFFC # macro +CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT = 0x1c # macro +CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK = 0xF0000000 # macro +CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_GFX_HQD_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_GFX_HQD_VMID__VMID__SHIFT = 0x0 # macro +CP_GFX_HQD_VMID__VMID_MASK = 0x0000000F # macro +CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT = 0x0 # macro +CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK = 0x0000000F # macro +CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT = 0x0 # macro +CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT = 0x3 # macro +CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT = 0x8 # macro +CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT = 0x1f # macro +CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK = 0x00000001 # macro +CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK = 0x00000018 # macro +CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK = 0x0000FF00 # macro +CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK = 0x80000000 # macro +CP_GFX_HQD_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_GFX_HQD_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT = 0x0 # macro +CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK = 0x000000FF # macro +CP_GFX_HQD_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_GFX_HQD_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT = 0x2 # macro +CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT = 0x0 # macro +CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT = 0x1 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK = 0x00000002 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT = 0x0 # macro +CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT = 0x1f # macro +CP_GFX_HQD_OFFSET__RB_OFFSET_MASK = 0x000FFFFF # macro +CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK = 0x80000000 # macro +CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_GFX_HQD_CNTL__TMZ_STATE__SHIFT = 0x6 # macro +CP_GFX_HQD_CNTL__TMZ_MATCH__SHIFT = 0x7 # macro +CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT = 0xf # macro +CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT = 0x10 # macro +CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT = 0x1a # macro +CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_GFX_HQD_CNTL__RB_EXE__SHIFT = 0x1c # macro +CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT = 0x1d # macro +CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_GFX_HQD_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_GFX_HQD_CNTL__TMZ_STATE_MASK = 0x00000040 # macro +CP_GFX_HQD_CNTL__TMZ_MATCH_MASK = 0x00000080 # macro +CP_GFX_HQD_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK = 0x00008000 # macro +CP_GFX_HQD_CNTL__BUF_SWAP_MASK = 0x00030000 # macro +CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_GFX_HQD_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_GFX_HQD_CNTL__RB_VOLATILE_MASK = 0x04000000 # macro +CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_GFX_HQD_CNTL__RB_EXE_MASK = 0x10000000 # macro +CP_GFX_HQD_CNTL__KMD_QUEUE_MASK = 0x20000000 # macro +CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_GFX_HQD_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_GFX_HQD_WPTR__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT = 0x0 # macro +CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT = 0x0 # macro +CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT = 0x4 # macro +CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT = 0x9 # macro +CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT = 0xa # macro +CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK = 0x00000001 # macro +CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK = 0x00000010 # macro +CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK = 0x00000200 # macro +CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK = 0x00000400 # macro +CP_GFX_HQD_MAPPED__MAPPED__SHIFT = 0x0 # macro +CP_GFX_HQD_MAPPED__MAPPED_MASK = 0x00000001 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT__SHIFT = 0x0 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE__SHIFT = 0x4 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT__SHIFT = 0x5 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN__SHIFT = 0x6 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN__SHIFT = 0x7 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE__SHIFT = 0x8 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE__SHIFT = 0xb # macro +CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE__SHIFT = 0xd # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR__SHIFT = 0xf # macro +CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE__SHIFT = 0x10 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE__SHIFT = 0x11 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT__SHIFT = 0x12 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG__SHIFT = 0x17 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT_MASK = 0x00000001 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE_MASK = 0x00000010 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT_MASK = 0x00000020 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN_MASK = 0x00000040 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN_MASK = 0x00000080 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_MASK = 0x00000700 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE_MASK = 0x00000800 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE_MASK = 0x00002000 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR_MASK = 0x00008000 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE_MASK = 0x00010000 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE_MASK = 0x00020000 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT_MASK = 0x00040000 # macro +CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG_MASK = 0x00800000 # macro +CP_GFX_HQD_IQ_TIMER__WAIT_TIME__SHIFT = 0x0 # macro +CP_GFX_HQD_IQ_TIMER__RETRY_TYPE__SHIFT = 0x8 # macro +CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT = 0xb # macro +CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT = 0xc # macro +CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT = 0xe # macro +CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT = 0x16 # macro +CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT = 0x1b # macro +CP_GFX_HQD_IQ_TIMER__REARM_TIMER__SHIFT = 0x1c # macro +CP_GFX_HQD_IQ_TIMER__ACTIVE__SHIFT = 0x1f # macro +CP_GFX_HQD_IQ_TIMER__WAIT_TIME_MASK = 0x000000FF # macro +CP_GFX_HQD_IQ_TIMER__RETRY_TYPE_MASK = 0x00000700 # macro +CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK = 0x00000800 # macro +CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK = 0x00003000 # macro +CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT_MASK = 0x0000C000 # macro +CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER_MASK = 0x00400000 # macro +CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE_MASK = 0x08000000 # macro +CP_GFX_HQD_IQ_TIMER__REARM_TIMER_MASK = 0x10000000 # macro +CP_GFX_HQD_IQ_TIMER__ACTIVE_MASK = 0x80000000 # macro +CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT = 0x0 # macro +CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT = 0x4 # macro +CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT = 0x6 # macro +CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT = 0x1e # macro +CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK = 0x00000001 # macro +CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK = 0x00000030 # macro +CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK = 0x00000040 # macro +CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK = 0x40000000 # macro +CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT = 0x0 # macro +CP_GFX_HQD_HQ_CONTROL0__SPARES__SHIFT = 0x4 # macro +CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK = 0x0000000F # macro +CP_GFX_HQD_HQ_CONTROL0__SPARES_MASK = 0x000000F0 # macro +CP_GFX_MQD_CONTROL__VMID__SHIFT = 0x0 # macro +CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT = 0x8 # macro +CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT = 0xc # macro +CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT = 0xd # macro +CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_GFX_MQD_CONTROL__VMID_MASK = 0x0000000F # macro +CP_GFX_MQD_CONTROL__PRIV_STATE_MASK = 0x00000100 # macro +CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK = 0x00001000 # macro +CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK = 0x00002000 # macro +CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_HQD_GFX_CONTROL__MESSAGE__SHIFT = 0x0 # macro +CP_HQD_GFX_CONTROL__MISC__SHIFT = 0x4 # macro +CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT = 0xf # macro +CP_HQD_GFX_CONTROL__MESSAGE_MASK = 0x0000000F # macro +CP_HQD_GFX_CONTROL__MISC_MASK = 0x00007FF0 # macro +CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK = 0x00008000 # macro +CP_HQD_GFX_STATUS__STATUS__SHIFT = 0x0 # macro +CP_HQD_GFX_STATUS__STATUS_MASK = 0x0000FFFF # macro +CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT = 0x7 # macro +CP_DMA_WATCH0_ADDR_LO__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_WATCH0_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +CP_DMA_WATCH0_MASK__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH0_MASK__MASK__SHIFT = 0x7 # macro +CP_DMA_WATCH0_MASK__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH0_MASK__MASK_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH0_CNTL__VMID__SHIFT = 0x0 # macro +CP_DMA_WATCH0_CNTL__RSVD1__SHIFT = 0x4 # macro +CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT = 0x8 # macro +CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT = 0x9 # macro +CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT = 0xa # macro +CP_DMA_WATCH0_CNTL__RSVD2__SHIFT = 0xb # macro +CP_DMA_WATCH0_CNTL__VMID_MASK = 0x0000000F # macro +CP_DMA_WATCH0_CNTL__RSVD1_MASK = 0x000000F0 # macro +CP_DMA_WATCH0_CNTL__WATCH_READS_MASK = 0x00000100 # macro +CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK = 0x00000200 # macro +CP_DMA_WATCH0_CNTL__ANY_VMID_MASK = 0x00000400 # macro +CP_DMA_WATCH0_CNTL__RSVD2_MASK = 0xFFFFF800 # macro +CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT = 0x7 # macro +CP_DMA_WATCH1_ADDR_LO__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_WATCH1_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +CP_DMA_WATCH1_MASK__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH1_MASK__MASK__SHIFT = 0x7 # macro +CP_DMA_WATCH1_MASK__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH1_MASK__MASK_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH1_CNTL__VMID__SHIFT = 0x0 # macro +CP_DMA_WATCH1_CNTL__RSVD1__SHIFT = 0x4 # macro +CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT = 0x8 # macro +CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT = 0x9 # macro +CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT = 0xa # macro +CP_DMA_WATCH1_CNTL__RSVD2__SHIFT = 0xb # macro +CP_DMA_WATCH1_CNTL__VMID_MASK = 0x0000000F # macro +CP_DMA_WATCH1_CNTL__RSVD1_MASK = 0x000000F0 # macro +CP_DMA_WATCH1_CNTL__WATCH_READS_MASK = 0x00000100 # macro +CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK = 0x00000200 # macro +CP_DMA_WATCH1_CNTL__ANY_VMID_MASK = 0x00000400 # macro +CP_DMA_WATCH1_CNTL__RSVD2_MASK = 0xFFFFF800 # macro +CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT = 0x7 # macro +CP_DMA_WATCH2_ADDR_LO__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_WATCH2_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +CP_DMA_WATCH2_MASK__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH2_MASK__MASK__SHIFT = 0x7 # macro +CP_DMA_WATCH2_MASK__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH2_MASK__MASK_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH2_CNTL__VMID__SHIFT = 0x0 # macro +CP_DMA_WATCH2_CNTL__RSVD1__SHIFT = 0x4 # macro +CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT = 0x8 # macro +CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT = 0x9 # macro +CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT = 0xa # macro +CP_DMA_WATCH2_CNTL__RSVD2__SHIFT = 0xb # macro +CP_DMA_WATCH2_CNTL__VMID_MASK = 0x0000000F # macro +CP_DMA_WATCH2_CNTL__RSVD1_MASK = 0x000000F0 # macro +CP_DMA_WATCH2_CNTL__WATCH_READS_MASK = 0x00000100 # macro +CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK = 0x00000200 # macro +CP_DMA_WATCH2_CNTL__ANY_VMID_MASK = 0x00000400 # macro +CP_DMA_WATCH2_CNTL__RSVD2_MASK = 0xFFFFF800 # macro +CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT = 0x7 # macro +CP_DMA_WATCH3_ADDR_LO__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_WATCH3_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +CP_DMA_WATCH3_MASK__RSVD__SHIFT = 0x0 # macro +CP_DMA_WATCH3_MASK__MASK__SHIFT = 0x7 # macro +CP_DMA_WATCH3_MASK__RSVD_MASK = 0x0000007F # macro +CP_DMA_WATCH3_MASK__MASK_MASK = 0xFFFFFF80 # macro +CP_DMA_WATCH3_CNTL__VMID__SHIFT = 0x0 # macro +CP_DMA_WATCH3_CNTL__RSVD1__SHIFT = 0x4 # macro +CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT = 0x8 # macro +CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT = 0x9 # macro +CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT = 0xa # macro +CP_DMA_WATCH3_CNTL__RSVD2__SHIFT = 0xb # macro +CP_DMA_WATCH3_CNTL__VMID_MASK = 0x0000000F # macro +CP_DMA_WATCH3_CNTL__RSVD1_MASK = 0x000000F0 # macro +CP_DMA_WATCH3_CNTL__WATCH_READS_MASK = 0x00000100 # macro +CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK = 0x00000200 # macro +CP_DMA_WATCH3_CNTL__ANY_VMID_MASK = 0x00000400 # macro +CP_DMA_WATCH3_CNTL__RSVD2_MASK = 0xFFFFF800 # macro +CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_WATCH_STAT__VMID__SHIFT = 0x0 # macro +CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT = 0x4 # macro +CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT = 0x8 # macro +CP_DMA_WATCH_STAT__PIPE__SHIFT = 0xc # macro +CP_DMA_WATCH_STAT__WATCH_ID__SHIFT = 0x10 # macro +CP_DMA_WATCH_STAT__RD_WR__SHIFT = 0x14 # macro +CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT = 0x1f # macro +CP_DMA_WATCH_STAT__VMID_MASK = 0x0000000F # macro +CP_DMA_WATCH_STAT__QUEUE_ID_MASK = 0x00000070 # macro +CP_DMA_WATCH_STAT__CLIENT_ID_MASK = 0x00000700 # macro +CP_DMA_WATCH_STAT__PIPE_MASK = 0x00003000 # macro +CP_DMA_WATCH_STAT__WATCH_ID_MASK = 0x00030000 # macro +CP_DMA_WATCH_STAT__RD_WR_MASK = 0x00100000 # macro +CP_DMA_WATCH_STAT__TRAP_FLAG_MASK = 0x80000000 # macro +CP_PFP_JT_STAT__JT_LOADED__SHIFT = 0x0 # macro +CP_PFP_JT_STAT__WR_MASK__SHIFT = 0x10 # macro +CP_PFP_JT_STAT__JT_LOADED_MASK = 0x00000003 # macro +CP_PFP_JT_STAT__WR_MASK_MASK = 0x00030000 # macro +CP_MEC_JT_STAT__JT_LOADED__SHIFT = 0x0 # macro +CP_MEC_JT_STAT__WR_MASK__SHIFT = 0x10 # macro +CP_MEC_JT_STAT__JT_LOADED_MASK = 0x000000FF # macro +CP_MEC_JT_STAT__WR_MASK_MASK = 0x00FF0000 # macro +CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT = 0x0 # macro +CP_CPC_BUSY_HYSTERESIS__CPC_BUSY__SHIFT = 0x8 # macro +CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE_MASK = 0x000000FF # macro +CP_CPC_BUSY_HYSTERESIS__CPC_BUSY_MASK = 0x0000FF00 # macro +CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT = 0x0 # macro +CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY__SHIFT = 0x8 # macro +CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY__SHIFT = 0x10 # macro +CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT = 0x18 # macro +CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK = 0x000000FF # macro +CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY_MASK = 0x0000FF00 # macro +CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY_MASK = 0x00FF0000 # macro +CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY_MASK = 0xFF000000 # macro +CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT = 0x0 # macro +CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY_MASK = 0x000000FF # macro +CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT = 0x0 # macro +CP_CPG_BUSY_HYSTERESIS1__CP_BUSY__SHIFT = 0x8 # macro +CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY__SHIFT = 0x10 # macro +CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT = 0x18 # macro +CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK = 0x000000FF # macro +CP_CPG_BUSY_HYSTERESIS1__CP_BUSY_MASK = 0x0000FF00 # macro +CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY_MASK = 0x00FF0000 # macro +CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY_MASK = 0xFF000000 # macro +CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT = 0x0 # macro +CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0__SHIFT = 0x8 # macro +CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1__SHIFT = 0x10 # macro +CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY_MASK = 0x000000FF # macro +CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0_MASK = 0x0000FF00 # macro +CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1_MASK = 0x00FF0000 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT = 0x0 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT = 0x8 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT = 0x9 # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT = 0xa # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT = 0xb # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT = 0xc # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT = 0xd # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK = 0x00000007 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK = 0x00000100 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK = 0x00000200 # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK = 0x00000400 # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK = 0x00000800 # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK = 0x00001000 # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK = 0x00002000 # macro +CP_RB0_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_RB0_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_RB_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_RB_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_RB1_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_RB1_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_RB_STATUS__DOORBELL_UPDATED__SHIFT = 0x0 # macro +CP_RB_STATUS__DOORBELL_ENABLE__SHIFT = 0x1 # macro +CP_RB_STATUS__DOORBELL_UPDATED_MASK = 0x00000001 # macro +CP_RB_STATUS__DOORBELL_ENABLE_MASK = 0x00000002 # macro +CPG_RCIU_CAM_INDEX__INDEX__SHIFT = 0x0 # macro +CPG_RCIU_CAM_INDEX__INDEX_MASK = 0x0000001F # macro +CPG_RCIU_CAM_DATA__DATA__SHIFT = 0x0 # macro +CPG_RCIU_CAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT = 0x0 # macro +CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT = 0x18 # macro +CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT = 0x19 # macro +CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT = 0x1f # macro +CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK = 0x0003FFFF # macro +CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK = 0x01000000 # macro +CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK = 0x02000000 # macro +CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK = 0x80000000 # macro +CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT = 0x0 # macro +CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK = 0xFFFFFFFF # macro +CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT = 0x0 # macro +CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK = 0xFFFFFFFF # macro +CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT = 0x0 # macro +CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK = 0xFFFFFFFF # macro +CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT = 0x0 # macro +CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK = 0xFFFFFFFF # macro +CP_SDMA_DMA_DONE__SDMA_ID__SHIFT = 0x0 # macro +CP_SDMA_DMA_DONE__SDMA_ID_MASK = 0x0000000F # macro +CP_PFP_SDMA_CS__REQUEST_GRANT__SHIFT = 0x0 # macro +CP_PFP_SDMA_CS__SDMA_ID__SHIFT = 0x4 # macro +CP_PFP_SDMA_CS__REQUEST_POSITION__SHIFT = 0x8 # macro +CP_PFP_SDMA_CS__SDMA_COUNT__SHIFT = 0xc # macro +CP_PFP_SDMA_CS__REQUEST_GRANT_MASK = 0x00000001 # macro +CP_PFP_SDMA_CS__SDMA_ID_MASK = 0x000000F0 # macro +CP_PFP_SDMA_CS__REQUEST_POSITION_MASK = 0x00000F00 # macro +CP_PFP_SDMA_CS__SDMA_COUNT_MASK = 0x00003000 # macro +CP_ME_SDMA_CS__REQUEST_GRANT__SHIFT = 0x0 # macro +CP_ME_SDMA_CS__SDMA_ID__SHIFT = 0x4 # macro +CP_ME_SDMA_CS__REQUEST_POSITION__SHIFT = 0x8 # macro +CP_ME_SDMA_CS__SDMA_COUNT__SHIFT = 0xc # macro +CP_ME_SDMA_CS__REQUEST_GRANT_MASK = 0x00000001 # macro +CP_ME_SDMA_CS__SDMA_ID_MASK = 0x000000F0 # macro +CP_ME_SDMA_CS__REQUEST_POSITION_MASK = 0x00000F00 # macro +CP_ME_SDMA_CS__SDMA_COUNT_MASK = 0x00003000 # macro +CPF_GCR_CNTL__GCR_GL_CMD__SHIFT = 0x0 # macro +CPF_GCR_CNTL__GCR_GL_CMD_MASK = 0x0007FFFF # macro +CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +CPG_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +CPG_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +CPG_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +CPC_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +CPC_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +CPC_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +CPF_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +CPF_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +CPF_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +CP_SD_CNTL__CPF_EN__SHIFT = 0x0 # macro +CP_SD_CNTL__CPG_EN__SHIFT = 0x1 # macro +CP_SD_CNTL__CPC_EN__SHIFT = 0x2 # macro +CP_SD_CNTL__RLC_EN__SHIFT = 0x3 # macro +CP_SD_CNTL__GE_EN__SHIFT = 0x5 # macro +CP_SD_CNTL__UTCL1_EN__SHIFT = 0x6 # macro +CP_SD_CNTL__EA_EN__SHIFT = 0x9 # macro +CP_SD_CNTL__SDMA_EN__SHIFT = 0xa # macro +CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT = 0x1f # macro +CP_SD_CNTL__CPF_EN_MASK = 0x00000001 # macro +CP_SD_CNTL__CPG_EN_MASK = 0x00000002 # macro +CP_SD_CNTL__CPC_EN_MASK = 0x00000004 # macro +CP_SD_CNTL__RLC_EN_MASK = 0x00000008 # macro +CP_SD_CNTL__GE_EN_MASK = 0x00000020 # macro +CP_SD_CNTL__UTCL1_EN_MASK = 0x00000040 # macro +CP_SD_CNTL__EA_EN_MASK = 0x00000200 # macro +CP_SD_CNTL__SDMA_EN_MASK = 0x00000400 # macro +CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK = 0x80000000 # macro +CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT = 0x0 # macro +CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT = 0x1 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT = 0x2 # macro +CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT = 0x3 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT = 0x4 # macro +CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT = 0x5 # macro +CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT = 0x6 # macro +CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET__SHIFT = 0x7 # macro +CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK = 0x00000001 # macro +CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK = 0x00000002 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK = 0x00000004 # macro +CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK = 0x00000008 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK = 0x00000010 # macro +CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK = 0x00000020 # macro +CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK = 0x00000040 # macro +CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET_MASK = 0x00000080 # macro +CP_CPC_GFX_CNTL__QUEUEID__SHIFT = 0x0 # macro +CP_CPC_GFX_CNTL__PIPEID__SHIFT = 0x3 # macro +CP_CPC_GFX_CNTL__MEID__SHIFT = 0x5 # macro +CP_CPC_GFX_CNTL__VALID__SHIFT = 0x7 # macro +CP_CPC_GFX_CNTL__QUEUEID_MASK = 0x00000007 # macro +CP_CPC_GFX_CNTL__PIPEID_MASK = 0x00000018 # macro +CP_CPC_GFX_CNTL__MEID_MASK = 0x00000060 # macro +CP_CPC_GFX_CNTL__VALID_MASK = 0x00000080 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT = 0x0 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT = 0x3 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT = 0x6 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT = 0x9 # macro +SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT = 0xc # macro +SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT = 0xe # macro +SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT = 0x10 # macro +SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT = 0x12 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK = 0x00000007 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK = 0x00000038 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK = 0x000001C0 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK = 0x00000E00 # macro +SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK = 0x00003000 # macro +SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK = 0x0000C000 # macro +SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK = 0x00030000 # macro +SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK = 0x000C0000 # macro +SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT = 0x0 # macro +SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT = 0x10 # macro +SPI_ARB_CYCLES_0__TS0_DURATION_MASK = 0x0000FFFF # macro +SPI_ARB_CYCLES_0__TS1_DURATION_MASK = 0xFFFF0000 # macro +SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT = 0x0 # macro +SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT = 0x10 # macro +SPI_ARB_CYCLES_1__TS2_DURATION_MASK = 0x0000FFFF # macro +SPI_ARB_CYCLES_1__TS3_DURATION_MASK = 0xFFFF0000 # macro +SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT = 0xc # macro +SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT = 0x16 # macro +SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK = 0x0000007F # macro +SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK = 0x0001F000 # macro +SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK = 0x07C00000 # macro +SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT = 0xc # macro +SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT = 0x16 # macro +SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK = 0x0000007F # macro +SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK = 0x0001F000 # macro +SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK = 0x07C00000 # macro +SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK = 0x7F # macro +SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT = 0x0 # macro +SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK = 0x0000000F # macro +SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT = 0x0 # macro +SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT = 0x1 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT = 0x3 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT = 0x4 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT = 0xd # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT = 0xe # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT = 0xf # macro +SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK = 0x00000001 # macro +SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK = 0x00000006 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK = 0x00000008 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK = 0x00001FF0 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK = 0x00002000 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK = 0x00004000 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK = 0x00008000 # macro +SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT = 0x0 # macro +SPI_COMPUTE_QUEUE_RESET__RESET_MASK = 0x01 # macro +SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT = 0x0 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT = 0x1 # macro +SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT = 0x2 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT = 0x1e # macro +SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT = 0x1f # macro +SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK = 0x00000001 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK = 0x00000002 # macro +SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK = 0x00000004 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK = 0x40000000 # macro +SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK = 0x80000000 # macro +CP_HPD_UTCL1_CNTL__SELECT__SHIFT = 0x0 # macro +CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT__SHIFT = 0xa # macro +CP_HPD_UTCL1_CNTL__SELECT_MASK = 0x0000000F # macro +CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT_MASK = 0x00000400 # macro +CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT = 0x0 # macro +CP_HPD_UTCL1_ERROR__TYPE__SHIFT = 0x10 # macro +CP_HPD_UTCL1_ERROR__VMID__SHIFT = 0x14 # macro +CP_HPD_UTCL1_ERROR__ADDR_HI_MASK = 0x0000FFFF # macro +CP_HPD_UTCL1_ERROR__TYPE_MASK = 0x00010000 # macro +CP_HPD_UTCL1_ERROR__VMID_MASK = 0x00F00000 # macro +CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT = 0xc # macro +CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK = 0xFFFFF000 # macro +CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT = 0x2 # macro +CP_MQD_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFFFFC # macro +CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_HQD_ACTIVE__BUSY_GATE__SHIFT = 0x1 # macro +CP_HQD_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_HQD_ACTIVE__BUSY_GATE_MASK = 0x00000002 # macro +CP_HQD_VMID__VMID__SHIFT = 0x0 # macro +CP_HQD_VMID__IB_VMID__SHIFT = 0x8 # macro +CP_HQD_VMID__VQID__SHIFT = 0x10 # macro +CP_HQD_VMID__VMID_MASK = 0x0000000F # macro +CP_HQD_VMID__IB_VMID_MASK = 0x00000F00 # macro +CP_HQD_VMID__VQID_MASK = 0x03FF0000 # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT = 0x0 # macro +CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE__SHIFT = 0x1 # macro +CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT = 0x7 # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT = 0x8 # macro +CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT__SHIFT = 0x12 # macro +CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS__SHIFT = 0x13 # macro +CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT = 0x14 # macro +CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT = 0x15 # macro +CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT = 0x16 # macro +CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT = 0x17 # macro +CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT = 0x18 # macro +CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT = 0x19 # macro +CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT = 0x1a # macro +CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT = 0x1b # macro +CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT = 0x1c # macro +CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT = 0x1d # macro +CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT = 0x1e # macro +CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT = 0x1f # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK = 0x00000001 # macro +CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE_MASK = 0x00000002 # macro +CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK = 0x00000080 # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK = 0x0003FF00 # macro +CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT_MASK = 0x00040000 # macro +CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS_MASK = 0x00080000 # macro +CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK = 0x00100000 # macro +CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK = 0x00200000 # macro +CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK = 0x00400000 # macro +CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK = 0x00800000 # macro +CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK = 0x01000000 # macro +CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK = 0x02000000 # macro +CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK = 0x04000000 # macro +CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK = 0x08000000 # macro +CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK = 0x10000000 # macro +CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK = 0x20000000 # macro +CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK = 0x40000000 # macro +CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK = 0x80000000 # macro +CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT = 0x0 # macro +CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK = 0x00000003 # macro +CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT = 0x0 # macro +CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK = 0x0000000F # macro +CP_HQD_QUANTUM__QUANTUM_EN__SHIFT = 0x0 # macro +CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT = 0x4 # macro +CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT = 0x8 # macro +CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT = 0x1f # macro +CP_HQD_QUANTUM__QUANTUM_EN_MASK = 0x00000001 # macro +CP_HQD_QUANTUM__QUANTUM_SCALE_MASK = 0x00000010 # macro +CP_HQD_QUANTUM__QUANTUM_DURATION_MASK = 0x00003F00 # macro +CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK = 0x80000000 # macro +CP_HQD_PQ_BASE__ADDR__SHIFT = 0x0 # macro +CP_HQD_PQ_BASE__ADDR_MASK = 0xFFFFFFFF # macro +CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_PQ_BASE_HI__ADDR_HI_MASK = 0x000000FF # macro +CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT = 0x0 # macro +CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK = 0xFFFFFFFF # macro +CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT = 0x2 # macro +CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK = 0xFFFFFFFC # macro +CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT = 0x3 # macro +CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK = 0xFFFFFFF8 # macro +CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT = 0x0 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT = 0x1 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT = 0x1c # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT = 0x1d # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT = 0x1e # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK = 0x00000001 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK = 0x00000002 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK = 0x10000000 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK = 0x20000000 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK = 0x40000000 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT = 0x0 # macro +CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT = 0x6 # macro +CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT = 0x7 # macro +CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT = 0x8 # macro +CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT = 0xe # macro +CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT = 0xf # macro +CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT = 0x12 # macro +CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT = 0x14 # macro +CP_HQD_PQ_CONTROL__TMZ__SHIFT = 0x16 # macro +CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT = 0x1a # macro +CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT = 0x1b # macro +CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT = 0x1c # macro +CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT = 0x1d # macro +CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT = 0x1e # macro +CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT = 0x1f # macro +CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK = 0x0000003F # macro +CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK = 0x00000040 # macro +CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK = 0x00000080 # macro +CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK = 0x00003F00 # macro +CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK = 0x00004000 # macro +CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK = 0x00008000 # macro +CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK = 0x000C0000 # macro +CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK = 0x00300000 # macro +CP_HQD_PQ_CONTROL__TMZ_MASK = 0x00400000 # macro +CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK = 0x04000000 # macro +CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK = 0x08000000 # macro +CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK = 0x10000000 # macro +CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK = 0x20000000 # macro +CP_HQD_PQ_CONTROL__PRIV_STATE_MASK = 0x40000000 # macro +CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK = 0x80000000 # macro +CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT = 0x2 # macro +CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK = 0xFFFFFFFC # macro +CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT = 0x0 # macro +CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK = 0x000FFFFF # macro +CP_HQD_IB_CONTROL__IB_SIZE__SHIFT = 0x0 # macro +CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT = 0x14 # macro +CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT = 0x1a # macro +CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT = 0x1f # macro +CP_HQD_IB_CONTROL__IB_SIZE_MASK = 0x000FFFFF # macro +CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK = 0x00300000 # macro +CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK = 0x03000000 # macro +CP_HQD_IB_CONTROL__IB_VOLATILE_MASK = 0x04000000 # macro +CP_HQD_IB_CONTROL__PROCESSING_IB_MASK = 0x80000000 # macro +CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT = 0x0 # macro +CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT = 0x8 # macro +CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT = 0xb # macro +CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT = 0xc # macro +CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT = 0xe # macro +CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT = 0x10 # macro +CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT = 0x16 # macro +CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT = 0x1a # macro +CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT = 0x1b # macro +CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT = 0x1c # macro +CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT = 0x1d # macro +CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT = 0x1e # macro +CP_HQD_IQ_TIMER__ACTIVE__SHIFT = 0x1f # macro +CP_HQD_IQ_TIMER__WAIT_TIME_MASK = 0x000000FF # macro +CP_HQD_IQ_TIMER__RETRY_TYPE_MASK = 0x00000700 # macro +CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK = 0x00000800 # macro +CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK = 0x00003000 # macro +CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK = 0x0000C000 # macro +CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK = 0x003F0000 # macro +CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK = 0x00400000 # macro +CP_HQD_IQ_TIMER__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_IQ_TIMER__CACHE_POLICY_MASK = 0x03000000 # macro +CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK = 0x04000000 # macro +CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK = 0x08000000 # macro +CP_HQD_IQ_TIMER__REARM_TIMER_MASK = 0x10000000 # macro +CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK = 0x20000000 # macro +CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK = 0x40000000 # macro +CP_HQD_IQ_TIMER__ACTIVE_MASK = 0x80000000 # macro +CP_HQD_IQ_RPTR__OFFSET__SHIFT = 0x0 # macro +CP_HQD_IQ_RPTR__OFFSET_MASK = 0x0000003F # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT = 0x0 # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT = 0x4 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT = 0x8 # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT = 0x9 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT = 0xa # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK = 0x0000000F # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK = 0x00000010 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK = 0x00000100 # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK = 0x00000200 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK = 0x00000400 # macro +CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT = 0x0 # macro +CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN__SHIFT = 0x1 # macro +CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD__SHIFT = 0x2 # macro +CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN__SHIFT = 0x3 # macro +CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD__SHIFT = 0x4 # macro +CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN__SHIFT = 0x5 # macro +CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK = 0x00000001 # macro +CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN_MASK = 0x00000002 # macro +CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_MASK = 0x00000004 # macro +CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN_MASK = 0x00000008 # macro +CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_MASK = 0x00000010 # macro +CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN_MASK = 0x00000020 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT = 0x0 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT = 0x1 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT = 0x2 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT = 0x3 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT = 0x4 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT = 0x5 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK = 0x00000001 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK = 0x00000002 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK = 0x00000004 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK = 0x00000008 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK = 0x00000010 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK = 0x00000020 # macro +CP_HQD_SEMA_CMD__RETRY__SHIFT = 0x0 # macro +CP_HQD_SEMA_CMD__RESULT__SHIFT = 0x1 # macro +CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT = 0x8 # macro +CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT = 0x9 # macro +CP_HQD_SEMA_CMD__RETRY_MASK = 0x00000001 # macro +CP_HQD_SEMA_CMD__RESULT_MASK = 0x00000006 # macro +CP_HQD_SEMA_CMD__POLLING_DIS_MASK = 0x00000100 # macro +CP_HQD_SEMA_CMD__MESSAGE_EN_MASK = 0x00000200 # macro +CP_HQD_MSG_TYPE__ACTION__SHIFT = 0x0 # macro +CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT = 0x4 # macro +CP_HQD_MSG_TYPE__ACTION_MASK = 0x00000007 # macro +CP_HQD_MSG_TYPE__SAVE_STATE_MASK = 0x00000070 # macro +CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_HQD_HQ_SCHEDULER0__CWSR__SHIFT = 0x0 # macro +CP_HQD_HQ_SCHEDULER0__SAVE_STATUS__SHIFT = 0x1 # macro +CP_HQD_HQ_SCHEDULER0__RSRV__SHIFT = 0x2 # macro +CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE__SHIFT = 0x3 # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT = 0x6 # macro +CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT = 0x7 # macro +CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT = 0x8 # macro +CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID__SHIFT = 0x9 # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE__SHIFT = 0xa # macro +CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS__SHIFT = 0xd # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED__SHIFT = 0xf # macro +CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED__SHIFT = 0x14 # macro +CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE__SHIFT = 0x15 # macro +CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT__SHIFT = 0x18 # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE__SHIFT = 0x1e # macro +CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN__SHIFT = 0x1f # macro +CP_HQD_HQ_SCHEDULER0__CWSR_MASK = 0x00000001 # macro +CP_HQD_HQ_SCHEDULER0__SAVE_STATUS_MASK = 0x00000002 # macro +CP_HQD_HQ_SCHEDULER0__RSRV_MASK = 0x00000004 # macro +CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE_MASK = 0x00000038 # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK = 0x00000040 # macro +CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK = 0x00000080 # macro +CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK = 0x00000100 # macro +CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID_MASK = 0x00000200 # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE_MASK = 0x00001C00 # macro +CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS_MASK = 0x00002000 # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED_MASK = 0x00008000 # macro +CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED_MASK = 0x00100000 # macro +CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE_MASK = 0x00600000 # macro +CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT_MASK = 0x0F000000 # macro +CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE_MASK = 0x40000000 # macro +CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN_MASK = 0x80000000 # macro +CP_HQD_HQ_STATUS0__CWSR__SHIFT = 0x0 # macro +CP_HQD_HQ_STATUS0__SAVE_STATUS__SHIFT = 0x1 # macro +CP_HQD_HQ_STATUS0__RSRV__SHIFT = 0x2 # macro +CP_HQD_HQ_STATUS0__STATIC_QUEUE__SHIFT = 0x3 # macro +CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE__SHIFT = 0x6 # macro +CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT = 0x7 # macro +CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT = 0x8 # macro +CP_HQD_HQ_STATUS0__C_INHERIT_VMID__SHIFT = 0x9 # macro +CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE__SHIFT = 0xa # macro +CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS__SHIFT = 0xd # macro +CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED__SHIFT = 0xf # macro +CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED__SHIFT = 0x14 # macro +CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE__SHIFT = 0x15 # macro +CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT__SHIFT = 0x18 # macro +CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT = 0x1e # macro +CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT = 0x1f # macro +CP_HQD_HQ_STATUS0__CWSR_MASK = 0x00000001 # macro +CP_HQD_HQ_STATUS0__SAVE_STATUS_MASK = 0x00000002 # macro +CP_HQD_HQ_STATUS0__RSRV_MASK = 0x00000004 # macro +CP_HQD_HQ_STATUS0__STATIC_QUEUE_MASK = 0x00000038 # macro +CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE_MASK = 0x00000040 # macro +CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK = 0x00000080 # macro +CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK = 0x00000100 # macro +CP_HQD_HQ_STATUS0__C_INHERIT_VMID_MASK = 0x00000200 # macro +CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE_MASK = 0x00001C00 # macro +CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS_MASK = 0x00002000 # macro +CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED_MASK = 0x00008000 # macro +CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED_MASK = 0x00100000 # macro +CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE_MASK = 0x00600000 # macro +CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT_MASK = 0x0F000000 # macro +CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK = 0x40000000 # macro +CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK = 0x80000000 # macro +CP_HQD_HQ_CONTROL0__CONTROL__SHIFT = 0x0 # macro +CP_HQD_HQ_CONTROL0__CONTROL_MASK = 0xFFFFFFFF # macro +CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT = 0x0 # macro +CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK = 0xFFFFFFFF # macro +CP_MQD_CONTROL__VMID__SHIFT = 0x0 # macro +CP_MQD_CONTROL__PRIV_STATE__SHIFT = 0x8 # macro +CP_MQD_CONTROL__PROCESSING_MQD__SHIFT = 0xc # macro +CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT = 0xd # macro +CP_MQD_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_MQD_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_MQD_CONTROL__MQD_VOLATILE__SHIFT = 0x1a # macro +CP_MQD_CONTROL__VMID_MASK = 0x0000000F # macro +CP_MQD_CONTROL__PRIV_STATE_MASK = 0x00000100 # macro +CP_MQD_CONTROL__PROCESSING_MQD_MASK = 0x00001000 # macro +CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK = 0x00002000 # macro +CP_MQD_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_MQD_CONTROL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_MQD_CONTROL__MQD_VOLATILE_MASK = 0x04000000 # macro +CP_HQD_HQ_STATUS1__STATUS__SHIFT = 0x0 # macro +CP_HQD_HQ_STATUS1__STATUS_MASK = 0xFFFFFFFF # macro +CP_HQD_HQ_CONTROL1__CONTROL__SHIFT = 0x0 # macro +CP_HQD_HQ_CONTROL1__CONTROL_MASK = 0xFFFFFFFF # macro +CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT = 0x0 # macro +CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFFFFF # macro +CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x000000FF # macro +CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT = 0x0 # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT = 0x8 # macro +CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT = 0xc # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT = 0xd # macro +CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT = 0xe # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT = 0x15 # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT = 0x16 # macro +CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT = 0x1a # macro +CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT = 0x1d # macro +CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT = 0x1f # macro +CP_HQD_EOP_CONTROL__EOP_SIZE_MASK = 0x0000003F # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK = 0x00000100 # macro +CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK = 0x00001000 # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK = 0x00002000 # macro +CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK = 0x00004000 # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK = 0x00200000 # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK = 0x00400000 # macro +CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK = 0x04000000 # macro +CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK = 0x60000000 # macro +CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK = 0x80000000 # macro +CP_HQD_EOP_RPTR__RPTR__SHIFT = 0x0 # macro +CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT = 0x1c # macro +CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT = 0x1d # macro +CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT = 0x1e # macro +CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT = 0x1f # macro +CP_HQD_EOP_RPTR__RPTR_MASK = 0x00001FFF # macro +CP_HQD_EOP_RPTR__RESET_FETCHER_MASK = 0x10000000 # macro +CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK = 0x20000000 # macro +CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK = 0x40000000 # macro +CP_HQD_EOP_RPTR__INIT_FETCHER_MASK = 0x80000000 # macro +CP_HQD_EOP_WPTR__WPTR__SHIFT = 0x0 # macro +CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT = 0xf # macro +CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT = 0x10 # macro +CP_HQD_EOP_WPTR__WPTR_MASK = 0x00001FFF # macro +CP_HQD_EOP_WPTR__EOP_EMPTY_MASK = 0x00008000 # macro +CP_HQD_EOP_WPTR__EOP_AVAIL_MASK = 0x1FFF0000 # macro +CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT = 0x0 # macro +CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT = 0x10 # macro +CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK = 0x00000FFF # macro +CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK = 0x00010000 # macro +CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT = 0xc # macro +CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK = 0xFFFFF000 # macro +CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT = 0x3 # macro +CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK = 0x00000018 # macro +CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT = 0x2 # macro +CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK = 0x0000FFFC # macro +CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT = 0xc # macro +CP_HQD_CNTL_STACK_SIZE__SIZE_MASK = 0x0000F000 # macro +CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT = 0x2 # macro +CP_HQD_WG_STATE_OFFSET__OFFSET_MASK = 0x03FFFFFC # macro +CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT = 0xc # macro +CP_HQD_CTX_SAVE_SIZE__SIZE_MASK = 0x03FFF000 # macro +CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT = 0x0 # macro +CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT = 0x1 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT = 0x4 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT = 0xc # macro +CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK = 0x00000001 # macro +CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK = 0x00000002 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK = 0x000003F0 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK = 0x0003F000 # macro +CP_HQD_ERROR__EDC_ERROR_ID__SHIFT = 0x0 # macro +CP_HQD_ERROR__SUA_ERROR__SHIFT = 0x4 # macro +CP_HQD_ERROR__AQL_ERROR__SHIFT = 0x5 # macro +CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT = 0x8 # macro +CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT = 0x9 # macro +CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT = 0xa # macro +CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT = 0xb # macro +CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT = 0xc # macro +CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT = 0xd # macro +CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT = 0xe # macro +CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT = 0xf # macro +CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT = 0x10 # macro +CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT = 0x11 # macro +CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT = 0x12 # macro +CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT = 0x13 # macro +CP_HQD_ERROR__EDC_ERROR_ID_MASK = 0x0000000F # macro +CP_HQD_ERROR__SUA_ERROR_MASK = 0x00000010 # macro +CP_HQD_ERROR__AQL_ERROR_MASK = 0x00000020 # macro +CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK = 0x00000100 # macro +CP_HQD_ERROR__IB_UTCL1_ERROR_MASK = 0x00000200 # macro +CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK = 0x00000400 # macro +CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK = 0x00000800 # macro +CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK = 0x00001000 # macro +CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK = 0x00002000 # macro +CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK = 0x00004000 # macro +CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK = 0x00008000 # macro +CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK = 0x00010000 # macro +CP_HQD_ERROR__SR_UTCL1_ERROR_MASK = 0x00020000 # macro +CP_HQD_ERROR__QU_UTCL1_ERROR_MASK = 0x00040000 # macro +CP_HQD_ERROR__TC_UTCL1_ERROR_MASK = 0x00080000 # macro +CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT = 0x0 # macro +CP_HQD_EOP_WPTR_MEM__WPTR_MASK = 0x00001FFF # macro +CP_HQD_AQL_CONTROL__CONTROL0__SHIFT = 0x0 # macro +CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT = 0xf # macro +CP_HQD_AQL_CONTROL__CONTROL1__SHIFT = 0x10 # macro +CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT = 0x1f # macro +CP_HQD_AQL_CONTROL__CONTROL0_MASK = 0x00007FFF # macro +CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK = 0x00008000 # macro +CP_HQD_AQL_CONTROL__CONTROL1_MASK = 0x7FFF0000 # macro +CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK = 0x80000000 # macro +CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT = 0x0 # macro +CP_HQD_PQ_WPTR_LO__OFFSET_MASK = 0xFFFFFFFF # macro +CP_HQD_PQ_WPTR_HI__DATA__SHIFT = 0x0 # macro +CP_HQD_PQ_WPTR_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT = 0x2 # macro +CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK = 0x0000FFFC # macro +CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT = 0x0 # macro +CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK = 0x00003FFF # macro +CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT = 0x2 # macro +CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK = 0x03FFFFFC # macro +CP_HQD_DDID_RPTR__RPTR__SHIFT = 0x0 # macro +CP_HQD_DDID_RPTR__RPTR_MASK = 0x000007FF # macro +CP_HQD_DDID_WPTR__WPTR__SHIFT = 0x0 # macro +CP_HQD_DDID_WPTR__WPTR_MASK = 0x000007FF # macro +CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT = 0x0 # macro +CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK = 0x0000FFFF # macro +CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT = 0x0 # macro +CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK = 0x000000FF # macro +CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT = 0x0 # macro +CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT = 0x4 # macro +CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT = 0x9 # macro +CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT = 0xa # macro +CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK = 0x0000000F # macro +CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK = 0x00000010 # macro +CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK = 0x00000200 # macro +CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK = 0x00000400 # macro +TCP_WATCH0_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH0_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH0_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH0_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH0_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH0_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH0_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH0_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH0_CNTL__MASK_MASK = 0x007FFFFF # macro +TCP_WATCH0_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH0_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH0_CNTL__VALID_MASK = 0x80000000 # macro +TCP_WATCH1_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH1_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH1_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH1_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH1_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH1_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH1_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH1_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH1_CNTL__MASK_MASK = 0x007FFFFF # macro +TCP_WATCH1_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH1_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH1_CNTL__VALID_MASK = 0x80000000 # macro +TCP_WATCH2_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH2_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH2_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH2_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH2_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH2_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH2_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH2_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH2_CNTL__MASK_MASK = 0x007FFFFF # macro +TCP_WATCH2_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH2_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH2_CNTL__VALID_MASK = 0x80000000 # macro +TCP_WATCH3_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH3_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH3_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH3_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH3_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH3_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH3_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH3_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH3_CNTL__MASK_MASK = 0x007FFFFF # macro +TCP_WATCH3_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH3_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH3_CNTL__VALID_MASK = 0x80000000 # macro +GDS_VMID0_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID0_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID0_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID0_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID0_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID0_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID0_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID0_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID1_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID1_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID1_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID1_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID1_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID1_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID1_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID1_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID2_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID2_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID2_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID2_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID2_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID2_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID2_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID2_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID3_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID3_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID3_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID3_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID3_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID3_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID3_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID3_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID4_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID4_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID4_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID4_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID4_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID4_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID4_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID4_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID5_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID5_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID5_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID5_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID5_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID5_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID5_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID5_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID6_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID6_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID6_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID6_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID6_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID6_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID6_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID6_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID7_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID7_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID7_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID7_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID7_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID7_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID7_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID7_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID8_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID8_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID8_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID8_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID8_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID8_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID8_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID8_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID9_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID9_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID9_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID9_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID9_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID9_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID9_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID9_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID10_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID10_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID10_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID10_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID10_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID10_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID10_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID10_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID11_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID11_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID11_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID11_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID11_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID11_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID11_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID11_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID12_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID12_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID12_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID12_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID12_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID12_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID12_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID12_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID13_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID13_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID13_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID13_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID13_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID13_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID13_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID13_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID14_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID14_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID14_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID14_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID14_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID14_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID14_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID14_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_VMID15_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID15_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_VMID15_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID15_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_VMID15_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID15_SIZE__UNUSED__SHIFT = 0x11 # macro +GDS_VMID15_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID15_SIZE__UNUSED_MASK = 0xFFFE0000 # macro +GDS_GWS_VMID0__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID0__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID0__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID0__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID0__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID0__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID0__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID0__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID1__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID1__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID1__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID1__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID1__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID1__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID1__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID1__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID2__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID2__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID2__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID2__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID2__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID2__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID2__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID2__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID3__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID3__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID3__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID3__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID3__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID3__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID3__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID3__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID4__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID4__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID4__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID4__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID4__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID4__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID4__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID4__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID5__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID5__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID5__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID5__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID5__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID5__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID5__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID5__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID6__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID6__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID6__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID6__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID6__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID6__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID6__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID6__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID7__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID7__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID7__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID7__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID7__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID7__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID7__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID7__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID8__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID8__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID8__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID8__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID8__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID8__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID8__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID8__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID9__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID9__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID9__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID9__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID9__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID9__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID9__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID9__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID10__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID10__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID10__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID10__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID10__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID10__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID10__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID10__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID11__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID11__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID11__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID11__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID11__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID11__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID11__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID11__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID12__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID12__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID12__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID12__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID12__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID12__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID12__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID12__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID13__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID13__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID13__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID13__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID13__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID13__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID13__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID13__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID14__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID14__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID14__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID14__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID14__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID14__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID14__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID14__UNUSED2_MASK = 0xFF800000 # macro +GDS_GWS_VMID15__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID15__UNUSED1__SHIFT = 0x6 # macro +GDS_GWS_VMID15__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID15__UNUSED2__SHIFT = 0x17 # macro +GDS_GWS_VMID15__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID15__UNUSED1_MASK = 0x0000FFC0 # macro +GDS_GWS_VMID15__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID15__UNUSED2_MASK = 0xFF800000 # macro +GDS_OA_VMID0__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID0__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID0__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID0__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID1__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID1__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID1__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID1__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID2__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID2__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID2__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID2__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID3__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID3__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID3__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID3__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID4__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID4__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID4__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID4__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID5__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID5__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID5__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID5__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID6__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID6__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID6__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID6__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID7__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID7__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID7__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID7__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID8__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID8__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID8__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID8__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID9__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID9__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID9__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID9__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID10__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID10__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID10__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID10__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID11__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID11__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID11__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID11__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID12__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID12__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID12__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID12__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID13__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID13__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID13__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID13__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID14__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID14__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID14__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID14__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID15__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID15__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID15__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID15__UNUSED_MASK = 0xFFFF0000 # macro +GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT = 0x0 # macro +GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT = 0x1 # macro +GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT = 0x2 # macro +GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT = 0x3 # macro +GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT = 0x4 # macro +GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT = 0x5 # macro +GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT = 0x6 # macro +GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT = 0x7 # macro +GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT = 0x8 # macro +GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT = 0x9 # macro +GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT = 0xa # macro +GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT = 0xb # macro +GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT = 0xc # macro +GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT = 0xd # macro +GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT = 0xe # macro +GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT = 0xf # macro +GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT = 0x10 # macro +GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT = 0x11 # macro +GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT = 0x12 # macro +GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT = 0x13 # macro +GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT = 0x14 # macro +GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT = 0x15 # macro +GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT = 0x16 # macro +GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT = 0x17 # macro +GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT = 0x18 # macro +GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT = 0x19 # macro +GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT = 0x1a # macro +GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT = 0x1b # macro +GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT = 0x1c # macro +GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT = 0x1d # macro +GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT = 0x1e # macro +GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT = 0x1f # macro +GDS_GWS_RESET0__RESOURCE0_RESET_MASK = 0x00000001 # macro +GDS_GWS_RESET0__RESOURCE1_RESET_MASK = 0x00000002 # macro +GDS_GWS_RESET0__RESOURCE2_RESET_MASK = 0x00000004 # macro +GDS_GWS_RESET0__RESOURCE3_RESET_MASK = 0x00000008 # macro +GDS_GWS_RESET0__RESOURCE4_RESET_MASK = 0x00000010 # macro +GDS_GWS_RESET0__RESOURCE5_RESET_MASK = 0x00000020 # macro +GDS_GWS_RESET0__RESOURCE6_RESET_MASK = 0x00000040 # macro +GDS_GWS_RESET0__RESOURCE7_RESET_MASK = 0x00000080 # macro +GDS_GWS_RESET0__RESOURCE8_RESET_MASK = 0x00000100 # macro +GDS_GWS_RESET0__RESOURCE9_RESET_MASK = 0x00000200 # macro +GDS_GWS_RESET0__RESOURCE10_RESET_MASK = 0x00000400 # macro +GDS_GWS_RESET0__RESOURCE11_RESET_MASK = 0x00000800 # macro +GDS_GWS_RESET0__RESOURCE12_RESET_MASK = 0x00001000 # macro +GDS_GWS_RESET0__RESOURCE13_RESET_MASK = 0x00002000 # macro +GDS_GWS_RESET0__RESOURCE14_RESET_MASK = 0x00004000 # macro +GDS_GWS_RESET0__RESOURCE15_RESET_MASK = 0x00008000 # macro +GDS_GWS_RESET0__RESOURCE16_RESET_MASK = 0x00010000 # macro +GDS_GWS_RESET0__RESOURCE17_RESET_MASK = 0x00020000 # macro +GDS_GWS_RESET0__RESOURCE18_RESET_MASK = 0x00040000 # macro +GDS_GWS_RESET0__RESOURCE19_RESET_MASK = 0x00080000 # macro +GDS_GWS_RESET0__RESOURCE20_RESET_MASK = 0x00100000 # macro +GDS_GWS_RESET0__RESOURCE21_RESET_MASK = 0x00200000 # macro +GDS_GWS_RESET0__RESOURCE22_RESET_MASK = 0x00400000 # macro +GDS_GWS_RESET0__RESOURCE23_RESET_MASK = 0x00800000 # macro +GDS_GWS_RESET0__RESOURCE24_RESET_MASK = 0x01000000 # macro +GDS_GWS_RESET0__RESOURCE25_RESET_MASK = 0x02000000 # macro +GDS_GWS_RESET0__RESOURCE26_RESET_MASK = 0x04000000 # macro +GDS_GWS_RESET0__RESOURCE27_RESET_MASK = 0x08000000 # macro +GDS_GWS_RESET0__RESOURCE28_RESET_MASK = 0x10000000 # macro +GDS_GWS_RESET0__RESOURCE29_RESET_MASK = 0x20000000 # macro +GDS_GWS_RESET0__RESOURCE30_RESET_MASK = 0x40000000 # macro +GDS_GWS_RESET0__RESOURCE31_RESET_MASK = 0x80000000 # macro +GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT = 0x0 # macro +GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT = 0x1 # macro +GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT = 0x2 # macro +GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT = 0x3 # macro +GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT = 0x4 # macro +GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT = 0x5 # macro +GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT = 0x6 # macro +GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT = 0x7 # macro +GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT = 0x8 # macro +GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT = 0x9 # macro +GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT = 0xa # macro +GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT = 0xb # macro +GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT = 0xc # macro +GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT = 0xd # macro +GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT = 0xe # macro +GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT = 0xf # macro +GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT = 0x10 # macro +GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT = 0x11 # macro +GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT = 0x12 # macro +GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT = 0x13 # macro +GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT = 0x14 # macro +GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT = 0x15 # macro +GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT = 0x16 # macro +GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT = 0x17 # macro +GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT = 0x18 # macro +GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT = 0x19 # macro +GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT = 0x1a # macro +GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT = 0x1b # macro +GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT = 0x1c # macro +GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT = 0x1d # macro +GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT = 0x1e # macro +GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT = 0x1f # macro +GDS_GWS_RESET1__RESOURCE32_RESET_MASK = 0x00000001 # macro +GDS_GWS_RESET1__RESOURCE33_RESET_MASK = 0x00000002 # macro +GDS_GWS_RESET1__RESOURCE34_RESET_MASK = 0x00000004 # macro +GDS_GWS_RESET1__RESOURCE35_RESET_MASK = 0x00000008 # macro +GDS_GWS_RESET1__RESOURCE36_RESET_MASK = 0x00000010 # macro +GDS_GWS_RESET1__RESOURCE37_RESET_MASK = 0x00000020 # macro +GDS_GWS_RESET1__RESOURCE38_RESET_MASK = 0x00000040 # macro +GDS_GWS_RESET1__RESOURCE39_RESET_MASK = 0x00000080 # macro +GDS_GWS_RESET1__RESOURCE40_RESET_MASK = 0x00000100 # macro +GDS_GWS_RESET1__RESOURCE41_RESET_MASK = 0x00000200 # macro +GDS_GWS_RESET1__RESOURCE42_RESET_MASK = 0x00000400 # macro +GDS_GWS_RESET1__RESOURCE43_RESET_MASK = 0x00000800 # macro +GDS_GWS_RESET1__RESOURCE44_RESET_MASK = 0x00001000 # macro +GDS_GWS_RESET1__RESOURCE45_RESET_MASK = 0x00002000 # macro +GDS_GWS_RESET1__RESOURCE46_RESET_MASK = 0x00004000 # macro +GDS_GWS_RESET1__RESOURCE47_RESET_MASK = 0x00008000 # macro +GDS_GWS_RESET1__RESOURCE48_RESET_MASK = 0x00010000 # macro +GDS_GWS_RESET1__RESOURCE49_RESET_MASK = 0x00020000 # macro +GDS_GWS_RESET1__RESOURCE50_RESET_MASK = 0x00040000 # macro +GDS_GWS_RESET1__RESOURCE51_RESET_MASK = 0x00080000 # macro +GDS_GWS_RESET1__RESOURCE52_RESET_MASK = 0x00100000 # macro +GDS_GWS_RESET1__RESOURCE53_RESET_MASK = 0x00200000 # macro +GDS_GWS_RESET1__RESOURCE54_RESET_MASK = 0x00400000 # macro +GDS_GWS_RESET1__RESOURCE55_RESET_MASK = 0x00800000 # macro +GDS_GWS_RESET1__RESOURCE56_RESET_MASK = 0x01000000 # macro +GDS_GWS_RESET1__RESOURCE57_RESET_MASK = 0x02000000 # macro +GDS_GWS_RESET1__RESOURCE58_RESET_MASK = 0x04000000 # macro +GDS_GWS_RESET1__RESOURCE59_RESET_MASK = 0x08000000 # macro +GDS_GWS_RESET1__RESOURCE60_RESET_MASK = 0x10000000 # macro +GDS_GWS_RESET1__RESOURCE61_RESET_MASK = 0x20000000 # macro +GDS_GWS_RESET1__RESOURCE62_RESET_MASK = 0x40000000 # macro +GDS_GWS_RESET1__RESOURCE63_RESET_MASK = 0x80000000 # macro +GDS_GWS_RESOURCE_RESET__RESET__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT = 0x8 # macro +GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT = 0x10 # macro +GDS_GWS_RESOURCE_RESET__RESET_MASK = 0x00000001 # macro +GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK = 0x0000FF00 # macro +GDS_GWS_RESOURCE_RESET__UNUSED_MASK = 0xFFFF0000 # macro +GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT = 0x0 # macro +GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT = 0xc # macro +GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK = 0x00000FFF # macro +GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK = 0xFFFFF000 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT = 0x0 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT = 0x1 # macro +GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT = 0x2 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT = 0x3 # macro +GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT = 0x4 # macro +GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT = 0x5 # macro +GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT = 0x6 # macro +GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT = 0x7 # macro +GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT = 0x8 # macro +GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT = 0x9 # macro +GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT = 0xa # macro +GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT = 0xb # macro +GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET__SHIFT = 0xc # macro +GDS_OA_RESET_MASK__UNUSED1__SHIFT = 0xd # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK = 0x00000001 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK = 0x00000002 # macro +GDS_OA_RESET_MASK__ME0_CS_RESET_MASK = 0x00000004 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK = 0x00000008 # macro +GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK = 0x00000010 # macro +GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK = 0x00000020 # macro +GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK = 0x00000040 # macro +GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK = 0x00000080 # macro +GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK = 0x00000100 # macro +GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK = 0x00000200 # macro +GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK = 0x00000400 # macro +GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK = 0x00000800 # macro +GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET_MASK = 0x00001000 # macro +GDS_OA_RESET_MASK__UNUSED1_MASK = 0xFFFFE000 # macro +GDS_OA_RESET__RESET__SHIFT = 0x0 # macro +GDS_OA_RESET__PIPE_ID__SHIFT = 0x8 # macro +GDS_OA_RESET__UNUSED__SHIFT = 0x10 # macro +GDS_OA_RESET__RESET_MASK = 0x00000001 # macro +GDS_OA_RESET__PIPE_ID_MASK = 0x0000FF00 # macro +GDS_OA_RESET__UNUSED_MASK = 0xFFFF0000 # macro +GDS_CS_CTXSW_STATUS__R__SHIFT = 0x0 # macro +GDS_CS_CTXSW_STATUS__W__SHIFT = 0x1 # macro +GDS_CS_CTXSW_STATUS__UNUSED__SHIFT = 0x2 # macro +GDS_CS_CTXSW_STATUS__R_MASK = 0x00000001 # macro +GDS_CS_CTXSW_STATUS__W_MASK = 0x00000002 # macro +GDS_CS_CTXSW_STATUS__UNUSED_MASK = 0xFFFFFFFC # macro +GDS_CS_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_CS_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_CS_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_CS_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_GFX_CTXSW_STATUS__R__SHIFT = 0x0 # macro +GDS_GFX_CTXSW_STATUS__W__SHIFT = 0x1 # macro +GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT = 0x2 # macro +GDS_GFX_CTXSW_STATUS__R_MASK = 0x00000001 # macro +GDS_GFX_CTXSW_STATUS__W_MASK = 0x00000002 # macro +GDS_GFX_CTXSW_STATUS__UNUSED_MASK = 0xFFFFFFFC # macro +GDS_PS_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT = 0x0 # macro +GDS_PS_CTXSW_IDX__UNUSED__SHIFT = 0x6 # macro +GDS_PS_CTXSW_IDX__PACKER_ID_MASK = 0x0000003F # macro +GDS_PS_CTXSW_IDX__UNUSED_MASK = 0xFFFFFFC0 # macro +GDS_GS_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_GS_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_GS_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_GS_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_MEMORY_CLEAN__START__SHIFT = 0x0 # macro +GDS_MEMORY_CLEAN__FINISH__SHIFT = 0x1 # macro +GDS_MEMORY_CLEAN__UNUSED__SHIFT = 0x2 # macro +GDS_MEMORY_CLEAN__START_MASK = 0x00000001 # macro +GDS_MEMORY_CLEAN__FINISH_MASK = 0x00000002 # macro +GDS_MEMORY_CLEAN__UNUSED_MASK = 0xFFFFFFFC # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT = 0x0 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT = 0x4 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT = 0x8 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT = 0xc # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT = 0x10 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT = 0x14 # macro +GUS_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT = 0x18 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK = 0x0000000F # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK = 0x000000F0 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK = 0x00000F00 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK = 0x0000F000 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK = 0x000F0000 # macro +GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK = 0x00F00000 # macro +GUS_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK = 0x03000000 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT = 0x0 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT = 0x4 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT = 0x8 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT = 0xc # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT = 0x10 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT = 0x14 # macro +GUS_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT = 0x18 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK = 0x0000000F # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK = 0x000000F0 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK = 0x00000F00 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK = 0x0000F000 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK = 0x000F0000 # macro +GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK = 0x00F00000 # macro +GUS_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK = 0x03000000 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT = 0xc # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT = 0xf # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK = 0x00007000 # macro +GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK = 0x00038000 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT = 0xc # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT = 0xf # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK = 0x00007000 # macro +GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK = 0x00038000 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT = 0xc # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT = 0xf # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK = 0x00007000 # macro +GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK = 0x00038000 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT = 0x1 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT = 0x2 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT = 0x3 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT = 0x4 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT = 0x5 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK = 0x00000001 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK = 0x00000002 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK = 0x00000004 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK = 0x00000008 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK = 0x00000010 # macro +GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK = 0x00000020 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT = 0x1 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT = 0x2 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT = 0x3 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT = 0x4 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT = 0x5 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK = 0x00000001 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK = 0x00000002 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK = 0x00000004 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK = 0x00000008 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK = 0x00000010 # macro +GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK = 0x00000020 # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT = 0x0 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT = 0x4 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT = 0x8 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT = 0xc # macro +GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT = 0x10 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT = 0x14 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK = 0x0000000F # macro +GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK = 0x000000F0 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK = 0x00000F00 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK = 0x0000F000 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK = 0x000F0000 # macro +GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK = 0x00F00000 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT = 0x0 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT = 0x2 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT = 0x4 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT = 0x6 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT = 0x8 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT = 0xa # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK = 0x00000003 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK = 0x0000000C # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK = 0x00000030 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK = 0x000000C0 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK = 0x00000300 # macro +GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK = 0x00000C00 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT = 0xc # macro +GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT = 0xf # macro +GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK = 0x00007000 # macro +GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK = 0x00038000 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT = 0x0 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT = 0x3 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT = 0x6 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT = 0x9 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT = 0xc # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT = 0xf # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK = 0x00000007 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK = 0x00000038 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT = 0xc # macro +GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT = 0xf # macro +GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK = 0x00007000 # macro +GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK = 0x00038000 # macro +GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT = 0xc # macro +GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT = 0xf # macro +GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK = 0x00007000 # macro +GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK = 0x00038000 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT = 0xc # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT = 0xf # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK = 0x00007000 # macro +GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK = 0x00038000 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT = 0x0 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT = 0x1 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT = 0x2 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT = 0x3 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT = 0x4 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT = 0x5 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK = 0x00000001 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK = 0x00000002 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK = 0x00000004 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK = 0x00000008 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK = 0x00000010 # macro +GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK = 0x00000020 # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT = 0x0 # macro +GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT = 0x8 # macro +GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK = 0x000000FF # macro +GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK = 0x0000FF00 # macro +GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT = 0x0 # macro +GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT = 0x8 # macro +GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT = 0x10 # macro +GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT = 0x18 # macro +GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK = 0x000000FF # macro +GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK = 0x0000FF00 # macro +GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK = 0x00FF0000 # macro +GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK = 0xFF000000 # macro +GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT = 0x0 # macro +GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT = 0x8 # macro +GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK = 0x000000FF # macro +GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK = 0x0000FF00 # macro +GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT = 0x0 # macro +GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT = 0x5 # macro +GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT = 0xa # macro +GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT = 0xf # macro +GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT = 0x11 # macro +GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT = 0x12 # macro +GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK = 0x0000001F # macro +GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK = 0x000003E0 # macro +GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK = 0x00007C00 # macro +GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK = 0x00018000 # macro +GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK = 0x00020000 # macro +GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK = 0x00040000 # macro +GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT = 0x0 # macro +GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT = 0x4 # macro +GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT = 0x8 # macro +GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT = 0xc # macro +GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK = 0x0000000F # macro +GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK = 0x000000F0 # macro +GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK = 0x00000F00 # macro +GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK = 0x0000F000 # macro +GUS_SDP_CREDITS__TAG_LIMIT__SHIFT = 0x0 # macro +GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT = 0x8 # macro +GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT = 0x10 # macro +GUS_SDP_CREDITS__TAG_LIMIT_MASK = 0x000000FF # macro +GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK = 0x00007F00 # macro +GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK = 0x007F0000 # macro +GUS_SDP_TAG_RESERVE0__VC0__SHIFT = 0x0 # macro +GUS_SDP_TAG_RESERVE0__VC1__SHIFT = 0x8 # macro +GUS_SDP_TAG_RESERVE0__VC2__SHIFT = 0x10 # macro +GUS_SDP_TAG_RESERVE0__VC3__SHIFT = 0x18 # macro +GUS_SDP_TAG_RESERVE0__VC0_MASK = 0x000000FF # macro +GUS_SDP_TAG_RESERVE0__VC1_MASK = 0x0000FF00 # macro +GUS_SDP_TAG_RESERVE0__VC2_MASK = 0x00FF0000 # macro +GUS_SDP_TAG_RESERVE0__VC3_MASK = 0xFF000000 # macro +GUS_SDP_TAG_RESERVE1__VC4__SHIFT = 0x0 # macro +GUS_SDP_TAG_RESERVE1__VC5__SHIFT = 0x8 # macro +GUS_SDP_TAG_RESERVE1__VC6__SHIFT = 0x10 # macro +GUS_SDP_TAG_RESERVE1__VC7__SHIFT = 0x18 # macro +GUS_SDP_TAG_RESERVE1__VC4_MASK = 0x000000FF # macro +GUS_SDP_TAG_RESERVE1__VC5_MASK = 0x0000FF00 # macro +GUS_SDP_TAG_RESERVE1__VC6_MASK = 0x00FF0000 # macro +GUS_SDP_TAG_RESERVE1__VC7_MASK = 0xFF000000 # macro +GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT = 0x0 # macro +GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT = 0x1 # macro +GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT = 0x2 # macro +GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT = 0x3 # macro +GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT = 0x4 # macro +GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK = 0x00000001 # macro +GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK = 0x00000002 # macro +GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK = 0x00000004 # macro +GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK = 0x00000008 # macro +GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK = 0x00000010 # macro +GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT = 0x0 # macro +GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT = 0x1 # macro +GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT = 0x2 # macro +GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT = 0x3 # macro +GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT = 0x4 # macro +GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT = 0x6 # macro +GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT = 0x8 # macro +GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT = 0xa # macro +GUS_MISC__SEND0_IOWR_ONLY__SHIFT = 0xf # macro +GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK = 0x00000001 # macro +GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK = 0x00000002 # macro +GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK = 0x00000004 # macro +GUS_MISC__EARLY_SDP_ORIGDATA_MASK = 0x00000008 # macro +GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK = 0x00000030 # macro +GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK = 0x000000C0 # macro +GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK = 0x00000300 # macro +GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK = 0x00007C00 # macro +GUS_MISC__SEND0_IOWR_ONLY_MASK = 0x00008000 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT = 0x0 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT = 0x1 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT = 0x2 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT = 0x3 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT = 0x4 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT = 0x5 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT = 0x6 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT = 0x7 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT = 0x8 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT = 0x9 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT = 0xa # macro +GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT = 0xb # macro +GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT = 0xc # macro +GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT = 0x14 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK = 0x00000001 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK = 0x00000002 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK = 0x00000004 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK = 0x00000008 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK = 0x00000010 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK = 0x00000020 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK = 0x00000040 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK = 0x00000080 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK = 0x00000100 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK = 0x00000200 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK = 0x00000400 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK = 0x00000800 # macro +GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK = 0x000FF000 # macro +GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK = 0x0FF00000 # macro +GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT = 0x0 # macro +GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT = 0x4 # macro +GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xb # macro +GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xc # macro +GUS_ERR_STATUS__FUE_FLAG__SHIFT = 0xd # macro +GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK = 0x0000000F # macro +GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK = 0x000000F0 # macro +GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00000800 # macro +GUS_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00001000 # macro +GUS_ERR_STATUS__FUE_FLAG_MASK = 0x00002000 # macro +GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT = 0x0 # macro +GUS_MISC2__CH_L1_RO_MASK__SHIFT = 0x1 # macro +GUS_MISC2__SA0_L1_RO_MASK__SHIFT = 0x2 # macro +GUS_MISC2__SA1_L1_RO_MASK__SHIFT = 0x3 # macro +GUS_MISC2__SA2_L1_RO_MASK__SHIFT = 0x4 # macro +GUS_MISC2__SA3_L1_RO_MASK__SHIFT = 0x5 # macro +GUS_MISC2__CH_L1_PERF_MASK__SHIFT = 0x6 # macro +GUS_MISC2__SA0_L1_PERF_MASK__SHIFT = 0x7 # macro +GUS_MISC2__SA1_L1_PERF_MASK__SHIFT = 0x8 # macro +GUS_MISC2__SA2_L1_PERF_MASK__SHIFT = 0x9 # macro +GUS_MISC2__SA3_L1_PERF_MASK__SHIFT = 0xa # macro +GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT = 0xb # macro +GUS_MISC2__L1_RET_CLKEN__SHIFT = 0xc # macro +GUS_MISC2__FGCLKEN_HIGH__SHIFT = 0xd # macro +GUS_MISC2__BLOCK_REQUESTS__SHIFT = 0xe # macro +GUS_MISC2__REQUESTS_BLOCKED__SHIFT = 0xf # macro +GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT = 0x10 # macro +GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT = 0x11 # macro +GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK__SHIFT = 0x12 # macro +GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK = 0x00000001 # macro +GUS_MISC2__CH_L1_RO_MASK_MASK = 0x00000002 # macro +GUS_MISC2__SA0_L1_RO_MASK_MASK = 0x00000004 # macro +GUS_MISC2__SA1_L1_RO_MASK_MASK = 0x00000008 # macro +GUS_MISC2__SA2_L1_RO_MASK_MASK = 0x00000010 # macro +GUS_MISC2__SA3_L1_RO_MASK_MASK = 0x00000020 # macro +GUS_MISC2__CH_L1_PERF_MASK_MASK = 0x00000040 # macro +GUS_MISC2__SA0_L1_PERF_MASK_MASK = 0x00000080 # macro +GUS_MISC2__SA1_L1_PERF_MASK_MASK = 0x00000100 # macro +GUS_MISC2__SA2_L1_PERF_MASK_MASK = 0x00000200 # macro +GUS_MISC2__SA3_L1_PERF_MASK_MASK = 0x00000400 # macro +GUS_MISC2__FP_ATOMICS_ENABLE_MASK = 0x00000800 # macro +GUS_MISC2__L1_RET_CLKEN_MASK = 0x00001000 # macro +GUS_MISC2__FGCLKEN_HIGH_MASK = 0x00002000 # macro +GUS_MISC2__BLOCK_REQUESTS_MASK = 0x00004000 # macro +GUS_MISC2__REQUESTS_BLOCKED_MASK = 0x00008000 # macro +GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK_MASK = 0x00010000 # macro +GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK_MASK = 0x00020000 # macro +GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK_MASK = 0x00040000 # macro +GUS_SDP_ENABLE__ENABLE__SHIFT = 0x0 # macro +GUS_SDP_ENABLE__ENABLE_MASK = 0x00000001 # macro +GUS_L1_CH0_CMD_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH0_CMD_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH0_CMD_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH0_CMD_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH0_DATA_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH0_DATA_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH0_DATA_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH0_DATA_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH0_DATA_U_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH0_DATA_U_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH0_DATA_U_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH0_DATA_U_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH1_CMD_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH1_CMD_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH1_CMD_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH1_CMD_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH1_DATA_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH1_DATA_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH1_DATA_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH1_DATA_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH1_DATA_U_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH1_DATA_U_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_CH1_DATA_U_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_CH1_DATA_U_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA0_CMD_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA0_CMD_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA0_CMD_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA0_CMD_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA0_DATA_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA0_DATA_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA0_DATA_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA0_DATA_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA0_DATA_U_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA0_DATA_U_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA1_CMD_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA1_CMD_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA1_CMD_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA1_CMD_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA1_DATA_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA1_DATA_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA1_DATA_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA1_DATA_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA1_DATA_U_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA1_DATA_U_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA2_CMD_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA2_CMD_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA2_CMD_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA2_CMD_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA2_DATA_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA2_DATA_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA2_DATA_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA2_DATA_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA2_DATA_U_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA2_DATA_U_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA3_CMD_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA3_CMD_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA3_CMD_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA3_CMD_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA3_DATA_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA3_DATA_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA3_DATA_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA3_DATA_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA3_DATA_U_IN__COUNT_MASK = 0xFFFFFFFF # macro +GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT = 0x0 # macro +GUS_L1_SA3_DATA_U_OUT__COUNT_MASK = 0xFFFFFFFF # macro +GUS_MISC3__FP_ATOMICS_LOG__SHIFT = 0x0 # macro +GUS_MISC3__CLEAR_LOG__SHIFT = 0x1 # macro +GUS_MISC3__FP_ATOMICS_LOG_MASK = 0x00000001 # macro +GUS_MISC3__CLEAR_LOG_MASK = 0x00000002 # macro +GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT = 0x0 # macro +GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK = 0x0000003F # macro +DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT = 0x0 # macro +DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT = 0x1 # macro +DB_RENDER_CONTROL__DEPTH_COPY__SHIFT = 0x2 # macro +DB_RENDER_CONTROL__STENCIL_COPY__SHIFT = 0x3 # macro +DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT = 0x4 # macro +DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT = 0x5 # macro +DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT = 0x6 # macro +DB_RENDER_CONTROL__COPY_CENTROID__SHIFT = 0x7 # macro +DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT = 0x8 # macro +DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT = 0xc # macro +DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT = 0xe # macro +DB_RENDER_CONTROL__OREO_MODE__SHIFT = 0x10 # macro +DB_RENDER_CONTROL__FORCE_OREO_MODE__SHIFT = 0x12 # macro +DB_RENDER_CONTROL__FORCE_EXPORT_ORDER__SHIFT = 0x13 # macro +DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE__SHIFT = 0x14 # macro +DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK = 0x00000001 # macro +DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK = 0x00000002 # macro +DB_RENDER_CONTROL__DEPTH_COPY_MASK = 0x00000004 # macro +DB_RENDER_CONTROL__STENCIL_COPY_MASK = 0x00000008 # macro +DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK = 0x00000010 # macro +DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK = 0x00000020 # macro +DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK = 0x00000040 # macro +DB_RENDER_CONTROL__COPY_CENTROID_MASK = 0x00000080 # macro +DB_RENDER_CONTROL__COPY_SAMPLE_MASK = 0x00000F00 # macro +DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK = 0x00001000 # macro +DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK = 0x00004000 # macro +DB_RENDER_CONTROL__OREO_MODE_MASK = 0x00030000 # macro +DB_RENDER_CONTROL__FORCE_OREO_MODE_MASK = 0x00040000 # macro +DB_RENDER_CONTROL__FORCE_EXPORT_ORDER_MASK = 0x00080000 # macro +DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE_MASK = 0x00F00000 # macro +DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT = 0x1 # macro +DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT = 0x2 # macro +DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT = 0x3 # macro +DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT = 0x4 # macro +DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT = 0x8 # macro +DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT = 0xc # macro +DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT = 0x10 # macro +DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT = 0x14 # macro +DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT = 0x18 # macro +DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT = 0x1c # macro +DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK = 0x00000002 # macro +DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK = 0x00000004 # macro +DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK = 0x00000008 # macro +DB_COUNT_CONTROL__SAMPLE_RATE_MASK = 0x00000070 # macro +DB_COUNT_CONTROL__ZPASS_ENABLE_MASK = 0x00000F00 # macro +DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK = 0x0000F000 # macro +DB_COUNT_CONTROL__SFAIL_ENABLE_MASK = 0x000F0000 # macro +DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK = 0x00F00000 # macro +DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK = 0x0F000000 # macro +DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK = 0xF0000000 # macro +DB_DEPTH_VIEW__SLICE_START__SHIFT = 0x0 # macro +DB_DEPTH_VIEW__SLICE_START_HI__SHIFT = 0xb # macro +DB_DEPTH_VIEW__SLICE_MAX__SHIFT = 0xd # macro +DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT = 0x18 # macro +DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT = 0x19 # macro +DB_DEPTH_VIEW__MIPID__SHIFT = 0x1a # macro +DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT = 0x1e # macro +DB_DEPTH_VIEW__SLICE_START_MASK = 0x000007FF # macro +DB_DEPTH_VIEW__SLICE_START_HI_MASK = 0x00001800 # macro +DB_DEPTH_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +DB_DEPTH_VIEW__Z_READ_ONLY_MASK = 0x01000000 # macro +DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK = 0x02000000 # macro +DB_DEPTH_VIEW__MIPID_MASK = 0x3C000000 # macro +DB_DEPTH_VIEW__SLICE_MAX_HI_MASK = 0xC0000000 # macro +DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT = 0x0 # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT = 0x2 # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT = 0x4 # macro +DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT = 0x6 # macro +DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT = 0x7 # macro +DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT = 0x8 # macro +DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT = 0x9 # macro +DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT = 0xa # macro +DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT = 0xb # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT = 0xc # macro +DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT = 0xd # macro +DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT = 0x10 # macro +DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT = 0x11 # macro +DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT = 0x12 # macro +DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT = 0x13 # macro +DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT = 0x15 # macro +DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT = 0x1a # macro +DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT = 0x1b # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT = 0x1c # macro +DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT = 0x1d # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT = 0x1e # macro +DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT = 0x1f # macro +DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK = 0x00000003 # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK = 0x0000000C # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK = 0x00000030 # macro +DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK = 0x00000040 # macro +DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK = 0x00000080 # macro +DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK = 0x00000100 # macro +DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK = 0x00000200 # macro +DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK = 0x00000400 # macro +DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK = 0x00000800 # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK = 0x00001000 # macro +DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK = 0x00006000 # macro +DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK = 0x00010000 # macro +DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK = 0x00020000 # macro +DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK = 0x00040000 # macro +DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK = 0x00180000 # macro +DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK = 0x03E00000 # macro +DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK = 0x04000000 # macro +DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK = 0x08000000 # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK = 0x10000000 # macro +DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK = 0x20000000 # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK = 0x40000000 # macro +DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK = 0x80000000 # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT = 0x0 # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT = 0x2 # macro +DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT = 0x5 # macro +DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT = 0x6 # macro +DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT = 0x7 # macro +DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT = 0x8 # macro +DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT = 0x9 # macro +DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT = 0xa # macro +DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT = 0xb # macro +DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT = 0xc # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT = 0xf # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT = 0x12 # macro +DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT = 0x15 # macro +DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT = 0x16 # macro +DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT = 0x17 # macro +DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT = 0x19 # macro +DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT = 0x1b # macro +DB_RENDER_OVERRIDE2__DISABLE_NOZ__SHIFT = 0x1d # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK = 0x00000003 # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK = 0x0000001C # macro +DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK = 0x00000020 # macro +DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK = 0x00000040 # macro +DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK = 0x00000080 # macro +DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK = 0x00000100 # macro +DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK = 0x00000200 # macro +DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK = 0x00000400 # macro +DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK = 0x00000800 # macro +DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK = 0x00007000 # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK = 0x00038000 # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK = 0x001C0000 # macro +DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK = 0x00200000 # macro +DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK = 0x00400000 # macro +DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK = 0x00800000 # macro +DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK = 0x02000000 # macro +DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK = 0x18000000 # macro +DB_RENDER_OVERRIDE2__DISABLE_NOZ_MASK = 0x20000000 # macro +DB_HTILE_DATA_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_HTILE_DATA_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_DEPTH_SIZE_XY__X_MAX__SHIFT = 0x0 # macro +DB_DEPTH_SIZE_XY__Y_MAX__SHIFT = 0x10 # macro +DB_DEPTH_SIZE_XY__X_MAX_MASK = 0x00003FFF # macro +DB_DEPTH_SIZE_XY__Y_MAX_MASK = 0x3FFF0000 # macro +DB_DEPTH_BOUNDS_MIN__MIN__SHIFT = 0x0 # macro +DB_DEPTH_BOUNDS_MIN__MIN_MASK = 0xFFFFFFFF # macro +DB_DEPTH_BOUNDS_MAX__MAX__SHIFT = 0x0 # macro +DB_DEPTH_BOUNDS_MAX__MAX_MASK = 0xFFFFFFFF # macro +DB_STENCIL_CLEAR__CLEAR__SHIFT = 0x0 # macro +DB_STENCIL_CLEAR__CLEAR_MASK = 0x000000FF # macro +DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT = 0x0 # macro +DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK = 0xFFFFFFFF # macro +PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK = 0xFFFF0000 # macro +DB_RESERVED_REG_2__FIELD_1__SHIFT = 0x0 # macro +DB_RESERVED_REG_2__FIELD_2__SHIFT = 0x4 # macro +DB_RESERVED_REG_2__FIELD_3__SHIFT = 0x8 # macro +DB_RESERVED_REG_2__FIELD_4__SHIFT = 0xd # macro +DB_RESERVED_REG_2__FIELD_5__SHIFT = 0xf # macro +DB_RESERVED_REG_2__FIELD_6__SHIFT = 0x11 # macro +DB_RESERVED_REG_2__FIELD_7__SHIFT = 0x13 # macro +DB_RESERVED_REG_2__FIELD_8__SHIFT = 0x1c # macro +DB_RESERVED_REG_2__FIELD_1_MASK = 0x0000000F # macro +DB_RESERVED_REG_2__FIELD_2_MASK = 0x000000F0 # macro +DB_RESERVED_REG_2__FIELD_3_MASK = 0x00001F00 # macro +DB_RESERVED_REG_2__FIELD_4_MASK = 0x00006000 # macro +DB_RESERVED_REG_2__FIELD_5_MASK = 0x00018000 # macro +DB_RESERVED_REG_2__FIELD_6_MASK = 0x00060000 # macro +DB_RESERVED_REG_2__FIELD_7_MASK = 0x00180000 # macro +DB_RESERVED_REG_2__FIELD_8_MASK = 0xF0000000 # macro +DB_Z_INFO__FORMAT__SHIFT = 0x0 # macro +DB_Z_INFO__NUM_SAMPLES__SHIFT = 0x2 # macro +DB_Z_INFO__SW_MODE__SHIFT = 0x4 # macro +DB_Z_INFO__FAULT_BEHAVIOR__SHIFT = 0x9 # macro +DB_Z_INFO__ITERATE_FLUSH__SHIFT = 0xb # macro +DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT = 0xc # macro +DB_Z_INFO__RESERVED_FIELD_1__SHIFT = 0xd # macro +DB_Z_INFO__MAXMIP__SHIFT = 0x10 # macro +DB_Z_INFO__ITERATE_256__SHIFT = 0x14 # macro +DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT = 0x17 # macro +DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT = 0x1b # macro +DB_Z_INFO__READ_SIZE__SHIFT = 0x1c # macro +DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT = 0x1d # macro +DB_Z_INFO__ZRANGE_PRECISION__SHIFT = 0x1f # macro +DB_Z_INFO__FORMAT_MASK = 0x00000003 # macro +DB_Z_INFO__NUM_SAMPLES_MASK = 0x0000000C # macro +DB_Z_INFO__SW_MODE_MASK = 0x000001F0 # macro +DB_Z_INFO__FAULT_BEHAVIOR_MASK = 0x00000600 # macro +DB_Z_INFO__ITERATE_FLUSH_MASK = 0x00000800 # macro +DB_Z_INFO__PARTIALLY_RESIDENT_MASK = 0x00001000 # macro +DB_Z_INFO__RESERVED_FIELD_1_MASK = 0x0000E000 # macro +DB_Z_INFO__MAXMIP_MASK = 0x000F0000 # macro +DB_Z_INFO__ITERATE_256_MASK = 0x00100000 # macro +DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK = 0x07800000 # macro +DB_Z_INFO__ALLOW_EXPCLEAR_MASK = 0x08000000 # macro +DB_Z_INFO__READ_SIZE_MASK = 0x10000000 # macro +DB_Z_INFO__TILE_SURFACE_ENABLE_MASK = 0x20000000 # macro +DB_Z_INFO__ZRANGE_PRECISION_MASK = 0x80000000 # macro +DB_STENCIL_INFO__FORMAT__SHIFT = 0x0 # macro +DB_STENCIL_INFO__SW_MODE__SHIFT = 0x4 # macro +DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT = 0x9 # macro +DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT = 0xb # macro +DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT = 0xc # macro +DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT = 0xd # macro +DB_STENCIL_INFO__ITERATE_256__SHIFT = 0x14 # macro +DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT = 0x1b # macro +DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT = 0x1d # macro +DB_STENCIL_INFO__FORMAT_MASK = 0x00000001 # macro +DB_STENCIL_INFO__SW_MODE_MASK = 0x000001F0 # macro +DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK = 0x00000600 # macro +DB_STENCIL_INFO__ITERATE_FLUSH_MASK = 0x00000800 # macro +DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK = 0x00001000 # macro +DB_STENCIL_INFO__RESERVED_FIELD_1_MASK = 0x0000E000 # macro +DB_STENCIL_INFO__ITERATE_256_MASK = 0x00100000 # macro +DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK = 0x08000000 # macro +DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK = 0x20000000 # macro +DB_Z_READ_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_Z_READ_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_STENCIL_READ_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_STENCIL_READ_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_Z_WRITE_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_Z_WRITE_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_STENCIL_WRITE_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_RESERVED_REG_1__FIELD_1__SHIFT = 0x0 # macro +DB_RESERVED_REG_1__FIELD_2__SHIFT = 0xb # macro +DB_RESERVED_REG_1__FIELD_1_MASK = 0x000007FF # macro +DB_RESERVED_REG_1__FIELD_2_MASK = 0x003FF800 # macro +DB_RESERVED_REG_3__FIELD_1__SHIFT = 0x0 # macro +DB_RESERVED_REG_3__FIELD_1_MASK = 0x003FFFFF # macro +DB_Z_READ_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_Z_READ_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_STENCIL_READ_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_Z_WRITE_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_HTILE_DATA_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT = 0x0 # macro +DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT = 0x2 # macro +DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT = 0x4 # macro +DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT = 0x6 # macro +DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT = 0x10 # macro +DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT = 0x12 # macro +DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT = 0x14 # macro +DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT = 0x18 # macro +DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT = 0x19 # macro +DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC__SHIFT = 0x1a # macro +DB_RMI_L2_CACHE_CONTROL__S_NOALLOC__SHIFT = 0x1b # macro +DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC__SHIFT = 0x1c # macro +DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC__SHIFT = 0x1d # macro +DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK = 0x00000003 # macro +DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK = 0x0000000C # macro +DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK = 0x00000030 # macro +DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK = 0x000000C0 # macro +DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK = 0x00030000 # macro +DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK = 0x000C0000 # macro +DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK = 0x00300000 # macro +DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK = 0x01000000 # macro +DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK = 0x02000000 # macro +DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC_MASK = 0x04000000 # macro +DB_RMI_L2_CACHE_CONTROL__S_NOALLOC_MASK = 0x08000000 # macro +DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC_MASK = 0x10000000 # macro +DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC_MASK = 0x20000000 # macro +TA_BC_BASE_ADDR__ADDRESS__SHIFT = 0x0 # macro +TA_BC_BASE_ADDR__ADDRESS_MASK = 0xFFFFFFFF # macro +TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT = 0x0 # macro +TA_BC_BASE_ADDR_HI__ADDRESS_MASK = 0x000000FF # macro +COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_2__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_3__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT = 0x0 # macro +PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT = 0x10 # macro +PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK = 0x0000FFFF # macro +PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK = 0xFFFF0000 # macro +PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK = 0x0000FFFF # macro +PA_SC_CLIPRECT_0_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_0_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_0_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_0_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_0_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_0_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_1_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_1_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_1_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_1_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_1_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_1_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_2_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_2_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_2_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_2_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_2_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_2_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_3_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_3_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_3_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_3_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_3_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_3_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_EDGERULE__ER_TRI__SHIFT = 0x0 # macro +PA_SC_EDGERULE__ER_POINT__SHIFT = 0x4 # macro +PA_SC_EDGERULE__ER_RECT__SHIFT = 0x8 # macro +PA_SC_EDGERULE__ER_LINE_LR__SHIFT = 0xc # macro +PA_SC_EDGERULE__ER_LINE_RL__SHIFT = 0x12 # macro +PA_SC_EDGERULE__ER_LINE_TB__SHIFT = 0x18 # macro +PA_SC_EDGERULE__ER_LINE_BT__SHIFT = 0x1c # macro +PA_SC_EDGERULE__ER_TRI_MASK = 0x0000000F # macro +PA_SC_EDGERULE__ER_POINT_MASK = 0x000000F0 # macro +PA_SC_EDGERULE__ER_RECT_MASK = 0x00000F00 # macro +PA_SC_EDGERULE__ER_LINE_LR_MASK = 0x0003F000 # macro +PA_SC_EDGERULE__ER_LINE_RL_MASK = 0x00FC0000 # macro +PA_SC_EDGERULE__ER_LINE_TB_MASK = 0x0F000000 # macro +PA_SC_EDGERULE__ER_LINE_BT_MASK = 0xF0000000 # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT = 0x0 # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT = 0x10 # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK = 0x000001FF # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK = 0x01FF0000 # macro +CB_TARGET_MASK__TARGET0_ENABLE__SHIFT = 0x0 # macro +CB_TARGET_MASK__TARGET1_ENABLE__SHIFT = 0x4 # macro +CB_TARGET_MASK__TARGET2_ENABLE__SHIFT = 0x8 # macro +CB_TARGET_MASK__TARGET3_ENABLE__SHIFT = 0xc # macro +CB_TARGET_MASK__TARGET4_ENABLE__SHIFT = 0x10 # macro +CB_TARGET_MASK__TARGET5_ENABLE__SHIFT = 0x14 # macro +CB_TARGET_MASK__TARGET6_ENABLE__SHIFT = 0x18 # macro +CB_TARGET_MASK__TARGET7_ENABLE__SHIFT = 0x1c # macro +CB_TARGET_MASK__TARGET0_ENABLE_MASK = 0x0000000F # macro +CB_TARGET_MASK__TARGET1_ENABLE_MASK = 0x000000F0 # macro +CB_TARGET_MASK__TARGET2_ENABLE_MASK = 0x00000F00 # macro +CB_TARGET_MASK__TARGET3_ENABLE_MASK = 0x0000F000 # macro +CB_TARGET_MASK__TARGET4_ENABLE_MASK = 0x000F0000 # macro +CB_TARGET_MASK__TARGET5_ENABLE_MASK = 0x00F00000 # macro +CB_TARGET_MASK__TARGET6_ENABLE_MASK = 0x0F000000 # macro +CB_TARGET_MASK__TARGET7_ENABLE_MASK = 0xF0000000 # macro +CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT = 0x0 # macro +CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT = 0x4 # macro +CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT = 0x8 # macro +CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT = 0xc # macro +CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT = 0x10 # macro +CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT = 0x14 # macro +CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT = 0x18 # macro +CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT = 0x1c # macro +CB_SHADER_MASK__OUTPUT0_ENABLE_MASK = 0x0000000F # macro +CB_SHADER_MASK__OUTPUT1_ENABLE_MASK = 0x000000F0 # macro +CB_SHADER_MASK__OUTPUT2_ENABLE_MASK = 0x00000F00 # macro +CB_SHADER_MASK__OUTPUT3_ENABLE_MASK = 0x0000F000 # macro +CB_SHADER_MASK__OUTPUT4_ENABLE_MASK = 0x000F0000 # macro +CB_SHADER_MASK__OUTPUT5_ENABLE_MASK = 0x00F00000 # macro +CB_SHADER_MASK__OUTPUT6_ENABLE_MASK = 0x0F000000 # macro +CB_SHADER_MASK__OUTPUT7_ENABLE_MASK = 0xF0000000 # macro +PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK = 0x7FFF0000 # macro +COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_0__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_1__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT = 0x0 # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT = 0x2 # macro +PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT = 0x4 # macro +PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT = 0x6 # macro +PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT = 0x7 # macro +PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT = 0x8 # macro +PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT = 0xa # macro +PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT = 0xc # macro +PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT = 0xe # macro +PA_SC_RASTER_CONFIG__SC_MAP__SHIFT = 0x10 # macro +PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT = 0x12 # macro +PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT = 0x14 # macro +PA_SC_RASTER_CONFIG__SE_MAP__SHIFT = 0x18 # macro +PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT = 0x1a # macro +PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT = 0x1c # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK = 0x00000003 # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK = 0x0000000C # macro +PA_SC_RASTER_CONFIG__RB_XSEL2_MASK = 0x00000030 # macro +PA_SC_RASTER_CONFIG__RB_XSEL_MASK = 0x00000040 # macro +PA_SC_RASTER_CONFIG__RB_YSEL_MASK = 0x00000080 # macro +PA_SC_RASTER_CONFIG__PKR_MAP_MASK = 0x00000300 # macro +PA_SC_RASTER_CONFIG__PKR_XSEL_MASK = 0x00000C00 # macro +PA_SC_RASTER_CONFIG__PKR_YSEL_MASK = 0x00003000 # macro +PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK = 0x0000C000 # macro +PA_SC_RASTER_CONFIG__SC_MAP_MASK = 0x00030000 # macro +PA_SC_RASTER_CONFIG__SC_XSEL_MASK = 0x000C0000 # macro +PA_SC_RASTER_CONFIG__SC_YSEL_MASK = 0x00300000 # macro +PA_SC_RASTER_CONFIG__SE_MAP_MASK = 0x03000000 # macro +PA_SC_RASTER_CONFIG__SE_XSEL_MASK = 0x0C000000 # macro +PA_SC_RASTER_CONFIG__SE_YSEL_MASK = 0x30000000 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT = 0x0 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT = 0x2 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT = 0x4 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK = 0x00000003 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK = 0x0000000C # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK = 0x00000030 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT = 0x2 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK = 0x00000003 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK = 0x0000000C # macro +PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT = 0xc # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT = 0x10 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT = 0x14 # macro +PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK = 0x00000001 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK = 0x00003000 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK = 0x00030000 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK = 0x00300000 # macro +CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT = 0x1f # macro +CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK = 0x80000000 # macro +CP_PIPEID__PIPE_ID__SHIFT = 0x0 # macro +CP_PIPEID__PIPE_ID_MASK = 0x00000003 # macro +CP_RINGID__RINGID__SHIFT = 0x0 # macro +CP_RINGID__RINGID_MASK = 0x00000003 # macro +CP_VMID__VMID__SHIFT = 0x0 # macro +CP_VMID__VMID_MASK = 0x0000000F # macro +CONTEXT_RESERVED_REG0__DATA__SHIFT = 0x0 # macro +CONTEXT_RESERVED_REG0__DATA_MASK = 0xFFFFFFFF # macro +CONTEXT_RESERVED_REG1__DATA__SHIFT = 0x0 # macro +CONTEXT_RESERVED_REG1__DATA_MASK = 0xFFFFFFFF # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT = 0x0 # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE__SHIFT = 0x4 # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE__SHIFT = 0xc # macro +PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE__SHIFT = 0xd # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT = 0xe # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK = 0x00000007 # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE_MASK = 0x000000F0 # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE_MASK = 0x00001000 # macro +PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE_MASK = 0x00002000 # macro +PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK = 0x00004000 # macro +PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B__SHIFT = 0x0 # macro +PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX__SHIFT = 0x0 # macro +PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX__SHIFT = 0x10 # macro +PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX_MASK = 0x000007FF # macro +PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX_MASK = 0x07FF0000 # macro +PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD__SHIFT = 0x0 # macro +PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR__SHIFT = 0x1 # macro +PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY__SHIFT = 0x2 # macro +PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY__SHIFT = 0x4 # macro +PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY__SHIFT = 0x6 # macro +PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC__SHIFT = 0x8 # macro +PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC__SHIFT = 0x9 # macro +PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD__SHIFT = 0xa # macro +PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR__SHIFT = 0xb # macro +PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD__SHIFT = 0xc # macro +PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR__SHIFT = 0xd # macro +PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD_MASK = 0x00000001 # macro +PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR_MASK = 0x00000002 # macro +PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY_MASK = 0x0000000C # macro +PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY_MASK = 0x00000030 # macro +PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY_MASK = 0x000000C0 # macro +PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC_MASK = 0x00000100 # macro +PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC_MASK = 0x00000200 # macro +PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD_MASK = 0x00000400 # macro +PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR_MASK = 0x00000800 # macro +PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD_MASK = 0x00001000 # macro +PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR_MASK = 0x00002000 # macro +PA_SC_VRS_RATE_BASE__BASE_256B__SHIFT = 0x0 # macro +PA_SC_VRS_RATE_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +PA_SC_VRS_RATE_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID__SHIFT = 0x1c # macro +PA_SC_VRS_RATE_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID_MASK = 0xF0000000 # macro +PA_SC_VRS_RATE_SIZE_XY__X_MAX__SHIFT = 0x0 # macro +PA_SC_VRS_RATE_SIZE_XY__Y_MAX__SHIFT = 0x10 # macro +PA_SC_VRS_RATE_SIZE_XY__X_MAX_MASK = 0x000007FF # macro +PA_SC_VRS_RATE_SIZE_XY__Y_MAX_MASK = 0x07FF0000 # macro +VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT = 0x0 # macro +VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK = 0xFFFFFFFF # macro +CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT = 0x0 # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT = 0x2 # macro +CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT = 0x14 # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT = 0x16 # macro +CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS__SHIFT = 0x1a # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS__SHIFT = 0x1b # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT = 0x1f # macro +CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK = 0x00000003 # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK = 0x0000000C # macro +CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK = 0x00300000 # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK = 0x00C00000 # macro +CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS_MASK = 0x04000000 # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS_MASK = 0x08000000 # macro +CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK = 0x80000000 # macro +CB_BLEND_RED__BLEND_RED__SHIFT = 0x0 # macro +CB_BLEND_RED__BLEND_RED_MASK = 0xFFFFFFFF # macro +CB_BLEND_GREEN__BLEND_GREEN__SHIFT = 0x0 # macro +CB_BLEND_GREEN__BLEND_GREEN_MASK = 0xFFFFFFFF # macro +CB_BLEND_BLUE__BLEND_BLUE__SHIFT = 0x0 # macro +CB_BLEND_BLUE__BLEND_BLUE_MASK = 0xFFFFFFFF # macro +CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT = 0x0 # macro +CB_BLEND_ALPHA__BLEND_ALPHA_MASK = 0xFFFFFFFF # macro +CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK__SHIFT = 0x2 # macro +CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT = 0x8 # macro +CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT = 0x9 # macro +CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0xa # macro +CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT = 0xc # macro +CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT = 0xd # macro +CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT = 0xe # macro +CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK_MASK = 0x0000007C # macro +CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK = 0x00000100 # macro +CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK = 0x00000200 # macro +CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00000400 # macro +CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK = 0x00001000 # macro +CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK = 0x00002000 # macro +CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK = 0x00004000 # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT = 0x0 # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT = 0x1 # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT = 0x4 # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT = 0x8 # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK = 0x00000001 # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK = 0x0000000E # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK = 0x00000030 # macro +CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK = 0x00000F00 # macro +DB_STENCIL_CONTROL__STENCILFAIL__SHIFT = 0x0 # macro +DB_STENCIL_CONTROL__STENCILZPASS__SHIFT = 0x4 # macro +DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT = 0x8 # macro +DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT = 0xc # macro +DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT = 0x10 # macro +DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT = 0x14 # macro +DB_STENCIL_CONTROL__STENCILFAIL_MASK = 0x0000000F # macro +DB_STENCIL_CONTROL__STENCILZPASS_MASK = 0x000000F0 # macro +DB_STENCIL_CONTROL__STENCILZFAIL_MASK = 0x00000F00 # macro +DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK = 0x0000F000 # macro +DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK = 0x000F0000 # macro +DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK = 0x00F00000 # macro +DB_STENCILREFMASK__STENCILTESTVAL__SHIFT = 0x0 # macro +DB_STENCILREFMASK__STENCILMASK__SHIFT = 0x8 # macro +DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT = 0x10 # macro +DB_STENCILREFMASK__STENCILOPVAL__SHIFT = 0x18 # macro +DB_STENCILREFMASK__STENCILTESTVAL_MASK = 0x000000FF # macro +DB_STENCILREFMASK__STENCILMASK_MASK = 0x0000FF00 # macro +DB_STENCILREFMASK__STENCILWRITEMASK_MASK = 0x00FF0000 # macro +DB_STENCILREFMASK__STENCILOPVAL_MASK = 0xFF000000 # macro +DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT = 0x0 # macro +DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT = 0x8 # macro +DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT = 0x10 # macro +DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT = 0x18 # macro +DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK = 0x000000FF # macro +DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK = 0x0000FF00 # macro +DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK = 0x00FF0000 # macro +DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK = 0xFF000000 # macro +PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_RATE_CNTL__VERTEX_RATE__SHIFT = 0x0 # macro +PA_RATE_CNTL__PRIM_RATE__SHIFT = 0x4 # macro +PA_RATE_CNTL__VERTEX_RATE_MASK = 0x0000000F # macro +PA_RATE_CNTL__PRIM_RATE_MASK = 0x000000F0 # macro +SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_0__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_0__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_0__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_0__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_0__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_1__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_1__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_1__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_1__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_1__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_2__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_2__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_2__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_2__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_2__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_3__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_3__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_3__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_3__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_3__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_4__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_4__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_4__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_4__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_4__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_5__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_5__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_5__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_5__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_5__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_6__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_6__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_6__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_6__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_6__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_7__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_7__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_7__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_7__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_7__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_8__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_8__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_8__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_8__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_8__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_9__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_9__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_9__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_9__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_9__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_10__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_10__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_10__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_10__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_10__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_11__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_11__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_11__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_11__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_11__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_12__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_12__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_12__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_12__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_12__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_13__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_13__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_13__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_13__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_13__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_14__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_14__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_14__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_14__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_14__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_15__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_15__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_15__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_15__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_15__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_16__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_16__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_16__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_16__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_16__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_17__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_17__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_17__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_17__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_17__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_18__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_18__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_18__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_18__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_18__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_19__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_19__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_19__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_19__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_19__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_20__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_20__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_20__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_20__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_20__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_21__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_21__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_21__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_21__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_21__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_22__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_22__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_22__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_22__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_22__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_23__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_23__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_23__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_23__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_23__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_24__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_24__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_24__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_24__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_24__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_25__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_25__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_25__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_25__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_25__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_26__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_26__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_26__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_26__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_26__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_27__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_27__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_27__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_27__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_27__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_28__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_28__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_28__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_28__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_28__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_29__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_29__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_29__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_29__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_29__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_30__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_30__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_30__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_30__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_30__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT = 0xb # macro +SPI_PS_INPUT_CNTL_31__PRIM_ATTR__SHIFT = 0xc # macro +SPI_PS_INPUT_CNTL_31__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_31__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK = 0x00000800 # macro +SPI_PS_INPUT_CNTL_31__PRIM_ATTR_MASK = 0x00001000 # macro +SPI_PS_INPUT_CNTL_31__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT = 0x1 # macro +SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT = 0x7 # macro +SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT__SHIFT = 0x8 # macro +SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK = 0x0000003E # macro +SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK = 0x00000080 # macro +SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT_MASK = 0x00001F00 # macro +SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT = 0x0 # macro +SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT = 0x1 # macro +SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT = 0x2 # macro +SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT = 0x3 # macro +SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT = 0x4 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT = 0x5 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT = 0x6 # macro +SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT = 0x7 # macro +SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT = 0x8 # macro +SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT = 0x9 # macro +SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT = 0xa # macro +SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT = 0xb # macro +SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT = 0xc # macro +SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT = 0xd # macro +SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT = 0xe # macro +SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT = 0xf # macro +SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK = 0x00000001 # macro +SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK = 0x00000002 # macro +SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK = 0x00000004 # macro +SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK = 0x00000008 # macro +SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK = 0x00000010 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK = 0x00000020 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK = 0x00000040 # macro +SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK = 0x00000080 # macro +SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK = 0x00000100 # macro +SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK = 0x00000200 # macro +SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK = 0x00000400 # macro +SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK = 0x00000800 # macro +SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK = 0x00001000 # macro +SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK = 0x00002000 # macro +SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK = 0x00004000 # macro +SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK = 0x00008000 # macro +SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT = 0x0 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT = 0x1 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT = 0x2 # macro +SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT = 0x3 # macro +SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT = 0x4 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT = 0x5 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT = 0x6 # macro +SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT = 0x7 # macro +SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT = 0x8 # macro +SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT = 0x9 # macro +SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT = 0xa # macro +SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT = 0xb # macro +SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT = 0xc # macro +SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT = 0xd # macro +SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT = 0xe # macro +SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT = 0xf # macro +SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK = 0x00000001 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK = 0x00000002 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK = 0x00000004 # macro +SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK = 0x00000008 # macro +SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK = 0x00000010 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK = 0x00000020 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK = 0x00000040 # macro +SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK = 0x00000080 # macro +SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK = 0x00000100 # macro +SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK = 0x00000200 # macro +SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK = 0x00000400 # macro +SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK = 0x00000800 # macro +SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK = 0x00001000 # macro +SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK = 0x00002000 # macro +SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK = 0x00004000 # macro +SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK = 0x00008000 # macro +SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT = 0x0 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT = 0x1 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT = 0x2 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT = 0x5 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT = 0x8 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT = 0xb # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT = 0xe # macro +SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK = 0x00000001 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK = 0x00000002 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK = 0x0000001C # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK = 0x000000E0 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK = 0x00000700 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK = 0x00003800 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK = 0x00004000 # macro +SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT = 0x0 # macro +SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT = 0x6 # macro +SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT = 0x7 # macro +SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT = 0x8 # macro +SPI_PS_IN_CONTROL__NUM_PRIM_INTERP__SHIFT = 0x9 # macro +SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT = 0xe # macro +SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT = 0xf # macro +SPI_PS_IN_CONTROL__NUM_INTERP_MASK = 0x0000003F # macro +SPI_PS_IN_CONTROL__PARAM_GEN_MASK = 0x00000040 # macro +SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK = 0x00000080 # macro +SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK = 0x00000100 # macro +SPI_PS_IN_CONTROL__NUM_PRIM_INTERP_MASK = 0x00003E00 # macro +SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK = 0x00004000 # macro +SPI_PS_IN_CONTROL__PS_W32_EN_MASK = 0x00008000 # macro +SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT = 0x0 # macro +SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT = 0x4 # macro +SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT = 0x8 # macro +SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT = 0xc # macro +SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT = 0x10 # macro +SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT = 0x14 # macro +SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT = 0x18 # macro +SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK = 0x00000001 # macro +SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK = 0x00000010 # macro +SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK = 0x00000100 # macro +SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK = 0x00001000 # macro +SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK = 0x00030000 # macro +SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK = 0x00100000 # macro +SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK = 0x01000000 # macro +SPI_TMPRING_SIZE__WAVES__SHIFT = 0x0 # macro +SPI_TMPRING_SIZE__WAVESIZE__SHIFT = 0xc # macro +SPI_TMPRING_SIZE__WAVES_MASK = 0x00000FFF # macro +SPI_TMPRING_SIZE__WAVESIZE_MASK = 0x07FFF000 # macro +SPI_GFX_SCRATCH_BASE_LO__DATA__SHIFT = 0x0 # macro +SPI_GFX_SCRATCH_BASE_LO__DATA_MASK = 0xFFFFFFFF # macro +SPI_GFX_SCRATCH_BASE_HI__DATA__SHIFT = 0x0 # macro +SPI_GFX_SCRATCH_BASE_HI__DATA_MASK = 0x000000FF # macro +SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT = 0x0 # macro +SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK = 0x0000000F # macro +SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT = 0x0 # macro +SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT = 0x4 # macro +SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT = 0x8 # macro +SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT = 0xc # macro +SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT = 0x10 # macro +SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK = 0x0000000F # macro +SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK = 0x000000F0 # macro +SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK = 0x00000F00 # macro +SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK = 0x0000F000 # macro +SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK = 0x000F0000 # macro +SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT = 0x0 # macro +SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK = 0x0000000F # macro +SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT = 0x0 # macro +SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT = 0x4 # macro +SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT = 0x8 # macro +SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT = 0xc # macro +SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT = 0x10 # macro +SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT = 0x14 # macro +SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT = 0x18 # macro +SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT = 0x1c # macro +SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK = 0x0000000F # macro +SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK = 0x000000F0 # macro +SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK = 0x00000F00 # macro +SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK = 0x0000F000 # macro +SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK = 0x000F0000 # macro +SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK = 0x00F00000 # macro +SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK = 0x0F000000 # macro +SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK = 0xF0000000 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT = 0x0 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT = 0x1 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT = 0x2 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT = 0x3 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT = 0x4 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT = 0x5 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT = 0x6 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT = 0x7 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK = 0x00000001 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK = 0x00000002 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK = 0x00000004 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK = 0x00000008 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK = 0x00000010 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK = 0x00000020 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK = 0x00000040 # macro +SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK = 0x00000080 # macro +SX_PS_DOWNCONVERT__MRT0__SHIFT = 0x0 # macro +SX_PS_DOWNCONVERT__MRT1__SHIFT = 0x4 # macro +SX_PS_DOWNCONVERT__MRT2__SHIFT = 0x8 # macro +SX_PS_DOWNCONVERT__MRT3__SHIFT = 0xc # macro +SX_PS_DOWNCONVERT__MRT4__SHIFT = 0x10 # macro +SX_PS_DOWNCONVERT__MRT5__SHIFT = 0x14 # macro +SX_PS_DOWNCONVERT__MRT6__SHIFT = 0x18 # macro +SX_PS_DOWNCONVERT__MRT7__SHIFT = 0x1c # macro +SX_PS_DOWNCONVERT__MRT0_MASK = 0x0000000F # macro +SX_PS_DOWNCONVERT__MRT1_MASK = 0x000000F0 # macro +SX_PS_DOWNCONVERT__MRT2_MASK = 0x00000F00 # macro +SX_PS_DOWNCONVERT__MRT3_MASK = 0x0000F000 # macro +SX_PS_DOWNCONVERT__MRT4_MASK = 0x000F0000 # macro +SX_PS_DOWNCONVERT__MRT5_MASK = 0x00F00000 # macro +SX_PS_DOWNCONVERT__MRT6_MASK = 0x0F000000 # macro +SX_PS_DOWNCONVERT__MRT7_MASK = 0xF0000000 # macro +SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT = 0x0 # macro +SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT = 0x4 # macro +SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT = 0x8 # macro +SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT = 0xc # macro +SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT = 0x10 # macro +SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT = 0x14 # macro +SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT = 0x18 # macro +SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT = 0x1c # macro +SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK = 0x0000000F # macro +SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK = 0x000000F0 # macro +SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK = 0x00000F00 # macro +SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK = 0x0000F000 # macro +SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK = 0x000F0000 # macro +SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK = 0x00F00000 # macro +SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK = 0x0F000000 # macro +SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK = 0xF0000000 # macro +SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT = 0x0 # macro +SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT = 0x1 # macro +SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT = 0x4 # macro +SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT = 0x5 # macro +SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT = 0x8 # macro +SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT = 0x9 # macro +SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT = 0xc # macro +SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT = 0xd # macro +SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT = 0x10 # macro +SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT = 0x11 # macro +SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT = 0x14 # macro +SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT = 0x15 # macro +SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT = 0x18 # macro +SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT = 0x19 # macro +SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT = 0x1c # macro +SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT = 0x1d # macro +SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT = 0x1f # macro +SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK = 0x00000001 # macro +SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK = 0x00000002 # macro +SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK = 0x00000010 # macro +SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK = 0x00000020 # macro +SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK = 0x00000100 # macro +SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK = 0x00000200 # macro +SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK = 0x00001000 # macro +SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK = 0x00002000 # macro +SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK = 0x00010000 # macro +SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK = 0x00020000 # macro +SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK = 0x00100000 # macro +SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK = 0x00200000 # macro +SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK = 0x01000000 # macro +SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK = 0x02000000 # macro +SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK = 0x10000000 # macro +SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK = 0x20000000 # macro +SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK = 0x80000000 # macro +SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT = 0x0 # macro +SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT = 0x4 # macro +SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT = 0x8 # macro +SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT = 0x10 # macro +SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT = 0x14 # macro +SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT = 0x18 # macro +SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK = 0x00000007 # macro +SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK = 0x00000070 # macro +SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK = 0x00000700 # macro +SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK = 0x00070000 # macro +SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK = 0x00700000 # macro +SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK = 0x07000000 # macro +CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND0_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND0_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND0_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND1_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND1_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND1_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND2_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND2_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND2_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND3_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND3_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND3_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND4_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND4_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND4_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND5_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND5_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND5_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND6_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND6_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND6_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND7_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND7_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND7_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +GFX_COPY_STATE__SRC_STATE_ID__SHIFT = 0x0 # macro +GFX_COPY_STATE__SRC_STATE_ID_MASK = 0x00000007 # macro +PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_X_RAD__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_SIZE__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +VGT_DMA_BASE_HI__BASE_ADDR__SHIFT = 0x0 # macro +VGT_DMA_BASE_HI__BASE_ADDR_MASK = 0x0000FFFF # macro +VGT_DMA_BASE__BASE_ADDR__SHIFT = 0x0 # macro +VGT_DMA_BASE__BASE_ADDR_MASK = 0xFFFFFFFF # macro +VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT = 0x0 # macro +VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT = 0x2 # macro +VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT = 0x4 # macro +VGT_DRAW_INITIATOR__NOT_EOP__SHIFT = 0x5 # macro +VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT = 0x6 # macro +VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT = 0x1d # macro +VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK = 0x00000003 # macro +VGT_DRAW_INITIATOR__MAJOR_MODE_MASK = 0x0000000C # macro +VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK = 0x00000010 # macro +VGT_DRAW_INITIATOR__NOT_EOP_MASK = 0x00000020 # macro +VGT_DRAW_INITIATOR__USE_OPAQUE_MASK = 0x00000040 # macro +VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK = 0xE0000000 # macro +VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT = 0x0 # macro +VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK = 0x0FFFFFFF # macro +GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT = 0x0 # macro +GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK = 0x000003FF # macro +DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT = 0x0 # macro +DB_DEPTH_CONTROL__Z_ENABLE__SHIFT = 0x1 # macro +DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT = 0x2 # macro +DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT = 0x3 # macro +DB_DEPTH_CONTROL__ZFUNC__SHIFT = 0x4 # macro +DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT = 0x7 # macro +DB_DEPTH_CONTROL__STENCILFUNC__SHIFT = 0x8 # macro +DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT = 0x14 # macro +DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT = 0x1e # macro +DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT = 0x1f # macro +DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK = 0x00000001 # macro +DB_DEPTH_CONTROL__Z_ENABLE_MASK = 0x00000002 # macro +DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK = 0x00000004 # macro +DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK = 0x00000008 # macro +DB_DEPTH_CONTROL__ZFUNC_MASK = 0x00000070 # macro +DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK = 0x00000080 # macro +DB_DEPTH_CONTROL__STENCILFUNC_MASK = 0x00000700 # macro +DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK = 0x00700000 # macro +DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK = 0x40000000 # macro +DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK = 0x80000000 # macro +DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT = 0x0 # macro +DB_EQAA__PS_ITER_SAMPLES__SHIFT = 0x4 # macro +DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT = 0x8 # macro +DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT = 0xc # macro +DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT = 0x10 # macro +DB_EQAA__INCOHERENT_EQAA_READS__SHIFT = 0x11 # macro +DB_EQAA__INTERPOLATE_COMP_Z__SHIFT = 0x12 # macro +DB_EQAA__INTERPOLATE_SRC_Z__SHIFT = 0x13 # macro +DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT = 0x14 # macro +DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT = 0x15 # macro +DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT = 0x18 # macro +DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT = 0x1b # macro +DB_EQAA__MAX_ANCHOR_SAMPLES_MASK = 0x00000007 # macro +DB_EQAA__PS_ITER_SAMPLES_MASK = 0x00000070 # macro +DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK = 0x00000700 # macro +DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK = 0x00007000 # macro +DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK = 0x00010000 # macro +DB_EQAA__INCOHERENT_EQAA_READS_MASK = 0x00020000 # macro +DB_EQAA__INTERPOLATE_COMP_Z_MASK = 0x00040000 # macro +DB_EQAA__INTERPOLATE_SRC_Z_MASK = 0x00080000 # macro +DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK = 0x00100000 # macro +DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK = 0x00200000 # macro +DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK = 0x07000000 # macro +DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK = 0x08000000 # macro +CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT = 0x0 # macro +CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT = 0x1 # macro +CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT = 0x3 # macro +CB_COLOR_CONTROL__MODE__SHIFT = 0x4 # macro +CB_COLOR_CONTROL__ROP3__SHIFT = 0x10 # macro +CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK = 0x00000001 # macro +CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK = 0x00000002 # macro +CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK = 0x00000008 # macro +CB_COLOR_CONTROL__MODE_MASK = 0x00000070 # macro +CB_COLOR_CONTROL__ROP3_MASK = 0x00FF0000 # macro +DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT = 0x0 # macro +DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT = 0x1 # macro +DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT = 0x2 # macro +DB_SHADER_CONTROL__Z_ORDER__SHIFT = 0x4 # macro +DB_SHADER_CONTROL__KILL_ENABLE__SHIFT = 0x6 # macro +DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT = 0x7 # macro +DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT = 0x8 # macro +DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT = 0x9 # macro +DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT = 0xa # macro +DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT = 0xb # macro +DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT = 0xc # macro +DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT = 0xd # macro +DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT = 0xf # macro +DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT = 0x10 # macro +DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT = 0x17 # macro +DB_SHADER_CONTROL__OREO_BLEND_ENABLE__SHIFT = 0x18 # macro +DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE__SHIFT = 0x19 # macro +DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE__SHIFT = 0x1a # macro +DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK = 0x00000001 # macro +DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK = 0x00000002 # macro +DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK = 0x00000004 # macro +DB_SHADER_CONTROL__Z_ORDER_MASK = 0x00000030 # macro +DB_SHADER_CONTROL__KILL_ENABLE_MASK = 0x00000040 # macro +DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK = 0x00000080 # macro +DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK = 0x00000100 # macro +DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK = 0x00000200 # macro +DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK = 0x00000400 # macro +DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK = 0x00000800 # macro +DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK = 0x00001000 # macro +DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK = 0x00006000 # macro +DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK = 0x00008000 # macro +DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK = 0x00010000 # macro +DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK = 0x00800000 # macro +DB_SHADER_CONTROL__OREO_BLEND_ENABLE_MASK = 0x01000000 # macro +DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE_MASK = 0x02000000 # macro +DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_MASK = 0x1C000000 # macro +PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT = 0x0 # macro +PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT = 0x1 # macro +PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT = 0x2 # macro +PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT = 0x3 # macro +PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT = 0x4 # macro +PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT = 0x5 # macro +PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT = 0xd # macro +PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT = 0xe # macro +PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT = 0x10 # macro +PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT = 0x11 # macro +PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT = 0x12 # macro +PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT = 0x13 # macro +PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT = 0x14 # macro +PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT = 0x15 # macro +PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT = 0x16 # macro +PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT = 0x18 # macro +PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT = 0x19 # macro +PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT = 0x1a # macro +PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT = 0x1b # macro +PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT = 0x1c # macro +PA_CL_CLIP_CNTL__UCP_ENA_0_MASK = 0x00000001 # macro +PA_CL_CLIP_CNTL__UCP_ENA_1_MASK = 0x00000002 # macro +PA_CL_CLIP_CNTL__UCP_ENA_2_MASK = 0x00000004 # macro +PA_CL_CLIP_CNTL__UCP_ENA_3_MASK = 0x00000008 # macro +PA_CL_CLIP_CNTL__UCP_ENA_4_MASK = 0x00000010 # macro +PA_CL_CLIP_CNTL__UCP_ENA_5_MASK = 0x00000020 # macro +PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK = 0x00002000 # macro +PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK = 0x0000C000 # macro +PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK = 0x00010000 # macro +PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK = 0x00020000 # macro +PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK = 0x00040000 # macro +PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK = 0x00080000 # macro +PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK = 0x00100000 # macro +PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK = 0x00200000 # macro +PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK = 0x00400000 # macro +PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK = 0x01000000 # macro +PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK = 0x02000000 # macro +PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK = 0x04000000 # macro +PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK = 0x08000000 # macro +PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK = 0x10000000 # macro +PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT = 0x0 # macro +PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT = 0x1 # macro +PA_SU_SC_MODE_CNTL__FACE__SHIFT = 0x2 # macro +PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT = 0x3 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT = 0x5 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT = 0x8 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT = 0xb # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT = 0xc # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT = 0xd # macro +PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT = 0x10 # macro +PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT = 0x13 # macro +PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT = 0x14 # macro +PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT = 0x15 # macro +PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT = 0x16 # macro +PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT = 0x17 # macro +PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT = 0x18 # macro +PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK = 0x00000001 # macro +PA_SU_SC_MODE_CNTL__CULL_BACK_MASK = 0x00000002 # macro +PA_SU_SC_MODE_CNTL__FACE_MASK = 0x00000004 # macro +PA_SU_SC_MODE_CNTL__POLY_MODE_MASK = 0x00000018 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK = 0x000000E0 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK = 0x00000700 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK = 0x00000800 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK = 0x00001000 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK = 0x00002000 # macro +PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK = 0x00010000 # macro +PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK = 0x00080000 # macro +PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK = 0x00100000 # macro +PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK = 0x00200000 # macro +PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK = 0x00400000 # macro +PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK = 0x00800000 # macro +PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK = 0x01000000 # macro +PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT = 0x0 # macro +PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT = 0x1 # macro +PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT = 0x2 # macro +PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT = 0x3 # macro +PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT = 0x4 # macro +PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT = 0x5 # macro +PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT = 0x8 # macro +PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT = 0x9 # macro +PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT = 0xa # macro +PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT = 0xb # macro +PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK = 0x00000001 # macro +PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK = 0x00000002 # macro +PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK = 0x00000004 # macro +PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK = 0x00000008 # macro +PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK = 0x00000010 # macro +PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK = 0x00000020 # macro +PA_CL_VTE_CNTL__VTX_XY_FMT_MASK = 0x00000100 # macro +PA_CL_VTE_CNTL__VTX_Z_FMT_MASK = 0x00000200 # macro +PA_CL_VTE_CNTL__VTX_W0_FMT_MASK = 0x00000400 # macro +PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK = 0x00000800 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT = 0x0 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT = 0x1 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT = 0x2 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT = 0x3 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT = 0x4 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT = 0x5 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT = 0x6 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT = 0x7 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT = 0x8 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT = 0x9 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT = 0xa # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT = 0xb # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT = 0xc # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT = 0xd # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT = 0xe # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT = 0xf # macro +PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT = 0x10 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT = 0x11 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT = 0x12 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT = 0x13 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT = 0x14 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT = 0x15 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT = 0x16 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT = 0x17 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT = 0x18 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT = 0x1b # macro +PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT = 0x1c # macro +PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT = 0x1d # macro +PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT = 0x1e # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK = 0x00000001 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK = 0x00000002 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK = 0x00000004 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK = 0x00000008 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK = 0x00000010 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK = 0x00000020 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK = 0x00000040 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK = 0x00000080 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK = 0x00000100 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK = 0x00000200 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK = 0x00000400 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK = 0x00000800 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK = 0x00001000 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK = 0x00002000 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK = 0x00004000 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK = 0x00008000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK = 0x00010000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK = 0x00020000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK = 0x00040000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK = 0x00080000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK = 0x00100000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK = 0x00200000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK = 0x00400000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK = 0x00800000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK = 0x01000000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK = 0x08000000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK = 0x10000000 # macro +PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK = 0x20000000 # macro +PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK = 0x40000000 # macro +PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT = 0x0 # macro +PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT = 0x1 # macro +PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT = 0x2 # macro +PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT = 0x3 # macro +PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT = 0x4 # macro +PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT = 0x5 # macro +PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT = 0x6 # macro +PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT = 0x7 # macro +PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT = 0x8 # macro +PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT = 0x9 # macro +PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT = 0xa # macro +PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT = 0xb # macro +PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT = 0xc # macro +PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT = 0xd # macro +PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT = 0xe # macro +PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT = 0x14 # macro +PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK = 0x00000001 # macro +PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK = 0x00000002 # macro +PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK = 0x00000004 # macro +PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK = 0x00000008 # macro +PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK = 0x00000010 # macro +PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK = 0x00000020 # macro +PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK = 0x00000040 # macro +PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK = 0x00000080 # macro +PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK = 0x00000100 # macro +PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK = 0x00000200 # macro +PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK = 0x00000400 # macro +PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK = 0x00000800 # macro +PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK = 0x00001000 # macro +PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK = 0x00002000 # macro +PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK = 0x00004000 # macro +PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK = 0x00100000 # macro +PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT = 0x0 # macro +PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT = 0x2 # macro +PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT = 0x3 # macro +PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK = 0x00000003 # macro +PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK = 0x00000004 # macro +PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK = 0x00000008 # macro +PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT = 0x0 # macro +PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK = 0xFFFFFFFF # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT = 0x0 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT = 0x1 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT = 0x2 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT = 0x3 # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT = 0x4 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT = 0x5 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT = 0x6 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT = 0x7 # macro +PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT = 0x8 # macro +PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT = 0x1e # macro +PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT = 0x1f # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK = 0x00000001 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK = 0x00000002 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK = 0x00000004 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK = 0x00000008 # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK = 0x00000010 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK = 0x00000020 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK = 0x00000040 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK = 0x00000080 # macro +PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK = 0x0000FF00 # macro +PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK = 0x40000000 # macro +PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK = 0x80000000 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT = 0x0 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT = 0x1 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT = 0x2 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT = 0x3 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT = 0x4 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK = 0x00000001 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK = 0x00000002 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK = 0x00000004 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK = 0x00000008 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK = 0x00000010 # macro +PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT = 0x0 # macro +PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT = 0x1 # macro +PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT = 0x2 # macro +PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK = 0x00000001 # macro +PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK = 0x00000002 # macro +PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK = 0x000003FC # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT = 0x0 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT = 0x1 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT = 0x2 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT = 0x3 # macro +PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT = 0x4 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK = 0x00000001 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK = 0x00000002 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK = 0x00000004 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK = 0x00000008 # macro +PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK = 0x00000010 # macro +PA_STEREO_CNTL__STEREO_MODE__SHIFT = 0x1 # macro +PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT = 0x5 # macro +PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT = 0x8 # macro +PA_STEREO_CNTL__VP_ID_MODE__SHIFT = 0x10 # macro +PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT = 0x13 # macro +PA_STEREO_CNTL__STEREO_MODE_MASK = 0x0000001E # macro +PA_STEREO_CNTL__RT_SLICE_MODE_MASK = 0x000000E0 # macro +PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK = 0x00000F00 # macro +PA_STEREO_CNTL__VP_ID_MODE_MASK = 0x00070000 # macro +PA_STEREO_CNTL__VP_ID_OFFSET_MASK = 0x00780000 # macro +PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT = 0x0 # macro +PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT = 0x0 # macro +PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT = 0x3 # macro +PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT = 0x6 # macro +PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT = 0x9 # macro +PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT = 0xd # macro +PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT = 0xe # macro +PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK = 0x00000007 # macro +PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK = 0x00000038 # macro +PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK = 0x000001C0 # macro +PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK = 0x00000E00 # macro +PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK = 0x00002000 # macro +PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK = 0x00004000 # macro +PA_SU_POINT_SIZE__HEIGHT__SHIFT = 0x0 # macro +PA_SU_POINT_SIZE__WIDTH__SHIFT = 0x10 # macro +PA_SU_POINT_SIZE__HEIGHT_MASK = 0x0000FFFF # macro +PA_SU_POINT_SIZE__WIDTH_MASK = 0xFFFF0000 # macro +PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT = 0x0 # macro +PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT = 0x10 # macro +PA_SU_POINT_MINMAX__MIN_SIZE_MASK = 0x0000FFFF # macro +PA_SU_POINT_MINMAX__MAX_SIZE_MASK = 0xFFFF0000 # macro +PA_SU_LINE_CNTL__WIDTH__SHIFT = 0x0 # macro +PA_SU_LINE_CNTL__WIDTH_MASK = 0x0000FFFF # macro +PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT = 0x0 # macro +PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT = 0x10 # macro +PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT = 0x1c # macro +PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT = 0x1d # macro +PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK = 0x0000FFFF # macro +PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK = 0x00FF0000 # macro +PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK = 0x10000000 # macro +PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK = 0x60000000 # macro +VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT = 0x0 # macro +VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK = 0xFFFFFFFF # macro +VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT = 0x0 # macro +VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK = 0xFFFFFFFF # macro +PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT = 0x0 # macro +PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT = 0x1 # macro +PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT = 0x2 # macro +PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT = 0x3 # macro +PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT = 0x5 # macro +PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT = 0x6 # macro +PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK = 0x00000001 # macro +PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK = 0x00000002 # macro +PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK = 0x00000004 # macro +PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK = 0x00000008 # macro +PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK = 0x00000020 # macro +PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK = 0x00000040 # macro +PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT = 0x0 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT = 0x1 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT = 0x2 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT = 0x3 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT = 0x4 # macro +PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT = 0x7 # macro +PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT = 0x8 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT = 0x9 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT = 0xa # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT = 0xb # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT = 0xc # macro +PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT = 0xd # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT = 0xe # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT = 0xf # macro +PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT = 0x10 # macro +PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT = 0x11 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT = 0x12 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT = 0x13 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT = 0x14 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT = 0x18 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT = 0x19 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT = 0x1a # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT = 0x1b # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT = 0x1c # macro +PA_SC_MODE_CNTL_1__WALK_SIZE_MASK = 0x00000001 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK = 0x00000002 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK = 0x00000004 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK = 0x00000008 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK = 0x00000070 # macro +PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK = 0x00000080 # macro +PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK = 0x00000100 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK = 0x00000200 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK = 0x00000400 # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK = 0x00000800 # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK = 0x00001000 # macro +PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK = 0x00002000 # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK = 0x00004000 # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK = 0x00008000 # macro +PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK = 0x00010000 # macro +PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK = 0x00020000 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK = 0x00040000 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK = 0x00080000 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK = 0x00F00000 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK = 0x01000000 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK = 0x02000000 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK = 0x04000000 # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK = 0x08000000 # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK = 0x70000000 # macro +VGT_ENHANCE__MISC__SHIFT = 0x0 # macro +VGT_ENHANCE__MISC_MASK = 0xFFFFFFFF # macro +IA_ENHANCE__MISC__SHIFT = 0x0 # macro +IA_ENHANCE__MISC_MASK = 0xFFFFFFFF # macro +VGT_DMA_SIZE__NUM_INDICES__SHIFT = 0x0 # macro +VGT_DMA_SIZE__NUM_INDICES_MASK = 0xFFFFFFFF # macro +VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT = 0x0 # macro +VGT_DMA_MAX_SIZE__MAX_SIZE_MASK = 0xFFFFFFFF # macro +VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT = 0x0 # macro +VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT = 0x2 # macro +VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT = 0x4 # macro +VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT = 0x6 # macro +VGT_DMA_INDEX_TYPE__ATC__SHIFT = 0x8 # macro +VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT = 0x9 # macro +VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT = 0xa # macro +VGT_DMA_INDEX_TYPE__MTYPE__SHIFT = 0xb # macro +VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT = 0xe # macro +VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK = 0x00000003 # macro +VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK = 0x0000000C # macro +VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK = 0x00000030 # macro +VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK = 0x000000C0 # macro +VGT_DMA_INDEX_TYPE__ATC_MASK = 0x00000100 # macro +VGT_DMA_INDEX_TYPE__NOT_EOP_MASK = 0x00000200 # macro +VGT_DMA_INDEX_TYPE__REQ_PATH_MASK = 0x00000400 # macro +VGT_DMA_INDEX_TYPE__MTYPE_MASK = 0x00003800 # macro +VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK = 0x00004000 # macro +WD_ENHANCE__MISC__SHIFT = 0x0 # macro +WD_ENHANCE__MISC_MASK = 0xFFFFFFFF # macro +VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT = 0x0 # macro +VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT = 0x1 # macro +VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT = 0x2 # macro +VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK = 0x00000001 # macro +VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK = 0x00000002 # macro +VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK = 0x00000004 # macro +VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT = 0x0 # macro +VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK = 0xFFFFFFFF # macro +VGT_PRIMITIVEID_RESET__VALUE__SHIFT = 0x0 # macro +VGT_PRIMITIVEID_RESET__VALUE_MASK = 0xFFFFFFFF # macro +VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT = 0x0 # macro +VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT = 0xa # macro +VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT = 0x1b # macro +VGT_EVENT_INITIATOR__EVENT_TYPE_MASK = 0x0000003F # macro +VGT_EVENT_INITIATOR__ADDRESS_HI_MASK = 0x07FFFC00 # macro +VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK = 0x08000000 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT = 0x1 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT = 0x3 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT = 0x4 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK = 0x00000002 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK = 0x00000008 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK = 0x00000010 # macro +VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT = 0x0 # macro +VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK = 0x00007FFF # macro +VGT_REUSE_OFF__REUSE_OFF__SHIFT = 0x0 # macro +VGT_REUSE_OFF__REUSE_OFF_MASK = 0x00000001 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT = 0x0 # macro +DB_HTILE_SURFACE__FULL_CACHE__SHIFT = 0x1 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT = 0x2 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT = 0x3 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT = 0x4 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT = 0xa # macro +DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT = 0x10 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT = 0x11 # macro +DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT = 0x12 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK = 0x00000001 # macro +DB_HTILE_SURFACE__FULL_CACHE_MASK = 0x00000002 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK = 0x00000004 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK = 0x00000008 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK = 0x000003F0 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK = 0x0000FC00 # macro +DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK = 0x00010000 # macro +DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK = 0x00020000 # macro +DB_HTILE_SURFACE__PIPE_ALIGNED_MASK = 0x00040000 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT = 0x0 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT = 0x4 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT = 0xc # macro +DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT = 0x18 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK = 0x00000007 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK = 0x00000FF0 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK = 0x000FF000 # macro +DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK = 0x01000000 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT = 0x0 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT = 0x4 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT = 0xc # macro +DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT = 0x18 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK = 0x00000007 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK = 0x00000FF0 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK = 0x000FF000 # macro +DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK = 0x01000000 # macro +DB_PRELOAD_CONTROL__START_X__SHIFT = 0x0 # macro +DB_PRELOAD_CONTROL__START_Y__SHIFT = 0x8 # macro +DB_PRELOAD_CONTROL__MAX_X__SHIFT = 0x10 # macro +DB_PRELOAD_CONTROL__MAX_Y__SHIFT = 0x18 # macro +DB_PRELOAD_CONTROL__START_X_MASK = 0x000000FF # macro +DB_PRELOAD_CONTROL__START_Y_MASK = 0x0000FF00 # macro +DB_PRELOAD_CONTROL__MAX_X_MASK = 0x00FF0000 # macro +DB_PRELOAD_CONTROL__MAX_Y_MASK = 0xFF000000 # macro +VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT = 0x0 # macro +VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT = 0x0 # macro +VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK = 0x000001FF # macro +VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT = 0x0 # macro +VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK = 0x000007FF # macro +GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT = 0x0 # macro +GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT = 0x9 # macro +GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK = 0x000001FF # macro +GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK = 0x0003FE00 # macro +VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT = 0x0 # macro +VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT = 0x8 # macro +VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT = 0x10 # macro +VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT = 0x18 # macro +VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT = 0x1d # macro +VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK = 0x000000FF # macro +VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK = 0x0000FF00 # macro +VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK = 0x00FF0000 # macro +VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK = 0x1F000000 # macro +VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK = 0xE0000000 # macro +VGT_SHADER_STAGES_EN__LS_EN__SHIFT = 0x0 # macro +VGT_SHADER_STAGES_EN__HS_EN__SHIFT = 0x2 # macro +VGT_SHADER_STAGES_EN__ES_EN__SHIFT = 0x3 # macro +VGT_SHADER_STAGES_EN__GS_EN__SHIFT = 0x5 # macro +VGT_SHADER_STAGES_EN__VS_EN__SHIFT = 0x6 # macro +VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT = 0x8 # macro +VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT = 0xc # macro +VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT = 0xd # macro +VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT = 0xe # macro +VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT = 0xf # macro +VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT = 0x13 # macro +VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT = 0x15 # macro +VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT = 0x16 # macro +VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT = 0x17 # macro +VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT = 0x18 # macro +VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT = 0x19 # macro +VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG__SHIFT = 0x1a # macro +VGT_SHADER_STAGES_EN__LS_EN_MASK = 0x00000003 # macro +VGT_SHADER_STAGES_EN__HS_EN_MASK = 0x00000004 # macro +VGT_SHADER_STAGES_EN__ES_EN_MASK = 0x00000018 # macro +VGT_SHADER_STAGES_EN__GS_EN_MASK = 0x00000020 # macro +VGT_SHADER_STAGES_EN__VS_EN_MASK = 0x000000C0 # macro +VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK = 0x00000100 # macro +VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK = 0x00001000 # macro +VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK = 0x00002000 # macro +VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK = 0x00004000 # macro +VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK = 0x00078000 # macro +VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK = 0x00180000 # macro +VGT_SHADER_STAGES_EN__HS_W32_EN_MASK = 0x00200000 # macro +VGT_SHADER_STAGES_EN__GS_W32_EN_MASK = 0x00400000 # macro +VGT_SHADER_STAGES_EN__VS_W32_EN_MASK = 0x00800000 # macro +VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK = 0x01000000 # macro +VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK = 0x02000000 # macro +VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG_MASK = 0x04000000 # macro +VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT = 0x0 # macro +VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT = 0x8 # macro +VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT = 0xe # macro +VGT_LS_HS_CONFIG__NUM_PATCHES_MASK = 0x000000FF # macro +VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK = 0x00003F00 # macro +VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK = 0x000FC000 # macro +VGT_TF_PARAM__TYPE__SHIFT = 0x0 # macro +VGT_TF_PARAM__PARTITIONING__SHIFT = 0x2 # macro +VGT_TF_PARAM__TOPOLOGY__SHIFT = 0x5 # macro +VGT_TF_PARAM__NOT_USED__SHIFT = 0x9 # macro +VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT = 0xa # macro +VGT_TF_PARAM__DISABLE_DONUTS__SHIFT = 0xe # macro +VGT_TF_PARAM__RDREQ_POLICY__SHIFT = 0xf # macro +VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT = 0x11 # macro +VGT_TF_PARAM__DETECT_ONE__SHIFT = 0x13 # macro +VGT_TF_PARAM__DETECT_ZERO__SHIFT = 0x14 # macro +VGT_TF_PARAM__MTYPE__SHIFT = 0x17 # macro +VGT_TF_PARAM__TYPE_MASK = 0x00000003 # macro +VGT_TF_PARAM__PARTITIONING_MASK = 0x0000001C # macro +VGT_TF_PARAM__TOPOLOGY_MASK = 0x000000E0 # macro +VGT_TF_PARAM__NOT_USED_MASK = 0x00000200 # macro +VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK = 0x00003C00 # macro +VGT_TF_PARAM__DISABLE_DONUTS_MASK = 0x00004000 # macro +VGT_TF_PARAM__RDREQ_POLICY_MASK = 0x00018000 # macro +VGT_TF_PARAM__DISTRIBUTION_MODE_MASK = 0x00060000 # macro +VGT_TF_PARAM__DETECT_ONE_MASK = 0x00080000 # macro +VGT_TF_PARAM__DETECT_ZERO_MASK = 0x00100000 # macro +VGT_TF_PARAM__MTYPE_MASK = 0x03800000 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT = 0x0 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT = 0x8 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT = 0xa # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT = 0xc # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT = 0xe # macro +DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT = 0x10 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK = 0x00000001 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK = 0x00000300 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK = 0x00000C00 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK = 0x00003000 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK = 0x0000C000 # macro +DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK = 0x00010000 # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT = 0x8 # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK = 0x000000FF # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK = 0x00000100 # macro +PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_GS_INSTANCE_CNT__ENABLE__SHIFT = 0x0 # macro +VGT_GS_INSTANCE_CNT__CNT__SHIFT = 0x2 # macro +VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT = 0x1f # macro +VGT_GS_INSTANCE_CNT__ENABLE_MASK = 0x00000001 # macro +VGT_GS_INSTANCE_CNT__CNT_MASK = 0x000001FC # macro +VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK = 0x80000000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT = 0x0 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT = 0x4 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT = 0x8 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT = 0xc # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT = 0x10 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT = 0x14 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT = 0x18 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT = 0x1c # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK = 0x0000000F # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK = 0x000000F0 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK = 0x00000F00 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK = 0x0000F000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK = 0x000F0000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK = 0x00F00000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK = 0x0F000000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK = 0xF0000000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT = 0x0 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT = 0x4 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT = 0x8 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT = 0xc # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT = 0x10 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT = 0x14 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT = 0x18 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT = 0x1c # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK = 0x0000000F # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK = 0x000000F0 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK = 0x00000F00 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK = 0x0000F000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK = 0x000F0000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK = 0x00F00000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK = 0x0F000000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK = 0xF0000000 # macro +PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT = 0x9 # macro +PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT = 0xa # macro +PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT = 0xb # macro +PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT = 0xc # macro +PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT = 0xd # macro +PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK = 0x00000200 # macro +PA_SC_LINE_CNTL__LAST_PIXEL_MASK = 0x00000400 # macro +PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK = 0x00000800 # macro +PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK = 0x00001000 # macro +PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK = 0x00002000 # macro +PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT = 0x0 # macro +PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT = 0x4 # macro +PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT = 0xd # macro +PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT = 0x14 # macro +PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT = 0x18 # macro +PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT = 0x1a # macro +PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING__SHIFT = 0x1c # macro +PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER__SHIFT = 0x1d # macro +PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK = 0x00000007 # macro +PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK = 0x00000010 # macro +PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK = 0x0001E000 # macro +PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK = 0x00700000 # macro +PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK = 0x03000000 # macro +PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK = 0x0C000000 # macro +PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING_MASK = 0x10000000 # macro +PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER_MASK = 0x20000000 # macro +PA_SU_VTX_CNTL__PIX_CENTER__SHIFT = 0x0 # macro +PA_SU_VTX_CNTL__ROUND_MODE__SHIFT = 0x1 # macro +PA_SU_VTX_CNTL__QUANT_MODE__SHIFT = 0x3 # macro +PA_SU_VTX_CNTL__PIX_CENTER_MASK = 0x00000001 # macro +PA_SU_VTX_CNTL__ROUND_MODE_MASK = 0x00000006 # macro +PA_SU_VTX_CNTL__QUANT_MODE_MASK = 0x00000038 # macro +PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT = 0x0 # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT = 0x10 # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK = 0x0000FFFF # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK = 0xFFFF0000 # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT = 0x0 # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT = 0x10 # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK = 0x0000FFFF # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK = 0xFFFF0000 # macro +PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT = 0x0 # macro +PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT = 0x2 # macro +PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT = 0x3 # macro +PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT = 0x5 # macro +PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD__SHIFT = 0x7 # macro +PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK = 0x00000003 # macro +PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK = 0x00000004 # macro +PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK = 0x00000008 # macro +PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK = 0x00000060 # macro +PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD_MASK = 0x00000080 # macro +PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT = 0x0 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT = 0x2 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT = 0x3 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT = 0x4 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT = 0x7 # macro +PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT = 0xa # macro +PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT = 0xd # macro +PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT = 0x12 # macro +PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT = 0x13 # macro +PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT = 0x1b # macro +PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT = 0x1c # macro +PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT = 0x1d # macro +PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK = 0x00000003 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK = 0x00000004 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK = 0x00000008 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK = 0x00000070 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK = 0x00000380 # macro +PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK = 0x00001C00 # macro +PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK = 0x0003E000 # macro +PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK = 0x00040000 # macro +PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK = 0x07F80000 # macro +PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK = 0x08000000 # macro +PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK = 0x10000000 # macro +PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK = 0x60000000 # macro +PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT = 0x0 # macro +PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT = 0x10 # macro +PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK = 0x0000FFFF # macro +PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK = 0xFFFF0000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT = 0x0 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT = 0x1 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT = 0x5 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT = 0x6 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT = 0xa # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT = 0xb # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT = 0xc # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT = 0xd # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT = 0xe # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT = 0xf # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT = 0x10 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT = 0x12 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT = 0x13 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT = 0x14 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT = 0x15 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT = 0x16 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT = 0x17 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT = 0x18 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT = 0x19 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT = 0x1b # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK = 0x00000001 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK = 0x0000001E # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK = 0x00000020 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK = 0x000003C0 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK = 0x00000400 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK = 0x00000800 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK = 0x00001000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK = 0x00002000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK = 0x00004000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK = 0x00008000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK = 0x00030000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK = 0x00040000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK = 0x00080000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK = 0x00100000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK = 0x00200000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK = 0x00400000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK = 0x00800000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK = 0x01000000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK = 0x06000000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK = 0x18000000 # macro +PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT = 0x0 # macro +PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT__SHIFT = 0xc # macro +PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC__SHIFT = 0xd # macro +PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT = 0xe # macro +PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT = 0x10 # macro +PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT = 0x18 # macro +PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK = 0x000007FF # macro +PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT_MASK = 0x00001000 # macro +PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC_MASK = 0x00002000 # macro +PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES_MASK = 0x00004000 # macro +PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK = 0x00FF0000 # macro +PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK = 0xFF000000 # macro +PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X__SHIFT = 0x0 # macro +PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X__SHIFT = 0x1 # macro +PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT = 0x2 # macro +PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW__SHIFT = 0x3 # macro +PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT = 0x4 # macro +PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN__SHIFT = 0x7 # macro +PA_SC_BINNER_CNTL_2__ZPP_ENABLED__SHIFT = 0xb # macro +PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED__SHIFT = 0xc # macro +PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD__SHIFT = 0xd # macro +PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION__SHIFT = 0x15 # macro +PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X_MASK = 0x00000001 # macro +PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X_MASK = 0x00000002 # macro +PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK = 0x00000004 # macro +PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW_MASK = 0x00000008 # macro +PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK = 0x00000070 # macro +PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN_MASK = 0x00000780 # macro +PA_SC_BINNER_CNTL_2__ZPP_ENABLED_MASK = 0x00000800 # macro +PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED_MASK = 0x00001000 # macro +PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD_MASK = 0x001FE000 # macro +PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION_MASK = 0x00200000 # macro +CB_COLOR0_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR0_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR0_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR0_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR0_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR0_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR0_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR0_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR0_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR0_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR0_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR0_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR0_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR0_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR0_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR0_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR0_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR0_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR0_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR0_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR0_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR0_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR1_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR1_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR1_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR1_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR1_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR1_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR1_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR1_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR1_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR1_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR1_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR1_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR1_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR1_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR1_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR1_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR1_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR1_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR1_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR1_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR1_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR1_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR2_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR2_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR2_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR2_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR2_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR2_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR2_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR2_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR2_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR2_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR2_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR2_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR2_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR2_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR2_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR2_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR2_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR2_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR2_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR2_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR2_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR2_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR3_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR3_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR3_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR3_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR3_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR3_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR3_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR3_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR3_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR3_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR3_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR3_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR3_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR3_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR3_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR3_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR3_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR3_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR3_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR3_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR3_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR3_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR4_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR4_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR4_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR4_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR4_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR4_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR4_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR4_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR4_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR4_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR4_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR4_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR4_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR4_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR4_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR4_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR4_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR4_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR4_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR4_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR4_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR4_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR5_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR5_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR5_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR5_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR5_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR5_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR5_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR5_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR5_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR5_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR5_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR5_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR5_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR5_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR5_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR5_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR5_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR5_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR5_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR5_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR5_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR5_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR6_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR6_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR6_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR6_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR6_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR6_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR6_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR6_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR6_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR6_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR6_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR6_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR6_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR6_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR6_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR6_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR6_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR6_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR6_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR6_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR6_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR6_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR7_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR7_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR7_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR7_VIEW__MIP_LEVEL__SHIFT = 0x1a # macro +CB_COLOR7_VIEW__SLICE_START_MASK = 0x00001FFF # macro +CB_COLOR7_VIEW__SLICE_MAX_MASK = 0x03FFE000 # macro +CB_COLOR7_VIEW__MIP_LEVEL_MASK = 0x3C000000 # macro +CB_COLOR7_INFO__FORMAT__SHIFT = 0x0 # macro +CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT = 0x7 # macro +CB_COLOR7_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR7_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR7_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR7_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR7_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR7_INFO__FORMAT_MASK = 0x0000001F # macro +CB_COLOR7_INFO__LINEAR_GENERAL_MASK = 0x00000080 # macro +CB_COLOR7_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR7_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR7_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR7_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR7_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR7_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT = 0x0 # macro +CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x2 # macro +CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT = 0x3 # macro +CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT = 0x4 # macro +CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT = 0x5 # macro +CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK = 0x00000003 # macro +CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00000004 # macro +CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK = 0x00000008 # macro +CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK = 0x00000010 # macro +CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK = 0x00000020 # macro +CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT = 0x1 # macro +CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT = 0xa # macro +CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT = 0x15 # macro +CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE__SHIFT = 0x16 # macro +CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT = 0x17 # macro +CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT = 0x18 # macro +CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK = 0x00000002 # macro +CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK = 0x00000400 # macro +CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK = 0x00200000 # macro +CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE_MASK = 0x00400000 # macro +CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK = 0x00800000 # macro +CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK = 0x01000000 # macro +CB_COLOR7_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR0_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR1_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR2_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR3_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR4_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR5_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR6_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR7_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR0_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR1_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR2_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR3_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR4_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR5_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR6_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR7_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR0_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR1_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR2_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR3_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR4_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR5_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR6_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT = 0xd # macro +CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT = 0xe # macro +CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT = 0x18 # macro +CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK = 0x00001FFF # macro +CB_COLOR7_ATTRIB3__META_LINEAR_MASK = 0x00002000 # macro +CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK = 0x0007C000 # macro +CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK = 0x03000000 # macro +CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK = 0x40000000 # macro +CONFIG_RESERVED_REG0__DATA__SHIFT = 0x0 # macro +CONFIG_RESERVED_REG0__DATA_MASK = 0xFFFFFFFF # macro +CONFIG_RESERVED_REG1__DATA__SHIFT = 0x0 # macro +CONFIG_RESERVED_REG1__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT = 0x10 # macro +CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT = 0x11 # macro +CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT = 0x12 # macro +CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT = 0x13 # macro +CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT = 0x14 # macro +CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT = 0x15 # macro +CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT = 0x16 # macro +CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT = 0x17 # macro +CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT = 0x1b # macro +CP_MEC_CNTL__MEC_ME2_HALT__SHIFT = 0x1c # macro +CP_MEC_CNTL__MEC_ME2_STEP__SHIFT = 0x1d # macro +CP_MEC_CNTL__MEC_ME1_HALT__SHIFT = 0x1e # macro +CP_MEC_CNTL__MEC_ME1_STEP__SHIFT = 0x1f # macro +CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK = 0x00010000 # macro +CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK = 0x00020000 # macro +CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK = 0x00040000 # macro +CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK = 0x00080000 # macro +CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK = 0x00100000 # macro +CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK = 0x00200000 # macro +CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK = 0x00400000 # macro +CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK = 0x00800000 # macro +CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK = 0x08000000 # macro +CP_MEC_CNTL__MEC_ME2_HALT_MASK = 0x10000000 # macro +CP_MEC_CNTL__MEC_ME2_STEP_MASK = 0x20000000 # macro +CP_MEC_CNTL__MEC_ME1_HALT_MASK = 0x40000000 # macro +CP_MEC_CNTL__MEC_ME1_STEP_MASK = 0x80000000 # macro +CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT = 0x4 # macro +CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT = 0x6 # macro +CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT = 0x8 # macro +CP_ME_CNTL__PFP_PIPE0_DISABLE__SHIFT = 0xc # macro +CP_ME_CNTL__PFP_PIPE1_DISABLE__SHIFT = 0xd # macro +CP_ME_CNTL__ME_PIPE0_DISABLE__SHIFT = 0xe # macro +CP_ME_CNTL__ME_PIPE1_DISABLE__SHIFT = 0xf # macro +CP_ME_CNTL__CE_PIPE0_RESET__SHIFT = 0x10 # macro +CP_ME_CNTL__CE_PIPE1_RESET__SHIFT = 0x11 # macro +CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT = 0x12 # macro +CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT = 0x13 # macro +CP_ME_CNTL__ME_PIPE0_RESET__SHIFT = 0x14 # macro +CP_ME_CNTL__ME_PIPE1_RESET__SHIFT = 0x15 # macro +CP_ME_CNTL__CE_HALT__SHIFT = 0x18 # macro +CP_ME_CNTL__CE_STEP__SHIFT = 0x19 # macro +CP_ME_CNTL__PFP_HALT__SHIFT = 0x1a # macro +CP_ME_CNTL__PFP_STEP__SHIFT = 0x1b # macro +CP_ME_CNTL__ME_HALT__SHIFT = 0x1c # macro +CP_ME_CNTL__ME_STEP__SHIFT = 0x1d # macro +CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK = 0x00000010 # macro +CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK = 0x00000040 # macro +CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK = 0x00000100 # macro +CP_ME_CNTL__PFP_PIPE0_DISABLE_MASK = 0x00001000 # macro +CP_ME_CNTL__PFP_PIPE1_DISABLE_MASK = 0x00002000 # macro +CP_ME_CNTL__ME_PIPE0_DISABLE_MASK = 0x00004000 # macro +CP_ME_CNTL__ME_PIPE1_DISABLE_MASK = 0x00008000 # macro +CP_ME_CNTL__CE_PIPE0_RESET_MASK = 0x00010000 # macro +CP_ME_CNTL__CE_PIPE1_RESET_MASK = 0x00020000 # macro +CP_ME_CNTL__PFP_PIPE0_RESET_MASK = 0x00040000 # macro +CP_ME_CNTL__PFP_PIPE1_RESET_MASK = 0x00080000 # macro +CP_ME_CNTL__ME_PIPE0_RESET_MASK = 0x00100000 # macro +CP_ME_CNTL__ME_PIPE1_RESET_MASK = 0x00200000 # macro +CP_ME_CNTL__CE_HALT_MASK = 0x01000000 # macro +CP_ME_CNTL__CE_STEP_MASK = 0x02000000 # macro +CP_ME_CNTL__PFP_HALT_MASK = 0x04000000 # macro +CP_ME_CNTL__PFP_STEP_MASK = 0x08000000 # macro +CP_ME_CNTL__ME_HALT_MASK = 0x10000000 # macro +CP_ME_CNTL__ME_STEP_MASK = 0x20000000 # macro +GRBM_GFX_CNTL__PIPEID__SHIFT = 0x0 # macro +GRBM_GFX_CNTL__MEID__SHIFT = 0x2 # macro +GRBM_GFX_CNTL__VMID__SHIFT = 0x4 # macro +GRBM_GFX_CNTL__QUEUEID__SHIFT = 0x8 # macro +GRBM_GFX_CNTL__CTXID__SHIFT = 0xb # macro +GRBM_GFX_CNTL__PIPEID_MASK = 0x00000003 # macro +GRBM_GFX_CNTL__MEID_MASK = 0x0000000C # macro +GRBM_GFX_CNTL__VMID_MASK = 0x000000F0 # macro +GRBM_GFX_CNTL__QUEUEID_MASK = 0x00000700 # macro +GRBM_GFX_CNTL__CTXID_MASK = 0x00003800 # macro +GRBM_NOWHERE__DATA__SHIFT = 0x0 # macro +GRBM_NOWHERE__DATA_MASK = 0xFFFFFFFF # macro +PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE__SHIFT = 0x6 # macro +PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT = 0x7 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE__SHIFT = 0x8 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE__SHIFT = 0xd # macro +PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE__SHIFT = 0xe # macro +PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE__SHIFT = 0xf # macro +PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE__SHIFT = 0x10 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH__SHIFT = 0x11 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE__SHIFT = 0x12 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS__SHIFT = 0x13 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT__SHIFT = 0x1a # macro +PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE_MASK = 0x00000040 # macro +PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK = 0x00000080 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE_MASK = 0x00001F00 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE_MASK = 0x00002000 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE_MASK = 0x00004000 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE_MASK = 0x00008000 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE_MASK = 0x00010000 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH_MASK = 0x00020000 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE_MASK = 0x00040000 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS_MASK = 0x03F80000 # macro +PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT_MASK = 0xFC000000 # macro +PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT = 0x0 # macro +PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT = 0x1 # macro +PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT = 0x2 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT = 0x3 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT = 0x4 # macro +PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT = 0x5 # macro +PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT = 0x6 # macro +PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT = 0x7 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT = 0x8 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT = 0x9 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT = 0xa # macro +PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT = 0xb # macro +PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT = 0xc # macro +PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT = 0xd # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT = 0xe # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT = 0xf # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT = 0x10 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT = 0x11 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT = 0x12 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT = 0x13 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT = 0x14 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT = 0x15 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT = 0x16 # macro +PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT = 0x17 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT = 0x18 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT = 0x19 # macro +PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT = 0x1a # macro +PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT = 0x1b # macro +PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT = 0x1c # macro +PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT = 0x1d # macro +PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK = 0x00000001 # macro +PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK = 0x00000002 # macro +PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK = 0x00000004 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK = 0x00000008 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK = 0x00000010 # macro +PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK = 0x00000020 # macro +PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK = 0x00000040 # macro +PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK = 0x00000080 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK = 0x00000100 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK = 0x00000200 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK = 0x00000400 # macro +PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK = 0x00000800 # macro +PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK = 0x00001000 # macro +PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK = 0x00002000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK = 0x00004000 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK = 0x00008000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK = 0x00010000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK = 0x00020000 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK = 0x00040000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK = 0x00080000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK = 0x00100000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK = 0x00200000 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK = 0x00400000 # macro +PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK = 0x00800000 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK = 0x01000000 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK = 0x02000000 # macro +PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK = 0x04000000 # macro +PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK = 0x08000000 # macro +PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK = 0x10000000 # macro +PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK = 0x20000000 # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT = 0x0 # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT = 0x1 # macro +PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT = 0x3 # macro +PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT = 0x4 # macro +PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE__SHIFT = 0x5 # macro +PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT = 0x6 # macro +PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT = 0x7 # macro +PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT = 0x8 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT = 0x9 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT = 0xa # macro +PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT = 0xb # macro +PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT = 0xe # macro +PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT = 0x10 # macro +PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT = 0x12 # macro +PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT = 0x13 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT = 0x14 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT = 0x15 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT = 0x16 # macro +PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT = 0x17 # macro +PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT = 0x18 # macro +PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT = 0x19 # macro +PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT = 0x1a # macro +PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT = 0x1b # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT = 0x1c # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT = 0x1d # macro +PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT = 0x1e # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK = 0x00000001 # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK = 0x00000006 # macro +PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK = 0x00000008 # macro +PA_SC_ENHANCE_1__BYPASS_PBB_MASK = 0x00000010 # macro +PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE_MASK = 0x00000020 # macro +PA_SC_ENHANCE_1__ECO_SPARE1_MASK = 0x00000040 # macro +PA_SC_ENHANCE_1__ECO_SPARE2_MASK = 0x00000080 # macro +PA_SC_ENHANCE_1__ECO_SPARE3_MASK = 0x00000100 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK = 0x00000200 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK = 0x00000400 # macro +PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK = 0x00000800 # macro +PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK = 0x00004000 # macro +PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK = 0x00010000 # macro +PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK = 0x00040000 # macro +PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK = 0x00080000 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK = 0x00100000 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK = 0x00200000 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK = 0x00400000 # macro +PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK = 0x00800000 # macro +PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK = 0x01000000 # macro +PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK = 0x02000000 # macro +PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK = 0x04000000 # macro +PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK = 0x08000000 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK = 0x10000000 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK = 0x20000000 # macro +PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK = 0x40000000 # macro +PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE__SHIFT = 0x0 # macro +PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE__SHIFT = 0x1 # macro +PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT = 0x2 # macro +PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT = 0x3 # macro +PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT = 0x4 # macro +PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT = 0x5 # macro +PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT = 0x7 # macro +PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT = 0x8 # macro +PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT = 0x9 # macro +PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT = 0xa # macro +PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT = 0xb # macro +PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT = 0xc # macro +PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT = 0xd # macro +PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT = 0xe # macro +PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT = 0xf # macro +PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT = 0x10 # macro +PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT = 0x11 # macro +PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT = 0x12 # macro +PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT = 0x15 # macro +PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT = 0x17 # macro +PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT = 0x1a # macro +PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT = 0x1b # macro +PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT = 0x1e # macro +PA_SC_ENHANCE_2__RSVD__SHIFT = 0x1f # macro +PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE_MASK = 0x00000001 # macro +PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE_MASK = 0x00000002 # macro +PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK = 0x00000004 # macro +PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK = 0x00000008 # macro +PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK = 0x00000010 # macro +PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK = 0x00000020 # macro +PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK = 0x00000080 # macro +PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK = 0x00000100 # macro +PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK = 0x00000200 # macro +PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK = 0x00000400 # macro +PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK = 0x00000800 # macro +PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK = 0x00001000 # macro +PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK = 0x00002000 # macro +PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK = 0x00004000 # macro +PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK = 0x00008000 # macro +PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK = 0x00010000 # macro +PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK = 0x00020000 # macro +PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK = 0x00040000 # macro +PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK = 0x00200000 # macro +PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK = 0x00800000 # macro +PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK = 0x04000000 # macro +PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK = 0x38000000 # macro +PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK = 0x40000000 # macro +PA_SC_ENHANCE_2__RSVD_MASK = 0x80000000 # macro +PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT = 0x0 # macro +PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST__SHIFT = 0x2 # macro +PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT = 0x3 # macro +PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT = 0x4 # macro +PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT = 0x5 # macro +PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER__SHIFT = 0x6 # macro +PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER__SHIFT = 0x7 # macro +PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS__SHIFT = 0x8 # macro +PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY__SHIFT = 0x9 # macro +PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES__SHIFT = 0xa # macro +PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION__SHIFT = 0xb # macro +PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED__SHIFT = 0xc # macro +PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT = 0xd # macro +PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION__SHIFT = 0xe # macro +PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN__SHIFT = 0xf # macro +PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS__SHIFT = 0x10 # macro +PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM__SHIFT = 0x11 # macro +PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE__SHIFT = 0x12 # macro +PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE__SHIFT = 0x13 # macro +PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT = 0x14 # macro +PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT = 0x15 # macro +PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE__SHIFT = 0x16 # macro +PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION__SHIFT = 0x17 # macro +PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY__SHIFT = 0x18 # macro +PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL__SHIFT = 0x19 # macro +PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL__SHIFT = 0x1a # macro +PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL__SHIFT = 0x1b # macro +PA_SC_ENHANCE_3__ECO_SPARE0__SHIFT = 0x1c # macro +PA_SC_ENHANCE_3__ECO_SPARE1__SHIFT = 0x1d # macro +PA_SC_ENHANCE_3__ECO_SPARE2__SHIFT = 0x1e # macro +PA_SC_ENHANCE_3__ECO_SPARE3__SHIFT = 0x1f # macro +PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK = 0x00000001 # macro +PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST_MASK = 0x00000004 # macro +PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK = 0x00000008 # macro +PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK = 0x00000010 # macro +PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK = 0x00000020 # macro +PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER_MASK = 0x00000040 # macro +PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_MASK = 0x00000080 # macro +PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS_MASK = 0x00000100 # macro +PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY_MASK = 0x00000200 # macro +PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES_MASK = 0x00000400 # macro +PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION_MASK = 0x00000800 # macro +PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED_MASK = 0x00001000 # macro +PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK = 0x00002000 # macro +PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION_MASK = 0x00004000 # macro +PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN_MASK = 0x00008000 # macro +PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS_MASK = 0x00010000 # macro +PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM_MASK = 0x00020000 # macro +PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE_MASK = 0x00040000 # macro +PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE_MASK = 0x00080000 # macro +PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK = 0x00100000 # macro +PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK = 0x00200000 # macro +PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE_MASK = 0x00400000 # macro +PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION_MASK = 0x00800000 # macro +PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY_MASK = 0x01000000 # macro +PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL_MASK = 0x02000000 # macro +PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL_MASK = 0x04000000 # macro +PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL_MASK = 0x08000000 # macro +PA_SC_ENHANCE_3__ECO_SPARE0_MASK = 0x10000000 # macro +PA_SC_ENHANCE_3__ECO_SPARE1_MASK = 0x20000000 # macro +PA_SC_ENHANCE_3__ECO_SPARE2_MASK = 0x40000000 # macro +PA_SC_ENHANCE_3__ECO_SPARE3_MASK = 0x80000000 # macro +PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT = 0x0 # macro +PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT = 0xa # macro +PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT = 0xd # macro +PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT = 0x13 # macro +PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT = 0x1b # macro +PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT = 0x1c # macro +PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK = 0x00000003 # macro +PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK = 0x00001C00 # macro +PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK = 0x0003E000 # macro +PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK = 0x07F80000 # macro +PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK = 0x08000000 # macro +PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK = 0xF0000000 # macro +PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT = 0x0 # macro +PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT = 0x1 # macro +PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK = 0x00000001 # macro +PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK = 0x00000002 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT = 0x0 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT = 0x1 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK = 0x00000001 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK = 0x00000002 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT = 0x0 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT = 0x1 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT = 0x5 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT = 0x8 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT = 0x1f # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK = 0x00000001 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK = 0x00000006 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK = 0x00000060 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK = 0x00000700 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK = 0x80000000 # macro +PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT = 0x0 # macro +PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT = 0x6 # macro +PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT = 0xf # macro +PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT = 0x15 # macro +PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK = 0x0000003F # macro +PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK = 0x00007FC0 # macro +PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK = 0x001F8000 # macro +PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK = 0xFFE00000 # macro +PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT = 0x0 # macro +PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT = 0x6 # macro +PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT = 0xc # macro +PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT = 0x12 # macro +PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK = 0x0000003F # macro +PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK = 0x00000FC0 # macro +PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK = 0x0003F000 # macro +PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK = 0x00FC0000 # macro +PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE__SHIFT = 0x0 # macro +PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE__SHIFT = 0xa # macro +PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN__SHIFT = 0x10 # macro +PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE__SHIFT = 0x11 # macro +PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN__SHIFT = 0x17 # macro +PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD__SHIFT = 0x1f # macro +PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE_MASK = 0x000003FF # macro +PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE_MASK = 0x0000FC00 # macro +PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN_MASK = 0x00010000 # macro +PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE_MASK = 0x007E0000 # macro +PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN_MASK = 0x00800000 # macro +PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD_MASK = 0x80000000 # macro +PA_SC_ATM_CNTL__SC_PC_IF_SIZE__SHIFT = 0x0 # macro +PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN__SHIFT = 0x7 # macro +PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT = 0x8 # macro +PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT = 0x10 # macro +PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES__SHIFT = 0x11 # macro +PA_SC_ATM_CNTL__SC_PC_IF_SIZE_MASK = 0x0000003F # macro +PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN_MASK = 0x00000080 # macro +PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK = 0x0000FF00 # macro +PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES_MASK = 0x00010000 # macro +PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES_MASK = 0x00020000 # macro +PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT = 0x0 # macro +PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK = 0x0000003F # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT = 0x0 # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT = 0x10 # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK = 0x0000FFFF # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK = 0xFFFF0000 # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK = 0xC0000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK = 0xC0000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK = 0xC0000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK = 0xC0000000 # macro +PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK = 0xFFFFFFFF # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT = 0xa # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT = 0x14 # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT = 0x17 # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK = 0x000003FF # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK = 0x000FFC00 # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK = 0x00700000 # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK = 0x03800000 # macro +PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT = 0x5 # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT = 0xa # macro +PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK = 0x0000001F # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK = 0x000003E0 # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK = 0x03FFFC00 # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT = 0xb # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK = 0x000007FF # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK = 0x003FF800 # macro +PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK = 0xFFFFFFFF # macro +PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK = 0x00000001 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK = 0x00000001 # macro +PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK = 0x00000001 # macro +PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT = 0x0 # macro +PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT = 0x10 # macro +PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK = 0x000003FF # macro +PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK = 0x003F0000 # macro +PA_PH_ENHANCE__ECO_SPARE0__SHIFT = 0x0 # macro +PA_PH_ENHANCE__ECO_SPARE1__SHIFT = 0x1 # macro +PA_PH_ENHANCE__ECO_SPARE2__SHIFT = 0x2 # macro +PA_PH_ENHANCE__ECO_SPARE3__SHIFT = 0x3 # macro +PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT = 0x4 # macro +PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT = 0x5 # macro +PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT = 0x6 # macro +PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT = 0x7 # macro +PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT = 0x9 # macro +PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT = 0xa # macro +PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT = 0xd # macro +PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS__SHIFT = 0xe # macro +PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON__SHIFT = 0xf # macro +PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE__SHIFT = 0x10 # macro +PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE__SHIFT = 0x11 # macro +PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE__SHIFT = 0x12 # macro +PA_PH_ENHANCE__ECO_SPARE0_MASK = 0x00000001 # macro +PA_PH_ENHANCE__ECO_SPARE1_MASK = 0x00000002 # macro +PA_PH_ENHANCE__ECO_SPARE2_MASK = 0x00000004 # macro +PA_PH_ENHANCE__ECO_SPARE3_MASK = 0x00000008 # macro +PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK = 0x00000010 # macro +PA_PH_ENHANCE__DISABLE_FOPKT_MASK = 0x00000020 # macro +PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK = 0x00000040 # macro +PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK = 0x00000080 # macro +PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK = 0x00000200 # macro +PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK = 0x00001C00 # macro +PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK = 0x00002000 # macro +PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS_MASK = 0x00004000 # macro +PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON_MASK = 0x00008000 # macro +PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_MASK = 0x00010000 # macro +PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE_MASK = 0x00020000 # macro +PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE_MASK = 0x00040000 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE__SHIFT = 0x0 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE__SHIFT = 0x1 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE__SHIFT = 0x2 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA__SHIFT = 0x3 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL__SHIFT = 0x4 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED__SHIFT = 0x5 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT__SHIFT = 0x6 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS__SHIFT = 0x7 # macro +PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG__SHIFT = 0x8 # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION__SHIFT = 0xc # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE__SHIFT = 0xf # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE__SHIFT = 0x13 # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING__SHIFT = 0x14 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0__SHIFT = 0x15 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1__SHIFT = 0x16 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2__SHIFT = 0x17 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3__SHIFT = 0x18 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4__SHIFT = 0x19 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5__SHIFT = 0x1a # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6__SHIFT = 0x1b # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7__SHIFT = 0x1c # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8__SHIFT = 0x1d # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9__SHIFT = 0x1e # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10__SHIFT = 0x1f # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK = 0x00000001 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE_MASK = 0x00000002 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE_MASK = 0x00000004 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA_MASK = 0x00000008 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL_MASK = 0x00000010 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED_MASK = 0x00000020 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT_MASK = 0x00000040 # macro +PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS_MASK = 0x00000080 # macro +PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG_MASK = 0x00000100 # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION_MASK = 0x00001000 # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE_MASK = 0x00008000 # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE_MASK = 0x00080000 # macro +PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING_MASK = 0x00100000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0_MASK = 0x00200000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1_MASK = 0x00400000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2_MASK = 0x00800000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3_MASK = 0x01000000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4_MASK = 0x02000000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5_MASK = 0x04000000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6_MASK = 0x08000000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7_MASK = 0x10000000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8_MASK = 0x20000000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9_MASK = 0x40000000 # macro +PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10_MASK = 0x80000000 # macro +SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT = 0x0 # macro +SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK = 0x00000001 # macro +SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT = 0x0 # macro +SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY__SHIFT = 0x1 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT = 0x4 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT = 0x10 # macro +SQ_DEBUG_STS_GLOBAL__BUSY_MASK = 0x00000001 # macro +SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY_MASK = 0x00000002 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK = 0x0000FFF0 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK = 0x0FFF0000 # macro +SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0__SHIFT = 0x0 # macro +SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1__SHIFT = 0x8 # macro +SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE__SHIFT = 0x10 # macro +SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0_MASK = 0x000000FF # macro +SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1_MASK = 0x0000FF00 # macro +SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE_MASK = 0x00FF0000 # macro +SH_MEM_BASES__PRIVATE_BASE__SHIFT = 0x0 # macro +SH_MEM_BASES__SHARED_BASE__SHIFT = 0x10 # macro +SH_MEM_BASES__PRIVATE_BASE_MASK = 0x0000FFFF # macro +SH_MEM_BASES__SHARED_BASE_MASK = 0xFFFF0000 # macro +SH_MEM_CONFIG__ADDRESS_MODE__SHIFT = 0x0 # macro +SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT = 0x2 # macro +SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT = 0xe # macro +SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT = 0x12 # macro +SH_MEM_CONFIG__ADDRESS_MODE_MASK = 0x00000001 # macro +SH_MEM_CONFIG__ALIGNMENT_MODE_MASK = 0x0000000C # macro +SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK = 0x0000C000 # macro +SH_MEM_CONFIG__ICACHE_USE_GL1_MASK = 0x00040000 # macro +SQ_DEBUG__SINGLE_MEMOP__SHIFT = 0x0 # macro +SQ_DEBUG__SINGLE_ALU_OP__SHIFT = 0x1 # macro +SQ_DEBUG__WAIT_DEP_CTR_ZERO__SHIFT = 0x2 # macro +SQ_DEBUG__SINGLE_MEMOP_MASK = 0x00000001 # macro +SQ_DEBUG__SINGLE_ALU_OP_MASK = 0x00000002 # macro +SQ_DEBUG__WAIT_DEP_CTR_ZERO_MASK = 0x00000004 # macro +SQ_SHADER_TBA_LO__ADDR_LO__SHIFT = 0x0 # macro +SQ_SHADER_TBA_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +SQ_SHADER_TBA_HI__ADDR_HI__SHIFT = 0x0 # macro +SQ_SHADER_TBA_HI__TRAP_EN__SHIFT = 0x1f # macro +SQ_SHADER_TBA_HI__ADDR_HI_MASK = 0x000000FF # macro +SQ_SHADER_TBA_HI__TRAP_EN_MASK = 0x80000000 # macro +SQ_SHADER_TMA_LO__ADDR_LO__SHIFT = 0x0 # macro +SQ_SHADER_TMA_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +SQ_SHADER_TMA_HI__ADDR_HI__SHIFT = 0x0 # macro +SQ_SHADER_TMA_HI__ADDR_HI_MASK = 0x000000FF # macro +CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE__SHIFT = 0xc # macro +CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE__SHIFT = 0xd # macro +CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE__SHIFT = 0xe # macro +CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE__SHIFT = 0xf # macro +CP_DEBUG_2__NOP_DISCARD_DISABLE__SHIFT = 0x10 # macro +CP_DEBUG_2__DC_INTERLEAVE_DISABLE__SHIFT = 0x11 # macro +CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE__SHIFT = 0x1b # macro +CP_DEBUG_2__DC_FORCE_CLK_EN__SHIFT = 0x1c # macro +CP_DEBUG_2__DC_DISABLE_BROADCAST__SHIFT = 0x1d # macro +CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE__SHIFT = 0x1e # macro +CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE__SHIFT = 0x1f # macro +CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE_MASK = 0x00001000 # macro +CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE_MASK = 0x00002000 # macro +CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE_MASK = 0x00004000 # macro +CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE_MASK = 0x00008000 # macro +CP_DEBUG_2__NOP_DISCARD_DISABLE_MASK = 0x00010000 # macro +CP_DEBUG_2__DC_INTERLEAVE_DISABLE_MASK = 0x00020000 # macro +CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE_MASK = 0x08000000 # macro +CP_DEBUG_2__DC_FORCE_CLK_EN_MASK = 0x10000000 # macro +CP_DEBUG_2__DC_DISABLE_BROADCAST_MASK = 0x20000000 # macro +CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE_MASK = 0x40000000 # macro +CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE_MASK = 0x80000000 # macro +CP_FETCHER_SOURCE__ME_SRC__SHIFT = 0x0 # macro +CP_FETCHER_SOURCE__ME_SRC_MASK = 0x00000001 # macro +CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT = 0x0 # macro +CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT = 0x8 # macro +CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT = 0x10 # macro +CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK = 0x00000007 # macro +CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK = 0x00003F00 # macro +CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK = 0x007F0000 # macro +CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT = 0x0 # macro +CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT = 0x8 # macro +CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT = 0x10 # macro +CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK = 0x00000007 # macro +CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK = 0x00003F00 # macro +CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK = 0x007F0000 # macro +CP_HPD_STATUS0__QUEUE_STATE__SHIFT = 0x0 # macro +CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT = 0x5 # macro +CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT = 0x8 # macro +CP_HPD_STATUS0__FETCHING_MQD__SHIFT = 0x10 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT = 0x11 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT = 0x12 # macro +CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT = 0x14 # macro +CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT = 0x1b # macro +CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT = 0x1c # macro +CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT = 0x1e # macro +CP_HPD_STATUS0__FORCE_QUEUE__SHIFT = 0x1f # macro +CP_HPD_STATUS0__QUEUE_STATE_MASK = 0x0000001F # macro +CP_HPD_STATUS0__MAPPED_QUEUE_MASK = 0x000000E0 # macro +CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK = 0x0000FF00 # macro +CP_HPD_STATUS0__FETCHING_MQD_MASK = 0x00010000 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK = 0x00020000 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK = 0x00040000 # macro +CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK = 0x01F00000 # macro +CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK = 0x08000000 # macro +CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK = 0x30000000 # macro +CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK = 0x40000000 # macro +CP_HPD_STATUS0__FORCE_QUEUE_MASK = 0x80000000 # macro +DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT = 0x0 # macro +DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK = 0x00000001 # macro +DIDT_EDC_CTRL__EDC_EN__SHIFT = 0x0 # macro +DIDT_EDC_CTRL__EDC_SW_RST__SHIFT = 0x1 # macro +DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT = 0x2 # macro +DIDT_EDC_CTRL__EDC_FORCE_STALL__SHIFT = 0x3 # macro +DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT = 0x4 # macro +DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT = 0xa # macro +DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT = 0xe # macro +DIDT_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT = 0xf # macro +DIDT_EDC_CTRL__EDC_AVGDIV__SHIFT = 0x10 # macro +DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL__SHIFT = 0x14 # macro +DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS__SHIFT = 0x15 # macro +DIDT_EDC_CTRL__RLC_FORCE_STALL_EN__SHIFT = 0x18 # macro +DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL__SHIFT = 0x19 # macro +DIDT_EDC_CTRL__EDC_EN_MASK = 0x00000001 # macro +DIDT_EDC_CTRL__EDC_SW_RST_MASK = 0x00000002 # macro +DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK = 0x00000004 # macro +DIDT_EDC_CTRL__EDC_FORCE_STALL_MASK = 0x00000008 # macro +DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK = 0x000003F0 # macro +DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK = 0x00003C00 # macro +DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK = 0x00004000 # macro +DIDT_EDC_CTRL__EDC_ALGORITHM_MODE_MASK = 0x00008000 # macro +DIDT_EDC_CTRL__EDC_AVGDIV_MASK = 0x000F0000 # macro +DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL_MASK = 0x00100000 # macro +DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS_MASK = 0x00E00000 # macro +DIDT_EDC_CTRL__RLC_FORCE_STALL_EN_MASK = 0x01000000 # macro +DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL_MASK = 0x02000000 # macro +DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN__SHIFT = 0x0 # macro +DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN__SHIFT = 0x1 # macro +DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN__SHIFT = 0x2 # macro +DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN__SHIFT = 0x3 # macro +DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN__SHIFT = 0x4 # macro +DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE__SHIFT = 0x5 # macro +DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN_MASK = 0x00000001 # macro +DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN_MASK = 0x00000002 # macro +DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN_MASK = 0x00000004 # macro +DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN_MASK = 0x00000008 # macro +DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN_MASK = 0x00000010 # macro +DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE_MASK = 0x000000E0 # macro +DIDT_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT = 0x0 # macro +DIDT_EDC_THRESHOLD__EDC_THRESHOLD_MASK = 0xFFFFFFFF # macro +DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT = 0x0 # macro +DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT = 0x10 # macro +DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK = 0x00007FFF # macro +DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK = 0x7FFF0000 # macro +DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT = 0x0 # macro +DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT = 0x10 # macro +DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK = 0x00007FFF # macro +DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK = 0x7FFF0000 # macro +DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT = 0x0 # macro +DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT = 0x10 # macro +DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK = 0x00007FFF # macro +DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK = 0x7FFF0000 # macro +DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT = 0x0 # macro +DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK = 0x00007FFF # macro +DIDT_EDC_STATUS__EDC_FSM_STATE__SHIFT = 0x0 # macro +DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT = 0x1 # macro +DIDT_EDC_STATUS__EDC_FSM_STATE_MASK = 0x00000001 # macro +DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK = 0x0000000E # macro +DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO__SHIFT = 0x0 # macro +DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO_MASK = 0x00000001 # macro +DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT = 0x0 # macro +DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT = 0x1 # macro +DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK = 0x00000001 # macro +DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK = 0x0001FFFE # macro +DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT = 0x0 # macro +DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK = 0xFFFFFFFF # macro +DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT = 0x0 # macro +DIDT_IND_INDEX__DIDT_IND_INDEX_MASK = 0xFFFFFFFF # macro +DIDT_IND_DATA__DIDT_IND_DATA__SHIFT = 0x0 # macro +DIDT_IND_DATA__DIDT_IND_DATA_MASK = 0xFFFFFFFF # macro +SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT = 0x0 # macro +SPI_GDBG_WAVE_CNTL__STALL_LAUNCH__SHIFT = 0x1 # macro +SPI_GDBG_WAVE_CNTL__STALL_RA_MASK = 0x00000001 # macro +SPI_GDBG_WAVE_CNTL__STALL_LAUNCH_MASK = 0x00000002 # macro +SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT = 0x0 # macro +SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT = 0x8 # macro +SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT = 0x10 # macro +SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT = 0x18 # macro +SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK = 0x000000FF # macro +SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK = 0x0000FF00 # macro +SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK = 0x00FF0000 # macro +SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK = 0xFF000000 # macro +SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT = 0x0 # macro +SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT = 0x2 # macro +SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT = 0x3 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT = 0x4 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT = 0x5 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT = 0x6 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT = 0x7 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT = 0x8 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT = 0x9 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT = 0xa # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT = 0xb # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT = 0xc # macro +SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT = 0xd # macro +SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT = 0x1c # macro +SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK = 0x00000001 # macro +SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK = 0x00000004 # macro +SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK = 0x00000008 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK = 0x00000010 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK = 0x00000020 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK = 0x00000040 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK = 0x00000080 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK = 0x00000100 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK = 0x00000200 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK = 0x00000400 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK = 0x00000800 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK = 0x00001000 # macro +SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK = 0x0FFFE000 # macro +SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK = 0x10000000 # macro +SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT = 0x0 # macro +SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT = 0x4 # macro +SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT = 0x8 # macro +SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK = 0x0000000F # macro +SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK = 0x000000F0 # macro +SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK = 0x00000F00 # macro +SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT = 0x0 # macro +SPI_FEATURE_CTRL__RA_PROBE_IGNORE__SHIFT = 0x4 # macro +SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT__SHIFT = 0x5 # macro +SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL__SHIFT = 0xb # macro +SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL__SHIFT = 0xd # macro +SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE__SHIFT = 0xe # macro +SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK = 0x0000000F # macro +SPI_FEATURE_CTRL__RA_PROBE_IGNORE_MASK = 0x00000010 # macro +SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT_MASK = 0x000007E0 # macro +SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL_MASK = 0x00001800 # macro +SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL_MASK = 0x00002000 # macro +SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE_MASK = 0x00004000 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT = 0x0 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT = 0x5 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT = 0xc # macro +SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT = 0xd # macro +SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT = 0x13 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT = 0x14 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT = 0x1c # macro +SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT = 0x1f # macro +SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK = 0x0000001F # macro +SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK = 0x00000FE0 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK = 0x00001000 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK = 0x0007E000 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK = 0x00080000 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK = 0x0FF00000 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK = 0x10000000 # macro +SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK = 0x80000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY__SHIFT = 0x0 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY__SHIFT = 0x1 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY__SHIFT = 0x2 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY__SHIFT = 0x3 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY__SHIFT = 0x4 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY__SHIFT = 0x5 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY__SHIFT = 0x6 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY__SHIFT = 0x7 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY__SHIFT = 0x8 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY__SHIFT = 0x9 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY__SHIFT = 0xa # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY__SHIFT = 0xb # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY__SHIFT = 0xc # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY__SHIFT = 0xd # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY__SHIFT = 0xe # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY__SHIFT = 0xf # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY__SHIFT = 0x10 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY__SHIFT = 0x11 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY__SHIFT = 0x12 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY__SHIFT = 0x13 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY__SHIFT = 0x14 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY__SHIFT = 0x15 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY__SHIFT = 0x16 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY__SHIFT = 0x17 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY__SHIFT = 0x18 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY__SHIFT = 0x19 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY__SHIFT = 0x1a # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY__SHIFT = 0x1b # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY__SHIFT = 0x1c # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY__SHIFT = 0x1d # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY__SHIFT = 0x1e # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY__SHIFT = 0x1f # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY_MASK = 0x00000001 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY_MASK = 0x00000002 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY_MASK = 0x00000004 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY_MASK = 0x00000008 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY_MASK = 0x00000010 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY_MASK = 0x00000020 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY_MASK = 0x00000040 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY_MASK = 0x00000080 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY_MASK = 0x00000100 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY_MASK = 0x00000200 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY_MASK = 0x00000400 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY_MASK = 0x00000800 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY_MASK = 0x00001000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY_MASK = 0x00002000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY_MASK = 0x00004000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY_MASK = 0x00008000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY_MASK = 0x00010000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY_MASK = 0x00020000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY_MASK = 0x00040000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY_MASK = 0x00080000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY_MASK = 0x00100000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY_MASK = 0x00200000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY_MASK = 0x00400000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY_MASK = 0x00800000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY_MASK = 0x01000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY_MASK = 0x02000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY_MASK = 0x04000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY_MASK = 0x08000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY_MASK = 0x10000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY_MASK = 0x20000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY_MASK = 0x40000000 # macro +SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY_MASK = 0x80000000 # macro +TCP_INVALIDATE__START__SHIFT = 0x0 # macro +TCP_INVALIDATE__START_MASK = 0x00000001 # macro +TCP_STATUS__TCP_BUSY__SHIFT = 0x0 # macro +TCP_STATUS__INPUT_BUSY__SHIFT = 0x1 # macro +TCP_STATUS__ADRS_BUSY__SHIFT = 0x2 # macro +TCP_STATUS__TAGRAMS_BUSY__SHIFT = 0x3 # macro +TCP_STATUS__CNTRL_BUSY__SHIFT = 0x4 # macro +TCP_STATUS__LFIFO_BUSY__SHIFT = 0x5 # macro +TCP_STATUS__READ_BUSY__SHIFT = 0x6 # macro +TCP_STATUS__FORMAT_BUSY__SHIFT = 0x7 # macro +TCP_STATUS__VM_BUSY__SHIFT = 0x8 # macro +TCP_STATUS__MEMIF_BUSY__SHIFT = 0x9 # macro +TCP_STATUS__GCR_BUSY__SHIFT = 0xa # macro +TCP_STATUS__OFIFO_BUSY__SHIFT = 0xb # macro +TCP_STATUS__OFIFO_QUEUE_BUSY__SHIFT = 0xc # macro +TCP_STATUS__XNACK_PRT__SHIFT = 0xf # macro +TCP_STATUS__TCP_BUSY_MASK = 0x00000001 # macro +TCP_STATUS__INPUT_BUSY_MASK = 0x00000002 # macro +TCP_STATUS__ADRS_BUSY_MASK = 0x00000004 # macro +TCP_STATUS__TAGRAMS_BUSY_MASK = 0x00000008 # macro +TCP_STATUS__CNTRL_BUSY_MASK = 0x00000010 # macro +TCP_STATUS__LFIFO_BUSY_MASK = 0x00000020 # macro +TCP_STATUS__READ_BUSY_MASK = 0x00000040 # macro +TCP_STATUS__FORMAT_BUSY_MASK = 0x00000080 # macro +TCP_STATUS__VM_BUSY_MASK = 0x00000100 # macro +TCP_STATUS__MEMIF_BUSY_MASK = 0x00000200 # macro +TCP_STATUS__GCR_BUSY_MASK = 0x00000400 # macro +TCP_STATUS__OFIFO_BUSY_MASK = 0x00000800 # macro +TCP_STATUS__OFIFO_QUEUE_BUSY_MASK = 0x00003000 # macro +TCP_STATUS__XNACK_PRT_MASK = 0x00008000 # macro +TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT = 0x0 # macro +TCP_CNTL2__TCP_FMT_MGCG_DISABLE__SHIFT = 0x8 # macro +TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT = 0x9 # macro +TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE__SHIFT = 0xa # macro +TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE__SHIFT = 0xb # macro +TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT = 0xc # macro +TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT = 0xd # macro +TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT = 0xe # macro +TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT = 0xf # macro +TCP_CNTL2__POWER_OPT_DISABLE__SHIFT = 0x10 # macro +TCP_CNTL2__GCR_RSP_FGCG_DISABLE__SHIFT = 0x11 # macro +TCP_CNTL2__PERF_EN_OVERRIDE__SHIFT = 0x12 # macro +TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE__SHIFT = 0x14 # macro +TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE__SHIFT = 0x15 # macro +TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE__SHIFT = 0x16 # macro +TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE__SHIFT = 0x17 # macro +TCP_CNTL2__SPARE_BIT__SHIFT = 0x1a # macro +TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE__SHIFT = 0x1b # macro +TCP_CNTL2__TCP_REQ_MGCG_DISABLE__SHIFT = 0x1d # macro +TCP_CNTL2__TCP_MISS_MGCG_DISABLE__SHIFT = 0x1e # macro +TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING__SHIFT = 0x1f # macro +TCP_CNTL2__LS_DISABLE_CLOCKS_MASK = 0x000000FF # macro +TCP_CNTL2__TCP_FMT_MGCG_DISABLE_MASK = 0x00000100 # macro +TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK = 0x00000200 # macro +TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE_MASK = 0x00000400 # macro +TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE_MASK = 0x00000800 # macro +TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE_MASK = 0x00001000 # macro +TCP_CNTL2__V64_COMBINE_ENABLE_MASK = 0x00002000 # macro +TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK = 0x00004000 # macro +TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK = 0x00008000 # macro +TCP_CNTL2__POWER_OPT_DISABLE_MASK = 0x00010000 # macro +TCP_CNTL2__GCR_RSP_FGCG_DISABLE_MASK = 0x00020000 # macro +TCP_CNTL2__PERF_EN_OVERRIDE_MASK = 0x000C0000 # macro +TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE_MASK = 0x00100000 # macro +TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE_MASK = 0x00200000 # macro +TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE_MASK = 0x00400000 # macro +TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE_MASK = 0x00800000 # macro +TCP_CNTL2__SPARE_BIT_MASK = 0x04000000 # macro +TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE_MASK = 0x18000000 # macro +TCP_CNTL2__TCP_REQ_MGCG_DISABLE_MASK = 0x20000000 # macro +TCP_CNTL2__TCP_MISS_MGCG_DISABLE_MASK = 0x40000000 # macro +TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING_MASK = 0x80000000 # macro +TCP_DEBUG_INDEX__INDEX__SHIFT = 0x0 # macro +TCP_DEBUG_INDEX__INDEX_MASK = 0x0000001F # macro +TCP_DEBUG_DATA__DATA__SHIFT = 0x0 # macro +TCP_DEBUG_DATA__DATA_MASK = 0x0003FFFF # macro +GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT__SHIFT = 0x0 # macro +GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE__SHIFT = 0x1 # macro +GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT__SHIFT = 0x2 # macro +GDS_ENHANCE2__UNUSED__SHIFT = 0x3 # macro +GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT_MASK = 0x00000001 # macro +GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE_MASK = 0x00000002 # macro +GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT_MASK = 0x00000004 # macro +GDS_ENHANCE2__UNUSED_MASK = 0xFFFFFFF8 # macro +GDS_OA_CGPG_RESTORE__VMID__SHIFT = 0x0 # macro +GDS_OA_CGPG_RESTORE__MEID__SHIFT = 0x8 # macro +GDS_OA_CGPG_RESTORE__PIPEID__SHIFT = 0xc # macro +GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT = 0x10 # macro +GDS_OA_CGPG_RESTORE__UNUSED__SHIFT = 0x14 # macro +GDS_OA_CGPG_RESTORE__VMID_MASK = 0x000000FF # macro +GDS_OA_CGPG_RESTORE__MEID_MASK = 0x00000F00 # macro +GDS_OA_CGPG_RESTORE__PIPEID_MASK = 0x0000F000 # macro +GDS_OA_CGPG_RESTORE__QUEUEID_MASK = 0x000F0000 # macro +GDS_OA_CGPG_RESTORE__UNUSED_MASK = 0xFFF00000 # macro +UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE__SHIFT = 0x0 # macro +UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE__SHIFT = 0x1 # macro +UTCL1_CTRL_0__RESERVED_0__SHIFT = 0x2 # macro +UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS__SHIFT = 0x3 # macro +UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS__SHIFT = 0x9 # macro +UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE__SHIFT = 0xd # macro +UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE__SHIFT = 0xe # macro +UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT = 0xf # macro +UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID__SHIFT = 0x10 # macro +UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT = 0x11 # macro +UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT = 0x12 # macro +UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT = 0x13 # macro +UTCL1_CTRL_0__GCRD_FGCG_DISABLE__SHIFT = 0x14 # macro +UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE__SHIFT = 0x15 # macro +UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES__SHIFT = 0x16 # macro +UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT = 0x17 # macro +UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT = 0x18 # macro +UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL__SHIFT = 0x19 # macro +UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE__SHIFT = 0x1b # macro +UTCL1_CTRL_0__RESERVED_1__SHIFT = 0x1d # macro +UTCL1_CTRL_0__MH_SPARE0__SHIFT = 0x1e # macro +UTCL1_CTRL_0__RESERVED_2__SHIFT = 0x1f # macro +UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE_MASK = 0x00000001 # macro +UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE_MASK = 0x00000002 # macro +UTCL1_CTRL_0__RESERVED_0_MASK = 0x00000004 # macro +UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_MASK = 0x000001F8 # macro +UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS_MASK = 0x00001E00 # macro +UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE_MASK = 0x00002000 # macro +UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE_MASK = 0x00004000 # macro +UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK = 0x00008000 # macro +UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID_MASK = 0x00010000 # macro +UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK = 0x00020000 # macro +UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK = 0x00040000 # macro +UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK = 0x00080000 # macro +UTCL1_CTRL_0__GCRD_FGCG_DISABLE_MASK = 0x00100000 # macro +UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE_MASK = 0x00200000 # macro +UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES_MASK = 0x00400000 # macro +UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK = 0x00800000 # macro +UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK = 0x01000000 # macro +UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL_MASK = 0x06000000 # macro +UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE_MASK = 0x18000000 # macro +UTCL1_CTRL_0__RESERVED_1_MASK = 0x20000000 # macro +UTCL1_CTRL_0__MH_SPARE0_MASK = 0x40000000 # macro +UTCL1_CTRL_0__RESERVED_2_MASK = 0x80000000 # macro +UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT = 0x0 # macro +UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK = 0xFFFFFFFF # macro +UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD__SHIFT = 0x0 # macro +UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE__SHIFT = 0x4 # macro +UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM__SHIFT = 0xa # macro +UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE__SHIFT = 0xb # macro +UTCL1_CTRL_2__UTCL1_SPARE0__SHIFT = 0xc # macro +UTCL1_CTRL_2__UTCL1_SPARE1__SHIFT = 0xd # macro +UTCL1_CTRL_2__RESERVED__SHIFT = 0xe # macro +UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD_MASK = 0x0000000F # macro +UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE_MASK = 0x000003F0 # macro +UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM_MASK = 0x00000400 # macro +UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE_MASK = 0x00000800 # macro +UTCL1_CTRL_2__UTCL1_SPARE0_MASK = 0x00001000 # macro +UTCL1_CTRL_2__UTCL1_SPARE1_MASK = 0x00002000 # macro +UTCL1_CTRL_2__RESERVED_MASK = 0xFFFFC000 # macro +UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH__SHIFT = 0x0 # macro +UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW__SHIFT = 0x3 # macro +UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH__SHIFT = 0x10 # macro +UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH_MASK = 0x00000007 # macro +UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW_MASK = 0x0000FFF8 # macro +UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH_MASK = 0xFFFF0000 # macro +GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE__SHIFT = 0x0 # macro +GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE_MASK = 0x0007FFFF # macro +GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE__SHIFT = 0x0 # macro +GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE_MASK = 0x0007FFFF # macro +GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG__SHIFT = 0x0 # macro +GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG__SHIFT = 0x4 # macro +GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG_MASK = 0x00000007 # macro +GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG_MASK = 0x00000070 # macro +GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT = 0x1 # macro +GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT = 0x2 # macro +GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT = 0x3 # macro +GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT = 0x4 # macro +GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT = 0x6 # macro +GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT = 0x7 # macro +GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT = 0x8 # macro +GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT = 0x9 # macro +GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT = 0xa # macro +GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT = 0xd # macro +GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT = 0xe # macro +GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT = 0xf # macro +GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT = 0x10 # macro +GCR_GENERAL_CNTL__CLIENT_ID__SHIFT = 0x14 # macro +GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK = 0x00000002 # macro +GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK = 0x00000004 # macro +GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK = 0x00000008 # macro +GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK = 0x00000030 # macro +GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK = 0x00000040 # macro +GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK = 0x00000080 # macro +GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK = 0x00000100 # macro +GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK = 0x00000200 # macro +GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK = 0x00001C00 # macro +GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK = 0x00002000 # macro +GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK = 0x00004000 # macro +GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK = 0x00008000 # macro +GCR_GENERAL_CNTL__DISABLE_FGCG_MASK = 0x00010000 # macro +GCR_GENERAL_CNTL__CLIENT_ID_MASK = 0x1FF00000 # macro +GCR_CMD_STATUS__GCR_CONTROL__SHIFT = 0x0 # macro +GCR_CMD_STATUS__GCR_SRC__SHIFT = 0x13 # macro +GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT = 0x17 # macro +GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT = 0x18 # macro +GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT = 0x1c # macro +GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT = 0x1e # macro +GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT = 0x1f # macro +GCR_CMD_STATUS__GCR_CONTROL_MASK = 0x0007FFFF # macro +GCR_CMD_STATUS__GCR_SRC_MASK = 0x00380000 # macro +GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK = 0x00800000 # macro +GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK = 0x0F000000 # macro +GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK = 0x30000000 # macro +GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK = 0x40000000 # macro +GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK = 0x80000000 # macro +GCR_SPARE__SPARE_BIT_1__SHIFT = 0x1 # macro +GCR_SPARE__SPARE_BIT_2__SHIFT = 0x2 # macro +GCR_SPARE__SPARE_BIT_3__SHIFT = 0x3 # macro +GCR_SPARE__SPARE_BIT_4__SHIFT = 0x4 # macro +GCR_SPARE__SPARE_BIT_5__SHIFT = 0x5 # macro +GCR_SPARE__SPARE_BIT_6__SHIFT = 0x6 # macro +GCR_SPARE__SPARE_BIT_7__SHIFT = 0x7 # macro +GCR_SPARE__UTCL2_REQ_CREDIT__SHIFT = 0x8 # macro +GCR_SPARE__GCRD_GL2A_REQ_CREDIT__SHIFT = 0x10 # macro +GCR_SPARE__GCRD_SE_REQ_CREDIT__SHIFT = 0x14 # macro +GCR_SPARE__SPARE_BIT_31_24__SHIFT = 0x18 # macro +GCR_SPARE__SPARE_BIT_1_MASK = 0x00000002 # macro +GCR_SPARE__SPARE_BIT_2_MASK = 0x00000004 # macro +GCR_SPARE__SPARE_BIT_3_MASK = 0x00000008 # macro +GCR_SPARE__SPARE_BIT_4_MASK = 0x00000010 # macro +GCR_SPARE__SPARE_BIT_5_MASK = 0x00000020 # macro +GCR_SPARE__SPARE_BIT_6_MASK = 0x00000040 # macro +GCR_SPARE__SPARE_BIT_7_MASK = 0x00000080 # macro +GCR_SPARE__UTCL2_REQ_CREDIT_MASK = 0x0000FF00 # macro +GCR_SPARE__GCRD_GL2A_REQ_CREDIT_MASK = 0x000F0000 # macro +GCR_SPARE__GCRD_SE_REQ_CREDIT_MASK = 0x00F00000 # macro +GCR_SPARE__SPARE_BIT_31_24_MASK = 0xFF000000 # macro +PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE__SHIFT = 0x18 # macro +PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE__SHIFT = 0x19 # macro +PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE__SHIFT = 0x1a # macro +PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE__SHIFT = 0x1e # macro +PMM_CNTL2__RESERVED__SHIFT = 0x1f # macro +PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE_MASK = 0x01000000 # macro +PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE_MASK = 0x02000000 # macro +PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE_MASK = 0x3C000000 # macro +PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE_MASK = 0x40000000 # macro +PMM_CNTL2__RESERVED_MASK = 0x80000000 # macro +SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_REQ_CREDITS__SHIFT = 0x0 # macro +SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_DATA_CREDITS__SHIFT = 0x8 # macro +SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_OUT_CLK_OVERRIDE__SHIFT = 0x10 # macro +SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_REQ_CREDITS_MASK = 0x0000003F # macro +SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_DATA_CREDITS_MASK = 0x00003F00 # macro +SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_OUT_CLK_OVERRIDE_MASK = 0x00010000 # macro +GC_CAC_CTRL_1__CAC_WINDOW__SHIFT = 0x0 # macro +GC_CAC_CTRL_1__TDP_WINDOW__SHIFT = 0x8 # macro +GC_CAC_CTRL_1__CAC_WINDOW_MASK = 0x000000FF # macro +GC_CAC_CTRL_1__TDP_WINDOW_MASK = 0xFFFFFF00 # macro +GC_CAC_CTRL_2__CAC_ENABLE__SHIFT = 0x0 # macro +GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT = 0x1 # macro +GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT = 0x2 # macro +GC_CAC_CTRL_2__TOGGLE_EN__SHIFT = 0x3 # macro +GC_CAC_CTRL_2__INTR_EN__SHIFT = 0x4 # macro +GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL__SHIFT = 0x5 # macro +GC_CAC_CTRL_2__SE_AGGR_ACC_EN__SHIFT = 0x6 # macro +GC_CAC_CTRL_2__GC_AGGR_ACC_EN__SHIFT = 0xe # macro +GC_CAC_CTRL_2__CAC_ENABLE_MASK = 0x00000001 # macro +GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK = 0x00000002 # macro +GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK = 0x00000004 # macro +GC_CAC_CTRL_2__TOGGLE_EN_MASK = 0x00000008 # macro +GC_CAC_CTRL_2__INTR_EN_MASK = 0x00000010 # macro +GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL_MASK = 0x00000020 # macro +GC_CAC_CTRL_2__SE_AGGR_ACC_EN_MASK = 0x00003FC0 # macro +GC_CAC_CTRL_2__GC_AGGR_ACC_EN_MASK = 0x00004000 # macro +GC_CAC_AGGR_LOWER__GC_AGGR_31_0__SHIFT = 0x0 # macro +GC_CAC_AGGR_LOWER__GC_AGGR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_AGGR_UPPER__GC_AGGR_63_32__SHIFT = 0x0 # macro +GC_CAC_AGGR_UPPER__GC_AGGR_63_32_MASK = 0xFFFFFFFF # macro +SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0__SHIFT = 0x0 # macro +SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0_MASK = 0xFFFFFFFF # macro +SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32__SHIFT = 0x0 # macro +SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32_MASK = 0xFFFFFFFF # macro +SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0__SHIFT = 0x0 # macro +SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0_MASK = 0xFFFFFFFF # macro +SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32__SHIFT = 0x0 # macro +SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32_MASK = 0xFFFFFFFF # macro +SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0__SHIFT = 0x0 # macro +SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0_MASK = 0xFFFFFFFF # macro +SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32__SHIFT = 0x0 # macro +SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32_MASK = 0xFFFFFFFF # macro +SE3_CAC_AGGR_LOWER__SE3_AGGR_31_0__SHIFT = 0x0 # macro +SE3_CAC_AGGR_LOWER__SE3_AGGR_31_0_MASK = 0xFFFFFFFF # macro +SE3_CAC_AGGR_UPPER__SE3_AGGR_63_32__SHIFT = 0x0 # macro +SE3_CAC_AGGR_UPPER__SE3_AGGR_63_32_MASK = 0xFFFFFFFF # macro +SE4_CAC_AGGR_LOWER__SE4_AGGR_31_0__SHIFT = 0x0 # macro +SE4_CAC_AGGR_LOWER__SE4_AGGR_31_0_MASK = 0xFFFFFFFF # macro +SE4_CAC_AGGR_UPPER__SE4_AGGR_63_32__SHIFT = 0x0 # macro +SE4_CAC_AGGR_UPPER__SE4_AGGR_63_32_MASK = 0xFFFFFFFF # macro +SE5_CAC_AGGR_LOWER__SE5_AGGR_31_0__SHIFT = 0x0 # macro +SE5_CAC_AGGR_LOWER__SE5_AGGR_31_0_MASK = 0xFFFFFFFF # macro +SE5_CAC_AGGR_UPPER__SE5_AGGR_63_32__SHIFT = 0x0 # macro +SE5_CAC_AGGR_UPPER__SE5_AGGR_63_32_MASK = 0xFFFFFFFF # macro +GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE__SHIFT = 0x0 # macro +GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE_MASK = 0xFFFFFFFF # macro +SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE__SHIFT = 0x0 # macro +SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE_MASK = 0xFFFFFFFF # macro +SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE__SHIFT = 0x0 # macro +SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE_MASK = 0xFFFFFFFF # macro +SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE__SHIFT = 0x0 # macro +SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE_MASK = 0xFFFFFFFF # macro +SE3_CAC_AGGR_GFXCLK_CYCLE__SE3_AGGR_GFXCLK_CYCLE__SHIFT = 0x0 # macro +SE3_CAC_AGGR_GFXCLK_CYCLE__SE3_AGGR_GFXCLK_CYCLE_MASK = 0xFFFFFFFF # macro +SE4_CAC_AGGR_GFXCLK_CYCLE__SE4_AGGR_GFXCLK_CYCLE__SHIFT = 0x0 # macro +SE4_CAC_AGGR_GFXCLK_CYCLE__SE4_AGGR_GFXCLK_CYCLE_MASK = 0xFFFFFFFF # macro +SE5_CAC_AGGR_GFXCLK_CYCLE__SE5_AGGR_GFXCLK_CYCLE__SHIFT = 0x0 # macro +SE5_CAC_AGGR_GFXCLK_CYCLE__SE5_AGGR_GFXCLK_CYCLE_MASK = 0xFFFFFFFF # macro +GC_EDC_CTRL__EDC_EN__SHIFT = 0x0 # macro +GC_EDC_CTRL__EDC_SW_RST__SHIFT = 0x1 # macro +GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT = 0x2 # macro +GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT = 0x3 # macro +GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT = 0x4 # macro +GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT = 0xa # macro +GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT = 0xb # macro +GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT = 0xf # macro +GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT = 0x10 # macro +GC_EDC_CTRL__EDC_AVGDIV__SHIFT = 0x11 # macro +GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT = 0x15 # macro +GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT = 0x18 # macro +GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT = 0x19 # macro +GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT = 0x1a # macro +GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT = 0x1b # macro +GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS__SHIFT = 0x1c # macro +GC_EDC_CTRL__EDC_EN_MASK = 0x00000001 # macro +GC_EDC_CTRL__EDC_SW_RST_MASK = 0x00000002 # macro +GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK = 0x00000004 # macro +GC_EDC_CTRL__EDC_FORCE_STALL_MASK = 0x00000008 # macro +GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK = 0x000003F0 # macro +GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK = 0x00000400 # macro +GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK = 0x00007800 # macro +GC_EDC_CTRL__EDC_LEVEL_SEL_MASK = 0x00008000 # macro +GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK = 0x00010000 # macro +GC_EDC_CTRL__EDC_AVGDIV_MASK = 0x001E0000 # macro +GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK = 0x00E00000 # macro +GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK = 0x01000000 # macro +GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK = 0x02000000 # macro +GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK = 0x04000000 # macro +GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK = 0x08000000 # macro +GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS_MASK = 0xF0000000 # macro +GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT = 0x0 # macro +GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK = 0xFFFFFFFF # macro +GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT = 0x0 # macro +GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT = 0x1 # macro +GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT = 0xa # macro +GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK = 0x00000001 # macro +GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK = 0x000003FE # macro +GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK = 0x0007FC00 # macro +GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT = 0x0 # macro +GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK = 0xFFFFFFFF # macro +EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT = 0x0 # macro +EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER__SHIFT = 0x8 # macro +EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN__SHIFT = 0x10 # macro +EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE__SHIFT = 0x11 # macro +EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE__SHIFT = 0x14 # macro +EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK = 0x000000FF # macro +EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER_MASK = 0x0000FF00 # macro +EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN_MASK = 0x00010000 # macro +EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE_MASK = 0x000E0000 # macro +EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE_MASK = 0x00100000 # macro +GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT = 0x0 # macro +GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT = 0x1 # macro +GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT = 0x2 # macro +GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT = 0x3 # macro +GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT = 0x4 # macro +GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT = 0x5 # macro +GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT = 0x6 # macro +GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT = 0x7 # macro +GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT = 0x8 # macro +GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT = 0x9 # macro +GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT = 0xa # macro +GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT = 0xb # macro +GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT = 0xc # macro +GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT = 0xd # macro +GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT = 0x17 # macro +GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT = 0x18 # macro +GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT = 0x1d # macro +GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT = 0x1e # macro +GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT = 0x1f # macro +GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK = 0x00000001 # macro +GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK = 0x00000002 # macro +GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK = 0x00000004 # macro +GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK = 0x00000008 # macro +GC_THROTTLE_CTRL__PCC_STALL_EN_MASK = 0x00000010 # macro +GC_THROTTLE_CTRL__PATTERN_MODE_MASK = 0x00000020 # macro +GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK = 0x00000040 # macro +GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK = 0x00000080 # macro +GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK = 0x00000100 # macro +GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK = 0x00000200 # macro +GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK = 0x00000400 # macro +GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK = 0x00000800 # macro +GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK = 0x00001000 # macro +GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK = 0x007FE000 # macro +GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK = 0x00800000 # macro +GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK = 0x1F000000 # macro +GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK = 0x20000000 # macro +GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK = 0x40000000 # macro +GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK = 0x80000000 # macro +GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT = 0x0 # macro +GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT = 0x1 # macro +GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT = 0x5 # macro +GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT = 0xa # macro +GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT = 0xd # macro +GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT = 0xe # macro +GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT = 0x12 # macro +GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT = 0x17 # macro +GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT = 0x1a # macro +GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT = 0x1e # macro +GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT = 0x1f # macro +GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK = 0x00000001 # macro +GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK = 0x0000001E # macro +GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK = 0x000003E0 # macro +GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK = 0x00001C00 # macro +GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK = 0x00002000 # macro +GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK = 0x0003C000 # macro +GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK = 0x007C0000 # macro +GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK = 0x03800000 # macro +GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK = 0x0C000000 # macro +GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK = 0x40000000 # macro +GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK = 0x80000000 # macro +PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT = 0x0 # macro +PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT = 0xa # macro +PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT = 0xf # macro +PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT = 0x14 # macro +PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT = 0x18 # macro +PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT = 0x19 # macro +PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT = 0x1a # macro +PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK = 0x000003FF # macro +PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK = 0x00007C00 # macro +PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK = 0x000F8000 # macro +PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK = 0x00F00000 # macro +PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK = 0x01000000 # macro +PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK = 0x02000000 # macro +PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK = 0x04000000 # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT = 0x0 # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT = 0xa # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT = 0xf # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT = 0x14 # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK = 0x000003FF # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK = 0x00007C00 # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK = 0x000F8000 # macro +PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK = 0x00F00000 # macro +PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT = 0x0 # macro +PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT = 0x10 # macro +PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK = 0x00007FFF # macro +PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK = 0x7FFF0000 # macro +PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT = 0x0 # macro +PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT = 0x10 # macro +PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK = 0x00007FFF # macro +PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK = 0x7FFF0000 # macro +PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT = 0x0 # macro +PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT = 0x10 # macro +PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK = 0x00007FFF # macro +PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK = 0x7FFF0000 # macro +PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT = 0x0 # macro +PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK = 0x00007FFF # macro +PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT = 0x0 # macro +PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT = 0x10 # macro +PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK = 0x00007FFF # macro +PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK = 0x7FFF0000 # macro +PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT = 0x0 # macro +PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT = 0x10 # macro +PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK = 0x00007FFF # macro +PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK = 0x7FFF0000 # macro +PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT = 0x0 # macro +PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT = 0x10 # macro +PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK = 0x00007FFF # macro +PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK = 0x7FFF0000 # macro +PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT = 0x0 # macro +PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK = 0x00007FFF # macro +DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN__SHIFT = 0x0 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST__SHIFT = 0x1 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE__SHIFT = 0x2 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT = 0x3 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN__SHIFT = 0x7 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE__SHIFT = 0x8 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN_MASK = 0x00000001 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST_MASK = 0x00000002 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE_MASK = 0x00000004 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS_MASK = 0x00000078 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN_MASK = 0x00000080 # macro +DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE_MASK = 0x00000700 # macro +DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT = 0x0 # macro +DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT = 0x10 # macro +DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK = 0x00007FFF # macro +DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK = 0x7FFF0000 # macro +DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT = 0x0 # macro +DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT = 0x10 # macro +DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK = 0x00007FFF # macro +DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK = 0x7FFF0000 # macro +DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT = 0x0 # macro +DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT = 0x10 # macro +DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK = 0x00007FFF # macro +DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK = 0x7FFF0000 # macro +DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT = 0x0 # macro +DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK = 0x00007FFF # macro +PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT = 0x0 # macro +PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT = 0x8 # macro +PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK = 0x000000FF # macro +PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK = 0x0000FF00 # macro +EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT = 0x0 # macro +EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK = 0xFFFFFFFF # macro +EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT = 0x0 # macro +EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK = 0xFFFFFFFF # macro +EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT = 0x0 # macro +EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK = 0xFFFFFFFF # macro +GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT = 0x0 # macro +GC_EDC_STATUS__GPIO_IN_0__SHIFT = 0x3 # macro +GC_EDC_STATUS__GPIO_IN_1__SHIFT = 0x4 # macro +GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK = 0x00000007 # macro +GC_EDC_STATUS__GPIO_IN_0_MASK = 0x00000008 # macro +GC_EDC_STATUS__GPIO_IN_1_MASK = 0x00000010 # macro +GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT = 0x0 # macro +GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT = 0x1 # macro +GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK = 0x00000001 # macro +GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK = 0x0001FFFE # macro +GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT = 0x0 # macro +GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK = 0xFFFFFFFF # macro +GC_THROTTLE_STATUS__FSM_STATE__SHIFT = 0x0 # macro +GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT = 0x4 # macro +GC_THROTTLE_STATUS__FSM_STATE_MASK = 0x0000000F # macro +GC_THROTTLE_STATUS__PATTERN_INDEX_MASK = 0x000001F0 # macro +EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT = 0x0 # macro +EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK = 0xFFFFFFFF # macro +PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT = 0x0 # macro +PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK = 0xFFFFFFFF # macro +PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT = 0x0 # macro +PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK = 0xFFFFFFFF # macro +EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT = 0x0 # macro +EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT = 0x8 # macro +EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW__SHIFT = 0x9 # macro +EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL__SHIFT = 0xa # macro +EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK = 0x000000FF # macro +EDC_HYSTERESIS_STAT__EDC_STATUS_MASK = 0x00000100 # macro +EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW_MASK = 0x00000200 # macro +EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL_MASK = 0x00000400 # macro +GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK = 0xFFFF0000 # macro +GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0__SHIFT = 0x0 # macro +GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1__SHIFT = 0x10 # macro +GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0_MASK = 0x0000FFFF # macro +GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1_MASK = 0xFFFF0000 # macro +GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN__SHIFT = 0x0 # macro +GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT = 0x1 # macro +GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT = 0x5 # macro +GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN_MASK = 0x00000001 # macro +GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK = 0x0000001E # macro +GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK = 0x0001FFE0 # macro +GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT = 0x0 # macro +GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK = 0xFFFFFFFF # macro +GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT = 0x0 # macro +GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK = 0xFFFFFFFF # macro +SE_CAC_CTRL_1__CAC_WINDOW__SHIFT = 0x0 # macro +SE_CAC_CTRL_1__TDP_WINDOW__SHIFT = 0x8 # macro +SE_CAC_CTRL_1__CAC_WINDOW_MASK = 0x000000FF # macro +SE_CAC_CTRL_1__TDP_WINDOW_MASK = 0xFFFFFF00 # macro +SE_CAC_CTRL_2__CAC_ENABLE__SHIFT = 0x0 # macro +SE_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT = 0x1 # macro +SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE__SHIFT = 0x2 # macro +SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN__SHIFT = 0x3 # macro +SE_CAC_CTRL_2__CAC_ENABLE_MASK = 0x00000001 # macro +SE_CAC_CTRL_2__SE_LCAC_ENABLE_MASK = 0x00000002 # macro +SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE_MASK = 0x00000004 # macro +SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN_MASK = 0x00000008 # macro +SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5_MASK = 0xFFFF0000 # macro +SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6__SHIFT = 0x0 # macro +SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7__SHIFT = 0x10 # macro +SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6_MASK = 0x0000FFFF # macro +SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7_MASK = 0xFFFF0000 # macro +SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE__SHIFT = 0x0 # macro +SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE_MASK = 0xFFFFFFFF # macro +SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE__SHIFT = 0x0 # macro +SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE_MASK = 0x000003FF # macro +SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT = 0x0 # macro +SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK = 0xFFFFFFFF # macro +SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT = 0x0 # macro +SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK = 0xFFFFFFFF # macro +SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_0__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_1__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_2__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_3__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_4__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_5__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_6__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_7__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_8__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_9__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_10__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_11__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_12__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_13__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_14__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_15__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK = 0x00FF0000 # macro +CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT = 0x0 # macro +CP_EOP_DONE_DATA_LO__DATA_LO_MASK = 0xFFFFFFFF # macro +CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT = 0x0 # macro +CP_EOP_DONE_DATA_HI__DATA_HI_MASK = 0xFFFFFFFF # macro +CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT = 0x0 # macro +CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK = 0xFFFFFFFF # macro +CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT = 0x0 # macro +CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK = 0xFFFFFFFF # macro +CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT = 0x2 # macro +CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT = 0x0 # macro +CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK = 0x0000FFFF # macro +CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT = 0x0 # macro +CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT = 0x0 # macro +CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK = 0xFFFFFFFF # macro +CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT = 0x19 # macro +CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK = 0x06000000 # macro +SCRATCH_REG0__SCRATCH_REG0__SHIFT = 0x0 # macro +SCRATCH_REG0__SCRATCH_REG0_MASK = 0xFFFFFFFF # macro +SCRATCH_REG1__SCRATCH_REG1__SHIFT = 0x0 # macro +SCRATCH_REG1__SCRATCH_REG1_MASK = 0xFFFFFFFF # macro +SCRATCH_REG2__SCRATCH_REG2__SHIFT = 0x0 # macro +SCRATCH_REG2__SCRATCH_REG2_MASK = 0xFFFFFFFF # macro +SCRATCH_REG3__SCRATCH_REG3__SHIFT = 0x0 # macro +SCRATCH_REG3__SCRATCH_REG3_MASK = 0xFFFFFFFF # macro +SCRATCH_REG4__SCRATCH_REG4__SHIFT = 0x0 # macro +SCRATCH_REG4__SCRATCH_REG4_MASK = 0xFFFFFFFF # macro +SCRATCH_REG5__SCRATCH_REG5__SHIFT = 0x0 # macro +SCRATCH_REG5__SCRATCH_REG5_MASK = 0xFFFFFFFF # macro +SCRATCH_REG6__SCRATCH_REG6__SHIFT = 0x0 # macro +SCRATCH_REG6__SCRATCH_REG6_MASK = 0xFFFFFFFF # macro +SCRATCH_REG7__SCRATCH_REG7__SHIFT = 0x0 # macro +SCRATCH_REG7__SCRATCH_REG7_MASK = 0xFFFFFFFF # macro +SCRATCH_REG_ATOMIC__IMMED__SHIFT = 0x0 # macro +SCRATCH_REG_ATOMIC__ID__SHIFT = 0x18 # macro +SCRATCH_REG_ATOMIC__reserved27__SHIFT = 0x1b # macro +SCRATCH_REG_ATOMIC__OP__SHIFT = 0x1c # macro +SCRATCH_REG_ATOMIC__reserved31__SHIFT = 0x1f # macro +SCRATCH_REG_ATOMIC__IMMED_MASK = 0x00FFFFFF # macro +SCRATCH_REG_ATOMIC__ID_MASK = 0x07000000 # macro +SCRATCH_REG_ATOMIC__reserved27_MASK = 0x08000000 # macro +SCRATCH_REG_ATOMIC__OP_MASK = 0x70000000 # macro +SCRATCH_REG_ATOMIC__reserved31_MASK = 0x80000000 # macro +SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT = 0x0 # macro +SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT = 0xc # macro +SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT = 0x18 # macro +SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT = 0x1b # macro +SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT = 0x1c # macro +SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT = 0x1f # macro +SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK = 0x00000FFF # macro +SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK = 0x00FFF000 # macro +SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK = 0x07000000 # macro +SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK = 0x08000000 # macro +SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK = 0x70000000 # macro +SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK = 0x80000000 # macro +CP_APPEND_DDID_CNT__DATA__SHIFT = 0x0 # macro +CP_APPEND_DDID_CNT__DATA_MASK = 0x000000FF # macro +CP_APPEND_DATA_HI__DATA__SHIFT = 0x0 # macro +CP_APPEND_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT = 0x0 # macro +CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT = 0x0 # macro +CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT = 0x2 # macro +CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT = 0x0 # macro +CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT = 0x10 # macro +CP_APPEND_ADDR_HI__FENCE_SIZE__SHIFT = 0x12 # macro +CP_APPEND_ADDR_HI__PWS_ENABLE__SHIFT = 0x13 # macro +CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT = 0x19 # macro +CP_APPEND_ADDR_HI__COMMAND__SHIFT = 0x1d # macro +CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK = 0x0000FFFF # macro +CP_APPEND_ADDR_HI__CS_PS_SEL_MASK = 0x00030000 # macro +CP_APPEND_ADDR_HI__FENCE_SIZE_MASK = 0x00040000 # macro +CP_APPEND_ADDR_HI__PWS_ENABLE_MASK = 0x00080000 # macro +CP_APPEND_ADDR_HI__CACHE_POLICY_MASK = 0x06000000 # macro +CP_APPEND_ADDR_HI__COMMAND_MASK = 0xE0000000 # macro +CP_APPEND_DATA__DATA__SHIFT = 0x0 # macro +CP_APPEND_DATA__DATA_MASK = 0xFFFFFFFF # macro +CP_APPEND_DATA_LO__DATA__SHIFT = 0x0 # macro +CP_APPEND_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT = 0x0 # macro +CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT = 0x0 # macro +CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT = 0x0 # macro +CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT = 0x0 # macro +CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT = 0x2 # macro +CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK = 0xFFFFFFFC # macro +CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT = 0x0 # macro +CP_ME_MC_WADDR_HI__WRITE_CONFIRM__SHIFT = 0x11 # macro +CP_ME_MC_WADDR_HI__WRITE64__SHIFT = 0x12 # macro +CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT = 0x16 # macro +CP_ME_MC_WADDR_HI__VMID__SHIFT = 0x18 # macro +CP_ME_MC_WADDR_HI__RINGID__SHIFT = 0x1c # macro +CP_ME_MC_WADDR_HI__PRIVILEGE__SHIFT = 0x1f # macro +CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK = 0x0000FFFF # macro +CP_ME_MC_WADDR_HI__WRITE_CONFIRM_MASK = 0x00020000 # macro +CP_ME_MC_WADDR_HI__WRITE64_MASK = 0x00040000 # macro +CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK = 0x00C00000 # macro +CP_ME_MC_WADDR_HI__VMID_MASK = 0x0F000000 # macro +CP_ME_MC_WADDR_HI__RINGID_MASK = 0x30000000 # macro +CP_ME_MC_WADDR_HI__PRIVILEGE_MASK = 0x80000000 # macro +CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT = 0x0 # macro +CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK = 0xFFFFFFFF # macro +CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT = 0x0 # macro +CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK = 0xFFFFFFFF # macro +CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT = 0x2 # macro +CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK = 0xFFFFFFFC # macro +CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT = 0x0 # macro +CP_ME_MC_RADDR_HI__SIZE__SHIFT = 0x10 # macro +CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT = 0x16 # macro +CP_ME_MC_RADDR_HI__VMID__SHIFT = 0x18 # macro +CP_ME_MC_RADDR_HI__PRIVILEGE__SHIFT = 0x1f # macro +CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK = 0x0000FFFF # macro +CP_ME_MC_RADDR_HI__SIZE_MASK = 0x000F0000 # macro +CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK = 0x00C00000 # macro +CP_ME_MC_RADDR_HI__VMID_MASK = 0x0F000000 # macro +CP_ME_MC_RADDR_HI__PRIVILEGE_MASK = 0x80000000 # macro +CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT = 0x0 # macro +CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK = 0xFFFFFFFF # macro +CP_SIG_SEM_ADDR_LO__SEM_PRIV__SHIFT = 0x0 # macro +CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT = 0x3 # macro +CP_SIG_SEM_ADDR_LO__SEM_PRIV_MASK = 0x00000001 # macro +CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK = 0xFFFFFFF8 # macro +CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT = 0x0 # macro +CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT = 0x10 # macro +CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT = 0x14 # macro +CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT = 0x18 # macro +CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT = 0x1d # macro +CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK = 0x0000FFFF # macro +CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK = 0x00010000 # macro +CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK = 0x00100000 # macro +CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK = 0x03000000 # macro +CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK = 0xE0000000 # macro +CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT = 0x0 # macro +CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK = 0xFFFFFFFF # macro +CP_WAIT_SEM_ADDR_LO__SEM_PRIV__SHIFT = 0x0 # macro +CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT = 0x3 # macro +CP_WAIT_SEM_ADDR_LO__SEM_PRIV_MASK = 0x00000001 # macro +CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK = 0xFFFFFFF8 # macro +CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT = 0x0 # macro +CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT = 0x10 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT = 0x14 # macro +CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT = 0x18 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT = 0x1d # macro +CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK = 0x0000FFFF # macro +CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK = 0x00010000 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK = 0x00100000 # macro +CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK = 0x03000000 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK = 0xE0000000 # macro +CP_DMA_PFP_CONTROL__VMID__SHIFT = 0x0 # macro +CP_DMA_PFP_CONTROL__TMZ__SHIFT = 0x4 # macro +CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT = 0xa # macro +CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT = 0xd # macro +CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT = 0xf # macro +CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT = 0x14 # macro +CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT = 0x19 # macro +CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT = 0x1b # macro +CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT = 0x1d # macro +CP_DMA_PFP_CONTROL__VMID_MASK = 0x0000000F # macro +CP_DMA_PFP_CONTROL__TMZ_MASK = 0x00000010 # macro +CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK = 0x00000400 # macro +CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK = 0x00006000 # macro +CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK = 0x00008000 # macro +CP_DMA_PFP_CONTROL__DST_SELECT_MASK = 0x00300000 # macro +CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK = 0x06000000 # macro +CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK = 0x08000000 # macro +CP_DMA_PFP_CONTROL__SRC_SELECT_MASK = 0x60000000 # macro +CP_DMA_ME_CONTROL__VMID__SHIFT = 0x0 # macro +CP_DMA_ME_CONTROL__TMZ__SHIFT = 0x4 # macro +CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT = 0xa # macro +CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT = 0xd # macro +CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT = 0xf # macro +CP_DMA_ME_CONTROL__DST_SELECT__SHIFT = 0x14 # macro +CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT = 0x19 # macro +CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT = 0x1b # macro +CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT = 0x1d # macro +CP_DMA_ME_CONTROL__VMID_MASK = 0x0000000F # macro +CP_DMA_ME_CONTROL__TMZ_MASK = 0x00000010 # macro +CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK = 0x00000400 # macro +CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK = 0x00006000 # macro +CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK = 0x00008000 # macro +CP_DMA_ME_CONTROL__DST_SELECT_MASK = 0x00300000 # macro +CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK = 0x06000000 # macro +CP_DMA_ME_CONTROL__DST_VOLATLE_MASK = 0x08000000 # macro +CP_DMA_ME_CONTROL__SRC_SELECT_MASK = 0x60000000 # macro +CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT = 0x0 # macro +CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT = 0x0 # macro +CP_DMA_ME_DST_ADDR__DST_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT = 0x0 # macro +CP_DMA_ME_COMMAND__SAS__SHIFT = 0x1a # macro +CP_DMA_ME_COMMAND__DAS__SHIFT = 0x1b # macro +CP_DMA_ME_COMMAND__SAIC__SHIFT = 0x1c # macro +CP_DMA_ME_COMMAND__DAIC__SHIFT = 0x1d # macro +CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT = 0x1e # macro +CP_DMA_ME_COMMAND__DIS_WC__SHIFT = 0x1f # macro +CP_DMA_ME_COMMAND__BYTE_COUNT_MASK = 0x03FFFFFF # macro +CP_DMA_ME_COMMAND__SAS_MASK = 0x04000000 # macro +CP_DMA_ME_COMMAND__DAS_MASK = 0x08000000 # macro +CP_DMA_ME_COMMAND__SAIC_MASK = 0x10000000 # macro +CP_DMA_ME_COMMAND__DAIC_MASK = 0x20000000 # macro +CP_DMA_ME_COMMAND__RAW_WAIT_MASK = 0x40000000 # macro +CP_DMA_ME_COMMAND__DIS_WC_MASK = 0x80000000 # macro +CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT = 0x0 # macro +CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT = 0x0 # macro +CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT = 0x0 # macro +CP_DMA_PFP_COMMAND__SAS__SHIFT = 0x1a # macro +CP_DMA_PFP_COMMAND__DAS__SHIFT = 0x1b # macro +CP_DMA_PFP_COMMAND__SAIC__SHIFT = 0x1c # macro +CP_DMA_PFP_COMMAND__DAIC__SHIFT = 0x1d # macro +CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT = 0x1e # macro +CP_DMA_PFP_COMMAND__DIS_WC__SHIFT = 0x1f # macro +CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK = 0x03FFFFFF # macro +CP_DMA_PFP_COMMAND__SAS_MASK = 0x04000000 # macro +CP_DMA_PFP_COMMAND__DAS_MASK = 0x08000000 # macro +CP_DMA_PFP_COMMAND__SAIC_MASK = 0x10000000 # macro +CP_DMA_PFP_COMMAND__DAIC_MASK = 0x20000000 # macro +CP_DMA_PFP_COMMAND__RAW_WAIT_MASK = 0x40000000 # macro +CP_DMA_PFP_COMMAND__DIS_WC_MASK = 0x80000000 # macro +CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT = 0x0 # macro +CP_DMA_CNTL__WATCH_CONTROL__SHIFT = 0x1 # macro +CP_DMA_CNTL__MIN_AVAILSZ__SHIFT = 0x4 # macro +CP_DMA_CNTL__BUFFER_DEPTH__SHIFT = 0x10 # macro +CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT = 0x1c # macro +CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT = 0x1d # macro +CP_DMA_CNTL__PIO_COUNT__SHIFT = 0x1e # macro +CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK = 0x00000001 # macro +CP_DMA_CNTL__WATCH_CONTROL_MASK = 0x00000002 # macro +CP_DMA_CNTL__MIN_AVAILSZ_MASK = 0x00000030 # macro +CP_DMA_CNTL__BUFFER_DEPTH_MASK = 0x01FF0000 # macro +CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK = 0x10000000 # macro +CP_DMA_CNTL__PIO_FIFO_FULL_MASK = 0x20000000 # macro +CP_DMA_CNTL__PIO_COUNT_MASK = 0xC0000000 # macro +CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT = 0x0 # macro +CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT = 0x1c # macro +CP_DMA_READ_TAGS__DMA_READ_TAG_MASK = 0x03FFFFFF # macro +CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK = 0x10000000 # macro +CP_PFP_IB_CONTROL__IB_EN__SHIFT = 0x0 # macro +CP_PFP_IB_CONTROL__IB_EN_MASK = 0x000000FF # macro +CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT = 0x0 # macro +CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT = 0x1 # macro +CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT = 0xf # macro +CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT = 0x10 # macro +CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT = 0x18 # macro +CP_PFP_LOAD_CONTROL__LOAD_ORDINAL__SHIFT = 0x1f # macro +CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK = 0x00000001 # macro +CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK = 0x00000002 # macro +CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK = 0x00008000 # macro +CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK = 0x00010000 # macro +CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK = 0x01000000 # macro +CP_PFP_LOAD_CONTROL__LOAD_ORDINAL_MASK = 0x80000000 # macro +CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT = 0x0 # macro +CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT = 0x1f # macro +CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK = 0x000001FF # macro +CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK = 0x80000000 # macro +CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT = 0x0 # macro +CP_SCRATCH_DATA__SCRATCH_DATA_MASK = 0xFFFFFFFF # macro +CP_RB_OFFSET__RB_OFFSET__SHIFT = 0x0 # macro +CP_RB_OFFSET__RB_OFFSET_MASK = 0x000FFFFF # macro +CP_IB2_OFFSET__IB2_OFFSET__SHIFT = 0x0 # macro +CP_IB2_OFFSET__IB2_OFFSET_MASK = 0x000FFFFF # macro +CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT = 0x0 # macro +CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK = 0x000FFFFF # macro +CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT = 0x0 # macro +CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK = 0x000FFFFF # macro +CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT = 0x0 # macro +CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK = 0x00000003 # macro +CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT = 0x0 # macro +CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK = 0x00000003 # macro +CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT = 0x0 # macro +CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_APPEND_CMD_ADDR_LO__RSVD_MASK = 0x00000003 # macro +CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT = 0x10 # macro +CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_APPEND_CMD_ADDR_HI__RSVD_MASK = 0xFFFF0000 # macro +UCONFIG_RESERVED_REG0__DATA__SHIFT = 0x0 # macro +UCONFIG_RESERVED_REG0__DATA_MASK = 0xFFFFFFFF # macro +UCONFIG_RESERVED_REG1__DATA__SHIFT = 0x0 # macro +UCONFIG_RESERVED_REG1__DATA_MASK = 0xFFFFFFFF # macro +CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO__SHIFT = 0x0 # macro +CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI__SHIFT = 0x0 # macro +CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT = 0x0 # macro +CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT = 0x0 # macro +CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT = 0x2 # macro +CP_IB2_BASE_LO__IB2_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT = 0x0 # macro +CP_IB2_BASE_HI__IB2_BASE_HI_MASK = 0x0000FFFF # macro +CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT = 0x0 # macro +CP_IB2_BUFSZ__IB2_BUFSZ_MASK = 0x000FFFFF # macro +CP_ST_BASE_LO__ST_BASE_LO__SHIFT = 0x2 # macro +CP_ST_BASE_LO__ST_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_ST_BASE_HI__ST_BASE_HI__SHIFT = 0x0 # macro +CP_ST_BASE_HI__ST_BASE_HI_MASK = 0x0000FFFF # macro +CP_ST_BUFSZ__ST_BUFSZ__SHIFT = 0x0 # macro +CP_ST_BUFSZ__ST_BUFSZ_MASK = 0x000FFFFF # macro +CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT = 0xc # macro +CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT = 0x19 # macro +CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT = 0x1b # macro +CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT = 0x1c # macro +CP_EOP_DONE_EVENT_CNTL__GLK_INV__SHIFT = 0x1e # macro +CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE__SHIFT = 0x1f # macro +CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK = 0x01FFF000 # macro +CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK = 0x06000000 # macro +CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK = 0x08000000 # macro +CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK = 0x10000000 # macro +CP_EOP_DONE_EVENT_CNTL__GLK_INV_MASK = 0x40000000 # macro +CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE_MASK = 0x80000000 # macro +CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT = 0x10 # macro +CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE__SHIFT = 0x13 # macro +CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT = 0x14 # macro +CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT = 0x16 # macro +CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT = 0x18 # macro +CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT = 0x1d # macro +CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK = 0x00030000 # macro +CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE_MASK = 0x00080000 # macro +CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK = 0x00300000 # macro +CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK = 0x00C00000 # macro +CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK = 0x07000000 # macro +CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK = 0xE0000000 # macro +CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT = 0x0 # macro +CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK = 0xFFFFFFFF # macro +CP_DB_BASE_LO__DB_BASE_LO__SHIFT = 0x2 # macro +CP_DB_BASE_LO__DB_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_DB_BASE_HI__DB_BASE_HI__SHIFT = 0x0 # macro +CP_DB_BASE_HI__DB_BASE_HI_MASK = 0x0000FFFF # macro +CP_DB_BUFSZ__DB_BUFSZ__SHIFT = 0x0 # macro +CP_DB_BUFSZ__DB_BUFSZ_MASK = 0x000FFFFF # macro +CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT = 0x0 # macro +CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_PFP_COMPLETION_STATUS__STATUS__SHIFT = 0x0 # macro +CP_PFP_COMPLETION_STATUS__STATUS_MASK = 0x00000003 # macro +CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT = 0x0 # macro +CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK = 0x00000001 # macro +CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_INDEX_BASE_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_INDEX_TYPE__INDEX_TYPE__SHIFT = 0x0 # macro +CP_INDEX_TYPE__INDEX_TYPE_MASK = 0x00000003 # macro +CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_GDS_BKUP_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT = 0x0 # macro +CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT = 0x1 # macro +CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT = 0x2 # macro +CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT = 0x3 # macro +CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT = 0x4 # macro +CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT = 0x5 # macro +CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT = 0x6 # macro +CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT = 0x7 # macro +CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK = 0x00000001 # macro +CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK = 0x00000002 # macro +CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK = 0x00000004 # macro +CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK = 0x00000008 # macro +CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK = 0x00000010 # macro +CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK = 0x00000020 # macro +CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK = 0x00000040 # macro +CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK = 0x00000080 # macro +CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT = 0x0 # macro +CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT = 0x1 # macro +CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT = 0x6 # macro +CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT = 0x7 # macro +CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT = 0x8 # macro +CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT = 0x9 # macro +CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT = 0xa # macro +CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT = 0xb # macro +CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT = 0xc # macro +CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT = 0xd # macro +CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT = 0xe # macro +CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT = 0x13 # macro +CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT = 0x15 # macro +CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK = 0x00000001 # macro +CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK = 0x00000002 # macro +CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK = 0x00000040 # macro +CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK = 0x00000080 # macro +CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK = 0x00000100 # macro +CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK = 0x00000200 # macro +CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK = 0x00000400 # macro +CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK = 0x00000800 # macro +CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK = 0x00001000 # macro +CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK = 0x00002000 # macro +CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK = 0x00004000 # macro +CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK = 0x00080000 # macro +CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK = 0x00200000 # macro +CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT = 0x0 # macro +CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK = 0xFFFFFFFF # macro +CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT = 0x0 # macro +CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK = 0x000000FF # macro +CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT = 0x0 # macro +CP_ME_COHER_BASE__COHER_BASE_256B_MASK = 0xFFFFFFFF # macro +CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT = 0x0 # macro +CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK = 0x000000FF # macro +CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT = 0x0 # macro +CP_ME_COHER_STATUS__STATUS__SHIFT = 0x1f # macro +CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK = 0x000000FF # macro +CP_ME_COHER_STATUS__STATUS_MASK = 0x80000000 # macro +RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT = 0x0 # macro +RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT = 0x4 # macro +RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT = 0x8 # macro +RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT = 0xc # macro +RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT = 0x10 # macro +RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT = 0x12 # macro +RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT = 0x14 # macro +RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT = 0x15 # macro +RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK = 0x0000000F # macro +RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK = 0x000000F0 # macro +RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK = 0x00000F00 # macro +RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK = 0x0000F000 # macro +RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK = 0x00030000 # macro +RLC_GPM_PERF_COUNT_0__UNUSED_MASK = 0x000C0000 # macro +RLC_GPM_PERF_COUNT_0__ENABLE_MASK = 0x00100000 # macro +RLC_GPM_PERF_COUNT_0__RESERVED_MASK = 0xFFE00000 # macro +RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT = 0x0 # macro +RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT = 0x4 # macro +RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT = 0x8 # macro +RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT = 0xc # macro +RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT = 0x10 # macro +RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT = 0x12 # macro +RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT = 0x14 # macro +RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT = 0x15 # macro +RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK = 0x0000000F # macro +RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK = 0x000000F0 # macro +RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK = 0x00000F00 # macro +RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK = 0x0000F000 # macro +RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK = 0x00030000 # macro +RLC_GPM_PERF_COUNT_1__UNUSED_MASK = 0x000C0000 # macro +RLC_GPM_PERF_COUNT_1__ENABLE_MASK = 0x00100000 # macro +RLC_GPM_PERF_COUNT_1__RESERVED_MASK = 0xFFE00000 # macro +GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT = 0x0 # macro +GRBM_GFX_INDEX__SA_INDEX__SHIFT = 0x8 # macro +GRBM_GFX_INDEX__SE_INDEX__SHIFT = 0x10 # macro +GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT = 0x1d # macro +GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT = 0x1e # macro +GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT = 0x1f # macro +GRBM_GFX_INDEX__INSTANCE_INDEX_MASK = 0x000000FF # macro +GRBM_GFX_INDEX__SA_INDEX_MASK = 0x0000FF00 # macro +GRBM_GFX_INDEX__SE_INDEX_MASK = 0x00FF0000 # macro +GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK = 0x20000000 # macro +GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK = 0x40000000 # macro +GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK = 0x80000000 # macro +VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT = 0x0 # macro +VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK = 0x0000003F # macro +VGT_INDEX_TYPE__INDEX_TYPE__SHIFT = 0x0 # macro +VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT = 0xe # macro +VGT_INDEX_TYPE__INDEX_TYPE_MASK = 0x00000003 # macro +VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK = 0x00004000 # macro +GE_MIN_VTX_INDX__MIN_INDX__SHIFT = 0x0 # macro +GE_MIN_VTX_INDX__MIN_INDX_MASK = 0xFFFFFFFF # macro +GE_INDX_OFFSET__INDX_OFFSET__SHIFT = 0x0 # macro +GE_INDX_OFFSET__INDX_OFFSET_MASK = 0xFFFFFFFF # macro +GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT = 0x0 # macro +GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT = 0x1 # macro +GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX__SHIFT = 0x2 # macro +GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK = 0x00000001 # macro +GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK = 0x00000002 # macro +GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX_MASK = 0x00000004 # macro +VGT_NUM_INDICES__NUM_INDICES__SHIFT = 0x0 # macro +VGT_NUM_INDICES__NUM_INDICES_MASK = 0xFFFFFFFF # macro +VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT = 0x0 # macro +VGT_NUM_INSTANCES__NUM_INSTANCES_MASK = 0xFFFFFFFF # macro +VGT_TF_RING_SIZE__SIZE__SHIFT = 0x0 # macro +VGT_TF_RING_SIZE__SIZE_MASK = 0x0001FFFF # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT = 0x0 # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT = 0xa # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK = 0x000003FF # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK = 0x00000C00 # macro +VGT_TF_MEMORY_BASE__BASE__SHIFT = 0x0 # macro +VGT_TF_MEMORY_BASE__BASE_MASK = 0xFFFFFFFF # macro +GE_MAX_VTX_INDX__MAX_INDX__SHIFT = 0x0 # macro +GE_MAX_VTX_INDX__MAX_INDX_MASK = 0xFFFFFFFF # macro +VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT = 0x0 # macro +VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK = 0xFFFFFFFF # macro +GE_CNTL__PRIMS_PER_SUBGRP__SHIFT = 0x0 # macro +GE_CNTL__VERTS_PER_SUBGRP__SHIFT = 0x9 # macro +GE_CNTL__BREAK_SUBGRP_AT_EOI__SHIFT = 0x12 # macro +GE_CNTL__PACKET_TO_ONE_PA__SHIFT = 0x13 # macro +GE_CNTL__BREAK_PRIMGRP_AT_EOI__SHIFT = 0x14 # macro +GE_CNTL__PRIM_GRP_SIZE__SHIFT = 0x15 # macro +GE_CNTL__GCR_DISABLE__SHIFT = 0x1e # macro +GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP__SHIFT = 0x1f # macro +GE_CNTL__PRIMS_PER_SUBGRP_MASK = 0x000001FF # macro +GE_CNTL__VERTS_PER_SUBGRP_MASK = 0x0003FE00 # macro +GE_CNTL__BREAK_SUBGRP_AT_EOI_MASK = 0x00040000 # macro +GE_CNTL__PACKET_TO_ONE_PA_MASK = 0x00080000 # macro +GE_CNTL__BREAK_PRIMGRP_AT_EOI_MASK = 0x00100000 # macro +GE_CNTL__PRIM_GRP_SIZE_MASK = 0x3FE00000 # macro +GE_CNTL__GCR_DISABLE_MASK = 0x40000000 # macro +GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP_MASK = 0x80000000 # macro +GE_USER_VGPR1__DATA__SHIFT = 0x0 # macro +GE_USER_VGPR1__DATA_MASK = 0xFFFFFFFF # macro +GE_USER_VGPR2__DATA__SHIFT = 0x0 # macro +GE_USER_VGPR2__DATA_MASK = 0xFFFFFFFF # macro +GE_USER_VGPR3__DATA__SHIFT = 0x0 # macro +GE_USER_VGPR3__DATA_MASK = 0xFFFFFFFF # macro +GE_STEREO_CNTL__RT_SLICE__SHIFT = 0x0 # macro +GE_STEREO_CNTL__VIEWPORT__SHIFT = 0x3 # macro +GE_STEREO_CNTL__EN_STEREO__SHIFT = 0x8 # macro +GE_STEREO_CNTL__RT_SLICE_MASK = 0x00000007 # macro +GE_STEREO_CNTL__VIEWPORT_MASK = 0x00000078 # macro +GE_STEREO_CNTL__EN_STEREO_MASK = 0x00000100 # macro +GE_PC_ALLOC__OVERSUB_EN__SHIFT = 0x0 # macro +GE_PC_ALLOC__NUM_PC_LINES__SHIFT = 0x1 # macro +GE_PC_ALLOC__OVERSUB_EN_MASK = 0x00000001 # macro +GE_PC_ALLOC__NUM_PC_LINES_MASK = 0x000007FE # macro +VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT = 0x0 # macro +GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT = 0x1 # macro +GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT = 0x2 # macro +GE_USER_VGPR_EN__EN_USER_VGPR1_MASK = 0x00000001 # macro +GE_USER_VGPR_EN__EN_USER_VGPR2_MASK = 0x00000002 # macro +GE_USER_VGPR_EN__EN_USER_VGPR3_MASK = 0x00000004 # macro +GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X__SHIFT = 0x0 # macro +GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y__SHIFT = 0x10 # macro +GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X_MASK = 0x0000FFFF # macro +GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y_MASK = 0xFFFF0000 # macro +GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z__SHIFT = 0x0 # macro +GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z_MASK = 0x0000FFFF # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT = 0x0 # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK = 0x0000003F # macro +PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT = 0x0 # macro +PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK = 0x00FFFFFF # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT = 0x0 # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT = 0x8 # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK = 0x0000000F # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK = 0x0000FF00 # macro +PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MIN_0__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MAX_0__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MIN_1__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MAX_1__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK = 0xFFFF0000 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT = 0x1 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK = 0x00000001 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK = 0x00000002 # macro +PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK = 0x00003FFF # macro +PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK = 0x00003FFF # macro +PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK = 0x0000FFFF # macro +PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK = 0x0000FFFF # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT = 0x1 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK = 0x00000001 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK = 0x00000002 # macro +PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK = 0x00003FFF # macro +PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK = 0x00003FFF # macro +PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK = 0x0000FFFF # macro +PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK = 0x0000FFFF # macro +PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT = 0x1 # macro +PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK = 0x00000001 # macro +PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK = 0x00000002 # macro +PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_H__X_COORD_MASK = 0x00003FFF # macro +PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_V__Y_COORD_MASK = 0x00003FFF # macro +PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK = 0x0000FFFF # macro +PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK = 0x0000FFFF # macro +SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_0__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_1__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_2__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_3__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_4__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_5__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_6__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_7__DATA_MASK = 0xFFFFFFFF # macro +SQC_CACHES__TARGET_INST__SHIFT = 0x0 # macro +SQC_CACHES__TARGET_DATA__SHIFT = 0x1 # macro +SQC_CACHES__INVALIDATE__SHIFT = 0x2 # macro +SQC_CACHES__COMPLETE__SHIFT = 0x10 # macro +SQC_CACHES__TARGET_INST_MASK = 0x00000001 # macro +SQC_CACHES__TARGET_DATA_MASK = 0x00000002 # macro +SQC_CACHES__INVALIDATE_MASK = 0x00000004 # macro +SQC_CACHES__COMPLETE_MASK = 0x00010000 # macro +TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT = 0x0 # macro +TA_CS_BC_BASE_ADDR__ADDRESS_MASK = 0xFFFFFFFF # macro +TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT = 0x0 # macro +TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK = 0x000000FF # macro +DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +GDS_RD_ADDR__READ_ADDR__SHIFT = 0x0 # macro +GDS_RD_ADDR__READ_ADDR_MASK = 0xFFFFFFFF # macro +GDS_RD_DATA__READ_DATA__SHIFT = 0x0 # macro +GDS_RD_DATA__READ_DATA_MASK = 0xFFFFFFFF # macro +GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT = 0x0 # macro +GDS_RD_BURST_ADDR__BURST_ADDR_MASK = 0xFFFFFFFF # macro +GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT = 0x0 # macro +GDS_RD_BURST_COUNT__BURST_COUNT_MASK = 0xFFFFFFFF # macro +GDS_RD_BURST_DATA__BURST_DATA__SHIFT = 0x0 # macro +GDS_RD_BURST_DATA__BURST_DATA_MASK = 0xFFFFFFFF # macro +GDS_WR_ADDR__WRITE_ADDR__SHIFT = 0x0 # macro +GDS_WR_ADDR__WRITE_ADDR_MASK = 0xFFFFFFFF # macro +GDS_WR_DATA__WRITE_DATA__SHIFT = 0x0 # macro +GDS_WR_DATA__WRITE_DATA_MASK = 0xFFFFFFFF # macro +GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT = 0x0 # macro +GDS_WR_BURST_ADDR__WRITE_ADDR_MASK = 0xFFFFFFFF # macro +GDS_WR_BURST_DATA__WRITE_DATA__SHIFT = 0x0 # macro +GDS_WR_BURST_DATA__WRITE_DATA_MASK = 0xFFFFFFFF # macro +GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT = 0x0 # macro +GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK = 0xFFFFFFFF # macro +GDS_ATOM_CNTL__AINC__SHIFT = 0x0 # macro +GDS_ATOM_CNTL__UNUSED1__SHIFT = 0x6 # macro +GDS_ATOM_CNTL__DMODE__SHIFT = 0x8 # macro +GDS_ATOM_CNTL__UNUSED2__SHIFT = 0xa # macro +GDS_ATOM_CNTL__AINC_MASK = 0x0000003F # macro +GDS_ATOM_CNTL__UNUSED1_MASK = 0x000000C0 # macro +GDS_ATOM_CNTL__DMODE_MASK = 0x00000300 # macro +GDS_ATOM_CNTL__UNUSED2_MASK = 0xFFFFFC00 # macro +GDS_ATOM_COMPLETE__COMPLETE__SHIFT = 0x0 # macro +GDS_ATOM_COMPLETE__UNUSED__SHIFT = 0x1 # macro +GDS_ATOM_COMPLETE__COMPLETE_MASK = 0x00000001 # macro +GDS_ATOM_COMPLETE__UNUSED_MASK = 0xFFFFFFFE # macro +GDS_ATOM_BASE__BASE__SHIFT = 0x0 # macro +GDS_ATOM_BASE__UNUSED__SHIFT = 0xc # macro +GDS_ATOM_BASE__BASE_MASK = 0x00000FFF # macro +GDS_ATOM_BASE__UNUSED_MASK = 0xFFFFF000 # macro +GDS_ATOM_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_ATOM_SIZE__UNUSED__SHIFT = 0xd # macro +GDS_ATOM_SIZE__SIZE_MASK = 0x00001FFF # macro +GDS_ATOM_SIZE__UNUSED_MASK = 0xFFFFE000 # macro +GDS_ATOM_OFFSET0__OFFSET0__SHIFT = 0x0 # macro +GDS_ATOM_OFFSET0__UNUSED__SHIFT = 0x8 # macro +GDS_ATOM_OFFSET0__OFFSET0_MASK = 0x000000FF # macro +GDS_ATOM_OFFSET0__UNUSED_MASK = 0xFFFFFF00 # macro +GDS_ATOM_OFFSET1__OFFSET1__SHIFT = 0x0 # macro +GDS_ATOM_OFFSET1__UNUSED__SHIFT = 0x8 # macro +GDS_ATOM_OFFSET1__OFFSET1_MASK = 0x000000FF # macro +GDS_ATOM_OFFSET1__UNUSED_MASK = 0xFFFFFF00 # macro +GDS_ATOM_DST__DST__SHIFT = 0x0 # macro +GDS_ATOM_DST__DST_MASK = 0xFFFFFFFF # macro +GDS_ATOM_OP__OP__SHIFT = 0x0 # macro +GDS_ATOM_OP__UNUSED__SHIFT = 0x8 # macro +GDS_ATOM_OP__OP_MASK = 0x000000FF # macro +GDS_ATOM_OP__UNUSED_MASK = 0xFFFFFF00 # macro +GDS_ATOM_SRC0__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC0__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_SRC0_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC0_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_SRC1__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC1__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_SRC1_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC1_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ0__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ0__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ0_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ0_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ1__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ1__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ1_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ1_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT = 0x6 # macro +GDS_GWS_RESOURCE_CNTL__INDEX_MASK = 0x0000003F # macro +GDS_GWS_RESOURCE_CNTL__UNUSED_MASK = 0xFFFFFFC0 # macro +GDS_GWS_RESOURCE__FLAG__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE__COUNTER__SHIFT = 0x1 # macro +GDS_GWS_RESOURCE__TYPE__SHIFT = 0xd # macro +GDS_GWS_RESOURCE__DED__SHIFT = 0xe # macro +GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT = 0xf # macro +GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT = 0x10 # macro +GDS_GWS_RESOURCE__HEAD_VALID__SHIFT = 0x1d # macro +GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT = 0x1e # macro +GDS_GWS_RESOURCE__HALTED__SHIFT = 0x1f # macro +GDS_GWS_RESOURCE__FLAG_MASK = 0x00000001 # macro +GDS_GWS_RESOURCE__COUNTER_MASK = 0x00001FFE # macro +GDS_GWS_RESOURCE__TYPE_MASK = 0x00002000 # macro +GDS_GWS_RESOURCE__DED_MASK = 0x00004000 # macro +GDS_GWS_RESOURCE__RELEASE_ALL_MASK = 0x00008000 # macro +GDS_GWS_RESOURCE__HEAD_QUEUE_MASK = 0x1FFF0000 # macro +GDS_GWS_RESOURCE__HEAD_VALID_MASK = 0x20000000 # macro +GDS_GWS_RESOURCE__HEAD_FLAG_MASK = 0x40000000 # macro +GDS_GWS_RESOURCE__HALTED_MASK = 0x80000000 # macro +GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT = 0x10 # macro +GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK = 0x0000FFFF # macro +GDS_GWS_RESOURCE_CNT__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_CNTL__INDEX__SHIFT = 0x0 # macro +GDS_OA_CNTL__UNUSED__SHIFT = 0x4 # macro +GDS_OA_CNTL__INDEX_MASK = 0x0000000F # macro +GDS_OA_CNTL__UNUSED_MASK = 0xFFFFFFF0 # macro +GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT = 0x0 # macro +GDS_OA_COUNTER__SPACE_AVAILABLE_MASK = 0xFFFFFFFF # macro +GDS_OA_ADDRESS__DS_ADDRESS__SHIFT = 0x0 # macro +GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT = 0x10 # macro +GDS_OA_ADDRESS__CRAWLER__SHIFT = 0x14 # macro +GDS_OA_ADDRESS__UNUSED__SHIFT = 0x18 # macro +GDS_OA_ADDRESS__NO_ALLOC__SHIFT = 0x1e # macro +GDS_OA_ADDRESS__ENABLE__SHIFT = 0x1f # macro +GDS_OA_ADDRESS__DS_ADDRESS_MASK = 0x0000FFFF # macro +GDS_OA_ADDRESS__CRAWLER_TYPE_MASK = 0x000F0000 # macro +GDS_OA_ADDRESS__CRAWLER_MASK = 0x00F00000 # macro +GDS_OA_ADDRESS__UNUSED_MASK = 0x3F000000 # macro +GDS_OA_ADDRESS__NO_ALLOC_MASK = 0x40000000 # macro +GDS_OA_ADDRESS__ENABLE_MASK = 0x80000000 # macro +GDS_OA_INCDEC__VALUE__SHIFT = 0x0 # macro +GDS_OA_INCDEC__INCDEC__SHIFT = 0x1f # macro +GDS_OA_INCDEC__VALUE_MASK = 0x7FFFFFFF # macro +GDS_OA_INCDEC__INCDEC_MASK = 0x80000000 # macro +GDS_OA_RING_SIZE__RING_SIZE__SHIFT = 0x0 # macro +GDS_OA_RING_SIZE__RING_SIZE_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_DWORDS_WRITTEN_0__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_DWORDS_WRITTEN_0__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_DWORDS_WRITTEN_1__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_DWORDS_WRITTEN_1__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_DWORDS_WRITTEN_2__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_DWORDS_WRITTEN_2__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_DWORDS_WRITTEN_3__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_DWORDS_WRITTEN_3__DATA_MASK = 0xFFFFFFFF # macro +GDS_GS_0__DATA__SHIFT = 0x0 # macro +GDS_GS_0__DATA_MASK = 0xFFFFFFFF # macro +GDS_GS_1__DATA__SHIFT = 0x0 # macro +GDS_GS_1__DATA_MASK = 0xFFFFFFFF # macro +GDS_GS_2__DATA__SHIFT = 0x0 # macro +GDS_GS_2__DATA_MASK = 0xFFFFFFFF # macro +GDS_GS_3__DATA__SHIFT = 0x0 # macro +GDS_GS_3__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA_MASK = 0xFFFFFFFF # macro +GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA__SHIFT = 0x0 # macro +GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA_MASK = 0xFFFFFFFF # macro +SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT = 0x0 # macro +SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT = 0x15 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT = 0x18 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT = 0x19 # macro +SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT = 0x1c # macro +SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT = 0x1d # macro +SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT = 0x1e # macro +SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK = 0x001FFFFF # macro +SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK = 0x00E00000 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK = 0x01000000 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK = 0x02000000 # macro +SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK = 0x10000000 # macro +SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK = 0x20000000 # macro +SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK = 0xC0000000 # macro +SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT = 0x0 # macro +SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT = 0x4 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT = 0x5 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT = 0x7 # macro +SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE__SHIFT = 0x8 # macro +SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL__SHIFT = 0x9 # macro +SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT = 0xa # macro +SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT = 0xe # macro +SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT = 0xf # macro +SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT = 0x10 # macro +SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT = 0x15 # macro +SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT = 0x16 # macro +SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT__SHIFT = 0x17 # macro +SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK = 0x0000000F # macro +SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK = 0x00000010 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK = 0x00000060 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK = 0x00000080 # macro +SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE_MASK = 0x00000100 # macro +SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL_MASK = 0x00000200 # macro +SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK = 0x00003C00 # macro +SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK = 0x00004000 # macro +SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK = 0x00008000 # macro +SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK = 0x001F0000 # macro +SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK = 0x00200000 # macro +SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK = 0x00400000 # macro +SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MASK = 0xFF800000 # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT = 0x0 # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT = 0x4 # macro +SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE__SHIFT = 0x8 # macro +SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE__SHIFT = 0x9 # macro +SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE__SHIFT = 0xa # macro +SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE__SHIFT = 0xb # macro +SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY__SHIFT = 0xc # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK = 0x0000000F # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK = 0x000000F0 # macro +SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE_MASK = 0x00000100 # macro +SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE_MASK = 0x00000200 # macro +SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE_MASK = 0x00000400 # macro +SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE_MASK = 0x00000800 # macro +SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY_MASK = 0x0001F000 # macro +SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT = 0x0 # macro +SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT = 0x4 # macro +SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT = 0x6 # macro +SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK = 0x00000003 # macro +SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK = 0x00000030 # macro +SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK = 0x000000C0 # macro +SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL__SHIFT = 0x0 # macro +SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE__SHIFT = 0x4 # macro +SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE__SHIFT = 0x8 # macro +SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD__SHIFT = 0xc # macro +SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD__SHIFT = 0x10 # macro +SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL__SHIFT = 0x14 # macro +SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE__SHIFT = 0x18 # macro +SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE__SHIFT = 0x1c # macro +SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL_MASK = 0x0000000F # macro +SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE_MASK = 0x000000F0 # macro +SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE_MASK = 0x00000F00 # macro +SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD_MASK = 0x0000F000 # macro +SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD_MASK = 0x000F0000 # macro +SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL_MASK = 0x00F00000 # macro +SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE_MASK = 0x0F000000 # macro +SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE_MASK = 0xF0000000 # macro +SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE__SHIFT = 0x0 # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD__SHIFT = 0x2 # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR__SHIFT = 0x6 # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1__SHIFT = 0x8 # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2__SHIFT = 0xb # macro +SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD__SHIFT = 0xe # macro +SPI_GS_THROTTLE_CNTL2__PH_MODE__SHIFT = 0x10 # macro +SPI_GS_THROTTLE_CNTL2__RESERVED__SHIFT = 0x11 # macro +SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE_MASK = 0x00000003 # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_MASK = 0x0000003C # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR_MASK = 0x000000C0 # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1_MASK = 0x00000700 # macro +SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2_MASK = 0x00003800 # macro +SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD_MASK = 0x0000C000 # macro +SPI_GS_THROTTLE_CNTL2__PH_MODE_MASK = 0x00010000 # macro +SPI_GS_THROTTLE_CNTL2__RESERVED_MASK = 0xFFFE0000 # macro +SPI_ATTRIBUTE_RING_BASE__BASE__SHIFT = 0x0 # macro +SPI_ATTRIBUTE_RING_BASE__BASE_MASK = 0xFFFFFFFF # macro +SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE__SHIFT = 0x0 # macro +SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE__SHIFT = 0x10 # macro +SPI_ATTRIBUTE_RING_SIZE__L1_POLICY__SHIFT = 0x11 # macro +SPI_ATTRIBUTE_RING_SIZE__L2_POLICY__SHIFT = 0x13 # macro +SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC__SHIFT = 0x15 # macro +SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE__SHIFT = 0x16 # macro +SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE_MASK = 0x000000FF # macro +SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE_MASK = 0x00010000 # macro +SPI_ATTRIBUTE_RING_SIZE__L1_POLICY_MASK = 0x00060000 # macro +SPI_ATTRIBUTE_RING_SIZE__L2_POLICY_MASK = 0x00180000 # macro +SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC_MASK = 0x00200000 # macro +SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE_MASK = 0x00400000 # macro +CP_MES_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_MES_PRGRM_CNTR_START__IP_START_MASK = 0xFFFFFFFF # macro +CP_MES_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_MES_INTR_ROUTINE_START__IR_START_MASK = 0xFFFFFFFF # macro +CP_MES_MTVEC_LO__ADDR_LO__SHIFT = 0x0 # macro +CP_MES_MTVEC_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT = 0x0 # macro +CP_MES_INTR_ROUTINE_START_HI__IR_START_MASK = 0xFFFFFFFF # macro +CP_MES_MTVEC_HI__ADDR_LO__SHIFT = 0x0 # macro +CP_MES_MTVEC_HI__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT = 0x4 # macro +CP_MES_CNTL__MES_PIPE0_RESET__SHIFT = 0x10 # macro +CP_MES_CNTL__MES_PIPE1_RESET__SHIFT = 0x11 # macro +CP_MES_CNTL__MES_PIPE2_RESET__SHIFT = 0x12 # macro +CP_MES_CNTL__MES_PIPE3_RESET__SHIFT = 0x13 # macro +CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT = 0x1a # macro +CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT = 0x1b # macro +CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT = 0x1c # macro +CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT = 0x1d # macro +CP_MES_CNTL__MES_HALT__SHIFT = 0x1e # macro +CP_MES_CNTL__MES_STEP__SHIFT = 0x1f # macro +CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK = 0x00000010 # macro +CP_MES_CNTL__MES_PIPE0_RESET_MASK = 0x00010000 # macro +CP_MES_CNTL__MES_PIPE1_RESET_MASK = 0x00020000 # macro +CP_MES_CNTL__MES_PIPE2_RESET_MASK = 0x00040000 # macro +CP_MES_CNTL__MES_PIPE3_RESET_MASK = 0x00080000 # macro +CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK = 0x04000000 # macro +CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK = 0x08000000 # macro +CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK = 0x10000000 # macro +CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK = 0x20000000 # macro +CP_MES_CNTL__MES_HALT_MASK = 0x40000000 # macro +CP_MES_CNTL__MES_STEP_MASK = 0x80000000 # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_MES_PIPE0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_MES_PIPE1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_MES_PIPE2_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_MES_PIPE3_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT = 0x0 # macro +CP_MES_HEADER_DUMP__HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_MES_MIE_LO__MES_INT__SHIFT = 0x0 # macro +CP_MES_MIE_LO__MES_INT_MASK = 0xFFFFFFFF # macro +CP_MES_MIE_HI__MES_INT__SHIFT = 0x0 # macro +CP_MES_MIE_HI__MES_INT_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT__MES_INT__SHIFT = 0x0 # macro +CP_MES_INTERRUPT__MES_INT_MASK = 0xFFFFFFFF # macro +CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT = 0x0 # macro +CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT = 0x1f # macro +CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK = 0x000001FF # macro +CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK = 0x80000000 # macro +CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT = 0x0 # macro +CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_MES_INSTR_PNTR__INSTR_PNTR_MASK = 0x000FFFFF # macro +CP_MES_MSCRATCH_HI__DATA__SHIFT = 0x0 # macro +CP_MES_MSCRATCH_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_MSCRATCH_LO__DATA__SHIFT = 0x0 # macro +CP_MES_MSCRATCH_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_MSTATUS_LO__STATUS_LO__SHIFT = 0x0 # macro +CP_MES_MSTATUS_LO__STATUS_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MSTATUS_HI__STATUS_HI__SHIFT = 0x0 # macro +CP_MES_MSTATUS_HI__STATUS_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MEPC_LO__MEPC_LO__SHIFT = 0x0 # macro +CP_MES_MEPC_LO__MEPC_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MEPC_HI__MEPC_HI__SHIFT = 0x0 # macro +CP_MES_MEPC_HI__MEPC_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT = 0x0 # macro +CP_MES_MCAUSE_LO__CAUSE_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT = 0x0 # macro +CP_MES_MCAUSE_HI__CAUSE_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MBADADDR_LO__ADDR_LO__SHIFT = 0x0 # macro +CP_MES_MBADADDR_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MBADADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_MES_MBADADDR_HI__ADDR_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MIP_LO__MIP_LO__SHIFT = 0x0 # macro +CP_MES_MIP_LO__MIP_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MIP_HI__MIP_HI__SHIFT = 0x0 # macro +CP_MES_MIP_HI__MIP_HI_MASK = 0xFFFFFFFF # macro +CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT = 0x0 # macro +CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT = 0x4 # macro +CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT = 0x5 # macro +CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK = 0x00000001 # macro +CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK = 0x00000010 # macro +CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK = 0x00000020 # macro +CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT = 0x0 # macro +CP_MES_MCYCLE_LO__CYCLE_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT = 0x0 # macro +CP_MES_MCYCLE_HI__CYCLE_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MTIME_LO__TIME_LO__SHIFT = 0x0 # macro +CP_MES_MTIME_LO__TIME_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MTIME_HI__TIME_HI__SHIFT = 0x0 # macro +CP_MES_MTIME_HI__TIME_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT = 0x0 # macro +CP_MES_MINSTRET_LO__INSTRET_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT = 0x0 # macro +CP_MES_MINSTRET_HI__INSTRET_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MISA_LO__MISA_LO__SHIFT = 0x0 # macro +CP_MES_MISA_LO__MISA_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MISA_HI__MISA_HI__SHIFT = 0x0 # macro +CP_MES_MISA_HI__MISA_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT = 0x0 # macro +CP_MES_MVENDORID_LO__MVENDORID_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT = 0x0 # macro +CP_MES_MVENDORID_HI__MVENDORID_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MARCHID_LO__MARCHID_LO__SHIFT = 0x0 # macro +CP_MES_MARCHID_LO__MARCHID_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MARCHID_HI__MARCHID_HI__SHIFT = 0x0 # macro +CP_MES_MARCHID_HI__MARCHID_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MIMPID_LO__MIMPID_LO__SHIFT = 0x0 # macro +CP_MES_MIMPID_LO__MIMPID_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MIMPID_HI__MIMPID_HI__SHIFT = 0x0 # macro +CP_MES_MIMPID_HI__MIMPID_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MHARTID_LO__MHARTID_LO__SHIFT = 0x0 # macro +CP_MES_MHARTID_LO__MHARTID_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MHARTID_HI__MHARTID_HI__SHIFT = 0x0 # macro +CP_MES_MHARTID_HI__MHARTID_HI_MASK = 0xFFFFFFFF # macro +CP_MES_DC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_MES_DC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT = 0x0 # macro +CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT = 0x1 # macro +CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT = 0x2 # macro +CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK = 0x00000001 # macro +CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK = 0x00000002 # macro +CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK = 0x00000004 # macro +CP_MES_MTIMECMP_LO__TIME_LO__SHIFT = 0x0 # macro +CP_MES_MTIMECMP_LO__TIME_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MTIMECMP_HI__TIME_HI__SHIFT = 0x0 # macro +CP_MES_MTIMECMP_HI__TIME_HI_MASK = 0xFFFFFFFF # macro +CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT = 0x0 # macro +CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT = 0x1c # macro +CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT = 0x1d # macro +CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT = 0x1f # macro +CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK = 0x0FFFFFFF # macro +CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK = 0x10000000 # macro +CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK = 0x60000000 # macro +CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK = 0x80000000 # macro +CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT = 0x0 # macro +CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT = 0x1c # macro +CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT = 0x1d # macro +CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT = 0x1f # macro +CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK = 0x0FFFFFFF # macro +CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK = 0x10000000 # macro +CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK = 0x60000000 # macro +CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK = 0x80000000 # macro +CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT = 0x1e # macro +CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK = 0x40000000 # macro +CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT = 0x1e # macro +CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK = 0x40000000 # macro +CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT = 0x1e # macro +CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK = 0x40000000 # macro +CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT = 0x1e # macro +CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK = 0x40000000 # macro +CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT = 0x1e # macro +CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK = 0x40000000 # macro +CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT = 0x1e # macro +CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK = 0x40000000 # macro +CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_MES_GP0_LO__DATA__SHIFT = 0x1 # macro +CP_MES_GP0_LO__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_MES_GP0_LO__DATA_MASK = 0xFFFFFFFE # macro +CP_MES_GP0_HI__M_RET_ADDR__SHIFT = 0x0 # macro +CP_MES_GP0_HI__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT = 0x0 # macro +CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK = 0xFFFFFFFF # macro +CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT = 0x0 # macro +CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK = 0xFFFFFFFF # macro +CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT = 0x0 # macro +CP_MES_GP2_LO__STACK_PNTR_LO_MASK = 0xFFFFFFFF # macro +CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT = 0x0 # macro +CP_MES_GP2_HI__STACK_PNTR_HI_MASK = 0xFFFFFFFF # macro +CP_MES_GP3_LO__DATA__SHIFT = 0x0 # macro +CP_MES_GP3_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_GP3_HI__DATA__SHIFT = 0x0 # macro +CP_MES_GP3_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_GP4_LO__DATA__SHIFT = 0x0 # macro +CP_MES_GP4_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_GP4_HI__DATA__SHIFT = 0x0 # macro +CP_MES_GP4_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_MES_GP5_LO__DATA__SHIFT = 0x1 # macro +CP_MES_GP5_LO__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_MES_GP5_LO__DATA_MASK = 0xFFFFFFFE # macro +CP_MES_GP5_HI__M_RET_ADDR__SHIFT = 0x0 # macro +CP_MES_GP5_HI__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT = 0x0 # macro +CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK = 0xFFFFFFFF # macro +CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT = 0x0 # macro +CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK = 0xFFFFFFFF # macro +CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT = 0x0 # macro +CP_MES_GP7_LO__STACK_PNTR_LO_MASK = 0xFFFFFFFF # macro +CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT = 0x0 # macro +CP_MES_GP7_HI__STACK_PNTR_HI_MASK = 0xFFFFFFFF # macro +CP_MES_GP8_LO__DATA__SHIFT = 0x0 # macro +CP_MES_GP8_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_GP8_HI__DATA__SHIFT = 0x0 # macro +CP_MES_GP8_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_GP9_LO__DATA__SHIFT = 0x0 # macro +CP_MES_GP9_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_GP9_HI__DATA__SHIFT = 0x0 # macro +CP_MES_GP9_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT = 0x10 # macro +CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK = 0xFFFF0000 # macro +CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT = 0x0 # macro +CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK = 0x0000FFFF # macro +CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT = 0x10 # macro +CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK = 0xFFFF0000 # macro +CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT = 0x0 # macro +CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK = 0x0000FFFF # macro +CP_MES_LOCAL_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_MES_LOCAL_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT = 0x10 # macro +CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK = 0xFFFF0000 # macro +CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT = 0x0 # macro +CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK = 0x0000FFFF # macro +CP_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT = 0x0 # macro +CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK = 0x0000001F # macro +CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT = 0x0 # macro +CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK = 0xFFFFFFFF # macro +CP_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT = 0x0 # macro +CP_MES_PRGRM_CNTR_START_HI__IP_START_MASK = 0x3FFFFFFF # macro +CP_MES_INTERRUPT_DATA_16__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_16__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_17__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_17__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_18__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_18__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_19__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_19__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_20__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_20__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_21__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_21__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_22__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_22__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_23__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_23__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_24__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_24__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_25__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_25__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_26__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_26__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_27__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_27__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_28__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_28__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_29__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_29__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_30__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_30__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_INTERRUPT_DATA_31__DATA__SHIFT = 0x0 # macro +CP_MES_INTERRUPT_DATA_31__DATA_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE0_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE0_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE0_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE0_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE0_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE0_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE1_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE1_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE1_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE1_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE1_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE1_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE2_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE2_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE2_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE2_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE2_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE2_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE3_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE3_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE3_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE3_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE3_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE3_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE4_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE4_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE4_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE4_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE4_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE4_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE5_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE5_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE5_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE5_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE5_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE5_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE6_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE6_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE6_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE6_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE6_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE6_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE7_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE7_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE7_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE7_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE7_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE7_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE8_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE8_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE8_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE8_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE8_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE8_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE9_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE9_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE9_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE9_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE9_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE9_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE10_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE10_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE10_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE10_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE10_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE10_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE11_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE11_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE11_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE11_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE11_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE11_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE12_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE12_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE12_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE12_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE12_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE12_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE13_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE13_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE13_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE13_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE13_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE13_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE14_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE14_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE14_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE14_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE14_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE14_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MES_DC_APERTURE15_BASE__BASE__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE15_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE15_MASK__MASK__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE15_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MES_DC_APERTURE15_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MES_DC_APERTURE15_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_RS64_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_MEC_RS64_PRGRM_CNTR_START__IP_START_MASK = 0xFFFFFFFF # macro +CP_MEC_MTVEC_LO__ADDR_LO__SHIFT = 0x0 # macro +CP_MEC_MTVEC_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_MTVEC_HI__ADDR_LO__SHIFT = 0x0 # macro +CP_MEC_MTVEC_HI__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_ISA_CNTL__ISA_MODE__SHIFT = 0x0 # macro +CP_MEC_ISA_CNTL__ISA_MODE_MASK = 0x00000001 # macro +CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT = 0x4 # macro +CP_MEC_RS64_CNTL__MEC_PIPE0_RESET__SHIFT = 0x10 # macro +CP_MEC_RS64_CNTL__MEC_PIPE1_RESET__SHIFT = 0x11 # macro +CP_MEC_RS64_CNTL__MEC_PIPE2_RESET__SHIFT = 0x12 # macro +CP_MEC_RS64_CNTL__MEC_PIPE3_RESET__SHIFT = 0x13 # macro +CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE__SHIFT = 0x1a # macro +CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE__SHIFT = 0x1b # macro +CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE__SHIFT = 0x1c # macro +CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE__SHIFT = 0x1d # macro +CP_MEC_RS64_CNTL__MEC_HALT__SHIFT = 0x1e # macro +CP_MEC_RS64_CNTL__MEC_STEP__SHIFT = 0x1f # macro +CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK = 0x00000010 # macro +CP_MEC_RS64_CNTL__MEC_PIPE0_RESET_MASK = 0x00010000 # macro +CP_MEC_RS64_CNTL__MEC_PIPE1_RESET_MASK = 0x00020000 # macro +CP_MEC_RS64_CNTL__MEC_PIPE2_RESET_MASK = 0x00040000 # macro +CP_MEC_RS64_CNTL__MEC_PIPE3_RESET_MASK = 0x00080000 # macro +CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE_MASK = 0x04000000 # macro +CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE_MASK = 0x08000000 # macro +CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE_MASK = 0x10000000 # macro +CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE_MASK = 0x20000000 # macro +CP_MEC_RS64_CNTL__MEC_HALT_MASK = 0x40000000 # macro +CP_MEC_RS64_CNTL__MEC_STEP_MASK = 0x80000000 # macro +CP_MEC_MIE_LO__MEC_INT__SHIFT = 0x0 # macro +CP_MEC_MIE_LO__MEC_INT_MASK = 0xFFFFFFFF # macro +CP_MEC_MIE_HI__MEC_INT__SHIFT = 0x0 # macro +CP_MEC_MIE_HI__MEC_INT_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT__MEC_INT__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT__MEC_INT_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR_MASK = 0x000FFFFF # macro +CP_MEC_MIP_LO__MIP_LO__SHIFT = 0x0 # macro +CP_MEC_MIP_LO__MIP_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_MIP_HI__MIP_HI__SHIFT = 0x0 # macro +CP_MEC_MIP_HI__MIP_HI_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_MEC_DC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_BASE_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT = 0x0 # macro +CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT = 0x1 # macro +CP_MEC_DC_OP_CNTL__BYPASS_ALL__SHIFT = 0x2 # macro +CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_MASK = 0x00000001 # macro +CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK = 0x00000002 # macro +CP_MEC_DC_OP_CNTL__BYPASS_ALL_MASK = 0x00000004 # macro +CP_MEC_MTIMECMP_LO__TIME_LO__SHIFT = 0x0 # macro +CP_MEC_MTIMECMP_LO__TIME_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_MTIMECMP_HI__TIME_HI__SHIFT = 0x0 # macro +CP_MEC_MTIMECMP_HI__TIME_HI_MASK = 0xFFFFFFFF # macro +CP_MEC_GP0_LO__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_MEC_GP0_LO__DATA__SHIFT = 0x1 # macro +CP_MEC_GP0_LO__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_MEC_GP0_LO__DATA_MASK = 0xFFFFFFFE # macro +CP_MEC_GP0_HI__M_RET_ADDR__SHIFT = 0x0 # macro +CP_MEC_GP0_HI__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_MEC_GP1_LO__RD_WR_SELECT_LO__SHIFT = 0x0 # macro +CP_MEC_GP1_LO__RD_WR_SELECT_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_GP1_HI__RD_WR_SELECT_HI__SHIFT = 0x0 # macro +CP_MEC_GP1_HI__RD_WR_SELECT_HI_MASK = 0xFFFFFFFF # macro +CP_MEC_GP2_LO__STACK_PNTR_LO__SHIFT = 0x0 # macro +CP_MEC_GP2_LO__STACK_PNTR_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_GP2_HI__STACK_PNTR_HI__SHIFT = 0x0 # macro +CP_MEC_GP2_HI__STACK_PNTR_HI_MASK = 0xFFFFFFFF # macro +CP_MEC_GP3_LO__DATA__SHIFT = 0x0 # macro +CP_MEC_GP3_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_GP3_HI__DATA__SHIFT = 0x0 # macro +CP_MEC_GP3_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_GP4_LO__DATA__SHIFT = 0x0 # macro +CP_MEC_GP4_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_GP4_HI__DATA__SHIFT = 0x0 # macro +CP_MEC_GP4_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_GP5_LO__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_MEC_GP5_LO__DATA__SHIFT = 0x1 # macro +CP_MEC_GP5_LO__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_MEC_GP5_LO__DATA_MASK = 0xFFFFFFFE # macro +CP_MEC_GP5_HI__M_RET_ADDR__SHIFT = 0x0 # macro +CP_MEC_GP5_HI__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_MEC_GP6_LO__RD_WR_SELECT_LO__SHIFT = 0x0 # macro +CP_MEC_GP6_LO__RD_WR_SELECT_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_GP6_HI__RD_WR_SELECT_HI__SHIFT = 0x0 # macro +CP_MEC_GP6_HI__RD_WR_SELECT_HI_MASK = 0xFFFFFFFF # macro +CP_MEC_GP7_LO__STACK_PNTR_LO__SHIFT = 0x0 # macro +CP_MEC_GP7_LO__STACK_PNTR_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_GP7_HI__STACK_PNTR_HI__SHIFT = 0x0 # macro +CP_MEC_GP7_HI__STACK_PNTR_HI_MASK = 0xFFFFFFFF # macro +CP_MEC_GP8_LO__DATA__SHIFT = 0x0 # macro +CP_MEC_GP8_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_GP8_HI__DATA__SHIFT = 0x0 # macro +CP_MEC_GP8_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_GP9_LO__DATA__SHIFT = 0x0 # macro +CP_MEC_GP9_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_GP9_HI__DATA__SHIFT = 0x0 # macro +CP_MEC_GP9_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_LOCAL_BASE0_LO__BASE0_LO__SHIFT = 0x10 # macro +CP_MEC_LOCAL_BASE0_LO__BASE0_LO_MASK = 0xFFFF0000 # macro +CP_MEC_LOCAL_BASE0_HI__BASE0_HI__SHIFT = 0x0 # macro +CP_MEC_LOCAL_BASE0_HI__BASE0_HI_MASK = 0x0000FFFF # macro +CP_MEC_LOCAL_MASK0_LO__MASK0_LO__SHIFT = 0x10 # macro +CP_MEC_LOCAL_MASK0_LO__MASK0_LO_MASK = 0xFFFF0000 # macro +CP_MEC_LOCAL_MASK0_HI__MASK0_HI__SHIFT = 0x0 # macro +CP_MEC_LOCAL_MASK0_HI__MASK0_HI_MASK = 0x0000FFFF # macro +CP_MEC_LOCAL_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_MEC_LOCAL_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT = 0x10 # macro +CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO_MASK = 0xFFFF0000 # macro +CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT = 0x0 # macro +CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI_MASK = 0x0000FFFF # macro +CP_MEC_LOCAL_INSTR_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_MEC_LOCAL_INSTR_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT = 0x0 # macro +CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK = 0x0000001F # macro +CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT = 0x0 # macro +CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT = 0x0 # macro +CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START_MASK = 0x3FFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_16__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_16__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_17__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_17__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_18__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_18__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_19__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_19__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_20__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_20__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_21__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_21__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_22__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_22__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_23__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_23__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_24__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_24__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_25__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_25__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_26__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_26__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_27__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_27__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_28__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_28__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_29__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_29__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_30__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_30__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_RS64_INTERRUPT_DATA_31__DATA__SHIFT = 0x0 # macro +CP_MEC_RS64_INTERRUPT_DATA_31__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE0_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE0_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE0_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE0_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE0_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE0_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE1_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE1_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE1_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE1_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE1_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE1_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE2_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE2_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE2_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE2_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE2_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE2_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE3_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE3_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE3_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE3_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE3_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE3_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE4_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE4_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE4_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE4_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE4_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE4_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE5_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE5_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE5_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE5_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE5_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE5_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE6_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE6_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE6_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE6_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE6_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE6_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE7_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE7_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE7_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE7_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE7_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE7_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE8_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE8_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE8_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE8_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE8_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE8_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE9_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE9_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE9_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE9_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE9_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE9_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE10_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE10_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE10_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE10_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE10_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE10_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE11_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE11_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE11_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE11_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE11_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE11_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE12_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE12_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE12_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE12_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE12_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE12_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE13_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE13_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE13_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE13_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE13_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE13_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE14_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE14_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE14_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE14_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE14_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE14_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_MEC_DC_APERTURE15_BASE__BASE__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE15_BASE__BASE_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE15_MASK__MASK__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE15_MASK__MASK_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_APERTURE15_CNTL__VMID__SHIFT = 0x0 # macro +CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT = 0x4 # macro +CP_MEC_DC_APERTURE15_CNTL__VMID_MASK = 0x0000000F # macro +CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE_MASK = 0x00000010 # macro +CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT = 0x0 # macro +CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT = 0x1 # macro +CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT = 0x4 # macro +CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT = 0x5 # macro +CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK = 0x00000001 # macro +CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK = 0x00000002 # macro +CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK = 0x00000010 # macro +CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK = 0x00000020 # macro +CP_GFX_CNTL__ENGINE_SEL__SHIFT = 0x0 # macro +CP_GFX_CNTL__CONFIG__SHIFT = 0x1 # macro +CP_GFX_CNTL__ENGINE_SEL_MASK = 0x00000001 # macro +CP_GFX_CNTL__CONFIG_MASK = 0x00000006 # macro +CP_GFX_RS64_INTERRUPT0__ME_INT__SHIFT = 0x0 # macro +CP_GFX_RS64_INTERRUPT0__ME_INT_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_INTR_EN0__ME_INT__SHIFT = 0x0 # macro +CP_GFX_RS64_INTR_EN0__ME_INT_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_INTR_EN1__ME_INT__SHIFT = 0x0 # macro +CP_GFX_RS64_INTR_EN1__ME_INT_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_GFX_RS64_DC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT = 0x1 # macro +CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL__SHIFT = 0x2 # macro +CP_GFX_RS64_DC_OP_CNTL__RESERVED__SHIFT = 0x3 # macro +CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED__SHIFT = 0x5 # macro +CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_MASK = 0x00000001 # macro +CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK = 0x00000002 # macro +CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL_MASK = 0x00000004 # macro +CP_GFX_RS64_DC_OP_CNTL__RESERVED_MASK = 0x00000008 # macro +CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED_MASK = 0x00000020 # macro +CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO__SHIFT = 0x10 # macro +CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO_MASK = 0xFFFF0000 # macro +CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI_MASK = 0x0000FFFF # macro +CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO__SHIFT = 0x10 # macro +CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO_MASK = 0xFFFF0000 # macro +CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI_MASK = 0x0000FFFF # macro +CP_GFX_RS64_LOCAL_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT = 0x10 # macro +CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO_MASK = 0xFFFF0000 # macro +CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI_MASK = 0x0000FFFF # macro +CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE_MASK = 0x00000007 # macro +CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL__SHIFT = 0x0 # macro +CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL_MASK = 0x0000001F # macro +CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL__SHIFT = 0x0 # macro +CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL_MASK = 0x0000001F # macro +CP_GFX_RS64_MIP_LO0__MIP_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_MIP_LO0__MIP_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MIP_LO1__MIP_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_MIP_LO1__MIP_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MIP_HI0__MIP_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_MIP_HI0__MIP_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MIP_HI1__MIP_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_MIP_HI1__MIP_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MTIMECMP_LO0__TIME_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_MTIMECMP_LO0__TIME_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MTIMECMP_LO1__TIME_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_MTIMECMP_LO1__TIME_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MTIMECMP_HI0__TIME_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_MTIMECMP_HI0__TIME_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MTIMECMP_HI1__TIME_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_MTIMECMP_HI1__TIME_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_GFX_RS64_GP0_LO0__DATA__SHIFT = 0x1 # macro +CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_GFX_RS64_GP0_LO0__DATA_MASK = 0xFFFFFFFE # macro +CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_GFX_RS64_GP0_LO1__DATA__SHIFT = 0x1 # macro +CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_GFX_RS64_GP0_LO1__DATA_MASK = 0xFFFFFFFE # macro +CP_GFX_RS64_GP0_HI0__M_RET_ADDR__SHIFT = 0x0 # macro +CP_GFX_RS64_GP0_HI0__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP0_HI1__M_RET_ADDR__SHIFT = 0x0 # macro +CP_GFX_RS64_GP0_HI1__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP3_LO0__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP3_LO0__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP3_LO1__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP3_LO1__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP3_HI0__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP3_HI0__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP3_HI1__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP3_HI1__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP4_LO0__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP4_LO0__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP4_LO1__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP4_LO1__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP4_HI0__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP4_HI0__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP4_HI1__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP4_HI1__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_GFX_RS64_GP5_LO0__DATA__SHIFT = 0x1 # macro +CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_GFX_RS64_GP5_LO0__DATA_MASK = 0xFFFFFFFE # macro +CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED__SHIFT = 0x0 # macro +CP_GFX_RS64_GP5_LO1__DATA__SHIFT = 0x1 # macro +CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED_MASK = 0x00000001 # macro +CP_GFX_RS64_GP5_LO1__DATA_MASK = 0xFFFFFFFE # macro +CP_GFX_RS64_GP5_HI0__M_RET_ADDR__SHIFT = 0x0 # macro +CP_GFX_RS64_GP5_HI0__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP5_HI1__M_RET_ADDR__SHIFT = 0x0 # macro +CP_GFX_RS64_GP5_HI1__M_RET_ADDR_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP7_LO__STACK_PNTR_LO__SHIFT = 0x0 # macro +CP_GFX_RS64_GP7_LO__STACK_PNTR_LO_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP7_HI__STACK_PNTR_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_GP7_HI__STACK_PNTR_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP8_LO__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP8_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP8_HI__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP8_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP9_LO__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP9_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_GP9_HI__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_GP9_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR__SHIFT = 0x0 # macro +CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR_MASK = 0x000FFFFF # macro +CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR__SHIFT = 0x0 # macro +CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR_MASK = 0x000FFFFF # macro +CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT__SHIFT = 0x0 # macro +CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT__SHIFT = 0x0 # macro +CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE0_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE0_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE0_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE0_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE1_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE1_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE1_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE1_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE2_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE2_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE2_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE2_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE3_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE3_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE3_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE3_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE4_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE4_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE4_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE4_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE5_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE5_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE5_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE5_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE6_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE6_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE6_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE6_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE7_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE7_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE7_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE7_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE8_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE8_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE8_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE8_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE9_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE9_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE9_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE9_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE10_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE10_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE10_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE10_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE11_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE11_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE11_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE11_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE12_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE12_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE12_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE12_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE13_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE13_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE13_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE13_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE14_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE14_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE14_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE14_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE15_BASE0__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE15_BASE0__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE15_MASK0__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE15_MASK0__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE0_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE0_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE0_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE0_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE1_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE1_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE1_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE1_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE2_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE2_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE2_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE2_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE3_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE3_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE3_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE3_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE4_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE4_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE4_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE4_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE5_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE5_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE5_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE5_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE6_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE6_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE6_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE6_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE7_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE7_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE7_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE7_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE8_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE8_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE8_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE8_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE9_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE9_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE9_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE9_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE10_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE10_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE10_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE10_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE11_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE11_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE11_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE11_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE12_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE12_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE12_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE12_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE13_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE13_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE13_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE13_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE14_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE14_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE14_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE14_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_DC_APERTURE15_BASE1__BASE__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE15_BASE1__BASE_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE15_MASK1__MASK__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE15_MASK1__MASK_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE__SHIFT = 0x4 # macro +CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID_MASK = 0x0000000F # macro +CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE_MASK = 0x00000010 # macro +CP_GFX_RS64_INTERRUPT1__ME_INT__SHIFT = 0x0 # macro +CP_GFX_RS64_INTERRUPT1__ME_INT_MASK = 0xFFFFFFFF # macro +GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT = 0x0 # macro +GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK = 0x000000FF # macro +GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT = 0x0 # macro +GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT = 0x1 # macro +GL1_ARB_STATUS__REQ_ARB_BUSY_MASK = 0x00000001 # macro +GL1_ARB_STATUS__RET_ARB_BUSY_MASK = 0x00000002 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE__SHIFT = 0x0 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE__SHIFT = 0x1 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE__SHIFT = 0x2 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE__SHIFT = 0x3 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE_MASK = 0x00000001 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE_MASK = 0x00000002 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE_MASK = 0x00000004 # macro +GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE_MASK = 0x00000008 # macro +GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT = 0x0 # macro +GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT = 0x1 # macro +GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT = 0x2 # macro +GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT = 0x3 # macro +GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT = 0x4 # macro +GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT = 0x5 # macro +GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT = 0x6 # macro +GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT = 0x7 # macro +GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT = 0x8 # macro +GL1C_STATUS__GL2_RH_BUSY__SHIFT = 0x9 # macro +GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT = 0xa # macro +GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT = 0x14 # macro +GL1C_STATUS__TAG_STALL__SHIFT = 0x15 # macro +GL1C_STATUS__TAG_BUSY__SHIFT = 0x16 # macro +GL1C_STATUS__TAG_ACK_STALL__SHIFT = 0x17 # macro +GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT = 0x18 # macro +GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT = 0x19 # macro +GL1C_STATUS__TAG_EVICT__SHIFT = 0x1a # macro +GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT = 0x1b # macro +GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT = 0x1f # macro +GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK = 0x00000001 # macro +GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK = 0x00000002 # macro +GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK = 0x00000004 # macro +GL1C_STATUS__GL2_REQ_VC0_STALL_MASK = 0x00000008 # macro +GL1C_STATUS__GL2_DATA_VC0_STALL_MASK = 0x00000010 # macro +GL1C_STATUS__GL2_REQ_VC1_STALL_MASK = 0x00000020 # macro +GL1C_STATUS__GL2_DATA_VC1_STALL_MASK = 0x00000040 # macro +GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK = 0x00000080 # macro +GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK = 0x00000100 # macro +GL1C_STATUS__GL2_RH_BUSY_MASK = 0x00000200 # macro +GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK = 0x000FFC00 # macro +GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK = 0x00100000 # macro +GL1C_STATUS__TAG_STALL_MASK = 0x00200000 # macro +GL1C_STATUS__TAG_BUSY_MASK = 0x00400000 # macro +GL1C_STATUS__TAG_ACK_STALL_MASK = 0x00800000 # macro +GL1C_STATUS__TAG_GCR_INV_STALL_MASK = 0x01000000 # macro +GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK = 0x02000000 # macro +GL1C_STATUS__TAG_EVICT_MASK = 0x04000000 # macro +GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK = 0x78000000 # macro +GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK = 0x80000000 # macro +GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +GL1C_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT = 0x1 # macro +GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +GL1C_UTCL0_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +GL1C_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +GL1C_UTCL0_CNTL1__CLIENTID__SHIFT = 0x7 # macro +GL1C_UTCL0_CNTL1__REG_INV_VMID__SHIFT = 0x13 # macro +GL1C_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT = 0x18 # macro +GL1C_UTCL0_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +GL1C_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT = 0x1b # macro +GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +GL1C_UTCL0_CNTL1__GPUVM_64K_DEF_MASK = 0x00000002 # macro +GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +GL1C_UTCL0_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +GL1C_UTCL0_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +GL1C_UTCL0_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +GL1C_UTCL0_CNTL1__REG_INV_VMID_MASK = 0x00780000 # macro +GL1C_UTCL0_CNTL1__REG_INV_TOGGLE_MASK = 0x01000000 # macro +GL1C_UTCL0_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +GL1C_UTCL0_CNTL1__FORCE_IN_ORDER_MASK = 0x06000000 # macro +GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +GL1C_UTCL0_CNTL2__SPARE__SHIFT = 0x0 # macro +GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT = 0x8 # macro +GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +GL1C_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT = 0xa # macro +GL1C_UTCL0_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +GL1C_UTCL0_CNTL2__DISABLE_BURST__SHIFT = 0x11 # macro +GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +GL1C_UTCL0_CNTL2__FGCG_DISABLE__SHIFT = 0x1e # macro +GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT = 0x1f # macro +GL1C_UTCL0_CNTL2__SPARE_MASK = 0x000000FF # macro +GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK = 0x00000100 # macro +GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +GL1C_UTCL0_CNTL2__ANY_LINE_VALID_MASK = 0x00000400 # macro +GL1C_UTCL0_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +GL1C_UTCL0_CNTL2__DISABLE_BURST_MASK = 0x00020000 # macro +GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +GL1C_UTCL0_CNTL2__FGCG_DISABLE_MASK = 0x40000000 # macro +GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK = 0x80000000 # macro +GL1C_UTCL0_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +GL1C_UTCL0_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +GL1C_UTCL0_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +GL1C_UTCL0_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +GL1C_UTCL0_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +GL1C_UTCL0_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +GL1C_UTCL0_RETRY__INCR__SHIFT = 0x0 # macro +GL1C_UTCL0_RETRY__COUNT__SHIFT = 0x8 # macro +GL1C_UTCL0_RETRY__INCR_MASK = 0x000000FF # macro +GL1C_UTCL0_RETRY__COUNT_MASK = 0x00000F00 # macro +CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT = 0x0 # macro +CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT = 0x2 # macro +CH_ARB_CTRL__FGCG_DISABLE__SHIFT = 0x3 # macro +CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT = 0x4 # macro +CH_ARB_CTRL__CHICKEN_BITS__SHIFT = 0x5 # macro +CH_ARB_CTRL__NUM_MEM_PIPES_MASK = 0x00000003 # macro +CH_ARB_CTRL__UC_IO_WR_PATH_MASK = 0x00000004 # macro +CH_ARB_CTRL__FGCG_DISABLE_MASK = 0x00000008 # macro +CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK = 0x00000010 # macro +CH_ARB_CTRL__CHICKEN_BITS_MASK = 0x00001FE0 # macro +CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT = 0x0 # macro +CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK = 0x000000FF # macro +CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT = 0x0 # macro +CH_ARB_STATUS__RET_ARB_BUSY__SHIFT = 0x1 # macro +CH_ARB_STATUS__REQ_ARB_BUSY_MASK = 0x00000001 # macro +CH_ARB_STATUS__RET_ARB_BUSY_MASK = 0x00000002 # macro +CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT = 0x0 # macro +CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT = 0x3 # macro +CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT = 0x4 # macro +CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT = 0x5 # macro +CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT = 0x6 # macro +CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE__SHIFT = 0x7 # macro +CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT = 0x8 # macro +CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK = 0x00000007 # macro +CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK = 0x00000008 # macro +CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK = 0x00000010 # macro +CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK = 0x00000020 # macro +CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK = 0x00000040 # macro +CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE_MASK = 0x00000080 # macro +CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK = 0x00000100 # macro +CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT = 0x0 # macro +CHA_CHC_CREDITS__CHCG_REQ_CREDITS__SHIFT = 0x8 # macro +CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK = 0x000000FF # macro +CHA_CHC_CREDITS__CHCG_REQ_CREDITS_MASK = 0x0000FF00 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT = 0x0 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT = 0x3 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT = 0x6 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT = 0x9 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT = 0xc # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK = 0x00000007 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK = 0x00000038 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK = 0x000001C0 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK = 0x00000E00 # macro +CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK = 0x00007000 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE__SHIFT = 0x0 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE__SHIFT = 0x1 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE__SHIFT = 0x2 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE__SHIFT = 0x3 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE_MASK = 0x00000001 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE_MASK = 0x00000002 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE_MASK = 0x00000004 # macro +CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE_MASK = 0x00000008 # macro +CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT = 0x1 # macro +CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK = 0x00000002 # macro +CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT = 0x0 # macro +CHC_CTRL__GL2_REQ_CREDITS__SHIFT = 0x4 # macro +CHC_CTRL__GL2_DATA_CREDITS__SHIFT = 0xb # macro +CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT = 0x12 # macro +CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT = 0x13 # macro +CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT__SHIFT = 0x1d # macro +CHC_CTRL__BUFFER_DEPTH_MAX_MASK = 0x0000000F # macro +CHC_CTRL__GL2_REQ_CREDITS_MASK = 0x000007F0 # macro +CHC_CTRL__GL2_DATA_CREDITS_MASK = 0x0003F800 # macro +CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK = 0x00040000 # macro +CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK = 0x00080000 # macro +CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT_MASK = 0x20000000 # macro +CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT = 0x0 # macro +CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT = 0x1 # macro +CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT = 0x2 # macro +CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT = 0x3 # macro +CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT = 0x4 # macro +CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT = 0x5 # macro +CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT = 0x6 # macro +CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT = 0x7 # macro +CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT = 0x8 # macro +CHC_STATUS__GL2_RH_BUSY__SHIFT = 0x9 # macro +CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT = 0xa # macro +CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT = 0x14 # macro +CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT = 0x15 # macro +CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT = 0x16 # macro +CHC_STATUS__BUFFER_FULL__SHIFT = 0x17 # macro +CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK = 0x00000001 # macro +CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK = 0x00000002 # macro +CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK = 0x00000004 # macro +CHC_STATUS__GL2_REQ_VC0_STALL_MASK = 0x00000008 # macro +CHC_STATUS__GL2_DATA_VC0_STALL_MASK = 0x00000010 # macro +CHC_STATUS__GL2_REQ_VC1_STALL_MASK = 0x00000020 # macro +CHC_STATUS__GL2_DATA_VC1_STALL_MASK = 0x00000040 # macro +CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK = 0x00000080 # macro +CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK = 0x00000100 # macro +CHC_STATUS__GL2_RH_BUSY_MASK = 0x00000200 # macro +CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK = 0x000FFC00 # macro +CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK = 0x00100000 # macro +CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK = 0x00200000 # macro +CHC_STATUS__REQUEST_TRACKER_BUSY_MASK = 0x00400000 # macro +CHC_STATUS__BUFFER_FULL_MASK = 0x00800000 # macro +CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT = 0x0 # macro +CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT = 0x4 # macro +CHCG_CTRL__GL2_REQ_CREDITS__SHIFT = 0x8 # macro +CHCG_CTRL__GL2_DATA_CREDITS__SHIFT = 0xf # macro +CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT = 0x16 # macro +CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT = 0x17 # macro +CHCG_CTRL__BUFFER_DEPTH_MAX_MASK = 0x0000000F # macro +CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK = 0x000000F0 # macro +CHCG_CTRL__GL2_REQ_CREDITS_MASK = 0x00007F00 # macro +CHCG_CTRL__GL2_DATA_CREDITS_MASK = 0x003F8000 # macro +CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK = 0x00400000 # macro +CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK = 0x00800000 # macro +CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT = 0x0 # macro +CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT = 0x1 # macro +CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT = 0x2 # macro +CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT = 0x3 # macro +CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT = 0x4 # macro +CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT = 0x5 # macro +CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT = 0x6 # macro +CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT = 0x7 # macro +CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT = 0x8 # macro +CHCG_STATUS__GL2_RH_BUSY__SHIFT = 0x9 # macro +CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT = 0xa # macro +CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT = 0x14 # macro +CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT = 0x15 # macro +CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT = 0x16 # macro +CHCG_STATUS__BUFFER_FULL__SHIFT = 0x17 # macro +CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT = 0x18 # macro +CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT = 0x19 # macro +CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT = 0x1a # macro +CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT = 0x1b # macro +CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK = 0x00000001 # macro +CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK = 0x00000002 # macro +CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK = 0x00000004 # macro +CHCG_STATUS__GL2_REQ_VC0_STALL_MASK = 0x00000008 # macro +CHCG_STATUS__GL2_DATA_VC0_STALL_MASK = 0x00000010 # macro +CHCG_STATUS__GL2_REQ_VC1_STALL_MASK = 0x00000020 # macro +CHCG_STATUS__GL2_DATA_VC1_STALL_MASK = 0x00000040 # macro +CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK = 0x00000080 # macro +CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK = 0x00000100 # macro +CHCG_STATUS__GL2_RH_BUSY_MASK = 0x00000200 # macro +CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK = 0x000FFC00 # macro +CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK = 0x00100000 # macro +CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK = 0x00200000 # macro +CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK = 0x00400000 # macro +CHCG_STATUS__BUFFER_FULL_MASK = 0x00800000 # macro +CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK = 0x01000000 # macro +CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK = 0x02000000 # macro +CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK = 0x04000000 # macro +CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK = 0x08000000 # macro +GL2C_CTRL__CACHE_SIZE__SHIFT = 0x0 # macro +GL2C_CTRL__RATE__SHIFT = 0x2 # macro +GL2C_CTRL__WRITEBACK_MARGIN__SHIFT = 0x4 # macro +GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT = 0x8 # macro +GL2C_CTRL__SRC_FIFO_SIZE__SHIFT = 0xc # macro +GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT = 0x10 # macro +GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT = 0x14 # macro +GL2C_CTRL__LINEAR_SET_HASH__SHIFT = 0x15 # macro +GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT = 0x16 # macro +GL2C_CTRL__MDC_SIZE__SHIFT = 0x18 # macro +GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT = 0x1a # macro +GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT = 0x1b # macro +GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT = 0x1c # macro +GL2C_CTRL__CACHE_SIZE_MASK = 0x00000003 # macro +GL2C_CTRL__RATE_MASK = 0x0000000C # macro +GL2C_CTRL__WRITEBACK_MARGIN_MASK = 0x000000F0 # macro +GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK = 0x00000F00 # macro +GL2C_CTRL__SRC_FIFO_SIZE_MASK = 0x0000F000 # macro +GL2C_CTRL__LATENCY_FIFO_SIZE_MASK = 0x000F0000 # macro +GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK = 0x00100000 # macro +GL2C_CTRL__LINEAR_SET_HASH_MASK = 0x00200000 # macro +GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK = 0x00C00000 # macro +GL2C_CTRL__MDC_SIZE_MASK = 0x03000000 # macro +GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK = 0x04000000 # macro +GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK = 0x08000000 # macro +GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK = 0xF0000000 # macro +GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT = 0x0 # macro +GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT = 0x4 # macro +GL2C_CTRL2__FILL_SIZE_32__SHIFT = 0x5 # macro +GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT = 0x6 # macro +GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT = 0x7 # macro +GL2C_CTRL2__RO_DISABLE__SHIFT = 0x8 # macro +GL2C_CTRL2__FORCE_MDC_INV__SHIFT = 0x9 # macro +GL2C_CTRL2__GCR_ARB_CTRL__SHIFT = 0xa # macro +GL2C_CTRL2__GCR_ALL_SET__SHIFT = 0xd # macro +GL2C_CTRL2__FILL_SIZE_64__SHIFT = 0x11 # macro +GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT = 0x12 # macro +GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT = 0x13 # macro +GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT = 0x14 # macro +GL2C_CTRL2__RB_VOLATILE_EN__SHIFT = 0x15 # macro +GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT = 0x16 # macro +GL2C_CTRL2__MAX_MIN_CTRL__SHIFT = 0x17 # macro +GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT = 0x1a # macro +GL2C_CTRL2__PROBE_FIFO_SIZE_MASK = 0x0000000F # macro +GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK = 0x00000010 # macro +GL2C_CTRL2__FILL_SIZE_32_MASK = 0x00000020 # macro +GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK = 0x00000040 # macro +GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK = 0x00000080 # macro +GL2C_CTRL2__RO_DISABLE_MASK = 0x00000100 # macro +GL2C_CTRL2__FORCE_MDC_INV_MASK = 0x00000200 # macro +GL2C_CTRL2__GCR_ARB_CTRL_MASK = 0x00001C00 # macro +GL2C_CTRL2__GCR_ALL_SET_MASK = 0x00002000 # macro +GL2C_CTRL2__FILL_SIZE_64_MASK = 0x00020000 # macro +GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK = 0x00040000 # macro +GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK = 0x00080000 # macro +GL2C_CTRL2__METADATA_VOLATILE_EN_MASK = 0x00100000 # macro +GL2C_CTRL2__RB_VOLATILE_EN_MASK = 0x00200000 # macro +GL2C_CTRL2__PROBE_UNSHARED_EN_MASK = 0x00400000 # macro +GL2C_CTRL2__MAX_MIN_CTRL_MASK = 0x01800000 # macro +GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK = 0x04000000 # macro +GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT = 0x0 # macro +GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK = 0xFFFFFFFF # macro +GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT = 0x0 # macro +GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK = 0x00000007 # macro +GL2C_WBINVL2__DONE__SHIFT = 0x4 # macro +GL2C_WBINVL2__DONE_MASK = 0x00000010 # macro +GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT = 0x0 # macro +GL2C_SOFT_RESET__HALT_FOR_RESET_MASK = 0x00000001 # macro +GL2C_CM_CTRL1__BURST_TIMER__SHIFT = 0x8 # macro +GL2C_CM_CTRL1__RVF_SIZE__SHIFT = 0x10 # macro +GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT = 0x17 # macro +GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT = 0x19 # macro +GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT = 0x1a # macro +GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT = 0x1b # macro +GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT = 0x1c # macro +GL2C_CM_CTRL1__BURST_MODE__SHIFT = 0x1d # macro +GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT = 0x1e # macro +GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT = 0x1f # macro +GL2C_CM_CTRL1__BURST_TIMER_MASK = 0x0000FF00 # macro +GL2C_CM_CTRL1__RVF_SIZE_MASK = 0x000F0000 # macro +GL2C_CM_CTRL1__WRITE_COH_MODE_MASK = 0x01800000 # macro +GL2C_CM_CTRL1__MDC_ARB_MODE_MASK = 0x02000000 # macro +GL2C_CM_CTRL1__READ_REQ_ONLY_MASK = 0x04000000 # macro +GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK = 0x08000000 # macro +GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK = 0x10000000 # macro +GL2C_CM_CTRL1__BURST_MODE_MASK = 0x20000000 # macro +GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK = 0x40000000 # macro +GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK = 0x80000000 # macro +GL2C_CM_STALL__QUEUE__SHIFT = 0x0 # macro +GL2C_CM_STALL__QUEUE_MASK = 0xFFFFFFFF # macro +GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT = 0x0 # macro +GL2C_CTRL3__METADATA_NOFILL__SHIFT = 0x3 # macro +GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT = 0x4 # macro +GL2C_CTRL3__BANK_LINEAR_HASH_MODE__SHIFT = 0x5 # macro +GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT = 0x6 # macro +GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT = 0x7 # macro +GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT = 0x8 # macro +GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT = 0x9 # macro +GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT = 0xa # macro +GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT = 0xb # macro +GL2C_CTRL3__HASH_256B_ENABLE__SHIFT = 0xc # macro +GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE__SHIFT = 0xd # macro +GL2C_CTRL3__FORCE_READ_ON_WRITE_OP__SHIFT = 0xe # macro +GL2C_CTRL3__FGCG_OVERRIDE__SHIFT = 0xf # macro +GL2C_CTRL3__FORCE_MTYPE_UC__SHIFT = 0x10 # macro +GL2C_CTRL3__DGPU_SHARED_MODE__SHIFT = 0x11 # macro +GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN__SHIFT = 0x12 # macro +GL2C_CTRL3__EA_READ_SIZE_LIMIT__SHIFT = 0x13 # macro +GL2C_CTRL3__READ_BYPASS_AS_UC__SHIFT = 0x14 # macro +GL2C_CTRL3__WB_OPT_ENABLE__SHIFT = 0x15 # macro +GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT__SHIFT = 0x16 # macro +GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE__SHIFT = 0x18 # macro +GL2C_CTRL3__EA_GMI_DISABLE__SHIFT = 0x19 # macro +GL2C_CTRL3__SQC_TO_HI_PRIORITY__SHIFT = 0x1a # macro +GL2C_CTRL3__INF_NAN_CLAMP__SHIFT = 0x1b # macro +GL2C_CTRL3__SCRATCH__SHIFT = 0x1c # macro +GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK = 0x00000003 # macro +GL2C_CTRL3__METADATA_NOFILL_MASK = 0x00000008 # macro +GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK = 0x00000010 # macro +GL2C_CTRL3__BANK_LINEAR_HASH_MODE_MASK = 0x00000020 # macro +GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK = 0x00000040 # macro +GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK = 0x00000080 # macro +GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK = 0x00000100 # macro +GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK = 0x00000200 # macro +GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK = 0x00000400 # macro +GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK = 0x00000800 # macro +GL2C_CTRL3__HASH_256B_ENABLE_MASK = 0x00001000 # macro +GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE_MASK = 0x00002000 # macro +GL2C_CTRL3__FORCE_READ_ON_WRITE_OP_MASK = 0x00004000 # macro +GL2C_CTRL3__FGCG_OVERRIDE_MASK = 0x00008000 # macro +GL2C_CTRL3__FORCE_MTYPE_UC_MASK = 0x00010000 # macro +GL2C_CTRL3__DGPU_SHARED_MODE_MASK = 0x00020000 # macro +GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN_MASK = 0x00040000 # macro +GL2C_CTRL3__EA_READ_SIZE_LIMIT_MASK = 0x00080000 # macro +GL2C_CTRL3__READ_BYPASS_AS_UC_MASK = 0x00100000 # macro +GL2C_CTRL3__WB_OPT_ENABLE_MASK = 0x00200000 # macro +GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT_MASK = 0x00C00000 # macro +GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE_MASK = 0x01000000 # macro +GL2C_CTRL3__EA_GMI_DISABLE_MASK = 0x02000000 # macro +GL2C_CTRL3__SQC_TO_HI_PRIORITY_MASK = 0x04000000 # macro +GL2C_CTRL3__INF_NAN_CLAMP_MASK = 0x08000000 # macro +GL2C_CTRL3__SCRATCH_MASK = 0xF0000000 # macro +GL2C_LB_CTR_CTRL__START__SHIFT = 0x0 # macro +GL2C_LB_CTR_CTRL__LOAD__SHIFT = 0x1 # macro +GL2C_LB_CTR_CTRL__CLEAR__SHIFT = 0x2 # macro +GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT = 0x1f # macro +GL2C_LB_CTR_CTRL__START_MASK = 0x00000001 # macro +GL2C_LB_CTR_CTRL__LOAD_MASK = 0x00000002 # macro +GL2C_LB_CTR_CTRL__CLEAR_MASK = 0x00000004 # macro +GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK = 0x80000000 # macro +GL2C_LB_DATA0__DATA__SHIFT = 0x0 # macro +GL2C_LB_DATA0__DATA_MASK = 0xFFFFFFFF # macro +GL2C_LB_DATA1__DATA__SHIFT = 0x0 # macro +GL2C_LB_DATA1__DATA_MASK = 0xFFFFFFFF # macro +GL2C_LB_DATA2__DATA__SHIFT = 0x0 # macro +GL2C_LB_DATA2__DATA_MASK = 0xFFFFFFFF # macro +GL2C_LB_DATA3__DATA__SHIFT = 0x0 # macro +GL2C_LB_DATA3__DATA_MASK = 0xFFFFFFFF # macro +GL2C_LB_CTR_SEL0__SEL0__SHIFT = 0x0 # macro +GL2C_LB_CTR_SEL0__DIV0__SHIFT = 0xf # macro +GL2C_LB_CTR_SEL0__SEL1__SHIFT = 0x10 # macro +GL2C_LB_CTR_SEL0__DIV1__SHIFT = 0x1f # macro +GL2C_LB_CTR_SEL0__SEL0_MASK = 0x000000FF # macro +GL2C_LB_CTR_SEL0__DIV0_MASK = 0x00008000 # macro +GL2C_LB_CTR_SEL0__SEL1_MASK = 0x00FF0000 # macro +GL2C_LB_CTR_SEL0__DIV1_MASK = 0x80000000 # macro +GL2C_LB_CTR_SEL1__SEL2__SHIFT = 0x0 # macro +GL2C_LB_CTR_SEL1__DIV2__SHIFT = 0xf # macro +GL2C_LB_CTR_SEL1__SEL3__SHIFT = 0x10 # macro +GL2C_LB_CTR_SEL1__DIV3__SHIFT = 0x1f # macro +GL2C_LB_CTR_SEL1__SEL2_MASK = 0x000000FF # macro +GL2C_LB_CTR_SEL1__DIV2_MASK = 0x00008000 # macro +GL2C_LB_CTR_SEL1__SEL3_MASK = 0x00FF0000 # macro +GL2C_LB_CTR_SEL1__DIV3_MASK = 0x80000000 # macro +GL2C_CTRL4__METADATA_WR_OP_CID__SHIFT = 0x0 # macro +GL2C_CTRL4__SPA_CHANNEL_ENABLE__SHIFT = 0x1 # macro +GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY__SHIFT = 0x2 # macro +GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE__SHIFT = 0x3 # macro +GL2C_CTRL4__CM_MGCG_MODE__SHIFT = 0x4 # macro +GL2C_CTRL4__MDC_MGCG_MODE__SHIFT = 0x5 # macro +GL2C_CTRL4__TAG_MGCG_MODE__SHIFT = 0x6 # macro +GL2C_CTRL4__CORE_MGCG_MODE__SHIFT = 0x7 # macro +GL2C_CTRL4__EXECUTE_MGCG_MODE__SHIFT = 0x8 # macro +GL2C_CTRL4__EA_NACK_DISABLE__SHIFT = 0x9 # macro +GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE__SHIFT = 0x1a # macro +GL2C_CTRL4__METADATA_WR_OP_CID_MASK = 0x00000001 # macro +GL2C_CTRL4__SPA_CHANNEL_ENABLE_MASK = 0x00000002 # macro +GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY_MASK = 0x00000004 # macro +GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE_MASK = 0x00000008 # macro +GL2C_CTRL4__CM_MGCG_MODE_MASK = 0x00000010 # macro +GL2C_CTRL4__MDC_MGCG_MODE_MASK = 0x00000020 # macro +GL2C_CTRL4__TAG_MGCG_MODE_MASK = 0x00000040 # macro +GL2C_CTRL4__CORE_MGCG_MODE_MASK = 0x00000080 # macro +GL2C_CTRL4__EXECUTE_MGCG_MODE_MASK = 0x00000100 # macro +GL2C_CTRL4__EA_NACK_DISABLE_MASK = 0x00000200 # macro +GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE_MASK = 0x04000000 # macro +GL2C_DISCARD_STALL_CTRL__LIMIT__SHIFT = 0x0 # macro +GL2C_DISCARD_STALL_CTRL__WINDOW__SHIFT = 0xf # macro +GL2C_DISCARD_STALL_CTRL__DROP_NEXT__SHIFT = 0x1e # macro +GL2C_DISCARD_STALL_CTRL__ENABLE__SHIFT = 0x1f # macro +GL2C_DISCARD_STALL_CTRL__LIMIT_MASK = 0x00007FFF # macro +GL2C_DISCARD_STALL_CTRL__WINDOW_MASK = 0x3FFF8000 # macro +GL2C_DISCARD_STALL_CTRL__DROP_NEXT_MASK = 0x40000000 # macro +GL2C_DISCARD_STALL_CTRL__ENABLE_MASK = 0x80000000 # macro +GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT = 0x0 # macro +GL2A_ADDR_MATCH_CTRL__DISABLE_MASK = 0xFFFFFFFF # macro +GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT = 0x0 # macro +GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK = 0xFFFFFFFF # macro +GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT = 0x0 # macro +GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK = 0x00000007 # macro +GL2A_PRIORITY_CTRL__DISABLE__SHIFT = 0x0 # macro +GL2A_PRIORITY_CTRL__DISABLE_MASK = 0xFFFFFFFF # macro +GL2A_RESP_THROTTLE_CTRL__DISABLE__SHIFT = 0x0 # macro +GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1__SHIFT = 0x10 # macro +GL2A_RESP_THROTTLE_CTRL__CREDIT_CH__SHIFT = 0x18 # macro +GL2A_RESP_THROTTLE_CTRL__DISABLE_MASK = 0x0000FFFF # macro +GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1_MASK = 0x00FF0000 # macro +GL2A_RESP_THROTTLE_CTRL__CREDIT_CH_MASK = 0xFF000000 # macro +GL1H_ARB_CTRL__REQ_FGCG_DISABLE__SHIFT = 0x0 # macro +GL1H_ARB_CTRL__SRC_FGCG_DISABLE__SHIFT = 0x1 # macro +GL1H_ARB_CTRL__RET_FGCG_DISABLE__SHIFT = 0x2 # macro +GL1H_ARB_CTRL__CHICKEN_BITS__SHIFT = 0x3 # macro +GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT = 0xb # macro +GL1H_ARB_CTRL__REQ_FGCG_DISABLE_MASK = 0x00000001 # macro +GL1H_ARB_CTRL__SRC_FGCG_DISABLE_MASK = 0x00000002 # macro +GL1H_ARB_CTRL__RET_FGCG_DISABLE_MASK = 0x00000004 # macro +GL1H_ARB_CTRL__CHICKEN_BITS_MASK = 0x000007F8 # macro +GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK = 0x00000800 # macro +GL1H_GL1_CREDITS__GL1_REQ_CREDITS__SHIFT = 0x0 # macro +GL1H_GL1_CREDITS__GL1_REQ_CREDITS_MASK = 0x000000FF # macro +GL1H_BURST_MASK__BURST_ADDR_MASK__SHIFT = 0x0 # macro +GL1H_BURST_MASK__BURST_ADDR_MASK_MASK = 0x000000FF # macro +GL1H_BURST_CTRL__MAX_BURST_SIZE__SHIFT = 0x0 # macro +GL1H_BURST_CTRL__BURST_DISABLE__SHIFT = 0x3 # macro +GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS__SHIFT = 0x4 # macro +GL1H_BURST_CTRL__MAX_BURST_SIZE_MASK = 0x00000007 # macro +GL1H_BURST_CTRL__BURST_DISABLE_MASK = 0x00000008 # macro +GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS_MASK = 0x00000030 # macro +GL1H_ARB_STATUS__REQ_ARB_BUSY__SHIFT = 0x0 # macro +GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ__SHIFT = 0x1 # macro +GL1H_ARB_STATUS__REQ_ARB_BUSY_MASK = 0x00000001 # macro +GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ_MASK = 0x00000002 # macro +CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPF_LATENCY_STATS_DATA__DATA__SHIFT = 0x0 # macro +CPF_LATENCY_STATS_DATA__DATA_MASK = 0xFFFFFFFF # macro +CPG_LATENCY_STATS_DATA__DATA__SHIFT = 0x0 # macro +CPG_LATENCY_STATS_DATA__DATA_MASK = 0xFFFFFFFF # macro +CPC_LATENCY_STATS_DATA__DATA__SHIFT = 0x0 # macro +CPC_LATENCY_STATS_DATA__DATA_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE4_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE4_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE4_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE4_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE5_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE5_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE5_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE5_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE6_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE6_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE6_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE6_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT = 0x0 # macro +TCP_PERFCOUNTER_FILTER__FLAT__SHIFT = 0x1 # macro +TCP_PERFCOUNTER_FILTER__DIM__SHIFT = 0x2 # macro +TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT = 0x5 # macro +TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT = 0xd # macro +TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT = 0x11 # macro +TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT = 0x16 # macro +TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT = 0x18 # macro +TCP_PERFCOUNTER_FILTER__SLC__SHIFT = 0x1b # macro +TCP_PERFCOUNTER_FILTER__DLC__SHIFT = 0x1c # macro +TCP_PERFCOUNTER_FILTER__GLC__SHIFT = 0x1d # macro +TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT = 0x1e # macro +TCP_PERFCOUNTER_FILTER__BUFFER_MASK = 0x00000001 # macro +TCP_PERFCOUNTER_FILTER__FLAT_MASK = 0x00000002 # macro +TCP_PERFCOUNTER_FILTER__DIM_MASK = 0x0000001C # macro +TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK = 0x00000FE0 # macro +TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK = 0x0001E000 # macro +TCP_PERFCOUNTER_FILTER__SW_MODE_MASK = 0x003E0000 # macro +TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK = 0x00C00000 # macro +TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK = 0x07000000 # macro +TCP_PERFCOUNTER_FILTER__SLC_MASK = 0x08000000 # macro +TCP_PERFCOUNTER_FILTER__DLC_MASK = 0x10000000 # macro +TCP_PERFCOUNTER_FILTER__GLC_MASK = 0x20000000 # macro +TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK = 0x40000000 # macro +TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT = 0x0 # macro +TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK = 0x00000007 # macro +TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT = 0x0 # macro +TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT = 0x1 # macro +TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT = 0x2 # macro +TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT = 0x3 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT = 0x4 # macro +TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT = 0x5 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT = 0x6 # macro +TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT = 0x7 # macro +TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT = 0x8 # macro +TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT = 0x9 # macro +TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT = 0xa # macro +TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT = 0xb # macro +TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT = 0xc # macro +TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK = 0x00000001 # macro +TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK = 0x00000002 # macro +TCP_PERFCOUNTER_FILTER_EN__DIM_MASK = 0x00000004 # macro +TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK = 0x00000008 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK = 0x00000010 # macro +TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK = 0x00000020 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK = 0x00000040 # macro +TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK = 0x00000080 # macro +TCP_PERFCOUNTER_FILTER_EN__SLC_MASK = 0x00000100 # macro +TCP_PERFCOUNTER_FILTER_EN__DLC_MASK = 0x00000200 # macro +TCP_PERFCOUNTER_FILTER_EN__GLC_MASK = 0x00000400 # macro +TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK = 0x00000800 # macro +TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK = 0x00001000 # macro +GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +GUS_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +GUS_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x1c # macro +CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0xF0000000 # macro +CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT = 0x18 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT = 0x1c # macro +CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK = 0x0F000000 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK = 0xF0000000 # macro +CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x1c # macro +CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0xF0000000 # macro +CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT = 0x18 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT = 0x1c # macro +CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK = 0x0F000000 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK = 0xF0000000 # macro +CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x1c # macro +CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0xF0000000 # macro +CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT = 0x18 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT = 0x1c # macro +CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK = 0x0F000000 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK = 0xF0000000 # macro +CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CP_PERFMON_CNTL__PERFMON_STATE__SHIFT = 0x0 # macro +CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT = 0x4 # macro +CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT = 0x8 # macro +CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT = 0xa # macro +CP_PERFMON_CNTL__PERFMON_STATE_MASK = 0x0000000F # macro +CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK = 0x000000F0 # macro +CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK = 0x00000300 # macro +CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK = 0x00000400 # macro +CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT = 0x0 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT = 0x1e # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT = 0x1f # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK = 0x00000007 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK = 0x40000000 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK = 0x80000000 # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT = 0x0 # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT = 0x1e # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT = 0x1f # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK = 0x0000001F # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK = 0x40000000 # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK = 0x80000000 # macro +CPF_LATENCY_STATS_SELECT__INDEX__SHIFT = 0x0 # macro +CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT = 0x1e # macro +CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT = 0x1f # macro +CPF_LATENCY_STATS_SELECT__INDEX_MASK = 0x0000000F # macro +CPF_LATENCY_STATS_SELECT__CLEAR_MASK = 0x40000000 # macro +CPF_LATENCY_STATS_SELECT__ENABLE_MASK = 0x80000000 # macro +CPG_LATENCY_STATS_SELECT__INDEX__SHIFT = 0x0 # macro +CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT = 0x1e # macro +CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT = 0x1f # macro +CPG_LATENCY_STATS_SELECT__INDEX_MASK = 0x0000001F # macro +CPG_LATENCY_STATS_SELECT__CLEAR_MASK = 0x40000000 # macro +CPG_LATENCY_STATS_SELECT__ENABLE_MASK = 0x80000000 # macro +CPC_LATENCY_STATS_SELECT__INDEX__SHIFT = 0x0 # macro +CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT = 0x1e # macro +CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT = 0x1f # macro +CPC_LATENCY_STATS_SELECT__INDEX_MASK = 0x0000000F # macro +CPC_LATENCY_STATS_SELECT__CLEAR_MASK = 0x40000000 # macro +CPC_LATENCY_STATS_SELECT__ENABLE_MASK = 0x80000000 # macro +CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT = 0x0 # macro +CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT = 0x1e # macro +CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT = 0x1f # macro +CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK = 0x0000001F # macro +CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK = 0x40000000 # macro +CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK = 0x80000000 # macro +CP_DRAW_OBJECT__OBJECT__SHIFT = 0x0 # macro +CP_DRAW_OBJECT__OBJECT_MASK = 0xFFFFFFFF # macro +CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT = 0x0 # macro +CP_DRAW_OBJECT_COUNTER__COUNT_MASK = 0x0000FFFF # macro +CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK = 0xFFFFFFFF # macro +CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_HI__WINDOW_HI_MASK = 0xFFFFFFFF # macro +CP_DRAW_WINDOW_LO__MIN__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_LO__MAX__SHIFT = 0x10 # macro +CP_DRAW_WINDOW_LO__MIN_MASK = 0x0000FFFF # macro +CP_DRAW_WINDOW_LO__MAX_MASK = 0xFFFF0000 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT = 0x1 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT = 0x2 # macro +CP_DRAW_WINDOW_CNTL__MODE__SHIFT = 0x8 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK = 0x00000001 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK = 0x00000002 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK = 0x00000004 # macro +CP_DRAW_WINDOW_CNTL__MODE_MASK = 0x00000100 # macro +GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xe # macro +GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT = 0x1d # macro +GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT = 0x1e # macro +GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x1f # macro +GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00004000 # macro +GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK = 0x20000000 # macro +GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK = 0x40000000 # macro +GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x80000000 # macro +GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xe # macro +GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT = 0x1d # macro +GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT = 0x1e # macro +GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x1f # macro +GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00004000 # macro +GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK = 0x20000000 # macro +GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK = 0x40000000 # macro +GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x80000000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE4_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE4_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE4_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE4_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE4_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE4_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE4_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE4_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE4_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE4_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE4_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE4_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_SE4_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_SE4_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_SE4_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_SE4_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_SE4_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_SE4_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE4_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE4_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE4_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_SE4_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE5_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE5_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE5_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE5_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE5_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE5_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE5_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE5_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE5_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE5_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE5_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE5_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_SE5_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_SE5_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_SE5_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_SE5_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_SE5_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_SE5_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE5_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE5_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE5_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_SE5_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE6_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE6_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE6_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE6_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE6_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE6_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE6_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE6_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE6_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE6_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE6_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE6_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_SE6_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_SE6_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_SE6_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_SE6_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_SE6_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_SE6_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE6_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE6_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE6_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_SE6_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x1 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x2 # macro +GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT = 0x3 # macro +GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT = 0x4 # macro +GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT = 0x5 # macro +GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT = 0x6 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT = 0x7 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x8 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x9 # macro +GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00000002 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK = 0x00000004 # macro +GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK = 0x00000008 # macro +GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK = 0x00000010 # macro +GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK = 0x00000020 # macro +GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK = 0x00000040 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK = 0x00000080 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x00000100 # macro +GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x00000200 # macro +GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT = 0x1 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x2 # macro +GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT = 0x3 # macro +GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT = 0x4 # macro +GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT = 0x5 # macro +GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT = 0x6 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT = 0x7 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT = 0x8 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT = 0x9 # macro +GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK = 0x00000002 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK = 0x00000004 # macro +GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK = 0x00000008 # macro +GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK = 0x00000010 # macro +GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK = 0x00000020 # macro +GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK = 0x00000040 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK = 0x00000080 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK = 0x00000100 # macro +GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK = 0x00000200 # macro +GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK = 0xF0000000 # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT = 0x0 # macro +SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT = 0x4 # macro +SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT = 0x8 # macro +SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT = 0xc # macro +SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT = 0x10 # macro +SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT = 0x14 # macro +SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT = 0x18 # macro +SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT = 0x1c # macro +SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK = 0x0000000F # macro +SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK = 0x000000F0 # macro +SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK = 0x00000F00 # macro +SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK = 0x0000F000 # macro +SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK = 0x000F0000 # macro +SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK = 0xF0000000 # macro +PC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PC_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PC_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PC_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PC_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PC_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PC_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PC_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PC_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER2_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER3_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER4_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER4_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER5_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER5_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER6_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER6_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER6_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQG_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQG_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQG_PERFCOUNTER7_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQG_PERFCOUNTER7_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQG_PERFCOUNTER7_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQG_PERFCOUNTER_CTRL__PS_EN__SHIFT = 0x0 # macro +SQG_PERFCOUNTER_CTRL__GS_EN__SHIFT = 0x2 # macro +SQG_PERFCOUNTER_CTRL__HS_EN__SHIFT = 0x4 # macro +SQG_PERFCOUNTER_CTRL__CS_EN__SHIFT = 0x6 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT = 0xe # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT = 0xf # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT = 0x10 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT = 0x11 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT = 0x12 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT = 0x13 # macro +SQG_PERFCOUNTER_CTRL__PS_EN_MASK = 0x00000001 # macro +SQG_PERFCOUNTER_CTRL__GS_EN_MASK = 0x00000004 # macro +SQG_PERFCOUNTER_CTRL__HS_EN_MASK = 0x00000010 # macro +SQG_PERFCOUNTER_CTRL__CS_EN_MASK = 0x00000040 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK = 0x00004000 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK = 0x00008000 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK = 0x00010000 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK = 0x00020000 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK = 0x00040000 # macro +SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK = 0x00080000 # macro +SQG_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT = 0x0 # macro +SQG_PERFCOUNTER_CTRL2__VMID_EN__SHIFT = 0x1 # macro +SQG_PERFCOUNTER_CTRL2__FORCE_EN_MASK = 0x00000001 # macro +SQG_PERFCOUNTER_CTRL2__VMID_EN_MASK = 0x0001FFFE # macro +SQG_PERF_SAMPLE_FINISH__STATUS__SHIFT = 0x0 # macro +SQG_PERF_SAMPLE_FINISH__STATUS_MASK = 0x0000007F # macro +SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT = 0x0 # macro +SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT = 0x2 # macro +SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT = 0x4 # macro +SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT = 0x6 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT = 0xe # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT = 0xf # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT = 0x10 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT = 0x11 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT = 0x12 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT = 0x13 # macro +SQ_PERFCOUNTER_CTRL__PS_EN_MASK = 0x00000001 # macro +SQ_PERFCOUNTER_CTRL__GS_EN_MASK = 0x00000004 # macro +SQ_PERFCOUNTER_CTRL__HS_EN_MASK = 0x00000010 # macro +SQ_PERFCOUNTER_CTRL__CS_EN_MASK = 0x00000040 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK = 0x00004000 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK = 0x00008000 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK = 0x00010000 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK = 0x00020000 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK = 0x00040000 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK = 0x00080000 # macro +SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT = 0x0 # macro +SQ_PERFCOUNTER_CTRL2__VMID_EN__SHIFT = 0x1 # macro +SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK = 0x00000001 # macro +SQ_PERFCOUNTER_CTRL2__VMID_EN_MASK = 0x0001FFFE # macro +SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT = 0x8 # macro +SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK = 0x3FFFFF00 # macro +SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT = 0x8 # macro +SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK = 0x3FFFFF00 # macro +SQ_THREAD_TRACE_CTRL__MODE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT = 0x2 # macro +SQ_THREAD_TRACE_CTRL__GL1_PERF_EN__SHIFT = 0x3 # macro +SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_CTRL__REG_AT_HWM__SHIFT = 0x9 # macro +SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT = 0xb # macro +SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT = 0xc # macro +SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT = 0xd # macro +SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT = 0xe # macro +SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT = 0x12 # macro +SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT = 0x13 # macro +SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT = 0x14 # macro +SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT = 0x1c # macro +SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT = 0x1d # macro +SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT = 0x1f # macro +SQ_THREAD_TRACE_CTRL__MODE_MASK = 0x00000003 # macro +SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK = 0x00000004 # macro +SQ_THREAD_TRACE_CTRL__GL1_PERF_EN_MASK = 0x00000008 # macro +SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK = 0x00000020 # macro +SQ_THREAD_TRACE_CTRL__HIWATER_MASK = 0x000001C0 # macro +SQ_THREAD_TRACE_CTRL__REG_AT_HWM_MASK = 0x00000600 # macro +SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK = 0x00000800 # macro +SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK = 0x00001000 # macro +SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK = 0x00002000 # macro +SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK = 0x0000C000 # macro +SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK = 0x00030000 # macro +SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK = 0x00040000 # macro +SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK = 0x00080000 # macro +SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK = 0x00700000 # macro +SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK = 0x10000000 # macro +SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK = 0x20000000 # macro +SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK = 0x80000000 # macro +SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT = 0x9 # macro +SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT = 0xa # macro +SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA__SHIFT = 0x11 # macro +SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK = 0x00000003 # macro +SQ_THREAD_TRACE_MASK__WGP_SEL_MASK = 0x000000F0 # macro +SQ_THREAD_TRACE_MASK__SA_SEL_MASK = 0x00000200 # macro +SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK = 0x0001FC00 # macro +SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA_MASK = 0x00020000 # macro +SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC__SHIFT = 0xb # macro +SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT = 0xc # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT = 0x18 # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT = 0x1a # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT = 0x1f # macro +SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK = 0x000007FF # macro +SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC_MASK = 0x00000800 # macro +SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK = 0x00001000 # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK = 0x00FF0000 # macro +SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK = 0x03000000 # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK = 0x1C000000 # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK = 0x80000000 # macro +SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT = 0x1f # macro +SQ_THREAD_TRACE_WPTR__OFFSET_MASK = 0x1FFFFFFF # macro +SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK = 0x80000000 # macro +SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT = 0xc # macro +SQ_THREAD_TRACE_STATUS__WRITE_ERROR__SHIFT = 0x18 # macro +SQ_THREAD_TRACE_STATUS__BUSY__SHIFT = 0x19 # macro +SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT = 0x1c # macro +SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK = 0x00000FFF # macro +SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK = 0x00FFF000 # macro +SQ_THREAD_TRACE_STATUS__WRITE_ERROR_MASK = 0x01000000 # macro +SQ_THREAD_TRACE_STATUS__BUSY_MASK = 0x02000000 # macro +SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK = 0xF0000000 # macro +SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT = 0x1 # macro +SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS__SHIFT = 0x8 # macro +SQ_THREAD_TRACE_STATUS2__BUF_ISSUE__SHIFT = 0xd # macro +SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL__SHIFT = 0xe # macro +SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK = 0x00000001 # macro +SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK = 0x00000002 # macro +SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS_MASK = 0x00001F00 # macro +SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_MASK = 0x00002000 # macro +SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL_MASK = 0x00004000 # macro +SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK = 0xFFFFFFFF # macro +GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT = 0x2 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT = 0x4 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT = 0x6 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT = 0x8 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT = 0xc # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT = 0x10 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT = 0x14 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK = 0x00000003 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK = 0x0000000C # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK = 0x00000030 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK = 0x000000C0 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK = 0x00000F00 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK = 0x0000F000 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK = 0x000F0000 # macro +GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK = 0x00F00000 # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCEA_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +GCEA_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCEA_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +GCEA_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GDS_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GDS_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GDS_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GDS_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GDS_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GDS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GDS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GDS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GDS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GDS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GDS_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GDS_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GDS_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GDS_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GDS_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT = 0x0 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT = 0x1 # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT = 0x4 # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT = 0x5 # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT = 0xa # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT = 0xb # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT = 0xc # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT = 0xd # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT = 0x11 # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT = 0x12 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT = 0x15 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT = 0x16 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK = 0x00000001 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK = 0x0000000E # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK = 0x00000010 # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK = 0x000003E0 # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK = 0x00000400 # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK = 0x00000800 # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK = 0x00001000 # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK = 0x0000E000 # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK = 0x00020000 # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK = 0x001C0000 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK = 0x00200000 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK = 0x00C00000 # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT = 0xc # macro +RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT__SHIFT = 0xe # macro +RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT = 0xf # macro +RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT = 0x10 # macro +RLC_SPM_PERFMON_CNTL__RESERVED1_MASK = 0x00000FFF # macro +RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK = 0x00003000 # macro +RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT_MASK = 0x00004000 # macro +RLC_SPM_PERFMON_CNTL__RESERVED_MASK = 0x00008000 # macro +RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK = 0xFFFF0000 # macro +RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK = 0xFFFFFFFF # macro +RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT = 0x10 # macro +RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK = 0x0000FFFF # macro +RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK = 0xFFFFFFFF # macro +RLC_SPM_RING_WRPTR__RESERVED__SHIFT = 0x0 # macro +RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT = 0x5 # macro +RLC_SPM_RING_WRPTR__RESERVED_MASK = 0x0000001F # macro +RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK = 0xFFFFFFE0 # macro +RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT = 0x0 # macro +RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK = 0xFFFFFFFF # macro +RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT = 0x0 # macro +RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK = 0x000000FF # macro +RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT__SHIFT = 0x10 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT__SHIFT = 0x18 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT_MASK = 0x0000FFFF # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT_MASK = 0x00FF0000 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT_MASK = 0xFF000000 # macro +RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR_MASK = 0x00000FFF # macro +RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0__SHIFT = 0x0 # macro +RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1__SHIFT = 0x10 # macro +RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0_MASK = 0x0000FFFF # macro +RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1_MASK = 0xFFFF0000 # macro +RLC_SPM_SE_MUXSEL_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SPM_SE_MUXSEL_ADDR__ADDR_MASK = 0x00000FFF # macro +RLC_SPM_SE_MUXSEL_DATA__SEL0__SHIFT = 0x0 # macro +RLC_SPM_SE_MUXSEL_DATA__SEL1__SHIFT = 0x10 # macro +RLC_SPM_SE_MUXSEL_DATA__SEL0_MASK = 0x0000FFFF # macro +RLC_SPM_SE_MUXSEL_DATA__SEL1_MASK = 0xFFFF0000 # macro +RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT = 0x7 # macro +RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK = 0x0000007F # macro +RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK = 0xFFFFFF80 # macro +RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_DATARAM_DATA__data_MASK = 0xFFFFFFFF # macro +RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED__SHIFT = 0x7 # macro +RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr_MASK = 0x0000007F # macro +RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED_MASK = 0xFFFFFF80 # macro +RLC_SPM_ACCUM_SWA_DATARAM_DATA__data__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_SWA_DATARAM_DATA__data_MASK = 0xFFFFFFFF # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT = 0xb # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK = 0x000007FF # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK = 0xFFFFF800 # macro +RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK = 0x000000FF # macro +RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT = 0x8 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT = 0x10 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED__SHIFT = 0x18 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK = 0x000000FF # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK = 0x0000FF00 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK = 0x00FF0000 # macro +RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED_MASK = 0xFF000000 # macro +RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT = 0x8 # macro +RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT = 0x9 # macro +RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT = 0xa # macro +RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT = 0xb # macro +RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT = 0xc # macro +RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT = 0xd # macro +RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT = 0xe # macro +RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT = 0xf # macro +RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT = 0x10 # macro +RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT = 0x11 # macro +RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT = 0x12 # macro +RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT = 0x13 # macro +RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT = 0x14 # macro +RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT = 0x15 # macro +RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT = 0x16 # macro +RLC_SPM_ACCUM_STATUS__MultiSampleAborted__SHIFT = 0x17 # macro +RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT = 0x18 # macro +RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK = 0x000000FF # macro +RLC_SPM_ACCUM_STATUS__AccumDone_MASK = 0x00000100 # macro +RLC_SPM_ACCUM_STATUS__SpmDone_MASK = 0x00000200 # macro +RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK = 0x00000400 # macro +RLC_SPM_ACCUM_STATUS__AccumArmed_MASK = 0x00000800 # macro +RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK = 0x00001000 # macro +RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK = 0x00002000 # macro +RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK = 0x00004000 # macro +RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK = 0x00008000 # macro +RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK = 0x00010000 # macro +RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK = 0x00020000 # macro +RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK = 0x00040000 # macro +RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK = 0x00080000 # macro +RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK = 0x00100000 # macro +RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK = 0x00200000 # macro +RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK = 0x00400000 # macro +RLC_SPM_ACCUM_STATUS__MultiSampleAborted_MASK = 0x00800000 # macro +RLC_SPM_ACCUM_STATUS__RESERVED_MASK = 0xFF000000 # macro +RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT = 0x1 # macro +RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT = 0x2 # macro +RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT = 0x3 # macro +RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT = 0x4 # macro +RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT = 0x8 # macro +RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT = 0x9 # macro +RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT = 0xa # macro +RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT = 0xb # macro +RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK = 0x00000001 # macro +RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK = 0x00000002 # macro +RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK = 0x00000004 # macro +RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK = 0x00000008 # macro +RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK = 0x000000F0 # macro +RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK = 0x00000100 # macro +RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK = 0x00000200 # macro +RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK = 0x00000400 # macro +RLC_SPM_ACCUM_CTRL__RESERVED_MASK = 0xFFFFF800 # macro +RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT = 0x1 # macro +RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT = 0x2 # macro +RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT = 0x3 # macro +RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT = 0x5 # macro +RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT = 0x6 # macro +RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT = 0x7 # macro +RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT = 0x8 # macro +RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT = 0x9 # macro +RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT = 0xa # macro +RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT = 0xb # macro +RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT = 0xc # macro +RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT = 0xd # macro +RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT = 0xe # macro +RLC_SPM_ACCUM_MODE__SE2_LoadOverride__SHIFT = 0xf # macro +RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride__SHIFT = 0x10 # macro +RLC_SPM_ACCUM_MODE__SE3_LoadOverride__SHIFT = 0x11 # macro +RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride__SHIFT = 0x12 # macro +RLC_SPM_ACCUM_MODE__SE4_LoadOverride__SHIFT = 0x13 # macro +RLC_SPM_ACCUM_MODE__SE4_SwaLoadOverride__SHIFT = 0x14 # macro +RLC_SPM_ACCUM_MODE__SE5_LoadOverride__SHIFT = 0x15 # macro +RLC_SPM_ACCUM_MODE__SE5_SwaLoadOverride__SHIFT = 0x16 # macro +RLC_SPM_ACCUM_MODE__EnableAccum_MASK = 0x00000001 # macro +RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK = 0x00000002 # macro +RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK = 0x00000004 # macro +RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK = 0x00000008 # macro +RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK = 0x00000020 # macro +RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK = 0x00000040 # macro +RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK = 0x00000080 # macro +RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK = 0x00000100 # macro +RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK = 0x00000200 # macro +RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK = 0x00000400 # macro +RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK = 0x00000800 # macro +RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK = 0x00001000 # macro +RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK = 0x00002000 # macro +RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK = 0x00004000 # macro +RLC_SPM_ACCUM_MODE__SE2_LoadOverride_MASK = 0x00008000 # macro +RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride_MASK = 0x00010000 # macro +RLC_SPM_ACCUM_MODE__SE3_LoadOverride_MASK = 0x00020000 # macro +RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride_MASK = 0x00040000 # macro +RLC_SPM_ACCUM_MODE__SE4_LoadOverride_MASK = 0x00080000 # macro +RLC_SPM_ACCUM_MODE__SE4_SwaLoadOverride_MASK = 0x00100000 # macro +RLC_SPM_ACCUM_MODE__SE5_LoadOverride_MASK = 0x00200000 # macro +RLC_SPM_ACCUM_MODE__SE5_SwaLoadOverride_MASK = 0x00400000 # macro +RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK = 0x0000FFFF # macro +RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK = 0x000000FF # macro +RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT = 0x13 # macro +RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK = 0x0007FFFF # macro +RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK = 0xFFF80000 # macro +RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT = 0x0 # macro +RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT = 0x8 # macro +RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED__SHIFT = 0x10 # macro +RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK = 0x000000FF # macro +RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK = 0x0000FF00 # macro +RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SPM_PAUSE__PAUSE__SHIFT = 0x0 # macro +RLC_SPM_PAUSE__PAUSED__SHIFT = 0x1 # macro +RLC_SPM_PAUSE__PAUSE_MASK = 0x00000001 # macro +RLC_SPM_PAUSE__PAUSED_MASK = 0x00000002 # macro +RLC_SPM_STATUS__CTL_BUSY__SHIFT = 0x0 # macro +RLC_SPM_STATUS__RSPM_REG_BUSY__SHIFT = 0x1 # macro +RLC_SPM_STATUS__SPM_RSPM_BUSY__SHIFT = 0x2 # macro +RLC_SPM_STATUS__SPM_RSPM_IO_BUSY__SHIFT = 0x3 # macro +RLC_SPM_STATUS__SE_RSPM_IO_BUSY__SHIFT = 0x4 # macro +RLC_SPM_STATUS__ACCUM_BUSY__SHIFT = 0xf # macro +RLC_SPM_STATUS__FSM_MASTER_STATE__SHIFT = 0x10 # macro +RLC_SPM_STATUS__FSM_MEMORY_STATE__SHIFT = 0x14 # macro +RLC_SPM_STATUS__CTL_REQ_STATE__SHIFT = 0x18 # macro +RLC_SPM_STATUS__CTL_RET_STATE__SHIFT = 0x1a # macro +RLC_SPM_STATUS__CTL_BUSY_MASK = 0x00000001 # macro +RLC_SPM_STATUS__RSPM_REG_BUSY_MASK = 0x00000002 # macro +RLC_SPM_STATUS__SPM_RSPM_BUSY_MASK = 0x00000004 # macro +RLC_SPM_STATUS__SPM_RSPM_IO_BUSY_MASK = 0x00000008 # macro +RLC_SPM_STATUS__SE_RSPM_IO_BUSY_MASK = 0x00000FF0 # macro +RLC_SPM_STATUS__ACCUM_BUSY_MASK = 0x00008000 # macro +RLC_SPM_STATUS__FSM_MASTER_STATE_MASK = 0x000F0000 # macro +RLC_SPM_STATUS__FSM_MEMORY_STATE_MASK = 0x00F00000 # macro +RLC_SPM_STATUS__CTL_REQ_STATE_MASK = 0x03000000 # macro +RLC_SPM_STATUS__CTL_RET_STATE_MASK = 0x04000000 # macro +RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT = 0x0 # macro +RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK = 0xFFFFFFFF # macro +RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT = 0x0 # macro +RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK = 0xFFFFFFFF # macro +RLC_SPM_MODE__MODE__SHIFT = 0x0 # macro +RLC_SPM_MODE__MODE_MASK = 0x00000001 # macro +RLC_SPM_RSPM_REQ_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_SPM_RSPM_REQ_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_SPM_RSPM_REQ_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_SPM_RSPM_REQ_DATA_HI__DATA_MASK = 0x00000FFF # macro +RLC_SPM_RSPM_REQ_OP__OP__SHIFT = 0x0 # macro +RLC_SPM_RSPM_REQ_OP__OP_MASK = 0x0000000F # macro +RLC_SPM_RSPM_RET_DATA__DATA__SHIFT = 0x0 # macro +RLC_SPM_RSPM_RET_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SPM_RSPM_RET_OP__OP__SHIFT = 0x0 # macro +RLC_SPM_RSPM_RET_OP__VALID__SHIFT = 0x8 # macro +RLC_SPM_RSPM_RET_OP__OP_MASK = 0x0000000F # macro +RLC_SPM_RSPM_RET_OP__VALID_MASK = 0x00000100 # macro +RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA_MASK = 0x00000FFF # macro +RLC_SPM_SE_RSPM_REQ_OP__OP__SHIFT = 0x0 # macro +RLC_SPM_SE_RSPM_REQ_OP__OP_MASK = 0x0000000F # macro +RLC_SPM_SE_RSPM_RET_DATA__DATA__SHIFT = 0x0 # macro +RLC_SPM_SE_RSPM_RET_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SPM_SE_RSPM_RET_OP__OP__SHIFT = 0x0 # macro +RLC_SPM_SE_RSPM_RET_OP__VALID__SHIFT = 0x8 # macro +RLC_SPM_SE_RSPM_RET_OP__OP_MASK = 0x0000000F # macro +RLC_SPM_SE_RSPM_RET_OP__VALID_MASK = 0x00000100 # macro +RLC_SPM_RSPM_CMD__CMD__SHIFT = 0x0 # macro +RLC_SPM_RSPM_CMD__CMD_MASK = 0x0000000F # macro +RLC_SPM_RSPM_CMD_ACK__SE0_ACK__SHIFT = 0x0 # macro +RLC_SPM_RSPM_CMD_ACK__SE1_ACK__SHIFT = 0x1 # macro +RLC_SPM_RSPM_CMD_ACK__SE2_ACK__SHIFT = 0x2 # macro +RLC_SPM_RSPM_CMD_ACK__SE3_ACK__SHIFT = 0x3 # macro +RLC_SPM_RSPM_CMD_ACK__SE4_ACK__SHIFT = 0x4 # macro +RLC_SPM_RSPM_CMD_ACK__SE5_ACK__SHIFT = 0x5 # macro +RLC_SPM_RSPM_CMD_ACK__SE6_ACK__SHIFT = 0x6 # macro +RLC_SPM_RSPM_CMD_ACK__SE7_ACK__SHIFT = 0x7 # macro +RLC_SPM_RSPM_CMD_ACK__SPM_ACK__SHIFT = 0x8 # macro +RLC_SPM_RSPM_CMD_ACK__SE0_ACK_MASK = 0x00000001 # macro +RLC_SPM_RSPM_CMD_ACK__SE1_ACK_MASK = 0x00000002 # macro +RLC_SPM_RSPM_CMD_ACK__SE2_ACK_MASK = 0x00000004 # macro +RLC_SPM_RSPM_CMD_ACK__SE3_ACK_MASK = 0x00000008 # macro +RLC_SPM_RSPM_CMD_ACK__SE4_ACK_MASK = 0x00000010 # macro +RLC_SPM_RSPM_CMD_ACK__SE5_ACK_MASK = 0x00000020 # macro +RLC_SPM_RSPM_CMD_ACK__SE6_ACK_MASK = 0x00000040 # macro +RLC_SPM_RSPM_CMD_ACK__SE7_ACK_MASK = 0x00000080 # macro +RLC_SPM_RSPM_CMD_ACK__SPM_ACK_MASK = 0x00000100 # macro +RLC_SPM_SPARE__SPARE__SHIFT = 0x0 # macro +RLC_SPM_SPARE__SPARE_MASK = 0xFFFFFFFF # macro +RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT = 0x0 # macro +RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT = 0xa # macro +RLC_PERFMON_CNTL__PERFMON_STATE_MASK = 0x00000007 # macro +RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK = 0x00000400 # macro +RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT = 0x0 # macro +RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK = 0x000000FF # macro +RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT = 0x0 # macro +RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK = 0x000000FF # macro +RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT = 0x1 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT = 0x2 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT = 0x3 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK = 0x00000001 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK = 0x00000002 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK = 0x00000004 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK = 0xFFFFFFF8 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT = 0x4 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK = 0x0000000F # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK = 0x00000030 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT = 0x4 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK = 0x0000000F # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK = 0x00000030 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT = 0x0 # macro +RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT = 0x2 # macro +RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT = 0x4 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT = 0x6 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT = 0x8 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT = 0xa # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT = 0xe # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT = 0x13 # macro +RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT = 0x19 # macro +RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT = 0x1a # macro +RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK = 0x00000003 # macro +RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK = 0x0000000C # macro +RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK = 0x00000030 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK = 0x000000C0 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK = 0x00000300 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK = 0x00003C00 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK = 0x0007C000 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK = 0x01F80000 # macro +RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK = 0x02000000 # macro +RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK = 0x04000000 # macro +GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GCR_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GCR_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT = 0x1c # macro +UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK = 0xF0000000 # macro +UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT = 0x1c # macro +UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK = 0xF0000000 # macro +UTCL1_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE__SHIFT = 0x1c # macro +UTCL1_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE_MASK = 0xF0000000 # macro +UTCL1_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE__SHIFT = 0x1c # macro +UTCL1_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE_MASK = 0xF0000000 # macro +GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1H_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GL1H_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1H_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GL1H_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1H_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1H_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GL1H_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1H_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GL1H_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +GL1H_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1H_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1H_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1H_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1H_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1H_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1H_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1H_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1H_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1H_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GL1H_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GL1H_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GL1H_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GL1H_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GL1H_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GL1H_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT = 0x0 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT = 0x2 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT = 0x4 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT = 0x6 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT = 0x8 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT = 0xc # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT = 0x10 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT = 0x14 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK = 0x00000003 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK = 0x0000000C # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK = 0x00000030 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK = 0x000000C0 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK = 0x00000F00 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK = 0x0000F000 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK = 0x000F0000 # macro +GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK = 0x00F00000 # macro +GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GUS_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +GUS_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GUS_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +GUS_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT = 0x0 # macro +GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK = 0x000003FF # macro +GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT = 0x0 # macro +GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK = 0xFFFFFFFF # macro +GRTAVFS_GENERAL_0__DATA__SHIFT = 0x0 # macro +GRTAVFS_GENERAL_0__DATA_MASK = 0xFFFFFFFF # macro +GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT = 0x0 # macro +GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA_MASK = 0xFFFFFFFF # macro +GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT = 0x0 # macro +GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT = 0x1 # macro +GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN_MASK = 0x00000001 # macro +GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN_MASK = 0x00000002 # macro +GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT = 0x0 # macro +GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT = 0x1 # macro +GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK = 0x00000001 # macro +GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK = 0x00000002 # macro +GRTAVFS_TARG_FREQ__TARGET_FREQUENCY__SHIFT = 0x0 # macro +GRTAVFS_TARG_FREQ__REQUEST__SHIFT = 0x10 # macro +GRTAVFS_TARG_FREQ__RESERVED__SHIFT = 0x11 # macro +GRTAVFS_TARG_FREQ__TARGET_FREQUENCY_MASK = 0x0000FFFF # macro +GRTAVFS_TARG_FREQ__REQUEST_MASK = 0x00010000 # macro +GRTAVFS_TARG_FREQ__RESERVED_MASK = 0xFFFE0000 # macro +GRTAVFS_TARG_VOLT__TARGET_VOLTAGE__SHIFT = 0x0 # macro +GRTAVFS_TARG_VOLT__VALID__SHIFT = 0xa # macro +GRTAVFS_TARG_VOLT__RESERVED__SHIFT = 0xb # macro +GRTAVFS_TARG_VOLT__TARGET_VOLTAGE_MASK = 0x000003FF # macro +GRTAVFS_TARG_VOLT__VALID_MASK = 0x00000400 # macro +GRTAVFS_TARG_VOLT__RESERVED_MASK = 0xFFFFF800 # macro +GRTAVFS_SOFT_RESET__RESETN_OVERRIDE__SHIFT = 0x0 # macro +GRTAVFS_SOFT_RESET__RESERVED__SHIFT = 0x1 # macro +GRTAVFS_SOFT_RESET__RESETN_OVERRIDE_MASK = 0x00000001 # macro +GRTAVFS_SOFT_RESET__RESERVED_MASK = 0xFFFFFFFE # macro +GRTAVFS_PSM_CNTL__PSM_COUNT__SHIFT = 0x0 # macro +GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN__SHIFT = 0xe # macro +GRTAVFS_PSM_CNTL__RESERVED__SHIFT = 0xf # macro +GRTAVFS_PSM_CNTL__PSM_COUNT_MASK = 0x00003FFF # macro +GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN_MASK = 0x00004000 # macro +GRTAVFS_PSM_CNTL__RESERVED_MASK = 0xFFFF8000 # macro +GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT = 0x0 # macro +GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT = 0x1 # macro +GRTAVFS_CLK_CNTL__RESERVED__SHIFT = 0x2 # macro +GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK = 0x00000001 # macro +GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK = 0x00000002 # macro +GRTAVFS_CLK_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT = 0x0 # macro +GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR_MASK = 0x000003FF # macro +GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT = 0x0 # macro +GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA_MASK = 0xFFFFFFFF # macro +GRTAVFS_SE_GENERAL_0__DATA__SHIFT = 0x0 # macro +GRTAVFS_SE_GENERAL_0__DATA_MASK = 0xFFFFFFFF # macro +GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT = 0x0 # macro +GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA_MASK = 0xFFFFFFFF # macro +GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT = 0x0 # macro +GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT = 0x1 # macro +GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN_MASK = 0x00000001 # macro +GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN_MASK = 0x00000002 # macro +GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT = 0x0 # macro +GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT = 0x1 # macro +GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK = 0x00000001 # macro +GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK = 0x00000002 # macro +GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY__SHIFT = 0x0 # macro +GRTAVFS_SE_TARG_FREQ__REQUEST__SHIFT = 0x10 # macro +GRTAVFS_SE_TARG_FREQ__RESERVED__SHIFT = 0x11 # macro +GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY_MASK = 0x0000FFFF # macro +GRTAVFS_SE_TARG_FREQ__REQUEST_MASK = 0x00010000 # macro +GRTAVFS_SE_TARG_FREQ__RESERVED_MASK = 0xFFFE0000 # macro +GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE__SHIFT = 0x0 # macro +GRTAVFS_SE_TARG_VOLT__VALID__SHIFT = 0xa # macro +GRTAVFS_SE_TARG_VOLT__RESERVED__SHIFT = 0xb # macro +GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE_MASK = 0x000003FF # macro +GRTAVFS_SE_TARG_VOLT__VALID_MASK = 0x00000400 # macro +GRTAVFS_SE_TARG_VOLT__RESERVED_MASK = 0xFFFFF800 # macro +GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE__SHIFT = 0x0 # macro +GRTAVFS_SE_SOFT_RESET__RESERVED__SHIFT = 0x1 # macro +GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE_MASK = 0x00000001 # macro +GRTAVFS_SE_SOFT_RESET__RESERVED_MASK = 0xFFFFFFFE # macro +GRTAVFS_SE_PSM_CNTL__PSM_COUNT__SHIFT = 0x0 # macro +GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN__SHIFT = 0xe # macro +GRTAVFS_SE_PSM_CNTL__RESERVED__SHIFT = 0xf # macro +GRTAVFS_SE_PSM_CNTL__PSM_COUNT_MASK = 0x00003FFF # macro +GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN_MASK = 0x00004000 # macro +GRTAVFS_SE_PSM_CNTL__RESERVED_MASK = 0xFFFF8000 # macro +GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT = 0x0 # macro +GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT = 0x1 # macro +GRTAVFS_SE_CLK_CNTL__RESERVED__SHIFT = 0x2 # macro +GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK = 0x00000001 # macro +GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK = 0x00000002 # macro +GRTAVFS_SE_CLK_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT = 0x0 # macro +RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK = 0x000003FF # macro +RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT = 0x0 # macro +RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK = 0xFFFFFFFF # macro +CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK = 0x000FFFFF # macro +CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK = 0x000FFFFF # macro +CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_PFP_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK = 0x000FFFFF # macro +CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT = 0x0 # macro +CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK = 0x000FFFFF # macro +CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT = 0x0 # macro +CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK = 0x001FFFFF # macro +CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT = 0x0 # macro +CP_ME_RAM_DATA__ME_RAM_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK = 0x000FFFFF # macro +CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK = 0x000FFFFF # macro +CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK = 0x000FFFFF # macro +CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK = 0x000FFFFF # macro +CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT = 0xc # macro +CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK = 0xFFFFF000 # macro +CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT = 0x0 # macro +CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK = 0x0000FFFF # macro +CP_PFP_IC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT = 0x4 # macro +CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_PFP_IC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK = 0x00000010 # macro +CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT = 0x0 # macro +CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT = 0x1 # macro +CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT = 0x4 # macro +CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT = 0x5 # macro +CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK = 0x00000001 # macro +CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK = 0x00000002 # macro +CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK = 0x00000010 # macro +CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK = 0x00000020 # macro +CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT = 0xc # macro +CP_ME_IC_BASE_LO__IC_BASE_LO_MASK = 0xFFFFF000 # macro +CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT = 0x0 # macro +CP_ME_IC_BASE_HI__IC_BASE_HI_MASK = 0x0000FFFF # macro +CP_ME_IC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT = 0x4 # macro +CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_ME_IC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK = 0x00000010 # macro +CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT = 0x0 # macro +CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT = 0x1 # macro +CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT = 0x4 # macro +CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT = 0x5 # macro +CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK = 0x00000001 # macro +CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK = 0x00000002 # macro +CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK = 0x00000010 # macro +CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK = 0x00000020 # macro +CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT = 0xc # macro +CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK = 0xFFFFF000 # macro +CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT = 0x0 # macro +CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK = 0x0000FFFF # macro +CP_CPC_IC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT = 0x4 # macro +CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_CPC_IC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK = 0x00000010 # macro +CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT = 0xc # macro +CP_MES_IC_BASE_LO__IC_BASE_LO_MASK = 0xFFFFF000 # macro +CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT = 0xc # macro +CP_MES_MIBASE_LO__IC_BASE_LO_MASK = 0xFFFFF000 # macro +CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT = 0x0 # macro +CP_MES_IC_BASE_HI__IC_BASE_HI_MASK = 0x0000FFFF # macro +CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT = 0x0 # macro +CP_MES_MIBASE_HI__IC_BASE_HI_MASK = 0x0000FFFF # macro +CP_MES_IC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_MES_IC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK = 0x03000000 # macro +CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT = 0x10 # macro +CP_MES_DC_BASE_LO__DC_BASE_LO_MASK = 0xFFFF0000 # macro +CP_MES_MDBASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_MES_MDBASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT = 0x0 # macro +CP_MES_DC_BASE_HI__DC_BASE_HI_MASK = 0x0000FFFF # macro +CP_MES_MDBASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_MES_MDBASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_MES_MIBOUND_LO__BOUND_LO__SHIFT = 0x0 # macro +CP_MES_MIBOUND_LO__BOUND_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MIBOUND_HI__BOUND_HI__SHIFT = 0x0 # macro +CP_MES_MIBOUND_HI__BOUND_HI_MASK = 0xFFFFFFFF # macro +CP_MES_MDBOUND_LO__BOUND_LO__SHIFT = 0x0 # macro +CP_MES_MDBOUND_LO__BOUND_LO_MASK = 0xFFFFFFFF # macro +CP_MES_MDBOUND_HI__BOUND_HI__SHIFT = 0x0 # macro +CP_MES_MDBOUND_HI__BOUND_HI_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO__SHIFT = 0x10 # macro +CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO_MASK = 0xFFFF0000 # macro +CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO__SHIFT = 0x10 # macro +CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO_MASK = 0xFFFF0000 # macro +CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI_MASK = 0x0000FFFF # macro +CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI__SHIFT = 0x0 # macro +CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI_MASK = 0x0000FFFF # macro +CP_GFX_RS64_MIBOUND_LO__BOUND__SHIFT = 0x0 # macro +CP_GFX_RS64_MIBOUND_LO__BOUND_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_MIBOUND_HI__BOUND__SHIFT = 0x0 # macro +CP_GFX_RS64_MIBOUND_HI__BOUND_MASK = 0xFFFFFFFF # macro +CP_MEC_DC_BASE_LO__DC_BASE_LO__SHIFT = 0x10 # macro +CP_MEC_DC_BASE_LO__DC_BASE_LO_MASK = 0xFFFF0000 # macro +CP_MEC_MDBASE_LO__BASE_LO__SHIFT = 0x10 # macro +CP_MEC_MDBASE_LO__BASE_LO_MASK = 0xFFFF0000 # macro +CP_MEC_DC_BASE_HI__DC_BASE_HI__SHIFT = 0x0 # macro +CP_MEC_DC_BASE_HI__DC_BASE_HI_MASK = 0x0000FFFF # macro +CP_MEC_MDBASE_HI__BASE_HI__SHIFT = 0x0 # macro +CP_MEC_MDBASE_HI__BASE_HI_MASK = 0x0000FFFF # macro +CP_MEC_MIBOUND_LO__BOUND_LO__SHIFT = 0x0 # macro +CP_MEC_MIBOUND_LO__BOUND_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_MIBOUND_HI__BOUND_HI__SHIFT = 0x0 # macro +CP_MEC_MIBOUND_HI__BOUND_HI_MASK = 0xFFFFFFFF # macro +CP_MEC_MDBOUND_LO__BOUND_LO__SHIFT = 0x0 # macro +CP_MEC_MDBOUND_LO__BOUND_LO_MASK = 0xFFFFFFFF # macro +CP_MEC_MDBOUND_HI__BOUND_HI__SHIFT = 0x0 # macro +CP_MEC_MDBOUND_HI__BOUND_HI_MASK = 0xFFFFFFFF # macro +RLC_CNTL__RLC_ENABLE_F32__SHIFT = 0x0 # macro +RLC_CNTL__FORCE_RETRY__SHIFT = 0x1 # macro +RLC_CNTL__READ_CACHE_DISABLE__SHIFT = 0x2 # macro +RLC_CNTL__RLC_STEP_F32__SHIFT = 0x3 # macro +RLC_CNTL__RESERVED__SHIFT = 0x4 # macro +RLC_CNTL__RLC_ENABLE_F32_MASK = 0x00000001 # macro +RLC_CNTL__FORCE_RETRY_MASK = 0x00000002 # macro +RLC_CNTL__READ_CACHE_DISABLE_MASK = 0x00000004 # macro +RLC_CNTL__RLC_STEP_F32_MASK = 0x00000008 # macro +RLC_CNTL__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT = 0x0 # macro +RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT = 0xa # macro +RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT = 0x14 # macro +RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK = 0x000003FF # macro +RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK = 0x000FFC00 # macro +RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK = 0x3FF00000 # macro +RLC_STAT__RLC_BUSY__SHIFT = 0x0 # macro +RLC_STAT__RLC_SRM_BUSY__SHIFT = 0x1 # macro +RLC_STAT__RLC_GPM_BUSY__SHIFT = 0x2 # macro +RLC_STAT__RLC_SPM_BUSY__SHIFT = 0x3 # macro +RLC_STAT__MC_BUSY__SHIFT = 0x4 # macro +RLC_STAT__RLC_THREAD_0_BUSY__SHIFT = 0x5 # macro +RLC_STAT__RLC_THREAD_1_BUSY__SHIFT = 0x6 # macro +RLC_STAT__RLC_THREAD_2_BUSY__SHIFT = 0x7 # macro +RLC_STAT__RESERVED__SHIFT = 0x8 # macro +RLC_STAT__RLC_BUSY_MASK = 0x00000001 # macro +RLC_STAT__RLC_SRM_BUSY_MASK = 0x00000002 # macro +RLC_STAT__RLC_GPM_BUSY_MASK = 0x00000004 # macro +RLC_STAT__RLC_SPM_BUSY_MASK = 0x00000008 # macro +RLC_STAT__MC_BUSY_MASK = 0x00000010 # macro +RLC_STAT__RLC_THREAD_0_BUSY_MASK = 0x00000020 # macro +RLC_STAT__RLC_THREAD_1_BUSY_MASK = 0x00000040 # macro +RLC_STAT__RLC_THREAD_2_BUSY_MASK = 0x00000080 # macro +RLC_STAT__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT = 0x0 # macro +RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK = 0xFFFFFFFF # macro +RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT = 0x0 # macro +RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_0__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_0__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_1__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_1__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_2__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_2__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_3__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_3__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_4__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_4__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT = 0x0 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT = 0x1 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT = 0x2 # macro +RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT = 0x3 # macro +RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT = 0x4 # macro +RLC_GPM_TIMER_CTRL__RESERVED_1__SHIFT = 0x5 # macro +RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT = 0x8 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT = 0x9 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT = 0xa # macro +RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT = 0xb # macro +RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT = 0xc # macro +RLC_GPM_TIMER_CTRL__RESERVED_2__SHIFT = 0xd # macro +RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT = 0x10 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT = 0x11 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT = 0x12 # macro +RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT = 0x13 # macro +RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT = 0x14 # macro +RLC_GPM_TIMER_CTRL__RESERVED__SHIFT = 0x15 # macro +RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK = 0x00000001 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK = 0x00000002 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK = 0x00000004 # macro +RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK = 0x00000008 # macro +RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK = 0x00000010 # macro +RLC_GPM_TIMER_CTRL__RESERVED_1_MASK = 0x000000E0 # macro +RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK = 0x00000100 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK = 0x00000200 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK = 0x00000400 # macro +RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK = 0x00000800 # macro +RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK = 0x00001000 # macro +RLC_GPM_TIMER_CTRL__RESERVED_2_MASK = 0x0000E000 # macro +RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK = 0x00010000 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK = 0x00020000 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK = 0x00040000 # macro +RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK = 0x00080000 # macro +RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK = 0x00100000 # macro +RLC_GPM_TIMER_CTRL__RESERVED_MASK = 0xFFE00000 # macro +RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT = 0x0 # macro +RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT = 0x1 # macro +RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT = 0x2 # macro +RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT = 0x3 # macro +RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT = 0x4 # macro +RLC_GPM_TIMER_STAT__RESERVED_1__SHIFT = 0x5 # macro +RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT = 0x8 # macro +RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT = 0x9 # macro +RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT = 0xa # macro +RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT = 0xb # macro +RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT = 0xc # macro +RLC_GPM_TIMER_STAT__RESERVED_2__SHIFT = 0xd # macro +RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT = 0x10 # macro +RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT = 0x11 # macro +RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT = 0x12 # macro +RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT = 0x13 # macro +RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT = 0x14 # macro +RLC_GPM_TIMER_STAT__RESERVED__SHIFT = 0x15 # macro +RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK = 0x00000001 # macro +RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK = 0x00000002 # macro +RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK = 0x00000004 # macro +RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK = 0x00000008 # macro +RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK = 0x00000010 # macro +RLC_GPM_TIMER_STAT__RESERVED_1_MASK = 0x000000E0 # macro +RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK = 0x00000100 # macro +RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK = 0x00000200 # macro +RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK = 0x00000400 # macro +RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK = 0x00000800 # macro +RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK = 0x00001000 # macro +RLC_GPM_TIMER_STAT__RESERVED_2_MASK = 0x0000E000 # macro +RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK = 0x00010000 # macro +RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK = 0x00020000 # macro +RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK = 0x00040000 # macro +RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK = 0x00080000 # macro +RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK = 0x00100000 # macro +RLC_GPM_TIMER_STAT__RESERVED_MASK = 0xFFE00000 # macro +RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT = 0x0 # macro +RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT = 0x1 # macro +RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT = 0x2 # macro +RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED__SHIFT = 0x3 # macro +RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK = 0x00000001 # macro +RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK = 0x00000002 # macro +RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK = 0x00000004 # macro +RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED_MASK = 0x00000008 # macro +RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT = 0x0 # macro +RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT = 0x1 # macro +RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT = 0x2 # macro +RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED__SHIFT = 0x3 # macro +RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK = 0x00000001 # macro +RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK = 0x00000002 # macro +RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK = 0x00000004 # macro +RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED_MASK = 0x00000008 # macro +RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT = 0x0 # macro +RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT = 0x8 # macro +RLC_INT_STAT__RESERVED__SHIFT = 0x9 # macro +RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK = 0x000000FF # macro +RLC_INT_STAT__CP_RLC_INT_PENDING_MASK = 0x00000100 # macro +RLC_INT_STAT__RESERVED_MASK = 0xFFFFFE00 # macro +RLC_MGCG_CTRL__MGCG_EN__SHIFT = 0x0 # macro +RLC_MGCG_CTRL__SILICON_EN__SHIFT = 0x1 # macro +RLC_MGCG_CTRL__SIMULATION_EN__SHIFT = 0x2 # macro +RLC_MGCG_CTRL__ON_DELAY__SHIFT = 0x3 # macro +RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT = 0x7 # macro +RLC_MGCG_CTRL__SPARE__SHIFT = 0xf # macro +RLC_MGCG_CTRL__MGCG_EN_MASK = 0x00000001 # macro +RLC_MGCG_CTRL__SILICON_EN_MASK = 0x00000002 # macro +RLC_MGCG_CTRL__SIMULATION_EN_MASK = 0x00000004 # macro +RLC_MGCG_CTRL__ON_DELAY_MASK = 0x00000078 # macro +RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK = 0x00007F80 # macro +RLC_MGCG_CTRL__SPARE_MASK = 0xFFFF8000 # macro +RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT = 0x0 # macro +RLC_JUMP_TABLE_RESTORE__ADDR_MASK = 0xFFFFFFFF # macro +RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT = 0x0 # macro +RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT = 0x8 # macro +RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT = 0x10 # macro +RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK = 0x000000FF # macro +RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK = 0x0000FF00 # macro +RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK = 0xFFFF0000 # macro +RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK = 0xFFFFFFFF # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT = 0x0 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT = 0x1 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK = 0x00000001 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT = 0x0 # macro +RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK = 0xFFFFFFFF # macro +RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT = 0x0 # macro +RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT = 0x1 # macro +RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT = 0x2 # macro +RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT = 0x3 # macro +RLC_GPM_THREAD_RESET__RESERVED__SHIFT = 0x4 # macro +RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK = 0x00000001 # macro +RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK = 0x00000002 # macro +RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK = 0x00000004 # macro +RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK = 0x00000008 # macro +RLC_GPM_THREAD_RESET__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT = 0x0 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT = 0x1 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK = 0x00000001 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT = 0x0 # macro +RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT = 0x1 # macro +RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK = 0x00000001 # macro +RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE__SHIFT = 0x0 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE__SHIFT = 0x1 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE__SHIFT = 0x2 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE__SHIFT = 0x3 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED__SHIFT = 0x4 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE_MASK = 0x00000001 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE_MASK = 0x00000002 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE_MASK = 0x00000004 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE_MASK = 0x00000008 # macro +RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT = 0x0 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT = 0x1 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT = 0x2 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT = 0x3 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT = 0x4 # macro +RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT = 0x5 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK = 0x00000001 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK = 0x00000002 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK = 0x00000004 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK = 0x00000008 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK = 0x00000010 # macro +RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK = 0x00000020 # macro +RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT = 0x0 # macro +RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT = 0x1 # macro +RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT = 0x2 # macro +RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT = 0x3 # macro +RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT = 0x4 # macro +RLC_CLK_COUNT_STAT__RESERVED__SHIFT = 0x5 # macro +RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK = 0x00000001 # macro +RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK = 0x00000002 # macro +RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK = 0x00000004 # macro +RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK = 0x00000008 # macro +RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK = 0x00000010 # macro +RLC_CLK_COUNT_STAT__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT = 0x2 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT = 0x4 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT = 0x6 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT = 0x10 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT = 0x15 # macro +RLC_RLCG_DOORBELL_CNTL__RESERVED__SHIFT = 0x16 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK = 0x00000003 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK = 0x0000000C # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK = 0x00000030 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK = 0x000000C0 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK = 0x001F0000 # macro +RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK = 0x00200000 # macro +RLC_RLCG_DOORBELL_CNTL__RESERVED_MASK = 0xFFC00000 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT = 0x1 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT = 0x2 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT = 0x3 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK = 0x00000001 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK = 0x00000002 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK = 0x00000004 # macro +RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK = 0x00000008 # macro +RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK = 0x0000003F # macro +RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK = 0xFFFFFFFF # macro +RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT = 0x0 # macro +RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT = 0x1 # macro +RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT = 0x2 # macro +RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT = 0x3 # macro +RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT = 0x4 # macro +RLC_PG_CNTL__RESERVED__SHIFT = 0x5 # macro +RLC_PG_CNTL__MEM_DS_DISABLE__SHIFT = 0xd # macro +RLC_PG_CNTL__PG_OVERRIDE__SHIFT = 0xe # macro +RLC_PG_CNTL__CP_PG_DISABLE__SHIFT = 0xf # macro +RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT = 0x10 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT = 0x11 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT = 0x12 # macro +RLC_PG_CNTL__RESERVED1__SHIFT = 0x13 # macro +RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT = 0x15 # macro +RLC_PG_CNTL__RESERVED2__SHIFT = 0x16 # macro +RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT = 0x17 # macro +RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK = 0x00000001 # macro +RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK = 0x00000002 # macro +RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK = 0x00000004 # macro +RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK = 0x00000008 # macro +RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK = 0x00000010 # macro +RLC_PG_CNTL__RESERVED_MASK = 0x00001FE0 # macro +RLC_PG_CNTL__MEM_DS_DISABLE_MASK = 0x00002000 # macro +RLC_PG_CNTL__PG_OVERRIDE_MASK = 0x00004000 # macro +RLC_PG_CNTL__CP_PG_DISABLE_MASK = 0x00008000 # macro +RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK = 0x00010000 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK = 0x00020000 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK = 0x00040000 # macro +RLC_PG_CNTL__RESERVED1_MASK = 0x00180000 # macro +RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK = 0x00200000 # macro +RLC_PG_CNTL__RESERVED2_MASK = 0x00400000 # macro +RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK = 0x00800000 # macro +RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT = 0x0 # macro +RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT = 0x8 # macro +RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT = 0x10 # macro +RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT = 0x18 # macro +RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK = 0x000000FF # macro +RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK = 0x0000FF00 # macro +RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK = 0x00FF0000 # macro +RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK = 0xFF000000 # macro +RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT = 0x0 # macro +RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT = 0x1 # macro +RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT = 0x2 # macro +RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT = 0x3 # macro +RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT = 0x4 # macro +RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK = 0x00000001 # macro +RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK = 0x00000002 # macro +RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK = 0x00000004 # macro +RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK = 0x00000008 # macro +RLC_GPM_THREAD_ENABLE__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT = 0x0 # macro +RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT = 0x2 # macro +RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT = 0x10 # macro +RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT = 0x12 # macro +RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK = 0x00000003 # macro +RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK = 0x00000FFC # macro +RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK = 0x00030000 # macro +RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK = 0x0FFC0000 # macro +RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE__SHIFT = 0x0 # macro +RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT = 0x1 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT = 0x2 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT = 0x3 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT = 0x4 # macro +RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT = 0x5 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT = 0x6 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT = 0x7 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT = 0x8 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE__SHIFT = 0x9 # macro +RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE__SHIFT = 0xa # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11__SHIFT = 0xb # macro +RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL__SHIFT = 0x11 # macro +RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL__SHIFT = 0x12 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19__SHIFT = 0x13 # macro +RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK = 0x00000001 # macro +RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK = 0x00000002 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK = 0x00000004 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK = 0x00000008 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK = 0x00000010 # macro +RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK = 0x00000020 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK = 0x00000040 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK = 0x00000080 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK = 0x00000100 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK = 0x00000200 # macro +RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK = 0x00000400 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11_MASK = 0x0001F800 # macro +RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL_MASK = 0x00020000 # macro +RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL_MASK = 0x00040000 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19_MASK = 0xFFF80000 # macro +RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT = 0x0 # macro +RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT = 0x1 # macro +RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT = 0x2 # macro +RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT = 0x8 # macro +RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT = 0x1b # macro +RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT = 0x1c # macro +RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT = 0x1d # macro +RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT = 0x1f # macro +RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK = 0x00000001 # macro +RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK = 0x00000002 # macro +RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK = 0x000000FC # macro +RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK = 0x07FFFF00 # macro +RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK = 0x08000000 # macro +RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK = 0x10000000 # macro +RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK = 0x60000000 # macro +RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK = 0x80000000 # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT = 0x0 # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT = 0x4 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT = 0x8 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT = 0xc # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT = 0x10 # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT = 0x1c # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK = 0x0000000F # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK = 0x000000F0 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK = 0x00000F00 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK = 0x0000F000 # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK = 0x0FFF0000 # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK = 0xF0000000 # macro +RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT = 0x0 # macro +RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK = 0xFFFFFFFF # macro +RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT = 0x0 # macro +RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK = 0xFFFFFFFF # macro +RLC_PG_DELAY__POWER_UP_DELAY__SHIFT = 0x0 # macro +RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT = 0x8 # macro +RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT = 0x10 # macro +RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT = 0x18 # macro +RLC_PG_DELAY__POWER_UP_DELAY_MASK = 0x000000FF # macro +RLC_PG_DELAY__POWER_DOWN_DELAY_MASK = 0x0000FF00 # macro +RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK = 0x00FF0000 # macro +RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK = 0xFF000000 # macro +RLC_WGP_STATUS__WORK_PENDING__SHIFT = 0x0 # macro +RLC_WGP_STATUS__WORK_PENDING_MASK = 0xFFFFFFFF # macro +RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT = 0x0 # macro +RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK = 0xFFFFFFFF # macro +RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT = 0x0 # macro +RLC_MAX_PG_WGP__SPARE__SHIFT = 0x8 # macro +RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK = 0x000000FF # macro +RLC_MAX_PG_WGP__SPARE_MASK = 0xFFFFFF00 # macro +RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT = 0x0 # macro +RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT = 0x1 # macro +RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT = 0x2 # macro +RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT = 0x3 # macro +RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT = 0x13 # macro +RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK = 0x00000001 # macro +RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK = 0x00000002 # macro +RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK = 0x00000004 # macro +RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK = 0x0007FFF8 # macro +RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK = 0xFFF80000 # macro +RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT = 0x0 # macro +RLC_SERDES_RD_INDEX__SPARE__SHIFT = 0x2 # macro +RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK = 0x00000003 # macro +RLC_SERDES_RD_INDEX__SPARE_MASK = 0xFFFFFFFC # macro +RLC_SERDES_RD_DATA_0__DATA__SHIFT = 0x0 # macro +RLC_SERDES_RD_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_RD_DATA_1__DATA__SHIFT = 0x0 # macro +RLC_SERDES_RD_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_RD_DATA_2__DATA__SHIFT = 0x0 # macro +RLC_SERDES_RD_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_RD_DATA_3__DATA__SHIFT = 0x0 # macro +RLC_SERDES_RD_DATA_3__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT = 0x0 # macro +RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT = 0x1 # macro +RLC_SERDES_MASK__RESERVED__SHIFT = 0x2 # macro +RLC_SERDES_MASK__GC_SE_0__SHIFT = 0x10 # macro +RLC_SERDES_MASK__GC_SE_1__SHIFT = 0x11 # macro +RLC_SERDES_MASK__GC_SE_2__SHIFT = 0x12 # macro +RLC_SERDES_MASK__GC_SE_3__SHIFT = 0x13 # macro +RLC_SERDES_MASK__GC_SE_4__SHIFT = 0x14 # macro +RLC_SERDES_MASK__GC_SE_5__SHIFT = 0x15 # macro +RLC_SERDES_MASK__GC_SE_6__SHIFT = 0x16 # macro +RLC_SERDES_MASK__GC_SE_7__SHIFT = 0x17 # macro +RLC_SERDES_MASK__RESERVED_31_24__SHIFT = 0x18 # macro +RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK = 0x00000001 # macro +RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK = 0x00000002 # macro +RLC_SERDES_MASK__RESERVED_MASK = 0x0000FFFC # macro +RLC_SERDES_MASK__GC_SE_0_MASK = 0x00010000 # macro +RLC_SERDES_MASK__GC_SE_1_MASK = 0x00020000 # macro +RLC_SERDES_MASK__GC_SE_2_MASK = 0x00040000 # macro +RLC_SERDES_MASK__GC_SE_3_MASK = 0x00080000 # macro +RLC_SERDES_MASK__GC_SE_4_MASK = 0x00100000 # macro +RLC_SERDES_MASK__GC_SE_5_MASK = 0x00200000 # macro +RLC_SERDES_MASK__GC_SE_6_MASK = 0x00400000 # macro +RLC_SERDES_MASK__GC_SE_7_MASK = 0x00800000 # macro +RLC_SERDES_MASK__RESERVED_31_24_MASK = 0xFF000000 # macro +RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT = 0x0 # macro +RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT = 0x1 # macro +RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT = 0x2 # macro +RLC_SERDES_CTRL__BPM_ADDR__SHIFT = 0x3 # macro +RLC_SERDES_CTRL__REG_ADDR__SHIFT = 0x10 # macro +RLC_SERDES_CTRL__BPM_BROADCAST_MASK = 0x000001 # macro +RLC_SERDES_CTRL__BPM_REG_WRITE_MASK = 0x000002 # macro +RLC_SERDES_CTRL__BPM_LONG_CMD_MASK = 0x000004 # macro +RLC_SERDES_CTRL__BPM_ADDR_MASK = 0x00FFF8 # macro +RLC_SERDES_CTRL__REG_ADDR_MASK = 0xFF0000 # macro +RLC_SERDES_DATA__DATA__SHIFT = 0x0 # macro +RLC_SERDES_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT = 0x0 # macro +RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT = 0x1 # macro +RLC_SERDES_BUSY__RESERVED__SHIFT = 0x2 # macro +RLC_SERDES_BUSY__GC_SE_0__SHIFT = 0x10 # macro +RLC_SERDES_BUSY__GC_SE_1__SHIFT = 0x11 # macro +RLC_SERDES_BUSY__GC_SE_2__SHIFT = 0x12 # macro +RLC_SERDES_BUSY__GC_SE_3__SHIFT = 0x13 # macro +RLC_SERDES_BUSY__GC_SE_4__SHIFT = 0x14 # macro +RLC_SERDES_BUSY__GC_SE_5__SHIFT = 0x15 # macro +RLC_SERDES_BUSY__GC_SE_6__SHIFT = 0x16 # macro +RLC_SERDES_BUSY__GC_SE_7__SHIFT = 0x17 # macro +RLC_SERDES_BUSY__RESERVED_29_24__SHIFT = 0x18 # macro +RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT = 0x1e # macro +RLC_SERDES_BUSY__RD_PENDING__SHIFT = 0x1f # macro +RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK = 0x00000001 # macro +RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK = 0x00000002 # macro +RLC_SERDES_BUSY__RESERVED_MASK = 0x0000FFFC # macro +RLC_SERDES_BUSY__GC_SE_0_MASK = 0x00010000 # macro +RLC_SERDES_BUSY__GC_SE_1_MASK = 0x00020000 # macro +RLC_SERDES_BUSY__GC_SE_2_MASK = 0x00040000 # macro +RLC_SERDES_BUSY__GC_SE_3_MASK = 0x00080000 # macro +RLC_SERDES_BUSY__GC_SE_4_MASK = 0x00100000 # macro +RLC_SERDES_BUSY__GC_SE_5_MASK = 0x00200000 # macro +RLC_SERDES_BUSY__GC_SE_6_MASK = 0x00400000 # macro +RLC_SERDES_BUSY__GC_SE_7_MASK = 0x00800000 # macro +RLC_SERDES_BUSY__RESERVED_29_24_MASK = 0x3F000000 # macro +RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK = 0x40000000 # macro +RLC_SERDES_BUSY__RD_PENDING_MASK = 0x80000000 # macro +RLC_GPM_GENERAL_0__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_1__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_2__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_3__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_3__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_4__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_4__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_5__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_5__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_6__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_6__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_7__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_7__DATA_MASK = 0xFFFFFFFF # macro +RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT = 0x0 # macro +RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_16__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_16__DATA_MASK = 0xFFFFFFFF # macro +RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT = 0x0 # macro +RLC_PG_DELAY_3__RESERVED__SHIFT = 0x8 # macro +RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK = 0x000000FF # macro +RLC_PG_DELAY_3__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_GPR_REG1__DATA__SHIFT = 0x0 # macro +RLC_GPR_REG1__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPR_REG2__DATA__SHIFT = 0x0 # macro +RLC_GPR_REG2__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT = 0x0 # macro +RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK = 0xFFFFFFFF # macro +RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT = 0x0 # macro +RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT = 0x1 # macro +RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT = 0x2 # macro +RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED__SHIFT = 0x3 # macro +RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK = 0x00000001 # macro +RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK = 0x00000002 # macro +RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK = 0x00000004 # macro +RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED_MASK = 0x00000008 # macro +RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT = 0x0 # macro +RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK = 0xFFFFFFFF # macro +RLC_SRM_CNTL__SRM_ENABLE__SHIFT = 0x0 # macro +RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT = 0x1 # macro +RLC_SRM_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_SRM_CNTL__SRM_ENABLE_MASK = 0x00000001 # macro +RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK = 0x00000002 # macro +RLC_SRM_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT = 0x0 # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT = 0x1 # macro +RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT = 0x2 # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK = 0x00000001 # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK = 0x00000002 # macro +RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK = 0x0003FFFF # macro +RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_STAT__SRM_BUSY__SHIFT = 0x0 # macro +RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT = 0x1 # macro +RLC_SRM_STAT__RESERVED__SHIFT = 0x2 # macro +RLC_SRM_STAT__SRM_BUSY_MASK = 0x00000001 # macro +RLC_SRM_STAT__SRM_BUSY_DELAY_MASK = 0x00000002 # macro +RLC_SRM_STAT__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_GPM_GENERAL_8__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_8__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_9__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_9__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_10__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_10__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_11__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_11__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_12__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_12__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT = 0x18 # macro +RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT = 0x19 # macro +RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT = 0x1a # macro +RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT = 0x1e # macro +RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK = 0x01000000 # macro +RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK = 0x02000000 # macro +RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK = 0x04000000 # macro +RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK = 0xC0000000 # macro +RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT = 0x18 # macro +RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT = 0x19 # macro +RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT = 0x1a # macro +RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT = 0x1e # macro +RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK = 0x01000000 # macro +RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK = 0x02000000 # macro +RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK = 0x04000000 # macro +RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK = 0xC0000000 # macro +RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT = 0x18 # macro +RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT = 0x19 # macro +RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT = 0x1a # macro +RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT = 0x1e # macro +RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK = 0x01000000 # macro +RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK = 0x02000000 # macro +RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK = 0x04000000 # macro +RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK = 0xC0000000 # macro +RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT = 0x19 # macro +RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT = 0x1e # macro +RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +RLC_SPM_UTCL1_CNTL__BYPASS_MASK = 0x02000000 # macro +RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_SPM_UTCL1_CNTL__RESERVED_MASK = 0xC0000000 # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT = 0x0 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT = 0x1 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT = 0x2 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT = 0x3 # macro +RLC_UTCL1_STATUS_2__RESERVED_1__SHIFT = 0x4 # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT = 0x5 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT = 0x6 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT = 0x7 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT = 0x8 # macro +RLC_UTCL1_STATUS_2__RESERVED__SHIFT = 0x9 # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK = 0x00000001 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK = 0x00000002 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK = 0x00000004 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK = 0x00000008 # macro +RLC_UTCL1_STATUS_2__RESERVED_1_MASK = 0x00000010 # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK = 0x00000020 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK = 0x00000040 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK = 0x00000080 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK = 0x00000100 # macro +RLC_UTCL1_STATUS_2__RESERVED_MASK = 0xFFFFFE00 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT = 0x0 # macro +RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT = 0x1 # macro +RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT = 0x2 # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT = 0x8 # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT = 0x1b # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT = 0x1c # macro +RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT = 0x1d # macro +RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT = 0x1f # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK = 0x00000001 # macro +RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK = 0x00000002 # macro +RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK = 0x000000FC # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK = 0x07FFFF00 # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK = 0x08000000 # macro +RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK = 0x10000000 # macro +RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK = 0x60000000 # macro +RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK = 0x80000000 # macro +RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT = 0x0 # macro +RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT = 0x4 # macro +RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT = 0x8 # macro +RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT = 0xc # macro +RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT = 0x10 # macro +RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT = 0x1c # macro +RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK = 0x0000000F # macro +RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK = 0x000000F0 # macro +RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK = 0x00000F00 # macro +RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK = 0x0000F000 # macro +RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK = 0x0FFF0000 # macro +RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK = 0xF0000000 # macro +RLC_SEMAPHORE_0__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_0__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_0__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_0__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_SEMAPHORE_1__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_1__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_1__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_1__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_SEMAPHORE_2__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_2__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_2__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_2__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_SEMAPHORE_3__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_3__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_3__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_3__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_PACE_INT_STAT__STATUS__SHIFT = 0x0 # macro +RLC_PACE_INT_STAT__STATUS_MASK = 0xFFFFFFFF # macro +RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +RLC_UTCL1_STATUS__RESERVED__SHIFT = 0x3 # macro +RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +RLC_UTCL1_STATUS__RESERVED_1__SHIFT = 0xe # macro +RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +RLC_UTCL1_STATUS__RESERVED_2__SHIFT = 0x16 # macro +RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +RLC_UTCL1_STATUS__RESERVED_3__SHIFT = 0x1e # macro +RLC_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +RLC_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +RLC_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +RLC_UTCL1_STATUS__RESERVED_MASK = 0x000000F8 # macro +RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +RLC_UTCL1_STATUS__RESERVED_1_MASK = 0x0000C000 # macro +RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +RLC_UTCL1_STATUS__RESERVED_2_MASK = 0x00C00000 # macro +RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +RLC_UTCL1_STATUS__RESERVED_3_MASK = 0xC0000000 # macro +RLC_R2I_CNTL_0__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_0__Data_MASK = 0xFFFFFFFF # macro +RLC_R2I_CNTL_1__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_1__Data_MASK = 0xFFFFFFFF # macro +RLC_R2I_CNTL_2__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_2__Data_MASK = 0xFFFFFFFF # macro +RLC_R2I_CNTL_3__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_3__Data_MASK = 0xFFFFFFFF # macro +RLC_GPM_INT_STAT_TH0__STATUS__SHIFT = 0x0 # macro +RLC_GPM_INT_STAT_TH0__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_13__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_13__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_14__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_14__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_15__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_15__DATA_MASK = 0xFFFFFFFF # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT = 0x0 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT = 0x1 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK = 0x00000001 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK = 0xFFFFFFFF # macro +RLC_PACE_INT_DISABLE__DISABLE_INT__SHIFT = 0x0 # macro +RLC_PACE_INT_DISABLE__DISABLE_INT_MASK = 0xFFFFFFFF # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT = 0x0 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT = 0x1 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK = 0x00000001 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT = 0x2 # macro +RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT = 0x10 # macro +RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT = 0x12 # macro +RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK = 0x00000003 # macro +RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK = 0x00000FFC # macro +RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK = 0x00030000 # macro +RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK = 0x0FFC0000 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT = 0x2 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT = 0x4 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT = 0x6 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT = 0x10 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT = 0x15 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK = 0x00000003 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK = 0x0000000C # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK = 0x00000030 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK = 0x000000C0 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK = 0x001F0000 # macro +RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK = 0x00200000 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT = 0x1 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT = 0x2 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT = 0x3 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK = 0x00000001 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK = 0x00000002 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK = 0x00000004 # macro +RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK = 0x00000008 # macro +RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK = 0xFFFFFFFF # macro +RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT = 0x0 # macro +RLC_RLCV_SPARE_INT__RESERVED__SHIFT = 0x1 # macro +RLC_RLCV_SPARE_INT__INTERRUPT_MASK = 0x00000001 # macro +RLC_RLCV_SPARE_INT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_PACE_TIMER_INT_0__TIMER__SHIFT = 0x0 # macro +RLC_PACE_TIMER_INT_0__TIMER_MASK = 0xFFFFFFFF # macro +RLC_PACE_TIMER_INT_1__TIMER__SHIFT = 0x0 # macro +RLC_PACE_TIMER_INT_1__TIMER_MASK = 0xFFFFFFFF # macro +RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT = 0x0 # macro +RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT = 0x1 # macro +RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT = 0x2 # macro +RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT = 0x3 # macro +RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT = 0x4 # macro +RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT = 0x5 # macro +RLC_PACE_TIMER_CTRL__RESERVED__SHIFT = 0x6 # macro +RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK = 0x00000001 # macro +RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK = 0x00000002 # macro +RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK = 0x00000004 # macro +RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK = 0x00000008 # macro +RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK = 0x00000010 # macro +RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK = 0x00000020 # macro +RLC_PACE_TIMER_CTRL__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_SMU_CLK_REQ__VALID__SHIFT = 0x0 # macro +RLC_SMU_CLK_REQ__VALID_MASK = 0x00000001 # macro +RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT = 0x0 # macro +RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT = 0x1 # macro +RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT = 0x2 # macro +RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT = 0x3 # macro +RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT = 0x4 # macro +RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT = 0x5 # macro +RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK = 0x00000001 # macro +RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK = 0x00000002 # macro +RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK = 0x00000004 # macro +RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK = 0x00000008 # macro +RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK = 0x00000010 # macro +RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK = 0x00000020 # macro +RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT = 0x0 # macro +RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT = 0x1 # macro +RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT = 0x2 # macro +RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK = 0x00000001 # macro +RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK = 0x00000002 # macro +RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK = 0x00000004 # macro +RLC_SPARE__SPARE__SHIFT = 0x0 # macro +RLC_SPARE__SPARE_MASK = 0xFFFFFFFF # macro +RLC_SPP_CTRL__ENABLE__SHIFT = 0x0 # macro +RLC_SPP_CTRL__ENABLE_PPROF__SHIFT = 0x1 # macro +RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT = 0x2 # macro +RLC_SPP_CTRL__PAUSE__SHIFT = 0x3 # macro +RLC_SPP_CTRL__ENABLE_MASK = 0x00000001 # macro +RLC_SPP_CTRL__ENABLE_PPROF_MASK = 0x00000002 # macro +RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK = 0x00000004 # macro +RLC_SPP_CTRL__PAUSE_MASK = 0x00000008 # macro +RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT = 0x0 # macro +RLC_SPP_SHADER_PROFILE_EN__RESERVED_1__SHIFT = 0x1 # macro +RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT = 0x2 # macro +RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT = 0x3 # macro +RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT = 0x4 # macro +RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT = 0x5 # macro +RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT = 0x6 # macro +RLC_SPP_SHADER_PROFILE_EN__RESERVED_7__SHIFT = 0x7 # macro +RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT = 0x8 # macro +RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT = 0x9 # macro +RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT = 0xa # macro +RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT = 0xb # macro +RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT = 0xc # macro +RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT = 0xd # macro +RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT = 0xe # macro +RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT = 0xf # macro +RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT = 0x10 # macro +RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK = 0x00000001 # macro +RLC_SPP_SHADER_PROFILE_EN__RESERVED_1_MASK = 0x00000002 # macro +RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK = 0x00000004 # macro +RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK = 0x00000008 # macro +RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK = 0x00000010 # macro +RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK = 0x00000020 # macro +RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK = 0x00000040 # macro +RLC_SPP_SHADER_PROFILE_EN__RESERVED_7_MASK = 0x00000080 # macro +RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK = 0x00000100 # macro +RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK = 0x00000200 # macro +RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK = 0x00000400 # macro +RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK = 0x00000800 # macro +RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK = 0x00001000 # macro +RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK = 0x00002000 # macro +RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK = 0x00004000 # macro +RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK = 0x00008000 # macro +RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK = 0x00010000 # macro +RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT = 0x0 # macro +RLC_SPP_SSF_CAPTURE_EN__RESERVED_1__SHIFT = 0x1 # macro +RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT = 0x2 # macro +RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT = 0x3 # macro +RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT = 0x4 # macro +RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT = 0x5 # macro +RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK = 0x00000001 # macro +RLC_SPP_SSF_CAPTURE_EN__RESERVED_1_MASK = 0x00000002 # macro +RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK = 0x00000004 # macro +RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK = 0x00000008 # macro +RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK = 0x00000010 # macro +RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK = 0x00000020 # macro +RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT = 0x0 # macro +RLC_SPP_SSF_THRESHOLD_0__RESERVED__SHIFT = 0x10 # macro +RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK = 0x0000FFFF # macro +RLC_SPP_SSF_THRESHOLD_0__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT = 0x0 # macro +RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT = 0x10 # macro +RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK = 0x0000FFFF # macro +RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK = 0xFFFF0000 # macro +RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT = 0x0 # macro +RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT = 0x10 # macro +RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK = 0x0000FFFF # macro +RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK = 0xFFFF0000 # macro +RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK = 0x0000001F # macro +RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT = 0x0 # macro +RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SPP_PROF_INFO_1__SH_ID__SHIFT = 0x0 # macro +RLC_SPP_PROF_INFO_1__SH_ID_MASK = 0xFFFFFFFF # macro +RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT = 0x0 # macro +RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT = 0x4 # macro +RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT = 0x5 # macro +RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT = 0x6 # macro +RLC_SPP_PROF_INFO_2__SH_TYPE_MASK = 0x0000000F # macro +RLC_SPP_PROF_INFO_2__CAM_HIT_MASK = 0x00000010 # macro +RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK = 0x00000020 # macro +RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK = 0x00000040 # macro +RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT = 0x0 # macro +RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK = 0xFFFFFFFF # macro +RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT = 0x0 # macro +RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK = 0x00000001 # macro +RLC_SPP_STATUS__RESERVED_0__SHIFT = 0x0 # macro +RLC_SPP_STATUS__SSF_BUSY__SHIFT = 0x1 # macro +RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT = 0x2 # macro +RLC_SPP_STATUS__SPP_BUSY__SHIFT = 0x1f # macro +RLC_SPP_STATUS__RESERVED_0_MASK = 0x00000001 # macro +RLC_SPP_STATUS__SSF_BUSY_MASK = 0x00000002 # macro +RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK = 0x00000004 # macro +RLC_SPP_STATUS__SPP_BUSY_MASK = 0x80000000 # macro +RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT = 0x0 # macro +RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT = 0x6 # macro +RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT = 0xc # macro +RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT = 0x12 # macro +RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT = 0x18 # macro +RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK = 0x0000003F # macro +RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK = 0x00000FC0 # macro +RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK = 0x0003F000 # macro +RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK = 0x00FC0000 # macro +RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK = 0x7F000000 # macro +RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT = 0x0 # macro +RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT = 0x6 # macro +RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT = 0xc # macro +RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT = 0x12 # macro +RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT = 0x18 # macro +RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK = 0x0000003F # macro +RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK = 0x00000FC0 # macro +RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK = 0x0003F000 # macro +RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK = 0x00FC0000 # macro +RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK = 0x7F000000 # macro +RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT = 0x0 # macro +RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT = 0x6 # macro +RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT = 0xc # macro +RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT = 0x12 # macro +RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT = 0x18 # macro +RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK = 0x0000003F # macro +RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK = 0x00000FC0 # macro +RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK = 0x0003F000 # macro +RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK = 0x00FC0000 # macro +RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK = 0x7F000000 # macro +RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT = 0x0 # macro +RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK = 0x0000003F # macro +RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT = 0x0 # macro +RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK = 0x0000000F # macro +RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT = 0x0 # macro +RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT = 0x1 # macro +RLC_SPP_STALL_STATE_UPDATE__STALL_MASK = 0x00000001 # macro +RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK = 0x00000002 # macro +RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT = 0x0 # macro +RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT = 0x1 # macro +RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT = 0x2 # macro +RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT = 0x3 # macro +RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK = 0x00000001 # macro +RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK = 0x00000002 # macro +RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK = 0x00000004 # macro +RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK = 0x00000008 # macro +RLC_SPP_RESET__SSF_RESET__SHIFT = 0x0 # macro +RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT = 0x1 # macro +RLC_SPP_RESET__CAM_RESET__SHIFT = 0x2 # macro +RLC_SPP_RESET__PVT_RESET__SHIFT = 0x3 # macro +RLC_SPP_RESET__SSF_RESET_MASK = 0x00000001 # macro +RLC_SPP_RESET__EVENT_ARB_RESET_MASK = 0x00000002 # macro +RLC_SPP_RESET__CAM_RESET_MASK = 0x00000004 # macro +RLC_SPP_RESET__PVT_RESET_MASK = 0x00000008 # macro +RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR__SHIFT = 0x2 # macro +RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT = 0x10 # macro +RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR__SHIFT = 0x12 # macro +RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK = 0x00000003 # macro +RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_MASK = 0x00000FFC # macro +RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK = 0x00030000 # macro +RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_MASK = 0x0FFC0000 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT = 0x2 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT = 0x4 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT = 0x6 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID__SHIFT = 0x10 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT = 0x15 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE_MASK = 0x00000003 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE_MASK = 0x0000000C # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE_MASK = 0x00000030 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE_MASK = 0x000000C0 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_MASK = 0x001F0000 # macro +RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN_MASK = 0x00200000 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT = 0x1 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT = 0x2 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT = 0x3 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID_MASK = 0x00000001 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID_MASK = 0x00000002 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID_MASK = 0x00000004 # macro +RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID_MASK = 0x00000008 # macro +RLC_RLCP_DOORBELL_0_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_0_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_DOORBELL_0_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_0_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_DOORBELL_1_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_1_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_DOORBELL_1_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_1_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_DOORBELL_2_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_2_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_DOORBELL_2_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_2_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_DOORBELL_3_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_3_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_DOORBELL_3_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_RLCP_DOORBELL_3_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT = 0x0 # macro +RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK = 0xFFFFFFFF # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__RESET__SHIFT = 0x0 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT = 0x1 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT = 0x2 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT = 0x3 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT = 0x4 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT = 0x5 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_MASK = 0x00000001 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_MASK = 0x00000002 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK = 0x00000004 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK = 0x00000008 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK = 0x00000010 # macro +RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__RESET__SHIFT = 0x0 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT = 0x1 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT = 0x2 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT = 0x3 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT = 0x4 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT = 0x5 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_MASK = 0x00000001 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_MASK = 0x00000002 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK = 0x00000004 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK = 0x00000008 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK = 0x00000010 # macro +RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__RESET__SHIFT = 0x0 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT = 0x1 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT = 0x2 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT = 0x3 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT = 0x4 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT = 0x5 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__RESET_MASK = 0x00000001 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_MASK = 0x00000002 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK = 0x00000004 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK = 0x00000008 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK = 0x00000010 # macro +RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__RESET__SHIFT = 0x0 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT = 0x1 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT = 0x2 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT = 0x3 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT = 0x4 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT = 0x5 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_MASK = 0x00000001 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_MASK = 0x00000002 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK = 0x00000004 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK = 0x00000008 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK = 0x00000010 # macro +RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__RESET__SHIFT = 0x0 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT = 0x1 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT = 0x2 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT = 0x3 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT = 0x4 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL__SHIFT = 0x5 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT = 0x9 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_MASK = 0x00000001 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_MASK = 0x00000002 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK = 0x00000004 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK = 0x00000008 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK = 0x00000010 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL_MASK = 0x000001E0 # macro +RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED_MASK = 0xFFFFFE00 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET__SHIFT = 0x0 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT = 0x1 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT = 0x2 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT = 0x3 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT = 0x4 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT = 0x5 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_MASK = 0x00000001 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_MASK = 0x00000002 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK = 0x00000004 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK = 0x00000008 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK = 0x00000010 # macro +RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_POWER_RESIDENCY_EVENT_CNTR__DATA__SHIFT = 0x0 # macro +RLC_POWER_RESIDENCY_EVENT_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_CLK_RESIDENCY_EVENT_CNTR__DATA__SHIFT = 0x0 # macro +RLC_CLK_RESIDENCY_EVENT_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_DS_RESIDENCY_EVENT_CNTR__DATA__SHIFT = 0x0 # macro +RLC_DS_RESIDENCY_EVENT_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_ULV_RESIDENCY_EVENT_CNTR__DATA__SHIFT = 0x0 # macro +RLC_ULV_RESIDENCY_EVENT_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_PCC_RESIDENCY_EVENT_CNTR__DATA__SHIFT = 0x0 # macro +RLC_PCC_RESIDENCY_EVENT_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA__SHIFT = 0x0 # macro +RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_POWER_RESIDENCY_REF_CNTR__DATA__SHIFT = 0x0 # macro +RLC_POWER_RESIDENCY_REF_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_CLK_RESIDENCY_REF_CNTR__DATA__SHIFT = 0x0 # macro +RLC_CLK_RESIDENCY_REF_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_DS_RESIDENCY_REF_CNTR__DATA__SHIFT = 0x0 # macro +RLC_DS_RESIDENCY_REF_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_ULV_RESIDENCY_REF_CNTR__DATA__SHIFT = 0x0 # macro +RLC_ULV_RESIDENCY_REF_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_PCC_RESIDENCY_REF_CNTR__DATA__SHIFT = 0x0 # macro +RLC_PCC_RESIDENCY_REF_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_GENERAL_RESIDENCY_REF_CNTR__DATA__SHIFT = 0x0 # macro +RLC_GENERAL_RESIDENCY_REF_CNTR__DATA_MASK = 0xFFFFFFFF # macro +RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK__SHIFT = 0x0 # macro +RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK__SHIFT = 0x8 # macro +RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK__SHIFT = 0xc # macro +RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK__SHIFT = 0xd # macro +RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_14__SHIFT = 0xe # macro +RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR__SHIFT = 0x10 # macro +RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR__SHIFT = 0x18 # macro +RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR__SHIFT = 0x1c # macro +RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR__SHIFT = 0x1d # macro +RLC_GFX_IH_CLIENT_CTRL__RESERVED_31_30__SHIFT = 0x1e # macro +RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK_MASK = 0x000000FF # macro +RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK_MASK = 0x00000F00 # macro +RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK_MASK = 0x00001000 # macro +RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK_MASK = 0x00002000 # macro +RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_14_MASK = 0x0000C000 # macro +RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR_MASK = 0x00FF0000 # macro +RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR_MASK = 0x0F000000 # macro +RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR_MASK = 0x10000000 # macro +RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR_MASK = 0x20000000 # macro +RLC_GFX_IH_CLIENT_CTRL__RESERVED_31_30_MASK = 0xC0000000 # macro +RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED__SHIFT = 0x0 # macro +RLC_GFX_IH_ARBITER_STAT__RESERVED__SHIFT = 0x10 # macro +RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED__SHIFT = 0x1c # macro +RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED_MASK = 0x0000FFFF # macro +RLC_GFX_IH_ARBITER_STAT__RESERVED_MASK = 0x0FFF0000 # macro +RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED_MASK = 0xF0000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL__SHIFT = 0x0 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING__SHIFT = 0x4 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW__SHIFT = 0x5 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR__SHIFT = 0x6 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED__SHIFT = 0x7 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL__SHIFT = 0x8 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING__SHIFT = 0xc # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW__SHIFT = 0xd # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR__SHIFT = 0xe # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED__SHIFT = 0xf # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL__SHIFT = 0x10 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING__SHIFT = 0x14 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW__SHIFT = 0x15 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR__SHIFT = 0x16 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED__SHIFT = 0x17 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL__SHIFT = 0x18 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING__SHIFT = 0x1c # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW__SHIFT = 0x1d # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR__SHIFT = 0x1e # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED__SHIFT = 0x1f # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL_MASK = 0x0000000F # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING_MASK = 0x00000010 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW_MASK = 0x00000020 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR_MASK = 0x00000040 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED_MASK = 0x00000080 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL_MASK = 0x00000F00 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING_MASK = 0x00001000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW_MASK = 0x00002000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR_MASK = 0x00004000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED_MASK = 0x00008000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL_MASK = 0x000F0000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING_MASK = 0x00100000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW_MASK = 0x00200000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR_MASK = 0x00400000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED_MASK = 0x00800000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL_MASK = 0x0F000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING_MASK = 0x10000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW_MASK = 0x20000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR_MASK = 0x40000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED_MASK = 0x80000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL__SHIFT = 0x0 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING__SHIFT = 0x4 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW__SHIFT = 0x5 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR__SHIFT = 0x6 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED__SHIFT = 0x7 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL__SHIFT = 0x8 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING__SHIFT = 0xc # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW__SHIFT = 0xd # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR__SHIFT = 0xe # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED__SHIFT = 0xf # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL__SHIFT = 0x10 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING__SHIFT = 0x14 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW__SHIFT = 0x15 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR__SHIFT = 0x16 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED__SHIFT = 0x17 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL__SHIFT = 0x18 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING__SHIFT = 0x1c # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW__SHIFT = 0x1d # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR__SHIFT = 0x1e # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED__SHIFT = 0x1f # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL_MASK = 0x0000000F # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING_MASK = 0x00000010 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW_MASK = 0x00000020 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR_MASK = 0x00000040 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED_MASK = 0x00000080 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL_MASK = 0x00000F00 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING_MASK = 0x00001000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW_MASK = 0x00002000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR_MASK = 0x00004000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED_MASK = 0x00008000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL_MASK = 0x000F0000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING_MASK = 0x00100000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW_MASK = 0x00200000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR_MASK = 0x00400000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED_MASK = 0x00800000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL_MASK = 0x0F000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING_MASK = 0x10000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW_MASK = 0x20000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR_MASK = 0x40000000 # macro +RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED_MASK = 0x80000000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL__SHIFT = 0x0 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING__SHIFT = 0x4 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW__SHIFT = 0x5 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR__SHIFT = 0x6 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED__SHIFT = 0x7 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL__SHIFT = 0x8 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING__SHIFT = 0xc # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW__SHIFT = 0xd # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR__SHIFT = 0xe # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED__SHIFT = 0xf # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL__SHIFT = 0x10 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING__SHIFT = 0x14 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW__SHIFT = 0x15 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR__SHIFT = 0x16 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED__SHIFT = 0x17 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL__SHIFT = 0x18 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING__SHIFT = 0x1c # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW__SHIFT = 0x1d # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR__SHIFT = 0x1e # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED__SHIFT = 0x1f # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL_MASK = 0x0000000F # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING_MASK = 0x00000010 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW_MASK = 0x00000020 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR_MASK = 0x00000040 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED_MASK = 0x00000080 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL_MASK = 0x00000F00 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING_MASK = 0x00001000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW_MASK = 0x00002000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR_MASK = 0x00004000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED_MASK = 0x00008000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL_MASK = 0x000F0000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING_MASK = 0x00100000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW_MASK = 0x00200000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR_MASK = 0x00400000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED_MASK = 0x00800000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL_MASK = 0x0F000000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING_MASK = 0x10000000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW_MASK = 0x20000000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR_MASK = 0x40000000 # macro +RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED_MASK = 0x80000000 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL__SHIFT = 0x0 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING__SHIFT = 0x4 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW__SHIFT = 0x5 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR__SHIFT = 0x6 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED__SHIFT = 0x7 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL__SHIFT = 0x8 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING__SHIFT = 0xc # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW__SHIFT = 0xd # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR__SHIFT = 0xe # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED__SHIFT = 0xf # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_16__SHIFT = 0x10 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL_MASK = 0x0000000F # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING_MASK = 0x00000010 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW_MASK = 0x00000020 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR_MASK = 0x00000040 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED_MASK = 0x00000080 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL_MASK = 0x00000F00 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING_MASK = 0x00001000 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW_MASK = 0x00002000 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR_MASK = 0x00004000 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED_MASK = 0x00008000 # macro +RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_16_MASK = 0xFFFF0000 # macro +RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR_MASK = 0x00000FFF # macro +RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA__SHIFT = 0x0 # macro +RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA_MASK = 0x0000003F # macro +RLC_SPM_SE_DELAY_IND_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SPM_SE_DELAY_IND_ADDR__ADDR_MASK = 0x00000FFF # macro +RLC_SPM_SE_DELAY_IND_DATA__DATA__SHIFT = 0x0 # macro +RLC_SPM_SE_DELAY_IND_DATA__DATA_MASK = 0x0000003F # macro +RLC_LX6_CNTL__BRESET__SHIFT = 0x0 # macro +RLC_LX6_CNTL__RUNSTALL__SHIFT = 0x1 # macro +RLC_LX6_CNTL__PDEBUG_ENABLE__SHIFT = 0x2 # macro +RLC_LX6_CNTL__STAT_VECTOR_SEL__SHIFT = 0x3 # macro +RLC_LX6_CNTL__BRESET_MASK = 0x00000001 # macro +RLC_LX6_CNTL__RUNSTALL_MASK = 0x00000002 # macro +RLC_LX6_CNTL__PDEBUG_ENABLE_MASK = 0x00000004 # macro +RLC_LX6_CNTL__STAT_VECTOR_SEL_MASK = 0x00000008 # macro +RLC_XT_CORE_STATUS__P_WAIT_MODE__SHIFT = 0x0 # macro +RLC_XT_CORE_STATUS__P_FATAL_ERROR__SHIFT = 0x1 # macro +RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR__SHIFT = 0x2 # macro +RLC_XT_CORE_STATUS__P_WAIT_MODE_MASK = 0x00000001 # macro +RLC_XT_CORE_STATUS__P_FATAL_ERROR_MASK = 0x00000002 # macro +RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR_MASK = 0x00000004 # macro +RLC_XT_CORE_INTERRUPT__EXTINT1__SHIFT = 0x0 # macro +RLC_XT_CORE_INTERRUPT__EXTINT2__SHIFT = 0x1a # macro +RLC_XT_CORE_INTERRUPT__NMI__SHIFT = 0x1b # macro +RLC_XT_CORE_INTERRUPT__EXTINT1_MASK = 0x03FFFFFF # macro +RLC_XT_CORE_INTERRUPT__EXTINT2_MASK = 0x04000000 # macro +RLC_XT_CORE_INTERRUPT__NMI_MASK = 0x08000000 # macro +RLC_XT_CORE_FAULT_INFO__FAULT_INFO__SHIFT = 0x0 # macro +RLC_XT_CORE_FAULT_INFO__FAULT_INFO_MASK = 0xFFFFFFFF # macro +RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC__SHIFT = 0x0 # macro +RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC_MASK = 0xFFFFFFFF # macro +RLC_XT_CORE_RESERVED__RESERVED__SHIFT = 0x0 # macro +RLC_XT_CORE_RESERVED__RESERVED_MASK = 0xFFFFFFFF # macro +RLC_XT_INT_VEC_FORCE__NUM_0__SHIFT = 0x0 # macro +RLC_XT_INT_VEC_FORCE__NUM_1__SHIFT = 0x1 # macro +RLC_XT_INT_VEC_FORCE__NUM_2__SHIFT = 0x2 # macro +RLC_XT_INT_VEC_FORCE__NUM_3__SHIFT = 0x3 # macro +RLC_XT_INT_VEC_FORCE__NUM_4__SHIFT = 0x4 # macro +RLC_XT_INT_VEC_FORCE__NUM_5__SHIFT = 0x5 # macro +RLC_XT_INT_VEC_FORCE__NUM_6__SHIFT = 0x6 # macro +RLC_XT_INT_VEC_FORCE__NUM_7__SHIFT = 0x7 # macro +RLC_XT_INT_VEC_FORCE__NUM_8__SHIFT = 0x8 # macro +RLC_XT_INT_VEC_FORCE__NUM_9__SHIFT = 0x9 # macro +RLC_XT_INT_VEC_FORCE__NUM_10__SHIFT = 0xa # macro +RLC_XT_INT_VEC_FORCE__NUM_11__SHIFT = 0xb # macro +RLC_XT_INT_VEC_FORCE__NUM_12__SHIFT = 0xc # macro +RLC_XT_INT_VEC_FORCE__NUM_13__SHIFT = 0xd # macro +RLC_XT_INT_VEC_FORCE__NUM_14__SHIFT = 0xe # macro +RLC_XT_INT_VEC_FORCE__NUM_15__SHIFT = 0xf # macro +RLC_XT_INT_VEC_FORCE__NUM_16__SHIFT = 0x10 # macro +RLC_XT_INT_VEC_FORCE__NUM_17__SHIFT = 0x11 # macro +RLC_XT_INT_VEC_FORCE__NUM_18__SHIFT = 0x12 # macro +RLC_XT_INT_VEC_FORCE__NUM_19__SHIFT = 0x13 # macro +RLC_XT_INT_VEC_FORCE__NUM_20__SHIFT = 0x14 # macro +RLC_XT_INT_VEC_FORCE__NUM_21__SHIFT = 0x15 # macro +RLC_XT_INT_VEC_FORCE__NUM_22__SHIFT = 0x16 # macro +RLC_XT_INT_VEC_FORCE__NUM_23__SHIFT = 0x17 # macro +RLC_XT_INT_VEC_FORCE__NUM_24__SHIFT = 0x18 # macro +RLC_XT_INT_VEC_FORCE__NUM_25__SHIFT = 0x19 # macro +RLC_XT_INT_VEC_FORCE__NUM_0_MASK = 0x00000001 # macro +RLC_XT_INT_VEC_FORCE__NUM_1_MASK = 0x00000002 # macro +RLC_XT_INT_VEC_FORCE__NUM_2_MASK = 0x00000004 # macro +RLC_XT_INT_VEC_FORCE__NUM_3_MASK = 0x00000008 # macro +RLC_XT_INT_VEC_FORCE__NUM_4_MASK = 0x00000010 # macro +RLC_XT_INT_VEC_FORCE__NUM_5_MASK = 0x00000020 # macro +RLC_XT_INT_VEC_FORCE__NUM_6_MASK = 0x00000040 # macro +RLC_XT_INT_VEC_FORCE__NUM_7_MASK = 0x00000080 # macro +RLC_XT_INT_VEC_FORCE__NUM_8_MASK = 0x00000100 # macro +RLC_XT_INT_VEC_FORCE__NUM_9_MASK = 0x00000200 # macro +RLC_XT_INT_VEC_FORCE__NUM_10_MASK = 0x00000400 # macro +RLC_XT_INT_VEC_FORCE__NUM_11_MASK = 0x00000800 # macro +RLC_XT_INT_VEC_FORCE__NUM_12_MASK = 0x00001000 # macro +RLC_XT_INT_VEC_FORCE__NUM_13_MASK = 0x00002000 # macro +RLC_XT_INT_VEC_FORCE__NUM_14_MASK = 0x00004000 # macro +RLC_XT_INT_VEC_FORCE__NUM_15_MASK = 0x00008000 # macro +RLC_XT_INT_VEC_FORCE__NUM_16_MASK = 0x00010000 # macro +RLC_XT_INT_VEC_FORCE__NUM_17_MASK = 0x00020000 # macro +RLC_XT_INT_VEC_FORCE__NUM_18_MASK = 0x00040000 # macro +RLC_XT_INT_VEC_FORCE__NUM_19_MASK = 0x00080000 # macro +RLC_XT_INT_VEC_FORCE__NUM_20_MASK = 0x00100000 # macro +RLC_XT_INT_VEC_FORCE__NUM_21_MASK = 0x00200000 # macro +RLC_XT_INT_VEC_FORCE__NUM_22_MASK = 0x00400000 # macro +RLC_XT_INT_VEC_FORCE__NUM_23_MASK = 0x00800000 # macro +RLC_XT_INT_VEC_FORCE__NUM_24_MASK = 0x01000000 # macro +RLC_XT_INT_VEC_FORCE__NUM_25_MASK = 0x02000000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_0__SHIFT = 0x0 # macro +RLC_XT_INT_VEC_CLEAR__NUM_1__SHIFT = 0x1 # macro +RLC_XT_INT_VEC_CLEAR__NUM_2__SHIFT = 0x2 # macro +RLC_XT_INT_VEC_CLEAR__NUM_3__SHIFT = 0x3 # macro +RLC_XT_INT_VEC_CLEAR__NUM_4__SHIFT = 0x4 # macro +RLC_XT_INT_VEC_CLEAR__NUM_5__SHIFT = 0x5 # macro +RLC_XT_INT_VEC_CLEAR__NUM_6__SHIFT = 0x6 # macro +RLC_XT_INT_VEC_CLEAR__NUM_7__SHIFT = 0x7 # macro +RLC_XT_INT_VEC_CLEAR__NUM_8__SHIFT = 0x8 # macro +RLC_XT_INT_VEC_CLEAR__NUM_9__SHIFT = 0x9 # macro +RLC_XT_INT_VEC_CLEAR__NUM_10__SHIFT = 0xa # macro +RLC_XT_INT_VEC_CLEAR__NUM_11__SHIFT = 0xb # macro +RLC_XT_INT_VEC_CLEAR__NUM_12__SHIFT = 0xc # macro +RLC_XT_INT_VEC_CLEAR__NUM_13__SHIFT = 0xd # macro +RLC_XT_INT_VEC_CLEAR__NUM_14__SHIFT = 0xe # macro +RLC_XT_INT_VEC_CLEAR__NUM_15__SHIFT = 0xf # macro +RLC_XT_INT_VEC_CLEAR__NUM_16__SHIFT = 0x10 # macro +RLC_XT_INT_VEC_CLEAR__NUM_17__SHIFT = 0x11 # macro +RLC_XT_INT_VEC_CLEAR__NUM_18__SHIFT = 0x12 # macro +RLC_XT_INT_VEC_CLEAR__NUM_19__SHIFT = 0x13 # macro +RLC_XT_INT_VEC_CLEAR__NUM_20__SHIFT = 0x14 # macro +RLC_XT_INT_VEC_CLEAR__NUM_21__SHIFT = 0x15 # macro +RLC_XT_INT_VEC_CLEAR__NUM_22__SHIFT = 0x16 # macro +RLC_XT_INT_VEC_CLEAR__NUM_23__SHIFT = 0x17 # macro +RLC_XT_INT_VEC_CLEAR__NUM_24__SHIFT = 0x18 # macro +RLC_XT_INT_VEC_CLEAR__NUM_25__SHIFT = 0x19 # macro +RLC_XT_INT_VEC_CLEAR__NUM_0_MASK = 0x00000001 # macro +RLC_XT_INT_VEC_CLEAR__NUM_1_MASK = 0x00000002 # macro +RLC_XT_INT_VEC_CLEAR__NUM_2_MASK = 0x00000004 # macro +RLC_XT_INT_VEC_CLEAR__NUM_3_MASK = 0x00000008 # macro +RLC_XT_INT_VEC_CLEAR__NUM_4_MASK = 0x00000010 # macro +RLC_XT_INT_VEC_CLEAR__NUM_5_MASK = 0x00000020 # macro +RLC_XT_INT_VEC_CLEAR__NUM_6_MASK = 0x00000040 # macro +RLC_XT_INT_VEC_CLEAR__NUM_7_MASK = 0x00000080 # macro +RLC_XT_INT_VEC_CLEAR__NUM_8_MASK = 0x00000100 # macro +RLC_XT_INT_VEC_CLEAR__NUM_9_MASK = 0x00000200 # macro +RLC_XT_INT_VEC_CLEAR__NUM_10_MASK = 0x00000400 # macro +RLC_XT_INT_VEC_CLEAR__NUM_11_MASK = 0x00000800 # macro +RLC_XT_INT_VEC_CLEAR__NUM_12_MASK = 0x00001000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_13_MASK = 0x00002000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_14_MASK = 0x00004000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_15_MASK = 0x00008000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_16_MASK = 0x00010000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_17_MASK = 0x00020000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_18_MASK = 0x00040000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_19_MASK = 0x00080000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_20_MASK = 0x00100000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_21_MASK = 0x00200000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_22_MASK = 0x00400000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_23_MASK = 0x00800000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_24_MASK = 0x01000000 # macro +RLC_XT_INT_VEC_CLEAR__NUM_25_MASK = 0x02000000 # macro +RLC_XT_INT_VEC_MUX_SEL__MUX_SEL__SHIFT = 0x0 # macro +RLC_XT_INT_VEC_MUX_SEL__MUX_SEL_MASK = 0x0000001F # macro +RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL__SHIFT = 0x0 # macro +RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL_MASK = 0x0000003F # macro +RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK = 0xFFFFFFFF # macro +RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT = 0x0 # macro +RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK = 0x00000001 # macro +RLC_SPP_CAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SPP_CAM_ADDR__ADDR_MASK = 0x000000FF # macro +RLC_SPP_CAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_SPP_CAM_DATA__TAG__SHIFT = 0x8 # macro +RLC_SPP_CAM_DATA__DATA_MASK = 0x000000FF # macro +RLC_SPP_CAM_DATA__TAG_MASK = 0xFFFFFF00 # macro +RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SPP_CAM_EXT_ADDR__ADDR_MASK = 0x000000FF # macro +RLC_SPP_CAM_EXT_DATA__VALID__SHIFT = 0x0 # macro +RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT = 0x1 # macro +RLC_SPP_CAM_EXT_DATA__VALID_MASK = 0x00000001 # macro +RLC_SPP_CAM_EXT_DATA__LOCK_MASK = 0x00000002 # macro +RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT = 0x2 # macro +RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT = 0x10 # macro +RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT = 0x12 # macro +RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK = 0x00000003 # macro +RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK = 0x00000FFC # macro +RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK = 0x00030000 # macro +RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK = 0x0FFC0000 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT = 0x2 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT = 0x4 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT = 0x6 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT = 0x10 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT = 0x15 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK = 0x00000003 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK = 0x0000000C # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK = 0x00000030 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK = 0x000000C0 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK = 0x001F0000 # macro +RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK = 0x00200000 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT = 0x1 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT = 0x2 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT = 0x3 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK = 0x00000001 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK = 0x00000002 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK = 0x00000004 # macro +RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK = 0x00000008 # macro +RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT = 0x0 # macro +RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT = 0x0 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT = 0x1 # macro +RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE__SHIFT = 0x2 # macro +RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE__SHIFT = 0x3 # macro +RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE__SHIFT = 0x4 # macro +RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE__SHIFT = 0x5 # macro +RLC_MEM_SLP_CNTL__RESERVED__SHIFT = 0x6 # macro +RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT = 0x7 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT = 0x8 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT = 0x10 # macro +RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE__SHIFT = 0x18 # macro +RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE__SHIFT = 0x19 # macro +RLC_MEM_SLP_CNTL__RESERVED1__SHIFT = 0x1a # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK = 0x00000001 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK = 0x00000002 # macro +RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE_MASK = 0x00000004 # macro +RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE_MASK = 0x00000008 # macro +RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE_MASK = 0x00000010 # macro +RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE_MASK = 0x00000020 # macro +RLC_MEM_SLP_CNTL__RESERVED_MASK = 0x00000040 # macro +RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK = 0x00000080 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK = 0x0000FF00 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK = 0x00FF0000 # macro +RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE_MASK = 0x01000000 # macro +RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE_MASK = 0x02000000 # macro +RLC_MEM_SLP_CNTL__RESERVED1_MASK = 0xFC000000 # macro +SMU_RLC_RESPONSE__RESP__SHIFT = 0x0 # macro +SMU_RLC_RESPONSE__RESP_MASK = 0xFFFFFFFF # macro +RLC_RLCV_SAFE_MODE__CMD__SHIFT = 0x0 # macro +RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT = 0x1 # macro +RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT = 0x5 # macro +RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT = 0x8 # macro +RLC_RLCV_SAFE_MODE__RESERVED__SHIFT = 0xc # macro +RLC_RLCV_SAFE_MODE__CMD_MASK = 0x00000001 # macro +RLC_RLCV_SAFE_MODE__MESSAGE_MASK = 0x0000001E # macro +RLC_RLCV_SAFE_MODE__RESERVED1_MASK = 0x000000E0 # macro +RLC_RLCV_SAFE_MODE__RESPONSE_MASK = 0x00000F00 # macro +RLC_RLCV_SAFE_MODE__RESERVED_MASK = 0xFFFFF000 # macro +RLC_SMU_SAFE_MODE__CMD__SHIFT = 0x0 # macro +RLC_SMU_SAFE_MODE__MESSAGE__SHIFT = 0x1 # macro +RLC_SMU_SAFE_MODE__RESERVED1__SHIFT = 0x5 # macro +RLC_SMU_SAFE_MODE__RESPONSE__SHIFT = 0x8 # macro +RLC_SMU_SAFE_MODE__RESERVED__SHIFT = 0xc # macro +RLC_SMU_SAFE_MODE__CMD_MASK = 0x00000001 # macro +RLC_SMU_SAFE_MODE__MESSAGE_MASK = 0x0000001E # macro +RLC_SMU_SAFE_MODE__RESERVED1_MASK = 0x000000E0 # macro +RLC_SMU_SAFE_MODE__RESPONSE_MASK = 0x00000F00 # macro +RLC_SMU_SAFE_MODE__RESERVED_MASK = 0xFFFFF000 # macro +RLC_RLCV_COMMAND__CMD__SHIFT = 0x0 # macro +RLC_RLCV_COMMAND__RESERVED__SHIFT = 0x4 # macro +RLC_RLCV_COMMAND__CMD_MASK = 0x0000000F # macro +RLC_RLCV_COMMAND__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_SMU_MESSAGE__CMD__SHIFT = 0x0 # macro +RLC_SMU_MESSAGE__CMD_MASK = 0xFFFFFFFF # macro +RLC_SMU_MESSAGE_1__CMD__SHIFT = 0x0 # macro +RLC_SMU_MESSAGE_1__CMD_MASK = 0xFFFFFFFF # macro +RLC_SMU_MESSAGE_2__CMD__SHIFT = 0x0 # macro +RLC_SMU_MESSAGE_2__CMD_MASK = 0xFFFFFFFF # macro +RLC_SRM_GPM_COMMAND__OP__SHIFT = 0x0 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT = 0x1 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT = 0x2 # macro +RLC_SRM_GPM_COMMAND__SIZE__SHIFT = 0x5 # macro +RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT = 0x12 # macro +RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT = 0x1f # macro +RLC_SRM_GPM_COMMAND__OP_MASK = 0x00000001 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK = 0x00000002 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK = 0x0000001C # macro +RLC_SRM_GPM_COMMAND__SIZE_MASK = 0x0003FFE0 # macro +RLC_SRM_GPM_COMMAND__START_OFFSET_MASK = 0x7FFC0000 # macro +RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK = 0x80000000 # macro +RLC_SRM_GPM_ABORT__ABORT__SHIFT = 0x0 # macro +RLC_SRM_GPM_ABORT__RESERVED__SHIFT = 0x1 # macro +RLC_SRM_GPM_ABORT__ABORT_MASK = 0x00000001 # macro +RLC_SRM_GPM_ABORT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SMU_COMMAND__CMD__SHIFT = 0x0 # macro +RLC_SMU_COMMAND__CMD_MASK = 0xFFFFFFFF # macro +RLC_SMU_ARGUMENT_1__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_1__ARG_MASK = 0xFFFFFFFF # macro +RLC_SMU_ARGUMENT_2__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_2__ARG_MASK = 0xFFFFFFFF # macro +RLC_SMU_ARGUMENT_3__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_3__ARG_MASK = 0xFFFFFFFF # macro +RLC_SMU_ARGUMENT_4__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_4__ARG_MASK = 0xFFFFFFFF # macro +RLC_SMU_ARGUMENT_5__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_5__ARG_MASK = 0xFFFFFFFF # macro +RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI_MASK = 0xFFFFFFFF # macro +RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT = 0x0 # macro +RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +RLC_IMU_BOOTLOAD_SIZE__SIZE__SHIFT = 0x0 # macro +RLC_IMU_BOOTLOAD_SIZE__RESERVED__SHIFT = 0x1a # macro +RLC_IMU_BOOTLOAD_SIZE__SIZE_MASK = 0x03FFFFFF # macro +RLC_IMU_BOOTLOAD_SIZE__RESERVED_MASK = 0xFC000000 # macro +RLC_IMU_MISC__THROTTLE_GFX__SHIFT = 0x0 # macro +RLC_IMU_MISC__EARLY_MGCG__SHIFT = 0x1 # macro +RLC_IMU_MISC__RESERVED__SHIFT = 0x2 # macro +RLC_IMU_MISC__THROTTLE_GFX_MASK = 0x00000001 # macro +RLC_IMU_MISC__EARLY_MGCG_MASK = 0x00000002 # macro +RLC_IMU_MISC__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT = 0x0 # macro +RLC_IMU_RESET_VECTOR__VDDGFX_EXIT__SHIFT = 0x1 # macro +RLC_IMU_RESET_VECTOR__VECTOR__SHIFT = 0x2 # macro +RLC_IMU_RESET_VECTOR__RESERVED__SHIFT = 0x8 # macro +RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT_MASK = 0x00000001 # macro +RLC_IMU_RESET_VECTOR__VDDGFX_EXIT_MASK = 0x00000002 # macro +RLC_IMU_RESET_VECTOR__VECTOR_MASK = 0x000000FC # macro +RLC_IMU_RESET_VECTOR__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT = 0x0 # macro +RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT = 0x1 # macro +RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK = 0x00000001 # macro +RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK = 0x00000002 # macro +RLC_RLCS_CGCG_REQUEST__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT = 0x0 # macro +RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT = 0x2 # macro +RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT = 0x3 # macro +RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT = 0x5 # macro +RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT = 0x6 # macro +RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK = 0x00000003 # macro +RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK = 0x00000004 # macro +RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK = 0x00000018 # macro +RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK = 0x00000020 # macro +RLC_RLCS_CGCG_STATUS__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT = 0x0 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT = 0x1 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT = 0x2 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT = 0x6 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT = 0x7 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT = 0x10 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT = 0x11 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT = 0x12 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT = 0x13 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT = 0x14 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT = 0x15 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT = 0x16 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT = 0x17 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK = 0x00000001 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK = 0x00000002 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK = 0x00000004 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK = 0x00000040 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK = 0x00000080 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK = 0x00010000 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK = 0x00020000 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK = 0x00040000 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK = 0x00080000 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK = 0x00100000 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK = 0x00200000 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK = 0x00400000 # macro +RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK = 0x00800000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT = 0x0 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT = 0x1 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT = 0x2 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT = 0x6 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT = 0x7 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK__SHIFT = 0x8 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT = 0x10 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT = 0x11 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT = 0x12 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT = 0x13 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT = 0x14 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT = 0x15 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT = 0x16 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT = 0x17 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK = 0x00000001 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK = 0x00000002 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK = 0x00000004 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK = 0x00000040 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK = 0x00000080 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK_MASK = 0x00000100 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK = 0x00010000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK = 0x00020000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK = 0x00040000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK = 0x00080000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK = 0x00100000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK = 0x00200000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK = 0x00400000 # macro +RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK = 0x00800000 # macro +RLC_GPM_STAT__RLC_BUSY__SHIFT = 0x0 # macro +RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT = 0x1 # macro +RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT = 0x2 # macro +RLC_GPM_STAT__GFX_LS_STATUS__SHIFT = 0x3 # macro +RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT = 0x4 # macro +RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT = 0x5 # macro +RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT = 0x6 # macro +RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT = 0x7 # macro +RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT = 0x8 # macro +RLC_GPM_STAT__SAVING_REGISTERS__SHIFT = 0x9 # macro +RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT = 0xa # macro +RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT = 0xb # macro +RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT = 0xc # macro +RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT = 0xd # macro +RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT = 0xe # macro +RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT = 0xf # macro +RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT = 0x10 # macro +RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT = 0x11 # macro +RLC_GPM_STAT__CMP_power_status__SHIFT = 0x12 # macro +RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT = 0x13 # macro +RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT = 0x14 # macro +RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT = 0x15 # macro +RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT = 0x16 # macro +RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT = 0x17 # macro +RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT = 0x18 # macro +RLC_GPM_STAT__RLC_BUSY_MASK = 0x00000001 # macro +RLC_GPM_STAT__GFX_POWER_STATUS_MASK = 0x00000002 # macro +RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK = 0x00000004 # macro +RLC_GPM_STAT__GFX_LS_STATUS_MASK = 0x00000008 # macro +RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK = 0x00000010 # macro +RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK = 0x00000020 # macro +RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK = 0x00000040 # macro +RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK = 0x00000080 # macro +RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK = 0x00000100 # macro +RLC_GPM_STAT__SAVING_REGISTERS_MASK = 0x00000200 # macro +RLC_GPM_STAT__RESTORING_REGISTERS_MASK = 0x00000400 # macro +RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK = 0x00000800 # macro +RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK = 0x00001000 # macro +RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK = 0x00002000 # macro +RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK = 0x00004000 # macro +RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK = 0x00008000 # macro +RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK = 0x00010000 # macro +RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK = 0x00020000 # macro +RLC_GPM_STAT__CMP_power_status_MASK = 0x00040000 # macro +RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK = 0x00080000 # macro +RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK = 0x00100000 # macro +RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK = 0x00200000 # macro +RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK = 0x00400000 # macro +RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK = 0x00800000 # macro +RLC_GPM_STAT__PG_ERROR_STATUS_MASK = 0xFF000000 # macro +RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT = 0x0 # macro +RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT = 0x1 # macro +RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT = 0x2 # macro +RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT = 0x3 # macro +RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT = 0x4 # macro +RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT = 0x5 # macro +RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT = 0x6 # macro +RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT = 0x7 # macro +RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT = 0x8 # macro +RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT = 0x9 # macro +RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT = 0xa # macro +RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT = 0xb # macro +RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT = 0xc # macro +RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT = 0xd # macro +RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT = 0xe # macro +RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT = 0xf # macro +RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT = 0x10 # macro +RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT = 0x11 # macro +RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT = 0x12 # macro +RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT = 0x13 # macro +RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT = 0x14 # macro +RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT = 0x15 # macro +RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT = 0x16 # macro +RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT = 0x17 # macro +RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT = 0x18 # macro +RLC_RLCS_GPM_STAT__RLC_BUSY_MASK = 0x00000001 # macro +RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK = 0x00000002 # macro +RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK = 0x00000004 # macro +RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK = 0x00000008 # macro +RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK = 0x00000010 # macro +RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK = 0x00000020 # macro +RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK = 0x00000040 # macro +RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK = 0x00000080 # macro +RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK = 0x00000100 # macro +RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK = 0x00000200 # macro +RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK = 0x00000400 # macro +RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK = 0x00000800 # macro +RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK = 0x00001000 # macro +RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK = 0x00002000 # macro +RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK = 0x00004000 # macro +RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK = 0x00008000 # macro +RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK = 0x00010000 # macro +RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK = 0x00020000 # macro +RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK = 0x00040000 # macro +RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK = 0x00080000 # macro +RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK = 0x00100000 # macro +RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK = 0x00200000 # macro +RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK = 0x00400000 # macro +RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK = 0x00800000 # macro +RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK = 0xFF000000 # macro +RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT = 0x0 # macro +RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT = 0x10 # macro +RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK = 0x0000FFFF # macro +RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK = 0xFFFF0000 # macro +RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT = 0x0 # macro +RLC_RLCS_DIDT_FORCE_STALL__VALID__SHIFT = 0x3 # macro +RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT = 0x4 # macro +RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK = 0x00000007 # macro +RLC_RLCS_DIDT_FORCE_STALL__VALID_MASK = 0x00000008 # macro +RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IOV_CMD_STATUS__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT = 0x8 # macro +RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK = 0x000000FF # macro +RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT = 0x0 # macro +RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT = 0x1 # macro +RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT = 0x2 # macro +RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT = 0x3 # macro +RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT = 0x4 # macro +RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT = 0x5 # macro +RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK = 0x00000001 # macro +RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK = 0x00000002 # macro +RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK = 0x00000004 # macro +RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK = 0x00000008 # macro +RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK = 0x00000010 # macro +RLC_RLCS_GPM_STAT_2__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT = 0x0 # macro +RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT = 0x1 # macro +RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK = 0x00000001 # macro +RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT = 0x0 # macro +RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT = 0x1 # macro +RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT = 0x2 # macro +RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT = 0x3 # macro +RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT = 0x4 # macro +RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK = 0x00000001 # macro +RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK = 0x00000002 # macro +RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK = 0x00000004 # macro +RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK = 0x00000008 # macro +RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT = 0x0 # macro +RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT = 0x1 # macro +RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT = 0x2 # macro +RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT = 0x3 # macro +RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK = 0x00000001 # macro +RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK = 0x00000002 # macro +RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK = 0x00000004 # macro +RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK = 0x00000008 # macro +RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT = 0x0 # macro +RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT = 0x5 # macro +RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK = 0x0000001F # macro +RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT = 0x0 # macro +RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT = 0x5 # macro +RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK = 0x0000001F # macro +RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT = 0x0 # macro +RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT = 0x1 # macro +RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT = 0x2 # macro +RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT = 0x3 # macro +RLC_RLCS_WGP_STATUS__RESERVED__SHIFT = 0x4 # macro +RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK = 0x00000001 # macro +RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK = 0x00000002 # macro +RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK = 0x00000004 # macro +RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK = 0x00000008 # macro +RLC_RLCS_WGP_STATUS__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT = 0x0 # macro +RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT = 0x1 # macro +RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT = 0x2 # macro +RLC_RLCS_WGP_READ__RESERVED__SHIFT = 0x3 # macro +RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK = 0x00000001 # macro +RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK = 0x00000002 # macro +RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK = 0x00000004 # macro +RLC_RLCS_WGP_READ__RESERVED_MASK = 0xFFFFFFF8 # macro +RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT = 0x0 # macro +RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT = 0x1 # macro +RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK = 0x00000001 # macro +RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT = 0x0 # macro +RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT = 0x1 # macro +RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE__SHIFT = 0x2 # macro +RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE__SHIFT = 0x3 # macro +RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING__SHIFT = 0x4 # macro +RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT = 0x5 # macro +RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK = 0x00000001 # macro +RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK = 0x00000002 # macro +RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE_MASK = 0x00000004 # macro +RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE_MASK = 0x00000008 # macro +RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING_MASK = 0x00000010 # macro +RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT = 0x0 # macro +RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK = 0xFFFFFFFF # macro +RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT = 0x0 # macro +RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT = 0x10 # macro +RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT = 0x19 # macro +RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK = 0x0000FFFF # macro +RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK = 0x01FF0000 # macro +RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK = 0xFE000000 # macro +RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT = 0x0 # macro +RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT = 0x1 # macro +RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK = 0x00000001 # macro +RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT = 0x0 # macro +RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK = 0xFFFFFFFF # macro +RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT = 0x0 # macro +RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT = 0x10 # macro +RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT = 0x19 # macro +RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK = 0x0000FFFF # macro +RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK = 0x01FF0000 # macro +RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK = 0xFE000000 # macro +RLC_RLCS_DSM_TRIG__START__SHIFT = 0x0 # macro +RLC_RLCS_DSM_TRIG__RESERVED__SHIFT = 0x1 # macro +RLC_RLCS_DSM_TRIG__START_MASK = 0x00000001 # macro +RLC_RLCS_DSM_TRIG__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE__SHIFT = 0x0 # macro +RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED__SHIFT = 0x3 # macro +RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE__SHIFT = 0x4 # macro +RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT = 0x5 # macro +RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT = 0x1f # macro +RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE_MASK = 0x00000001 # macro +RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED_MASK = 0x00000008 # macro +RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE_MASK = 0x00000010 # macro +RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK = 0x7FFFFFE0 # macro +RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK = 0x80000000 # macro +RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT = 0x0 # macro +RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT = 0x1 # macro +RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT = 0x2 # macro +RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT = 0xa # macro +RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK = 0x00000001 # macro +RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK = 0x00000002 # macro +RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK = 0x000003FC # macro +RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK = 0x0003FC00 # macro +RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT = 0x0 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT = 0x1 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT = 0x2 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT = 0xa # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK = 0x00000001 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK = 0x00000002 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK = 0x000003FC # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK = 0x0003FC00 # macro +RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT = 0x0 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT = 0x10 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT = 0x11 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT = 0x12 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT = 0x13 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT = 0x14 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT = 0x15 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT = 0x16 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT = 0x17 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT = 0x18 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT = 0x19 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT = 0x1a # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT = 0x1b # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT = 0x1c # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT = 0x1d # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT = 0x1e # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT = 0x1f # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK = 0x00000003 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK = 0x00010000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK = 0x00020000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK = 0x00040000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK = 0x00080000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK = 0x00100000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK = 0x00200000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK = 0x00400000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK = 0x00800000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK = 0x01000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK = 0x02000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK = 0x04000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK = 0x08000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK = 0x10000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK = 0x20000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK = 0x40000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK = 0x80000000 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT = 0x0 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT = 0x1 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT = 0x2 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT = 0x3 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT = 0x4 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT = 0x5 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT = 0x6 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT = 0x7 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK = 0x00000001 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK = 0x00000002 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK = 0x00000004 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK = 0x00000008 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK = 0x00000010 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK = 0x00000020 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK = 0x00000040 # macro +RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK = 0x00000080 # macro +RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT = 0x0 # macro +RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT = 0x1 # macro +RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT = 0x2 # macro +RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT = 0x3 # macro +RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT = 0xb # macro +RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT = 0x13 # macro +RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK = 0x00000001 # macro +RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK = 0x00000002 # macro +RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK = 0x00000004 # macro +RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK = 0x000007F8 # macro +RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK = 0x0007F800 # macro +RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK = 0xFFF80000 # macro +RLC_RLCS_GENERAL_0__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_1__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_2__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_3__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_3__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_4__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_4__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_5__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_5__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_6__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_6__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_7__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_7__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_8__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_8__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_9__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_9__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_10__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_10__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_11__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_11__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_12__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_12__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_13__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_13__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_14__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_14__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_15__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_15__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GENERAL_16__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GENERAL_16__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT = 0x0 # macro +RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK = 0x0003FFFF # macro +RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT = 0x0 # macro +RLC_RLCS_SPM_SQTT_MODE__MODE_MASK = 0x00000001 # macro +RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT = 0x0 # macro +RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK = 0x00000001 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT = 0x0 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT = 0x1 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT = 0x2 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT = 0x3 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT = 0x4 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT = 0x5 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT = 0x6 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT = 0x7 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT = 0x8 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT = 0x9 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT = 0xa # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT = 0xb # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT = 0xc # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT = 0xd # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT = 0xe # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT = 0xf # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT = 0x10 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT = 0x11 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT = 0x12 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT = 0x13 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT = 0x14 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT = 0x15 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT = 0x16 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT = 0x17 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT = 0x18 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT = 0x19 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT = 0x1a # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT = 0x1b # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT = 0x1c # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT = 0x1d # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT = 0x1e # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT = 0x1f # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK = 0x00000001 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK = 0x00000002 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK = 0x00000004 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK = 0x00000008 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK = 0x00000010 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK = 0x00000020 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK = 0x00000040 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK = 0x00000080 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK = 0x00000100 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK = 0x00000200 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK = 0x00000400 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK = 0x00000800 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK = 0x00001000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK = 0x00002000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK = 0x00004000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK = 0x00008000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK = 0x00010000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK = 0x00020000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK = 0x00040000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK = 0x00080000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK = 0x00100000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK = 0x00200000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK = 0x00400000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK = 0x00800000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK = 0x01000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK = 0x02000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK = 0x04000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK = 0x08000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK = 0x10000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK = 0x20000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK = 0x40000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK = 0x80000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT = 0x0 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT = 0x1 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT = 0x2 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT = 0x3 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT = 0x4 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT = 0x5 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT = 0x6 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT = 0x7 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT = 0x8 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT = 0x9 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT = 0xa # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT = 0xb # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT = 0xc # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT = 0xd # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT = 0xe # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT = 0xf # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT = 0x10 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT = 0x11 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT = 0x12 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT = 0x13 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT = 0x14 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT = 0x15 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT = 0x16 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT = 0x17 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT = 0x18 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT = 0x19 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT = 0x1a # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT = 0x1b # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT = 0x1c # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT = 0x1d # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT = 0x1e # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT = 0x1f # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK = 0x00000001 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK = 0x00000002 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK = 0x00000004 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK = 0x00000008 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK = 0x00000010 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK = 0x00000020 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK = 0x00000040 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK = 0x00000080 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK = 0x00000100 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK = 0x00000200 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK = 0x00000400 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK = 0x00000800 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK = 0x00001000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK = 0x00002000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK = 0x00004000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK = 0x00008000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK = 0x00010000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK = 0x00020000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK = 0x00040000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK = 0x00080000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK = 0x00100000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK = 0x00200000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK = 0x00400000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK = 0x00800000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK = 0x01000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK = 0x02000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK = 0x04000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK = 0x08000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK = 0x10000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK = 0x20000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK = 0x40000000 # macro +RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK = 0x80000000 # macro +RLC_RLCS_IMU_VIDCHG_CNTL__REQ__SHIFT = 0x0 # macro +RLC_RLCS_IMU_VIDCHG_CNTL__DATA__SHIFT = 0x1 # macro +RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN__SHIFT = 0xa # macro +RLC_RLCS_IMU_VIDCHG_CNTL__ACK__SHIFT = 0xb # macro +RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED__SHIFT = 0xc # macro +RLC_RLCS_IMU_VIDCHG_CNTL__REQ_MASK = 0x00000001 # macro +RLC_RLCS_IMU_VIDCHG_CNTL__DATA_MASK = 0x000003FE # macro +RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN_MASK = 0x00000400 # macro +RLC_RLCS_IMU_VIDCHG_CNTL__ACK_MASK = 0x00000800 # macro +RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED_MASK = 0xFFFFF000 # macro +RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT = 0x0 # macro +RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK = 0x00000001 # macro +RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT = 0x0 # macro +RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT = 0x0 # macro +RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED__SHIFT = 0x0 # macro +RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED__SHIFT = 0x1 # macro +RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED_MASK = 0x00000001 # macro +RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED_MASK = 0x00000002 # macro +RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED__SHIFT = 0x0 # macro +RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED__SHIFT = 0x1 # macro +RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED_MASK = 0x00000001 # macro +RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED_MASK = 0x00000002 # macro +RLC_RLCS_SRM_SRCID_CNTL__SRCID__SHIFT = 0x0 # macro +RLC_RLCS_SRM_SRCID_CNTL__SRCID_MASK = 0x00000007 # macro +RLC_RLCS_GCR_DATA_0__PHASE_0__SHIFT = 0x0 # macro +RLC_RLCS_GCR_DATA_0__PHASE_1__SHIFT = 0x10 # macro +RLC_RLCS_GCR_DATA_0__PHASE_0_MASK = 0x0000FFFF # macro +RLC_RLCS_GCR_DATA_0__PHASE_1_MASK = 0xFFFF0000 # macro +RLC_RLCS_GCR_DATA_1__PHASE_2__SHIFT = 0x0 # macro +RLC_RLCS_GCR_DATA_1__PHASE_3__SHIFT = 0x10 # macro +RLC_RLCS_GCR_DATA_1__PHASE_2_MASK = 0x0000FFFF # macro +RLC_RLCS_GCR_DATA_1__PHASE_3_MASK = 0xFFFF0000 # macro +RLC_RLCS_GCR_DATA_2__PHASE_4__SHIFT = 0x0 # macro +RLC_RLCS_GCR_DATA_2__PHASE_5__SHIFT = 0x10 # macro +RLC_RLCS_GCR_DATA_2__PHASE_4_MASK = 0x0000FFFF # macro +RLC_RLCS_GCR_DATA_2__PHASE_5_MASK = 0xFFFF0000 # macro +RLC_RLCS_GCR_DATA_3__PHASE_6__SHIFT = 0x0 # macro +RLC_RLCS_GCR_DATA_3__PHASE_7__SHIFT = 0x10 # macro +RLC_RLCS_GCR_DATA_3__PHASE_6_MASK = 0x0000FFFF # macro +RLC_RLCS_GCR_DATA_3__PHASE_7_MASK = 0xFFFF0000 # macro +RLC_RLCS_GCR_STATUS__GCR_BUSY__SHIFT = 0x0 # macro +RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT__SHIFT = 0x1 # macro +RLC_RLCS_GCR_STATUS__RESERVED_2__SHIFT = 0x5 # macro +RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG__SHIFT = 0x8 # macro +RLC_RLCS_GCR_STATUS__RESERVED__SHIFT = 0x10 # macro +RLC_RLCS_GCR_STATUS__GCR_BUSY_MASK = 0x00000001 # macro +RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT_MASK = 0x0000001E # macro +RLC_RLCS_GCR_STATUS__RESERVED_2_MASK = 0x000000E0 # macro +RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG_MASK = 0x0000FF00 # macro +RLC_RLCS_GCR_STATUS__RESERVED_MASK = 0xFFFF0000 # macro +RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT = 0x0 # macro +RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK = 0x00000001 # macro +RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x0 # macro +RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT = 0x1 # macro +RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT = 0x2 # macro +RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT = 0x3 # macro +RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT = 0x5 # macro +RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x6 # macro +RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT = 0x7 # macro +RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x00000001 # macro +RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK = 0x00000002 # macro +RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK = 0x00000004 # macro +RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK = 0x00000018 # macro +RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK = 0x00000020 # macro +RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x00000040 # macro +RLC_RLCS_UTCL2_CNTL__RESERVED_MASK = 0xFFFFFF80 # macro +RLC_RLCS_IMU_RLC_MSG_DATA0__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MSG_DATA0__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RLC_MSG_DATA1__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MSG_DATA1__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RLC_MSG_DATA2__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MSG_DATA2__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RLC_MSG_DATA3__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MSG_DATA3__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RLC_MSG_DATA4__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MSG_DATA4__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG__SHIFT = 0x1 # macro +RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG_MASK = 0x00000001 # macro +RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG_MASK = 0x00000002 # macro +RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_RLC_IMU_MSG_DATA0__DATA__SHIFT = 0x0 # macro +RLC_RLCS_RLC_IMU_MSG_DATA0__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA__SHIFT = 0x0 # macro +RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG__SHIFT = 0x0 # macro +RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG__SHIFT = 0x1 # macro +RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG_MASK = 0x00000001 # macro +RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG_MASK = 0x00000002 # macro +RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE__SHIFT = 0x10 # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT_MASK = 0x0000FFFF # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE_MASK = 0xFFFF0000 # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED__SHIFT = 0x10 # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1_MASK = 0x0000FFFF # macro +RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED_MASK = 0xFFFF0000 # macro +RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE__SHIFT = 0x1 # macro +RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ_MASK = 0x00000001 # macro +RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE_MASK = 0x00000002 # macro +RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS__SHIFT = 0x1 # macro +RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2__SHIFT = 0x2 # macro +RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS__SHIFT = 0xf # macro +RLC_RLCS_IMU_RLC_STATUS__RESERVED__SHIFT = 0x10 # macro +RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF_MASK = 0x00000001 # macro +RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS_MASK = 0x00000002 # macro +RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2_MASK = 0x00007FFC # macro +RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS_MASK = 0x00008000 # macro +RLC_RLCS_IMU_RLC_STATUS__RESERVED_MASK = 0xFFFF0000 # macro +RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE__SHIFT = 0x0 # macro +RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE__SHIFT = 0x1 # macro +RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2__SHIFT = 0x2 # macro +RLC_RLCS_RLC_IMU_STATUS__RESERVED__SHIFT = 0x4 # macro +RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE_MASK = 0x00000001 # macro +RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE_MASK = 0x00000002 # macro +RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2_MASK = 0x0000000C # macro +RLC_RLCS_RLC_IMU_STATUS__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_RLCS_IMU_RAM_DATA_1__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RAM_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED__SHIFT = 0x10 # macro +RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA_MASK = 0x0000FFFF # macro +RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED_MASK = 0xFFFF0000 # macro +RLC_RLCS_IMU_RAM_DATA_0__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RAM_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED__SHIFT = 0x10 # macro +RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA_MASK = 0x0000FFFF # macro +RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED_MASK = 0xFFFF0000 # macro +RLC_RLCS_IMU_RAM_CNTL__REQTOG__SHIFT = 0x0 # macro +RLC_RLCS_IMU_RAM_CNTL__ACKTOG__SHIFT = 0x1 # macro +RLC_RLCS_IMU_RAM_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_IMU_RAM_CNTL__REQTOG_MASK = 0x00000001 # macro +RLC_RLCS_IMU_RAM_CNTL__ACKTOG_MASK = 0x00000002 # macro +RLC_RLCS_IMU_RAM_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE__SHIFT = 0x0 # macro +RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK__SHIFT = 0x1 # macro +RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE_MASK = 0x00000001 # macro +RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK_MASK = 0x00000002 # macro +RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK__SHIFT = 0x0 # macro +RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID__SHIFT = 0x1 # macro +RLC_RLCS_SDMA_INT_CNTL_1__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK_MASK = 0x00000001 # macro +RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID_MASK = 0x00000002 # macro +RLC_RLCS_SDMA_INT_CNTL_1__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN__SHIFT = 0x0 # macro +RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE__SHIFT = 0x1 # macro +RLC_RLCS_SDMA_INT_CNTL_2__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN_MASK = 0x00000001 # macro +RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE_MASK = 0x00000002 # macro +RLC_RLCS_SDMA_INT_CNTL_2__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST__SHIFT = 0x0 # macro +RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST__SHIFT = 0x8 # macro +RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID__SHIFT = 0x10 # macro +RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING__SHIFT = 0x11 # macro +RLC_RLCS_SDMA_INT_STAT__RESERVED__SHIFT = 0x12 # macro +RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST_MASK = 0x000000FF # macro +RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST_MASK = 0x0000FF00 # macro +RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID_MASK = 0x00010000 # macro +RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING_MASK = 0x00020000 # macro +RLC_RLCS_SDMA_INT_STAT__RESERVED_MASK = 0xFFFC0000 # macro +RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW__SHIFT = 0x0 # macro +RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW__SHIFT = 0x8 # macro +RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID__SHIFT = 0x10 # macro +RLC_RLCS_SDMA_INT_INFO__RESERVED__SHIFT = 0x11 # macro +RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW_MASK = 0x000000FF # macro +RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW_MASK = 0x0000FF00 # macro +RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID_MASK = 0x00010000 # macro +RLC_RLCS_SDMA_INT_INFO__RESERVED_MASK = 0xFFFE0000 # macro +RLC_RLCS_PMM_CGCG_CNTL__VALID__SHIFT = 0x0 # macro +RLC_RLCS_PMM_CGCG_CNTL__CLEAN__SHIFT = 0x1 # macro +RLC_RLCS_PMM_CGCG_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_RLCS_PMM_CGCG_CNTL__VALID_MASK = 0x00000001 # macro +RLC_RLCS_PMM_CGCG_CNTL__CLEAN_MASK = 0x00000002 # macro +RLC_RLCS_PMM_CGCG_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA__SHIFT = 0x0 # macro +RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT = 0x0 # macro +RLC_RLCS_GFX_RM_CNTL__RESERVED__SHIFT = 0x1 # macro +RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK = 0x00000001 # macro +RLC_RLCS_GFX_RM_CNTL__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SAFE_MODE__CMD__SHIFT = 0x0 # macro +RLC_SAFE_MODE__MESSAGE__SHIFT = 0x1 # macro +RLC_SAFE_MODE__RESERVED1__SHIFT = 0x5 # macro +RLC_SAFE_MODE__RESPONSE__SHIFT = 0x8 # macro +RLC_SAFE_MODE__RESERVED__SHIFT = 0xc # macro +RLC_SAFE_MODE__CMD_MASK = 0x00000001 # macro +RLC_SAFE_MODE__MESSAGE_MASK = 0x0000001E # macro +RLC_SAFE_MODE__RESERVED1_MASK = 0x000000E0 # macro +RLC_SAFE_MODE__RESPONSE_MASK = 0x00000F00 # macro +RLC_SAFE_MODE__RESERVED_MASK = 0xFFFFF000 # macro +RLC_SPM_SAMPLE_CNT__COUNT__SHIFT = 0x0 # macro +RLC_SPM_SAMPLE_CNT__COUNT_MASK = 0xFFFFFFFF # macro +RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT = 0x0 # macro +RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT = 0x4 # macro +RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT = 0x6 # macro +RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT = 0x7 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT = 0x8 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT = 0x9 # macro +RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT = 0xc # macro +RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT = 0xd # macro +RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT = 0xe # macro +RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT = 0xf # macro +RLC_SPM_MC_CNTL__RESERVED_3__SHIFT = 0x10 # macro +RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC__SHIFT = 0x12 # macro +RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER__SHIFT = 0x13 # macro +RLC_SPM_MC_CNTL__RESERVED__SHIFT = 0x14 # macro +RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK = 0x0000000F # macro +RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK = 0x00000030 # macro +RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK = 0x00000040 # macro +RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK = 0x00000080 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK = 0x00000100 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK = 0x00000E00 # macro +RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK = 0x00001000 # macro +RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK = 0x00002000 # macro +RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK = 0x00004000 # macro +RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK = 0x00008000 # macro +RLC_SPM_MC_CNTL__RESERVED_3_MASK = 0x00030000 # macro +RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_MASK = 0x00040000 # macro +RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER_MASK = 0x00080000 # macro +RLC_SPM_MC_CNTL__RESERVED_MASK = 0xFFF00000 # macro +RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT = 0x0 # macro +RLC_SPM_INT_CNTL__RESERVED__SHIFT = 0x1 # macro +RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK = 0x00000001 # macro +RLC_SPM_INT_CNTL__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT = 0x0 # macro +RLC_SPM_INT_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK = 0x00000001 # macro +RLC_SPM_INT_STATUS__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT = 0x0 # macro +RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK = 0xFFFFFFFF # macro +RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT = 0x0 # macro +RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT = 0x10 # macro +RLC_SPM_INT_INFO_2__RESERVED__SHIFT = 0x18 # macro +RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK = 0x0000FFFF # macro +RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK = 0x00FF0000 # macro +RLC_SPM_INT_INFO_2__RESERVED_MASK = 0xFF000000 # macro +RLC_CSIB_ADDR_LO__ADDRESS__SHIFT = 0x0 # macro +RLC_CSIB_ADDR_LO__ADDRESS_MASK = 0xFFFFFFFF # macro +RLC_CSIB_ADDR_HI__ADDRESS__SHIFT = 0x0 # macro +RLC_CSIB_ADDR_HI__ADDRESS_MASK = 0x0000FFFF # macro +RLC_CSIB_LENGTH__LENGTH__SHIFT = 0x0 # macro +RLC_CSIB_LENGTH__LENGTH_MASK = 0xFFFFFFFF # macro +RLC_CP_SCHEDULERS__scheduler0__SHIFT = 0x0 # macro +RLC_CP_SCHEDULERS__scheduler1__SHIFT = 0x8 # macro +RLC_CP_SCHEDULERS__scheduler0_MASK = 0x000000FF # macro +RLC_CP_SCHEDULERS__scheduler1_MASK = 0x0000FF00 # macro +RLC_CP_EOF_INT__INTERRUPT__SHIFT = 0x0 # macro +RLC_CP_EOF_INT__RESERVED__SHIFT = 0x1 # macro +RLC_CP_EOF_INT__INTERRUPT_MASK = 0x00000001 # macro +RLC_CP_EOF_INT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_CP_EOF_INT_CNT__CNT__SHIFT = 0x0 # macro +RLC_CP_EOF_INT_CNT__CNT_MASK = 0xFFFFFFFF # macro +RLC_SPARE_INT_0__DATA__SHIFT = 0x0 # macro +RLC_SPARE_INT_0__PROCESSING__SHIFT = 0x1e # macro +RLC_SPARE_INT_0__COMPLETE__SHIFT = 0x1f # macro +RLC_SPARE_INT_0__DATA_MASK = 0x3FFFFFFF # macro +RLC_SPARE_INT_0__PROCESSING_MASK = 0x40000000 # macro +RLC_SPARE_INT_0__COMPLETE_MASK = 0x80000000 # macro +RLC_SPARE_INT_1__DATA__SHIFT = 0x0 # macro +RLC_SPARE_INT_1__PROCESSING__SHIFT = 0x1e # macro +RLC_SPARE_INT_1__COMPLETE__SHIFT = 0x1f # macro +RLC_SPARE_INT_1__DATA_MASK = 0x3FFFFFFF # macro +RLC_SPARE_INT_1__PROCESSING_MASK = 0x40000000 # macro +RLC_SPARE_INT_1__COMPLETE_MASK = 0x80000000 # macro +RLC_SPARE_INT_2__DATA__SHIFT = 0x0 # macro +RLC_SPARE_INT_2__PROCESSING__SHIFT = 0x1e # macro +RLC_SPARE_INT_2__COMPLETE__SHIFT = 0x1f # macro +RLC_SPARE_INT_2__DATA_MASK = 0x3FFFFFFF # macro +RLC_SPARE_INT_2__PROCESSING_MASK = 0x40000000 # macro +RLC_SPARE_INT_2__COMPLETE_MASK = 0x80000000 # macro +RLC_PACE_SPARE_INT__INTERRUPT__SHIFT = 0x0 # macro +RLC_PACE_SPARE_INT__RESERVED__SHIFT = 0x1 # macro +RLC_PACE_SPARE_INT__INTERRUPT_MASK = 0x00000001 # macro +RLC_PACE_SPARE_INT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT = 0x0 # macro +RLC_PACE_SPARE_INT_1__RESERVED__SHIFT = 0x1 # macro +RLC_PACE_SPARE_INT_1__INTERRUPT_MASK = 0x00000001 # macro +RLC_PACE_SPARE_INT_1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT = 0x0 # macro +RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT = 0x1 # macro +RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK = 0x00000001 # macro +RLC_RLCV_SPARE_INT_1__RESERVED_MASK = 0xFFFFFFFE # macro +CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT = 0x8 # macro +CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT = 0x10 # macro +CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK = 0x0000FF00 # macro +CGTS_TCC_DISABLE__TCC_DISABLE_MASK = 0xFFFF0000 # macro +CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT = 0xf # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE__SHIFT = 0x1b # macro +CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT = 0x1c # macro +CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK = 0x00008000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE_MASK = 0x08000000 # macro +CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK = 0x10000000 # macro +CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT = 0xc # macro +CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE__SHIFT = 0xd # macro +CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE__SHIFT = 0xe # macro +CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE__SHIFT = 0xf # macro +CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE__SHIFT = 0x10 # macro +CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE__SHIFT = 0x11 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE__SHIFT = 0x14 # macro +CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE__SHIFT = 0x15 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE__SHIFT = 0x18 # macro +CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE__SHIFT = 0x19 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE__SHIFT = 0x1b # macro +CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE__SHIFT = 0x1c # macro +CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK = 0x00001000 # macro +CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE_MASK = 0x00002000 # macro +CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE_MASK = 0x00004000 # macro +CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE_MASK = 0x00008000 # macro +CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE_MASK = 0x00010000 # macro +CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE_MASK = 0x00020000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE_MASK = 0x00100000 # macro +CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE_MASK = 0x00200000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE_MASK = 0x01000000 # macro +CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE_MASK = 0x02000000 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE_MASK = 0x08000000 # macro +CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE_MASK = 0x10000000 # macro +CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT = 0x10 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT = 0x11 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT = 0x12 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT = 0x13 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT = 0x14 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT = 0x15 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT = 0x16 # macro +CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT = 0x17 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT = 0x18 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT = 0x19 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT = 0x1a # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SC_CLK_CTRL0__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK = 0x00010000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK = 0x00020000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK = 0x00040000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK = 0x00080000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK = 0x00100000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK = 0x00200000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK = 0x00400000 # macro +CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK = 0x00800000 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK = 0x01000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK = 0x02000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK = 0x04000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK = 0x40000000 # macro +CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT = 0x10 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT = 0x11 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT = 0x12 # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT = 0x13 # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT = 0x14 # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT = 0x15 # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT = 0x16 # macro +CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT = 0x17 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT = 0x18 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT = 0x19 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT = 0x1a # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SC_CLK_CTRL1__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK = 0x00010000 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK = 0x00020000 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK = 0x00040000 # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK = 0x00080000 # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK = 0x00100000 # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK = 0x00200000 # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK = 0x00400000 # macro +CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK = 0x00800000 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK = 0x01000000 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK = 0x02000000 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK = 0x04000000 # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE__SHIFT = 0x10 # macro +CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE__SHIFT = 0x11 # macro +CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE__SHIFT = 0x12 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE__SHIFT = 0x13 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE__SHIFT = 0x14 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE__SHIFT = 0x15 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE__SHIFT = 0x16 # macro +CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE__SHIFT = 0x17 # macro +CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE__SHIFT = 0x18 # macro +CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE__SHIFT = 0x19 # macro +CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE__SHIFT = 0x1a # macro +CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL2__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE_MASK = 0x00010000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE_MASK = 0x00020000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE_MASK = 0x00040000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE_MASK = 0x00080000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE_MASK = 0x00100000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE_MASK = 0x00200000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE_MASK = 0x00400000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE_MASK = 0x00800000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE_MASK = 0x01000000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE_MASK = 0x02000000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE_MASK = 0x04000000 # macro +CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN__SHIFT = 0x17 # macro +CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG__SHIFT = 0x18 # macro +CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG__SHIFT = 0x19 # macro +CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG__SHIFT = 0x1a # macro +CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG__SHIFT = 0x1b # macro +CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SQG_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN_MASK = 0x00800000 # macro +CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG_MASK = 0x01000000 # macro +CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG_MASK = 0x02000000 # macro +CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG_MASK = 0x04000000 # macro +CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG_MASK = 0x08000000 # macro +CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT = 0x0 # macro +SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT = 0x10 # macro +SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK = 0x0000FFFF # macro +SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK = 0xFFFF0000 # macro +SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT = 0x0 # macro +SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT = 0x10 # macro +SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK = 0x0000FFFF # macro +SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK = 0xFFFF0000 # macro +SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT = 0x0 # macro +SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT = 0x10 # macro +SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK = 0x0000FFFF # macro +SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK = 0xFFFF0000 # macro +ICG_SP_CLK_CTRL__CLK_OVERRIDE__SHIFT = 0x0 # macro +ICG_SP_CLK_CTRL__CLK_OVERRIDE_MASK = 0xFFFFFFFF # macro +TA_CGTT_CTRL__ON_DELAY__SHIFT = 0x0 # macro +TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +TA_CGTT_CTRL__ON_DELAY_MASK = 0x0000000F # macro +TA_CGTT_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT = 0x0 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT = 0x1 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT = 0x2 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT = 0x3 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT = 0x4 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT = 0x5 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT = 0x6 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT = 0x7 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8__SHIFT = 0x8 # macro +DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT = 0x9 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK = 0x00000001 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK = 0x00000002 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK = 0x00000004 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK = 0x00000008 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK = 0x00000010 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK = 0x00000020 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK = 0x00000040 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK = 0x00000080 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8_MASK = 0x00000100 # macro +DB_CGTT_CLK_CTRL_0__RESERVED_MASK = 0xFFFFFE00 # macro +CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +CB_CGTT_SCLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT = 0x1d # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT = 0x1e # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT = 0x1f # macro +CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK = 0x20000000 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK = 0x40000000 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK = 0x80000000 # macro +CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT = 0x1a # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT = 0x1b # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT = 0x1c # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT = 0x1d # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT = 0x1e # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT = 0x1f # macro +CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK = 0x04000000 # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK = 0x08000000 # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK = 0x10000000 # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK = 0x20000000 # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK = 0x40000000 # macro +CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK = 0x80000000 # macro +CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT = 0x1d # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT = 0x1e # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT = 0x1f # macro +CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK = 0x20000000 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK = 0x40000000 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK = 0x80000000 # macro +CGTT_RLC_CLK_CTRL__RESERVED__SHIFT = 0x0 # macro +CGTT_RLC_CLK_CTRL__RESERVED_MASK = 0xFFFFFFFF # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE__SHIFT = 0x1 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE__SHIFT = 0x2 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE__SHIFT = 0x5 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE__SHIFT = 0x6 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE__SHIFT = 0x7 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE__SHIFT = 0x8 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE__SHIFT = 0x9 # macro +CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE__SHIFT = 0xa # macro +CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE__SHIFT = 0xb # macro +CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE__SHIFT = 0xc # macro +CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE__SHIFT = 0xd # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE__SHIFT = 0x12 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE__SHIFT = 0x13 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE__SHIFT = 0x14 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE__SHIFT = 0x16 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE__SHIFT = 0x17 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE__SHIFT = 0x18 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE__SHIFT = 0x19 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE__SHIFT = 0x1a # macro +CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE_MASK = 0x00000001 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE_MASK = 0x00000002 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE_MASK = 0x00000004 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE_MASK = 0x00000010 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE_MASK = 0x00000020 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE_MASK = 0x00000040 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE_MASK = 0x00000080 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE_MASK = 0x00000100 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE_MASK = 0x00000200 # macro +CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE_MASK = 0x00000400 # macro +CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE_MASK = 0x00000800 # macro +CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE_MASK = 0x00001000 # macro +CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE_MASK = 0x00002000 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE_MASK = 0x00040000 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE_MASK = 0x00080000 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE_MASK = 0x00100000 # macro +CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE_MASK = 0x00400000 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE_MASK = 0x00800000 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE_MASK = 0x01000000 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE_MASK = 0x02000000 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE_MASK = 0x04000000 # macro +CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE__SHIFT = 0x1 # macro +CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE__SHIFT = 0x2 # macro +CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE__SHIFT = 0x3 # macro +CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE__SHIFT = 0x5 # macro +CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE__SHIFT = 0x6 # macro +CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE__SHIFT = 0x7 # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE__SHIFT = 0x8 # macro +CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE__SHIFT = 0x9 # macro +CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE__SHIFT = 0xa # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE__SHIFT = 0xb # macro +CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE__SHIFT = 0xc # macro +CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE__SHIFT = 0x13 # macro +CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE__SHIFT = 0x14 # macro +CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE__SHIFT = 0x15 # macro +CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE__SHIFT = 0x16 # macro +CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE__SHIFT = 0x17 # macro +CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE__SHIFT = 0x18 # macro +CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE__SHIFT = 0x19 # macro +CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE__SHIFT = 0x1a # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE_MASK = 0x00000001 # macro +CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE_MASK = 0x00000002 # macro +CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE_MASK = 0x00000004 # macro +CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE_MASK = 0x00000008 # macro +CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE_MASK = 0x00000010 # macro +CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE_MASK = 0x00000020 # macro +CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE_MASK = 0x00000040 # macro +CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE_MASK = 0x00000080 # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE_MASK = 0x00000100 # macro +CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE_MASK = 0x00000200 # macro +CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE_MASK = 0x00000400 # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE_MASK = 0x00000800 # macro +CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE_MASK = 0x00001000 # macro +CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE_MASK = 0x00080000 # macro +CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE_MASK = 0x00100000 # macro +CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE_MASK = 0x00200000 # macro +CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE_MASK = 0x00400000 # macro +CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE_MASK = 0x00800000 # macro +CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE_MASK = 0x01000000 # macro +CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE_MASK = 0x02000000 # macro +CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE_MASK = 0x04000000 # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE_MASK = 0x80000000 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT = 0x0 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT = 0x1 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT = 0x2 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT = 0x3 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT = 0x4 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK = 0x00000001 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK = 0x00000002 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK = 0x00000004 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK = 0x00000008 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK = 0x00000010 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE__SHIFT = 0x0 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE__SHIFT = 0x1 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE__SHIFT = 0x2 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE__SHIFT = 0x3 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE__SHIFT = 0x4 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE__SHIFT = 0x5 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE__SHIFT = 0x6 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE_MASK = 0x00000001 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE_MASK = 0x00000002 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE_MASK = 0x00000004 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE_MASK = 0x00000008 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE_MASK = 0x00000010 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE_MASK = 0x00000020 # macro +GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE_MASK = 0x00000040 # macro +GL1H_ICG_CTRL__REG_DCLK_OVERRIDE__SHIFT = 0x0 # macro +GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE__SHIFT = 0x1 # macro +GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE__SHIFT = 0x2 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE__SHIFT = 0x3 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE__SHIFT = 0x4 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE__SHIFT = 0x5 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE__SHIFT = 0x6 # macro +GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE__SHIFT = 0x7 # macro +GL1H_ICG_CTRL__RET_DCLK_OVERRIDE__SHIFT = 0x8 # macro +GL1H_ICG_CTRL__REG_DCLK_OVERRIDE_MASK = 0x00000001 # macro +GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE_MASK = 0x00000002 # macro +GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE_MASK = 0x00000004 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE_MASK = 0x00000008 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE_MASK = 0x00000010 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE_MASK = 0x00000020 # macro +GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE_MASK = 0x00000040 # macro +GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE_MASK = 0x00000080 # macro +GL1H_ICG_CTRL__RET_DCLK_OVERRIDE_MASK = 0x00000100 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE__SHIFT = 0x0 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE__SHIFT = 0x1 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE__SHIFT = 0x2 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE__SHIFT = 0x3 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT = 0x4 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE__SHIFT = 0x5 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE__SHIFT = 0x6 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE_MASK = 0x00000001 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE_MASK = 0x00000002 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE_MASK = 0x00000004 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE_MASK = 0x00000008 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE_MASK = 0x00000010 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE_MASK = 0x00000020 # macro +CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE_MASK = 0x00000040 # macro +ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT = 0x0 # macro +ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT = 0x1 # macro +ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT = 0x2 # macro +ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT = 0x3 # macro +ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE__SHIFT = 0x4 # macro +ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT = 0x5 # macro +ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT = 0x6 # macro +ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT = 0x7 # macro +ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT = 0x8 # macro +ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT = 0x9 # macro +ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE__SHIFT = 0xa # macro +ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK = 0x00000001 # macro +ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK = 0x00000002 # macro +ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK = 0x00000004 # macro +ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE_MASK = 0x00000008 # macro +ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE_MASK = 0x00000010 # macro +ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE_MASK = 0x00000020 # macro +ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK = 0x00000040 # macro +ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK = 0x00000080 # macro +ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK = 0x00000100 # macro +ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE_MASK = 0x00000200 # macro +ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE_MASK = 0x00000400 # macro +ICG_GL1A_CTRL__REG_CLK_OVERRIDE__SHIFT = 0x0 # macro +ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT = 0x1 # macro +ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT = 0x2 # macro +ICG_GL1A_CTRL__RET_CLK_OVERRIDE__SHIFT = 0x3 # macro +ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT = 0x4 # macro +ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE__SHIFT = 0x5 # macro +ICG_GL1A_CTRL__REG_CLK_OVERRIDE_MASK = 0x00000001 # macro +ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE_MASK = 0x00000002 # macro +ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE_MASK = 0x00000004 # macro +ICG_GL1A_CTRL__RET_CLK_OVERRIDE_MASK = 0x00000008 # macro +ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK = 0x00000010 # macro +ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE_MASK = 0x00000020 # macro +ICG_CHA_CTRL__REG_CLK_OVERRIDE__SHIFT = 0x0 # macro +ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT = 0x1 # macro +ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT = 0x2 # macro +ICG_CHA_CTRL__RET_CLK_OVERRIDE__SHIFT = 0x3 # macro +ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT = 0x4 # macro +ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT = 0x5 # macro +ICG_CHA_CTRL__REG_CLK_OVERRIDE_MASK = 0x00000001 # macro +ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK = 0x00000002 # macro +ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK = 0x00000004 # macro +ICG_CHA_CTRL__RET_CLK_OVERRIDE_MASK = 0x00000008 # macro +ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK = 0x00000010 # macro +ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE_MASK = 0x00000020 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM__SHIFT = 0x0 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT = 0x1 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT = 0x2 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX__SHIFT = 0x3 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE__SHIFT = 0x4 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ__SHIFT = 0x5 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT = 0x6 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT = 0x7 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC__SHIFT = 0x8 # macro +GUS_ICG_CTRL__SPARE1__SHIFT = 0x9 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM_MASK = 0x00000001 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK = 0x00000002 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_READ_MASK = 0x00000004 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX_MASK = 0x00000008 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE_MASK = 0x00000010 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ_MASK = 0x00000020 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK = 0x00000040 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK = 0x00000080 # macro +GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC_MASK = 0x00000100 # macro +GUS_ICG_CTRL__SPARE1_MASK = 0x0003FE00 # macro +CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT = 0x0 # macro +CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_PH_CLK_CTRL0__ON_DELAY_MASK = 0x0000000F # macro +CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK = 0x80000000 # macro +CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT = 0x0 # macro +CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +CGTT_PH_CLK_CTRL1__ON_DELAY_MASK = 0x0000000F # macro +CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT = 0x0 # macro +CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +CGTT_PH_CLK_CTRL2__ON_DELAY_MASK = 0x0000000F # macro +CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT = 0x0 # macro +CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +CGTT_PH_CLK_CTRL3__ON_DELAY_MASK = 0x0000000F # macro +CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +GFX_ICG_GL2C_CTRL__REG_OVERRIDE__SHIFT = 0x0 # macro +GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE__SHIFT = 0x1 # macro +GFX_ICG_GL2C_CTRL__IB_OVERRIDE__SHIFT = 0x2 # macro +GFX_ICG_GL2C_CTRL__TAG_OVERRIDE__SHIFT = 0x3 # macro +GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE__SHIFT = 0x4 # macro +GFX_ICG_GL2C_CTRL__CORE_OVERRIDE__SHIFT = 0x5 # macro +GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE__SHIFT = 0x6 # macro +GFX_ICG_GL2C_CTRL__GCR_OVERRIDE__SHIFT = 0x7 # macro +GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE__SHIFT = 0x8 # macro +GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE__SHIFT = 0x9 # macro +GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE__SHIFT = 0xa # macro +GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE__SHIFT = 0xb # macro +GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE__SHIFT = 0xc # macro +GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE__SHIFT = 0xd # macro +GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE__SHIFT = 0xe # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE__SHIFT = 0xf # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE__SHIFT = 0x10 # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE__SHIFT = 0x11 # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE__SHIFT = 0x12 # macro +GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE__SHIFT = 0x14 # macro +GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE__SHIFT = 0x15 # macro +GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE__SHIFT = 0x16 # macro +GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE__SHIFT = 0x17 # macro +GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE__SHIFT = 0x18 # macro +GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE__SHIFT = 0x19 # macro +GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE__SHIFT = 0x1a # macro +GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE__SHIFT = 0x1b # macro +GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE__SHIFT = 0x1c # macro +GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE__SHIFT = 0x1d # macro +GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE__SHIFT = 0x1e # macro +GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE__SHIFT = 0x1f # macro +GFX_ICG_GL2C_CTRL__REG_OVERRIDE_MASK = 0x00000001 # macro +GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE_MASK = 0x00000002 # macro +GFX_ICG_GL2C_CTRL__IB_OVERRIDE_MASK = 0x00000004 # macro +GFX_ICG_GL2C_CTRL__TAG_OVERRIDE_MASK = 0x00000008 # macro +GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE_MASK = 0x00000010 # macro +GFX_ICG_GL2C_CTRL__CORE_OVERRIDE_MASK = 0x00000020 # macro +GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE_MASK = 0x00000040 # macro +GFX_ICG_GL2C_CTRL__GCR_OVERRIDE_MASK = 0x00000080 # macro +GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE_MASK = 0x00000100 # macro +GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE_MASK = 0x00000200 # macro +GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE_MASK = 0x00000400 # macro +GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE_MASK = 0x00000800 # macro +GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE_MASK = 0x00001000 # macro +GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE_MASK = 0x00002000 # macro +GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE_MASK = 0x00004000 # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE_MASK = 0x00008000 # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE_MASK = 0x00010000 # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE_MASK = 0x00020000 # macro +GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE_MASK = 0x00040000 # macro +GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE_MASK = 0x00100000 # macro +GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE_MASK = 0x00200000 # macro +GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE_MASK = 0x00400000 # macro +GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE_MASK = 0x00800000 # macro +GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE_MASK = 0x01000000 # macro +GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE_MASK = 0x02000000 # macro +GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE_MASK = 0x04000000 # macro +GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE_MASK = 0x08000000 # macro +GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE_MASK = 0x10000000 # macro +GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE_MASK = 0x20000000 # macro +GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE_MASK = 0x40000000 # macro +GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE_MASK = 0x80000000 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE__SHIFT = 0x0 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE__SHIFT = 0x1 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE__SHIFT = 0x2 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE__SHIFT = 0x3 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE__SHIFT = 0x4 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE__SHIFT = 0x5 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE__SHIFT = 0x6 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE__SHIFT = 0x7 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE__SHIFT = 0x8 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE__SHIFT = 0x9 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE__SHIFT = 0xa # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE__SHIFT = 0xb # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE__SHIFT = 0xc # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE__SHIFT = 0xd # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE__SHIFT = 0xe # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE__SHIFT = 0xf # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE__SHIFT = 0x10 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE__SHIFT = 0x11 # macro +GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE__SHIFT = 0x18 # macro +GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE__SHIFT = 0x19 # macro +GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE__SHIFT = 0x1a # macro +GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE__SHIFT = 0x1b # macro +GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE__SHIFT = 0x1c # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE_MASK = 0x00000001 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE_MASK = 0x00000002 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE_MASK = 0x00000004 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE_MASK = 0x00000008 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE_MASK = 0x00000010 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE_MASK = 0x00000020 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE_MASK = 0x00000040 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE_MASK = 0x00000080 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE_MASK = 0x00000100 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE_MASK = 0x00000200 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE_MASK = 0x00000400 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE_MASK = 0x00000800 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE_MASK = 0x00001000 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE_MASK = 0x00002000 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE_MASK = 0x00004000 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE_MASK = 0x00008000 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE_MASK = 0x00010000 # macro +GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE_MASK = 0x00020000 # macro +GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE_MASK = 0x01000000 # macro +GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE_MASK = 0x02000000 # macro +GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE_MASK = 0x04000000 # macro +GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE_MASK = 0x08000000 # macro +GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE_MASK = 0x10000000 # macro +ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE__SHIFT = 0x0 # macro +ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE__SHIFT = 0x1 # macro +ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE__SHIFT = 0x2 # macro +ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE__SHIFT = 0x3 # macro +ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE__SHIFT = 0x4 # macro +ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE__SHIFT = 0x5 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE__SHIFT = 0x6 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE__SHIFT = 0x7 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE__SHIFT = 0x8 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE__SHIFT = 0x9 # macro +ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE__SHIFT = 0xa # macro +ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE__SHIFT = 0xb # macro +ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE__SHIFT = 0xc # macro +ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE__SHIFT = 0xd # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE__SHIFT = 0xe # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE__SHIFT = 0xf # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE__SHIFT = 0x10 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE__SHIFT = 0x11 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE__SHIFT = 0x12 # macro +ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE__SHIFT = 0x13 # macro +ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE__SHIFT = 0x14 # macro +ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE__SHIFT = 0x15 # macro +ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE__SHIFT = 0x16 # macro +ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE__SHIFT = 0x17 # macro +ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE__SHIFT = 0x18 # macro +ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE__SHIFT = 0x19 # macro +ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED__SHIFT = 0x1a # macro +ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE_MASK = 0x00000001 # macro +ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE_MASK = 0x00000002 # macro +ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE_MASK = 0x00000004 # macro +ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE_MASK = 0x00000008 # macro +ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE_MASK = 0x00000010 # macro +ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE_MASK = 0x00000020 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE_MASK = 0x00000040 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE_MASK = 0x00000080 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE_MASK = 0x00000100 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE_MASK = 0x00000200 # macro +ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE_MASK = 0x00000400 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE_MASK = 0x00000800 # macro +ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE_MASK = 0x00001000 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE_MASK = 0x00002000 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE_MASK = 0x00004000 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE_MASK = 0x00008000 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE_MASK = 0x00010000 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE_MASK = 0x00020000 # macro +ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE_MASK = 0x00040000 # macro +ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE_MASK = 0x00080000 # macro +ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE_MASK = 0x00100000 # macro +ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE_MASK = 0x00200000 # macro +ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE_MASK = 0x00400000 # macro +ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE_MASK = 0x00800000 # macro +ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE_MASK = 0x01000000 # macro +ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE_MASK = 0x02000000 # macro +ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED_MASK = 0xFC000000 # macro +ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT = 0x0 # macro +ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT = 0x1 # macro +ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT = 0x2 # macro +ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT = 0x3 # macro +ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT = 0x4 # macro +ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT = 0x5 # macro +ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT = 0x6 # macro +ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK = 0x00000001 # macro +ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK = 0x00000002 # macro +ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK = 0x00000004 # macro +ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK = 0x00000008 # macro +ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK = 0x00000010 # macro +ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK = 0x00000020 # macro +ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK = 0x00000040 # macro +ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT = 0x0 # macro +ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT = 0x1 # macro +ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT = 0x2 # macro +ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT = 0x3 # macro +ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT = 0x4 # macro +ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT = 0x5 # macro +ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT = 0x6 # macro +ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK = 0x00000001 # macro +ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK = 0x00000002 # macro +ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK = 0x00000004 # macro +ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK = 0x00000008 # macro +ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK = 0x00000010 # macro +ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK = 0x00000020 # macro +ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE_MASK = 0x00000040 # macro +GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT = 0x0 # macro +GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK = 0x00000001 # macro +GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT = 0x0 # macro +GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT = 0x1f # macro +GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK = 0x00000007 # macro +GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK = 0x80000000 # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT = 0x0 # macro +GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT = 0x8 # macro +GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT = 0x10 # macro +GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT = 0x1d # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT = 0x1e # macro +GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT = 0x1f # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK = 0x000000FF # macro +GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK = 0x0000FF00 # macro +GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK = 0x00FF0000 # macro +GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK = 0x20000000 # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK = 0x40000000 # macro +GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK = 0x80000000 # macro +GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT = 0x0 # macro +GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT = 0x1f # macro +GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK = 0x00000007 # macro +GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK = 0x80000000 # macro +GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT = 0x0 # macro +GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT = 0x2 # macro +GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT = 0x4 # macro +GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT = 0x8 # macro +GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK = 0x00000003 # macro +GRBM_GFX_CNTL_SR_DATA__MEID_MASK = 0x0000000C # macro +GRBM_GFX_CNTL_SR_DATA__VMID_MASK = 0x000000F0 # macro +GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK = 0x00000700 # macro +GC_IH_COOKIE_0_PTR__ADDR__SHIFT = 0x0 # macro +GC_IH_COOKIE_0_PTR__ADDR_MASK = 0x000FFFFF # macro +GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT = 0x0 # macro +GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT = 0x1 # macro +GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT = 0x4 # macro +GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT = 0x5 # macro +GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT = 0x8 # macro +GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT = 0x9 # macro +GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT = 0xc # macro +GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT = 0xd # macro +GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT = 0x10 # macro +GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT = 0x11 # macro +GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT = 0x14 # macro +GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT = 0x15 # macro +GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT = 0x18 # macro +GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT = 0x19 # macro +GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT = 0x1c # macro +GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT = 0x1d # macro +GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK = 0x00000001 # macro +GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK = 0x0000000E # macro +GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK = 0x00000010 # macro +GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK = 0x000000E0 # macro +GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK = 0x00000100 # macro +GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK = 0x00000E00 # macro +GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK = 0x00001000 # macro +GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK = 0x0000E000 # macro +GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK = 0x00010000 # macro +GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK = 0x000E0000 # macro +GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK = 0x00100000 # macro +GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK = 0x00E00000 # macro +GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK = 0x01000000 # macro +GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK = 0x0E000000 # macro +GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK = 0x10000000 # macro +GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK = 0xE0000000 # macro +RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT = 0x10 # macro +RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK = 0x00000001 # macro +RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK = 0x0000FFFE # macro +RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK = 0xFFFF0000 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT = 0x7 # macro +RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT = 0xa # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK = 0x0000007F # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK = 0x00000080 # macro +RLC_GPU_IOV_CFG_REG6__RESERVED_MASK = 0x00000300 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK = 0xFFFFFC00 # macro +RLC_SDMA0_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_SDMA0_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_SDMA1_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_SDMA1_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_SDMA2_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_SDMA2_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_SDMA3_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_SDMA3_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT = 0x0 # macro +RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT = 0x0 # macro +RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT = 0x0 # macro +RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT = 0x0 # macro +RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_RLCV_TIMER_INT_0__TIMER__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_INT_0__TIMER_MASK = 0xFFFFFFFF # macro +RLC_RLCV_TIMER_INT_1__TIMER__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_INT_1__TIMER_MASK = 0xFFFFFFFF # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT = 0x1 # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT = 0x2 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT = 0x3 # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT = 0x4 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT = 0x5 # macro +RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT = 0x6 # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK = 0x00000001 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK = 0x00000002 # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK = 0x00000004 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK = 0x00000008 # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK = 0x00000010 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK = 0x00000020 # macro +RLC_RLCV_TIMER_CTRL__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT = 0x1 # macro +RLC_RLCV_TIMER_STAT__RESERVED__SHIFT = 0x2 # macro +RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT = 0x8 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT = 0x9 # macro +RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT = 0xa # macro +RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT = 0xb # macro +RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK = 0x00000001 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK = 0x00000002 # macro +RLC_RLCV_TIMER_STAT__RESERVED_MASK = 0x000000FC # macro +RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK = 0x00000100 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK = 0x00000200 # macro +RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK = 0x00000400 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK = 0x00000800 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT = 0x1f # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK = 0x7FFFFFFF # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK = 0x80000000 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT = 0x1f # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK = 0x7FFFFFFF # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK = 0x80000000 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT = 0x1f # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK = 0x7FFFFFFF # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK = 0x80000000 # macro +RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_MASK__VF_MASK_MASK = 0x7FFFFFFF # macro +RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_0__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_1__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT = 0x0 # macro +RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY__SHIFT = 0x8 # macro +RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK = 0x0000003F # macro +RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY_MASK = 0x00003F00 # macro +RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE__SHIFT = 0x0 # macro +RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE__SHIFT = 0x1 # macro +RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE__SHIFT = 0x2 # macro +RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE__SHIFT = 0x3 # macro +RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE__SHIFT = 0x4 # macro +RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE__SHIFT = 0x5 # macro +RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE__SHIFT = 0x6 # macro +RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE__SHIFT = 0x7 # macro +RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT = 0x8 # macro +RLC_CLK_CNTL__RESERVED_9__SHIFT = 0x9 # macro +RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE__SHIFT = 0xa # macro +RLC_CLK_CNTL__RESERVED_11__SHIFT = 0xb # macro +RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT = 0xc # macro +RLC_CLK_CNTL__RESERVED_15__SHIFT = 0xf # macro +RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT = 0x12 # macro +RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE__SHIFT = 0x13 # macro +RLC_CLK_CNTL__RESERVED__SHIFT = 0x14 # macro +RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE_MASK = 0x00000001 # macro +RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE_MASK = 0x00000002 # macro +RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE_MASK = 0x00000004 # macro +RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE_MASK = 0x00000008 # macro +RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE_MASK = 0x00000010 # macro +RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE_MASK = 0x00000020 # macro +RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE_MASK = 0x00000040 # macro +RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE_MASK = 0x00000080 # macro +RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK = 0x00000100 # macro +RLC_CLK_CNTL__RESERVED_9_MASK = 0x00000200 # macro +RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE_MASK = 0x00000400 # macro +RLC_CLK_CNTL__RESERVED_11_MASK = 0x00000800 # macro +RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK = 0x00001000 # macro +RLC_CLK_CNTL__RESERVED_15_MASK = 0x00008000 # macro +RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK = 0x00040000 # macro +RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE_MASK = 0x00080000 # macro +RLC_CLK_CNTL__RESERVED_MASK = 0xFFF00000 # macro +RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT = 0x0 # macro +RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT = 0x1 # macro +RLC_PACE_TIMER_STAT__RESERVED__SHIFT = 0x2 # macro +RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT = 0x8 # macro +RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT = 0x9 # macro +RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT = 0xa # macro +RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT = 0xb # macro +RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK = 0x00000001 # macro +RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK = 0x00000002 # macro +RLC_PACE_TIMER_STAT__RESERVED_MASK = 0x000000FC # macro +RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK = 0x00000100 # macro +RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK = 0x00000200 # macro +RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK = 0x00000400 # macro +RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK = 0x00000800 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT = 0x4 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT = 0x8 # macro +RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT = 0x10 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK = 0x0000000F # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK = 0x000000F0 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK = 0x0000FF00 # macro +RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK = 0xFFFF0000 # macro +RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT = 0x4 # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT = 0x5 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT = 0x8 # macro +RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT = 0x10 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT = 0x18 # macro +RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK = 0x0000000F # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK = 0x00000010 # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK = 0x00000020 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED_MASK = 0x000000C0 # macro +RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK = 0x0000FF00 # macro +RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK = 0x00FF0000 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK = 0xFF000000 # macro +RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT = 0x4 # macro +RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK = 0x0000000F # macro +RLC_GPU_IOV_CFG_REG2__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCH_1__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCH_2__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_PACE_INT_FORCE__FORCE_INT__SHIFT = 0x0 # macro +RLC_PACE_INT_FORCE__FORCE_INT_MASK = 0xFFFFFFFF # macro +RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR__SHIFT = 0x0 # macro +RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR__SHIFT = 0x1 # macro +RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR_MASK = 0x00000001 # macro +RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR_MASK = 0x00000002 # macro +RLC_GPU_IOV_INT_STAT__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_INT_STAT__STATUS_MASK = 0xFFFFFFFF # macro +RLC_IH_COOKIE__DATA__SHIFT = 0x0 # macro +RLC_IH_COOKIE__DATA_MASK = 0xFFFFFFFF # macro +RLC_IH_COOKIE_CNTL__CREDIT__SHIFT = 0x0 # macro +RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT = 0x2 # macro +RLC_IH_COOKIE_CNTL__CREDIT_MASK = 0x00000003 # macro +RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK = 0x00000004 # macro +RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT = 0x0 # macro +RLC_GPU_IOV_F32_CNTL__ENABLE_MASK = 0x00000001 # macro +RLC_GPU_IOV_F32_RESET__RESET__SHIFT = 0x0 # macro +RLC_GPU_IOV_F32_RESET__RESET_MASK = 0x00000001 # macro +RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT = 0xc # macro +RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK = 0x00000FFF # macro +RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK = 0xFFFFF000 # macro +RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT = 0x0 # macro +RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE__SHIFT = 0x0 # macro +RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE_MASK = 0x00000001 # macro +RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT = 0x0 # macro +RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_INT_DISABLE__DISABLE_INT__SHIFT = 0x0 # macro +RLC_GPU_IOV_INT_DISABLE__DISABLE_INT_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_INT_FORCE__FORCE_INT__SHIFT = 0x0 # macro +RLC_GPU_IOV_INT_FORCE__FORCE_INT_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK = 0x0000FFFF # macro +RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_2__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_3__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +RLC_GPM_UCODE_ADDR__RESERVED__SHIFT = 0xe # macro +RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK = 0x00003FFF # macro +RLC_GPM_UCODE_ADDR__RESERVED_MASK = 0xFFFFC000 # macro +RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +RLC_GPM_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_IRAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_GPM_IRAM_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +RLC_GPM_IRAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPM_IRAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCP_IRAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_RLCP_IRAM_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +RLC_RLCP_IRAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_RLCP_IRAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_RLCV_IRAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_RLCV_IRAM_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +RLC_RLCV_IRAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_RLCV_IRAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_LX6_DRAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_LX6_DRAM_ADDR__ADDR_MASK = 0x000007FF # macro +RLC_LX6_DRAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_LX6_DRAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_LX6_IRAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_LX6_IRAM_ADDR__ADDR_MASK = 0x00000FFF # macro +RLC_LX6_IRAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_LX6_IRAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +RLC_PACE_UCODE_ADDR__RESERVED__SHIFT = 0xc # macro +RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK = 0x00000FFF # macro +RLC_PACE_UCODE_ADDR__RESERVED_MASK = 0xFFFFF000 # macro +RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +RLC_PACE_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_GPM_SCRATCH_ADDR__ADDR_MASK = 0x0000FFFF # macro +RLC_GPM_SCRATCH_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPM_SCRATCH_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_DRAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SRM_DRAM_ADDR__RESERVED__SHIFT = 0xd # macro +RLC_SRM_DRAM_ADDR__ADDR_MASK = 0x00001FFF # macro +RLC_SRM_DRAM_ADDR__RESERVED_MASK = 0xFFFFE000 # macro +RLC_SRM_DRAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_SRM_DRAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_ARAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SRM_ARAM_ADDR__RESERVED__SHIFT = 0xd # macro +RLC_SRM_ARAM_ADDR__ADDR_MASK = 0x00001FFF # macro +RLC_SRM_ARAM_ADDR__RESERVED_MASK = 0xFFFFE000 # macro +RLC_SRM_ARAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_SRM_ARAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_PACE_SCRATCH_ADDR__ADDR_MASK = 0x0000FFFF # macro +RLC_PACE_SCRATCH_DATA__DATA__SHIFT = 0x0 # macro +RLC_PACE_SCRATCH_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_GTS_OFFSET_LSB__DATA__SHIFT = 0x0 # macro +RLC_GTS_OFFSET_LSB__DATA_MASK = 0xFFFFFFFF # macro +RLC_GTS_OFFSET_MSB__DATA__SHIFT = 0x0 # macro +RLC_GTS_OFFSET_MSB__DATA_MASK = 0xFFFFFFFF # macro +GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT = 0x0 # macro +GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT = 0x4 # macro +GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT = 0x8 # macro +GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT = 0xc # macro +GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT = 0x10 # macro +GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT = 0x14 # macro +GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT = 0x18 # macro +GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT = 0x1c # macro +GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK = 0x00000007 # macro +GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK = 0x00000070 # macro +GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK = 0x00000700 # macro +GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK = 0x00007000 # macro +GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK = 0x00070000 # macro +GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK = 0x00700000 # macro +GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK = 0x07000000 # macro +GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK = 0x70000000 # macro +GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT = 0x0 # macro +GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT = 0x4 # macro +GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT = 0x8 # macro +GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT = 0xc # macro +GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT = 0x10 # macro +GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT = 0x14 # macro +GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT = 0x18 # macro +GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT = 0x1c # macro +GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK = 0x00000007 # macro +GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK = 0x00000070 # macro +GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK = 0x00000700 # macro +GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK = 0x00007000 # macro +GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK = 0x00070000 # macro +GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK = 0x00700000 # macro +GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK = 0x07000000 # macro +GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK = 0x70000000 # macro +GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0__SHIFT = 0x0 # macro +GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0__SHIFT = 0x4 # macro +GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0__SHIFT = 0x8 # macro +GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0__SHIFT = 0xc # macro +GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1__SHIFT = 0x10 # macro +GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1__SHIFT = 0x14 # macro +GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1__SHIFT = 0x18 # macro +GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1__SHIFT = 0x1c # macro +GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0_MASK = 0x00000007 # macro +GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0_MASK = 0x00000070 # macro +GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0_MASK = 0x00000700 # macro +GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0_MASK = 0x00007000 # macro +GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1_MASK = 0x00070000 # macro +GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1_MASK = 0x00700000 # macro +GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1_MASK = 0x07000000 # macro +GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1_MASK = 0x70000000 # macro +GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2__SHIFT = 0x0 # macro +GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2__SHIFT = 0x4 # macro +GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2__SHIFT = 0x8 # macro +GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2__SHIFT = 0xc # macro +GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3__SHIFT = 0x10 # macro +GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3__SHIFT = 0x14 # macro +GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3__SHIFT = 0x18 # macro +GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3__SHIFT = 0x1c # macro +GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2_MASK = 0x00000007 # macro +GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2_MASK = 0x00000070 # macro +GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2_MASK = 0x00000700 # macro +GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2_MASK = 0x00007000 # macro +GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3_MASK = 0x00070000 # macro +GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3_MASK = 0x00700000 # macro +GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3_MASK = 0x07000000 # macro +GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3_MASK = 0x70000000 # macro +GL1_PIPE_STEER__PIPE0__SHIFT = 0x0 # macro +GL1_PIPE_STEER__PIPE1__SHIFT = 0x2 # macro +GL1_PIPE_STEER__PIPE2__SHIFT = 0x4 # macro +GL1_PIPE_STEER__PIPE3__SHIFT = 0x6 # macro +GL1_PIPE_STEER__PIPE0_MASK = 0x00000003 # macro +GL1_PIPE_STEER__PIPE1_MASK = 0x0000000C # macro +GL1_PIPE_STEER__PIPE2_MASK = 0x00000030 # macro +GL1_PIPE_STEER__PIPE3_MASK = 0x000000C0 # macro +CH_PIPE_STEER__PIPE0__SHIFT = 0x0 # macro +CH_PIPE_STEER__PIPE1__SHIFT = 0x2 # macro +CH_PIPE_STEER__PIPE2__SHIFT = 0x4 # macro +CH_PIPE_STEER__PIPE3__SHIFT = 0x6 # macro +CH_PIPE_STEER__PIPE0_MASK = 0x00000003 # macro +CH_PIPE_STEER__PIPE1_MASK = 0x0000000C # macro +CH_PIPE_STEER__PIPE2_MASK = 0x00000030 # macro +CH_PIPE_STEER__PIPE3_MASK = 0x000000C0 # macro +GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT = 0x10 # macro +GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK = 0xFFFF0000 # macro +GC_USER_PRIM_CONFIG__INACTIVE_PA__SHIFT = 0x4 # macro +GC_USER_PRIM_CONFIG__INACTIVE_PA_MASK = 0x000FFFF0 # macro +GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT = 0x8 # macro +GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK = 0x00FFFF00 # macro +GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT = 0x8 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT = 0xc # macro +GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT = 0x10 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT = 0x14 # macro +GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK = 0x00000F00 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK = 0x00001000 # macro +GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK = 0x000F0000 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK = 0x00100000 # macro +GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT = 0x4 # macro +GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK = 0xFFFFFFF0 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT = 0x1 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT = 0x2 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT = 0x3 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT = 0x4 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK = 0x00000002 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK = 0x00000004 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK = 0x00000008 # macro +GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK = 0x00000010 # macro +CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT = 0x8 # macro +CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT = 0x10 # macro +CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK = 0x0000FF00 # macro +CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK = 0xFFFF0000 # macro +GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT = 0x1 # macro +GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK = 0x00000006 # macro +RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +CP_MES_DM_INDEX_ADDR__ADDR__SHIFT = 0x0 # macro +CP_MES_DM_INDEX_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +CP_MES_DM_INDEX_DATA__DATA__SHIFT = 0x0 # macro +CP_MES_DM_INDEX_DATA__DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_DM_INDEX_ADDR__ADDR__SHIFT = 0x0 # macro +CP_MEC_DM_INDEX_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +CP_MEC_DM_INDEX_DATA__DATA__SHIFT = 0x0 # macro +CP_MEC_DM_INDEX_DATA__DATA_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DM_INDEX_ADDR__ADDR__SHIFT = 0x0 # macro +CP_GFX_RS64_DM_INDEX_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +CP_GFX_RS64_DM_INDEX_DATA__DATA__SHIFT = 0x0 # macro +CP_GFX_RS64_DM_INDEX_DATA__DATA_MASK = 0xFFFFFFFF # macro +CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT = 0x0 # macro +CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT = 0x2 # macro +CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT = 0x3 # macro +CPG_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT = 0x4 # macro +CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT = 0x5 # macro +CPG_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT = 0x6 # macro +CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK = 0x00000003 # macro +CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK = 0x00000004 # macro +CPG_PSP_DEBUG__GPA_OVERRIDE_MASK = 0x00000008 # macro +CPG_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK = 0x00000010 # macro +CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK = 0x00000020 # macro +CPG_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK = 0x00000040 # macro +CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT = 0x0 # macro +CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT = 0x3 # macro +CPC_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT = 0x4 # macro +CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT = 0x5 # macro +CPC_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT = 0x6 # macro +CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK = 0x00000003 # macro +CPC_PSP_DEBUG__GPA_OVERRIDE_MASK = 0x00000008 # macro +CPC_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK = 0x00000010 # macro +CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK = 0x00000020 # macro +CPC_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK = 0x00000040 # macro +GRBM_CAM_INDEX__CAM_INDEX__SHIFT = 0x0 # macro +GRBM_CAM_INDEX__CAM_INDEX_MASK = 0x0000000F # macro +GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT = 0x0 # macro +GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK = 0x0000000F # macro +GRBM_CAM_DATA__CAM_ADDR__SHIFT = 0x0 # macro +GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT = 0x10 # macro +GRBM_CAM_DATA__CAM_ADDR_MASK = 0x0000FFFF # macro +GRBM_CAM_DATA__CAM_REMAPADDR_MASK = 0xFFFF0000 # macro +GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT = 0x0 # macro +GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT = 0x10 # macro +GRBM_HYP_CAM_DATA__CAM_ADDR_MASK = 0x0000FFFF # macro +GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK = 0xFFFF0000 # macro +GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT = 0x0 # macro +GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT = 0x10 # macro +GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK = 0x00000003 # macro +GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK = 0x00030000 # macro +GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT = 0x0 # macro +GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT = 0x10 # macro +GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK = 0x00000003 # macro +GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK = 0x00030000 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT = 0x0 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT = 0x12 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT = 0x1e # macro +RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT = 0x1f # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK = 0x0003FFFF # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK = 0x3FFC0000 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK = 0x40000000 # macro +RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK = 0x80000000 # macro +GFX_IMU_C2PMSG_0__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_0__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_1__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_1__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_2__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_2__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_3__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_3__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_4__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_4__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_5__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_5__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_6__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_6__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_7__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_7__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_8__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_8__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_9__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_9__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_10__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_10__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_11__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_11__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_12__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_12__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_13__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_13__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_14__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_14__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_15__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_15__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_16__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_16__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_17__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_17__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_18__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_18__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_19__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_19__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_20__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_20__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_21__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_21__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_22__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_22__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_23__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_23__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_24__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_24__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_25__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_25__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_26__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_26__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_27__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_27__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_28__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_28__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_29__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_29__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_30__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_30__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_31__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_31__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_32__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_32__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_33__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_33__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_34__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_34__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_35__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_35__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_36__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_36__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_37__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_37__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_38__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_38__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_39__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_39__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_40__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_40__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_41__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_41__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_42__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_42__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_43__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_43__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_44__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_44__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_45__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_45__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_46__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_46__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_47__DATA__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_47__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_MSG_FLAGS__STATUS__SHIFT = 0x0 # macro +GFX_IMU_MSG_FLAGS__STATUS_MASK = 0xFFFFFFFF # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1__SHIFT = 0x3 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2__SHIFT = 0x6 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3__SHIFT = 0x9 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4__SHIFT = 0xc # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5__SHIFT = 0xf # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6__SHIFT = 0x12 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7__SHIFT = 0x15 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0_MASK = 0x00000007 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1_MASK = 0x00000038 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2_MASK = 0x000001C0 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3_MASK = 0x00000E00 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4_MASK = 0x00007000 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5_MASK = 0x00038000 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6_MASK = 0x001C0000 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7_MASK = 0x00E00000 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15__SHIFT = 0x0 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23__SHIFT = 0x3 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31__SHIFT = 0x6 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39__SHIFT = 0x9 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47__SHIFT = 0xc # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15_MASK = 0x00000007 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23_MASK = 0x00000038 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31_MASK = 0x000001C0 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39_MASK = 0x00000E00 # macro +GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47_MASK = 0x00007000 # macro +GFX_IMU_PWRMGT_IRQ_CTRL__REQ__SHIFT = 0x0 # macro +GFX_IMU_PWRMGT_IRQ_CTRL__REQ_MASK = 0x00000001 # macro +GFX_IMU_MP1_MUTEX__MUTEX__SHIFT = 0x0 # macro +GFX_IMU_MP1_MUTEX__MUTEX_MASK = 0x00000003 # macro +GFX_IMU_RLC_DATA_4__DATA__SHIFT = 0x0 # macro +GFX_IMU_RLC_DATA_4__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_DATA_3__DATA__SHIFT = 0x0 # macro +GFX_IMU_RLC_DATA_3__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_DATA_2__DATA__SHIFT = 0x0 # macro +GFX_IMU_RLC_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_DATA_1__DATA__SHIFT = 0x0 # macro +GFX_IMU_RLC_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_DATA_0__DATA__SHIFT = 0x0 # macro +GFX_IMU_RLC_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_CMD__CMD__SHIFT = 0x0 # macro +GFX_IMU_RLC_CMD__CMD_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_MUTEX__MUTEX__SHIFT = 0x0 # macro +GFX_IMU_RLC_MUTEX__MUTEX_MASK = 0x00000003 # macro +GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY__SHIFT = 0x0 # macro +GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR__SHIFT = 0x1 # macro +GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE__SHIFT = 0x10 # macro +GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG__SHIFT = 0x1e # macro +GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG__SHIFT = 0x1f # macro +GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY_MASK = 0x00000001 # macro +GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR_MASK = 0x00000002 # macro +GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE_MASK = 0x00010000 # macro +GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG_MASK = 0x40000000 # macro +GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG_MASK = 0x80000000 # macro +RLC_GFX_IMU_DATA_0__DATA__SHIFT = 0x0 # macro +RLC_GFX_IMU_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_GFX_IMU_CMD__CMD__SHIFT = 0x0 # macro +RLC_GFX_IMU_CMD__CMD_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_STATUS__PD_ACTIVE__SHIFT = 0x0 # macro +GFX_IMU_RLC_STATUS__RLC_ALIVE__SHIFT = 0x1 # macro +GFX_IMU_RLC_STATUS__TBD2__SHIFT = 0x2 # macro +GFX_IMU_RLC_STATUS__TBD3__SHIFT = 0x3 # macro +GFX_IMU_RLC_STATUS__PD_ACTIVE_MASK = 0x00000001 # macro +GFX_IMU_RLC_STATUS__RLC_ALIVE_MASK = 0x00000002 # macro +GFX_IMU_RLC_STATUS__TBD2_MASK = 0x00000004 # macro +GFX_IMU_RLC_STATUS__TBD3_MASK = 0x00000008 # macro +GFX_IMU_STATUS__ALLOW_GFXOFF__SHIFT = 0x0 # macro +GFX_IMU_STATUS__ALLOW_FA_DCS__SHIFT = 0x1 # macro +GFX_IMU_STATUS__TBD2__SHIFT = 0x2 # macro +GFX_IMU_STATUS__TBD3__SHIFT = 0x3 # macro +GFX_IMU_STATUS__TBD4__SHIFT = 0x4 # macro +GFX_IMU_STATUS__TBD5__SHIFT = 0x5 # macro +GFX_IMU_STATUS__TBD6__SHIFT = 0x6 # macro +GFX_IMU_STATUS__TBD7__SHIFT = 0x7 # macro +GFX_IMU_STATUS__TBD8__SHIFT = 0x8 # macro +GFX_IMU_STATUS__TBD9__SHIFT = 0x9 # macro +GFX_IMU_STATUS__TBD10__SHIFT = 0xa # macro +GFX_IMU_STATUS__TBD11__SHIFT = 0xb # macro +GFX_IMU_STATUS__TBD12__SHIFT = 0xc # macro +GFX_IMU_STATUS__TBD13__SHIFT = 0xd # macro +GFX_IMU_STATUS__TBD14__SHIFT = 0xe # macro +GFX_IMU_STATUS__DISABLE_GFXCLK_DS__SHIFT = 0xf # macro +GFX_IMU_STATUS__ALLOW_GFXOFF_MASK = 0x00000001 # macro +GFX_IMU_STATUS__ALLOW_FA_DCS_MASK = 0x00000002 # macro +GFX_IMU_STATUS__TBD2_MASK = 0x00000004 # macro +GFX_IMU_STATUS__TBD3_MASK = 0x00000008 # macro +GFX_IMU_STATUS__TBD4_MASK = 0x00000010 # macro +GFX_IMU_STATUS__TBD5_MASK = 0x00000020 # macro +GFX_IMU_STATUS__TBD6_MASK = 0x00000040 # macro +GFX_IMU_STATUS__TBD7_MASK = 0x00000080 # macro +GFX_IMU_STATUS__TBD8_MASK = 0x00000100 # macro +GFX_IMU_STATUS__TBD9_MASK = 0x00000200 # macro +GFX_IMU_STATUS__TBD10_MASK = 0x00000400 # macro +GFX_IMU_STATUS__TBD11_MASK = 0x00000800 # macro +GFX_IMU_STATUS__TBD12_MASK = 0x00001000 # macro +GFX_IMU_STATUS__TBD13_MASK = 0x00002000 # macro +GFX_IMU_STATUS__TBD14_MASK = 0x00004000 # macro +GFX_IMU_STATUS__DISABLE_GFXCLK_DS_MASK = 0x00008000 # macro +GFX_IMU_SOC_DATA__DATA__SHIFT = 0x0 # macro +GFX_IMU_SOC_DATA__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SOC_ADDR__ADDR__SHIFT = 0x0 # macro +GFX_IMU_SOC_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +GFX_IMU_SOC_REQ__REQ_BUSY__SHIFT = 0x0 # macro +GFX_IMU_SOC_REQ__R_W__SHIFT = 0x1 # macro +GFX_IMU_SOC_REQ__ERR__SHIFT = 0x1f # macro +GFX_IMU_SOC_REQ__REQ_BUSY_MASK = 0x00000001 # macro +GFX_IMU_SOC_REQ__R_W_MASK = 0x00000002 # macro +GFX_IMU_SOC_REQ__ERR_MASK = 0x80000000 # macro +GFX_IMU_VF_CTRL__VF__SHIFT = 0x0 # macro +GFX_IMU_VF_CTRL__VFID__SHIFT = 0x1 # macro +GFX_IMU_VF_CTRL__QOS__SHIFT = 0x7 # macro +GFX_IMU_VF_CTRL__VF_MASK = 0x00000001 # macro +GFX_IMU_VF_CTRL__VFID_MASK = 0x0000007E # macro +GFX_IMU_VF_CTRL__QOS_MASK = 0x00000780 # macro +GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES__SHIFT = 0x0 # macro +GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE__SHIFT = 0x5 # macro +GFX_IMU_TELEMETRY__FIFO_OVERFLOW__SHIFT = 0x6 # macro +GFX_IMU_TELEMETRY__FIFO_UNDERFLOW__SHIFT = 0x7 # macro +GFX_IMU_TELEMETRY__FSM_STATE__SHIFT = 0x8 # macro +GFX_IMU_TELEMETRY__SVI_TYPE__SHIFT = 0xc # macro +GFX_IMU_TELEMETRY__ENABLE_FIFO__SHIFT = 0x1e # macro +GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY__SHIFT = 0x1f # macro +GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES_MASK = 0x0000001F # macro +GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE_MASK = 0x00000020 # macro +GFX_IMU_TELEMETRY__FIFO_OVERFLOW_MASK = 0x00000040 # macro +GFX_IMU_TELEMETRY__FIFO_UNDERFLOW_MASK = 0x00000080 # macro +GFX_IMU_TELEMETRY__FSM_STATE_MASK = 0x00000700 # macro +GFX_IMU_TELEMETRY__SVI_TYPE_MASK = 0x00003000 # macro +GFX_IMU_TELEMETRY__ENABLE_FIFO_MASK = 0x40000000 # macro +GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY_MASK = 0x80000000 # macro +GFX_IMU_TELEMETRY_DATA__CURRENT__SHIFT = 0x0 # macro +GFX_IMU_TELEMETRY_DATA__VOLTAGE__SHIFT = 0x10 # macro +GFX_IMU_TELEMETRY_DATA__CURRENT_MASK = 0x0000FFFF # macro +GFX_IMU_TELEMETRY_DATA__VOLTAGE_MASK = 0xFFFF0000 # macro +GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE__SHIFT = 0x0 # macro +GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE_MASK = 0x0000FFFF # macro +GFX_IMU_SCRATCH_0__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_0__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_1__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_1__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_2__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_2__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_3__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_3__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_4__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_4__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_5__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_5__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_6__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_6__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_7__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_7__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_8__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_8__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_9__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_9__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_10__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_10__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_11__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_11__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_12__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_12__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_13__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_13__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_14__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_14__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_SCRATCH_15__DATA__SHIFT = 0x0 # macro +GFX_IMU_SCRATCH_15__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_FW_GTS_LO__TSTAMP_LO__SHIFT = 0x0 # macro +GFX_IMU_FW_GTS_LO__TSTAMP_LO_MASK = 0xFFFFFFFF # macro +GFX_IMU_FW_GTS_HI__TSTAMP_HI__SHIFT = 0x0 # macro +GFX_IMU_FW_GTS_HI__TSTAMP_HI_MASK = 0x00FFFFFF # macro +GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT = 0x0 # macro +GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK = 0xFFFFFFFF # macro +GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT = 0x0 # macro +GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK = 0x00FFFFFF # macro +GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT = 0x0 # macro +GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT = 0x0 # macro +GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK = 0x00FFFFFF # macro +GFX_IMU_CORE_INT_STATUS__INTERRUPT_24__SHIFT = 0x18 # macro +GFX_IMU_CORE_INT_STATUS__INTERRUPT_25__SHIFT = 0x19 # macro +GFX_IMU_CORE_INT_STATUS__INTERRUPT_29__SHIFT = 0x1d # macro +GFX_IMU_CORE_INT_STATUS__INTERRUPT_24_MASK = 0x01000000 # macro +GFX_IMU_CORE_INT_STATUS__INTERRUPT_25_MASK = 0x02000000 # macro +GFX_IMU_CORE_INT_STATUS__INTERRUPT_29_MASK = 0x20000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_0__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_MASK__MASK_1__SHIFT = 0x1 # macro +GFX_IMU_PIC_INT_MASK__MASK_2__SHIFT = 0x2 # macro +GFX_IMU_PIC_INT_MASK__MASK_3__SHIFT = 0x3 # macro +GFX_IMU_PIC_INT_MASK__MASK_4__SHIFT = 0x4 # macro +GFX_IMU_PIC_INT_MASK__MASK_5__SHIFT = 0x5 # macro +GFX_IMU_PIC_INT_MASK__MASK_6__SHIFT = 0x6 # macro +GFX_IMU_PIC_INT_MASK__MASK_7__SHIFT = 0x7 # macro +GFX_IMU_PIC_INT_MASK__MASK_8__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_MASK__MASK_9__SHIFT = 0x9 # macro +GFX_IMU_PIC_INT_MASK__MASK_10__SHIFT = 0xa # macro +GFX_IMU_PIC_INT_MASK__MASK_11__SHIFT = 0xb # macro +GFX_IMU_PIC_INT_MASK__MASK_12__SHIFT = 0xc # macro +GFX_IMU_PIC_INT_MASK__MASK_13__SHIFT = 0xd # macro +GFX_IMU_PIC_INT_MASK__MASK_14__SHIFT = 0xe # macro +GFX_IMU_PIC_INT_MASK__MASK_15__SHIFT = 0xf # macro +GFX_IMU_PIC_INT_MASK__MASK_16__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_MASK__MASK_17__SHIFT = 0x11 # macro +GFX_IMU_PIC_INT_MASK__MASK_18__SHIFT = 0x12 # macro +GFX_IMU_PIC_INT_MASK__MASK_19__SHIFT = 0x13 # macro +GFX_IMU_PIC_INT_MASK__MASK_20__SHIFT = 0x14 # macro +GFX_IMU_PIC_INT_MASK__MASK_21__SHIFT = 0x15 # macro +GFX_IMU_PIC_INT_MASK__MASK_22__SHIFT = 0x16 # macro +GFX_IMU_PIC_INT_MASK__MASK_23__SHIFT = 0x17 # macro +GFX_IMU_PIC_INT_MASK__MASK_24__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_MASK__MASK_25__SHIFT = 0x19 # macro +GFX_IMU_PIC_INT_MASK__MASK_26__SHIFT = 0x1a # macro +GFX_IMU_PIC_INT_MASK__MASK_27__SHIFT = 0x1b # macro +GFX_IMU_PIC_INT_MASK__MASK_28__SHIFT = 0x1c # macro +GFX_IMU_PIC_INT_MASK__MASK_29__SHIFT = 0x1d # macro +GFX_IMU_PIC_INT_MASK__MASK_30__SHIFT = 0x1e # macro +GFX_IMU_PIC_INT_MASK__MASK_31__SHIFT = 0x1f # macro +GFX_IMU_PIC_INT_MASK__MASK_0_MASK = 0x00000001 # macro +GFX_IMU_PIC_INT_MASK__MASK_1_MASK = 0x00000002 # macro +GFX_IMU_PIC_INT_MASK__MASK_2_MASK = 0x00000004 # macro +GFX_IMU_PIC_INT_MASK__MASK_3_MASK = 0x00000008 # macro +GFX_IMU_PIC_INT_MASK__MASK_4_MASK = 0x00000010 # macro +GFX_IMU_PIC_INT_MASK__MASK_5_MASK = 0x00000020 # macro +GFX_IMU_PIC_INT_MASK__MASK_6_MASK = 0x00000040 # macro +GFX_IMU_PIC_INT_MASK__MASK_7_MASK = 0x00000080 # macro +GFX_IMU_PIC_INT_MASK__MASK_8_MASK = 0x00000100 # macro +GFX_IMU_PIC_INT_MASK__MASK_9_MASK = 0x00000200 # macro +GFX_IMU_PIC_INT_MASK__MASK_10_MASK = 0x00000400 # macro +GFX_IMU_PIC_INT_MASK__MASK_11_MASK = 0x00000800 # macro +GFX_IMU_PIC_INT_MASK__MASK_12_MASK = 0x00001000 # macro +GFX_IMU_PIC_INT_MASK__MASK_13_MASK = 0x00002000 # macro +GFX_IMU_PIC_INT_MASK__MASK_14_MASK = 0x00004000 # macro +GFX_IMU_PIC_INT_MASK__MASK_15_MASK = 0x00008000 # macro +GFX_IMU_PIC_INT_MASK__MASK_16_MASK = 0x00010000 # macro +GFX_IMU_PIC_INT_MASK__MASK_17_MASK = 0x00020000 # macro +GFX_IMU_PIC_INT_MASK__MASK_18_MASK = 0x00040000 # macro +GFX_IMU_PIC_INT_MASK__MASK_19_MASK = 0x00080000 # macro +GFX_IMU_PIC_INT_MASK__MASK_20_MASK = 0x00100000 # macro +GFX_IMU_PIC_INT_MASK__MASK_21_MASK = 0x00200000 # macro +GFX_IMU_PIC_INT_MASK__MASK_22_MASK = 0x00400000 # macro +GFX_IMU_PIC_INT_MASK__MASK_23_MASK = 0x00800000 # macro +GFX_IMU_PIC_INT_MASK__MASK_24_MASK = 0x01000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_25_MASK = 0x02000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_26_MASK = 0x04000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_27_MASK = 0x08000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_28_MASK = 0x10000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_29_MASK = 0x20000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_30_MASK = 0x40000000 # macro +GFX_IMU_PIC_INT_MASK__MASK_31_MASK = 0x80000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_0__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_LVL__LVL_1__SHIFT = 0x1 # macro +GFX_IMU_PIC_INT_LVL__LVL_2__SHIFT = 0x2 # macro +GFX_IMU_PIC_INT_LVL__LVL_3__SHIFT = 0x3 # macro +GFX_IMU_PIC_INT_LVL__LVL_4__SHIFT = 0x4 # macro +GFX_IMU_PIC_INT_LVL__LVL_5__SHIFT = 0x5 # macro +GFX_IMU_PIC_INT_LVL__LVL_6__SHIFT = 0x6 # macro +GFX_IMU_PIC_INT_LVL__LVL_7__SHIFT = 0x7 # macro +GFX_IMU_PIC_INT_LVL__LVL_8__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_LVL__LVL_9__SHIFT = 0x9 # macro +GFX_IMU_PIC_INT_LVL__LVL_10__SHIFT = 0xa # macro +GFX_IMU_PIC_INT_LVL__LVL_11__SHIFT = 0xb # macro +GFX_IMU_PIC_INT_LVL__LVL_12__SHIFT = 0xc # macro +GFX_IMU_PIC_INT_LVL__LVL_13__SHIFT = 0xd # macro +GFX_IMU_PIC_INT_LVL__LVL_14__SHIFT = 0xe # macro +GFX_IMU_PIC_INT_LVL__LVL_15__SHIFT = 0xf # macro +GFX_IMU_PIC_INT_LVL__LVL_16__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_LVL__LVL_17__SHIFT = 0x11 # macro +GFX_IMU_PIC_INT_LVL__LVL_18__SHIFT = 0x12 # macro +GFX_IMU_PIC_INT_LVL__LVL_19__SHIFT = 0x13 # macro +GFX_IMU_PIC_INT_LVL__LVL_20__SHIFT = 0x14 # macro +GFX_IMU_PIC_INT_LVL__LVL_21__SHIFT = 0x15 # macro +GFX_IMU_PIC_INT_LVL__LVL_22__SHIFT = 0x16 # macro +GFX_IMU_PIC_INT_LVL__LVL_23__SHIFT = 0x17 # macro +GFX_IMU_PIC_INT_LVL__LVL_24__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_LVL__LVL_25__SHIFT = 0x19 # macro +GFX_IMU_PIC_INT_LVL__LVL_26__SHIFT = 0x1a # macro +GFX_IMU_PIC_INT_LVL__LVL_27__SHIFT = 0x1b # macro +GFX_IMU_PIC_INT_LVL__LVL_28__SHIFT = 0x1c # macro +GFX_IMU_PIC_INT_LVL__LVL_29__SHIFT = 0x1d # macro +GFX_IMU_PIC_INT_LVL__LVL_30__SHIFT = 0x1e # macro +GFX_IMU_PIC_INT_LVL__LVL_31__SHIFT = 0x1f # macro +GFX_IMU_PIC_INT_LVL__LVL_0_MASK = 0x00000001 # macro +GFX_IMU_PIC_INT_LVL__LVL_1_MASK = 0x00000002 # macro +GFX_IMU_PIC_INT_LVL__LVL_2_MASK = 0x00000004 # macro +GFX_IMU_PIC_INT_LVL__LVL_3_MASK = 0x00000008 # macro +GFX_IMU_PIC_INT_LVL__LVL_4_MASK = 0x00000010 # macro +GFX_IMU_PIC_INT_LVL__LVL_5_MASK = 0x00000020 # macro +GFX_IMU_PIC_INT_LVL__LVL_6_MASK = 0x00000040 # macro +GFX_IMU_PIC_INT_LVL__LVL_7_MASK = 0x00000080 # macro +GFX_IMU_PIC_INT_LVL__LVL_8_MASK = 0x00000100 # macro +GFX_IMU_PIC_INT_LVL__LVL_9_MASK = 0x00000200 # macro +GFX_IMU_PIC_INT_LVL__LVL_10_MASK = 0x00000400 # macro +GFX_IMU_PIC_INT_LVL__LVL_11_MASK = 0x00000800 # macro +GFX_IMU_PIC_INT_LVL__LVL_12_MASK = 0x00001000 # macro +GFX_IMU_PIC_INT_LVL__LVL_13_MASK = 0x00002000 # macro +GFX_IMU_PIC_INT_LVL__LVL_14_MASK = 0x00004000 # macro +GFX_IMU_PIC_INT_LVL__LVL_15_MASK = 0x00008000 # macro +GFX_IMU_PIC_INT_LVL__LVL_16_MASK = 0x00010000 # macro +GFX_IMU_PIC_INT_LVL__LVL_17_MASK = 0x00020000 # macro +GFX_IMU_PIC_INT_LVL__LVL_18_MASK = 0x00040000 # macro +GFX_IMU_PIC_INT_LVL__LVL_19_MASK = 0x00080000 # macro +GFX_IMU_PIC_INT_LVL__LVL_20_MASK = 0x00100000 # macro +GFX_IMU_PIC_INT_LVL__LVL_21_MASK = 0x00200000 # macro +GFX_IMU_PIC_INT_LVL__LVL_22_MASK = 0x00400000 # macro +GFX_IMU_PIC_INT_LVL__LVL_23_MASK = 0x00800000 # macro +GFX_IMU_PIC_INT_LVL__LVL_24_MASK = 0x01000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_25_MASK = 0x02000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_26_MASK = 0x04000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_27_MASK = 0x08000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_28_MASK = 0x10000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_29_MASK = 0x20000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_30_MASK = 0x40000000 # macro +GFX_IMU_PIC_INT_LVL__LVL_31_MASK = 0x80000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_0__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_1__SHIFT = 0x1 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_2__SHIFT = 0x2 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_3__SHIFT = 0x3 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_4__SHIFT = 0x4 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_5__SHIFT = 0x5 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_6__SHIFT = 0x6 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_7__SHIFT = 0x7 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_8__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_9__SHIFT = 0x9 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_10__SHIFT = 0xa # macro +GFX_IMU_PIC_INT_EDGE__EDGE_11__SHIFT = 0xb # macro +GFX_IMU_PIC_INT_EDGE__EDGE_12__SHIFT = 0xc # macro +GFX_IMU_PIC_INT_EDGE__EDGE_13__SHIFT = 0xd # macro +GFX_IMU_PIC_INT_EDGE__EDGE_14__SHIFT = 0xe # macro +GFX_IMU_PIC_INT_EDGE__EDGE_15__SHIFT = 0xf # macro +GFX_IMU_PIC_INT_EDGE__EDGE_16__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_17__SHIFT = 0x11 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_18__SHIFT = 0x12 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_19__SHIFT = 0x13 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_20__SHIFT = 0x14 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_21__SHIFT = 0x15 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_22__SHIFT = 0x16 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_23__SHIFT = 0x17 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_24__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_25__SHIFT = 0x19 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_26__SHIFT = 0x1a # macro +GFX_IMU_PIC_INT_EDGE__EDGE_27__SHIFT = 0x1b # macro +GFX_IMU_PIC_INT_EDGE__EDGE_28__SHIFT = 0x1c # macro +GFX_IMU_PIC_INT_EDGE__EDGE_29__SHIFT = 0x1d # macro +GFX_IMU_PIC_INT_EDGE__EDGE_30__SHIFT = 0x1e # macro +GFX_IMU_PIC_INT_EDGE__EDGE_31__SHIFT = 0x1f # macro +GFX_IMU_PIC_INT_EDGE__EDGE_0_MASK = 0x00000001 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_1_MASK = 0x00000002 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_2_MASK = 0x00000004 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_3_MASK = 0x00000008 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_4_MASK = 0x00000010 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_5_MASK = 0x00000020 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_6_MASK = 0x00000040 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_7_MASK = 0x00000080 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_8_MASK = 0x00000100 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_9_MASK = 0x00000200 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_10_MASK = 0x00000400 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_11_MASK = 0x00000800 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_12_MASK = 0x00001000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_13_MASK = 0x00002000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_14_MASK = 0x00004000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_15_MASK = 0x00008000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_16_MASK = 0x00010000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_17_MASK = 0x00020000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_18_MASK = 0x00040000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_19_MASK = 0x00080000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_20_MASK = 0x00100000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_21_MASK = 0x00200000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_22_MASK = 0x00400000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_23_MASK = 0x00800000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_24_MASK = 0x01000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_25_MASK = 0x02000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_26_MASK = 0x04000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_27_MASK = 0x08000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_28_MASK = 0x10000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_29_MASK = 0x20000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_30_MASK = 0x40000000 # macro +GFX_IMU_PIC_INT_EDGE__EDGE_31_MASK = 0x80000000 # macro +GFX_IMU_PIC_INT_PRI_0__PRI_0__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_0__PRI_1__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_0__PRI_2__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_0__PRI_3__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_0__PRI_0_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_0__PRI_1_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_0__PRI_2_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_0__PRI_3_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_PRI_1__PRI_4__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_1__PRI_5__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_1__PRI_6__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_1__PRI_7__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_1__PRI_4_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_1__PRI_5_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_1__PRI_6_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_1__PRI_7_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_PRI_2__PRI_8__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_2__PRI_9__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_2__PRI_10__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_2__PRI_11__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_2__PRI_8_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_2__PRI_9_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_2__PRI_10_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_2__PRI_11_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_PRI_3__PRI_12__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_3__PRI_13__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_3__PRI_14__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_3__PRI_15__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_3__PRI_12_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_3__PRI_13_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_3__PRI_14_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_3__PRI_15_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_PRI_4__PRI_16__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_4__PRI_17__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_4__PRI_18__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_4__PRI_19__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_4__PRI_16_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_4__PRI_17_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_4__PRI_18_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_4__PRI_19_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_PRI_5__PRI_20__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_5__PRI_21__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_5__PRI_22__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_5__PRI_23__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_5__PRI_20_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_5__PRI_21_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_5__PRI_22_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_5__PRI_23_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_PRI_6__PRI_24__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_6__PRI_25__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_6__PRI_26__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_6__PRI_27__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_6__PRI_24_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_6__PRI_25_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_6__PRI_26_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_6__PRI_27_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_PRI_7__PRI_28__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_PRI_7__PRI_29__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_PRI_7__PRI_30__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_PRI_7__PRI_31__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_PRI_7__PRI_28_MASK = 0x000000FF # macro +GFX_IMU_PIC_INT_PRI_7__PRI_29_MASK = 0x0000FF00 # macro +GFX_IMU_PIC_INT_PRI_7__PRI_30_MASK = 0x00FF0000 # macro +GFX_IMU_PIC_INT_PRI_7__PRI_31_MASK = 0xFF000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS0__SHIFT = 0x0 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS1__SHIFT = 0x1 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS2__SHIFT = 0x2 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS3__SHIFT = 0x3 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS4__SHIFT = 0x4 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS5__SHIFT = 0x5 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS6__SHIFT = 0x6 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS7__SHIFT = 0x7 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS8__SHIFT = 0x8 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS9__SHIFT = 0x9 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS10__SHIFT = 0xa # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS11__SHIFT = 0xb # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS12__SHIFT = 0xc # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS13__SHIFT = 0xd # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS14__SHIFT = 0xe # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS15__SHIFT = 0xf # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS16__SHIFT = 0x10 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS17__SHIFT = 0x11 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS18__SHIFT = 0x12 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS19__SHIFT = 0x13 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS20__SHIFT = 0x14 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS21__SHIFT = 0x15 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS22__SHIFT = 0x16 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS23__SHIFT = 0x17 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS24__SHIFT = 0x18 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS25__SHIFT = 0x19 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS26__SHIFT = 0x1a # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS27__SHIFT = 0x1b # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS28__SHIFT = 0x1c # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS29__SHIFT = 0x1d # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS30__SHIFT = 0x1e # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS31__SHIFT = 0x1f # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS0_MASK = 0x00000001 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS1_MASK = 0x00000002 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS2_MASK = 0x00000004 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS3_MASK = 0x00000008 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS4_MASK = 0x00000010 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS5_MASK = 0x00000020 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS6_MASK = 0x00000040 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS7_MASK = 0x00000080 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS8_MASK = 0x00000100 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS9_MASK = 0x00000200 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS10_MASK = 0x00000400 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS11_MASK = 0x00000800 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS12_MASK = 0x00001000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS13_MASK = 0x00002000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS14_MASK = 0x00004000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS15_MASK = 0x00008000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS16_MASK = 0x00010000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS17_MASK = 0x00020000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS18_MASK = 0x00040000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS19_MASK = 0x00080000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS20_MASK = 0x00100000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS21_MASK = 0x00200000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS22_MASK = 0x00400000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS23_MASK = 0x00800000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS24_MASK = 0x01000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS25_MASK = 0x02000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS26_MASK = 0x04000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS27_MASK = 0x08000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS28_MASK = 0x10000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS29_MASK = 0x20000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS30_MASK = 0x40000000 # macro +GFX_IMU_PIC_INT_STATUS__INT_STATUS31_MASK = 0x80000000 # macro +GFX_IMU_PIC_INTR__INTR_n__SHIFT = 0x0 # macro +GFX_IMU_PIC_INTR__INTR_n_MASK = 0x00000001 # macro +GFX_IMU_PIC_INTR_ID__INTR_n__SHIFT = 0x0 # macro +GFX_IMU_PIC_INTR_ID__INTR_n_MASK = 0x000000FF # macro +GFX_IMU_IH_CTRL_1__CONTEXT_ID__SHIFT = 0x0 # macro +GFX_IMU_IH_CTRL_1__CONTEXT_ID_MASK = 0xFFFFFFFF # macro +GFX_IMU_IH_CTRL_2__CONTEXT_ID__SHIFT = 0x0 # macro +GFX_IMU_IH_CTRL_2__RING_ID__SHIFT = 0x8 # macro +GFX_IMU_IH_CTRL_2__VM_ID__SHIFT = 0x10 # macro +GFX_IMU_IH_CTRL_2__SRSTB__SHIFT = 0x1f # macro +GFX_IMU_IH_CTRL_2__CONTEXT_ID_MASK = 0x000000FF # macro +GFX_IMU_IH_CTRL_2__RING_ID_MASK = 0x0000FF00 # macro +GFX_IMU_IH_CTRL_2__VM_ID_MASK = 0x000F0000 # macro +GFX_IMU_IH_CTRL_2__SRSTB_MASK = 0x80000000 # macro +GFX_IMU_IH_CTRL_3__SOURCE_ID__SHIFT = 0x0 # macro +GFX_IMU_IH_CTRL_3__VF_ID__SHIFT = 0x8 # macro +GFX_IMU_IH_CTRL_3__VF__SHIFT = 0xd # macro +GFX_IMU_IH_CTRL_3__SOURCE_ID_MASK = 0x000000FF # macro +GFX_IMU_IH_CTRL_3__VF_ID_MASK = 0x00001F00 # macro +GFX_IMU_IH_CTRL_3__VF_MASK = 0x00002000 # macro +GFX_IMU_IH_STATUS__IH_BUSY__SHIFT = 0x0 # macro +GFX_IMU_IH_STATUS__IH_BUSY_MASK = 0x00000001 # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__REQ__SHIFT = 0x0 # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__DATA__SHIFT = 0x1 # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN__SHIFT = 0xa # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__ACK__SHIFT = 0xb # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL__SHIFT = 0x1f # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__REQ_MASK = 0x00000001 # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__DATA_MASK = 0x000003FE # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN_MASK = 0x00000400 # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__ACK_MASK = 0x00000800 # macro +GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL_MASK = 0x80000000 # macro +GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL__SHIFT = 0x0 # macro +GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL_MASK = 0x00000001 # macro +GFX_IMU_CLK_CTRL__CG_OVR__SHIFT = 0x0 # macro +GFX_IMU_CLK_CTRL__CG_OVR_CORE__SHIFT = 0x1 # macro +GFX_IMU_CLK_CTRL__CLKDIV__SHIFT = 0x4 # macro +GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG__SHIFT = 0x8 # macro +GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG__SHIFT = 0x9 # macro +GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV__SHIFT = 0x10 # macro +GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD__SHIFT = 0x1c # macro +GFX_IMU_CLK_CTRL__CG_OVR_MASK = 0x00000001 # macro +GFX_IMU_CLK_CTRL__CG_OVR_CORE_MASK = 0x00000002 # macro +GFX_IMU_CLK_CTRL__CLKDIV_MASK = 0x00000010 # macro +GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG_MASK = 0x00000100 # macro +GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG_MASK = 0x00000200 # macro +GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV_MASK = 0x007F0000 # macro +GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD_MASK = 0xF0000000 # macro +GFX_IMU_DOORBELL_CONTROL__OVR_EN__SHIFT = 0x0 # macro +GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR__SHIFT = 0x1 # macro +GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT__SHIFT = 0x18 # macro +GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS__SHIFT = 0x1f # macro +GFX_IMU_DOORBELL_CONTROL__OVR_EN_MASK = 0x00000001 # macro +GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR_MASK = 0x00000002 # macro +GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT_MASK = 0x7F000000 # macro +GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS_MASK = 0x80000000 # macro +GFX_IMU_RLC_CG_CTRL__FORCE_CGCG__SHIFT = 0x0 # macro +GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN__SHIFT = 0x1 # macro +GFX_IMU_RLC_CG_CTRL__FORCE_CGCG_MASK = 0x00000001 # macro +GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN_MASK = 0x00000002 # macro +GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN__SHIFT = 0x0 # macro +GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN_MASK = 0x00000001 # macro +GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF__SHIFT = 0x0 # macro +GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT__SHIFT = 0x2 # macro +GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT__SHIFT = 0x3 # macro +GFX_IMU_RLC_RESET_VECTOR__VECTOR__SHIFT = 0x4 # macro +GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF_MASK = 0x00000001 # macro +GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT_MASK = 0x00000004 # macro +GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT_MASK = 0x00000008 # macro +GFX_IMU_RLC_RESET_VECTOR__VECTOR_MASK = 0x000000F0 # macro +GFX_IMU_RLC_OVERRIDE__DS_ALLOW__SHIFT = 0x0 # macro +GFX_IMU_RLC_OVERRIDE__DS_ALLOW_MASK = 0x00000001 # macro +GFX_IMU_DPM_CONTROL__ACC_RESET__SHIFT = 0x0 # macro +GFX_IMU_DPM_CONTROL__ACC_START__SHIFT = 0x1 # macro +GFX_IMU_DPM_CONTROL__BUSY_MASK__SHIFT = 0x2 # macro +GFX_IMU_DPM_CONTROL__ACC_RESET_MASK = 0x00000001 # macro +GFX_IMU_DPM_CONTROL__ACC_START_MASK = 0x00000002 # macro +GFX_IMU_DPM_CONTROL__BUSY_MASK_MASK = 0x0003FFFC # macro +GFX_IMU_DPM_ACC__COUNT__SHIFT = 0x0 # macro +GFX_IMU_DPM_ACC__COUNT_MASK = 0x00FFFFFF # macro +GFX_IMU_DPM_REF_COUNTER__COUNT__SHIFT = 0x0 # macro +GFX_IMU_DPM_REF_COUNTER__COUNT_MASK = 0x00FFFFFF # macro +GFX_IMU_RLC_RAM_INDEX__INDEX__SHIFT = 0x0 # macro +GFX_IMU_RLC_RAM_INDEX__RLC_INDEX__SHIFT = 0x10 # macro +GFX_IMU_RLC_RAM_INDEX__RAM_VALID__SHIFT = 0x1f # macro +GFX_IMU_RLC_RAM_INDEX__INDEX_MASK = 0x000000FF # macro +GFX_IMU_RLC_RAM_INDEX__RLC_INDEX_MASK = 0x00FF0000 # macro +GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK = 0x80000000 # macro +GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB__SHIFT = 0x0 # macro +GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB_MASK = 0x0000FFFF # macro +GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB__SHIFT = 0x0 # macro +GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB_MASK = 0xFFFFFFFF # macro +GFX_IMU_RLC_RAM_DATA__DATA__SHIFT = 0x0 # macro +GFX_IMU_RLC_RAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_FENCE_CTRL__ENABLED__SHIFT = 0x0 # macro +GFX_IMU_FENCE_CTRL__ARM_LOG__SHIFT = 0x1 # macro +GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS__SHIFT = 0x3 # macro +GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN__SHIFT = 0x8 # macro +GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR__SHIFT = 0x9 # macro +GFX_IMU_FENCE_CTRL__ENABLED_MASK = 0x00000001 # macro +GFX_IMU_FENCE_CTRL__ARM_LOG_MASK = 0x00000002 # macro +GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS_MASK = 0x00000008 # macro +GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN_MASK = 0x00000100 # macro +GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_MASK = 0x00000200 # macro +GFX_IMU_FENCE_LOG_INIT__UNIT_ID__SHIFT = 0x0 # macro +GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID__SHIFT = 0x7 # macro +GFX_IMU_FENCE_LOG_INIT__UNIT_ID_MASK = 0x0000007F # macro +GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID_MASK = 0x0001FF80 # macro +GFX_IMU_FENCE_LOG_ADDR__ADDR__SHIFT = 0x2 # macro +GFX_IMU_FENCE_LOG_ADDR__ADDR_MASK = 0x000FFFFC # macro +GFX_IMU_PROGRAM_CTR__PC__SHIFT = 0x0 # macro +GFX_IMU_PROGRAM_CTR__PC_MASK = 0xFFFFFFFF # macro +GFX_IMU_CORE_CTRL__CRESET__SHIFT = 0x0 # macro +GFX_IMU_CORE_CTRL__CSTALL__SHIFT = 0x1 # macro +GFX_IMU_CORE_CTRL__DRESET__SHIFT = 0x3 # macro +GFX_IMU_CORE_CTRL__HALT_ON_RESET__SHIFT = 0x4 # macro +GFX_IMU_CORE_CTRL__BREAK_IN__SHIFT = 0x8 # macro +GFX_IMU_CORE_CTRL__BREAK_OUT_ACK__SHIFT = 0x9 # macro +GFX_IMU_CORE_CTRL__CRESET_MASK = 0x00000001 # macro +GFX_IMU_CORE_CTRL__CSTALL_MASK = 0x00000002 # macro +GFX_IMU_CORE_CTRL__DRESET_MASK = 0x00000008 # macro +GFX_IMU_CORE_CTRL__HALT_ON_RESET_MASK = 0x00000010 # macro +GFX_IMU_CORE_CTRL__BREAK_IN_MASK = 0x00000100 # macro +GFX_IMU_CORE_CTRL__BREAK_OUT_ACK_MASK = 0x00000200 # macro +GFX_IMU_CORE_STATUS__CBUSY__SHIFT = 0x0 # macro +GFX_IMU_CORE_STATUS__PWAIT_MODE__SHIFT = 0x1 # macro +GFX_IMU_CORE_STATUS__CINTLEVEL__SHIFT = 0x4 # macro +GFX_IMU_CORE_STATUS__BREAK_IN_ACK__SHIFT = 0x8 # macro +GFX_IMU_CORE_STATUS__BREAK_OUT__SHIFT = 0x9 # macro +GFX_IMU_CORE_STATUS__P_FATAL_ERROR__SHIFT = 0xb # macro +GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL__SHIFT = 0x18 # macro +GFX_IMU_CORE_STATUS__FAULT_TYPE__SHIFT = 0x1c # macro +GFX_IMU_CORE_STATUS__CBUSY_MASK = 0x00000001 # macro +GFX_IMU_CORE_STATUS__PWAIT_MODE_MASK = 0x00000002 # macro +GFX_IMU_CORE_STATUS__CINTLEVEL_MASK = 0x000000F0 # macro +GFX_IMU_CORE_STATUS__BREAK_IN_ACK_MASK = 0x00000100 # macro +GFX_IMU_CORE_STATUS__BREAK_OUT_MASK = 0x00000200 # macro +GFX_IMU_CORE_STATUS__P_FATAL_ERROR_MASK = 0x00000800 # macro +GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL_MASK = 0x0F000000 # macro +GFX_IMU_CORE_STATUS__FAULT_TYPE_MASK = 0xF0000000 # macro +GFX_IMU_PWROKRAW__PWROKRAW__SHIFT = 0x0 # macro +GFX_IMU_PWROKRAW__PWROKRAW_MASK = 0x00000001 # macro +GFX_IMU_PWROK__PWROK__SHIFT = 0x0 # macro +GFX_IMU_PWROK__PWROK_MASK = 0x00000001 # macro +GFX_IMU_GAP_PWROK__GAP_PWROK__SHIFT = 0x0 # macro +GFX_IMU_GAP_PWROK__GAP_PWROK_MASK = 0x00000001 # macro +GFX_IMU_RESETn__Cpl_RESETn__SHIFT = 0x0 # macro +GFX_IMU_RESETn__Cpl_RESETn_MASK = 0x00000001 # macro +GFX_IMU_GFX_RESET_CTRL__HARD_RESETB__SHIFT = 0x0 # macro +GFX_IMU_GFX_RESET_CTRL__EA_RESETB__SHIFT = 0x1 # macro +GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB__SHIFT = 0x2 # macro +GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB__SHIFT = 0x3 # macro +GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB__SHIFT = 0x4 # macro +GFX_IMU_GFX_RESET_CTRL__HARD_RESETB_MASK = 0x00000001 # macro +GFX_IMU_GFX_RESET_CTRL__EA_RESETB_MASK = 0x00000002 # macro +GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB_MASK = 0x00000004 # macro +GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB_MASK = 0x00000008 # macro +GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB_MASK = 0x00000010 # macro +GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL__SHIFT = 0x0 # macro +GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE__SHIFT = 0x1 # macro +GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE__SHIFT = 0x2 # macro +GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL_MASK = 0x00000001 # macro +GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE_MASK = 0x00000002 # macro +GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE_MASK = 0x00000004 # macro +GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn__SHIFT = 0x0 # macro +GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET__SHIFT = 0x1 # macro +GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET__SHIFT = 0x2 # macro +GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn__SHIFT = 0x4 # macro +GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn_MASK = 0x00000001 # macro +GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET_MASK = 0x00000002 # macro +GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET_MASK = 0x00000004 # macro +GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn_MASK = 0x00000010 # macro +GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn__SHIFT = 0x0 # macro +GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN__SHIFT = 0x1 # macro +GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN__SHIFT = 0x2 # macro +GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn__SHIFT = 0x3 # macro +GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn__SHIFT = 0x4 # macro +GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn_MASK = 0x00000001 # macro +GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN_MASK = 0x00000002 # macro +GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN_MASK = 0x00000004 # macro +GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn_MASK = 0x00000008 # macro +GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn_MASK = 0x00000010 # macro +GFX_IMU_TIMER0_CTRL0__START_STOP__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_CTRL0__CLEAR__SHIFT = 0x8 # macro +GFX_IMU_TIMER0_CTRL0__UP_DOWN__SHIFT = 0x10 # macro +GFX_IMU_TIMER0_CTRL0__PULSE_EN__SHIFT = 0x18 # macro +GFX_IMU_TIMER0_CTRL0__START_STOP_MASK = 0x00000001 # macro +GFX_IMU_TIMER0_CTRL0__CLEAR_MASK = 0x00000100 # macro +GFX_IMU_TIMER0_CTRL0__UP_DOWN_MASK = 0x00010000 # macro +GFX_IMU_TIMER0_CTRL0__PULSE_EN_MASK = 0x01000000 # macro +GFX_IMU_TIMER0_CTRL1__PWM_EN__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_CTRL1__TS_MODE__SHIFT = 0x8 # macro +GFX_IMU_TIMER0_CTRL1__SAT_EN__SHIFT = 0x10 # macro +GFX_IMU_TIMER0_CTRL1__PWM_EN_MASK = 0x00000001 # macro +GFX_IMU_TIMER0_CTRL1__TS_MODE_MASK = 0x00000100 # macro +GFX_IMU_TIMER0_CTRL1__SAT_EN_MASK = 0x00010000 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1__SHIFT = 0x1 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2__SHIFT = 0x2 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3__SHIFT = 0x3 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0_MASK = 0x00000001 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1_MASK = 0x00000002 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2_MASK = 0x00000004 # macro +GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3_MASK = 0x00000008 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN0__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN1__SHIFT = 0x1 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN2__SHIFT = 0x2 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN3__SHIFT = 0x3 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN0_MASK = 0x00000001 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN1_MASK = 0x00000002 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN2_MASK = 0x00000004 # macro +GFX_IMU_TIMER0_CMP_INTEN__INT_EN3_MASK = 0x00000008 # macro +GFX_IMU_TIMER0_CMP0__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_CMP0__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER0_CMP1__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_CMP1__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER0_CMP3__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_CMP3__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER0_VALUE__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER0_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER1_CTRL0__START_STOP__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_CTRL0__CLEAR__SHIFT = 0x8 # macro +GFX_IMU_TIMER1_CTRL0__UP_DOWN__SHIFT = 0x10 # macro +GFX_IMU_TIMER1_CTRL0__PULSE_EN__SHIFT = 0x18 # macro +GFX_IMU_TIMER1_CTRL0__START_STOP_MASK = 0x00000001 # macro +GFX_IMU_TIMER1_CTRL0__CLEAR_MASK = 0x00000100 # macro +GFX_IMU_TIMER1_CTRL0__UP_DOWN_MASK = 0x00010000 # macro +GFX_IMU_TIMER1_CTRL0__PULSE_EN_MASK = 0x01000000 # macro +GFX_IMU_TIMER1_CTRL1__PWM_EN__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_CTRL1__TS_MODE__SHIFT = 0x8 # macro +GFX_IMU_TIMER1_CTRL1__SAT_EN__SHIFT = 0x10 # macro +GFX_IMU_TIMER1_CTRL1__PWM_EN_MASK = 0x00000001 # macro +GFX_IMU_TIMER1_CTRL1__TS_MODE_MASK = 0x00000100 # macro +GFX_IMU_TIMER1_CTRL1__SAT_EN_MASK = 0x00010000 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1__SHIFT = 0x1 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2__SHIFT = 0x2 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3__SHIFT = 0x3 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0_MASK = 0x00000001 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1_MASK = 0x00000002 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2_MASK = 0x00000004 # macro +GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3_MASK = 0x00000008 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN0__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN1__SHIFT = 0x1 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN2__SHIFT = 0x2 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN3__SHIFT = 0x3 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN0_MASK = 0x00000001 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN1_MASK = 0x00000002 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN2_MASK = 0x00000004 # macro +GFX_IMU_TIMER1_CMP_INTEN__INT_EN3_MASK = 0x00000008 # macro +GFX_IMU_TIMER1_CMP0__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_CMP0__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER1_CMP1__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_CMP1__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER1_CMP3__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_CMP3__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER1_VALUE__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER1_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER2_CTRL0__START_STOP__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_CTRL0__CLEAR__SHIFT = 0x8 # macro +GFX_IMU_TIMER2_CTRL0__UP_DOWN__SHIFT = 0x10 # macro +GFX_IMU_TIMER2_CTRL0__PULSE_EN__SHIFT = 0x18 # macro +GFX_IMU_TIMER2_CTRL0__START_STOP_MASK = 0x00000001 # macro +GFX_IMU_TIMER2_CTRL0__CLEAR_MASK = 0x00000100 # macro +GFX_IMU_TIMER2_CTRL0__UP_DOWN_MASK = 0x00010000 # macro +GFX_IMU_TIMER2_CTRL0__PULSE_EN_MASK = 0x01000000 # macro +GFX_IMU_TIMER2_CTRL1__PWM_EN__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_CTRL1__TS_MODE__SHIFT = 0x8 # macro +GFX_IMU_TIMER2_CTRL1__SAT_EN__SHIFT = 0x10 # macro +GFX_IMU_TIMER2_CTRL1__PWM_EN_MASK = 0x00000001 # macro +GFX_IMU_TIMER2_CTRL1__TS_MODE_MASK = 0x00000100 # macro +GFX_IMU_TIMER2_CTRL1__SAT_EN_MASK = 0x00010000 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1__SHIFT = 0x1 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2__SHIFT = 0x2 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3__SHIFT = 0x3 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0_MASK = 0x00000001 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1_MASK = 0x00000002 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2_MASK = 0x00000004 # macro +GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3_MASK = 0x00000008 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN0__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN1__SHIFT = 0x1 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN2__SHIFT = 0x2 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN3__SHIFT = 0x3 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN0_MASK = 0x00000001 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN1_MASK = 0x00000002 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN2_MASK = 0x00000004 # macro +GFX_IMU_TIMER2_CMP_INTEN__INT_EN3_MASK = 0x00000008 # macro +GFX_IMU_TIMER2_CMP0__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_CMP0__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER2_CMP1__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_CMP1__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER2_CMP3__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_CMP3__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_TIMER2_VALUE__VALUE__SHIFT = 0x0 # macro +GFX_IMU_TIMER2_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +GFX_IMU_FUSE_CTRL__DIV_OVR__SHIFT = 0x0 # macro +GFX_IMU_FUSE_CTRL__DIV_OVR_EN__SHIFT = 0x5 # macro +GFX_IMU_FUSE_CTRL__FORCE_DONE__SHIFT = 0x6 # macro +GFX_IMU_FUSE_CTRL__DIV_OVR_MASK = 0x0000001F # macro +GFX_IMU_FUSE_CTRL__DIV_OVR_EN_MASK = 0x00000020 # macro +GFX_IMU_FUSE_CTRL__FORCE_DONE_MASK = 0x00000040 # macro +GFX_IMU_D_RAM_ADDR__ADDR__SHIFT = 0x2 # macro +GFX_IMU_D_RAM_ADDR__ADDR_MASK = 0x0000FFFC # macro +GFX_IMU_D_RAM_DATA__DATA__SHIFT = 0x0 # macro +GFX_IMU_D_RAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB__SHIFT = 0x0 # macro +GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL__SHIFT = 0x10 # macro +GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW__SHIFT = 0x14 # macro +GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB_MASK = 0x00000001 # macro +GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL_MASK = 0x000F0000 # macro +GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW_MASK = 0x00100000 # macro +GFX_IMU_I_RAM_ADDR__ADDR__SHIFT = 0x2 # macro +GFX_IMU_I_RAM_ADDR__ADDR_MASK = 0x0000FFFC # macro +GFX_IMU_I_RAM_DATA__DATA__SHIFT = 0x0 # macro +GFX_IMU_I_RAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +GC_CAC_ID__CAC_BLOCK_ID__SHIFT = 0x0 # macro +GC_CAC_ID__CAC_SIGNAL_ID__SHIFT = 0x6 # macro +GC_CAC_ID__CAC_BLOCK_ID_MASK = 0x0000003F # macro +GC_CAC_ID__CAC_SIGNAL_ID_MASK = 0x00003FC0 # macro +GC_CAC_CNTL__CAC_THRESHOLD__SHIFT = 0x0 # macro +GC_CAC_CNTL__CAC_THRESHOLD_MASK = 0x0000FFFF # macro +GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GDS4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GDS4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE5__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE5__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE6__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE6__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE7__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE7__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE8__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE8__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE9__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE9__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE10__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE10__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE11__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE11__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE12__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE12__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE13__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE13__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE14__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE14__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE15__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE15__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE16__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE16__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE17__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE17__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE18__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE18__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE19__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE19__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GE20__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GE20__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH5__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH5__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH6__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH6__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_PH7__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_PH7__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_CHC0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_CHC0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_CHC1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_CHC1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_CHC2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_CHC2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +GC_CAC_ACC_RLC0__ACCUMULATOR_31_0__SHIFT = 0x0 # macro +GC_CAC_ACC_RLC0__ACCUMULATOR_31_0_MASK = 0xFFFFFFFF # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT = 0x0 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT = 0x4 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT = 0x8 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT = 0xc # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT = 0x10 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT = 0x14 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT = 0x18 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT = 0x1c # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK = 0x00000007 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK = 0x00000070 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK = 0x00000700 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK = 0x00007000 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK = 0x00070000 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK = 0x00700000 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK = 0x07000000 # macro +RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK = 0x70000000 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT = 0x0 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT = 0x4 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT = 0x8 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT = 0xc # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT = 0x10 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT = 0x14 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT = 0x18 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT = 0x1c # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK = 0x00000007 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK = 0x00000070 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK = 0x00000700 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK = 0x00007000 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK = 0x00070000 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK = 0x00700000 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK = 0x07000000 # macro +RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK = 0x70000000 # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT = 0x0 # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT = 0x4 # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT = 0x8 # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT = 0xc # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK = 0x00000007 # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK = 0x00000070 # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK = 0x00000700 # macro +RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK = 0x00007000 # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT = 0x0 # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT = 0x8 # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT = 0x10 # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT = 0x18 # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK = 0x0000001F # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK = 0x00001F00 # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK = 0x001F0000 # macro +STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK = 0x1F000000 # macro +STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT = 0x0 # macro +STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT = 0x8 # macro +STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT = 0x10 # macro +STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK = 0x0000001F # macro +STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK = 0x00001F00 # macro +STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK = 0x001F0000 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT = 0x0 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT = 0x8 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT = 0x10 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT = 0x18 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK = 0x00000007 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK = 0x00000700 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK = 0x00070000 # macro +STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK = 0x07000000 # macro +STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT = 0x0 # macro +STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT = 0x8 # macro +STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT = 0x10 # macro +STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK = 0x00000007 # macro +STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK = 0x00000700 # macro +STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK = 0x00070000 # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT = 0x0 # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT = 0x8 # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT = 0x10 # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT = 0x18 # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK = 0x0000001F # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK = 0x00001F00 # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK = 0x001F0000 # macro +PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK = 0x1F000000 # macro +PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT = 0x0 # macro +PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT = 0x8 # macro +PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT = 0x10 # macro +PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK = 0x0000001F # macro +PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK = 0x00001F00 # macro +PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK = 0x001F0000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT = 0x0 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT = 0x4 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT = 0x8 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT = 0xc # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT = 0x10 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT = 0x14 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT = 0x18 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT = 0x1c # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK = 0x00000007 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK = 0x00000070 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK = 0x00000700 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK = 0x00007000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK = 0x00070000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK = 0x00700000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK = 0x07000000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK = 0x70000000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT = 0x0 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT = 0x4 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT = 0x8 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT = 0xc # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT = 0x10 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT = 0x14 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT = 0x18 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT = 0x1c # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK = 0x00000007 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK = 0x00000070 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK = 0x00000700 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK = 0x00007000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK = 0x00070000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK = 0x00700000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK = 0x07000000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK = 0x70000000 # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT = 0x0 # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT = 0x4 # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT = 0x8 # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT = 0xc # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK = 0x00000007 # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK = 0x00000070 # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK = 0x00000700 # macro +PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK = 0x00007000 # macro +FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK = 0x0001FFFF # macro +FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT = 0x0 # macro +FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK = 0x0001FFFF # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT = 0x0 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT = 0x1 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT = 0x2 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT = 0x5 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT = 0x6 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT = 0x7 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT = 0xa # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT = 0xb # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT = 0xc # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT = 0x11 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT = 0x12 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT = 0x13 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT = 0x16 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT = 0x17 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT = 0x18 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK = 0x00000001 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK = 0x00000002 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK = 0x0000001C # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK = 0x00000020 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK = 0x00000040 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK = 0x00000380 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK = 0x00000400 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK = 0x00000800 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK = 0x0001F000 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK = 0x00020000 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK = 0x00040000 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK = 0x00380000 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK = 0x00400000 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK = 0x00800000 # macro +HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK = 0x1F000000 # macro +SE_CAC_ID__CAC_BLOCK_ID__SHIFT = 0x0 # macro +SE_CAC_ID__CAC_SIGNAL_ID__SHIFT = 0x6 # macro +SE_CAC_ID__CAC_BLOCK_ID_MASK = 0x0000003F # macro +SE_CAC_ID__CAC_SIGNAL_ID_MASK = 0x00003FC0 # macro +SE_CAC_CNTL__CAC_THRESHOLD__SHIFT = 0x0 # macro +SE_CAC_CNTL__CAC_THRESHOLD_MASK = 0x0000FFFF # macro +RTAVFS_REG0__RTAVFSZONE0STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG0__RTAVFSZONE0STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG0__RTAVFSZONE0STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG0__RTAVFSZONE0STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG1__RTAVFSZONE1STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG1__RTAVFSZONE1STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG1__RTAVFSZONE1STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG1__RTAVFSZONE1STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG2__RTAVFSZONE2STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG2__RTAVFSZONE2STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG2__RTAVFSZONE2STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG2__RTAVFSZONE2STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG3__RTAVFSZONE3STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG3__RTAVFSZONE3STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG3__RTAVFSZONE3STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG3__RTAVFSZONE3STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG4__RTAVFSZONE4STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG4__RTAVFSZONE4STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG4__RTAVFSZONE4STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG4__RTAVFSZONE4STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG5__RTAVFSZONE0EN0__SHIFT = 0x0 # macro +RTAVFS_REG5__RTAVFSZONE0EN0_MASK = 0xFFFFFFFF # macro +RTAVFS_REG6__RTAVFSZONE0EN1__SHIFT = 0x0 # macro +RTAVFS_REG6__RTAVFSZONE0EN1_MASK = 0xFFFFFFFF # macro +RTAVFS_REG7__RTAVFSZONE1EN0__SHIFT = 0x0 # macro +RTAVFS_REG7__RTAVFSZONE1EN0_MASK = 0xFFFFFFFF # macro +RTAVFS_REG8__RTAVFSZONE1EN1__SHIFT = 0x0 # macro +RTAVFS_REG8__RTAVFSZONE1EN1_MASK = 0xFFFFFFFF # macro +RTAVFS_REG9__RTAVFSZONE2EN0__SHIFT = 0x0 # macro +RTAVFS_REG9__RTAVFSZONE2EN0_MASK = 0xFFFFFFFF # macro +RTAVFS_REG10__RTAVFSZONE2EN1__SHIFT = 0x0 # macro +RTAVFS_REG10__RTAVFSZONE2EN1_MASK = 0xFFFFFFFF # macro +RTAVFS_REG11__RTAVFSZONE3EN0__SHIFT = 0x0 # macro +RTAVFS_REG11__RTAVFSZONE3EN0_MASK = 0xFFFFFFFF # macro +RTAVFS_REG12__RTAVFSZONE3EN1__SHIFT = 0x0 # macro +RTAVFS_REG12__RTAVFSZONE3EN1_MASK = 0xFFFFFFFF # macro +RTAVFS_REG13__RTAVFSZONE4EN0__SHIFT = 0x0 # macro +RTAVFS_REG13__RTAVFSZONE4EN0_MASK = 0xFFFFFFFF # macro +RTAVFS_REG14__RTAVFSZONE4EN1__SHIFT = 0x0 # macro +RTAVFS_REG14__RTAVFSZONE4EN1_MASK = 0xFFFFFFFF # macro +RTAVFS_REG15__RTAVFSVF0FREQCOUNT__SHIFT = 0x0 # macro +RTAVFS_REG15__RTAVFSVF0VOLTCODE__SHIFT = 0x10 # macro +RTAVFS_REG15__RTAVFSVF0FREQCOUNT_MASK = 0x0000FFFF # macro +RTAVFS_REG15__RTAVFSVF0VOLTCODE_MASK = 0xFFFF0000 # macro +RTAVFS_REG16__RTAVFSVF1FREQCOUNT__SHIFT = 0x0 # macro +RTAVFS_REG16__RTAVFSVF1VOLTCODE__SHIFT = 0x10 # macro +RTAVFS_REG16__RTAVFSVF1FREQCOUNT_MASK = 0x0000FFFF # macro +RTAVFS_REG16__RTAVFSVF1VOLTCODE_MASK = 0xFFFF0000 # macro +RTAVFS_REG17__RTAVFSVF2FREQCOUNT__SHIFT = 0x0 # macro +RTAVFS_REG17__RTAVFSVF2VOLTCODE__SHIFT = 0x10 # macro +RTAVFS_REG17__RTAVFSVF2FREQCOUNT_MASK = 0x0000FFFF # macro +RTAVFS_REG17__RTAVFSVF2VOLTCODE_MASK = 0xFFFF0000 # macro +RTAVFS_REG18__RTAVFSVF3FREQCOUNT__SHIFT = 0x0 # macro +RTAVFS_REG18__RTAVFSVF3VOLTCODE__SHIFT = 0x10 # macro +RTAVFS_REG18__RTAVFSVF3FREQCOUNT_MASK = 0x0000FFFF # macro +RTAVFS_REG18__RTAVFSVF3VOLTCODE_MASK = 0xFFFF0000 # macro +RTAVFS_REG19__RTAVFSGB_ZONE0__SHIFT = 0x0 # macro +RTAVFS_REG19__RTAVFSGB_ZONE1__SHIFT = 0x6 # macro +RTAVFS_REG19__RTAVFSGB_ZONE2__SHIFT = 0xc # macro +RTAVFS_REG19__RTAVFSGB_ZONE3__SHIFT = 0x12 # macro +RTAVFS_REG19__RTAVFSGB_ZONE4__SHIFT = 0x19 # macro +RTAVFS_REG19__RTAVFSGB_ZONE0_MASK = 0x0000003F # macro +RTAVFS_REG19__RTAVFSGB_ZONE1_MASK = 0x00000FC0 # macro +RTAVFS_REG19__RTAVFSGB_ZONE2_MASK = 0x0003F000 # macro +RTAVFS_REG19__RTAVFSGB_ZONE3_MASK = 0x01FC0000 # macro +RTAVFS_REG19__RTAVFSGB_ZONE4_MASK = 0xFE000000 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0__SHIFT = 0x0 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1__SHIFT = 0x2 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2__SHIFT = 0x4 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3__SHIFT = 0x6 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4__SHIFT = 0x8 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5__SHIFT = 0xa # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6__SHIFT = 0xc # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7__SHIFT = 0xe # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL__SHIFT = 0x10 # macro +RTAVFS_REG20__RTAVFSZONE0RESERVED__SHIFT = 0x12 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0_MASK = 0x00000003 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1_MASK = 0x0000000C # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2_MASK = 0x00000030 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3_MASK = 0x000000C0 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4_MASK = 0x00000300 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK = 0x00000C00 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6_MASK = 0x00003000 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7_MASK = 0x0000C000 # macro +RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL_MASK = 0x00030000 # macro +RTAVFS_REG20__RTAVFSZONE0RESERVED_MASK = 0xFFFC0000 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0__SHIFT = 0x0 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1__SHIFT = 0x2 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2__SHIFT = 0x4 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3__SHIFT = 0x6 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4__SHIFT = 0x8 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5__SHIFT = 0xa # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6__SHIFT = 0xc # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7__SHIFT = 0xe # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL__SHIFT = 0x10 # macro +RTAVFS_REG21__RTAVFSZONE1RESERVED__SHIFT = 0x12 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0_MASK = 0x00000003 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1_MASK = 0x0000000C # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2_MASK = 0x00000030 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3_MASK = 0x000000C0 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4_MASK = 0x00000300 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5_MASK = 0x00000C00 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6_MASK = 0x00003000 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7_MASK = 0x0000C000 # macro +RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL_MASK = 0x00030000 # macro +RTAVFS_REG21__RTAVFSZONE1RESERVED_MASK = 0xFFFC0000 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0__SHIFT = 0x0 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1__SHIFT = 0x2 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2__SHIFT = 0x4 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3__SHIFT = 0x6 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4__SHIFT = 0x8 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5__SHIFT = 0xa # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6__SHIFT = 0xc # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7__SHIFT = 0xe # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL__SHIFT = 0x10 # macro +RTAVFS_REG22__RTAVFSZONE2RESERVED__SHIFT = 0x12 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0_MASK = 0x00000003 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1_MASK = 0x0000000C # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2_MASK = 0x00000030 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3_MASK = 0x000000C0 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4_MASK = 0x00000300 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5_MASK = 0x00000C00 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6_MASK = 0x00003000 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7_MASK = 0x0000C000 # macro +RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL_MASK = 0x00030000 # macro +RTAVFS_REG22__RTAVFSZONE2RESERVED_MASK = 0xFFFC0000 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0__SHIFT = 0x0 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1__SHIFT = 0x2 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2__SHIFT = 0x4 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3__SHIFT = 0x6 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4__SHIFT = 0x8 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5__SHIFT = 0xa # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6__SHIFT = 0xc # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7__SHIFT = 0xe # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL__SHIFT = 0x10 # macro +RTAVFS_REG23__RTAVFSZONE3RESERVED__SHIFT = 0x12 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0_MASK = 0x00000003 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1_MASK = 0x0000000C # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2_MASK = 0x00000030 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3_MASK = 0x000000C0 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4_MASK = 0x00000300 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5_MASK = 0x00000C00 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6_MASK = 0x00003000 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7_MASK = 0x0000C000 # macro +RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL_MASK = 0x00030000 # macro +RTAVFS_REG23__RTAVFSZONE3RESERVED_MASK = 0xFFFC0000 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0__SHIFT = 0x0 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1__SHIFT = 0x2 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2__SHIFT = 0x4 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3__SHIFT = 0x6 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4__SHIFT = 0x8 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT = 0xa # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6__SHIFT = 0xc # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7__SHIFT = 0xe # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL__SHIFT = 0x10 # macro +RTAVFS_REG24__RTAVFSZONE4RESERVED__SHIFT = 0x12 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0_MASK = 0x00000003 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1_MASK = 0x0000000C # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2_MASK = 0x00000030 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3_MASK = 0x000000C0 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4_MASK = 0x00000300 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5_MASK = 0x00000C00 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6_MASK = 0x00003000 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7_MASK = 0x0000C000 # macro +RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL_MASK = 0x00030000 # macro +RTAVFS_REG24__RTAVFSZONE4RESERVED_MASK = 0xFFFC0000 # macro +RTAVFS_REG25__RTAVFSRESERVED0__SHIFT = 0x0 # macro +RTAVFS_REG25__RTAVFSRESERVED0_MASK = 0xFFFFFFFF # macro +RTAVFS_REG26__RTAVFSRESERVED1__SHIFT = 0x0 # macro +RTAVFS_REG26__RTAVFSRESERVED1_MASK = 0xFFFFFFFF # macro +RTAVFS_REG27__RTAVFSRESERVED2__SHIFT = 0x0 # macro +RTAVFS_REG27__RTAVFSRESERVED2_MASK = 0xFFFFFFFF # macro +RTAVFS_REG28__RTAVFSZONE0INTERCEPT__SHIFT = 0x0 # macro +RTAVFS_REG28__RTAVFSZONE1INTERCEPT__SHIFT = 0x10 # macro +RTAVFS_REG28__RTAVFSZONE0INTERCEPT_MASK = 0x0000FFFF # macro +RTAVFS_REG28__RTAVFSZONE1INTERCEPT_MASK = 0xFFFF0000 # macro +RTAVFS_REG29__RTAVFSZONE2INTERCEPT__SHIFT = 0x0 # macro +RTAVFS_REG29__RTAVFSZONE3INTERCEPT__SHIFT = 0x10 # macro +RTAVFS_REG29__RTAVFSZONE2INTERCEPT_MASK = 0x0000FFFF # macro +RTAVFS_REG29__RTAVFSZONE3INTERCEPT_MASK = 0xFFFF0000 # macro +RTAVFS_REG30__RTAVFSZONE4INTERCEPT__SHIFT = 0x0 # macro +RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT__SHIFT = 0x10 # macro +RTAVFS_REG30__RTAVFSZONE4INTERCEPT_MASK = 0x0000FFFF # macro +RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT_MASK = 0xFFFF0000 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV0__SHIFT = 0x0 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV1__SHIFT = 0x2 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV2__SHIFT = 0x4 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV3__SHIFT = 0x6 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV4__SHIFT = 0x8 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV5__SHIFT = 0xa # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV6__SHIFT = 0xc # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV7__SHIFT = 0xe # macro +RTAVFS_REG31__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV0_MASK = 0x00000003 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV1_MASK = 0x0000000C # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV2_MASK = 0x00000030 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV3_MASK = 0x000000C0 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV4_MASK = 0x00000300 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV5_MASK = 0x00000C00 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV6_MASK = 0x00003000 # macro +RTAVFS_REG31__RTAVFSCPOCLKDIV7_MASK = 0x0000C000 # macro +RTAVFS_REG31__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG32__RTAVFSFSMSTARTUPCNT__SHIFT = 0x0 # macro +RTAVFS_REG32__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG32__RTAVFSFSMSTARTUPCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG32__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG33__RTAVFSFSMIDLECNT__SHIFT = 0x0 # macro +RTAVFS_REG33__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG33__RTAVFSFSMIDLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG33__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT__SHIFT = 0x0 # macro +RTAVFS_REG34__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG34__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT__SHIFT = 0x0 # macro +RTAVFS_REG35__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG35__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT__SHIFT = 0x0 # macro +RTAVFS_REG36__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG36__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT__SHIFT = 0x0 # macro +RTAVFS_REG37__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG37__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT__SHIFT = 0x0 # macro +RTAVFS_REG38__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG38__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT__SHIFT = 0x0 # macro +RTAVFS_REG39__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG39__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT__SHIFT = 0x0 # macro +RTAVFS_REG40__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG40__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT__SHIFT = 0x0 # macro +RTAVFS_REG41__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG41__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT__SHIFT = 0x0 # macro +RTAVFS_REG42__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG42__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG43__RTAVFSKP0__SHIFT = 0x0 # macro +RTAVFS_REG43__RTAVFSKP1__SHIFT = 0x4 # macro +RTAVFS_REG43__RTAVFSKP2__SHIFT = 0x8 # macro +RTAVFS_REG43__RTAVFSKP3__SHIFT = 0xc # macro +RTAVFS_REG43__RTAVFSKI0__SHIFT = 0x10 # macro +RTAVFS_REG43__RTAVFSKI1__SHIFT = 0x14 # macro +RTAVFS_REG43__RTAVFSKI2__SHIFT = 0x18 # macro +RTAVFS_REG43__RTAVFSKI3__SHIFT = 0x1c # macro +RTAVFS_REG43__RTAVFSKP0_MASK = 0x0000000F # macro +RTAVFS_REG43__RTAVFSKP1_MASK = 0x000000F0 # macro +RTAVFS_REG43__RTAVFSKP2_MASK = 0x00000F00 # macro +RTAVFS_REG43__RTAVFSKP3_MASK = 0x0000F000 # macro +RTAVFS_REG43__RTAVFSKI0_MASK = 0x000F0000 # macro +RTAVFS_REG43__RTAVFSKI1_MASK = 0x00F00000 # macro +RTAVFS_REG43__RTAVFSKI2_MASK = 0x0F000000 # macro +RTAVFS_REG43__RTAVFSKI3_MASK = 0xF0000000 # macro +RTAVFS_REG44__RTAVFSV1__SHIFT = 0x0 # macro +RTAVFS_REG44__RTAVFSV2__SHIFT = 0xa # macro +RTAVFS_REG44__RTAVFSV3__SHIFT = 0x14 # macro +RTAVFS_REG44__RTAVFSUSEBINARYSEARCH__SHIFT = 0x1e # macro +RTAVFS_REG44__RTAVFSVOLTCODEHWCAL__SHIFT = 0x1f # macro +RTAVFS_REG44__RTAVFSV1_MASK = 0x000003FF # macro +RTAVFS_REG44__RTAVFSV2_MASK = 0x000FFC00 # macro +RTAVFS_REG44__RTAVFSV3_MASK = 0x3FF00000 # macro +RTAVFS_REG44__RTAVFSUSEBINARYSEARCH_MASK = 0x40000000 # macro +RTAVFS_REG44__RTAVFSVOLTCODEHWCAL_MASK = 0x80000000 # macro +RTAVFS_REG45__RTAVFSVRBLEEDCNTRL__SHIFT = 0x0 # macro +RTAVFS_REG45__RTAVFSVRENABLE__SHIFT = 0x1 # macro +RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE__SHIFT = 0x2 # macro +RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL__SHIFT = 0xc # macro +RTAVFS_REG45__RTAVFSLOWPWREN__SHIFT = 0xd # macro +RTAVFS_REG45__RTAVFSUREGENABLE__SHIFT = 0xe # macro +RTAVFS_REG45__RTAVFSBGENABLE__SHIFT = 0xf # macro +RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING__SHIFT = 0x10 # macro +RTAVFS_REG45__RESERVED__SHIFT = 0x11 # macro +RTAVFS_REG45__RTAVFSVRBLEEDCNTRL_MASK = 0x00000001 # macro +RTAVFS_REG45__RTAVFSVRENABLE_MASK = 0x00000002 # macro +RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE_MASK = 0x00000FFC # macro +RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL_MASK = 0x00001000 # macro +RTAVFS_REG45__RTAVFSLOWPWREN_MASK = 0x00002000 # macro +RTAVFS_REG45__RTAVFSUREGENABLE_MASK = 0x00004000 # macro +RTAVFS_REG45__RTAVFSBGENABLE_MASK = 0x00008000 # macro +RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING_MASK = 0x00010000 # macro +RTAVFS_REG45__RESERVED_MASK = 0xFFFE0000 # macro +RTAVFS_REG46__RTAVFSKP__SHIFT = 0x0 # macro +RTAVFS_REG46__RTAVFSKI__SHIFT = 0x4 # macro +RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP__SHIFT = 0x8 # macro +RTAVFS_REG46__RTAVFSPISHIFT__SHIFT = 0x9 # macro +RTAVFS_REG46__RTAVFSPIERREN__SHIFT = 0xd # macro +RTAVFS_REG46__RTAVFSPISHIFTOUT__SHIFT = 0xe # macro +RTAVFS_REG46__RTAVFSUSELUTKPKI__SHIFT = 0x12 # macro +RTAVFS_REG46__RESERVED__SHIFT = 0x13 # macro +RTAVFS_REG46__RTAVFSKP_MASK = 0x0000000F # macro +RTAVFS_REG46__RTAVFSKI_MASK = 0x000000F0 # macro +RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP_MASK = 0x00000100 # macro +RTAVFS_REG46__RTAVFSPISHIFT_MASK = 0x00001E00 # macro +RTAVFS_REG46__RTAVFSPIERREN_MASK = 0x00002000 # macro +RTAVFS_REG46__RTAVFSPISHIFTOUT_MASK = 0x0003C000 # macro +RTAVFS_REG46__RTAVFSUSELUTKPKI_MASK = 0x00040000 # macro +RTAVFS_REG46__RESERVED_MASK = 0xFFF80000 # macro +RTAVFS_REG47__RTAVFSVOLTCODEPIMIN__SHIFT = 0x0 # macro +RTAVFS_REG47__RTAVFSVOLTCODEPIMAX__SHIFT = 0xa # macro +RTAVFS_REG47__RTAVFSPIERRMASK__SHIFT = 0x14 # macro +RTAVFS_REG47__RTAVFSFORCEDISABLEPI__SHIFT = 0x1b # macro +RTAVFS_REG47__RESERVED__SHIFT = 0x1c # macro +RTAVFS_REG47__RTAVFSVOLTCODEPIMIN_MASK = 0x000003FF # macro +RTAVFS_REG47__RTAVFSVOLTCODEPIMAX_MASK = 0x000FFC00 # macro +RTAVFS_REG47__RTAVFSPIERRMASK_MASK = 0x07F00000 # macro +RTAVFS_REG47__RTAVFSFORCEDISABLEPI_MASK = 0x08000000 # macro +RTAVFS_REG47__RESERVED_MASK = 0xF0000000 # macro +RTAVFS_REG48__RTAVFSPILOOPNITERATIONS__SHIFT = 0x0 # macro +RTAVFS_REG48__RTAVFSPIERRTHRESHOLD__SHIFT = 0x10 # macro +RTAVFS_REG48__RTAVFSPILOOPNITERATIONS_MASK = 0x0000FFFF # macro +RTAVFS_REG48__RTAVFSPIERRTHRESHOLD_MASK = 0xFFFF0000 # macro +RTAVFS_REG49__RTAVFSPSMRSTAVGVDD__SHIFT = 0x0 # macro +RTAVFS_REG49__RTAVFSPSMMEASMAXVDD__SHIFT = 0x1 # macro +RTAVFS_REG49__RTAVFSPSMCLKDIVVDD__SHIFT = 0x2 # macro +RTAVFS_REG49__RTAVFSPSMAVGDIVVDD__SHIFT = 0x4 # macro +RTAVFS_REG49__RTAVFSPSMOSCENVDD__SHIFT = 0xa # macro +RTAVFS_REG49__RTAVFSPSMAVGENVDD__SHIFT = 0xb # macro +RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD__SHIFT = 0xc # macro +RTAVFS_REG49__RESERVED__SHIFT = 0xd # macro +RTAVFS_REG49__RTAVFSPSMRSTAVGVDD_MASK = 0x00000001 # macro +RTAVFS_REG49__RTAVFSPSMMEASMAXVDD_MASK = 0x00000002 # macro +RTAVFS_REG49__RTAVFSPSMCLKDIVVDD_MASK = 0x0000000C # macro +RTAVFS_REG49__RTAVFSPSMAVGDIVVDD_MASK = 0x000003F0 # macro +RTAVFS_REG49__RTAVFSPSMOSCENVDD_MASK = 0x00000400 # macro +RTAVFS_REG49__RTAVFSPSMAVGENVDD_MASK = 0x00000800 # macro +RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD_MASK = 0x00001000 # macro +RTAVFS_REG49__RESERVED_MASK = 0xFFFFE000 # macro +RTAVFS_REG50__RTAVFSPSMRSTAVGVREG__SHIFT = 0x0 # macro +RTAVFS_REG50__RTAVFSPSMMEASMAXVREG__SHIFT = 0x1 # macro +RTAVFS_REG50__RTAVFSPSMCLKDIVVREG__SHIFT = 0x2 # macro +RTAVFS_REG50__RTAVFSPSMAVGDIVVREG__SHIFT = 0x4 # macro +RTAVFS_REG50__RTAVFSPSMOSCENVREG__SHIFT = 0xa # macro +RTAVFS_REG50__RTAVFSPSMAVGENVREG__SHIFT = 0xb # macro +RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG__SHIFT = 0xc # macro +RTAVFS_REG50__RESERVED__SHIFT = 0xd # macro +RTAVFS_REG50__RTAVFSPSMRSTAVGVREG_MASK = 0x00000001 # macro +RTAVFS_REG50__RTAVFSPSMMEASMAXVREG_MASK = 0x00000002 # macro +RTAVFS_REG50__RTAVFSPSMCLKDIVVREG_MASK = 0x0000000C # macro +RTAVFS_REG50__RTAVFSPSMAVGDIVVREG_MASK = 0x000003F0 # macro +RTAVFS_REG50__RTAVFSPSMOSCENVREG_MASK = 0x00000400 # macro +RTAVFS_REG50__RTAVFSPSMAVGENVREG_MASK = 0x00000800 # macro +RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG_MASK = 0x00001000 # macro +RTAVFS_REG50__RESERVED_MASK = 0xFFFFE000 # macro +RTAVFS_REG51__RTAVFSAVFSENABLE__SHIFT = 0x0 # macro +RTAVFS_REG51__RTAVFSCPOTURNONDELAY__SHIFT = 0x1 # macro +RTAVFS_REG51__RTAVFSSELECTMINMAX__SHIFT = 0x5 # macro +RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING__SHIFT = 0x6 # macro +RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND__SHIFT = 0x7 # macro +RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT__SHIFT = 0x8 # macro +RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES__SHIFT = 0x9 # macro +RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT__SHIFT = 0xa # macro +RTAVFS_REG51__RESERVED__SHIFT = 0xb # macro +RTAVFS_REG51__RTAVFSAVFSENABLE_MASK = 0x00000001 # macro +RTAVFS_REG51__RTAVFSCPOTURNONDELAY_MASK = 0x0000001E # macro +RTAVFS_REG51__RTAVFSSELECTMINMAX_MASK = 0x00000020 # macro +RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING_MASK = 0x00000040 # macro +RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND_MASK = 0x00000080 # macro +RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT_MASK = 0x00000100 # macro +RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES_MASK = 0x00000200 # macro +RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT_MASK = 0x00000400 # macro +RTAVFS_REG51__RESERVED_MASK = 0xFFFFF800 # macro +RTAVFS_REG52__RTAVFSMINMAXPSMVDD__SHIFT = 0x0 # macro +RTAVFS_REG52__RTAVFSAVGPSMVDD__SHIFT = 0xe # macro +RTAVFS_REG52__RESERVED__SHIFT = 0x1c # macro +RTAVFS_REG52__RTAVFSMINMAXPSMVDD_MASK = 0x00003FFF # macro +RTAVFS_REG52__RTAVFSAVGPSMVDD_MASK = 0x0FFFC000 # macro +RTAVFS_REG52__RESERVED_MASK = 0xF0000000 # macro +RTAVFS_REG53__RTAVFSMINMAXPSMVREG__SHIFT = 0x0 # macro +RTAVFS_REG53__RTAVFSAVGPSMVREG__SHIFT = 0xe # macro +RTAVFS_REG53__RESERVED__SHIFT = 0x1c # macro +RTAVFS_REG53__RTAVFSMINMAXPSMVREG_MASK = 0x00003FFF # macro +RTAVFS_REG53__RTAVFSAVGPSMVREG_MASK = 0x0FFFC000 # macro +RTAVFS_REG53__RESERVED_MASK = 0xF0000000 # macro +RTAVFS_REG54__RTAVFSCPO0_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG54__RTAVFSCPO0_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG54__RTAVFSCPO0_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG54__RTAVFSCPO0_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG55__RTAVFSCPO1_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG55__RTAVFSCPO1_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG55__RTAVFSCPO1_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG55__RTAVFSCPO1_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG56__RTAVFSCPO2_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG56__RTAVFSCPO2_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG56__RTAVFSCPO2_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG56__RTAVFSCPO2_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG57__RTAVFSCPO3_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG57__RTAVFSCPO3_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG57__RTAVFSCPO3_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG57__RTAVFSCPO3_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG58__RTAVFSCPO4_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG58__RTAVFSCPO4_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG58__RTAVFSCPO4_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG58__RTAVFSCPO4_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG59__RTAVFSCPO5_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG59__RTAVFSCPO5_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG59__RTAVFSCPO5_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG59__RTAVFSCPO5_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG60__RTAVFSCPO6_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG60__RTAVFSCPO6_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG60__RTAVFSCPO6_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG60__RTAVFSCPO6_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG61__RTAVFSCPO7_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG61__RTAVFSCPO7_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG61__RTAVFSCPO7_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG61__RTAVFSCPO7_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG62__RTAVFSCPO8_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG62__RTAVFSCPO8_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG62__RTAVFSCPO8_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG62__RTAVFSCPO8_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG63__RTAVFSCPO9_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG63__RTAVFSCPO9_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG63__RTAVFSCPO9_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG63__RTAVFSCPO9_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG64__RTAVFSCPO10_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG64__RTAVFSCPO10_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG64__RTAVFSCPO10_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG64__RTAVFSCPO10_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG65__RTAVFSCPO11_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG65__RTAVFSCPO11_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG65__RTAVFSCPO11_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG65__RTAVFSCPO11_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG66__RTAVFSCPO12_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG66__RTAVFSCPO12_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG66__RTAVFSCPO12_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG66__RTAVFSCPO12_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG67__RTAVFSCPO13_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG67__RTAVFSCPO13_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG67__RTAVFSCPO13_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG67__RTAVFSCPO13_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG68__RTAVFSCPO14_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG68__RTAVFSCPO14_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG68__RTAVFSCPO14_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG68__RTAVFSCPO14_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG69__RTAVFSCPO15_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG69__RTAVFSCPO15_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG69__RTAVFSCPO15_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG69__RTAVFSCPO15_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG70__RTAVFSCPO16_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG70__RTAVFSCPO16_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG70__RTAVFSCPO16_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG70__RTAVFSCPO16_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG71__RTAVFSCPO17_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG71__RTAVFSCPO17_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG71__RTAVFSCPO17_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG71__RTAVFSCPO17_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG72__RTAVFSCPO18_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG72__RTAVFSCPO18_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG72__RTAVFSCPO18_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG72__RTAVFSCPO18_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG73__RTAVFSCPO19_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG73__RTAVFSCPO19_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG73__RTAVFSCPO19_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG73__RTAVFSCPO19_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG74__RTAVFSCPO20_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG74__RTAVFSCPO20_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG74__RTAVFSCPO20_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG74__RTAVFSCPO20_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG75__RTAVFSCPO21_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG75__RTAVFSCPO21_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG75__RTAVFSCPO21_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG75__RTAVFSCPO21_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG76__RTAVFSCPO22_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG76__RTAVFSCPO22_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG76__RTAVFSCPO22_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG76__RTAVFSCPO22_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG77__RTAVFSCPO23_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG77__RTAVFSCPO23_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG77__RTAVFSCPO23_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG77__RTAVFSCPO23_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG78__RTAVFSCPO24_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG78__RTAVFSCPO24_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG78__RTAVFSCPO24_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG78__RTAVFSCPO24_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG79__RTAVFSCPO25_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG79__RTAVFSCPO25_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG79__RTAVFSCPO25_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG79__RTAVFSCPO25_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG80__RTAVFSCPO26_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG80__RTAVFSCPO26_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG80__RTAVFSCPO26_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG80__RTAVFSCPO26_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG81__RTAVFSCPO27_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG81__RTAVFSCPO27_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG81__RTAVFSCPO27_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG81__RTAVFSCPO27_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG82__RTAVFSCPO28_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG82__RTAVFSCPO28_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG82__RTAVFSCPO28_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG82__RTAVFSCPO28_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG83__RTAVFSCPO29_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG83__RTAVFSCPO29_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG83__RTAVFSCPO29_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG83__RTAVFSCPO29_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG84__RTAVFSCPO30_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG84__RTAVFSCPO30_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG84__RTAVFSCPO30_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG84__RTAVFSCPO30_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG85__RTAVFSCPO31_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG85__RTAVFSCPO31_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG85__RTAVFSCPO31_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG85__RTAVFSCPO31_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG86__RTAVFSCPO32_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG86__RTAVFSCPO32_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG86__RTAVFSCPO32_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG86__RTAVFSCPO32_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG87__RTAVFSCPO33_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG87__RTAVFSCPO33_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG87__RTAVFSCPO33_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG87__RTAVFSCPO33_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG88__RTAVFSCPO34_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG88__RTAVFSCPO34_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG88__RTAVFSCPO34_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG88__RTAVFSCPO34_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG89__RTAVFSCPO35_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG89__RTAVFSCPO35_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG89__RTAVFSCPO35_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG89__RTAVFSCPO35_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG90__RTAVFSCPO36_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG90__RTAVFSCPO36_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG90__RTAVFSCPO36_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG90__RTAVFSCPO36_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG91__RTAVFSCPO37_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG91__RTAVFSCPO37_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG91__RTAVFSCPO37_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG91__RTAVFSCPO37_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG92__RTAVFSCPO38_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG92__RTAVFSCPO38_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG92__RTAVFSCPO38_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG92__RTAVFSCPO38_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG93__RTAVFSCPO39_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG93__RTAVFSCPO39_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG93__RTAVFSCPO39_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG93__RTAVFSCPO39_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG94__RTAVFSCPO40_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG94__RTAVFSCPO40_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG94__RTAVFSCPO40_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG94__RTAVFSCPO40_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG95__RTAVFSCPO41_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG95__RTAVFSCPO41_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG95__RTAVFSCPO41_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG95__RTAVFSCPO41_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG96__RTAVFSCPO42_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG96__RTAVFSCPO42_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG96__RTAVFSCPO42_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG96__RTAVFSCPO42_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG97__RTAVFSCPO43_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG97__RTAVFSCPO43_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG97__RTAVFSCPO43_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG97__RTAVFSCPO43_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG98__RTAVFSCPO44_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG98__RTAVFSCPO44_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG98__RTAVFSCPO44_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG98__RTAVFSCPO44_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG99__RTAVFSCPO45_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG99__RTAVFSCPO45_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG99__RTAVFSCPO45_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG99__RTAVFSCPO45_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG100__RTAVFSCPO46_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG100__RTAVFSCPO46_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG100__RTAVFSCPO46_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG100__RTAVFSCPO46_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG101__RTAVFSCPO47_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG101__RTAVFSCPO47_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG101__RTAVFSCPO47_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG101__RTAVFSCPO47_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG102__RTAVFSCPO48_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG102__RTAVFSCPO48_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG102__RTAVFSCPO48_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG102__RTAVFSCPO48_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG103__RTAVFSCPO49_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG103__RTAVFSCPO49_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG103__RTAVFSCPO49_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG103__RTAVFSCPO49_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG104__RTAVFSCPO50_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG104__RTAVFSCPO50_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG104__RTAVFSCPO50_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG104__RTAVFSCPO50_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG105__RTAVFSCPO51_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG105__RTAVFSCPO51_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG105__RTAVFSCPO51_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG105__RTAVFSCPO51_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG106__RTAVFSCPO52_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG106__RTAVFSCPO52_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG106__RTAVFSCPO52_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG106__RTAVFSCPO52_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG107__RTAVFSCPO53_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG107__RTAVFSCPO53_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG107__RTAVFSCPO53_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG107__RTAVFSCPO53_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG108__RTAVFSCPO54_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG108__RTAVFSCPO54_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG108__RTAVFSCPO54_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG108__RTAVFSCPO54_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG109__RTAVFSCPO55_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG109__RTAVFSCPO55_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG109__RTAVFSCPO55_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG109__RTAVFSCPO55_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG110__RTAVFSCPO56_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG110__RTAVFSCPO56_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG110__RTAVFSCPO56_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG110__RTAVFSCPO56_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG111__RTAVFSCPO57_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG111__RTAVFSCPO57_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG111__RTAVFSCPO57_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG111__RTAVFSCPO57_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG112__RTAVFSCPO58_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG112__RTAVFSCPO58_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG112__RTAVFSCPO58_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG112__RTAVFSCPO58_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG113__RTAVFSCPO59_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG113__RTAVFSCPO59_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG113__RTAVFSCPO59_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG113__RTAVFSCPO59_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG114__RTAVFSCPO60_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG114__RTAVFSCPO60_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG114__RTAVFSCPO60_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG114__RTAVFSCPO60_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG115__RTAVFSCPO61_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG115__RTAVFSCPO61_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG115__RTAVFSCPO61_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG115__RTAVFSCPO61_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG116__RTAVFSCPO62_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG116__RTAVFSCPO62_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG116__RTAVFSCPO62_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG116__RTAVFSCPO62_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG117__RTAVFSCPO63_STARTCNT__SHIFT = 0x0 # macro +RTAVFS_REG117__RTAVFSCPO63_STOPCNT__SHIFT = 0x10 # macro +RTAVFS_REG117__RTAVFSCPO63_STARTCNT_MASK = 0x0000FFFF # macro +RTAVFS_REG117__RTAVFSCPO63_STOPCNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG118__RTAVFSCPOEN0__SHIFT = 0x0 # macro +RTAVFS_REG118__RTAVFSCPOEN0_MASK = 0xFFFFFFFF # macro +RTAVFS_REG119__RTAVFSCPOEN1__SHIFT = 0x0 # macro +RTAVFS_REG119__RTAVFSCPOEN1_MASK = 0xFFFFFFFF # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV0__SHIFT = 0x0 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV1__SHIFT = 0x2 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV2__SHIFT = 0x4 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV3__SHIFT = 0x6 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV4__SHIFT = 0x8 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV5__SHIFT = 0xa # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV6__SHIFT = 0xc # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV7__SHIFT = 0xe # macro +RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL__SHIFT = 0x10 # macro +RTAVFS_REG120__RESERVED__SHIFT = 0x12 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV0_MASK = 0x00000003 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV1_MASK = 0x0000000C # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV2_MASK = 0x00000030 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV3_MASK = 0x000000C0 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV4_MASK = 0x00000300 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV5_MASK = 0x00000C00 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV6_MASK = 0x00003000 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIV7_MASK = 0x0000C000 # macro +RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL_MASK = 0x00030000 # macro +RTAVFS_REG120__RESERVED_MASK = 0xFFFC0000 # macro +RTAVFS_REG121__RTAVFSZONE0INUSE__SHIFT = 0x0 # macro +RTAVFS_REG121__RTAVFSZONE1INUSE__SHIFT = 0x1 # macro +RTAVFS_REG121__RTAVFSZONE2INUSE__SHIFT = 0x2 # macro +RTAVFS_REG121__RTAVFSZONE3INUSE__SHIFT = 0x3 # macro +RTAVFS_REG121__RTAVFSZONE4INUSE__SHIFT = 0x4 # macro +RTAVFS_REG121__RTAVFSRESERVED__SHIFT = 0x5 # macro +RTAVFS_REG121__RTAVFSERRORCODE__SHIFT = 0x1c # macro +RTAVFS_REG121__RTAVFSZONE0INUSE_MASK = 0x00000001 # macro +RTAVFS_REG121__RTAVFSZONE1INUSE_MASK = 0x00000002 # macro +RTAVFS_REG121__RTAVFSZONE2INUSE_MASK = 0x00000004 # macro +RTAVFS_REG121__RTAVFSZONE3INUSE_MASK = 0x00000008 # macro +RTAVFS_REG121__RTAVFSZONE4INUSE_MASK = 0x00000010 # macro +RTAVFS_REG121__RTAVFSRESERVED_MASK = 0x0FFFFFE0 # macro +RTAVFS_REG121__RTAVFSERRORCODE_MASK = 0xF0000000 # macro +RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG122__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG122__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG123__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG123__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG124__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG124__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG125__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG125__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG126__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG126__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG127__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG127__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG128__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG128__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG129__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG129__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG130__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG130__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG131__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG131__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG132__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG132__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG133__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG133__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG134__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG134__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG135__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG135__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG136__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG136__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG137__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG137__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG138__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG138__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG139__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG139__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG140__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG140__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG141__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG141__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG142__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG142__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG143__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG143__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG144__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG144__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG145__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG145__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG146__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG146__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG147__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG147__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG148__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG148__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG149__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG149__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG150__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG150__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG151__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG151__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG152__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG152__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG153__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG153__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG154__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG154__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG155__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG155__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG156__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG156__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG157__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG157__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG158__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG158__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG159__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG159__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG160__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG160__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG161__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG161__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG162__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG162__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG163__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG163__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG164__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG164__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG165__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG165__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG166__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG166__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG167__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG167__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG168__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG168__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG169__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG169__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG170__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG170__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG171__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG171__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG172__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG172__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG173__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG173__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG174__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG174__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG175__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG175__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG176__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG176__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG177__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG177__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG178__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG178__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG179__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG179__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG180__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG180__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG181__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG181__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG182__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG182__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG183__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG183__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG184__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG184__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT__SHIFT = 0x0 # macro +RTAVFS_REG185__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT_MASK = 0x0000FFFF # macro +RTAVFS_REG185__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE__SHIFT = 0x0 # macro +RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL__SHIFT = 0x10 # macro +RTAVFS_REG186__RESERVED__SHIFT = 0x11 # macro +RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE_MASK = 0x0000FFFF # macro +RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL_MASK = 0x00010000 # macro +RTAVFS_REG186__RESERVED_MASK = 0xFFFE0000 # macro +RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE__SHIFT = 0x0 # macro +RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL__SHIFT = 0x10 # macro +RTAVFS_REG187__RESERVED__SHIFT = 0x11 # macro +RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE_MASK = 0x0000FFFF # macro +RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL_MASK = 0x00010000 # macro +RTAVFS_REG187__RESERVED_MASK = 0xFFFE0000 # macro +RTAVFS_REG188__RESERVED__SHIFT = 0x16 # macro +RTAVFS_REG188__RESERVED_MASK = 0xFFC00000 # macro +RTAVFS_REG189__RTAVFSVOLTCODEFROMPI__SHIFT = 0x0 # macro +RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH__SHIFT = 0xa # macro +RTAVFS_REG189__RTAVFSVDDREGON__SHIFT = 0x14 # macro +RTAVFS_REG189__RTAVFSVDDABOVEVDDRET__SHIFT = 0x15 # macro +RTAVFS_REG189__RESERVED__SHIFT = 0x16 # macro +RTAVFS_REG189__RTAVFSVOLTCODEFROMPI_MASK = 0x000003FF # macro +RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH_MASK = 0x000FFC00 # macro +RTAVFS_REG189__RTAVFSVDDREGON_MASK = 0x00100000 # macro +RTAVFS_REG189__RTAVFSVDDABOVEVDDRET_MASK = 0x00200000 # macro +RTAVFS_REG189__RESERVED_MASK = 0xFFC00000 # macro +RTAVFS_REG190__RTAVFSIGNORERLCREQ__SHIFT = 0x0 # macro +RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL__SHIFT = 0x1 # macro +RTAVFS_REG190__RTAVFSRUNLOOP__SHIFT = 0x6 # macro +RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS__SHIFT = 0x7 # macro +RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS__SHIFT = 0x8 # macro +RTAVFS_REG190__RTAVFSRESETRETENTIONREGS__SHIFT = 0x9 # macro +RTAVFS_REG190__RESERVED__SHIFT = 0xa # macro +RTAVFS_REG190__RTAVFSIGNORERLCREQ_MASK = 0x00000001 # macro +RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL_MASK = 0x0000003E # macro +RTAVFS_REG190__RTAVFSRUNLOOP_MASK = 0x00000040 # macro +RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS_MASK = 0x00000080 # macro +RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS_MASK = 0x00000100 # macro +RTAVFS_REG190__RTAVFSRESETRETENTIONREGS_MASK = 0x00000200 # macro +RTAVFS_REG190__RESERVED_MASK = 0xFFFFFC00 # macro +RTAVFS_REG191__RTAVFSSTOPATSTARTUP__SHIFT = 0x0 # macro +RTAVFS_REG191__RTAVFSSTOPATIDLE__SHIFT = 0x1 # macro +RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS__SHIFT = 0x2 # macro +RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS__SHIFT = 0x3 # macro +RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS__SHIFT = 0x4 # macro +RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE__SHIFT = 0x5 # macro +RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY__SHIFT = 0x6 # macro +RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY__SHIFT = 0x7 # macro +RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY__SHIFT = 0x8 # macro +RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS__SHIFT = 0x9 # macro +RTAVFS_REG191__RTAVFSSTOPATWAITFORACK__SHIFT = 0xa # macro +RTAVFS_REG191__RESERVED__SHIFT = 0xb # macro +RTAVFS_REG191__RTAVFSSTOPATSTARTUP_MASK = 0x00000001 # macro +RTAVFS_REG191__RTAVFSSTOPATIDLE_MASK = 0x00000002 # macro +RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS_MASK = 0x00000004 # macro +RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS_MASK = 0x00000008 # macro +RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS_MASK = 0x00000010 # macro +RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE_MASK = 0x00000020 # macro +RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY_MASK = 0x00000040 # macro +RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY_MASK = 0x00000080 # macro +RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY_MASK = 0x00000100 # macro +RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS_MASK = 0x00000200 # macro +RTAVFS_REG191__RTAVFSSTOPATWAITFORACK_MASK = 0x00000400 # macro +RTAVFS_REG191__RESERVED_MASK = 0xFFFFF800 # macro +RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT__SHIFT = 0x0 # macro +RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT__SHIFT = 0x10 # macro +RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT_MASK = 0x0000FFFF # macro +RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT_MASK = 0xFFFF0000 # macro +RTAVFS_REG193__RTAVFSFSMSTATE__SHIFT = 0x0 # macro +RTAVFS_REG193__RESERVED__SHIFT = 0x10 # macro +RTAVFS_REG193__RTAVFSFSMSTATE_MASK = 0x0000FFFF # macro +RTAVFS_REG193__RESERVED_MASK = 0xFFFF0000 # macro +RTAVFS_REG194__RTAVFSRIPPLECNTREAD__SHIFT = 0x0 # macro +RTAVFS_REG194__RTAVFSRIPPLECNTREAD_MASK = 0xFFFFFFFF # macro +SQ_DEBUG_STS_LOCAL__BUSY__SHIFT = 0x0 # macro +SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT = 0x4 # macro +SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT = 0xc # macro +SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT = 0xd # macro +SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT = 0xe # macro +SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT = 0xf # macro +SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT = 0x10 # macro +SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT = 0x11 # macro +SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT = 0x12 # macro +SQ_DEBUG_STS_LOCAL__BUSY_MASK = 0x00000001 # macro +SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK = 0x000003F0 # macro +SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK = 0x00001000 # macro +SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK = 0x00002000 # macro +SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK = 0x00004000 # macro +SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK = 0x00008000 # macro +SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK = 0x00010000 # macro +SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK = 0x00020000 # macro +SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK = 0x00040000 # macro +SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT = 0x0 # macro +SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK = 0x000000FF # macro +SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT = 0x0 # macro +SQ_WAVE_ACTIVE__WAVE_SLOT_MASK = 0x000FFFFF # macro +SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT = 0x0 # macro +SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK = 0x000FFFFF # macro +SQ_WAVE_MODE__FP_ROUND__SHIFT = 0x0 # macro +SQ_WAVE_MODE__FP_DENORM__SHIFT = 0x4 # macro +SQ_WAVE_MODE__DX10_CLAMP__SHIFT = 0x8 # macro +SQ_WAVE_MODE__IEEE__SHIFT = 0x9 # macro +SQ_WAVE_MODE__LOD_CLAMPED__SHIFT = 0xa # macro +SQ_WAVE_MODE__TRAP_AFTER_INST_EN__SHIFT = 0xb # macro +SQ_WAVE_MODE__EXCP_EN__SHIFT = 0xc # macro +SQ_WAVE_MODE__WAVE_END__SHIFT = 0x15 # macro +SQ_WAVE_MODE__FP16_OVFL__SHIFT = 0x17 # macro +SQ_WAVE_MODE__DISABLE_PERF__SHIFT = 0x1b # macro +SQ_WAVE_MODE__FP_ROUND_MASK = 0x0000000F # macro +SQ_WAVE_MODE__FP_DENORM_MASK = 0x000000F0 # macro +SQ_WAVE_MODE__DX10_CLAMP_MASK = 0x00000100 # macro +SQ_WAVE_MODE__IEEE_MASK = 0x00000200 # macro +SQ_WAVE_MODE__LOD_CLAMPED_MASK = 0x00000400 # macro +SQ_WAVE_MODE__TRAP_AFTER_INST_EN_MASK = 0x00000800 # macro +SQ_WAVE_MODE__EXCP_EN_MASK = 0x001FF000 # macro +SQ_WAVE_MODE__WAVE_END_MASK = 0x00200000 # macro +SQ_WAVE_MODE__FP16_OVFL_MASK = 0x00800000 # macro +SQ_WAVE_MODE__DISABLE_PERF_MASK = 0x08000000 # macro +SQ_WAVE_STATUS__SCC__SHIFT = 0x0 # macro +SQ_WAVE_STATUS__SPI_PRIO__SHIFT = 0x1 # macro +SQ_WAVE_STATUS__USER_PRIO__SHIFT = 0x3 # macro +SQ_WAVE_STATUS__PRIV__SHIFT = 0x5 # macro +SQ_WAVE_STATUS__TRAP_EN__SHIFT = 0x6 # macro +SQ_WAVE_STATUS__TTRACE_EN__SHIFT = 0x7 # macro +SQ_WAVE_STATUS__EXPORT_RDY__SHIFT = 0x8 # macro +SQ_WAVE_STATUS__EXECZ__SHIFT = 0x9 # macro +SQ_WAVE_STATUS__VCCZ__SHIFT = 0xa # macro +SQ_WAVE_STATUS__IN_TG__SHIFT = 0xb # macro +SQ_WAVE_STATUS__IN_BARRIER__SHIFT = 0xc # macro +SQ_WAVE_STATUS__HALT__SHIFT = 0xd # macro +SQ_WAVE_STATUS__TRAP__SHIFT = 0xe # macro +SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT = 0xf # macro +SQ_WAVE_STATUS__VALID__SHIFT = 0x10 # macro +SQ_WAVE_STATUS__ECC_ERR__SHIFT = 0x11 # macro +SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT = 0x12 # macro +SQ_WAVE_STATUS__PERF_EN__SHIFT = 0x13 # macro +SQ_WAVE_STATUS__OREO_CONFLICT__SHIFT = 0x16 # macro +SQ_WAVE_STATUS__FATAL_HALT__SHIFT = 0x17 # macro +SQ_WAVE_STATUS__NO_VGPRS__SHIFT = 0x18 # macro +SQ_WAVE_STATUS__LDS_PARAM_READY__SHIFT = 0x19 # macro +SQ_WAVE_STATUS__MUST_GS_ALLOC__SHIFT = 0x1a # macro +SQ_WAVE_STATUS__MUST_EXPORT__SHIFT = 0x1b # macro +SQ_WAVE_STATUS__IDLE__SHIFT = 0x1c # macro +SQ_WAVE_STATUS__SCRATCH_EN__SHIFT = 0x1d # macro +SQ_WAVE_STATUS__SCC_MASK = 0x00000001 # macro +SQ_WAVE_STATUS__SPI_PRIO_MASK = 0x00000006 # macro +SQ_WAVE_STATUS__USER_PRIO_MASK = 0x00000018 # macro +SQ_WAVE_STATUS__PRIV_MASK = 0x00000020 # macro +SQ_WAVE_STATUS__TRAP_EN_MASK = 0x00000040 # macro +SQ_WAVE_STATUS__TTRACE_EN_MASK = 0x00000080 # macro +SQ_WAVE_STATUS__EXPORT_RDY_MASK = 0x00000100 # macro +SQ_WAVE_STATUS__EXECZ_MASK = 0x00000200 # macro +SQ_WAVE_STATUS__VCCZ_MASK = 0x00000400 # macro +SQ_WAVE_STATUS__IN_TG_MASK = 0x00000800 # macro +SQ_WAVE_STATUS__IN_BARRIER_MASK = 0x00001000 # macro +SQ_WAVE_STATUS__HALT_MASK = 0x00002000 # macro +SQ_WAVE_STATUS__TRAP_MASK = 0x00004000 # macro +SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK = 0x00008000 # macro +SQ_WAVE_STATUS__VALID_MASK = 0x00010000 # macro +SQ_WAVE_STATUS__ECC_ERR_MASK = 0x00020000 # macro +SQ_WAVE_STATUS__SKIP_EXPORT_MASK = 0x00040000 # macro +SQ_WAVE_STATUS__PERF_EN_MASK = 0x00080000 # macro +SQ_WAVE_STATUS__OREO_CONFLICT_MASK = 0x00400000 # macro +SQ_WAVE_STATUS__FATAL_HALT_MASK = 0x00800000 # macro +SQ_WAVE_STATUS__NO_VGPRS_MASK = 0x01000000 # macro +SQ_WAVE_STATUS__LDS_PARAM_READY_MASK = 0x02000000 # macro +SQ_WAVE_STATUS__MUST_GS_ALLOC_MASK = 0x04000000 # macro +SQ_WAVE_STATUS__MUST_EXPORT_MASK = 0x08000000 # macro +SQ_WAVE_STATUS__IDLE_MASK = 0x10000000 # macro +SQ_WAVE_STATUS__SCRATCH_EN_MASK = 0x20000000 # macro +SQ_WAVE_TRAPSTS__EXCP__SHIFT = 0x0 # macro +SQ_WAVE_TRAPSTS__SAVECTX__SHIFT = 0xa # macro +SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT = 0xb # macro +SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT = 0xc # macro +SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT = 0xf # macro +SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT = 0x10 # macro +SQ_WAVE_TRAPSTS__WAVESTART__SHIFT = 0x11 # macro +SQ_WAVE_TRAPSTS__WAVE_END__SHIFT = 0x12 # macro +SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT = 0x13 # macro +SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT = 0x14 # macro +SQ_WAVE_TRAPSTS__UTC_ERROR__SHIFT = 0x1c # macro +SQ_WAVE_TRAPSTS__EXCP_MASK = 0x000001FF # macro +SQ_WAVE_TRAPSTS__SAVECTX_MASK = 0x00000400 # macro +SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK = 0x00000800 # macro +SQ_WAVE_TRAPSTS__EXCP_HI_MASK = 0x00007000 # macro +SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK = 0x00008000 # macro +SQ_WAVE_TRAPSTS__HOST_TRAP_MASK = 0x00010000 # macro +SQ_WAVE_TRAPSTS__WAVESTART_MASK = 0x00020000 # macro +SQ_WAVE_TRAPSTS__WAVE_END_MASK = 0x00040000 # macro +SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK = 0x00080000 # macro +SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK = 0x00100000 # macro +SQ_WAVE_TRAPSTS__UTC_ERROR_MASK = 0x10000000 # macro +SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT = 0x0 # macro +SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT = 0xc # macro +SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK = 0x000001FF # macro +SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK = 0x000FF000 # macro +SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT = 0x0 # macro +SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT = 0xc # macro +SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT = 0x18 # macro +SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK = 0x000001FF # macro +SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK = 0x001FF000 # macro +SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK = 0x0F000000 # macro +SQ_WAVE_IB_STS__EXP_CNT__SHIFT = 0x0 # macro +SQ_WAVE_IB_STS__LGKM_CNT__SHIFT = 0x4 # macro +SQ_WAVE_IB_STS__VM_CNT__SHIFT = 0xa # macro +SQ_WAVE_IB_STS__VS_CNT__SHIFT = 0x1a # macro +SQ_WAVE_IB_STS__EXP_CNT_MASK = 0x00000007 # macro +SQ_WAVE_IB_STS__LGKM_CNT_MASK = 0x000003F0 # macro +SQ_WAVE_IB_STS__VM_CNT_MASK = 0x0000FC00 # macro +SQ_WAVE_IB_STS__VS_CNT_MASK = 0xFC000000 # macro +SQ_WAVE_PC_LO__PC_LO__SHIFT = 0x0 # macro +SQ_WAVE_PC_LO__PC_LO_MASK = 0xFFFFFFFF # macro +SQ_WAVE_PC_HI__PC_HI__SHIFT = 0x0 # macro +SQ_WAVE_PC_HI__PC_HI_MASK = 0x0000FFFF # macro +SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT = 0x18 # macro +SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT = 0x19 # macro +SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK = 0x01000000 # macro +SQ_WAVE_IB_DBG1__MISC_CNT_MASK = 0xFE000000 # macro +SQ_WAVE_FLUSH_IB__UNUSED__SHIFT = 0x0 # macro +SQ_WAVE_FLUSH_IB__UNUSED_MASK = 0xFFFFFFFF # macro +SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT = 0x0 # macro +SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT = 0x0 # macro +SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_HW_ID1__WAVE_ID__SHIFT = 0x0 # macro +SQ_WAVE_HW_ID1__SIMD_ID__SHIFT = 0x8 # macro +SQ_WAVE_HW_ID1__WGP_ID__SHIFT = 0xa # macro +SQ_WAVE_HW_ID1__SA_ID__SHIFT = 0x10 # macro +SQ_WAVE_HW_ID1__SE_ID__SHIFT = 0x12 # macro +SQ_WAVE_HW_ID1__DP_RATE__SHIFT = 0x1d # macro +SQ_WAVE_HW_ID1__WAVE_ID_MASK = 0x0000001F # macro +SQ_WAVE_HW_ID1__SIMD_ID_MASK = 0x00000300 # macro +SQ_WAVE_HW_ID1__WGP_ID_MASK = 0x00003C00 # macro +SQ_WAVE_HW_ID1__SA_ID_MASK = 0x00010000 # macro +SQ_WAVE_HW_ID1__SE_ID_MASK = 0x001C0000 # macro +SQ_WAVE_HW_ID1__DP_RATE_MASK = 0xE0000000 # macro +SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT = 0x0 # macro +SQ_WAVE_HW_ID2__PIPE_ID__SHIFT = 0x4 # macro +SQ_WAVE_HW_ID2__ME_ID__SHIFT = 0x8 # macro +SQ_WAVE_HW_ID2__STATE_ID__SHIFT = 0xc # macro +SQ_WAVE_HW_ID2__WG_ID__SHIFT = 0x10 # macro +SQ_WAVE_HW_ID2__VM_ID__SHIFT = 0x18 # macro +SQ_WAVE_HW_ID2__QUEUE_ID_MASK = 0x0000000F # macro +SQ_WAVE_HW_ID2__PIPE_ID_MASK = 0x00000030 # macro +SQ_WAVE_HW_ID2__ME_ID_MASK = 0x00000300 # macro +SQ_WAVE_HW_ID2__STATE_ID_MASK = 0x00007000 # macro +SQ_WAVE_HW_ID2__WG_ID_MASK = 0x001F0000 # macro +SQ_WAVE_HW_ID2__VM_ID_MASK = 0x0F000000 # macro +SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT = 0x0 # macro +SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT = 0x1 # macro +SQ_WAVE_POPS_PACKER__POPS_EN_MASK = 0x00000001 # macro +SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK = 0x00000006 # macro +SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT = 0x0 # macro +SQ_WAVE_SCHED_MODE__DEP_MODE_MASK = 0x00000003 # macro +SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT = 0x0 # macro +SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT = 0x8 # macro +SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT = 0xa # macro +SQ_WAVE_IB_STS2__WAVE64__SHIFT = 0xb # macro +SQ_WAVE_IB_STS2__INST_PREFETCH_MASK = 0x00000003 # macro +SQ_WAVE_IB_STS2__MEM_ORDER_MASK = 0x00000300 # macro +SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK = 0x00000400 # macro +SQ_WAVE_IB_STS2__WAVE64_MASK = 0x00000800 # macro +SQ_WAVE_SHADER_CYCLES__CYCLES__SHIFT = 0x0 # macro +SQ_WAVE_SHADER_CYCLES__CYCLES_MASK = 0x000FFFFF # macro +SQ_WAVE_TTMP0__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP0__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP1__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP1__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP3__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP3__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP4__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP4__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP5__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP5__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP6__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP6__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP7__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP7__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP8__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP8__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP9__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP9__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP10__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP10__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP11__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP11__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP12__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP12__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP13__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP13__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP14__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP14__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP15__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP15__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_M0__M0__SHIFT = 0x0 # macro +SQ_WAVE_M0__M0_MASK = 0xFFFFFFFF # macro +SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT = 0x0 # macro +SQ_WAVE_EXEC_LO__EXEC_LO_MASK = 0xFFFFFFFF # macro +SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT = 0x0 # macro +SQ_WAVE_EXEC_HI__EXEC_HI_MASK = 0xFFFFFFFF # macro +__all__ = \ + ['CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND0_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND0_CONTROL__ENABLE_MASK', + 'CB_BLEND0_CONTROL__ENABLE__SHIFT', + 'CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND1_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND1_CONTROL__ENABLE_MASK', + 'CB_BLEND1_CONTROL__ENABLE__SHIFT', + 'CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND2_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND2_CONTROL__ENABLE_MASK', + 'CB_BLEND2_CONTROL__ENABLE__SHIFT', + 'CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND3_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND3_CONTROL__ENABLE_MASK', + 'CB_BLEND3_CONTROL__ENABLE__SHIFT', + 'CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND4_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND4_CONTROL__ENABLE_MASK', + 'CB_BLEND4_CONTROL__ENABLE__SHIFT', + 'CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND5_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND5_CONTROL__ENABLE_MASK', + 'CB_BLEND5_CONTROL__ENABLE__SHIFT', + 'CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND6_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND6_CONTROL__ENABLE_MASK', + 'CB_BLEND6_CONTROL__ENABLE__SHIFT', + 'CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND7_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND7_CONTROL__ENABLE_MASK', + 'CB_BLEND7_CONTROL__ENABLE__SHIFT', + 'CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND_ALPHA__BLEND_ALPHA_MASK', + 'CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT', + 'CB_BLEND_BLUE__BLEND_BLUE_MASK', + 'CB_BLEND_BLUE__BLEND_BLUE__SHIFT', + 'CB_BLEND_GREEN__BLEND_GREEN_MASK', + 'CB_BLEND_GREEN__BLEND_GREEN__SHIFT', + 'CB_BLEND_RED__BLEND_RED_MASK', 'CB_BLEND_RED__BLEND_RED__SHIFT', + 'CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK', + 'CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT', + 'CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT_MASK', + 'CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT__SHIFT', + 'CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT_MASK', + 'CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT__SHIFT', + 'CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK', + 'CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT', + 'CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK', + 'CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CB_CGTT_SCLK_CTRL__ON_DELAY_MASK', + 'CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CB_COLOR0_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR0_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR0_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR0_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR0_BASE__BASE_256B_MASK', + 'CB_COLOR0_BASE__BASE_256B__SHIFT', + 'CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR0_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR0_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR0_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR0_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR0_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR0_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR0_INFO__COMP_SWAP_MASK', + 'CB_COLOR0_INFO__COMP_SWAP__SHIFT', 'CB_COLOR0_INFO__FORMAT_MASK', + 'CB_COLOR0_INFO__FORMAT__SHIFT', + 'CB_COLOR0_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR0_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR0_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR0_INFO__ROUND_MODE_MASK', + 'CB_COLOR0_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR0_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR0_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR0_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR0_VIEW__SLICE_MAX_MASK', + 'CB_COLOR0_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR0_VIEW__SLICE_START_MASK', + 'CB_COLOR0_VIEW__SLICE_START__SHIFT', + 'CB_COLOR1_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR1_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR1_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR1_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR1_BASE__BASE_256B_MASK', + 'CB_COLOR1_BASE__BASE_256B__SHIFT', + 'CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR1_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR1_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR1_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR1_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR1_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR1_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR1_INFO__COMP_SWAP_MASK', + 'CB_COLOR1_INFO__COMP_SWAP__SHIFT', 'CB_COLOR1_INFO__FORMAT_MASK', + 'CB_COLOR1_INFO__FORMAT__SHIFT', + 'CB_COLOR1_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR1_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR1_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR1_INFO__ROUND_MODE_MASK', + 'CB_COLOR1_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR1_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR1_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR1_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR1_VIEW__SLICE_MAX_MASK', + 'CB_COLOR1_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR1_VIEW__SLICE_START_MASK', + 'CB_COLOR1_VIEW__SLICE_START__SHIFT', + 'CB_COLOR2_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR2_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR2_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR2_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR2_BASE__BASE_256B_MASK', + 'CB_COLOR2_BASE__BASE_256B__SHIFT', + 'CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR2_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR2_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR2_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR2_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR2_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR2_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR2_INFO__COMP_SWAP_MASK', + 'CB_COLOR2_INFO__COMP_SWAP__SHIFT', 'CB_COLOR2_INFO__FORMAT_MASK', + 'CB_COLOR2_INFO__FORMAT__SHIFT', + 'CB_COLOR2_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR2_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR2_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR2_INFO__ROUND_MODE_MASK', + 'CB_COLOR2_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR2_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR2_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR2_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR2_VIEW__SLICE_MAX_MASK', + 'CB_COLOR2_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR2_VIEW__SLICE_START_MASK', + 'CB_COLOR2_VIEW__SLICE_START__SHIFT', + 'CB_COLOR3_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR3_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR3_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR3_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR3_BASE__BASE_256B_MASK', + 'CB_COLOR3_BASE__BASE_256B__SHIFT', + 'CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR3_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR3_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR3_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR3_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR3_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR3_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR3_INFO__COMP_SWAP_MASK', + 'CB_COLOR3_INFO__COMP_SWAP__SHIFT', 'CB_COLOR3_INFO__FORMAT_MASK', + 'CB_COLOR3_INFO__FORMAT__SHIFT', + 'CB_COLOR3_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR3_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR3_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR3_INFO__ROUND_MODE_MASK', + 'CB_COLOR3_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR3_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR3_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR3_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR3_VIEW__SLICE_MAX_MASK', + 'CB_COLOR3_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR3_VIEW__SLICE_START_MASK', + 'CB_COLOR3_VIEW__SLICE_START__SHIFT', + 'CB_COLOR4_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR4_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR4_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR4_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR4_BASE__BASE_256B_MASK', + 'CB_COLOR4_BASE__BASE_256B__SHIFT', + 'CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR4_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR4_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR4_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR4_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR4_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR4_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR4_INFO__COMP_SWAP_MASK', + 'CB_COLOR4_INFO__COMP_SWAP__SHIFT', 'CB_COLOR4_INFO__FORMAT_MASK', + 'CB_COLOR4_INFO__FORMAT__SHIFT', + 'CB_COLOR4_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR4_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR4_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR4_INFO__ROUND_MODE_MASK', + 'CB_COLOR4_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR4_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR4_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR4_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR4_VIEW__SLICE_MAX_MASK', + 'CB_COLOR4_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR4_VIEW__SLICE_START_MASK', + 'CB_COLOR4_VIEW__SLICE_START__SHIFT', + 'CB_COLOR5_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR5_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR5_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR5_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR5_BASE__BASE_256B_MASK', + 'CB_COLOR5_BASE__BASE_256B__SHIFT', + 'CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR5_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR5_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR5_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR5_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR5_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR5_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR5_INFO__COMP_SWAP_MASK', + 'CB_COLOR5_INFO__COMP_SWAP__SHIFT', 'CB_COLOR5_INFO__FORMAT_MASK', + 'CB_COLOR5_INFO__FORMAT__SHIFT', + 'CB_COLOR5_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR5_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR5_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR5_INFO__ROUND_MODE_MASK', + 'CB_COLOR5_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR5_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR5_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR5_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR5_VIEW__SLICE_MAX_MASK', + 'CB_COLOR5_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR5_VIEW__SLICE_START_MASK', + 'CB_COLOR5_VIEW__SLICE_START__SHIFT', + 'CB_COLOR6_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR6_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR6_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR6_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR6_BASE__BASE_256B_MASK', + 'CB_COLOR6_BASE__BASE_256B__SHIFT', + 'CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR6_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR6_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR6_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR6_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR6_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR6_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR6_INFO__COMP_SWAP_MASK', + 'CB_COLOR6_INFO__COMP_SWAP__SHIFT', 'CB_COLOR6_INFO__FORMAT_MASK', + 'CB_COLOR6_INFO__FORMAT__SHIFT', + 'CB_COLOR6_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR6_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR6_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR6_INFO__ROUND_MODE_MASK', + 'CB_COLOR6_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR6_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR6_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR6_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR6_VIEW__SLICE_MAX_MASK', + 'CB_COLOR6_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR6_VIEW__SLICE_START_MASK', + 'CB_COLOR6_VIEW__SLICE_START__SHIFT', + 'CB_COLOR7_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK', + 'CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT', + 'CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK', + 'CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT', + 'CB_COLOR7_ATTRIB3__META_LINEAR_MASK', + 'CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT', + 'CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK', + 'CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT', + 'CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK', + 'CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT', + 'CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK', + 'CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT', + 'CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK', + 'CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT', + 'CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR7_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR7_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR7_BASE__BASE_256B_MASK', + 'CB_COLOR7_BASE__BASE_256B__SHIFT', + 'CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR7_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR7_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK', + 'CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE_MASK', + 'CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK', + 'CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK', + 'CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK', + 'CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT', + 'CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK', + 'CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT', + 'CB_COLOR7_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR7_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR7_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR7_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR7_INFO__COMP_SWAP_MASK', + 'CB_COLOR7_INFO__COMP_SWAP__SHIFT', 'CB_COLOR7_INFO__FORMAT_MASK', + 'CB_COLOR7_INFO__FORMAT__SHIFT', + 'CB_COLOR7_INFO__LINEAR_GENERAL_MASK', + 'CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT', + 'CB_COLOR7_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR7_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR7_INFO__ROUND_MODE_MASK', + 'CB_COLOR7_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR7_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR7_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR7_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR7_VIEW__SLICE_MAX_MASK', + 'CB_COLOR7_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR7_VIEW__SLICE_START_MASK', + 'CB_COLOR7_VIEW__SLICE_START__SHIFT', + 'CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK', + 'CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT', + 'CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK', + 'CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT', + 'CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK', + 'CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT', + 'CB_COLOR_CONTROL__MODE_MASK', 'CB_COLOR_CONTROL__MODE__SHIFT', + 'CB_COLOR_CONTROL__ROP3_MASK', 'CB_COLOR_CONTROL__ROP3__SHIFT', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK', + 'CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT', + 'CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK', + 'CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT', + 'CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK', + 'CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT', + 'CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK', + 'CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT', + 'CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH_MASK', + 'CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH__SHIFT', + 'CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_DCC_CONFIG__SPARE_13_MASK', 'CB_DCC_CONFIG__SPARE_13__SHIFT', + 'CB_DCC_CONFIG__SPARE_14_MASK', 'CB_DCC_CONFIG__SPARE_14__SHIFT', + 'CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK', + 'CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT', + 'CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK', + 'CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT', + 'CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK', + 'CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT', + 'CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK', + 'CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT', + 'CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK', + 'CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT', + 'CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK', + 'CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT', + 'CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK_MASK', + 'CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK__SHIFT', + 'CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG_MASK', + 'CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG__SHIFT', + 'CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK', + 'CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT', + 'CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK', + 'CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT', + 'CB_HW_CONTROL_2__SPARE_4_MASK', + 'CB_HW_CONTROL_2__SPARE_4__SHIFT', 'CB_HW_CONTROL_2__SPARE_MASK', + 'CB_HW_CONTROL_2__SPARE__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT_MASK', + 'CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT_MASK', + 'CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK', + 'CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT', + 'CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK', + 'CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT', + 'CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK', + 'CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT', + 'CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK', + 'CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT', + 'CB_HW_CONTROL_3__SPARE_5_MASK', + 'CB_HW_CONTROL_3__SPARE_5__SHIFT', + 'CB_HW_CONTROL_3__SPARE_6_MASK', + 'CB_HW_CONTROL_3__SPARE_6__SHIFT', + 'CB_HW_CONTROL_3__SPARE_7_MASK', + 'CB_HW_CONTROL_3__SPARE_7__SHIFT', + 'CB_HW_CONTROL_3__SPARE_8_MASK', + 'CB_HW_CONTROL_3__SPARE_8__SHIFT', + 'CB_HW_CONTROL_3__SPARE_9_MASK', + 'CB_HW_CONTROL_3__SPARE_9__SHIFT', + 'CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK', + 'CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT', + 'CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM_MASK', + 'CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM__SHIFT', + 'CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2_MASK', + 'CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2__SHIFT', + 'CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK', + 'CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT', + 'CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE_MASK', + 'CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE__SHIFT', + 'CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD_MASK', + 'CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD__SHIFT', + 'CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD_MASK', + 'CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD__SHIFT', + 'CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD_MASK', + 'CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD__SHIFT', + 'CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD_MASK', + 'CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD__SHIFT', + 'CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD_MASK', + 'CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD__SHIFT', + 'CB_HW_CONTROL_4__SPARE_10_MASK', + 'CB_HW_CONTROL_4__SPARE_10__SHIFT', + 'CB_HW_CONTROL_4__SPARE_11_MASK', + 'CB_HW_CONTROL_4__SPARE_11__SHIFT', + 'CB_HW_CONTROL_4__SPARE_12_MASK', + 'CB_HW_CONTROL_4__SPARE_12__SHIFT', + 'CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK', + 'CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT', + 'CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK', + 'CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT', + 'CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING_MASK', + 'CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING__SHIFT', + 'CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK', + 'CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT', + 'CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX_MASK', + 'CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX__SHIFT', + 'CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK', + 'CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT', + 'CB_HW_CONTROL__FORCE_EVICT_ALL_VALID_MASK', + 'CB_HW_CONTROL__FORCE_EVICT_ALL_VALID__SHIFT', + 'CB_HW_CONTROL__FORCE_FEA_HIGH_MASK', + 'CB_HW_CONTROL__FORCE_FEA_HIGH__SHIFT', + 'CB_HW_CONTROL__FORCE_NEEDS_DST_MASK', + 'CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT', + 'CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES_MASK', + 'CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES__SHIFT', + 'CB_HW_CONTROL__RMI_CREDITS_MASK', + 'CB_HW_CONTROL__RMI_CREDITS__SHIFT', + 'CB_HW_CONTROL__SPARE_2_MASK', 'CB_HW_CONTROL__SPARE_2__SHIFT', + 'CB_HW_CONTROL__SPARE_3_MASK', 'CB_HW_CONTROL__SPARE_3__SHIFT', + 'CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK', + 'CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK', + 'CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__MODE_MASK', + 'CB_HW_MEM_ARBITER_RD__MODE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK', + 'CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK', + 'CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT', + 'CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK', + 'CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK', + 'CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK', + 'CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__MODE_MASK', + 'CB_HW_MEM_ARBITER_WR__MODE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK', + 'CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK', + 'CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT', + 'CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK', + 'CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT', + 'CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS_MASK', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS__SHIFT', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK', + 'CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT', + 'CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS_MASK', + 'CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS__SHIFT', + 'CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK', + 'CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT', + 'CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK', + 'CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT', + 'CB_SHADER_MASK__OUTPUT0_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT1_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT2_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT3_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT4_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT5_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT6_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT7_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET0_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET0_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET1_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET1_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET2_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET2_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET3_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET3_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET4_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET4_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET5_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET5_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET6_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET6_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET7_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET7_ENABLE__SHIFT', + 'CC_GC_EDC_CONFIG__DIS_EDC_MASK', + 'CC_GC_EDC_CONFIG__DIS_EDC__SHIFT', + 'CC_GC_PRIM_CONFIG__INACTIVE_PA_MASK', + 'CC_GC_PRIM_CONFIG__INACTIVE_PA__SHIFT', + 'CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK', + 'CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT', + 'CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK', + 'CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT', + 'CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK', + 'CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT', + 'CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK', + 'CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT', + 'CC_RB_BACKEND_DISABLE__RESERVED_MASK', + 'CC_RB_BACKEND_DISABLE__RESERVED__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_0_MASK', 'CC_RB_DAISY_CHAIN__RB_0__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_1_MASK', 'CC_RB_DAISY_CHAIN__RB_1__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_2_MASK', 'CC_RB_DAISY_CHAIN__RB_2__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_3_MASK', 'CC_RB_DAISY_CHAIN__RB_3__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_4_MASK', 'CC_RB_DAISY_CHAIN__RB_4__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_5_MASK', 'CC_RB_DAISY_CHAIN__RB_5__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_6_MASK', 'CC_RB_DAISY_CHAIN__RB_6__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_7_MASK', 'CC_RB_DAISY_CHAIN__RB_7__SHIFT', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT', + 'CC_RB_REDUNDANCY__FAILED_RB0_MASK', + 'CC_RB_REDUNDANCY__FAILED_RB0__SHIFT', + 'CC_RB_REDUNDANCY__FAILED_RB1_MASK', + 'CC_RB_REDUNDANCY__FAILED_RB1__SHIFT', + 'CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK', + 'CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT', + 'CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK', + 'CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT', + 'CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK', + 'CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT', + 'CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK', + 'CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT', + 'CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK', + 'CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT', + 'CGTS_TCC_DISABLE__TCC_DISABLE_MASK', + 'CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT', + 'CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK', + 'CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT', + 'CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK', + 'CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT', + 'CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK', + 'CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE_MASK', + 'CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK', + 'CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK', + 'CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT', + 'CGTT_PH_CLK_CTRL0__ON_DELAY_MASK', + 'CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT', + 'CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK', + 'CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT', + 'CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK', + 'CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK', + 'CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT', + 'CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK', + 'CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT', + 'CGTT_PH_CLK_CTRL1__ON_DELAY_MASK', + 'CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK', + 'CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT', + 'CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK', + 'CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT', + 'CGTT_PH_CLK_CTRL2__ON_DELAY_MASK', + 'CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK', + 'CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT', + 'CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK', + 'CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT', + 'CGTT_PH_CLK_CTRL3__ON_DELAY_MASK', + 'CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK', + 'CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT', + 'CGTT_RLC_CLK_CTRL__RESERVED_MASK', + 'CGTT_RLC_CLK_CTRL__RESERVED__SHIFT', + 'CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK', + 'CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT', + 'CGTT_SC_CLK_CTRL0__ON_DELAY_MASK', + 'CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK', + 'CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT', + 'CGTT_SC_CLK_CTRL1__ON_DELAY_MASK', + 'CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK', + 'CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT', + 'CGTT_SC_CLK_CTRL2__ON_DELAY_MASK', + 'CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT', + 'CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT', + 'CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG_MASK', + 'CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG__SHIFT', + 'CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG_MASK', + 'CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG__SHIFT', + 'CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG_MASK', + 'CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG__SHIFT', + 'CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG_MASK', + 'CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG__SHIFT', + 'CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN_MASK', + 'CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN__SHIFT', + 'CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_SQG_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT', + 'CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT', + 'CHA_CHC_CREDITS__CHCG_REQ_CREDITS_MASK', + 'CHA_CHC_CREDITS__CHCG_REQ_CREDITS__SHIFT', + 'CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK', + 'CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK', + 'CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT', + 'CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'CHCG_CTRL__BUFFER_DEPTH_MAX_MASK', + 'CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT', + 'CHCG_CTRL__GL2_DATA_CREDITS_MASK', + 'CHCG_CTRL__GL2_DATA_CREDITS__SHIFT', + 'CHCG_CTRL__GL2_REQ_CREDITS_MASK', + 'CHCG_CTRL__GL2_REQ_CREDITS__SHIFT', + 'CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK', + 'CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT', + 'CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK', + 'CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT', + 'CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK', + 'CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT', + 'CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'CHCG_STATUS__BUFFER_FULL_MASK', + 'CHCG_STATUS__BUFFER_FULL__SHIFT', + 'CHCG_STATUS__GL2_DATA_VC0_STALL_MASK', + 'CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT', + 'CHCG_STATUS__GL2_DATA_VC1_STALL_MASK', + 'CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT', + 'CHCG_STATUS__GL2_REQ_VC0_STALL_MASK', + 'CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT', + 'CHCG_STATUS__GL2_REQ_VC1_STALL_MASK', + 'CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT', + 'CHCG_STATUS__GL2_RH_BUSY_MASK', + 'CHCG_STATUS__GL2_RH_BUSY__SHIFT', + 'CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK', + 'CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT', + 'CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK', + 'CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT', + 'CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK', + 'CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT', + 'CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK', + 'CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT', + 'CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK', + 'CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT', + 'CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK', + 'CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT', + 'CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK', + 'CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT', + 'CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK', + 'CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT', + 'CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK', + 'CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT', + 'CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK', + 'CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT', + 'CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK', + 'CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT', + 'CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK', + 'CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT', + 'CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK', + 'CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT', + 'CHC_CTRL__BUFFER_DEPTH_MAX_MASK', + 'CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT', + 'CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT_MASK', + 'CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT__SHIFT', + 'CHC_CTRL__GL2_DATA_CREDITS_MASK', + 'CHC_CTRL__GL2_DATA_CREDITS__SHIFT', + 'CHC_CTRL__GL2_REQ_CREDITS_MASK', + 'CHC_CTRL__GL2_REQ_CREDITS__SHIFT', + 'CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK', + 'CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT', + 'CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK', + 'CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT', + 'CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'CHC_STATUS__BUFFER_FULL_MASK', 'CHC_STATUS__BUFFER_FULL__SHIFT', + 'CHC_STATUS__GL2_DATA_VC0_STALL_MASK', + 'CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT', + 'CHC_STATUS__GL2_DATA_VC1_STALL_MASK', + 'CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT', + 'CHC_STATUS__GL2_REQ_VC0_STALL_MASK', + 'CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT', + 'CHC_STATUS__GL2_REQ_VC1_STALL_MASK', + 'CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT', + 'CHC_STATUS__GL2_RH_BUSY_MASK', 'CHC_STATUS__GL2_RH_BUSY__SHIFT', + 'CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK', + 'CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT', + 'CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK', + 'CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT', + 'CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK', + 'CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT', + 'CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK', + 'CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT', + 'CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK', + 'CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT', + 'CHC_STATUS__REQUEST_TRACKER_BUSY_MASK', + 'CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT', + 'CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK', + 'CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT', + 'CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK', + 'CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT', + 'CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK', + 'CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT', + 'CHICKEN_BITS__SPARE_MASK', 'CHICKEN_BITS__SPARE__SHIFT', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE_MASK', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE__SHIFT', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE_MASK', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE__SHIFT', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE_MASK', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE__SHIFT', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE_MASK', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE__SHIFT', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE_MASK', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE_MASK', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE__SHIFT', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE_MASK', + 'CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE__SHIFT', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE_MASK', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE__SHIFT', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE_MASK', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE__SHIFT', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE_MASK', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE__SHIFT', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE_MASK', + 'CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE__SHIFT', + 'CH_ARB_CTRL__CHICKEN_BITS_MASK', + 'CH_ARB_CTRL__CHICKEN_BITS__SHIFT', + 'CH_ARB_CTRL__FGCG_DISABLE_MASK', + 'CH_ARB_CTRL__FGCG_DISABLE__SHIFT', + 'CH_ARB_CTRL__NUM_MEM_PIPES_MASK', + 'CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT', + 'CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK', + 'CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT', + 'CH_ARB_CTRL__UC_IO_WR_PATH_MASK', + 'CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT', + 'CH_ARB_STATUS__REQ_ARB_BUSY_MASK', + 'CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT', + 'CH_ARB_STATUS__RET_ARB_BUSY_MASK', + 'CH_ARB_STATUS__RET_ARB_BUSY__SHIFT', + 'CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK', + 'CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT', + 'CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE_MASK', + 'CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE__SHIFT', + 'CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK', + 'CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT', + 'CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK', + 'CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT', + 'CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK', + 'CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT', + 'CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK', + 'CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT', + 'CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK', + 'CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT', + 'CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK', + 'CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT', + 'CH_PIPE_STEER__PIPE0_MASK', 'CH_PIPE_STEER__PIPE0__SHIFT', + 'CH_PIPE_STEER__PIPE1_MASK', 'CH_PIPE_STEER__PIPE1__SHIFT', + 'CH_PIPE_STEER__PIPE2_MASK', 'CH_PIPE_STEER__PIPE2__SHIFT', + 'CH_PIPE_STEER__PIPE3_MASK', 'CH_PIPE_STEER__PIPE3__SHIFT', + 'CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK', + 'CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT', + 'COHER_DEST_BASE_0__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_1__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_2__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_3__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT', + 'COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT', + 'COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT', + 'COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT', + 'COMPUTE_DDID_INDEX__INDEX_MASK', + 'COMPUTE_DDID_INDEX__INDEX__SHIFT', + 'COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK', + 'COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT', + 'COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK', + 'COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT', + 'COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK', + 'COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT', + 'COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK', + 'COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT', + 'COMPUTE_DIM_X__SIZE_MASK', 'COMPUTE_DIM_X__SIZE__SHIFT', + 'COMPUTE_DIM_Y__SIZE_MASK', 'COMPUTE_DIM_Y__SIZE__SHIFT', + 'COMPUTE_DIM_Z__SIZE_MASK', 'COMPUTE_DIM_Z__SIZE__SHIFT', + 'COMPUTE_DISPATCH_END__DATA_MASK', + 'COMPUTE_DISPATCH_END__DATA__SHIFT', + 'COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK', + 'COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK', + 'COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK', + 'COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK', + 'COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK', + 'COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK', + 'COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK', + 'COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK', + 'COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK', + 'COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK', + 'COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK', + 'COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK', + 'COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK', + 'COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK', + 'COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT', + 'COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_MASK', + 'COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE__SHIFT', + 'COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK', + 'COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT', + 'COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK', + 'COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT', + 'COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK', + 'COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT', + 'COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK', + 'COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT', + 'COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK', + 'COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT', + 'COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK', + 'COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT', + 'COMPUTE_MISC_RESERVED__RESERVED3_MASK', + 'COMPUTE_MISC_RESERVED__RESERVED3__SHIFT', + 'COMPUTE_MISC_RESERVED__RESERVED4_MASK', + 'COMPUTE_MISC_RESERVED__RESERVED4__SHIFT', + 'COMPUTE_MISC_RESERVED__SEND_SEID_MASK', + 'COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT', + 'COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK', + 'COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT', + 'COMPUTE_NOWHERE__DATA_MASK', 'COMPUTE_NOWHERE__DATA__SHIFT', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT', + 'COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK', + 'COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT', + 'COMPUTE_PGM_HI__DATA_MASK', 'COMPUTE_PGM_HI__DATA__SHIFT', + 'COMPUTE_PGM_LO__DATA_MASK', 'COMPUTE_PGM_LO__DATA__SHIFT', + 'COMPUTE_PGM_RSRC1__BULKY_MASK', + 'COMPUTE_PGM_RSRC1__BULKY__SHIFT', + 'COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK', + 'COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT', + 'COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK', + 'COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT', + 'COMPUTE_PGM_RSRC1__FP16_OVFL_MASK', + 'COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT', + 'COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK', + 'COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT', + 'COMPUTE_PGM_RSRC1__IEEE_MODE_MASK', + 'COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT', + 'COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK', + 'COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT', + 'COMPUTE_PGM_RSRC1__PRIORITY_MASK', + 'COMPUTE_PGM_RSRC1__PRIORITY__SHIFT', + 'COMPUTE_PGM_RSRC1__PRIV_MASK', 'COMPUTE_PGM_RSRC1__PRIV__SHIFT', + 'COMPUTE_PGM_RSRC1__SGPRS_MASK', + 'COMPUTE_PGM_RSRC1__SGPRS__SHIFT', + 'COMPUTE_PGM_RSRC1__VGPRS_MASK', + 'COMPUTE_PGM_RSRC1__VGPRS__SHIFT', + 'COMPUTE_PGM_RSRC1__WGP_MODE_MASK', + 'COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT', + 'COMPUTE_PGM_RSRC2__EXCP_EN_MASK', + 'COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK', + 'COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT', + 'COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__LDS_SIZE_MASK', + 'COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT', + 'COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK', + 'COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TGID_X_EN_MASK', + 'COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK', + 'COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK', + 'COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK', + 'COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK', + 'COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT', + 'COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK', + 'COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT', + 'COMPUTE_PGM_RSRC2__USER_SGPR_MASK', + 'COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT', + 'COMPUTE_PGM_RSRC3__IMAGE_OP_MASK', + 'COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT', + 'COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK', + 'COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT', + 'COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK', + 'COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT', + 'COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK', + 'COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT', + 'COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK', + 'COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT', + 'COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK', + 'COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT', + 'COMPUTE_RELAUNCH2__IS_EVENT_MASK', + 'COMPUTE_RELAUNCH2__IS_EVENT__SHIFT', + 'COMPUTE_RELAUNCH2__IS_STATE_MASK', + 'COMPUTE_RELAUNCH2__IS_STATE__SHIFT', + 'COMPUTE_RELAUNCH2__PAYLOAD_MASK', + 'COMPUTE_RELAUNCH2__PAYLOAD__SHIFT', + 'COMPUTE_RELAUNCH__IS_EVENT_MASK', + 'COMPUTE_RELAUNCH__IS_EVENT__SHIFT', + 'COMPUTE_RELAUNCH__IS_STATE_MASK', + 'COMPUTE_RELAUNCH__IS_STATE__SHIFT', + 'COMPUTE_RELAUNCH__PAYLOAD_MASK', + 'COMPUTE_RELAUNCH__PAYLOAD__SHIFT', + 'COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK', + 'COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT', + 'COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK', + 'COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT', + 'COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK', + 'COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT', + 'COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK', + 'COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT', + 'COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK', + 'COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT', + 'COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK', + 'COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT', + 'COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK', + 'COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT', + 'COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK', + 'COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT', + 'COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK', + 'COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK', + 'COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK', + 'COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK', + 'COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK', + 'COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK', + 'COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK', + 'COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT', + 'COMPUTE_RESTART_X__RESTART_MASK', + 'COMPUTE_RESTART_X__RESTART__SHIFT', + 'COMPUTE_RESTART_Y__RESTART_MASK', + 'COMPUTE_RESTART_Y__RESTART__SHIFT', + 'COMPUTE_RESTART_Z__RESTART_MASK', + 'COMPUTE_RESTART_Z__RESTART__SHIFT', + 'COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK', + 'COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT', + 'COMPUTE_START_X__START_MASK', 'COMPUTE_START_X__START__SHIFT', + 'COMPUTE_START_Y__START_MASK', 'COMPUTE_START_Y__START__SHIFT', + 'COMPUTE_START_Z__START_MASK', 'COMPUTE_START_Z__START__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT', + 'COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK', + 'COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT', + 'COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK', + 'COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT', + 'COMPUTE_TMPRING_SIZE__WAVESIZE_MASK', + 'COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT', + 'COMPUTE_TMPRING_SIZE__WAVES_MASK', + 'COMPUTE_TMPRING_SIZE__WAVES__SHIFT', + 'COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK', + 'COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT', + 'COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK', + 'COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT', + 'COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK', + 'COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT', + 'COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK', + 'COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT', + 'COMPUTE_USER_DATA_0__DATA_MASK', + 'COMPUTE_USER_DATA_0__DATA__SHIFT', + 'COMPUTE_USER_DATA_10__DATA_MASK', + 'COMPUTE_USER_DATA_10__DATA__SHIFT', + 'COMPUTE_USER_DATA_11__DATA_MASK', + 'COMPUTE_USER_DATA_11__DATA__SHIFT', + 'COMPUTE_USER_DATA_12__DATA_MASK', + 'COMPUTE_USER_DATA_12__DATA__SHIFT', + 'COMPUTE_USER_DATA_13__DATA_MASK', + 'COMPUTE_USER_DATA_13__DATA__SHIFT', + 'COMPUTE_USER_DATA_14__DATA_MASK', + 'COMPUTE_USER_DATA_14__DATA__SHIFT', + 'COMPUTE_USER_DATA_15__DATA_MASK', + 'COMPUTE_USER_DATA_15__DATA__SHIFT', + 'COMPUTE_USER_DATA_1__DATA_MASK', + 'COMPUTE_USER_DATA_1__DATA__SHIFT', + 'COMPUTE_USER_DATA_2__DATA_MASK', + 'COMPUTE_USER_DATA_2__DATA__SHIFT', + 'COMPUTE_USER_DATA_3__DATA_MASK', + 'COMPUTE_USER_DATA_3__DATA__SHIFT', + 'COMPUTE_USER_DATA_4__DATA_MASK', + 'COMPUTE_USER_DATA_4__DATA__SHIFT', + 'COMPUTE_USER_DATA_5__DATA_MASK', + 'COMPUTE_USER_DATA_5__DATA__SHIFT', + 'COMPUTE_USER_DATA_6__DATA_MASK', + 'COMPUTE_USER_DATA_6__DATA__SHIFT', + 'COMPUTE_USER_DATA_7__DATA_MASK', + 'COMPUTE_USER_DATA_7__DATA__SHIFT', + 'COMPUTE_USER_DATA_8__DATA_MASK', + 'COMPUTE_USER_DATA_8__DATA__SHIFT', + 'COMPUTE_USER_DATA_9__DATA_MASK', + 'COMPUTE_USER_DATA_9__DATA__SHIFT', 'COMPUTE_VMID__DATA_MASK', + 'COMPUTE_VMID__DATA__SHIFT', + 'COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK', + 'COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT', + 'COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK', + 'COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT', + 'CONFIG_RESERVED_REG0__DATA_MASK', + 'CONFIG_RESERVED_REG0__DATA__SHIFT', + 'CONFIG_RESERVED_REG1__DATA_MASK', + 'CONFIG_RESERVED_REG1__DATA__SHIFT', + 'CONTEXT_RESERVED_REG0__DATA_MASK', + 'CONTEXT_RESERVED_REG0__DATA__SHIFT', + 'CONTEXT_RESERVED_REG1__DATA_MASK', + 'CONTEXT_RESERVED_REG1__DATA__SHIFT', + 'CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK', + 'CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT', + 'CPC_DDID_CNTL__ENABLE_MASK', 'CPC_DDID_CNTL__ENABLE__SHIFT', + 'CPC_DDID_CNTL__MODE_MASK', 'CPC_DDID_CNTL__MODE__SHIFT', + 'CPC_DDID_CNTL__NO_RING_MEMORY_MASK', + 'CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT', + 'CPC_DDID_CNTL__POLICY_MASK', 'CPC_DDID_CNTL__POLICY__SHIFT', + 'CPC_DDID_CNTL__SIZE_MASK', 'CPC_DDID_CNTL__SIZE__SHIFT', + 'CPC_DDID_CNTL__THRESHOLD_MASK', + 'CPC_DDID_CNTL__THRESHOLD__SHIFT', 'CPC_INT_ADDR__ADDR_MASK', + 'CPC_INT_ADDR__ADDR__SHIFT', + 'CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CPC_INT_CNTX_ID__CNTX_ID_MASK', + 'CPC_INT_CNTX_ID__CNTX_ID__SHIFT', 'CPC_INT_INFO__ADDR_HI_MASK', + 'CPC_INT_INFO__ADDR_HI__SHIFT', 'CPC_INT_INFO__QUEUE_ID_MASK', + 'CPC_INT_INFO__QUEUE_ID__SHIFT', 'CPC_INT_INFO__TYPE_MASK', + 'CPC_INT_INFO__TYPE__SHIFT', 'CPC_INT_INFO__VMID_MASK', + 'CPC_INT_INFO__VMID__SHIFT', 'CPC_INT_PASID__BYPASS_PASID_MASK', + 'CPC_INT_PASID__BYPASS_PASID__SHIFT', 'CPC_INT_PASID__PASID_MASK', + 'CPC_INT_PASID__PASID__SHIFT', + 'CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GPF_INT_STATUS_MASK', + 'CPC_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CPC_LATENCY_STATS_DATA__DATA_MASK', + 'CPC_LATENCY_STATS_DATA__DATA__SHIFT', + 'CPC_LATENCY_STATS_SELECT__CLEAR_MASK', + 'CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT', + 'CPC_LATENCY_STATS_SELECT__ENABLE_MASK', + 'CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT', + 'CPC_LATENCY_STATS_SELECT__INDEX_MASK', + 'CPC_LATENCY_STATS_SELECT__INDEX__SHIFT', + 'CPC_OS_PIPES__OS_PIPES_MASK', 'CPC_OS_PIPES__OS_PIPES__SHIFT', + 'CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CPC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'CPC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'CPC_PSP_DEBUG__GPA_OVERRIDE_MASK', + 'CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT', + 'CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK', + 'CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT', + 'CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK', + 'CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT', + 'CPC_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK', + 'CPC_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT', + 'CPC_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK', + 'CPC_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT', + 'CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK', + 'CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT', + 'CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK', + 'CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT', + 'CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK', + 'CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK', + 'CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT', + 'CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK', + 'CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT', + 'CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK', + 'CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT', + 'CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK', + 'CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT', + 'CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK', + 'CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT', + 'CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK', + 'CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT', + 'CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK', + 'CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT', + 'CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK', + 'CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT', + 'CPC_UTCL1_CNTL__DROP_MODE_MASK', + 'CPC_UTCL1_CNTL__DROP_MODE__SHIFT', + 'CPC_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'CPC_UTCL1_CNTL__INVALIDATE_MASK', + 'CPC_UTCL1_CNTL__INVALIDATE__SHIFT', + 'CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK', + 'CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT', + 'CPC_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'CPC_UTCL1_STATUS__PRT_DETECTED_MASK', + 'CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'CPC_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'CPF_GCR_CNTL__GCR_GL_CMD_MASK', + 'CPF_GCR_CNTL__GCR_GL_CMD__SHIFT', + 'CPF_LATENCY_STATS_DATA__DATA_MASK', + 'CPF_LATENCY_STATS_DATA__DATA__SHIFT', + 'CPF_LATENCY_STATS_SELECT__CLEAR_MASK', + 'CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT', + 'CPF_LATENCY_STATS_SELECT__ENABLE_MASK', + 'CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT', + 'CPF_LATENCY_STATS_SELECT__INDEX_MASK', + 'CPF_LATENCY_STATS_SELECT__INDEX__SHIFT', + 'CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'CPF_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT', + 'CPF_UTCL1_CNTL__DROP_MODE_MASK', + 'CPF_UTCL1_CNTL__DROP_MODE__SHIFT', + 'CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK', + 'CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT', + 'CPF_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'CPF_UTCL1_CNTL__INVALIDATE_MASK', + 'CPF_UTCL1_CNTL__INVALIDATE__SHIFT', + 'CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'CPF_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'CPF_UTCL1_STATUS__PRT_DETECTED_MASK', + 'CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'CPF_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'CPG_LATENCY_STATS_DATA__DATA_MASK', + 'CPG_LATENCY_STATS_DATA__DATA__SHIFT', + 'CPG_LATENCY_STATS_SELECT__CLEAR_MASK', + 'CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT', + 'CPG_LATENCY_STATS_SELECT__ENABLE_MASK', + 'CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT', + 'CPG_LATENCY_STATS_SELECT__INDEX_MASK', + 'CPG_LATENCY_STATS_SELECT__INDEX__SHIFT', + 'CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'CPG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'CPG_PSP_DEBUG__GPA_OVERRIDE_MASK', + 'CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT', + 'CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK', + 'CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT', + 'CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK', + 'CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT', + 'CPG_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK', + 'CPG_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT', + 'CPG_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK', + 'CPG_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT', + 'CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK', + 'CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT', + 'CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK', + 'CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT', + 'CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK', + 'CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT', + 'CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK', + 'CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT', + 'CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK', + 'CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT', + 'CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK', + 'CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT', + 'CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK', + 'CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT', + 'CPG_RCIU_CAM_DATA__DATA_MASK', 'CPG_RCIU_CAM_DATA__DATA__SHIFT', + 'CPG_RCIU_CAM_INDEX__INDEX_MASK', + 'CPG_RCIU_CAM_INDEX__INDEX__SHIFT', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT', + 'CPG_UTCL1_CNTL__DROP_MODE_MASK', + 'CPG_UTCL1_CNTL__DROP_MODE__SHIFT', + 'CPG_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'CPG_UTCL1_CNTL__INVALIDATE_MASK', + 'CPG_UTCL1_CNTL__INVALIDATE__SHIFT', + 'CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK', + 'CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT', + 'CPG_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'CPG_UTCL1_STATUS__PRT_DETECTED_MASK', + 'CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'CPG_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'CP_APPEND_ADDR_HI__CACHE_POLICY_MASK', + 'CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT', + 'CP_APPEND_ADDR_HI__COMMAND_MASK', + 'CP_APPEND_ADDR_HI__COMMAND__SHIFT', + 'CP_APPEND_ADDR_HI__CS_PS_SEL_MASK', + 'CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT', + 'CP_APPEND_ADDR_HI__FENCE_SIZE_MASK', + 'CP_APPEND_ADDR_HI__FENCE_SIZE__SHIFT', + 'CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK', + 'CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT', + 'CP_APPEND_ADDR_HI__PWS_ENABLE_MASK', + 'CP_APPEND_ADDR_HI__PWS_ENABLE__SHIFT', + 'CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK', + 'CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT', + 'CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK', + 'CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT', + 'CP_APPEND_CMD_ADDR_HI__RSVD_MASK', + 'CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT', + 'CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK', + 'CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT', + 'CP_APPEND_CMD_ADDR_LO__RSVD_MASK', + 'CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT', + 'CP_APPEND_DATA_HI__DATA_MASK', 'CP_APPEND_DATA_HI__DATA__SHIFT', + 'CP_APPEND_DATA_LO__DATA_MASK', 'CP_APPEND_DATA_LO__DATA__SHIFT', + 'CP_APPEND_DATA__DATA_MASK', 'CP_APPEND_DATA__DATA__SHIFT', + 'CP_APPEND_DDID_CNT__DATA_MASK', + 'CP_APPEND_DDID_CNT__DATA__SHIFT', + 'CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK', + 'CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK', + 'CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK', + 'CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK', + 'CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK', + 'CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK', + 'CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT', + 'CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK', + 'CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT', + 'CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK', + 'CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT', + 'CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK', + 'CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT', + 'CP_BUSY_STAT__CE_PARSING_PACKETS_MASK', + 'CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT', + 'CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK', + 'CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT', + 'CP_BUSY_STAT__EOP_DONE_BUSY_MASK', + 'CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT', + 'CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK', + 'CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT', + 'CP_BUSY_STAT__ME_PARSER_BUSY_MASK', + 'CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT', + 'CP_BUSY_STAT__ME_PARSING_PACKETS_MASK', + 'CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT', + 'CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK', + 'CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT', + 'CP_BUSY_STAT__PIPE_STATS_BUSY_MASK', + 'CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT', + 'CP_BUSY_STAT__RCIU_CE_BUSY_MASK', + 'CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT', + 'CP_BUSY_STAT__RCIU_ME_BUSY_MASK', + 'CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT', + 'CP_BUSY_STAT__RCIU_PFP_BUSY_MASK', + 'CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT', + 'CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK', + 'CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT', + 'CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK', + 'CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT', + 'CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK', + 'CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT', + 'CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK', + 'CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT', + 'CP_BUSY_STAT__STRM_OUT_BUSY_MASK', + 'CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT', + 'CP_CMD_DATA__CMD_DATA_MASK', 'CP_CMD_DATA__CMD_DATA__SHIFT', + 'CP_CMD_INDEX__CMD_INDEX_MASK', 'CP_CMD_INDEX__CMD_INDEX__SHIFT', + 'CP_CMD_INDEX__CMD_ME_SEL_MASK', + 'CP_CMD_INDEX__CMD_ME_SEL__SHIFT', + 'CP_CMD_INDEX__CMD_QUEUE_SEL_MASK', + 'CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT', + 'CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK', + 'CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT', + 'CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK', + 'CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT', + 'CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK', + 'CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT', + 'CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK', + 'CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT', + 'CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE_MASK', + 'CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT', + 'CP_CPC_BUSY_HYSTERESIS__CPC_BUSY_MASK', + 'CP_CPC_BUSY_HYSTERESIS__CPC_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK', + 'CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT', + 'CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK', + 'CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT', + 'CP_CPC_DEBUG_DATA__DEBUG_DATA_MASK', + 'CP_CPC_DEBUG_DATA__DEBUG_DATA__SHIFT', + 'CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE_MASK', + 'CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE_MASK', + 'CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE__SHIFT', + 'CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE_MASK', + 'CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE__SHIFT', + 'CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS_MASK', + 'CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS__SHIFT', + 'CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK', + 'CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT', + 'CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK', + 'CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT', + 'CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN_MASK', + 'CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT', + 'CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK', + 'CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT', + 'CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK', + 'CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT', + 'CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK', + 'CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT', + 'CP_CPC_DEBUG__ME_SELECT_MASK', 'CP_CPC_DEBUG__ME_SELECT__SHIFT', + 'CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK', + 'CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT', + 'CP_CPC_DEBUG__PIPE_SELECT_MASK', + 'CP_CPC_DEBUG__PIPE_SELECT__SHIFT', + 'CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK', + 'CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT', + 'CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK', + 'CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT', + 'CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK', + 'CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT', + 'CP_CPC_GFX_CNTL__MEID_MASK', 'CP_CPC_GFX_CNTL__MEID__SHIFT', + 'CP_CPC_GFX_CNTL__PIPEID_MASK', 'CP_CPC_GFX_CNTL__PIPEID__SHIFT', + 'CP_CPC_GFX_CNTL__QUEUEID_MASK', + 'CP_CPC_GFX_CNTL__QUEUEID__SHIFT', 'CP_CPC_GFX_CNTL__VALID_MASK', + 'CP_CPC_GFX_CNTL__VALID__SHIFT', + 'CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK', + 'CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT', + 'CP_CPC_HALT_HYST_COUNT__COUNT_MASK', + 'CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT', + 'CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK', + 'CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT', + 'CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK', + 'CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT', + 'CP_CPC_IC_BASE_CNTL__VMID_MASK', + 'CP_CPC_IC_BASE_CNTL__VMID__SHIFT', + 'CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK', + 'CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT', + 'CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK', + 'CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT', + 'CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK', + 'CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT', + 'CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK', + 'CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT', + 'CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK', + 'CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT', + 'CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK', + 'CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT', + 'CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK', + 'CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT', + 'CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK', + 'CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT', + 'CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK', + 'CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT', + 'CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK', + 'CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT', + 'CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK', + 'CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT', + 'CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK', + 'CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT', + 'CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK', + 'CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT', + 'CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK', + 'CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT', + 'CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK', + 'CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT', + 'CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK', + 'CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT', + 'CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK', + 'CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT', + 'CP_CPC_STATUS__CPC_BUSY_MASK', 'CP_CPC_STATUS__CPC_BUSY__SHIFT', + 'CP_CPC_STATUS__CPF_CPC_BUSY_MASK', + 'CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT', + 'CP_CPC_STATUS__CPG_CPC_BUSY_MASK', + 'CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT', + 'CP_CPC_STATUS__DC0_BUSY_MASK', 'CP_CPC_STATUS__DC0_BUSY__SHIFT', + 'CP_CPC_STATUS__DC1_BUSY_MASK', 'CP_CPC_STATUS__DC1_BUSY__SHIFT', + 'CP_CPC_STATUS__GCRIU_BUSY_MASK', + 'CP_CPC_STATUS__GCRIU_BUSY__SHIFT', + 'CP_CPC_STATUS__MEC1_BUSY_MASK', + 'CP_CPC_STATUS__MEC1_BUSY__SHIFT', + 'CP_CPC_STATUS__MEC2_BUSY_MASK', + 'CP_CPC_STATUS__MEC2_BUSY__SHIFT', + 'CP_CPC_STATUS__MEC_DATA_CACHE_BUSY_MASK', + 'CP_CPC_STATUS__MEC_DATA_CACHE_BUSY__SHIFT', + 'CP_CPC_STATUS__MES_BUSY_MASK', 'CP_CPC_STATUS__MES_BUSY__SHIFT', + 'CP_CPC_STATUS__MES_DATA_CACHE_BUSY_MASK', + 'CP_CPC_STATUS__MES_DATA_CACHE_BUSY__SHIFT', + 'CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK', + 'CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT', + 'CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK', + 'CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT', + 'CP_CPC_STATUS__QU_BUSY_MASK', 'CP_CPC_STATUS__QU_BUSY__SHIFT', + 'CP_CPC_STATUS__RCIU1_BUSY_MASK', + 'CP_CPC_STATUS__RCIU1_BUSY__SHIFT', + 'CP_CPC_STATUS__RCIU2_BUSY_MASK', + 'CP_CPC_STATUS__RCIU2_BUSY__SHIFT', + 'CP_CPC_STATUS__RCIU3_BUSY_MASK', + 'CP_CPC_STATUS__RCIU3_BUSY__SHIFT', + 'CP_CPC_STATUS__ROQ1_BUSY_MASK', + 'CP_CPC_STATUS__ROQ1_BUSY__SHIFT', + 'CP_CPC_STATUS__ROQ2_BUSY_MASK', + 'CP_CPC_STATUS__ROQ2_BUSY__SHIFT', + 'CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK', + 'CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT', + 'CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK', + 'CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT', + 'CP_CPC_STATUS__TCIU_BUSY_MASK', + 'CP_CPC_STATUS__TCIU_BUSY__SHIFT', + 'CP_CPC_STATUS__UTCL2IU_BUSY_MASK', + 'CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT', + 'CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK', + 'CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT', + 'CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY_MASK', + 'CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY__SHIFT', + 'CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY_MASK', + 'CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY__SHIFT', + 'CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY_MASK', + 'CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT', + 'CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY_MASK', + 'CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK', + 'CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT', + 'CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK', + 'CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT', + 'CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK', + 'CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK', + 'CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT', + 'CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK', + 'CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK', + 'CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT', + 'CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT', + 'CP_CPF_STATUS__CPC_CPF_BUSY_MASK', + 'CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT', + 'CP_CPF_STATUS__CPF_BUSY_MASK', 'CP_CPF_STATUS__CPF_BUSY__SHIFT', + 'CP_CPF_STATUS__CPF_CMP_BUSY_MASK', + 'CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT', + 'CP_CPF_STATUS__CPF_GFX_BUSY_MASK', + 'CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT', + 'CP_CPF_STATUS__CSF_BUSY_MASK', 'CP_CPF_STATUS__CSF_BUSY__SHIFT', + 'CP_CPF_STATUS__GCRIU_BUSY_MASK', + 'CP_CPF_STATUS__GCRIU_BUSY__SHIFT', + 'CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK', + 'CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT', + 'CP_CPF_STATUS__HQD_BUSY_MASK', 'CP_CPF_STATUS__HQD_BUSY__SHIFT', + 'CP_CPF_STATUS__INTERRUPT_BUSY_MASK', + 'CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT', + 'CP_CPF_STATUS__MES_HQD_BUSY_MASK', + 'CP_CPF_STATUS__MES_HQD_BUSY__SHIFT', + 'CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK', + 'CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT', + 'CP_CPF_STATUS__PRT_BUSY_MASK', 'CP_CPF_STATUS__PRT_BUSY__SHIFT', + 'CP_CPF_STATUS__RCIU_BUSY_MASK', + 'CP_CPF_STATUS__RCIU_BUSY__SHIFT', + 'CP_CPF_STATUS__RCIU_CMP_BUSY_MASK', + 'CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT', + 'CP_CPF_STATUS__RCIU_GFX_BUSY_MASK', + 'CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_DATA_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_RING_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_STATE_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT', + 'CP_CPF_STATUS__SEMAPHORE_BUSY_MASK', + 'CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT', + 'CP_CPF_STATUS__TCIU_BUSY_MASK', + 'CP_CPF_STATUS__TCIU_BUSY__SHIFT', + 'CP_CPF_STATUS__UTCL2IU_BUSY_MASK', + 'CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT', + 'CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK', + 'CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT', + 'CP_CPG_BUSY_HYSTERESIS1__CP_BUSY_MASK', + 'CP_CPG_BUSY_HYSTERESIS1__CP_BUSY__SHIFT', + 'CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY_MASK', + 'CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY__SHIFT', + 'CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY_MASK', + 'CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT', + 'CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY_MASK', + 'CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT', + 'CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0_MASK', + 'CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0__SHIFT', + 'CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1_MASK', + 'CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1__SHIFT', + 'CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK', + 'CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT', + 'CP_CU_MASK_ADDR_HI__ADDR_HI_MASK', + 'CP_CU_MASK_ADDR_HI__ADDR_HI__SHIFT', + 'CP_CU_MASK_ADDR_LO__ADDR_LO_MASK', + 'CP_CU_MASK_ADDR_LO__ADDR_LO__SHIFT', + 'CP_CU_MASK_CNTL__POLICY_MASK', 'CP_CU_MASK_CNTL__POLICY__SHIFT', + 'CP_DB_BASE_HI__DB_BASE_HI_MASK', + 'CP_DB_BASE_HI__DB_BASE_HI__SHIFT', + 'CP_DB_BASE_LO__DB_BASE_LO_MASK', + 'CP_DB_BASE_LO__DB_BASE_LO__SHIFT', 'CP_DB_BUFSZ__DB_BUFSZ_MASK', + 'CP_DB_BUFSZ__DB_BUFSZ__SHIFT', + 'CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK', + 'CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT', + 'CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK', + 'CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT', + 'CP_DDID_CNTL__ENABLE_MASK', 'CP_DDID_CNTL__ENABLE__SHIFT', + 'CP_DDID_CNTL__MODE_MASK', 'CP_DDID_CNTL__MODE__SHIFT', + 'CP_DDID_CNTL__NO_RING_MEMORY_MASK', + 'CP_DDID_CNTL__NO_RING_MEMORY__SHIFT', + 'CP_DDID_CNTL__POLICY_MASK', 'CP_DDID_CNTL__POLICY__SHIFT', + 'CP_DDID_CNTL__SIZE_MASK', 'CP_DDID_CNTL__SIZE__SHIFT', + 'CP_DDID_CNTL__THRESHOLD_MASK', 'CP_DDID_CNTL__THRESHOLD__SHIFT', + 'CP_DDID_CNTL__VMID_MASK', 'CP_DDID_CNTL__VMID_SEL_MASK', + 'CP_DDID_CNTL__VMID_SEL__SHIFT', 'CP_DDID_CNTL__VMID__SHIFT', + 'CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE_MASK', + 'CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE__SHIFT', + 'CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE_MASK', + 'CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE__SHIFT', + 'CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE_MASK', + 'CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE__SHIFT', + 'CP_DEBUG_2__DC_DISABLE_BROADCAST_MASK', + 'CP_DEBUG_2__DC_DISABLE_BROADCAST__SHIFT', + 'CP_DEBUG_2__DC_FORCE_CLK_EN_MASK', + 'CP_DEBUG_2__DC_FORCE_CLK_EN__SHIFT', + 'CP_DEBUG_2__DC_INTERLEAVE_DISABLE_MASK', + 'CP_DEBUG_2__DC_INTERLEAVE_DISABLE__SHIFT', + 'CP_DEBUG_2__NOP_DISCARD_DISABLE_MASK', + 'CP_DEBUG_2__NOP_DISCARD_DISABLE__SHIFT', + 'CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE_MASK', + 'CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE__SHIFT', + 'CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE_MASK', + 'CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE__SHIFT', + 'CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE_MASK', + 'CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE__SHIFT', + 'CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE_MASK', + 'CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE__SHIFT', + 'CP_DEBUG_CNTL__DEBUG_INDX_MASK', + 'CP_DEBUG_CNTL__DEBUG_INDX__SHIFT', + 'CP_DEBUG_DATA__DEBUG_DATA_MASK', + 'CP_DEBUG_DATA__DEBUG_DATA__SHIFT', + 'CP_DEBUG__CPG_CHIU_GUS_DISABLE_MASK', + 'CP_DEBUG__CPG_CHIU_GUS_DISABLE__SHIFT', + 'CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE_MASK', + 'CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE__SHIFT', + 'CP_DEBUG__CPG_CHIU_RO_DISABLE_MASK', + 'CP_DEBUG__CPG_CHIU_RO_DISABLE__SHIFT', + 'CP_DEBUG__CPG_GCR_CNTL_BYPASS_MASK', + 'CP_DEBUG__CPG_GCR_CNTL_BYPASS__SHIFT', + 'CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK', + 'CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT', + 'CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK', + 'CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT', + 'CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK', + 'CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT', + 'CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE_MASK', + 'CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE__SHIFT', + 'CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK', + 'CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT', + 'CP_DEBUG__CS_STATE_FILT_DISABLE_MASK', + 'CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT', + 'CP_DEBUG__DEBUG_BUS_FLOP_EN_MASK', + 'CP_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT', + 'CP_DEBUG__DEBUG_BUS_SELECT_BITS_MASK', + 'CP_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT', + 'CP_DEBUG__EVENT_FILT_DISABLE_MASK', + 'CP_DEBUG__EVENT_FILT_DISABLE__SHIFT', + 'CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK', + 'CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT', + 'CP_DEBUG__INTERRUPT_DISABLE_MASK', + 'CP_DEBUG__INTERRUPT_DISABLE__SHIFT', + 'CP_DEBUG__NOT_EOP_PREEMPT_DISABLE_MASK', + 'CP_DEBUG__NOT_EOP_PREEMPT_DISABLE__SHIFT', + 'CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK', + 'CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT', + 'CP_DEBUG__PACKET_FILTER_DISABLE_MASK', + 'CP_DEBUG__PACKET_FILTER_DISABLE__SHIFT', + 'CP_DEBUG__PERFMON_RING_SEL_MASK', + 'CP_DEBUG__PERFMON_RING_SEL__SHIFT', + 'CP_DEBUG__PREDICATE_DISABLE_MASK', + 'CP_DEBUG__PREDICATE_DISABLE__SHIFT', + 'CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK', + 'CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT', + 'CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK', + 'CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT', + 'CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK', + 'CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT', + 'CP_DEVICE_ID__DEVICE_ID_MASK', 'CP_DEVICE_ID__DEVICE_ID__SHIFT', + 'CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK', + 'CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK', + 'CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT', + 'CP_DMA_CNTL__BUFFER_DEPTH_MASK', + 'CP_DMA_CNTL__BUFFER_DEPTH__SHIFT', + 'CP_DMA_CNTL__MIN_AVAILSZ_MASK', + 'CP_DMA_CNTL__MIN_AVAILSZ__SHIFT', 'CP_DMA_CNTL__PIO_COUNT_MASK', + 'CP_DMA_CNTL__PIO_COUNT__SHIFT', + 'CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK', + 'CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT', + 'CP_DMA_CNTL__PIO_FIFO_FULL_MASK', + 'CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT', + 'CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK', + 'CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT', + 'CP_DMA_CNTL__WATCH_CONTROL_MASK', + 'CP_DMA_CNTL__WATCH_CONTROL__SHIFT', + 'CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK', + 'CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK', + 'CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT', + 'CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK', + 'CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK', + 'CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT', + 'CP_DMA_ME_COMMAND__BYTE_COUNT_MASK', + 'CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT', + 'CP_DMA_ME_COMMAND__DAIC_MASK', 'CP_DMA_ME_COMMAND__DAIC__SHIFT', + 'CP_DMA_ME_COMMAND__DAS_MASK', 'CP_DMA_ME_COMMAND__DAS__SHIFT', + 'CP_DMA_ME_COMMAND__DIS_WC_MASK', + 'CP_DMA_ME_COMMAND__DIS_WC__SHIFT', + 'CP_DMA_ME_COMMAND__RAW_WAIT_MASK', + 'CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT', + 'CP_DMA_ME_COMMAND__SAIC_MASK', 'CP_DMA_ME_COMMAND__SAIC__SHIFT', + 'CP_DMA_ME_COMMAND__SAS_MASK', 'CP_DMA_ME_COMMAND__SAS__SHIFT', + 'CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK', + 'CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT', + 'CP_DMA_ME_CONTROL__DST_SELECT_MASK', + 'CP_DMA_ME_CONTROL__DST_SELECT__SHIFT', + 'CP_DMA_ME_CONTROL__DST_VOLATLE_MASK', + 'CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT', + 'CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK', + 'CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT', + 'CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK', + 'CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT', + 'CP_DMA_ME_CONTROL__SRC_SELECT_MASK', + 'CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT', + 'CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK', + 'CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT', + 'CP_DMA_ME_CONTROL__TMZ_MASK', 'CP_DMA_ME_CONTROL__TMZ__SHIFT', + 'CP_DMA_ME_CONTROL__VMID_MASK', 'CP_DMA_ME_CONTROL__VMID__SHIFT', + 'CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK', + 'CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT', + 'CP_DMA_ME_DST_ADDR__DST_ADDR_MASK', + 'CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT', + 'CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK', + 'CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT', + 'CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK', + 'CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT', + 'CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK', + 'CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK', + 'CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT', + 'CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK', + 'CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK', + 'CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT', + 'CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK', + 'CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT', + 'CP_DMA_PFP_COMMAND__DAIC_MASK', + 'CP_DMA_PFP_COMMAND__DAIC__SHIFT', 'CP_DMA_PFP_COMMAND__DAS_MASK', + 'CP_DMA_PFP_COMMAND__DAS__SHIFT', + 'CP_DMA_PFP_COMMAND__DIS_WC_MASK', + 'CP_DMA_PFP_COMMAND__DIS_WC__SHIFT', + 'CP_DMA_PFP_COMMAND__RAW_WAIT_MASK', + 'CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT', + 'CP_DMA_PFP_COMMAND__SAIC_MASK', + 'CP_DMA_PFP_COMMAND__SAIC__SHIFT', 'CP_DMA_PFP_COMMAND__SAS_MASK', + 'CP_DMA_PFP_COMMAND__SAS__SHIFT', + 'CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK', + 'CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT', + 'CP_DMA_PFP_CONTROL__DST_SELECT_MASK', + 'CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT', + 'CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK', + 'CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT', + 'CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK', + 'CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT', + 'CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK', + 'CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT', + 'CP_DMA_PFP_CONTROL__SRC_SELECT_MASK', + 'CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT', + 'CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK', + 'CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT', + 'CP_DMA_PFP_CONTROL__TMZ_MASK', 'CP_DMA_PFP_CONTROL__TMZ__SHIFT', + 'CP_DMA_PFP_CONTROL__VMID_MASK', + 'CP_DMA_PFP_CONTROL__VMID__SHIFT', + 'CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK', + 'CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT', + 'CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK', + 'CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT', + 'CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK', + 'CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT', + 'CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK', + 'CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT', + 'CP_DMA_READ_TAGS__DMA_READ_TAG_MASK', + 'CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK', + 'CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT', + 'CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT', + 'CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK', + 'CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DMA_WATCH0_ADDR_HI__RSVD_MASK', + 'CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT', + 'CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK', + 'CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DMA_WATCH0_ADDR_LO__RSVD_MASK', + 'CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT', + 'CP_DMA_WATCH0_CNTL__ANY_VMID_MASK', + 'CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT', + 'CP_DMA_WATCH0_CNTL__RSVD1_MASK', + 'CP_DMA_WATCH0_CNTL__RSVD1__SHIFT', + 'CP_DMA_WATCH0_CNTL__RSVD2_MASK', + 'CP_DMA_WATCH0_CNTL__RSVD2__SHIFT', + 'CP_DMA_WATCH0_CNTL__VMID_MASK', + 'CP_DMA_WATCH0_CNTL__VMID__SHIFT', + 'CP_DMA_WATCH0_CNTL__WATCH_READS_MASK', + 'CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT', + 'CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK', + 'CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT', + 'CP_DMA_WATCH0_MASK__MASK_MASK', + 'CP_DMA_WATCH0_MASK__MASK__SHIFT', + 'CP_DMA_WATCH0_MASK__RSVD_MASK', + 'CP_DMA_WATCH0_MASK__RSVD__SHIFT', + 'CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK', + 'CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DMA_WATCH1_ADDR_HI__RSVD_MASK', + 'CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT', + 'CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK', + 'CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DMA_WATCH1_ADDR_LO__RSVD_MASK', + 'CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT', + 'CP_DMA_WATCH1_CNTL__ANY_VMID_MASK', + 'CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT', + 'CP_DMA_WATCH1_CNTL__RSVD1_MASK', + 'CP_DMA_WATCH1_CNTL__RSVD1__SHIFT', + 'CP_DMA_WATCH1_CNTL__RSVD2_MASK', + 'CP_DMA_WATCH1_CNTL__RSVD2__SHIFT', + 'CP_DMA_WATCH1_CNTL__VMID_MASK', + 'CP_DMA_WATCH1_CNTL__VMID__SHIFT', + 'CP_DMA_WATCH1_CNTL__WATCH_READS_MASK', + 'CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT', + 'CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK', + 'CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT', + 'CP_DMA_WATCH1_MASK__MASK_MASK', + 'CP_DMA_WATCH1_MASK__MASK__SHIFT', + 'CP_DMA_WATCH1_MASK__RSVD_MASK', + 'CP_DMA_WATCH1_MASK__RSVD__SHIFT', + 'CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK', + 'CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DMA_WATCH2_ADDR_HI__RSVD_MASK', + 'CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT', + 'CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK', + 'CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DMA_WATCH2_ADDR_LO__RSVD_MASK', + 'CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT', + 'CP_DMA_WATCH2_CNTL__ANY_VMID_MASK', + 'CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT', + 'CP_DMA_WATCH2_CNTL__RSVD1_MASK', + 'CP_DMA_WATCH2_CNTL__RSVD1__SHIFT', + 'CP_DMA_WATCH2_CNTL__RSVD2_MASK', + 'CP_DMA_WATCH2_CNTL__RSVD2__SHIFT', + 'CP_DMA_WATCH2_CNTL__VMID_MASK', + 'CP_DMA_WATCH2_CNTL__VMID__SHIFT', + 'CP_DMA_WATCH2_CNTL__WATCH_READS_MASK', + 'CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT', + 'CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK', + 'CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT', + 'CP_DMA_WATCH2_MASK__MASK_MASK', + 'CP_DMA_WATCH2_MASK__MASK__SHIFT', + 'CP_DMA_WATCH2_MASK__RSVD_MASK', + 'CP_DMA_WATCH2_MASK__RSVD__SHIFT', + 'CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK', + 'CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DMA_WATCH3_ADDR_HI__RSVD_MASK', + 'CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT', + 'CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK', + 'CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DMA_WATCH3_ADDR_LO__RSVD_MASK', + 'CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT', + 'CP_DMA_WATCH3_CNTL__ANY_VMID_MASK', + 'CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT', + 'CP_DMA_WATCH3_CNTL__RSVD1_MASK', + 'CP_DMA_WATCH3_CNTL__RSVD1__SHIFT', + 'CP_DMA_WATCH3_CNTL__RSVD2_MASK', + 'CP_DMA_WATCH3_CNTL__RSVD2__SHIFT', + 'CP_DMA_WATCH3_CNTL__VMID_MASK', + 'CP_DMA_WATCH3_CNTL__VMID__SHIFT', + 'CP_DMA_WATCH3_CNTL__WATCH_READS_MASK', + 'CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT', + 'CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK', + 'CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT', + 'CP_DMA_WATCH3_MASK__MASK_MASK', + 'CP_DMA_WATCH3_MASK__MASK__SHIFT', + 'CP_DMA_WATCH3_MASK__RSVD_MASK', + 'CP_DMA_WATCH3_MASK__RSVD__SHIFT', + 'CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK', + 'CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK', + 'CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DMA_WATCH_STAT__CLIENT_ID_MASK', + 'CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT', + 'CP_DMA_WATCH_STAT__PIPE_MASK', 'CP_DMA_WATCH_STAT__PIPE__SHIFT', + 'CP_DMA_WATCH_STAT__QUEUE_ID_MASK', + 'CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT', + 'CP_DMA_WATCH_STAT__RD_WR_MASK', + 'CP_DMA_WATCH_STAT__RD_WR__SHIFT', + 'CP_DMA_WATCH_STAT__TRAP_FLAG_MASK', + 'CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT', + 'CP_DMA_WATCH_STAT__VMID_MASK', 'CP_DMA_WATCH_STAT__VMID__SHIFT', + 'CP_DMA_WATCH_STAT__WATCH_ID_MASK', + 'CP_DMA_WATCH_STAT__WATCH_ID__SHIFT', + 'CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK', + 'CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK', + 'CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT', + 'CP_DRAW_OBJECT_COUNTER__COUNT_MASK', + 'CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT', + 'CP_DRAW_OBJECT__OBJECT_MASK', 'CP_DRAW_OBJECT__OBJECT__SHIFT', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT', + 'CP_DRAW_WINDOW_CNTL__MODE_MASK', + 'CP_DRAW_WINDOW_CNTL__MODE__SHIFT', + 'CP_DRAW_WINDOW_HI__WINDOW_HI_MASK', + 'CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT', + 'CP_DRAW_WINDOW_LO__MAX_MASK', 'CP_DRAW_WINDOW_LO__MAX__SHIFT', + 'CP_DRAW_WINDOW_LO__MIN_MASK', 'CP_DRAW_WINDOW_LO__MIN__SHIFT', + 'CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK', + 'CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK', + 'CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK', + 'CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK', + 'CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK', + 'CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__ME_MASK', + 'CP_ECC_FIRSTOCCURRENCE__ME__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__PIPE_MASK', + 'CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__VMID_MASK', + 'CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT', + 'CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK', + 'CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT', + 'CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK', + 'CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT', + 'CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK', + 'CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK', + 'CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT', + 'CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK', + 'CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK', + 'CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK', + 'CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK', + 'CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK', + 'CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK', + 'CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE_MASK', + 'CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE__SHIFT', + 'CP_EOP_DONE_DATA_HI__DATA_HI_MASK', + 'CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT', + 'CP_EOP_DONE_DATA_LO__DATA_LO_MASK', + 'CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK', + 'CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK', + 'CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK', + 'CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK', + 'CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__GLK_INV_MASK', + 'CP_EOP_DONE_EVENT_CNTL__GLK_INV__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE_MASK', + 'CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE__SHIFT', + 'CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK', + 'CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT', + 'CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK', + 'CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT', + 'CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK', + 'CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT', + 'CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK', + 'CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT', + 'CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK', + 'CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT', + 'CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK', + 'CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT', + 'CP_FATAL_ERROR__GFX_HALT_PROC_MASK', + 'CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT', + 'CP_FETCHER_SOURCE__ME_SRC_MASK', + 'CP_FETCHER_SOURCE__ME_SRC__SHIFT', + 'CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK', + 'CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT', + 'CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK', + 'CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT', + 'CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK', + 'CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT', + 'CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK', + 'CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT', + 'CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK', + 'CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT', + 'CP_GDS_BKUP_ADDR__ADDR_LO_MASK', + 'CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT', + 'CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI_MASK', + 'CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI__SHIFT', + 'CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO_MASK', + 'CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO__SHIFT', + 'CP_GFX_CNTL__CONFIG_MASK', 'CP_GFX_CNTL__CONFIG__SHIFT', + 'CP_GFX_CNTL__ENGINE_SEL_MASK', 'CP_GFX_CNTL__ENGINE_SEL__SHIFT', + 'CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK', + 'CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT', + 'CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK', + 'CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT', + 'CP_GFX_DDID_RPTR__COUNT_MASK', 'CP_GFX_DDID_RPTR__COUNT__SHIFT', + 'CP_GFX_DDID_WPTR__COUNT_MASK', 'CP_GFX_DDID_WPTR__COUNT__SHIFT', + 'CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__RESERVED_MASK', 'CP_GFX_ERROR__RESERVED__SHIFT', + 'CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__SUA_ERROR_MASK', 'CP_GFX_ERROR__SUA_ERROR__SHIFT', + 'CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT', + 'CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK', + 'CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT', + 'CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL_MASK', + 'CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL__SHIFT', + 'CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK', + 'CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT', + 'CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK', + 'CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK', + 'CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT', + 'CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK', + 'CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT', + 'CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK', + 'CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT', + 'CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK', + 'CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT', + 'CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK', + 'CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT', + 'CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK', + 'CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT', + 'CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK', + 'CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK', + 'CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT', + 'CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT', + 'CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK', + 'CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT', + 'CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK', + 'CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT', + 'CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK', + 'CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT', + 'CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK', + 'CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT', + 'CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK', + 'CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT', + 'CP_GFX_HQD_ACTIVE__ACTIVE_MASK', + 'CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT', + 'CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK', + 'CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT', + 'CP_GFX_HQD_BASE__RB_BASE_MASK', + 'CP_GFX_HQD_BASE__RB_BASE__SHIFT', + 'CP_GFX_HQD_CNTL__BUF_SWAP_MASK', + 'CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT', + 'CP_GFX_HQD_CNTL__CACHE_POLICY_MASK', + 'CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT', + 'CP_GFX_HQD_CNTL__KMD_QUEUE_MASK', + 'CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT', + 'CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK', + 'CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT', + 'CP_GFX_HQD_CNTL__RB_BLKSZ_MASK', + 'CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT', + 'CP_GFX_HQD_CNTL__RB_BUFSZ_MASK', + 'CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT', + 'CP_GFX_HQD_CNTL__RB_EXE_MASK', 'CP_GFX_HQD_CNTL__RB_EXE__SHIFT', + 'CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK', + 'CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT', + 'CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK', + 'CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_GFX_HQD_CNTL__RB_VOLATILE_MASK', + 'CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT', + 'CP_GFX_HQD_CNTL__TMZ_MATCH_MASK', + 'CP_GFX_HQD_CNTL__TMZ_MATCH__SHIFT', + 'CP_GFX_HQD_CNTL__TMZ_STATE_MASK', + 'CP_GFX_HQD_CNTL__TMZ_STATE__SHIFT', + 'CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK', + 'CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT', + 'CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK', + 'CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT', + 'CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK', + 'CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT', + 'CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK', + 'CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT', + 'CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK', + 'CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT', + 'CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK', + 'CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT', + 'CP_GFX_HQD_HQ_CONTROL0__SPARES_MASK', + 'CP_GFX_HQD_HQ_CONTROL0__SPARES__SHIFT', + 'CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK', + 'CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT', + 'CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK', + 'CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT', + 'CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK', + 'CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT', + 'CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK', + 'CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__ACTIVE_MASK', + 'CP_GFX_HQD_IQ_TIMER__ACTIVE__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT_MASK', + 'CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK', + 'CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK', + 'CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER_MASK', + 'CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE_MASK', + 'CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__REARM_TIMER_MASK', + 'CP_GFX_HQD_IQ_TIMER__REARM_TIMER__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__RETRY_TYPE_MASK', + 'CP_GFX_HQD_IQ_TIMER__RETRY_TYPE__SHIFT', + 'CP_GFX_HQD_IQ_TIMER__WAIT_TIME_MASK', + 'CP_GFX_HQD_IQ_TIMER__WAIT_TIME__SHIFT', + 'CP_GFX_HQD_MAPPED__MAPPED_MASK', + 'CP_GFX_HQD_MAPPED__MAPPED__SHIFT', + 'CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK', + 'CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT', + 'CP_GFX_HQD_OFFSET__RB_OFFSET_MASK', + 'CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT', + 'CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK', + 'CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT', + 'CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK', + 'CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT', + 'CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK', + 'CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT', + 'CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK', + 'CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT', + 'CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK', + 'CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE__SHIFT', + 'CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE_MASK', + 'CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE__SHIFT', + 'CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_GFX_HQD_RPTR__RB_RPTR_MASK', + 'CP_GFX_HQD_RPTR__RB_RPTR__SHIFT', 'CP_GFX_HQD_VMID__VMID_MASK', + 'CP_GFX_HQD_VMID__VMID__SHIFT', + 'CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK', + 'CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT', + 'CP_GFX_HQD_WPTR__RB_WPTR_MASK', + 'CP_GFX_HQD_WPTR__RB_WPTR__SHIFT', + 'CP_GFX_INDEX_MUTEX__CLIENTID_MASK', + 'CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT', + 'CP_GFX_INDEX_MUTEX__REQUEST_MASK', + 'CP_GFX_INDEX_MUTEX__REQUEST__SHIFT', + 'CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK', + 'CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT', + 'CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK', + 'CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT', + 'CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK', + 'CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT', + 'CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK', + 'CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT', + 'CP_GFX_MQD_CONTROL__PRIV_STATE_MASK', + 'CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT', + 'CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK', + 'CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT', + 'CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK', + 'CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT', + 'CP_GFX_MQD_CONTROL__VMID_MASK', + 'CP_GFX_MQD_CONTROL__VMID__SHIFT', + 'CP_GFX_QUEUE_INDEX__PIPE_ID_MASK', + 'CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT', + 'CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK', + 'CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT', + 'CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK', + 'CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE0_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE0_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE0_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE0_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE0_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE10_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE10_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE10_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE10_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE10_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE11_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE11_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE11_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE11_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE11_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE12_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE12_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE12_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE12_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE12_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE13_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE13_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE13_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE13_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE13_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE14_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE14_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE14_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE14_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE14_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE15_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE15_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE15_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE15_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE15_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE1_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE1_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE1_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE1_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE1_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE2_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE2_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE2_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE2_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE2_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE3_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE3_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE3_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE3_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE3_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE4_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE4_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE4_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE4_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE4_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE5_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE5_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE5_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE5_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE5_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE6_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE6_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE6_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE6_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE6_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE7_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE7_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE7_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE7_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE7_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE8_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE8_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE8_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE8_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE8_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_BASE0__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE9_BASE0__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_BASE1__BASE_MASK', + 'CP_GFX_RS64_DC_APERTURE9_BASE1__BASE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE_MASK', + 'CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID_MASK', + 'CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_MASK0__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE9_MASK0__MASK__SHIFT', + 'CP_GFX_RS64_DC_APERTURE9_MASK1__MASK_MASK', + 'CP_GFX_RS64_DC_APERTURE9_MASK1__MASK__SHIFT', + 'CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI_MASK', + 'CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI__SHIFT', + 'CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO_MASK', + 'CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO__SHIFT', + 'CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI_MASK', + 'CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI__SHIFT', + 'CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO_MASK', + 'CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO__SHIFT', + 'CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_GFX_RS64_DC_BASE_CNTL__VMID_MASK', + 'CP_GFX_RS64_DC_BASE_CNTL__VMID__SHIFT', + 'CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL_MASK', + 'CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL__SHIFT', + 'CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED_MASK', + 'CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED__SHIFT', + 'CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK', + 'CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT', + 'CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_MASK', + 'CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT', + 'CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE_MASK', + 'CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE__SHIFT', + 'CP_GFX_RS64_DC_OP_CNTL__RESERVED_MASK', + 'CP_GFX_RS64_DC_OP_CNTL__RESERVED__SHIFT', + 'CP_GFX_RS64_DM_INDEX_ADDR__ADDR_MASK', + 'CP_GFX_RS64_DM_INDEX_ADDR__ADDR__SHIFT', + 'CP_GFX_RS64_DM_INDEX_DATA__DATA_MASK', + 'CP_GFX_RS64_DM_INDEX_DATA__DATA__SHIFT', + 'CP_GFX_RS64_GP0_HI0__M_RET_ADDR_MASK', + 'CP_GFX_RS64_GP0_HI0__M_RET_ADDR__SHIFT', + 'CP_GFX_RS64_GP0_HI1__M_RET_ADDR_MASK', + 'CP_GFX_RS64_GP0_HI1__M_RET_ADDR__SHIFT', + 'CP_GFX_RS64_GP0_LO0__DATA_MASK', + 'CP_GFX_RS64_GP0_LO0__DATA__SHIFT', + 'CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED_MASK', + 'CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED__SHIFT', + 'CP_GFX_RS64_GP0_LO1__DATA_MASK', + 'CP_GFX_RS64_GP0_LO1__DATA__SHIFT', + 'CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED_MASK', + 'CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED__SHIFT', + 'CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI_MASK', + 'CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI__SHIFT', + 'CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI_MASK', + 'CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI__SHIFT', + 'CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO_MASK', + 'CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO__SHIFT', + 'CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO_MASK', + 'CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO__SHIFT', + 'CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI_MASK', + 'CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI__SHIFT', + 'CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI_MASK', + 'CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI__SHIFT', + 'CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO_MASK', + 'CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO__SHIFT', + 'CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO_MASK', + 'CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO__SHIFT', + 'CP_GFX_RS64_GP3_HI0__DATA_MASK', + 'CP_GFX_RS64_GP3_HI0__DATA__SHIFT', + 'CP_GFX_RS64_GP3_HI1__DATA_MASK', + 'CP_GFX_RS64_GP3_HI1__DATA__SHIFT', + 'CP_GFX_RS64_GP3_LO0__DATA_MASK', + 'CP_GFX_RS64_GP3_LO0__DATA__SHIFT', + 'CP_GFX_RS64_GP3_LO1__DATA_MASK', + 'CP_GFX_RS64_GP3_LO1__DATA__SHIFT', + 'CP_GFX_RS64_GP4_HI0__DATA_MASK', + 'CP_GFX_RS64_GP4_HI0__DATA__SHIFT', + 'CP_GFX_RS64_GP4_HI1__DATA_MASK', + 'CP_GFX_RS64_GP4_HI1__DATA__SHIFT', + 'CP_GFX_RS64_GP4_LO0__DATA_MASK', + 'CP_GFX_RS64_GP4_LO0__DATA__SHIFT', + 'CP_GFX_RS64_GP4_LO1__DATA_MASK', + 'CP_GFX_RS64_GP4_LO1__DATA__SHIFT', + 'CP_GFX_RS64_GP5_HI0__M_RET_ADDR_MASK', + 'CP_GFX_RS64_GP5_HI0__M_RET_ADDR__SHIFT', + 'CP_GFX_RS64_GP5_HI1__M_RET_ADDR_MASK', + 'CP_GFX_RS64_GP5_HI1__M_RET_ADDR__SHIFT', + 'CP_GFX_RS64_GP5_LO0__DATA_MASK', + 'CP_GFX_RS64_GP5_LO0__DATA__SHIFT', + 'CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED_MASK', + 'CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED__SHIFT', + 'CP_GFX_RS64_GP5_LO1__DATA_MASK', + 'CP_GFX_RS64_GP5_LO1__DATA__SHIFT', + 'CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED_MASK', + 'CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED__SHIFT', + 'CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI_MASK', + 'CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI__SHIFT', + 'CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO_MASK', + 'CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO__SHIFT', + 'CP_GFX_RS64_GP7_HI__STACK_PNTR_HI_MASK', + 'CP_GFX_RS64_GP7_HI__STACK_PNTR_HI__SHIFT', + 'CP_GFX_RS64_GP7_LO__STACK_PNTR_LO_MASK', + 'CP_GFX_RS64_GP7_LO__STACK_PNTR_LO__SHIFT', + 'CP_GFX_RS64_GP8_HI__DATA_MASK', + 'CP_GFX_RS64_GP8_HI__DATA__SHIFT', + 'CP_GFX_RS64_GP8_LO__DATA_MASK', + 'CP_GFX_RS64_GP8_LO__DATA__SHIFT', + 'CP_GFX_RS64_GP9_HI__DATA_MASK', + 'CP_GFX_RS64_GP9_HI__DATA__SHIFT', + 'CP_GFX_RS64_GP9_LO__DATA_MASK', + 'CP_GFX_RS64_GP9_LO__DATA__SHIFT', + 'CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR_MASK', + 'CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR__SHIFT', + 'CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR_MASK', + 'CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR__SHIFT', + 'CP_GFX_RS64_INTERRUPT0__ME_INT_MASK', + 'CP_GFX_RS64_INTERRUPT0__ME_INT__SHIFT', + 'CP_GFX_RS64_INTERRUPT1__ME_INT_MASK', + 'CP_GFX_RS64_INTERRUPT1__ME_INT__SHIFT', + 'CP_GFX_RS64_INTR_EN0__ME_INT_MASK', + 'CP_GFX_RS64_INTR_EN0__ME_INT__SHIFT', + 'CP_GFX_RS64_INTR_EN1__ME_INT_MASK', + 'CP_GFX_RS64_INTR_EN1__ME_INT__SHIFT', + 'CP_GFX_RS64_LOCAL_APERTURE__APERTURE_MASK', + 'CP_GFX_RS64_LOCAL_APERTURE__APERTURE__SHIFT', + 'CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI_MASK', + 'CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI__SHIFT', + 'CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO_MASK', + 'CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO__SHIFT', + 'CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE_MASK', + 'CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE__SHIFT', + 'CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI_MASK', + 'CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT', + 'CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO_MASK', + 'CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT', + 'CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI_MASK', + 'CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT', + 'CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO_MASK', + 'CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT', + 'CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI_MASK', + 'CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI__SHIFT', + 'CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO_MASK', + 'CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO__SHIFT', + 'CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE_MASK', + 'CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT', + 'CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK', + 'CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT', + 'CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK', + 'CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT', + 'CP_GFX_RS64_MIBOUND_HI__BOUND_MASK', + 'CP_GFX_RS64_MIBOUND_HI__BOUND__SHIFT', + 'CP_GFX_RS64_MIBOUND_LO__BOUND_MASK', + 'CP_GFX_RS64_MIBOUND_LO__BOUND__SHIFT', + 'CP_GFX_RS64_MIP_HI0__MIP_HI_MASK', + 'CP_GFX_RS64_MIP_HI0__MIP_HI__SHIFT', + 'CP_GFX_RS64_MIP_HI1__MIP_HI_MASK', + 'CP_GFX_RS64_MIP_HI1__MIP_HI__SHIFT', + 'CP_GFX_RS64_MIP_LO0__MIP_LO_MASK', + 'CP_GFX_RS64_MIP_LO0__MIP_LO__SHIFT', + 'CP_GFX_RS64_MIP_LO1__MIP_LO_MASK', + 'CP_GFX_RS64_MIP_LO1__MIP_LO__SHIFT', + 'CP_GFX_RS64_MTIMECMP_HI0__TIME_HI_MASK', + 'CP_GFX_RS64_MTIMECMP_HI0__TIME_HI__SHIFT', + 'CP_GFX_RS64_MTIMECMP_HI1__TIME_HI_MASK', + 'CP_GFX_RS64_MTIMECMP_HI1__TIME_HI__SHIFT', + 'CP_GFX_RS64_MTIMECMP_LO0__TIME_LO_MASK', + 'CP_GFX_RS64_MTIMECMP_LO0__TIME_LO__SHIFT', + 'CP_GFX_RS64_MTIMECMP_LO1__TIME_LO_MASK', + 'CP_GFX_RS64_MTIMECMP_LO1__TIME_LO__SHIFT', + 'CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT_MASK', + 'CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT__SHIFT', + 'CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT_MASK', + 'CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT__SHIFT', + 'CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL_MASK', + 'CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL__SHIFT', + 'CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL_MASK', + 'CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL__SHIFT', + 'CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK', + 'CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT', + 'CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK', + 'CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_MASK', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT', + 'CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT', + 'CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK', + 'CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT', + 'CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK', + 'CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT', + 'CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK', + 'CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT', + 'CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK', + 'CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT', + 'CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK', + 'CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT', + 'CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK', + 'CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT', + 'CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK', + 'CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT', + 'CP_HPD_STATUS0__FETCHING_MQD_MASK', + 'CP_HPD_STATUS0__FETCHING_MQD__SHIFT', + 'CP_HPD_STATUS0__FORCE_QUEUE_MASK', + 'CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK', + 'CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT', + 'CP_HPD_STATUS0__FORCE_QUEUE__SHIFT', + 'CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK', + 'CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT', + 'CP_HPD_STATUS0__MAPPED_QUEUE_MASK', + 'CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT', + 'CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK', + 'CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT', + 'CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK', + 'CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT', + 'CP_HPD_STATUS0__QUEUE_STATE_MASK', + 'CP_HPD_STATUS0__QUEUE_STATE__SHIFT', + 'CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT_MASK', + 'CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT__SHIFT', + 'CP_HPD_UTCL1_CNTL__SELECT_MASK', + 'CP_HPD_UTCL1_CNTL__SELECT__SHIFT', + 'CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK', + 'CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT', + 'CP_HPD_UTCL1_ERROR__ADDR_HI_MASK', + 'CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT', + 'CP_HPD_UTCL1_ERROR__TYPE_MASK', + 'CP_HPD_UTCL1_ERROR__TYPE__SHIFT', + 'CP_HPD_UTCL1_ERROR__VMID_MASK', + 'CP_HPD_UTCL1_ERROR__VMID__SHIFT', 'CP_HQD_ACTIVE__ACTIVE_MASK', + 'CP_HQD_ACTIVE__ACTIVE__SHIFT', 'CP_HQD_ACTIVE__BUSY_GATE_MASK', + 'CP_HQD_ACTIVE__BUSY_GATE__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL0_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL0__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL1_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL1__SHIFT', + 'CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK', + 'CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT', + 'CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK', + 'CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT', + 'CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK', + 'CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT', + 'CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK', + 'CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT', + 'CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK', + 'CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT', + 'CP_HQD_CNTL_STACK_SIZE__SIZE_MASK', + 'CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT', + 'CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK', + 'CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK', + 'CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT', + 'CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK', + 'CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT', + 'CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK', + 'CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT', + 'CP_HQD_CTX_SAVE_SIZE__SIZE_MASK', + 'CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT', + 'CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK', + 'CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT', + 'CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK', + 'CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT', + 'CP_HQD_DDID_RPTR__RPTR_MASK', 'CP_HQD_DDID_RPTR__RPTR__SHIFT', + 'CP_HQD_DDID_WPTR__WPTR_MASK', 'CP_HQD_DDID_WPTR__WPTR__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT', + 'CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK', + 'CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT', + 'CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK', + 'CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT', + 'CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK', + 'CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT', + 'CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK', + 'CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT', + 'CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN_MASK', + 'CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN__SHIFT', + 'CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_MASK', + 'CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD__SHIFT', + 'CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN_MASK', + 'CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN__SHIFT', + 'CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK', + 'CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT', + 'CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN_MASK', + 'CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN__SHIFT', + 'CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_MASK', + 'CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD__SHIFT', + 'CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK', + 'CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT', + 'CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK', + 'CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT', + 'CP_HQD_EOP_CONTROL__EOP_SIZE_MASK', + 'CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT', + 'CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK', + 'CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT', + 'CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK', + 'CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT', + 'CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK', + 'CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK', + 'CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK', + 'CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT', + 'CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK', + 'CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT', + 'CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK', + 'CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT', + 'CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK', + 'CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT', + 'CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK', + 'CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT', + 'CP_HQD_EOP_RPTR__INIT_FETCHER_MASK', + 'CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT', + 'CP_HQD_EOP_RPTR__RESET_FETCHER_MASK', + 'CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT', + 'CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK', + 'CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT', + 'CP_HQD_EOP_RPTR__RPTR_MASK', 'CP_HQD_EOP_RPTR__RPTR__SHIFT', + 'CP_HQD_EOP_WPTR_MEM__WPTR_MASK', + 'CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT', + 'CP_HQD_EOP_WPTR__EOP_AVAIL_MASK', + 'CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT', + 'CP_HQD_EOP_WPTR__EOP_EMPTY_MASK', + 'CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT', 'CP_HQD_EOP_WPTR__WPTR_MASK', + 'CP_HQD_EOP_WPTR__WPTR__SHIFT', 'CP_HQD_ERROR__AQL_ERROR_MASK', + 'CP_HQD_ERROR__AQL_ERROR__SHIFT', + 'CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__EDC_ERROR_ID_MASK', + 'CP_HQD_ERROR__EDC_ERROR_ID__SHIFT', + 'CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__IB_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__QU_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__SR_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__SUA_ERROR_MASK', 'CP_HQD_ERROR__SUA_ERROR__SHIFT', + 'CP_HQD_ERROR__TC_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT', + 'CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK', + 'CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT', + 'CP_HQD_GFX_CONTROL__MESSAGE_MASK', + 'CP_HQD_GFX_CONTROL__MESSAGE__SHIFT', + 'CP_HQD_GFX_CONTROL__MISC_MASK', + 'CP_HQD_GFX_CONTROL__MISC__SHIFT', + 'CP_HQD_GFX_STATUS__STATUS_MASK', + 'CP_HQD_GFX_STATUS__STATUS__SHIFT', + 'CP_HQD_HQ_CONTROL0__CONTROL_MASK', + 'CP_HQD_HQ_CONTROL0__CONTROL__SHIFT', + 'CP_HQD_HQ_CONTROL1__CONTROL_MASK', + 'CP_HQD_HQ_CONTROL1__CONTROL__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT_MASK', + 'CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__CWSR_MASK', + 'CP_HQD_HQ_SCHEDULER0__CWSR__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID_MASK', + 'CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS_MASK', + 'CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN_MASK', + 'CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED_MASK', + 'CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE_MASK', + 'CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE_MASK', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE_MASK', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED_MASK', + 'CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__RSRV_MASK', + 'CP_HQD_HQ_SCHEDULER0__RSRV__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__SAVE_STATUS_MASK', + 'CP_HQD_HQ_SCHEDULER0__SAVE_STATUS__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK', + 'CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE_MASK', + 'CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK', + 'CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT', + 'CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK', + 'CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT', + 'CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT_MASK', + 'CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT__SHIFT', + 'CP_HQD_HQ_STATUS0__CWSR_MASK', 'CP_HQD_HQ_STATUS0__CWSR__SHIFT', + 'CP_HQD_HQ_STATUS0__C_INHERIT_VMID_MASK', + 'CP_HQD_HQ_STATUS0__C_INHERIT_VMID__SHIFT', + 'CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS_MASK', + 'CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS__SHIFT', + 'CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK', + 'CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT', + 'CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED_MASK', + 'CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED__SHIFT', + 'CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE_MASK', + 'CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE__SHIFT', + 'CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK', + 'CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT', + 'CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE_MASK', + 'CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE__SHIFT', + 'CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE_MASK', + 'CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE__SHIFT', + 'CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED_MASK', + 'CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED__SHIFT', + 'CP_HQD_HQ_STATUS0__RSRV_MASK', 'CP_HQD_HQ_STATUS0__RSRV__SHIFT', + 'CP_HQD_HQ_STATUS0__SAVE_STATUS_MASK', + 'CP_HQD_HQ_STATUS0__SAVE_STATUS__SHIFT', + 'CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK', + 'CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT', + 'CP_HQD_HQ_STATUS0__STATIC_QUEUE_MASK', + 'CP_HQD_HQ_STATUS0__STATIC_QUEUE__SHIFT', + 'CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK', + 'CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT', + 'CP_HQD_HQ_STATUS1__STATUS_MASK', + 'CP_HQD_HQ_STATUS1__STATUS__SHIFT', + 'CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK', + 'CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT', + 'CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK', + 'CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT', + 'CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK', + 'CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT', + 'CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK', + 'CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT', + 'CP_HQD_IB_CONTROL__IB_SIZE_MASK', + 'CP_HQD_IB_CONTROL__IB_SIZE__SHIFT', + 'CP_HQD_IB_CONTROL__IB_VOLATILE_MASK', + 'CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT', + 'CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK', + 'CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT', + 'CP_HQD_IB_CONTROL__PROCESSING_IB_MASK', + 'CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT', + 'CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK', + 'CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT', + 'CP_HQD_IQ_RPTR__OFFSET_MASK', 'CP_HQD_IQ_RPTR__OFFSET__SHIFT', + 'CP_HQD_IQ_TIMER__ACTIVE_MASK', 'CP_HQD_IQ_TIMER__ACTIVE__SHIFT', + 'CP_HQD_IQ_TIMER__CACHE_POLICY_MASK', + 'CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT', + 'CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK', + 'CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT', + 'CP_HQD_IQ_TIMER__EXE_DISABLE_MASK', + 'CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT', + 'CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK', + 'CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT', + 'CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK', + 'CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT', + 'CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK', + 'CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT', + 'CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK', + 'CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT', + 'CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK', + 'CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT', + 'CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK', + 'CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT', + 'CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK', + 'CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT', + 'CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK', + 'CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT', + 'CP_HQD_IQ_TIMER__REARM_TIMER_MASK', + 'CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT', + 'CP_HQD_IQ_TIMER__RETRY_TYPE_MASK', + 'CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT', + 'CP_HQD_IQ_TIMER__WAIT_TIME_MASK', + 'CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT', + 'CP_HQD_MSG_TYPE__ACTION_MASK', 'CP_HQD_MSG_TYPE__ACTION__SHIFT', + 'CP_HQD_MSG_TYPE__SAVE_STATE_MASK', + 'CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT', + 'CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK', + 'CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK', + 'CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK', + 'CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT', + 'CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK', + 'CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK', + 'CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT', + 'CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE_MASK', + 'CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS_MASK', + 'CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS__SHIFT', + 'CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT_MASK', + 'CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT__SHIFT', + 'CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK', + 'CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT', + 'CP_HQD_PQ_BASE_HI__ADDR_HI_MASK', + 'CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT', 'CP_HQD_PQ_BASE__ADDR_MASK', + 'CP_HQD_PQ_BASE__ADDR__SHIFT', + 'CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK', + 'CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT', + 'CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK', + 'CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT', + 'CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK', + 'CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT', + 'CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK', + 'CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT', + 'CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK', + 'CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT', + 'CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK', + 'CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT', + 'CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK', + 'CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT', + 'CP_HQD_PQ_CONTROL__PRIV_STATE_MASK', + 'CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT', + 'CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK', + 'CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT', + 'CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK', + 'CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT', + 'CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK', + 'CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT', + 'CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK', + 'CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT', + 'CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK', + 'CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT', + 'CP_HQD_PQ_CONTROL__TMZ_MASK', 'CP_HQD_PQ_CONTROL__TMZ__SHIFT', + 'CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK', + 'CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT', + 'CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK', + 'CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT', + 'CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK', + 'CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT', + 'CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK', + 'CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT', + 'CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK', + 'CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT', + 'CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK', + 'CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT', + 'CP_HQD_PQ_WPTR_HI__DATA_MASK', 'CP_HQD_PQ_WPTR_HI__DATA__SHIFT', + 'CP_HQD_PQ_WPTR_LO__OFFSET_MASK', + 'CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT', + 'CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK', + 'CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT', + 'CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK', + 'CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK', + 'CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_DURATION_MASK', + 'CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_EN_MASK', + 'CP_HQD_QUANTUM__QUANTUM_EN__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_SCALE_MASK', + 'CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT', + 'CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK', + 'CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT', + 'CP_HQD_SEMA_CMD__MESSAGE_EN_MASK', + 'CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT', + 'CP_HQD_SEMA_CMD__POLLING_DIS_MASK', + 'CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT', + 'CP_HQD_SEMA_CMD__RESULT_MASK', 'CP_HQD_SEMA_CMD__RESULT__SHIFT', + 'CP_HQD_SEMA_CMD__RETRY_MASK', 'CP_HQD_SEMA_CMD__RETRY__SHIFT', + 'CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK', + 'CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT', + 'CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK', + 'CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT', + 'CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK', + 'CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT', + 'CP_HQD_VMID__IB_VMID_MASK', 'CP_HQD_VMID__IB_VMID__SHIFT', + 'CP_HQD_VMID__VMID_MASK', 'CP_HQD_VMID__VMID__SHIFT', + 'CP_HQD_VMID__VQID_MASK', 'CP_HQD_VMID__VQID__SHIFT', + 'CP_HQD_WG_STATE_OFFSET__OFFSET_MASK', + 'CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT', + 'CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_IB2_BASE_HI__IB2_BASE_HI_MASK', + 'CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT', + 'CP_IB2_BASE_LO__IB2_BASE_LO_MASK', + 'CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT', + 'CP_IB2_BUFSZ__IB2_BUFSZ_MASK', 'CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT', + 'CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK', + 'CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT', + 'CP_IB2_OFFSET__IB2_OFFSET_MASK', + 'CP_IB2_OFFSET__IB2_OFFSET__SHIFT', + 'CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK', + 'CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT', + 'CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK', + 'CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT', + 'CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK', + 'CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_INDEX_BASE_ADDR__ADDR_LO_MASK', + 'CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT', + 'CP_INDEX_TYPE__INDEX_TYPE_MASK', + 'CP_INDEX_TYPE__INDEX_TYPE__SHIFT', + 'CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK', + 'CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK', + 'CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK', + 'CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK', + 'CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK', + 'CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__RESUME_INT_ENABLE_MASK', + 'CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK', + 'CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GPF_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GPF_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT', + 'CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK', + 'CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT', + 'CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK', + 'CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT', + 'CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK', + 'CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT', + 'CP_INT_STATUS__GENERIC0_INT_STAT_MASK', + 'CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT', + 'CP_INT_STATUS__GENERIC1_INT_STAT_MASK', + 'CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT', + 'CP_INT_STATUS__GENERIC2_INT_STAT_MASK', + 'CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT', + 'CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK', + 'CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT', + 'CP_INT_STATUS__GPF_INT_STAT_MASK', + 'CP_INT_STATUS__GPF_INT_STAT__SHIFT', + 'CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK', + 'CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT', + 'CP_INT_STATUS__PRIV_REG_INT_STAT_MASK', + 'CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT', + 'CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS__RESUME_INT_STAT_MASK', + 'CP_INT_STATUS__RESUME_INT_STAT__SHIFT', + 'CP_INT_STATUS__SUSPEND_INT_STAT_MASK', + 'CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT', + 'CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK', + 'CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT', + 'CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK', + 'CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT', + 'CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT', + 'CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK', + 'CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT', + 'CP_IQ_WAIT_TIME1__GWS_MASK', 'CP_IQ_WAIT_TIME1__GWS__SHIFT', + 'CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK', + 'CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT', + 'CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK', + 'CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT', + 'CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK', + 'CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT', + 'CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK', + 'CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT', + 'CP_IQ_WAIT_TIME2__SCH_WAVE_MASK', + 'CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT', + 'CP_IQ_WAIT_TIME2__SEM_REARM_MASK', + 'CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT', + 'CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK', + 'CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT', + 'CP_MAX_CONTEXT__MAX_CONTEXT_MASK', + 'CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT', + 'CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT_MASK', + 'CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT__SHIFT', + 'CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK', + 'CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT', + 'CP_ME0_PIPE0_VMID__VMID_MASK', 'CP_ME0_PIPE0_VMID__VMID__SHIFT', + 'CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK', + 'CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT', + 'CP_ME0_PIPE1_VMID__VMID_MASK', 'CP_ME0_PIPE1_VMID__VMID__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT', + 'CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT', + 'CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK', + 'CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT', + 'CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK', + 'CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK', + 'CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK', + 'CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK', + 'CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_MEC1_INTR_ROUTINE_START__IR_START_MASK', + 'CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_MEC1_PRGRM_CNTR_START__IP_START_MASK', + 'CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT', + 'CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT', + 'CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK', + 'CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT', + 'CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK', + 'CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK', + 'CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK', + 'CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK', + 'CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_MEC2_INTR_ROUTINE_START__IR_START_MASK', + 'CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_MEC2_PRGRM_CNTR_START__IP_START_MASK', + 'CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK', + 'CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_HALT_MASK', + 'CP_MEC_CNTL__MEC_ME1_HALT__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_STEP_MASK', + 'CP_MEC_CNTL__MEC_ME1_STEP__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_HALT_MASK', + 'CP_MEC_CNTL__MEC_ME2_HALT__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_STEP_MASK', + 'CP_MEC_CNTL__MEC_ME2_STEP__SHIFT', + 'CP_MEC_DC_APERTURE0_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE0_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE0_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE0_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE0_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE0_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE10_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE10_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE10_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE10_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE10_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE10_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE11_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE11_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE11_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE11_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE11_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE11_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE12_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE12_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE12_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE12_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE12_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE12_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE13_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE13_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE13_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE13_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE13_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE13_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE14_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE14_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE14_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE14_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE14_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE14_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE15_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE15_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE15_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE15_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE15_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE15_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE1_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE1_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE1_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE1_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE1_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE1_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE2_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE2_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE2_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE2_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE2_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE2_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE3_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE3_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE3_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE3_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE3_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE3_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE4_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE4_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE4_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE4_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE4_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE4_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE5_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE5_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE5_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE5_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE5_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE5_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE6_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE6_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE6_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE6_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE6_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE6_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE7_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE7_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE7_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE7_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE7_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE7_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE8_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE8_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE8_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE8_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE8_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE8_MASK__MASK__SHIFT', + 'CP_MEC_DC_APERTURE9_BASE__BASE_MASK', + 'CP_MEC_DC_APERTURE9_BASE__BASE__SHIFT', + 'CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE_MASK', + 'CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT', + 'CP_MEC_DC_APERTURE9_CNTL__VMID_MASK', + 'CP_MEC_DC_APERTURE9_CNTL__VMID__SHIFT', + 'CP_MEC_DC_APERTURE9_MASK__MASK_MASK', + 'CP_MEC_DC_APERTURE9_MASK__MASK__SHIFT', + 'CP_MEC_DC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_MEC_DC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_MEC_DC_BASE_CNTL__VMID_MASK', + 'CP_MEC_DC_BASE_CNTL__VMID__SHIFT', + 'CP_MEC_DC_BASE_HI__DC_BASE_HI_MASK', + 'CP_MEC_DC_BASE_HI__DC_BASE_HI__SHIFT', + 'CP_MEC_DC_BASE_LO__DC_BASE_LO_MASK', + 'CP_MEC_DC_BASE_LO__DC_BASE_LO__SHIFT', + 'CP_MEC_DC_OP_CNTL__BYPASS_ALL_MASK', + 'CP_MEC_DC_OP_CNTL__BYPASS_ALL__SHIFT', + 'CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK', + 'CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT', + 'CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_MASK', + 'CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT', + 'CP_MEC_DM_INDEX_ADDR__ADDR_MASK', + 'CP_MEC_DM_INDEX_ADDR__ADDR__SHIFT', + 'CP_MEC_DM_INDEX_DATA__DATA_MASK', + 'CP_MEC_DM_INDEX_DATA__DATA__SHIFT', + 'CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK', + 'CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT', + 'CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK', + 'CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT', + 'CP_MEC_GP0_HI__M_RET_ADDR_MASK', + 'CP_MEC_GP0_HI__M_RET_ADDR__SHIFT', 'CP_MEC_GP0_LO__DATA_MASK', + 'CP_MEC_GP0_LO__DATA__SHIFT', + 'CP_MEC_GP0_LO__PG_VIRT_HALTED_MASK', + 'CP_MEC_GP0_LO__PG_VIRT_HALTED__SHIFT', + 'CP_MEC_GP1_HI__RD_WR_SELECT_HI_MASK', + 'CP_MEC_GP1_HI__RD_WR_SELECT_HI__SHIFT', + 'CP_MEC_GP1_LO__RD_WR_SELECT_LO_MASK', + 'CP_MEC_GP1_LO__RD_WR_SELECT_LO__SHIFT', + 'CP_MEC_GP2_HI__STACK_PNTR_HI_MASK', + 'CP_MEC_GP2_HI__STACK_PNTR_HI__SHIFT', + 'CP_MEC_GP2_LO__STACK_PNTR_LO_MASK', + 'CP_MEC_GP2_LO__STACK_PNTR_LO__SHIFT', 'CP_MEC_GP3_HI__DATA_MASK', + 'CP_MEC_GP3_HI__DATA__SHIFT', 'CP_MEC_GP3_LO__DATA_MASK', + 'CP_MEC_GP3_LO__DATA__SHIFT', 'CP_MEC_GP4_HI__DATA_MASK', + 'CP_MEC_GP4_HI__DATA__SHIFT', 'CP_MEC_GP4_LO__DATA_MASK', + 'CP_MEC_GP4_LO__DATA__SHIFT', 'CP_MEC_GP5_HI__M_RET_ADDR_MASK', + 'CP_MEC_GP5_HI__M_RET_ADDR__SHIFT', 'CP_MEC_GP5_LO__DATA_MASK', + 'CP_MEC_GP5_LO__DATA__SHIFT', + 'CP_MEC_GP5_LO__PG_VIRT_HALTED_MASK', + 'CP_MEC_GP5_LO__PG_VIRT_HALTED__SHIFT', + 'CP_MEC_GP6_HI__RD_WR_SELECT_HI_MASK', + 'CP_MEC_GP6_HI__RD_WR_SELECT_HI__SHIFT', + 'CP_MEC_GP6_LO__RD_WR_SELECT_LO_MASK', + 'CP_MEC_GP6_LO__RD_WR_SELECT_LO__SHIFT', + 'CP_MEC_GP7_HI__STACK_PNTR_HI_MASK', + 'CP_MEC_GP7_HI__STACK_PNTR_HI__SHIFT', + 'CP_MEC_GP7_LO__STACK_PNTR_LO_MASK', + 'CP_MEC_GP7_LO__STACK_PNTR_LO__SHIFT', 'CP_MEC_GP8_HI__DATA_MASK', + 'CP_MEC_GP8_HI__DATA__SHIFT', 'CP_MEC_GP8_LO__DATA_MASK', + 'CP_MEC_GP8_LO__DATA__SHIFT', 'CP_MEC_GP9_HI__DATA_MASK', + 'CP_MEC_GP9_HI__DATA__SHIFT', 'CP_MEC_GP9_LO__DATA_MASK', + 'CP_MEC_GP9_LO__DATA__SHIFT', 'CP_MEC_ISA_CNTL__ISA_MODE_MASK', + 'CP_MEC_ISA_CNTL__ISA_MODE__SHIFT', + 'CP_MEC_JT_STAT__JT_LOADED_MASK', + 'CP_MEC_JT_STAT__JT_LOADED__SHIFT', + 'CP_MEC_JT_STAT__WR_MASK_MASK', 'CP_MEC_JT_STAT__WR_MASK__SHIFT', + 'CP_MEC_LOCAL_APERTURE__APERTURE_MASK', + 'CP_MEC_LOCAL_APERTURE__APERTURE__SHIFT', + 'CP_MEC_LOCAL_BASE0_HI__BASE0_HI_MASK', + 'CP_MEC_LOCAL_BASE0_HI__BASE0_HI__SHIFT', + 'CP_MEC_LOCAL_BASE0_LO__BASE0_LO_MASK', + 'CP_MEC_LOCAL_BASE0_LO__BASE0_LO__SHIFT', + 'CP_MEC_LOCAL_INSTR_APERTURE__APERTURE_MASK', + 'CP_MEC_LOCAL_INSTR_APERTURE__APERTURE__SHIFT', + 'CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI_MASK', + 'CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT', + 'CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO_MASK', + 'CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT', + 'CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI_MASK', + 'CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT', + 'CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO_MASK', + 'CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT', + 'CP_MEC_LOCAL_MASK0_HI__MASK0_HI_MASK', + 'CP_MEC_LOCAL_MASK0_HI__MASK0_HI__SHIFT', + 'CP_MEC_LOCAL_MASK0_LO__MASK0_LO_MASK', + 'CP_MEC_LOCAL_MASK0_LO__MASK0_LO__SHIFT', + 'CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE_MASK', + 'CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT', + 'CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK', + 'CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT', + 'CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK', + 'CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT', + 'CP_MEC_MDBASE_HI__BASE_HI_MASK', + 'CP_MEC_MDBASE_HI__BASE_HI__SHIFT', + 'CP_MEC_MDBASE_LO__BASE_LO_MASK', + 'CP_MEC_MDBASE_LO__BASE_LO__SHIFT', + 'CP_MEC_MDBOUND_HI__BOUND_HI_MASK', + 'CP_MEC_MDBOUND_HI__BOUND_HI__SHIFT', + 'CP_MEC_MDBOUND_LO__BOUND_LO_MASK', + 'CP_MEC_MDBOUND_LO__BOUND_LO__SHIFT', + 'CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK', + 'CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT', + 'CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK', + 'CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK', + 'CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT', + 'CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK', + 'CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_MEC_MIBOUND_HI__BOUND_HI_MASK', + 'CP_MEC_MIBOUND_HI__BOUND_HI__SHIFT', + 'CP_MEC_MIBOUND_LO__BOUND_LO_MASK', + 'CP_MEC_MIBOUND_LO__BOUND_LO__SHIFT', + 'CP_MEC_MIE_HI__MEC_INT_MASK', 'CP_MEC_MIE_HI__MEC_INT__SHIFT', + 'CP_MEC_MIE_LO__MEC_INT_MASK', 'CP_MEC_MIE_LO__MEC_INT__SHIFT', + 'CP_MEC_MIP_HI__MIP_HI_MASK', 'CP_MEC_MIP_HI__MIP_HI__SHIFT', + 'CP_MEC_MIP_LO__MIP_LO_MASK', 'CP_MEC_MIP_LO__MIP_LO__SHIFT', + 'CP_MEC_MTIMECMP_HI__TIME_HI_MASK', + 'CP_MEC_MTIMECMP_HI__TIME_HI__SHIFT', + 'CP_MEC_MTIMECMP_LO__TIME_LO_MASK', + 'CP_MEC_MTIMECMP_LO__TIME_LO__SHIFT', + 'CP_MEC_MTVEC_HI__ADDR_LO_MASK', + 'CP_MEC_MTVEC_HI__ADDR_LO__SHIFT', + 'CP_MEC_MTVEC_LO__ADDR_LO_MASK', + 'CP_MEC_MTVEC_LO__ADDR_LO__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_HALT_MASK', + 'CP_MEC_RS64_CNTL__MEC_HALT__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK', + 'CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE0_RESET_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE0_RESET__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE1_RESET_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE1_RESET__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE2_RESET_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE2_RESET__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_PIPE3_RESET_MASK', + 'CP_MEC_RS64_CNTL__MEC_PIPE3_RESET__SHIFT', + 'CP_MEC_RS64_CNTL__MEC_STEP_MASK', + 'CP_MEC_RS64_CNTL__MEC_STEP__SHIFT', + 'CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_16__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_16__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_17__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_17__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_18__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_18__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_19__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_19__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_20__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_20__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_21__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_21__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_22__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_22__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_23__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_23__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_24__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_24__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_25__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_25__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_26__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_26__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_27__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_27__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_28__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_28__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_29__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_29__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_30__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_30__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT_DATA_31__DATA_MASK', + 'CP_MEC_RS64_INTERRUPT_DATA_31__DATA__SHIFT', + 'CP_MEC_RS64_INTERRUPT__MEC_INT_MASK', + 'CP_MEC_RS64_INTERRUPT__MEC_INT__SHIFT', + 'CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK', + 'CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT', + 'CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK', + 'CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT', + 'CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START_MASK', + 'CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT', + 'CP_MEC_RS64_PRGRM_CNTR_START__IP_START_MASK', + 'CP_MEC_RS64_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_MEQ_AVAIL__MEQ_CNT_MASK', 'CP_MEQ_AVAIL__MEQ_CNT__SHIFT', + 'CP_MEQ_STAT__MEQ_RPTR_MASK', 'CP_MEQ_STAT__MEQ_RPTR__SHIFT', + 'CP_MEQ_STAT__MEQ_WPTR_MASK', 'CP_MEQ_STAT__MEQ_WPTR__SHIFT', + 'CP_MEQ_THRESHOLDS__MEQ1_START_MASK', + 'CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT', + 'CP_MEQ_THRESHOLDS__MEQ2_START_MASK', + 'CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT', + 'CP_MES_CNTL__MES_HALT_MASK', 'CP_MES_CNTL__MES_HALT__SHIFT', + 'CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK', + 'CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT', + 'CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK', + 'CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT', + 'CP_MES_CNTL__MES_PIPE0_RESET_MASK', + 'CP_MES_CNTL__MES_PIPE0_RESET__SHIFT', + 'CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK', + 'CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT', + 'CP_MES_CNTL__MES_PIPE1_RESET_MASK', + 'CP_MES_CNTL__MES_PIPE1_RESET__SHIFT', + 'CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK', + 'CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT', + 'CP_MES_CNTL__MES_PIPE2_RESET_MASK', + 'CP_MES_CNTL__MES_PIPE2_RESET__SHIFT', + 'CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK', + 'CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT', + 'CP_MES_CNTL__MES_PIPE3_RESET_MASK', + 'CP_MES_CNTL__MES_PIPE3_RESET__SHIFT', + 'CP_MES_CNTL__MES_STEP_MASK', 'CP_MES_CNTL__MES_STEP__SHIFT', + 'CP_MES_DC_APERTURE0_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE0_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE0_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE0_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE0_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE0_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE10_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE10_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE10_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE10_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE10_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE10_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE11_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE11_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE11_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE11_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE11_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE11_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE12_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE12_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE12_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE12_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE12_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE12_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE13_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE13_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE13_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE13_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE13_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE13_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE14_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE14_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE14_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE14_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE14_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE14_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE15_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE15_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE15_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE15_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE15_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE15_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE1_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE1_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE1_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE1_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE1_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE1_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE2_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE2_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE2_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE2_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE2_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE2_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE3_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE3_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE3_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE3_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE3_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE3_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE4_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE4_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE4_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE4_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE4_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE4_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE5_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE5_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE5_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE5_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE5_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE5_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE6_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE6_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE6_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE6_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE6_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE6_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE7_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE7_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE7_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE7_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE7_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE7_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE8_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE8_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE8_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE8_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE8_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE8_MASK__MASK__SHIFT', + 'CP_MES_DC_APERTURE9_BASE__BASE_MASK', + 'CP_MES_DC_APERTURE9_BASE__BASE__SHIFT', + 'CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK', + 'CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT', + 'CP_MES_DC_APERTURE9_CNTL__VMID_MASK', + 'CP_MES_DC_APERTURE9_CNTL__VMID__SHIFT', + 'CP_MES_DC_APERTURE9_MASK__MASK_MASK', + 'CP_MES_DC_APERTURE9_MASK__MASK__SHIFT', + 'CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_MES_DC_BASE_CNTL__VMID_MASK', + 'CP_MES_DC_BASE_CNTL__VMID__SHIFT', + 'CP_MES_DC_BASE_HI__DC_BASE_HI_MASK', + 'CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT', + 'CP_MES_DC_BASE_LO__DC_BASE_LO_MASK', + 'CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT', + 'CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK', + 'CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT', + 'CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK', + 'CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT', + 'CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK', + 'CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT', + 'CP_MES_DM_INDEX_ADDR__ADDR_MASK', + 'CP_MES_DM_INDEX_ADDR__ADDR__SHIFT', + 'CP_MES_DM_INDEX_DATA__DATA_MASK', + 'CP_MES_DM_INDEX_DATA__DATA__SHIFT', + 'CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK', + 'CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT', + 'CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK', + 'CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT', + 'CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK', + 'CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT', + 'CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK', + 'CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT', + 'CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK', + 'CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT', + 'CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK', + 'CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT', + 'CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK', + 'CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT', + 'CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK', + 'CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT', + 'CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK', + 'CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT', + 'CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK', + 'CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT', + 'CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK', + 'CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT', + 'CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK', + 'CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT', + 'CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK', + 'CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT', + 'CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK', + 'CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT', + 'CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK', + 'CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT', + 'CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK', + 'CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT', + 'CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK', + 'CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT', + 'CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK', + 'CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT', + 'CP_MES_GP0_HI__M_RET_ADDR_MASK', + 'CP_MES_GP0_HI__M_RET_ADDR__SHIFT', 'CP_MES_GP0_LO__DATA_MASK', + 'CP_MES_GP0_LO__DATA__SHIFT', + 'CP_MES_GP0_LO__PG_VIRT_HALTED_MASK', + 'CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT', + 'CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK', + 'CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT', + 'CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK', + 'CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT', + 'CP_MES_GP2_HI__STACK_PNTR_HI_MASK', + 'CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT', + 'CP_MES_GP2_LO__STACK_PNTR_LO_MASK', + 'CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT', 'CP_MES_GP3_HI__DATA_MASK', + 'CP_MES_GP3_HI__DATA__SHIFT', 'CP_MES_GP3_LO__DATA_MASK', + 'CP_MES_GP3_LO__DATA__SHIFT', 'CP_MES_GP4_HI__DATA_MASK', + 'CP_MES_GP4_HI__DATA__SHIFT', 'CP_MES_GP4_LO__DATA_MASK', + 'CP_MES_GP4_LO__DATA__SHIFT', 'CP_MES_GP5_HI__M_RET_ADDR_MASK', + 'CP_MES_GP5_HI__M_RET_ADDR__SHIFT', 'CP_MES_GP5_LO__DATA_MASK', + 'CP_MES_GP5_LO__DATA__SHIFT', + 'CP_MES_GP5_LO__PG_VIRT_HALTED_MASK', + 'CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT', + 'CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK', + 'CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT', + 'CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK', + 'CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT', + 'CP_MES_GP7_HI__STACK_PNTR_HI_MASK', + 'CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT', + 'CP_MES_GP7_LO__STACK_PNTR_LO_MASK', + 'CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT', 'CP_MES_GP8_HI__DATA_MASK', + 'CP_MES_GP8_HI__DATA__SHIFT', 'CP_MES_GP8_LO__DATA_MASK', + 'CP_MES_GP8_LO__DATA__SHIFT', 'CP_MES_GP9_HI__DATA_MASK', + 'CP_MES_GP9_HI__DATA__SHIFT', 'CP_MES_GP9_LO__DATA_MASK', + 'CP_MES_GP9_LO__DATA__SHIFT', + 'CP_MES_HEADER_DUMP__HEADER_DUMP_MASK', + 'CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT', + 'CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK', + 'CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT', + 'CP_MES_IC_BASE_CNTL__VMID_MASK', + 'CP_MES_IC_BASE_CNTL__VMID__SHIFT', + 'CP_MES_IC_BASE_HI__IC_BASE_HI_MASK', + 'CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT', + 'CP_MES_IC_BASE_LO__IC_BASE_LO_MASK', + 'CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT', + 'CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK', + 'CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT', + 'CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK', + 'CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT', + 'CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK', + 'CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT', + 'CP_MES_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_MES_INTERRUPT_DATA_16__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_16__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_17__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_17__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_18__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_18__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_19__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_19__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_20__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_20__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_21__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_21__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_22__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_22__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_23__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_23__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_24__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_24__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_25__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_25__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_26__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_26__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_27__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_27__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_28__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_28__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_29__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_29__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_30__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_30__DATA__SHIFT', + 'CP_MES_INTERRUPT_DATA_31__DATA_MASK', + 'CP_MES_INTERRUPT_DATA_31__DATA__SHIFT', + 'CP_MES_INTERRUPT__MES_INT_MASK', + 'CP_MES_INTERRUPT__MES_INT__SHIFT', + 'CP_MES_INTR_ROUTINE_START_HI__IR_START_MASK', + 'CP_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT', + 'CP_MES_INTR_ROUTINE_START__IR_START_MASK', + 'CP_MES_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_MES_LOCAL_APERTURE__APERTURE_MASK', + 'CP_MES_LOCAL_APERTURE__APERTURE__SHIFT', + 'CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK', + 'CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT', + 'CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK', + 'CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT', + 'CP_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK', + 'CP_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT', + 'CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK', + 'CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT', + 'CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK', + 'CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT', + 'CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK', + 'CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT', + 'CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK', + 'CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT', + 'CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK', + 'CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT', + 'CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK', + 'CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT', + 'CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK', + 'CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT', + 'CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK', + 'CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT', + 'CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK', + 'CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT', + 'CP_MES_MARCHID_HI__MARCHID_HI_MASK', + 'CP_MES_MARCHID_HI__MARCHID_HI__SHIFT', + 'CP_MES_MARCHID_LO__MARCHID_LO_MASK', + 'CP_MES_MARCHID_LO__MARCHID_LO__SHIFT', + 'CP_MES_MBADADDR_HI__ADDR_HI_MASK', + 'CP_MES_MBADADDR_HI__ADDR_HI__SHIFT', + 'CP_MES_MBADADDR_LO__ADDR_LO_MASK', + 'CP_MES_MBADADDR_LO__ADDR_LO__SHIFT', + 'CP_MES_MCAUSE_HI__CAUSE_HI_MASK', + 'CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT', + 'CP_MES_MCAUSE_LO__CAUSE_LO_MASK', + 'CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT', + 'CP_MES_MCYCLE_HI__CYCLE_HI_MASK', + 'CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT', + 'CP_MES_MCYCLE_LO__CYCLE_LO_MASK', + 'CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT', + 'CP_MES_MDBASE_HI__BASE_HI_MASK', + 'CP_MES_MDBASE_HI__BASE_HI__SHIFT', + 'CP_MES_MDBASE_LO__BASE_LO_MASK', + 'CP_MES_MDBASE_LO__BASE_LO__SHIFT', + 'CP_MES_MDBOUND_HI__BOUND_HI_MASK', + 'CP_MES_MDBOUND_HI__BOUND_HI__SHIFT', + 'CP_MES_MDBOUND_LO__BOUND_LO_MASK', + 'CP_MES_MDBOUND_LO__BOUND_LO__SHIFT', + 'CP_MES_MEPC_HI__MEPC_HI_MASK', 'CP_MES_MEPC_HI__MEPC_HI__SHIFT', + 'CP_MES_MEPC_LO__MEPC_LO_MASK', 'CP_MES_MEPC_LO__MEPC_LO__SHIFT', + 'CP_MES_MHARTID_HI__MHARTID_HI_MASK', + 'CP_MES_MHARTID_HI__MHARTID_HI__SHIFT', + 'CP_MES_MHARTID_LO__MHARTID_LO_MASK', + 'CP_MES_MHARTID_LO__MHARTID_LO__SHIFT', + 'CP_MES_MIBASE_HI__IC_BASE_HI_MASK', + 'CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT', + 'CP_MES_MIBASE_LO__IC_BASE_LO_MASK', + 'CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT', + 'CP_MES_MIBOUND_HI__BOUND_HI_MASK', + 'CP_MES_MIBOUND_HI__BOUND_HI__SHIFT', + 'CP_MES_MIBOUND_LO__BOUND_LO_MASK', + 'CP_MES_MIBOUND_LO__BOUND_LO__SHIFT', + 'CP_MES_MIE_HI__MES_INT_MASK', 'CP_MES_MIE_HI__MES_INT__SHIFT', + 'CP_MES_MIE_LO__MES_INT_MASK', 'CP_MES_MIE_LO__MES_INT__SHIFT', + 'CP_MES_MIMPID_HI__MIMPID_HI_MASK', + 'CP_MES_MIMPID_HI__MIMPID_HI__SHIFT', + 'CP_MES_MIMPID_LO__MIMPID_LO_MASK', + 'CP_MES_MIMPID_LO__MIMPID_LO__SHIFT', + 'CP_MES_MINSTRET_HI__INSTRET_HI_MASK', + 'CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT', + 'CP_MES_MINSTRET_LO__INSTRET_LO_MASK', + 'CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT', + 'CP_MES_MIP_HI__MIP_HI_MASK', 'CP_MES_MIP_HI__MIP_HI__SHIFT', + 'CP_MES_MIP_LO__MIP_LO_MASK', 'CP_MES_MIP_LO__MIP_LO__SHIFT', + 'CP_MES_MISA_HI__MISA_HI_MASK', 'CP_MES_MISA_HI__MISA_HI__SHIFT', + 'CP_MES_MISA_LO__MISA_LO_MASK', 'CP_MES_MISA_LO__MISA_LO__SHIFT', + 'CP_MES_MSCRATCH_HI__DATA_MASK', + 'CP_MES_MSCRATCH_HI__DATA__SHIFT', + 'CP_MES_MSCRATCH_LO__DATA_MASK', + 'CP_MES_MSCRATCH_LO__DATA__SHIFT', + 'CP_MES_MSTATUS_HI__STATUS_HI_MASK', + 'CP_MES_MSTATUS_HI__STATUS_HI__SHIFT', + 'CP_MES_MSTATUS_LO__STATUS_LO_MASK', + 'CP_MES_MSTATUS_LO__STATUS_LO__SHIFT', + 'CP_MES_MTIMECMP_HI__TIME_HI_MASK', + 'CP_MES_MTIMECMP_HI__TIME_HI__SHIFT', + 'CP_MES_MTIMECMP_LO__TIME_LO_MASK', + 'CP_MES_MTIMECMP_LO__TIME_LO__SHIFT', + 'CP_MES_MTIME_HI__TIME_HI_MASK', + 'CP_MES_MTIME_HI__TIME_HI__SHIFT', + 'CP_MES_MTIME_LO__TIME_LO_MASK', + 'CP_MES_MTIME_LO__TIME_LO__SHIFT', + 'CP_MES_MTVEC_HI__ADDR_LO_MASK', + 'CP_MES_MTVEC_HI__ADDR_LO__SHIFT', + 'CP_MES_MTVEC_LO__ADDR_LO_MASK', + 'CP_MES_MTVEC_LO__ADDR_LO__SHIFT', + 'CP_MES_MVENDORID_HI__MVENDORID_HI_MASK', + 'CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT', + 'CP_MES_MVENDORID_LO__MVENDORID_LO_MASK', + 'CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT', + 'CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK', + 'CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT', + 'CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK', + 'CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT', + 'CP_MES_PIPE0_PRIORITY__PRIORITY_MASK', + 'CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT', + 'CP_MES_PIPE1_PRIORITY__PRIORITY_MASK', + 'CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT', + 'CP_MES_PIPE2_PRIORITY__PRIORITY_MASK', + 'CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT', + 'CP_MES_PIPE3_PRIORITY__PRIORITY_MASK', + 'CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_MES_PRGRM_CNTR_START_HI__IP_START_MASK', + 'CP_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT', + 'CP_MES_PRGRM_CNTR_START__IP_START_MASK', + 'CP_MES_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT', + 'CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK', + 'CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT', + 'CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK', + 'CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT', + 'CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK', + 'CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT', + 'CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK', + 'CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT', + 'CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK', + 'CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT', + 'CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK', + 'CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT', + 'CP_ME_CNTL__CE_HALT_MASK', 'CP_ME_CNTL__CE_HALT__SHIFT', + 'CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK', + 'CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT', + 'CP_ME_CNTL__CE_PIPE0_RESET_MASK', + 'CP_ME_CNTL__CE_PIPE0_RESET__SHIFT', + 'CP_ME_CNTL__CE_PIPE1_RESET_MASK', + 'CP_ME_CNTL__CE_PIPE1_RESET__SHIFT', 'CP_ME_CNTL__CE_STEP_MASK', + 'CP_ME_CNTL__CE_STEP__SHIFT', 'CP_ME_CNTL__ME_HALT_MASK', + 'CP_ME_CNTL__ME_HALT__SHIFT', + 'CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK', + 'CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT', + 'CP_ME_CNTL__ME_PIPE0_DISABLE_MASK', + 'CP_ME_CNTL__ME_PIPE0_DISABLE__SHIFT', + 'CP_ME_CNTL__ME_PIPE0_RESET_MASK', + 'CP_ME_CNTL__ME_PIPE0_RESET__SHIFT', + 'CP_ME_CNTL__ME_PIPE1_DISABLE_MASK', + 'CP_ME_CNTL__ME_PIPE1_DISABLE__SHIFT', + 'CP_ME_CNTL__ME_PIPE1_RESET_MASK', + 'CP_ME_CNTL__ME_PIPE1_RESET__SHIFT', 'CP_ME_CNTL__ME_STEP_MASK', + 'CP_ME_CNTL__ME_STEP__SHIFT', 'CP_ME_CNTL__PFP_HALT_MASK', + 'CP_ME_CNTL__PFP_HALT__SHIFT', + 'CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK', + 'CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT', + 'CP_ME_CNTL__PFP_PIPE0_DISABLE_MASK', + 'CP_ME_CNTL__PFP_PIPE0_DISABLE__SHIFT', + 'CP_ME_CNTL__PFP_PIPE0_RESET_MASK', + 'CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT', + 'CP_ME_CNTL__PFP_PIPE1_DISABLE_MASK', + 'CP_ME_CNTL__PFP_PIPE1_DISABLE__SHIFT', + 'CP_ME_CNTL__PFP_PIPE1_RESET_MASK', + 'CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT', 'CP_ME_CNTL__PFP_STEP_MASK', + 'CP_ME_CNTL__PFP_STEP__SHIFT', + 'CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK', + 'CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT', + 'CP_ME_COHER_BASE__COHER_BASE_256B_MASK', + 'CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT', + 'CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT', + 'CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK', + 'CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT', + 'CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK', + 'CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT', + 'CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK', + 'CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT', + 'CP_ME_COHER_STATUS__STATUS_MASK', + 'CP_ME_COHER_STATUS__STATUS__SHIFT', + 'CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK', + 'CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT', + 'CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK', + 'CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT', + 'CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK', + 'CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT', + 'CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK', + 'CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT', + 'CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK', + 'CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT', + 'CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK', + 'CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT', + 'CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK', + 'CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT', + 'CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK', + 'CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT', + 'CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK', + 'CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT', + 'CP_ME_IC_BASE_CNTL__VMID_MASK', + 'CP_ME_IC_BASE_CNTL__VMID__SHIFT', + 'CP_ME_IC_BASE_HI__IC_BASE_HI_MASK', + 'CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT', + 'CP_ME_IC_BASE_LO__IC_BASE_LO_MASK', + 'CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT', + 'CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK', + 'CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT', + 'CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK', + 'CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT', + 'CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK', + 'CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT', + 'CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK', + 'CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT', + 'CP_ME_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_ME_INTR_ROUTINE_START_HI__IR_START_MASK', + 'CP_ME_INTR_ROUTINE_START_HI__IR_START__SHIFT', + 'CP_ME_INTR_ROUTINE_START__IR_START_MASK', + 'CP_ME_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK', + 'CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT', + 'CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK', + 'CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT', + 'CP_ME_MC_RADDR_HI__PRIVILEGE_MASK', + 'CP_ME_MC_RADDR_HI__PRIVILEGE__SHIFT', + 'CP_ME_MC_RADDR_HI__SIZE_MASK', 'CP_ME_MC_RADDR_HI__SIZE__SHIFT', + 'CP_ME_MC_RADDR_HI__VMID_MASK', 'CP_ME_MC_RADDR_HI__VMID__SHIFT', + 'CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK', + 'CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT', + 'CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK', + 'CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT', + 'CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK', + 'CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT', + 'CP_ME_MC_WADDR_HI__PRIVILEGE_MASK', + 'CP_ME_MC_WADDR_HI__PRIVILEGE__SHIFT', + 'CP_ME_MC_WADDR_HI__RINGID_MASK', + 'CP_ME_MC_WADDR_HI__RINGID__SHIFT', + 'CP_ME_MC_WADDR_HI__VMID_MASK', 'CP_ME_MC_WADDR_HI__VMID__SHIFT', + 'CP_ME_MC_WADDR_HI__WRITE64_MASK', + 'CP_ME_MC_WADDR_HI__WRITE64__SHIFT', + 'CP_ME_MC_WADDR_HI__WRITE_CONFIRM_MASK', + 'CP_ME_MC_WADDR_HI__WRITE_CONFIRM__SHIFT', + 'CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK', + 'CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT', + 'CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK', + 'CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT', + 'CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK', + 'CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT', + 'CP_ME_PREEMPTION__OBSOLETE_MASK', + 'CP_ME_PREEMPTION__OBSOLETE__SHIFT', + 'CP_ME_PRGRM_CNTR_START_HI__IP_START_MASK', + 'CP_ME_PRGRM_CNTR_START_HI__IP_START__SHIFT', + 'CP_ME_PRGRM_CNTR_START__IP_START_MASK', + 'CP_ME_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_ME_RAM_DATA__ME_RAM_DATA_MASK', + 'CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT', + 'CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK', + 'CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT', + 'CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK', + 'CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT', + 'CP_ME_SDMA_CS__REQUEST_GRANT_MASK', + 'CP_ME_SDMA_CS__REQUEST_GRANT__SHIFT', + 'CP_ME_SDMA_CS__REQUEST_POSITION_MASK', + 'CP_ME_SDMA_CS__REQUEST_POSITION__SHIFT', + 'CP_ME_SDMA_CS__SDMA_COUNT_MASK', + 'CP_ME_SDMA_CS__SDMA_COUNT__SHIFT', 'CP_ME_SDMA_CS__SDMA_ID_MASK', + 'CP_ME_SDMA_CS__SDMA_ID__SHIFT', + 'CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CP_MQD_BASE_ADDR__BASE_ADDR_MASK', + 'CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT', + 'CP_MQD_CONTROL__CACHE_POLICY_MASK', + 'CP_MQD_CONTROL__CACHE_POLICY__SHIFT', + 'CP_MQD_CONTROL__EXE_DISABLE_MASK', + 'CP_MQD_CONTROL__EXE_DISABLE__SHIFT', + 'CP_MQD_CONTROL__MQD_VOLATILE_MASK', + 'CP_MQD_CONTROL__MQD_VOLATILE__SHIFT', + 'CP_MQD_CONTROL__PRIV_STATE_MASK', + 'CP_MQD_CONTROL__PRIV_STATE__SHIFT', + 'CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK', + 'CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT', + 'CP_MQD_CONTROL__PROCESSING_MQD_MASK', + 'CP_MQD_CONTROL__PROCESSING_MQD__SHIFT', + 'CP_MQD_CONTROL__VMID_MASK', 'CP_MQD_CONTROL__VMID__SHIFT', + 'CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK', + 'CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT', + 'CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK', + 'CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT', + 'CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK', + 'CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT', + 'CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK', + 'CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT', + 'CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI_MASK', + 'CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI__SHIFT', + 'CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO_MASK', + 'CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO__SHIFT', + 'CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK', + 'CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT', + 'CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK', + 'CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT', + 'CP_PERFMON_CNTL__PERFMON_STATE_MASK', + 'CP_PERFMON_CNTL__PERFMON_STATE__SHIFT', + 'CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK', + 'CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT', + 'CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK', + 'CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT', + 'CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK', + 'CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT', + 'CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK', + 'CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT', + 'CP_PFP_COMPLETION_STATUS__STATUS_MASK', + 'CP_PFP_COMPLETION_STATUS__STATUS__SHIFT', + 'CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK', + 'CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT', + 'CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK', + 'CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT', + 'CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK', + 'CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT', + 'CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK', + 'CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK', + 'CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT', + 'CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK', + 'CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT', + 'CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK', + 'CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT', + 'CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK', + 'CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT', + 'CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK', + 'CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT', + 'CP_PFP_IB_CONTROL__IB_EN_MASK', + 'CP_PFP_IB_CONTROL__IB_EN__SHIFT', + 'CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK', + 'CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT', + 'CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK', + 'CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT', + 'CP_PFP_IC_BASE_CNTL__VMID_MASK', + 'CP_PFP_IC_BASE_CNTL__VMID__SHIFT', + 'CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK', + 'CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT', + 'CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK', + 'CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT', + 'CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK', + 'CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT', + 'CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK', + 'CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT', + 'CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK', + 'CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT', + 'CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK', + 'CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT', + 'CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_PFP_INTR_ROUTINE_START_HI__IR_START_MASK', + 'CP_PFP_INTR_ROUTINE_START_HI__IR_START__SHIFT', + 'CP_PFP_INTR_ROUTINE_START__IR_START_MASK', + 'CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_PFP_JT_STAT__JT_LOADED_MASK', + 'CP_PFP_JT_STAT__JT_LOADED__SHIFT', + 'CP_PFP_JT_STAT__WR_MASK_MASK', 'CP_PFP_JT_STAT__WR_MASK__SHIFT', + 'CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT', + 'CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT', + 'CP_PFP_LOAD_CONTROL__LOAD_ORDINAL_MASK', + 'CP_PFP_LOAD_CONTROL__LOAD_ORDINAL__SHIFT', + 'CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT', + 'CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT', + 'CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT', + 'CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK', + 'CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK', + 'CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT', + 'CP_PFP_PRGRM_CNTR_START_HI__IP_START_MASK', + 'CP_PFP_PRGRM_CNTR_START_HI__IP_START__SHIFT', + 'CP_PFP_PRGRM_CNTR_START__IP_START_MASK', + 'CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_PFP_SDMA_CS__REQUEST_GRANT_MASK', + 'CP_PFP_SDMA_CS__REQUEST_GRANT__SHIFT', + 'CP_PFP_SDMA_CS__REQUEST_POSITION_MASK', + 'CP_PFP_SDMA_CS__REQUEST_POSITION__SHIFT', + 'CP_PFP_SDMA_CS__SDMA_COUNT_MASK', + 'CP_PFP_SDMA_CS__SDMA_COUNT__SHIFT', + 'CP_PFP_SDMA_CS__SDMA_ID_MASK', 'CP_PFP_SDMA_CS__SDMA_ID__SHIFT', + 'CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_PFP_UCODE_DATA__UCODE_DATA_MASK', + 'CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT', 'CP_PIPEID__PIPE_ID_MASK', + 'CP_PIPEID__PIPE_ID__SHIFT', + 'CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK', + 'CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT', + 'CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK', + 'CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT', + 'CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK', + 'CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT', + 'CP_PQ_STATUS__DOORBELL_ENABLE_MASK', + 'CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT', + 'CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK', + 'CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT', + 'CP_PQ_STATUS__DOORBELL_UPDATED_MASK', + 'CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK', + 'CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT', + 'CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK', + 'CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK', + 'CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__EN_MASK', + 'CP_PQ_WPTR_POLL_CNTL__EN__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK', + 'CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK', + 'CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT', + 'CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK', + 'CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT', + 'CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK', + 'CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT', + 'CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK', + 'CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT', + 'CP_PROCESS_QUANTUM__QUANTUM_EN_MASK', + 'CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT', + 'CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK', + 'CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT', + 'CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK', + 'CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT', + 'CP_RB0_ACTIVE__ACTIVE_MASK', 'CP_RB0_ACTIVE__ACTIVE__SHIFT', + 'CP_RB0_BASE_HI__RB_BASE_HI_MASK', + 'CP_RB0_BASE_HI__RB_BASE_HI__SHIFT', 'CP_RB0_BASE__RB_BASE_MASK', + 'CP_RB0_BASE__RB_BASE__SHIFT', 'CP_RB0_BUFSZ_MASK__DATA_MASK', + 'CP_RB0_BUFSZ_MASK__DATA__SHIFT', + 'CP_RB0_CNTL__CACHE_POLICY_MASK', + 'CP_RB0_CNTL__CACHE_POLICY__SHIFT', 'CP_RB0_CNTL__KMD_QUEUE_MASK', + 'CP_RB0_CNTL__KMD_QUEUE__SHIFT', 'CP_RB0_CNTL__MIN_AVAILSZ_MASK', + 'CP_RB0_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT', + 'CP_RB0_CNTL__RB_BLKSZ_MASK', 'CP_RB0_CNTL__RB_BLKSZ__SHIFT', + 'CP_RB0_CNTL__RB_BUFSZ_MASK', 'CP_RB0_CNTL__RB_BUFSZ__SHIFT', + 'CP_RB0_CNTL__RB_EXE_MASK', 'CP_RB0_CNTL__RB_EXE__SHIFT', + 'CP_RB0_CNTL__RB_NON_PRIV_MASK', + 'CP_RB0_CNTL__RB_NON_PRIV__SHIFT', + 'CP_RB0_CNTL__RB_NO_UPDATE_MASK', + 'CP_RB0_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_RB0_CNTL__RB_VOLATILE_MASK', + 'CP_RB0_CNTL__RB_VOLATILE__SHIFT', 'CP_RB0_CNTL__TMZ_MATCH_MASK', + 'CP_RB0_CNTL__TMZ_MATCH__SHIFT', 'CP_RB0_CNTL__TMZ_STATE_MASK', + 'CP_RB0_CNTL__TMZ_STATE__SHIFT', + 'CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_RB0_RPTR__RB_RPTR_MASK', 'CP_RB0_RPTR__RB_RPTR__SHIFT', + 'CP_RB0_WPTR_HI__RB_WPTR_MASK', 'CP_RB0_WPTR_HI__RB_WPTR__SHIFT', + 'CP_RB0_WPTR__RB_WPTR_MASK', 'CP_RB0_WPTR__RB_WPTR__SHIFT', + 'CP_RB1_ACTIVE__ACTIVE_MASK', 'CP_RB1_ACTIVE__ACTIVE__SHIFT', + 'CP_RB1_BASE_HI__RB_BASE_HI_MASK', + 'CP_RB1_BASE_HI__RB_BASE_HI__SHIFT', 'CP_RB1_BASE__RB_BASE_MASK', + 'CP_RB1_BASE__RB_BASE__SHIFT', 'CP_RB1_BUFSZ_MASK__DATA_MASK', + 'CP_RB1_BUFSZ_MASK__DATA__SHIFT', + 'CP_RB1_CNTL__CACHE_POLICY_MASK', + 'CP_RB1_CNTL__CACHE_POLICY__SHIFT', 'CP_RB1_CNTL__KMD_QUEUE_MASK', + 'CP_RB1_CNTL__KMD_QUEUE__SHIFT', 'CP_RB1_CNTL__MIN_AVAILSZ_MASK', + 'CP_RB1_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT', + 'CP_RB1_CNTL__RB_BLKSZ_MASK', 'CP_RB1_CNTL__RB_BLKSZ__SHIFT', + 'CP_RB1_CNTL__RB_BUFSZ_MASK', 'CP_RB1_CNTL__RB_BUFSZ__SHIFT', + 'CP_RB1_CNTL__RB_EXE_MASK', 'CP_RB1_CNTL__RB_EXE__SHIFT', + 'CP_RB1_CNTL__RB_NON_PRIV_MASK', + 'CP_RB1_CNTL__RB_NON_PRIV__SHIFT', + 'CP_RB1_CNTL__RB_NO_UPDATE_MASK', + 'CP_RB1_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_RB1_CNTL__RB_VOLATILE_MASK', + 'CP_RB1_CNTL__RB_VOLATILE__SHIFT', 'CP_RB1_CNTL__TMZ_MATCH_MASK', + 'CP_RB1_CNTL__TMZ_MATCH__SHIFT', 'CP_RB1_CNTL__TMZ_STATE_MASK', + 'CP_RB1_CNTL__TMZ_STATE__SHIFT', + 'CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_RB1_RPTR__RB_RPTR_MASK', 'CP_RB1_RPTR__RB_RPTR__SHIFT', + 'CP_RB1_WPTR_HI__RB_WPTR_MASK', 'CP_RB1_WPTR_HI__RB_WPTR__SHIFT', + 'CP_RB1_WPTR__RB_WPTR_MASK', 'CP_RB1_WPTR__RB_WPTR__SHIFT', + 'CP_RB_ACTIVE__ACTIVE_MASK', 'CP_RB_ACTIVE__ACTIVE__SHIFT', + 'CP_RB_BASE__RB_BASE_MASK', 'CP_RB_BASE__RB_BASE__SHIFT', + 'CP_RB_BUFSZ_MASK__DATA_MASK', 'CP_RB_BUFSZ_MASK__DATA__SHIFT', + 'CP_RB_CNTL__CACHE_POLICY_MASK', + 'CP_RB_CNTL__CACHE_POLICY__SHIFT', 'CP_RB_CNTL__KMD_QUEUE_MASK', + 'CP_RB_CNTL__KMD_QUEUE__SHIFT', 'CP_RB_CNTL__MIN_AVAILSZ_MASK', + 'CP_RB_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_RB_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT', 'CP_RB_CNTL__RB_BLKSZ_MASK', + 'CP_RB_CNTL__RB_BLKSZ__SHIFT', 'CP_RB_CNTL__RB_BUFSZ_MASK', + 'CP_RB_CNTL__RB_BUFSZ__SHIFT', 'CP_RB_CNTL__RB_EXE_MASK', + 'CP_RB_CNTL__RB_EXE__SHIFT', 'CP_RB_CNTL__RB_NON_PRIV_MASK', + 'CP_RB_CNTL__RB_NON_PRIV__SHIFT', 'CP_RB_CNTL__RB_NO_UPDATE_MASK', + 'CP_RB_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_RB_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_RB_CNTL__RB_VOLATILE_MASK', 'CP_RB_CNTL__RB_VOLATILE__SHIFT', + 'CP_RB_CNTL__TMZ_MATCH_MASK', 'CP_RB_CNTL__TMZ_MATCH__SHIFT', + 'CP_RB_CNTL__TMZ_STATE_MASK', 'CP_RB_CNTL__TMZ_STATE__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK', + 'CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT', + 'CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK', + 'CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT', + 'CP_RB_OFFSET__RB_OFFSET_MASK', 'CP_RB_OFFSET__RB_OFFSET__SHIFT', + 'CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_RB_RPTR_WR__RB_RPTR_WR_MASK', + 'CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT', 'CP_RB_RPTR__RB_RPTR_MASK', + 'CP_RB_RPTR__RB_RPTR__SHIFT', + 'CP_RB_STATUS__DOORBELL_ENABLE_MASK', + 'CP_RB_STATUS__DOORBELL_ENABLE__SHIFT', + 'CP_RB_STATUS__DOORBELL_UPDATED_MASK', + 'CP_RB_STATUS__DOORBELL_UPDATED__SHIFT', + 'CP_RB_VMID__RB0_VMID_MASK', 'CP_RB_VMID__RB0_VMID__SHIFT', + 'CP_RB_VMID__RB1_VMID_MASK', 'CP_RB_VMID__RB1_VMID__SHIFT', + 'CP_RB_VMID__RB2_VMID_MASK', 'CP_RB_VMID__RB2_VMID__SHIFT', + 'CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK', + 'CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT', + 'CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK', + 'CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT', + 'CP_RB_WPTR_HI__RB_WPTR_MASK', 'CP_RB_WPTR_HI__RB_WPTR__SHIFT', + 'CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK', + 'CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT', + 'CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK', + 'CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT', + 'CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK', + 'CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT', + 'CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK', + 'CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT', + 'CP_RB_WPTR__RB_WPTR_MASK', 'CP_RB_WPTR__RB_WPTR__SHIFT', + 'CP_RING0_PRIORITY__PRIORITY_MASK', + 'CP_RING0_PRIORITY__PRIORITY__SHIFT', + 'CP_RING1_PRIORITY__PRIORITY_MASK', + 'CP_RING1_PRIORITY__PRIORITY__SHIFT', 'CP_RINGID__RINGID_MASK', + 'CP_RINGID__RINGID__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK', + 'CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT', + 'CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK', + 'CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT', + 'CP_ROQ1_THRESHOLDS__RB1_START_MASK', + 'CP_ROQ1_THRESHOLDS__RB1_START__SHIFT', + 'CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK', + 'CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT', + 'CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK', + 'CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT', + 'CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK', + 'CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT', + 'CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK', + 'CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT', + 'CP_ROQ3_THRESHOLDS__R0_DB_START_MASK', + 'CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT', + 'CP_ROQ3_THRESHOLDS__R1_DB_START_MASK', + 'CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT', + 'CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK', + 'CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT', + 'CP_ROQ_AVAIL__ROQ_CNT_RING_MASK', + 'CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT', + 'CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK', + 'CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT', + 'CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK', + 'CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT', + 'CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK', + 'CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT', + 'CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK', + 'CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT', + 'CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK', + 'CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT', + 'CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK', + 'CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT', + 'CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK', + 'CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT', + 'CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK', + 'CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT', + 'CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK', + 'CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT', + 'CP_SCRATCH_DATA__SCRATCH_DATA_MASK', + 'CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT', + 'CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK', + 'CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT', + 'CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK', + 'CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT', + 'CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK', + 'CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT', + 'CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK', + 'CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT', + 'CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK', + 'CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT', + 'CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK', + 'CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT', + 'CP_SDMA_DMA_DONE__SDMA_ID_MASK', + 'CP_SDMA_DMA_DONE__SDMA_ID__SHIFT', 'CP_SD_CNTL__CPC_EN_MASK', + 'CP_SD_CNTL__CPC_EN__SHIFT', 'CP_SD_CNTL__CPF_EN_MASK', + 'CP_SD_CNTL__CPF_EN__SHIFT', 'CP_SD_CNTL__CPG_EN_MASK', + 'CP_SD_CNTL__CPG_EN__SHIFT', 'CP_SD_CNTL__EA_EN_MASK', + 'CP_SD_CNTL__EA_EN__SHIFT', 'CP_SD_CNTL__GE_EN_MASK', + 'CP_SD_CNTL__GE_EN__SHIFT', 'CP_SD_CNTL__RLC_EN_MASK', + 'CP_SD_CNTL__RLC_EN__SHIFT', 'CP_SD_CNTL__SDMA_EN_MASK', + 'CP_SD_CNTL__SDMA_EN__SHIFT', + 'CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK', + 'CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT', + 'CP_SD_CNTL__UTCL1_EN_MASK', 'CP_SD_CNTL__UTCL1_EN__SHIFT', + 'CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK', + 'CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT', + 'CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK', + 'CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT', + 'CP_SIG_SEM_ADDR_LO__SEM_PRIV_MASK', + 'CP_SIG_SEM_ADDR_LO__SEM_PRIV__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET_MASK', + 'CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK', + 'CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK', + 'CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK', + 'CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT', + 'CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK', + 'CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT', + 'CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK', + 'CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK', + 'CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT', + 'CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK', + 'CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK', + 'CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK', + 'CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0_MASK', + 'CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1_MASK', + 'CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1__SHIFT', + 'CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK', + 'CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT', + 'CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK', + 'CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT', + 'CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK', + 'CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT', + 'CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK', + 'CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK', + 'CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT', + 'CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT', + 'CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK', + 'CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT', + 'CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK', + 'CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT', + 'CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK', + 'CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT', + 'CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK', + 'CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT', + 'CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK', + 'CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT', + 'CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK', + 'CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK', + 'CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT', + 'CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK', + 'CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT', + 'CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK', + 'CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT', + 'CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK', + 'CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT', + 'CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK', + 'CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK', + 'CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT', + 'CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK', + 'CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT', + 'CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK', + 'CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT', + 'CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT', + 'CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK', + 'CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT', + 'CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK', + 'CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT', + 'CP_STAT__CE_BUSY_MASK', 'CP_STAT__CE_BUSY__SHIFT', + 'CP_STAT__CP_BUSY_MASK', 'CP_STAT__CP_BUSY__SHIFT', + 'CP_STAT__DC_BUSY_MASK', 'CP_STAT__DC_BUSY__SHIFT', + 'CP_STAT__DMA_BUSY_MASK', 'CP_STAT__DMA_BUSY__SHIFT', + 'CP_STAT__GCRIU_BUSY_MASK', 'CP_STAT__GCRIU_BUSY__SHIFT', + 'CP_STAT__INTERRUPT_BUSY_MASK', 'CP_STAT__INTERRUPT_BUSY__SHIFT', + 'CP_STAT__MEQ_BUSY_MASK', 'CP_STAT__MEQ_BUSY__SHIFT', + 'CP_STAT__ME_BUSY_MASK', 'CP_STAT__ME_BUSY__SHIFT', + 'CP_STAT__PFP_BUSY_MASK', 'CP_STAT__PFP_BUSY__SHIFT', + 'CP_STAT__QUERY_BUSY_MASK', 'CP_STAT__QUERY_BUSY__SHIFT', + 'CP_STAT__RCIU_BUSY_MASK', 'CP_STAT__RCIU_BUSY__SHIFT', + 'CP_STAT__ROQ_CE_DB_BUSY_MASK', 'CP_STAT__ROQ_CE_DB_BUSY__SHIFT', + 'CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK', + 'CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT', + 'CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK', + 'CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT', + 'CP_STAT__ROQ_CE_RING_BUSY_MASK', + 'CP_STAT__ROQ_CE_RING_BUSY__SHIFT', 'CP_STAT__ROQ_DB_BUSY_MASK', + 'CP_STAT__ROQ_DB_BUSY__SHIFT', 'CP_STAT__ROQ_INDIRECT1_BUSY_MASK', + 'CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT', + 'CP_STAT__ROQ_INDIRECT2_BUSY_MASK', + 'CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT', + 'CP_STAT__ROQ_RING_BUSY_MASK', 'CP_STAT__ROQ_RING_BUSY__SHIFT', + 'CP_STAT__ROQ_STATE_BUSY_MASK', 'CP_STAT__ROQ_STATE_BUSY__SHIFT', + 'CP_STAT__SCRATCH_RAM_BUSY_MASK', + 'CP_STAT__SCRATCH_RAM_BUSY__SHIFT', + 'CP_STAT__SEMAPHORE_BUSY_MASK', 'CP_STAT__SEMAPHORE_BUSY__SHIFT', + 'CP_STAT__SURFACE_SYNC_BUSY_MASK', + 'CP_STAT__SURFACE_SYNC_BUSY__SHIFT', 'CP_STAT__TCIU_BUSY_MASK', + 'CP_STAT__TCIU_BUSY__SHIFT', 'CP_STAT__UTCL2IU_BUSY_MASK', + 'CP_STAT__UTCL2IU_BUSY__SHIFT', 'CP_STQ_AVAIL__STQ_CNT_MASK', + 'CP_STQ_AVAIL__STQ_CNT__SHIFT', 'CP_STQ_STAT__STQ_RPTR_MASK', + 'CP_STQ_STAT__STQ_RPTR__SHIFT', + 'CP_STQ_THRESHOLDS__STQ0_START_MASK', + 'CP_STQ_THRESHOLDS__STQ0_START__SHIFT', + 'CP_STQ_THRESHOLDS__STQ1_START_MASK', + 'CP_STQ_THRESHOLDS__STQ1_START__SHIFT', + 'CP_STQ_THRESHOLDS__STQ2_START_MASK', + 'CP_STQ_THRESHOLDS__STQ2_START__SHIFT', + 'CP_STQ_WR_STAT__STQ_WPTR_MASK', + 'CP_STQ_WR_STAT__STQ_WPTR__SHIFT', + 'CP_ST_BASE_HI__ST_BASE_HI_MASK', + 'CP_ST_BASE_HI__ST_BASE_HI__SHIFT', + 'CP_ST_BASE_LO__ST_BASE_LO_MASK', + 'CP_ST_BASE_LO__ST_BASE_LO__SHIFT', 'CP_ST_BUFSZ__ST_BUFSZ_MASK', + 'CP_ST_BUFSZ__ST_BUFSZ__SHIFT', + 'CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK', + 'CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT', + 'CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK', + 'CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT', + 'CP_SUSPEND_CNTL__RESUME_LOCK_MASK', + 'CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT', + 'CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK', + 'CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT', + 'CP_SUSPEND_CNTL__SUSPEND_MODE_MASK', + 'CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT', + 'CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK', + 'CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT', + 'CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK', + 'CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT', + 'CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI_MASK', + 'CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI__SHIFT', + 'CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO_MASK', + 'CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO__SHIFT', + 'CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK', + 'CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK', + 'CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK', + 'CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK', + 'CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK', + 'CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK', + 'CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK', + 'CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT', + 'CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK', + 'CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT', + 'CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK', + 'CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK', + 'CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK', + 'CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT', + 'CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK', + 'CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT', + 'CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK', + 'CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT', + 'CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK', + 'CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT', + 'CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK', + 'CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK', + 'CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT', + 'CP_VIRT_STATUS__VIRT_STATUS_MASK', + 'CP_VIRT_STATUS__VIRT_STATUS__SHIFT', + 'CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK', + 'CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT', + 'CP_VMID_PREEMPT__VIRT_COMMAND_MASK', + 'CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT', + 'CP_VMID_RESET__PIPE0_QUEUES_MASK', + 'CP_VMID_RESET__PIPE0_QUEUES__SHIFT', + 'CP_VMID_RESET__PIPE1_QUEUES_MASK', + 'CP_VMID_RESET__PIPE1_QUEUES__SHIFT', + 'CP_VMID_RESET__RESET_REQUEST_MASK', + 'CP_VMID_RESET__RESET_REQUEST__SHIFT', + 'CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK', + 'CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT', + 'CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK', + 'CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT', 'CP_VMID__VMID_MASK', + 'CP_VMID__VMID__SHIFT', + 'CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK', + 'CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT', + 'CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK', + 'CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT', + 'CP_WAIT_SEM_ADDR_LO__SEM_PRIV_MASK', + 'CP_WAIT_SEM_ADDR_LO__SEM_PRIV__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT', + 'DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK', + 'DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT', + 'DB_CGTT_CLK_CTRL_0__RESERVED_MASK', + 'DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8__SHIFT', + 'DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK', + 'DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK', + 'DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT', + 'DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK', + 'DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT', + 'DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK', + 'DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT', + 'DB_COUNT_CONTROL__SAMPLE_RATE_MASK', + 'DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT', + 'DB_COUNT_CONTROL__SFAIL_ENABLE_MASK', + 'DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK', + 'DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK', + 'DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK', + 'DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__ZPASS_ENABLE_MASK', + 'DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT', + 'DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT', + 'DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS__SHIFT', + 'DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT', + 'DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT', + 'DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS__SHIFT', + 'DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK', + 'DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT', + 'DB_DEBUG2__CLK_OFF_DELAY_MASK', + 'DB_DEBUG2__CLK_OFF_DELAY__SHIFT', + 'DB_DEBUG2__DEBUG_BUS_FLOP_EN_MASK', + 'DB_DEBUG2__DEBUG_BUS_FLOP_EN__SHIFT', + 'DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK', + 'DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT', + 'DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK_MASK', + 'DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT', + 'DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK', + 'DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT', + 'DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK', + 'DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT', + 'DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK', + 'DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT', + 'DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK', + 'DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT', + 'DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK', + 'DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT', + 'DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK', + 'DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT', + 'DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK', + 'DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT', + 'DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK', + 'DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT', + 'DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK', + 'DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT', + 'DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK', + 'DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT', + 'DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES_MASK', + 'DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES__SHIFT', + 'DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK', + 'DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT', + 'DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK', + 'DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT', + 'DB_DEBUG2__FORCE_ITERATE_256_MASK', + 'DB_DEBUG2__FORCE_ITERATE_256__SHIFT', + 'DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK', + 'DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT', + 'DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK', + 'DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT', + 'DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK', + 'DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT', + 'DB_DEBUG2__RESERVED1_MASK', 'DB_DEBUG2__RESERVED1__SHIFT', + 'DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK', + 'DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT', + 'DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK', + 'DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT', + 'DB_DEBUG3__DISABLE_DI_DT_STALL_MASK', + 'DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT', + 'DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK', + 'DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT', + 'DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK', + 'DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT', + 'DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK', + 'DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT', + 'DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK', + 'DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT', + 'DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK', + 'DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT', + 'DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK', + 'DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT', + 'DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK', + 'DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT', + 'DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK', + 'DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT', + 'DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK', + 'DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT', + 'DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK', + 'DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT', + 'DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK', + 'DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT', + 'DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK', + 'DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT', + 'DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK', + 'DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT', + 'DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK', + 'DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT', + 'DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK', + 'DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT', + 'DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK', + 'DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT', + 'DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK', + 'DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT', + 'DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK', + 'DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT', + 'DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK', + 'DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT', + 'DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK', + 'DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT', + 'DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK', + 'DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT', + 'DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK', + 'DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT', + 'DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK', + 'DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT', + 'DB_DEBUG3__FORCE_DB_IS_GOOD_MASK', + 'DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT', + 'DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK', + 'DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT', + 'DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK', + 'DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT', + 'DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK', + 'DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT', + 'DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK', + 'DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT', + 'DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK', + 'DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT', + 'DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK', + 'DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT', + 'DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK', + 'DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT', + 'DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK', + 'DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT', + 'DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK', + 'DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT', + 'DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK', + 'DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT', + 'DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK', + 'DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT', + 'DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK', + 'DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT', + 'DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK', + 'DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT', + 'DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK', + 'DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT', + 'DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK_MASK', + 'DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK__SHIFT', + 'DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK', + 'DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT', + 'DB_DEBUG4__DISABLE_SEPARATE_SX_CLK_MASK', + 'DB_DEBUG4__DISABLE_SEPARATE_SX_CLK__SHIFT', + 'DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK', + 'DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT', + 'DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK', + 'DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT', + 'DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK', + 'DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT', + 'DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK', + 'DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT', + 'DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK', + 'DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT', + 'DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK', + 'DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT', + 'DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK', + 'DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT', + 'DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD_MASK', + 'DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD__SHIFT', + 'DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK', + 'DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT', + 'DB_DEBUG4__WR_MEM_BURST_CTL_MASK', + 'DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT', + 'DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT_MASK', + 'DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT__SHIFT', + 'DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT_MASK', + 'DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT__SHIFT', + 'DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE_MASK', + 'DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE__SHIFT', + 'DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK', + 'DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT', + 'DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK', + 'DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT', + 'DB_DEBUG5__DISABLE_HTILE_HARVESTING_MASK', + 'DB_DEBUG5__DISABLE_HTILE_HARVESTING__SHIFT', + 'DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK', + 'DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT', + 'DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK', + 'DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT', + 'DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK', + 'DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT', + 'DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK', + 'DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT', + 'DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK', + 'DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT', + 'DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK', + 'DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT', + 'DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK_MASK', + 'DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK__SHIFT', + 'DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK_MASK', + 'DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK__SHIFT', + 'DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH_MASK', + 'DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH__SHIFT', + 'DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD_MASK', + 'DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD__SHIFT', + 'DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX_MASK', + 'DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX__SHIFT', + 'DB_DEBUG5__DISABLE_VRS_1X2_2XAA_MASK', + 'DB_DEBUG5__DISABLE_VRS_1X2_2XAA__SHIFT', + 'DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK', + 'DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT', + 'DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK', + 'DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT', + 'DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION_MASK', + 'DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION__SHIFT', + 'DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK', + 'DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT', + 'DB_DEBUG5__SPARE_BITS_MASK', 'DB_DEBUG5__SPARE_BITS__SHIFT', + 'DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK', + 'DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT', + 'DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK', + 'DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT', + 'DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT_MASK', + 'DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT__SHIFT', + 'DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX_MASK', + 'DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX__SHIFT', + 'DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC_MASK', + 'DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC__SHIFT', + 'DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL_MASK', + 'DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL__SHIFT', + 'DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL_MASK', + 'DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL__SHIFT', + 'DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT_MASK', + 'DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT__SHIFT', + 'DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT_MASK', + 'DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT__SHIFT', + 'DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT_MASK', + 'DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT__SHIFT', + 'DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK_MASK', + 'DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK__SHIFT', + 'DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL_MASK', + 'DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL__SHIFT', + 'DB_DEBUG6__OREO_TRANSITION_EVENT_ALL_MASK', + 'DB_DEBUG6__OREO_TRANSITION_EVENT_ALL__SHIFT', + 'DB_DEBUG6__OREO_TRANSITION_EVENT_EN_MASK', + 'DB_DEBUG6__OREO_TRANSITION_EVENT_EN__SHIFT', + 'DB_DEBUG6__OREO_TRANSITION_EVENT_ID_MASK', + 'DB_DEBUG6__OREO_TRANSITION_EVENT_ID__SHIFT', + 'DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID_MASK', + 'DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID__SHIFT', + 'DB_DEBUG7__SPARE_BITS_MASK', 'DB_DEBUG7__SPARE_BITS__SHIFT', + 'DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK', + 'DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK', + 'DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK', + 'DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK', + 'DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK', + 'DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK', + 'DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK', + 'DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT', + 'DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK', + 'DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK', + 'DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT', + 'DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK', + 'DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT', + 'DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK', + 'DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT', + 'DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK', + 'DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT', + 'DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK', + 'DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT', + 'DB_DEBUG__DISABLE_SUMM_SQUADS_MASK', + 'DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT', + 'DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK', + 'DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT', + 'DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK', + 'DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT', + 'DB_DEBUG__FETCH_FULL_Z_TILE_MASK', + 'DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT', + 'DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK', + 'DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT', + 'DB_DEBUG__FORCE_Z_MODE_MASK', 'DB_DEBUG__FORCE_Z_MODE__SHIFT', + 'DB_DEBUG__NEVER_FREE_Z_ONLY_MASK', + 'DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT', + 'DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK', + 'DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT', + 'DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK', + 'DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT', + 'DB_DEPTH_BOUNDS_MAX__MAX_MASK', + 'DB_DEPTH_BOUNDS_MAX__MAX__SHIFT', + 'DB_DEPTH_BOUNDS_MIN__MIN_MASK', + 'DB_DEPTH_BOUNDS_MIN__MIN__SHIFT', + 'DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK', + 'DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT', + 'DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK', + 'DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK', + 'DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK', + 'DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT', + 'DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK', + 'DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT', + 'DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK', + 'DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT', + 'DB_DEPTH_CONTROL__STENCILFUNC_MASK', + 'DB_DEPTH_CONTROL__STENCILFUNC__SHIFT', + 'DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK', + 'DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__ZFUNC_MASK', 'DB_DEPTH_CONTROL__ZFUNC__SHIFT', + 'DB_DEPTH_CONTROL__Z_ENABLE_MASK', + 'DB_DEPTH_CONTROL__Z_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK', + 'DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT', + 'DB_DEPTH_SIZE_XY__X_MAX_MASK', 'DB_DEPTH_SIZE_XY__X_MAX__SHIFT', + 'DB_DEPTH_SIZE_XY__Y_MAX_MASK', 'DB_DEPTH_SIZE_XY__Y_MAX__SHIFT', + 'DB_DEPTH_VIEW__MIPID_MASK', 'DB_DEPTH_VIEW__MIPID__SHIFT', + 'DB_DEPTH_VIEW__SLICE_MAX_HI_MASK', + 'DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT', + 'DB_DEPTH_VIEW__SLICE_MAX_MASK', + 'DB_DEPTH_VIEW__SLICE_MAX__SHIFT', + 'DB_DEPTH_VIEW__SLICE_START_HI_MASK', + 'DB_DEPTH_VIEW__SLICE_START_HI__SHIFT', + 'DB_DEPTH_VIEW__SLICE_START_MASK', + 'DB_DEPTH_VIEW__SLICE_START__SHIFT', + 'DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK', + 'DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT', + 'DB_DEPTH_VIEW__Z_READ_ONLY_MASK', + 'DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT', + 'DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK', + 'DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT', + 'DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK', + 'DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT', + 'DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK', + 'DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT', + 'DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK', + 'DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT', + 'DB_EQAA__INCOHERENT_EQAA_READS_MASK', + 'DB_EQAA__INCOHERENT_EQAA_READS__SHIFT', + 'DB_EQAA__INTERPOLATE_COMP_Z_MASK', + 'DB_EQAA__INTERPOLATE_COMP_Z__SHIFT', + 'DB_EQAA__INTERPOLATE_SRC_Z_MASK', + 'DB_EQAA__INTERPOLATE_SRC_Z__SHIFT', + 'DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK', + 'DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT', + 'DB_EQAA__MAX_ANCHOR_SAMPLES_MASK', + 'DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT', + 'DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK', + 'DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT', + 'DB_EQAA__PS_ITER_SAMPLES_MASK', + 'DB_EQAA__PS_ITER_SAMPLES__SHIFT', + 'DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK', + 'DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT', + 'DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK', + 'DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT', + 'DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK', + 'DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT', + 'DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK', + 'DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT', + 'DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK', + 'DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT', + 'DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK', + 'DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT', + 'DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK', + 'DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT', + 'DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK', + 'DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT', + 'DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK', + 'DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT', + 'DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK', + 'DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT', + 'DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK', + 'DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT', + 'DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK', + 'DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE_MASK', + 'DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK', + 'DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT', + 'DB_FIFO_DEPTH1__MCC_DEPTH_MASK', + 'DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT', + 'DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH1__QC_DEPTH_MASK', + 'DB_FIFO_DEPTH1__QC_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH_MASK', + 'DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH__SHIFT', + 'DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH_MASK', + 'DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH__SHIFT', + 'DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK', + 'DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT', + 'DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH_MASK', + 'DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH__SHIFT', + 'DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH_MASK', + 'DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH__SHIFT', + 'DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH_MASK', + 'DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT', + 'DB_HTILE_DATA_BASE_HI__BASE_HI_MASK', + 'DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT', + 'DB_HTILE_DATA_BASE__BASE_256B_MASK', + 'DB_HTILE_DATA_BASE__BASE_256B__SHIFT', + 'DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK', + 'DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT', + 'DB_HTILE_SURFACE__FULL_CACHE_MASK', + 'DB_HTILE_SURFACE__FULL_CACHE__SHIFT', + 'DB_HTILE_SURFACE__PIPE_ALIGNED_MASK', + 'DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT', + 'DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK', + 'DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT', + 'DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK', + 'DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT', + 'DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK', + 'DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT', + 'DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK', + 'DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT', + 'DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK', + 'DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT', + 'DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK', + 'DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK', + 'DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK', + 'DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE_MASK', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK', + 'DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK', + 'DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK', + 'DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK', + 'DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT', + 'DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK', + 'DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT', + 'DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK', + 'DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT', + 'DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK', + 'DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT', + 'DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK', + 'DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT', + 'DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK', + 'DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT', + 'DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT', + 'DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT', + 'DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT', + 'DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT', + 'DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'DB_PRELOAD_CONTROL__MAX_X_MASK', + 'DB_PRELOAD_CONTROL__MAX_X__SHIFT', + 'DB_PRELOAD_CONTROL__MAX_Y_MASK', + 'DB_PRELOAD_CONTROL__MAX_Y__SHIFT', + 'DB_PRELOAD_CONTROL__START_X_MASK', + 'DB_PRELOAD_CONTROL__START_X__SHIFT', + 'DB_PRELOAD_CONTROL__START_Y_MASK', + 'DB_PRELOAD_CONTROL__START_Y__SHIFT', + 'DB_RENDER_CONTROL__COPY_CENTROID_MASK', + 'DB_RENDER_CONTROL__COPY_CENTROID__SHIFT', + 'DB_RENDER_CONTROL__COPY_SAMPLE_MASK', + 'DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT', + 'DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK', + 'DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK', + 'DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK', + 'DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT', + 'DB_RENDER_CONTROL__DEPTH_COPY_MASK', + 'DB_RENDER_CONTROL__DEPTH_COPY__SHIFT', + 'DB_RENDER_CONTROL__FORCE_EXPORT_ORDER_MASK', + 'DB_RENDER_CONTROL__FORCE_EXPORT_ORDER__SHIFT', + 'DB_RENDER_CONTROL__FORCE_OREO_MODE_MASK', + 'DB_RENDER_CONTROL__FORCE_OREO_MODE__SHIFT', + 'DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE_MASK', + 'DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE__SHIFT', + 'DB_RENDER_CONTROL__OREO_MODE_MASK', + 'DB_RENDER_CONTROL__OREO_MODE__SHIFT', + 'DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK', + 'DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT', + 'DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK', + 'DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK', + 'DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK', + 'DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT', + 'DB_RENDER_CONTROL__STENCIL_COPY_MASK', + 'DB_RENDER_CONTROL__STENCIL_COPY__SHIFT', + 'DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK', + 'DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT', + 'DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK', + 'DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT', + 'DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK', + 'DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT', + 'DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK', + 'DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_NOZ_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_NOZ__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT', + 'DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK', + 'DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT', + 'DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK', + 'DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT', + 'DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK', + 'DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT', + 'DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK', + 'DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT', + 'DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK', + 'DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT', + 'DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK', + 'DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT', + 'DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK', + 'DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT', + 'DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK', + 'DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK', + 'DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK', + 'DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK', + 'DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK', + 'DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK', + 'DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT', + 'DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK', + 'DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT', + 'DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK', + 'DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT', + 'DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK', + 'DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK', + 'DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT', + 'DB_RESERVED_REG_1__FIELD_1_MASK', + 'DB_RESERVED_REG_1__FIELD_1__SHIFT', + 'DB_RESERVED_REG_1__FIELD_2_MASK', + 'DB_RESERVED_REG_1__FIELD_2__SHIFT', + 'DB_RESERVED_REG_2__FIELD_1_MASK', + 'DB_RESERVED_REG_2__FIELD_1__SHIFT', + 'DB_RESERVED_REG_2__FIELD_2_MASK', + 'DB_RESERVED_REG_2__FIELD_2__SHIFT', + 'DB_RESERVED_REG_2__FIELD_3_MASK', + 'DB_RESERVED_REG_2__FIELD_3__SHIFT', + 'DB_RESERVED_REG_2__FIELD_4_MASK', + 'DB_RESERVED_REG_2__FIELD_4__SHIFT', + 'DB_RESERVED_REG_2__FIELD_5_MASK', + 'DB_RESERVED_REG_2__FIELD_5__SHIFT', + 'DB_RESERVED_REG_2__FIELD_6_MASK', + 'DB_RESERVED_REG_2__FIELD_6__SHIFT', + 'DB_RESERVED_REG_2__FIELD_7_MASK', + 'DB_RESERVED_REG_2__FIELD_7__SHIFT', + 'DB_RESERVED_REG_2__FIELD_8_MASK', + 'DB_RESERVED_REG_2__FIELD_8__SHIFT', + 'DB_RESERVED_REG_3__FIELD_1_MASK', + 'DB_RESERVED_REG_3__FIELD_1__SHIFT', + 'DB_RING_CONTROL__COUNTER_CONTROL_MASK', + 'DB_RING_CONTROL__COUNTER_CONTROL__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC_MASK', + 'DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK', + 'DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK', + 'DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK', + 'DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__S_NOALLOC_MASK', + 'DB_RMI_L2_CACHE_CONTROL__S_NOALLOC__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK', + 'DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK', + 'DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC_MASK', + 'DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK', + 'DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK', + 'DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC_MASK', + 'DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK', + 'DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT', + 'DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK', + 'DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT', + 'DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK', + 'DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT', + 'DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK', + 'DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT', + 'DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK', + 'DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK', + 'DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT', + 'DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK', + 'DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT', + 'DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK', + 'DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT', + 'DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK', + 'DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT', + 'DB_SHADER_CONTROL__KILL_ENABLE_MASK', + 'DB_SHADER_CONTROL__KILL_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__OREO_BLEND_ENABLE_MASK', + 'DB_SHADER_CONTROL__OREO_BLEND_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE_MASK', + 'DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_MASK', + 'DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE__SHIFT', + 'DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK', + 'DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK', + 'DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT', + 'DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__Z_ORDER_MASK', + 'DB_SHADER_CONTROL__Z_ORDER__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT', + 'DB_STENCILREFMASK__STENCILMASK_MASK', + 'DB_STENCILREFMASK__STENCILMASK__SHIFT', + 'DB_STENCILREFMASK__STENCILOPVAL_MASK', + 'DB_STENCILREFMASK__STENCILOPVAL__SHIFT', + 'DB_STENCILREFMASK__STENCILTESTVAL_MASK', + 'DB_STENCILREFMASK__STENCILTESTVAL__SHIFT', + 'DB_STENCILREFMASK__STENCILWRITEMASK_MASK', + 'DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT', + 'DB_STENCIL_CLEAR__CLEAR_MASK', 'DB_STENCIL_CLEAR__CLEAR__SHIFT', + 'DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK', + 'DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT', + 'DB_STENCIL_CONTROL__STENCILFAIL_MASK', + 'DB_STENCIL_CONTROL__STENCILFAIL__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK', + 'DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZFAIL_MASK', + 'DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK', + 'DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZPASS_MASK', + 'DB_STENCIL_CONTROL__STENCILZPASS__SHIFT', + 'DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK', + 'DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT', + 'DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK', + 'DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT', + 'DB_STENCIL_INFO__FORMAT_MASK', 'DB_STENCIL_INFO__FORMAT__SHIFT', + 'DB_STENCIL_INFO__ITERATE_256_MASK', + 'DB_STENCIL_INFO__ITERATE_256__SHIFT', + 'DB_STENCIL_INFO__ITERATE_FLUSH_MASK', + 'DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT', + 'DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK', + 'DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT', + 'DB_STENCIL_INFO__RESERVED_FIELD_1_MASK', + 'DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT', + 'DB_STENCIL_INFO__SW_MODE_MASK', + 'DB_STENCIL_INFO__SW_MODE__SHIFT', + 'DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK', + 'DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT', + 'DB_STENCIL_READ_BASE_HI__BASE_HI_MASK', + 'DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT', + 'DB_STENCIL_READ_BASE__BASE_256B_MASK', + 'DB_STENCIL_READ_BASE__BASE_256B__SHIFT', + 'DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK', + 'DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT', + 'DB_STENCIL_WRITE_BASE__BASE_256B_MASK', + 'DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA16_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA16_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA16_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA1_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA1_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA1_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA2_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA2_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA2_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA4_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA4_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA4_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA8_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA8_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA8_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT', + 'DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK', + 'DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT', + 'DB_WATERMARKS__DEPTH_FLUSH_MASK', + 'DB_WATERMARKS__DEPTH_FLUSH__SHIFT', + 'DB_WATERMARKS__DEPTH_FREE_MASK', + 'DB_WATERMARKS__DEPTH_FREE__SHIFT', + 'DB_WATERMARKS__DEPTH_PENDING_FREE_MASK', + 'DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT', + 'DB_Z_INFO__ALLOW_EXPCLEAR_MASK', + 'DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT', + 'DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK', + 'DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT', + 'DB_Z_INFO__FAULT_BEHAVIOR_MASK', + 'DB_Z_INFO__FAULT_BEHAVIOR__SHIFT', 'DB_Z_INFO__FORMAT_MASK', + 'DB_Z_INFO__FORMAT__SHIFT', 'DB_Z_INFO__ITERATE_256_MASK', + 'DB_Z_INFO__ITERATE_256__SHIFT', 'DB_Z_INFO__ITERATE_FLUSH_MASK', + 'DB_Z_INFO__ITERATE_FLUSH__SHIFT', 'DB_Z_INFO__MAXMIP_MASK', + 'DB_Z_INFO__MAXMIP__SHIFT', 'DB_Z_INFO__NUM_SAMPLES_MASK', + 'DB_Z_INFO__NUM_SAMPLES__SHIFT', + 'DB_Z_INFO__PARTIALLY_RESIDENT_MASK', + 'DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT', + 'DB_Z_INFO__READ_SIZE_MASK', 'DB_Z_INFO__READ_SIZE__SHIFT', + 'DB_Z_INFO__RESERVED_FIELD_1_MASK', + 'DB_Z_INFO__RESERVED_FIELD_1__SHIFT', 'DB_Z_INFO__SW_MODE_MASK', + 'DB_Z_INFO__SW_MODE__SHIFT', + 'DB_Z_INFO__TILE_SURFACE_ENABLE_MASK', + 'DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT', + 'DB_Z_INFO__ZRANGE_PRECISION_MASK', + 'DB_Z_INFO__ZRANGE_PRECISION__SHIFT', + 'DB_Z_READ_BASE_HI__BASE_HI_MASK', + 'DB_Z_READ_BASE_HI__BASE_HI__SHIFT', + 'DB_Z_READ_BASE__BASE_256B_MASK', + 'DB_Z_READ_BASE__BASE_256B__SHIFT', + 'DB_Z_WRITE_BASE_HI__BASE_HI_MASK', + 'DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT', + 'DB_Z_WRITE_BASE__BASE_256B_MASK', + 'DB_Z_WRITE_BASE__BASE_256B__SHIFT', + 'DIDT_EDC_CTRL__EDC_ALGORITHM_MODE_MASK', + 'DIDT_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT', + 'DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK', + 'DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT', + 'DIDT_EDC_CTRL__EDC_AVGDIV_MASK', + 'DIDT_EDC_CTRL__EDC_AVGDIV__SHIFT', + 'DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK', + 'DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT', + 'DIDT_EDC_CTRL__EDC_EN_MASK', 'DIDT_EDC_CTRL__EDC_EN__SHIFT', + 'DIDT_EDC_CTRL__EDC_FORCE_STALL_MASK', + 'DIDT_EDC_CTRL__EDC_FORCE_STALL__SHIFT', + 'DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK', + 'DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT', + 'DIDT_EDC_CTRL__EDC_SW_RST_MASK', + 'DIDT_EDC_CTRL__EDC_SW_RST__SHIFT', + 'DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS_MASK', + 'DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS__SHIFT', + 'DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL_MASK', + 'DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL__SHIFT', + 'DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK', + 'DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT', + 'DIDT_EDC_CTRL__RLC_FORCE_STALL_EN_MASK', + 'DIDT_EDC_CTRL__RLC_FORCE_STALL_EN__SHIFT', + 'DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL_MASK', + 'DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL__SHIFT', + 'DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO_MASK', + 'DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO__SHIFT', + 'DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK', + 'DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT', + 'DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK', + 'DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT', + 'DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK', + 'DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT', + 'DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK', + 'DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT', + 'DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK', + 'DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT', + 'DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK', + 'DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT', + 'DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK', + 'DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT', + 'DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK', + 'DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT', + 'DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK', + 'DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT', + 'DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK', + 'DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT', + 'DIDT_EDC_STATUS__EDC_FSM_STATE_MASK', + 'DIDT_EDC_STATUS__EDC_FSM_STATE__SHIFT', + 'DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK', + 'DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT', + 'DIDT_EDC_THRESHOLD__EDC_THRESHOLD_MASK', + 'DIDT_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT', + 'DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN_MASK', + 'DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN__SHIFT', + 'DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN_MASK', + 'DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN__SHIFT', + 'DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE_MASK', + 'DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE__SHIFT', + 'DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN_MASK', + 'DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN__SHIFT', + 'DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN_MASK', + 'DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN__SHIFT', + 'DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN_MASK', + 'DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN__SHIFT', + 'DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK', + 'DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT', + 'DIDT_IND_DATA__DIDT_IND_DATA_MASK', + 'DIDT_IND_DATA__DIDT_IND_DATA__SHIFT', + 'DIDT_IND_INDEX__DIDT_IND_INDEX_MASK', + 'DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT', + 'DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK', + 'DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT', + 'DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK', + 'DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT', + 'DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK', + 'DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT', + 'DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK', + 'DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT', + 'DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK', + 'DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT', + 'DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK', + 'DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT', + 'DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK', + 'DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT', + 'DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE_MASK', + 'DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE__SHIFT', + 'DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN_MASK', + 'DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN__SHIFT', + 'DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST_MASK', + 'DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST__SHIFT', + 'DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN_MASK', + 'DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN__SHIFT', + 'DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE_MASK', + 'DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE__SHIFT', + 'DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS_MASK', + 'DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT', + 'EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE_MASK', + 'EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE__SHIFT', + 'EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER_MASK', + 'EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER__SHIFT', + 'EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK', + 'EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT', + 'EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN_MASK', + 'EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN__SHIFT', + 'EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE_MASK', + 'EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE__SHIFT', + 'EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW_MASK', + 'EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW__SHIFT', + 'EDC_HYSTERESIS_STAT__EDC_STATUS_MASK', + 'EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT', + 'EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL_MASK', + 'EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL__SHIFT', + 'EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK', + 'EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT', + 'EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK', + 'EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT', + 'EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK', + 'EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT', + 'EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK', + 'EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT', + 'EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK', + 'EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT', + 'FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK', + 'FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT', + 'GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK', + 'GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_PIPES_MASK', + 'GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_PKRS_MASK', + 'GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK', + 'GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK', + 'GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT', + 'GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK', + 'GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT', + 'GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK', + 'GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT', + 'GB_ADDR_CONFIG__NUM_PIPES_MASK', + 'GB_ADDR_CONFIG__NUM_PIPES__SHIFT', + 'GB_ADDR_CONFIG__NUM_PKRS_MASK', + 'GB_ADDR_CONFIG__NUM_PKRS__SHIFT', + 'GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK', + 'GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT', + 'GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK', + 'GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT', + 'GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK', + 'GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT', + 'GB_BACKEND_MAP__BACKEND_MAP_MASK', + 'GB_BACKEND_MAP__BACKEND_MAP__SHIFT', 'GB_EDC_MODE__BYPASS_MASK', + 'GB_EDC_MODE__BYPASS__SHIFT', 'GB_EDC_MODE__COUNT_FED_OUT_MASK', + 'GB_EDC_MODE__COUNT_FED_OUT__SHIFT', 'GB_EDC_MODE__DED_MODE_MASK', + 'GB_EDC_MODE__DED_MODE__SHIFT', + 'GB_EDC_MODE__FORCE_SEC_ON_DED_MASK', + 'GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT', + 'GB_EDC_MODE__GATE_FUE_MASK', 'GB_EDC_MODE__GATE_FUE__SHIFT', + 'GB_EDC_MODE__PROP_FED_MASK', 'GB_EDC_MODE__PROP_FED__SHIFT', + 'GB_GPU_ID__GPU_ID_MASK', 'GB_GPU_ID__GPU_ID__SHIFT', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK', + 'GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT', + 'GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT', + 'GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK', + 'GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT', + 'GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK', + 'GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT', + 'GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'GCEA_ERR_STATUS__FUE_FLAG_MASK', + 'GCEA_ERR_STATUS__FUE_FLAG__SHIFT', + 'GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK', + 'GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT', + 'GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK', + 'GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT', + 'GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK', + 'GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT', + 'GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK', + 'GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT', + 'GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK', + 'GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT', + 'GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK', + 'GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK', + 'GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK', + 'GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK', + 'GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK', + 'GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK', + 'GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK', + 'GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK', + 'GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT', + 'GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK', + 'GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK', + 'GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK', + 'GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT', + 'GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK', + 'GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT', + 'GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE_MASK', + 'GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE__SHIFT', + 'GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE_MASK', + 'GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE_MASK', + 'GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE_MASK', + 'GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP_MASK', + 'GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE_MASK', + 'GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER_MASK', + 'GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT_MASK', + 'GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT__SHIFT', + 'GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY_MASK', + 'GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY__SHIFT', + 'GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY_MASK', + 'GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY__SHIFT', + 'GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT_MASK', + 'GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT__SHIFT', + 'GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE_MASK', + 'GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE__SHIFT', + 'GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE_MASK', + 'GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE__SHIFT', + 'GCEA_MAM_CTRL2__RESERVED_FIELD_MASK', + 'GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT', + 'GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE_MASK', + 'GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE__SHIFT', + 'GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC_MASK', + 'GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC__SHIFT', + 'GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN_MASK', + 'GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN__SHIFT', + 'GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES_MASK', + 'GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES__SHIFT', + 'GCEA_MAM_CTRL__ARAM_RB_ADDR_HI_MASK', + 'GCEA_MAM_CTRL__ARAM_RB_ADDR_HI__SHIFT', + 'GCEA_MAM_CTRL__CLEAR_TRACKER_MASK', + 'GCEA_MAM_CTRL__CLEAR_TRACKER__SHIFT', + 'GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE_MASK', + 'GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE__SHIFT', + 'GCEA_MAM_CTRL__FLUSH_TRACKER_MASK', + 'GCEA_MAM_CTRL__FLUSH_TRACKER__SHIFT', + 'GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT_MASK', + 'GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT__SHIFT', + 'GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER_MASK', + 'GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER__SHIFT', + 'GCEA_MAM_CTRL__MAM_DISABLE_MASK', + 'GCEA_MAM_CTRL__MAM_DISABLE__SHIFT', + 'GCEA_MAM_CTRL__RESERVED_FIELD_MASK', + 'GCEA_MAM_CTRL__RESERVED_FIELD__SHIFT', + 'GCEA_MAM_CTRL__SDMA_UPDT_ARAM_MASK', + 'GCEA_MAM_CTRL__SDMA_UPDT_ARAM__SHIFT', + 'GCEA_MAM_CTRL__SDP_PRIORITY_MASK', + 'GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT', + 'GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT_MASK', + 'GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT__SHIFT', + 'GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER_MASK', + 'GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER__SHIFT', + 'GCEA_MISC2__BLOCK_REQUESTS_MASK', + 'GCEA_MISC2__BLOCK_REQUESTS__SHIFT', + 'GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK', + 'GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK', + 'GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT', + 'GCEA_MISC2__FGCLKEN_OVERRIDE_MASK', + 'GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT', + 'GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK', + 'GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT', + 'GCEA_MISC2__LINKMGR_CRBUSY_MASK_MASK', + 'GCEA_MISC2__LINKMGR_CRBUSY_MASK__SHIFT', + 'GCEA_MISC2__REQUESTS_BLOCKED_MASK', + 'GCEA_MISC2__REQUESTS_BLOCKED__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT', + 'GCEA_MISC__EARLY_SDP_ORIGDATA_MASK', + 'GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT', + 'GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK', + 'GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT', + 'GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK', + 'GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT', + 'GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK', + 'GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT', + 'GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK', + 'GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__CLEAR_MASK', + 'GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__ENABLE_MASK', + 'GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__CLEAR_MASK', + 'GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__ENABLE_MASK', + 'GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK', + 'GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK', + 'GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT', + 'GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK', + 'GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT', + 'GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK', + 'GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT', + 'GCEA_PROBE_MAP__INTLV_SIZE_MASK', + 'GCEA_PROBE_MAP__INTLV_SIZE__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC0_MASK', + 'GCEA_RRET_MEM_RESERVE__VC0__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC1_MASK', + 'GCEA_RRET_MEM_RESERVE__VC1__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC2_MASK', + 'GCEA_RRET_MEM_RESERVE__VC2__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC3_MASK', + 'GCEA_RRET_MEM_RESERVE__VC3__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC4_MASK', + 'GCEA_RRET_MEM_RESERVE__VC4__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC5_MASK', + 'GCEA_RRET_MEM_RESERVE__VC5__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC6_MASK', + 'GCEA_RRET_MEM_RESERVE__VC6__SHIFT', + 'GCEA_RRET_MEM_RESERVE__VC7_MASK', + 'GCEA_RRET_MEM_RESERVE__VC7__SHIFT', + 'GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK', + 'GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT', + 'GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK', + 'GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT', + 'GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK', + 'GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT', + 'GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK', + 'GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT', + 'GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK', + 'GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT', + 'GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK', + 'GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT', + 'GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK', + 'GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT', + 'GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK', + 'GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT', + 'GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK', + 'GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT', + 'GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK', + 'GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT', + 'GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK', + 'GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT', + 'GCEA_SDP_CREDITS__TAG_LIMIT_MASK', + 'GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT', + 'GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK', + 'GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT', + 'GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST_MASK', + 'GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST__SHIFT', + 'GCEA_SDP_ENABLE__ENABLE_MASK', 'GCEA_SDP_ENABLE__ENABLE__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC0_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC0__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC1_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC1__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC2_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC2__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC3_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC3__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC4_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC4__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC5_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC5__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC6_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC6__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC7_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC7__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK', + 'GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT', + 'GCMC_MEM_POWER_LS__LS_HOLD_MASK', + 'GCMC_MEM_POWER_LS__LS_HOLD__SHIFT', + 'GCMC_MEM_POWER_LS__LS_SETUP_MASK', + 'GCMC_MEM_POWER_LS__LS_SETUP__SHIFT', + 'GCMC_VM_AGP_BASE__AGP_BASE_MASK', + 'GCMC_VM_AGP_BASE__AGP_BASE__SHIFT', + 'GCMC_VM_AGP_BOT__AGP_BOT_MASK', + 'GCMC_VM_AGP_BOT__AGP_BOT__SHIFT', + 'GCMC_VM_AGP_TOP__AGP_TOP_MASK', + 'GCMC_VM_AGP_TOP__AGP_TOP__SHIFT', + 'GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK', + 'GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT', + 'GCMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK', + 'GCMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT', + 'GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK', + 'GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT', + 'GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK', + 'GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT', + 'GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK', + 'GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT', + 'GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK', + 'GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT', + 'GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK', + 'GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT', + 'GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK', + 'GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT', + 'GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK', + 'GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT', + 'GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK', + 'GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT', + 'GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH_MASK', + 'GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH__SHIFT', + 'GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK', + 'GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT', + 'GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK', + 'GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT', + 'GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK', + 'GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT', + 'GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK', + 'GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT', + 'GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK', + 'GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT', + 'GCMC_VM_FB_OFFSET__FB_OFFSET_MASK', + 'GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT', + 'GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK', + 'GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK', + 'GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK', + 'GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT', + 'GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK', + 'GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT', + 'GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK', + 'GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT', + 'GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK', + 'GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT', + 'GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK', + 'GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT', + 'GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK', + 'GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT', + 'GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10_MASK', + 'GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10__SHIFT', + 'GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11_MASK', + 'GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11__SHIFT', + 'GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12_MASK', + 'GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12__SHIFT', + 'GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13_MASK', + 'GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13__SHIFT', + 'GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14_MASK', + 'GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14__SHIFT', + 'GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15_MASK', + 'GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15__SHIFT', + 'GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK', + 'GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT', + 'GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK', + 'GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT', + 'GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK', + 'GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT', + 'GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4_MASK', + 'GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4__SHIFT', + 'GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5_MASK', + 'GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5__SHIFT', + 'GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6_MASK', + 'GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6__SHIFT', + 'GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7_MASK', + 'GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7__SHIFT', + 'GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8_MASK', + 'GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8__SHIFT', + 'GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9_MASK', + 'GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9__SHIFT', + 'GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK', + 'GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT', + 'GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10_MASK', + 'GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10__SHIFT', + 'GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11_MASK', + 'GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11__SHIFT', + 'GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12_MASK', + 'GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12__SHIFT', + 'GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13_MASK', + 'GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13__SHIFT', + 'GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14_MASK', + 'GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14__SHIFT', + 'GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15_MASK', + 'GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15__SHIFT', + 'GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK', + 'GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT', + 'GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK', + 'GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT', + 'GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK', + 'GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT', + 'GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4_MASK', + 'GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4__SHIFT', + 'GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5_MASK', + 'GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5__SHIFT', + 'GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6_MASK', + 'GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6__SHIFT', + 'GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7_MASK', + 'GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7__SHIFT', + 'GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8_MASK', + 'GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8__SHIFT', + 'GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9_MASK', + 'GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9__SHIFT', + 'GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK', + 'GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT', + 'GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10_MASK', + 'GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10__SHIFT', + 'GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11_MASK', + 'GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11__SHIFT', + 'GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12_MASK', + 'GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12__SHIFT', + 'GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13_MASK', + 'GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13__SHIFT', + 'GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14_MASK', + 'GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14__SHIFT', + 'GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15_MASK', + 'GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15__SHIFT', + 'GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK', + 'GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT', + 'GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK', + 'GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT', + 'GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK', + 'GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT', + 'GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4_MASK', + 'GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4__SHIFT', + 'GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5_MASK', + 'GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5__SHIFT', + 'GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6_MASK', + 'GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6__SHIFT', + 'GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7_MASK', + 'GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7__SHIFT', + 'GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8_MASK', + 'GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8__SHIFT', + 'GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9_MASK', + 'GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9__SHIFT', + 'GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK', + 'GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT', + 'GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10_MASK', + 'GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10__SHIFT', + 'GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11_MASK', + 'GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11__SHIFT', + 'GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12_MASK', + 'GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12__SHIFT', + 'GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13_MASK', + 'GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13__SHIFT', + 'GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14_MASK', + 'GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14__SHIFT', + 'GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15_MASK', + 'GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15__SHIFT', + 'GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK', + 'GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT', + 'GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK', + 'GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT', + 'GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK', + 'GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT', + 'GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4_MASK', + 'GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4__SHIFT', + 'GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5_MASK', + 'GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5__SHIFT', + 'GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6_MASK', + 'GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6__SHIFT', + 'GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7_MASK', + 'GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7__SHIFT', + 'GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8_MASK', + 'GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8__SHIFT', + 'GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9_MASK', + 'GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF__SHIFT', + 'GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS_MASK', + 'GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK', + 'GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10_MASK', + 'GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11_MASK', + 'GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12_MASK', + 'GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13_MASK', + 'GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14_MASK', + 'GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15_MASK', + 'GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK', + 'GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK', + 'GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK', + 'GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4_MASK', + 'GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5_MASK', + 'GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6_MASK', + 'GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7_MASK', + 'GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8_MASK', + 'GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8__SHIFT', + 'GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9_MASK', + 'GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK', + 'GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK', + 'GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK', + 'GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10_MASK', + 'GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10_MASK', + 'GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10_MASK', + 'GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11_MASK', + 'GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11_MASK', + 'GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11_MASK', + 'GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12_MASK', + 'GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12_MASK', + 'GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12_MASK', + 'GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13_MASK', + 'GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13_MASK', + 'GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13_MASK', + 'GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14_MASK', + 'GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14_MASK', + 'GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14_MASK', + 'GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15_MASK', + 'GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15_MASK', + 'GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15_MASK', + 'GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK', + 'GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK', + 'GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK', + 'GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK', + 'GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK', + 'GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK', + 'GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK', + 'GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK', + 'GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK', + 'GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4_MASK', + 'GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4_MASK', + 'GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4_MASK', + 'GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5_MASK', + 'GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5_MASK', + 'GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5_MASK', + 'GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6_MASK', + 'GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6_MASK', + 'GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6_MASK', + 'GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7_MASK', + 'GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7_MASK', + 'GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7_MASK', + 'GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8_MASK', + 'GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8_MASK', + 'GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8_MASK', + 'GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9_MASK', + 'GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9_MASK', + 'GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9__SHIFT', + 'GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9_MASK', + 'GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9__SHIFT', + 'GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK', + 'GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT', + 'GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK', + 'GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT', + 'GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK', + 'GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT', + 'GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK', + 'GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT', + 'GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK', + 'GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT', + 'GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK', + 'GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT', + 'GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK', + 'GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT', + 'GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK', + 'GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT', + 'GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK', + 'GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT', + 'GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK', + 'GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT', + 'GCMC_VM_STEERING__DEFAULT_STEERING_MASK', + 'GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT', + 'GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK', + 'GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT', + 'GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK', + 'GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT', + 'GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK', + 'GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT', + 'GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK', + 'GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT', + 'GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG_MASK', + 'GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG__SHIFT', + 'GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG_MASK', + 'GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG__SHIFT', + 'GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE_MASK', + 'GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE__SHIFT', + 'GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE_MASK', + 'GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE__SHIFT', + 'GCR_CMD_STATUS__GCR_CONTROL_MASK', + 'GCR_CMD_STATUS__GCR_CONTROL__SHIFT', + 'GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK', + 'GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT', + 'GCR_CMD_STATUS__GCR_SRC_MASK', 'GCR_CMD_STATUS__GCR_SRC__SHIFT', + 'GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK', + 'GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK', + 'GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT', + 'GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT', + 'GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK', + 'GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT', + 'GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK', + 'GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT', + 'GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK', + 'GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT', + 'GCR_GENERAL_CNTL__CLIENT_ID_MASK', + 'GCR_GENERAL_CNTL__CLIENT_ID__SHIFT', + 'GCR_GENERAL_CNTL__DISABLE_FGCG_MASK', + 'GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT', + 'GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK', + 'GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT', + 'GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK', + 'GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT', + 'GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK', + 'GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT', + 'GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK', + 'GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT', + 'GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK', + 'GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT', + 'GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK', + 'GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT', + 'GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK', + 'GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT', + 'GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK', + 'GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT', + 'GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK', + 'GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT', + 'GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK', + 'GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT', + 'GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK', + 'GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT', + 'GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK', + 'GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT', + 'GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GCR_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GCR_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GCR_PIO_CNTL__GCR_DATA_INDEX_MASK', + 'GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT', + 'GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK', + 'GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT', + 'GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK', + 'GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT', + 'GCR_PIO_CNTL__GCR_READY_MASK', 'GCR_PIO_CNTL__GCR_READY__SHIFT', + 'GCR_PIO_CNTL__GCR_REG_DONE_MASK', + 'GCR_PIO_CNTL__GCR_REG_DONE__SHIFT', + 'GCR_PIO_CNTL__GCR_REG_RESET_MASK', + 'GCR_PIO_CNTL__GCR_REG_RESET__SHIFT', + 'GCR_PIO_DATA__GCR_DATA_MASK', 'GCR_PIO_DATA__GCR_DATA__SHIFT', + 'GCR_SPARE__GCRD_GL2A_REQ_CREDIT_MASK', + 'GCR_SPARE__GCRD_GL2A_REQ_CREDIT__SHIFT', + 'GCR_SPARE__GCRD_SE_REQ_CREDIT_MASK', + 'GCR_SPARE__GCRD_SE_REQ_CREDIT__SHIFT', + 'GCR_SPARE__SPARE_BIT_1_MASK', 'GCR_SPARE__SPARE_BIT_1__SHIFT', + 'GCR_SPARE__SPARE_BIT_2_MASK', 'GCR_SPARE__SPARE_BIT_2__SHIFT', + 'GCR_SPARE__SPARE_BIT_31_24_MASK', + 'GCR_SPARE__SPARE_BIT_31_24__SHIFT', + 'GCR_SPARE__SPARE_BIT_3_MASK', 'GCR_SPARE__SPARE_BIT_3__SHIFT', + 'GCR_SPARE__SPARE_BIT_4_MASK', 'GCR_SPARE__SPARE_BIT_4__SHIFT', + 'GCR_SPARE__SPARE_BIT_5_MASK', 'GCR_SPARE__SPARE_BIT_5__SHIFT', + 'GCR_SPARE__SPARE_BIT_6_MASK', 'GCR_SPARE__SPARE_BIT_6__SHIFT', + 'GCR_SPARE__SPARE_BIT_7_MASK', 'GCR_SPARE__SPARE_BIT_7__SHIFT', + 'GCR_SPARE__UTCL2_REQ_CREDIT_MASK', + 'GCR_SPARE__UTCL2_REQ_CREDIT__SHIFT', + 'GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK', + 'GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT', + 'GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK', + 'GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK', + 'GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT', + 'GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK', + 'GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT', + 'GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK', + 'GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT', + 'GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK', + 'GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT', + 'GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK', + 'GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT', + 'GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK', + 'GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT', + 'GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK', + 'GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT', + 'GCUTCL2_ICG_CTRL__OFF_HYSTERESIS_MASK', + 'GCUTCL2_ICG_CTRL__OFF_HYSTERESIS__SHIFT', + 'GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK', + 'GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT', + 'GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK', + 'GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT', + 'GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK', + 'GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK', + 'GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK', + 'GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK', + 'GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK', + 'GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT', + 'GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK', + 'GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK', + 'GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT', + 'GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK', + 'GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK', + 'GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT', + 'GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK', + 'GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT', + 'GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK', + 'GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT', + 'GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK', + 'GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT', + 'GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK', + 'GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK', + 'GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK', + 'GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT', + 'GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK', + 'GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT', + 'GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK', + 'GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK', + 'GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK', + 'GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT', + 'GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK', + 'GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT', + 'GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK', + 'GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT', + 'GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK', + 'GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT', + 'GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK', + 'GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT', + 'GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK', + 'GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT', + 'GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK', + 'GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT', + 'GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK', + 'GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT', + 'GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK', + 'GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK', + 'GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK', + 'GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT', + 'GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK', + 'GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT', + 'GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK', + 'GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT', + 'GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK', + 'GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT', + 'GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK', + 'GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT', + 'GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK', + 'GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT', + 'GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK', + 'GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT', + 'GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK', + 'GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT', + 'GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT', + 'GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK', + 'GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT', + 'GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK', + 'GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT', + 'GCVM_L2_BANK_SELECT_MASKS__MASK0_MASK', + 'GCVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT', + 'GCVM_L2_BANK_SELECT_MASKS__MASK1_MASK', + 'GCVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT', + 'GCVM_L2_BANK_SELECT_MASKS__MASK2_MASK', + 'GCVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT', + 'GCVM_L2_BANK_SELECT_MASKS__MASK3_MASK', + 'GCVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK', + 'GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK', + 'GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT', + 'GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK', + 'GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT', + 'GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK', + 'GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT', + 'GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK', + 'GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT', + 'GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK', + 'GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT', + 'GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK', + 'GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT', + 'GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK', + 'GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT', + 'GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK', + 'GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT', + 'GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK', + 'GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT', + 'GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK', + 'GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT', + 'GCVM_L2_CNTL3__BANK_SELECT_MASK', + 'GCVM_L2_CNTL3__BANK_SELECT__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT', + 'GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK', + 'GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT', + 'GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK', + 'GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT', + 'GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK', + 'GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT', + 'GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK', + 'GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT', + 'GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK', + 'GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT', + 'GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK', + 'GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT', + 'GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK', + 'GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT', + 'GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK', + 'GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT', + 'GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK', + 'GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT', + 'GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK', + 'GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT', + 'GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK', + 'GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT', + 'GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK', + 'GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT', + 'GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK', + 'GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT', + 'GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK', + 'GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT', + 'GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK', + 'GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT', + 'GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK', + 'GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT', + 'GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK', + 'GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT', + 'GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK', + 'GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT', + 'GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK', + 'GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT', + 'GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK', + 'GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT', + 'GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK', + 'GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT', + 'GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK', + 'GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT', + 'GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK', + 'GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT', + 'GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK', + 'GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT', + 'GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK', + 'GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT', + 'GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK', + 'GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT', + 'GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK', + 'GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT', + 'GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK', + 'GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT', + 'GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK', + 'GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT', + 'GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK', + 'GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT', + 'GCVM_L2_ICG_CTRL__OFF_HYSTERESIS_MASK', + 'GCVM_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT', + 'GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK', + 'GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT', + 'GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK', + 'GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK', + 'GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT', + 'GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK', + 'GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK', + 'GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK', + 'GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK', + 'GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT', + 'GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK', + 'GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK', + 'GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT', + 'GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK', + 'GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT', + 'GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK', + 'GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT', + 'GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK', + 'GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK', + 'GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK', + 'GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT', + 'GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK', + 'GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT', + 'GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK', + 'GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT', + 'GCVM_L2_STATUS__L2_BUSY_MASK', 'GCVM_L2_STATUS__L2_BUSY__SHIFT', + 'GC_CAC_ACC_CHC0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_CHC0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_CHC1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_CHC1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_CHC2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_CHC2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GDS4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GDS4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE10__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE10__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE11__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE11__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE12__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE12__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE13__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE13__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE14__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE14__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE15__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE15__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE16__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE16__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE17__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE17__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE18__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE18__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE19__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE19__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE20__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE20__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE5__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE5__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE6__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE6__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE7__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE7__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE8__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE8__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GE9__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GE9__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH5__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH5__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH6__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH6__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PH7__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PH7__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_RLC0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_RLC0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK', + 'GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT', + 'GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE_MASK', + 'GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE__SHIFT', + 'GC_CAC_AGGR_LOWER__GC_AGGR_31_0_MASK', + 'GC_CAC_AGGR_LOWER__GC_AGGR_31_0__SHIFT', + 'GC_CAC_AGGR_UPPER__GC_AGGR_63_32_MASK', + 'GC_CAC_AGGR_UPPER__GC_AGGR_63_32__SHIFT', + 'GC_CAC_CNTL__CAC_THRESHOLD_MASK', + 'GC_CAC_CNTL__CAC_THRESHOLD__SHIFT', + 'GC_CAC_CTRL_1__CAC_WINDOW_MASK', + 'GC_CAC_CTRL_1__CAC_WINDOW__SHIFT', + 'GC_CAC_CTRL_1__TDP_WINDOW_MASK', + 'GC_CAC_CTRL_1__TDP_WINDOW__SHIFT', + 'GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL_MASK', + 'GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL__SHIFT', + 'GC_CAC_CTRL_2__CAC_ENABLE_MASK', + 'GC_CAC_CTRL_2__CAC_ENABLE__SHIFT', + 'GC_CAC_CTRL_2__GC_AGGR_ACC_EN_MASK', + 'GC_CAC_CTRL_2__GC_AGGR_ACC_EN__SHIFT', + 'GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK', + 'GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT', + 'GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK', + 'GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT', + 'GC_CAC_CTRL_2__INTR_EN_MASK', 'GC_CAC_CTRL_2__INTR_EN__SHIFT', + 'GC_CAC_CTRL_2__SE_AGGR_ACC_EN_MASK', + 'GC_CAC_CTRL_2__SE_AGGR_ACC_EN__SHIFT', + 'GC_CAC_CTRL_2__TOGGLE_EN_MASK', + 'GC_CAC_CTRL_2__TOGGLE_EN__SHIFT', 'GC_CAC_ID__CAC_BLOCK_ID_MASK', + 'GC_CAC_ID__CAC_BLOCK_ID__SHIFT', 'GC_CAC_ID__CAC_SIGNAL_ID_MASK', + 'GC_CAC_ID__CAC_SIGNAL_ID__SHIFT', + 'GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK', + 'GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT', + 'GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK', + 'GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT', + 'GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK', + 'GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT', + 'GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK', + 'GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT', + 'GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK', + 'GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT', + 'GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK', + 'GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT', + 'GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK', + 'GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT', + 'GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK', + 'GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT', + 'GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK', + 'GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT', + 'GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK', + 'GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT', + 'GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK', + 'GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT', + 'GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK', + 'GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT', + 'GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK', + 'GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT', + 'GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK', + 'GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT', + 'GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK', + 'GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT', + 'GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK', + 'GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT', + 'GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK', + 'GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT', + 'GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK', + 'GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT', + 'GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4_MASK', + 'GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4__SHIFT', + 'GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK', + 'GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT', + 'GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1_MASK', + 'GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1__SHIFT', + 'GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2_MASK', + 'GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2__SHIFT', + 'GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3_MASK', + 'GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3__SHIFT', + 'GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4_MASK', + 'GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4__SHIFT', + 'GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5_MASK', + 'GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5__SHIFT', + 'GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6_MASK', + 'GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6__SHIFT', + 'GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7_MASK', + 'GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7__SHIFT', + 'GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8_MASK', + 'GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8__SHIFT', + 'GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9_MASK', + 'GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9__SHIFT', + 'GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10_MASK', + 'GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10__SHIFT', + 'GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11_MASK', + 'GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11__SHIFT', + 'GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12_MASK', + 'GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12__SHIFT', + 'GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK', + 'GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT', + 'GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK', + 'GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT', + 'GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK', + 'GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT', + 'GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK', + 'GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT', + 'GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK', + 'GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT', + 'GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0_MASK', + 'GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0__SHIFT', + 'GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1_MASK', + 'GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1__SHIFT', + 'GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK', + 'GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT', + 'GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK', + 'GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT', + 'GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK', + 'GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT', + 'GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK', + 'GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT', + 'GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1_MASK', + 'GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1__SHIFT', + 'GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2_MASK', + 'GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2__SHIFT', + 'GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3_MASK', + 'GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3__SHIFT', + 'GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4_MASK', + 'GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4__SHIFT', + 'GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5_MASK', + 'GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5__SHIFT', + 'GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6_MASK', + 'GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6__SHIFT', + 'GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7_MASK', + 'GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7__SHIFT', + 'GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK', + 'GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT', + 'GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK', + 'GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT', + 'GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK', + 'GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT', + 'GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK', + 'GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT', + 'GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK', + 'GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT', + 'GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK', + 'GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT', + 'GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK', + 'GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT', + 'GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK', + 'GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT', + 'GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK', + 'GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT', + 'GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK', + 'GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT', + 'GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK', + 'GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT', + 'GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK', + 'GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT', + 'GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK', + 'GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT', + 'GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK', + 'GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK', + 'GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK', + 'GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK', + 'GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK', + 'GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK', + 'GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK', + 'GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK', + 'GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK', + 'GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK', + 'GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK', + 'GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT', + 'GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK', + 'GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT', + 'GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN_MASK', + 'GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN__SHIFT', + 'GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK', + 'GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT', + 'GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK', + 'GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT', + 'GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK', + 'GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT', + 'GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK', + 'GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT', + 'GC_EDC_CTRL__EDC_AVGDIV_MASK', 'GC_EDC_CTRL__EDC_AVGDIV__SHIFT', + 'GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK', + 'GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT', + 'GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS_MASK', + 'GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS__SHIFT', + 'GC_EDC_CTRL__EDC_EN_MASK', 'GC_EDC_CTRL__EDC_EN__SHIFT', + 'GC_EDC_CTRL__EDC_FORCE_STALL_MASK', + 'GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT', + 'GC_EDC_CTRL__EDC_LEVEL_SEL_MASK', + 'GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT', + 'GC_EDC_CTRL__EDC_SW_RST_MASK', 'GC_EDC_CTRL__EDC_SW_RST__SHIFT', + 'GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK', + 'GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT', + 'GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK', + 'GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT', + 'GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK', + 'GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT', + 'GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK', + 'GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT', + 'GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK', + 'GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT', + 'GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK', + 'GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT', + 'GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK', + 'GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT', + 'GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK', + 'GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT', + 'GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK', + 'GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT', + 'GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK', + 'GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT', + 'GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK', + 'GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT', + 'GC_EDC_STATUS__GPIO_IN_0_MASK', + 'GC_EDC_STATUS__GPIO_IN_0__SHIFT', + 'GC_EDC_STATUS__GPIO_IN_1_MASK', + 'GC_EDC_STATUS__GPIO_IN_1__SHIFT', + 'GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK', + 'GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT', + 'GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK', + 'GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT', + 'GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK', + 'GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT', + 'GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK', + 'GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT', + 'GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK', + 'GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT', + 'GC_IH_COOKIE_0_PTR__ADDR_MASK', + 'GC_IH_COOKIE_0_PTR__ADDR__SHIFT', + 'GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK', + 'GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT', + 'GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK', + 'GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT', + 'GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK', + 'GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT', + 'GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK', + 'GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT', + 'GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK', + 'GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT', + 'GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK', + 'GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT', + 'GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK', + 'GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT', + 'GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK', + 'GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT', + 'GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK', + 'GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT', + 'GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK', + 'GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT', + 'GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK', + 'GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT', + 'GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK', + 'GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT', + 'GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK', + 'GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT', + 'GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK', + 'GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT', + 'GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK', + 'GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT', + 'GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK', + 'GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT', + 'GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK', + 'GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT', + 'GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK', + 'GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT', + 'GC_THROTTLE_CTRL__PATTERN_MODE_MASK', + 'GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT', + 'GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK', + 'GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT', + 'GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK', + 'GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT', + 'GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK', + 'GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT', + 'GC_THROTTLE_CTRL__PCC_STALL_EN_MASK', + 'GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT', + 'GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK', + 'GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT', + 'GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK', + 'GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT', + 'GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK', + 'GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT', + 'GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK', + 'GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT', + 'GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK', + 'GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT', + 'GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK', + 'GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT', + 'GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK', + 'GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT', + 'GC_THROTTLE_STATUS__FSM_STATE_MASK', + 'GC_THROTTLE_STATUS__FSM_STATE__SHIFT', + 'GC_THROTTLE_STATUS__PATTERN_INDEX_MASK', + 'GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT', + 'GC_USER_PRIM_CONFIG__INACTIVE_PA_MASK', + 'GC_USER_PRIM_CONFIG__INACTIVE_PA__SHIFT', + 'GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK', + 'GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT', + 'GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK', + 'GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT', + 'GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK', + 'GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT', + 'GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK', + 'GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT', + 'GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK', + 'GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT', + 'GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK', + 'GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT', + 'GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK', + 'GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT', + 'GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK', + 'GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT', + 'GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK', + 'GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT', + 'GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK', + 'GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT', + 'GDS_ATOM_BASE__BASE_MASK', 'GDS_ATOM_BASE__BASE__SHIFT', + 'GDS_ATOM_BASE__UNUSED_MASK', 'GDS_ATOM_BASE__UNUSED__SHIFT', + 'GDS_ATOM_CNTL__AINC_MASK', 'GDS_ATOM_CNTL__AINC__SHIFT', + 'GDS_ATOM_CNTL__DMODE_MASK', 'GDS_ATOM_CNTL__DMODE__SHIFT', + 'GDS_ATOM_CNTL__UNUSED1_MASK', 'GDS_ATOM_CNTL__UNUSED1__SHIFT', + 'GDS_ATOM_CNTL__UNUSED2_MASK', 'GDS_ATOM_CNTL__UNUSED2__SHIFT', + 'GDS_ATOM_COMPLETE__COMPLETE_MASK', + 'GDS_ATOM_COMPLETE__COMPLETE__SHIFT', + 'GDS_ATOM_COMPLETE__UNUSED_MASK', + 'GDS_ATOM_COMPLETE__UNUSED__SHIFT', 'GDS_ATOM_DST__DST_MASK', + 'GDS_ATOM_DST__DST__SHIFT', 'GDS_ATOM_OFFSET0__OFFSET0_MASK', + 'GDS_ATOM_OFFSET0__OFFSET0__SHIFT', + 'GDS_ATOM_OFFSET0__UNUSED_MASK', + 'GDS_ATOM_OFFSET0__UNUSED__SHIFT', + 'GDS_ATOM_OFFSET1__OFFSET1_MASK', + 'GDS_ATOM_OFFSET1__OFFSET1__SHIFT', + 'GDS_ATOM_OFFSET1__UNUSED_MASK', + 'GDS_ATOM_OFFSET1__UNUSED__SHIFT', 'GDS_ATOM_OP__OP_MASK', + 'GDS_ATOM_OP__OP__SHIFT', 'GDS_ATOM_OP__UNUSED_MASK', + 'GDS_ATOM_OP__UNUSED__SHIFT', 'GDS_ATOM_READ0_U__DATA_MASK', + 'GDS_ATOM_READ0_U__DATA__SHIFT', 'GDS_ATOM_READ0__DATA_MASK', + 'GDS_ATOM_READ0__DATA__SHIFT', 'GDS_ATOM_READ1_U__DATA_MASK', + 'GDS_ATOM_READ1_U__DATA__SHIFT', 'GDS_ATOM_READ1__DATA_MASK', + 'GDS_ATOM_READ1__DATA__SHIFT', 'GDS_ATOM_SIZE__SIZE_MASK', + 'GDS_ATOM_SIZE__SIZE__SHIFT', 'GDS_ATOM_SIZE__UNUSED_MASK', + 'GDS_ATOM_SIZE__UNUSED__SHIFT', 'GDS_ATOM_SRC0_U__DATA_MASK', + 'GDS_ATOM_SRC0_U__DATA__SHIFT', 'GDS_ATOM_SRC0__DATA_MASK', + 'GDS_ATOM_SRC0__DATA__SHIFT', 'GDS_ATOM_SRC1_U__DATA_MASK', + 'GDS_ATOM_SRC1_U__DATA__SHIFT', 'GDS_ATOM_SRC1__DATA_MASK', + 'GDS_ATOM_SRC1__DATA__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY0_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY1_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY2_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY3_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY4_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY5_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY6_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY7_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT', + 'GDS_CNTL_STATUS__DS_BUSY_MASK', + 'GDS_CNTL_STATUS__DS_BUSY__SHIFT', + 'GDS_CNTL_STATUS__DS_RD_CLAMP_MASK', + 'GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT', + 'GDS_CNTL_STATUS__DS_WR_CLAMP_MASK', + 'GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT', + 'GDS_CNTL_STATUS__GDS_BUSY_MASK', + 'GDS_CNTL_STATUS__GDS_BUSY__SHIFT', + 'GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK', + 'GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT', + 'GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK', + 'GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT', + 'GDS_CNTL_STATUS__GWS_BUSY_MASK', + 'GDS_CNTL_STATUS__GWS_BUSY__SHIFT', + 'GDS_CNTL_STATUS__ORD_APP_BUSY_MASK', + 'GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT', + 'GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK', + 'GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT', + 'GDS_CNTL_STATUS__UNUSED_MASK', 'GDS_CNTL_STATUS__UNUSED__SHIFT', + 'GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK', + 'GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT', + 'GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK', + 'GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT', + 'GDS_CONFIG__UNUSED_MASK', 'GDS_CONFIG__UNUSED__SHIFT', + 'GDS_CS_CTXSW_CNT0__PTR_MASK', 'GDS_CS_CTXSW_CNT0__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT0__UPDN_MASK', 'GDS_CS_CTXSW_CNT0__UPDN__SHIFT', + 'GDS_CS_CTXSW_CNT1__PTR_MASK', 'GDS_CS_CTXSW_CNT1__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT1__UPDN_MASK', 'GDS_CS_CTXSW_CNT1__UPDN__SHIFT', + 'GDS_CS_CTXSW_CNT2__PTR_MASK', 'GDS_CS_CTXSW_CNT2__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT2__UPDN_MASK', 'GDS_CS_CTXSW_CNT2__UPDN__SHIFT', + 'GDS_CS_CTXSW_CNT3__PTR_MASK', 'GDS_CS_CTXSW_CNT3__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT3__UPDN_MASK', 'GDS_CS_CTXSW_CNT3__UPDN__SHIFT', + 'GDS_CS_CTXSW_STATUS__R_MASK', 'GDS_CS_CTXSW_STATUS__R__SHIFT', + 'GDS_CS_CTXSW_STATUS__UNUSED_MASK', + 'GDS_CS_CTXSW_STATUS__UNUSED__SHIFT', + 'GDS_CS_CTXSW_STATUS__W_MASK', 'GDS_CS_CTXSW_STATUS__W__SHIFT', + 'GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__UNUSED_MASK', 'GDS_DSM_CNTL2__UNUSED__SHIFT', + 'GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__UNUSED_MASK', 'GDS_DSM_CNTL__UNUSED__SHIFT', + 'GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK', + 'GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT', + 'GDS_EDC_CNT__GDS_MEM_DED_MASK', + 'GDS_EDC_CNT__GDS_MEM_DED__SHIFT', + 'GDS_EDC_CNT__GDS_MEM_SEC_MASK', + 'GDS_EDC_CNT__GDS_MEM_SEC__SHIFT', 'GDS_EDC_CNT__UNUSED_MASK', + 'GDS_EDC_CNT__UNUSED__SHIFT', 'GDS_EDC_GRBM_CNT__DED_MASK', + 'GDS_EDC_GRBM_CNT__DED__SHIFT', 'GDS_EDC_GRBM_CNT__SEC_MASK', + 'GDS_EDC_GRBM_CNT__SEC__SHIFT', 'GDS_EDC_GRBM_CNT__UNUSED_MASK', + 'GDS_EDC_GRBM_CNT__UNUSED__SHIFT', + 'GDS_EDC_OA_DED__ME0_CS_DED_MASK', + 'GDS_EDC_OA_DED__ME0_CS_DED__SHIFT', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT', + 'GDS_EDC_OA_DED__ME0_PIPE1_CS_DED_MASK', + 'GDS_EDC_OA_DED__ME0_PIPE1_CS_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT', + 'GDS_EDC_OA_DED__UNUSED1_MASK', 'GDS_EDC_OA_DED__UNUSED1__SHIFT', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK', + 'GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT', + 'GDS_EDC_OA_PHY_CNT__UNUSED1_MASK', + 'GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__UNUSED_MASK', + 'GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT', + 'GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT_MASK', + 'GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT__SHIFT', + 'GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT_MASK', + 'GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT__SHIFT', + 'GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE_MASK', + 'GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE__SHIFT', + 'GDS_ENHANCE2__UNUSED_MASK', 'GDS_ENHANCE2__UNUSED__SHIFT', + 'GDS_ENHANCE__AUTO_INC_INDEX_MASK', + 'GDS_ENHANCE__AUTO_INC_INDEX__SHIFT', + 'GDS_ENHANCE__CGPG_RESTORE_MASK', + 'GDS_ENHANCE__CGPG_RESTORE__SHIFT', 'GDS_ENHANCE__MISC_MASK', + 'GDS_ENHANCE__MISC__SHIFT', 'GDS_ENHANCE__UNUSED_MASK', + 'GDS_ENHANCE__UNUSED__SHIFT', 'GDS_GFX_CTXSW_STATUS__R_MASK', + 'GDS_GFX_CTXSW_STATUS__R__SHIFT', + 'GDS_GFX_CTXSW_STATUS__UNUSED_MASK', + 'GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT', + 'GDS_GFX_CTXSW_STATUS__W_MASK', 'GDS_GFX_CTXSW_STATUS__W__SHIFT', + 'GDS_GS_0__DATA_MASK', 'GDS_GS_0__DATA__SHIFT', + 'GDS_GS_1__DATA_MASK', 'GDS_GS_1__DATA__SHIFT', + 'GDS_GS_2__DATA_MASK', 'GDS_GS_2__DATA__SHIFT', + 'GDS_GS_3__DATA_MASK', 'GDS_GS_3__DATA__SHIFT', + 'GDS_GS_CTXSW_CNT0__PTR_MASK', 'GDS_GS_CTXSW_CNT0__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT0__UPDN_MASK', 'GDS_GS_CTXSW_CNT0__UPDN__SHIFT', + 'GDS_GS_CTXSW_CNT1__PTR_MASK', 'GDS_GS_CTXSW_CNT1__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT1__UPDN_MASK', 'GDS_GS_CTXSW_CNT1__UPDN__SHIFT', + 'GDS_GS_CTXSW_CNT2__PTR_MASK', 'GDS_GS_CTXSW_CNT2__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT2__UPDN_MASK', 'GDS_GS_CTXSW_CNT2__UPDN__SHIFT', + 'GDS_GS_CTXSW_CNT3__PTR_MASK', 'GDS_GS_CTXSW_CNT3__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT3__UPDN_MASK', 'GDS_GS_CTXSW_CNT3__UPDN__SHIFT', + 'GDS_GWS_RESET0__RESOURCE0_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE10_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE11_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE12_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE13_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE14_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE15_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE16_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE17_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE18_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE19_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE1_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE20_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE21_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE22_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE23_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE24_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE25_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE26_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE27_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE28_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE29_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE2_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE30_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE31_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE3_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE4_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE5_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE6_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE7_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE8_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE9_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE32_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE33_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE34_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE35_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE36_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE37_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE38_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE39_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE40_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE41_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE42_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE43_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE44_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE45_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE46_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE47_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE48_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE49_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE50_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE51_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE52_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE53_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE54_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE55_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE56_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE57_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE58_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE59_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE60_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE61_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE62_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE63_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT', + 'GDS_GWS_RESOURCE_CNTL__INDEX_MASK', + 'GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT', + 'GDS_GWS_RESOURCE_CNTL__UNUSED_MASK', + 'GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT', + 'GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK', + 'GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT', + 'GDS_GWS_RESOURCE_CNT__UNUSED_MASK', + 'GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT', + 'GDS_GWS_RESOURCE_RESET__RESET_MASK', + 'GDS_GWS_RESOURCE_RESET__RESET__SHIFT', + 'GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK', + 'GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT', + 'GDS_GWS_RESOURCE_RESET__UNUSED_MASK', + 'GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT', + 'GDS_GWS_RESOURCE__COUNTER_MASK', + 'GDS_GWS_RESOURCE__COUNTER__SHIFT', 'GDS_GWS_RESOURCE__DED_MASK', + 'GDS_GWS_RESOURCE__DED__SHIFT', 'GDS_GWS_RESOURCE__FLAG_MASK', + 'GDS_GWS_RESOURCE__FLAG__SHIFT', 'GDS_GWS_RESOURCE__HALTED_MASK', + 'GDS_GWS_RESOURCE__HALTED__SHIFT', + 'GDS_GWS_RESOURCE__HEAD_FLAG_MASK', + 'GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT', + 'GDS_GWS_RESOURCE__HEAD_QUEUE_MASK', + 'GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT', + 'GDS_GWS_RESOURCE__HEAD_VALID_MASK', + 'GDS_GWS_RESOURCE__HEAD_VALID__SHIFT', + 'GDS_GWS_RESOURCE__RELEASE_ALL_MASK', + 'GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT', + 'GDS_GWS_RESOURCE__TYPE_MASK', 'GDS_GWS_RESOURCE__TYPE__SHIFT', + 'GDS_GWS_VMID0__BASE_MASK', 'GDS_GWS_VMID0__BASE__SHIFT', + 'GDS_GWS_VMID0__SIZE_MASK', 'GDS_GWS_VMID0__SIZE__SHIFT', + 'GDS_GWS_VMID0__UNUSED1_MASK', 'GDS_GWS_VMID0__UNUSED1__SHIFT', + 'GDS_GWS_VMID0__UNUSED2_MASK', 'GDS_GWS_VMID0__UNUSED2__SHIFT', + 'GDS_GWS_VMID10__BASE_MASK', 'GDS_GWS_VMID10__BASE__SHIFT', + 'GDS_GWS_VMID10__SIZE_MASK', 'GDS_GWS_VMID10__SIZE__SHIFT', + 'GDS_GWS_VMID10__UNUSED1_MASK', 'GDS_GWS_VMID10__UNUSED1__SHIFT', + 'GDS_GWS_VMID10__UNUSED2_MASK', 'GDS_GWS_VMID10__UNUSED2__SHIFT', + 'GDS_GWS_VMID11__BASE_MASK', 'GDS_GWS_VMID11__BASE__SHIFT', + 'GDS_GWS_VMID11__SIZE_MASK', 'GDS_GWS_VMID11__SIZE__SHIFT', + 'GDS_GWS_VMID11__UNUSED1_MASK', 'GDS_GWS_VMID11__UNUSED1__SHIFT', + 'GDS_GWS_VMID11__UNUSED2_MASK', 'GDS_GWS_VMID11__UNUSED2__SHIFT', + 'GDS_GWS_VMID12__BASE_MASK', 'GDS_GWS_VMID12__BASE__SHIFT', + 'GDS_GWS_VMID12__SIZE_MASK', 'GDS_GWS_VMID12__SIZE__SHIFT', + 'GDS_GWS_VMID12__UNUSED1_MASK', 'GDS_GWS_VMID12__UNUSED1__SHIFT', + 'GDS_GWS_VMID12__UNUSED2_MASK', 'GDS_GWS_VMID12__UNUSED2__SHIFT', + 'GDS_GWS_VMID13__BASE_MASK', 'GDS_GWS_VMID13__BASE__SHIFT', + 'GDS_GWS_VMID13__SIZE_MASK', 'GDS_GWS_VMID13__SIZE__SHIFT', + 'GDS_GWS_VMID13__UNUSED1_MASK', 'GDS_GWS_VMID13__UNUSED1__SHIFT', + 'GDS_GWS_VMID13__UNUSED2_MASK', 'GDS_GWS_VMID13__UNUSED2__SHIFT', + 'GDS_GWS_VMID14__BASE_MASK', 'GDS_GWS_VMID14__BASE__SHIFT', + 'GDS_GWS_VMID14__SIZE_MASK', 'GDS_GWS_VMID14__SIZE__SHIFT', + 'GDS_GWS_VMID14__UNUSED1_MASK', 'GDS_GWS_VMID14__UNUSED1__SHIFT', + 'GDS_GWS_VMID14__UNUSED2_MASK', 'GDS_GWS_VMID14__UNUSED2__SHIFT', + 'GDS_GWS_VMID15__BASE_MASK', 'GDS_GWS_VMID15__BASE__SHIFT', + 'GDS_GWS_VMID15__SIZE_MASK', 'GDS_GWS_VMID15__SIZE__SHIFT', + 'GDS_GWS_VMID15__UNUSED1_MASK', 'GDS_GWS_VMID15__UNUSED1__SHIFT', + 'GDS_GWS_VMID15__UNUSED2_MASK', 'GDS_GWS_VMID15__UNUSED2__SHIFT', + 'GDS_GWS_VMID1__BASE_MASK', 'GDS_GWS_VMID1__BASE__SHIFT', + 'GDS_GWS_VMID1__SIZE_MASK', 'GDS_GWS_VMID1__SIZE__SHIFT', + 'GDS_GWS_VMID1__UNUSED1_MASK', 'GDS_GWS_VMID1__UNUSED1__SHIFT', + 'GDS_GWS_VMID1__UNUSED2_MASK', 'GDS_GWS_VMID1__UNUSED2__SHIFT', + 'GDS_GWS_VMID2__BASE_MASK', 'GDS_GWS_VMID2__BASE__SHIFT', + 'GDS_GWS_VMID2__SIZE_MASK', 'GDS_GWS_VMID2__SIZE__SHIFT', + 'GDS_GWS_VMID2__UNUSED1_MASK', 'GDS_GWS_VMID2__UNUSED1__SHIFT', + 'GDS_GWS_VMID2__UNUSED2_MASK', 'GDS_GWS_VMID2__UNUSED2__SHIFT', + 'GDS_GWS_VMID3__BASE_MASK', 'GDS_GWS_VMID3__BASE__SHIFT', + 'GDS_GWS_VMID3__SIZE_MASK', 'GDS_GWS_VMID3__SIZE__SHIFT', + 'GDS_GWS_VMID3__UNUSED1_MASK', 'GDS_GWS_VMID3__UNUSED1__SHIFT', + 'GDS_GWS_VMID3__UNUSED2_MASK', 'GDS_GWS_VMID3__UNUSED2__SHIFT', + 'GDS_GWS_VMID4__BASE_MASK', 'GDS_GWS_VMID4__BASE__SHIFT', + 'GDS_GWS_VMID4__SIZE_MASK', 'GDS_GWS_VMID4__SIZE__SHIFT', + 'GDS_GWS_VMID4__UNUSED1_MASK', 'GDS_GWS_VMID4__UNUSED1__SHIFT', + 'GDS_GWS_VMID4__UNUSED2_MASK', 'GDS_GWS_VMID4__UNUSED2__SHIFT', + 'GDS_GWS_VMID5__BASE_MASK', 'GDS_GWS_VMID5__BASE__SHIFT', + 'GDS_GWS_VMID5__SIZE_MASK', 'GDS_GWS_VMID5__SIZE__SHIFT', + 'GDS_GWS_VMID5__UNUSED1_MASK', 'GDS_GWS_VMID5__UNUSED1__SHIFT', + 'GDS_GWS_VMID5__UNUSED2_MASK', 'GDS_GWS_VMID5__UNUSED2__SHIFT', + 'GDS_GWS_VMID6__BASE_MASK', 'GDS_GWS_VMID6__BASE__SHIFT', + 'GDS_GWS_VMID6__SIZE_MASK', 'GDS_GWS_VMID6__SIZE__SHIFT', + 'GDS_GWS_VMID6__UNUSED1_MASK', 'GDS_GWS_VMID6__UNUSED1__SHIFT', + 'GDS_GWS_VMID6__UNUSED2_MASK', 'GDS_GWS_VMID6__UNUSED2__SHIFT', + 'GDS_GWS_VMID7__BASE_MASK', 'GDS_GWS_VMID7__BASE__SHIFT', + 'GDS_GWS_VMID7__SIZE_MASK', 'GDS_GWS_VMID7__SIZE__SHIFT', + 'GDS_GWS_VMID7__UNUSED1_MASK', 'GDS_GWS_VMID7__UNUSED1__SHIFT', + 'GDS_GWS_VMID7__UNUSED2_MASK', 'GDS_GWS_VMID7__UNUSED2__SHIFT', + 'GDS_GWS_VMID8__BASE_MASK', 'GDS_GWS_VMID8__BASE__SHIFT', + 'GDS_GWS_VMID8__SIZE_MASK', 'GDS_GWS_VMID8__SIZE__SHIFT', + 'GDS_GWS_VMID8__UNUSED1_MASK', 'GDS_GWS_VMID8__UNUSED1__SHIFT', + 'GDS_GWS_VMID8__UNUSED2_MASK', 'GDS_GWS_VMID8__UNUSED2__SHIFT', + 'GDS_GWS_VMID9__BASE_MASK', 'GDS_GWS_VMID9__BASE__SHIFT', + 'GDS_GWS_VMID9__SIZE_MASK', 'GDS_GWS_VMID9__SIZE__SHIFT', + 'GDS_GWS_VMID9__UNUSED1_MASK', 'GDS_GWS_VMID9__UNUSED1__SHIFT', + 'GDS_GWS_VMID9__UNUSED2_MASK', 'GDS_GWS_VMID9__UNUSED2__SHIFT', + 'GDS_MEMORY_CLEAN__FINISH_MASK', + 'GDS_MEMORY_CLEAN__FINISH__SHIFT', 'GDS_MEMORY_CLEAN__START_MASK', + 'GDS_MEMORY_CLEAN__START__SHIFT', 'GDS_MEMORY_CLEAN__UNUSED_MASK', + 'GDS_MEMORY_CLEAN__UNUSED__SHIFT', 'GDS_OA_ADDRESS__CRAWLER_MASK', + 'GDS_OA_ADDRESS__CRAWLER_TYPE_MASK', + 'GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT', + 'GDS_OA_ADDRESS__CRAWLER__SHIFT', + 'GDS_OA_ADDRESS__DS_ADDRESS_MASK', + 'GDS_OA_ADDRESS__DS_ADDRESS__SHIFT', + 'GDS_OA_ADDRESS__ENABLE_MASK', 'GDS_OA_ADDRESS__ENABLE__SHIFT', + 'GDS_OA_ADDRESS__NO_ALLOC_MASK', + 'GDS_OA_ADDRESS__NO_ALLOC__SHIFT', 'GDS_OA_ADDRESS__UNUSED_MASK', + 'GDS_OA_ADDRESS__UNUSED__SHIFT', 'GDS_OA_CGPG_RESTORE__MEID_MASK', + 'GDS_OA_CGPG_RESTORE__MEID__SHIFT', + 'GDS_OA_CGPG_RESTORE__PIPEID_MASK', + 'GDS_OA_CGPG_RESTORE__PIPEID__SHIFT', + 'GDS_OA_CGPG_RESTORE__QUEUEID_MASK', + 'GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT', + 'GDS_OA_CGPG_RESTORE__UNUSED_MASK', + 'GDS_OA_CGPG_RESTORE__UNUSED__SHIFT', + 'GDS_OA_CGPG_RESTORE__VMID_MASK', + 'GDS_OA_CGPG_RESTORE__VMID__SHIFT', 'GDS_OA_CNTL__INDEX_MASK', + 'GDS_OA_CNTL__INDEX__SHIFT', 'GDS_OA_CNTL__UNUSED_MASK', + 'GDS_OA_CNTL__UNUSED__SHIFT', + 'GDS_OA_COUNTER__SPACE_AVAILABLE_MASK', + 'GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT', + 'GDS_OA_INCDEC__INCDEC_MASK', 'GDS_OA_INCDEC__INCDEC__SHIFT', + 'GDS_OA_INCDEC__VALUE_MASK', 'GDS_OA_INCDEC__VALUE__SHIFT', + 'GDS_OA_RESET_MASK__ME0_CS_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT', + 'GDS_OA_RESET_MASK__UNUSED1_MASK', + 'GDS_OA_RESET_MASK__UNUSED1__SHIFT', 'GDS_OA_RESET__PIPE_ID_MASK', + 'GDS_OA_RESET__PIPE_ID__SHIFT', 'GDS_OA_RESET__RESET_MASK', + 'GDS_OA_RESET__RESET__SHIFT', 'GDS_OA_RESET__UNUSED_MASK', + 'GDS_OA_RESET__UNUSED__SHIFT', 'GDS_OA_RING_SIZE__RING_SIZE_MASK', + 'GDS_OA_RING_SIZE__RING_SIZE__SHIFT', 'GDS_OA_VMID0__MASK_MASK', + 'GDS_OA_VMID0__MASK__SHIFT', 'GDS_OA_VMID0__UNUSED_MASK', + 'GDS_OA_VMID0__UNUSED__SHIFT', 'GDS_OA_VMID10__MASK_MASK', + 'GDS_OA_VMID10__MASK__SHIFT', 'GDS_OA_VMID10__UNUSED_MASK', + 'GDS_OA_VMID10__UNUSED__SHIFT', 'GDS_OA_VMID11__MASK_MASK', + 'GDS_OA_VMID11__MASK__SHIFT', 'GDS_OA_VMID11__UNUSED_MASK', + 'GDS_OA_VMID11__UNUSED__SHIFT', 'GDS_OA_VMID12__MASK_MASK', + 'GDS_OA_VMID12__MASK__SHIFT', 'GDS_OA_VMID12__UNUSED_MASK', + 'GDS_OA_VMID12__UNUSED__SHIFT', 'GDS_OA_VMID13__MASK_MASK', + 'GDS_OA_VMID13__MASK__SHIFT', 'GDS_OA_VMID13__UNUSED_MASK', + 'GDS_OA_VMID13__UNUSED__SHIFT', 'GDS_OA_VMID14__MASK_MASK', + 'GDS_OA_VMID14__MASK__SHIFT', 'GDS_OA_VMID14__UNUSED_MASK', + 'GDS_OA_VMID14__UNUSED__SHIFT', 'GDS_OA_VMID15__MASK_MASK', + 'GDS_OA_VMID15__MASK__SHIFT', 'GDS_OA_VMID15__UNUSED_MASK', + 'GDS_OA_VMID15__UNUSED__SHIFT', 'GDS_OA_VMID1__MASK_MASK', + 'GDS_OA_VMID1__MASK__SHIFT', 'GDS_OA_VMID1__UNUSED_MASK', + 'GDS_OA_VMID1__UNUSED__SHIFT', 'GDS_OA_VMID2__MASK_MASK', + 'GDS_OA_VMID2__MASK__SHIFT', 'GDS_OA_VMID2__UNUSED_MASK', + 'GDS_OA_VMID2__UNUSED__SHIFT', 'GDS_OA_VMID3__MASK_MASK', + 'GDS_OA_VMID3__MASK__SHIFT', 'GDS_OA_VMID3__UNUSED_MASK', + 'GDS_OA_VMID3__UNUSED__SHIFT', 'GDS_OA_VMID4__MASK_MASK', + 'GDS_OA_VMID4__MASK__SHIFT', 'GDS_OA_VMID4__UNUSED_MASK', + 'GDS_OA_VMID4__UNUSED__SHIFT', 'GDS_OA_VMID5__MASK_MASK', + 'GDS_OA_VMID5__MASK__SHIFT', 'GDS_OA_VMID5__UNUSED_MASK', + 'GDS_OA_VMID5__UNUSED__SHIFT', 'GDS_OA_VMID6__MASK_MASK', + 'GDS_OA_VMID6__MASK__SHIFT', 'GDS_OA_VMID6__UNUSED_MASK', + 'GDS_OA_VMID6__UNUSED__SHIFT', 'GDS_OA_VMID7__MASK_MASK', + 'GDS_OA_VMID7__MASK__SHIFT', 'GDS_OA_VMID7__UNUSED_MASK', + 'GDS_OA_VMID7__UNUSED__SHIFT', 'GDS_OA_VMID8__MASK_MASK', + 'GDS_OA_VMID8__MASK__SHIFT', 'GDS_OA_VMID8__UNUSED_MASK', + 'GDS_OA_VMID8__UNUSED__SHIFT', 'GDS_OA_VMID9__MASK_MASK', + 'GDS_OA_VMID9__MASK__SHIFT', 'GDS_OA_VMID9__UNUSED_MASK', + 'GDS_OA_VMID9__UNUSED__SHIFT', + 'GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'GDS_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'GDS_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'GDS_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'GDS_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'GDS_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'GDS_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'GDS_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'GDS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'GDS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'GDS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'GDS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'GDS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'GDS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'GDS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'GDS_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'GDS_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'GDS_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'GDS_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'GDS_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'GDS_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'GDS_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'GDS_PROTECTION_FAULT__ADDRESS_MASK', + 'GDS_PROTECTION_FAULT__ADDRESS__SHIFT', + 'GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK', + 'GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT', + 'GDS_PROTECTION_FAULT__GRBM_MASK', + 'GDS_PROTECTION_FAULT__GRBM__SHIFT', + 'GDS_PROTECTION_FAULT__SA_ID_MASK', + 'GDS_PROTECTION_FAULT__SA_ID__SHIFT', + 'GDS_PROTECTION_FAULT__SE_ID_MASK', + 'GDS_PROTECTION_FAULT__SE_ID__SHIFT', + 'GDS_PROTECTION_FAULT__SIMD_ID_MASK', + 'GDS_PROTECTION_FAULT__SIMD_ID__SHIFT', + 'GDS_PROTECTION_FAULT__WAVE_ID_MASK', + 'GDS_PROTECTION_FAULT__WAVE_ID__SHIFT', + 'GDS_PROTECTION_FAULT__WGP_ID_MASK', + 'GDS_PROTECTION_FAULT__WGP_ID__SHIFT', + 'GDS_PROTECTION_FAULT__WRITE_DIS_MASK', + 'GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT', + 'GDS_PS_CTXSW_CNT0__PTR_MASK', 'GDS_PS_CTXSW_CNT0__PTR__SHIFT', + 'GDS_PS_CTXSW_CNT0__UPDN_MASK', 'GDS_PS_CTXSW_CNT0__UPDN__SHIFT', + 'GDS_PS_CTXSW_CNT1__PTR_MASK', 'GDS_PS_CTXSW_CNT1__PTR__SHIFT', + 'GDS_PS_CTXSW_CNT1__UPDN_MASK', 'GDS_PS_CTXSW_CNT1__UPDN__SHIFT', + 'GDS_PS_CTXSW_CNT2__PTR_MASK', 'GDS_PS_CTXSW_CNT2__PTR__SHIFT', + 'GDS_PS_CTXSW_CNT2__UPDN_MASK', 'GDS_PS_CTXSW_CNT2__UPDN__SHIFT', + 'GDS_PS_CTXSW_CNT3__PTR_MASK', 'GDS_PS_CTXSW_CNT3__PTR__SHIFT', + 'GDS_PS_CTXSW_CNT3__UPDN_MASK', 'GDS_PS_CTXSW_CNT3__UPDN__SHIFT', + 'GDS_PS_CTXSW_IDX__PACKER_ID_MASK', + 'GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT', + 'GDS_PS_CTXSW_IDX__UNUSED_MASK', + 'GDS_PS_CTXSW_IDX__UNUSED__SHIFT', 'GDS_RD_ADDR__READ_ADDR_MASK', + 'GDS_RD_ADDR__READ_ADDR__SHIFT', + 'GDS_RD_BURST_ADDR__BURST_ADDR_MASK', + 'GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT', + 'GDS_RD_BURST_COUNT__BURST_COUNT_MASK', + 'GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT', + 'GDS_RD_BURST_DATA__BURST_DATA_MASK', + 'GDS_RD_BURST_DATA__BURST_DATA__SHIFT', + 'GDS_RD_DATA__READ_DATA_MASK', 'GDS_RD_DATA__READ_DATA__SHIFT', + 'GDS_STRMOUT_DWORDS_WRITTEN_0__DATA_MASK', + 'GDS_STRMOUT_DWORDS_WRITTEN_0__DATA__SHIFT', + 'GDS_STRMOUT_DWORDS_WRITTEN_1__DATA_MASK', + 'GDS_STRMOUT_DWORDS_WRITTEN_1__DATA__SHIFT', + 'GDS_STRMOUT_DWORDS_WRITTEN_2__DATA_MASK', + 'GDS_STRMOUT_DWORDS_WRITTEN_2__DATA__SHIFT', + 'GDS_STRMOUT_DWORDS_WRITTEN_3__DATA_MASK', + 'GDS_STRMOUT_DWORDS_WRITTEN_3__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA__SHIFT', + 'GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA_MASK', + 'GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA__SHIFT', + 'GDS_VMID0_BASE__BASE_MASK', 'GDS_VMID0_BASE__BASE__SHIFT', + 'GDS_VMID0_BASE__UNUSED_MASK', 'GDS_VMID0_BASE__UNUSED__SHIFT', + 'GDS_VMID0_SIZE__SIZE_MASK', 'GDS_VMID0_SIZE__SIZE__SHIFT', + 'GDS_VMID0_SIZE__UNUSED_MASK', 'GDS_VMID0_SIZE__UNUSED__SHIFT', + 'GDS_VMID10_BASE__BASE_MASK', 'GDS_VMID10_BASE__BASE__SHIFT', + 'GDS_VMID10_BASE__UNUSED_MASK', 'GDS_VMID10_BASE__UNUSED__SHIFT', + 'GDS_VMID10_SIZE__SIZE_MASK', 'GDS_VMID10_SIZE__SIZE__SHIFT', + 'GDS_VMID10_SIZE__UNUSED_MASK', 'GDS_VMID10_SIZE__UNUSED__SHIFT', + 'GDS_VMID11_BASE__BASE_MASK', 'GDS_VMID11_BASE__BASE__SHIFT', + 'GDS_VMID11_BASE__UNUSED_MASK', 'GDS_VMID11_BASE__UNUSED__SHIFT', + 'GDS_VMID11_SIZE__SIZE_MASK', 'GDS_VMID11_SIZE__SIZE__SHIFT', + 'GDS_VMID11_SIZE__UNUSED_MASK', 'GDS_VMID11_SIZE__UNUSED__SHIFT', + 'GDS_VMID12_BASE__BASE_MASK', 'GDS_VMID12_BASE__BASE__SHIFT', + 'GDS_VMID12_BASE__UNUSED_MASK', 'GDS_VMID12_BASE__UNUSED__SHIFT', + 'GDS_VMID12_SIZE__SIZE_MASK', 'GDS_VMID12_SIZE__SIZE__SHIFT', + 'GDS_VMID12_SIZE__UNUSED_MASK', 'GDS_VMID12_SIZE__UNUSED__SHIFT', + 'GDS_VMID13_BASE__BASE_MASK', 'GDS_VMID13_BASE__BASE__SHIFT', + 'GDS_VMID13_BASE__UNUSED_MASK', 'GDS_VMID13_BASE__UNUSED__SHIFT', + 'GDS_VMID13_SIZE__SIZE_MASK', 'GDS_VMID13_SIZE__SIZE__SHIFT', + 'GDS_VMID13_SIZE__UNUSED_MASK', 'GDS_VMID13_SIZE__UNUSED__SHIFT', + 'GDS_VMID14_BASE__BASE_MASK', 'GDS_VMID14_BASE__BASE__SHIFT', + 'GDS_VMID14_BASE__UNUSED_MASK', 'GDS_VMID14_BASE__UNUSED__SHIFT', + 'GDS_VMID14_SIZE__SIZE_MASK', 'GDS_VMID14_SIZE__SIZE__SHIFT', + 'GDS_VMID14_SIZE__UNUSED_MASK', 'GDS_VMID14_SIZE__UNUSED__SHIFT', + 'GDS_VMID15_BASE__BASE_MASK', 'GDS_VMID15_BASE__BASE__SHIFT', + 'GDS_VMID15_BASE__UNUSED_MASK', 'GDS_VMID15_BASE__UNUSED__SHIFT', + 'GDS_VMID15_SIZE__SIZE_MASK', 'GDS_VMID15_SIZE__SIZE__SHIFT', + 'GDS_VMID15_SIZE__UNUSED_MASK', 'GDS_VMID15_SIZE__UNUSED__SHIFT', + 'GDS_VMID1_BASE__BASE_MASK', 'GDS_VMID1_BASE__BASE__SHIFT', + 'GDS_VMID1_BASE__UNUSED_MASK', 'GDS_VMID1_BASE__UNUSED__SHIFT', + 'GDS_VMID1_SIZE__SIZE_MASK', 'GDS_VMID1_SIZE__SIZE__SHIFT', + 'GDS_VMID1_SIZE__UNUSED_MASK', 'GDS_VMID1_SIZE__UNUSED__SHIFT', + 'GDS_VMID2_BASE__BASE_MASK', 'GDS_VMID2_BASE__BASE__SHIFT', + 'GDS_VMID2_BASE__UNUSED_MASK', 'GDS_VMID2_BASE__UNUSED__SHIFT', + 'GDS_VMID2_SIZE__SIZE_MASK', 'GDS_VMID2_SIZE__SIZE__SHIFT', + 'GDS_VMID2_SIZE__UNUSED_MASK', 'GDS_VMID2_SIZE__UNUSED__SHIFT', + 'GDS_VMID3_BASE__BASE_MASK', 'GDS_VMID3_BASE__BASE__SHIFT', + 'GDS_VMID3_BASE__UNUSED_MASK', 'GDS_VMID3_BASE__UNUSED__SHIFT', + 'GDS_VMID3_SIZE__SIZE_MASK', 'GDS_VMID3_SIZE__SIZE__SHIFT', + 'GDS_VMID3_SIZE__UNUSED_MASK', 'GDS_VMID3_SIZE__UNUSED__SHIFT', + 'GDS_VMID4_BASE__BASE_MASK', 'GDS_VMID4_BASE__BASE__SHIFT', + 'GDS_VMID4_BASE__UNUSED_MASK', 'GDS_VMID4_BASE__UNUSED__SHIFT', + 'GDS_VMID4_SIZE__SIZE_MASK', 'GDS_VMID4_SIZE__SIZE__SHIFT', + 'GDS_VMID4_SIZE__UNUSED_MASK', 'GDS_VMID4_SIZE__UNUSED__SHIFT', + 'GDS_VMID5_BASE__BASE_MASK', 'GDS_VMID5_BASE__BASE__SHIFT', + 'GDS_VMID5_BASE__UNUSED_MASK', 'GDS_VMID5_BASE__UNUSED__SHIFT', + 'GDS_VMID5_SIZE__SIZE_MASK', 'GDS_VMID5_SIZE__SIZE__SHIFT', + 'GDS_VMID5_SIZE__UNUSED_MASK', 'GDS_VMID5_SIZE__UNUSED__SHIFT', + 'GDS_VMID6_BASE__BASE_MASK', 'GDS_VMID6_BASE__BASE__SHIFT', + 'GDS_VMID6_BASE__UNUSED_MASK', 'GDS_VMID6_BASE__UNUSED__SHIFT', + 'GDS_VMID6_SIZE__SIZE_MASK', 'GDS_VMID6_SIZE__SIZE__SHIFT', + 'GDS_VMID6_SIZE__UNUSED_MASK', 'GDS_VMID6_SIZE__UNUSED__SHIFT', + 'GDS_VMID7_BASE__BASE_MASK', 'GDS_VMID7_BASE__BASE__SHIFT', + 'GDS_VMID7_BASE__UNUSED_MASK', 'GDS_VMID7_BASE__UNUSED__SHIFT', + 'GDS_VMID7_SIZE__SIZE_MASK', 'GDS_VMID7_SIZE__SIZE__SHIFT', + 'GDS_VMID7_SIZE__UNUSED_MASK', 'GDS_VMID7_SIZE__UNUSED__SHIFT', + 'GDS_VMID8_BASE__BASE_MASK', 'GDS_VMID8_BASE__BASE__SHIFT', + 'GDS_VMID8_BASE__UNUSED_MASK', 'GDS_VMID8_BASE__UNUSED__SHIFT', + 'GDS_VMID8_SIZE__SIZE_MASK', 'GDS_VMID8_SIZE__SIZE__SHIFT', + 'GDS_VMID8_SIZE__UNUSED_MASK', 'GDS_VMID8_SIZE__UNUSED__SHIFT', + 'GDS_VMID9_BASE__BASE_MASK', 'GDS_VMID9_BASE__BASE__SHIFT', + 'GDS_VMID9_BASE__UNUSED_MASK', 'GDS_VMID9_BASE__UNUSED__SHIFT', + 'GDS_VMID9_SIZE__SIZE_MASK', 'GDS_VMID9_SIZE__SIZE__SHIFT', + 'GDS_VMID9_SIZE__UNUSED_MASK', 'GDS_VMID9_SIZE__UNUSED__SHIFT', + 'GDS_VM_PROTECTION_FAULT__ADDRESS_MASK', + 'GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT', + 'GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK', + 'GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT', + 'GDS_VM_PROTECTION_FAULT__GRBM_MASK', + 'GDS_VM_PROTECTION_FAULT__GRBM__SHIFT', + 'GDS_VM_PROTECTION_FAULT__GWS_MASK', + 'GDS_VM_PROTECTION_FAULT__GWS__SHIFT', + 'GDS_VM_PROTECTION_FAULT__OA_MASK', + 'GDS_VM_PROTECTION_FAULT__OA__SHIFT', + 'GDS_VM_PROTECTION_FAULT__TMZ_MASK', + 'GDS_VM_PROTECTION_FAULT__TMZ__SHIFT', + 'GDS_VM_PROTECTION_FAULT__UNUSED1_MASK', + 'GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT', + 'GDS_VM_PROTECTION_FAULT__UNUSED2_MASK', + 'GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT', + 'GDS_VM_PROTECTION_FAULT__VMID_MASK', + 'GDS_VM_PROTECTION_FAULT__VMID__SHIFT', + 'GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK', + 'GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT', + 'GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK', + 'GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT', + 'GDS_WR_ADDR__WRITE_ADDR_MASK', 'GDS_WR_ADDR__WRITE_ADDR__SHIFT', + 'GDS_WR_BURST_ADDR__WRITE_ADDR_MASK', + 'GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT', + 'GDS_WR_BURST_DATA__WRITE_DATA_MASK', + 'GDS_WR_BURST_DATA__WRITE_DATA__SHIFT', + 'GDS_WR_DATA__WRITE_DATA_MASK', 'GDS_WR_DATA__WRITE_DATA__SHIFT', + 'GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK', + 'GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT', + 'GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK', + 'GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT', + 'GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK', + 'GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT', + 'GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK', + 'GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT', + 'GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK', + 'GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT', + 'GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK', + 'GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT', + 'GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK', + 'GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT', + 'GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK', + 'GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT', + 'GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'GE2_SE_CNTL_STATUS__HS_BUSY_MASK', + 'GE2_SE_CNTL_STATUS__HS_BUSY__SHIFT', + 'GE2_SE_CNTL_STATUS__NGG_BUSY_MASK', + 'GE2_SE_CNTL_STATUS__NGG_BUSY__SHIFT', + 'GE2_SE_CNTL_STATUS__TE_BUSY_MASK', + 'GE2_SE_CNTL_STATUS__TE_BUSY__SHIFT', + 'GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'GE_CNTL__BREAK_PRIMGRP_AT_EOI_MASK', + 'GE_CNTL__BREAK_PRIMGRP_AT_EOI__SHIFT', + 'GE_CNTL__BREAK_SUBGRP_AT_EOI_MASK', + 'GE_CNTL__BREAK_SUBGRP_AT_EOI__SHIFT', + 'GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP_MASK', + 'GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP__SHIFT', + 'GE_CNTL__GCR_DISABLE_MASK', 'GE_CNTL__GCR_DISABLE__SHIFT', + 'GE_CNTL__PACKET_TO_ONE_PA_MASK', + 'GE_CNTL__PACKET_TO_ONE_PA__SHIFT', + 'GE_CNTL__PRIMS_PER_SUBGRP_MASK', + 'GE_CNTL__PRIMS_PER_SUBGRP__SHIFT', 'GE_CNTL__PRIM_GRP_SIZE_MASK', + 'GE_CNTL__PRIM_GRP_SIZE__SHIFT', 'GE_CNTL__VERTS_PER_SUBGRP_MASK', + 'GE_CNTL__VERTS_PER_SUBGRP__SHIFT', + 'GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z_MASK', + 'GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z__SHIFT', + 'GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X_MASK', + 'GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X__SHIFT', + 'GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y_MASK', + 'GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y__SHIFT', + 'GE_INDX_OFFSET__INDX_OFFSET_MASK', + 'GE_INDX_OFFSET__INDX_OFFSET__SHIFT', + 'GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK', + 'GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT', + 'GE_MAX_VTX_INDX__MAX_INDX_MASK', + 'GE_MAX_VTX_INDX__MAX_INDX__SHIFT', + 'GE_MIN_VTX_INDX__MIN_INDX_MASK', + 'GE_MIN_VTX_INDX__MIN_INDX__SHIFT', + 'GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX_MASK', + 'GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX__SHIFT', + 'GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK', + 'GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT', + 'GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK', + 'GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT', + 'GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK', + 'GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT', + 'GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK', + 'GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT', + 'GE_PA_IF_SAFE_REG__GE_PA_CSB_MASK', + 'GE_PA_IF_SAFE_REG__GE_PA_CSB__SHIFT', + 'GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD_MASK', + 'GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD__SHIFT', + 'GE_PC_ALLOC__NUM_PC_LINES_MASK', + 'GE_PC_ALLOC__NUM_PC_LINES__SHIFT', + 'GE_PC_ALLOC__OVERSUB_EN_MASK', 'GE_PC_ALLOC__OVERSUB_EN__SHIFT', + 'GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK', + 'GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT', + 'GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK', + 'GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT', + 'GE_PRIV_CONTROL__DISABLE_ACCUM_AGM_MASK', + 'GE_PRIV_CONTROL__DISABLE_ACCUM_AGM__SHIFT', + 'GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK', + 'GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT', + 'GE_PRIV_CONTROL__RESERVED_MASK', + 'GE_PRIV_CONTROL__RESERVED__SHIFT', + 'GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK', + 'GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT', + 'GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT_MASK', + 'GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT__SHIFT', + 'GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM_MASK', + 'GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM__SHIFT', + 'GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT_MASK', + 'GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT__SHIFT', + 'GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT_MASK', + 'GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT__SHIFT', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT_MASK', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT__SHIFT', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM_MASK', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM__SHIFT', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT_MASK', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT__SHIFT', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT_MASK', + 'GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT__SHIFT', + 'GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS_MASK', + 'GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS__SHIFT', + 'GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES_MASK', + 'GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES__SHIFT', + 'GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM_MASK', + 'GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM__SHIFT', + 'GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT_MASK', + 'GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT__SHIFT', + 'GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM_MASK', + 'GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM__SHIFT', + 'GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT_MASK', + 'GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT__SHIFT', + 'GE_RATE_CNTL_2__ENABLE_RATE_CNTL_MASK', + 'GE_RATE_CNTL_2__ENABLE_RATE_CNTL__SHIFT', + 'GE_RATE_CNTL_2__MERGED_HS_GS_MODE_MASK', + 'GE_RATE_CNTL_2__MERGED_HS_GS_MODE__SHIFT', + 'GE_RATE_CNTL_2__MERGED_LS_ES_MODE_MASK', + 'GE_RATE_CNTL_2__MERGED_LS_ES_MODE__SHIFT', + 'GE_RATE_CNTL_2__SWAP_PRIORITY_MASK', + 'GE_RATE_CNTL_2__SWAP_PRIORITY__SHIFT', + 'GE_SPI_IF_SAFE_REG__GE_SPI_GRP_MASK', + 'GE_SPI_IF_SAFE_REG__GE_SPI_GRP__SHIFT', + 'GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA_MASK', + 'GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA__SHIFT', + 'GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA_MASK', + 'GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA__SHIFT', + 'GE_STATUS__PERFCOUNTER_STATUS_MASK', + 'GE_STATUS__PERFCOUNTER_STATUS__SHIFT', + 'GE_STATUS__THREAD_TRACE_STATUS_MASK', + 'GE_STATUS__THREAD_TRACE_STATUS__SHIFT', + 'GE_STEREO_CNTL__EN_STEREO_MASK', + 'GE_STEREO_CNTL__EN_STEREO__SHIFT', + 'GE_STEREO_CNTL__RT_SLICE_MASK', + 'GE_STEREO_CNTL__RT_SLICE__SHIFT', + 'GE_STEREO_CNTL__VIEWPORT_MASK', + 'GE_STEREO_CNTL__VIEWPORT__SHIFT', 'GE_USER_VGPR1__DATA_MASK', + 'GE_USER_VGPR1__DATA__SHIFT', 'GE_USER_VGPR2__DATA_MASK', + 'GE_USER_VGPR2__DATA__SHIFT', 'GE_USER_VGPR3__DATA_MASK', + 'GE_USER_VGPR3__DATA__SHIFT', + 'GE_USER_VGPR_EN__EN_USER_VGPR1_MASK', + 'GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT', + 'GE_USER_VGPR_EN__EN_USER_VGPR2_MASK', + 'GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT', + 'GE_USER_VGPR_EN__EN_USER_VGPR3_MASK', + 'GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT', + 'GFX_COPY_STATE__SRC_STATE_ID_MASK', + 'GFX_COPY_STATE__SRC_STATE_ID__SHIFT', + 'GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__CORE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__CORE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__GCR_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__GCR_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__IB_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__IB_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__REG_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__REG_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE__SHIFT', + 'GFX_ICG_GL2C_CTRL__TAG_OVERRIDE_MASK', + 'GFX_ICG_GL2C_CTRL__TAG_OVERRIDE__SHIFT', + 'GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL_MASK', + 'GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL__SHIFT', + 'GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE_MASK', + 'GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE__SHIFT', + 'GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE_MASK', + 'GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE__SHIFT', + 'GFX_IMU_C2PMSG_0__DATA_MASK', 'GFX_IMU_C2PMSG_0__DATA__SHIFT', + 'GFX_IMU_C2PMSG_10__DATA_MASK', 'GFX_IMU_C2PMSG_10__DATA__SHIFT', + 'GFX_IMU_C2PMSG_11__DATA_MASK', 'GFX_IMU_C2PMSG_11__DATA__SHIFT', + 'GFX_IMU_C2PMSG_12__DATA_MASK', 'GFX_IMU_C2PMSG_12__DATA__SHIFT', + 'GFX_IMU_C2PMSG_13__DATA_MASK', 'GFX_IMU_C2PMSG_13__DATA__SHIFT', + 'GFX_IMU_C2PMSG_14__DATA_MASK', 'GFX_IMU_C2PMSG_14__DATA__SHIFT', + 'GFX_IMU_C2PMSG_15__DATA_MASK', 'GFX_IMU_C2PMSG_15__DATA__SHIFT', + 'GFX_IMU_C2PMSG_16__DATA_MASK', 'GFX_IMU_C2PMSG_16__DATA__SHIFT', + 'GFX_IMU_C2PMSG_17__DATA_MASK', 'GFX_IMU_C2PMSG_17__DATA__SHIFT', + 'GFX_IMU_C2PMSG_18__DATA_MASK', 'GFX_IMU_C2PMSG_18__DATA__SHIFT', + 'GFX_IMU_C2PMSG_19__DATA_MASK', 'GFX_IMU_C2PMSG_19__DATA__SHIFT', + 'GFX_IMU_C2PMSG_1__DATA_MASK', 'GFX_IMU_C2PMSG_1__DATA__SHIFT', + 'GFX_IMU_C2PMSG_20__DATA_MASK', 'GFX_IMU_C2PMSG_20__DATA__SHIFT', + 'GFX_IMU_C2PMSG_21__DATA_MASK', 'GFX_IMU_C2PMSG_21__DATA__SHIFT', + 'GFX_IMU_C2PMSG_22__DATA_MASK', 'GFX_IMU_C2PMSG_22__DATA__SHIFT', + 'GFX_IMU_C2PMSG_23__DATA_MASK', 'GFX_IMU_C2PMSG_23__DATA__SHIFT', + 'GFX_IMU_C2PMSG_24__DATA_MASK', 'GFX_IMU_C2PMSG_24__DATA__SHIFT', + 'GFX_IMU_C2PMSG_25__DATA_MASK', 'GFX_IMU_C2PMSG_25__DATA__SHIFT', + 'GFX_IMU_C2PMSG_26__DATA_MASK', 'GFX_IMU_C2PMSG_26__DATA__SHIFT', + 'GFX_IMU_C2PMSG_27__DATA_MASK', 'GFX_IMU_C2PMSG_27__DATA__SHIFT', + 'GFX_IMU_C2PMSG_28__DATA_MASK', 'GFX_IMU_C2PMSG_28__DATA__SHIFT', + 'GFX_IMU_C2PMSG_29__DATA_MASK', 'GFX_IMU_C2PMSG_29__DATA__SHIFT', + 'GFX_IMU_C2PMSG_2__DATA_MASK', 'GFX_IMU_C2PMSG_2__DATA__SHIFT', + 'GFX_IMU_C2PMSG_30__DATA_MASK', 'GFX_IMU_C2PMSG_30__DATA__SHIFT', + 'GFX_IMU_C2PMSG_31__DATA_MASK', 'GFX_IMU_C2PMSG_31__DATA__SHIFT', + 'GFX_IMU_C2PMSG_32__DATA_MASK', 'GFX_IMU_C2PMSG_32__DATA__SHIFT', + 'GFX_IMU_C2PMSG_33__DATA_MASK', 'GFX_IMU_C2PMSG_33__DATA__SHIFT', + 'GFX_IMU_C2PMSG_34__DATA_MASK', 'GFX_IMU_C2PMSG_34__DATA__SHIFT', + 'GFX_IMU_C2PMSG_35__DATA_MASK', 'GFX_IMU_C2PMSG_35__DATA__SHIFT', + 'GFX_IMU_C2PMSG_36__DATA_MASK', 'GFX_IMU_C2PMSG_36__DATA__SHIFT', + 'GFX_IMU_C2PMSG_37__DATA_MASK', 'GFX_IMU_C2PMSG_37__DATA__SHIFT', + 'GFX_IMU_C2PMSG_38__DATA_MASK', 'GFX_IMU_C2PMSG_38__DATA__SHIFT', + 'GFX_IMU_C2PMSG_39__DATA_MASK', 'GFX_IMU_C2PMSG_39__DATA__SHIFT', + 'GFX_IMU_C2PMSG_3__DATA_MASK', 'GFX_IMU_C2PMSG_3__DATA__SHIFT', + 'GFX_IMU_C2PMSG_40__DATA_MASK', 'GFX_IMU_C2PMSG_40__DATA__SHIFT', + 'GFX_IMU_C2PMSG_41__DATA_MASK', 'GFX_IMU_C2PMSG_41__DATA__SHIFT', + 'GFX_IMU_C2PMSG_42__DATA_MASK', 'GFX_IMU_C2PMSG_42__DATA__SHIFT', + 'GFX_IMU_C2PMSG_43__DATA_MASK', 'GFX_IMU_C2PMSG_43__DATA__SHIFT', + 'GFX_IMU_C2PMSG_44__DATA_MASK', 'GFX_IMU_C2PMSG_44__DATA__SHIFT', + 'GFX_IMU_C2PMSG_45__DATA_MASK', 'GFX_IMU_C2PMSG_45__DATA__SHIFT', + 'GFX_IMU_C2PMSG_46__DATA_MASK', 'GFX_IMU_C2PMSG_46__DATA__SHIFT', + 'GFX_IMU_C2PMSG_47__DATA_MASK', 'GFX_IMU_C2PMSG_47__DATA__SHIFT', + 'GFX_IMU_C2PMSG_4__DATA_MASK', 'GFX_IMU_C2PMSG_4__DATA__SHIFT', + 'GFX_IMU_C2PMSG_5__DATA_MASK', 'GFX_IMU_C2PMSG_5__DATA__SHIFT', + 'GFX_IMU_C2PMSG_6__DATA_MASK', 'GFX_IMU_C2PMSG_6__DATA__SHIFT', + 'GFX_IMU_C2PMSG_7__DATA_MASK', 'GFX_IMU_C2PMSG_7__DATA__SHIFT', + 'GFX_IMU_C2PMSG_8__DATA_MASK', 'GFX_IMU_C2PMSG_8__DATA__SHIFT', + 'GFX_IMU_C2PMSG_9__DATA_MASK', 'GFX_IMU_C2PMSG_9__DATA__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47__SHIFT', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15_MASK', + 'GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15__SHIFT', + 'GFX_IMU_CLK_CTRL__CG_OVR_CORE_MASK', + 'GFX_IMU_CLK_CTRL__CG_OVR_CORE__SHIFT', + 'GFX_IMU_CLK_CTRL__CG_OVR_MASK', + 'GFX_IMU_CLK_CTRL__CG_OVR__SHIFT', + 'GFX_IMU_CLK_CTRL__CLKDIV_MASK', + 'GFX_IMU_CLK_CTRL__CLKDIV__SHIFT', + 'GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD_MASK', + 'GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD__SHIFT', + 'GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG_MASK', + 'GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG__SHIFT', + 'GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV_MASK', + 'GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV__SHIFT', + 'GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG_MASK', + 'GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG__SHIFT', + 'GFX_IMU_CORE_CTRL__BREAK_IN_MASK', + 'GFX_IMU_CORE_CTRL__BREAK_IN__SHIFT', + 'GFX_IMU_CORE_CTRL__BREAK_OUT_ACK_MASK', + 'GFX_IMU_CORE_CTRL__BREAK_OUT_ACK__SHIFT', + 'GFX_IMU_CORE_CTRL__CRESET_MASK', + 'GFX_IMU_CORE_CTRL__CRESET__SHIFT', + 'GFX_IMU_CORE_CTRL__CSTALL_MASK', + 'GFX_IMU_CORE_CTRL__CSTALL__SHIFT', + 'GFX_IMU_CORE_CTRL__DRESET_MASK', + 'GFX_IMU_CORE_CTRL__DRESET__SHIFT', + 'GFX_IMU_CORE_CTRL__HALT_ON_RESET_MASK', + 'GFX_IMU_CORE_CTRL__HALT_ON_RESET__SHIFT', + 'GFX_IMU_CORE_INT_STATUS__INTERRUPT_24_MASK', + 'GFX_IMU_CORE_INT_STATUS__INTERRUPT_24__SHIFT', + 'GFX_IMU_CORE_INT_STATUS__INTERRUPT_25_MASK', + 'GFX_IMU_CORE_INT_STATUS__INTERRUPT_25__SHIFT', + 'GFX_IMU_CORE_INT_STATUS__INTERRUPT_29_MASK', + 'GFX_IMU_CORE_INT_STATUS__INTERRUPT_29__SHIFT', + 'GFX_IMU_CORE_STATUS__BREAK_IN_ACK_MASK', + 'GFX_IMU_CORE_STATUS__BREAK_IN_ACK__SHIFT', + 'GFX_IMU_CORE_STATUS__BREAK_OUT_MASK', + 'GFX_IMU_CORE_STATUS__BREAK_OUT__SHIFT', + 'GFX_IMU_CORE_STATUS__CBUSY_MASK', + 'GFX_IMU_CORE_STATUS__CBUSY__SHIFT', + 'GFX_IMU_CORE_STATUS__CINTLEVEL_MASK', + 'GFX_IMU_CORE_STATUS__CINTLEVEL__SHIFT', + 'GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL_MASK', + 'GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL__SHIFT', + 'GFX_IMU_CORE_STATUS__FAULT_TYPE_MASK', + 'GFX_IMU_CORE_STATUS__FAULT_TYPE__SHIFT', + 'GFX_IMU_CORE_STATUS__PWAIT_MODE_MASK', + 'GFX_IMU_CORE_STATUS__PWAIT_MODE__SHIFT', + 'GFX_IMU_CORE_STATUS__P_FATAL_ERROR_MASK', + 'GFX_IMU_CORE_STATUS__P_FATAL_ERROR__SHIFT', + 'GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT_MASK', + 'GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT__SHIFT', + 'GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR_MASK', + 'GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR__SHIFT', + 'GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS_MASK', + 'GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS__SHIFT', + 'GFX_IMU_DOORBELL_CONTROL__OVR_EN_MASK', + 'GFX_IMU_DOORBELL_CONTROL__OVR_EN__SHIFT', + 'GFX_IMU_DPM_ACC__COUNT_MASK', 'GFX_IMU_DPM_ACC__COUNT__SHIFT', + 'GFX_IMU_DPM_CONTROL__ACC_RESET_MASK', + 'GFX_IMU_DPM_CONTROL__ACC_RESET__SHIFT', + 'GFX_IMU_DPM_CONTROL__ACC_START_MASK', + 'GFX_IMU_DPM_CONTROL__ACC_START__SHIFT', + 'GFX_IMU_DPM_CONTROL__BUSY_MASK_MASK', + 'GFX_IMU_DPM_CONTROL__BUSY_MASK__SHIFT', + 'GFX_IMU_DPM_REF_COUNTER__COUNT_MASK', + 'GFX_IMU_DPM_REF_COUNTER__COUNT__SHIFT', + 'GFX_IMU_D_RAM_ADDR__ADDR_MASK', + 'GFX_IMU_D_RAM_ADDR__ADDR__SHIFT', + 'GFX_IMU_D_RAM_DATA__DATA_MASK', + 'GFX_IMU_D_RAM_DATA__DATA__SHIFT', + 'GFX_IMU_FENCE_CTRL__ARM_LOG_MASK', + 'GFX_IMU_FENCE_CTRL__ARM_LOG__SHIFT', + 'GFX_IMU_FENCE_CTRL__ENABLED_MASK', + 'GFX_IMU_FENCE_CTRL__ENABLED__SHIFT', + 'GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS_MASK', + 'GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS__SHIFT', + 'GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN_MASK', + 'GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN__SHIFT', + 'GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_MASK', + 'GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR__SHIFT', + 'GFX_IMU_FENCE_LOG_ADDR__ADDR_MASK', + 'GFX_IMU_FENCE_LOG_ADDR__ADDR__SHIFT', + 'GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID_MASK', + 'GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID__SHIFT', + 'GFX_IMU_FENCE_LOG_INIT__UNIT_ID_MASK', + 'GFX_IMU_FENCE_LOG_INIT__UNIT_ID__SHIFT', + 'GFX_IMU_FUSE_CTRL__DIV_OVR_EN_MASK', + 'GFX_IMU_FUSE_CTRL__DIV_OVR_EN__SHIFT', + 'GFX_IMU_FUSE_CTRL__DIV_OVR_MASK', + 'GFX_IMU_FUSE_CTRL__DIV_OVR__SHIFT', + 'GFX_IMU_FUSE_CTRL__FORCE_DONE_MASK', + 'GFX_IMU_FUSE_CTRL__FORCE_DONE__SHIFT', + 'GFX_IMU_FW_GTS_HI__TSTAMP_HI_MASK', + 'GFX_IMU_FW_GTS_HI__TSTAMP_HI__SHIFT', + 'GFX_IMU_FW_GTS_LO__TSTAMP_LO_MASK', + 'GFX_IMU_FW_GTS_LO__TSTAMP_LO__SHIFT', + 'GFX_IMU_GAP_PWROK__GAP_PWROK_MASK', + 'GFX_IMU_GAP_PWROK__GAP_PWROK__SHIFT', + 'GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL_MASK', + 'GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL__SHIFT', + 'GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL_MASK', + 'GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL__SHIFT', + 'GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW_MASK', + 'GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW__SHIFT', + 'GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB_MASK', + 'GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB__SHIFT', + 'GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn_MASK', + 'GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn__SHIFT', + 'GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn_MASK', + 'GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn__SHIFT', + 'GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn_MASK', + 'GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn__SHIFT', + 'GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN_MASK', + 'GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN__SHIFT', + 'GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN_MASK', + 'GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN__SHIFT', + 'GFX_IMU_GFX_RESET_CTRL__EA_RESETB_MASK', + 'GFX_IMU_GFX_RESET_CTRL__EA_RESETB__SHIFT', + 'GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB_MASK', + 'GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB__SHIFT', + 'GFX_IMU_GFX_RESET_CTRL__HARD_RESETB_MASK', + 'GFX_IMU_GFX_RESET_CTRL__HARD_RESETB__SHIFT', + 'GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB_MASK', + 'GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB__SHIFT', + 'GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB_MASK', + 'GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB__SHIFT', + 'GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK', + 'GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT', + 'GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK', + 'GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT', + 'GFX_IMU_IH_CTRL_1__CONTEXT_ID_MASK', + 'GFX_IMU_IH_CTRL_1__CONTEXT_ID__SHIFT', + 'GFX_IMU_IH_CTRL_2__CONTEXT_ID_MASK', + 'GFX_IMU_IH_CTRL_2__CONTEXT_ID__SHIFT', + 'GFX_IMU_IH_CTRL_2__RING_ID_MASK', + 'GFX_IMU_IH_CTRL_2__RING_ID__SHIFT', + 'GFX_IMU_IH_CTRL_2__SRSTB_MASK', + 'GFX_IMU_IH_CTRL_2__SRSTB__SHIFT', + 'GFX_IMU_IH_CTRL_2__VM_ID_MASK', + 'GFX_IMU_IH_CTRL_2__VM_ID__SHIFT', + 'GFX_IMU_IH_CTRL_3__SOURCE_ID_MASK', + 'GFX_IMU_IH_CTRL_3__SOURCE_ID__SHIFT', + 'GFX_IMU_IH_CTRL_3__VF_ID_MASK', + 'GFX_IMU_IH_CTRL_3__VF_ID__SHIFT', 'GFX_IMU_IH_CTRL_3__VF_MASK', + 'GFX_IMU_IH_CTRL_3__VF__SHIFT', 'GFX_IMU_IH_STATUS__IH_BUSY_MASK', + 'GFX_IMU_IH_STATUS__IH_BUSY__SHIFT', + 'GFX_IMU_I_RAM_ADDR__ADDR_MASK', + 'GFX_IMU_I_RAM_ADDR__ADDR__SHIFT', + 'GFX_IMU_I_RAM_DATA__DATA_MASK', + 'GFX_IMU_I_RAM_DATA__DATA__SHIFT', + 'GFX_IMU_MP1_MUTEX__MUTEX_MASK', + 'GFX_IMU_MP1_MUTEX__MUTEX__SHIFT', + 'GFX_IMU_MSG_FLAGS__STATUS_MASK', + 'GFX_IMU_MSG_FLAGS__STATUS__SHIFT', + 'GFX_IMU_PIC_INTR_ID__INTR_n_MASK', + 'GFX_IMU_PIC_INTR_ID__INTR_n__SHIFT', + 'GFX_IMU_PIC_INTR__INTR_n_MASK', + 'GFX_IMU_PIC_INTR__INTR_n__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_0_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_0__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_10_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_10__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_11_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_11__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_12_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_12__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_13_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_13__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_14_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_14__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_15_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_15__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_16_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_16__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_17_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_17__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_18_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_18__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_19_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_19__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_1_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_1__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_20_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_20__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_21_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_21__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_22_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_22__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_23_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_23__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_24_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_24__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_25_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_25__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_26_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_26__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_27_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_27__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_28_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_28__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_29_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_29__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_2_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_2__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_30_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_30__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_31_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_31__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_3_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_3__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_4_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_4__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_5_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_5__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_6_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_6__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_7_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_7__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_8_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_8__SHIFT', + 'GFX_IMU_PIC_INT_EDGE__EDGE_9_MASK', + 'GFX_IMU_PIC_INT_EDGE__EDGE_9__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_0_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_0__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_10_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_10__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_11_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_11__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_12_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_12__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_13_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_13__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_14_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_14__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_15_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_15__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_16_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_16__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_17_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_17__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_18_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_18__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_19_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_19__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_1_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_1__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_20_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_20__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_21_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_21__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_22_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_22__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_23_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_23__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_24_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_24__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_25_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_25__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_26_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_26__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_27_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_27__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_28_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_28__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_29_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_29__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_2_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_2__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_30_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_30__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_31_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_31__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_3_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_3__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_4_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_4__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_5_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_5__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_6_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_6__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_7_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_7__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_8_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_8__SHIFT', + 'GFX_IMU_PIC_INT_LVL__LVL_9_MASK', + 'GFX_IMU_PIC_INT_LVL__LVL_9__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_0_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_0__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_10_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_10__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_11_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_11__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_12_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_12__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_13_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_13__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_14_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_14__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_15_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_15__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_16_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_16__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_17_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_17__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_18_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_18__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_19_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_19__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_1_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_1__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_20_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_20__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_21_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_21__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_22_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_22__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_23_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_23__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_24_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_24__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_25_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_25__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_26_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_26__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_27_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_27__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_28_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_28__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_29_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_29__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_2_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_2__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_30_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_30__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_31_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_31__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_3_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_3__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_4_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_4__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_5_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_5__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_6_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_6__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_7_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_7__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_8_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_8__SHIFT', + 'GFX_IMU_PIC_INT_MASK__MASK_9_MASK', + 'GFX_IMU_PIC_INT_MASK__MASK_9__SHIFT', + 'GFX_IMU_PIC_INT_PRI_0__PRI_0_MASK', + 'GFX_IMU_PIC_INT_PRI_0__PRI_0__SHIFT', + 'GFX_IMU_PIC_INT_PRI_0__PRI_1_MASK', + 'GFX_IMU_PIC_INT_PRI_0__PRI_1__SHIFT', + 'GFX_IMU_PIC_INT_PRI_0__PRI_2_MASK', + 'GFX_IMU_PIC_INT_PRI_0__PRI_2__SHIFT', + 'GFX_IMU_PIC_INT_PRI_0__PRI_3_MASK', + 'GFX_IMU_PIC_INT_PRI_0__PRI_3__SHIFT', + 'GFX_IMU_PIC_INT_PRI_1__PRI_4_MASK', + 'GFX_IMU_PIC_INT_PRI_1__PRI_4__SHIFT', + 'GFX_IMU_PIC_INT_PRI_1__PRI_5_MASK', + 'GFX_IMU_PIC_INT_PRI_1__PRI_5__SHIFT', + 'GFX_IMU_PIC_INT_PRI_1__PRI_6_MASK', + 'GFX_IMU_PIC_INT_PRI_1__PRI_6__SHIFT', + 'GFX_IMU_PIC_INT_PRI_1__PRI_7_MASK', + 'GFX_IMU_PIC_INT_PRI_1__PRI_7__SHIFT', + 'GFX_IMU_PIC_INT_PRI_2__PRI_10_MASK', + 'GFX_IMU_PIC_INT_PRI_2__PRI_10__SHIFT', + 'GFX_IMU_PIC_INT_PRI_2__PRI_11_MASK', + 'GFX_IMU_PIC_INT_PRI_2__PRI_11__SHIFT', + 'GFX_IMU_PIC_INT_PRI_2__PRI_8_MASK', + 'GFX_IMU_PIC_INT_PRI_2__PRI_8__SHIFT', + 'GFX_IMU_PIC_INT_PRI_2__PRI_9_MASK', + 'GFX_IMU_PIC_INT_PRI_2__PRI_9__SHIFT', + 'GFX_IMU_PIC_INT_PRI_3__PRI_12_MASK', + 'GFX_IMU_PIC_INT_PRI_3__PRI_12__SHIFT', + 'GFX_IMU_PIC_INT_PRI_3__PRI_13_MASK', + 'GFX_IMU_PIC_INT_PRI_3__PRI_13__SHIFT', + 'GFX_IMU_PIC_INT_PRI_3__PRI_14_MASK', + 'GFX_IMU_PIC_INT_PRI_3__PRI_14__SHIFT', + 'GFX_IMU_PIC_INT_PRI_3__PRI_15_MASK', + 'GFX_IMU_PIC_INT_PRI_3__PRI_15__SHIFT', + 'GFX_IMU_PIC_INT_PRI_4__PRI_16_MASK', + 'GFX_IMU_PIC_INT_PRI_4__PRI_16__SHIFT', + 'GFX_IMU_PIC_INT_PRI_4__PRI_17_MASK', + 'GFX_IMU_PIC_INT_PRI_4__PRI_17__SHIFT', + 'GFX_IMU_PIC_INT_PRI_4__PRI_18_MASK', + 'GFX_IMU_PIC_INT_PRI_4__PRI_18__SHIFT', + 'GFX_IMU_PIC_INT_PRI_4__PRI_19_MASK', + 'GFX_IMU_PIC_INT_PRI_4__PRI_19__SHIFT', + 'GFX_IMU_PIC_INT_PRI_5__PRI_20_MASK', + 'GFX_IMU_PIC_INT_PRI_5__PRI_20__SHIFT', + 'GFX_IMU_PIC_INT_PRI_5__PRI_21_MASK', + 'GFX_IMU_PIC_INT_PRI_5__PRI_21__SHIFT', + 'GFX_IMU_PIC_INT_PRI_5__PRI_22_MASK', + 'GFX_IMU_PIC_INT_PRI_5__PRI_22__SHIFT', + 'GFX_IMU_PIC_INT_PRI_5__PRI_23_MASK', + 'GFX_IMU_PIC_INT_PRI_5__PRI_23__SHIFT', + 'GFX_IMU_PIC_INT_PRI_6__PRI_24_MASK', + 'GFX_IMU_PIC_INT_PRI_6__PRI_24__SHIFT', + 'GFX_IMU_PIC_INT_PRI_6__PRI_25_MASK', + 'GFX_IMU_PIC_INT_PRI_6__PRI_25__SHIFT', + 'GFX_IMU_PIC_INT_PRI_6__PRI_26_MASK', + 'GFX_IMU_PIC_INT_PRI_6__PRI_26__SHIFT', + 'GFX_IMU_PIC_INT_PRI_6__PRI_27_MASK', + 'GFX_IMU_PIC_INT_PRI_6__PRI_27__SHIFT', + 'GFX_IMU_PIC_INT_PRI_7__PRI_28_MASK', + 'GFX_IMU_PIC_INT_PRI_7__PRI_28__SHIFT', + 'GFX_IMU_PIC_INT_PRI_7__PRI_29_MASK', + 'GFX_IMU_PIC_INT_PRI_7__PRI_29__SHIFT', + 'GFX_IMU_PIC_INT_PRI_7__PRI_30_MASK', + 'GFX_IMU_PIC_INT_PRI_7__PRI_30__SHIFT', + 'GFX_IMU_PIC_INT_PRI_7__PRI_31_MASK', + 'GFX_IMU_PIC_INT_PRI_7__PRI_31__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS0_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS0__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS10_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS10__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS11_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS11__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS12_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS12__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS13_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS13__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS14_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS14__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS15_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS15__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS16_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS16__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS17_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS17__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS18_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS18__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS19_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS19__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS1_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS1__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS20_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS20__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS21_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS21__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS22_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS22__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS23_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS23__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS24_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS24__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS25_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS25__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS26_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS26__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS27_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS27__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS28_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS28__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS29_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS29__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS2_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS2__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS30_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS30__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS31_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS31__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS3_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS3__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS4_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS4__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS5_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS5__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS6_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS6__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS7_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS7__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS8_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS8__SHIFT', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS9_MASK', + 'GFX_IMU_PIC_INT_STATUS__INT_STATUS9__SHIFT', + 'GFX_IMU_PROGRAM_CTR__PC_MASK', 'GFX_IMU_PROGRAM_CTR__PC__SHIFT', + 'GFX_IMU_PWRMGT_IRQ_CTRL__REQ_MASK', + 'GFX_IMU_PWRMGT_IRQ_CTRL__REQ__SHIFT', + 'GFX_IMU_PWROKRAW__PWROKRAW_MASK', + 'GFX_IMU_PWROKRAW__PWROKRAW__SHIFT', 'GFX_IMU_PWROK__PWROK_MASK', + 'GFX_IMU_PWROK__PWROK__SHIFT', 'GFX_IMU_RESETn__Cpl_RESETn_MASK', + 'GFX_IMU_RESETn__Cpl_RESETn__SHIFT', + 'GFX_IMU_RLC_CG_CTRL__FORCE_CGCG_MASK', + 'GFX_IMU_RLC_CG_CTRL__FORCE_CGCG__SHIFT', + 'GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN_MASK', + 'GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN__SHIFT', + 'GFX_IMU_RLC_CMD__CMD_MASK', 'GFX_IMU_RLC_CMD__CMD__SHIFT', + 'GFX_IMU_RLC_DATA_0__DATA_MASK', + 'GFX_IMU_RLC_DATA_0__DATA__SHIFT', + 'GFX_IMU_RLC_DATA_1__DATA_MASK', + 'GFX_IMU_RLC_DATA_1__DATA__SHIFT', + 'GFX_IMU_RLC_DATA_2__DATA_MASK', + 'GFX_IMU_RLC_DATA_2__DATA__SHIFT', + 'GFX_IMU_RLC_DATA_3__DATA_MASK', + 'GFX_IMU_RLC_DATA_3__DATA__SHIFT', + 'GFX_IMU_RLC_DATA_4__DATA_MASK', + 'GFX_IMU_RLC_DATA_4__DATA__SHIFT', + 'GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK', + 'GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT', + 'GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK', + 'GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT', + 'GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY_MASK', + 'GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY__SHIFT', + 'GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR_MASK', + 'GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR__SHIFT', + 'GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG_MASK', + 'GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG__SHIFT', + 'GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG_MASK', + 'GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG__SHIFT', + 'GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE_MASK', + 'GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE__SHIFT', + 'GFX_IMU_RLC_MUTEX__MUTEX_MASK', + 'GFX_IMU_RLC_MUTEX__MUTEX__SHIFT', + 'GFX_IMU_RLC_OVERRIDE__DS_ALLOW_MASK', + 'GFX_IMU_RLC_OVERRIDE__DS_ALLOW__SHIFT', + 'GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB_MASK', + 'GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB__SHIFT', + 'GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB_MASK', + 'GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB__SHIFT', + 'GFX_IMU_RLC_RAM_DATA__DATA_MASK', + 'GFX_IMU_RLC_RAM_DATA__DATA__SHIFT', + 'GFX_IMU_RLC_RAM_INDEX__INDEX_MASK', + 'GFX_IMU_RLC_RAM_INDEX__INDEX__SHIFT', + 'GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK', + 'GFX_IMU_RLC_RAM_INDEX__RAM_VALID__SHIFT', + 'GFX_IMU_RLC_RAM_INDEX__RLC_INDEX_MASK', + 'GFX_IMU_RLC_RAM_INDEX__RLC_INDEX__SHIFT', + 'GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF_MASK', + 'GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF__SHIFT', + 'GFX_IMU_RLC_RESET_VECTOR__VECTOR_MASK', + 'GFX_IMU_RLC_RESET_VECTOR__VECTOR__SHIFT', + 'GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT_MASK', + 'GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT__SHIFT', + 'GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT_MASK', + 'GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT__SHIFT', + 'GFX_IMU_RLC_STATUS__PD_ACTIVE_MASK', + 'GFX_IMU_RLC_STATUS__PD_ACTIVE__SHIFT', + 'GFX_IMU_RLC_STATUS__RLC_ALIVE_MASK', + 'GFX_IMU_RLC_STATUS__RLC_ALIVE__SHIFT', + 'GFX_IMU_RLC_STATUS__TBD2_MASK', + 'GFX_IMU_RLC_STATUS__TBD2__SHIFT', + 'GFX_IMU_RLC_STATUS__TBD3_MASK', + 'GFX_IMU_RLC_STATUS__TBD3__SHIFT', + 'GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN_MASK', + 'GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN__SHIFT', + 'GFX_IMU_SCRATCH_0__DATA_MASK', 'GFX_IMU_SCRATCH_0__DATA__SHIFT', + 'GFX_IMU_SCRATCH_10__DATA_MASK', + 'GFX_IMU_SCRATCH_10__DATA__SHIFT', + 'GFX_IMU_SCRATCH_11__DATA_MASK', + 'GFX_IMU_SCRATCH_11__DATA__SHIFT', + 'GFX_IMU_SCRATCH_12__DATA_MASK', + 'GFX_IMU_SCRATCH_12__DATA__SHIFT', + 'GFX_IMU_SCRATCH_13__DATA_MASK', + 'GFX_IMU_SCRATCH_13__DATA__SHIFT', + 'GFX_IMU_SCRATCH_14__DATA_MASK', + 'GFX_IMU_SCRATCH_14__DATA__SHIFT', + 'GFX_IMU_SCRATCH_15__DATA_MASK', + 'GFX_IMU_SCRATCH_15__DATA__SHIFT', 'GFX_IMU_SCRATCH_1__DATA_MASK', + 'GFX_IMU_SCRATCH_1__DATA__SHIFT', 'GFX_IMU_SCRATCH_2__DATA_MASK', + 'GFX_IMU_SCRATCH_2__DATA__SHIFT', 'GFX_IMU_SCRATCH_3__DATA_MASK', + 'GFX_IMU_SCRATCH_3__DATA__SHIFT', 'GFX_IMU_SCRATCH_4__DATA_MASK', + 'GFX_IMU_SCRATCH_4__DATA__SHIFT', 'GFX_IMU_SCRATCH_5__DATA_MASK', + 'GFX_IMU_SCRATCH_5__DATA__SHIFT', 'GFX_IMU_SCRATCH_6__DATA_MASK', + 'GFX_IMU_SCRATCH_6__DATA__SHIFT', 'GFX_IMU_SCRATCH_7__DATA_MASK', + 'GFX_IMU_SCRATCH_7__DATA__SHIFT', 'GFX_IMU_SCRATCH_8__DATA_MASK', + 'GFX_IMU_SCRATCH_8__DATA__SHIFT', 'GFX_IMU_SCRATCH_9__DATA_MASK', + 'GFX_IMU_SCRATCH_9__DATA__SHIFT', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__ACK_MASK', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__ACK__SHIFT', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__DATA_MASK', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__DATA__SHIFT', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN_MASK', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN__SHIFT', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__REQ_MASK', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__REQ__SHIFT', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL_MASK', + 'GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL__SHIFT', + 'GFX_IMU_SOC_ADDR__ADDR_MASK', 'GFX_IMU_SOC_ADDR__ADDR__SHIFT', + 'GFX_IMU_SOC_DATA__DATA_MASK', 'GFX_IMU_SOC_DATA__DATA__SHIFT', + 'GFX_IMU_SOC_REQ__ERR_MASK', 'GFX_IMU_SOC_REQ__ERR__SHIFT', + 'GFX_IMU_SOC_REQ__REQ_BUSY_MASK', + 'GFX_IMU_SOC_REQ__REQ_BUSY__SHIFT', 'GFX_IMU_SOC_REQ__R_W_MASK', + 'GFX_IMU_SOC_REQ__R_W__SHIFT', + 'GFX_IMU_STATUS__ALLOW_FA_DCS_MASK', + 'GFX_IMU_STATUS__ALLOW_FA_DCS__SHIFT', + 'GFX_IMU_STATUS__ALLOW_GFXOFF_MASK', + 'GFX_IMU_STATUS__ALLOW_GFXOFF__SHIFT', + 'GFX_IMU_STATUS__DISABLE_GFXCLK_DS_MASK', + 'GFX_IMU_STATUS__DISABLE_GFXCLK_DS__SHIFT', + 'GFX_IMU_STATUS__TBD10_MASK', 'GFX_IMU_STATUS__TBD10__SHIFT', + 'GFX_IMU_STATUS__TBD11_MASK', 'GFX_IMU_STATUS__TBD11__SHIFT', + 'GFX_IMU_STATUS__TBD12_MASK', 'GFX_IMU_STATUS__TBD12__SHIFT', + 'GFX_IMU_STATUS__TBD13_MASK', 'GFX_IMU_STATUS__TBD13__SHIFT', + 'GFX_IMU_STATUS__TBD14_MASK', 'GFX_IMU_STATUS__TBD14__SHIFT', + 'GFX_IMU_STATUS__TBD2_MASK', 'GFX_IMU_STATUS__TBD2__SHIFT', + 'GFX_IMU_STATUS__TBD3_MASK', 'GFX_IMU_STATUS__TBD3__SHIFT', + 'GFX_IMU_STATUS__TBD4_MASK', 'GFX_IMU_STATUS__TBD4__SHIFT', + 'GFX_IMU_STATUS__TBD5_MASK', 'GFX_IMU_STATUS__TBD5__SHIFT', + 'GFX_IMU_STATUS__TBD6_MASK', 'GFX_IMU_STATUS__TBD6__SHIFT', + 'GFX_IMU_STATUS__TBD7_MASK', 'GFX_IMU_STATUS__TBD7__SHIFT', + 'GFX_IMU_STATUS__TBD8_MASK', 'GFX_IMU_STATUS__TBD8__SHIFT', + 'GFX_IMU_STATUS__TBD9_MASK', 'GFX_IMU_STATUS__TBD9__SHIFT', + 'GFX_IMU_TELEMETRY_DATA__CURRENT_MASK', + 'GFX_IMU_TELEMETRY_DATA__CURRENT__SHIFT', + 'GFX_IMU_TELEMETRY_DATA__VOLTAGE_MASK', + 'GFX_IMU_TELEMETRY_DATA__VOLTAGE__SHIFT', + 'GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE_MASK', + 'GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE__SHIFT', + 'GFX_IMU_TELEMETRY__ENABLE_FIFO_MASK', + 'GFX_IMU_TELEMETRY__ENABLE_FIFO__SHIFT', + 'GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY_MASK', + 'GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY__SHIFT', + 'GFX_IMU_TELEMETRY__FIFO_OVERFLOW_MASK', + 'GFX_IMU_TELEMETRY__FIFO_OVERFLOW__SHIFT', + 'GFX_IMU_TELEMETRY__FIFO_UNDERFLOW_MASK', + 'GFX_IMU_TELEMETRY__FIFO_UNDERFLOW__SHIFT', + 'GFX_IMU_TELEMETRY__FSM_STATE_MASK', + 'GFX_IMU_TELEMETRY__FSM_STATE__SHIFT', + 'GFX_IMU_TELEMETRY__SVI_TYPE_MASK', + 'GFX_IMU_TELEMETRY__SVI_TYPE__SHIFT', + 'GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE_MASK', + 'GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE__SHIFT', + 'GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES_MASK', + 'GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES__SHIFT', + 'GFX_IMU_TIMER0_CMP0__VALUE_MASK', + 'GFX_IMU_TIMER0_CMP0__VALUE__SHIFT', + 'GFX_IMU_TIMER0_CMP1__VALUE_MASK', + 'GFX_IMU_TIMER0_CMP1__VALUE__SHIFT', + 'GFX_IMU_TIMER0_CMP3__VALUE_MASK', + 'GFX_IMU_TIMER0_CMP3__VALUE__SHIFT', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0_MASK', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0__SHIFT', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1_MASK', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1__SHIFT', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2_MASK', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2__SHIFT', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3_MASK', + 'GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3__SHIFT', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN0_MASK', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN0__SHIFT', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN1_MASK', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN1__SHIFT', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN2_MASK', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN2__SHIFT', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN3_MASK', + 'GFX_IMU_TIMER0_CMP_INTEN__INT_EN3__SHIFT', + 'GFX_IMU_TIMER0_CTRL0__CLEAR_MASK', + 'GFX_IMU_TIMER0_CTRL0__CLEAR__SHIFT', + 'GFX_IMU_TIMER0_CTRL0__PULSE_EN_MASK', + 'GFX_IMU_TIMER0_CTRL0__PULSE_EN__SHIFT', + 'GFX_IMU_TIMER0_CTRL0__START_STOP_MASK', + 'GFX_IMU_TIMER0_CTRL0__START_STOP__SHIFT', + 'GFX_IMU_TIMER0_CTRL0__UP_DOWN_MASK', + 'GFX_IMU_TIMER0_CTRL0__UP_DOWN__SHIFT', + 'GFX_IMU_TIMER0_CTRL1__PWM_EN_MASK', + 'GFX_IMU_TIMER0_CTRL1__PWM_EN__SHIFT', + 'GFX_IMU_TIMER0_CTRL1__SAT_EN_MASK', + 'GFX_IMU_TIMER0_CTRL1__SAT_EN__SHIFT', + 'GFX_IMU_TIMER0_CTRL1__TS_MODE_MASK', + 'GFX_IMU_TIMER0_CTRL1__TS_MODE__SHIFT', + 'GFX_IMU_TIMER0_VALUE__VALUE_MASK', + 'GFX_IMU_TIMER0_VALUE__VALUE__SHIFT', + 'GFX_IMU_TIMER1_CMP0__VALUE_MASK', + 'GFX_IMU_TIMER1_CMP0__VALUE__SHIFT', + 'GFX_IMU_TIMER1_CMP1__VALUE_MASK', + 'GFX_IMU_TIMER1_CMP1__VALUE__SHIFT', + 'GFX_IMU_TIMER1_CMP3__VALUE_MASK', + 'GFX_IMU_TIMER1_CMP3__VALUE__SHIFT', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0_MASK', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0__SHIFT', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1_MASK', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1__SHIFT', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2_MASK', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2__SHIFT', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3_MASK', + 'GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3__SHIFT', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN0_MASK', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN0__SHIFT', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN1_MASK', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN1__SHIFT', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN2_MASK', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN2__SHIFT', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN3_MASK', + 'GFX_IMU_TIMER1_CMP_INTEN__INT_EN3__SHIFT', + 'GFX_IMU_TIMER1_CTRL0__CLEAR_MASK', + 'GFX_IMU_TIMER1_CTRL0__CLEAR__SHIFT', + 'GFX_IMU_TIMER1_CTRL0__PULSE_EN_MASK', + 'GFX_IMU_TIMER1_CTRL0__PULSE_EN__SHIFT', + 'GFX_IMU_TIMER1_CTRL0__START_STOP_MASK', + 'GFX_IMU_TIMER1_CTRL0__START_STOP__SHIFT', + 'GFX_IMU_TIMER1_CTRL0__UP_DOWN_MASK', + 'GFX_IMU_TIMER1_CTRL0__UP_DOWN__SHIFT', + 'GFX_IMU_TIMER1_CTRL1__PWM_EN_MASK', + 'GFX_IMU_TIMER1_CTRL1__PWM_EN__SHIFT', + 'GFX_IMU_TIMER1_CTRL1__SAT_EN_MASK', + 'GFX_IMU_TIMER1_CTRL1__SAT_EN__SHIFT', + 'GFX_IMU_TIMER1_CTRL1__TS_MODE_MASK', + 'GFX_IMU_TIMER1_CTRL1__TS_MODE__SHIFT', + 'GFX_IMU_TIMER1_VALUE__VALUE_MASK', + 'GFX_IMU_TIMER1_VALUE__VALUE__SHIFT', + 'GFX_IMU_TIMER2_CMP0__VALUE_MASK', + 'GFX_IMU_TIMER2_CMP0__VALUE__SHIFT', + 'GFX_IMU_TIMER2_CMP1__VALUE_MASK', + 'GFX_IMU_TIMER2_CMP1__VALUE__SHIFT', + 'GFX_IMU_TIMER2_CMP3__VALUE_MASK', + 'GFX_IMU_TIMER2_CMP3__VALUE__SHIFT', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0_MASK', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0__SHIFT', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1_MASK', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1__SHIFT', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2_MASK', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2__SHIFT', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3_MASK', + 'GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3__SHIFT', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN0_MASK', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN0__SHIFT', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN1_MASK', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN1__SHIFT', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN2_MASK', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN2__SHIFT', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN3_MASK', + 'GFX_IMU_TIMER2_CMP_INTEN__INT_EN3__SHIFT', + 'GFX_IMU_TIMER2_CTRL0__CLEAR_MASK', + 'GFX_IMU_TIMER2_CTRL0__CLEAR__SHIFT', + 'GFX_IMU_TIMER2_CTRL0__PULSE_EN_MASK', + 'GFX_IMU_TIMER2_CTRL0__PULSE_EN__SHIFT', + 'GFX_IMU_TIMER2_CTRL0__START_STOP_MASK', + 'GFX_IMU_TIMER2_CTRL0__START_STOP__SHIFT', + 'GFX_IMU_TIMER2_CTRL0__UP_DOWN_MASK', + 'GFX_IMU_TIMER2_CTRL0__UP_DOWN__SHIFT', + 'GFX_IMU_TIMER2_CTRL1__PWM_EN_MASK', + 'GFX_IMU_TIMER2_CTRL1__PWM_EN__SHIFT', + 'GFX_IMU_TIMER2_CTRL1__SAT_EN_MASK', + 'GFX_IMU_TIMER2_CTRL1__SAT_EN__SHIFT', + 'GFX_IMU_TIMER2_CTRL1__TS_MODE_MASK', + 'GFX_IMU_TIMER2_CTRL1__TS_MODE__SHIFT', + 'GFX_IMU_TIMER2_VALUE__VALUE_MASK', + 'GFX_IMU_TIMER2_VALUE__VALUE__SHIFT', + 'GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn_MASK', + 'GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn__SHIFT', + 'GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn_MASK', + 'GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn__SHIFT', + 'GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET_MASK', + 'GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET__SHIFT', + 'GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET_MASK', + 'GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET__SHIFT', + 'GFX_IMU_VF_CTRL__QOS_MASK', 'GFX_IMU_VF_CTRL__QOS__SHIFT', + 'GFX_IMU_VF_CTRL__VFID_MASK', 'GFX_IMU_VF_CTRL__VFID__SHIFT', + 'GFX_IMU_VF_CTRL__VF_MASK', 'GFX_IMU_VF_CTRL__VF__SHIFT', + 'GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK', + 'GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT', + 'GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK', + 'GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT', + 'GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK', + 'GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT', + 'GFX_PIPE_CONTROL__RESERVED_MASK', + 'GFX_PIPE_CONTROL__RESERVED__SHIFT', + 'GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK', + 'GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT', + 'GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'GL1C_STATUS__GL2_DATA_VC0_STALL_MASK', + 'GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT', + 'GL1C_STATUS__GL2_DATA_VC1_STALL_MASK', + 'GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT', + 'GL1C_STATUS__GL2_REQ_VC0_STALL_MASK', + 'GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT', + 'GL1C_STATUS__GL2_REQ_VC1_STALL_MASK', + 'GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT', + 'GL1C_STATUS__GL2_RH_BUSY_MASK', + 'GL1C_STATUS__GL2_RH_BUSY__SHIFT', + 'GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK', + 'GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT', + 'GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK', + 'GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT', + 'GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK', + 'GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT', + 'GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK', + 'GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT', + 'GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK', + 'GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT', + 'GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK', + 'GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT', + 'GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK', + 'GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT', + 'GL1C_STATUS__TAG_ACK_STALL_MASK', + 'GL1C_STATUS__TAG_ACK_STALL__SHIFT', 'GL1C_STATUS__TAG_BUSY_MASK', + 'GL1C_STATUS__TAG_BUSY__SHIFT', 'GL1C_STATUS__TAG_EVICT_MASK', + 'GL1C_STATUS__TAG_EVICT__SHIFT', + 'GL1C_STATUS__TAG_GCR_INV_STALL_MASK', + 'GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT', + 'GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK', + 'GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT', + 'GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK', + 'GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT', + 'GL1C_STATUS__TAG_STALL_MASK', 'GL1C_STATUS__TAG_STALL__SHIFT', + 'GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK', + 'GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT', + 'GL1C_UTCL0_CNTL1__CLIENTID_MASK', + 'GL1C_UTCL0_CNTL1__CLIENTID__SHIFT', + 'GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK', + 'GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'GL1C_UTCL0_CNTL1__FORCE_IN_ORDER_MASK', + 'GL1C_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT', + 'GL1C_UTCL0_CNTL1__FORCE_MISS_MASK', + 'GL1C_UTCL0_CNTL1__FORCE_MISS__SHIFT', + 'GL1C_UTCL0_CNTL1__GPUVM_64K_DEF_MASK', + 'GL1C_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT', + 'GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK', + 'GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'GL1C_UTCL0_CNTL1__REG_INV_TOGGLE_MASK', + 'GL1C_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT', + 'GL1C_UTCL0_CNTL1__REG_INV_VMID_MASK', + 'GL1C_UTCL0_CNTL1__REG_INV_VMID__SHIFT', + 'GL1C_UTCL0_CNTL1__RESP_FAULT_MODE_MASK', + 'GL1C_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT', + 'GL1C_UTCL0_CNTL1__RESP_MODE_MASK', + 'GL1C_UTCL0_CNTL1__RESP_MODE__SHIFT', + 'GL1C_UTCL0_CNTL2__ANY_LINE_VALID_MASK', + 'GL1C_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT', + 'GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK', + 'GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT', + 'GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK', + 'GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT', + 'GL1C_UTCL0_CNTL2__DISABLE_BURST_MASK', + 'GL1C_UTCL0_CNTL2__DISABLE_BURST__SHIFT', + 'GL1C_UTCL0_CNTL2__FGCG_DISABLE_MASK', + 'GL1C_UTCL0_CNTL2__FGCG_DISABLE__SHIFT', + 'GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK', + 'GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT', + 'GL1C_UTCL0_CNTL2__FORCE_SNOOP_MASK', + 'GL1C_UTCL0_CNTL2__FORCE_SNOOP__SHIFT', + 'GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK', + 'GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'GL1C_UTCL0_CNTL2__SPARE_MASK', 'GL1C_UTCL0_CNTL2__SPARE__SHIFT', + 'GL1C_UTCL0_RETRY__COUNT_MASK', 'GL1C_UTCL0_RETRY__COUNT__SHIFT', + 'GL1C_UTCL0_RETRY__INCR_MASK', 'GL1C_UTCL0_RETRY__INCR__SHIFT', + 'GL1C_UTCL0_STATUS__FAULT_DETECTED_MASK', + 'GL1C_UTCL0_STATUS__FAULT_DETECTED__SHIFT', + 'GL1C_UTCL0_STATUS__PRT_DETECTED_MASK', + 'GL1C_UTCL0_STATUS__PRT_DETECTED__SHIFT', + 'GL1C_UTCL0_STATUS__RETRY_DETECTED_MASK', + 'GL1C_UTCL0_STATUS__RETRY_DETECTED__SHIFT', + 'GL1H_ARB_CTRL__CHICKEN_BITS_MASK', + 'GL1H_ARB_CTRL__CHICKEN_BITS__SHIFT', + 'GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK', + 'GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT', + 'GL1H_ARB_CTRL__REQ_FGCG_DISABLE_MASK', + 'GL1H_ARB_CTRL__REQ_FGCG_DISABLE__SHIFT', + 'GL1H_ARB_CTRL__RET_FGCG_DISABLE_MASK', + 'GL1H_ARB_CTRL__RET_FGCG_DISABLE__SHIFT', + 'GL1H_ARB_CTRL__SRC_FGCG_DISABLE_MASK', + 'GL1H_ARB_CTRL__SRC_FGCG_DISABLE__SHIFT', + 'GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ_MASK', + 'GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ__SHIFT', + 'GL1H_ARB_STATUS__REQ_ARB_BUSY_MASK', + 'GL1H_ARB_STATUS__REQ_ARB_BUSY__SHIFT', + 'GL1H_BURST_CTRL__BURST_DISABLE_MASK', + 'GL1H_BURST_CTRL__BURST_DISABLE__SHIFT', + 'GL1H_BURST_CTRL__MAX_BURST_SIZE_MASK', + 'GL1H_BURST_CTRL__MAX_BURST_SIZE__SHIFT', + 'GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS_MASK', + 'GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS__SHIFT', + 'GL1H_BURST_MASK__BURST_ADDR_MASK_MASK', + 'GL1H_BURST_MASK__BURST_ADDR_MASK__SHIFT', + 'GL1H_GL1_CREDITS__GL1_REQ_CREDITS_MASK', + 'GL1H_GL1_CREDITS__GL1_REQ_CREDITS__SHIFT', + 'GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__REG_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__REG_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__RET_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__RET_DCLK_OVERRIDE__SHIFT', + 'GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE_MASK', + 'GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE__SHIFT', + 'GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GL1H_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GL1H_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GL1H_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GL1H_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GL1H_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GL1H_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GL1H_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GL1H_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GL1H_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GL1H_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GL1H_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GL1H_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GL1H_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GL1H_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GL1H_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GL1H_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GL1H_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GL1H_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GL1H_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GL1H_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GL1H_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'GL1H_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'GL1H_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'GL1H_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE_MASK', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE__SHIFT', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE_MASK', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE__SHIFT', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE_MASK', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE__SHIFT', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE_MASK', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE__SHIFT', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE_MASK', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE__SHIFT', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE_MASK', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE__SHIFT', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE_MASK', + 'GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE__SHIFT', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE_MASK', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE__SHIFT', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE_MASK', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE__SHIFT', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE_MASK', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE__SHIFT', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE_MASK', + 'GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE__SHIFT', + 'GL1_ARB_STATUS__REQ_ARB_BUSY_MASK', + 'GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT', + 'GL1_ARB_STATUS__RET_ARB_BUSY_MASK', + 'GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT', + 'GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK', + 'GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT', + 'GL1_PIPE_STEER__PIPE0_MASK', 'GL1_PIPE_STEER__PIPE0__SHIFT', + 'GL1_PIPE_STEER__PIPE1_MASK', 'GL1_PIPE_STEER__PIPE1__SHIFT', + 'GL1_PIPE_STEER__PIPE2_MASK', 'GL1_PIPE_STEER__PIPE2__SHIFT', + 'GL1_PIPE_STEER__PIPE3_MASK', 'GL1_PIPE_STEER__PIPE3__SHIFT', + 'GL2A_ADDR_MATCH_CTRL__DISABLE_MASK', + 'GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT', + 'GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK', + 'GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT', + 'GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK', + 'GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT', + 'GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'GL2A_PRIORITY_CTRL__DISABLE_MASK', + 'GL2A_PRIORITY_CTRL__DISABLE__SHIFT', + 'GL2A_RESP_THROTTLE_CTRL__CREDIT_CH_MASK', + 'GL2A_RESP_THROTTLE_CTRL__CREDIT_CH__SHIFT', + 'GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1_MASK', + 'GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1__SHIFT', + 'GL2A_RESP_THROTTLE_CTRL__DISABLE_MASK', + 'GL2A_RESP_THROTTLE_CTRL__DISABLE__SHIFT', + 'GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK', + 'GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT', + 'GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK', + 'GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT', + 'GL2C_CM_CTRL1__BURST_MODE_MASK', + 'GL2C_CM_CTRL1__BURST_MODE__SHIFT', + 'GL2C_CM_CTRL1__BURST_TIMER_MASK', + 'GL2C_CM_CTRL1__BURST_TIMER__SHIFT', + 'GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK', + 'GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT', + 'GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK', + 'GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT', + 'GL2C_CM_CTRL1__MDC_ARB_MODE_MASK', + 'GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT', + 'GL2C_CM_CTRL1__READ_REQ_ONLY_MASK', + 'GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT', + 'GL2C_CM_CTRL1__RVF_SIZE_MASK', 'GL2C_CM_CTRL1__RVF_SIZE__SHIFT', + 'GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK', + 'GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT', + 'GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK', + 'GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT', + 'GL2C_CM_CTRL1__WRITE_COH_MODE_MASK', + 'GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT', + 'GL2C_CM_STALL__QUEUE_MASK', 'GL2C_CM_STALL__QUEUE__SHIFT', + 'GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK', + 'GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT', + 'GL2C_CTRL2__FILL_SIZE_32_MASK', + 'GL2C_CTRL2__FILL_SIZE_32__SHIFT', + 'GL2C_CTRL2__FILL_SIZE_64_MASK', + 'GL2C_CTRL2__FILL_SIZE_64__SHIFT', + 'GL2C_CTRL2__FORCE_MDC_INV_MASK', + 'GL2C_CTRL2__FORCE_MDC_INV__SHIFT', + 'GL2C_CTRL2__GCR_ALL_SET_MASK', 'GL2C_CTRL2__GCR_ALL_SET__SHIFT', + 'GL2C_CTRL2__GCR_ARB_CTRL_MASK', + 'GL2C_CTRL2__GCR_ARB_CTRL__SHIFT', + 'GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK', + 'GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT', + 'GL2C_CTRL2__MAX_MIN_CTRL_MASK', + 'GL2C_CTRL2__MAX_MIN_CTRL__SHIFT', + 'GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK', + 'GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT', + 'GL2C_CTRL2__METADATA_VOLATILE_EN_MASK', + 'GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT', + 'GL2C_CTRL2__PROBE_FIFO_SIZE_MASK', + 'GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT', + 'GL2C_CTRL2__PROBE_UNSHARED_EN_MASK', + 'GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT', + 'GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK', + 'GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT', + 'GL2C_CTRL2__RB_VOLATILE_EN_MASK', + 'GL2C_CTRL2__RB_VOLATILE_EN__SHIFT', + 'GL2C_CTRL2__RO_DISABLE_MASK', 'GL2C_CTRL2__RO_DISABLE__SHIFT', + 'GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK', + 'GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT', + 'GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK', + 'GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT', + 'GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK', + 'GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT', + 'GL2C_CTRL3__BANK_LINEAR_HASH_MODE_MASK', + 'GL2C_CTRL3__BANK_LINEAR_HASH_MODE__SHIFT', + 'GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK', + 'GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT', + 'GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE_MASK', + 'GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE__SHIFT', + 'GL2C_CTRL3__DGPU_SHARED_MODE_MASK', + 'GL2C_CTRL3__DGPU_SHARED_MODE__SHIFT', + 'GL2C_CTRL3__EA_GMI_DISABLE_MASK', + 'GL2C_CTRL3__EA_GMI_DISABLE__SHIFT', + 'GL2C_CTRL3__EA_READ_SIZE_LIMIT_MASK', + 'GL2C_CTRL3__EA_READ_SIZE_LIMIT__SHIFT', + 'GL2C_CTRL3__FGCG_OVERRIDE_MASK', + 'GL2C_CTRL3__FGCG_OVERRIDE__SHIFT', + 'GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK', + 'GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT', + 'GL2C_CTRL3__FORCE_MTYPE_UC_MASK', + 'GL2C_CTRL3__FORCE_MTYPE_UC__SHIFT', + 'GL2C_CTRL3__FORCE_READ_ON_WRITE_OP_MASK', + 'GL2C_CTRL3__FORCE_READ_ON_WRITE_OP__SHIFT', + 'GL2C_CTRL3__HASH_256B_ENABLE_MASK', + 'GL2C_CTRL3__HASH_256B_ENABLE__SHIFT', + 'GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK', + 'GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT', + 'GL2C_CTRL3__INF_NAN_CLAMP_MASK', + 'GL2C_CTRL3__INF_NAN_CLAMP__SHIFT', + 'GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK', + 'GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT', + 'GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK', + 'GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT', + 'GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK', + 'GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT', + 'GL2C_CTRL3__METADATA_NOFILL_MASK', + 'GL2C_CTRL3__METADATA_NOFILL__SHIFT', + 'GL2C_CTRL3__READ_BYPASS_AS_UC_MASK', + 'GL2C_CTRL3__READ_BYPASS_AS_UC__SHIFT', + 'GL2C_CTRL3__SCRATCH_MASK', 'GL2C_CTRL3__SCRATCH__SHIFT', + 'GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE_MASK', + 'GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE__SHIFT', + 'GL2C_CTRL3__SQC_TO_HI_PRIORITY_MASK', + 'GL2C_CTRL3__SQC_TO_HI_PRIORITY__SHIFT', + 'GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK', + 'GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT', + 'GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT_MASK', + 'GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT__SHIFT', + 'GL2C_CTRL3__WB_OPT_ENABLE_MASK', + 'GL2C_CTRL3__WB_OPT_ENABLE__SHIFT', + 'GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN_MASK', + 'GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN__SHIFT', + 'GL2C_CTRL4__CM_MGCG_MODE_MASK', + 'GL2C_CTRL4__CM_MGCG_MODE__SHIFT', + 'GL2C_CTRL4__CORE_MGCG_MODE_MASK', + 'GL2C_CTRL4__CORE_MGCG_MODE__SHIFT', + 'GL2C_CTRL4__EA_NACK_DISABLE_MASK', + 'GL2C_CTRL4__EA_NACK_DISABLE__SHIFT', + 'GL2C_CTRL4__EXECUTE_MGCG_MODE_MASK', + 'GL2C_CTRL4__EXECUTE_MGCG_MODE__SHIFT', + 'GL2C_CTRL4__MDC_MGCG_MODE_MASK', + 'GL2C_CTRL4__MDC_MGCG_MODE__SHIFT', + 'GL2C_CTRL4__METADATA_WR_OP_CID_MASK', + 'GL2C_CTRL4__METADATA_WR_OP_CID__SHIFT', + 'GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE_MASK', + 'GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE__SHIFT', + 'GL2C_CTRL4__SPA_CHANNEL_ENABLE_MASK', + 'GL2C_CTRL4__SPA_CHANNEL_ENABLE__SHIFT', + 'GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY_MASK', + 'GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY__SHIFT', + 'GL2C_CTRL4__TAG_MGCG_MODE_MASK', + 'GL2C_CTRL4__TAG_MGCG_MODE__SHIFT', + 'GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE_MASK', + 'GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE__SHIFT', + 'GL2C_CTRL__CACHE_SIZE_MASK', 'GL2C_CTRL__CACHE_SIZE__SHIFT', + 'GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK', + 'GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT', + 'GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK', + 'GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT', + 'GL2C_CTRL__LATENCY_FIFO_SIZE_MASK', + 'GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT', + 'GL2C_CTRL__LINEAR_SET_HASH_MASK', + 'GL2C_CTRL__LINEAR_SET_HASH__SHIFT', + 'GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK', + 'GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT', + 'GL2C_CTRL__MDC_SIZE_MASK', 'GL2C_CTRL__MDC_SIZE__SHIFT', + 'GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK', + 'GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT', + 'GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK', + 'GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT', + 'GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK', + 'GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT', + 'GL2C_CTRL__RATE_MASK', 'GL2C_CTRL__RATE__SHIFT', + 'GL2C_CTRL__SRC_FIFO_SIZE_MASK', + 'GL2C_CTRL__SRC_FIFO_SIZE__SHIFT', + 'GL2C_CTRL__WRITEBACK_MARGIN_MASK', + 'GL2C_CTRL__WRITEBACK_MARGIN__SHIFT', + 'GL2C_DISCARD_STALL_CTRL__DROP_NEXT_MASK', + 'GL2C_DISCARD_STALL_CTRL__DROP_NEXT__SHIFT', + 'GL2C_DISCARD_STALL_CTRL__ENABLE_MASK', + 'GL2C_DISCARD_STALL_CTRL__ENABLE__SHIFT', + 'GL2C_DISCARD_STALL_CTRL__LIMIT_MASK', + 'GL2C_DISCARD_STALL_CTRL__LIMIT__SHIFT', + 'GL2C_DISCARD_STALL_CTRL__WINDOW_MASK', + 'GL2C_DISCARD_STALL_CTRL__WINDOW__SHIFT', + 'GL2C_LB_CTR_CTRL__CLEAR_MASK', 'GL2C_LB_CTR_CTRL__CLEAR__SHIFT', + 'GL2C_LB_CTR_CTRL__LOAD_MASK', 'GL2C_LB_CTR_CTRL__LOAD__SHIFT', + 'GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK', + 'GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT', + 'GL2C_LB_CTR_CTRL__START_MASK', 'GL2C_LB_CTR_CTRL__START__SHIFT', + 'GL2C_LB_CTR_SEL0__DIV0_MASK', 'GL2C_LB_CTR_SEL0__DIV0__SHIFT', + 'GL2C_LB_CTR_SEL0__DIV1_MASK', 'GL2C_LB_CTR_SEL0__DIV1__SHIFT', + 'GL2C_LB_CTR_SEL0__SEL0_MASK', 'GL2C_LB_CTR_SEL0__SEL0__SHIFT', + 'GL2C_LB_CTR_SEL0__SEL1_MASK', 'GL2C_LB_CTR_SEL0__SEL1__SHIFT', + 'GL2C_LB_CTR_SEL1__DIV2_MASK', 'GL2C_LB_CTR_SEL1__DIV2__SHIFT', + 'GL2C_LB_CTR_SEL1__DIV3_MASK', 'GL2C_LB_CTR_SEL1__DIV3__SHIFT', + 'GL2C_LB_CTR_SEL1__SEL2_MASK', 'GL2C_LB_CTR_SEL1__SEL2__SHIFT', + 'GL2C_LB_CTR_SEL1__SEL3_MASK', 'GL2C_LB_CTR_SEL1__SEL3__SHIFT', + 'GL2C_LB_DATA0__DATA_MASK', 'GL2C_LB_DATA0__DATA__SHIFT', + 'GL2C_LB_DATA1__DATA_MASK', 'GL2C_LB_DATA1__DATA__SHIFT', + 'GL2C_LB_DATA2__DATA_MASK', 'GL2C_LB_DATA2__DATA__SHIFT', + 'GL2C_LB_DATA3__DATA_MASK', 'GL2C_LB_DATA3__DATA__SHIFT', + 'GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'GL2C_SOFT_RESET__HALT_FOR_RESET_MASK', + 'GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT', + 'GL2C_WBINVL2__DONE_MASK', 'GL2C_WBINVL2__DONE__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0_MASK', + 'GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0__SHIFT', + 'GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1_MASK', + 'GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2_MASK', + 'GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2__SHIFT', + 'GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3_MASK', + 'GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3__SHIFT', + 'GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK', + 'GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT', + 'GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK', + 'GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT', + 'GRBM_CAM_DATA__CAM_ADDR_MASK', 'GRBM_CAM_DATA__CAM_ADDR__SHIFT', + 'GRBM_CAM_DATA__CAM_REMAPADDR_MASK', + 'GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT', + 'GRBM_CAM_INDEX__CAM_INDEX_MASK', + 'GRBM_CAM_INDEX__CAM_INDEX__SHIFT', + 'GRBM_CHIP_REVISION__CHIP_REVISION_MASK', + 'GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT', + 'GRBM_CNTL__READ_TIMEOUT_MASK', 'GRBM_CNTL__READ_TIMEOUT__SHIFT', + 'GRBM_CNTL__REPORT_LAST_RDERR_MASK', + 'GRBM_CNTL__REPORT_LAST_RDERR__SHIFT', + 'GRBM_DSM_BYPASS__BYPASS_BITS_MASK', + 'GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT', + 'GRBM_DSM_BYPASS__BYPASS_EN_MASK', + 'GRBM_DSM_BYPASS__BYPASS_EN__SHIFT', + 'GRBM_FENCE_RANGE0__END_MASK', 'GRBM_FENCE_RANGE0__END__SHIFT', + 'GRBM_FENCE_RANGE0__START_MASK', + 'GRBM_FENCE_RANGE0__START__SHIFT', 'GRBM_FENCE_RANGE1__END_MASK', + 'GRBM_FENCE_RANGE1__END__SHIFT', 'GRBM_FENCE_RANGE1__START_MASK', + 'GRBM_FENCE_RANGE1__START__SHIFT', + 'GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK', + 'GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT', + 'GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK', + 'GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__MEID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__VMID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT', + 'GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK', + 'GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT', + 'GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK', + 'GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT', + 'GRBM_GFX_CNTL__CTXID_MASK', 'GRBM_GFX_CNTL__CTXID__SHIFT', + 'GRBM_GFX_CNTL__MEID_MASK', 'GRBM_GFX_CNTL__MEID__SHIFT', + 'GRBM_GFX_CNTL__PIPEID_MASK', 'GRBM_GFX_CNTL__PIPEID__SHIFT', + 'GRBM_GFX_CNTL__QUEUEID_MASK', 'GRBM_GFX_CNTL__QUEUEID__SHIFT', + 'GRBM_GFX_CNTL__VMID_MASK', 'GRBM_GFX_CNTL__VMID__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK', + 'GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK', + 'GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT', + 'GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX__INSTANCE_INDEX_MASK', + 'GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT', + 'GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX__SA_INDEX_MASK', + 'GRBM_GFX_INDEX__SA_INDEX__SHIFT', + 'GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX__SE_INDEX_MASK', + 'GRBM_GFX_INDEX__SE_INDEX__SHIFT', + 'GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK', + 'GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT', + 'GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK', + 'GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT', + 'GRBM_HYP_CAM_DATA__CAM_ADDR_MASK', + 'GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT', + 'GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK', + 'GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT', + 'GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK', + 'GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT', + 'GRBM_IH_CREDIT__CREDIT_VALUE_MASK', + 'GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT', + 'GRBM_IH_CREDIT__IH_CLIENT_ID_MASK', + 'GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT', + 'GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK', + 'GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT', + 'GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK', + 'GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT', + 'GRBM_INVALID_PIPE__ADDR_MASK', 'GRBM_INVALID_PIPE__ADDR__SHIFT', + 'GRBM_INVALID_PIPE__INVALID_PIPE_MASK', + 'GRBM_INVALID_PIPE__INVALID_PIPE__SHIFT', + 'GRBM_INVALID_PIPE__MEID_MASK', 'GRBM_INVALID_PIPE__MEID__SHIFT', + 'GRBM_INVALID_PIPE__PIPEID_MASK', + 'GRBM_INVALID_PIPE__PIPEID__SHIFT', + 'GRBM_INVALID_PIPE__QUEUEID_MASK', + 'GRBM_INVALID_PIPE__QUEUEID__SHIFT', + 'GRBM_INVALID_PIPE__SSRCID_MASK', + 'GRBM_INVALID_PIPE__SSRCID__SHIFT', 'GRBM_NOWHERE__DATA_MASK', + 'GRBM_NOWHERE__DATA__SHIFT', + 'GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK', + 'GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT', + 'GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK', + 'GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT', + 'GRBM_PWR_CNTL__ALL_REQ_EN_MASK', + 'GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT', + 'GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK', + 'GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT', + 'GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK', + 'GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT', + 'GRBM_PWR_CNTL__GFX_REQ_EN_MASK', + 'GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT', + 'GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK', + 'GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT', + 'GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK', + 'GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT', + 'GRBM_READ_ERROR__READ_ADDRESS_MASK', + 'GRBM_READ_ERROR__READ_ADDRESS__SHIFT', + 'GRBM_READ_ERROR__READ_ERROR_MASK', + 'GRBM_READ_ERROR__READ_ERROR__SHIFT', + 'GRBM_READ_ERROR__READ_MEID_MASK', + 'GRBM_READ_ERROR__READ_MEID__SHIFT', + 'GRBM_READ_ERROR__READ_PIPEID_MASK', + 'GRBM_READ_ERROR__READ_PIPEID__SHIFT', + 'GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK', + 'GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT', + 'GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK', + 'GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT', + 'GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK', + 'GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT', + 'GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK', + 'GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT', + 'GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK', + 'GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT', + 'GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK', + 'GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT', + 'GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK', + 'GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT', + 'GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK', + 'GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT', + 'GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE4_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE4_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE4_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE4_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE4_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE5_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE5_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE5_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE5_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE5_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE6_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE6_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE6_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE6_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE6_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK', + 'GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT', + 'GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK', + 'GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT', + 'GRBM_SKEW_CNTL__SKEW_COUNT_MASK', + 'GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT', + 'GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK', + 'GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CP_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_EA_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT', + 'GRBM_STATUS2__CPC_BUSY_MASK', 'GRBM_STATUS2__CPC_BUSY__SHIFT', + 'GRBM_STATUS2__CPF_BUSY_MASK', 'GRBM_STATUS2__CPF_BUSY__SHIFT', + 'GRBM_STATUS2__CPG_BUSY_MASK', 'GRBM_STATUS2__CPG_BUSY__SHIFT', + 'GRBM_STATUS2__EA_BUSY_MASK', 'GRBM_STATUS2__EA_BUSY__SHIFT', + 'GRBM_STATUS2__EA_LINK_BUSY_MASK', + 'GRBM_STATUS2__EA_LINK_BUSY__SHIFT', + 'GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK', + 'GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT', + 'GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__RLC_BUSY_MASK', 'GRBM_STATUS2__RLC_BUSY__SHIFT', + 'GRBM_STATUS2__RLC_RQ_PENDING_MASK', + 'GRBM_STATUS2__RLC_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__RMI_BUSY_MASK', 'GRBM_STATUS2__RMI_BUSY__SHIFT', + 'GRBM_STATUS2__SDMA0_RQ_PENDING_MASK', + 'GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__SDMA1_RQ_PENDING_MASK', + 'GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__SDMA_BUSY_MASK', 'GRBM_STATUS2__SDMA_BUSY__SHIFT', + 'GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK', + 'GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__TCP_BUSY_MASK', 'GRBM_STATUS2__TCP_BUSY__SHIFT', + 'GRBM_STATUS2__UTCL2_BUSY_MASK', + 'GRBM_STATUS2__UTCL2_BUSY__SHIFT', + 'GRBM_STATUS2__UTCL2_RQ_PENDING_MASK', + 'GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT', + 'GRBM_STATUS3__CH_BUSY_MASK', 'GRBM_STATUS3__CH_BUSY__SHIFT', + 'GRBM_STATUS3__GL1CC_BUSY_MASK', + 'GRBM_STATUS3__GL1CC_BUSY__SHIFT', 'GRBM_STATUS3__GL1H_BUSY_MASK', + 'GRBM_STATUS3__GL1H_BUSY__SHIFT', 'GRBM_STATUS3__GL2CC_BUSY_MASK', + 'GRBM_STATUS3__GL2CC_BUSY__SHIFT', + 'GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK', + 'GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT', + 'GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK', + 'GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT', + 'GRBM_STATUS3__GUS_BUSY_MASK', 'GRBM_STATUS3__GUS_BUSY__SHIFT', + 'GRBM_STATUS3__GUS_LINK_BUSY_MASK', + 'GRBM_STATUS3__GUS_LINK_BUSY__SHIFT', + 'GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK', + 'GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT', + 'GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK', + 'GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT', + 'GRBM_STATUS3__PC_BUSY_MASK', 'GRBM_STATUS3__PC_BUSY__SHIFT', + 'GRBM_STATUS3__PH_BUSY_MASK', 'GRBM_STATUS3__PH_BUSY__SHIFT', + 'GRBM_STATUS3__PMM_BUSY_MASK', 'GRBM_STATUS3__PMM_BUSY__SHIFT', + 'GRBM_STATUS3__SEDC_BUSY_MASK', 'GRBM_STATUS3__SEDC_BUSY__SHIFT', + 'GRBM_STATUS3__UTCL1_BUSY_MASK', + 'GRBM_STATUS3__UTCL1_BUSY__SHIFT', + 'GRBM_STATUS_SE0__BCI_BUSY_MASK', + 'GRBM_STATUS_SE0__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE0__CB_BUSY_MASK', + 'GRBM_STATUS_SE0__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE0__CB_CLEAN_MASK', + 'GRBM_STATUS_SE0__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE0__DB_BUSY_MASK', + 'GRBM_STATUS_SE0__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE0__DB_CLEAN_MASK', + 'GRBM_STATUS_SE0__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE0__GL1CC_BUSY_MASK', + 'GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT', + 'GRBM_STATUS_SE0__GL1H_BUSY_MASK', + 'GRBM_STATUS_SE0__GL1H_BUSY__SHIFT', + 'GRBM_STATUS_SE0__PA_BUSY_MASK', + 'GRBM_STATUS_SE0__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE0__PC_BUSY_MASK', + 'GRBM_STATUS_SE0__PC_BUSY__SHIFT', + 'GRBM_STATUS_SE0__RMI_BUSY_MASK', + 'GRBM_STATUS_SE0__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE0__SC_BUSY_MASK', + 'GRBM_STATUS_SE0__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE0__SEDC_BUSY_MASK', + 'GRBM_STATUS_SE0__SEDC_BUSY__SHIFT', + 'GRBM_STATUS_SE0__SPI_BUSY_MASK', + 'GRBM_STATUS_SE0__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE0__SX_BUSY_MASK', + 'GRBM_STATUS_SE0__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE0__TA_BUSY_MASK', + 'GRBM_STATUS_SE0__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE0__TCP_BUSY_MASK', + 'GRBM_STATUS_SE0__TCP_BUSY__SHIFT', + 'GRBM_STATUS_SE0__UTCL1_BUSY_MASK', + 'GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT', + 'GRBM_STATUS_SE1__BCI_BUSY_MASK', + 'GRBM_STATUS_SE1__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE1__CB_BUSY_MASK', + 'GRBM_STATUS_SE1__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE1__CB_CLEAN_MASK', + 'GRBM_STATUS_SE1__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE1__DB_BUSY_MASK', + 'GRBM_STATUS_SE1__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE1__DB_CLEAN_MASK', + 'GRBM_STATUS_SE1__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE1__GL1CC_BUSY_MASK', + 'GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT', + 'GRBM_STATUS_SE1__GL1H_BUSY_MASK', + 'GRBM_STATUS_SE1__GL1H_BUSY__SHIFT', + 'GRBM_STATUS_SE1__PA_BUSY_MASK', + 'GRBM_STATUS_SE1__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE1__PC_BUSY_MASK', + 'GRBM_STATUS_SE1__PC_BUSY__SHIFT', + 'GRBM_STATUS_SE1__RMI_BUSY_MASK', + 'GRBM_STATUS_SE1__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE1__SC_BUSY_MASK', + 'GRBM_STATUS_SE1__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE1__SEDC_BUSY_MASK', + 'GRBM_STATUS_SE1__SEDC_BUSY__SHIFT', + 'GRBM_STATUS_SE1__SPI_BUSY_MASK', + 'GRBM_STATUS_SE1__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE1__SX_BUSY_MASK', + 'GRBM_STATUS_SE1__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE1__TA_BUSY_MASK', + 'GRBM_STATUS_SE1__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE1__TCP_BUSY_MASK', + 'GRBM_STATUS_SE1__TCP_BUSY__SHIFT', + 'GRBM_STATUS_SE1__UTCL1_BUSY_MASK', + 'GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT', + 'GRBM_STATUS_SE2__BCI_BUSY_MASK', + 'GRBM_STATUS_SE2__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE2__CB_BUSY_MASK', + 'GRBM_STATUS_SE2__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE2__CB_CLEAN_MASK', + 'GRBM_STATUS_SE2__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE2__DB_BUSY_MASK', + 'GRBM_STATUS_SE2__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE2__DB_CLEAN_MASK', + 'GRBM_STATUS_SE2__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE2__GL1CC_BUSY_MASK', + 'GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT', + 'GRBM_STATUS_SE2__GL1H_BUSY_MASK', + 'GRBM_STATUS_SE2__GL1H_BUSY__SHIFT', + 'GRBM_STATUS_SE2__PA_BUSY_MASK', + 'GRBM_STATUS_SE2__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE2__PC_BUSY_MASK', + 'GRBM_STATUS_SE2__PC_BUSY__SHIFT', + 'GRBM_STATUS_SE2__RMI_BUSY_MASK', + 'GRBM_STATUS_SE2__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE2__SC_BUSY_MASK', + 'GRBM_STATUS_SE2__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE2__SEDC_BUSY_MASK', + 'GRBM_STATUS_SE2__SEDC_BUSY__SHIFT', + 'GRBM_STATUS_SE2__SPI_BUSY_MASK', + 'GRBM_STATUS_SE2__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE2__SX_BUSY_MASK', + 'GRBM_STATUS_SE2__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE2__TA_BUSY_MASK', + 'GRBM_STATUS_SE2__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE2__TCP_BUSY_MASK', + 'GRBM_STATUS_SE2__TCP_BUSY__SHIFT', + 'GRBM_STATUS_SE2__UTCL1_BUSY_MASK', + 'GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT', + 'GRBM_STATUS_SE3__BCI_BUSY_MASK', + 'GRBM_STATUS_SE3__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE3__CB_BUSY_MASK', + 'GRBM_STATUS_SE3__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE3__CB_CLEAN_MASK', + 'GRBM_STATUS_SE3__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE3__DB_BUSY_MASK', + 'GRBM_STATUS_SE3__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE3__DB_CLEAN_MASK', + 'GRBM_STATUS_SE3__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE3__GL1CC_BUSY_MASK', + 'GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT', + 'GRBM_STATUS_SE3__GL1H_BUSY_MASK', + 'GRBM_STATUS_SE3__GL1H_BUSY__SHIFT', + 'GRBM_STATUS_SE3__PA_BUSY_MASK', + 'GRBM_STATUS_SE3__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE3__PC_BUSY_MASK', + 'GRBM_STATUS_SE3__PC_BUSY__SHIFT', + 'GRBM_STATUS_SE3__RMI_BUSY_MASK', + 'GRBM_STATUS_SE3__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE3__SC_BUSY_MASK', + 'GRBM_STATUS_SE3__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE3__SEDC_BUSY_MASK', + 'GRBM_STATUS_SE3__SEDC_BUSY__SHIFT', + 'GRBM_STATUS_SE3__SPI_BUSY_MASK', + 'GRBM_STATUS_SE3__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE3__SX_BUSY_MASK', + 'GRBM_STATUS_SE3__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE3__TA_BUSY_MASK', + 'GRBM_STATUS_SE3__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE3__TCP_BUSY_MASK', + 'GRBM_STATUS_SE3__TCP_BUSY__SHIFT', + 'GRBM_STATUS_SE3__UTCL1_BUSY_MASK', + 'GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT', + 'GRBM_STATUS_SE4__BCI_BUSY_MASK', + 'GRBM_STATUS_SE4__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE4__CB_BUSY_MASK', + 'GRBM_STATUS_SE4__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE4__CB_CLEAN_MASK', + 'GRBM_STATUS_SE4__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE4__DB_BUSY_MASK', + 'GRBM_STATUS_SE4__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE4__DB_CLEAN_MASK', + 'GRBM_STATUS_SE4__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE4__GL1CC_BUSY_MASK', + 'GRBM_STATUS_SE4__GL1CC_BUSY__SHIFT', + 'GRBM_STATUS_SE4__GL1H_BUSY_MASK', + 'GRBM_STATUS_SE4__GL1H_BUSY__SHIFT', + 'GRBM_STATUS_SE4__PA_BUSY_MASK', + 'GRBM_STATUS_SE4__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE4__PC_BUSY_MASK', + 'GRBM_STATUS_SE4__PC_BUSY__SHIFT', + 'GRBM_STATUS_SE4__RMI_BUSY_MASK', + 'GRBM_STATUS_SE4__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE4__SC_BUSY_MASK', + 'GRBM_STATUS_SE4__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE4__SEDC_BUSY_MASK', + 'GRBM_STATUS_SE4__SEDC_BUSY__SHIFT', + 'GRBM_STATUS_SE4__SPI_BUSY_MASK', + 'GRBM_STATUS_SE4__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE4__SX_BUSY_MASK', + 'GRBM_STATUS_SE4__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE4__TA_BUSY_MASK', + 'GRBM_STATUS_SE4__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE4__TCP_BUSY_MASK', + 'GRBM_STATUS_SE4__TCP_BUSY__SHIFT', + 'GRBM_STATUS_SE4__UTCL1_BUSY_MASK', + 'GRBM_STATUS_SE4__UTCL1_BUSY__SHIFT', + 'GRBM_STATUS_SE5__BCI_BUSY_MASK', + 'GRBM_STATUS_SE5__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE5__CB_BUSY_MASK', + 'GRBM_STATUS_SE5__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE5__CB_CLEAN_MASK', + 'GRBM_STATUS_SE5__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE5__DB_BUSY_MASK', + 'GRBM_STATUS_SE5__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE5__DB_CLEAN_MASK', + 'GRBM_STATUS_SE5__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE5__GL1CC_BUSY_MASK', + 'GRBM_STATUS_SE5__GL1CC_BUSY__SHIFT', + 'GRBM_STATUS_SE5__GL1H_BUSY_MASK', + 'GRBM_STATUS_SE5__GL1H_BUSY__SHIFT', + 'GRBM_STATUS_SE5__PA_BUSY_MASK', + 'GRBM_STATUS_SE5__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE5__PC_BUSY_MASK', + 'GRBM_STATUS_SE5__PC_BUSY__SHIFT', + 'GRBM_STATUS_SE5__RMI_BUSY_MASK', + 'GRBM_STATUS_SE5__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE5__SC_BUSY_MASK', + 'GRBM_STATUS_SE5__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE5__SEDC_BUSY_MASK', + 'GRBM_STATUS_SE5__SEDC_BUSY__SHIFT', + 'GRBM_STATUS_SE5__SPI_BUSY_MASK', + 'GRBM_STATUS_SE5__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE5__SX_BUSY_MASK', + 'GRBM_STATUS_SE5__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE5__TA_BUSY_MASK', + 'GRBM_STATUS_SE5__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE5__TCP_BUSY_MASK', + 'GRBM_STATUS_SE5__TCP_BUSY__SHIFT', + 'GRBM_STATUS_SE5__UTCL1_BUSY_MASK', + 'GRBM_STATUS_SE5__UTCL1_BUSY__SHIFT', + 'GRBM_STATUS__ANY_ACTIVE_MASK', 'GRBM_STATUS__ANY_ACTIVE__SHIFT', + 'GRBM_STATUS__BCI_BUSY_MASK', 'GRBM_STATUS__BCI_BUSY__SHIFT', + 'GRBM_STATUS__CB_BUSY_MASK', 'GRBM_STATUS__CB_BUSY__SHIFT', + 'GRBM_STATUS__CB_CLEAN_MASK', 'GRBM_STATUS__CB_CLEAN__SHIFT', + 'GRBM_STATUS__CP_BUSY_MASK', 'GRBM_STATUS__CP_BUSY__SHIFT', + 'GRBM_STATUS__CP_COHERENCY_BUSY_MASK', + 'GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT', + 'GRBM_STATUS__DB_BUSY_MASK', 'GRBM_STATUS__DB_BUSY__SHIFT', + 'GRBM_STATUS__DB_CLEAN_MASK', 'GRBM_STATUS__DB_CLEAN__SHIFT', + 'GRBM_STATUS__GDS_BUSY_MASK', 'GRBM_STATUS__GDS_BUSY__SHIFT', + 'GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK', + 'GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT', + 'GRBM_STATUS__GE_BUSY_MASK', 'GRBM_STATUS__GE_BUSY_NO_DMA_MASK', + 'GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT', + 'GRBM_STATUS__GE_BUSY__SHIFT', 'GRBM_STATUS__GUI_ACTIVE_MASK', + 'GRBM_STATUS__GUI_ACTIVE__SHIFT', + 'GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK', + 'GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT', + 'GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK', + 'GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT', + 'GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK', + 'GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT', + 'GRBM_STATUS__PA_BUSY_MASK', 'GRBM_STATUS__PA_BUSY__SHIFT', + 'GRBM_STATUS__SC_BUSY_MASK', 'GRBM_STATUS__SC_BUSY__SHIFT', + 'GRBM_STATUS__SDMA_RQ_PENDING_MASK', + 'GRBM_STATUS__SDMA_RQ_PENDING__SHIFT', + 'GRBM_STATUS__SPI_BUSY_MASK', 'GRBM_STATUS__SPI_BUSY__SHIFT', + 'GRBM_STATUS__SX_BUSY_MASK', 'GRBM_STATUS__SX_BUSY__SHIFT', + 'GRBM_STATUS__TA_BUSY_MASK', 'GRBM_STATUS__TA_BUSY__SHIFT', + 'GRBM_TRAP_ADDR_MSK__DATA_MASK', + 'GRBM_TRAP_ADDR_MSK__DATA__SHIFT', 'GRBM_TRAP_ADDR__DATA_MASK', + 'GRBM_TRAP_ADDR__DATA__SHIFT', 'GRBM_TRAP_OP__RW_MASK', + 'GRBM_TRAP_OP__RW__SHIFT', 'GRBM_TRAP_WD_MSK__DATA_MASK', + 'GRBM_TRAP_WD_MSK__DATA__SHIFT', 'GRBM_TRAP_WD__DATA_MASK', + 'GRBM_TRAP_WD__DATA__SHIFT', + 'GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK', + 'GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT', + 'GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK', + 'GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT', + 'GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK', + 'GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT', + 'GRBM_WRITE_ERROR__TMZ_MASK', 'GRBM_WRITE_ERROR__TMZ__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_ERROR_MASK', + 'GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_MEID_MASK', + 'GRBM_WRITE_ERROR__WRITE_MEID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_PIPEID_MASK', + 'GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK', + 'GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_SSRCID_MASK', + 'GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_VFID_MASK', + 'GRBM_WRITE_ERROR__WRITE_VFID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_VF_MASK', + 'GRBM_WRITE_ERROR__WRITE_VF__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_VMID_MASK', + 'GRBM_WRITE_ERROR__WRITE_VMID__SHIFT', + 'GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK', + 'GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT', + 'GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK', + 'GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT', + 'GRTAVFS_CLK_CNTL__RESERVED_MASK', + 'GRTAVFS_CLK_CNTL__RESERVED__SHIFT', + 'GRTAVFS_GENERAL_0__DATA_MASK', 'GRTAVFS_GENERAL_0__DATA__SHIFT', + 'GRTAVFS_PSM_CNTL__PSM_COUNT_MASK', + 'GRTAVFS_PSM_CNTL__PSM_COUNT__SHIFT', + 'GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN_MASK', + 'GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN__SHIFT', + 'GRTAVFS_PSM_CNTL__RESERVED_MASK', + 'GRTAVFS_PSM_CNTL__RESERVED__SHIFT', + 'GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA_MASK', + 'GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT', + 'GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK', + 'GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT', + 'GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN_MASK', + 'GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT', + 'GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN_MASK', + 'GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT', + 'GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK', + 'GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT', + 'GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK', + 'GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT', + 'GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK', + 'GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT', + 'GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK', + 'GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT', + 'GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK', + 'GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT', + 'GRTAVFS_SE_CLK_CNTL__RESERVED_MASK', + 'GRTAVFS_SE_CLK_CNTL__RESERVED__SHIFT', + 'GRTAVFS_SE_GENERAL_0__DATA_MASK', + 'GRTAVFS_SE_GENERAL_0__DATA__SHIFT', + 'GRTAVFS_SE_PSM_CNTL__PSM_COUNT_MASK', + 'GRTAVFS_SE_PSM_CNTL__PSM_COUNT__SHIFT', + 'GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN_MASK', + 'GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN__SHIFT', + 'GRTAVFS_SE_PSM_CNTL__RESERVED_MASK', + 'GRTAVFS_SE_PSM_CNTL__RESERVED__SHIFT', + 'GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA_MASK', + 'GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT', + 'GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR_MASK', + 'GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT', + 'GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN_MASK', + 'GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT', + 'GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN_MASK', + 'GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT', + 'GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK', + 'GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT', + 'GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK', + 'GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT', + 'GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA_MASK', + 'GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT', + 'GRTAVFS_SE_SOFT_RESET__RESERVED_MASK', + 'GRTAVFS_SE_SOFT_RESET__RESERVED__SHIFT', + 'GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE_MASK', + 'GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE__SHIFT', + 'GRTAVFS_SE_TARG_FREQ__REQUEST_MASK', + 'GRTAVFS_SE_TARG_FREQ__REQUEST__SHIFT', + 'GRTAVFS_SE_TARG_FREQ__RESERVED_MASK', + 'GRTAVFS_SE_TARG_FREQ__RESERVED__SHIFT', + 'GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY_MASK', + 'GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY__SHIFT', + 'GRTAVFS_SE_TARG_VOLT__RESERVED_MASK', + 'GRTAVFS_SE_TARG_VOLT__RESERVED__SHIFT', + 'GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE_MASK', + 'GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE__SHIFT', + 'GRTAVFS_SE_TARG_VOLT__VALID_MASK', + 'GRTAVFS_SE_TARG_VOLT__VALID__SHIFT', + 'GRTAVFS_SOFT_RESET__RESERVED_MASK', + 'GRTAVFS_SOFT_RESET__RESERVED__SHIFT', + 'GRTAVFS_SOFT_RESET__RESETN_OVERRIDE_MASK', + 'GRTAVFS_SOFT_RESET__RESETN_OVERRIDE__SHIFT', + 'GRTAVFS_TARG_FREQ__REQUEST_MASK', + 'GRTAVFS_TARG_FREQ__REQUEST__SHIFT', + 'GRTAVFS_TARG_FREQ__RESERVED_MASK', + 'GRTAVFS_TARG_FREQ__RESERVED__SHIFT', + 'GRTAVFS_TARG_FREQ__TARGET_FREQUENCY_MASK', + 'GRTAVFS_TARG_FREQ__TARGET_FREQUENCY__SHIFT', + 'GRTAVFS_TARG_VOLT__RESERVED_MASK', + 'GRTAVFS_TARG_VOLT__RESERVED__SHIFT', + 'GRTAVFS_TARG_VOLT__TARGET_VOLTAGE_MASK', + 'GRTAVFS_TARG_VOLT__TARGET_VOLTAGE__SHIFT', + 'GRTAVFS_TARG_VOLT__VALID_MASK', + 'GRTAVFS_TARG_VOLT__VALID__SHIFT', + 'GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK', + 'GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK', + 'GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK', + 'GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK', + 'GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK', + 'GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK', + 'GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK', + 'GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT', + 'GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK', + 'GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT', + 'GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK', + 'GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK', + 'GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT', + 'GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK', + 'GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT', + 'GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK', + 'GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT', + 'GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK', + 'GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT', + 'GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK', + 'GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT', + 'GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK', + 'GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT', + 'GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK', + 'GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT', + 'GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK', + 'GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK', + 'GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT', + 'GUS_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'GUS_ERR_STATUS__FUE_FLAG_MASK', + 'GUS_ERR_STATUS__FUE_FLAG__SHIFT', + 'GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK', + 'GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT', + 'GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK', + 'GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT', + 'GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK', + 'GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT', + 'GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK', + 'GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_READ_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC__SHIFT', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK', + 'GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT', + 'GUS_ICG_CTRL__SPARE1_MASK', 'GUS_ICG_CTRL__SPARE1__SHIFT', + 'GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK', + 'GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT', + 'GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK', + 'GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT', + 'GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK', + 'GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT', + 'GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK', + 'GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT', + 'GUS_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK', + 'GUS_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK', + 'GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK', + 'GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT', + 'GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK', + 'GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK', + 'GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT', + 'GUS_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK', + 'GUS_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK', + 'GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK', + 'GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT', + 'GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK', + 'GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT', + 'GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK', + 'GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK', + 'GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT', + 'GUS_L1_CH0_CMD_IN__COUNT_MASK', + 'GUS_L1_CH0_CMD_IN__COUNT__SHIFT', + 'GUS_L1_CH0_CMD_OUT__COUNT_MASK', + 'GUS_L1_CH0_CMD_OUT__COUNT__SHIFT', + 'GUS_L1_CH0_DATA_IN__COUNT_MASK', + 'GUS_L1_CH0_DATA_IN__COUNT__SHIFT', + 'GUS_L1_CH0_DATA_OUT__COUNT_MASK', + 'GUS_L1_CH0_DATA_OUT__COUNT__SHIFT', + 'GUS_L1_CH0_DATA_U_IN__COUNT_MASK', + 'GUS_L1_CH0_DATA_U_IN__COUNT__SHIFT', + 'GUS_L1_CH0_DATA_U_OUT__COUNT_MASK', + 'GUS_L1_CH0_DATA_U_OUT__COUNT__SHIFT', + 'GUS_L1_CH1_CMD_IN__COUNT_MASK', + 'GUS_L1_CH1_CMD_IN__COUNT__SHIFT', + 'GUS_L1_CH1_CMD_OUT__COUNT_MASK', + 'GUS_L1_CH1_CMD_OUT__COUNT__SHIFT', + 'GUS_L1_CH1_DATA_IN__COUNT_MASK', + 'GUS_L1_CH1_DATA_IN__COUNT__SHIFT', + 'GUS_L1_CH1_DATA_OUT__COUNT_MASK', + 'GUS_L1_CH1_DATA_OUT__COUNT__SHIFT', + 'GUS_L1_CH1_DATA_U_IN__COUNT_MASK', + 'GUS_L1_CH1_DATA_U_IN__COUNT__SHIFT', + 'GUS_L1_CH1_DATA_U_OUT__COUNT_MASK', + 'GUS_L1_CH1_DATA_U_OUT__COUNT__SHIFT', + 'GUS_L1_SA0_CMD_IN__COUNT_MASK', + 'GUS_L1_SA0_CMD_IN__COUNT__SHIFT', + 'GUS_L1_SA0_CMD_OUT__COUNT_MASK', + 'GUS_L1_SA0_CMD_OUT__COUNT__SHIFT', + 'GUS_L1_SA0_DATA_IN__COUNT_MASK', + 'GUS_L1_SA0_DATA_IN__COUNT__SHIFT', + 'GUS_L1_SA0_DATA_OUT__COUNT_MASK', + 'GUS_L1_SA0_DATA_OUT__COUNT__SHIFT', + 'GUS_L1_SA0_DATA_U_IN__COUNT_MASK', + 'GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT', + 'GUS_L1_SA0_DATA_U_OUT__COUNT_MASK', + 'GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT', + 'GUS_L1_SA1_CMD_IN__COUNT_MASK', + 'GUS_L1_SA1_CMD_IN__COUNT__SHIFT', + 'GUS_L1_SA1_CMD_OUT__COUNT_MASK', + 'GUS_L1_SA1_CMD_OUT__COUNT__SHIFT', + 'GUS_L1_SA1_DATA_IN__COUNT_MASK', + 'GUS_L1_SA1_DATA_IN__COUNT__SHIFT', + 'GUS_L1_SA1_DATA_OUT__COUNT_MASK', + 'GUS_L1_SA1_DATA_OUT__COUNT__SHIFT', + 'GUS_L1_SA1_DATA_U_IN__COUNT_MASK', + 'GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT', + 'GUS_L1_SA1_DATA_U_OUT__COUNT_MASK', + 'GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT', + 'GUS_L1_SA2_CMD_IN__COUNT_MASK', + 'GUS_L1_SA2_CMD_IN__COUNT__SHIFT', + 'GUS_L1_SA2_CMD_OUT__COUNT_MASK', + 'GUS_L1_SA2_CMD_OUT__COUNT__SHIFT', + 'GUS_L1_SA2_DATA_IN__COUNT_MASK', + 'GUS_L1_SA2_DATA_IN__COUNT__SHIFT', + 'GUS_L1_SA2_DATA_OUT__COUNT_MASK', + 'GUS_L1_SA2_DATA_OUT__COUNT__SHIFT', + 'GUS_L1_SA2_DATA_U_IN__COUNT_MASK', + 'GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT', + 'GUS_L1_SA2_DATA_U_OUT__COUNT_MASK', + 'GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT', + 'GUS_L1_SA3_CMD_IN__COUNT_MASK', + 'GUS_L1_SA3_CMD_IN__COUNT__SHIFT', + 'GUS_L1_SA3_CMD_OUT__COUNT_MASK', + 'GUS_L1_SA3_CMD_OUT__COUNT__SHIFT', + 'GUS_L1_SA3_DATA_IN__COUNT_MASK', + 'GUS_L1_SA3_DATA_IN__COUNT__SHIFT', + 'GUS_L1_SA3_DATA_OUT__COUNT_MASK', + 'GUS_L1_SA3_DATA_OUT__COUNT__SHIFT', + 'GUS_L1_SA3_DATA_U_IN__COUNT_MASK', + 'GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT', + 'GUS_L1_SA3_DATA_U_OUT__COUNT_MASK', + 'GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT', + 'GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK', + 'GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT', + 'GUS_MISC2__BLOCK_REQUESTS_MASK', + 'GUS_MISC2__BLOCK_REQUESTS__SHIFT', + 'GUS_MISC2__CH_L1_PERF_MASK_MASK', + 'GUS_MISC2__CH_L1_PERF_MASK__SHIFT', + 'GUS_MISC2__CH_L1_RO_MASK_MASK', + 'GUS_MISC2__CH_L1_RO_MASK__SHIFT', + 'GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK_MASK', + 'GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK__SHIFT', + 'GUS_MISC2__FGCLKEN_HIGH_MASK', 'GUS_MISC2__FGCLKEN_HIGH__SHIFT', + 'GUS_MISC2__FP_ATOMICS_ENABLE_MASK', + 'GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT', + 'GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK', + 'GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT', + 'GUS_MISC2__L1_RET_CLKEN_MASK', 'GUS_MISC2__L1_RET_CLKEN__SHIFT', + 'GUS_MISC2__REQUESTS_BLOCKED_MASK', + 'GUS_MISC2__REQUESTS_BLOCKED__SHIFT', + 'GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK_MASK', + 'GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT', + 'GUS_MISC2__SA0_L1_PERF_MASK_MASK', + 'GUS_MISC2__SA0_L1_PERF_MASK__SHIFT', + 'GUS_MISC2__SA0_L1_RO_MASK_MASK', + 'GUS_MISC2__SA0_L1_RO_MASK__SHIFT', + 'GUS_MISC2__SA1_L1_PERF_MASK_MASK', + 'GUS_MISC2__SA1_L1_PERF_MASK__SHIFT', + 'GUS_MISC2__SA1_L1_RO_MASK_MASK', + 'GUS_MISC2__SA1_L1_RO_MASK__SHIFT', + 'GUS_MISC2__SA2_L1_PERF_MASK_MASK', + 'GUS_MISC2__SA2_L1_PERF_MASK__SHIFT', + 'GUS_MISC2__SA2_L1_RO_MASK_MASK', + 'GUS_MISC2__SA2_L1_RO_MASK__SHIFT', + 'GUS_MISC2__SA3_L1_PERF_MASK_MASK', + 'GUS_MISC2__SA3_L1_PERF_MASK__SHIFT', + 'GUS_MISC2__SA3_L1_RO_MASK_MASK', + 'GUS_MISC2__SA3_L1_RO_MASK__SHIFT', + 'GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK_MASK', + 'GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT', + 'GUS_MISC3__CLEAR_LOG_MASK', 'GUS_MISC3__CLEAR_LOG__SHIFT', + 'GUS_MISC3__FP_ATOMICS_LOG_MASK', + 'GUS_MISC3__FP_ATOMICS_LOG__SHIFT', + 'GUS_MISC__EARLY_SDP_ORIGDATA_MASK', + 'GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT', + 'GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK', + 'GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT', + 'GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK', + 'GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT', + 'GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK', + 'GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT', + 'GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK', + 'GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT', + 'GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK', + 'GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT', + 'GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK', + 'GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT', + 'GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK', + 'GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT', + 'GUS_MISC__SEND0_IOWR_ONLY_MASK', + 'GUS_MISC__SEND0_IOWR_ONLY__SHIFT', + 'GUS_PERFCOUNTER0_CFG__CLEAR_MASK', + 'GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'GUS_PERFCOUNTER0_CFG__ENABLE_MASK', + 'GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'GUS_PERFCOUNTER1_CFG__CLEAR_MASK', + 'GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'GUS_PERFCOUNTER1_CFG__ENABLE_MASK', + 'GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK', + 'GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT', + 'GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'GUS_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'GUS_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK', + 'GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT', + 'GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK', + 'GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT', + 'GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK', + 'GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT', + 'GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK', + 'GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT', + 'GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK', + 'GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT', + 'GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK', + 'GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT', + 'GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK', + 'GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT', + 'GUS_SDP_CREDITS__TAG_LIMIT_MASK', + 'GUS_SDP_CREDITS__TAG_LIMIT__SHIFT', + 'GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK', + 'GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT', + 'GUS_SDP_ENABLE__ENABLE_MASK', 'GUS_SDP_ENABLE__ENABLE__SHIFT', + 'GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK', + 'GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT', + 'GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK', + 'GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT', + 'GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK', + 'GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT', + 'GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK', + 'GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT', + 'GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK', + 'GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT', + 'GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK', + 'GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT', + 'GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK', + 'GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT', + 'GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK', + 'GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT', + 'GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK', + 'GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT', + 'GUS_SDP_TAG_RESERVE0__VC0_MASK', + 'GUS_SDP_TAG_RESERVE0__VC0__SHIFT', + 'GUS_SDP_TAG_RESERVE0__VC1_MASK', + 'GUS_SDP_TAG_RESERVE0__VC1__SHIFT', + 'GUS_SDP_TAG_RESERVE0__VC2_MASK', + 'GUS_SDP_TAG_RESERVE0__VC2__SHIFT', + 'GUS_SDP_TAG_RESERVE0__VC3_MASK', + 'GUS_SDP_TAG_RESERVE0__VC3__SHIFT', + 'GUS_SDP_TAG_RESERVE1__VC4_MASK', + 'GUS_SDP_TAG_RESERVE1__VC4__SHIFT', + 'GUS_SDP_TAG_RESERVE1__VC5_MASK', + 'GUS_SDP_TAG_RESERVE1__VC5__SHIFT', + 'GUS_SDP_TAG_RESERVE1__VC6_MASK', + 'GUS_SDP_TAG_RESERVE1__VC6__SHIFT', + 'GUS_SDP_TAG_RESERVE1__VC7_MASK', + 'GUS_SDP_TAG_RESERVE1__VC7__SHIFT', + 'GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT', + 'GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT', + 'GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT', + 'GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT', + 'GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT', + 'GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK', + 'GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT', + 'GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT', + 'GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK', + 'GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK', + 'GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT', + 'GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK', + 'GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT', + 'GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK', + 'GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT', + 'HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT', + 'IA_ENHANCE__MISC_MASK', 'IA_ENHANCE__MISC__SHIFT', + 'IA_UTCL1_CNTL__BYPASS_MASK', 'IA_UTCL1_CNTL__BYPASS__SHIFT', + 'IA_UTCL1_CNTL__DROP_MODE_MASK', + 'IA_UTCL1_CNTL__DROP_MODE__SHIFT', + 'IA_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'IA_UTCL1_CNTL__INVALIDATE_MASK', + 'IA_UTCL1_CNTL__INVALIDATE__SHIFT', + 'IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK', + 'IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT', + 'IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK', + 'IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT', + 'IA_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK', + 'IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT', + 'IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK', + 'IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT', + 'IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK', + 'IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT', + 'IA_UTCL1_STATUS_2__IA_BUSY_MASK', + 'IA_UTCL1_STATUS_2__IA_BUSY__SHIFT', + 'IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK', + 'IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT', + 'IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK', + 'IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT', + 'IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK', + 'IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT', + 'IA_UTCL1_STATUS_2__PRT_DETECTED_MASK', + 'IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT', + 'IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK', + 'IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT', + 'IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK', + 'IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT', + 'IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK', + 'IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT', + 'IA_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'IA_UTCL1_STATUS__PRT_DETECTED_MASK', + 'IA_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'IA_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'IA_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE_MASK', + 'ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT', + 'ICG_CHA_CTRL__REG_CLK_OVERRIDE_MASK', + 'ICG_CHA_CTRL__REG_CLK_OVERRIDE__SHIFT', + 'ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK', + 'ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT', + 'ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK', + 'ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT', + 'ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK', + 'ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT', + 'ICG_CHA_CTRL__RET_CLK_OVERRIDE_MASK', + 'ICG_CHA_CTRL__RET_CLK_OVERRIDE__SHIFT', + 'ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK', + 'ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT', + 'ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK', + 'ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT', + 'ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK', + 'ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT', + 'ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE_MASK', + 'ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT', + 'ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK', + 'ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT', + 'ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK', + 'ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT', + 'ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK', + 'ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT', + 'ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK', + 'ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT', + 'ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK', + 'ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT', + 'ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK', + 'ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT', + 'ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK', + 'ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT', + 'ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK', + 'ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT', + 'ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK', + 'ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT', + 'ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK', + 'ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT', + 'ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE_MASK', + 'ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE__SHIFT', + 'ICG_GL1A_CTRL__REG_CLK_OVERRIDE_MASK', + 'ICG_GL1A_CTRL__REG_CLK_OVERRIDE__SHIFT', + 'ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE_MASK', + 'ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT', + 'ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE_MASK', + 'ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT', + 'ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK', + 'ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT', + 'ICG_GL1A_CTRL__RET_CLK_OVERRIDE_MASK', + 'ICG_GL1A_CTRL__RET_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE__SHIFT', + 'ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE_MASK', + 'ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED_MASK', + 'ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE__SHIFT', + 'ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE_MASK', + 'ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE__SHIFT', + 'ICG_SP_CLK_CTRL__CLK_OVERRIDE_MASK', + 'ICG_SP_CLK_CTRL__CLK_OVERRIDE__SHIFT', + 'LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK', + 'LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT', + 'LDS_CONFIG__CONF_BIT_1_MASK', 'LDS_CONFIG__CONF_BIT_1__SHIFT', + 'LDS_CONFIG__CONF_BIT_5_MASK', 'LDS_CONFIG__CONF_BIT_5__SHIFT', + 'LDS_CONFIG__CONF_BIT_6_MASK', 'LDS_CONFIG__CONF_BIT_6__SHIFT', + 'LDS_CONFIG__CONF_BIT_7_MASK', 'LDS_CONFIG__CONF_BIT_7__SHIFT', + 'LDS_CONFIG__CONF_BIT_8_MASK', 'LDS_CONFIG__CONF_BIT_8__SHIFT', + 'LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK', + 'LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT', + 'LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK', + 'LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT', + 'LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE_MASK', + 'LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK', + 'PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT', + 'PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK', + 'PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT', + 'PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK', + 'PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT', + 'PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK', + 'PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT', + 'PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK', + 'PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT', + 'PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK', + 'PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT', + 'PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK', + 'PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK', + 'PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_0_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_1_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_2_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_3_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_4_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_5_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT', + 'PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK', + 'PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT', + 'PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK', + 'PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT', + 'PA_CL_CNTL_STATUS__CL_BUSY_MASK', + 'PA_CL_CNTL_STATUS__CL_BUSY__SHIFT', + 'PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK', + 'PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT', + 'PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK', + 'PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT', + 'PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK', + 'PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT', + 'PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK', + 'PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE_MASK', + 'PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE0_MASK', + 'PA_CL_ENHANCE__ECO_SPARE0__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE1_MASK', + 'PA_CL_ENHANCE__ECO_SPARE1__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE2_MASK', + 'PA_CL_ENHANCE__ECO_SPARE2__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE3_MASK', + 'PA_CL_ENHANCE__ECO_SPARE3__SHIFT', + 'PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL_MASK', + 'PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL__SHIFT', + 'PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK', + 'PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT', + 'PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK', + 'PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT', + 'PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK', + 'PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT', + 'PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK', + 'PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT', + 'PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK', + 'PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT', + 'PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK', + 'PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT', + 'PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK', + 'PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT', + 'PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK', + 'PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT', + 'PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK', + 'PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT', + 'PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK', + 'PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT', + 'PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK', + 'PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT', + 'PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK', + 'PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT', + 'PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK', + 'PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT', + 'PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK', + 'PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT', + 'PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK', + 'PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK', + 'PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK', + 'PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK', + 'PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT', + 'PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK', + 'PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT', + 'PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK', + 'PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT', + 'PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK', + 'PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT', + 'PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK', + 'PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT', + 'PA_CL_POINT_SIZE__DATA_REGISTER_MASK', + 'PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT', + 'PA_CL_POINT_X_RAD__DATA_REGISTER_MASK', + 'PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT', + 'PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK', + 'PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT', + 'PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK', + 'PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_0_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_0_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_0_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_0_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT', + 'PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT', + 'PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK', + 'PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT', + 'PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK', + 'PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT', + 'PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK', + 'PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT', + 'PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK', + 'PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT', + 'PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK', + 'PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT', + 'PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK', + 'PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT', + 'PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK', + 'PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT', + 'PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK', + 'PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT', + 'PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK', + 'PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VTX_W0_FMT_MASK', + 'PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT', + 'PA_CL_VTE_CNTL__VTX_XY_FMT_MASK', + 'PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT', + 'PA_CL_VTE_CNTL__VTX_Z_FMT_MASK', + 'PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT', + 'PA_PH_ENHANCE__DISABLE_FOPKT_MASK', + 'PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK', + 'PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT', + 'PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT', + 'PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK', + 'PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT', + 'PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK', + 'PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT', + 'PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK', + 'PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK', + 'PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT', + 'PA_PH_ENHANCE__ECO_SPARE0_MASK', + 'PA_PH_ENHANCE__ECO_SPARE0__SHIFT', + 'PA_PH_ENHANCE__ECO_SPARE1_MASK', + 'PA_PH_ENHANCE__ECO_SPARE1__SHIFT', + 'PA_PH_ENHANCE__ECO_SPARE2_MASK', + 'PA_PH_ENHANCE__ECO_SPARE2__SHIFT', + 'PA_PH_ENHANCE__ECO_SPARE3_MASK', + 'PA_PH_ENHANCE__ECO_SPARE3__SHIFT', + 'PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK', + 'PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT', + 'PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON_MASK', + 'PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON__SHIFT', + 'PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE_MASK', + 'PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE__SHIFT', + 'PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_MASK', + 'PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE__SHIFT', + 'PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE_MASK', + 'PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE__SHIFT', + 'PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS_MASK', + 'PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS__SHIFT', + 'PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK', + 'PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT', + 'PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK', + 'PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT', + 'PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT', + 'PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK', + 'PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT', + 'PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK', + 'PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT', + 'PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK', + 'PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT', + 'PA_RATE_CNTL__PRIM_RATE_MASK', 'PA_RATE_CNTL__PRIM_RATE__SHIFT', + 'PA_RATE_CNTL__VERTEX_RATE_MASK', + 'PA_RATE_CNTL__VERTEX_RATE__SHIFT', + 'PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK', + 'PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT', + 'PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK', + 'PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT', + 'PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER_MASK', + 'PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER__SHIFT', + 'PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK', + 'PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT', + 'PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK', + 'PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT', + 'PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK', + 'PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT', + 'PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK', + 'PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT', + 'PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING_MASK', + 'PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING__SHIFT', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT', + 'PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES_MASK', + 'PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT', + 'PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN_MASK', + 'PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN__SHIFT', + 'PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK', + 'PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT', + 'PA_SC_ATM_CNTL__SC_PC_IF_SIZE_MASK', + 'PA_SC_ATM_CNTL__SC_PC_IF_SIZE__SHIFT', + 'PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES_MASK', + 'PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES__SHIFT', + 'PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK', + 'PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT', + 'PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK', + 'PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT', + 'PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK', + 'PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT', + 'PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK', + 'PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT', + 'PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK', + 'PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT', + 'PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK', + 'PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT', + 'PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK', + 'PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT', + 'PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK', + 'PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT', + 'PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK', + 'PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT', + 'PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X_MASK', + 'PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X__SHIFT', + 'PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X_MASK', + 'PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X__SHIFT', + 'PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN_MASK', + 'PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN__SHIFT', + 'PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION_MASK', + 'PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION__SHIFT', + 'PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW_MASK', + 'PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW__SHIFT', + 'PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK', + 'PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT', + 'PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK', + 'PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT', + 'PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD_MASK', + 'PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD__SHIFT', + 'PA_SC_BINNER_CNTL_2__ZPP_ENABLED_MASK', + 'PA_SC_BINNER_CNTL_2__ZPP_ENABLED__SHIFT', + 'PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED_MASK', + 'PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED__SHIFT', + 'PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK', + 'PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT', + 'PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK', + 'PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT', + 'PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK', + 'PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT', + 'PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK', + 'PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT', + 'PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK', + 'PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT', + 'PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK', + 'PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK', + 'PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT', + 'PA_SC_CLIPRECT_0_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_0_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_0_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_0_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_0_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_0_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_1_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_1_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_1_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_1_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_1_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_1_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_2_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_2_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_2_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_2_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_2_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_2_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_3_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_3_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_3_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_3_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_3_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_3_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK', + 'PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_BT_MASK', + 'PA_SC_EDGERULE__ER_LINE_BT__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_LR_MASK', + 'PA_SC_EDGERULE__ER_LINE_LR__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_RL_MASK', + 'PA_SC_EDGERULE__ER_LINE_RL__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_TB_MASK', + 'PA_SC_EDGERULE__ER_LINE_TB__SHIFT', + 'PA_SC_EDGERULE__ER_POINT_MASK', + 'PA_SC_EDGERULE__ER_POINT__SHIFT', 'PA_SC_EDGERULE__ER_RECT_MASK', + 'PA_SC_EDGERULE__ER_RECT__SHIFT', 'PA_SC_EDGERULE__ER_TRI_MASK', + 'PA_SC_EDGERULE__ER_TRI__SHIFT', + 'PA_SC_ENHANCE_1__BYPASS_PBB_MASK', + 'PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK', + 'PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK', + 'PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT', + 'PA_SC_ENHANCE_1__ECO_SPARE1_MASK', + 'PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT', + 'PA_SC_ENHANCE_1__ECO_SPARE2_MASK', + 'PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT', + 'PA_SC_ENHANCE_1__ECO_SPARE3_MASK', + 'PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT', + 'PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK', + 'PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT', + 'PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK', + 'PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT', + 'PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK', + 'PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT', + 'PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK', + 'PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT', + 'PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK', + 'PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT', + 'PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK', + 'PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK', + 'PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK', + 'PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK', + 'PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK', + 'PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK', + 'PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK', + 'PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK', + 'PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK', + 'PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK', + 'PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT', + 'PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK', + 'PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT', + 'PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK', + 'PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT', + 'PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK', + 'PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT', + 'PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK', + 'PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT', + 'PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK', + 'PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT', + 'PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK', + 'PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT', + 'PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK', + 'PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT', + 'PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK', + 'PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT', + 'PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK', + 'PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT', + 'PA_SC_ENHANCE_2__RSVD_MASK', 'PA_SC_ENHANCE_2__RSVD__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK', + 'PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN_MASK', + 'PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES_MASK', + 'PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS_MASK', + 'PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK', + 'PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK', + 'PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION_MASK', + 'PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST_MASK', + 'PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM_MASK', + 'PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY_MASK', + 'PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY__SHIFT', + 'PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE_MASK', + 'PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE__SHIFT', + 'PA_SC_ENHANCE_3__ECO_SPARE0_MASK', + 'PA_SC_ENHANCE_3__ECO_SPARE0__SHIFT', + 'PA_SC_ENHANCE_3__ECO_SPARE1_MASK', + 'PA_SC_ENHANCE_3__ECO_SPARE1__SHIFT', + 'PA_SC_ENHANCE_3__ECO_SPARE2_MASK', + 'PA_SC_ENHANCE_3__ECO_SPARE2__SHIFT', + 'PA_SC_ENHANCE_3__ECO_SPARE3_MASK', + 'PA_SC_ENHANCE_3__ECO_SPARE3__SHIFT', + 'PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER_MASK', + 'PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER__SHIFT', + 'PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS_MASK', + 'PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS__SHIFT', + 'PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_MASK', + 'PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER__SHIFT', + 'PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK', + 'PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT', + 'PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK', + 'PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT', + 'PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY_MASK', + 'PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY__SHIFT', + 'PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL_MASK', + 'PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL__SHIFT', + 'PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL_MASK', + 'PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL__SHIFT', + 'PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL_MASK', + 'PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL__SHIFT', + 'PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED_MASK', + 'PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED__SHIFT', + 'PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK', + 'PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT', + 'PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK', + 'PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT', + 'PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK', + 'PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK', + 'PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK', + 'PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK', + 'PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK', + 'PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT', + 'PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK', + 'PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT', + 'PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK', + 'PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT', + 'PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK', + 'PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT', + 'PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK', + 'PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK', + 'PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT', + 'PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK', + 'PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK', + 'PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT', + 'PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK', + 'PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT', + 'PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT', + 'PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT', + 'PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT', + 'PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT', + 'PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK', + 'PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT', + 'PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK', + 'PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT', + 'PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK', + 'PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT', + 'PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK', + 'PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT', + 'PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT', + 'PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK', + 'PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT', + 'PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK', + 'PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT', + 'PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK', + 'PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT', + 'PA_SC_LINE_CNTL__LAST_PIXEL_MASK', + 'PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT', + 'PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK', + 'PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT', + 'PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK', + 'PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT', + 'PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK', + 'PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT', + 'PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK', + 'PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT', + 'PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK', + 'PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT', + 'PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK', + 'PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT', + 'PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK', + 'PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT', + 'PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK', + 'PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK', + 'PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT', + 'PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK', + 'PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT', + 'PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK', + 'PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT', + 'PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK', + 'PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK', + 'PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT', + 'PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK', + 'PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK', + 'PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_SIZE_MASK', + 'PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT', + 'PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK', + 'PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT', + 'PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT_MASK', + 'PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT__SHIFT', + 'PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES_MASK', + 'PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT', + 'PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC_MASK', + 'PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC__SHIFT', + 'PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK', + 'PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT', + 'PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK', + 'PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT', + 'PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK', + 'PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK', + 'PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK', + 'PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK', + 'PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK', + 'PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK', + 'PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT', + 'PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD_MASK', + 'PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD__SHIFT', + 'PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN_MASK', + 'PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN__SHIFT', + 'PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN_MASK', + 'PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN__SHIFT', + 'PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE_MASK', + 'PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE__SHIFT', + 'PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE_MASK', + 'PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE__SHIFT', + 'PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE_MASK', + 'PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE__SHIFT', + 'PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK', + 'PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT', + 'PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK', + 'PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT', + 'PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK', + 'PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_MAP_MASK', + 'PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK', + 'PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_XSEL2_MASK', + 'PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SC_MAP_MASK', + 'PA_SC_RASTER_CONFIG__SC_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG__SC_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SC_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SE_MAP_MASK', + 'PA_SC_RASTER_CONFIG__SE_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG__SE_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SE_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_0__X_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_1__X_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_0__X_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_1__X_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT', + 'PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK', + 'PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT', + 'PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK', + 'PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT', + 'PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK', + 'PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT', + 'PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK', + 'PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT', + 'PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD_MASK', + 'PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD__SHIFT', + 'PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK', + 'PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT', + 'PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK', + 'PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT', + 'PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK', + 'PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT', + 'PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK', + 'PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT', + 'PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK', + 'PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT', + 'PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK', + 'PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT', + 'PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK', + 'PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT', + 'PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK', + 'PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT', + 'PA_SC_TRAP_SCREEN_H__X_COORD_MASK', + 'PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT', + 'PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK', + 'PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT', + 'PA_SC_TRAP_SCREEN_V__Y_COORD_MASK', + 'PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT', + 'PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE_MASK', + 'PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE__SHIFT', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE_MASK', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE__SHIFT', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE_MASK', + 'PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE__SHIFT', + 'PA_SC_VRS_RATE_BASE_EXT__BASE_256B_MASK', + 'PA_SC_VRS_RATE_BASE_EXT__BASE_256B__SHIFT', + 'PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID_MASK', + 'PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID__SHIFT', + 'PA_SC_VRS_RATE_BASE__BASE_256B_MASK', + 'PA_SC_VRS_RATE_BASE__BASE_256B__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD__SHIFT', + 'PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR_MASK', + 'PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR__SHIFT', + 'PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B_MASK', + 'PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B__SHIFT', + 'PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B_MASK', + 'PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B__SHIFT', + 'PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX_MASK', + 'PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX__SHIFT', + 'PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX_MASK', + 'PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX__SHIFT', + 'PA_SC_VRS_RATE_SIZE_XY__X_MAX_MASK', + 'PA_SC_VRS_RATE_SIZE_XY__X_MAX__SHIFT', + 'PA_SC_VRS_RATE_SIZE_XY__Y_MAX_MASK', + 'PA_SC_VRS_RATE_SIZE_XY__Y_MAX__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9_MASK', + 'PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE__SHIFT', + 'PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK', + 'PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT', + 'PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK', + 'PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT', + 'PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK', + 'PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT', + 'PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK', + 'PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT', + 'PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK', + 'PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT', + 'PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK', + 'PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT', + 'PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK', + 'PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT', + 'PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK', + 'PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT', + 'PA_STEREO_CNTL__RT_SLICE_MODE_MASK', + 'PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT', + 'PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK', + 'PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT', + 'PA_STEREO_CNTL__STEREO_MODE_MASK', + 'PA_STEREO_CNTL__STEREO_MODE__SHIFT', + 'PA_STEREO_CNTL__VP_ID_MODE_MASK', + 'PA_STEREO_CNTL__VP_ID_MODE__SHIFT', + 'PA_STEREO_CNTL__VP_ID_OFFSET_MASK', + 'PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT', + 'PA_SU_CNTL_STATUS__SU_BUSY_MASK', + 'PA_SU_CNTL_STATUS__SU_BUSY__SHIFT', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT', + 'PA_SU_LINE_CNTL__WIDTH_MASK', 'PA_SU_LINE_CNTL__WIDTH__SHIFT', + 'PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK', + 'PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT', + 'PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK', + 'PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT', + 'PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK', + 'PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT', + 'PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK', + 'PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT', + 'PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK', + 'PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT', + 'PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'PA_SU_POINT_MINMAX__MAX_SIZE_MASK', + 'PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT', + 'PA_SU_POINT_MINMAX__MIN_SIZE_MASK', + 'PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT', + 'PA_SU_POINT_SIZE__HEIGHT_MASK', + 'PA_SU_POINT_SIZE__HEIGHT__SHIFT', 'PA_SU_POINT_SIZE__WIDTH_MASK', + 'PA_SU_POINT_SIZE__WIDTH__SHIFT', + 'PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK', + 'PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT', + 'PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK', + 'PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT', + 'PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK', + 'PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT', + 'PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK', + 'PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT', + 'PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK', + 'PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK', + 'PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK', + 'PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK', + 'PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT', + 'PA_SU_SC_MODE_CNTL__CULL_BACK_MASK', + 'PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT', + 'PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK', + 'PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT', + 'PA_SU_SC_MODE_CNTL__FACE_MASK', + 'PA_SU_SC_MODE_CNTL__FACE__SHIFT', + 'PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT', + 'PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK', + 'PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT', + 'PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK', + 'PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT', + 'PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK', + 'PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK', + 'PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK', + 'PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_MODE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT', + 'PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK', + 'PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT', + 'PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK', + 'PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT', + 'PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_VTX_CNTL__PIX_CENTER_MASK', + 'PA_SU_VTX_CNTL__PIX_CENTER__SHIFT', + 'PA_SU_VTX_CNTL__QUANT_MODE_MASK', + 'PA_SU_VTX_CNTL__QUANT_MODE__SHIFT', + 'PA_SU_VTX_CNTL__ROUND_MODE_MASK', + 'PA_SU_VTX_CNTL__ROUND_MODE__SHIFT', + 'PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK', + 'PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT', + 'PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK', + 'PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT', + 'PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK', + 'PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT', + 'PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK', + 'PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT', + 'PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK', + 'PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT', + 'PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK', + 'PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT', + 'PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK', + 'PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT', + 'PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK', + 'PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT', + 'PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK', + 'PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT', + 'PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK', + 'PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT', + 'PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK', + 'PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT', + 'PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK', + 'PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT', + 'PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK', + 'PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT', + 'PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK', + 'PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT', + 'PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK', + 'PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT', + 'PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK', + 'PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT', + 'PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK', + 'PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT', + 'PC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'PC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'PC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'PC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'PC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'PC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'PC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'PC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'PC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'PC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'PC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'PC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'PC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'PC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'PC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'PC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'PC_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'PC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'PC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'PC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'PC_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'PC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'PC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'PC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'PC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'PC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'PC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'PC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'PC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'PC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'PC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'PC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'PC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'PC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'PC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'PC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'PC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'PC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'PC_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'PC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'PC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'PC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'PC_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'PC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'PC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'PC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'PC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'PC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'PC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'PC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'PC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'PC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'PC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'PC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'PC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'PC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'PC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'PC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'PC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'PC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'PC_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'PC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'PC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'PC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'PC_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'PC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'PC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'PC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'PC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'PC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'PC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'PC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'PC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'PC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'PC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'PC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'PC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'PC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'PC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'PC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'PC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'PC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'PC_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'PC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'PC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'PC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'PC_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'PC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE_MASK', + 'PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE__SHIFT', + 'PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE_MASK', + 'PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE__SHIFT', + 'PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE_MASK', + 'PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE__SHIFT', + 'PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE_MASK', + 'PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE__SHIFT', + 'PMM_CNTL2__RESERVED_MASK', 'PMM_CNTL2__RESERVED__SHIFT', + 'PMM_CNTL__ABIT_FORCE_FLUSH_MASK', + 'PMM_CNTL__ABIT_FORCE_FLUSH__SHIFT', + 'PMM_CNTL__ABIT_TIMER_DISABLE_MASK', + 'PMM_CNTL__ABIT_TIMER_DISABLE__SHIFT', + 'PMM_CNTL__ABIT_TIMER_RESET_MASK', + 'PMM_CNTL__ABIT_TIMER_RESET__SHIFT', + 'PMM_CNTL__ABIT_TIMER_THRESHOLD_MASK', + 'PMM_CNTL__ABIT_TIMER_THRESHOLD__SHIFT', + 'PMM_CNTL__INTERRUPT_PRIORITY_MASK', + 'PMM_CNTL__INTERRUPT_PRIORITY__SHIFT', + 'PMM_CNTL__PMM_DISABLE_MASK', 'PMM_CNTL__PMM_DISABLE__SHIFT', + 'PMM_CNTL__PMM_INTERRUPTS_DISABLE_MASK', + 'PMM_CNTL__PMM_INTERRUPTS_DISABLE__SHIFT', + 'PMM_CNTL__RESERVED_MASK', 'PMM_CNTL__RESERVED__SHIFT', + 'PMM_STATUS__ABIT_FLUSH_ERROR_MASK', + 'PMM_STATUS__ABIT_FLUSH_ERROR__SHIFT', + 'PMM_STATUS__ABIT_FORCE_FLUSH_DONE_MASK', + 'PMM_STATUS__ABIT_FORCE_FLUSH_DONE__SHIFT', + 'PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS_MASK', + 'PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS__SHIFT', + 'PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS_MASK', + 'PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS__SHIFT', + 'PMM_STATUS__ABIT_TIMER_FLUSH_DONE_MASK', + 'PMM_STATUS__ABIT_TIMER_FLUSH_DONE__SHIFT', + 'PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS_MASK', + 'PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS__SHIFT', + 'PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS_MASK', + 'PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS__SHIFT', + 'PMM_STATUS__ABIT_TIMER_RUNNING_MASK', + 'PMM_STATUS__ABIT_TIMER_RUNNING__SHIFT', + 'PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS_MASK', + 'PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS__SHIFT', + 'PMM_STATUS__PMM_IDLE_MASK', 'PMM_STATUS__PMM_IDLE__SHIFT', + 'PMM_STATUS__PMM_INTERRUPTS_PENDING_MASK', + 'PMM_STATUS__PMM_INTERRUPTS_PENDING__SHIFT', + 'PMM_STATUS__RESERVED_MASK', 'PMM_STATUS__RESERVED__SHIFT', + 'PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK', + 'PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK', + 'PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT', + 'PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK', + 'PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT', + 'PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK', + 'PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT', + 'PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK', + 'PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT', + 'PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK', + 'PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT', + 'PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK', + 'PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT', + 'PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK', + 'PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT', + 'PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK', + 'PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK', + 'PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK', + 'PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT', + 'PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK', + 'PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT', + 'PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK', + 'PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT', + 'PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK', + 'PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK', + 'RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK', + 'RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK', + 'RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT', + 'RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK', + 'RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT', + 'RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK', + 'RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT', + 'RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK', + 'RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT', + 'RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK', + 'RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT', + 'RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK', + 'RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT', + 'RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK', + 'RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT', + 'RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY_MASK', + 'RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY__SHIFT', + 'RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK', + 'RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK', + 'RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK', + 'RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK', + 'RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT', + 'RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK', + 'RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK', + 'RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT', + 'RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK', + 'RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT', + 'RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RESERVED_11_MASK', + 'RLC_CLK_CNTL__RESERVED_11__SHIFT', + 'RLC_CLK_CNTL__RESERVED_15_MASK', + 'RLC_CLK_CNTL__RESERVED_15__SHIFT', + 'RLC_CLK_CNTL__RESERVED_9_MASK', + 'RLC_CLK_CNTL__RESERVED_9__SHIFT', 'RLC_CLK_CNTL__RESERVED_MASK', + 'RLC_CLK_CNTL__RESERVED__SHIFT', + 'RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT', + 'RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK', + 'RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT', + 'RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK', + 'RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT', + 'RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK', + 'RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT', + 'RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK', + 'RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT', + 'RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK', + 'RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK', + 'RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK', + 'RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK', + 'RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK', + 'RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT', + 'RLC_CLK_COUNT_STAT__RESERVED_MASK', + 'RLC_CLK_COUNT_STAT__RESERVED__SHIFT', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_MASK', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED_MASK', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_MASK', + 'RLC_CLK_RESIDENCY_CNTR_CTRL__RESET__SHIFT', + 'RLC_CLK_RESIDENCY_EVENT_CNTR__DATA_MASK', + 'RLC_CLK_RESIDENCY_EVENT_CNTR__DATA__SHIFT', + 'RLC_CLK_RESIDENCY_REF_CNTR__DATA_MASK', + 'RLC_CLK_RESIDENCY_REF_CNTR__DATA__SHIFT', + 'RLC_CNTL__FORCE_RETRY_MASK', 'RLC_CNTL__FORCE_RETRY__SHIFT', + 'RLC_CNTL__READ_CACHE_DISABLE_MASK', + 'RLC_CNTL__READ_CACHE_DISABLE__SHIFT', 'RLC_CNTL__RESERVED_MASK', + 'RLC_CNTL__RESERVED__SHIFT', 'RLC_CNTL__RLC_ENABLE_F32_MASK', + 'RLC_CNTL__RLC_ENABLE_F32__SHIFT', 'RLC_CNTL__RLC_STEP_F32_MASK', + 'RLC_CNTL__RLC_STEP_F32__SHIFT', 'RLC_CP_EOF_INT_CNT__CNT_MASK', + 'RLC_CP_EOF_INT_CNT__CNT__SHIFT', + 'RLC_CP_EOF_INT__INTERRUPT_MASK', + 'RLC_CP_EOF_INT__INTERRUPT__SHIFT', + 'RLC_CP_EOF_INT__RESERVED_MASK', + 'RLC_CP_EOF_INT__RESERVED__SHIFT', + 'RLC_CP_SCHEDULERS__scheduler0_MASK', + 'RLC_CP_SCHEDULERS__scheduler0__SHIFT', + 'RLC_CP_SCHEDULERS__scheduler1_MASK', + 'RLC_CP_SCHEDULERS__scheduler1__SHIFT', + 'RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK', + 'RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT', + 'RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK', + 'RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT', + 'RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK', + 'RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT', + 'RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK', + 'RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT', + 'RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK', + 'RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT', + 'RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK', + 'RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT', + 'RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK', + 'RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT', + 'RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK', + 'RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT', + 'RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK', + 'RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT', + 'RLC_CSIB_ADDR_HI__ADDRESS_MASK', + 'RLC_CSIB_ADDR_HI__ADDRESS__SHIFT', + 'RLC_CSIB_ADDR_LO__ADDRESS_MASK', + 'RLC_CSIB_ADDR_LO__ADDRESS__SHIFT', + 'RLC_CSIB_LENGTH__LENGTH_MASK', 'RLC_CSIB_LENGTH__LENGTH__SHIFT', + 'RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK', + 'RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT', + 'RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK', + 'RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT', + 'RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_MASK', + 'RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT', + 'RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED_MASK', + 'RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT', + 'RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK', + 'RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT', + 'RLC_DS_RESIDENCY_CNTR_CTRL__RESET_MASK', + 'RLC_DS_RESIDENCY_CNTR_CTRL__RESET__SHIFT', + 'RLC_DS_RESIDENCY_EVENT_CNTR__DATA_MASK', + 'RLC_DS_RESIDENCY_EVENT_CNTR__DATA__SHIFT', + 'RLC_DS_RESIDENCY_REF_CNTR__DATA_MASK', + 'RLC_DS_RESIDENCY_REF_CNTR__DATA__SHIFT', + 'RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK', + 'RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT', + 'RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK', + 'RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT', + 'RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK', + 'RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT', + 'RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK', + 'RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT', + 'RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK', + 'RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_MASK', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED_MASK', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_MASK', + 'RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET__SHIFT', + 'RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA_MASK', + 'RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA__SHIFT', + 'RLC_GENERAL_RESIDENCY_REF_CNTR__DATA_MASK', + 'RLC_GENERAL_RESIDENCY_REF_CNTR__DATA__SHIFT', + 'RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED_MASK', + 'RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED__SHIFT', + 'RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED_MASK', + 'RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED__SHIFT', + 'RLC_GFX_IH_ARBITER_STAT__RESERVED_MASK', + 'RLC_GFX_IH_ARBITER_STAT__RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_14_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_14__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__RESERVED_31_30_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__RESERVED_31_30__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR__SHIFT', + 'RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK_MASK', + 'RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_16_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_16__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR__SHIFT', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED_MASK', + 'RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED__SHIFT', + 'RLC_GFX_IMU_CMD__CMD_MASK', 'RLC_GFX_IMU_CMD__CMD__SHIFT', + 'RLC_GFX_IMU_DATA_0__DATA_MASK', + 'RLC_GFX_IMU_DATA_0__DATA__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT', + 'RLC_GPM_GENERAL_0__DATA_MASK', 'RLC_GPM_GENERAL_0__DATA__SHIFT', + 'RLC_GPM_GENERAL_10__DATA_MASK', + 'RLC_GPM_GENERAL_10__DATA__SHIFT', + 'RLC_GPM_GENERAL_11__DATA_MASK', + 'RLC_GPM_GENERAL_11__DATA__SHIFT', + 'RLC_GPM_GENERAL_12__DATA_MASK', + 'RLC_GPM_GENERAL_12__DATA__SHIFT', + 'RLC_GPM_GENERAL_13__DATA_MASK', + 'RLC_GPM_GENERAL_13__DATA__SHIFT', + 'RLC_GPM_GENERAL_14__DATA_MASK', + 'RLC_GPM_GENERAL_14__DATA__SHIFT', + 'RLC_GPM_GENERAL_15__DATA_MASK', + 'RLC_GPM_GENERAL_15__DATA__SHIFT', + 'RLC_GPM_GENERAL_16__DATA_MASK', + 'RLC_GPM_GENERAL_16__DATA__SHIFT', 'RLC_GPM_GENERAL_1__DATA_MASK', + 'RLC_GPM_GENERAL_1__DATA__SHIFT', 'RLC_GPM_GENERAL_2__DATA_MASK', + 'RLC_GPM_GENERAL_2__DATA__SHIFT', 'RLC_GPM_GENERAL_3__DATA_MASK', + 'RLC_GPM_GENERAL_3__DATA__SHIFT', 'RLC_GPM_GENERAL_4__DATA_MASK', + 'RLC_GPM_GENERAL_4__DATA__SHIFT', 'RLC_GPM_GENERAL_5__DATA_MASK', + 'RLC_GPM_GENERAL_5__DATA__SHIFT', 'RLC_GPM_GENERAL_6__DATA_MASK', + 'RLC_GPM_GENERAL_6__DATA__SHIFT', 'RLC_GPM_GENERAL_7__DATA_MASK', + 'RLC_GPM_GENERAL_7__DATA__SHIFT', 'RLC_GPM_GENERAL_8__DATA_MASK', + 'RLC_GPM_GENERAL_8__DATA__SHIFT', 'RLC_GPM_GENERAL_9__DATA_MASK', + 'RLC_GPM_GENERAL_9__DATA__SHIFT', + 'RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK', + 'RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT', + 'RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK', + 'RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT', + 'RLC_GPM_INT_STAT_TH0__STATUS_MASK', + 'RLC_GPM_INT_STAT_TH0__STATUS__SHIFT', + 'RLC_GPM_IRAM_ADDR__ADDR_MASK', 'RLC_GPM_IRAM_ADDR__ADDR__SHIFT', + 'RLC_GPM_IRAM_DATA__DATA_MASK', 'RLC_GPM_IRAM_DATA__DATA__SHIFT', + 'RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED__SHIFT', + 'RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK', + 'RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT', + 'RLC_GPM_PERF_COUNT_0__ENABLE_MASK', + 'RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT', + 'RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK', + 'RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK', + 'RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_0__RESERVED_MASK', + 'RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT', + 'RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_0__UNUSED_MASK', + 'RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT', + 'RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_1__ENABLE_MASK', + 'RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT', + 'RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK', + 'RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK', + 'RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_1__RESERVED_MASK', + 'RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT', + 'RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_1__UNUSED_MASK', + 'RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT', + 'RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT', + 'RLC_GPM_SCRATCH_ADDR__ADDR_MASK', + 'RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT', + 'RLC_GPM_SCRATCH_DATA__DATA_MASK', + 'RLC_GPM_SCRATCH_DATA__DATA__SHIFT', + 'RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK', + 'RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT', + 'RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK', + 'RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT', + 'RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__CMP_power_status_MASK', + 'RLC_GPM_STAT__CMP_power_status__SHIFT', + 'RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK', + 'RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT', + 'RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK', + 'RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT', + 'RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK', + 'RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK', + 'RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT', + 'RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK', + 'RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT', + 'RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK', + 'RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK', + 'RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT', + 'RLC_GPM_STAT__GFX_LS_STATUS_MASK', + 'RLC_GPM_STAT__GFX_LS_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK', + 'RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX_POWER_STATUS_MASK', + 'RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT', + 'RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK', + 'RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT', + 'RLC_GPM_STAT__PG_ERROR_STATUS_MASK', + 'RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT', + 'RLC_GPM_STAT__RESTORING_REGISTERS_MASK', + 'RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT', + 'RLC_GPM_STAT__RLC_BUSY_MASK', 'RLC_GPM_STAT__RLC_BUSY__SHIFT', + 'RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK', + 'RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT', + 'RLC_GPM_STAT__SAVING_REGISTERS_MASK', + 'RLC_GPM_STAT__SAVING_REGISTERS__SHIFT', + 'RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK', + 'RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT', + 'RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK', + 'RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT', + 'RLC_GPM_THREAD_ENABLE__RESERVED_MASK', + 'RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED_MASK', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED__SHIFT', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE_MASK', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE__SHIFT', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE_MASK', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE__SHIFT', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE_MASK', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE__SHIFT', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE_MASK', + 'RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_RESET__RESERVED_MASK', + 'RLC_GPM_THREAD_RESET__RESERVED__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT', + 'RLC_GPM_TIMER_CTRL__RESERVED_1_MASK', + 'RLC_GPM_TIMER_CTRL__RESERVED_1__SHIFT', + 'RLC_GPM_TIMER_CTRL__RESERVED_2_MASK', + 'RLC_GPM_TIMER_CTRL__RESERVED_2__SHIFT', + 'RLC_GPM_TIMER_CTRL__RESERVED_MASK', + 'RLC_GPM_TIMER_CTRL__RESERVED__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT', + 'RLC_GPM_TIMER_INT_0__TIMER_MASK', + 'RLC_GPM_TIMER_INT_0__TIMER__SHIFT', + 'RLC_GPM_TIMER_INT_1__TIMER_MASK', + 'RLC_GPM_TIMER_INT_1__TIMER__SHIFT', + 'RLC_GPM_TIMER_INT_2__TIMER_MASK', + 'RLC_GPM_TIMER_INT_2__TIMER__SHIFT', + 'RLC_GPM_TIMER_INT_3__TIMER_MASK', + 'RLC_GPM_TIMER_INT_3__TIMER__SHIFT', + 'RLC_GPM_TIMER_INT_4__TIMER_MASK', + 'RLC_GPM_TIMER_INT_4__TIMER__SHIFT', + 'RLC_GPM_TIMER_STAT__RESERVED_1_MASK', + 'RLC_GPM_TIMER_STAT__RESERVED_1__SHIFT', + 'RLC_GPM_TIMER_STAT__RESERVED_2_MASK', + 'RLC_GPM_TIMER_STAT__RESERVED_2__SHIFT', + 'RLC_GPM_TIMER_STAT__RESERVED_MASK', + 'RLC_GPM_TIMER_STAT__RESERVED__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT', + 'RLC_GPM_UCODE_ADDR__RESERVED_MASK', + 'RLC_GPM_UCODE_ADDR__RESERVED__SHIFT', + 'RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK', + 'RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'RLC_GPM_UCODE_DATA__UCODE_DATA_MASK', + 'RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK', + 'RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK', + 'RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK', + 'RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK', + 'RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK', + 'RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK', + 'RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK', + 'RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK', + 'RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK', + 'RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK', + 'RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK', + 'RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK', + 'RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_GPR_REG1__DATA_MASK', 'RLC_GPR_REG1__DATA__SHIFT', + 'RLC_GPR_REG2__DATA_MASK', 'RLC_GPR_REG2__DATA__SHIFT', + 'RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK', + 'RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT', + 'RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK', + 'RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT', + 'RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK', + 'RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT', + 'RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK', + 'RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK', + 'RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK', + 'RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK', + 'RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK', + 'RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK', + 'RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK', + 'RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK', + 'RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK', + 'RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK', + 'RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK', + 'RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK', + 'RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__RESERVED_MASK', + 'RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT', + 'RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK', + 'RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT', + 'RLC_GPU_IOV_CFG_REG2__RESERVED_MASK', + 'RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__RESERVED_MASK', + 'RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT', + 'RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_F32_CNTL__ENABLE_MASK', + 'RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT', + 'RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE_MASK', + 'RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE__SHIFT', + 'RLC_GPU_IOV_F32_RESET__RESET_MASK', + 'RLC_GPU_IOV_F32_RESET__RESET__SHIFT', + 'RLC_GPU_IOV_INT_DISABLE__DISABLE_INT_MASK', + 'RLC_GPU_IOV_INT_DISABLE__DISABLE_INT__SHIFT', + 'RLC_GPU_IOV_INT_FORCE__FORCE_INT_MASK', + 'RLC_GPU_IOV_INT_FORCE__FORCE_INT__SHIFT', + 'RLC_GPU_IOV_INT_STAT__STATUS_MASK', + 'RLC_GPU_IOV_INT_STAT__STATUS__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT', + 'RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK', + 'RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT', + 'RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK', + 'RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT', + 'RLC_GPU_IOV_SCH_1__DATA_MASK', 'RLC_GPU_IOV_SCH_1__DATA__SHIFT', + 'RLC_GPU_IOV_SCH_2__DATA_MASK', 'RLC_GPU_IOV_SCH_2__DATA__SHIFT', + 'RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK', + 'RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT', + 'RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK', + 'RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT', + 'RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK', + 'RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT', + 'RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK', + 'RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT', + 'RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK', + 'RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT', + 'RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK', + 'RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT', + 'RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK', + 'RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK', + 'RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT', + 'RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK', + 'RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT', + 'RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK', + 'RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT', + 'RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK', + 'RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT', + 'RLC_GPU_IOV_VF_MASK__VF_MASK_MASK', + 'RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT', + 'RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GTS_OFFSET_LSB__DATA_MASK', + 'RLC_GTS_OFFSET_LSB__DATA__SHIFT', + 'RLC_GTS_OFFSET_MSB__DATA_MASK', + 'RLC_GTS_OFFSET_MSB__DATA__SHIFT', + 'RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_0__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT', + 'RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_1__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT', + 'RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_2__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT', + 'RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_3__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT', + 'RLC_IH_COOKIE_CNTL__CREDIT_MASK', + 'RLC_IH_COOKIE_CNTL__CREDIT__SHIFT', + 'RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK', + 'RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT', + 'RLC_IH_COOKIE__DATA_MASK', 'RLC_IH_COOKIE__DATA__SHIFT', + 'RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI_MASK', + 'RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT', + 'RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO_MASK', + 'RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT', + 'RLC_IMU_BOOTLOAD_SIZE__RESERVED_MASK', + 'RLC_IMU_BOOTLOAD_SIZE__RESERVED__SHIFT', + 'RLC_IMU_BOOTLOAD_SIZE__SIZE_MASK', + 'RLC_IMU_BOOTLOAD_SIZE__SIZE__SHIFT', + 'RLC_IMU_MISC__EARLY_MGCG_MASK', + 'RLC_IMU_MISC__EARLY_MGCG__SHIFT', 'RLC_IMU_MISC__RESERVED_MASK', + 'RLC_IMU_MISC__RESERVED__SHIFT', + 'RLC_IMU_MISC__THROTTLE_GFX_MASK', + 'RLC_IMU_MISC__THROTTLE_GFX__SHIFT', + 'RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT_MASK', + 'RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT', + 'RLC_IMU_RESET_VECTOR__RESERVED_MASK', + 'RLC_IMU_RESET_VECTOR__RESERVED__SHIFT', + 'RLC_IMU_RESET_VECTOR__VDDGFX_EXIT_MASK', + 'RLC_IMU_RESET_VECTOR__VDDGFX_EXIT__SHIFT', + 'RLC_IMU_RESET_VECTOR__VECTOR_MASK', + 'RLC_IMU_RESET_VECTOR__VECTOR__SHIFT', + 'RLC_INT_STAT__CP_RLC_INT_PENDING_MASK', + 'RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT', + 'RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK', + 'RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT', + 'RLC_INT_STAT__RESERVED_MASK', 'RLC_INT_STAT__RESERVED__SHIFT', + 'RLC_JUMP_TABLE_RESTORE__ADDR_MASK', + 'RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT', + 'RLC_LX6_CNTL__BRESET_MASK', 'RLC_LX6_CNTL__BRESET__SHIFT', + 'RLC_LX6_CNTL__PDEBUG_ENABLE_MASK', + 'RLC_LX6_CNTL__PDEBUG_ENABLE__SHIFT', + 'RLC_LX6_CNTL__RUNSTALL_MASK', 'RLC_LX6_CNTL__RUNSTALL__SHIFT', + 'RLC_LX6_CNTL__STAT_VECTOR_SEL_MASK', + 'RLC_LX6_CNTL__STAT_VECTOR_SEL__SHIFT', + 'RLC_LX6_DRAM_ADDR__ADDR_MASK', 'RLC_LX6_DRAM_ADDR__ADDR__SHIFT', + 'RLC_LX6_DRAM_DATA__DATA_MASK', 'RLC_LX6_DRAM_DATA__DATA__SHIFT', + 'RLC_LX6_IRAM_ADDR__ADDR_MASK', 'RLC_LX6_IRAM_ADDR__ADDR__SHIFT', + 'RLC_LX6_IRAM_DATA__DATA_MASK', 'RLC_LX6_IRAM_DATA__DATA__SHIFT', + 'RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK', + 'RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT', + 'RLC_MAX_PG_WGP__SPARE_MASK', 'RLC_MAX_PG_WGP__SPARE__SHIFT', + 'RLC_MEM_SLP_CNTL__RESERVED1_MASK', + 'RLC_MEM_SLP_CNTL__RESERVED1__SHIFT', + 'RLC_MEM_SLP_CNTL__RESERVED_MASK', + 'RLC_MEM_SLP_CNTL__RESERVED__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE__SHIFT', + 'RLC_MGCG_CTRL__MGCG_EN_MASK', 'RLC_MGCG_CTRL__MGCG_EN__SHIFT', + 'RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK', + 'RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT', + 'RLC_MGCG_CTRL__ON_DELAY_MASK', 'RLC_MGCG_CTRL__ON_DELAY__SHIFT', + 'RLC_MGCG_CTRL__SILICON_EN_MASK', + 'RLC_MGCG_CTRL__SILICON_EN__SHIFT', + 'RLC_MGCG_CTRL__SIMULATION_EN_MASK', + 'RLC_MGCG_CTRL__SIMULATION_EN__SHIFT', + 'RLC_MGCG_CTRL__SPARE_MASK', 'RLC_MGCG_CTRL__SPARE__SHIFT', + 'RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR_MASK', + 'RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR__SHIFT', + 'RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR_MASK', + 'RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR__SHIFT', + 'RLC_PACE_INT_DISABLE__DISABLE_INT_MASK', + 'RLC_PACE_INT_DISABLE__DISABLE_INT__SHIFT', + 'RLC_PACE_INT_FORCE__FORCE_INT_MASK', + 'RLC_PACE_INT_FORCE__FORCE_INT__SHIFT', + 'RLC_PACE_INT_STAT__STATUS_MASK', + 'RLC_PACE_INT_STAT__STATUS__SHIFT', + 'RLC_PACE_SCRATCH_ADDR__ADDR_MASK', + 'RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT', + 'RLC_PACE_SCRATCH_DATA__DATA_MASK', + 'RLC_PACE_SCRATCH_DATA__DATA__SHIFT', + 'RLC_PACE_SPARE_INT_1__INTERRUPT_MASK', + 'RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT', + 'RLC_PACE_SPARE_INT_1__RESERVED_MASK', + 'RLC_PACE_SPARE_INT_1__RESERVED__SHIFT', + 'RLC_PACE_SPARE_INT__INTERRUPT_MASK', + 'RLC_PACE_SPARE_INT__INTERRUPT__SHIFT', + 'RLC_PACE_SPARE_INT__RESERVED_MASK', + 'RLC_PACE_SPARE_INT__RESERVED__SHIFT', + 'RLC_PACE_TIMER_CTRL__RESERVED_MASK', + 'RLC_PACE_TIMER_CTRL__RESERVED__SHIFT', + 'RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK', + 'RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT', + 'RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK', + 'RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT', + 'RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK', + 'RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT', + 'RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK', + 'RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT', + 'RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK', + 'RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT', + 'RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK', + 'RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT', + 'RLC_PACE_TIMER_INT_0__TIMER_MASK', + 'RLC_PACE_TIMER_INT_0__TIMER__SHIFT', + 'RLC_PACE_TIMER_INT_1__TIMER_MASK', + 'RLC_PACE_TIMER_INT_1__TIMER__SHIFT', + 'RLC_PACE_TIMER_STAT__RESERVED_MASK', + 'RLC_PACE_TIMER_STAT__RESERVED__SHIFT', + 'RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK', + 'RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT', + 'RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK', + 'RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT', + 'RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK', + 'RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT', + 'RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK', + 'RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT', + 'RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK', + 'RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT', + 'RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK', + 'RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT', + 'RLC_PACE_UCODE_ADDR__RESERVED_MASK', + 'RLC_PACE_UCODE_ADDR__RESERVED__SHIFT', + 'RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK', + 'RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'RLC_PACE_UCODE_DATA__UCODE_DATA_MASK', + 'RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_MASK', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL_MASK', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL__SHIFT', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED_MASK', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_MASK', + 'RLC_PCC_RESIDENCY_CNTR_CTRL__RESET__SHIFT', + 'RLC_PCC_RESIDENCY_EVENT_CNTR__DATA_MASK', + 'RLC_PCC_RESIDENCY_EVENT_CNTR__DATA__SHIFT', + 'RLC_PCC_RESIDENCY_REF_CNTR__DATA_MASK', + 'RLC_PCC_RESIDENCY_REF_CNTR__DATA__SHIFT', + 'RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK', + 'RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT', + 'RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK', + 'RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT', + 'RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK', + 'RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT', + 'RLC_PERFMON_CNTL__PERFMON_STATE_MASK', + 'RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT', + 'RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK', + 'RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT', + 'RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK', + 'RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT', + 'RLC_PG_CNTL__CP_PG_DISABLE_MASK', + 'RLC_PG_CNTL__CP_PG_DISABLE__SHIFT', + 'RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK', + 'RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT', + 'RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK', + 'RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT', + 'RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK', + 'RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT', + 'RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK', + 'RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT', + 'RLC_PG_CNTL__MEM_DS_DISABLE_MASK', + 'RLC_PG_CNTL__MEM_DS_DISABLE__SHIFT', + 'RLC_PG_CNTL__PG_OVERRIDE_MASK', + 'RLC_PG_CNTL__PG_OVERRIDE__SHIFT', 'RLC_PG_CNTL__RESERVED1_MASK', + 'RLC_PG_CNTL__RESERVED1__SHIFT', 'RLC_PG_CNTL__RESERVED2_MASK', + 'RLC_PG_CNTL__RESERVED2__SHIFT', 'RLC_PG_CNTL__RESERVED_MASK', + 'RLC_PG_CNTL__RESERVED__SHIFT', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT', + 'RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK', + 'RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT', + 'RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK', + 'RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT', + 'RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK', + 'RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT', + 'RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK', + 'RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT', + 'RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK', + 'RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT', + 'RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK', + 'RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT', + 'RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK', + 'RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT', + 'RLC_PG_DELAY_3__RESERVED_MASK', + 'RLC_PG_DELAY_3__RESERVED__SHIFT', + 'RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK', + 'RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT', + 'RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK', + 'RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT', + 'RLC_PG_DELAY__POWER_DOWN_DELAY_MASK', + 'RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT', + 'RLC_PG_DELAY__POWER_UP_DELAY_MASK', + 'RLC_PG_DELAY__POWER_UP_DELAY__SHIFT', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_MASK', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED_MASK', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_MASK', + 'RLC_POWER_RESIDENCY_CNTR_CTRL__RESET__SHIFT', + 'RLC_POWER_RESIDENCY_EVENT_CNTR__DATA_MASK', + 'RLC_POWER_RESIDENCY_EVENT_CNTR__DATA__SHIFT', + 'RLC_POWER_RESIDENCY_REF_CNTR__DATA_MASK', + 'RLC_POWER_RESIDENCY_REF_CNTR__DATA__SHIFT', + 'RLC_R2I_CNTL_0__Data_MASK', 'RLC_R2I_CNTL_0__Data__SHIFT', + 'RLC_R2I_CNTL_1__Data_MASK', 'RLC_R2I_CNTL_1__Data__SHIFT', + 'RLC_R2I_CNTL_2__Data_MASK', 'RLC_R2I_CNTL_2__Data__SHIFT', + 'RLC_R2I_CNTL_3__Data_MASK', 'RLC_R2I_CNTL_3__Data__SHIFT', + 'RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK', + 'RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT', + 'RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK', + 'RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT', + 'RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK', + 'RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK', + 'RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK', + 'RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK', + 'RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK', + 'RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK', + 'RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK', + 'RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK', + 'RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK', + 'RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT', + 'RLC_RLCG_DOORBELL_CNTL__RESERVED_MASK', + 'RLC_RLCG_DOORBELL_CNTL__RESERVED__SHIFT', + 'RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK', + 'RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK', + 'RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT', + 'RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT', + 'RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK', + 'RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK', + 'RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT', + 'RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK', + 'RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT', + 'RLC_RLCP_DOORBELL_0_DATA_HI__DATA_MASK', + 'RLC_RLCP_DOORBELL_0_DATA_HI__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_0_DATA_LO__DATA_MASK', + 'RLC_RLCP_DOORBELL_0_DATA_LO__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_1_DATA_HI__DATA_MASK', + 'RLC_RLCP_DOORBELL_1_DATA_HI__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_1_DATA_LO__DATA_MASK', + 'RLC_RLCP_DOORBELL_1_DATA_LO__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_2_DATA_HI__DATA_MASK', + 'RLC_RLCP_DOORBELL_2_DATA_HI__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_2_DATA_LO__DATA_MASK', + 'RLC_RLCP_DOORBELL_2_DATA_LO__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_3_DATA_HI__DATA_MASK', + 'RLC_RLCP_DOORBELL_3_DATA_HI__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_3_DATA_LO__DATA_MASK', + 'RLC_RLCP_DOORBELL_3_DATA_LO__DATA__SHIFT', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE_MASK', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE_MASK', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE_MASK', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE_MASK', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN_MASK', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_MASK', + 'RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID__SHIFT', + 'RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_MASK', + 'RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK', + 'RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT', + 'RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR__SHIFT', + 'RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_MASK', + 'RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK', + 'RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT', + 'RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR__SHIFT', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID_MASK', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID_MASK', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID_MASK', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID_MASK', + 'RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT', + 'RLC_RLCP_IRAM_ADDR__ADDR_MASK', + 'RLC_RLCP_IRAM_ADDR__ADDR__SHIFT', + 'RLC_RLCP_IRAM_DATA__DATA_MASK', + 'RLC_RLCP_IRAM_DATA__DATA__SHIFT', + 'RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK', + 'RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT', + 'RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK', + 'RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK', + 'RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK', + 'RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK', + 'RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK', + 'RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK', + 'RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK', + 'RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK', + 'RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT', + 'RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK', + 'RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT', + 'RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK', + 'RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT', + 'RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE_MASK', + 'RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE__SHIFT', + 'RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK', + 'RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT', + 'RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE_MASK', + 'RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE__SHIFT', + 'RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED_MASK', + 'RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED__SHIFT', + 'RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK', + 'RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT', + 'RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK', + 'RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT', + 'RLC_RLCS_CGCG_REQUEST__RESERVED_MASK', + 'RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT', + 'RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK', + 'RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT', + 'RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK', + 'RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT', + 'RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK', + 'RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT', + 'RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK', + 'RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT', + 'RLC_RLCS_CGCG_STATUS__RESERVED_MASK', + 'RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT', + 'RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK', + 'RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT', + 'RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK', + 'RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT', + 'RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK', + 'RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT', + 'RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK', + 'RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT', + 'RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK', + 'RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT', + 'RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK', + 'RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK', + 'RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK', + 'RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK', + 'RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE_MASK', + 'RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK', + 'RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE_MASK', + 'RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK', + 'RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING_MASK', + 'RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING__SHIFT', + 'RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK', + 'RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT', + 'RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK', + 'RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT', + 'RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK', + 'RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT', + 'RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK', + 'RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT', + 'RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK', + 'RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT', + 'RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK', + 'RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT', + 'RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK', + 'RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT', + 'RLC_RLCS_DIDT_FORCE_STALL__VALID_MASK', + 'RLC_RLCS_DIDT_FORCE_STALL__VALID__SHIFT', + 'RLC_RLCS_DSM_TRIG__RESERVED_MASK', + 'RLC_RLCS_DSM_TRIG__RESERVED__SHIFT', + 'RLC_RLCS_DSM_TRIG__START_MASK', + 'RLC_RLCS_DSM_TRIG__START__SHIFT', + 'RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK', + 'RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK', + 'RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK', + 'RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK', + 'RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK', + 'RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK', + 'RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK', + 'RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK', + 'RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT', + 'RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK', + 'RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT', + 'RLC_RLCS_GCR_DATA_0__PHASE_0_MASK', + 'RLC_RLCS_GCR_DATA_0__PHASE_0__SHIFT', + 'RLC_RLCS_GCR_DATA_0__PHASE_1_MASK', + 'RLC_RLCS_GCR_DATA_0__PHASE_1__SHIFT', + 'RLC_RLCS_GCR_DATA_1__PHASE_2_MASK', + 'RLC_RLCS_GCR_DATA_1__PHASE_2__SHIFT', + 'RLC_RLCS_GCR_DATA_1__PHASE_3_MASK', + 'RLC_RLCS_GCR_DATA_1__PHASE_3__SHIFT', + 'RLC_RLCS_GCR_DATA_2__PHASE_4_MASK', + 'RLC_RLCS_GCR_DATA_2__PHASE_4__SHIFT', + 'RLC_RLCS_GCR_DATA_2__PHASE_5_MASK', + 'RLC_RLCS_GCR_DATA_2__PHASE_5__SHIFT', + 'RLC_RLCS_GCR_DATA_3__PHASE_6_MASK', + 'RLC_RLCS_GCR_DATA_3__PHASE_6__SHIFT', + 'RLC_RLCS_GCR_DATA_3__PHASE_7_MASK', + 'RLC_RLCS_GCR_DATA_3__PHASE_7__SHIFT', + 'RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG_MASK', + 'RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG__SHIFT', + 'RLC_RLCS_GCR_STATUS__GCR_BUSY_MASK', + 'RLC_RLCS_GCR_STATUS__GCR_BUSY__SHIFT', + 'RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT_MASK', + 'RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT__SHIFT', + 'RLC_RLCS_GCR_STATUS__RESERVED_2_MASK', + 'RLC_RLCS_GCR_STATUS__RESERVED_2__SHIFT', + 'RLC_RLCS_GCR_STATUS__RESERVED_MASK', + 'RLC_RLCS_GCR_STATUS__RESERVED__SHIFT', + 'RLC_RLCS_GENERAL_0__DATA_MASK', + 'RLC_RLCS_GENERAL_0__DATA__SHIFT', + 'RLC_RLCS_GENERAL_10__DATA_MASK', + 'RLC_RLCS_GENERAL_10__DATA__SHIFT', + 'RLC_RLCS_GENERAL_11__DATA_MASK', + 'RLC_RLCS_GENERAL_11__DATA__SHIFT', + 'RLC_RLCS_GENERAL_12__DATA_MASK', + 'RLC_RLCS_GENERAL_12__DATA__SHIFT', + 'RLC_RLCS_GENERAL_13__DATA_MASK', + 'RLC_RLCS_GENERAL_13__DATA__SHIFT', + 'RLC_RLCS_GENERAL_14__DATA_MASK', + 'RLC_RLCS_GENERAL_14__DATA__SHIFT', + 'RLC_RLCS_GENERAL_15__DATA_MASK', + 'RLC_RLCS_GENERAL_15__DATA__SHIFT', + 'RLC_RLCS_GENERAL_16__DATA_MASK', + 'RLC_RLCS_GENERAL_16__DATA__SHIFT', + 'RLC_RLCS_GENERAL_1__DATA_MASK', + 'RLC_RLCS_GENERAL_1__DATA__SHIFT', + 'RLC_RLCS_GENERAL_2__DATA_MASK', + 'RLC_RLCS_GENERAL_2__DATA__SHIFT', + 'RLC_RLCS_GENERAL_3__DATA_MASK', + 'RLC_RLCS_GENERAL_3__DATA__SHIFT', + 'RLC_RLCS_GENERAL_4__DATA_MASK', + 'RLC_RLCS_GENERAL_4__DATA__SHIFT', + 'RLC_RLCS_GENERAL_5__DATA_MASK', + 'RLC_RLCS_GENERAL_5__DATA__SHIFT', + 'RLC_RLCS_GENERAL_6__DATA_MASK', + 'RLC_RLCS_GENERAL_6__DATA__SHIFT', + 'RLC_RLCS_GENERAL_7__DATA_MASK', + 'RLC_RLCS_GENERAL_7__DATA__SHIFT', + 'RLC_RLCS_GENERAL_8__DATA_MASK', + 'RLC_RLCS_GENERAL_8__DATA__SHIFT', + 'RLC_RLCS_GENERAL_9__DATA_MASK', + 'RLC_RLCS_GENERAL_9__DATA__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK', + 'RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT', + 'RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA_MASK', + 'RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA__SHIFT', + 'RLC_RLCS_GFX_RM_CNTL__RESERVED_MASK', + 'RLC_RLCS_GFX_RM_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK', + 'RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT', + 'RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED_MASK', + 'RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED__SHIFT', + 'RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED_MASK', + 'RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED__SHIFT', + 'RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED_MASK', + 'RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED__SHIFT', + 'RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED_MASK', + 'RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED__SHIFT', + 'RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK', + 'RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK', + 'RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK', + 'RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT_2__RESERVED_MASK', + 'RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT', + 'RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK', + 'RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT', + 'RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK', + 'RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT', + 'RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK', + 'RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT', + 'RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK', + 'RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT', + 'RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK', + 'RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT', + 'RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK', + 'RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT', + 'RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK', + 'RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT', + 'RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK', + 'RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT', + 'RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK', + 'RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT', + 'RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK', + 'RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK', + 'RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK', + 'RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK', + 'RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK', + 'RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT', + 'RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK', + 'RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT', + 'RLC_RLCS_GPM_STAT__RLC_BUSY_MASK', + 'RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT', + 'RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK', + 'RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT', + 'RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK', + 'RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT', + 'RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK', + 'RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT', + 'RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK', + 'RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK', + 'RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT', + 'RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK', + 'RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT', + 'RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK', + 'RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT', + 'RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK', + 'RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT', + 'RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK', + 'RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT', + 'RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK', + 'RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT', + 'RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK', + 'RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT', + 'RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK_MASK', + 'RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK__SHIFT', + 'RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE_MASK', + 'RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE__SHIFT', + 'RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED_MASK', + 'RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA_MASK', + 'RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA__SHIFT', + 'RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA_MASK', + 'RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA__SHIFT', + 'RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED_MASK', + 'RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA_MASK', + 'RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA__SHIFT', + 'RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA_MASK', + 'RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA__SHIFT', + 'RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED_MASK', + 'RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RAM_CNTL__ACKTOG_MASK', + 'RLC_RLCS_IMU_RAM_CNTL__ACKTOG__SHIFT', + 'RLC_RLCS_IMU_RAM_CNTL__REQTOG_MASK', + 'RLC_RLCS_IMU_RAM_CNTL__REQTOG__SHIFT', + 'RLC_RLCS_IMU_RAM_CNTL__RESERVED_MASK', + 'RLC_RLCS_IMU_RAM_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RAM_DATA_0__DATA_MASK', + 'RLC_RLCS_IMU_RAM_DATA_0__DATA__SHIFT', + 'RLC_RLCS_IMU_RAM_DATA_1__DATA_MASK', + 'RLC_RLCS_IMU_RAM_DATA_1__DATA__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG_MASK', + 'RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG_MASK', + 'RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED_MASK', + 'RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA_MASK', + 'RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_DATA0__DATA_MASK', + 'RLC_RLCS_IMU_RLC_MSG_DATA0__DATA__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_DATA1__DATA_MASK', + 'RLC_RLCS_IMU_RLC_MSG_DATA1__DATA__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_DATA2__DATA_MASK', + 'RLC_RLCS_IMU_RLC_MSG_DATA2__DATA__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_DATA3__DATA_MASK', + 'RLC_RLCS_IMU_RLC_MSG_DATA3__DATA__SHIFT', + 'RLC_RLCS_IMU_RLC_MSG_DATA4__DATA_MASK', + 'RLC_RLCS_IMU_RLC_MSG_DATA4__DATA__SHIFT', + 'RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE_MASK', + 'RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE__SHIFT', + 'RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ_MASK', + 'RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ__SHIFT', + 'RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED_MASK', + 'RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS_MASK', + 'RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS__SHIFT', + 'RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF_MASK', + 'RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF__SHIFT', + 'RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS_MASK', + 'RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS__SHIFT', + 'RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2_MASK', + 'RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2__SHIFT', + 'RLC_RLCS_IMU_RLC_STATUS__RESERVED_MASK', + 'RLC_RLCS_IMU_RLC_STATUS__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT_MASK', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT__SHIFT', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE_MASK', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE__SHIFT', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED_MASK', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED__SHIFT', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1_MASK', + 'RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1__SHIFT', + 'RLC_RLCS_IMU_VIDCHG_CNTL__ACK_MASK', + 'RLC_RLCS_IMU_VIDCHG_CNTL__ACK__SHIFT', + 'RLC_RLCS_IMU_VIDCHG_CNTL__DATA_MASK', + 'RLC_RLCS_IMU_VIDCHG_CNTL__DATA__SHIFT', + 'RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN_MASK', + 'RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN__SHIFT', + 'RLC_RLCS_IMU_VIDCHG_CNTL__REQ_MASK', + 'RLC_RLCS_IMU_VIDCHG_CNTL__REQ__SHIFT', + 'RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED_MASK', + 'RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_IOV_CMD_STATUS__DATA_MASK', + 'RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT', + 'RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK', + 'RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT', + 'RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK', + 'RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT', + 'RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK', + 'RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT', + 'RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK', + 'RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT', + 'RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK', + 'RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT', + 'RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK', + 'RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT', + 'RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK', + 'RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT', + 'RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK', + 'RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT', + 'RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK', + 'RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT', + 'RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK', + 'RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT', + 'RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK', + 'RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT', + 'RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK', + 'RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT', + 'RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK', + 'RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT', + 'RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK', + 'RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT', + 'RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK', + 'RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT', + 'RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK', + 'RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT', + 'RLC_RLCS_PMM_CGCG_CNTL__CLEAN_MASK', + 'RLC_RLCS_PMM_CGCG_CNTL__CLEAN__SHIFT', + 'RLC_RLCS_PMM_CGCG_CNTL__RESERVED_MASK', + 'RLC_RLCS_PMM_CGCG_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_PMM_CGCG_CNTL__VALID_MASK', + 'RLC_RLCS_PMM_CGCG_CNTL__VALID__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT', + 'RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK', + 'RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG_MASK', + 'RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG__SHIFT', + 'RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG_MASK', + 'RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG__SHIFT', + 'RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED_MASK', + 'RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA_MASK', + 'RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA__SHIFT', + 'RLC_RLCS_RLC_IMU_MSG_DATA0__DATA_MASK', + 'RLC_RLCS_RLC_IMU_MSG_DATA0__DATA__SHIFT', + 'RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE_MASK', + 'RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE__SHIFT', + 'RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2_MASK', + 'RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2__SHIFT', + 'RLC_RLCS_RLC_IMU_STATUS__RESERVED_MASK', + 'RLC_RLCS_RLC_IMU_STATUS__RESERVED__SHIFT', + 'RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE_MASK', + 'RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE__SHIFT', + 'RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK_MASK', + 'RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK__SHIFT', + 'RLC_RLCS_SDMA_INT_CNTL_1__RESERVED_MASK', + 'RLC_RLCS_SDMA_INT_CNTL_1__RESERVED__SHIFT', + 'RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID_MASK', + 'RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID__SHIFT', + 'RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE_MASK', + 'RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE__SHIFT', + 'RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN_MASK', + 'RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN__SHIFT', + 'RLC_RLCS_SDMA_INT_CNTL_2__RESERVED_MASK', + 'RLC_RLCS_SDMA_INT_CNTL_2__RESERVED__SHIFT', + 'RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID_MASK', + 'RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID__SHIFT', + 'RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW_MASK', + 'RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW__SHIFT', + 'RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW_MASK', + 'RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW__SHIFT', + 'RLC_RLCS_SDMA_INT_INFO__RESERVED_MASK', + 'RLC_RLCS_SDMA_INT_INFO__RESERVED__SHIFT', + 'RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID_MASK', + 'RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID__SHIFT', + 'RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST_MASK', + 'RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST__SHIFT', + 'RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST_MASK', + 'RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST__SHIFT', + 'RLC_RLCS_SDMA_INT_STAT__RESERVED_MASK', + 'RLC_RLCS_SDMA_INT_STAT__RESERVED__SHIFT', + 'RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING_MASK', + 'RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK', + 'RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT', + 'RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK', + 'RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT', + 'RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK', + 'RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT', + 'RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK', + 'RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT', + 'RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK', + 'RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT', + 'RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK', + 'RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT', + 'RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK', + 'RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT', + 'RLC_RLCS_SPM_SQTT_MODE__MODE_MASK', + 'RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT', + 'RLC_RLCS_SRM_SRCID_CNTL__SRCID_MASK', + 'RLC_RLCS_SRM_SRCID_CNTL__SRCID__SHIFT', + 'RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK', + 'RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK', + 'RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT', + 'RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT', + 'RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'RLC_RLCS_UTCL2_CNTL__RESERVED_MASK', + 'RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT', + 'RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK', + 'RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK', + 'RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT', + 'RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT', + 'RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK', + 'RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT', + 'RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK', + 'RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT', + 'RLC_RLCS_WGP_READ__RESERVED_MASK', + 'RLC_RLCS_WGP_READ__RESERVED__SHIFT', + 'RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK', + 'RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT', + 'RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK', + 'RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT', + 'RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK', + 'RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT', + 'RLC_RLCS_WGP_STATUS__RESERVED_MASK', + 'RLC_RLCS_WGP_STATUS__RESERVED__SHIFT', + 'RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK', + 'RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT', + 'RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK', + 'RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT', + 'RLC_RLCV_COMMAND__CMD_MASK', 'RLC_RLCV_COMMAND__CMD__SHIFT', + 'RLC_RLCV_COMMAND__RESERVED_MASK', + 'RLC_RLCV_COMMAND__RESERVED__SHIFT', + 'RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK', + 'RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK', + 'RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK', + 'RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK', + 'RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK', + 'RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK', + 'RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK', + 'RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK', + 'RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK', + 'RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT', + 'RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK', + 'RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK', + 'RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT', + 'RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT', + 'RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK', + 'RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK', + 'RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT', + 'RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK', + 'RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT', + 'RLC_RLCV_IRAM_ADDR__ADDR_MASK', + 'RLC_RLCV_IRAM_ADDR__ADDR__SHIFT', + 'RLC_RLCV_IRAM_DATA__DATA_MASK', + 'RLC_RLCV_IRAM_DATA__DATA__SHIFT', 'RLC_RLCV_SAFE_MODE__CMD_MASK', + 'RLC_RLCV_SAFE_MODE__CMD__SHIFT', + 'RLC_RLCV_SAFE_MODE__MESSAGE_MASK', + 'RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT', + 'RLC_RLCV_SAFE_MODE__RESERVED1_MASK', + 'RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT', + 'RLC_RLCV_SAFE_MODE__RESERVED_MASK', + 'RLC_RLCV_SAFE_MODE__RESERVED__SHIFT', + 'RLC_RLCV_SAFE_MODE__RESPONSE_MASK', + 'RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT', + 'RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK', + 'RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT', + 'RLC_RLCV_SPARE_INT_1__RESERVED_MASK', + 'RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT', + 'RLC_RLCV_SPARE_INT__INTERRUPT_MASK', + 'RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT', + 'RLC_RLCV_SPARE_INT__RESERVED_MASK', + 'RLC_RLCV_SPARE_INT__RESERVED__SHIFT', + 'RLC_RLCV_TIMER_CTRL__RESERVED_MASK', + 'RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT', + 'RLC_RLCV_TIMER_INT_0__TIMER_MASK', + 'RLC_RLCV_TIMER_INT_0__TIMER__SHIFT', + 'RLC_RLCV_TIMER_INT_1__TIMER_MASK', + 'RLC_RLCV_TIMER_INT_1__TIMER__SHIFT', + 'RLC_RLCV_TIMER_STAT__RESERVED_MASK', + 'RLC_RLCV_TIMER_STAT__RESERVED__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT', + 'RLC_SAFE_MODE__CMD_MASK', 'RLC_SAFE_MODE__CMD__SHIFT', + 'RLC_SAFE_MODE__MESSAGE_MASK', 'RLC_SAFE_MODE__MESSAGE__SHIFT', + 'RLC_SAFE_MODE__RESERVED1_MASK', + 'RLC_SAFE_MODE__RESERVED1__SHIFT', 'RLC_SAFE_MODE__RESERVED_MASK', + 'RLC_SAFE_MODE__RESERVED__SHIFT', 'RLC_SAFE_MODE__RESPONSE_MASK', + 'RLC_SAFE_MODE__RESPONSE__SHIFT', + 'RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK', + 'RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT', + 'RLC_SDMA0_STATUS__STATUS_MASK', + 'RLC_SDMA0_STATUS__STATUS__SHIFT', + 'RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK', + 'RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT', + 'RLC_SDMA1_STATUS__STATUS_MASK', + 'RLC_SDMA1_STATUS__STATUS__SHIFT', + 'RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK', + 'RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT', + 'RLC_SDMA2_STATUS__STATUS_MASK', + 'RLC_SDMA2_STATUS__STATUS__SHIFT', + 'RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK', + 'RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT', + 'RLC_SDMA3_STATUS__STATUS_MASK', + 'RLC_SDMA3_STATUS__STATUS__SHIFT', + 'RLC_SEMAPHORE_0__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_0__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_0__RESERVED_MASK', + 'RLC_SEMAPHORE_0__RESERVED__SHIFT', + 'RLC_SEMAPHORE_1__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_1__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_1__RESERVED_MASK', + 'RLC_SEMAPHORE_1__RESERVED__SHIFT', + 'RLC_SEMAPHORE_2__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_2__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_2__RESERVED_MASK', + 'RLC_SEMAPHORE_2__RESERVED__SHIFT', + 'RLC_SEMAPHORE_3__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_3__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_3__RESERVED_MASK', + 'RLC_SEMAPHORE_3__RESERVED__SHIFT', + 'RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK', + 'RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT', + 'RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK', + 'RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_0_MASK', + 'RLC_SERDES_BUSY__GC_SE_0__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_1_MASK', + 'RLC_SERDES_BUSY__GC_SE_1__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_2_MASK', + 'RLC_SERDES_BUSY__GC_SE_2__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_3_MASK', + 'RLC_SERDES_BUSY__GC_SE_3__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_4_MASK', + 'RLC_SERDES_BUSY__GC_SE_4__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_5_MASK', + 'RLC_SERDES_BUSY__GC_SE_5__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_6_MASK', + 'RLC_SERDES_BUSY__GC_SE_6__SHIFT', + 'RLC_SERDES_BUSY__GC_SE_7_MASK', + 'RLC_SERDES_BUSY__GC_SE_7__SHIFT', + 'RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK', + 'RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT', + 'RLC_SERDES_BUSY__RD_PENDING_MASK', + 'RLC_SERDES_BUSY__RD_PENDING__SHIFT', + 'RLC_SERDES_BUSY__RESERVED_29_24_MASK', + 'RLC_SERDES_BUSY__RESERVED_29_24__SHIFT', + 'RLC_SERDES_BUSY__RESERVED_MASK', + 'RLC_SERDES_BUSY__RESERVED__SHIFT', + 'RLC_SERDES_CTRL__BPM_ADDR_MASK', + 'RLC_SERDES_CTRL__BPM_ADDR__SHIFT', + 'RLC_SERDES_CTRL__BPM_BROADCAST_MASK', + 'RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT', + 'RLC_SERDES_CTRL__BPM_LONG_CMD_MASK', + 'RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT', + 'RLC_SERDES_CTRL__BPM_REG_WRITE_MASK', + 'RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT', + 'RLC_SERDES_CTRL__REG_ADDR_MASK', + 'RLC_SERDES_CTRL__REG_ADDR__SHIFT', 'RLC_SERDES_DATA__DATA_MASK', + 'RLC_SERDES_DATA__DATA__SHIFT', + 'RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK', + 'RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT', + 'RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK', + 'RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT', + 'RLC_SERDES_MASK__GC_SE_0_MASK', + 'RLC_SERDES_MASK__GC_SE_0__SHIFT', + 'RLC_SERDES_MASK__GC_SE_1_MASK', + 'RLC_SERDES_MASK__GC_SE_1__SHIFT', + 'RLC_SERDES_MASK__GC_SE_2_MASK', + 'RLC_SERDES_MASK__GC_SE_2__SHIFT', + 'RLC_SERDES_MASK__GC_SE_3_MASK', + 'RLC_SERDES_MASK__GC_SE_3__SHIFT', + 'RLC_SERDES_MASK__GC_SE_4_MASK', + 'RLC_SERDES_MASK__GC_SE_4__SHIFT', + 'RLC_SERDES_MASK__GC_SE_5_MASK', + 'RLC_SERDES_MASK__GC_SE_5__SHIFT', + 'RLC_SERDES_MASK__GC_SE_6_MASK', + 'RLC_SERDES_MASK__GC_SE_6__SHIFT', + 'RLC_SERDES_MASK__GC_SE_7_MASK', + 'RLC_SERDES_MASK__GC_SE_7__SHIFT', + 'RLC_SERDES_MASK__RESERVED_31_24_MASK', + 'RLC_SERDES_MASK__RESERVED_31_24__SHIFT', + 'RLC_SERDES_MASK__RESERVED_MASK', + 'RLC_SERDES_MASK__RESERVED__SHIFT', + 'RLC_SERDES_RD_DATA_0__DATA_MASK', + 'RLC_SERDES_RD_DATA_0__DATA__SHIFT', + 'RLC_SERDES_RD_DATA_1__DATA_MASK', + 'RLC_SERDES_RD_DATA_1__DATA__SHIFT', + 'RLC_SERDES_RD_DATA_2__DATA_MASK', + 'RLC_SERDES_RD_DATA_2__DATA__SHIFT', + 'RLC_SERDES_RD_DATA_3__DATA_MASK', + 'RLC_SERDES_RD_DATA_3__DATA__SHIFT', + 'RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK', + 'RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT', + 'RLC_SERDES_RD_INDEX__SPARE_MASK', + 'RLC_SERDES_RD_INDEX__SPARE__SHIFT', + 'RLC_SMU_ARGUMENT_1__ARG_MASK', 'RLC_SMU_ARGUMENT_1__ARG__SHIFT', + 'RLC_SMU_ARGUMENT_2__ARG_MASK', 'RLC_SMU_ARGUMENT_2__ARG__SHIFT', + 'RLC_SMU_ARGUMENT_3__ARG_MASK', 'RLC_SMU_ARGUMENT_3__ARG__SHIFT', + 'RLC_SMU_ARGUMENT_4__ARG_MASK', 'RLC_SMU_ARGUMENT_4__ARG__SHIFT', + 'RLC_SMU_ARGUMENT_5__ARG_MASK', 'RLC_SMU_ARGUMENT_5__ARG__SHIFT', + 'RLC_SMU_CLK_REQ__VALID_MASK', 'RLC_SMU_CLK_REQ__VALID__SHIFT', + 'RLC_SMU_COMMAND__CMD_MASK', 'RLC_SMU_COMMAND__CMD__SHIFT', + 'RLC_SMU_MESSAGE_1__CMD_MASK', 'RLC_SMU_MESSAGE_1__CMD__SHIFT', + 'RLC_SMU_MESSAGE_2__CMD_MASK', 'RLC_SMU_MESSAGE_2__CMD__SHIFT', + 'RLC_SMU_MESSAGE__CMD_MASK', 'RLC_SMU_MESSAGE__CMD__SHIFT', + 'RLC_SMU_SAFE_MODE__CMD_MASK', 'RLC_SMU_SAFE_MODE__CMD__SHIFT', + 'RLC_SMU_SAFE_MODE__MESSAGE_MASK', + 'RLC_SMU_SAFE_MODE__MESSAGE__SHIFT', + 'RLC_SMU_SAFE_MODE__RESERVED1_MASK', + 'RLC_SMU_SAFE_MODE__RESERVED1__SHIFT', + 'RLC_SMU_SAFE_MODE__RESERVED_MASK', + 'RLC_SMU_SAFE_MODE__RESERVED__SHIFT', + 'RLC_SMU_SAFE_MODE__RESPONSE_MASK', + 'RLC_SMU_SAFE_MODE__RESPONSE__SHIFT', + 'RLC_SPARE_INT_0__COMPLETE_MASK', + 'RLC_SPARE_INT_0__COMPLETE__SHIFT', 'RLC_SPARE_INT_0__DATA_MASK', + 'RLC_SPARE_INT_0__DATA__SHIFT', + 'RLC_SPARE_INT_0__PROCESSING_MASK', + 'RLC_SPARE_INT_0__PROCESSING__SHIFT', + 'RLC_SPARE_INT_1__COMPLETE_MASK', + 'RLC_SPARE_INT_1__COMPLETE__SHIFT', 'RLC_SPARE_INT_1__DATA_MASK', + 'RLC_SPARE_INT_1__DATA__SHIFT', + 'RLC_SPARE_INT_1__PROCESSING_MASK', + 'RLC_SPARE_INT_1__PROCESSING__SHIFT', + 'RLC_SPARE_INT_2__COMPLETE_MASK', + 'RLC_SPARE_INT_2__COMPLETE__SHIFT', 'RLC_SPARE_INT_2__DATA_MASK', + 'RLC_SPARE_INT_2__DATA__SHIFT', + 'RLC_SPARE_INT_2__PROCESSING_MASK', + 'RLC_SPARE_INT_2__PROCESSING__SHIFT', 'RLC_SPARE__SPARE_MASK', + 'RLC_SPARE__SPARE__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK', + 'RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT', + 'RLC_SPM_ACCUM_CTRL__RESERVED_MASK', + 'RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT', + 'RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK', + 'RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED_MASK', + 'RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK', + 'RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK', + 'RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK', + 'RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK', + 'RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_DATA__data_MASK', + 'RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK', + 'RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT', + 'RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK', + 'RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK', + 'RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT', + 'RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK', + 'RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT', + 'RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK', + 'RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT', + 'RLC_SPM_ACCUM_MODE__EnableAccum_MASK', + 'RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT', + 'RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK', + 'RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT', + 'RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK', + 'RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT', + 'RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE2_LoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE2_LoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE3_LoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE3_LoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE4_LoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE4_LoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE4_SwaLoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE4_SwaLoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE5_LoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE5_LoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SE5_SwaLoadOverride_MASK', + 'RLC_SPM_ACCUM_MODE__SE5_SwaLoadOverride__SHIFT', + 'RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK', + 'RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT', + 'RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK', + 'RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT', + 'RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK', + 'RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT', + 'RLC_SPM_ACCUM_STATUS__AccumArmed_MASK', + 'RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT', + 'RLC_SPM_ACCUM_STATUS__AccumDone_MASK', + 'RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT', + 'RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK', + 'RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT', + 'RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK', + 'RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT', + 'RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK', + 'RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT', + 'RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK', + 'RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT', + 'RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK', + 'RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT', + 'RLC_SPM_ACCUM_STATUS__MultiSampleAborted_MASK', + 'RLC_SPM_ACCUM_STATUS__MultiSampleAborted__SHIFT', + 'RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK', + 'RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT', + 'RLC_SPM_ACCUM_STATUS__RESERVED_MASK', + 'RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK', + 'RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT', + 'RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK', + 'RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT', + 'RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK', + 'RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT', + 'RLC_SPM_ACCUM_STATUS__SpmDone_MASK', + 'RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT', + 'RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK', + 'RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT', + 'RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK', + 'RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT', + 'RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK', + 'RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT', + 'RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK', + 'RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT', + 'RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED_MASK', + 'RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED__SHIFT', + 'RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr_MASK', + 'RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr__SHIFT', + 'RLC_SPM_ACCUM_SWA_DATARAM_DATA__data_MASK', + 'RLC_SPM_ACCUM_SWA_DATARAM_DATA__data__SHIFT', + 'RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK', + 'RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT', + 'RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK', + 'RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT', + 'RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK', + 'RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT', + 'RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR_MASK', + 'RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR__SHIFT', + 'RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA_MASK', + 'RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA__SHIFT', + 'RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR_MASK', + 'RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR__SHIFT', + 'RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0_MASK', + 'RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0__SHIFT', + 'RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1_MASK', + 'RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1__SHIFT', + 'RLC_SPM_INT_CNTL__RESERVED_MASK', + 'RLC_SPM_INT_CNTL__RESERVED__SHIFT', + 'RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK', + 'RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT', + 'RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK', + 'RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT', + 'RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK', + 'RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT', + 'RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK', + 'RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT', + 'RLC_SPM_INT_INFO_2__RESERVED_MASK', + 'RLC_SPM_INT_INFO_2__RESERVED__SHIFT', + 'RLC_SPM_INT_STATUS__RESERVED_MASK', + 'RLC_SPM_INT_STATUS__RESERVED__SHIFT', + 'RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK', + 'RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT', + 'RLC_SPM_MC_CNTL__RESERVED_3_MASK', + 'RLC_SPM_MC_CNTL__RESERVED_3__SHIFT', + 'RLC_SPM_MC_CNTL__RESERVED_MASK', + 'RLC_SPM_MC_CNTL__RESERVED__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT', 'RLC_SPM_MODE__MODE_MASK', + 'RLC_SPM_MODE__MODE__SHIFT', 'RLC_SPM_PAUSE__PAUSED_MASK', + 'RLC_SPM_PAUSE__PAUSED__SHIFT', 'RLC_SPM_PAUSE__PAUSE_MASK', + 'RLC_SPM_PAUSE__PAUSE__SHIFT', + 'RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT_MASK', + 'RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT__SHIFT', + 'RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK', + 'RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT', + 'RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK', + 'RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT', + 'RLC_SPM_PERFMON_CNTL__RESERVED1_MASK', + 'RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT', + 'RLC_SPM_PERFMON_CNTL__RESERVED_MASK', + 'RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT', + 'RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK', + 'RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT', + 'RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK', + 'RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT', + 'RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK', + 'RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT', + 'RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK', + 'RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT__SHIFT', + 'RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK', + 'RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT', + 'RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK', + 'RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT', + 'RLC_SPM_RING_WRPTR__RESERVED_MASK', + 'RLC_SPM_RING_WRPTR__RESERVED__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE0_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE0_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE1_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE1_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE2_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE2_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE3_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE3_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE4_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE4_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE5_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE5_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE6_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE6_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SE7_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SE7_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD_ACK__SPM_ACK_MASK', + 'RLC_SPM_RSPM_CMD_ACK__SPM_ACK__SHIFT', + 'RLC_SPM_RSPM_CMD__CMD_MASK', 'RLC_SPM_RSPM_CMD__CMD__SHIFT', + 'RLC_SPM_RSPM_REQ_DATA_HI__DATA_MASK', + 'RLC_SPM_RSPM_REQ_DATA_HI__DATA__SHIFT', + 'RLC_SPM_RSPM_REQ_DATA_LO__DATA_MASK', + 'RLC_SPM_RSPM_REQ_DATA_LO__DATA__SHIFT', + 'RLC_SPM_RSPM_REQ_OP__OP_MASK', 'RLC_SPM_RSPM_REQ_OP__OP__SHIFT', + 'RLC_SPM_RSPM_RET_DATA__DATA_MASK', + 'RLC_SPM_RSPM_RET_DATA__DATA__SHIFT', + 'RLC_SPM_RSPM_RET_OP__OP_MASK', 'RLC_SPM_RSPM_RET_OP__OP__SHIFT', + 'RLC_SPM_RSPM_RET_OP__VALID_MASK', + 'RLC_SPM_RSPM_RET_OP__VALID__SHIFT', + 'RLC_SPM_SAMPLE_CNT__COUNT_MASK', + 'RLC_SPM_SAMPLE_CNT__COUNT__SHIFT', + 'RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK', + 'RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT', + 'RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK', + 'RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT', + 'RLC_SPM_SE_DELAY_IND_ADDR__ADDR_MASK', + 'RLC_SPM_SE_DELAY_IND_ADDR__ADDR__SHIFT', + 'RLC_SPM_SE_DELAY_IND_DATA__DATA_MASK', + 'RLC_SPM_SE_DELAY_IND_DATA__DATA__SHIFT', + 'RLC_SPM_SE_MUXSEL_ADDR__ADDR_MASK', + 'RLC_SPM_SE_MUXSEL_ADDR__ADDR__SHIFT', + 'RLC_SPM_SE_MUXSEL_DATA__SEL0_MASK', + 'RLC_SPM_SE_MUXSEL_DATA__SEL0__SHIFT', + 'RLC_SPM_SE_MUXSEL_DATA__SEL1_MASK', + 'RLC_SPM_SE_MUXSEL_DATA__SEL1__SHIFT', + 'RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA_MASK', + 'RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA__SHIFT', + 'RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA_MASK', + 'RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA__SHIFT', + 'RLC_SPM_SE_RSPM_REQ_OP__OP_MASK', + 'RLC_SPM_SE_RSPM_REQ_OP__OP__SHIFT', + 'RLC_SPM_SE_RSPM_RET_DATA__DATA_MASK', + 'RLC_SPM_SE_RSPM_RET_DATA__DATA__SHIFT', + 'RLC_SPM_SE_RSPM_RET_OP__OP_MASK', + 'RLC_SPM_SE_RSPM_RET_OP__OP__SHIFT', + 'RLC_SPM_SE_RSPM_RET_OP__VALID_MASK', + 'RLC_SPM_SE_RSPM_RET_OP__VALID__SHIFT', + 'RLC_SPM_SPARE__SPARE_MASK', 'RLC_SPM_SPARE__SPARE__SHIFT', + 'RLC_SPM_STATUS__ACCUM_BUSY_MASK', + 'RLC_SPM_STATUS__ACCUM_BUSY__SHIFT', + 'RLC_SPM_STATUS__CTL_BUSY_MASK', + 'RLC_SPM_STATUS__CTL_BUSY__SHIFT', + 'RLC_SPM_STATUS__CTL_REQ_STATE_MASK', + 'RLC_SPM_STATUS__CTL_REQ_STATE__SHIFT', + 'RLC_SPM_STATUS__CTL_RET_STATE_MASK', + 'RLC_SPM_STATUS__CTL_RET_STATE__SHIFT', + 'RLC_SPM_STATUS__FSM_MASTER_STATE_MASK', + 'RLC_SPM_STATUS__FSM_MASTER_STATE__SHIFT', + 'RLC_SPM_STATUS__FSM_MEMORY_STATE_MASK', + 'RLC_SPM_STATUS__FSM_MEMORY_STATE__SHIFT', + 'RLC_SPM_STATUS__RSPM_REG_BUSY_MASK', + 'RLC_SPM_STATUS__RSPM_REG_BUSY__SHIFT', + 'RLC_SPM_STATUS__SE_RSPM_IO_BUSY_MASK', + 'RLC_SPM_STATUS__SE_RSPM_IO_BUSY__SHIFT', + 'RLC_SPM_STATUS__SPM_RSPM_BUSY_MASK', + 'RLC_SPM_STATUS__SPM_RSPM_BUSY__SHIFT', + 'RLC_SPM_STATUS__SPM_RSPM_IO_BUSY_MASK', + 'RLC_SPM_STATUS__SPM_RSPM_IO_BUSY__SHIFT', + 'RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK', + 'RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT', + 'RLC_SPM_UTCL1_CNTL__BYPASS_MASK', + 'RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT', + 'RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK', + 'RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT', + 'RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK', + 'RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT', + 'RLC_SPM_UTCL1_CNTL__RESERVED_MASK', + 'RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT', + 'RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_SPP_CAM_ADDR__ADDR_MASK', 'RLC_SPP_CAM_ADDR__ADDR__SHIFT', + 'RLC_SPP_CAM_DATA__DATA_MASK', 'RLC_SPP_CAM_DATA__DATA__SHIFT', + 'RLC_SPP_CAM_DATA__TAG_MASK', 'RLC_SPP_CAM_DATA__TAG__SHIFT', + 'RLC_SPP_CAM_EXT_ADDR__ADDR_MASK', + 'RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT', + 'RLC_SPP_CAM_EXT_DATA__LOCK_MASK', + 'RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT', + 'RLC_SPP_CAM_EXT_DATA__VALID_MASK', + 'RLC_SPP_CAM_EXT_DATA__VALID__SHIFT', 'RLC_SPP_CTRL__ENABLE_MASK', + 'RLC_SPP_CTRL__ENABLE_PPROF_MASK', + 'RLC_SPP_CTRL__ENABLE_PPROF__SHIFT', + 'RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK', + 'RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT', + 'RLC_SPP_CTRL__ENABLE__SHIFT', 'RLC_SPP_CTRL__PAUSE_MASK', + 'RLC_SPP_CTRL__PAUSE__SHIFT', + 'RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK', + 'RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT', + 'RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK', + 'RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT', + 'RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK', + 'RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT', + 'RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK', + 'RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT', + 'RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK', + 'RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK', + 'RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT', + 'RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT', + 'RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK', + 'RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK', + 'RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT', + 'RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT', + 'RLC_SPP_PROF_INFO_1__SH_ID_MASK', + 'RLC_SPP_PROF_INFO_1__SH_ID__SHIFT', + 'RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK', + 'RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT', + 'RLC_SPP_PROF_INFO_2__CAM_HIT_MASK', + 'RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT', + 'RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK', + 'RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT', + 'RLC_SPP_PROF_INFO_2__SH_TYPE_MASK', + 'RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT', + 'RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK', + 'RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT', + 'RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT', + 'RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK', + 'RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT', + 'RLC_SPP_RESET__CAM_RESET_MASK', + 'RLC_SPP_RESET__CAM_RESET__SHIFT', + 'RLC_SPP_RESET__EVENT_ARB_RESET_MASK', + 'RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT', + 'RLC_SPP_RESET__PVT_RESET_MASK', + 'RLC_SPP_RESET__PVT_RESET__SHIFT', + 'RLC_SPP_RESET__SSF_RESET_MASK', + 'RLC_SPP_RESET__SSF_RESET__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__RESERVED_1_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__RESERVED_1__SHIFT', + 'RLC_SPP_SHADER_PROFILE_EN__RESERVED_7_MASK', + 'RLC_SPP_SHADER_PROFILE_EN__RESERVED_7__SHIFT', + 'RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK', + 'RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT', + 'RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK', + 'RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT', + 'RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK', + 'RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT', + 'RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK', + 'RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT', + 'RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK', + 'RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT', + 'RLC_SPP_SSF_CAPTURE_EN__RESERVED_1_MASK', + 'RLC_SPP_SSF_CAPTURE_EN__RESERVED_1__SHIFT', + 'RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK', + 'RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT', + 'RLC_SPP_SSF_THRESHOLD_0__RESERVED_MASK', + 'RLC_SPP_SSF_THRESHOLD_0__RESERVED__SHIFT', + 'RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK', + 'RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT', + 'RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK', + 'RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT', + 'RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK', + 'RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT', + 'RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK', + 'RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT', + 'RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK', + 'RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT', + 'RLC_SPP_STALL_STATE_UPDATE__STALL_MASK', + 'RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT', + 'RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK', + 'RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT', + 'RLC_SPP_STATUS__RESERVED_0_MASK', + 'RLC_SPP_STATUS__RESERVED_0__SHIFT', + 'RLC_SPP_STATUS__SPP_BUSY_MASK', + 'RLC_SPP_STATUS__SPP_BUSY__SHIFT', + 'RLC_SPP_STATUS__SSF_BUSY_MASK', + 'RLC_SPP_STATUS__SSF_BUSY__SHIFT', 'RLC_SRM_ARAM_ADDR__ADDR_MASK', + 'RLC_SRM_ARAM_ADDR__ADDR__SHIFT', + 'RLC_SRM_ARAM_ADDR__RESERVED_MASK', + 'RLC_SRM_ARAM_ADDR__RESERVED__SHIFT', + 'RLC_SRM_ARAM_DATA__DATA_MASK', 'RLC_SRM_ARAM_DATA__DATA__SHIFT', + 'RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK', + 'RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT', + 'RLC_SRM_CNTL__RESERVED_MASK', 'RLC_SRM_CNTL__RESERVED__SHIFT', + 'RLC_SRM_CNTL__SRM_ENABLE_MASK', + 'RLC_SRM_CNTL__SRM_ENABLE__SHIFT', 'RLC_SRM_DRAM_ADDR__ADDR_MASK', + 'RLC_SRM_DRAM_ADDR__ADDR__SHIFT', + 'RLC_SRM_DRAM_ADDR__RESERVED_MASK', + 'RLC_SRM_DRAM_ADDR__RESERVED__SHIFT', + 'RLC_SRM_DRAM_DATA__DATA_MASK', 'RLC_SRM_DRAM_DATA__DATA__SHIFT', + 'RLC_SRM_GPM_ABORT__ABORT_MASK', + 'RLC_SRM_GPM_ABORT__ABORT__SHIFT', + 'RLC_SRM_GPM_ABORT__RESERVED_MASK', + 'RLC_SRM_GPM_ABORT__RESERVED__SHIFT', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT', + 'RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK', + 'RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT', + 'RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK', + 'RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT', + 'RLC_SRM_GPM_COMMAND__OP_MASK', 'RLC_SRM_GPM_COMMAND__OP__SHIFT', + 'RLC_SRM_GPM_COMMAND__SIZE_MASK', + 'RLC_SRM_GPM_COMMAND__SIZE__SHIFT', + 'RLC_SRM_GPM_COMMAND__START_OFFSET_MASK', + 'RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT', + 'RLC_SRM_STAT__RESERVED_MASK', 'RLC_SRM_STAT__RESERVED__SHIFT', + 'RLC_SRM_STAT__SRM_BUSY_DELAY_MASK', + 'RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT', + 'RLC_SRM_STAT__SRM_BUSY_MASK', 'RLC_SRM_STAT__SRM_BUSY__SHIFT', + 'RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK', + 'RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT', + 'RLC_STAT__MC_BUSY_MASK', 'RLC_STAT__MC_BUSY__SHIFT', + 'RLC_STAT__RESERVED_MASK', 'RLC_STAT__RESERVED__SHIFT', + 'RLC_STAT__RLC_BUSY_MASK', 'RLC_STAT__RLC_BUSY__SHIFT', + 'RLC_STAT__RLC_GPM_BUSY_MASK', 'RLC_STAT__RLC_GPM_BUSY__SHIFT', + 'RLC_STAT__RLC_SPM_BUSY_MASK', 'RLC_STAT__RLC_SPM_BUSY__SHIFT', + 'RLC_STAT__RLC_SRM_BUSY_MASK', 'RLC_STAT__RLC_SRM_BUSY__SHIFT', + 'RLC_STAT__RLC_THREAD_0_BUSY_MASK', + 'RLC_STAT__RLC_THREAD_0_BUSY__SHIFT', + 'RLC_STAT__RLC_THREAD_1_BUSY_MASK', + 'RLC_STAT__RLC_THREAD_1_BUSY__SHIFT', + 'RLC_STAT__RLC_THREAD_2_BUSY_MASK', + 'RLC_STAT__RLC_THREAD_2_BUSY__SHIFT', + 'RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK', + 'RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_MASK', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED_MASK', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_MASK', + 'RLC_ULV_RESIDENCY_CNTR_CTRL__RESET__SHIFT', + 'RLC_ULV_RESIDENCY_EVENT_CNTR__DATA_MASK', + 'RLC_ULV_RESIDENCY_EVENT_CNTR__DATA__SHIFT', + 'RLC_ULV_RESIDENCY_REF_CNTR__DATA_MASK', + 'RLC_ULV_RESIDENCY_REF_CNTR__DATA__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS_2__RESERVED_1_MASK', + 'RLC_UTCL1_STATUS_2__RESERVED_1__SHIFT', + 'RLC_UTCL1_STATUS_2__RESERVED_MASK', + 'RLC_UTCL1_STATUS_2__RESERVED__SHIFT', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'RLC_UTCL1_STATUS__PRT_DETECTED_MASK', + 'RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_1_MASK', + 'RLC_UTCL1_STATUS__RESERVED_1__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_2_MASK', + 'RLC_UTCL1_STATUS__RESERVED_2__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_3_MASK', + 'RLC_UTCL1_STATUS__RESERVED_3__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_MASK', + 'RLC_UTCL1_STATUS__RESERVED__SHIFT', + 'RLC_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'RLC_WGP_STATUS__WORK_PENDING_MASK', + 'RLC_WGP_STATUS__WORK_PENDING__SHIFT', + 'RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC_MASK', + 'RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC__SHIFT', + 'RLC_XT_CORE_FAULT_INFO__FAULT_INFO_MASK', + 'RLC_XT_CORE_FAULT_INFO__FAULT_INFO__SHIFT', + 'RLC_XT_CORE_INTERRUPT__EXTINT1_MASK', + 'RLC_XT_CORE_INTERRUPT__EXTINT1__SHIFT', + 'RLC_XT_CORE_INTERRUPT__EXTINT2_MASK', + 'RLC_XT_CORE_INTERRUPT__EXTINT2__SHIFT', + 'RLC_XT_CORE_INTERRUPT__NMI_MASK', + 'RLC_XT_CORE_INTERRUPT__NMI__SHIFT', + 'RLC_XT_CORE_RESERVED__RESERVED_MASK', + 'RLC_XT_CORE_RESERVED__RESERVED__SHIFT', + 'RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR_MASK', + 'RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR__SHIFT', + 'RLC_XT_CORE_STATUS__P_FATAL_ERROR_MASK', + 'RLC_XT_CORE_STATUS__P_FATAL_ERROR__SHIFT', + 'RLC_XT_CORE_STATUS__P_WAIT_MODE_MASK', + 'RLC_XT_CORE_STATUS__P_WAIT_MODE__SHIFT', + 'RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK', + 'RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT', + 'RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK', + 'RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT', + 'RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK', + 'RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT', + 'RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK', + 'RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT', + 'RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK', + 'RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT', + 'RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK', + 'RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT', + 'RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK', + 'RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT', + 'RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK', + 'RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK', + 'RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT', + 'RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK', + 'RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK', + 'RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT', + 'RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT', + 'RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK', + 'RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK', + 'RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT', + 'RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT', + 'RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK', + 'RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT', + 'RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK', + 'RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT', + 'RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK', + 'RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT', + 'RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK', + 'RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_0_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_0__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_10_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_10__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_11_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_11__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_12_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_12__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_13_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_13__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_14_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_14__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_15_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_15__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_16_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_16__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_17_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_17__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_18_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_18__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_19_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_19__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_1_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_1__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_20_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_20__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_21_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_21__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_22_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_22__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_23_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_23__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_24_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_24__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_25_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_25__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_2_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_2__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_3_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_3__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_4_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_4__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_5_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_5__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_6_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_6__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_7_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_7__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_8_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_8__SHIFT', + 'RLC_XT_INT_VEC_CLEAR__NUM_9_MASK', + 'RLC_XT_INT_VEC_CLEAR__NUM_9__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_0_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_0__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_10_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_10__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_11_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_11__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_12_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_12__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_13_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_13__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_14_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_14__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_15_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_15__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_16_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_16__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_17_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_17__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_18_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_18__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_19_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_19__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_1_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_1__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_20_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_20__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_21_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_21__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_22_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_22__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_23_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_23__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_24_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_24__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_25_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_25__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_2_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_2__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_3_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_3__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_4_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_4__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_5_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_5__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_6_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_6__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_7_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_7__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_8_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_8__SHIFT', + 'RLC_XT_INT_VEC_FORCE__NUM_9_MASK', + 'RLC_XT_INT_VEC_FORCE__NUM_9__SHIFT', + 'RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL_MASK', + 'RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL__SHIFT', + 'RLC_XT_INT_VEC_MUX_SEL__MUX_SEL_MASK', + 'RLC_XT_INT_VEC_MUX_SEL__MUX_SEL__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK', + 'RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT', + 'RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK', + 'RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT', + 'RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK', + 'RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT', + 'RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS_MASK', + 'RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS__SHIFT', + 'RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK', + 'RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT', + 'RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS_MASK', + 'RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS__SHIFT', + 'RMI_GENERAL_CNTL__BURST_DISABLE_MASK', + 'RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT', + 'RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK', + 'RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT', + 'RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK', + 'RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT', + 'RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK', + 'RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT', + 'RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK', + 'RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT', + 'RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK', + 'RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__RESERVED_BITS_28_21_MASK', + 'RMI_GENERAL_STATUS__RESERVED_BITS_28_21__SHIFT', + 'RMI_GENERAL_STATUS__RESERVED_BIT_18_MASK', + 'RMI_GENERAL_STATUS__RESERVED_BIT_18__SHIFT', + 'RMI_GENERAL_STATUS__RESERVED_BIT_19_MASK', + 'RMI_GENERAL_STATUS__RESERVED_BIT_19__SHIFT', + 'RMI_GENERAL_STATUS__RESERVED_BIT_20_MASK', + 'RMI_GENERAL_STATUS__RESERVED_BIT_20__SHIFT', + 'RMI_GENERAL_STATUS__RESERVED_BIT_29_MASK', + 'RMI_GENERAL_STATUS__RESERVED_BIT_29__SHIFT', + 'RMI_GENERAL_STATUS__RESERVED_BIT_30_MASK', + 'RMI_GENERAL_STATUS__RESERVED_BIT_30__SHIFT', + 'RMI_GENERAL_STATUS__RESERVED_BIT_6_MASK', + 'RMI_GENERAL_STATUS__RESERVED_BIT_6__SHIFT', + 'RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK', + 'RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK', + 'RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK', + 'RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT', + 'RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT', + 'RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT', + 'RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT', + 'RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT', + 'RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT', + 'RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT', + 'RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT', + 'RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT', + 'RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT', + 'RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK', + 'RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT', + 'RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK', + 'RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK', + 'RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK', + 'RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT', + 'RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK', + 'RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK', + 'RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT', + 'RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK', + 'RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT', + 'RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK', + 'RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_10_MASK', + 'RMI_SPARE_1__SPARE_BIT_10__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_11_MASK', + 'RMI_SPARE_1__SPARE_BIT_11__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_12_MASK', + 'RMI_SPARE_1__SPARE_BIT_12__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_13_MASK', + 'RMI_SPARE_1__SPARE_BIT_13__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_14_MASK', + 'RMI_SPARE_1__SPARE_BIT_14__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_15_MASK', + 'RMI_SPARE_1__SPARE_BIT_15__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_16_1_MASK', + 'RMI_SPARE_1__SPARE_BIT_16_1__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_9_MASK', + 'RMI_SPARE_1__SPARE_BIT_9__SHIFT', + 'RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK', + 'RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_8_2_MASK', + 'RMI_SPARE_2__SPARE_BIT_8_2__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_8_3_MASK', + 'RMI_SPARE_2__SPARE_BIT_8_3__SHIFT', + 'RMI_SPARE__ARBITER_ADDRESS_MASK_MASK', + 'RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT', + 'RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK', + 'RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT', + 'RMI_SPARE__NOFILL_RMI_CID_CC_MASK', + 'RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT', + 'RMI_SPARE__NOFILL_RMI_CID_CM_MASK', + 'RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT', + 'RMI_SPARE__NOFILL_RMI_CID_DC_MASK', + 'RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT', + 'RMI_SPARE__NOFILL_RMI_CID_FC_MASK', + 'RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT', + 'RMI_SPARE__NOFILL_RMI_CID_S_MASK', + 'RMI_SPARE__NOFILL_RMI_CID_S__SHIFT', + 'RMI_SPARE__NOFILL_RMI_CID_TILE_MASK', + 'RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT', + 'RMI_SPARE__NOFILL_RMI_CID_Z_MASK', + 'RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT', + 'RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK', + 'RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT', + 'RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK', + 'RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT', + 'RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK', + 'RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT', + 'RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK', + 'RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT', + 'RMI_SPARE__SPARE_BIT_15_0_MASK', + 'RMI_SPARE__SPARE_BIT_15_0__SHIFT', 'RMI_SPARE__SPARE_BIT_7_MASK', + 'RMI_SPARE__SPARE_BIT_7__SHIFT', + 'RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK', + 'RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT', + 'RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK', + 'RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT', + 'RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK', + 'RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT', + 'RMI_UTCL1_CNTL1__CLIENTID_MASK', + 'RMI_UTCL1_CNTL1__CLIENTID__SHIFT', + 'RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK', + 'RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT', + 'RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK', + 'RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT', + 'RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK', + 'RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT', + 'RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK', + 'RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK', + 'RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT', + 'RMI_UTCL1_CNTL1__FORCE_MISS_MASK', + 'RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT', + 'RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK', + 'RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT', + 'RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK', + 'RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK', + 'RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT', + 'RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK', + 'RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT', + 'RMI_UTCL1_CNTL1__REG_INV_VMID_MASK', + 'RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT', + 'RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK', + 'RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT', + 'RMI_UTCL1_CNTL1__RESP_MODE_MASK', + 'RMI_UTCL1_CNTL1__RESP_MODE__SHIFT', + 'RMI_UTCL1_CNTL1__USERVM_DIS_MASK', + 'RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT', + 'RMI_UTCL1_CNTL2__DIS_EDC_MASK', + 'RMI_UTCL1_CNTL2__DIS_EDC__SHIFT', + 'RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK', + 'RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT', + 'RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK', + 'RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT', + 'RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK', + 'RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT', + 'RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK', + 'RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT', + 'RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK', + 'RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT', + 'RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK', + 'RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT', + 'RMI_UTCL1_CNTL2__LINE_VALID_MASK', + 'RMI_UTCL1_CNTL2__LINE_VALID__SHIFT', + 'RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK', + 'RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK', + 'RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT', + 'RMI_UTCL1_CNTL2__RESERVED_MASK', + 'RMI_UTCL1_CNTL2__RESERVED__SHIFT', + 'RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK', + 'RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT', + 'RMI_UTCL1_CNTL2__UTC_SPARE_MASK', + 'RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT', + 'RMI_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'RMI_UTCL1_STATUS__PRT_DETECTED_MASK', + 'RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'RMI_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK', + 'RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT', + 'RMI_XBAR_CONFIG__ARBITER_DIS_MASK', + 'RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT', + 'RTAVFS_REG0__RTAVFSZONE0STARTCNT_MASK', + 'RTAVFS_REG0__RTAVFSZONE0STARTCNT__SHIFT', + 'RTAVFS_REG0__RTAVFSZONE0STOPCNT_MASK', + 'RTAVFS_REG0__RTAVFSZONE0STOPCNT__SHIFT', + 'RTAVFS_REG100__RTAVFSCPO46_STARTCNT_MASK', + 'RTAVFS_REG100__RTAVFSCPO46_STARTCNT__SHIFT', + 'RTAVFS_REG100__RTAVFSCPO46_STOPCNT_MASK', + 'RTAVFS_REG100__RTAVFSCPO46_STOPCNT__SHIFT', + 'RTAVFS_REG101__RTAVFSCPO47_STARTCNT_MASK', + 'RTAVFS_REG101__RTAVFSCPO47_STARTCNT__SHIFT', + 'RTAVFS_REG101__RTAVFSCPO47_STOPCNT_MASK', + 'RTAVFS_REG101__RTAVFSCPO47_STOPCNT__SHIFT', + 'RTAVFS_REG102__RTAVFSCPO48_STARTCNT_MASK', + 'RTAVFS_REG102__RTAVFSCPO48_STARTCNT__SHIFT', + 'RTAVFS_REG102__RTAVFSCPO48_STOPCNT_MASK', + 'RTAVFS_REG102__RTAVFSCPO48_STOPCNT__SHIFT', + 'RTAVFS_REG103__RTAVFSCPO49_STARTCNT_MASK', + 'RTAVFS_REG103__RTAVFSCPO49_STARTCNT__SHIFT', + 'RTAVFS_REG103__RTAVFSCPO49_STOPCNT_MASK', + 'RTAVFS_REG103__RTAVFSCPO49_STOPCNT__SHIFT', + 'RTAVFS_REG104__RTAVFSCPO50_STARTCNT_MASK', + 'RTAVFS_REG104__RTAVFSCPO50_STARTCNT__SHIFT', + 'RTAVFS_REG104__RTAVFSCPO50_STOPCNT_MASK', + 'RTAVFS_REG104__RTAVFSCPO50_STOPCNT__SHIFT', + 'RTAVFS_REG105__RTAVFSCPO51_STARTCNT_MASK', + 'RTAVFS_REG105__RTAVFSCPO51_STARTCNT__SHIFT', + 'RTAVFS_REG105__RTAVFSCPO51_STOPCNT_MASK', + 'RTAVFS_REG105__RTAVFSCPO51_STOPCNT__SHIFT', + 'RTAVFS_REG106__RTAVFSCPO52_STARTCNT_MASK', + 'RTAVFS_REG106__RTAVFSCPO52_STARTCNT__SHIFT', + 'RTAVFS_REG106__RTAVFSCPO52_STOPCNT_MASK', + 'RTAVFS_REG106__RTAVFSCPO52_STOPCNT__SHIFT', + 'RTAVFS_REG107__RTAVFSCPO53_STARTCNT_MASK', + 'RTAVFS_REG107__RTAVFSCPO53_STARTCNT__SHIFT', + 'RTAVFS_REG107__RTAVFSCPO53_STOPCNT_MASK', + 'RTAVFS_REG107__RTAVFSCPO53_STOPCNT__SHIFT', + 'RTAVFS_REG108__RTAVFSCPO54_STARTCNT_MASK', + 'RTAVFS_REG108__RTAVFSCPO54_STARTCNT__SHIFT', + 'RTAVFS_REG108__RTAVFSCPO54_STOPCNT_MASK', + 'RTAVFS_REG108__RTAVFSCPO54_STOPCNT__SHIFT', + 'RTAVFS_REG109__RTAVFSCPO55_STARTCNT_MASK', + 'RTAVFS_REG109__RTAVFSCPO55_STARTCNT__SHIFT', + 'RTAVFS_REG109__RTAVFSCPO55_STOPCNT_MASK', + 'RTAVFS_REG109__RTAVFSCPO55_STOPCNT__SHIFT', + 'RTAVFS_REG10__RTAVFSZONE2EN1_MASK', + 'RTAVFS_REG10__RTAVFSZONE2EN1__SHIFT', + 'RTAVFS_REG110__RTAVFSCPO56_STARTCNT_MASK', + 'RTAVFS_REG110__RTAVFSCPO56_STARTCNT__SHIFT', + 'RTAVFS_REG110__RTAVFSCPO56_STOPCNT_MASK', + 'RTAVFS_REG110__RTAVFSCPO56_STOPCNT__SHIFT', + 'RTAVFS_REG111__RTAVFSCPO57_STARTCNT_MASK', + 'RTAVFS_REG111__RTAVFSCPO57_STARTCNT__SHIFT', + 'RTAVFS_REG111__RTAVFSCPO57_STOPCNT_MASK', + 'RTAVFS_REG111__RTAVFSCPO57_STOPCNT__SHIFT', + 'RTAVFS_REG112__RTAVFSCPO58_STARTCNT_MASK', + 'RTAVFS_REG112__RTAVFSCPO58_STARTCNT__SHIFT', + 'RTAVFS_REG112__RTAVFSCPO58_STOPCNT_MASK', + 'RTAVFS_REG112__RTAVFSCPO58_STOPCNT__SHIFT', + 'RTAVFS_REG113__RTAVFSCPO59_STARTCNT_MASK', + 'RTAVFS_REG113__RTAVFSCPO59_STARTCNT__SHIFT', + 'RTAVFS_REG113__RTAVFSCPO59_STOPCNT_MASK', + 'RTAVFS_REG113__RTAVFSCPO59_STOPCNT__SHIFT', + 'RTAVFS_REG114__RTAVFSCPO60_STARTCNT_MASK', + 'RTAVFS_REG114__RTAVFSCPO60_STARTCNT__SHIFT', + 'RTAVFS_REG114__RTAVFSCPO60_STOPCNT_MASK', + 'RTAVFS_REG114__RTAVFSCPO60_STOPCNT__SHIFT', + 'RTAVFS_REG115__RTAVFSCPO61_STARTCNT_MASK', + 'RTAVFS_REG115__RTAVFSCPO61_STARTCNT__SHIFT', + 'RTAVFS_REG115__RTAVFSCPO61_STOPCNT_MASK', + 'RTAVFS_REG115__RTAVFSCPO61_STOPCNT__SHIFT', + 'RTAVFS_REG116__RTAVFSCPO62_STARTCNT_MASK', + 'RTAVFS_REG116__RTAVFSCPO62_STARTCNT__SHIFT', + 'RTAVFS_REG116__RTAVFSCPO62_STOPCNT_MASK', + 'RTAVFS_REG116__RTAVFSCPO62_STOPCNT__SHIFT', + 'RTAVFS_REG117__RTAVFSCPO63_STARTCNT_MASK', + 'RTAVFS_REG117__RTAVFSCPO63_STARTCNT__SHIFT', + 'RTAVFS_REG117__RTAVFSCPO63_STOPCNT_MASK', + 'RTAVFS_REG117__RTAVFSCPO63_STOPCNT__SHIFT', + 'RTAVFS_REG118__RTAVFSCPOEN0_MASK', + 'RTAVFS_REG118__RTAVFSCPOEN0__SHIFT', + 'RTAVFS_REG119__RTAVFSCPOEN1_MASK', + 'RTAVFS_REG119__RTAVFSCPOEN1__SHIFT', + 'RTAVFS_REG11__RTAVFSZONE3EN0_MASK', + 'RTAVFS_REG11__RTAVFSZONE3EN0__SHIFT', + 'RTAVFS_REG120__RESERVED_MASK', 'RTAVFS_REG120__RESERVED__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV0_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV0__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV1_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV1__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV2_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV2__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV3_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV3__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV4_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV4__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV5_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV5__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV6_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV6__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV7_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIV7__SHIFT', + 'RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL_MASK', + 'RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL__SHIFT', + 'RTAVFS_REG121__RTAVFSERRORCODE_MASK', + 'RTAVFS_REG121__RTAVFSERRORCODE__SHIFT', + 'RTAVFS_REG121__RTAVFSRESERVED_MASK', + 'RTAVFS_REG121__RTAVFSRESERVED__SHIFT', + 'RTAVFS_REG121__RTAVFSZONE0INUSE_MASK', + 'RTAVFS_REG121__RTAVFSZONE0INUSE__SHIFT', + 'RTAVFS_REG121__RTAVFSZONE1INUSE_MASK', + 'RTAVFS_REG121__RTAVFSZONE1INUSE__SHIFT', + 'RTAVFS_REG121__RTAVFSZONE2INUSE_MASK', + 'RTAVFS_REG121__RTAVFSZONE2INUSE__SHIFT', + 'RTAVFS_REG121__RTAVFSZONE3INUSE_MASK', + 'RTAVFS_REG121__RTAVFSZONE3INUSE__SHIFT', + 'RTAVFS_REG121__RTAVFSZONE4INUSE_MASK', + 'RTAVFS_REG121__RTAVFSZONE4INUSE__SHIFT', + 'RTAVFS_REG122__RESERVED_MASK', 'RTAVFS_REG122__RESERVED__SHIFT', + 'RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT_MASK', + 'RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT__SHIFT', + 'RTAVFS_REG123__RESERVED_MASK', 'RTAVFS_REG123__RESERVED__SHIFT', + 'RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT_MASK', + 'RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT__SHIFT', + 'RTAVFS_REG124__RESERVED_MASK', 'RTAVFS_REG124__RESERVED__SHIFT', + 'RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT_MASK', + 'RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT__SHIFT', + 'RTAVFS_REG125__RESERVED_MASK', 'RTAVFS_REG125__RESERVED__SHIFT', + 'RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT_MASK', + 'RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT__SHIFT', + 'RTAVFS_REG126__RESERVED_MASK', 'RTAVFS_REG126__RESERVED__SHIFT', + 'RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT_MASK', + 'RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT__SHIFT', + 'RTAVFS_REG127__RESERVED_MASK', 'RTAVFS_REG127__RESERVED__SHIFT', + 'RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT_MASK', + 'RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT__SHIFT', + 'RTAVFS_REG128__RESERVED_MASK', 'RTAVFS_REG128__RESERVED__SHIFT', + 'RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT_MASK', + 'RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT__SHIFT', + 'RTAVFS_REG129__RESERVED_MASK', 'RTAVFS_REG129__RESERVED__SHIFT', + 'RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT_MASK', + 'RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT__SHIFT', + 'RTAVFS_REG12__RTAVFSZONE3EN1_MASK', + 'RTAVFS_REG12__RTAVFSZONE3EN1__SHIFT', + 'RTAVFS_REG130__RESERVED_MASK', 'RTAVFS_REG130__RESERVED__SHIFT', + 'RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT_MASK', + 'RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT__SHIFT', + 'RTAVFS_REG131__RESERVED_MASK', 'RTAVFS_REG131__RESERVED__SHIFT', + 'RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT_MASK', + 'RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT__SHIFT', + 'RTAVFS_REG132__RESERVED_MASK', 'RTAVFS_REG132__RESERVED__SHIFT', + 'RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT_MASK', + 'RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT__SHIFT', + 'RTAVFS_REG133__RESERVED_MASK', 'RTAVFS_REG133__RESERVED__SHIFT', + 'RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT_MASK', + 'RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT__SHIFT', + 'RTAVFS_REG134__RESERVED_MASK', 'RTAVFS_REG134__RESERVED__SHIFT', + 'RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT_MASK', + 'RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT__SHIFT', + 'RTAVFS_REG135__RESERVED_MASK', 'RTAVFS_REG135__RESERVED__SHIFT', + 'RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT_MASK', + 'RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT__SHIFT', + 'RTAVFS_REG136__RESERVED_MASK', 'RTAVFS_REG136__RESERVED__SHIFT', + 'RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT_MASK', + 'RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT__SHIFT', + 'RTAVFS_REG137__RESERVED_MASK', 'RTAVFS_REG137__RESERVED__SHIFT', + 'RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT_MASK', + 'RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT__SHIFT', + 'RTAVFS_REG138__RESERVED_MASK', 'RTAVFS_REG138__RESERVED__SHIFT', + 'RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT_MASK', + 'RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT__SHIFT', + 'RTAVFS_REG139__RESERVED_MASK', 'RTAVFS_REG139__RESERVED__SHIFT', + 'RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT_MASK', + 'RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT__SHIFT', + 'RTAVFS_REG13__RTAVFSZONE4EN0_MASK', + 'RTAVFS_REG13__RTAVFSZONE4EN0__SHIFT', + 'RTAVFS_REG140__RESERVED_MASK', 'RTAVFS_REG140__RESERVED__SHIFT', + 'RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT_MASK', + 'RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT__SHIFT', + 'RTAVFS_REG141__RESERVED_MASK', 'RTAVFS_REG141__RESERVED__SHIFT', + 'RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT_MASK', + 'RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT__SHIFT', + 'RTAVFS_REG142__RESERVED_MASK', 'RTAVFS_REG142__RESERVED__SHIFT', + 'RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT_MASK', + 'RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT__SHIFT', + 'RTAVFS_REG143__RESERVED_MASK', 'RTAVFS_REG143__RESERVED__SHIFT', + 'RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT_MASK', + 'RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT__SHIFT', + 'RTAVFS_REG144__RESERVED_MASK', 'RTAVFS_REG144__RESERVED__SHIFT', + 'RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT_MASK', + 'RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT__SHIFT', + 'RTAVFS_REG145__RESERVED_MASK', 'RTAVFS_REG145__RESERVED__SHIFT', + 'RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT_MASK', + 'RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT__SHIFT', + 'RTAVFS_REG146__RESERVED_MASK', 'RTAVFS_REG146__RESERVED__SHIFT', + 'RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT_MASK', + 'RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT__SHIFT', + 'RTAVFS_REG147__RESERVED_MASK', 'RTAVFS_REG147__RESERVED__SHIFT', + 'RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT_MASK', + 'RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT__SHIFT', + 'RTAVFS_REG148__RESERVED_MASK', 'RTAVFS_REG148__RESERVED__SHIFT', + 'RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT_MASK', + 'RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT__SHIFT', + 'RTAVFS_REG149__RESERVED_MASK', 'RTAVFS_REG149__RESERVED__SHIFT', + 'RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT_MASK', + 'RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT__SHIFT', + 'RTAVFS_REG14__RTAVFSZONE4EN1_MASK', + 'RTAVFS_REG14__RTAVFSZONE4EN1__SHIFT', + 'RTAVFS_REG150__RESERVED_MASK', 'RTAVFS_REG150__RESERVED__SHIFT', + 'RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT_MASK', + 'RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT__SHIFT', + 'RTAVFS_REG151__RESERVED_MASK', 'RTAVFS_REG151__RESERVED__SHIFT', + 'RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT_MASK', + 'RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT__SHIFT', + 'RTAVFS_REG152__RESERVED_MASK', 'RTAVFS_REG152__RESERVED__SHIFT', + 'RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT_MASK', + 'RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT__SHIFT', + 'RTAVFS_REG153__RESERVED_MASK', 'RTAVFS_REG153__RESERVED__SHIFT', + 'RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT_MASK', + 'RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT__SHIFT', + 'RTAVFS_REG154__RESERVED_MASK', 'RTAVFS_REG154__RESERVED__SHIFT', + 'RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT_MASK', + 'RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT__SHIFT', + 'RTAVFS_REG155__RESERVED_MASK', 'RTAVFS_REG155__RESERVED__SHIFT', + 'RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT_MASK', + 'RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT__SHIFT', + 'RTAVFS_REG156__RESERVED_MASK', 'RTAVFS_REG156__RESERVED__SHIFT', + 'RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT_MASK', + 'RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT__SHIFT', + 'RTAVFS_REG157__RESERVED_MASK', 'RTAVFS_REG157__RESERVED__SHIFT', + 'RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT_MASK', + 'RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT__SHIFT', + 'RTAVFS_REG158__RESERVED_MASK', 'RTAVFS_REG158__RESERVED__SHIFT', + 'RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT_MASK', + 'RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT__SHIFT', + 'RTAVFS_REG159__RESERVED_MASK', 'RTAVFS_REG159__RESERVED__SHIFT', + 'RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT_MASK', + 'RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT__SHIFT', + 'RTAVFS_REG15__RTAVFSVF0FREQCOUNT_MASK', + 'RTAVFS_REG15__RTAVFSVF0FREQCOUNT__SHIFT', + 'RTAVFS_REG15__RTAVFSVF0VOLTCODE_MASK', + 'RTAVFS_REG15__RTAVFSVF0VOLTCODE__SHIFT', + 'RTAVFS_REG160__RESERVED_MASK', 'RTAVFS_REG160__RESERVED__SHIFT', + 'RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT_MASK', + 'RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT__SHIFT', + 'RTAVFS_REG161__RESERVED_MASK', 'RTAVFS_REG161__RESERVED__SHIFT', + 'RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT_MASK', + 'RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT__SHIFT', + 'RTAVFS_REG162__RESERVED_MASK', 'RTAVFS_REG162__RESERVED__SHIFT', + 'RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT_MASK', + 'RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT__SHIFT', + 'RTAVFS_REG163__RESERVED_MASK', 'RTAVFS_REG163__RESERVED__SHIFT', + 'RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT_MASK', + 'RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT__SHIFT', + 'RTAVFS_REG164__RESERVED_MASK', 'RTAVFS_REG164__RESERVED__SHIFT', + 'RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT_MASK', + 'RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT__SHIFT', + 'RTAVFS_REG165__RESERVED_MASK', 'RTAVFS_REG165__RESERVED__SHIFT', + 'RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT_MASK', + 'RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT__SHIFT', + 'RTAVFS_REG166__RESERVED_MASK', 'RTAVFS_REG166__RESERVED__SHIFT', + 'RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT_MASK', + 'RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT__SHIFT', + 'RTAVFS_REG167__RESERVED_MASK', 'RTAVFS_REG167__RESERVED__SHIFT', + 'RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT_MASK', + 'RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT__SHIFT', + 'RTAVFS_REG168__RESERVED_MASK', 'RTAVFS_REG168__RESERVED__SHIFT', + 'RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT_MASK', + 'RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT__SHIFT', + 'RTAVFS_REG169__RESERVED_MASK', 'RTAVFS_REG169__RESERVED__SHIFT', + 'RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT_MASK', + 'RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT__SHIFT', + 'RTAVFS_REG16__RTAVFSVF1FREQCOUNT_MASK', + 'RTAVFS_REG16__RTAVFSVF1FREQCOUNT__SHIFT', + 'RTAVFS_REG16__RTAVFSVF1VOLTCODE_MASK', + 'RTAVFS_REG16__RTAVFSVF1VOLTCODE__SHIFT', + 'RTAVFS_REG170__RESERVED_MASK', 'RTAVFS_REG170__RESERVED__SHIFT', + 'RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT_MASK', + 'RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT__SHIFT', + 'RTAVFS_REG171__RESERVED_MASK', 'RTAVFS_REG171__RESERVED__SHIFT', + 'RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT_MASK', + 'RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT__SHIFT', + 'RTAVFS_REG172__RESERVED_MASK', 'RTAVFS_REG172__RESERVED__SHIFT', + 'RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT_MASK', + 'RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT__SHIFT', + 'RTAVFS_REG173__RESERVED_MASK', 'RTAVFS_REG173__RESERVED__SHIFT', + 'RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT_MASK', + 'RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT__SHIFT', + 'RTAVFS_REG174__RESERVED_MASK', 'RTAVFS_REG174__RESERVED__SHIFT', + 'RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT_MASK', + 'RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT__SHIFT', + 'RTAVFS_REG175__RESERVED_MASK', 'RTAVFS_REG175__RESERVED__SHIFT', + 'RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT_MASK', + 'RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT__SHIFT', + 'RTAVFS_REG176__RESERVED_MASK', 'RTAVFS_REG176__RESERVED__SHIFT', + 'RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT_MASK', + 'RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT__SHIFT', + 'RTAVFS_REG177__RESERVED_MASK', 'RTAVFS_REG177__RESERVED__SHIFT', + 'RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT_MASK', + 'RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT__SHIFT', + 'RTAVFS_REG178__RESERVED_MASK', 'RTAVFS_REG178__RESERVED__SHIFT', + 'RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT_MASK', + 'RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT__SHIFT', + 'RTAVFS_REG179__RESERVED_MASK', 'RTAVFS_REG179__RESERVED__SHIFT', + 'RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT_MASK', + 'RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT__SHIFT', + 'RTAVFS_REG17__RTAVFSVF2FREQCOUNT_MASK', + 'RTAVFS_REG17__RTAVFSVF2FREQCOUNT__SHIFT', + 'RTAVFS_REG17__RTAVFSVF2VOLTCODE_MASK', + 'RTAVFS_REG17__RTAVFSVF2VOLTCODE__SHIFT', + 'RTAVFS_REG180__RESERVED_MASK', 'RTAVFS_REG180__RESERVED__SHIFT', + 'RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT_MASK', + 'RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT__SHIFT', + 'RTAVFS_REG181__RESERVED_MASK', 'RTAVFS_REG181__RESERVED__SHIFT', + 'RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT_MASK', + 'RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT__SHIFT', + 'RTAVFS_REG182__RESERVED_MASK', 'RTAVFS_REG182__RESERVED__SHIFT', + 'RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT_MASK', + 'RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT__SHIFT', + 'RTAVFS_REG183__RESERVED_MASK', 'RTAVFS_REG183__RESERVED__SHIFT', + 'RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT_MASK', + 'RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT__SHIFT', + 'RTAVFS_REG184__RESERVED_MASK', 'RTAVFS_REG184__RESERVED__SHIFT', + 'RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT_MASK', + 'RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT__SHIFT', + 'RTAVFS_REG185__RESERVED_MASK', 'RTAVFS_REG185__RESERVED__SHIFT', + 'RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT_MASK', + 'RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT__SHIFT', + 'RTAVFS_REG186__RESERVED_MASK', 'RTAVFS_REG186__RESERVED__SHIFT', + 'RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL_MASK', + 'RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL__SHIFT', + 'RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE_MASK', + 'RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE__SHIFT', + 'RTAVFS_REG187__RESERVED_MASK', 'RTAVFS_REG187__RESERVED__SHIFT', + 'RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL_MASK', + 'RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL__SHIFT', + 'RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE_MASK', + 'RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE__SHIFT', + 'RTAVFS_REG188__RESERVED_MASK', 'RTAVFS_REG188__RESERVED__SHIFT', + 'RTAVFS_REG189__RESERVED_MASK', 'RTAVFS_REG189__RESERVED__SHIFT', + 'RTAVFS_REG189__RTAVFSVDDABOVEVDDRET_MASK', + 'RTAVFS_REG189__RTAVFSVDDABOVEVDDRET__SHIFT', + 'RTAVFS_REG189__RTAVFSVDDREGON_MASK', + 'RTAVFS_REG189__RTAVFSVDDREGON__SHIFT', + 'RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH_MASK', + 'RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH__SHIFT', + 'RTAVFS_REG189__RTAVFSVOLTCODEFROMPI_MASK', + 'RTAVFS_REG189__RTAVFSVOLTCODEFROMPI__SHIFT', + 'RTAVFS_REG18__RTAVFSVF3FREQCOUNT_MASK', + 'RTAVFS_REG18__RTAVFSVF3FREQCOUNT__SHIFT', + 'RTAVFS_REG18__RTAVFSVF3VOLTCODE_MASK', + 'RTAVFS_REG18__RTAVFSVF3VOLTCODE__SHIFT', + 'RTAVFS_REG190__RESERVED_MASK', 'RTAVFS_REG190__RESERVED__SHIFT', + 'RTAVFS_REG190__RTAVFSIGNORERLCREQ_MASK', + 'RTAVFS_REG190__RTAVFSIGNORERLCREQ__SHIFT', + 'RTAVFS_REG190__RTAVFSRESETRETENTIONREGS_MASK', + 'RTAVFS_REG190__RTAVFSRESETRETENTIONREGS__SHIFT', + 'RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS_MASK', + 'RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS__SHIFT', + 'RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL_MASK', + 'RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL__SHIFT', + 'RTAVFS_REG190__RTAVFSRUNLOOP_MASK', + 'RTAVFS_REG190__RTAVFSRUNLOOP__SHIFT', + 'RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS_MASK', + 'RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS__SHIFT', + 'RTAVFS_REG191__RESERVED_MASK', 'RTAVFS_REG191__RESERVED__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATIDLE_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATIDLE__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATSTARTUP_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATSTARTUP__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY__SHIFT', + 'RTAVFS_REG191__RTAVFSSTOPATWAITFORACK_MASK', + 'RTAVFS_REG191__RTAVFSSTOPATWAITFORACK__SHIFT', + 'RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT_MASK', + 'RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT__SHIFT', + 'RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT_MASK', + 'RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT__SHIFT', + 'RTAVFS_REG193__RESERVED_MASK', 'RTAVFS_REG193__RESERVED__SHIFT', + 'RTAVFS_REG193__RTAVFSFSMSTATE_MASK', + 'RTAVFS_REG193__RTAVFSFSMSTATE__SHIFT', + 'RTAVFS_REG194__RTAVFSRIPPLECNTREAD_MASK', + 'RTAVFS_REG194__RTAVFSRIPPLECNTREAD__SHIFT', + 'RTAVFS_REG19__RTAVFSGB_ZONE0_MASK', + 'RTAVFS_REG19__RTAVFSGB_ZONE0__SHIFT', + 'RTAVFS_REG19__RTAVFSGB_ZONE1_MASK', + 'RTAVFS_REG19__RTAVFSGB_ZONE1__SHIFT', + 'RTAVFS_REG19__RTAVFSGB_ZONE2_MASK', + 'RTAVFS_REG19__RTAVFSGB_ZONE2__SHIFT', + 'RTAVFS_REG19__RTAVFSGB_ZONE3_MASK', + 'RTAVFS_REG19__RTAVFSGB_ZONE3__SHIFT', + 'RTAVFS_REG19__RTAVFSGB_ZONE4_MASK', + 'RTAVFS_REG19__RTAVFSGB_ZONE4__SHIFT', + 'RTAVFS_REG1__RTAVFSZONE1STARTCNT_MASK', + 'RTAVFS_REG1__RTAVFSZONE1STARTCNT__SHIFT', + 'RTAVFS_REG1__RTAVFSZONE1STOPCNT_MASK', + 'RTAVFS_REG1__RTAVFSZONE1STOPCNT__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL_MASK', + 'RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL__SHIFT', + 'RTAVFS_REG20__RTAVFSZONE0RESERVED_MASK', + 'RTAVFS_REG20__RTAVFSZONE0RESERVED__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL_MASK', + 'RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL__SHIFT', + 'RTAVFS_REG21__RTAVFSZONE1RESERVED_MASK', + 'RTAVFS_REG21__RTAVFSZONE1RESERVED__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL_MASK', + 'RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL__SHIFT', + 'RTAVFS_REG22__RTAVFSZONE2RESERVED_MASK', + 'RTAVFS_REG22__RTAVFSZONE2RESERVED__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL_MASK', + 'RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL__SHIFT', + 'RTAVFS_REG23__RTAVFSZONE3RESERVED_MASK', + 'RTAVFS_REG23__RTAVFSZONE3RESERVED__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL_MASK', + 'RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL__SHIFT', + 'RTAVFS_REG24__RTAVFSZONE4RESERVED_MASK', + 'RTAVFS_REG24__RTAVFSZONE4RESERVED__SHIFT', + 'RTAVFS_REG25__RTAVFSRESERVED0_MASK', + 'RTAVFS_REG25__RTAVFSRESERVED0__SHIFT', + 'RTAVFS_REG26__RTAVFSRESERVED1_MASK', + 'RTAVFS_REG26__RTAVFSRESERVED1__SHIFT', + 'RTAVFS_REG27__RTAVFSRESERVED2_MASK', + 'RTAVFS_REG27__RTAVFSRESERVED2__SHIFT', + 'RTAVFS_REG28__RTAVFSZONE0INTERCEPT_MASK', + 'RTAVFS_REG28__RTAVFSZONE0INTERCEPT__SHIFT', + 'RTAVFS_REG28__RTAVFSZONE1INTERCEPT_MASK', + 'RTAVFS_REG28__RTAVFSZONE1INTERCEPT__SHIFT', + 'RTAVFS_REG29__RTAVFSZONE2INTERCEPT_MASK', + 'RTAVFS_REG29__RTAVFSZONE2INTERCEPT__SHIFT', + 'RTAVFS_REG29__RTAVFSZONE3INTERCEPT_MASK', + 'RTAVFS_REG29__RTAVFSZONE3INTERCEPT__SHIFT', + 'RTAVFS_REG2__RTAVFSZONE2STARTCNT_MASK', + 'RTAVFS_REG2__RTAVFSZONE2STARTCNT__SHIFT', + 'RTAVFS_REG2__RTAVFSZONE2STOPCNT_MASK', + 'RTAVFS_REG2__RTAVFSZONE2STOPCNT__SHIFT', + 'RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT_MASK', + 'RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT__SHIFT', + 'RTAVFS_REG30__RTAVFSZONE4INTERCEPT_MASK', + 'RTAVFS_REG30__RTAVFSZONE4INTERCEPT__SHIFT', + 'RTAVFS_REG31__RESERVED_MASK', 'RTAVFS_REG31__RESERVED__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV0_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV0__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV1_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV1__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV2_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV2__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV3_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV3__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV4_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV4__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV5_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV5__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV6_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV6__SHIFT', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV7_MASK', + 'RTAVFS_REG31__RTAVFSCPOCLKDIV7__SHIFT', + 'RTAVFS_REG32__RESERVED_MASK', 'RTAVFS_REG32__RESERVED__SHIFT', + 'RTAVFS_REG32__RTAVFSFSMSTARTUPCNT_MASK', + 'RTAVFS_REG32__RTAVFSFSMSTARTUPCNT__SHIFT', + 'RTAVFS_REG33__RESERVED_MASK', 'RTAVFS_REG33__RESERVED__SHIFT', + 'RTAVFS_REG33__RTAVFSFSMIDLECNT_MASK', + 'RTAVFS_REG33__RTAVFSFSMIDLECNT__SHIFT', + 'RTAVFS_REG34__RESERVED_MASK', 'RTAVFS_REG34__RESERVED__SHIFT', + 'RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT_MASK', + 'RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT__SHIFT', + 'RTAVFS_REG35__RESERVED_MASK', 'RTAVFS_REG35__RESERVED__SHIFT', + 'RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT_MASK', + 'RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT__SHIFT', + 'RTAVFS_REG36__RESERVED_MASK', 'RTAVFS_REG36__RESERVED__SHIFT', + 'RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT_MASK', + 'RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT__SHIFT', + 'RTAVFS_REG37__RESERVED_MASK', 'RTAVFS_REG37__RESERVED__SHIFT', + 'RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT_MASK', + 'RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT__SHIFT', + 'RTAVFS_REG38__RESERVED_MASK', 'RTAVFS_REG38__RESERVED__SHIFT', + 'RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT_MASK', + 'RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT__SHIFT', + 'RTAVFS_REG39__RESERVED_MASK', 'RTAVFS_REG39__RESERVED__SHIFT', + 'RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT_MASK', + 'RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT__SHIFT', + 'RTAVFS_REG3__RTAVFSZONE3STARTCNT_MASK', + 'RTAVFS_REG3__RTAVFSZONE3STARTCNT__SHIFT', + 'RTAVFS_REG3__RTAVFSZONE3STOPCNT_MASK', + 'RTAVFS_REG3__RTAVFSZONE3STOPCNT__SHIFT', + 'RTAVFS_REG40__RESERVED_MASK', 'RTAVFS_REG40__RESERVED__SHIFT', + 'RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT_MASK', + 'RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT__SHIFT', + 'RTAVFS_REG41__RESERVED_MASK', 'RTAVFS_REG41__RESERVED__SHIFT', + 'RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT_MASK', + 'RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT__SHIFT', + 'RTAVFS_REG42__RESERVED_MASK', 'RTAVFS_REG42__RESERVED__SHIFT', + 'RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT_MASK', + 'RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT__SHIFT', + 'RTAVFS_REG43__RTAVFSKI0_MASK', 'RTAVFS_REG43__RTAVFSKI0__SHIFT', + 'RTAVFS_REG43__RTAVFSKI1_MASK', 'RTAVFS_REG43__RTAVFSKI1__SHIFT', + 'RTAVFS_REG43__RTAVFSKI2_MASK', 'RTAVFS_REG43__RTAVFSKI2__SHIFT', + 'RTAVFS_REG43__RTAVFSKI3_MASK', 'RTAVFS_REG43__RTAVFSKI3__SHIFT', + 'RTAVFS_REG43__RTAVFSKP0_MASK', 'RTAVFS_REG43__RTAVFSKP0__SHIFT', + 'RTAVFS_REG43__RTAVFSKP1_MASK', 'RTAVFS_REG43__RTAVFSKP1__SHIFT', + 'RTAVFS_REG43__RTAVFSKP2_MASK', 'RTAVFS_REG43__RTAVFSKP2__SHIFT', + 'RTAVFS_REG43__RTAVFSKP3_MASK', 'RTAVFS_REG43__RTAVFSKP3__SHIFT', + 'RTAVFS_REG44__RTAVFSUSEBINARYSEARCH_MASK', + 'RTAVFS_REG44__RTAVFSUSEBINARYSEARCH__SHIFT', + 'RTAVFS_REG44__RTAVFSV1_MASK', 'RTAVFS_REG44__RTAVFSV1__SHIFT', + 'RTAVFS_REG44__RTAVFSV2_MASK', 'RTAVFS_REG44__RTAVFSV2__SHIFT', + 'RTAVFS_REG44__RTAVFSV3_MASK', 'RTAVFS_REG44__RTAVFSV3__SHIFT', + 'RTAVFS_REG44__RTAVFSVOLTCODEHWCAL_MASK', + 'RTAVFS_REG44__RTAVFSVOLTCODEHWCAL__SHIFT', + 'RTAVFS_REG45__RESERVED_MASK', 'RTAVFS_REG45__RESERVED__SHIFT', + 'RTAVFS_REG45__RTAVFSBGENABLE_MASK', + 'RTAVFS_REG45__RTAVFSBGENABLE__SHIFT', + 'RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING_MASK', + 'RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING__SHIFT', + 'RTAVFS_REG45__RTAVFSLOWPWREN_MASK', + 'RTAVFS_REG45__RTAVFSLOWPWREN__SHIFT', + 'RTAVFS_REG45__RTAVFSUREGENABLE_MASK', + 'RTAVFS_REG45__RTAVFSUREGENABLE__SHIFT', + 'RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL_MASK', + 'RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL__SHIFT', + 'RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE_MASK', + 'RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE__SHIFT', + 'RTAVFS_REG45__RTAVFSVRBLEEDCNTRL_MASK', + 'RTAVFS_REG45__RTAVFSVRBLEEDCNTRL__SHIFT', + 'RTAVFS_REG45__RTAVFSVRENABLE_MASK', + 'RTAVFS_REG45__RTAVFSVRENABLE__SHIFT', + 'RTAVFS_REG46__RESERVED_MASK', 'RTAVFS_REG46__RESERVED__SHIFT', + 'RTAVFS_REG46__RTAVFSKI_MASK', 'RTAVFS_REG46__RTAVFSKI__SHIFT', + 'RTAVFS_REG46__RTAVFSKP_MASK', 'RTAVFS_REG46__RTAVFSKP__SHIFT', + 'RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP_MASK', + 'RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP__SHIFT', + 'RTAVFS_REG46__RTAVFSPIERREN_MASK', + 'RTAVFS_REG46__RTAVFSPIERREN__SHIFT', + 'RTAVFS_REG46__RTAVFSPISHIFTOUT_MASK', + 'RTAVFS_REG46__RTAVFSPISHIFTOUT__SHIFT', + 'RTAVFS_REG46__RTAVFSPISHIFT_MASK', + 'RTAVFS_REG46__RTAVFSPISHIFT__SHIFT', + 'RTAVFS_REG46__RTAVFSUSELUTKPKI_MASK', + 'RTAVFS_REG46__RTAVFSUSELUTKPKI__SHIFT', + 'RTAVFS_REG47__RESERVED_MASK', 'RTAVFS_REG47__RESERVED__SHIFT', + 'RTAVFS_REG47__RTAVFSFORCEDISABLEPI_MASK', + 'RTAVFS_REG47__RTAVFSFORCEDISABLEPI__SHIFT', + 'RTAVFS_REG47__RTAVFSPIERRMASK_MASK', + 'RTAVFS_REG47__RTAVFSPIERRMASK__SHIFT', + 'RTAVFS_REG47__RTAVFSVOLTCODEPIMAX_MASK', + 'RTAVFS_REG47__RTAVFSVOLTCODEPIMAX__SHIFT', + 'RTAVFS_REG47__RTAVFSVOLTCODEPIMIN_MASK', + 'RTAVFS_REG47__RTAVFSVOLTCODEPIMIN__SHIFT', + 'RTAVFS_REG48__RTAVFSPIERRTHRESHOLD_MASK', + 'RTAVFS_REG48__RTAVFSPIERRTHRESHOLD__SHIFT', + 'RTAVFS_REG48__RTAVFSPILOOPNITERATIONS_MASK', + 'RTAVFS_REG48__RTAVFSPILOOPNITERATIONS__SHIFT', + 'RTAVFS_REG49__RESERVED_MASK', 'RTAVFS_REG49__RESERVED__SHIFT', + 'RTAVFS_REG49__RTAVFSPSMAVGDIVVDD_MASK', + 'RTAVFS_REG49__RTAVFSPSMAVGDIVVDD__SHIFT', + 'RTAVFS_REG49__RTAVFSPSMAVGENVDD_MASK', + 'RTAVFS_REG49__RTAVFSPSMAVGENVDD__SHIFT', + 'RTAVFS_REG49__RTAVFSPSMCLKDIVVDD_MASK', + 'RTAVFS_REG49__RTAVFSPSMCLKDIVVDD__SHIFT', + 'RTAVFS_REG49__RTAVFSPSMMEASMAXVDD_MASK', + 'RTAVFS_REG49__RTAVFSPSMMEASMAXVDD__SHIFT', + 'RTAVFS_REG49__RTAVFSPSMOSCENVDD_MASK', + 'RTAVFS_REG49__RTAVFSPSMOSCENVDD__SHIFT', + 'RTAVFS_REG49__RTAVFSPSMRSTAVGVDD_MASK', + 'RTAVFS_REG49__RTAVFSPSMRSTAVGVDD__SHIFT', + 'RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD_MASK', + 'RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD__SHIFT', + 'RTAVFS_REG4__RTAVFSZONE4STARTCNT_MASK', + 'RTAVFS_REG4__RTAVFSZONE4STARTCNT__SHIFT', + 'RTAVFS_REG4__RTAVFSZONE4STOPCNT_MASK', + 'RTAVFS_REG4__RTAVFSZONE4STOPCNT__SHIFT', + 'RTAVFS_REG50__RESERVED_MASK', 'RTAVFS_REG50__RESERVED__SHIFT', + 'RTAVFS_REG50__RTAVFSPSMAVGDIVVREG_MASK', + 'RTAVFS_REG50__RTAVFSPSMAVGDIVVREG__SHIFT', + 'RTAVFS_REG50__RTAVFSPSMAVGENVREG_MASK', + 'RTAVFS_REG50__RTAVFSPSMAVGENVREG__SHIFT', + 'RTAVFS_REG50__RTAVFSPSMCLKDIVVREG_MASK', + 'RTAVFS_REG50__RTAVFSPSMCLKDIVVREG__SHIFT', + 'RTAVFS_REG50__RTAVFSPSMMEASMAXVREG_MASK', + 'RTAVFS_REG50__RTAVFSPSMMEASMAXVREG__SHIFT', + 'RTAVFS_REG50__RTAVFSPSMOSCENVREG_MASK', + 'RTAVFS_REG50__RTAVFSPSMOSCENVREG__SHIFT', + 'RTAVFS_REG50__RTAVFSPSMRSTAVGVREG_MASK', + 'RTAVFS_REG50__RTAVFSPSMRSTAVGVREG__SHIFT', + 'RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG_MASK', + 'RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG__SHIFT', + 'RTAVFS_REG51__RESERVED_MASK', 'RTAVFS_REG51__RESERVED__SHIFT', + 'RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND_MASK', + 'RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND__SHIFT', + 'RTAVFS_REG51__RTAVFSAVFSENABLE_MASK', + 'RTAVFS_REG51__RTAVFSAVFSENABLE__SHIFT', + 'RTAVFS_REG51__RTAVFSCPOTURNONDELAY_MASK', + 'RTAVFS_REG51__RTAVFSCPOTURNONDELAY__SHIFT', + 'RTAVFS_REG51__RTAVFSSELECTMINMAX_MASK', + 'RTAVFS_REG51__RTAVFSSELECTMINMAX__SHIFT', + 'RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING_MASK', + 'RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING__SHIFT', + 'RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT_MASK', + 'RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT__SHIFT', + 'RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT_MASK', + 'RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT__SHIFT', + 'RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES_MASK', + 'RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES__SHIFT', + 'RTAVFS_REG52__RESERVED_MASK', 'RTAVFS_REG52__RESERVED__SHIFT', + 'RTAVFS_REG52__RTAVFSAVGPSMVDD_MASK', + 'RTAVFS_REG52__RTAVFSAVGPSMVDD__SHIFT', + 'RTAVFS_REG52__RTAVFSMINMAXPSMVDD_MASK', + 'RTAVFS_REG52__RTAVFSMINMAXPSMVDD__SHIFT', + 'RTAVFS_REG53__RESERVED_MASK', 'RTAVFS_REG53__RESERVED__SHIFT', + 'RTAVFS_REG53__RTAVFSAVGPSMVREG_MASK', + 'RTAVFS_REG53__RTAVFSAVGPSMVREG__SHIFT', + 'RTAVFS_REG53__RTAVFSMINMAXPSMVREG_MASK', + 'RTAVFS_REG53__RTAVFSMINMAXPSMVREG__SHIFT', + 'RTAVFS_REG54__RTAVFSCPO0_STARTCNT_MASK', + 'RTAVFS_REG54__RTAVFSCPO0_STARTCNT__SHIFT', + 'RTAVFS_REG54__RTAVFSCPO0_STOPCNT_MASK', + 'RTAVFS_REG54__RTAVFSCPO0_STOPCNT__SHIFT', + 'RTAVFS_REG55__RTAVFSCPO1_STARTCNT_MASK', + 'RTAVFS_REG55__RTAVFSCPO1_STARTCNT__SHIFT', + 'RTAVFS_REG55__RTAVFSCPO1_STOPCNT_MASK', + 'RTAVFS_REG55__RTAVFSCPO1_STOPCNT__SHIFT', + 'RTAVFS_REG56__RTAVFSCPO2_STARTCNT_MASK', + 'RTAVFS_REG56__RTAVFSCPO2_STARTCNT__SHIFT', + 'RTAVFS_REG56__RTAVFSCPO2_STOPCNT_MASK', + 'RTAVFS_REG56__RTAVFSCPO2_STOPCNT__SHIFT', + 'RTAVFS_REG57__RTAVFSCPO3_STARTCNT_MASK', + 'RTAVFS_REG57__RTAVFSCPO3_STARTCNT__SHIFT', + 'RTAVFS_REG57__RTAVFSCPO3_STOPCNT_MASK', + 'RTAVFS_REG57__RTAVFSCPO3_STOPCNT__SHIFT', + 'RTAVFS_REG58__RTAVFSCPO4_STARTCNT_MASK', + 'RTAVFS_REG58__RTAVFSCPO4_STARTCNT__SHIFT', + 'RTAVFS_REG58__RTAVFSCPO4_STOPCNT_MASK', + 'RTAVFS_REG58__RTAVFSCPO4_STOPCNT__SHIFT', + 'RTAVFS_REG59__RTAVFSCPO5_STARTCNT_MASK', + 'RTAVFS_REG59__RTAVFSCPO5_STARTCNT__SHIFT', + 'RTAVFS_REG59__RTAVFSCPO5_STOPCNT_MASK', + 'RTAVFS_REG59__RTAVFSCPO5_STOPCNT__SHIFT', + 'RTAVFS_REG5__RTAVFSZONE0EN0_MASK', + 'RTAVFS_REG5__RTAVFSZONE0EN0__SHIFT', + 'RTAVFS_REG60__RTAVFSCPO6_STARTCNT_MASK', + 'RTAVFS_REG60__RTAVFSCPO6_STARTCNT__SHIFT', + 'RTAVFS_REG60__RTAVFSCPO6_STOPCNT_MASK', + 'RTAVFS_REG60__RTAVFSCPO6_STOPCNT__SHIFT', + 'RTAVFS_REG61__RTAVFSCPO7_STARTCNT_MASK', + 'RTAVFS_REG61__RTAVFSCPO7_STARTCNT__SHIFT', + 'RTAVFS_REG61__RTAVFSCPO7_STOPCNT_MASK', + 'RTAVFS_REG61__RTAVFSCPO7_STOPCNT__SHIFT', + 'RTAVFS_REG62__RTAVFSCPO8_STARTCNT_MASK', + 'RTAVFS_REG62__RTAVFSCPO8_STARTCNT__SHIFT', + 'RTAVFS_REG62__RTAVFSCPO8_STOPCNT_MASK', + 'RTAVFS_REG62__RTAVFSCPO8_STOPCNT__SHIFT', + 'RTAVFS_REG63__RTAVFSCPO9_STARTCNT_MASK', + 'RTAVFS_REG63__RTAVFSCPO9_STARTCNT__SHIFT', + 'RTAVFS_REG63__RTAVFSCPO9_STOPCNT_MASK', + 'RTAVFS_REG63__RTAVFSCPO9_STOPCNT__SHIFT', + 'RTAVFS_REG64__RTAVFSCPO10_STARTCNT_MASK', + 'RTAVFS_REG64__RTAVFSCPO10_STARTCNT__SHIFT', + 'RTAVFS_REG64__RTAVFSCPO10_STOPCNT_MASK', + 'RTAVFS_REG64__RTAVFSCPO10_STOPCNT__SHIFT', + 'RTAVFS_REG65__RTAVFSCPO11_STARTCNT_MASK', + 'RTAVFS_REG65__RTAVFSCPO11_STARTCNT__SHIFT', + 'RTAVFS_REG65__RTAVFSCPO11_STOPCNT_MASK', + 'RTAVFS_REG65__RTAVFSCPO11_STOPCNT__SHIFT', + 'RTAVFS_REG66__RTAVFSCPO12_STARTCNT_MASK', + 'RTAVFS_REG66__RTAVFSCPO12_STARTCNT__SHIFT', + 'RTAVFS_REG66__RTAVFSCPO12_STOPCNT_MASK', + 'RTAVFS_REG66__RTAVFSCPO12_STOPCNT__SHIFT', + 'RTAVFS_REG67__RTAVFSCPO13_STARTCNT_MASK', + 'RTAVFS_REG67__RTAVFSCPO13_STARTCNT__SHIFT', + 'RTAVFS_REG67__RTAVFSCPO13_STOPCNT_MASK', + 'RTAVFS_REG67__RTAVFSCPO13_STOPCNT__SHIFT', + 'RTAVFS_REG68__RTAVFSCPO14_STARTCNT_MASK', + 'RTAVFS_REG68__RTAVFSCPO14_STARTCNT__SHIFT', + 'RTAVFS_REG68__RTAVFSCPO14_STOPCNT_MASK', + 'RTAVFS_REG68__RTAVFSCPO14_STOPCNT__SHIFT', + 'RTAVFS_REG69__RTAVFSCPO15_STARTCNT_MASK', + 'RTAVFS_REG69__RTAVFSCPO15_STARTCNT__SHIFT', + 'RTAVFS_REG69__RTAVFSCPO15_STOPCNT_MASK', + 'RTAVFS_REG69__RTAVFSCPO15_STOPCNT__SHIFT', + 'RTAVFS_REG6__RTAVFSZONE0EN1_MASK', + 'RTAVFS_REG6__RTAVFSZONE0EN1__SHIFT', + 'RTAVFS_REG70__RTAVFSCPO16_STARTCNT_MASK', + 'RTAVFS_REG70__RTAVFSCPO16_STARTCNT__SHIFT', + 'RTAVFS_REG70__RTAVFSCPO16_STOPCNT_MASK', + 'RTAVFS_REG70__RTAVFSCPO16_STOPCNT__SHIFT', + 'RTAVFS_REG71__RTAVFSCPO17_STARTCNT_MASK', + 'RTAVFS_REG71__RTAVFSCPO17_STARTCNT__SHIFT', + 'RTAVFS_REG71__RTAVFSCPO17_STOPCNT_MASK', + 'RTAVFS_REG71__RTAVFSCPO17_STOPCNT__SHIFT', + 'RTAVFS_REG72__RTAVFSCPO18_STARTCNT_MASK', + 'RTAVFS_REG72__RTAVFSCPO18_STARTCNT__SHIFT', + 'RTAVFS_REG72__RTAVFSCPO18_STOPCNT_MASK', + 'RTAVFS_REG72__RTAVFSCPO18_STOPCNT__SHIFT', + 'RTAVFS_REG73__RTAVFSCPO19_STARTCNT_MASK', + 'RTAVFS_REG73__RTAVFSCPO19_STARTCNT__SHIFT', + 'RTAVFS_REG73__RTAVFSCPO19_STOPCNT_MASK', + 'RTAVFS_REG73__RTAVFSCPO19_STOPCNT__SHIFT', + 'RTAVFS_REG74__RTAVFSCPO20_STARTCNT_MASK', + 'RTAVFS_REG74__RTAVFSCPO20_STARTCNT__SHIFT', + 'RTAVFS_REG74__RTAVFSCPO20_STOPCNT_MASK', + 'RTAVFS_REG74__RTAVFSCPO20_STOPCNT__SHIFT', + 'RTAVFS_REG75__RTAVFSCPO21_STARTCNT_MASK', + 'RTAVFS_REG75__RTAVFSCPO21_STARTCNT__SHIFT', + 'RTAVFS_REG75__RTAVFSCPO21_STOPCNT_MASK', + 'RTAVFS_REG75__RTAVFSCPO21_STOPCNT__SHIFT', + 'RTAVFS_REG76__RTAVFSCPO22_STARTCNT_MASK', + 'RTAVFS_REG76__RTAVFSCPO22_STARTCNT__SHIFT', + 'RTAVFS_REG76__RTAVFSCPO22_STOPCNT_MASK', + 'RTAVFS_REG76__RTAVFSCPO22_STOPCNT__SHIFT', + 'RTAVFS_REG77__RTAVFSCPO23_STARTCNT_MASK', + 'RTAVFS_REG77__RTAVFSCPO23_STARTCNT__SHIFT', + 'RTAVFS_REG77__RTAVFSCPO23_STOPCNT_MASK', + 'RTAVFS_REG77__RTAVFSCPO23_STOPCNT__SHIFT', + 'RTAVFS_REG78__RTAVFSCPO24_STARTCNT_MASK', + 'RTAVFS_REG78__RTAVFSCPO24_STARTCNT__SHIFT', + 'RTAVFS_REG78__RTAVFSCPO24_STOPCNT_MASK', + 'RTAVFS_REG78__RTAVFSCPO24_STOPCNT__SHIFT', + 'RTAVFS_REG79__RTAVFSCPO25_STARTCNT_MASK', + 'RTAVFS_REG79__RTAVFSCPO25_STARTCNT__SHIFT', + 'RTAVFS_REG79__RTAVFSCPO25_STOPCNT_MASK', + 'RTAVFS_REG79__RTAVFSCPO25_STOPCNT__SHIFT', + 'RTAVFS_REG7__RTAVFSZONE1EN0_MASK', + 'RTAVFS_REG7__RTAVFSZONE1EN0__SHIFT', + 'RTAVFS_REG80__RTAVFSCPO26_STARTCNT_MASK', + 'RTAVFS_REG80__RTAVFSCPO26_STARTCNT__SHIFT', + 'RTAVFS_REG80__RTAVFSCPO26_STOPCNT_MASK', + 'RTAVFS_REG80__RTAVFSCPO26_STOPCNT__SHIFT', + 'RTAVFS_REG81__RTAVFSCPO27_STARTCNT_MASK', + 'RTAVFS_REG81__RTAVFSCPO27_STARTCNT__SHIFT', + 'RTAVFS_REG81__RTAVFSCPO27_STOPCNT_MASK', + 'RTAVFS_REG81__RTAVFSCPO27_STOPCNT__SHIFT', + 'RTAVFS_REG82__RTAVFSCPO28_STARTCNT_MASK', + 'RTAVFS_REG82__RTAVFSCPO28_STARTCNT__SHIFT', + 'RTAVFS_REG82__RTAVFSCPO28_STOPCNT_MASK', + 'RTAVFS_REG82__RTAVFSCPO28_STOPCNT__SHIFT', + 'RTAVFS_REG83__RTAVFSCPO29_STARTCNT_MASK', + 'RTAVFS_REG83__RTAVFSCPO29_STARTCNT__SHIFT', + 'RTAVFS_REG83__RTAVFSCPO29_STOPCNT_MASK', + 'RTAVFS_REG83__RTAVFSCPO29_STOPCNT__SHIFT', + 'RTAVFS_REG84__RTAVFSCPO30_STARTCNT_MASK', + 'RTAVFS_REG84__RTAVFSCPO30_STARTCNT__SHIFT', + 'RTAVFS_REG84__RTAVFSCPO30_STOPCNT_MASK', + 'RTAVFS_REG84__RTAVFSCPO30_STOPCNT__SHIFT', + 'RTAVFS_REG85__RTAVFSCPO31_STARTCNT_MASK', + 'RTAVFS_REG85__RTAVFSCPO31_STARTCNT__SHIFT', + 'RTAVFS_REG85__RTAVFSCPO31_STOPCNT_MASK', + 'RTAVFS_REG85__RTAVFSCPO31_STOPCNT__SHIFT', + 'RTAVFS_REG86__RTAVFSCPO32_STARTCNT_MASK', + 'RTAVFS_REG86__RTAVFSCPO32_STARTCNT__SHIFT', + 'RTAVFS_REG86__RTAVFSCPO32_STOPCNT_MASK', + 'RTAVFS_REG86__RTAVFSCPO32_STOPCNT__SHIFT', + 'RTAVFS_REG87__RTAVFSCPO33_STARTCNT_MASK', + 'RTAVFS_REG87__RTAVFSCPO33_STARTCNT__SHIFT', + 'RTAVFS_REG87__RTAVFSCPO33_STOPCNT_MASK', + 'RTAVFS_REG87__RTAVFSCPO33_STOPCNT__SHIFT', + 'RTAVFS_REG88__RTAVFSCPO34_STARTCNT_MASK', + 'RTAVFS_REG88__RTAVFSCPO34_STARTCNT__SHIFT', + 'RTAVFS_REG88__RTAVFSCPO34_STOPCNT_MASK', + 'RTAVFS_REG88__RTAVFSCPO34_STOPCNT__SHIFT', + 'RTAVFS_REG89__RTAVFSCPO35_STARTCNT_MASK', + 'RTAVFS_REG89__RTAVFSCPO35_STARTCNT__SHIFT', + 'RTAVFS_REG89__RTAVFSCPO35_STOPCNT_MASK', + 'RTAVFS_REG89__RTAVFSCPO35_STOPCNT__SHIFT', + 'RTAVFS_REG8__RTAVFSZONE1EN1_MASK', + 'RTAVFS_REG8__RTAVFSZONE1EN1__SHIFT', + 'RTAVFS_REG90__RTAVFSCPO36_STARTCNT_MASK', + 'RTAVFS_REG90__RTAVFSCPO36_STARTCNT__SHIFT', + 'RTAVFS_REG90__RTAVFSCPO36_STOPCNT_MASK', + 'RTAVFS_REG90__RTAVFSCPO36_STOPCNT__SHIFT', + 'RTAVFS_REG91__RTAVFSCPO37_STARTCNT_MASK', + 'RTAVFS_REG91__RTAVFSCPO37_STARTCNT__SHIFT', + 'RTAVFS_REG91__RTAVFSCPO37_STOPCNT_MASK', + 'RTAVFS_REG91__RTAVFSCPO37_STOPCNT__SHIFT', + 'RTAVFS_REG92__RTAVFSCPO38_STARTCNT_MASK', + 'RTAVFS_REG92__RTAVFSCPO38_STARTCNT__SHIFT', + 'RTAVFS_REG92__RTAVFSCPO38_STOPCNT_MASK', + 'RTAVFS_REG92__RTAVFSCPO38_STOPCNT__SHIFT', + 'RTAVFS_REG93__RTAVFSCPO39_STARTCNT_MASK', + 'RTAVFS_REG93__RTAVFSCPO39_STARTCNT__SHIFT', + 'RTAVFS_REG93__RTAVFSCPO39_STOPCNT_MASK', + 'RTAVFS_REG93__RTAVFSCPO39_STOPCNT__SHIFT', + 'RTAVFS_REG94__RTAVFSCPO40_STARTCNT_MASK', + 'RTAVFS_REG94__RTAVFSCPO40_STARTCNT__SHIFT', + 'RTAVFS_REG94__RTAVFSCPO40_STOPCNT_MASK', + 'RTAVFS_REG94__RTAVFSCPO40_STOPCNT__SHIFT', + 'RTAVFS_REG95__RTAVFSCPO41_STARTCNT_MASK', + 'RTAVFS_REG95__RTAVFSCPO41_STARTCNT__SHIFT', + 'RTAVFS_REG95__RTAVFSCPO41_STOPCNT_MASK', + 'RTAVFS_REG95__RTAVFSCPO41_STOPCNT__SHIFT', + 'RTAVFS_REG96__RTAVFSCPO42_STARTCNT_MASK', + 'RTAVFS_REG96__RTAVFSCPO42_STARTCNT__SHIFT', + 'RTAVFS_REG96__RTAVFSCPO42_STOPCNT_MASK', + 'RTAVFS_REG96__RTAVFSCPO42_STOPCNT__SHIFT', + 'RTAVFS_REG97__RTAVFSCPO43_STARTCNT_MASK', + 'RTAVFS_REG97__RTAVFSCPO43_STARTCNT__SHIFT', + 'RTAVFS_REG97__RTAVFSCPO43_STOPCNT_MASK', + 'RTAVFS_REG97__RTAVFSCPO43_STOPCNT__SHIFT', + 'RTAVFS_REG98__RTAVFSCPO44_STARTCNT_MASK', + 'RTAVFS_REG98__RTAVFSCPO44_STARTCNT__SHIFT', + 'RTAVFS_REG98__RTAVFSCPO44_STOPCNT_MASK', + 'RTAVFS_REG98__RTAVFSCPO44_STOPCNT__SHIFT', + 'RTAVFS_REG99__RTAVFSCPO45_STARTCNT_MASK', + 'RTAVFS_REG99__RTAVFSCPO45_STARTCNT__SHIFT', + 'RTAVFS_REG99__RTAVFSCPO45_STOPCNT_MASK', + 'RTAVFS_REG99__RTAVFSCPO45_STOPCNT__SHIFT', + 'RTAVFS_REG9__RTAVFSZONE2EN0_MASK', + 'RTAVFS_REG9__RTAVFSZONE2EN0__SHIFT', + 'RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK', + 'RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT', + 'RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK', + 'RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT', + 'SCRATCH_REG0__SCRATCH_REG0_MASK', + 'SCRATCH_REG0__SCRATCH_REG0__SHIFT', + 'SCRATCH_REG1__SCRATCH_REG1_MASK', + 'SCRATCH_REG1__SCRATCH_REG1__SHIFT', + 'SCRATCH_REG2__SCRATCH_REG2_MASK', + 'SCRATCH_REG2__SCRATCH_REG2__SHIFT', + 'SCRATCH_REG3__SCRATCH_REG3_MASK', + 'SCRATCH_REG3__SCRATCH_REG3__SHIFT', + 'SCRATCH_REG4__SCRATCH_REG4_MASK', + 'SCRATCH_REG4__SCRATCH_REG4__SHIFT', + 'SCRATCH_REG5__SCRATCH_REG5_MASK', + 'SCRATCH_REG5__SCRATCH_REG5__SHIFT', + 'SCRATCH_REG6__SCRATCH_REG6_MASK', + 'SCRATCH_REG6__SCRATCH_REG6__SHIFT', + 'SCRATCH_REG7__SCRATCH_REG7_MASK', + 'SCRATCH_REG7__SCRATCH_REG7__SHIFT', + 'SCRATCH_REG_ATOMIC__ID_MASK', 'SCRATCH_REG_ATOMIC__ID__SHIFT', + 'SCRATCH_REG_ATOMIC__IMMED_MASK', + 'SCRATCH_REG_ATOMIC__IMMED__SHIFT', 'SCRATCH_REG_ATOMIC__OP_MASK', + 'SCRATCH_REG_ATOMIC__OP__SHIFT', + 'SCRATCH_REG_ATOMIC__reserved27_MASK', + 'SCRATCH_REG_ATOMIC__reserved27__SHIFT', + 'SCRATCH_REG_ATOMIC__reserved31_MASK', + 'SCRATCH_REG_ATOMIC__reserved31__SHIFT', + 'SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK', + 'SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT', + 'SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK', + 'SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT', + 'SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK', + 'SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT', + 'SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK', + 'SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT', + 'SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK', + 'SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT', + 'SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK', + 'SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT', + 'SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK', + 'SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT', + 'SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK', + 'SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT', + 'SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK', + 'SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT', + 'SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK', + 'SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT', + 'SDMA0_ATOMIC_PREOP_HI__DATA_MASK', + 'SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT', + 'SDMA0_ATOMIC_PREOP_LO__DATA_MASK', + 'SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT', + 'SDMA0_BA_THRESHOLD__READ_THRES_MASK', + 'SDMA0_BA_THRESHOLD__READ_THRES__SHIFT', + 'SDMA0_BA_THRESHOLD__WRITE_THRES_MASK', + 'SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT', + 'SDMA0_BROADCAST_UCODE_ADDR__THID_MASK', + 'SDMA0_BROADCAST_UCODE_ADDR__THID__SHIFT', + 'SDMA0_BROADCAST_UCODE_ADDR__VALUE_MASK', + 'SDMA0_BROADCAST_UCODE_ADDR__VALUE__SHIFT', + 'SDMA0_BROADCAST_UCODE_DATA__VALUE_MASK', + 'SDMA0_BROADCAST_UCODE_DATA__VALUE__SHIFT', + 'SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK', + 'SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT', + 'SDMA0_CE_CTRL__RD_LUT_DEPTH_MASK', + 'SDMA0_CE_CTRL__RD_LUT_DEPTH__SHIFT', + 'SDMA0_CE_CTRL__RD_LUT_WATERMARK_MASK', + 'SDMA0_CE_CTRL__RD_LUT_WATERMARK__SHIFT', + 'SDMA0_CE_CTRL__RESERVED_MASK', 'SDMA0_CE_CTRL__RESERVED__SHIFT', + 'SDMA0_CE_CTRL__WR_AFIFO_WATERMARK_MASK', + 'SDMA0_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT', + 'SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK', + 'SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT', + 'SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK', + 'SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT', + 'SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK', + 'SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT', + 'SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK', + 'SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT', + 'SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK', + 'SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT', + 'SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK', + 'SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT', + 'SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK', + 'SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT', + 'SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK', + 'SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT', + 'SDMA0_CHICKEN_BITS_2__RESERVED_14_12_MASK', + 'SDMA0_CHICKEN_BITS_2__RESERVED_14_12__SHIFT', + 'SDMA0_CHICKEN_BITS_2__RESERVED_15_MASK', + 'SDMA0_CHICKEN_BITS_2__RESERVED_15__SHIFT', + 'SDMA0_CHICKEN_BITS_2__RESERVED_22_20_MASK', + 'SDMA0_CHICKEN_BITS_2__RESERVED_22_20__SHIFT', + 'SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK', + 'SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT', + 'SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK', + 'SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT', + 'SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK', + 'SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT', + 'SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK', + 'SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT', + 'SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK', + 'SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT', + 'SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT', + 'SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT', + 'SDMA0_CHICKEN_BITS__RD_BURST_MASK', + 'SDMA0_CHICKEN_BITS__RD_BURST__SHIFT', + 'SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT', + 'SDMA0_CHICKEN_BITS__RESERVED_MASK', + 'SDMA0_CHICKEN_BITS__RESERVED__SHIFT', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK', + 'SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT', + 'SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK', + 'SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT', + 'SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT', + 'SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT', + 'SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT', + 'SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT', + 'SDMA0_CHICKEN_BITS__WR_BURST_MASK', + 'SDMA0_CHICKEN_BITS__WR_BURST__SHIFT', + 'SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK', + 'SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT', + 'SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK', + 'SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT', + 'SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK', + 'SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT', + 'SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK', + 'SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT', + 'SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK', + 'SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT', + 'SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK', + 'SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT', + 'SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK', + 'SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT', + 'SDMA0_CNTL1__WPTR_POLL_FREQUENCY_MASK', + 'SDMA0_CNTL1__WPTR_POLL_FREQUENCY__SHIFT', + 'SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK', + 'SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT', + 'SDMA0_CNTL__CP_MES_INT_ENABLE_MASK', + 'SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK', + 'SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__DATA_SWAP_ENABLE_MASK', + 'SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT', + 'SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK', + 'SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT', + 'SDMA0_CNTL__FROZEN_INT_ENABLE_MASK', + 'SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK', + 'SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK', + 'SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT', + 'SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK', + 'SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT', + 'SDMA0_CNTL__PAGE_FAULT_INT_ENABLE_MASK', + 'SDMA0_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__PAGE_NULL_INT_ENABLE_MASK', + 'SDMA0_CNTL__PAGE_NULL_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK', + 'SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__PIO_DONE_ACK_ENABLE_MASK', + 'SDMA0_CNTL__PIO_DONE_ACK_ENABLE__SHIFT', + 'SDMA0_CNTL__RB_PREEMPT_INT_ENABLE_MASK', + 'SDMA0_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK', + 'SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT', + 'SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_CNTL__TRAP_ENABLE_MASK', 'SDMA0_CNTL__TRAP_ENABLE__SHIFT', + 'SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK', + 'SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT', + 'SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK', + 'SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT', + 'SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK', + 'SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT', + 'SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK', + 'SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT', + 'SDMA0_DEC_START__START_MASK', 'SDMA0_DEC_START__START__SHIFT', + 'SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK', + 'SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT', + 'SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK', + 'SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT', + 'SDMA0_EDC_CONFIG__DIS_EDC_MASK', + 'SDMA0_EDC_CONFIG__DIS_EDC__SHIFT', + 'SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK', + 'SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT', + 'SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK', + 'SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK', + 'SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT', + 'SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK', + 'SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT', + 'SDMA0_ERROR_LOG__OVERRIDE_MASK', + 'SDMA0_ERROR_LOG__OVERRIDE__SHIFT', + 'SDMA0_ERROR_LOG__STATUS_MASK', 'SDMA0_ERROR_LOG__STATUS__SHIFT', + 'SDMA0_F32_CNTL__HALT_MASK', 'SDMA0_F32_CNTL__HALT__SHIFT', + 'SDMA0_F32_CNTL__TH0_CHECKSUM_CLR_MASK', + 'SDMA0_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT', + 'SDMA0_F32_CNTL__TH0_ENABLE_MASK', + 'SDMA0_F32_CNTL__TH0_ENABLE__SHIFT', + 'SDMA0_F32_CNTL__TH0_PRIORITY_MASK', + 'SDMA0_F32_CNTL__TH0_PRIORITY__SHIFT', + 'SDMA0_F32_CNTL__TH0_RESET_MASK', + 'SDMA0_F32_CNTL__TH0_RESET__SHIFT', + 'SDMA0_F32_CNTL__TH1_CHECKSUM_CLR_MASK', + 'SDMA0_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT', + 'SDMA0_F32_CNTL__TH1_ENABLE_MASK', + 'SDMA0_F32_CNTL__TH1_ENABLE__SHIFT', + 'SDMA0_F32_CNTL__TH1_PRIORITY_MASK', + 'SDMA0_F32_CNTL__TH1_PRIORITY__SHIFT', + 'SDMA0_F32_CNTL__TH1_RESET_MASK', + 'SDMA0_F32_CNTL__TH1_RESET__SHIFT', + 'SDMA0_F32_COUNTER__VALUE_MASK', + 'SDMA0_F32_COUNTER__VALUE__SHIFT', + 'SDMA0_F32_MISC_CNTL__F32_WAKEUP_MASK', + 'SDMA0_F32_MISC_CNTL__F32_WAKEUP__SHIFT', + 'SDMA0_FED_STATUS__COPY_DATA_ECC_MASK', + 'SDMA0_FED_STATUS__COPY_DATA_ECC__SHIFT', + 'SDMA0_FED_STATUS__COPY_METADATA_ECC_MASK', + 'SDMA0_FED_STATUS__COPY_METADATA_ECC__SHIFT', + 'SDMA0_FED_STATUS__F32_DATA_ECC_MASK', + 'SDMA0_FED_STATUS__F32_DATA_ECC__SHIFT', + 'SDMA0_FED_STATUS__IB_FETCH_ECC_MASK', + 'SDMA0_FED_STATUS__IB_FETCH_ECC__SHIFT', + 'SDMA0_FED_STATUS__RB_FETCH_ECC_MASK', + 'SDMA0_FED_STATUS__RB_FETCH_ECC__SHIFT', + 'SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC_MASK', + 'SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT', + 'SDMA0_FED_STATUS__WPTR_ATOMIC_ECC_MASK', + 'SDMA0_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT', + 'SDMA0_FREEZE__F32_FREEZE_MASK', + 'SDMA0_FREEZE__F32_FREEZE__SHIFT', 'SDMA0_FREEZE__FREEZE_MASK', + 'SDMA0_FREEZE__FREEZE__SHIFT', 'SDMA0_FREEZE__FROZEN_MASK', + 'SDMA0_FREEZE__FROZEN__SHIFT', 'SDMA0_FREEZE__PREEMPT_MASK', + 'SDMA0_FREEZE__PREEMPT__SHIFT', + 'SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK', + 'SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK', + 'SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT', + 'SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK', + 'SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT', + 'SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK', + 'SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT', + 'SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK', + 'SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT', + 'SDMA0_GB_ADDR_CONFIG__NUM_PKRS_MASK', + 'SDMA0_GB_ADDR_CONFIG__NUM_PKRS__SHIFT', + 'SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK', + 'SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT', + 'SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK', + 'SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT', + 'SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK', + 'SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT', + 'SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK', + 'SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT', + 'SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK', + 'SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT', + 'SDMA0_GLOBAL_TIMESTAMP_HI__DATA_MASK', + 'SDMA0_GLOBAL_TIMESTAMP_HI__DATA__SHIFT', + 'SDMA0_GLOBAL_TIMESTAMP_LO__DATA_MASK', + 'SDMA0_GLOBAL_TIMESTAMP_LO__DATA__SHIFT', + 'SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK', + 'SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT', + 'SDMA0_HOLE_ADDR_HI__VALUE_MASK', + 'SDMA0_HOLE_ADDR_HI__VALUE__SHIFT', + 'SDMA0_HOLE_ADDR_LO__VALUE_MASK', + 'SDMA0_HOLE_ADDR_LO__VALUE__SHIFT', + 'SDMA0_IB_OFFSET_FETCH__OFFSET_MASK', + 'SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT', + 'SDMA0_ID__DEVICE_ID_MASK', 'SDMA0_ID__DEVICE_ID__SHIFT', + 'SDMA0_INT_STATUS__DATA_MASK', 'SDMA0_INT_STATUS__DATA__SHIFT', + 'SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK', + 'SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK', + 'SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK', + 'SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK', + 'SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT', + 'SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK', + 'SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT', + 'SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK', + 'SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT', + 'SDMA0_POWER_CNTL__LS_ENABLE_MASK', + 'SDMA0_POWER_CNTL__LS_ENABLE__SHIFT', + 'SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT', + 'SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT', + 'SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT', + 'SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT', + 'SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT', + 'SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT', + 'SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT', + 'SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK', + 'SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT', + 'SDMA0_PROGRAM__STREAM_MASK', 'SDMA0_PROGRAM__STREAM__SHIFT', + 'SDMA0_PUB_DUMMY_REG0__VALUE_MASK', + 'SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT', + 'SDMA0_PUB_DUMMY_REG1__VALUE_MASK', + 'SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT', + 'SDMA0_PUB_DUMMY_REG2__VALUE_MASK', + 'SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT', + 'SDMA0_PUB_DUMMY_REG3__VALUE_MASK', + 'SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE0_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE0_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE0_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE0_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE0_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE0_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE0_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE0_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE0_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE0_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE0_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE0_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE0_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE0_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE0_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE0_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE0_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE0_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE0_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE0_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE0_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE0_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE0_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE0_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE0_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE0_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE0_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE0_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE0_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE0_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE0_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE0_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE0_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE0_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE0_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE1_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE1_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE1_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE1_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE1_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE1_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE1_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE1_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE1_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE1_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE1_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE1_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE1_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE1_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE1_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE1_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE1_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE1_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE1_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE1_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE1_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE1_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE1_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE1_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE1_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE1_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE1_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE1_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE1_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE1_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE1_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE1_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE1_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE1_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE1_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE2_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE2_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE2_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE2_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE2_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE2_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE2_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE2_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE2_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE2_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE2_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE2_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE2_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE2_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE2_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE2_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE2_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE2_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE2_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE2_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE2_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE2_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE2_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE2_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE2_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE2_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE2_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE2_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE2_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE2_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE2_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE2_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE2_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE2_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE2_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE3_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE3_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE3_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE3_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE3_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE3_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE3_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE3_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE3_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE3_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE3_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE3_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE3_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE3_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE3_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE3_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE3_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE3_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE3_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE3_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE3_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE3_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE3_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE3_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE3_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE3_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE3_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE3_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE3_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE3_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE3_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE3_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE3_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE3_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE3_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE4_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE4_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE4_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE4_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE4_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE4_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE4_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE4_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE4_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE4_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE4_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE4_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE4_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE4_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE4_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE4_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE4_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE4_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE4_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE4_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE4_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE4_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE4_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE4_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE4_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE4_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE4_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE4_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE4_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE4_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE4_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE4_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE4_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE4_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE4_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE5_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE5_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE5_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE5_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE5_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE5_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE5_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE5_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE5_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE5_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE5_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE5_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE5_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE5_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE5_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE5_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE5_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE5_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE5_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE5_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE5_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE5_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE5_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE5_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE5_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE5_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE5_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE5_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE5_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE5_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE5_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE5_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE5_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE5_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE5_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE6_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE6_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE6_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE6_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE6_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE6_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE6_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE6_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE6_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE6_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE6_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE6_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE6_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE6_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE6_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE6_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE6_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE6_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE6_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE6_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE6_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE6_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE6_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE6_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE6_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE6_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE6_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE6_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE6_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE6_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE6_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE6_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE6_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE6_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE6_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__IDLE_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA0_QUEUE7_CSA_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE7_CSA_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA0_QUEUE7_DOORBELL_LOG__DATA_MASK', + 'SDMA0_QUEUE7_DOORBELL_LOG__DATA__SHIFT', + 'SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE7_DOORBELL__CAPTURED_MASK', + 'SDMA0_QUEUE7_DOORBELL__CAPTURED__SHIFT', + 'SDMA0_QUEUE7_DOORBELL__ENABLE_MASK', + 'SDMA0_QUEUE7_DOORBELL__ENABLE__SHIFT', + 'SDMA0_QUEUE7_DUMMY_REG__DUMMY_MASK', + 'SDMA0_QUEUE7_DUMMY_REG__DUMMY__SHIFT', + 'SDMA0_QUEUE7_IB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE7_IB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE7_IB_BASE_LO__ADDR_MASK', + 'SDMA0_QUEUE7_IB_BASE_LO__ADDR__SHIFT', + 'SDMA0_QUEUE7_IB_CNTL__CMD_VMID_MASK', + 'SDMA0_QUEUE7_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA0_QUEUE7_IB_CNTL__IB_ENABLE_MASK', + 'SDMA0_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA0_QUEUE7_IB_OFFSET__OFFSET_MASK', + 'SDMA0_QUEUE7_IB_OFFSET__OFFSET__SHIFT', + 'SDMA0_QUEUE7_IB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE7_IB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE7_IB_SIZE__SIZE_MASK', + 'SDMA0_QUEUE7_IB_SIZE__SIZE__SHIFT', + 'SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA0__DATA0_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA10__DATA10_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA1__DATA1_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA2__DATA2_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA3__DATA3_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA4__DATA4_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA5__DATA5_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA6__DATA6_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA7__DATA7_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA8__DATA8_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA0_QUEUE7_MIDCMD_DATA9__DATA9_MASK', + 'SDMA0_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA0_QUEUE7_PREEMPT__IB_PREEMPT_MASK', + 'SDMA0_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA0_QUEUE7_RB_BASE_HI__ADDR_MASK', + 'SDMA0_QUEUE7_RB_BASE_HI__ADDR__SHIFT', + 'SDMA0_QUEUE7_RB_BASE__ADDR_MASK', + 'SDMA0_QUEUE7_RB_BASE__ADDR__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RB_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RB_PRIV_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RB_SIZE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RB_VMID_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RB_VMID__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE7_RB_RPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE7_RB_RPTR__OFFSET_MASK', + 'SDMA0_QUEUE7_RB_RPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE7_RB_WPTR_HI__OFFSET_MASK', + 'SDMA0_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA0_QUEUE7_RB_WPTR__OFFSET_MASK', + 'SDMA0_QUEUE7_RB_WPTR__OFFSET__SHIFT', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET_MASK', + 'SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT', + 'SDMA0_QUEUE_RESET_REQ__RESERVED_MASK', + 'SDMA0_QUEUE_RESET_REQ__RESERVED__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE0_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE1_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE2_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE3_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE4_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE5_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE6_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT', + 'SDMA0_QUEUE_STATUS0__QUEUE7_STATUS_MASK', + 'SDMA0_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT', + 'SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK', + 'SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT', + 'SDMA0_RB_RPTR_FETCH__OFFSET_MASK', + 'SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK', + 'SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK', + 'SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK', + 'SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__COPY_MASK', + 'SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__FENCE_MASK', + 'SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK', + 'SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK', + 'SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK', + 'SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK', + 'SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK', + 'SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK', + 'SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK', + 'SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK', + 'SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK', + 'SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT', + 'SDMA0_RELAX_ORDERING_LUT__WRITE_MASK', + 'SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT', + 'SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK', + 'SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT', + 'SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK', + 'SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT', + 'SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK', + 'SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT', + 'SDMA0_SCRATCH_RAM_DATA__DATA_MASK', + 'SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT', + 'SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK', + 'SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT', + 'SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK', + 'SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT', + 'SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_DST_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK', + 'SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT', + 'SDMA0_STATUS1_REG__CE_INFO_FULL_MASK', + 'SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT', + 'SDMA0_STATUS1_REG__CE_IN_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_RD_STALL_MASK', + 'SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT', + 'SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_WR_IDLE_MASK', + 'SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__CE_WR_STALL_MASK', + 'SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT', + 'SDMA0_STATUS1_REG__EX_START_MASK', + 'SDMA0_STATUS1_REG__EX_START__SHIFT', + 'SDMA0_STATUS1_REG__SDMA_IDLE_MASK', + 'SDMA0_STATUS1_REG__SDMA_IDLE__SHIFT', + 'SDMA0_STATUS1_REG__SEC_INTR_STATUS_MASK', + 'SDMA0_STATUS1_REG__SEC_INTR_STATUS__SHIFT', + 'SDMA0_STATUS1_REG__WPTR_POLL_IDLE_MASK', + 'SDMA0_STATUS1_REG__WPTR_POLL_IDLE__SHIFT', + 'SDMA0_STATUS2_REG__CMD_OP_MASK', + 'SDMA0_STATUS2_REG__CMD_OP__SHIFT', 'SDMA0_STATUS2_REG__ID_MASK', + 'SDMA0_STATUS2_REG__ID__SHIFT', + 'SDMA0_STATUS2_REG__TH0F32_INSTR_PTR_MASK', + 'SDMA0_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT', + 'SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK', + 'SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT', + 'SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK', + 'SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT', + 'SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK', + 'SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT', + 'SDMA0_STATUS3_REG__GCR_IDLE_MASK', + 'SDMA0_STATUS3_REG__GCR_IDLE__SHIFT', + 'SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK', + 'SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT', + 'SDMA0_STATUS3_REG__INVREQ_IDLE_MASK', + 'SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT', + 'SDMA0_STATUS3_REG__PREV_VM_CMD_MASK', + 'SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT', + 'SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK', + 'SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT', + 'SDMA0_STATUS3_REG__TLBI_IDLE_MASK', + 'SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT', + 'SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS_MASK', + 'SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT', + 'SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK', + 'SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT', + 'SDMA0_STATUS4_REG__CH_RD_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__CH_WR_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__GCR_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__GCR_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__IDLE_MASK', 'SDMA0_STATUS4_REG__IDLE__SHIFT', + 'SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__MEM_POLLING_MASK', + 'SDMA0_STATUS4_REG__MEM_POLLING__SHIFT', + 'SDMA0_STATUS4_REG__REG_POLLING_MASK', + 'SDMA0_STATUS4_REG__REG_POLLING__SHIFT', + 'SDMA0_STATUS4_REG__RESERVED_13_12_MASK', + 'SDMA0_STATUS4_REG__RESERVED_13_12__SHIFT', + 'SDMA0_STATUS4_REG__RESERVED_15_14_MASK', + 'SDMA0_STATUS4_REG__RESERVED_15_14__SHIFT', + 'SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK', + 'SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT', + 'SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK', + 'SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT', + 'SDMA0_STATUS4_REG__TLBI_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__TLBI_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK', + 'SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK', + 'SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK', + 'SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK', + 'SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK', + 'SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK', + 'SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT', + 'SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK', + 'SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT', + 'SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID_MASK', + 'SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK', + 'SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT', + 'SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA0_STATUS6_REG__ID_MASK', 'SDMA0_STATUS6_REG__ID__SHIFT', + 'SDMA0_STATUS6_REG__TH1F32_INSTR_PTR_MASK', + 'SDMA0_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT', + 'SDMA0_STATUS6_REG__TH1_EXCEPTION_MASK', + 'SDMA0_STATUS6_REG__TH1_EXCEPTION__SHIFT', + 'SDMA0_STATUS_REG__BLOCK_IDLE_MASK', + 'SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT', + 'SDMA0_STATUS_REG__CGCG_FENCE_MASK', + 'SDMA0_STATUS_REG__CGCG_FENCE__SHIFT', + 'SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK', + 'SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT', + 'SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK', + 'SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT', + 'SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK', + 'SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT', + 'SDMA0_STATUS_REG__EX_IDLE_MASK', + 'SDMA0_STATUS_REG__EX_IDLE__SHIFT', + 'SDMA0_STATUS_REG__IB_CMD_FULL_MASK', + 'SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT', + 'SDMA0_STATUS_REG__IB_CMD_IDLE_MASK', + 'SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT', + 'SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK', + 'SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT', + 'SDMA0_STATUS_REG__IDLE_MASK', 'SDMA0_STATUS_REG__IDLE__SHIFT', + 'SDMA0_STATUS_REG__INSIDE_IB_MASK', + 'SDMA0_STATUS_REG__INSIDE_IB__SHIFT', + 'SDMA0_STATUS_REG__INT_IDLE_MASK', + 'SDMA0_STATUS_REG__INT_IDLE__SHIFT', + 'SDMA0_STATUS_REG__INT_REQ_STALL_MASK', + 'SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT', + 'SDMA0_STATUS_REG__MC_RD_IDLE_MASK', + 'SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT', + 'SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK', + 'SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT', + 'SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK', + 'SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT', + 'SDMA0_STATUS_REG__MC_WR_IDLE_MASK', + 'SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT', + 'SDMA0_STATUS_REG__PACKET_READY_MASK', + 'SDMA0_STATUS_REG__PACKET_READY__SHIFT', + 'SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK', + 'SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT', + 'SDMA0_STATUS_REG__RB_CMD_FULL_MASK', + 'SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT', + 'SDMA0_STATUS_REG__RB_CMD_IDLE_MASK', + 'SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT', + 'SDMA0_STATUS_REG__RB_EMPTY_MASK', + 'SDMA0_STATUS_REG__RB_EMPTY__SHIFT', + 'SDMA0_STATUS_REG__RB_FULL_MASK', + 'SDMA0_STATUS_REG__RB_FULL__SHIFT', + 'SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK', + 'SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT', + 'SDMA0_STATUS_REG__REG_IDLE_MASK', + 'SDMA0_STATUS_REG__REG_IDLE__SHIFT', + 'SDMA0_STATUS_REG__SEM_IDLE_MASK', + 'SDMA0_STATUS_REG__SEM_IDLE__SHIFT', + 'SDMA0_STATUS_REG__SEM_REQ_STALL_MASK', + 'SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT', + 'SDMA0_STATUS_REG__SEM_RESP_STATE_MASK', + 'SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT', + 'SDMA0_STATUS_REG__SRBM_IDLE_MASK', + 'SDMA0_STATUS_REG__SRBM_IDLE__SHIFT', + 'SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK', + 'SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT', + 'SDMA0_TIMESTAMP_CNTL__CAPTURE_MASK', + 'SDMA0_TIMESTAMP_CNTL__CAPTURE__SHIFT', + 'SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK', + 'SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT', + 'SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK', + 'SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT', + 'SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK', + 'SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT', + 'SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK', + 'SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT', + 'SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK', + 'SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT', + 'SDMA0_UCODE1_CHECKSUM__DATA_MASK', + 'SDMA0_UCODE1_CHECKSUM__DATA__SHIFT', + 'SDMA0_UCODE_ADDR__THID_MASK', 'SDMA0_UCODE_ADDR__THID__SHIFT', + 'SDMA0_UCODE_ADDR__VALUE_MASK', 'SDMA0_UCODE_ADDR__VALUE__SHIFT', + 'SDMA0_UCODE_CHECKSUM__DATA_MASK', + 'SDMA0_UCODE_CHECKSUM__DATA__SHIFT', + 'SDMA0_UCODE_DATA__VALUE_MASK', 'SDMA0_UCODE_DATA__VALUE__SHIFT', + 'SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK', + 'SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT', + 'SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK', + 'SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT', + 'SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK', + 'SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT', + 'SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK', + 'SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT', + 'SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK', + 'SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT', + 'SDMA0_UTCL1_CNTL__REDO_DELAY_MASK', + 'SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT', + 'SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK', + 'SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT', + 'SDMA0_UTCL1_CNTL__RESP_MODE_MASK', + 'SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT', + 'SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK', + 'SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT', + 'SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK', + 'SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT', + 'SDMA0_UTCL1_INV0__GPUVM_HIGH_MASK', + 'SDMA0_UTCL1_INV0__GPUVM_HIGH__SHIFT', + 'SDMA0_UTCL1_INV0__GPUVM_MODE_MASK', + 'SDMA0_UTCL1_INV0__GPUVM_MODE__SHIFT', + 'SDMA0_UTCL1_INV0__GPUVM_TAG_MASK', + 'SDMA0_UTCL1_INV0__GPUVM_TAG__SHIFT', + 'SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH_MASK', + 'SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT', + 'SDMA0_UTCL1_INV0__GPUVM_VMID_LOW_MASK', + 'SDMA0_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT', + 'SDMA0_UTCL1_INV0__GPUVM_VMID_MASK', + 'SDMA0_UTCL1_INV0__GPUVM_VMID__SHIFT', + 'SDMA0_UTCL1_INV0__INV_PROC_BUSY_MASK', + 'SDMA0_UTCL1_INV0__INV_PROC_BUSY__SHIFT', + 'SDMA0_UTCL1_INV0__INV_TYPE_MASK', + 'SDMA0_UTCL1_INV0__INV_TYPE__SHIFT', + 'SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK', + 'SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT', + 'SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE_MASK', + 'SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT', + 'SDMA0_UTCL1_INV2__CPF_FRAG_SIZE_MASK', + 'SDMA0_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT', + 'SDMA0_UTCL1_INV2__CPF_VMID_MASK', + 'SDMA0_UTCL1_INV2__CPF_VMID__SHIFT', + 'SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK', + 'SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT', + 'SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK', + 'SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT', + 'SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK', + 'SDMA0_UTCL1_PAGE__LLC_NOALLOC__SHIFT', + 'SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK', + 'SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT', + 'SDMA0_UTCL1_PAGE__REQ_TYPE_MASK', + 'SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT', + 'SDMA0_UTCL1_PAGE__USE_BC_MASK', + 'SDMA0_UTCL1_PAGE__USE_BC__SHIFT', + 'SDMA0_UTCL1_PAGE__USE_IO_MASK', + 'SDMA0_UTCL1_PAGE__USE_IO__SHIFT', + 'SDMA0_UTCL1_PAGE__USE_MTYPE_MASK', + 'SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT', + 'SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK', + 'SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT', + 'SDMA0_UTCL1_PAGE__VM_HOLE_MASK', + 'SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT', + 'SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK', + 'SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK', + 'SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__INV_BUSY_MASK', + 'SDMA0_UTCL1_RD_STATUS__INV_BUSY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY_MASK', + 'SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__META_Q_FULL_MASK', + 'SDMA0_UTCL1_RD_STATUS__META_Q_FULL__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK', + 'SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK', + 'SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK', + 'SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RESERVED0_MASK', + 'SDMA0_UTCL1_RD_STATUS__RESERVED0__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RESERVED1_MASK', + 'SDMA0_UTCL1_RD_STATUS__RESERVED1__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RESERVED2_MASK', + 'SDMA0_UTCL1_RD_STATUS__RESERVED2__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RESERVED3_MASK', + 'SDMA0_UTCL1_RD_STATUS__RESERVED3__SHIFT', + 'SDMA0_UTCL1_RD_STATUS__RESERVED4_MASK', + 'SDMA0_UTCL1_RD_STATUS__RESERVED4__SHIFT', + 'SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK', + 'SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK', + 'SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT', + 'SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT_MASK', + 'SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT', + 'SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK', + 'SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT', + 'SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK', + 'SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT', + 'SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK', + 'SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT', + 'SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK', + 'SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT', + 'SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK', + 'SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT', + 'SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK', + 'SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT', + 'SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK', + 'SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT', + 'SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK', + 'SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK', + 'SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__RESERVED0_MASK', + 'SDMA0_UTCL1_WR_STATUS__RESERVED0__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK', + 'SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK', + 'SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT', + 'SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK', + 'SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK', + 'SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT', + 'SDMA0_VERSION__MAJVER_MASK', 'SDMA0_VERSION__MAJVER__SHIFT', + 'SDMA0_VERSION__MINVER_MASK', 'SDMA0_VERSION__MINVER__SHIFT', + 'SDMA0_VERSION__REV_MASK', 'SDMA0_VERSION__REV__SHIFT', + 'SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK', + 'SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT', + 'SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK', + 'SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT', + 'SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK', + 'SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT', + 'SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK', + 'SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT', + 'SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK', + 'SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT', + 'SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK', + 'SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT', + 'SDMA1_ATOMIC_PREOP_HI__DATA_MASK', + 'SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT', + 'SDMA1_ATOMIC_PREOP_LO__DATA_MASK', + 'SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT', + 'SDMA1_BA_THRESHOLD__READ_THRES_MASK', + 'SDMA1_BA_THRESHOLD__READ_THRES__SHIFT', + 'SDMA1_BA_THRESHOLD__WRITE_THRES_MASK', + 'SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT', + 'SDMA1_BROADCAST_UCODE_ADDR__THID_MASK', + 'SDMA1_BROADCAST_UCODE_ADDR__THID__SHIFT', + 'SDMA1_BROADCAST_UCODE_ADDR__VALUE_MASK', + 'SDMA1_BROADCAST_UCODE_ADDR__VALUE__SHIFT', + 'SDMA1_BROADCAST_UCODE_DATA__VALUE_MASK', + 'SDMA1_BROADCAST_UCODE_DATA__VALUE__SHIFT', + 'SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK', + 'SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT', + 'SDMA1_CE_CTRL__RD_LUT_DEPTH_MASK', + 'SDMA1_CE_CTRL__RD_LUT_DEPTH__SHIFT', + 'SDMA1_CE_CTRL__RD_LUT_WATERMARK_MASK', + 'SDMA1_CE_CTRL__RD_LUT_WATERMARK__SHIFT', + 'SDMA1_CE_CTRL__RESERVED_MASK', 'SDMA1_CE_CTRL__RESERVED__SHIFT', + 'SDMA1_CE_CTRL__WR_AFIFO_WATERMARK_MASK', + 'SDMA1_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT', + 'SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK', + 'SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT', + 'SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK', + 'SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT', + 'SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK', + 'SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT', + 'SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK', + 'SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT', + 'SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK', + 'SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT', + 'SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK', + 'SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT', + 'SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK', + 'SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT', + 'SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK', + 'SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT', + 'SDMA1_CHICKEN_BITS_2__RESERVED_14_12_MASK', + 'SDMA1_CHICKEN_BITS_2__RESERVED_14_12__SHIFT', + 'SDMA1_CHICKEN_BITS_2__RESERVED_15_MASK', + 'SDMA1_CHICKEN_BITS_2__RESERVED_15__SHIFT', + 'SDMA1_CHICKEN_BITS_2__RESERVED_22_20_MASK', + 'SDMA1_CHICKEN_BITS_2__RESERVED_22_20__SHIFT', + 'SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK', + 'SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT', + 'SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK', + 'SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT', + 'SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK', + 'SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT', + 'SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK', + 'SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT', + 'SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK', + 'SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT', + 'SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT', + 'SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT', + 'SDMA1_CHICKEN_BITS__RD_BURST_MASK', + 'SDMA1_CHICKEN_BITS__RD_BURST__SHIFT', + 'SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT', + 'SDMA1_CHICKEN_BITS__RESERVED_MASK', + 'SDMA1_CHICKEN_BITS__RESERVED__SHIFT', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK', + 'SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT', + 'SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK', + 'SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT', + 'SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT', + 'SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT', + 'SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT', + 'SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT', + 'SDMA1_CHICKEN_BITS__WR_BURST_MASK', + 'SDMA1_CHICKEN_BITS__WR_BURST__SHIFT', + 'SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK', + 'SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT', + 'SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK', + 'SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT', + 'SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK', + 'SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT', + 'SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK', + 'SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT', + 'SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK', + 'SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT', + 'SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK', + 'SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT', + 'SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK', + 'SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT', + 'SDMA1_CNTL1__WPTR_POLL_FREQUENCY_MASK', + 'SDMA1_CNTL1__WPTR_POLL_FREQUENCY__SHIFT', + 'SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK', + 'SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT', + 'SDMA1_CNTL__CP_MES_INT_ENABLE_MASK', + 'SDMA1_CNTL__CP_MES_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK', + 'SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__DATA_SWAP_ENABLE_MASK', + 'SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT', + 'SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK', + 'SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT', + 'SDMA1_CNTL__FROZEN_INT_ENABLE_MASK', + 'SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK', + 'SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE_MASK', + 'SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT', + 'SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK', + 'SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT', + 'SDMA1_CNTL__PAGE_FAULT_INT_ENABLE_MASK', + 'SDMA1_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__PAGE_NULL_INT_ENABLE_MASK', + 'SDMA1_CNTL__PAGE_NULL_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK', + 'SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__PIO_DONE_ACK_ENABLE_MASK', + 'SDMA1_CNTL__PIO_DONE_ACK_ENABLE__SHIFT', + 'SDMA1_CNTL__RB_PREEMPT_INT_ENABLE_MASK', + 'SDMA1_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK', + 'SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT', + 'SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_CNTL__TRAP_ENABLE_MASK', 'SDMA1_CNTL__TRAP_ENABLE__SHIFT', + 'SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK', + 'SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT', + 'SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK', + 'SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT', + 'SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK', + 'SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT', + 'SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK', + 'SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT', + 'SDMA1_DEC_START__START_MASK', 'SDMA1_DEC_START__START__SHIFT', + 'SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK', + 'SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT', + 'SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK', + 'SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT', + 'SDMA1_EDC_CONFIG__DIS_EDC_MASK', + 'SDMA1_EDC_CONFIG__DIS_EDC__SHIFT', + 'SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK', + 'SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT', + 'SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK', + 'SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK', + 'SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT', + 'SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK', + 'SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT', + 'SDMA1_ERROR_LOG__OVERRIDE_MASK', + 'SDMA1_ERROR_LOG__OVERRIDE__SHIFT', + 'SDMA1_ERROR_LOG__STATUS_MASK', 'SDMA1_ERROR_LOG__STATUS__SHIFT', + 'SDMA1_F32_CNTL__HALT_MASK', 'SDMA1_F32_CNTL__HALT__SHIFT', + 'SDMA1_F32_CNTL__TH0_CHECKSUM_CLR_MASK', + 'SDMA1_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT', + 'SDMA1_F32_CNTL__TH0_ENABLE_MASK', + 'SDMA1_F32_CNTL__TH0_ENABLE__SHIFT', + 'SDMA1_F32_CNTL__TH0_PRIORITY_MASK', + 'SDMA1_F32_CNTL__TH0_PRIORITY__SHIFT', + 'SDMA1_F32_CNTL__TH0_RESET_MASK', + 'SDMA1_F32_CNTL__TH0_RESET__SHIFT', + 'SDMA1_F32_CNTL__TH1_CHECKSUM_CLR_MASK', + 'SDMA1_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT', + 'SDMA1_F32_CNTL__TH1_ENABLE_MASK', + 'SDMA1_F32_CNTL__TH1_ENABLE__SHIFT', + 'SDMA1_F32_CNTL__TH1_PRIORITY_MASK', + 'SDMA1_F32_CNTL__TH1_PRIORITY__SHIFT', + 'SDMA1_F32_CNTL__TH1_RESET_MASK', + 'SDMA1_F32_CNTL__TH1_RESET__SHIFT', + 'SDMA1_F32_COUNTER__VALUE_MASK', + 'SDMA1_F32_COUNTER__VALUE__SHIFT', + 'SDMA1_F32_MISC_CNTL__F32_WAKEUP_MASK', + 'SDMA1_F32_MISC_CNTL__F32_WAKEUP__SHIFT', + 'SDMA1_FED_STATUS__COPY_DATA_ECC_MASK', + 'SDMA1_FED_STATUS__COPY_DATA_ECC__SHIFT', + 'SDMA1_FED_STATUS__COPY_METADATA_ECC_MASK', + 'SDMA1_FED_STATUS__COPY_METADATA_ECC__SHIFT', + 'SDMA1_FED_STATUS__F32_DATA_ECC_MASK', + 'SDMA1_FED_STATUS__F32_DATA_ECC__SHIFT', + 'SDMA1_FED_STATUS__IB_FETCH_ECC_MASK', + 'SDMA1_FED_STATUS__IB_FETCH_ECC__SHIFT', + 'SDMA1_FED_STATUS__RB_FETCH_ECC_MASK', + 'SDMA1_FED_STATUS__RB_FETCH_ECC__SHIFT', + 'SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC_MASK', + 'SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT', + 'SDMA1_FED_STATUS__WPTR_ATOMIC_ECC_MASK', + 'SDMA1_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT', + 'SDMA1_FREEZE__F32_FREEZE_MASK', + 'SDMA1_FREEZE__F32_FREEZE__SHIFT', 'SDMA1_FREEZE__FREEZE_MASK', + 'SDMA1_FREEZE__FREEZE__SHIFT', 'SDMA1_FREEZE__FROZEN_MASK', + 'SDMA1_FREEZE__FROZEN__SHIFT', 'SDMA1_FREEZE__PREEMPT_MASK', + 'SDMA1_FREEZE__PREEMPT__SHIFT', + 'SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK', + 'SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK', + 'SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT', + 'SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK', + 'SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT', + 'SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK', + 'SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT', + 'SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK', + 'SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT', + 'SDMA1_GB_ADDR_CONFIG__NUM_PKRS_MASK', + 'SDMA1_GB_ADDR_CONFIG__NUM_PKRS__SHIFT', + 'SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK', + 'SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT', + 'SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK', + 'SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT', + 'SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK', + 'SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT', + 'SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK', + 'SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT', + 'SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK', + 'SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT', + 'SDMA1_GLOBAL_TIMESTAMP_HI__DATA_MASK', + 'SDMA1_GLOBAL_TIMESTAMP_HI__DATA__SHIFT', + 'SDMA1_GLOBAL_TIMESTAMP_LO__DATA_MASK', + 'SDMA1_GLOBAL_TIMESTAMP_LO__DATA__SHIFT', + 'SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK', + 'SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT', + 'SDMA1_HOLE_ADDR_HI__VALUE_MASK', + 'SDMA1_HOLE_ADDR_HI__VALUE__SHIFT', + 'SDMA1_HOLE_ADDR_LO__VALUE_MASK', + 'SDMA1_HOLE_ADDR_LO__VALUE__SHIFT', + 'SDMA1_IB_OFFSET_FETCH__OFFSET_MASK', + 'SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT', + 'SDMA1_ID__DEVICE_ID_MASK', 'SDMA1_ID__DEVICE_ID__SHIFT', + 'SDMA1_INT_STATUS__DATA_MASK', 'SDMA1_INT_STATUS__DATA__SHIFT', + 'SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK', + 'SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK', + 'SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK', + 'SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK', + 'SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT', + 'SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK', + 'SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT', + 'SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK', + 'SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT', + 'SDMA1_POWER_CNTL__LS_ENABLE_MASK', + 'SDMA1_POWER_CNTL__LS_ENABLE__SHIFT', + 'SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT', + 'SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT', + 'SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT', + 'SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT', + 'SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT', + 'SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT', + 'SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT', + 'SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK', + 'SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT', + 'SDMA1_PROGRAM__STREAM_MASK', 'SDMA1_PROGRAM__STREAM__SHIFT', + 'SDMA1_PUB_DUMMY_REG0__VALUE_MASK', + 'SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT', + 'SDMA1_PUB_DUMMY_REG1__VALUE_MASK', + 'SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT', + 'SDMA1_PUB_DUMMY_REG2__VALUE_MASK', + 'SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT', + 'SDMA1_PUB_DUMMY_REG3__VALUE_MASK', + 'SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE0_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE0_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE0_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE0_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE0_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE0_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE0_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE0_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE0_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE0_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE0_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE0_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE0_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE0_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE0_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE0_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE0_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE0_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE0_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE0_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE0_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE0_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE0_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE0_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE0_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE0_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE0_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE0_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE0_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE0_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE0_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE0_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE0_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE0_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE0_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE1_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE1_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE1_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE1_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE1_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE1_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE1_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE1_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE1_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE1_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE1_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE1_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE1_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE1_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE1_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE1_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE1_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE1_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE1_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE1_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE1_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE1_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE1_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE1_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE1_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE1_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE1_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE1_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE1_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE1_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE1_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE1_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE1_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE1_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE1_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE2_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE2_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE2_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE2_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE2_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE2_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE2_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE2_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE2_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE2_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE2_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE2_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE2_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE2_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE2_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE2_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE2_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE2_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE2_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE2_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE2_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE2_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE2_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE2_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE2_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE2_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE2_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE2_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE2_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE2_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE2_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE2_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE2_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE2_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE2_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE3_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE3_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE3_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE3_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE3_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE3_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE3_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE3_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE3_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE3_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE3_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE3_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE3_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE3_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE3_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE3_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE3_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE3_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE3_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE3_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE3_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE3_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE3_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE3_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE3_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE3_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE3_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE3_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE3_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE3_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE3_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE3_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE3_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE3_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE3_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE4_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE4_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE4_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE4_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE4_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE4_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE4_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE4_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE4_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE4_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE4_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE4_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE4_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE4_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE4_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE4_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE4_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE4_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE4_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE4_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE4_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE4_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE4_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE4_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE4_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE4_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE4_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE4_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE4_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE4_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE4_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE4_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE4_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE4_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE4_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE5_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE5_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE5_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE5_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE5_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE5_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE5_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE5_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE5_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE5_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE5_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE5_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE5_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE5_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE5_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE5_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE5_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE5_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE5_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE5_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE5_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE5_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE5_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE5_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE5_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE5_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE5_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE5_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE5_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE5_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE5_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE5_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE5_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE5_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE5_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE6_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE6_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE6_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE6_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE6_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE6_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE6_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE6_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE6_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE6_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE6_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE6_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE6_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE6_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE6_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE6_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE6_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE6_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE6_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE6_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE6_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE6_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE6_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE6_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE6_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE6_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE6_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE6_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE6_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE6_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE6_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE6_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE6_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE6_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE6_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__IDLE_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT', + 'SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK', + 'SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT', + 'SDMA1_QUEUE7_CSA_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE7_CSA_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK', + 'SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT', + 'SDMA1_QUEUE7_DOORBELL_LOG__DATA_MASK', + 'SDMA1_QUEUE7_DOORBELL_LOG__DATA__SHIFT', + 'SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE7_DOORBELL__CAPTURED_MASK', + 'SDMA1_QUEUE7_DOORBELL__CAPTURED__SHIFT', + 'SDMA1_QUEUE7_DOORBELL__ENABLE_MASK', + 'SDMA1_QUEUE7_DOORBELL__ENABLE__SHIFT', + 'SDMA1_QUEUE7_DUMMY_REG__DUMMY_MASK', + 'SDMA1_QUEUE7_DUMMY_REG__DUMMY__SHIFT', + 'SDMA1_QUEUE7_IB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE7_IB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE7_IB_BASE_LO__ADDR_MASK', + 'SDMA1_QUEUE7_IB_BASE_LO__ADDR__SHIFT', + 'SDMA1_QUEUE7_IB_CNTL__CMD_VMID_MASK', + 'SDMA1_QUEUE7_IB_CNTL__CMD_VMID__SHIFT', + 'SDMA1_QUEUE7_IB_CNTL__IB_ENABLE_MASK', + 'SDMA1_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT', + 'SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK', + 'SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT', + 'SDMA1_QUEUE7_IB_OFFSET__OFFSET_MASK', + 'SDMA1_QUEUE7_IB_OFFSET__OFFSET__SHIFT', + 'SDMA1_QUEUE7_IB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE7_IB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE7_IB_SIZE__SIZE_MASK', + 'SDMA1_QUEUE7_IB_SIZE__SIZE__SHIFT', + 'SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE_MASK', + 'SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK', + 'SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK', + 'SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK', + 'SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK', + 'SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA0__DATA0_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA10__DATA10_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA1__DATA1_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA2__DATA2_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA3__DATA3_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA4__DATA4_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA5__DATA5_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA6__DATA6_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA7__DATA7_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA8__DATA8_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT', + 'SDMA1_QUEUE7_MIDCMD_DATA9__DATA9_MASK', + 'SDMA1_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT', + 'SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK', + 'SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT', + 'SDMA1_QUEUE7_PREEMPT__IB_PREEMPT_MASK', + 'SDMA1_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT', + 'SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK', + 'SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT', + 'SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK', + 'SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT', + 'SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK', + 'SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT', + 'SDMA1_QUEUE7_RB_BASE_HI__ADDR_MASK', + 'SDMA1_QUEUE7_RB_BASE_HI__ADDR__SHIFT', + 'SDMA1_QUEUE7_RB_BASE__ADDR_MASK', + 'SDMA1_QUEUE7_RB_BASE__ADDR__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RB_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RB_PRIV_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RB_PRIV__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RB_SIZE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RB_SIZE__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RB_VMID_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RB_VMID__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK', + 'SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK', + 'SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT', + 'SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK', + 'SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT', + 'SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE7_RB_RPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE7_RB_RPTR__OFFSET_MASK', + 'SDMA1_QUEUE7_RB_RPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE7_RB_WPTR_HI__OFFSET_MASK', + 'SDMA1_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT', + 'SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK', + 'SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT', + 'SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK', + 'SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT', + 'SDMA1_QUEUE7_RB_WPTR__OFFSET_MASK', + 'SDMA1_QUEUE7_RB_WPTR__OFFSET__SHIFT', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK', + 'SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT', + 'SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK', + 'SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET_MASK', + 'SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT', + 'SDMA1_QUEUE_RESET_REQ__RESERVED_MASK', + 'SDMA1_QUEUE_RESET_REQ__RESERVED__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE0_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE1_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE2_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE3_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE4_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE5_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE6_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT', + 'SDMA1_QUEUE_STATUS0__QUEUE7_STATUS_MASK', + 'SDMA1_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT', + 'SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK', + 'SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT', + 'SDMA1_RB_RPTR_FETCH__OFFSET_MASK', + 'SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK', + 'SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK', + 'SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK', + 'SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__COPY_MASK', + 'SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__FENCE_MASK', + 'SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK', + 'SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK', + 'SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK', + 'SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK', + 'SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK', + 'SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK', + 'SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK', + 'SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK', + 'SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK', + 'SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT', + 'SDMA1_RELAX_ORDERING_LUT__WRITE_MASK', + 'SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT', + 'SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK', + 'SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT', + 'SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK', + 'SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT', + 'SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK', + 'SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT', + 'SDMA1_SCRATCH_RAM_DATA__DATA_MASK', + 'SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT', + 'SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK', + 'SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT', + 'SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK', + 'SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT', + 'SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_DST_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK', + 'SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT', + 'SDMA1_STATUS1_REG__CE_INFO_FULL_MASK', + 'SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT', + 'SDMA1_STATUS1_REG__CE_IN_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_RD_STALL_MASK', + 'SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT', + 'SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_WR_IDLE_MASK', + 'SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__CE_WR_STALL_MASK', + 'SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT', + 'SDMA1_STATUS1_REG__EX_START_MASK', + 'SDMA1_STATUS1_REG__EX_START__SHIFT', + 'SDMA1_STATUS1_REG__SDMA_IDLE_MASK', + 'SDMA1_STATUS1_REG__SDMA_IDLE__SHIFT', + 'SDMA1_STATUS1_REG__SEC_INTR_STATUS_MASK', + 'SDMA1_STATUS1_REG__SEC_INTR_STATUS__SHIFT', + 'SDMA1_STATUS1_REG__WPTR_POLL_IDLE_MASK', + 'SDMA1_STATUS1_REG__WPTR_POLL_IDLE__SHIFT', + 'SDMA1_STATUS2_REG__CMD_OP_MASK', + 'SDMA1_STATUS2_REG__CMD_OP__SHIFT', 'SDMA1_STATUS2_REG__ID_MASK', + 'SDMA1_STATUS2_REG__ID__SHIFT', + 'SDMA1_STATUS2_REG__TH0F32_INSTR_PTR_MASK', + 'SDMA1_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT', + 'SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK', + 'SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT', + 'SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK', + 'SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT', + 'SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK', + 'SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT', + 'SDMA1_STATUS3_REG__GCR_IDLE_MASK', + 'SDMA1_STATUS3_REG__GCR_IDLE__SHIFT', + 'SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK', + 'SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT', + 'SDMA1_STATUS3_REG__INVREQ_IDLE_MASK', + 'SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT', + 'SDMA1_STATUS3_REG__PREV_VM_CMD_MASK', + 'SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT', + 'SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK', + 'SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT', + 'SDMA1_STATUS3_REG__TLBI_IDLE_MASK', + 'SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT', + 'SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS_MASK', + 'SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT', + 'SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK', + 'SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT', + 'SDMA1_STATUS4_REG__CH_RD_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__CH_WR_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__GCR_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__GCR_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__IDLE_MASK', 'SDMA1_STATUS4_REG__IDLE__SHIFT', + 'SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__MEM_POLLING_MASK', + 'SDMA1_STATUS4_REG__MEM_POLLING__SHIFT', + 'SDMA1_STATUS4_REG__REG_POLLING_MASK', + 'SDMA1_STATUS4_REG__REG_POLLING__SHIFT', + 'SDMA1_STATUS4_REG__RESERVED_13_12_MASK', + 'SDMA1_STATUS4_REG__RESERVED_13_12__SHIFT', + 'SDMA1_STATUS4_REG__RESERVED_15_14_MASK', + 'SDMA1_STATUS4_REG__RESERVED_15_14__SHIFT', + 'SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK', + 'SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT', + 'SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK', + 'SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT', + 'SDMA1_STATUS4_REG__TLBI_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__TLBI_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK', + 'SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK', + 'SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK', + 'SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK', + 'SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK', + 'SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK', + 'SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT', + 'SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK', + 'SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT', + 'SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID_MASK', + 'SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK', + 'SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT', + 'SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK', + 'SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT', + 'SDMA1_STATUS6_REG__ID_MASK', 'SDMA1_STATUS6_REG__ID__SHIFT', + 'SDMA1_STATUS6_REG__TH1F32_INSTR_PTR_MASK', + 'SDMA1_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT', + 'SDMA1_STATUS6_REG__TH1_EXCEPTION_MASK', + 'SDMA1_STATUS6_REG__TH1_EXCEPTION__SHIFT', + 'SDMA1_STATUS_REG__BLOCK_IDLE_MASK', + 'SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT', + 'SDMA1_STATUS_REG__CGCG_FENCE_MASK', + 'SDMA1_STATUS_REG__CGCG_FENCE__SHIFT', + 'SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK', + 'SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT', + 'SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK', + 'SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT', + 'SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK', + 'SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT', + 'SDMA1_STATUS_REG__EX_IDLE_MASK', + 'SDMA1_STATUS_REG__EX_IDLE__SHIFT', + 'SDMA1_STATUS_REG__IB_CMD_FULL_MASK', + 'SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT', + 'SDMA1_STATUS_REG__IB_CMD_IDLE_MASK', + 'SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT', + 'SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK', + 'SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT', + 'SDMA1_STATUS_REG__IDLE_MASK', 'SDMA1_STATUS_REG__IDLE__SHIFT', + 'SDMA1_STATUS_REG__INSIDE_IB_MASK', + 'SDMA1_STATUS_REG__INSIDE_IB__SHIFT', + 'SDMA1_STATUS_REG__INT_IDLE_MASK', + 'SDMA1_STATUS_REG__INT_IDLE__SHIFT', + 'SDMA1_STATUS_REG__INT_REQ_STALL_MASK', + 'SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT', + 'SDMA1_STATUS_REG__MC_RD_IDLE_MASK', + 'SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT', + 'SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK', + 'SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT', + 'SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK', + 'SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT', + 'SDMA1_STATUS_REG__MC_WR_IDLE_MASK', + 'SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT', + 'SDMA1_STATUS_REG__PACKET_READY_MASK', + 'SDMA1_STATUS_REG__PACKET_READY__SHIFT', + 'SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK', + 'SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT', + 'SDMA1_STATUS_REG__RB_CMD_FULL_MASK', + 'SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT', + 'SDMA1_STATUS_REG__RB_CMD_IDLE_MASK', + 'SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT', + 'SDMA1_STATUS_REG__RB_EMPTY_MASK', + 'SDMA1_STATUS_REG__RB_EMPTY__SHIFT', + 'SDMA1_STATUS_REG__RB_FULL_MASK', + 'SDMA1_STATUS_REG__RB_FULL__SHIFT', + 'SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK', + 'SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT', + 'SDMA1_STATUS_REG__REG_IDLE_MASK', + 'SDMA1_STATUS_REG__REG_IDLE__SHIFT', + 'SDMA1_STATUS_REG__SEM_IDLE_MASK', + 'SDMA1_STATUS_REG__SEM_IDLE__SHIFT', + 'SDMA1_STATUS_REG__SEM_REQ_STALL_MASK', + 'SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT', + 'SDMA1_STATUS_REG__SEM_RESP_STATE_MASK', + 'SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT', + 'SDMA1_STATUS_REG__SRBM_IDLE_MASK', + 'SDMA1_STATUS_REG__SRBM_IDLE__SHIFT', + 'SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK', + 'SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT', + 'SDMA1_TIMESTAMP_CNTL__CAPTURE_MASK', + 'SDMA1_TIMESTAMP_CNTL__CAPTURE__SHIFT', + 'SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK', + 'SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT', + 'SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK', + 'SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT', + 'SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK', + 'SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT', + 'SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK', + 'SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT', + 'SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK', + 'SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT', + 'SDMA1_UCODE1_CHECKSUM__DATA_MASK', + 'SDMA1_UCODE1_CHECKSUM__DATA__SHIFT', + 'SDMA1_UCODE_ADDR__THID_MASK', 'SDMA1_UCODE_ADDR__THID__SHIFT', + 'SDMA1_UCODE_ADDR__VALUE_MASK', 'SDMA1_UCODE_ADDR__VALUE__SHIFT', + 'SDMA1_UCODE_CHECKSUM__DATA_MASK', + 'SDMA1_UCODE_CHECKSUM__DATA__SHIFT', + 'SDMA1_UCODE_DATA__VALUE_MASK', 'SDMA1_UCODE_DATA__VALUE__SHIFT', + 'SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK', + 'SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT', + 'SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK', + 'SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT', + 'SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK', + 'SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT', + 'SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK', + 'SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT', + 'SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK', + 'SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT', + 'SDMA1_UTCL1_CNTL__REDO_DELAY_MASK', + 'SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT', + 'SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK', + 'SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT', + 'SDMA1_UTCL1_CNTL__RESP_MODE_MASK', + 'SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT', + 'SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK', + 'SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT', + 'SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK', + 'SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT', + 'SDMA1_UTCL1_INV0__GPUVM_HIGH_MASK', + 'SDMA1_UTCL1_INV0__GPUVM_HIGH__SHIFT', + 'SDMA1_UTCL1_INV0__GPUVM_MODE_MASK', + 'SDMA1_UTCL1_INV0__GPUVM_MODE__SHIFT', + 'SDMA1_UTCL1_INV0__GPUVM_TAG_MASK', + 'SDMA1_UTCL1_INV0__GPUVM_TAG__SHIFT', + 'SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH_MASK', + 'SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT', + 'SDMA1_UTCL1_INV0__GPUVM_VMID_LOW_MASK', + 'SDMA1_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT', + 'SDMA1_UTCL1_INV0__GPUVM_VMID_MASK', + 'SDMA1_UTCL1_INV0__GPUVM_VMID__SHIFT', + 'SDMA1_UTCL1_INV0__INV_PROC_BUSY_MASK', + 'SDMA1_UTCL1_INV0__INV_PROC_BUSY__SHIFT', + 'SDMA1_UTCL1_INV0__INV_TYPE_MASK', + 'SDMA1_UTCL1_INV0__INV_TYPE__SHIFT', + 'SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK', + 'SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT', + 'SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE_MASK', + 'SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT', + 'SDMA1_UTCL1_INV2__CPF_FRAG_SIZE_MASK', + 'SDMA1_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT', + 'SDMA1_UTCL1_INV2__CPF_VMID_MASK', + 'SDMA1_UTCL1_INV2__CPF_VMID__SHIFT', + 'SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK', + 'SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT', + 'SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK', + 'SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT', + 'SDMA1_UTCL1_PAGE__LLC_NOALLOC_MASK', + 'SDMA1_UTCL1_PAGE__LLC_NOALLOC__SHIFT', + 'SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK', + 'SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT', + 'SDMA1_UTCL1_PAGE__REQ_TYPE_MASK', + 'SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT', + 'SDMA1_UTCL1_PAGE__USE_BC_MASK', + 'SDMA1_UTCL1_PAGE__USE_BC__SHIFT', + 'SDMA1_UTCL1_PAGE__USE_IO_MASK', + 'SDMA1_UTCL1_PAGE__USE_IO__SHIFT', + 'SDMA1_UTCL1_PAGE__USE_MTYPE_MASK', + 'SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT', + 'SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK', + 'SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT', + 'SDMA1_UTCL1_PAGE__VM_HOLE_MASK', + 'SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT', + 'SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK', + 'SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK', + 'SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__INV_BUSY_MASK', + 'SDMA1_UTCL1_RD_STATUS__INV_BUSY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY_MASK', + 'SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__META_Q_FULL_MASK', + 'SDMA1_UTCL1_RD_STATUS__META_Q_FULL__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK', + 'SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK', + 'SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK', + 'SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RESERVED0_MASK', + 'SDMA1_UTCL1_RD_STATUS__RESERVED0__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RESERVED1_MASK', + 'SDMA1_UTCL1_RD_STATUS__RESERVED1__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RESERVED2_MASK', + 'SDMA1_UTCL1_RD_STATUS__RESERVED2__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RESERVED3_MASK', + 'SDMA1_UTCL1_RD_STATUS__RESERVED3__SHIFT', + 'SDMA1_UTCL1_RD_STATUS__RESERVED4_MASK', + 'SDMA1_UTCL1_RD_STATUS__RESERVED4__SHIFT', + 'SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK', + 'SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK', + 'SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT', + 'SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT_MASK', + 'SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT', + 'SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK', + 'SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT', + 'SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK', + 'SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT', + 'SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK', + 'SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT', + 'SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK', + 'SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT', + 'SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK', + 'SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT', + 'SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK', + 'SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT', + 'SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK', + 'SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT', + 'SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK', + 'SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK', + 'SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__RESERVED0_MASK', + 'SDMA1_UTCL1_WR_STATUS__RESERVED0__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK', + 'SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK', + 'SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT', + 'SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK', + 'SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK', + 'SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT', + 'SDMA1_VERSION__MAJVER_MASK', 'SDMA1_VERSION__MAJVER__SHIFT', + 'SDMA1_VERSION__MINVER_MASK', 'SDMA1_VERSION__MINVER__SHIFT', + 'SDMA1_VERSION__REV_MASK', 'SDMA1_VERSION__REV__SHIFT', + 'SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK', + 'SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT', + 'SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK', + 'SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT', + 'SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE_MASK', + 'SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE__SHIFT', + 'SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0_MASK', + 'SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0__SHIFT', + 'SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32_MASK', + 'SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32__SHIFT', + 'SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE_MASK', + 'SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE__SHIFT', + 'SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0_MASK', + 'SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0__SHIFT', + 'SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32_MASK', + 'SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32__SHIFT', + 'SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE_MASK', + 'SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE__SHIFT', + 'SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0_MASK', + 'SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0__SHIFT', + 'SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32_MASK', + 'SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32__SHIFT', + 'SE3_CAC_AGGR_GFXCLK_CYCLE__SE3_AGGR_GFXCLK_CYCLE_MASK', + 'SE3_CAC_AGGR_GFXCLK_CYCLE__SE3_AGGR_GFXCLK_CYCLE__SHIFT', + 'SE3_CAC_AGGR_LOWER__SE3_AGGR_31_0_MASK', + 'SE3_CAC_AGGR_LOWER__SE3_AGGR_31_0__SHIFT', + 'SE3_CAC_AGGR_UPPER__SE3_AGGR_63_32_MASK', + 'SE3_CAC_AGGR_UPPER__SE3_AGGR_63_32__SHIFT', + 'SE4_CAC_AGGR_GFXCLK_CYCLE__SE4_AGGR_GFXCLK_CYCLE_MASK', + 'SE4_CAC_AGGR_GFXCLK_CYCLE__SE4_AGGR_GFXCLK_CYCLE__SHIFT', + 'SE4_CAC_AGGR_LOWER__SE4_AGGR_31_0_MASK', + 'SE4_CAC_AGGR_LOWER__SE4_AGGR_31_0__SHIFT', + 'SE4_CAC_AGGR_UPPER__SE4_AGGR_63_32_MASK', + 'SE4_CAC_AGGR_UPPER__SE4_AGGR_63_32__SHIFT', + 'SE5_CAC_AGGR_GFXCLK_CYCLE__SE5_AGGR_GFXCLK_CYCLE_MASK', + 'SE5_CAC_AGGR_GFXCLK_CYCLE__SE5_AGGR_GFXCLK_CYCLE__SHIFT', + 'SE5_CAC_AGGR_LOWER__SE5_AGGR_31_0_MASK', + 'SE5_CAC_AGGR_LOWER__SE5_AGGR_31_0__SHIFT', + 'SE5_CAC_AGGR_UPPER__SE5_AGGR_63_32_MASK', + 'SE5_CAC_AGGR_UPPER__SE5_AGGR_63_32__SHIFT', + 'SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_DATA_CREDITS_MASK', + 'SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_DATA_CREDITS__SHIFT', + 'SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_OUT_CLK_OVERRIDE_MASK', + 'SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_OUT_CLK_OVERRIDE__SHIFT', + 'SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_REQ_CREDITS_MASK', + 'SEDC_GL1_GL2_OVERRIDES__SEDC_GL1C_GL2R_REQ_CREDITS__SHIFT', + 'SE_CAC_CNTL__CAC_THRESHOLD_MASK', + 'SE_CAC_CNTL__CAC_THRESHOLD__SHIFT', + 'SE_CAC_CTRL_1__CAC_WINDOW_MASK', + 'SE_CAC_CTRL_1__CAC_WINDOW__SHIFT', + 'SE_CAC_CTRL_1__TDP_WINDOW_MASK', + 'SE_CAC_CTRL_1__TDP_WINDOW__SHIFT', + 'SE_CAC_CTRL_2__CAC_ENABLE_MASK', + 'SE_CAC_CTRL_2__CAC_ENABLE__SHIFT', + 'SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN_MASK', + 'SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN__SHIFT', + 'SE_CAC_CTRL_2__SE_LCAC_ENABLE_MASK', + 'SE_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT', + 'SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE_MASK', + 'SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE__SHIFT', + 'SE_CAC_ID__CAC_BLOCK_ID_MASK', 'SE_CAC_ID__CAC_BLOCK_ID__SHIFT', + 'SE_CAC_ID__CAC_SIGNAL_ID_MASK', + 'SE_CAC_ID__CAC_SIGNAL_ID__SHIFT', + 'SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK', + 'SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT', + 'SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK', + 'SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT', + 'SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK', + 'SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT', + 'SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK', + 'SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT', + 'SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK', + 'SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT', + 'SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK', + 'SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT', + 'SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20_MASK', + 'SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20__SHIFT', + 'SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21_MASK', + 'SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21__SHIFT', + 'SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22_MASK', + 'SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22__SHIFT', + 'SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23_MASK', + 'SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23__SHIFT', + 'SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK', + 'SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT', + 'SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK', + 'SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT', + 'SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4_MASK', + 'SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4__SHIFT', + 'SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5_MASK', + 'SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5__SHIFT', + 'SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6_MASK', + 'SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6__SHIFT', + 'SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7_MASK', + 'SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7__SHIFT', + 'SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8_MASK', + 'SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8__SHIFT', + 'SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9_MASK', + 'SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9__SHIFT', + 'SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10_MASK', + 'SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10__SHIFT', + 'SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11_MASK', + 'SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11__SHIFT', + 'SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12_MASK', + 'SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12__SHIFT', + 'SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13_MASK', + 'SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13__SHIFT', + 'SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14_MASK', + 'SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14__SHIFT', + 'SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15_MASK', + 'SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15__SHIFT', + 'SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16_MASK', + 'SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16__SHIFT', + 'SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17_MASK', + 'SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17__SHIFT', + 'SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18_MASK', + 'SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18__SHIFT', + 'SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19_MASK', + 'SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19__SHIFT', + 'SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK', + 'SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT', + 'SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK', + 'SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT', + 'SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK', + 'SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT', + 'SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK', + 'SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT', + 'SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK', + 'SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT', + 'SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4_MASK', + 'SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4__SHIFT', + 'SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5_MASK', + 'SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5__SHIFT', + 'SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6_MASK', + 'SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6__SHIFT', + 'SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7_MASK', + 'SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7__SHIFT', + 'SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8_MASK', + 'SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8__SHIFT', + 'SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9_MASK', + 'SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9__SHIFT', + 'SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK', + 'SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT', + 'SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK', + 'SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT', + 'SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK', + 'SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT', + 'SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK', + 'SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT', + 'SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4_MASK', + 'SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4__SHIFT', + 'SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK', + 'SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT', + 'SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK', + 'SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT', + 'SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK', + 'SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT', + 'SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK', + 'SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT', + 'SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4_MASK', + 'SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4__SHIFT', + 'SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5_MASK', + 'SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5__SHIFT', + 'SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6_MASK', + 'SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6__SHIFT', + 'SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7_MASK', + 'SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7__SHIFT', + 'SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK', + 'SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT', + 'SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK', + 'SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT', + 'SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2_MASK', + 'SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2__SHIFT', + 'SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3_MASK', + 'SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3__SHIFT', + 'SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4_MASK', + 'SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4__SHIFT', + 'SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5_MASK', + 'SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5__SHIFT', + 'SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6_MASK', + 'SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6__SHIFT', + 'SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7_MASK', + 'SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7__SHIFT', + 'SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK', + 'SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT', + 'SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK', + 'SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT', + 'SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1_MASK', + 'SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1__SHIFT', + 'SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2_MASK', + 'SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2__SHIFT', + 'SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3_MASK', + 'SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3__SHIFT', + 'SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK', + 'SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT', + 'SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1_MASK', + 'SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1__SHIFT', + 'SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2_MASK', + 'SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2__SHIFT', + 'SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3_MASK', + 'SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3__SHIFT', + 'SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4_MASK', + 'SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4__SHIFT', + 'SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5_MASK', + 'SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5__SHIFT', + 'SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6_MASK', + 'SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6__SHIFT', + 'SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7_MASK', + 'SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7__SHIFT', + 'SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK', + 'SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT', + 'SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK', + 'SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT', + 'SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK', + 'SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT', + 'SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK', + 'SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT', + 'SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK', + 'SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT', + 'SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK', + 'SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT', + 'SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK', + 'SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT', + 'SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK', + 'SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT', + 'SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK', + 'SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT', + 'SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK', + 'SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT', + 'SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK', + 'SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT', + 'SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK', + 'SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT', + 'SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK', + 'SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT', + 'SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK', + 'SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT', + 'SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK', + 'SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT', + 'SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK', + 'SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT', + 'SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK', + 'SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT', + 'SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK', + 'SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT', + 'SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK', + 'SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT', + 'SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK', + 'SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT', + 'SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK', + 'SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT', + 'SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK', + 'SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT', + 'SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK', + 'SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT', + 'SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK', + 'SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT', + 'SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK', + 'SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT', + 'SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK', + 'SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT', + 'SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK', + 'SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT', + 'SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK', + 'SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT', + 'SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK', + 'SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT', + 'SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK', + 'SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT', + 'SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK', + 'SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT', + 'SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK', + 'SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT', + 'SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK', + 'SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT', + 'SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK', + 'SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT', + 'SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK', + 'SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT', + 'SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK', + 'SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT', + 'SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK', + 'SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT', + 'SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10_MASK', + 'SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10__SHIFT', + 'SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK', + 'SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT', + 'SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE_MASK', + 'SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE__SHIFT', + 'SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE_MASK', + 'SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE__SHIFT', + 'SH_MEM_BASES__PRIVATE_BASE_MASK', + 'SH_MEM_BASES__PRIVATE_BASE__SHIFT', + 'SH_MEM_BASES__SHARED_BASE_MASK', + 'SH_MEM_BASES__SHARED_BASE__SHIFT', + 'SH_MEM_CONFIG__ADDRESS_MODE_MASK', + 'SH_MEM_CONFIG__ADDRESS_MODE__SHIFT', + 'SH_MEM_CONFIG__ALIGNMENT_MODE_MASK', + 'SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT', + 'SH_MEM_CONFIG__ICACHE_USE_GL1_MASK', + 'SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT', + 'SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK', + 'SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT', + 'SH_RESERVED_REG0__DATA_MASK', 'SH_RESERVED_REG0__DATA__SHIFT', + 'SH_RESERVED_REG1__DATA_MASK', 'SH_RESERVED_REG1__DATA__SHIFT', + 'SMU_RLC_RESPONSE__RESP_MASK', 'SMU_RLC_RESPONSE__RESP__SHIFT', + 'SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK', + 'SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT', + 'SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK', + 'SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT', + 'SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK', + 'SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT', + 'SPI_ARB_CYCLES_0__TS0_DURATION_MASK', + 'SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT', + 'SPI_ARB_CYCLES_0__TS1_DURATION_MASK', + 'SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT', + 'SPI_ARB_CYCLES_1__TS2_DURATION_MASK', + 'SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT', + 'SPI_ARB_CYCLES_1__TS3_DURATION_MASK', + 'SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT', + 'SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT', + 'SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT', + 'SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT', + 'SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT', + 'SPI_ATTRIBUTE_RING_BASE__BASE_MASK', + 'SPI_ATTRIBUTE_RING_BASE__BASE__SHIFT', + 'SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE_MASK', + 'SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE__SHIFT', + 'SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE_MASK', + 'SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE__SHIFT', + 'SPI_ATTRIBUTE_RING_SIZE__L1_POLICY_MASK', + 'SPI_ATTRIBUTE_RING_SIZE__L1_POLICY__SHIFT', + 'SPI_ATTRIBUTE_RING_SIZE__L2_POLICY_MASK', + 'SPI_ATTRIBUTE_RING_SIZE__L2_POLICY__SHIFT', + 'SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC_MASK', + 'SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC__SHIFT', + 'SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE_MASK', + 'SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE__SHIFT', + 'SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK', + 'SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT', + 'SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK', + 'SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT', + 'SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK', + 'SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT', + 'SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK', + 'SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT', + 'SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK', + 'SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT', + 'SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK', + 'SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT', + 'SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK', + 'SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT', + 'SPI_COMPUTE_QUEUE_RESET__RESET_MASK', + 'SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT', + 'SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK', + 'SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK', + 'SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK', + 'SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT', + 'SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK', + 'SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT', + 'SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK', + 'SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT', + 'SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK', + 'SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT', + 'SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL_MASK', + 'SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL__SHIFT', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT', + 'SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MASK', + 'SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE_MASK', + 'SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE__SHIFT', + 'SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT__SHIFT', + 'SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK', + 'SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT', + 'SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK', + 'SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT', + 'SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY_MASK', + 'SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY__SHIFT', + 'SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE_MASK', + 'SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE_MASK', + 'SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE_MASK', + 'SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE_MASK', + 'SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK', + 'SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT', + 'SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK', + 'SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT', + 'SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK', + 'SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT', + 'SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK', + 'SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT', + 'SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK', + 'SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT', + 'SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK', + 'SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT', + 'SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK', + 'SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT', + 'SPI_CONFIG_PS_CU_EN__PKR2_OFFSET_MASK', + 'SPI_CONFIG_PS_CU_EN__PKR2_OFFSET__SHIFT', + 'SPI_CONFIG_PS_CU_EN__PKR3_OFFSET_MASK', + 'SPI_CONFIG_PS_CU_EN__PKR3_OFFSET__SHIFT', + 'SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK', + 'SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK', + 'SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT', + 'SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK', + 'SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK', + 'SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT', + 'SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK', + 'SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT', + 'SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK', + 'SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT', + 'SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK', + 'SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK', + 'SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK', + 'SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__ENABLE_MASK', + 'SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK', + 'SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK', + 'SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK', + 'SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__PERIOD_MASK', + 'SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK', + 'SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK', + 'SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT', + 'SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK', + 'SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT', + 'SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT_MASK', + 'SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT__SHIFT', + 'SPI_FEATURE_CTRL__RA_PROBE_IGNORE_MASK', + 'SPI_FEATURE_CTRL__RA_PROBE_IGNORE__SHIFT', + 'SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE_MASK', + 'SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE__SHIFT', + 'SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL_MASK', + 'SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL__SHIFT', + 'SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL_MASK', + 'SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL__SHIFT', + 'SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK', + 'SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK', + 'SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK', + 'SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT', + 'SPI_GDBG_WAVE_CNTL__STALL_LAUNCH_MASK', + 'SPI_GDBG_WAVE_CNTL__STALL_LAUNCH__SHIFT', + 'SPI_GDBG_WAVE_CNTL__STALL_RA_MASK', + 'SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT', + 'SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK', + 'SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT', + 'SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK', + 'SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT', + 'SPI_GFX_CNTL__RESET_COUNTS_MASK', + 'SPI_GFX_CNTL__RESET_COUNTS__SHIFT', + 'SPI_GFX_SCRATCH_BASE_HI__DATA_MASK', + 'SPI_GFX_SCRATCH_BASE_HI__DATA__SHIFT', + 'SPI_GFX_SCRATCH_BASE_LO__DATA_MASK', + 'SPI_GFX_SCRATCH_BASE_LO__DATA__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL_MASK', + 'SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE_MASK', + 'SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE_MASK', + 'SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD_MASK', + 'SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL_MASK', + 'SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE_MASK', + 'SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE_MASK', + 'SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE__SHIFT', + 'SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD_MASK', + 'SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1_MASK', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2_MASK', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR_MASK', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_MASK', + 'SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__PH_MODE_MASK', + 'SPI_GS_THROTTLE_CNTL2__PH_MODE__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD_MASK', + 'SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__RESERVED_MASK', + 'SPI_GS_THROTTLE_CNTL2__RESERVED__SHIFT', + 'SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE_MASK', + 'SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE__SHIFT', + 'SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK', + 'SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT', + 'SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK', + 'SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT', + 'SPI_LB_CTR_CTRL__LOAD_MASK', 'SPI_LB_CTR_CTRL__LOAD__SHIFT', + 'SPI_LB_CTR_CTRL__RESET_COUNTS_MASK', + 'SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT', + 'SPI_LB_CTR_CTRL__WAVES_SELECT_MASK', + 'SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT', + 'SPI_LB_DATA_REG__CNT_DATA_MASK', + 'SPI_LB_DATA_REG__CNT_DATA__SHIFT', + 'SPI_LB_DATA_WAVES__COUNT0_MASK', + 'SPI_LB_DATA_WAVES__COUNT0__SHIFT', + 'SPI_LB_DATA_WAVES__COUNT1_MASK', + 'SPI_LB_DATA_WAVES__COUNT1__SHIFT', + 'SPI_LB_WGP_MASK__WGP_MASK_MASK', + 'SPI_LB_WGP_MASK__WGP_MASK__SHIFT', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT', + 'SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT', + 'SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK', + 'SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT', + 'SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK', + 'SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT', + 'SPI_PQEV_CTRL__QUEUE_DURATION_MASK', + 'SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT', + 'SPI_PQEV_CTRL__SCAN_PERIOD_MASK', + 'SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT', + 'SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK', + 'SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT', + 'SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_0__DUP_MASK', + 'SPI_PS_INPUT_CNTL_0__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_0__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_0__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_0__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_10__DUP_MASK', + 'SPI_PS_INPUT_CNTL_10__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_10__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_10__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_10__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_11__DUP_MASK', + 'SPI_PS_INPUT_CNTL_11__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_11__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_11__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_11__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_12__DUP_MASK', + 'SPI_PS_INPUT_CNTL_12__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_12__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_12__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_12__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_13__DUP_MASK', + 'SPI_PS_INPUT_CNTL_13__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_13__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_13__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_13__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_14__DUP_MASK', + 'SPI_PS_INPUT_CNTL_14__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_14__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_14__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_14__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_15__DUP_MASK', + 'SPI_PS_INPUT_CNTL_15__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_15__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_15__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_15__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_16__DUP_MASK', + 'SPI_PS_INPUT_CNTL_16__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_16__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_16__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_16__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_17__DUP_MASK', + 'SPI_PS_INPUT_CNTL_17__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_17__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_17__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_17__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_18__DUP_MASK', + 'SPI_PS_INPUT_CNTL_18__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_18__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_18__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_18__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_19__DUP_MASK', + 'SPI_PS_INPUT_CNTL_19__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_19__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_19__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_19__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_1__DUP_MASK', + 'SPI_PS_INPUT_CNTL_1__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_1__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_1__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_1__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_20__DUP_MASK', + 'SPI_PS_INPUT_CNTL_20__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_20__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_20__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_20__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_21__DUP_MASK', + 'SPI_PS_INPUT_CNTL_21__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_21__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_21__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_21__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_22__DUP_MASK', + 'SPI_PS_INPUT_CNTL_22__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_22__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_22__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_22__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_23__DUP_MASK', + 'SPI_PS_INPUT_CNTL_23__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_23__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_23__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_23__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_24__DUP_MASK', + 'SPI_PS_INPUT_CNTL_24__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_24__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_24__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_24__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_25__DUP_MASK', + 'SPI_PS_INPUT_CNTL_25__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_25__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_25__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_25__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_26__DUP_MASK', + 'SPI_PS_INPUT_CNTL_26__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_26__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_26__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_26__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_27__DUP_MASK', + 'SPI_PS_INPUT_CNTL_27__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_27__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_27__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_27__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_28__DUP_MASK', + 'SPI_PS_INPUT_CNTL_28__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_28__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_28__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_28__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_29__DUP_MASK', + 'SPI_PS_INPUT_CNTL_29__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_29__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_29__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_29__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_2__DUP_MASK', + 'SPI_PS_INPUT_CNTL_2__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_2__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_2__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_2__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_30__DUP_MASK', + 'SPI_PS_INPUT_CNTL_30__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_30__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_30__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_30__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_31__DUP_MASK', + 'SPI_PS_INPUT_CNTL_31__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_31__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_31__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_31__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_3__DUP_MASK', + 'SPI_PS_INPUT_CNTL_3__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_3__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_3__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_3__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_4__DUP_MASK', + 'SPI_PS_INPUT_CNTL_4__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_4__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_4__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_4__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_5__DUP_MASK', + 'SPI_PS_INPUT_CNTL_5__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_5__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_5__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_5__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_6__DUP_MASK', + 'SPI_PS_INPUT_CNTL_6__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_6__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_6__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_6__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_7__DUP_MASK', + 'SPI_PS_INPUT_CNTL_7__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_7__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_7__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_7__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_8__DUP_MASK', + 'SPI_PS_INPUT_CNTL_8__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_8__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_8__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_8__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_9__DUP_MASK', + 'SPI_PS_INPUT_CNTL_9__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_9__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_9__PRIM_ATTR_MASK', + 'SPI_PS_INPUT_CNTL_9__PRIM_ATTR__SHIFT', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK', + 'SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT', + 'SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK', + 'SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK', + 'SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK', + 'SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT', + 'SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK', + 'SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT', + 'SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK', + 'SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT', + 'SPI_PS_IN_CONTROL__NUM_INTERP_MASK', + 'SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT', + 'SPI_PS_IN_CONTROL__NUM_PRIM_INTERP_MASK', + 'SPI_PS_IN_CONTROL__NUM_PRIM_INTERP__SHIFT', + 'SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK', + 'SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT', + 'SPI_PS_IN_CONTROL__PARAM_GEN_MASK', + 'SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT', + 'SPI_PS_IN_CONTROL__PS_W32_EN_MASK', + 'SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT', + 'SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK', + 'SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT', + 'SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK', + 'SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X_MASK', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X__SHIFT', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y_MASK', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y__SHIFT', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z_MASK', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z__SHIFT', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE_MASK', + 'SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE__SHIFT', + 'SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS_MASK', + 'SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS__SHIFT', + 'SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS_MASK', + 'SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS__SHIFT', + 'SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK', + 'SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK', + 'SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT', + 'SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK', + 'SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT', + 'SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK', + 'SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT', + 'SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT', + 'SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK', + 'SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__RESERVED_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__RESERVED__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START__SHIFT', + 'SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP_MASK', + 'SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP__SHIFT', + 'SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END_MASK', + 'SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END__SHIFT', + 'SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START_MASK', + 'SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START__SHIFT', + 'SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP_MASK', + 'SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP__SHIFT', + 'SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END_MASK', + 'SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END__SHIFT', + 'SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START_MASK', + 'SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT', + 'SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK', + 'SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT', + 'SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK', + 'SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK', + 'SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK', + 'SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK', + 'SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK', + 'SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK', + 'SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK', + 'SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT', + 'SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK', + 'SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT', + 'SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK', + 'SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT', + 'SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK', + 'SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_GS_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_GS_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_HS_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT', + 'SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK', + 'SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT', + 'SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK', + 'SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT', + 'SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK', + 'SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT', + 'SPI_TMPRING_SIZE__WAVESIZE_MASK', + 'SPI_TMPRING_SIZE__WAVESIZE__SHIFT', + 'SPI_TMPRING_SIZE__WAVES_MASK', 'SPI_TMPRING_SIZE__WAVES__SHIFT', + 'SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK', + 'SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT', + 'SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK', + 'SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT', + 'SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT_MASK', + 'SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT__SHIFT', + 'SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK', + 'SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT', + 'SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK', + 'SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT', + 'SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK', + 'SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT', + 'SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK', + 'SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT', + 'SPI_WF_LIFETIME_CNTL__EN_MASK', + 'SPI_WF_LIFETIME_CNTL__EN__SHIFT', + 'SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK', + 'SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT', + 'SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK', + 'SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT', + 'SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK', + 'SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT', + 'SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK', + 'SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT', + 'SP_CONFIG__DISABLE_TRANS_COEXEC_MASK', + 'SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT', + 'SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK', + 'SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT', + 'SQC_CACHES__COMPLETE_MASK', 'SQC_CACHES__COMPLETE__SHIFT', + 'SQC_CACHES__INVALIDATE_MASK', 'SQC_CACHES__INVALIDATE__SHIFT', + 'SQC_CACHES__TARGET_DATA_MASK', 'SQC_CACHES__TARGET_DATA__SHIFT', + 'SQC_CACHES__TARGET_INST_MASK', 'SQC_CACHES__TARGET_INST__SHIFT', + 'SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG_MASK', + 'SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG__SHIFT', + 'SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE_MASK', + 'SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE__SHIFT', + 'SQC_CONFIG__DATA_CACHE_SIZE_MASK', + 'SQC_CONFIG__DATA_CACHE_SIZE__SHIFT', + 'SQC_CONFIG__EVICT_LRU_MASK', 'SQC_CONFIG__EVICT_LRU__SHIFT', + 'SQC_CONFIG__FORCE_1_BANK_MASK', + 'SQC_CONFIG__FORCE_1_BANK__SHIFT', + 'SQC_CONFIG__FORCE_2_BANK_MASK', + 'SQC_CONFIG__FORCE_2_BANK__SHIFT', + 'SQC_CONFIG__FORCE_ALWAYS_MISS_MASK', + 'SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT', + 'SQC_CONFIG__FORCE_IN_ORDER_MASK', + 'SQC_CONFIG__FORCE_IN_ORDER__SHIFT', + 'SQC_CONFIG__HIT_FIFO_DEPTH_MASK', + 'SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT', + 'SQC_CONFIG__INST_CACHE_SIZE_MASK', + 'SQC_CONFIG__INST_CACHE_SIZE__SHIFT', + 'SQC_CONFIG__LS_DISABLE_CLOCKS_MASK', + 'SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT', + 'SQC_CONFIG__MISS_FIFO_DEPTH_MASK', + 'SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT', + 'SQC_CONFIG__PER_VMID_INV_DISABLE_MASK', + 'SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT', + 'SQC_CONFIG__SPARE_MASK', 'SQC_CONFIG__SPARE__SHIFT', + 'SQG_CONFIG__GL1H_PREFETCH_PAGE_MASK', + 'SQG_CONFIG__GL1H_PREFETCH_PAGE__SHIFT', + 'SQG_CONFIG__SQG_ICPFT_CLR_MASK', + 'SQG_CONFIG__SQG_ICPFT_CLR__SHIFT', + 'SQG_CONFIG__SQG_ICPFT_EN_MASK', + 'SQG_CONFIG__SQG_ICPFT_EN__SHIFT', + 'SQG_CONFIG__XNACK_INTR_MASK_MASK', + 'SQG_CONFIG__XNACK_INTR_MASK__SHIFT', + 'SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED_MASK', + 'SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED__SHIFT', + 'SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED_MASK', + 'SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED__SHIFT', + 'SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED_MASK', + 'SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED__SHIFT', + 'SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED_MASK', + 'SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED__SHIFT', + 'SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER2_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER3_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER4_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER4_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER5_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER5_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER6_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER6_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER6_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK', + 'SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT', + 'SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK', + 'SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT', + 'SQG_PERFCOUNTER7_SELECT__PERF_MODE_MASK', + 'SQG_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT', + 'SQG_PERFCOUNTER7_SELECT__PERF_SEL_MASK', + 'SQG_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT', + 'SQG_PERFCOUNTER7_SELECT__SPM_MODE_MASK', + 'SQG_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT', + 'SQG_PERFCOUNTER_CTRL2__FORCE_EN_MASK', + 'SQG_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT', + 'SQG_PERFCOUNTER_CTRL2__VMID_EN_MASK', + 'SQG_PERFCOUNTER_CTRL2__VMID_EN__SHIFT', + 'SQG_PERFCOUNTER_CTRL__CS_EN_MASK', + 'SQG_PERFCOUNTER_CTRL__CS_EN__SHIFT', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK', + 'SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT', + 'SQG_PERFCOUNTER_CTRL__GS_EN_MASK', + 'SQG_PERFCOUNTER_CTRL__GS_EN__SHIFT', + 'SQG_PERFCOUNTER_CTRL__HS_EN_MASK', + 'SQG_PERFCOUNTER_CTRL__HS_EN__SHIFT', + 'SQG_PERFCOUNTER_CTRL__PS_EN_MASK', + 'SQG_PERFCOUNTER_CTRL__PS_EN__SHIFT', + 'SQG_PERF_SAMPLE_FINISH__STATUS_MASK', + 'SQG_PERF_SAMPLE_FINISH__STATUS__SHIFT', + 'SQG_STATUS__REG_BUSY_MASK', 'SQG_STATUS__REG_BUSY__SHIFT', + 'SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK', + 'SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT', + 'SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK', + 'SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT', + 'SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK', + 'SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT', + 'SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK', + 'SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT', 'SQ_CMD__CHECK_VMID_MASK', + 'SQ_CMD__CHECK_VMID__SHIFT', 'SQ_CMD__CMD_MASK', + 'SQ_CMD__CMD__SHIFT', 'SQ_CMD__DATA_MASK', 'SQ_CMD__DATA__SHIFT', + 'SQ_CMD__MODE_MASK', 'SQ_CMD__MODE__SHIFT', + 'SQ_CMD__QUEUE_ID_MASK', 'SQ_CMD__QUEUE_ID__SHIFT', + 'SQ_CMD__VM_ID_MASK', 'SQ_CMD__VM_ID__SHIFT', + 'SQ_CMD__WAVE_ID_MASK', 'SQ_CMD__WAVE_ID__SHIFT', + 'SQ_CONFIG__DISABLE_END_CLAUSE_TX_MASK', + 'SQ_CONFIG__DISABLE_END_CLAUSE_TX__SHIFT', + 'SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT', + 'SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP_MASK', + 'SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP__SHIFT', + 'SQ_CONFIG__ECO_SPARE_MASK', 'SQ_CONFIG__ECO_SPARE__SHIFT', + 'SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS_MASK', + 'SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS__SHIFT', + 'SQ_CONFIG__NEW_TRANS_ARB_SCHEME_MASK', + 'SQ_CONFIG__NEW_TRANS_ARB_SCHEME__SHIFT', + 'SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS_MASK', + 'SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS__SHIFT', + 'SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT', + 'SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK', + 'SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT', + 'SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT_MASK', + 'SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT__SHIFT', + 'SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE_MASK', + 'SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE__SHIFT', + 'SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0_MASK', + 'SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0__SHIFT', + 'SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1_MASK', + 'SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__BUSY_MASK', + 'SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY_MASK', + 'SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT', + 'SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK', + 'SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT', + 'SQ_DEBUG__SINGLE_ALU_OP_MASK', 'SQ_DEBUG__SINGLE_ALU_OP__SHIFT', + 'SQ_DEBUG__SINGLE_MEMOP_MASK', 'SQ_DEBUG__SINGLE_MEMOP__SHIFT', + 'SQ_DEBUG__WAIT_DEP_CTR_ZERO_MASK', + 'SQ_DEBUG__WAIT_DEP_CTR_ZERO__SHIFT', + 'SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT', + 'SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK', + 'SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT', + 'SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK', + 'SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT', + 'SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED_MASK', + 'SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED__SHIFT', + 'SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT_MASK', + 'SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT__SHIFT', + 'SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK', + 'SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT', + 'SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK', + 'SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT', + 'SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK', + 'SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT', + 'SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK', + 'SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT', + 'SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK', + 'SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT', + 'SQ_IND_DATA__DATA_MASK', 'SQ_IND_DATA__DATA__SHIFT', + 'SQ_IND_INDEX__AUTO_INCR_MASK', 'SQ_IND_INDEX__AUTO_INCR__SHIFT', + 'SQ_IND_INDEX__INDEX_MASK', 'SQ_IND_INDEX__INDEX__SHIFT', + 'SQ_IND_INDEX__WAVE_ID_MASK', 'SQ_IND_INDEX__WAVE_ID__SHIFT', + 'SQ_IND_INDEX__WORKITEM_ID_MASK', + 'SQ_IND_INDEX__WORKITEM_ID__SHIFT', + 'SQ_INTERRUPT_AUTO_MASK__MASK_MASK', + 'SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT', + 'SQ_INTERRUPT_MSG_CTRL__STALL_MASK', + 'SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT', + 'SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK', + 'SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT', + 'SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK', + 'SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT', + 'SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK', + 'SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL2__VMID_EN_MASK', + 'SQ_PERFCOUNTER_CTRL2__VMID_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__CS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK', + 'SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT', + 'SQ_PERFCOUNTER_CTRL__GS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__HS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__PS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT', + 'SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK', + 'SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT', + 'SQ_RANDOM_WAVE_PRI__RET_MASK', 'SQ_RANDOM_WAVE_PRI__RET__SHIFT', + 'SQ_RANDOM_WAVE_PRI__RNG_MASK', 'SQ_RANDOM_WAVE_PRI__RNG__SHIFT', + 'SQ_RANDOM_WAVE_PRI__RUI_MASK', 'SQ_RANDOM_WAVE_PRI__RUI__SHIFT', + 'SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK', + 'SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT', + 'SQ_SHADER_TBA_HI__ADDR_HI_MASK', + 'SQ_SHADER_TBA_HI__ADDR_HI__SHIFT', + 'SQ_SHADER_TBA_HI__TRAP_EN_MASK', + 'SQ_SHADER_TBA_HI__TRAP_EN__SHIFT', + 'SQ_SHADER_TBA_LO__ADDR_LO_MASK', + 'SQ_SHADER_TBA_LO__ADDR_LO__SHIFT', + 'SQ_SHADER_TMA_HI__ADDR_HI_MASK', + 'SQ_SHADER_TMA_HI__ADDR_HI__SHIFT', + 'SQ_SHADER_TMA_LO__ADDR_LO_MASK', + 'SQ_SHADER_TMA_LO__ADDR_LO__SHIFT', + 'SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK', + 'SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT', + 'SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK', + 'SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT', + 'SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK', + 'SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT', + 'SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK', + 'SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT', + 'SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK', + 'SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT', + 'SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK', + 'SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT', + 'SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK', + 'SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT', + 'SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK', + 'SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT', + 'SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK', + 'SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT', + 'SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK', + 'SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT', + 'SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK', + 'SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT', + 'SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK', + 'SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT', + 'SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK', + 'SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT', + 'SQ_THREAD_TRACE_CTRL__GL1_PERF_EN_MASK', + 'SQ_THREAD_TRACE_CTRL__GL1_PERF_EN__SHIFT', + 'SQ_THREAD_TRACE_CTRL__HIWATER_MASK', + 'SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT', + 'SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK', + 'SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT', + 'SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK', + 'SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT', + 'SQ_THREAD_TRACE_CTRL__MODE_MASK', + 'SQ_THREAD_TRACE_CTRL__MODE__SHIFT', + 'SQ_THREAD_TRACE_CTRL__REG_AT_HWM_MASK', + 'SQ_THREAD_TRACE_CTRL__REG_AT_HWM__SHIFT', + 'SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK', + 'SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT', + 'SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK', + 'SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT', + 'SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK', + 'SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT', + 'SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK', + 'SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT', + 'SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK', + 'SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT', + 'SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK', + 'SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT', + 'SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK', + 'SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT', + 'SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK', + 'SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT', + 'SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK', + 'SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT', + 'SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK', + 'SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT', + 'SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK', + 'SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT', + 'SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK', + 'SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT', + 'SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA_MASK', + 'SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA__SHIFT', + 'SQ_THREAD_TRACE_MASK__SA_SEL_MASK', + 'SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT', + 'SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK', + 'SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT', + 'SQ_THREAD_TRACE_MASK__WGP_SEL_MASK', + 'SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT', + 'SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK', + 'SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT', + 'SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK', + 'SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT', + 'SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK', + 'SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT', + 'SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_MASK', + 'SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS_MASK', + 'SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS__SHIFT', + 'SQ_THREAD_TRACE_STATUS2__BUF_ISSUE__SHIFT', + 'SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK', + 'SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT', + 'SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL_MASK', + 'SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL__SHIFT', + 'SQ_THREAD_TRACE_STATUS__BUSY_MASK', + 'SQ_THREAD_TRACE_STATUS__BUSY__SHIFT', + 'SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK', + 'SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT', + 'SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK', + 'SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT', + 'SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK', + 'SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT', + 'SQ_THREAD_TRACE_STATUS__WRITE_ERROR_MASK', + 'SQ_THREAD_TRACE_STATUS__WRITE_ERROR__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_0__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_1__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_2__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_3__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_4__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_5__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_6__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_7__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT', + 'SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK', + 'SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT', + 'SQ_THREAD_TRACE_WPTR__OFFSET_MASK', + 'SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT', + 'SQ_WATCH0_ADDR_H__ADDR_MASK', 'SQ_WATCH0_ADDR_H__ADDR__SHIFT', + 'SQ_WATCH0_ADDR_L__ADDR_MASK', 'SQ_WATCH0_ADDR_L__ADDR__SHIFT', + 'SQ_WATCH0_CNTL__MASK_MASK', 'SQ_WATCH0_CNTL__MASK__SHIFT', + 'SQ_WATCH0_CNTL__VALID_MASK', 'SQ_WATCH0_CNTL__VALID__SHIFT', + 'SQ_WATCH0_CNTL__VMID_MASK', 'SQ_WATCH0_CNTL__VMID__SHIFT', + 'SQ_WATCH1_ADDR_H__ADDR_MASK', 'SQ_WATCH1_ADDR_H__ADDR__SHIFT', + 'SQ_WATCH1_ADDR_L__ADDR_MASK', 'SQ_WATCH1_ADDR_L__ADDR__SHIFT', + 'SQ_WATCH1_CNTL__MASK_MASK', 'SQ_WATCH1_CNTL__MASK__SHIFT', + 'SQ_WATCH1_CNTL__VALID_MASK', 'SQ_WATCH1_CNTL__VALID__SHIFT', + 'SQ_WATCH1_CNTL__VMID_MASK', 'SQ_WATCH1_CNTL__VMID__SHIFT', + 'SQ_WATCH2_ADDR_H__ADDR_MASK', 'SQ_WATCH2_ADDR_H__ADDR__SHIFT', + 'SQ_WATCH2_ADDR_L__ADDR_MASK', 'SQ_WATCH2_ADDR_L__ADDR__SHIFT', + 'SQ_WATCH2_CNTL__MASK_MASK', 'SQ_WATCH2_CNTL__MASK__SHIFT', + 'SQ_WATCH2_CNTL__VALID_MASK', 'SQ_WATCH2_CNTL__VALID__SHIFT', + 'SQ_WATCH2_CNTL__VMID_MASK', 'SQ_WATCH2_CNTL__VMID__SHIFT', + 'SQ_WATCH3_ADDR_H__ADDR_MASK', 'SQ_WATCH3_ADDR_H__ADDR__SHIFT', + 'SQ_WATCH3_ADDR_L__ADDR_MASK', 'SQ_WATCH3_ADDR_L__ADDR__SHIFT', + 'SQ_WATCH3_CNTL__MASK_MASK', 'SQ_WATCH3_CNTL__MASK__SHIFT', + 'SQ_WATCH3_CNTL__VALID_MASK', 'SQ_WATCH3_CNTL__VALID__SHIFT', + 'SQ_WATCH3_CNTL__VMID_MASK', 'SQ_WATCH3_CNTL__VMID__SHIFT', + 'SQ_WAVE_ACTIVE__WAVE_SLOT_MASK', + 'SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT', + 'SQ_WAVE_EXEC_HI__EXEC_HI_MASK', + 'SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT', + 'SQ_WAVE_EXEC_LO__EXEC_LO_MASK', + 'SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT', + 'SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK', + 'SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT', + 'SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK', + 'SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT', + 'SQ_WAVE_FLUSH_IB__UNUSED_MASK', + 'SQ_WAVE_FLUSH_IB__UNUSED__SHIFT', + 'SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK', + 'SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT', + 'SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK', + 'SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT', + 'SQ_WAVE_HW_ID1__DP_RATE_MASK', 'SQ_WAVE_HW_ID1__DP_RATE__SHIFT', + 'SQ_WAVE_HW_ID1__SA_ID_MASK', 'SQ_WAVE_HW_ID1__SA_ID__SHIFT', + 'SQ_WAVE_HW_ID1__SE_ID_MASK', 'SQ_WAVE_HW_ID1__SE_ID__SHIFT', + 'SQ_WAVE_HW_ID1__SIMD_ID_MASK', 'SQ_WAVE_HW_ID1__SIMD_ID__SHIFT', + 'SQ_WAVE_HW_ID1__WAVE_ID_MASK', 'SQ_WAVE_HW_ID1__WAVE_ID__SHIFT', + 'SQ_WAVE_HW_ID1__WGP_ID_MASK', 'SQ_WAVE_HW_ID1__WGP_ID__SHIFT', + 'SQ_WAVE_HW_ID2__ME_ID_MASK', 'SQ_WAVE_HW_ID2__ME_ID__SHIFT', + 'SQ_WAVE_HW_ID2__PIPE_ID_MASK', 'SQ_WAVE_HW_ID2__PIPE_ID__SHIFT', + 'SQ_WAVE_HW_ID2__QUEUE_ID_MASK', + 'SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT', + 'SQ_WAVE_HW_ID2__STATE_ID_MASK', + 'SQ_WAVE_HW_ID2__STATE_ID__SHIFT', 'SQ_WAVE_HW_ID2__VM_ID_MASK', + 'SQ_WAVE_HW_ID2__VM_ID__SHIFT', 'SQ_WAVE_HW_ID2__WG_ID_MASK', + 'SQ_WAVE_HW_ID2__WG_ID__SHIFT', 'SQ_WAVE_IB_DBG1__MISC_CNT_MASK', + 'SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT', + 'SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK', + 'SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT', + 'SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK', + 'SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT', + 'SQ_WAVE_IB_STS2__INST_PREFETCH_MASK', + 'SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT', + 'SQ_WAVE_IB_STS2__MEM_ORDER_MASK', + 'SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT', + 'SQ_WAVE_IB_STS2__WAVE64_MASK', 'SQ_WAVE_IB_STS2__WAVE64__SHIFT', + 'SQ_WAVE_IB_STS__EXP_CNT_MASK', 'SQ_WAVE_IB_STS__EXP_CNT__SHIFT', + 'SQ_WAVE_IB_STS__LGKM_CNT_MASK', + 'SQ_WAVE_IB_STS__LGKM_CNT__SHIFT', 'SQ_WAVE_IB_STS__VM_CNT_MASK', + 'SQ_WAVE_IB_STS__VM_CNT__SHIFT', 'SQ_WAVE_IB_STS__VS_CNT_MASK', + 'SQ_WAVE_IB_STS__VS_CNT__SHIFT', + 'SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK', + 'SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT', + 'SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK', + 'SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT', + 'SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK', + 'SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT', + 'SQ_WAVE_M0__M0_MASK', 'SQ_WAVE_M0__M0__SHIFT', + 'SQ_WAVE_MODE__DISABLE_PERF_MASK', + 'SQ_WAVE_MODE__DISABLE_PERF__SHIFT', + 'SQ_WAVE_MODE__DX10_CLAMP_MASK', + 'SQ_WAVE_MODE__DX10_CLAMP__SHIFT', 'SQ_WAVE_MODE__EXCP_EN_MASK', + 'SQ_WAVE_MODE__EXCP_EN__SHIFT', 'SQ_WAVE_MODE__FP16_OVFL_MASK', + 'SQ_WAVE_MODE__FP16_OVFL__SHIFT', 'SQ_WAVE_MODE__FP_DENORM_MASK', + 'SQ_WAVE_MODE__FP_DENORM__SHIFT', 'SQ_WAVE_MODE__FP_ROUND_MASK', + 'SQ_WAVE_MODE__FP_ROUND__SHIFT', 'SQ_WAVE_MODE__IEEE_MASK', + 'SQ_WAVE_MODE__IEEE__SHIFT', 'SQ_WAVE_MODE__LOD_CLAMPED_MASK', + 'SQ_WAVE_MODE__LOD_CLAMPED__SHIFT', + 'SQ_WAVE_MODE__TRAP_AFTER_INST_EN_MASK', + 'SQ_WAVE_MODE__TRAP_AFTER_INST_EN__SHIFT', + 'SQ_WAVE_MODE__WAVE_END_MASK', 'SQ_WAVE_MODE__WAVE_END__SHIFT', + 'SQ_WAVE_PC_HI__PC_HI_MASK', 'SQ_WAVE_PC_HI__PC_HI__SHIFT', + 'SQ_WAVE_PC_LO__PC_LO_MASK', 'SQ_WAVE_PC_LO__PC_LO__SHIFT', + 'SQ_WAVE_POPS_PACKER__POPS_EN_MASK', + 'SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT', + 'SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK', + 'SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT', + 'SQ_WAVE_SCHED_MODE__DEP_MODE_MASK', + 'SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT', + 'SQ_WAVE_SHADER_CYCLES__CYCLES_MASK', + 'SQ_WAVE_SHADER_CYCLES__CYCLES__SHIFT', + 'SQ_WAVE_STATUS__ECC_ERR_MASK', 'SQ_WAVE_STATUS__ECC_ERR__SHIFT', + 'SQ_WAVE_STATUS__EXECZ_MASK', 'SQ_WAVE_STATUS__EXECZ__SHIFT', + 'SQ_WAVE_STATUS__EXPORT_RDY_MASK', + 'SQ_WAVE_STATUS__EXPORT_RDY__SHIFT', + 'SQ_WAVE_STATUS__FATAL_HALT_MASK', + 'SQ_WAVE_STATUS__FATAL_HALT__SHIFT', 'SQ_WAVE_STATUS__HALT_MASK', + 'SQ_WAVE_STATUS__HALT__SHIFT', 'SQ_WAVE_STATUS__IDLE_MASK', + 'SQ_WAVE_STATUS__IDLE__SHIFT', 'SQ_WAVE_STATUS__IN_BARRIER_MASK', + 'SQ_WAVE_STATUS__IN_BARRIER__SHIFT', 'SQ_WAVE_STATUS__IN_TG_MASK', + 'SQ_WAVE_STATUS__IN_TG__SHIFT', + 'SQ_WAVE_STATUS__LDS_PARAM_READY_MASK', + 'SQ_WAVE_STATUS__LDS_PARAM_READY__SHIFT', + 'SQ_WAVE_STATUS__MUST_EXPORT_MASK', + 'SQ_WAVE_STATUS__MUST_EXPORT__SHIFT', + 'SQ_WAVE_STATUS__MUST_GS_ALLOC_MASK', + 'SQ_WAVE_STATUS__MUST_GS_ALLOC__SHIFT', + 'SQ_WAVE_STATUS__NO_VGPRS_MASK', + 'SQ_WAVE_STATUS__NO_VGPRS__SHIFT', + 'SQ_WAVE_STATUS__OREO_CONFLICT_MASK', + 'SQ_WAVE_STATUS__OREO_CONFLICT__SHIFT', + 'SQ_WAVE_STATUS__PERF_EN_MASK', 'SQ_WAVE_STATUS__PERF_EN__SHIFT', + 'SQ_WAVE_STATUS__PRIV_MASK', 'SQ_WAVE_STATUS__PRIV__SHIFT', + 'SQ_WAVE_STATUS__SCC_MASK', 'SQ_WAVE_STATUS__SCC__SHIFT', + 'SQ_WAVE_STATUS__SCRATCH_EN_MASK', + 'SQ_WAVE_STATUS__SCRATCH_EN__SHIFT', + 'SQ_WAVE_STATUS__SKIP_EXPORT_MASK', + 'SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT', + 'SQ_WAVE_STATUS__SPI_PRIO_MASK', + 'SQ_WAVE_STATUS__SPI_PRIO__SHIFT', 'SQ_WAVE_STATUS__TRAP_EN_MASK', + 'SQ_WAVE_STATUS__TRAP_EN__SHIFT', 'SQ_WAVE_STATUS__TRAP_MASK', + 'SQ_WAVE_STATUS__TRAP__SHIFT', 'SQ_WAVE_STATUS__TTRACE_EN_MASK', + 'SQ_WAVE_STATUS__TTRACE_EN__SHIFT', + 'SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK', + 'SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT', + 'SQ_WAVE_STATUS__USER_PRIO_MASK', + 'SQ_WAVE_STATUS__USER_PRIO__SHIFT', 'SQ_WAVE_STATUS__VALID_MASK', + 'SQ_WAVE_STATUS__VALID__SHIFT', 'SQ_WAVE_STATUS__VCCZ_MASK', + 'SQ_WAVE_STATUS__VCCZ__SHIFT', 'SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK', + 'SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT', + 'SQ_WAVE_TRAPSTS__EXCP_HI_MASK', + 'SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT', 'SQ_WAVE_TRAPSTS__EXCP_MASK', + 'SQ_WAVE_TRAPSTS__EXCP__SHIFT', 'SQ_WAVE_TRAPSTS__HOST_TRAP_MASK', + 'SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT', + 'SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK', + 'SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT', + 'SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK', + 'SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT', + 'SQ_WAVE_TRAPSTS__SAVECTX_MASK', + 'SQ_WAVE_TRAPSTS__SAVECTX__SHIFT', + 'SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK', + 'SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT', + 'SQ_WAVE_TRAPSTS__UTC_ERROR_MASK', + 'SQ_WAVE_TRAPSTS__UTC_ERROR__SHIFT', + 'SQ_WAVE_TRAPSTS__WAVESTART_MASK', + 'SQ_WAVE_TRAPSTS__WAVESTART__SHIFT', + 'SQ_WAVE_TRAPSTS__WAVE_END_MASK', + 'SQ_WAVE_TRAPSTS__WAVE_END__SHIFT', 'SQ_WAVE_TTMP0__DATA_MASK', + 'SQ_WAVE_TTMP0__DATA__SHIFT', 'SQ_WAVE_TTMP10__DATA_MASK', + 'SQ_WAVE_TTMP10__DATA__SHIFT', 'SQ_WAVE_TTMP11__DATA_MASK', + 'SQ_WAVE_TTMP11__DATA__SHIFT', 'SQ_WAVE_TTMP12__DATA_MASK', + 'SQ_WAVE_TTMP12__DATA__SHIFT', 'SQ_WAVE_TTMP13__DATA_MASK', + 'SQ_WAVE_TTMP13__DATA__SHIFT', 'SQ_WAVE_TTMP14__DATA_MASK', + 'SQ_WAVE_TTMP14__DATA__SHIFT', 'SQ_WAVE_TTMP15__DATA_MASK', + 'SQ_WAVE_TTMP15__DATA__SHIFT', 'SQ_WAVE_TTMP1__DATA_MASK', + 'SQ_WAVE_TTMP1__DATA__SHIFT', 'SQ_WAVE_TTMP3__DATA_MASK', + 'SQ_WAVE_TTMP3__DATA__SHIFT', 'SQ_WAVE_TTMP4__DATA_MASK', + 'SQ_WAVE_TTMP4__DATA__SHIFT', 'SQ_WAVE_TTMP5__DATA_MASK', + 'SQ_WAVE_TTMP5__DATA__SHIFT', 'SQ_WAVE_TTMP6__DATA_MASK', + 'SQ_WAVE_TTMP6__DATA__SHIFT', 'SQ_WAVE_TTMP7__DATA_MASK', + 'SQ_WAVE_TTMP7__DATA__SHIFT', 'SQ_WAVE_TTMP8__DATA_MASK', + 'SQ_WAVE_TTMP8__DATA__SHIFT', 'SQ_WAVE_TTMP9__DATA_MASK', + 'SQ_WAVE_TTMP9__DATA__SHIFT', + 'SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK', + 'SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK', + 'STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT', + 'STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK', + 'STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT', + 'STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK', + 'STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT', + 'STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK', + 'STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK', + 'STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT', + 'STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK', + 'STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT', + 'STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK', + 'STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT', + 'STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK', + 'STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK', + 'SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT', + 'SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK', + 'SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT', + 'SX_DEBUG_1__DEBUG_DATA_MASK', 'SX_DEBUG_1__DEBUG_DATA__SHIFT', + 'SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK', + 'SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT', + 'SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK', + 'SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT', + 'SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK', + 'SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK', + 'SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT', + 'SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK', + 'SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT', + 'SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK', + 'SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT', + 'SX_DEBUG_1__DISABLE_GDS_CGTS_OPT_MASK', + 'SX_DEBUG_1__DISABLE_GDS_CGTS_OPT__SHIFT', + 'SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK', + 'SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT', + 'SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK', + 'SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT', + 'SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT_MASK', + 'SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT__SHIFT', + 'SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK', + 'SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT', + 'SX_DEBUG_1__DISABLE_RAM_FGCG_MASK', + 'SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT', + 'SX_DEBUG_1__DISABLE_REP_FGCG_MASK', + 'SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT', + 'SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK', + 'SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT', + 'SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE_MASK', + 'SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT', + 'SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK', + 'SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT', + 'SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK', + 'SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT', + 'SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK', + 'SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT', + 'SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK', + 'SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT', + 'SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK', + 'SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT', + 'SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK', + 'SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT', + 'SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK', + 'SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT', + 'SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK', + 'SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT', + 'SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK', + 'SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT', + 'SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK', + 'SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT', + 'SX_PS_DOWNCONVERT__MRT0_MASK', 'SX_PS_DOWNCONVERT__MRT0__SHIFT', + 'SX_PS_DOWNCONVERT__MRT1_MASK', 'SX_PS_DOWNCONVERT__MRT1__SHIFT', + 'SX_PS_DOWNCONVERT__MRT2_MASK', 'SX_PS_DOWNCONVERT__MRT2__SHIFT', + 'SX_PS_DOWNCONVERT__MRT3_MASK', 'SX_PS_DOWNCONVERT__MRT3__SHIFT', + 'SX_PS_DOWNCONVERT__MRT4_MASK', 'SX_PS_DOWNCONVERT__MRT4__SHIFT', + 'SX_PS_DOWNCONVERT__MRT5_MASK', 'SX_PS_DOWNCONVERT__MRT5__SHIFT', + 'SX_PS_DOWNCONVERT__MRT6_MASK', 'SX_PS_DOWNCONVERT__MRT6__SHIFT', + 'SX_PS_DOWNCONVERT__MRT7_MASK', 'SX_PS_DOWNCONVERT__MRT7__SHIFT', + 'TA_BC_BASE_ADDR_HI__ADDRESS_MASK', + 'TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT', + 'TA_BC_BASE_ADDR__ADDRESS_MASK', + 'TA_BC_BASE_ADDR__ADDRESS__SHIFT', + 'TA_CGTT_CTRL__OFF_HYSTERESIS_MASK', + 'TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT', + 'TA_CGTT_CTRL__ON_DELAY_MASK', 'TA_CGTT_CTRL__ON_DELAY__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS_MASK', + 'TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS__SHIFT', + 'TA_CNTL2__POINT_SAMPLE_ACCEL_DIS_MASK', + 'TA_CNTL2__POINT_SAMPLE_ACCEL_DIS__SHIFT', + 'TA_CNTL2__TRUNCATE_COORD_MODE_MASK', + 'TA_CNTL2__TRUNCATE_COORD_MODE__SHIFT', + 'TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK', + 'TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT', + 'TA_CNTL_AUX__ANISO_HALF_THRESH_MASK', + 'TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT', + 'TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK', + 'TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT', + 'TA_CNTL_AUX__ANISO_RATIO_LUT_MASK', + 'TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT', + 'TA_CNTL_AUX__ANISO_STEP_MASK', + 'TA_CNTL_AUX__ANISO_STEP_ORDER_MASK', + 'TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT', + 'TA_CNTL_AUX__ANISO_STEP__SHIFT', 'TA_CNTL_AUX__ANISO_TAP_MASK', + 'TA_CNTL_AUX__ANISO_TAP__SHIFT', + 'TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK', + 'TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT', + 'TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK', + 'TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT', + 'TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK', + 'TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT', + 'TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM_MASK', + 'TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM__SHIFT', + 'TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK', + 'TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT', + 'TA_CNTL_AUX__DEPTH_AS_PITCH_DIS_MASK', + 'TA_CNTL_AUX__DEPTH_AS_PITCH_DIS__SHIFT', + 'TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK', + 'TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK', + 'TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT', + 'TA_CNTL_AUX__GATHERH_DST_SEL_MASK', + 'TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT', + 'TA_CNTL_AUX__MINMAG_UNNORM_MASK', + 'TA_CNTL_AUX__MINMAG_UNNORM__SHIFT', + 'TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS_MASK', + 'TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS__SHIFT', + 'TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK', + 'TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT', + 'TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK', + 'TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT', + 'TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK', + 'TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT', + 'TA_CNTL__ALIGNER_CREDIT_MASK', 'TA_CNTL__ALIGNER_CREDIT__SHIFT', + 'TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK', + 'TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT', + 'TA_CNTL__TD_FIFO_CREDIT_MASK', 'TA_CNTL__TD_FIFO_CREDIT__SHIFT', + 'TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK', + 'TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT', + 'TA_CS_BC_BASE_ADDR__ADDRESS_MASK', + 'TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT', + 'TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TA_SCRATCH__SCRATCH_MASK', 'TA_SCRATCH__SCRATCH__SHIFT', + 'TA_STATUS__AL_BUSY_MASK', 'TA_STATUS__AL_BUSY__SHIFT', + 'TA_STATUS__BUSY_MASK', 'TA_STATUS__BUSY__SHIFT', + 'TA_STATUS__FA_BUSY_MASK', 'TA_STATUS__FA_BUSY__SHIFT', + 'TA_STATUS__FA_LFIFO_EMPTYB_MASK', + 'TA_STATUS__FA_LFIFO_EMPTYB__SHIFT', + 'TA_STATUS__FA_PFIFO_EMPTYB_MASK', + 'TA_STATUS__FA_PFIFO_EMPTYB__SHIFT', + 'TA_STATUS__FA_SFIFO_EMPTYB_MASK', + 'TA_STATUS__FA_SFIFO_EMPTYB__SHIFT', 'TA_STATUS__FG_BUSY_MASK', + 'TA_STATUS__FG_BUSY__SHIFT', 'TA_STATUS__FG_LFIFO_EMPTYB_MASK', + 'TA_STATUS__FG_LFIFO_EMPTYB__SHIFT', + 'TA_STATUS__FG_PFIFO_EMPTYB_MASK', + 'TA_STATUS__FG_PFIFO_EMPTYB__SHIFT', + 'TA_STATUS__FG_SFIFO_EMPTYB_MASK', + 'TA_STATUS__FG_SFIFO_EMPTYB__SHIFT', 'TA_STATUS__FL_BUSY_MASK', + 'TA_STATUS__FL_BUSY__SHIFT', 'TA_STATUS__FL_LFIFO_EMPTYB_MASK', + 'TA_STATUS__FL_LFIFO_EMPTYB__SHIFT', + 'TA_STATUS__FL_PFIFO_EMPTYB_MASK', + 'TA_STATUS__FL_PFIFO_EMPTYB__SHIFT', + 'TA_STATUS__FL_SFIFO_EMPTYB_MASK', + 'TA_STATUS__FL_SFIFO_EMPTYB__SHIFT', 'TA_STATUS__IN_BUSY_MASK', + 'TA_STATUS__IN_BUSY__SHIFT', 'TA_STATUS__LA_BUSY_MASK', + 'TA_STATUS__LA_BUSY__SHIFT', 'TA_STATUS__TA_BUSY_MASK', + 'TA_STATUS__TA_BUSY__SHIFT', + 'TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING_MASK', + 'TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING__SHIFT', + 'TCP_CNTL2__GCR_RSP_FGCG_DISABLE_MASK', + 'TCP_CNTL2__GCR_RSP_FGCG_DISABLE__SHIFT', + 'TCP_CNTL2__LS_DISABLE_CLOCKS_MASK', + 'TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT', + 'TCP_CNTL2__PERF_EN_OVERRIDE_MASK', + 'TCP_CNTL2__PERF_EN_OVERRIDE__SHIFT', + 'TCP_CNTL2__POWER_OPT_DISABLE_MASK', + 'TCP_CNTL2__POWER_OPT_DISABLE__SHIFT', + 'TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK', + 'TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT', + 'TCP_CNTL2__SPARE_BIT_MASK', 'TCP_CNTL2__SPARE_BIT__SHIFT', + 'TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK', + 'TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT', + 'TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE_MASK', + 'TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE__SHIFT', + 'TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK', + 'TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE_MASK', + 'TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_FMT_MGCG_DISABLE_MASK', + 'TCP_CNTL2__TCP_FMT_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE_MASK', + 'TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE_MASK', + 'TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE_MASK', + 'TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_MISS_MGCG_DISABLE_MASK', + 'TCP_CNTL2__TCP_MISS_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_REQ_MGCG_DISABLE_MASK', + 'TCP_CNTL2__TCP_REQ_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE_MASK', + 'TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE_MASK', + 'TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE__SHIFT', + 'TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE_MASK', + 'TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE__SHIFT', + 'TCP_CNTL2__V64_COMBINE_ENABLE_MASK', + 'TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT', + 'TCP_DEBUG_DATA__DATA_MASK', 'TCP_DEBUG_DATA__DATA__SHIFT', + 'TCP_DEBUG_INDEX__INDEX_MASK', 'TCP_DEBUG_INDEX__INDEX__SHIFT', + 'TCP_INVALIDATE__START_MASK', 'TCP_INVALIDATE__START__SHIFT', + 'TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__DIM_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__DLC_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__GLC_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__SLC_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT', + 'TCP_PERFCOUNTER_FILTER__BUFFER_MASK', + 'TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT', + 'TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK', + 'TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT', + 'TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER__DIM_MASK', + 'TCP_PERFCOUNTER_FILTER__DIM__SHIFT', + 'TCP_PERFCOUNTER_FILTER__DLC_MASK', + 'TCP_PERFCOUNTER_FILTER__DLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER__FLAT_MASK', + 'TCP_PERFCOUNTER_FILTER__FLAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER__GLC_MASK', + 'TCP_PERFCOUNTER_FILTER__GLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK', + 'TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT', + 'TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK', + 'TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT', + 'TCP_PERFCOUNTER_FILTER__SLC_MASK', + 'TCP_PERFCOUNTER_FILTER__SLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER__SW_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT', + 'TCP_STATUS__ADRS_BUSY_MASK', 'TCP_STATUS__ADRS_BUSY__SHIFT', + 'TCP_STATUS__CNTRL_BUSY_MASK', 'TCP_STATUS__CNTRL_BUSY__SHIFT', + 'TCP_STATUS__FORMAT_BUSY_MASK', 'TCP_STATUS__FORMAT_BUSY__SHIFT', + 'TCP_STATUS__GCR_BUSY_MASK', 'TCP_STATUS__GCR_BUSY__SHIFT', + 'TCP_STATUS__INPUT_BUSY_MASK', 'TCP_STATUS__INPUT_BUSY__SHIFT', + 'TCP_STATUS__LFIFO_BUSY_MASK', 'TCP_STATUS__LFIFO_BUSY__SHIFT', + 'TCP_STATUS__MEMIF_BUSY_MASK', 'TCP_STATUS__MEMIF_BUSY__SHIFT', + 'TCP_STATUS__OFIFO_BUSY_MASK', 'TCP_STATUS__OFIFO_BUSY__SHIFT', + 'TCP_STATUS__OFIFO_QUEUE_BUSY_MASK', + 'TCP_STATUS__OFIFO_QUEUE_BUSY__SHIFT', + 'TCP_STATUS__READ_BUSY_MASK', 'TCP_STATUS__READ_BUSY__SHIFT', + 'TCP_STATUS__TAGRAMS_BUSY_MASK', + 'TCP_STATUS__TAGRAMS_BUSY__SHIFT', 'TCP_STATUS__TCP_BUSY_MASK', + 'TCP_STATUS__TCP_BUSY__SHIFT', 'TCP_STATUS__VM_BUSY_MASK', + 'TCP_STATUS__VM_BUSY__SHIFT', 'TCP_STATUS__XNACK_PRT_MASK', + 'TCP_STATUS__XNACK_PRT__SHIFT', 'TCP_WATCH0_ADDR_H__ADDR_MASK', + 'TCP_WATCH0_ADDR_H__ADDR__SHIFT', 'TCP_WATCH0_ADDR_L__ADDR_MASK', + 'TCP_WATCH0_ADDR_L__ADDR__SHIFT', 'TCP_WATCH0_CNTL__MASK_MASK', + 'TCP_WATCH0_CNTL__MASK__SHIFT', 'TCP_WATCH0_CNTL__MODE_MASK', + 'TCP_WATCH0_CNTL__MODE__SHIFT', 'TCP_WATCH0_CNTL__VALID_MASK', + 'TCP_WATCH0_CNTL__VALID__SHIFT', 'TCP_WATCH0_CNTL__VMID_MASK', + 'TCP_WATCH0_CNTL__VMID__SHIFT', 'TCP_WATCH1_ADDR_H__ADDR_MASK', + 'TCP_WATCH1_ADDR_H__ADDR__SHIFT', 'TCP_WATCH1_ADDR_L__ADDR_MASK', + 'TCP_WATCH1_ADDR_L__ADDR__SHIFT', 'TCP_WATCH1_CNTL__MASK_MASK', + 'TCP_WATCH1_CNTL__MASK__SHIFT', 'TCP_WATCH1_CNTL__MODE_MASK', + 'TCP_WATCH1_CNTL__MODE__SHIFT', 'TCP_WATCH1_CNTL__VALID_MASK', + 'TCP_WATCH1_CNTL__VALID__SHIFT', 'TCP_WATCH1_CNTL__VMID_MASK', + 'TCP_WATCH1_CNTL__VMID__SHIFT', 'TCP_WATCH2_ADDR_H__ADDR_MASK', + 'TCP_WATCH2_ADDR_H__ADDR__SHIFT', 'TCP_WATCH2_ADDR_L__ADDR_MASK', + 'TCP_WATCH2_ADDR_L__ADDR__SHIFT', 'TCP_WATCH2_CNTL__MASK_MASK', + 'TCP_WATCH2_CNTL__MASK__SHIFT', 'TCP_WATCH2_CNTL__MODE_MASK', + 'TCP_WATCH2_CNTL__MODE__SHIFT', 'TCP_WATCH2_CNTL__VALID_MASK', + 'TCP_WATCH2_CNTL__VALID__SHIFT', 'TCP_WATCH2_CNTL__VMID_MASK', + 'TCP_WATCH2_CNTL__VMID__SHIFT', 'TCP_WATCH3_ADDR_H__ADDR_MASK', + 'TCP_WATCH3_ADDR_H__ADDR__SHIFT', 'TCP_WATCH3_ADDR_L__ADDR_MASK', + 'TCP_WATCH3_ADDR_L__ADDR__SHIFT', 'TCP_WATCH3_CNTL__MASK_MASK', + 'TCP_WATCH3_CNTL__MASK__SHIFT', 'TCP_WATCH3_CNTL__MODE_MASK', + 'TCP_WATCH3_CNTL__MODE__SHIFT', 'TCP_WATCH3_CNTL__VALID_MASK', + 'TCP_WATCH3_CNTL__VALID__SHIFT', 'TCP_WATCH3_CNTL__VMID_MASK', + 'TCP_WATCH3_CNTL__VMID__SHIFT', + 'TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TD_SCRATCH__SCRATCH_MASK', 'TD_SCRATCH__SCRATCH__SHIFT', + 'TD_STATUS__BUSY_MASK', 'TD_STATUS__BUSY__SHIFT', + 'UCONFIG_RESERVED_REG0__DATA_MASK', + 'UCONFIG_RESERVED_REG0__DATA__SHIFT', + 'UCONFIG_RESERVED_REG1__DATA_MASK', + 'UCONFIG_RESERVED_REG1__DATA__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_MODE_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT', + 'UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK', + 'UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT', + 'UTCL1_CTRL_0__GCRD_FGCG_DISABLE_MASK', + 'UTCL1_CTRL_0__GCRD_FGCG_DISABLE__SHIFT', + 'UTCL1_CTRL_0__MH_SPARE0_MASK', 'UTCL1_CTRL_0__MH_SPARE0__SHIFT', + 'UTCL1_CTRL_0__RESERVED_0_MASK', + 'UTCL1_CTRL_0__RESERVED_0__SHIFT', + 'UTCL1_CTRL_0__RESERVED_1_MASK', + 'UTCL1_CTRL_0__RESERVED_1__SHIFT', + 'UTCL1_CTRL_0__RESERVED_2_MASK', + 'UTCL1_CTRL_0__RESERVED_2__SHIFT', + 'UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID_MASK', + 'UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID__SHIFT', + 'UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE_MASK', + 'UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE_MASK', + 'UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE_MASK', + 'UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES_MASK', + 'UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES__SHIFT', + 'UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK', + 'UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT', + 'UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK', + 'UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT', + 'UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE_MASK', + 'UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK', + 'UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT', + 'UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE_MASK', + 'UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS_MASK', + 'UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS__SHIFT', + 'UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK', + 'UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK', + 'UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK', + 'UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE_MASK', + 'UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE__SHIFT', + 'UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_MASK', + 'UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS__SHIFT', + 'UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL_MASK', + 'UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL__SHIFT', + 'UTCL1_CTRL_1__RESERVED_MASK', 'UTCL1_CTRL_1__RESERVED__SHIFT', + 'UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS_MASK', + 'UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS__SHIFT', + 'UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE_MASK', + 'UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE__SHIFT', + 'UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_MASK', + 'UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL__SHIFT', + 'UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK', + 'UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1_MASK', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1__SHIFT', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2_MASK', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2__SHIFT', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3_MASK', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3__SHIFT', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4_MASK', + 'UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4__SHIFT', + 'UTCL1_CTRL_1__UTCL1_RMI_BYPASS_MASK', + 'UTCL1_CTRL_1__UTCL1_RMI_BYPASS__SHIFT', + 'UTCL1_CTRL_1__UTCL1_SQCD_BYPASS_MASK', + 'UTCL1_CTRL_1__UTCL1_SQCD_BYPASS__SHIFT', + 'UTCL1_CTRL_1__UTCL1_SQCI_BYPASS_MASK', + 'UTCL1_CTRL_1__UTCL1_SQCI_BYPASS__SHIFT', + 'UTCL1_CTRL_1__UTCL1_SQG_BYPASS_MASK', + 'UTCL1_CTRL_1__UTCL1_SQG_BYPASS__SHIFT', + 'UTCL1_CTRL_1__UTCL1_TCP_BYPASS_MASK', + 'UTCL1_CTRL_1__UTCL1_TCP_BYPASS__SHIFT', + 'UTCL1_CTRL_2__RESERVED_MASK', 'UTCL1_CTRL_2__RESERVED__SHIFT', + 'UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM_MASK', + 'UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM__SHIFT', + 'UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE_MASK', + 'UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE__SHIFT', + 'UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE_MASK', + 'UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE__SHIFT', + 'UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD_MASK', + 'UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD__SHIFT', + 'UTCL1_CTRL_2__UTCL1_SPARE0_MASK', + 'UTCL1_CTRL_2__UTCL1_SPARE0__SHIFT', + 'UTCL1_CTRL_2__UTCL1_SPARE1_MASK', + 'UTCL1_CTRL_2__UTCL1_SPARE1__SHIFT', + 'UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH_MASK', + 'UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH__SHIFT', + 'UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW_MASK', + 'UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW__SHIFT', + 'UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH_MASK', + 'UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH__SHIFT', + 'UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK', + 'UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT', + 'UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK', + 'UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT', + 'UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE_MASK', + 'UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE__SHIFT', + 'UTCL1_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'UTCL1_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE_MASK', + 'UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE__SHIFT', + 'UTCL1_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'UTCL1_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'UTCL1_STATUS__RESERVED_MASK', 'UTCL1_STATUS__RESERVED__SHIFT', + 'UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK', + 'UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT', + 'UTCL1_STATUS__UTCL1_INV_BUSY_MASK', + 'UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT', + 'UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK', + 'UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT', + 'UTCL1_STATUS__UTCL1_MH_BUSY_MASK', + 'UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT', + 'UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK', + 'UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT', + 'UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK', + 'UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT', + 'UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK', + 'UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT', + 'UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK', + 'UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT', + 'VGT_DMA_BASE_HI__BASE_ADDR_MASK', + 'VGT_DMA_BASE_HI__BASE_ADDR__SHIFT', + 'VGT_DMA_BASE__BASE_ADDR_MASK', 'VGT_DMA_BASE__BASE_ADDR__SHIFT', + 'VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK', + 'VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT', + 'VGT_DMA_INDEX_TYPE__ATC_MASK', 'VGT_DMA_INDEX_TYPE__ATC__SHIFT', + 'VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK', + 'VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT', + 'VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK', + 'VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT', + 'VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK', + 'VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT', + 'VGT_DMA_INDEX_TYPE__MTYPE_MASK', + 'VGT_DMA_INDEX_TYPE__MTYPE__SHIFT', + 'VGT_DMA_INDEX_TYPE__NOT_EOP_MASK', + 'VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT', + 'VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK', + 'VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT', + 'VGT_DMA_INDEX_TYPE__REQ_PATH_MASK', + 'VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT', + 'VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK', + 'VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT', + 'VGT_DMA_MAX_SIZE__MAX_SIZE_MASK', + 'VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT', + 'VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK', + 'VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT', + 'VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK', + 'VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT', + 'VGT_DMA_SIZE__NUM_INDICES_MASK', + 'VGT_DMA_SIZE__NUM_INDICES__SHIFT', + 'VGT_DRAW_INITIATOR__MAJOR_MODE_MASK', + 'VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT', + 'VGT_DRAW_INITIATOR__NOT_EOP_MASK', + 'VGT_DRAW_INITIATOR__NOT_EOP__SHIFT', + 'VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK', + 'VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT', + 'VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK', + 'VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT', + 'VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK', + 'VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT', + 'VGT_DRAW_INITIATOR__USE_OPAQUE_MASK', + 'VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT', + 'VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK', + 'VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT', + 'VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK', + 'VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT', + 'VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK', + 'VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT', + 'VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK', + 'VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT', + 'VGT_ENHANCE__MISC_MASK', 'VGT_ENHANCE__MISC__SHIFT', + 'VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK', + 'VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT', + 'VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK', + 'VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT', + 'VGT_EVENT_INITIATOR__ADDRESS_HI_MASK', + 'VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT', + 'VGT_EVENT_INITIATOR__EVENT_TYPE_MASK', + 'VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT', + 'VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK', + 'VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT', + 'VGT_GS_INSTANCE_CNT__CNT_MASK', + 'VGT_GS_INSTANCE_CNT__CNT__SHIFT', + 'VGT_GS_INSTANCE_CNT__ENABLE_MASK', + 'VGT_GS_INSTANCE_CNT__ENABLE__SHIFT', + 'VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK', + 'VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT', + 'VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK', + 'VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT', + 'VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK', + 'VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT', + 'VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK', + 'VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT', + 'VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK', + 'VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT', + 'VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK', + 'VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT', + 'VGT_INDEX_TYPE__INDEX_TYPE_MASK', + 'VGT_INDEX_TYPE__INDEX_TYPE__SHIFT', + 'VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK', + 'VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT', + 'VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK', + 'VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT', + 'VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK', + 'VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT', + 'VGT_LS_HS_CONFIG__NUM_PATCHES_MASK', + 'VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT', + 'VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK', + 'VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT', + 'VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK', + 'VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT', + 'VGT_NUM_INDICES__NUM_INDICES_MASK', + 'VGT_NUM_INDICES__NUM_INDICES__SHIFT', + 'VGT_NUM_INSTANCES__NUM_INSTANCES_MASK', + 'VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT', + 'VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK', + 'VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT', + 'VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK', + 'VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT', + 'VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK', + 'VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT', + 'VGT_PRIMITIVEID_RESET__VALUE_MASK', + 'VGT_PRIMITIVEID_RESET__VALUE__SHIFT', + 'VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK', + 'VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT', + 'VGT_REUSE_OFF__REUSE_OFF_MASK', + 'VGT_REUSE_OFF__REUSE_OFF__SHIFT', + 'VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK', + 'VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT', + 'VGT_SHADER_STAGES_EN__ES_EN_MASK', + 'VGT_SHADER_STAGES_EN__ES_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__GS_EN_MASK', + 'VGT_SHADER_STAGES_EN__GS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK', + 'VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT', + 'VGT_SHADER_STAGES_EN__GS_W32_EN_MASK', + 'VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__HS_EN_MASK', + 'VGT_SHADER_STAGES_EN__HS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__HS_W32_EN_MASK', + 'VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__LS_EN_MASK', + 'VGT_SHADER_STAGES_EN__LS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK', + 'VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT', + 'VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK', + 'VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK', + 'VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT', + 'VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK', + 'VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK', + 'VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG_MASK', + 'VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG__SHIFT', + 'VGT_SHADER_STAGES_EN__VS_EN_MASK', + 'VGT_SHADER_STAGES_EN__VS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__VS_W32_EN_MASK', + 'VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK', + 'VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT', + 'VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK', + 'VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT', + 'VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK', + 'VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT', + 'VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK', + 'VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT', + 'VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK', + 'VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT', + 'VGT_SYS_CONFIG__DUAL_CORE_EN_MASK', + 'VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT', + 'VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK', + 'VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT', + 'VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT_MASK', + 'VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT__SHIFT', + 'VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK', + 'VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT', + 'VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK', + 'VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT', + 'VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK', + 'VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT', + 'VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK', + 'VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT', + 'VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK', + 'VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT', + 'VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK', + 'VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT', + 'VGT_TF_MEMORY_BASE__BASE_MASK', + 'VGT_TF_MEMORY_BASE__BASE__SHIFT', + 'VGT_TF_PARAM__DETECT_ONE_MASK', + 'VGT_TF_PARAM__DETECT_ONE__SHIFT', + 'VGT_TF_PARAM__DETECT_ZERO_MASK', + 'VGT_TF_PARAM__DETECT_ZERO__SHIFT', + 'VGT_TF_PARAM__DISABLE_DONUTS_MASK', + 'VGT_TF_PARAM__DISABLE_DONUTS__SHIFT', + 'VGT_TF_PARAM__DISTRIBUTION_MODE_MASK', + 'VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT', + 'VGT_TF_PARAM__MTYPE_MASK', 'VGT_TF_PARAM__MTYPE__SHIFT', + 'VGT_TF_PARAM__NOT_USED_MASK', 'VGT_TF_PARAM__NOT_USED__SHIFT', + 'VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK', + 'VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT', + 'VGT_TF_PARAM__PARTITIONING_MASK', + 'VGT_TF_PARAM__PARTITIONING__SHIFT', + 'VGT_TF_PARAM__RDREQ_POLICY_MASK', + 'VGT_TF_PARAM__RDREQ_POLICY__SHIFT', + 'VGT_TF_PARAM__TOPOLOGY_MASK', 'VGT_TF_PARAM__TOPOLOGY__SHIFT', + 'VGT_TF_PARAM__TYPE_MASK', 'VGT_TF_PARAM__TYPE__SHIFT', + 'VGT_TF_RING_SIZE__SIZE_MASK', 'VGT_TF_RING_SIZE__SIZE__SHIFT', + 'VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK', + 'VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT', + 'VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK', + 'VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT', + 'VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK', + 'VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT', + 'WD_CNTL_STATUS__DIST_BE_BUSY_MASK', + 'WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT', + 'WD_CNTL_STATUS__DIST_BUSY_MASK', + 'WD_CNTL_STATUS__DIST_BUSY__SHIFT', + 'WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK', + 'WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT', + 'WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK', + 'WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT', + 'WD_CNTL_STATUS__WD_TE11_BUSY_MASK', + 'WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT', + 'WD_CNTL_STATUS__WLC_BUSY_MASK', + 'WD_CNTL_STATUS__WLC_BUSY__SHIFT', 'WD_ENHANCE__MISC_MASK', + 'WD_ENHANCE__MISC__SHIFT', 'WD_QOS__DRAW_STALL_MASK', + 'WD_QOS__DRAW_STALL__SHIFT', 'WD_UTCL1_CNTL__BYPASS_MASK', + 'WD_UTCL1_CNTL__BYPASS__SHIFT', 'WD_UTCL1_CNTL__DROP_MODE_MASK', + 'WD_UTCL1_CNTL__DROP_MODE__SHIFT', + 'WD_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'WD_UTCL1_CNTL__INVALIDATE_MASK', + 'WD_UTCL1_CNTL__INVALIDATE__SHIFT', + 'WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK', + 'WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT', + 'WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK', + 'WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT', + 'WD_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'WD_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'WD_UTCL1_STATUS__PRT_DETECTED_MASK', + 'WD_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'WD_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'WD_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + '_gc_11_0_0_OFFSET_HEADER', '_gc_11_0_0_SH_MASK_HEADER', + 'ixFIXED_PATTERN_PERF_COUNTER_1', + 'ixFIXED_PATTERN_PERF_COUNTER_10', + 'ixFIXED_PATTERN_PERF_COUNTER_2', + 'ixFIXED_PATTERN_PERF_COUNTER_3', + 'ixFIXED_PATTERN_PERF_COUNTER_4', + 'ixFIXED_PATTERN_PERF_COUNTER_5', + 'ixFIXED_PATTERN_PERF_COUNTER_6', + 'ixFIXED_PATTERN_PERF_COUNTER_7', + 'ixFIXED_PATTERN_PERF_COUNTER_8', + 'ixFIXED_PATTERN_PERF_COUNTER_9', 'ixGC_CAC_ACC_CHC0', + 'ixGC_CAC_ACC_CHC1', 'ixGC_CAC_ACC_CHC2', 'ixGC_CAC_ACC_CP0', + 'ixGC_CAC_ACC_CP1', 'ixGC_CAC_ACC_CP2', 'ixGC_CAC_ACC_EA0', + 'ixGC_CAC_ACC_EA1', 'ixGC_CAC_ACC_EA2', 'ixGC_CAC_ACC_EA3', + 'ixGC_CAC_ACC_EA4', 'ixGC_CAC_ACC_EA5', 'ixGC_CAC_ACC_GDS0', + 'ixGC_CAC_ACC_GDS1', 'ixGC_CAC_ACC_GDS2', 'ixGC_CAC_ACC_GDS3', + 'ixGC_CAC_ACC_GDS4', 'ixGC_CAC_ACC_GE0', 'ixGC_CAC_ACC_GE1', + 'ixGC_CAC_ACC_GE10', 'ixGC_CAC_ACC_GE11', 'ixGC_CAC_ACC_GE12', + 'ixGC_CAC_ACC_GE13', 'ixGC_CAC_ACC_GE14', 'ixGC_CAC_ACC_GE15', + 'ixGC_CAC_ACC_GE16', 'ixGC_CAC_ACC_GE17', 'ixGC_CAC_ACC_GE18', + 'ixGC_CAC_ACC_GE19', 'ixGC_CAC_ACC_GE2', 'ixGC_CAC_ACC_GE20', + 'ixGC_CAC_ACC_GE3', 'ixGC_CAC_ACC_GE4', 'ixGC_CAC_ACC_GE5', + 'ixGC_CAC_ACC_GE6', 'ixGC_CAC_ACC_GE7', 'ixGC_CAC_ACC_GE8', + 'ixGC_CAC_ACC_GE9', 'ixGC_CAC_ACC_GL2C0', 'ixGC_CAC_ACC_GL2C1', + 'ixGC_CAC_ACC_GL2C2', 'ixGC_CAC_ACC_GL2C3', 'ixGC_CAC_ACC_GL2C4', + 'ixGC_CAC_ACC_GUS0', 'ixGC_CAC_ACC_GUS1', 'ixGC_CAC_ACC_GUS2', + 'ixGC_CAC_ACC_PH0', 'ixGC_CAC_ACC_PH1', 'ixGC_CAC_ACC_PH2', + 'ixGC_CAC_ACC_PH3', 'ixGC_CAC_ACC_PH4', 'ixGC_CAC_ACC_PH5', + 'ixGC_CAC_ACC_PH6', 'ixGC_CAC_ACC_PH7', 'ixGC_CAC_ACC_PMM0', + 'ixGC_CAC_ACC_RLC0', 'ixGC_CAC_ACC_SDMA0', 'ixGC_CAC_ACC_SDMA1', + 'ixGC_CAC_ACC_SDMA10', 'ixGC_CAC_ACC_SDMA11', + 'ixGC_CAC_ACC_SDMA2', 'ixGC_CAC_ACC_SDMA3', 'ixGC_CAC_ACC_SDMA4', + 'ixGC_CAC_ACC_SDMA5', 'ixGC_CAC_ACC_SDMA6', 'ixGC_CAC_ACC_SDMA7', + 'ixGC_CAC_ACC_SDMA8', 'ixGC_CAC_ACC_SDMA9', + 'ixGC_CAC_ACC_UTCL2_ROUTER0', 'ixGC_CAC_ACC_UTCL2_ROUTER1', + 'ixGC_CAC_ACC_UTCL2_ROUTER2', 'ixGC_CAC_ACC_UTCL2_ROUTER3', + 'ixGC_CAC_ACC_UTCL2_ROUTER4', 'ixGC_CAC_ACC_UTCL2_ROUTER5', + 'ixGC_CAC_ACC_UTCL2_ROUTER6', 'ixGC_CAC_ACC_UTCL2_ROUTER7', + 'ixGC_CAC_ACC_UTCL2_ROUTER8', 'ixGC_CAC_ACC_UTCL2_ROUTER9', + 'ixGC_CAC_ACC_UTCL2_VML20', 'ixGC_CAC_ACC_UTCL2_VML21', + 'ixGC_CAC_ACC_UTCL2_VML22', 'ixGC_CAC_ACC_UTCL2_VML23', + 'ixGC_CAC_ACC_UTCL2_VML24', 'ixGC_CAC_ACC_UTCL2_WALKER0', + 'ixGC_CAC_ACC_UTCL2_WALKER1', 'ixGC_CAC_ACC_UTCL2_WALKER2', + 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'regCB_PERFCOUNTER1_SELECT', + 'regCB_PERFCOUNTER1_SELECT_BASE_IDX', 'regCB_PERFCOUNTER2_HI', + 'regCB_PERFCOUNTER2_HI_BASE_IDX', 'regCB_PERFCOUNTER2_LO', + 'regCB_PERFCOUNTER2_LO_BASE_IDX', 'regCB_PERFCOUNTER2_SELECT', + 'regCB_PERFCOUNTER2_SELECT_BASE_IDX', 'regCB_PERFCOUNTER3_HI', + 'regCB_PERFCOUNTER3_HI_BASE_IDX', 'regCB_PERFCOUNTER3_LO', + 'regCB_PERFCOUNTER3_LO_BASE_IDX', 'regCB_PERFCOUNTER3_SELECT', + 'regCB_PERFCOUNTER3_SELECT_BASE_IDX', 'regCB_PERFCOUNTER_FILTER', + 'regCB_PERFCOUNTER_FILTER_BASE_IDX', + 'regCB_RMI_GL2_CACHE_CONTROL', + 'regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'regCB_SHADER_MASK', + 'regCB_SHADER_MASK_BASE_IDX', 'regCB_TARGET_MASK', + 'regCB_TARGET_MASK_BASE_IDX', 'regCC_GC_EDC_CONFIG', + 'regCC_GC_EDC_CONFIG_BASE_IDX', 'regCC_GC_PRIM_CONFIG', + 'regCC_GC_PRIM_CONFIG_BASE_IDX', 'regCC_GC_SA_UNIT_DISABLE', + 'regCC_GC_SA_UNIT_DISABLE_BASE_IDX', + 'regCC_GC_SHADER_ARRAY_CONFIG', + 'regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX', + 'regCC_GC_SHADER_RATE_CONFIG', + 'regCC_GC_SHADER_RATE_CONFIG_BASE_IDX', + 'regCC_RB_BACKEND_DISABLE', 'regCC_RB_BACKEND_DISABLE_BASE_IDX', + 'regCC_RB_DAISY_CHAIN', 'regCC_RB_DAISY_CHAIN_BASE_IDX', + 'regCC_RB_REDUNDANCY', 'regCC_RB_REDUNDANCY_BASE_IDX', + 'regCC_RMI_REDUNDANCY', 'regCC_RMI_REDUNDANCY_BASE_IDX', + 'regCGTS_TCC_DISABLE', 'regCGTS_TCC_DISABLE_BASE_IDX', + 'regCGTS_USER_TCC_DISABLE', 'regCGTS_USER_TCC_DISABLE_BASE_IDX', + 'regCGTT_CPC_CLK_CTRL', 'regCGTT_CPC_CLK_CTRL_BASE_IDX', + 'regCGTT_CPF_CLK_CTRL', 'regCGTT_CPF_CLK_CTRL_BASE_IDX', + 'regCGTT_CP_CLK_CTRL', 'regCGTT_CP_CLK_CTRL_BASE_IDX', + 'regCGTT_GS_NGG_CLK_CTRL', 'regCGTT_GS_NGG_CLK_CTRL_BASE_IDX', + 'regCGTT_PA_CLK_CTRL', 'regCGTT_PA_CLK_CTRL_BASE_IDX', + 'regCGTT_PH_CLK_CTRL0', 'regCGTT_PH_CLK_CTRL0_BASE_IDX', + 'regCGTT_PH_CLK_CTRL1', 'regCGTT_PH_CLK_CTRL1_BASE_IDX', + 'regCGTT_PH_CLK_CTRL2', 'regCGTT_PH_CLK_CTRL2_BASE_IDX', + 'regCGTT_PH_CLK_CTRL3', 'regCGTT_PH_CLK_CTRL3_BASE_IDX', + 'regCGTT_RLC_CLK_CTRL', 'regCGTT_RLC_CLK_CTRL_BASE_IDX', + 'regCGTT_SC_CLK_CTRL0', 'regCGTT_SC_CLK_CTRL0_BASE_IDX', + 'regCGTT_SC_CLK_CTRL1', 'regCGTT_SC_CLK_CTRL1_BASE_IDX', + 'regCGTT_SC_CLK_CTRL2', 'regCGTT_SC_CLK_CTRL2_BASE_IDX', + 'regCGTT_SC_CLK_CTRL3', 'regCGTT_SC_CLK_CTRL3_BASE_IDX', + 'regCGTT_SC_CLK_CTRL4', 'regCGTT_SC_CLK_CTRL4_BASE_IDX', + 'regCGTT_SQG_CLK_CTRL', 'regCGTT_SQG_CLK_CTRL_BASE_IDX', + 'regCHA_CHC_CREDITS', 'regCHA_CHC_CREDITS_BASE_IDX', + 'regCHA_CLIENT_FREE_DELAY', 'regCHA_CLIENT_FREE_DELAY_BASE_IDX', + 'regCHA_PERFCOUNTER0_HI', 'regCHA_PERFCOUNTER0_HI_BASE_IDX', + 'regCHA_PERFCOUNTER0_LO', 'regCHA_PERFCOUNTER0_LO_BASE_IDX', + 'regCHA_PERFCOUNTER0_SELECT', 'regCHA_PERFCOUNTER0_SELECT1', + 'regCHA_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER1_HI', + 'regCHA_PERFCOUNTER1_HI_BASE_IDX', 'regCHA_PERFCOUNTER1_LO', + 'regCHA_PERFCOUNTER1_LO_BASE_IDX', 'regCHA_PERFCOUNTER1_SELECT', + 'regCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER2_HI', + 'regCHA_PERFCOUNTER2_HI_BASE_IDX', 'regCHA_PERFCOUNTER2_LO', + 'regCHA_PERFCOUNTER2_LO_BASE_IDX', 'regCHA_PERFCOUNTER2_SELECT', + 'regCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER3_HI', + 'regCHA_PERFCOUNTER3_HI_BASE_IDX', 'regCHA_PERFCOUNTER3_LO', + 'regCHA_PERFCOUNTER3_LO_BASE_IDX', 'regCHA_PERFCOUNTER3_SELECT', + 'regCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_CTRL', + 'regCHCG_CTRL_BASE_IDX', 'regCHCG_PERFCOUNTER0_HI', + 'regCHCG_PERFCOUNTER0_HI_BASE_IDX', 'regCHCG_PERFCOUNTER0_LO', + 'regCHCG_PERFCOUNTER0_LO_BASE_IDX', 'regCHCG_PERFCOUNTER0_SELECT', + 'regCHCG_PERFCOUNTER0_SELECT1', + 'regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER1_HI', + 'regCHCG_PERFCOUNTER1_HI_BASE_IDX', 'regCHCG_PERFCOUNTER1_LO', + 'regCHCG_PERFCOUNTER1_LO_BASE_IDX', 'regCHCG_PERFCOUNTER1_SELECT', + 'regCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER2_HI', + 'regCHCG_PERFCOUNTER2_HI_BASE_IDX', 'regCHCG_PERFCOUNTER2_LO', + 'regCHCG_PERFCOUNTER2_LO_BASE_IDX', 'regCHCG_PERFCOUNTER2_SELECT', + 'regCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER3_HI', + 'regCHCG_PERFCOUNTER3_HI_BASE_IDX', 'regCHCG_PERFCOUNTER3_LO', + 'regCHCG_PERFCOUNTER3_LO_BASE_IDX', 'regCHCG_PERFCOUNTER3_SELECT', + 'regCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_STATUS', + 'regCHCG_STATUS_BASE_IDX', 'regCHC_CTRL', 'regCHC_CTRL_BASE_IDX', + 'regCHC_PERFCOUNTER0_HI', 'regCHC_PERFCOUNTER0_HI_BASE_IDX', + 'regCHC_PERFCOUNTER0_LO', 'regCHC_PERFCOUNTER0_LO_BASE_IDX', + 'regCHC_PERFCOUNTER0_SELECT', 'regCHC_PERFCOUNTER0_SELECT1', + 'regCHC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER1_HI', + 'regCHC_PERFCOUNTER1_HI_BASE_IDX', 'regCHC_PERFCOUNTER1_LO', + 'regCHC_PERFCOUNTER1_LO_BASE_IDX', 'regCHC_PERFCOUNTER1_SELECT', + 'regCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER2_HI', + 'regCHC_PERFCOUNTER2_HI_BASE_IDX', 'regCHC_PERFCOUNTER2_LO', + 'regCHC_PERFCOUNTER2_LO_BASE_IDX', 'regCHC_PERFCOUNTER2_SELECT', + 'regCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER3_HI', + 'regCHC_PERFCOUNTER3_HI_BASE_IDX', 'regCHC_PERFCOUNTER3_LO', + 'regCHC_PERFCOUNTER3_LO_BASE_IDX', 'regCHC_PERFCOUNTER3_SELECT', + 'regCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHC_STATUS', + 'regCHC_STATUS_BASE_IDX', 'regCHICKEN_BITS', + 'regCHICKEN_BITS_BASE_IDX', 'regCHI_CHR_MGCG_OVERRIDE', + 'regCHI_CHR_MGCG_OVERRIDE_BASE_IDX', + 'regCHI_CHR_REP_FGCG_OVERRIDE', + 'regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX', 'regCH_ARB_CTRL', + 'regCH_ARB_CTRL_BASE_IDX', 'regCH_ARB_STATUS', + 'regCH_ARB_STATUS_BASE_IDX', 'regCH_DRAM_BURST_CTRL', + 'regCH_DRAM_BURST_CTRL_BASE_IDX', 'regCH_DRAM_BURST_MASK', + 'regCH_DRAM_BURST_MASK_BASE_IDX', 'regCH_PIPE_STEER', + 'regCH_PIPE_STEER_BASE_IDX', 'regCH_VC5_ENABLE', + 'regCH_VC5_ENABLE_BASE_IDX', 'regCOHER_DEST_BASE_0', + 'regCOHER_DEST_BASE_0_BASE_IDX', 'regCOHER_DEST_BASE_1', + 'regCOHER_DEST_BASE_1_BASE_IDX', 'regCOHER_DEST_BASE_2', + 'regCOHER_DEST_BASE_2_BASE_IDX', 'regCOHER_DEST_BASE_3', + 'regCOHER_DEST_BASE_3_BASE_IDX', 'regCOHER_DEST_BASE_HI_0', + 'regCOHER_DEST_BASE_HI_0_BASE_IDX', 'regCOHER_DEST_BASE_HI_1', + 'regCOHER_DEST_BASE_HI_1_BASE_IDX', 'regCOHER_DEST_BASE_HI_2', + 'regCOHER_DEST_BASE_HI_2_BASE_IDX', 'regCOHER_DEST_BASE_HI_3', + 'regCOHER_DEST_BASE_HI_3_BASE_IDX', 'regCOMPUTE_DDID_INDEX', + 'regCOMPUTE_DDID_INDEX_BASE_IDX', 'regCOMPUTE_DESTINATION_EN_SE0', + 'regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX', + 'regCOMPUTE_DESTINATION_EN_SE1', + 'regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX', + 'regCOMPUTE_DESTINATION_EN_SE2', + 'regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX', + 'regCOMPUTE_DESTINATION_EN_SE3', + 'regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'regCOMPUTE_DIM_X', + 'regCOMPUTE_DIM_X_BASE_IDX', 'regCOMPUTE_DIM_Y', + 'regCOMPUTE_DIM_Y_BASE_IDX', 'regCOMPUTE_DIM_Z', + 'regCOMPUTE_DIM_Z_BASE_IDX', 'regCOMPUTE_DISPATCH_END', + 'regCOMPUTE_DISPATCH_END_BASE_IDX', 'regCOMPUTE_DISPATCH_ID', + 'regCOMPUTE_DISPATCH_ID_BASE_IDX', + 'regCOMPUTE_DISPATCH_INITIATOR', + 'regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX', + 'regCOMPUTE_DISPATCH_INTERLEAVE', + 'regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX', + 'regCOMPUTE_DISPATCH_PKT_ADDR_HI', + 'regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX', + 'regCOMPUTE_DISPATCH_PKT_ADDR_LO', + 'regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX', + 'regCOMPUTE_DISPATCH_TUNNEL', + 'regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX', 'regCOMPUTE_MISC_RESERVED', + 'regCOMPUTE_MISC_RESERVED_BASE_IDX', 'regCOMPUTE_NOWHERE', + 'regCOMPUTE_NOWHERE_BASE_IDX', 'regCOMPUTE_NUM_THREAD_X', + 'regCOMPUTE_NUM_THREAD_X_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Y', + 'regCOMPUTE_NUM_THREAD_Y_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Z', + 'regCOMPUTE_NUM_THREAD_Z_BASE_IDX', 'regCOMPUTE_PERFCOUNT_ENABLE', + 'regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'regCOMPUTE_PGM_HI', + 'regCOMPUTE_PGM_HI_BASE_IDX', 'regCOMPUTE_PGM_LO', + 'regCOMPUTE_PGM_LO_BASE_IDX', 'regCOMPUTE_PGM_RSRC1', + 'regCOMPUTE_PGM_RSRC1_BASE_IDX', 'regCOMPUTE_PGM_RSRC2', + 'regCOMPUTE_PGM_RSRC2_BASE_IDX', 'regCOMPUTE_PGM_RSRC3', + 'regCOMPUTE_PGM_RSRC3_BASE_IDX', 'regCOMPUTE_PIPELINESTAT_ENABLE', + 'regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'regCOMPUTE_RELAUNCH', + 'regCOMPUTE_RELAUNCH2', 'regCOMPUTE_RELAUNCH2_BASE_IDX', + 'regCOMPUTE_RELAUNCH_BASE_IDX', 'regCOMPUTE_REQ_CTRL', + 'regCOMPUTE_REQ_CTRL_BASE_IDX', 'regCOMPUTE_RESOURCE_LIMITS', + 'regCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'regCOMPUTE_RESTART_X', + 'regCOMPUTE_RESTART_X_BASE_IDX', 'regCOMPUTE_RESTART_Y', + 'regCOMPUTE_RESTART_Y_BASE_IDX', 'regCOMPUTE_RESTART_Z', + 'regCOMPUTE_RESTART_Z_BASE_IDX', 'regCOMPUTE_SHADER_CHKSUM', + 'regCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'regCOMPUTE_START_X', + 'regCOMPUTE_START_X_BASE_IDX', 'regCOMPUTE_START_Y', + 'regCOMPUTE_START_Y_BASE_IDX', 'regCOMPUTE_START_Z', + 'regCOMPUTE_START_Z_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE0', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE1', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE2', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE3', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE4', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE5', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE6', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE7', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX', + 'regCOMPUTE_THREADGROUP_ID', 'regCOMPUTE_THREADGROUP_ID_BASE_IDX', + 'regCOMPUTE_THREAD_TRACE_ENABLE', + 'regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX', + 'regCOMPUTE_TMPRING_SIZE', 'regCOMPUTE_TMPRING_SIZE_BASE_IDX', + 'regCOMPUTE_USER_ACCUM_0', 'regCOMPUTE_USER_ACCUM_0_BASE_IDX', + 'regCOMPUTE_USER_ACCUM_1', 'regCOMPUTE_USER_ACCUM_1_BASE_IDX', + 'regCOMPUTE_USER_ACCUM_2', 'regCOMPUTE_USER_ACCUM_2_BASE_IDX', + 'regCOMPUTE_USER_ACCUM_3', 'regCOMPUTE_USER_ACCUM_3_BASE_IDX', + 'regCOMPUTE_USER_DATA_0', 'regCOMPUTE_USER_DATA_0_BASE_IDX', + 'regCOMPUTE_USER_DATA_1', 'regCOMPUTE_USER_DATA_10', + 'regCOMPUTE_USER_DATA_10_BASE_IDX', 'regCOMPUTE_USER_DATA_11', + 'regCOMPUTE_USER_DATA_11_BASE_IDX', 'regCOMPUTE_USER_DATA_12', + 'regCOMPUTE_USER_DATA_12_BASE_IDX', 'regCOMPUTE_USER_DATA_13', + 'regCOMPUTE_USER_DATA_13_BASE_IDX', 'regCOMPUTE_USER_DATA_14', + 'regCOMPUTE_USER_DATA_14_BASE_IDX', 'regCOMPUTE_USER_DATA_15', + 'regCOMPUTE_USER_DATA_15_BASE_IDX', + 'regCOMPUTE_USER_DATA_1_BASE_IDX', 'regCOMPUTE_USER_DATA_2', + 'regCOMPUTE_USER_DATA_2_BASE_IDX', 'regCOMPUTE_USER_DATA_3', + 'regCOMPUTE_USER_DATA_3_BASE_IDX', 'regCOMPUTE_USER_DATA_4', + 'regCOMPUTE_USER_DATA_4_BASE_IDX', 'regCOMPUTE_USER_DATA_5', + 'regCOMPUTE_USER_DATA_5_BASE_IDX', 'regCOMPUTE_USER_DATA_6', + 'regCOMPUTE_USER_DATA_6_BASE_IDX', 'regCOMPUTE_USER_DATA_7', + 'regCOMPUTE_USER_DATA_7_BASE_IDX', 'regCOMPUTE_USER_DATA_8', + 'regCOMPUTE_USER_DATA_8_BASE_IDX', 'regCOMPUTE_USER_DATA_9', + 'regCOMPUTE_USER_DATA_9_BASE_IDX', 'regCOMPUTE_VMID', + 'regCOMPUTE_VMID_BASE_IDX', 'regCOMPUTE_WAVE_RESTORE_ADDR_HI', + 'regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX', + 'regCOMPUTE_WAVE_RESTORE_ADDR_LO', + 'regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX', + 'regCONFIG_RESERVED_REG0', 'regCONFIG_RESERVED_REG0_BASE_IDX', + 'regCONFIG_RESERVED_REG1', 'regCONFIG_RESERVED_REG1_BASE_IDX', + 'regCONTEXT_RESERVED_REG0', 'regCONTEXT_RESERVED_REG0_BASE_IDX', + 'regCONTEXT_RESERVED_REG1', 'regCONTEXT_RESERVED_REG1_BASE_IDX', + 'regCPC_DDID_BASE_ADDR_HI', 'regCPC_DDID_BASE_ADDR_HI_BASE_IDX', + 'regCPC_DDID_BASE_ADDR_LO', 'regCPC_DDID_BASE_ADDR_LO_BASE_IDX', + 'regCPC_DDID_CNTL', 'regCPC_DDID_CNTL_BASE_IDX', + 'regCPC_INT_ADDR', 'regCPC_INT_ADDR_BASE_IDX', 'regCPC_INT_CNTL', + 'regCPC_INT_CNTL_BASE_IDX', 'regCPC_INT_CNTX_ID', + 'regCPC_INT_CNTX_ID_BASE_IDX', 'regCPC_INT_INFO', + 'regCPC_INT_INFO_BASE_IDX', 'regCPC_INT_PASID', + 'regCPC_INT_PASID_BASE_IDX', 'regCPC_INT_STATUS', + 'regCPC_INT_STATUS_BASE_IDX', 'regCPC_LATENCY_STATS_DATA', + 'regCPC_LATENCY_STATS_DATA_BASE_IDX', + 'regCPC_LATENCY_STATS_SELECT', + 'regCPC_LATENCY_STATS_SELECT_BASE_IDX', 'regCPC_OS_PIPES', + 'regCPC_OS_PIPES_BASE_IDX', 'regCPC_PERFCOUNTER0_HI', + 'regCPC_PERFCOUNTER0_HI_BASE_IDX', 'regCPC_PERFCOUNTER0_LO', + 'regCPC_PERFCOUNTER0_LO_BASE_IDX', 'regCPC_PERFCOUNTER0_SELECT', + 'regCPC_PERFCOUNTER0_SELECT1', + 'regCPC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPC_PERFCOUNTER1_HI', + 'regCPC_PERFCOUNTER1_HI_BASE_IDX', 'regCPC_PERFCOUNTER1_LO', + 'regCPC_PERFCOUNTER1_LO_BASE_IDX', 'regCPC_PERFCOUNTER1_SELECT', + 'regCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPC_PSP_DEBUG', + 'regCPC_PSP_DEBUG_BASE_IDX', 'regCPC_SUSPEND_CNTL_STACK_OFFSET', + 'regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', + 'regCPC_SUSPEND_CNTL_STACK_SIZE', + 'regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX', + 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI', + 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', + 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO', + 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', + 'regCPC_SUSPEND_CTX_SAVE_CONTROL', + 'regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX', + 'regCPC_SUSPEND_CTX_SAVE_SIZE', + 'regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX', + 'regCPC_SUSPEND_WG_STATE_OFFSET', + 'regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX', + 'regCPC_TC_PERF_COUNTER_WINDOW_SELECT', + 'regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', + 'regCPC_UTCL1_CNTL', 'regCPC_UTCL1_CNTL_BASE_IDX', + 'regCPC_UTCL1_ERROR', 'regCPC_UTCL1_ERROR_BASE_IDX', + 'regCPC_UTCL1_STATUS', 'regCPC_UTCL1_STATUS_BASE_IDX', + 'regCPF_GCR_CNTL', 'regCPF_GCR_CNTL_BASE_IDX', + 'regCPF_LATENCY_STATS_DATA', 'regCPF_LATENCY_STATS_DATA_BASE_IDX', + 'regCPF_LATENCY_STATS_SELECT', + 'regCPF_LATENCY_STATS_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER0_HI', + 'regCPF_PERFCOUNTER0_HI_BASE_IDX', 'regCPF_PERFCOUNTER0_LO', + 'regCPF_PERFCOUNTER0_LO_BASE_IDX', 'regCPF_PERFCOUNTER0_SELECT', + 'regCPF_PERFCOUNTER0_SELECT1', + 'regCPF_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER1_HI', + 'regCPF_PERFCOUNTER1_HI_BASE_IDX', 'regCPF_PERFCOUNTER1_LO', + 'regCPF_PERFCOUNTER1_LO_BASE_IDX', 'regCPF_PERFCOUNTER1_SELECT', + 'regCPF_PERFCOUNTER1_SELECT_BASE_IDX', + 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT', + 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', + 'regCPF_UTCL1_CNTL', 'regCPF_UTCL1_CNTL_BASE_IDX', + 'regCPF_UTCL1_STATUS', 'regCPF_UTCL1_STATUS_BASE_IDX', + 'regCPG_LATENCY_STATS_DATA', 'regCPG_LATENCY_STATS_DATA_BASE_IDX', + 'regCPG_LATENCY_STATS_SELECT', + 'regCPG_LATENCY_STATS_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER0_HI', + 'regCPG_PERFCOUNTER0_HI_BASE_IDX', 'regCPG_PERFCOUNTER0_LO', + 'regCPG_PERFCOUNTER0_LO_BASE_IDX', 'regCPG_PERFCOUNTER0_SELECT', + 'regCPG_PERFCOUNTER0_SELECT1', + 'regCPG_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER1_HI', + 'regCPG_PERFCOUNTER1_HI_BASE_IDX', 'regCPG_PERFCOUNTER1_LO', + 'regCPG_PERFCOUNTER1_LO_BASE_IDX', 'regCPG_PERFCOUNTER1_SELECT', + 'regCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPG_PSP_DEBUG', + 'regCPG_PSP_DEBUG_BASE_IDX', 'regCPG_RCIU_CAM_DATA', + 'regCPG_RCIU_CAM_DATA_BASE_IDX', 'regCPG_RCIU_CAM_DATA_PHASE0', + 'regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX', + 'regCPG_RCIU_CAM_DATA_PHASE1', + 'regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX', + 'regCPG_RCIU_CAM_DATA_PHASE2', + 'regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'regCPG_RCIU_CAM_INDEX', + 'regCPG_RCIU_CAM_INDEX_BASE_IDX', + 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT', + 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', + 'regCPG_UTCL1_CNTL', 'regCPG_UTCL1_CNTL_BASE_IDX', + 'regCPG_UTCL1_ERROR', 'regCPG_UTCL1_ERROR_BASE_IDX', + 'regCPG_UTCL1_STATUS', 'regCPG_UTCL1_STATUS_BASE_IDX', + 'regCP_APPEND_ADDR_HI', 'regCP_APPEND_ADDR_HI_BASE_IDX', + 'regCP_APPEND_ADDR_LO', 'regCP_APPEND_ADDR_LO_BASE_IDX', + 'regCP_APPEND_CMD_ADDR_HI', 'regCP_APPEND_CMD_ADDR_HI_BASE_IDX', + 'regCP_APPEND_CMD_ADDR_LO', 'regCP_APPEND_CMD_ADDR_LO_BASE_IDX', + 'regCP_APPEND_DATA', 'regCP_APPEND_DATA_BASE_IDX', + 'regCP_APPEND_DATA_HI', 'regCP_APPEND_DATA_HI_BASE_IDX', + 'regCP_APPEND_DATA_LO', 'regCP_APPEND_DATA_LO_BASE_IDX', + 'regCP_APPEND_DDID_CNT', 'regCP_APPEND_DDID_CNT_BASE_IDX', + 'regCP_APPEND_LAST_CS_FENCE', + 'regCP_APPEND_LAST_CS_FENCE_BASE_IDX', + 'regCP_APPEND_LAST_CS_FENCE_HI', + 'regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX', + 'regCP_APPEND_LAST_CS_FENCE_LO', + 'regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX', + 'regCP_APPEND_LAST_PS_FENCE', + 'regCP_APPEND_LAST_PS_FENCE_BASE_IDX', + 'regCP_APPEND_LAST_PS_FENCE_HI', + 'regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX', + 'regCP_APPEND_LAST_PS_FENCE_LO', + 'regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'regCP_AQL_SMM_STATUS', + 'regCP_AQL_SMM_STATUS_BASE_IDX', 'regCP_ATOMIC_PREOP_HI', + 'regCP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_ATOMIC_PREOP_LO', + 'regCP_ATOMIC_PREOP_LO_BASE_IDX', 'regCP_BUSY_STAT', + 'regCP_BUSY_STAT_BASE_IDX', 'regCP_CMD_DATA', + 'regCP_CMD_DATA_BASE_IDX', 'regCP_CMD_INDEX', + 'regCP_CMD_INDEX_BASE_IDX', 'regCP_CNTX_STAT', + 'regCP_CNTX_STAT_BASE_IDX', 'regCP_CONTEXT_CNTL', + 'regCP_CONTEXT_CNTL_BASE_IDX', 'regCP_CPC_BUSY_HYSTERESIS', + 'regCP_CPC_BUSY_HYSTERESIS_BASE_IDX', 'regCP_CPC_BUSY_STAT', + 'regCP_CPC_BUSY_STAT2', 'regCP_CPC_BUSY_STAT2_BASE_IDX', + 'regCP_CPC_BUSY_STAT_BASE_IDX', 'regCP_CPC_DEBUG', + 'regCP_CPC_DEBUG_BASE_IDX', 'regCP_CPC_DEBUG_CNTL', + 'regCP_CPC_DEBUG_CNTL_BASE_IDX', 'regCP_CPC_DEBUG_DATA', + 'regCP_CPC_DEBUG_DATA_BASE_IDX', 'regCP_CPC_GFX_CNTL', + 'regCP_CPC_GFX_CNTL_BASE_IDX', 'regCP_CPC_GRBM_FREE_COUNT', + 'regCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPC_HALT_HYST_COUNT', + 'regCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'regCP_CPC_IC_BASE_CNTL', + 'regCP_CPC_IC_BASE_CNTL_BASE_IDX', 'regCP_CPC_IC_BASE_HI', + 'regCP_CPC_IC_BASE_HI_BASE_IDX', 'regCP_CPC_IC_BASE_LO', + 'regCP_CPC_IC_BASE_LO_BASE_IDX', 'regCP_CPC_IC_OP_CNTL', + 'regCP_CPC_IC_OP_CNTL_BASE_IDX', 'regCP_CPC_MGCG_SYNC_CNTL', + 'regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX', + 'regCP_CPC_PRIV_VIOLATION_ADDR', + 'regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX', + 'regCP_CPC_SCRATCH_DATA', 'regCP_CPC_SCRATCH_DATA_BASE_IDX', + 'regCP_CPC_SCRATCH_INDEX', 'regCP_CPC_SCRATCH_INDEX_BASE_IDX', + 'regCP_CPC_STALLED_STAT1', 'regCP_CPC_STALLED_STAT1_BASE_IDX', + 'regCP_CPC_STATUS', 'regCP_CPC_STATUS_BASE_IDX', + 'regCP_CPF_BUSY_HYSTERESIS1', + 'regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX', + 'regCP_CPF_BUSY_HYSTERESIS2', + 'regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CPF_BUSY_STAT', + 'regCP_CPF_BUSY_STAT2', 'regCP_CPF_BUSY_STAT2_BASE_IDX', + 'regCP_CPF_BUSY_STAT_BASE_IDX', 'regCP_CPF_GRBM_FREE_COUNT', + 'regCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPF_STALLED_STAT1', + 'regCP_CPF_STALLED_STAT1_BASE_IDX', 'regCP_CPF_STATUS', + 'regCP_CPF_STATUS_BASE_IDX', 'regCP_CPG_BUSY_HYSTERESIS1', + 'regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX', + 'regCP_CPG_BUSY_HYSTERESIS2', + 'regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CSF_STAT', + 'regCP_CSF_STAT_BASE_IDX', 'regCP_CU_MASK_ADDR_HI', + 'regCP_CU_MASK_ADDR_HI_BASE_IDX', 'regCP_CU_MASK_ADDR_LO', + 'regCP_CU_MASK_ADDR_LO_BASE_IDX', 'regCP_CU_MASK_CNTL', + 'regCP_CU_MASK_CNTL_BASE_IDX', 'regCP_DB_BASE_HI', + 'regCP_DB_BASE_HI_BASE_IDX', 'regCP_DB_BASE_LO', + 'regCP_DB_BASE_LO_BASE_IDX', 'regCP_DB_BUFSZ', + 'regCP_DB_BUFSZ_BASE_IDX', 'regCP_DB_CMD_BUFSZ', + 'regCP_DB_CMD_BUFSZ_BASE_IDX', 'regCP_DDID_BASE_ADDR_HI', + 'regCP_DDID_BASE_ADDR_HI_BASE_IDX', 'regCP_DDID_BASE_ADDR_LO', + 'regCP_DDID_BASE_ADDR_LO_BASE_IDX', 'regCP_DDID_CNTL', + 'regCP_DDID_CNTL_BASE_IDX', 'regCP_DEBUG', 'regCP_DEBUG_2', + 'regCP_DEBUG_2_BASE_IDX', 'regCP_DEBUG_BASE_IDX', + 'regCP_DEBUG_CNTL', 'regCP_DEBUG_CNTL_BASE_IDX', + 'regCP_DEBUG_DATA', 'regCP_DEBUG_DATA_BASE_IDX', + 'regCP_DEVICE_ID', 'regCP_DEVICE_ID_BASE_IDX', + 'regCP_DISPATCH_INDR_ADDR', 'regCP_DISPATCH_INDR_ADDR_BASE_IDX', + 'regCP_DISPATCH_INDR_ADDR_HI', + 'regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'regCP_DMA_CNTL', + 'regCP_DMA_CNTL_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_HI', + 'regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_LO', + 'regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_ME_COMMAND', + 'regCP_DMA_ME_COMMAND_BASE_IDX', 'regCP_DMA_ME_CONTROL', + 'regCP_DMA_ME_CONTROL_BASE_IDX', 'regCP_DMA_ME_DST_ADDR', + 'regCP_DMA_ME_DST_ADDR_BASE_IDX', 'regCP_DMA_ME_DST_ADDR_HI', + 'regCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR', + 'regCP_DMA_ME_SRC_ADDR_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR_HI', + 'regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_HI', + 'regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_LO', + 'regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_PFP_COMMAND', + 'regCP_DMA_PFP_COMMAND_BASE_IDX', 'regCP_DMA_PFP_CONTROL', + 'regCP_DMA_PFP_CONTROL_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR', + 'regCP_DMA_PFP_DST_ADDR_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR_HI', + 'regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR', + 'regCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR_HI', + 'regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_READ_TAGS', + 'regCP_DMA_READ_TAGS_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_HI', + 'regCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_LO', + 'regCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH0_CNTL', + 'regCP_DMA_WATCH0_CNTL_BASE_IDX', 'regCP_DMA_WATCH0_MASK', + 'regCP_DMA_WATCH0_MASK_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_HI', + 'regCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_LO', + 'regCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH1_CNTL', + 'regCP_DMA_WATCH1_CNTL_BASE_IDX', 'regCP_DMA_WATCH1_MASK', + 'regCP_DMA_WATCH1_MASK_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_HI', + 'regCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_LO', + 'regCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH2_CNTL', + 'regCP_DMA_WATCH2_CNTL_BASE_IDX', 'regCP_DMA_WATCH2_MASK', + 'regCP_DMA_WATCH2_MASK_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_HI', + 'regCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_LO', + 'regCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH3_CNTL', + 'regCP_DMA_WATCH3_CNTL_BASE_IDX', 'regCP_DMA_WATCH3_MASK', + 'regCP_DMA_WATCH3_MASK_BASE_IDX', 'regCP_DMA_WATCH_STAT', + 'regCP_DMA_WATCH_STAT_ADDR_HI', + 'regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX', + 'regCP_DMA_WATCH_STAT_ADDR_LO', + 'regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX', + 'regCP_DMA_WATCH_STAT_BASE_IDX', 'regCP_DRAW_INDX_INDR_ADDR', + 'regCP_DRAW_INDX_INDR_ADDR_BASE_IDX', + 'regCP_DRAW_INDX_INDR_ADDR_HI', + 'regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'regCP_DRAW_OBJECT', + 'regCP_DRAW_OBJECT_BASE_IDX', 'regCP_DRAW_OBJECT_COUNTER', + 'regCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'regCP_DRAW_WINDOW_CNTL', + 'regCP_DRAW_WINDOW_CNTL_BASE_IDX', 'regCP_DRAW_WINDOW_HI', + 'regCP_DRAW_WINDOW_HI_BASE_IDX', 'regCP_DRAW_WINDOW_LO', + 'regCP_DRAW_WINDOW_LO_BASE_IDX', 'regCP_DRAW_WINDOW_MASK_HI', + 'regCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'regCP_ECC_FIRSTOCCURRENCE', + 'regCP_ECC_FIRSTOCCURRENCE_BASE_IDX', + 'regCP_ECC_FIRSTOCCURRENCE_RING0', + 'regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX', + 'regCP_ECC_FIRSTOCCURRENCE_RING1', + 'regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX', + 'regCP_EOPQ_WAIT_TIME', 'regCP_EOPQ_WAIT_TIME_BASE_IDX', + 'regCP_EOP_DONE_ADDR_HI', 'regCP_EOP_DONE_ADDR_HI_BASE_IDX', + 'regCP_EOP_DONE_ADDR_LO', 'regCP_EOP_DONE_ADDR_LO_BASE_IDX', + 'regCP_EOP_DONE_CNTX_ID', 'regCP_EOP_DONE_CNTX_ID_BASE_IDX', + 'regCP_EOP_DONE_DATA_CNTL', 'regCP_EOP_DONE_DATA_CNTL_BASE_IDX', + 'regCP_EOP_DONE_DATA_HI', 'regCP_EOP_DONE_DATA_HI_BASE_IDX', + 'regCP_EOP_DONE_DATA_LO', 'regCP_EOP_DONE_DATA_LO_BASE_IDX', + 'regCP_EOP_DONE_EVENT_CNTL', 'regCP_EOP_DONE_EVENT_CNTL_BASE_IDX', + 'regCP_EOP_LAST_FENCE_HI', 'regCP_EOP_LAST_FENCE_HI_BASE_IDX', + 'regCP_EOP_LAST_FENCE_LO', 'regCP_EOP_LAST_FENCE_LO_BASE_IDX', + 'regCP_FATAL_ERROR', 'regCP_FATAL_ERROR_BASE_IDX', + 'regCP_FETCHER_SOURCE', 'regCP_FETCHER_SOURCE_BASE_IDX', + 'regCP_GDS_ATOMIC0_PREOP_HI', + 'regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_GDS_ATOMIC0_PREOP_LO', + 'regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_GDS_ATOMIC1_PREOP_HI', + 'regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_GDS_ATOMIC1_PREOP_LO', + 'regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_GDS_BKUP_ADDR', + 'regCP_GDS_BKUP_ADDR_BASE_IDX', 'regCP_GDS_BKUP_ADDR_HI', + 'regCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_HI', + 'regCP_GE_MSINVOC_COUNT_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_LO', + 'regCP_GE_MSINVOC_COUNT_LO_BASE_IDX', 'regCP_GFX_CNTL', + 'regCP_GFX_CNTL_BASE_IDX', 'regCP_GFX_DDID_DELTA_RPT_COUNT', + 'regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX', + 'regCP_GFX_DDID_INFLIGHT_COUNT', + 'regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_GFX_DDID_RPTR', + 'regCP_GFX_DDID_RPTR_BASE_IDX', 'regCP_GFX_DDID_WPTR', + 'regCP_GFX_DDID_WPTR_BASE_IDX', 'regCP_GFX_ERROR', + 'regCP_GFX_ERROR_BASE_IDX', 'regCP_GFX_HPD_CONTROL0', + 'regCP_GFX_HPD_CONTROL0_BASE_IDX', + 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI', + 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX', + 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO', + 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX', + 'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI', + 'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX', + 'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO', + 'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX', + 'regCP_GFX_HPD_STATUS0', 'regCP_GFX_HPD_STATUS0_BASE_IDX', + 'regCP_GFX_HQD_ACTIVE', 'regCP_GFX_HQD_ACTIVE_BASE_IDX', + 'regCP_GFX_HQD_BASE', 'regCP_GFX_HQD_BASE_BASE_IDX', + 'regCP_GFX_HQD_BASE_HI', 'regCP_GFX_HQD_BASE_HI_BASE_IDX', + 'regCP_GFX_HQD_CNTL', 'regCP_GFX_HQD_CNTL_BASE_IDX', + 'regCP_GFX_HQD_CSMD_RPTR', 'regCP_GFX_HQD_CSMD_RPTR_BASE_IDX', + 'regCP_GFX_HQD_DEQUEUE_REQUEST', + 'regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX', + 'regCP_GFX_HQD_HQ_CONTROL0', 'regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX', + 'regCP_GFX_HQD_HQ_STATUS0', 'regCP_GFX_HQD_HQ_STATUS0_BASE_IDX', + 'regCP_GFX_HQD_IQ_TIMER', 'regCP_GFX_HQD_IQ_TIMER_BASE_IDX', + 'regCP_GFX_HQD_MAPPED', 'regCP_GFX_HQD_MAPPED_BASE_IDX', + 'regCP_GFX_HQD_OFFSET', 'regCP_GFX_HQD_OFFSET_BASE_IDX', + 'regCP_GFX_HQD_QUANTUM', 'regCP_GFX_HQD_QUANTUM_BASE_IDX', + 'regCP_GFX_HQD_QUEUE_PRIORITY', + 'regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX', + 'regCP_GFX_HQD_QUE_MGR_CONTROL', + 'regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'regCP_GFX_HQD_RPTR', + 'regCP_GFX_HQD_RPTR_ADDR', 'regCP_GFX_HQD_RPTR_ADDR_BASE_IDX', + 'regCP_GFX_HQD_RPTR_ADDR_HI', + 'regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX', + 'regCP_GFX_HQD_RPTR_BASE_IDX', 'regCP_GFX_HQD_VMID', + 'regCP_GFX_HQD_VMID_BASE_IDX', 'regCP_GFX_HQD_WPTR', + 'regCP_GFX_HQD_WPTR_BASE_IDX', 'regCP_GFX_HQD_WPTR_HI', + 'regCP_GFX_HQD_WPTR_HI_BASE_IDX', 'regCP_GFX_INDEX_MUTEX', + 'regCP_GFX_INDEX_MUTEX_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR', + 'regCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR_HI', + 'regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_GFX_MQD_CONTROL', + 'regCP_GFX_MQD_CONTROL_BASE_IDX', 'regCP_GFX_QUEUE_INDEX', + 'regCP_GFX_QUEUE_INDEX_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE0_BASE0', + 'regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE0_BASE1', + 'regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE0_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE0_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE0_MASK0', + 'regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE0_MASK1', + 'regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE10_BASE0', + 'regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE10_BASE1', + 'regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE10_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE10_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE10_MASK0', + 'regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE10_MASK1', + 'regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE11_BASE0', + 'regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE11_BASE1', + 'regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE11_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE11_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE11_MASK0', + 'regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE11_MASK1', + 'regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE12_BASE0', + 'regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE12_BASE1', + 'regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE12_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE12_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE12_MASK0', + 'regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE12_MASK1', + 'regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE13_BASE0', + 'regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE13_BASE1', + 'regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE13_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE13_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE13_MASK0', + 'regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE13_MASK1', + 'regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE14_BASE0', + 'regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE14_BASE1', + 'regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE14_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE14_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE14_MASK0', + 'regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE14_MASK1', + 'regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE15_BASE0', + 'regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE15_BASE1', + 'regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE15_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE15_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE15_MASK0', + 'regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE15_MASK1', + 'regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE1_BASE0', + 'regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE1_BASE1', + 'regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE1_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE1_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE1_MASK0', + 'regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE1_MASK1', + 'regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE2_BASE0', + 'regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE2_BASE1', + 'regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE2_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE2_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE2_MASK0', + 'regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE2_MASK1', + 'regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE3_BASE0', + 'regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE3_BASE1', + 'regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE3_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE3_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE3_MASK0', + 'regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE3_MASK1', + 'regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE4_BASE0', + 'regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE4_BASE1', + 'regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE4_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE4_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE4_MASK0', + 'regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE4_MASK1', + 'regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE5_BASE0', + 'regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE5_BASE1', + 'regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE5_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE5_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE5_MASK0', + 'regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE5_MASK1', + 'regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE6_BASE0', + 'regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE6_BASE1', + 'regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE6_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE6_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE6_MASK0', + 'regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE6_MASK1', + 'regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE7_BASE0', + 'regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE7_BASE1', + 'regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE7_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE7_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE7_MASK0', + 'regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE7_MASK1', + 'regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE8_BASE0', + 'regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE8_BASE1', + 'regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE8_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE8_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE8_MASK0', + 'regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE8_MASK1', + 'regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE9_BASE0', + 'regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE9_BASE1', + 'regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE9_CNTL0', + 'regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE9_CNTL1', + 'regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE9_MASK0', + 'regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX', + 'regCP_GFX_RS64_DC_APERTURE9_MASK1', + 'regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX', + 'regCP_GFX_RS64_DC_BASE0_HI', + 'regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX', + 'regCP_GFX_RS64_DC_BASE0_LO', + 'regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX', + 'regCP_GFX_RS64_DC_BASE1_HI', + 'regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX', + 'regCP_GFX_RS64_DC_BASE1_LO', + 'regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX', + 'regCP_GFX_RS64_DC_BASE_CNTL', + 'regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX', + 'regCP_GFX_RS64_DC_OP_CNTL', 'regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX', + 'regCP_GFX_RS64_DM_INDEX_ADDR', + 'regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX', + 'regCP_GFX_RS64_DM_INDEX_DATA', + 'regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX', 'regCP_GFX_RS64_GP0_HI0', + 'regCP_GFX_RS64_GP0_HI0_BASE_IDX', 'regCP_GFX_RS64_GP0_HI1', + 'regCP_GFX_RS64_GP0_HI1_BASE_IDX', 'regCP_GFX_RS64_GP0_LO0', + 'regCP_GFX_RS64_GP0_LO0_BASE_IDX', 'regCP_GFX_RS64_GP0_LO1', + 'regCP_GFX_RS64_GP0_LO1_BASE_IDX', 'regCP_GFX_RS64_GP1_HI0', + 'regCP_GFX_RS64_GP1_HI0_BASE_IDX', 'regCP_GFX_RS64_GP1_HI1', + 'regCP_GFX_RS64_GP1_HI1_BASE_IDX', 'regCP_GFX_RS64_GP1_LO0', + 'regCP_GFX_RS64_GP1_LO0_BASE_IDX', 'regCP_GFX_RS64_GP1_LO1', + 'regCP_GFX_RS64_GP1_LO1_BASE_IDX', 'regCP_GFX_RS64_GP2_HI0', + 'regCP_GFX_RS64_GP2_HI0_BASE_IDX', 'regCP_GFX_RS64_GP2_HI1', + 'regCP_GFX_RS64_GP2_HI1_BASE_IDX', 'regCP_GFX_RS64_GP2_LO0', + 'regCP_GFX_RS64_GP2_LO0_BASE_IDX', 'regCP_GFX_RS64_GP2_LO1', + 'regCP_GFX_RS64_GP2_LO1_BASE_IDX', 'regCP_GFX_RS64_GP3_HI0', + 'regCP_GFX_RS64_GP3_HI0_BASE_IDX', 'regCP_GFX_RS64_GP3_HI1', + 'regCP_GFX_RS64_GP3_HI1_BASE_IDX', 'regCP_GFX_RS64_GP3_LO0', + 'regCP_GFX_RS64_GP3_LO0_BASE_IDX', 'regCP_GFX_RS64_GP3_LO1', + 'regCP_GFX_RS64_GP3_LO1_BASE_IDX', 'regCP_GFX_RS64_GP4_HI0', + 'regCP_GFX_RS64_GP4_HI0_BASE_IDX', 'regCP_GFX_RS64_GP4_HI1', + 'regCP_GFX_RS64_GP4_HI1_BASE_IDX', 'regCP_GFX_RS64_GP4_LO0', + 'regCP_GFX_RS64_GP4_LO0_BASE_IDX', 'regCP_GFX_RS64_GP4_LO1', + 'regCP_GFX_RS64_GP4_LO1_BASE_IDX', 'regCP_GFX_RS64_GP5_HI0', + 'regCP_GFX_RS64_GP5_HI0_BASE_IDX', 'regCP_GFX_RS64_GP5_HI1', + 'regCP_GFX_RS64_GP5_HI1_BASE_IDX', 'regCP_GFX_RS64_GP5_LO0', + 'regCP_GFX_RS64_GP5_LO0_BASE_IDX', 'regCP_GFX_RS64_GP5_LO1', + 'regCP_GFX_RS64_GP5_LO1_BASE_IDX', 'regCP_GFX_RS64_GP6_HI', + 'regCP_GFX_RS64_GP6_HI_BASE_IDX', 'regCP_GFX_RS64_GP6_LO', + 'regCP_GFX_RS64_GP6_LO_BASE_IDX', 'regCP_GFX_RS64_GP7_HI', + 'regCP_GFX_RS64_GP7_HI_BASE_IDX', 'regCP_GFX_RS64_GP7_LO', + 'regCP_GFX_RS64_GP7_LO_BASE_IDX', 'regCP_GFX_RS64_GP8_HI', + 'regCP_GFX_RS64_GP8_HI_BASE_IDX', 'regCP_GFX_RS64_GP8_LO', + 'regCP_GFX_RS64_GP8_LO_BASE_IDX', 'regCP_GFX_RS64_GP9_HI', + 'regCP_GFX_RS64_GP9_HI_BASE_IDX', 'regCP_GFX_RS64_GP9_LO', + 'regCP_GFX_RS64_GP9_LO_BASE_IDX', 'regCP_GFX_RS64_INSTR_PNTR0', + 'regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX', + 'regCP_GFX_RS64_INSTR_PNTR1', + 'regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX', + 'regCP_GFX_RS64_INTERRUPT0', 'regCP_GFX_RS64_INTERRUPT0_BASE_IDX', + 'regCP_GFX_RS64_INTERRUPT1', 'regCP_GFX_RS64_INTERRUPT1_BASE_IDX', + 'regCP_GFX_RS64_INTR_EN0', 'regCP_GFX_RS64_INTR_EN0_BASE_IDX', + 'regCP_GFX_RS64_INTR_EN1', 'regCP_GFX_RS64_INTR_EN1_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_APERTURE', + 'regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_BASE0_HI', + 'regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_BASE0_LO', + 'regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_INSTR_APERTURE', + 'regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI', + 'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO', + 'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI', + 'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO', + 'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_MASK0_HI', + 'regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_MASK0_LO', + 'regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE', + 'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI', + 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX', + 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO', + 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX', + 'regCP_GFX_RS64_MIBOUND_HI', 'regCP_GFX_RS64_MIBOUND_HI_BASE_IDX', + 'regCP_GFX_RS64_MIBOUND_LO', 'regCP_GFX_RS64_MIBOUND_LO_BASE_IDX', + 'regCP_GFX_RS64_MIP_HI0', 'regCP_GFX_RS64_MIP_HI0_BASE_IDX', + 'regCP_GFX_RS64_MIP_HI1', 'regCP_GFX_RS64_MIP_HI1_BASE_IDX', + 'regCP_GFX_RS64_MIP_LO0', 'regCP_GFX_RS64_MIP_LO0_BASE_IDX', + 'regCP_GFX_RS64_MIP_LO1', 'regCP_GFX_RS64_MIP_LO1_BASE_IDX', + 'regCP_GFX_RS64_MTIMECMP_HI0', + 'regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX', + 'regCP_GFX_RS64_MTIMECMP_HI1', + 'regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX', + 'regCP_GFX_RS64_MTIMECMP_LO0', + 'regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX', + 'regCP_GFX_RS64_MTIMECMP_LO1', + 'regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX', + 'regCP_GFX_RS64_PENDING_INTERRUPT0', + 'regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX', + 'regCP_GFX_RS64_PENDING_INTERRUPT1', + 'regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX', + 'regCP_GFX_RS64_PERFCOUNT_CNTL0', + 'regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX', + 'regCP_GFX_RS64_PERFCOUNT_CNTL1', + 'regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX', + 'regCP_GPU_TIMESTAMP_OFFSET_HI', + 'regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX', + 'regCP_GPU_TIMESTAMP_OFFSET_LO', + 'regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'regCP_GRBM_FREE_COUNT', + 'regCP_GRBM_FREE_COUNT_BASE_IDX', 'regCP_HPD_MES_ROQ_OFFSETS', + 'regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_ROQ_OFFSETS', + 'regCP_HPD_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_STATUS0', + 'regCP_HPD_STATUS0_BASE_IDX', 'regCP_HPD_UTCL1_CNTL', + 'regCP_HPD_UTCL1_CNTL_BASE_IDX', 'regCP_HPD_UTCL1_ERROR', + 'regCP_HPD_UTCL1_ERROR_ADDR', + 'regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX', + 'regCP_HPD_UTCL1_ERROR_BASE_IDX', 'regCP_HQD_ACTIVE', + 'regCP_HQD_ACTIVE_BASE_IDX', 'regCP_HQD_AQL_CONTROL', + 'regCP_HQD_AQL_CONTROL_BASE_IDX', 'regCP_HQD_ATOMIC0_PREOP_HI', + 'regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_HQD_ATOMIC0_PREOP_LO', + 'regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_HQD_ATOMIC1_PREOP_HI', + 'regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_HQD_ATOMIC1_PREOP_LO', + 'regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX', + 'regCP_HQD_CNTL_STACK_OFFSET', + 'regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX', + 'regCP_HQD_CNTL_STACK_SIZE', 'regCP_HQD_CNTL_STACK_SIZE_BASE_IDX', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', + 'regCP_HQD_CTX_SAVE_CONTROL', + 'regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', 'regCP_HQD_CTX_SAVE_SIZE', + 'regCP_HQD_CTX_SAVE_SIZE_BASE_IDX', + 'regCP_HQD_DDID_DELTA_RPT_COUNT', + 'regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX', + 'regCP_HQD_DDID_INFLIGHT_COUNT', + 'regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_HQD_DDID_RPTR', + 'regCP_HQD_DDID_RPTR_BASE_IDX', 'regCP_HQD_DDID_WPTR', + 'regCP_HQD_DDID_WPTR_BASE_IDX', 'regCP_HQD_DEQUEUE_REQUEST', + 'regCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'regCP_HQD_DEQUEUE_STATUS', + 'regCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'regCP_HQD_DMA_OFFLOAD', + 'regCP_HQD_DMA_OFFLOAD_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR', + 'regCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR_HI', + 'regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_EOP_CONTROL', + 'regCP_HQD_EOP_CONTROL_BASE_IDX', 'regCP_HQD_EOP_EVENTS', + 'regCP_HQD_EOP_EVENTS_BASE_IDX', 'regCP_HQD_EOP_RPTR', + 'regCP_HQD_EOP_RPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR', + 'regCP_HQD_EOP_WPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR_MEM', + 'regCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'regCP_HQD_ERROR', + 'regCP_HQD_ERROR_BASE_IDX', 'regCP_HQD_GDS_RESOURCE_STATE', + 'regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'regCP_HQD_GFX_CONTROL', + 'regCP_HQD_GFX_CONTROL_BASE_IDX', 'regCP_HQD_GFX_STATUS', + 'regCP_HQD_GFX_STATUS_BASE_IDX', 'regCP_HQD_HQ_CONTROL0', + 'regCP_HQD_HQ_CONTROL0_BASE_IDX', 'regCP_HQD_HQ_CONTROL1', + 'regCP_HQD_HQ_CONTROL1_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER0', + 'regCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER1', + 'regCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'regCP_HQD_HQ_STATUS0', + 'regCP_HQD_HQ_STATUS0_BASE_IDX', 'regCP_HQD_HQ_STATUS1', + 'regCP_HQD_HQ_STATUS1_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR', + 'regCP_HQD_IB_BASE_ADDR_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR_HI', + 'regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_IB_CONTROL', + 'regCP_HQD_IB_CONTROL_BASE_IDX', 'regCP_HQD_IB_RPTR', + 'regCP_HQD_IB_RPTR_BASE_IDX', 'regCP_HQD_IQ_RPTR', + 'regCP_HQD_IQ_RPTR_BASE_IDX', 'regCP_HQD_IQ_TIMER', + 'regCP_HQD_IQ_TIMER_BASE_IDX', 'regCP_HQD_MSG_TYPE', + 'regCP_HQD_MSG_TYPE_BASE_IDX', 'regCP_HQD_OFFLOAD', + 'regCP_HQD_OFFLOAD_BASE_IDX', 'regCP_HQD_PERSISTENT_STATE', + 'regCP_HQD_PERSISTENT_STATE_BASE_IDX', 'regCP_HQD_PIPE_PRIORITY', + 'regCP_HQD_PIPE_PRIORITY_BASE_IDX', 'regCP_HQD_PQ_BASE', + 'regCP_HQD_PQ_BASE_BASE_IDX', 'regCP_HQD_PQ_BASE_HI', + 'regCP_HQD_PQ_BASE_HI_BASE_IDX', 'regCP_HQD_PQ_CONTROL', + 'regCP_HQD_PQ_CONTROL_BASE_IDX', 'regCP_HQD_PQ_DOORBELL_CONTROL', + 'regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'regCP_HQD_PQ_RPTR', + 'regCP_HQD_PQ_RPTR_BASE_IDX', 'regCP_HQD_PQ_RPTR_REPORT_ADDR', + 'regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX', + 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI', + 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX', + 'regCP_HQD_PQ_WPTR_HI', 'regCP_HQD_PQ_WPTR_HI_BASE_IDX', + 'regCP_HQD_PQ_WPTR_LO', 'regCP_HQD_PQ_WPTR_LO_BASE_IDX', + 'regCP_HQD_PQ_WPTR_POLL_ADDR', + 'regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX', + 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI', + 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'regCP_HQD_QUANTUM', + 'regCP_HQD_QUANTUM_BASE_IDX', 'regCP_HQD_QUEUE_PRIORITY', + 'regCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'regCP_HQD_SEMA_CMD', + 'regCP_HQD_SEMA_CMD_BASE_IDX', + 'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT', + 'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX', + 'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET', + 'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', + 'regCP_HQD_SUSPEND_WG_STATE_OFFSET', + 'regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'regCP_HQD_VMID', + 'regCP_HQD_VMID_BASE_IDX', 'regCP_HQD_WG_STATE_OFFSET', + 'regCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'regCP_HYP_MEC1_UCODE_ADDR', + 'regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC1_UCODE_DATA', + 'regCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'regCP_HYP_MEC2_UCODE_ADDR', + 'regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC2_UCODE_DATA', + 'regCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'regCP_HYP_ME_UCODE_ADDR', + 'regCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'regCP_HYP_ME_UCODE_DATA', + 'regCP_HYP_ME_UCODE_DATA_BASE_IDX', 'regCP_HYP_PFP_UCODE_ADDR', + 'regCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_HYP_PFP_UCODE_DATA', + 'regCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'regCP_IB1_BASE_HI', + 'regCP_IB1_BASE_HI_BASE_IDX', 'regCP_IB1_BASE_LO', + 'regCP_IB1_BASE_LO_BASE_IDX', 'regCP_IB1_BUFSZ', + 'regCP_IB1_BUFSZ_BASE_IDX', 'regCP_IB1_CMD_BUFSZ', + 'regCP_IB1_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_BASE_HI', + 'regCP_IB2_BASE_HI_BASE_IDX', 'regCP_IB2_BASE_LO', + 'regCP_IB2_BASE_LO_BASE_IDX', 'regCP_IB2_BUFSZ', + 'regCP_IB2_BUFSZ_BASE_IDX', 'regCP_IB2_CMD_BUFSZ', + 'regCP_IB2_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_OFFSET', + 'regCP_IB2_OFFSET_BASE_IDX', 'regCP_IB2_PREAMBLE_BEGIN', + 'regCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'regCP_IB2_PREAMBLE_END', + 'regCP_IB2_PREAMBLE_END_BASE_IDX', 'regCP_INDEX_BASE_ADDR', + 'regCP_INDEX_BASE_ADDR_BASE_IDX', 'regCP_INDEX_BASE_ADDR_HI', + 'regCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'regCP_INDEX_TYPE', + 'regCP_INDEX_TYPE_BASE_IDX', 'regCP_INT_CNTL', + 'regCP_INT_CNTL_BASE_IDX', 'regCP_INT_CNTL_RING0', + 'regCP_INT_CNTL_RING0_BASE_IDX', 'regCP_INT_CNTL_RING1', + 'regCP_INT_CNTL_RING1_BASE_IDX', 'regCP_INT_STATUS', + 'regCP_INT_STATUS_BASE_IDX', 'regCP_INT_STATUS_RING0', + 'regCP_INT_STATUS_RING0_BASE_IDX', 'regCP_INT_STATUS_RING1', + 'regCP_INT_STATUS_RING1_BASE_IDX', 'regCP_IQ_WAIT_TIME1', + 'regCP_IQ_WAIT_TIME1_BASE_IDX', 'regCP_IQ_WAIT_TIME2', + 'regCP_IQ_WAIT_TIME2_BASE_IDX', 'regCP_IQ_WAIT_TIME3', + 'regCP_IQ_WAIT_TIME3_BASE_IDX', 'regCP_MAX_CONTEXT', + 'regCP_MAX_CONTEXT_BASE_IDX', 'regCP_MAX_DRAW_COUNT', + 'regCP_MAX_DRAW_COUNT_BASE_IDX', 'regCP_ME0_PIPE0_PRIORITY', + 'regCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE0_VMID', + 'regCP_ME0_PIPE0_VMID_BASE_IDX', 'regCP_ME0_PIPE1_PRIORITY', + 'regCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE1_VMID', + 'regCP_ME0_PIPE1_VMID_BASE_IDX', 'regCP_ME0_PIPE_PRIORITY_CNTS', + 'regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX', + 'regCP_ME1_PIPE0_INT_CNTL', 'regCP_ME1_PIPE0_INT_CNTL_BASE_IDX', + 'regCP_ME1_PIPE0_INT_STATUS', + 'regCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE0_PRIORITY', + 'regCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE1_INT_CNTL', + 'regCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE1_INT_STATUS', + 'regCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE1_PRIORITY', + 'regCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE2_INT_CNTL', + 'regCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE2_INT_STATUS', + 'regCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE2_PRIORITY', + 'regCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE3_INT_CNTL', + 'regCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE3_INT_STATUS', + 'regCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE3_PRIORITY', + 'regCP_ME1_PIPE3_PRIORITY_BASE_IDX', + 'regCP_ME1_PIPE_PRIORITY_CNTS', + 'regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX', + 'regCP_ME2_PIPE0_INT_CNTL', 'regCP_ME2_PIPE0_INT_CNTL_BASE_IDX', + 'regCP_ME2_PIPE0_INT_STATUS', + 'regCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE0_PRIORITY', + 'regCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE1_INT_CNTL', + 'regCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE1_INT_STATUS', + 'regCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE1_PRIORITY', + 'regCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE2_INT_CNTL', + 'regCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE2_INT_STATUS', + 'regCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE2_PRIORITY', + 'regCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE3_INT_CNTL', + 'regCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE3_INT_STATUS', + 'regCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE3_PRIORITY', + 'regCP_ME2_PIPE3_PRIORITY_BASE_IDX', + 'regCP_ME2_PIPE_PRIORITY_CNTS', + 'regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX', + 'regCP_MEC1_F32_INTERRUPT', 'regCP_MEC1_F32_INTERRUPT_BASE_IDX', + 'regCP_MEC1_F32_INT_DIS', 'regCP_MEC1_F32_INT_DIS_BASE_IDX', + 'regCP_MEC1_INSTR_PNTR', 'regCP_MEC1_INSTR_PNTR_BASE_IDX', + 'regCP_MEC1_INTR_ROUTINE_START', + 'regCP_MEC1_INTR_ROUTINE_START_BASE_IDX', + 'regCP_MEC1_PRGRM_CNTR_START', + 'regCP_MEC1_PRGRM_CNTR_START_BASE_IDX', + 'regCP_MEC2_F32_INTERRUPT', 'regCP_MEC2_F32_INTERRUPT_BASE_IDX', + 'regCP_MEC2_F32_INT_DIS', 'regCP_MEC2_F32_INT_DIS_BASE_IDX', + 'regCP_MEC2_INSTR_PNTR', 'regCP_MEC2_INSTR_PNTR_BASE_IDX', + 'regCP_MEC2_INTR_ROUTINE_START', + 'regCP_MEC2_INTR_ROUTINE_START_BASE_IDX', + 'regCP_MEC2_PRGRM_CNTR_START', + 'regCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'regCP_MEC_CNTL', + 'regCP_MEC_CNTL_BASE_IDX', 'regCP_MEC_DC_APERTURE0_BASE', + 'regCP_MEC_DC_APERTURE0_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE0_CNTL', + 'regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE0_MASK', + 'regCP_MEC_DC_APERTURE0_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE10_BASE', + 'regCP_MEC_DC_APERTURE10_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE10_CNTL', + 'regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE10_MASK', + 'regCP_MEC_DC_APERTURE10_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE11_BASE', + 'regCP_MEC_DC_APERTURE11_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE11_CNTL', + 'regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE11_MASK', + 'regCP_MEC_DC_APERTURE11_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE12_BASE', + 'regCP_MEC_DC_APERTURE12_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE12_CNTL', + 'regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE12_MASK', + 'regCP_MEC_DC_APERTURE12_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE13_BASE', + 'regCP_MEC_DC_APERTURE13_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE13_CNTL', + 'regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE13_MASK', + 'regCP_MEC_DC_APERTURE13_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE14_BASE', + 'regCP_MEC_DC_APERTURE14_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE14_CNTL', + 'regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE14_MASK', + 'regCP_MEC_DC_APERTURE14_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE15_BASE', + 'regCP_MEC_DC_APERTURE15_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE15_CNTL', + 'regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE15_MASK', + 'regCP_MEC_DC_APERTURE15_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE1_BASE', + 'regCP_MEC_DC_APERTURE1_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE1_CNTL', + 'regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE1_MASK', + 'regCP_MEC_DC_APERTURE1_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE2_BASE', + 'regCP_MEC_DC_APERTURE2_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE2_CNTL', + 'regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE2_MASK', + 'regCP_MEC_DC_APERTURE2_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE3_BASE', + 'regCP_MEC_DC_APERTURE3_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE3_CNTL', + 'regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE3_MASK', + 'regCP_MEC_DC_APERTURE3_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE4_BASE', + 'regCP_MEC_DC_APERTURE4_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE4_CNTL', + 'regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE4_MASK', + 'regCP_MEC_DC_APERTURE4_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE5_BASE', + 'regCP_MEC_DC_APERTURE5_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE5_CNTL', + 'regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE5_MASK', + 'regCP_MEC_DC_APERTURE5_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE6_BASE', + 'regCP_MEC_DC_APERTURE6_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE6_CNTL', + 'regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE6_MASK', + 'regCP_MEC_DC_APERTURE6_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE7_BASE', + 'regCP_MEC_DC_APERTURE7_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE7_CNTL', + 'regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE7_MASK', + 'regCP_MEC_DC_APERTURE7_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE8_BASE', + 'regCP_MEC_DC_APERTURE8_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE8_CNTL', + 'regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE8_MASK', + 'regCP_MEC_DC_APERTURE8_MASK_BASE_IDX', + 'regCP_MEC_DC_APERTURE9_BASE', + 'regCP_MEC_DC_APERTURE9_BASE_BASE_IDX', + 'regCP_MEC_DC_APERTURE9_CNTL', + 'regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX', + 'regCP_MEC_DC_APERTURE9_MASK', + 'regCP_MEC_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MEC_DC_BASE_CNTL', + 'regCP_MEC_DC_BASE_CNTL_BASE_IDX', 'regCP_MEC_DC_BASE_HI', + 'regCP_MEC_DC_BASE_HI_BASE_IDX', 'regCP_MEC_DC_BASE_LO', + 'regCP_MEC_DC_BASE_LO_BASE_IDX', 'regCP_MEC_DC_OP_CNTL', + 'regCP_MEC_DC_OP_CNTL_BASE_IDX', 'regCP_MEC_DM_INDEX_ADDR', + 'regCP_MEC_DM_INDEX_ADDR_BASE_IDX', 'regCP_MEC_DM_INDEX_DATA', + 'regCP_MEC_DM_INDEX_DATA_BASE_IDX', + 'regCP_MEC_DOORBELL_RANGE_LOWER', + 'regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX', + 'regCP_MEC_DOORBELL_RANGE_UPPER', + 'regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_MEC_GP0_HI', + 'regCP_MEC_GP0_HI_BASE_IDX', 'regCP_MEC_GP0_LO', + 'regCP_MEC_GP0_LO_BASE_IDX', 'regCP_MEC_GP1_HI', + 'regCP_MEC_GP1_HI_BASE_IDX', 'regCP_MEC_GP1_LO', + 'regCP_MEC_GP1_LO_BASE_IDX', 'regCP_MEC_GP2_HI', + 'regCP_MEC_GP2_HI_BASE_IDX', 'regCP_MEC_GP2_LO', + 'regCP_MEC_GP2_LO_BASE_IDX', 'regCP_MEC_GP3_HI', + 'regCP_MEC_GP3_HI_BASE_IDX', 'regCP_MEC_GP3_LO', + 'regCP_MEC_GP3_LO_BASE_IDX', 'regCP_MEC_GP4_HI', + 'regCP_MEC_GP4_HI_BASE_IDX', 'regCP_MEC_GP4_LO', + 'regCP_MEC_GP4_LO_BASE_IDX', 'regCP_MEC_GP5_HI', + 'regCP_MEC_GP5_HI_BASE_IDX', 'regCP_MEC_GP5_LO', + 'regCP_MEC_GP5_LO_BASE_IDX', 'regCP_MEC_GP6_HI', + 'regCP_MEC_GP6_HI_BASE_IDX', 'regCP_MEC_GP6_LO', + 'regCP_MEC_GP6_LO_BASE_IDX', 'regCP_MEC_GP7_HI', + 'regCP_MEC_GP7_HI_BASE_IDX', 'regCP_MEC_GP7_LO', + 'regCP_MEC_GP7_LO_BASE_IDX', 'regCP_MEC_GP8_HI', + 'regCP_MEC_GP8_HI_BASE_IDX', 'regCP_MEC_GP8_LO', + 'regCP_MEC_GP8_LO_BASE_IDX', 'regCP_MEC_GP9_HI', + 'regCP_MEC_GP9_HI_BASE_IDX', 'regCP_MEC_GP9_LO', + 'regCP_MEC_GP9_LO_BASE_IDX', 'regCP_MEC_ISA_CNTL', + 'regCP_MEC_ISA_CNTL_BASE_IDX', 'regCP_MEC_JT_STAT', + 'regCP_MEC_JT_STAT_BASE_IDX', 'regCP_MEC_LOCAL_APERTURE', + 'regCP_MEC_LOCAL_APERTURE_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_HI', + 'regCP_MEC_LOCAL_BASE0_HI_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_LO', + 'regCP_MEC_LOCAL_BASE0_LO_BASE_IDX', + 'regCP_MEC_LOCAL_INSTR_APERTURE', + 'regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX', + 'regCP_MEC_LOCAL_INSTR_BASE_HI', + 'regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX', + 'regCP_MEC_LOCAL_INSTR_BASE_LO', + 'regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX', + 'regCP_MEC_LOCAL_INSTR_MASK_HI', + 'regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX', + 'regCP_MEC_LOCAL_INSTR_MASK_LO', + 'regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX', + 'regCP_MEC_LOCAL_MASK0_HI', 'regCP_MEC_LOCAL_MASK0_HI_BASE_IDX', + 'regCP_MEC_LOCAL_MASK0_LO', 'regCP_MEC_LOCAL_MASK0_LO_BASE_IDX', + 'regCP_MEC_LOCAL_SCRATCH_APERTURE', + 'regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX', + 'regCP_MEC_LOCAL_SCRATCH_BASE_HI', + 'regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX', + 'regCP_MEC_LOCAL_SCRATCH_BASE_LO', + 'regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX', 'regCP_MEC_MDBASE_HI', + 'regCP_MEC_MDBASE_HI_BASE_IDX', 'regCP_MEC_MDBASE_LO', + 'regCP_MEC_MDBASE_LO_BASE_IDX', 'regCP_MEC_MDBOUND_HI', + 'regCP_MEC_MDBOUND_HI_BASE_IDX', 'regCP_MEC_MDBOUND_LO', + 'regCP_MEC_MDBOUND_LO_BASE_IDX', 'regCP_MEC_ME1_HEADER_DUMP', + 'regCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME1_UCODE_ADDR', + 'regCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME1_UCODE_DATA', + 'regCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'regCP_MEC_ME2_HEADER_DUMP', + 'regCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME2_UCODE_ADDR', + 'regCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME2_UCODE_DATA', + 'regCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'regCP_MEC_MIBOUND_HI', + 'regCP_MEC_MIBOUND_HI_BASE_IDX', 'regCP_MEC_MIBOUND_LO', + 'regCP_MEC_MIBOUND_LO_BASE_IDX', 'regCP_MEC_MIE_HI', + 'regCP_MEC_MIE_HI_BASE_IDX', 'regCP_MEC_MIE_LO', + 'regCP_MEC_MIE_LO_BASE_IDX', 'regCP_MEC_MIP_HI', + 'regCP_MEC_MIP_HI_BASE_IDX', 'regCP_MEC_MIP_LO', + 'regCP_MEC_MIP_LO_BASE_IDX', 'regCP_MEC_MTIMECMP_HI', + 'regCP_MEC_MTIMECMP_HI_BASE_IDX', 'regCP_MEC_MTIMECMP_LO', + 'regCP_MEC_MTIMECMP_LO_BASE_IDX', 'regCP_MEC_MTVEC_HI', + 'regCP_MEC_MTVEC_HI_BASE_IDX', 'regCP_MEC_MTVEC_LO', + 'regCP_MEC_MTVEC_LO_BASE_IDX', 'regCP_MEC_RS64_CNTL', + 'regCP_MEC_RS64_CNTL_BASE_IDX', 'regCP_MEC_RS64_INSTR_PNTR', + 'regCP_MEC_RS64_INSTR_PNTR_BASE_IDX', 'regCP_MEC_RS64_INTERRUPT', + 'regCP_MEC_RS64_INTERRUPT_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_16', + 'regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_17', + 'regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_18', + 'regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_19', + 'regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_20', + 'regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_21', + 'regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_22', + 'regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_23', + 'regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_24', + 'regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_25', + 'regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_26', + 'regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_27', + 'regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_28', + 'regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_29', + 'regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_30', + 'regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX', + 'regCP_MEC_RS64_INTERRUPT_DATA_31', + 'regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX', + 'regCP_MEC_RS64_PENDING_INTERRUPT', + 'regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX', + 'regCP_MEC_RS64_PERFCOUNT_CNTL', + 'regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX', + 'regCP_MEC_RS64_PRGRM_CNTR_START', + 'regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX', + 'regCP_MEC_RS64_PRGRM_CNTR_START_HI', + 'regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_MEQ_AVAIL', + 'regCP_MEQ_AVAIL_BASE_IDX', 'regCP_MEQ_STAT', + 'regCP_MEQ_STAT_BASE_IDX', 'regCP_MEQ_THRESHOLDS', + 'regCP_MEQ_THRESHOLDS_BASE_IDX', 'regCP_MES_CNTL', + 'regCP_MES_CNTL_BASE_IDX', 'regCP_MES_DC_APERTURE0_BASE', + 'regCP_MES_DC_APERTURE0_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE0_CNTL', + 'regCP_MES_DC_APERTURE0_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE0_MASK', + 'regCP_MES_DC_APERTURE0_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE10_BASE', + 'regCP_MES_DC_APERTURE10_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE10_CNTL', + 'regCP_MES_DC_APERTURE10_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE10_MASK', + 'regCP_MES_DC_APERTURE10_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE11_BASE', + 'regCP_MES_DC_APERTURE11_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE11_CNTL', + 'regCP_MES_DC_APERTURE11_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE11_MASK', + 'regCP_MES_DC_APERTURE11_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE12_BASE', + 'regCP_MES_DC_APERTURE12_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE12_CNTL', + 'regCP_MES_DC_APERTURE12_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE12_MASK', + 'regCP_MES_DC_APERTURE12_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE13_BASE', + 'regCP_MES_DC_APERTURE13_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE13_CNTL', + 'regCP_MES_DC_APERTURE13_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE13_MASK', + 'regCP_MES_DC_APERTURE13_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE14_BASE', + 'regCP_MES_DC_APERTURE14_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE14_CNTL', + 'regCP_MES_DC_APERTURE14_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE14_MASK', + 'regCP_MES_DC_APERTURE14_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE15_BASE', + 'regCP_MES_DC_APERTURE15_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE15_CNTL', + 'regCP_MES_DC_APERTURE15_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE15_MASK', + 'regCP_MES_DC_APERTURE15_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE1_BASE', + 'regCP_MES_DC_APERTURE1_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE1_CNTL', + 'regCP_MES_DC_APERTURE1_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE1_MASK', + 'regCP_MES_DC_APERTURE1_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE2_BASE', + 'regCP_MES_DC_APERTURE2_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE2_CNTL', + 'regCP_MES_DC_APERTURE2_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE2_MASK', + 'regCP_MES_DC_APERTURE2_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE3_BASE', + 'regCP_MES_DC_APERTURE3_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE3_CNTL', + 'regCP_MES_DC_APERTURE3_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE3_MASK', + 'regCP_MES_DC_APERTURE3_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE4_BASE', + 'regCP_MES_DC_APERTURE4_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE4_CNTL', + 'regCP_MES_DC_APERTURE4_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE4_MASK', + 'regCP_MES_DC_APERTURE4_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE5_BASE', + 'regCP_MES_DC_APERTURE5_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE5_CNTL', + 'regCP_MES_DC_APERTURE5_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE5_MASK', + 'regCP_MES_DC_APERTURE5_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE6_BASE', + 'regCP_MES_DC_APERTURE6_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE6_CNTL', + 'regCP_MES_DC_APERTURE6_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE6_MASK', + 'regCP_MES_DC_APERTURE6_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE7_BASE', + 'regCP_MES_DC_APERTURE7_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE7_CNTL', + 'regCP_MES_DC_APERTURE7_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE7_MASK', + 'regCP_MES_DC_APERTURE7_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE8_BASE', + 'regCP_MES_DC_APERTURE8_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE8_CNTL', + 'regCP_MES_DC_APERTURE8_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE8_MASK', + 'regCP_MES_DC_APERTURE8_MASK_BASE_IDX', + 'regCP_MES_DC_APERTURE9_BASE', + 'regCP_MES_DC_APERTURE9_BASE_BASE_IDX', + 'regCP_MES_DC_APERTURE9_CNTL', + 'regCP_MES_DC_APERTURE9_CNTL_BASE_IDX', + 'regCP_MES_DC_APERTURE9_MASK', + 'regCP_MES_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MES_DC_BASE_CNTL', + 'regCP_MES_DC_BASE_CNTL_BASE_IDX', 'regCP_MES_DC_BASE_HI', + 'regCP_MES_DC_BASE_HI_BASE_IDX', 'regCP_MES_DC_BASE_LO', + 'regCP_MES_DC_BASE_LO_BASE_IDX', 'regCP_MES_DC_OP_CNTL', + 'regCP_MES_DC_OP_CNTL_BASE_IDX', + 'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR', + 'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX', + 'regCP_MES_DM_INDEX_ADDR', 'regCP_MES_DM_INDEX_ADDR_BASE_IDX', + 'regCP_MES_DM_INDEX_DATA', 'regCP_MES_DM_INDEX_DATA_BASE_IDX', + 'regCP_MES_DOORBELL_CONTROL1', + 'regCP_MES_DOORBELL_CONTROL1_BASE_IDX', + 'regCP_MES_DOORBELL_CONTROL2', + 'regCP_MES_DOORBELL_CONTROL2_BASE_IDX', + 'regCP_MES_DOORBELL_CONTROL3', + 'regCP_MES_DOORBELL_CONTROL3_BASE_IDX', + 'regCP_MES_DOORBELL_CONTROL4', + 'regCP_MES_DOORBELL_CONTROL4_BASE_IDX', + 'regCP_MES_DOORBELL_CONTROL5', + 'regCP_MES_DOORBELL_CONTROL5_BASE_IDX', + 'regCP_MES_DOORBELL_CONTROL6', + 'regCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'regCP_MES_GP0_HI', + 'regCP_MES_GP0_HI_BASE_IDX', 'regCP_MES_GP0_LO', + 'regCP_MES_GP0_LO_BASE_IDX', 'regCP_MES_GP1_HI', + 'regCP_MES_GP1_HI_BASE_IDX', 'regCP_MES_GP1_LO', + 'regCP_MES_GP1_LO_BASE_IDX', 'regCP_MES_GP2_HI', + 'regCP_MES_GP2_HI_BASE_IDX', 'regCP_MES_GP2_LO', + 'regCP_MES_GP2_LO_BASE_IDX', 'regCP_MES_GP3_HI', + 'regCP_MES_GP3_HI_BASE_IDX', 'regCP_MES_GP3_LO', + 'regCP_MES_GP3_LO_BASE_IDX', 'regCP_MES_GP4_HI', + 'regCP_MES_GP4_HI_BASE_IDX', 'regCP_MES_GP4_LO', + 'regCP_MES_GP4_LO_BASE_IDX', 'regCP_MES_GP5_HI', + 'regCP_MES_GP5_HI_BASE_IDX', 'regCP_MES_GP5_LO', + 'regCP_MES_GP5_LO_BASE_IDX', 'regCP_MES_GP6_HI', + 'regCP_MES_GP6_HI_BASE_IDX', 'regCP_MES_GP6_LO', + 'regCP_MES_GP6_LO_BASE_IDX', 'regCP_MES_GP7_HI', + 'regCP_MES_GP7_HI_BASE_IDX', 'regCP_MES_GP7_LO', + 'regCP_MES_GP7_LO_BASE_IDX', 'regCP_MES_GP8_HI', + 'regCP_MES_GP8_HI_BASE_IDX', 'regCP_MES_GP8_LO', + 'regCP_MES_GP8_LO_BASE_IDX', 'regCP_MES_GP9_HI', + 'regCP_MES_GP9_HI_BASE_IDX', 'regCP_MES_GP9_LO', + 'regCP_MES_GP9_LO_BASE_IDX', 'regCP_MES_HEADER_DUMP', + 'regCP_MES_HEADER_DUMP_BASE_IDX', 'regCP_MES_IC_BASE_CNTL', + 'regCP_MES_IC_BASE_CNTL_BASE_IDX', 'regCP_MES_IC_BASE_HI', + 'regCP_MES_IC_BASE_HI_BASE_IDX', 'regCP_MES_IC_BASE_LO', + 'regCP_MES_IC_BASE_LO_BASE_IDX', 'regCP_MES_IC_OP_CNTL', + 'regCP_MES_IC_OP_CNTL_BASE_IDX', 'regCP_MES_INSTR_PNTR', + 'regCP_MES_INSTR_PNTR_BASE_IDX', 'regCP_MES_INTERRUPT', + 'regCP_MES_INTERRUPT_BASE_IDX', 'regCP_MES_INTERRUPT_DATA_16', + 'regCP_MES_INTERRUPT_DATA_16_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_17', + 'regCP_MES_INTERRUPT_DATA_17_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_18', + 'regCP_MES_INTERRUPT_DATA_18_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_19', + 'regCP_MES_INTERRUPT_DATA_19_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_20', + 'regCP_MES_INTERRUPT_DATA_20_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_21', + 'regCP_MES_INTERRUPT_DATA_21_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_22', + 'regCP_MES_INTERRUPT_DATA_22_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_23', + 'regCP_MES_INTERRUPT_DATA_23_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_24', + 'regCP_MES_INTERRUPT_DATA_24_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_25', + 'regCP_MES_INTERRUPT_DATA_25_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_26', + 'regCP_MES_INTERRUPT_DATA_26_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_27', + 'regCP_MES_INTERRUPT_DATA_27_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_28', + 'regCP_MES_INTERRUPT_DATA_28_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_29', + 'regCP_MES_INTERRUPT_DATA_29_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_30', + 'regCP_MES_INTERRUPT_DATA_30_BASE_IDX', + 'regCP_MES_INTERRUPT_DATA_31', + 'regCP_MES_INTERRUPT_DATA_31_BASE_IDX', + 'regCP_MES_INTR_ROUTINE_START', + 'regCP_MES_INTR_ROUTINE_START_BASE_IDX', + 'regCP_MES_INTR_ROUTINE_START_HI', + 'regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX', + 'regCP_MES_LOCAL_APERTURE', 'regCP_MES_LOCAL_APERTURE_BASE_IDX', + 'regCP_MES_LOCAL_BASE0_HI', 'regCP_MES_LOCAL_BASE0_HI_BASE_IDX', + 'regCP_MES_LOCAL_BASE0_LO', 'regCP_MES_LOCAL_BASE0_LO_BASE_IDX', + 'regCP_MES_LOCAL_INSTR_APERTURE', + 'regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX', + 'regCP_MES_LOCAL_INSTR_BASE_HI', + 'regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX', + 'regCP_MES_LOCAL_INSTR_BASE_LO', + 'regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX', + 'regCP_MES_LOCAL_INSTR_MASK_HI', + 'regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX', + 'regCP_MES_LOCAL_INSTR_MASK_LO', + 'regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX', + 'regCP_MES_LOCAL_MASK0_HI', 'regCP_MES_LOCAL_MASK0_HI_BASE_IDX', + 'regCP_MES_LOCAL_MASK0_LO', 'regCP_MES_LOCAL_MASK0_LO_BASE_IDX', + 'regCP_MES_LOCAL_SCRATCH_APERTURE', + 'regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX', + 'regCP_MES_LOCAL_SCRATCH_BASE_HI', + 'regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX', + 'regCP_MES_LOCAL_SCRATCH_BASE_LO', + 'regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX', + 'regCP_MES_MARCHID_HI', 'regCP_MES_MARCHID_HI_BASE_IDX', + 'regCP_MES_MARCHID_LO', 'regCP_MES_MARCHID_LO_BASE_IDX', + 'regCP_MES_MBADADDR_HI', 'regCP_MES_MBADADDR_HI_BASE_IDX', + 'regCP_MES_MBADADDR_LO', 'regCP_MES_MBADADDR_LO_BASE_IDX', + 'regCP_MES_MCAUSE_HI', 'regCP_MES_MCAUSE_HI_BASE_IDX', + 'regCP_MES_MCAUSE_LO', 'regCP_MES_MCAUSE_LO_BASE_IDX', + 'regCP_MES_MCYCLE_HI', 'regCP_MES_MCYCLE_HI_BASE_IDX', + 'regCP_MES_MCYCLE_LO', 'regCP_MES_MCYCLE_LO_BASE_IDX', + 'regCP_MES_MDBASE_HI', 'regCP_MES_MDBASE_HI_BASE_IDX', + 'regCP_MES_MDBASE_LO', 'regCP_MES_MDBASE_LO_BASE_IDX', + 'regCP_MES_MDBOUND_HI', 'regCP_MES_MDBOUND_HI_BASE_IDX', + 'regCP_MES_MDBOUND_LO', 'regCP_MES_MDBOUND_LO_BASE_IDX', + 'regCP_MES_MEPC_HI', 'regCP_MES_MEPC_HI_BASE_IDX', + 'regCP_MES_MEPC_LO', 'regCP_MES_MEPC_LO_BASE_IDX', + 'regCP_MES_MHARTID_HI', 'regCP_MES_MHARTID_HI_BASE_IDX', + 'regCP_MES_MHARTID_LO', 'regCP_MES_MHARTID_LO_BASE_IDX', + 'regCP_MES_MIBASE_HI', 'regCP_MES_MIBASE_HI_BASE_IDX', + 'regCP_MES_MIBASE_LO', 'regCP_MES_MIBASE_LO_BASE_IDX', + 'regCP_MES_MIBOUND_HI', 'regCP_MES_MIBOUND_HI_BASE_IDX', + 'regCP_MES_MIBOUND_LO', 'regCP_MES_MIBOUND_LO_BASE_IDX', + 'regCP_MES_MIE_HI', 'regCP_MES_MIE_HI_BASE_IDX', + 'regCP_MES_MIE_LO', 'regCP_MES_MIE_LO_BASE_IDX', + 'regCP_MES_MIMPID_HI', 'regCP_MES_MIMPID_HI_BASE_IDX', + 'regCP_MES_MIMPID_LO', 'regCP_MES_MIMPID_LO_BASE_IDX', + 'regCP_MES_MINSTRET_HI', 'regCP_MES_MINSTRET_HI_BASE_IDX', + 'regCP_MES_MINSTRET_LO', 'regCP_MES_MINSTRET_LO_BASE_IDX', + 'regCP_MES_MIP_HI', 'regCP_MES_MIP_HI_BASE_IDX', + 'regCP_MES_MIP_LO', 'regCP_MES_MIP_LO_BASE_IDX', + 'regCP_MES_MISA_HI', 'regCP_MES_MISA_HI_BASE_IDX', + 'regCP_MES_MISA_LO', 'regCP_MES_MISA_LO_BASE_IDX', + 'regCP_MES_MSCRATCH_HI', 'regCP_MES_MSCRATCH_HI_BASE_IDX', + 'regCP_MES_MSCRATCH_LO', 'regCP_MES_MSCRATCH_LO_BASE_IDX', + 'regCP_MES_MSTATUS_HI', 'regCP_MES_MSTATUS_HI_BASE_IDX', + 'regCP_MES_MSTATUS_LO', 'regCP_MES_MSTATUS_LO_BASE_IDX', + 'regCP_MES_MTIMECMP_HI', 'regCP_MES_MTIMECMP_HI_BASE_IDX', + 'regCP_MES_MTIMECMP_LO', 'regCP_MES_MTIMECMP_LO_BASE_IDX', + 'regCP_MES_MTIME_HI', 'regCP_MES_MTIME_HI_BASE_IDX', + 'regCP_MES_MTIME_LO', 'regCP_MES_MTIME_LO_BASE_IDX', + 'regCP_MES_MTVEC_HI', 'regCP_MES_MTVEC_HI_BASE_IDX', + 'regCP_MES_MTVEC_LO', 'regCP_MES_MTVEC_LO_BASE_IDX', + 'regCP_MES_MVENDORID_HI', 'regCP_MES_MVENDORID_HI_BASE_IDX', + 'regCP_MES_MVENDORID_LO', 'regCP_MES_MVENDORID_LO_BASE_IDX', + 'regCP_MES_PENDING_INTERRUPT', + 'regCP_MES_PENDING_INTERRUPT_BASE_IDX', + 'regCP_MES_PERFCOUNT_CNTL', 'regCP_MES_PERFCOUNT_CNTL_BASE_IDX', + 'regCP_MES_PIPE0_PRIORITY', 'regCP_MES_PIPE0_PRIORITY_BASE_IDX', + 'regCP_MES_PIPE1_PRIORITY', 'regCP_MES_PIPE1_PRIORITY_BASE_IDX', + 'regCP_MES_PIPE2_PRIORITY', 'regCP_MES_PIPE2_PRIORITY_BASE_IDX', + 'regCP_MES_PIPE3_PRIORITY', 'regCP_MES_PIPE3_PRIORITY_BASE_IDX', + 'regCP_MES_PIPE_PRIORITY_CNTS', + 'regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX', + 'regCP_MES_PRGRM_CNTR_START', + 'regCP_MES_PRGRM_CNTR_START_BASE_IDX', + 'regCP_MES_PRGRM_CNTR_START_HI', + 'regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX', + 'regCP_MES_PROCESS_QUANTUM_PIPE0', + 'regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX', + 'regCP_MES_PROCESS_QUANTUM_PIPE1', + 'regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX', + 'regCP_MES_SCRATCH_DATA', 'regCP_MES_SCRATCH_DATA_BASE_IDX', + 'regCP_MES_SCRATCH_INDEX', 'regCP_MES_SCRATCH_INDEX_BASE_IDX', + 'regCP_ME_ATOMIC_PREOP_HI', 'regCP_ME_ATOMIC_PREOP_HI_BASE_IDX', + 'regCP_ME_ATOMIC_PREOP_LO', 'regCP_ME_ATOMIC_PREOP_LO_BASE_IDX', + 'regCP_ME_CNTL', 'regCP_ME_CNTL_BASE_IDX', 'regCP_ME_COHER_BASE', + 'regCP_ME_COHER_BASE_BASE_IDX', 'regCP_ME_COHER_BASE_HI', + 'regCP_ME_COHER_BASE_HI_BASE_IDX', 'regCP_ME_COHER_CNTL', + 'regCP_ME_COHER_CNTL_BASE_IDX', 'regCP_ME_COHER_SIZE', + 'regCP_ME_COHER_SIZE_BASE_IDX', 'regCP_ME_COHER_SIZE_HI', + 'regCP_ME_COHER_SIZE_HI_BASE_IDX', 'regCP_ME_COHER_STATUS', + 'regCP_ME_COHER_STATUS_BASE_IDX', 'regCP_ME_F32_INTERRUPT', + 'regCP_ME_F32_INTERRUPT_BASE_IDX', + 'regCP_ME_GDS_ATOMIC0_PREOP_HI', + 'regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_ME_GDS_ATOMIC0_PREOP_LO', + 'regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_ME_GDS_ATOMIC1_PREOP_HI', + 'regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_ME_GDS_ATOMIC1_PREOP_LO', + 'regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_ME_HEADER_DUMP', + 'regCP_ME_HEADER_DUMP_BASE_IDX', 'regCP_ME_IC_BASE_CNTL', + 'regCP_ME_IC_BASE_CNTL_BASE_IDX', 'regCP_ME_IC_BASE_HI', + 'regCP_ME_IC_BASE_HI_BASE_IDX', 'regCP_ME_IC_BASE_LO', + 'regCP_ME_IC_BASE_LO_BASE_IDX', 'regCP_ME_IC_OP_CNTL', + 'regCP_ME_IC_OP_CNTL_BASE_IDX', 'regCP_ME_INSTR_PNTR', + 'regCP_ME_INSTR_PNTR_BASE_IDX', 'regCP_ME_INTR_ROUTINE_START', + 'regCP_ME_INTR_ROUTINE_START_BASE_IDX', + 'regCP_ME_INTR_ROUTINE_START_HI', + 'regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_ME_MC_RADDR_HI', + 'regCP_ME_MC_RADDR_HI_BASE_IDX', 'regCP_ME_MC_RADDR_LO', + 'regCP_ME_MC_RADDR_LO_BASE_IDX', 'regCP_ME_MC_WADDR_HI', + 'regCP_ME_MC_WADDR_HI_BASE_IDX', 'regCP_ME_MC_WADDR_LO', + 'regCP_ME_MC_WADDR_LO_BASE_IDX', 'regCP_ME_MC_WDATA_HI', + 'regCP_ME_MC_WDATA_HI_BASE_IDX', 'regCP_ME_MC_WDATA_LO', + 'regCP_ME_MC_WDATA_LO_BASE_IDX', 'regCP_ME_PREEMPTION', + 'regCP_ME_PREEMPTION_BASE_IDX', 'regCP_ME_PRGRM_CNTR_START', + 'regCP_ME_PRGRM_CNTR_START_BASE_IDX', + 'regCP_ME_PRGRM_CNTR_START_HI', + 'regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_ME_RAM_DATA', + 'regCP_ME_RAM_DATA_BASE_IDX', 'regCP_ME_RAM_RADDR', + 'regCP_ME_RAM_RADDR_BASE_IDX', 'regCP_ME_RAM_WADDR', + 'regCP_ME_RAM_WADDR_BASE_IDX', 'regCP_ME_SDMA_CS', + 'regCP_ME_SDMA_CS_BASE_IDX', 'regCP_MQD_BASE_ADDR', + 'regCP_MQD_BASE_ADDR_BASE_IDX', 'regCP_MQD_BASE_ADDR_HI', + 'regCP_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_MQD_CONTROL', + 'regCP_MQD_CONTROL_BASE_IDX', 'regCP_PA_CINVOC_COUNT_HI', + 'regCP_PA_CINVOC_COUNT_HI_BASE_IDX', 'regCP_PA_CINVOC_COUNT_LO', + 'regCP_PA_CINVOC_COUNT_LO_BASE_IDX', 'regCP_PA_CPRIM_COUNT_HI', + 'regCP_PA_CPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_CPRIM_COUNT_LO', + 'regCP_PA_CPRIM_COUNT_LO_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_HI', + 'regCP_PA_MSPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_LO', + 'regCP_PA_MSPRIM_COUNT_LO_BASE_IDX', 'regCP_PERFMON_CNTL', + 'regCP_PERFMON_CNTL_BASE_IDX', 'regCP_PERFMON_CNTX_CNTL', + 'regCP_PERFMON_CNTX_CNTL_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_HI', + 'regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_LO', + 'regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX', + 'regCP_PFP_COMPLETION_STATUS', + 'regCP_PFP_COMPLETION_STATUS_BASE_IDX', 'regCP_PFP_F32_INTERRUPT', + 'regCP_PFP_F32_INTERRUPT_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC0_PREOP_HI', + 'regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC0_PREOP_LO', + 'regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC1_PREOP_HI', + 'regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC1_PREOP_LO', + 'regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', + 'regCP_PFP_HEADER_DUMP', 'regCP_PFP_HEADER_DUMP_BASE_IDX', + 'regCP_PFP_IB_CONTROL', 'regCP_PFP_IB_CONTROL_BASE_IDX', + 'regCP_PFP_IC_BASE_CNTL', 'regCP_PFP_IC_BASE_CNTL_BASE_IDX', + 'regCP_PFP_IC_BASE_HI', 'regCP_PFP_IC_BASE_HI_BASE_IDX', + 'regCP_PFP_IC_BASE_LO', 'regCP_PFP_IC_BASE_LO_BASE_IDX', + 'regCP_PFP_IC_OP_CNTL', 'regCP_PFP_IC_OP_CNTL_BASE_IDX', + 'regCP_PFP_INSTR_PNTR', 'regCP_PFP_INSTR_PNTR_BASE_IDX', + 'regCP_PFP_INTR_ROUTINE_START', + 'regCP_PFP_INTR_ROUTINE_START_BASE_IDX', + 'regCP_PFP_INTR_ROUTINE_START_HI', + 'regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_PFP_JT_STAT', + 'regCP_PFP_JT_STAT_BASE_IDX', 'regCP_PFP_LOAD_CONTROL', + 'regCP_PFP_LOAD_CONTROL_BASE_IDX', 'regCP_PFP_METADATA_BASE_ADDR', + 'regCP_PFP_METADATA_BASE_ADDR_BASE_IDX', + 'regCP_PFP_METADATA_BASE_ADDR_HI', + 'regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX', + 'regCP_PFP_PRGRM_CNTR_START', + 'regCP_PFP_PRGRM_CNTR_START_BASE_IDX', + 'regCP_PFP_PRGRM_CNTR_START_HI', + 'regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_PFP_SDMA_CS', + 'regCP_PFP_SDMA_CS_BASE_IDX', 'regCP_PFP_UCODE_ADDR', + 'regCP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_PFP_UCODE_DATA', + 'regCP_PFP_UCODE_DATA_BASE_IDX', 'regCP_PIPEID', + 'regCP_PIPEID_BASE_IDX', 'regCP_PIPE_STATS_ADDR_HI', + 'regCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'regCP_PIPE_STATS_ADDR_LO', + 'regCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'regCP_PIPE_STATS_CONTROL', + 'regCP_PIPE_STATS_CONTROL_BASE_IDX', 'regCP_PQ_STATUS', + 'regCP_PQ_STATUS_BASE_IDX', 'regCP_PQ_WPTR_POLL_CNTL', + 'regCP_PQ_WPTR_POLL_CNTL1', 'regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX', + 'regCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'regCP_PRED_NOT_VISIBLE', + 'regCP_PRED_NOT_VISIBLE_BASE_IDX', 'regCP_PRIV_VIOLATION_ADDR', + 'regCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'regCP_PROCESS_QUANTUM', + 'regCP_PROCESS_QUANTUM_BASE_IDX', 'regCP_PWR_CNTL', + 'regCP_PWR_CNTL_BASE_IDX', 'regCP_RB0_ACTIVE', + 'regCP_RB0_ACTIVE_BASE_IDX', 'regCP_RB0_BASE', + 'regCP_RB0_BASE_BASE_IDX', 'regCP_RB0_BASE_HI', + 'regCP_RB0_BASE_HI_BASE_IDX', 'regCP_RB0_BUFSZ_MASK', + 'regCP_RB0_BUFSZ_MASK_BASE_IDX', 'regCP_RB0_CNTL', + 'regCP_RB0_CNTL_BASE_IDX', 'regCP_RB0_RPTR', + 'regCP_RB0_RPTR_ADDR', 'regCP_RB0_RPTR_ADDR_BASE_IDX', + 'regCP_RB0_RPTR_ADDR_HI', 'regCP_RB0_RPTR_ADDR_HI_BASE_IDX', + 'regCP_RB0_RPTR_BASE_IDX', 'regCP_RB0_WPTR', + 'regCP_RB0_WPTR_BASE_IDX', 'regCP_RB0_WPTR_HI', + 'regCP_RB0_WPTR_HI_BASE_IDX', 'regCP_RB1_ACTIVE', + 'regCP_RB1_ACTIVE_BASE_IDX', 'regCP_RB1_BASE', + 'regCP_RB1_BASE_BASE_IDX', 'regCP_RB1_BASE_HI', + 'regCP_RB1_BASE_HI_BASE_IDX', 'regCP_RB1_BUFSZ_MASK', + 'regCP_RB1_BUFSZ_MASK_BASE_IDX', 'regCP_RB1_CNTL', + 'regCP_RB1_CNTL_BASE_IDX', 'regCP_RB1_RPTR', + 'regCP_RB1_RPTR_ADDR', 'regCP_RB1_RPTR_ADDR_BASE_IDX', + 'regCP_RB1_RPTR_ADDR_HI', 'regCP_RB1_RPTR_ADDR_HI_BASE_IDX', + 'regCP_RB1_RPTR_BASE_IDX', 'regCP_RB1_WPTR', + 'regCP_RB1_WPTR_BASE_IDX', 'regCP_RB1_WPTR_HI', + 'regCP_RB1_WPTR_HI_BASE_IDX', 'regCP_RB_ACTIVE', + 'regCP_RB_ACTIVE_BASE_IDX', 'regCP_RB_BASE', + 'regCP_RB_BASE_BASE_IDX', 'regCP_RB_BUFSZ_MASK', + 'regCP_RB_BUFSZ_MASK_BASE_IDX', 'regCP_RB_CNTL', + 'regCP_RB_CNTL_BASE_IDX', 'regCP_RB_DOORBELL_CLEAR', + 'regCP_RB_DOORBELL_CLEAR_BASE_IDX', 'regCP_RB_DOORBELL_CONTROL', + 'regCP_RB_DOORBELL_CONTROL_BASE_IDX', + 'regCP_RB_DOORBELL_RANGE_LOWER', + 'regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX', + 'regCP_RB_DOORBELL_RANGE_UPPER', + 'regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_RB_OFFSET', + 'regCP_RB_OFFSET_BASE_IDX', 'regCP_RB_RPTR', 'regCP_RB_RPTR_ADDR', + 'regCP_RB_RPTR_ADDR_BASE_IDX', 'regCP_RB_RPTR_ADDR_HI', + 'regCP_RB_RPTR_ADDR_HI_BASE_IDX', 'regCP_RB_RPTR_BASE_IDX', + 'regCP_RB_RPTR_WR', 'regCP_RB_RPTR_WR_BASE_IDX', + 'regCP_RB_STATUS', 'regCP_RB_STATUS_BASE_IDX', 'regCP_RB_VMID', + 'regCP_RB_VMID_BASE_IDX', 'regCP_RB_WPTR', + 'regCP_RB_WPTR_BASE_IDX', 'regCP_RB_WPTR_DELAY', + 'regCP_RB_WPTR_DELAY_BASE_IDX', 'regCP_RB_WPTR_HI', + 'regCP_RB_WPTR_HI_BASE_IDX', 'regCP_RB_WPTR_POLL_ADDR_HI', + 'regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regCP_RB_WPTR_POLL_ADDR_LO', + 'regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', 'regCP_RB_WPTR_POLL_CNTL', + 'regCP_RB_WPTR_POLL_CNTL_BASE_IDX', 'regCP_RING0_PRIORITY', + 'regCP_RING0_PRIORITY_BASE_IDX', 'regCP_RING1_PRIORITY', + 'regCP_RING1_PRIORITY_BASE_IDX', 'regCP_RINGID', + 'regCP_RINGID_BASE_IDX', 'regCP_RING_PRIORITY_CNTS', + 'regCP_RING_PRIORITY_CNTS_BASE_IDX', 'regCP_ROQ1_THRESHOLDS', + 'regCP_ROQ1_THRESHOLDS_BASE_IDX', 'regCP_ROQ2_AVAIL', + 'regCP_ROQ2_AVAIL_BASE_IDX', 'regCP_ROQ2_THRESHOLDS', + 'regCP_ROQ2_THRESHOLDS_BASE_IDX', 'regCP_ROQ3_THRESHOLDS', + 'regCP_ROQ3_THRESHOLDS_BASE_IDX', 'regCP_ROQ_AVAIL', + 'regCP_ROQ_AVAIL_BASE_IDX', 'regCP_ROQ_DB_STAT', + 'regCP_ROQ_DB_STAT_BASE_IDX', 'regCP_ROQ_IB1_STAT', + 'regCP_ROQ_IB1_STAT_BASE_IDX', 'regCP_ROQ_IB2_STAT', + 'regCP_ROQ_IB2_STAT_BASE_IDX', 'regCP_ROQ_RB_STAT', + 'regCP_ROQ_RB_STAT_BASE_IDX', 'regCP_SAMPLE_STATUS', + 'regCP_SAMPLE_STATUS_BASE_IDX', 'regCP_SCRATCH_DATA', + 'regCP_SCRATCH_DATA_BASE_IDX', 'regCP_SCRATCH_INDEX', + 'regCP_SCRATCH_INDEX_BASE_IDX', 'regCP_SC_PSINVOC_COUNT0_HI', + 'regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX', + 'regCP_SC_PSINVOC_COUNT0_LO', + 'regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX', + 'regCP_SC_PSINVOC_COUNT1_HI', + 'regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX', + 'regCP_SC_PSINVOC_COUNT1_LO', + 'regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'regCP_SDMA_DMA_DONE', + 'regCP_SDMA_DMA_DONE_BASE_IDX', 'regCP_SD_CNTL', + 'regCP_SD_CNTL_BASE_IDX', 'regCP_SEM_WAIT_TIMER', + 'regCP_SEM_WAIT_TIMER_BASE_IDX', 'regCP_SIG_SEM_ADDR_HI', + 'regCP_SIG_SEM_ADDR_HI_BASE_IDX', 'regCP_SIG_SEM_ADDR_LO', + 'regCP_SIG_SEM_ADDR_LO_BASE_IDX', 'regCP_SOFT_RESET_CNTL', + 'regCP_SOFT_RESET_CNTL_BASE_IDX', 'regCP_STALLED_STAT1', + 'regCP_STALLED_STAT1_BASE_IDX', 'regCP_STALLED_STAT2', + 'regCP_STALLED_STAT2_BASE_IDX', 'regCP_STALLED_STAT3', + 'regCP_STALLED_STAT3_BASE_IDX', 'regCP_STAT', + 'regCP_STAT_BASE_IDX', 'regCP_STQ_AVAIL', + 'regCP_STQ_AVAIL_BASE_IDX', 'regCP_STQ_STAT', + 'regCP_STQ_STAT_BASE_IDX', 'regCP_STQ_THRESHOLDS', + 'regCP_STQ_THRESHOLDS_BASE_IDX', 'regCP_STQ_WR_STAT', + 'regCP_STQ_WR_STAT_BASE_IDX', 'regCP_ST_BASE_HI', + 'regCP_ST_BASE_HI_BASE_IDX', 'regCP_ST_BASE_LO', + 'regCP_ST_BASE_LO_BASE_IDX', 'regCP_ST_BUFSZ', + 'regCP_ST_BUFSZ_BASE_IDX', 'regCP_ST_CMD_BUFSZ', + 'regCP_ST_CMD_BUFSZ_BASE_IDX', 'regCP_SUSPEND_CNTL', + 'regCP_SUSPEND_CNTL_BASE_IDX', 'regCP_SUSPEND_RESUME_REQ', + 'regCP_SUSPEND_RESUME_REQ_BASE_IDX', 'regCP_VGT_ASINVOC_COUNT_HI', + 'regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_ASINVOC_COUNT_LO', + 'regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_CSINVOC_COUNT_HI', + 'regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_CSINVOC_COUNT_LO', + 'regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_DSINVOC_COUNT_HI', + 'regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_DSINVOC_COUNT_LO', + 'regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_GSINVOC_COUNT_HI', + 'regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_GSINVOC_COUNT_LO', + 'regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_GSPRIM_COUNT_HI', 'regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX', + 'regCP_VGT_GSPRIM_COUNT_LO', 'regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX', + 'regCP_VGT_HSINVOC_COUNT_HI', + 'regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_HSINVOC_COUNT_LO', + 'regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_IAPRIM_COUNT_HI', 'regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX', + 'regCP_VGT_IAPRIM_COUNT_LO', 'regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX', + 'regCP_VGT_IAVERT_COUNT_HI', 'regCP_VGT_IAVERT_COUNT_HI_BASE_IDX', + 'regCP_VGT_IAVERT_COUNT_LO', 'regCP_VGT_IAVERT_COUNT_LO_BASE_IDX', + 'regCP_VGT_VSINVOC_COUNT_HI', + 'regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_VSINVOC_COUNT_LO', + 'regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'regCP_VIRT_STATUS', + 'regCP_VIRT_STATUS_BASE_IDX', 'regCP_VMID', 'regCP_VMID_BASE_IDX', + 'regCP_VMID_PREEMPT', 'regCP_VMID_PREEMPT_BASE_IDX', + 'regCP_VMID_RESET', 'regCP_VMID_RESET_BASE_IDX', + 'regCP_VMID_STATUS', 'regCP_VMID_STATUS_BASE_IDX', + 'regCP_WAIT_REG_MEM_TIMEOUT', + 'regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'regCP_WAIT_SEM_ADDR_HI', + 'regCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'regCP_WAIT_SEM_ADDR_LO', + 'regCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'regDB_ALPHA_TO_MASK', + 'regDB_ALPHA_TO_MASK_BASE_IDX', 'regDB_CGTT_CLK_CTRL_0', + 'regDB_CGTT_CLK_CTRL_0_BASE_IDX', 'regDB_COUNT_CONTROL', + 'regDB_COUNT_CONTROL_BASE_IDX', 'regDB_CREDIT_LIMIT', + 'regDB_CREDIT_LIMIT_BASE_IDX', 'regDB_DEBUG', 'regDB_DEBUG2', + 'regDB_DEBUG2_BASE_IDX', 'regDB_DEBUG3', 'regDB_DEBUG3_BASE_IDX', + 'regDB_DEBUG4', 'regDB_DEBUG4_BASE_IDX', 'regDB_DEBUG5', + 'regDB_DEBUG5_BASE_IDX', 'regDB_DEBUG6', 'regDB_DEBUG6_BASE_IDX', + 'regDB_DEBUG7', 'regDB_DEBUG7_BASE_IDX', 'regDB_DEBUG_BASE_IDX', + 'regDB_DEPTH_BOUNDS_MAX', 'regDB_DEPTH_BOUNDS_MAX_BASE_IDX', + 'regDB_DEPTH_BOUNDS_MIN', 'regDB_DEPTH_BOUNDS_MIN_BASE_IDX', + 'regDB_DEPTH_CLEAR', 'regDB_DEPTH_CLEAR_BASE_IDX', + 'regDB_DEPTH_CONTROL', 'regDB_DEPTH_CONTROL_BASE_IDX', + 'regDB_DEPTH_SIZE_XY', 'regDB_DEPTH_SIZE_XY_BASE_IDX', + 'regDB_DEPTH_VIEW', 'regDB_DEPTH_VIEW_BASE_IDX', 'regDB_EQAA', + 'regDB_EQAA_BASE_IDX', 'regDB_EQUAD_STUTTER_CONTROL', + 'regDB_EQUAD_STUTTER_CONTROL_BASE_IDX', + 'regDB_ETILE_STUTTER_CONTROL', + 'regDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'regDB_EXCEPTION_CONTROL', + 'regDB_EXCEPTION_CONTROL_BASE_IDX', + 'regDB_FGCG_INTERFACES_CLK_CTRL', + 'regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX', + 'regDB_FGCG_SRAMS_CLK_CTRL', 'regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX', + 'regDB_FIFO_DEPTH1', 'regDB_FIFO_DEPTH1_BASE_IDX', + 'regDB_FIFO_DEPTH2', 'regDB_FIFO_DEPTH2_BASE_IDX', + 'regDB_FIFO_DEPTH3', 'regDB_FIFO_DEPTH3_BASE_IDX', + 'regDB_FIFO_DEPTH4', 'regDB_FIFO_DEPTH4_BASE_IDX', + 'regDB_FREE_CACHELINES', 'regDB_FREE_CACHELINES_BASE_IDX', + 'regDB_HTILE_DATA_BASE', 'regDB_HTILE_DATA_BASE_BASE_IDX', + 'regDB_HTILE_DATA_BASE_HI', 'regDB_HTILE_DATA_BASE_HI_BASE_IDX', + 'regDB_HTILE_SURFACE', 'regDB_HTILE_SURFACE_BASE_IDX', + 'regDB_LAST_OF_BURST_CONFIG', + 'regDB_LAST_OF_BURST_CONFIG_BASE_IDX', + 'regDB_LQUAD_STUTTER_CONTROL', + 'regDB_LQUAD_STUTTER_CONTROL_BASE_IDX', + 'regDB_LTILE_STUTTER_CONTROL', + 'regDB_LTILE_STUTTER_CONTROL_BASE_IDX', + 'regDB_MEM_ARB_WATERMARKS', 'regDB_MEM_ARB_WATERMARKS_BASE_IDX', + 'regDB_OCCLUSION_COUNT0_HI', 'regDB_OCCLUSION_COUNT0_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT0_LOW', + 'regDB_OCCLUSION_COUNT0_LOW_BASE_IDX', + 'regDB_OCCLUSION_COUNT1_HI', 'regDB_OCCLUSION_COUNT1_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT1_LOW', + 'regDB_OCCLUSION_COUNT1_LOW_BASE_IDX', + 'regDB_OCCLUSION_COUNT2_HI', 'regDB_OCCLUSION_COUNT2_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT2_LOW', + 'regDB_OCCLUSION_COUNT2_LOW_BASE_IDX', + 'regDB_OCCLUSION_COUNT3_HI', 'regDB_OCCLUSION_COUNT3_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT3_LOW', + 'regDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'regDB_PERFCOUNTER0_HI', + 'regDB_PERFCOUNTER0_HI_BASE_IDX', 'regDB_PERFCOUNTER0_LO', + 'regDB_PERFCOUNTER0_LO_BASE_IDX', 'regDB_PERFCOUNTER0_SELECT', + 'regDB_PERFCOUNTER0_SELECT1', + 'regDB_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regDB_PERFCOUNTER0_SELECT_BASE_IDX', 'regDB_PERFCOUNTER1_HI', + 'regDB_PERFCOUNTER1_HI_BASE_IDX', 'regDB_PERFCOUNTER1_LO', + 'regDB_PERFCOUNTER1_LO_BASE_IDX', 'regDB_PERFCOUNTER1_SELECT', + 'regDB_PERFCOUNTER1_SELECT1', + 'regDB_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regDB_PERFCOUNTER1_SELECT_BASE_IDX', 'regDB_PERFCOUNTER2_HI', + 'regDB_PERFCOUNTER2_HI_BASE_IDX', 'regDB_PERFCOUNTER2_LO', + 'regDB_PERFCOUNTER2_LO_BASE_IDX', 'regDB_PERFCOUNTER2_SELECT', + 'regDB_PERFCOUNTER2_SELECT_BASE_IDX', 'regDB_PERFCOUNTER3_HI', + 'regDB_PERFCOUNTER3_HI_BASE_IDX', 'regDB_PERFCOUNTER3_LO', + 'regDB_PERFCOUNTER3_LO_BASE_IDX', 'regDB_PERFCOUNTER3_SELECT', + 'regDB_PERFCOUNTER3_SELECT_BASE_IDX', 'regDB_PRELOAD_CONTROL', + 'regDB_PRELOAD_CONTROL_BASE_IDX', 'regDB_RENDER_CONTROL', + 'regDB_RENDER_CONTROL_BASE_IDX', 'regDB_RENDER_OVERRIDE', + 'regDB_RENDER_OVERRIDE2', 'regDB_RENDER_OVERRIDE2_BASE_IDX', + 'regDB_RENDER_OVERRIDE_BASE_IDX', 'regDB_RESERVED_REG_1', + 'regDB_RESERVED_REG_1_BASE_IDX', 'regDB_RESERVED_REG_2', + 'regDB_RESERVED_REG_2_BASE_IDX', 'regDB_RESERVED_REG_3', + 'regDB_RESERVED_REG_3_BASE_IDX', 'regDB_RING_CONTROL', + 'regDB_RING_CONTROL_BASE_IDX', 'regDB_RMI_L2_CACHE_CONTROL', + 'regDB_RMI_L2_CACHE_CONTROL_BASE_IDX', 'regDB_SHADER_CONTROL', + 'regDB_SHADER_CONTROL_BASE_IDX', 'regDB_SRESULTS_COMPARE_STATE0', + 'regDB_SRESULTS_COMPARE_STATE0_BASE_IDX', + 'regDB_SRESULTS_COMPARE_STATE1', + 'regDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'regDB_STENCILREFMASK', + 'regDB_STENCILREFMASK_BASE_IDX', 'regDB_STENCILREFMASK_BF', + 'regDB_STENCILREFMASK_BF_BASE_IDX', 'regDB_STENCIL_CLEAR', + 'regDB_STENCIL_CLEAR_BASE_IDX', 'regDB_STENCIL_CONTROL', + 'regDB_STENCIL_CONTROL_BASE_IDX', 'regDB_STENCIL_INFO', + 'regDB_STENCIL_INFO_BASE_IDX', 'regDB_STENCIL_READ_BASE', + 'regDB_STENCIL_READ_BASE_BASE_IDX', 'regDB_STENCIL_READ_BASE_HI', + 'regDB_STENCIL_READ_BASE_HI_BASE_IDX', 'regDB_STENCIL_WRITE_BASE', + 'regDB_STENCIL_WRITE_BASE_BASE_IDX', + 'regDB_STENCIL_WRITE_BASE_HI', + 'regDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'regDB_SUBTILE_CONTROL', + 'regDB_SUBTILE_CONTROL_BASE_IDX', 'regDB_WATERMARKS', + 'regDB_WATERMARKS_BASE_IDX', 'regDB_Z_INFO', + 'regDB_Z_INFO_BASE_IDX', 'regDB_Z_READ_BASE', + 'regDB_Z_READ_BASE_BASE_IDX', 'regDB_Z_READ_BASE_HI', + 'regDB_Z_READ_BASE_HI_BASE_IDX', 'regDB_Z_WRITE_BASE', + 'regDB_Z_WRITE_BASE_BASE_IDX', 'regDB_Z_WRITE_BASE_HI', + 'regDB_Z_WRITE_BASE_HI_BASE_IDX', 'regDIDT_EDC_CTRL', + 'regDIDT_EDC_CTRL_BASE_IDX', 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO', + 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX', + 'regDIDT_EDC_OVERFLOW', 'regDIDT_EDC_OVERFLOW_BASE_IDX', + 'regDIDT_EDC_ROLLING_POWER_DELTA', + 'regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX', + 'regDIDT_EDC_STALL_PATTERN_1_2', + 'regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX', + 'regDIDT_EDC_STALL_PATTERN_3_4', + 'regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX', + 'regDIDT_EDC_STALL_PATTERN_5_6', + 'regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX', + 'regDIDT_EDC_STALL_PATTERN_7', + 'regDIDT_EDC_STALL_PATTERN_7_BASE_IDX', 'regDIDT_EDC_STATUS', + 'regDIDT_EDC_STATUS_BASE_IDX', 'regDIDT_EDC_THRESHOLD', + 'regDIDT_EDC_THRESHOLD_BASE_IDX', 'regDIDT_EDC_THROTTLE_CTRL', + 'regDIDT_EDC_THROTTLE_CTRL_BASE_IDX', + 'regDIDT_INDEX_AUTO_INCR_EN', + 'regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'regDIDT_IND_DATA', + 'regDIDT_IND_DATA_BASE_IDX', 'regDIDT_IND_INDEX', + 'regDIDT_IND_INDEX_BASE_IDX', 'regDIDT_STALL_PATTERN_1_2', + 'regDIDT_STALL_PATTERN_1_2_BASE_IDX', 'regDIDT_STALL_PATTERN_3_4', + 'regDIDT_STALL_PATTERN_3_4_BASE_IDX', 'regDIDT_STALL_PATTERN_5_6', + 'regDIDT_STALL_PATTERN_5_6_BASE_IDX', 'regDIDT_STALL_PATTERN_7', + 'regDIDT_STALL_PATTERN_7_BASE_IDX', 'regDIDT_STALL_PATTERN_CTRL', + 'regDIDT_STALL_PATTERN_CTRL_BASE_IDX', 'regEDC_HYSTERESIS_CNTL', + 'regEDC_HYSTERESIS_CNTL_BASE_IDX', 'regEDC_HYSTERESIS_STAT', + 'regEDC_HYSTERESIS_STAT_BASE_IDX', 'regEDC_PERF_COUNTER', + 'regEDC_PERF_COUNTER_BASE_IDX', 'regEDC_STRETCH_NUM_PERF_COUNTER', + 'regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX', + 'regEDC_STRETCH_PERF_COUNTER', + 'regEDC_STRETCH_PERF_COUNTER_BASE_IDX', + 'regEDC_UNSTRETCH_PERF_COUNTER', + 'regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX', 'regGB_ADDR_CONFIG', + 'regGB_ADDR_CONFIG_BASE_IDX', 'regGB_ADDR_CONFIG_READ', + 'regGB_ADDR_CONFIG_READ_BASE_IDX', 'regGB_BACKEND_MAP', + 'regGB_BACKEND_MAP_BASE_IDX', 'regGB_EDC_MODE', + 'regGB_EDC_MODE_BASE_IDX', 'regGB_GPU_ID', + 'regGB_GPU_ID_BASE_IDX', 'regGCEA_DRAM_PAGE_BURST', + 'regGCEA_DRAM_PAGE_BURST_BASE_IDX', 'regGCEA_DRAM_RD_CAM_CNTL', + 'regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX', + 'regGCEA_DRAM_RD_CLI2GRP_MAP0', + 'regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_DRAM_RD_CLI2GRP_MAP1', + 'regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_DRAM_RD_GRP2VC_MAP', + 'regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_RD_LAZY', + 'regGCEA_DRAM_RD_LAZY_BASE_IDX', 'regGCEA_DRAM_RD_PRI_AGE', + 'regGCEA_DRAM_RD_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_RD_PRI_FIXED', + 'regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI1', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI2', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI3', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUEUING', + 'regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_URGENCY', + 'regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX', + 'regGCEA_DRAM_WR_CAM_CNTL', 'regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX', + 'regGCEA_DRAM_WR_CLI2GRP_MAP0', + 'regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_DRAM_WR_CLI2GRP_MAP1', + 'regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_DRAM_WR_GRP2VC_MAP', + 'regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_WR_LAZY', + 'regGCEA_DRAM_WR_LAZY_BASE_IDX', 'regGCEA_DRAM_WR_PRI_AGE', + 'regGCEA_DRAM_WR_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_WR_PRI_FIXED', + 'regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI1', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI2', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI3', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUEUING', + 'regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_URGENCY', + 'regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'regGCEA_DSM_CNTL', + 'regGCEA_DSM_CNTL2', 'regGCEA_DSM_CNTL2A', + 'regGCEA_DSM_CNTL2A_BASE_IDX', 'regGCEA_DSM_CNTL2B', + 'regGCEA_DSM_CNTL2B_BASE_IDX', 'regGCEA_DSM_CNTL2_BASE_IDX', + 'regGCEA_DSM_CNTLA', 'regGCEA_DSM_CNTLA_BASE_IDX', + 'regGCEA_DSM_CNTLB', 'regGCEA_DSM_CNTLB_BASE_IDX', + 'regGCEA_DSM_CNTL_BASE_IDX', 'regGCEA_EDC_CNT', + 'regGCEA_EDC_CNT2', 'regGCEA_EDC_CNT2_BASE_IDX', + 'regGCEA_EDC_CNT3', 'regGCEA_EDC_CNT3_BASE_IDX', + 'regGCEA_EDC_CNT_BASE_IDX', 'regGCEA_ERR_STATUS', + 'regGCEA_ERR_STATUS_BASE_IDX', 'regGCEA_GL2C_XBR_CREDITS', + 'regGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'regGCEA_GL2C_XBR_MAXBURST', + 'regGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'regGCEA_ICG_CTRL', + 'regGCEA_ICG_CTRL_BASE_IDX', 'regGCEA_IO_GROUP_BURST', + 'regGCEA_IO_GROUP_BURST_BASE_IDX', 'regGCEA_IO_RD_CLI2GRP_MAP0', + 'regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_IO_RD_CLI2GRP_MAP1', + 'regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_IO_RD_COMBINE_FLUSH', + 'regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_RD_PRI_AGE', + 'regGCEA_IO_RD_PRI_AGE_BASE_IDX', 'regGCEA_IO_RD_PRI_FIXED', + 'regGCEA_IO_RD_PRI_FIXED_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUANT_PRI1', + 'regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUANT_PRI2', + 'regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUANT_PRI3', + 'regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUEUING', 'regGCEA_IO_RD_PRI_QUEUING_BASE_IDX', + 'regGCEA_IO_RD_PRI_URGENCY', 'regGCEA_IO_RD_PRI_URGENCY_BASE_IDX', + 'regGCEA_IO_RD_PRI_URGENCY_MASKING', + 'regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX', + 'regGCEA_IO_WR_CLI2GRP_MAP0', + 'regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_IO_WR_CLI2GRP_MAP1', + 'regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_IO_WR_COMBINE_FLUSH', + 'regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_WR_PRI_AGE', + 'regGCEA_IO_WR_PRI_AGE_BASE_IDX', 'regGCEA_IO_WR_PRI_FIXED', + 'regGCEA_IO_WR_PRI_FIXED_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUANT_PRI1', + 'regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUANT_PRI2', + 'regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUANT_PRI3', + 'regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUEUING', 'regGCEA_IO_WR_PRI_QUEUING_BASE_IDX', + 'regGCEA_IO_WR_PRI_URGENCY', 'regGCEA_IO_WR_PRI_URGENCY_BASE_IDX', + 'regGCEA_IO_WR_PRI_URGENCY_MASKING', + 'regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX', + 'regGCEA_LATENCY_SAMPLING', 'regGCEA_LATENCY_SAMPLING_BASE_IDX', + 'regGCEA_MAM_CTRL', 'regGCEA_MAM_CTRL2', + 'regGCEA_MAM_CTRL2_BASE_IDX', 'regGCEA_MAM_CTRL_BASE_IDX', + 'regGCEA_MISC', 'regGCEA_MISC2', 'regGCEA_MISC2_BASE_IDX', + 'regGCEA_MISC_BASE_IDX', 'regGCEA_PERFCOUNTER0_CFG', + 'regGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER1_CFG', + 'regGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER2_HI', + 'regGCEA_PERFCOUNTER2_HI_BASE_IDX', 'regGCEA_PERFCOUNTER2_LO', + 'regGCEA_PERFCOUNTER2_LO_BASE_IDX', 'regGCEA_PERFCOUNTER2_MODE', + 'regGCEA_PERFCOUNTER2_MODE_BASE_IDX', + 'regGCEA_PERFCOUNTER2_SELECT', 'regGCEA_PERFCOUNTER2_SELECT1', + 'regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'regGCEA_PERFCOUNTER_HI', + 'regGCEA_PERFCOUNTER_HI_BASE_IDX', 'regGCEA_PERFCOUNTER_LO', + 'regGCEA_PERFCOUNTER_LO_BASE_IDX', + 'regGCEA_PERFCOUNTER_RSLT_CNTL', + 'regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGCEA_PROBE_CNTL', + 'regGCEA_PROBE_CNTL_BASE_IDX', 'regGCEA_PROBE_MAP', + 'regGCEA_PROBE_MAP_BASE_IDX', 'regGCEA_RRET_MEM_RESERVE', + 'regGCEA_RRET_MEM_RESERVE_BASE_IDX', 'regGCEA_SDP_ARB_FINAL', + 'regGCEA_SDP_ARB_FINAL_BASE_IDX', 'regGCEA_SDP_CREDITS', + 'regGCEA_SDP_CREDITS_BASE_IDX', 'regGCEA_SDP_ENABLE', + 'regGCEA_SDP_ENABLE_BASE_IDX', 'regGCEA_SDP_IO_PRIORITY', + 'regGCEA_SDP_IO_PRIORITY_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE0', + 'regGCEA_SDP_TAG_RESERVE0_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE1', + 'regGCEA_SDP_TAG_RESERVE1_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE0', + 'regGCEA_SDP_VCC_RESERVE0_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE1', + 'regGCEA_SDP_VCC_RESERVE1_BASE_IDX', 'regGCMC_MEM_POWER_LS', + 'regGCMC_MEM_POWER_LS_BASE_IDX', 'regGCMC_VM_AGP_BASE', + 'regGCMC_VM_AGP_BASE_BASE_IDX', 'regGCMC_VM_AGP_BOT', + 'regGCMC_VM_AGP_BOT_BASE_IDX', 'regGCMC_VM_AGP_TOP', + 'regGCMC_VM_AGP_TOP_BASE_IDX', 'regGCMC_VM_APT_CNTL', + 'regGCMC_VM_APT_CNTL_BASE_IDX', + 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END', + 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', + 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START', + 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', + 'regGCMC_VM_FB_LOCATION_BASE', + 'regGCMC_VM_FB_LOCATION_BASE_BASE_IDX', + 'regGCMC_VM_FB_LOCATION_TOP', + 'regGCMC_VM_FB_LOCATION_TOP_BASE_IDX', + 'regGCMC_VM_FB_NOALLOC_CNTL', + 'regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX', 'regGCMC_VM_FB_OFFSET', + 'regGCMC_VM_FB_OFFSET_BASE_IDX', 'regGCMC_VM_FB_SIZE_OFFSET_VF0', + 'regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF1', 'regGCMC_VM_FB_SIZE_OFFSET_VF10', + 'regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF11', + 'regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF12', + 'regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF13', + 'regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF14', + 'regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF15', + 'regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF2', + 'regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF3', + 'regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF4', + 'regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF5', + 'regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF6', + 'regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF7', + 'regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF8', + 'regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', + 'regGCMC_VM_FB_SIZE_OFFSET_VF9', + 'regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER0_CFG', + 'regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER1_CFG', + 'regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER2_CFG', + 'regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER3_CFG', + 'regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER4_CFG', + 'regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER5_CFG', + 'regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER6_CFG', + 'regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER7_CFG', + 'regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER_HI', + 'regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER_LO', + 'regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', + 'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL', + 'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regGCMC_VM_LOCAL_FB_ADDRESS_END', + 'regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX', + 'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL', + 'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX', + 'regGCMC_VM_LOCAL_FB_ADDRESS_START', + 'regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX', + 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END', + 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX', + 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START', + 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_0', 'regGCMC_VM_MARC_BASE_HI_0_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_1', 'regGCMC_VM_MARC_BASE_HI_10', + 'regGCMC_VM_MARC_BASE_HI_10_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_11', + 'regGCMC_VM_MARC_BASE_HI_11_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_12', + 'regGCMC_VM_MARC_BASE_HI_12_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_13', + 'regGCMC_VM_MARC_BASE_HI_13_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_14', + 'regGCMC_VM_MARC_BASE_HI_14_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_15', + 'regGCMC_VM_MARC_BASE_HI_15_BASE_IDX', + 'regGCMC_VM_MARC_BASE_HI_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_2', + 'regGCMC_VM_MARC_BASE_HI_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_3', + 'regGCMC_VM_MARC_BASE_HI_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_4', + 'regGCMC_VM_MARC_BASE_HI_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_5', + 'regGCMC_VM_MARC_BASE_HI_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_6', + 'regGCMC_VM_MARC_BASE_HI_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_7', + 'regGCMC_VM_MARC_BASE_HI_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_8', + 'regGCMC_VM_MARC_BASE_HI_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_9', + 'regGCMC_VM_MARC_BASE_HI_9_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_0', + 'regGCMC_VM_MARC_BASE_LO_0_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_1', + 'regGCMC_VM_MARC_BASE_LO_10', + 'regGCMC_VM_MARC_BASE_LO_10_BASE_IDX', + 'regGCMC_VM_MARC_BASE_LO_11', + 'regGCMC_VM_MARC_BASE_LO_11_BASE_IDX', + 'regGCMC_VM_MARC_BASE_LO_12', + 'regGCMC_VM_MARC_BASE_LO_12_BASE_IDX', + 'regGCMC_VM_MARC_BASE_LO_13', + 'regGCMC_VM_MARC_BASE_LO_13_BASE_IDX', + 'regGCMC_VM_MARC_BASE_LO_14', + 'regGCMC_VM_MARC_BASE_LO_14_BASE_IDX', + 'regGCMC_VM_MARC_BASE_LO_15', + 'regGCMC_VM_MARC_BASE_LO_15_BASE_IDX', + 'regGCMC_VM_MARC_BASE_LO_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_2', + 'regGCMC_VM_MARC_BASE_LO_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_3', + 'regGCMC_VM_MARC_BASE_LO_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_4', + 'regGCMC_VM_MARC_BASE_LO_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_5', + 'regGCMC_VM_MARC_BASE_LO_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_6', + 'regGCMC_VM_MARC_BASE_LO_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_7', + 'regGCMC_VM_MARC_BASE_LO_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_8', + 'regGCMC_VM_MARC_BASE_LO_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_9', + 'regGCMC_VM_MARC_BASE_LO_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_0', + 'regGCMC_VM_MARC_LEN_HI_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_1', + 'regGCMC_VM_MARC_LEN_HI_10', 'regGCMC_VM_MARC_LEN_HI_10_BASE_IDX', + 'regGCMC_VM_MARC_LEN_HI_11', 'regGCMC_VM_MARC_LEN_HI_11_BASE_IDX', + 'regGCMC_VM_MARC_LEN_HI_12', 'regGCMC_VM_MARC_LEN_HI_12_BASE_IDX', + 'regGCMC_VM_MARC_LEN_HI_13', 'regGCMC_VM_MARC_LEN_HI_13_BASE_IDX', + 'regGCMC_VM_MARC_LEN_HI_14', 'regGCMC_VM_MARC_LEN_HI_14_BASE_IDX', + 'regGCMC_VM_MARC_LEN_HI_15', 'regGCMC_VM_MARC_LEN_HI_15_BASE_IDX', + 'regGCMC_VM_MARC_LEN_HI_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_2', + 'regGCMC_VM_MARC_LEN_HI_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_3', + 'regGCMC_VM_MARC_LEN_HI_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_4', + 'regGCMC_VM_MARC_LEN_HI_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_5', + 'regGCMC_VM_MARC_LEN_HI_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_6', + 'regGCMC_VM_MARC_LEN_HI_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_7', + 'regGCMC_VM_MARC_LEN_HI_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_8', + 'regGCMC_VM_MARC_LEN_HI_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_9', + 'regGCMC_VM_MARC_LEN_HI_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_0', + 'regGCMC_VM_MARC_LEN_LO_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_1', + 'regGCMC_VM_MARC_LEN_LO_10', 'regGCMC_VM_MARC_LEN_LO_10_BASE_IDX', + 'regGCMC_VM_MARC_LEN_LO_11', 'regGCMC_VM_MARC_LEN_LO_11_BASE_IDX', + 'regGCMC_VM_MARC_LEN_LO_12', 'regGCMC_VM_MARC_LEN_LO_12_BASE_IDX', + 'regGCMC_VM_MARC_LEN_LO_13', 'regGCMC_VM_MARC_LEN_LO_13_BASE_IDX', + 'regGCMC_VM_MARC_LEN_LO_14', 'regGCMC_VM_MARC_LEN_LO_14_BASE_IDX', + 'regGCMC_VM_MARC_LEN_LO_15', 'regGCMC_VM_MARC_LEN_LO_15_BASE_IDX', + 'regGCMC_VM_MARC_LEN_LO_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_2', + 'regGCMC_VM_MARC_LEN_LO_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_3', + 'regGCMC_VM_MARC_LEN_LO_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_4', + 'regGCMC_VM_MARC_LEN_LO_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_5', + 'regGCMC_VM_MARC_LEN_LO_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_6', + 'regGCMC_VM_MARC_LEN_LO_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_7', + 'regGCMC_VM_MARC_LEN_LO_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_8', + 'regGCMC_VM_MARC_LEN_LO_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_9', + 'regGCMC_VM_MARC_LEN_LO_9_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_0', + 'regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_1', + 'regGCMC_VM_MARC_PFVF_MAPPING_10', + 'regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_11', + 'regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_12', + 'regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_13', + 'regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_14', + 'regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_15', + 'regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_2', + 'regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_3', + 'regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_4', + 'regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_5', + 'regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_6', + 'regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_7', + 'regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_8', + 'regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX', + 'regGCMC_VM_MARC_PFVF_MAPPING_9', + 'regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_0', + 'regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_1', 'regGCMC_VM_MARC_RELOC_HI_10', + 'regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_11', + 'regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_12', + 'regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_13', + 'regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_14', + 'regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_15', + 'regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_2', + 'regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_3', + 'regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_4', + 'regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_5', + 'regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_6', + 'regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_7', + 'regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_8', + 'regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_HI_9', + 'regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_0', + 'regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_1', 'regGCMC_VM_MARC_RELOC_LO_10', + 'regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_11', + 'regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_12', + 'regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_13', + 'regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_14', + 'regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_15', + 'regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_2', + 'regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_3', + 'regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_4', + 'regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_5', + 'regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_6', + 'regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_7', + 'regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_8', + 'regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX', + 'regGCMC_VM_MARC_RELOC_LO_9', + 'regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX', + 'regGCMC_VM_MX_L1_TLB_CNTL', 'regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX', + 'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2', + 'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX', + 'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1', + 'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX', + 'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2', + 'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX', + 'regGCMC_VM_STEERING', 'regGCMC_VM_STEERING_BASE_IDX', + 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', + 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', + 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', + 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', + 'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR', + 'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', + 'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR', + 'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', + 'regGCRD_CREDIT_SAFE', 'regGCRD_CREDIT_SAFE_BASE_IDX', + 'regGCRD_SA0_TARGETS_DISABLE', + 'regGCRD_SA0_TARGETS_DISABLE_BASE_IDX', + 'regGCRD_SA1_TARGETS_DISABLE', + 'regGCRD_SA1_TARGETS_DISABLE_BASE_IDX', 'regGCR_CMD_STATUS', + 'regGCR_CMD_STATUS_BASE_IDX', 'regGCR_GENERAL_CNTL', + 'regGCR_GENERAL_CNTL_BASE_IDX', 'regGCR_PERFCOUNTER0_HI', + 'regGCR_PERFCOUNTER0_HI_BASE_IDX', 'regGCR_PERFCOUNTER0_LO', + 'regGCR_PERFCOUNTER0_LO_BASE_IDX', 'regGCR_PERFCOUNTER0_SELECT', + 'regGCR_PERFCOUNTER0_SELECT1', + 'regGCR_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'regGCR_PERFCOUNTER1_HI', + 'regGCR_PERFCOUNTER1_HI_BASE_IDX', 'regGCR_PERFCOUNTER1_LO', + 'regGCR_PERFCOUNTER1_LO_BASE_IDX', 'regGCR_PERFCOUNTER1_SELECT', + 'regGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'regGCR_PIO_CNTL', + 'regGCR_PIO_CNTL_BASE_IDX', 'regGCR_PIO_DATA', + 'regGCR_PIO_DATA_BASE_IDX', 'regGCR_SPARE', + 'regGCR_SPARE_BASE_IDX', 'regGCUTCL2_CGTT_BUSY_CTRL', + 'regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX', + 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC', + 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX', + 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC', + 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX', + 'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC', + 'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX', + 'regGCUTCL2_GROUP_RET_FAULT_STATUS', + 'regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX', + 'regGCUTCL2_HARVEST_BYPASS_GROUPS', + 'regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX', + 'regGCUTCL2_ICG_CTRL', 'regGCUTCL2_ICG_CTRL_BASE_IDX', + 'regGCUTCL2_PERFCOUNTER0_CFG', + 'regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX', + 'regGCUTCL2_PERFCOUNTER1_CFG', + 'regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX', + 'regGCUTCL2_PERFCOUNTER2_CFG', + 'regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX', + 'regGCUTCL2_PERFCOUNTER3_CFG', + 'regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX', + 'regGCUTCL2_PERFCOUNTER_HI', 'regGCUTCL2_PERFCOUNTER_HI_BASE_IDX', + 'regGCUTCL2_PERFCOUNTER_LO', 'regGCUTCL2_PERFCOUNTER_LO_BASE_IDX', + 'regGCUTCL2_PERFCOUNTER_RSLT_CNTL', + 'regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID', + 'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', + 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', + 'regGCUTC_TRANSLATION_FAULT_CNTL0', + 'regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX', + 'regGCUTC_TRANSLATION_FAULT_CNTL1', + 'regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX', + 'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT', + 'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_0_HI', + 'regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_0_LO', + 'regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_0_MODE', + 'regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_0_SELECT', + 'regGCVML2_PERFCOUNTER2_0_SELECT1', + 'regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_1_HI', + 'regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_1_LO', + 'regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_1_MODE', + 'regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_1_SELECT', + 'regGCVML2_PERFCOUNTER2_1_SELECT1', + 'regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX', + 'regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX', + 'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ', + 'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX', + 'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT', + 'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX', + 'regGCVML2_WALKER_MACRO_THROTTLE_TIME', + 'regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX', + 'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT', + 'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX', + 'regGCVML2_WALKER_MICRO_THROTTLE_TIME', + 'regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX', + 'regGCVM_CONTEXT0_CNTL', 'regGCVM_CONTEXT0_CNTL_BASE_IDX', + 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT10_CNTL', 'regGCVM_CONTEXT10_CNTL_BASE_IDX', + 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT11_CNTL', 'regGCVM_CONTEXT11_CNTL_BASE_IDX', + 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT12_CNTL', 'regGCVM_CONTEXT12_CNTL_BASE_IDX', + 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT13_CNTL', 'regGCVM_CONTEXT13_CNTL_BASE_IDX', + 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT14_CNTL', 'regGCVM_CONTEXT14_CNTL_BASE_IDX', + 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT15_CNTL', 'regGCVM_CONTEXT15_CNTL_BASE_IDX', + 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT1_CNTL', 'regGCVM_CONTEXT1_CNTL_BASE_IDX', + 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT2_CNTL', 'regGCVM_CONTEXT2_CNTL_BASE_IDX', + 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT3_CNTL', 'regGCVM_CONTEXT3_CNTL_BASE_IDX', + 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT4_CNTL', 'regGCVM_CONTEXT4_CNTL_BASE_IDX', + 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT5_CNTL', 'regGCVM_CONTEXT5_CNTL_BASE_IDX', + 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT6_CNTL', 'regGCVM_CONTEXT6_CNTL_BASE_IDX', + 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT7_CNTL', 'regGCVM_CONTEXT7_CNTL_BASE_IDX', + 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT8_CNTL', 'regGCVM_CONTEXT8_CNTL_BASE_IDX', + 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT9_CNTL', 'regGCVM_CONTEXT9_CNTL_BASE_IDX', + 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', + 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', + 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', + 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', + 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', + 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', + 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regGCVM_CONTEXTS_DISABLE', 'regGCVM_CONTEXTS_DISABLE_BASE_IDX', + 'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32', + 'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', + 'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32', + 'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', + 'regGCVM_DUMMY_PAGE_FAULT_CNTL', + 'regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', + 'regGCVM_INVALIDATE_CNTL', 'regGCVM_INVALIDATE_CNTL_BASE_IDX', + 'regGCVM_INVALIDATE_ENG0_ACK', + 'regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG0_REQ', + 'regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG0_SEM', + 'regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG10_ACK', + 'regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG10_REQ', + 'regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG10_SEM', + 'regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG11_ACK', + 'regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG11_REQ', + 'regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG11_SEM', + 'regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG12_ACK', + 'regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG12_REQ', + 'regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG12_SEM', + 'regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG13_ACK', + 'regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG13_REQ', + 'regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG13_SEM', + 'regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG14_ACK', + 'regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG14_REQ', + 'regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG14_SEM', + 'regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG15_ACK', + 'regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG15_REQ', + 'regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG15_SEM', + 'regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG16_ACK', + 'regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG16_REQ', + 'regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG16_SEM', + 'regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG17_ACK', + 'regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG17_REQ', + 'regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG17_SEM', + 'regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG1_ACK', + 'regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG1_REQ', + 'regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG1_SEM', + 'regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG2_ACK', + 'regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG2_REQ', + 'regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG2_SEM', + 'regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG3_ACK', + 'regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG3_REQ', + 'regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG3_SEM', + 'regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG4_ACK', + 'regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG4_REQ', + 'regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG4_SEM', + 'regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG5_ACK', + 'regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG5_REQ', + 'regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG5_SEM', + 'regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG6_ACK', + 'regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG6_REQ', + 'regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG6_SEM', + 'regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG7_ACK', + 'regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG7_REQ', + 'regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG7_SEM', + 'regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG8_ACK', + 'regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG8_REQ', + 'regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG8_SEM', + 'regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX', + 'regGCVM_INVALIDATE_ENG9_ACK', + 'regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX', + 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', + 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', + 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', + 'regGCVM_INVALIDATE_ENG9_REQ', + 'regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX', + 'regGCVM_INVALIDATE_ENG9_SEM', + 'regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX', + 'regGCVM_L2_BANK_SELECT_MASKS', + 'regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX', + 'regGCVM_L2_BANK_SELECT_RESERVED_CID', + 'regGCVM_L2_BANK_SELECT_RESERVED_CID2', + 'regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', + 'regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', + 'regGCVM_L2_CACHE_PARITY_CNTL', + 'regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX', + 'regGCVM_L2_CGTT_BUSY_CTRL', 'regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX', + 'regGCVM_L2_CNTL', 'regGCVM_L2_CNTL2', + 'regGCVM_L2_CNTL2_BASE_IDX', 'regGCVM_L2_CNTL3', + 'regGCVM_L2_CNTL3_BASE_IDX', 'regGCVM_L2_CNTL4', + 'regGCVM_L2_CNTL4_BASE_IDX', 'regGCVM_L2_CNTL5', + 'regGCVM_L2_CNTL5_BASE_IDX', 'regGCVM_L2_CNTL_BASE_IDX', + 'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', + 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', + 'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', + 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', + 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', + 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', + 'regGCVM_L2_GCR_CNTL', 'regGCVM_L2_GCR_CNTL_BASE_IDX', + 'regGCVM_L2_ICG_CTRL', 'regGCVM_L2_ICG_CTRL_BASE_IDX', + 'regGCVM_L2_MM_GROUP_RT_CLASSES', + 'regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', + 'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32', + 'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32', + 'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_CNTL', + 'regGCVM_L2_PROTECTION_FAULT_CNTL2', + 'regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', + 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', + 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3', + 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4', + 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', + 'regGCVM_L2_PROTECTION_FAULT_STATUS', + 'regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', + 'regGCVM_L2_PTE_CACHE_DUMP_CNTL', + 'regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX', + 'regGCVM_L2_PTE_CACHE_DUMP_READ', + 'regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'regGCVM_L2_STATUS', + 'regGCVM_L2_STATUS_BASE_IDX', 'regGC_CAC_AGGR_GFXCLK_CYCLE', + 'regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regGC_CAC_AGGR_LOWER', + 'regGC_CAC_AGGR_LOWER_BASE_IDX', 'regGC_CAC_AGGR_UPPER', + 'regGC_CAC_AGGR_UPPER_BASE_IDX', 'regGC_CAC_CTRL_1', + 'regGC_CAC_CTRL_1_BASE_IDX', 'regGC_CAC_CTRL_2', + 'regGC_CAC_CTRL_2_BASE_IDX', 'regGC_CAC_IND_DATA', + 'regGC_CAC_IND_DATA_BASE_IDX', 'regGC_CAC_IND_INDEX', + 'regGC_CAC_IND_INDEX_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_0', + 'regGC_CAC_WEIGHT_CHC_0_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_1', + 'regGC_CAC_WEIGHT_CHC_1_BASE_IDX', 'regGC_CAC_WEIGHT_CP_0', + 'regGC_CAC_WEIGHT_CP_0_BASE_IDX', 'regGC_CAC_WEIGHT_CP_1', + 'regGC_CAC_WEIGHT_CP_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_0', + 'regGC_CAC_WEIGHT_EA_0_BASE_IDX', 'regGC_CAC_WEIGHT_EA_1', + 'regGC_CAC_WEIGHT_EA_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_2', + 'regGC_CAC_WEIGHT_EA_2_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_0', + 'regGC_CAC_WEIGHT_GDS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_1', + 'regGC_CAC_WEIGHT_GDS_1_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_2', + 'regGC_CAC_WEIGHT_GDS_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_0', + 'regGC_CAC_WEIGHT_GE_0_BASE_IDX', 'regGC_CAC_WEIGHT_GE_1', + 'regGC_CAC_WEIGHT_GE_1_BASE_IDX', 'regGC_CAC_WEIGHT_GE_2', + 'regGC_CAC_WEIGHT_GE_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_3', + 'regGC_CAC_WEIGHT_GE_3_BASE_IDX', 'regGC_CAC_WEIGHT_GE_4', + 'regGC_CAC_WEIGHT_GE_4_BASE_IDX', 'regGC_CAC_WEIGHT_GE_5', + 'regGC_CAC_WEIGHT_GE_5_BASE_IDX', 'regGC_CAC_WEIGHT_GE_6', + 'regGC_CAC_WEIGHT_GE_6_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_0', + 'regGC_CAC_WEIGHT_GL2C_0_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_1', + 'regGC_CAC_WEIGHT_GL2C_1_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_2', + 'regGC_CAC_WEIGHT_GL2C_2_BASE_IDX', 'regGC_CAC_WEIGHT_GRBM_0', + 'regGC_CAC_WEIGHT_GRBM_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_0', + 'regGC_CAC_WEIGHT_GUS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_1', + 'regGC_CAC_WEIGHT_GUS_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_0', + 'regGC_CAC_WEIGHT_PH_0_BASE_IDX', 'regGC_CAC_WEIGHT_PH_1', + 'regGC_CAC_WEIGHT_PH_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_2', + 'regGC_CAC_WEIGHT_PH_2_BASE_IDX', 'regGC_CAC_WEIGHT_PH_3', + 'regGC_CAC_WEIGHT_PH_3_BASE_IDX', 'regGC_CAC_WEIGHT_PMM_0', + 'regGC_CAC_WEIGHT_PMM_0_BASE_IDX', 'regGC_CAC_WEIGHT_RLC_0', + 'regGC_CAC_WEIGHT_RLC_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_0', + 'regGC_CAC_WEIGHT_SDMA_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_1', + 'regGC_CAC_WEIGHT_SDMA_1_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_2', + 'regGC_CAC_WEIGHT_SDMA_2_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_3', + 'regGC_CAC_WEIGHT_SDMA_3_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_4', + 'regGC_CAC_WEIGHT_SDMA_4_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_5', + 'regGC_CAC_WEIGHT_SDMA_5_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_0', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_1', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_2', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_3', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_4', + 'regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_VML2_0', + 'regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_VML2_1', + 'regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_VML2_2', + 'regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_WALKER_0', + 'regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_WALKER_1', + 'regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX', + 'regGC_CAC_WEIGHT_UTCL2_WALKER_2', + 'regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX', + 'regGC_EDC_CLK_MONITOR_CTRL', + 'regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX', 'regGC_EDC_CTRL', + 'regGC_EDC_CTRL_BASE_IDX', 'regGC_EDC_OVERFLOW', + 'regGC_EDC_OVERFLOW_BASE_IDX', 'regGC_EDC_ROLLING_POWER_DELTA', + 'regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'regGC_EDC_STATUS', + 'regGC_EDC_STATUS_BASE_IDX', 'regGC_EDC_STRETCH_CTRL', + 'regGC_EDC_STRETCH_CTRL_BASE_IDX', 'regGC_EDC_STRETCH_THRESHOLD', + 'regGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'regGC_EDC_THRESHOLD', + 'regGC_EDC_THRESHOLD_BASE_IDX', 'regGC_IH_COOKIE_0_PTR', + 'regGC_IH_COOKIE_0_PTR_BASE_IDX', 'regGC_THROTTLE_CTRL', + 'regGC_THROTTLE_CTRL1', 'regGC_THROTTLE_CTRL1_BASE_IDX', + 'regGC_THROTTLE_CTRL_BASE_IDX', 'regGC_THROTTLE_STATUS', + 'regGC_THROTTLE_STATUS_BASE_IDX', 'regGC_USER_PRIM_CONFIG', + 'regGC_USER_PRIM_CONFIG_BASE_IDX', + 'regGC_USER_RB_BACKEND_DISABLE', + 'regGC_USER_RB_BACKEND_DISABLE_BASE_IDX', + 'regGC_USER_RB_REDUNDANCY', 'regGC_USER_RB_REDUNDANCY_BASE_IDX', + 'regGC_USER_RMI_REDUNDANCY', 'regGC_USER_RMI_REDUNDANCY_BASE_IDX', + 'regGC_USER_SA_UNIT_DISABLE', + 'regGC_USER_SA_UNIT_DISABLE_BASE_IDX', + 'regGC_USER_SHADER_ARRAY_CONFIG', + 'regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX', + 'regGC_USER_SHADER_RATE_CONFIG', + 'regGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'regGDS_ATOM_BASE', + 'regGDS_ATOM_BASE_BASE_IDX', 'regGDS_ATOM_CNTL', + 'regGDS_ATOM_CNTL_BASE_IDX', 'regGDS_ATOM_COMPLETE', + 'regGDS_ATOM_COMPLETE_BASE_IDX', 'regGDS_ATOM_DST', + 'regGDS_ATOM_DST_BASE_IDX', 'regGDS_ATOM_OFFSET0', + 'regGDS_ATOM_OFFSET0_BASE_IDX', 'regGDS_ATOM_OFFSET1', + 'regGDS_ATOM_OFFSET1_BASE_IDX', 'regGDS_ATOM_OP', + 'regGDS_ATOM_OP_BASE_IDX', 'regGDS_ATOM_READ0', + 'regGDS_ATOM_READ0_BASE_IDX', 'regGDS_ATOM_READ0_U', + 'regGDS_ATOM_READ0_U_BASE_IDX', 'regGDS_ATOM_READ1', + 'regGDS_ATOM_READ1_BASE_IDX', 'regGDS_ATOM_READ1_U', + 'regGDS_ATOM_READ1_U_BASE_IDX', 'regGDS_ATOM_SIZE', + 'regGDS_ATOM_SIZE_BASE_IDX', 'regGDS_ATOM_SRC0', + 'regGDS_ATOM_SRC0_BASE_IDX', 'regGDS_ATOM_SRC0_U', + 'regGDS_ATOM_SRC0_U_BASE_IDX', 'regGDS_ATOM_SRC1', + 'regGDS_ATOM_SRC1_BASE_IDX', 'regGDS_ATOM_SRC1_U', + 'regGDS_ATOM_SRC1_U_BASE_IDX', 'regGDS_CNTL_STATUS', + 'regGDS_CNTL_STATUS_BASE_IDX', 'regGDS_COMPUTE_MAX_WAVE_ID', + 'regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'regGDS_CONFIG', + 'regGDS_CONFIG_BASE_IDX', 'regGDS_CS_CTXSW_CNT0', + 'regGDS_CS_CTXSW_CNT0_BASE_IDX', 'regGDS_CS_CTXSW_CNT1', + 'regGDS_CS_CTXSW_CNT1_BASE_IDX', 'regGDS_CS_CTXSW_CNT2', + 'regGDS_CS_CTXSW_CNT2_BASE_IDX', 'regGDS_CS_CTXSW_CNT3', + 'regGDS_CS_CTXSW_CNT3_BASE_IDX', 'regGDS_CS_CTXSW_STATUS', + 'regGDS_CS_CTXSW_STATUS_BASE_IDX', 'regGDS_DSM_CNTL', + 'regGDS_DSM_CNTL2', 'regGDS_DSM_CNTL2_BASE_IDX', + 'regGDS_DSM_CNTL_BASE_IDX', 'regGDS_EDC_CNT', + 'regGDS_EDC_CNT_BASE_IDX', 'regGDS_EDC_GRBM_CNT', + 'regGDS_EDC_GRBM_CNT_BASE_IDX', 'regGDS_EDC_OA_DED', + 'regGDS_EDC_OA_DED_BASE_IDX', 'regGDS_EDC_OA_PHY_CNT', + 'regGDS_EDC_OA_PHY_CNT_BASE_IDX', 'regGDS_EDC_OA_PIPE_CNT', + 'regGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'regGDS_ENHANCE', + 'regGDS_ENHANCE2', 'regGDS_ENHANCE2_BASE_IDX', + 'regGDS_ENHANCE_BASE_IDX', 'regGDS_GFX_CTXSW_STATUS', + 'regGDS_GFX_CTXSW_STATUS_BASE_IDX', 'regGDS_GS_0', + 'regGDS_GS_0_BASE_IDX', 'regGDS_GS_1', 'regGDS_GS_1_BASE_IDX', + 'regGDS_GS_2', 'regGDS_GS_2_BASE_IDX', 'regGDS_GS_3', + 'regGDS_GS_3_BASE_IDX', 'regGDS_GS_CTXSW_CNT0', + 'regGDS_GS_CTXSW_CNT0_BASE_IDX', 'regGDS_GS_CTXSW_CNT1', + 'regGDS_GS_CTXSW_CNT1_BASE_IDX', 'regGDS_GS_CTXSW_CNT2', + 'regGDS_GS_CTXSW_CNT2_BASE_IDX', 'regGDS_GS_CTXSW_CNT3', + 'regGDS_GS_CTXSW_CNT3_BASE_IDX', 'regGDS_GWS_RESET0', + 'regGDS_GWS_RESET0_BASE_IDX', 'regGDS_GWS_RESET1', + 'regGDS_GWS_RESET1_BASE_IDX', 'regGDS_GWS_RESOURCE', + 'regGDS_GWS_RESOURCE_BASE_IDX', 'regGDS_GWS_RESOURCE_CNT', + 'regGDS_GWS_RESOURCE_CNTL', 'regGDS_GWS_RESOURCE_CNTL_BASE_IDX', + 'regGDS_GWS_RESOURCE_CNT_BASE_IDX', 'regGDS_GWS_RESOURCE_RESET', + 'regGDS_GWS_RESOURCE_RESET_BASE_IDX', 'regGDS_GWS_VMID0', + 'regGDS_GWS_VMID0_BASE_IDX', 'regGDS_GWS_VMID1', + 'regGDS_GWS_VMID10', 'regGDS_GWS_VMID10_BASE_IDX', + 'regGDS_GWS_VMID11', 'regGDS_GWS_VMID11_BASE_IDX', + 'regGDS_GWS_VMID12', 'regGDS_GWS_VMID12_BASE_IDX', + 'regGDS_GWS_VMID13', 'regGDS_GWS_VMID13_BASE_IDX', + 'regGDS_GWS_VMID14', 'regGDS_GWS_VMID14_BASE_IDX', + 'regGDS_GWS_VMID15', 'regGDS_GWS_VMID15_BASE_IDX', + 'regGDS_GWS_VMID1_BASE_IDX', 'regGDS_GWS_VMID2', + 'regGDS_GWS_VMID2_BASE_IDX', 'regGDS_GWS_VMID3', + 'regGDS_GWS_VMID3_BASE_IDX', 'regGDS_GWS_VMID4', + 'regGDS_GWS_VMID4_BASE_IDX', 'regGDS_GWS_VMID5', + 'regGDS_GWS_VMID5_BASE_IDX', 'regGDS_GWS_VMID6', + 'regGDS_GWS_VMID6_BASE_IDX', 'regGDS_GWS_VMID7', + 'regGDS_GWS_VMID7_BASE_IDX', 'regGDS_GWS_VMID8', + 'regGDS_GWS_VMID8_BASE_IDX', 'regGDS_GWS_VMID9', + 'regGDS_GWS_VMID9_BASE_IDX', 'regGDS_MEMORY_CLEAN', + 'regGDS_MEMORY_CLEAN_BASE_IDX', 'regGDS_OA_ADDRESS', + 'regGDS_OA_ADDRESS_BASE_IDX', 'regGDS_OA_CGPG_RESTORE', + 'regGDS_OA_CGPG_RESTORE_BASE_IDX', 'regGDS_OA_CNTL', + 'regGDS_OA_CNTL_BASE_IDX', 'regGDS_OA_COUNTER', + 'regGDS_OA_COUNTER_BASE_IDX', 'regGDS_OA_INCDEC', + 'regGDS_OA_INCDEC_BASE_IDX', 'regGDS_OA_RESET', + 'regGDS_OA_RESET_BASE_IDX', 'regGDS_OA_RESET_MASK', + 'regGDS_OA_RESET_MASK_BASE_IDX', 'regGDS_OA_RING_SIZE', + 'regGDS_OA_RING_SIZE_BASE_IDX', 'regGDS_OA_VMID0', + 'regGDS_OA_VMID0_BASE_IDX', 'regGDS_OA_VMID1', 'regGDS_OA_VMID10', + 'regGDS_OA_VMID10_BASE_IDX', 'regGDS_OA_VMID11', + 'regGDS_OA_VMID11_BASE_IDX', 'regGDS_OA_VMID12', + 'regGDS_OA_VMID12_BASE_IDX', 'regGDS_OA_VMID13', + 'regGDS_OA_VMID13_BASE_IDX', 'regGDS_OA_VMID14', + 'regGDS_OA_VMID14_BASE_IDX', 'regGDS_OA_VMID15', + 'regGDS_OA_VMID15_BASE_IDX', 'regGDS_OA_VMID1_BASE_IDX', + 'regGDS_OA_VMID2', 'regGDS_OA_VMID2_BASE_IDX', 'regGDS_OA_VMID3', + 'regGDS_OA_VMID3_BASE_IDX', 'regGDS_OA_VMID4', + 'regGDS_OA_VMID4_BASE_IDX', 'regGDS_OA_VMID5', + 'regGDS_OA_VMID5_BASE_IDX', 'regGDS_OA_VMID6', + 'regGDS_OA_VMID6_BASE_IDX', 'regGDS_OA_VMID7', + 'regGDS_OA_VMID7_BASE_IDX', 'regGDS_OA_VMID8', + 'regGDS_OA_VMID8_BASE_IDX', 'regGDS_OA_VMID9', + 'regGDS_OA_VMID9_BASE_IDX', 'regGDS_PERFCOUNTER0_HI', + 'regGDS_PERFCOUNTER0_HI_BASE_IDX', 'regGDS_PERFCOUNTER0_LO', + 'regGDS_PERFCOUNTER0_LO_BASE_IDX', 'regGDS_PERFCOUNTER0_SELECT', + 'regGDS_PERFCOUNTER0_SELECT1', + 'regGDS_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER1_HI', + 'regGDS_PERFCOUNTER1_HI_BASE_IDX', 'regGDS_PERFCOUNTER1_LO', + 'regGDS_PERFCOUNTER1_LO_BASE_IDX', 'regGDS_PERFCOUNTER1_SELECT', + 'regGDS_PERFCOUNTER1_SELECT1', + 'regGDS_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER2_HI', + 'regGDS_PERFCOUNTER2_HI_BASE_IDX', 'regGDS_PERFCOUNTER2_LO', + 'regGDS_PERFCOUNTER2_LO_BASE_IDX', 'regGDS_PERFCOUNTER2_SELECT', + 'regGDS_PERFCOUNTER2_SELECT1', + 'regGDS_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER3_HI', + 'regGDS_PERFCOUNTER3_HI_BASE_IDX', 'regGDS_PERFCOUNTER3_LO', + 'regGDS_PERFCOUNTER3_LO_BASE_IDX', 'regGDS_PERFCOUNTER3_SELECT', + 'regGDS_PERFCOUNTER3_SELECT1', + 'regGDS_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'regGDS_PROTECTION_FAULT', + 'regGDS_PROTECTION_FAULT_BASE_IDX', 'regGDS_PS_CTXSW_CNT0', + 'regGDS_PS_CTXSW_CNT0_BASE_IDX', 'regGDS_PS_CTXSW_CNT1', + 'regGDS_PS_CTXSW_CNT1_BASE_IDX', 'regGDS_PS_CTXSW_CNT2', + 'regGDS_PS_CTXSW_CNT2_BASE_IDX', 'regGDS_PS_CTXSW_CNT3', + 'regGDS_PS_CTXSW_CNT3_BASE_IDX', 'regGDS_PS_CTXSW_IDX', + 'regGDS_PS_CTXSW_IDX_BASE_IDX', 'regGDS_RD_ADDR', + 'regGDS_RD_ADDR_BASE_IDX', 'regGDS_RD_BURST_ADDR', + 'regGDS_RD_BURST_ADDR_BASE_IDX', 'regGDS_RD_BURST_COUNT', + 'regGDS_RD_BURST_COUNT_BASE_IDX', 'regGDS_RD_BURST_DATA', + 'regGDS_RD_BURST_DATA_BASE_IDX', 'regGDS_RD_DATA', + 'regGDS_RD_DATA_BASE_IDX', 'regGDS_STRMOUT_DWORDS_WRITTEN_0', + 'regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX', + 'regGDS_STRMOUT_DWORDS_WRITTEN_1', + 'regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX', + 'regGDS_STRMOUT_DWORDS_WRITTEN_2', + 'regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX', + 'regGDS_STRMOUT_DWORDS_WRITTEN_3', + 'regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_0_HI', + 'regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_0_LO', + 'regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_1_HI', + 'regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_1_LO', + 'regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_2_HI', + 'regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_2_LO', + 'regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_3_HI', + 'regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_NEEDED_3_LO', + 'regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI', + 'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO', + 'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI', + 'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO', + 'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI', + 'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO', + 'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI', + 'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX', + 'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO', + 'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX', 'regGDS_VMID0_BASE', + 'regGDS_VMID0_BASE_BASE_IDX', 'regGDS_VMID0_SIZE', + 'regGDS_VMID0_SIZE_BASE_IDX', 'regGDS_VMID10_BASE', + 'regGDS_VMID10_BASE_BASE_IDX', 'regGDS_VMID10_SIZE', + 'regGDS_VMID10_SIZE_BASE_IDX', 'regGDS_VMID11_BASE', + 'regGDS_VMID11_BASE_BASE_IDX', 'regGDS_VMID11_SIZE', + 'regGDS_VMID11_SIZE_BASE_IDX', 'regGDS_VMID12_BASE', + 'regGDS_VMID12_BASE_BASE_IDX', 'regGDS_VMID12_SIZE', + 'regGDS_VMID12_SIZE_BASE_IDX', 'regGDS_VMID13_BASE', + 'regGDS_VMID13_BASE_BASE_IDX', 'regGDS_VMID13_SIZE', + 'regGDS_VMID13_SIZE_BASE_IDX', 'regGDS_VMID14_BASE', + 'regGDS_VMID14_BASE_BASE_IDX', 'regGDS_VMID14_SIZE', + 'regGDS_VMID14_SIZE_BASE_IDX', 'regGDS_VMID15_BASE', + 'regGDS_VMID15_BASE_BASE_IDX', 'regGDS_VMID15_SIZE', + 'regGDS_VMID15_SIZE_BASE_IDX', 'regGDS_VMID1_BASE', + 'regGDS_VMID1_BASE_BASE_IDX', 'regGDS_VMID1_SIZE', + 'regGDS_VMID1_SIZE_BASE_IDX', 'regGDS_VMID2_BASE', + 'regGDS_VMID2_BASE_BASE_IDX', 'regGDS_VMID2_SIZE', + 'regGDS_VMID2_SIZE_BASE_IDX', 'regGDS_VMID3_BASE', + 'regGDS_VMID3_BASE_BASE_IDX', 'regGDS_VMID3_SIZE', + 'regGDS_VMID3_SIZE_BASE_IDX', 'regGDS_VMID4_BASE', + 'regGDS_VMID4_BASE_BASE_IDX', 'regGDS_VMID4_SIZE', + 'regGDS_VMID4_SIZE_BASE_IDX', 'regGDS_VMID5_BASE', + 'regGDS_VMID5_BASE_BASE_IDX', 'regGDS_VMID5_SIZE', + 'regGDS_VMID5_SIZE_BASE_IDX', 'regGDS_VMID6_BASE', + 'regGDS_VMID6_BASE_BASE_IDX', 'regGDS_VMID6_SIZE', + 'regGDS_VMID6_SIZE_BASE_IDX', 'regGDS_VMID7_BASE', + 'regGDS_VMID7_BASE_BASE_IDX', 'regGDS_VMID7_SIZE', + 'regGDS_VMID7_SIZE_BASE_IDX', 'regGDS_VMID8_BASE', + 'regGDS_VMID8_BASE_BASE_IDX', 'regGDS_VMID8_SIZE', + 'regGDS_VMID8_SIZE_BASE_IDX', 'regGDS_VMID9_BASE', + 'regGDS_VMID9_BASE_BASE_IDX', 'regGDS_VMID9_SIZE', + 'regGDS_VMID9_SIZE_BASE_IDX', 'regGDS_VM_PROTECTION_FAULT', + 'regGDS_VM_PROTECTION_FAULT_BASE_IDX', 'regGDS_WRITE_COMPLETE', + 'regGDS_WRITE_COMPLETE_BASE_IDX', 'regGDS_WR_ADDR', + 'regGDS_WR_ADDR_BASE_IDX', 'regGDS_WR_BURST_ADDR', + 'regGDS_WR_BURST_ADDR_BASE_IDX', 'regGDS_WR_BURST_DATA', + 'regGDS_WR_BURST_DATA_BASE_IDX', 'regGDS_WR_DATA', + 'regGDS_WR_DATA_BASE_IDX', 'regGE1_PERFCOUNTER0_HI', + 'regGE1_PERFCOUNTER0_HI_BASE_IDX', 'regGE1_PERFCOUNTER0_LO', + 'regGE1_PERFCOUNTER0_LO_BASE_IDX', 'regGE1_PERFCOUNTER0_SELECT', + 'regGE1_PERFCOUNTER0_SELECT1', + 'regGE1_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER1_HI', + 'regGE1_PERFCOUNTER1_HI_BASE_IDX', 'regGE1_PERFCOUNTER1_LO', + 'regGE1_PERFCOUNTER1_LO_BASE_IDX', 'regGE1_PERFCOUNTER1_SELECT', + 'regGE1_PERFCOUNTER1_SELECT1', + 'regGE1_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER2_HI', + 'regGE1_PERFCOUNTER2_HI_BASE_IDX', 'regGE1_PERFCOUNTER2_LO', + 'regGE1_PERFCOUNTER2_LO_BASE_IDX', 'regGE1_PERFCOUNTER2_SELECT', + 'regGE1_PERFCOUNTER2_SELECT1', + 'regGE1_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER3_HI', + 'regGE1_PERFCOUNTER3_HI_BASE_IDX', 'regGE1_PERFCOUNTER3_LO', + 'regGE1_PERFCOUNTER3_LO_BASE_IDX', 'regGE1_PERFCOUNTER3_SELECT', + 'regGE1_PERFCOUNTER3_SELECT1', + 'regGE1_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regGE1_PERFCOUNTER3_SELECT_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER0_HI', + 'regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER0_LO', + 'regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER0_SELECT', + 'regGE2_DIST_PERFCOUNTER0_SELECT1', + 'regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER1_HI', + 'regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER1_LO', + 'regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER1_SELECT', + 'regGE2_DIST_PERFCOUNTER1_SELECT1', + 'regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER2_HI', + 'regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER2_LO', + 'regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER2_SELECT', + 'regGE2_DIST_PERFCOUNTER2_SELECT1', + 'regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER3_HI', + 'regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER3_LO', + 'regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER3_SELECT', + 'regGE2_DIST_PERFCOUNTER3_SELECT1', + 'regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX', + 'regGE2_SE_CNTL_STATUS', 'regGE2_SE_CNTL_STATUS_BASE_IDX', + 'regGE2_SE_PERFCOUNTER0_HI', 'regGE2_SE_PERFCOUNTER0_HI_BASE_IDX', + 'regGE2_SE_PERFCOUNTER0_LO', 'regGE2_SE_PERFCOUNTER0_LO_BASE_IDX', + 'regGE2_SE_PERFCOUNTER0_SELECT', 'regGE2_SE_PERFCOUNTER0_SELECT1', + 'regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX', + 'regGE2_SE_PERFCOUNTER1_HI', 'regGE2_SE_PERFCOUNTER1_HI_BASE_IDX', + 'regGE2_SE_PERFCOUNTER1_LO', 'regGE2_SE_PERFCOUNTER1_LO_BASE_IDX', + 'regGE2_SE_PERFCOUNTER1_SELECT', 'regGE2_SE_PERFCOUNTER1_SELECT1', + 'regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX', + 'regGE2_SE_PERFCOUNTER2_HI', 'regGE2_SE_PERFCOUNTER2_HI_BASE_IDX', + 'regGE2_SE_PERFCOUNTER2_LO', 'regGE2_SE_PERFCOUNTER2_LO_BASE_IDX', + 'regGE2_SE_PERFCOUNTER2_SELECT', 'regGE2_SE_PERFCOUNTER2_SELECT1', + 'regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX', + 'regGE2_SE_PERFCOUNTER3_HI', 'regGE2_SE_PERFCOUNTER3_HI_BASE_IDX', + 'regGE2_SE_PERFCOUNTER3_LO', 'regGE2_SE_PERFCOUNTER3_LO_BASE_IDX', + 'regGE2_SE_PERFCOUNTER3_SELECT', 'regGE2_SE_PERFCOUNTER3_SELECT1', + 'regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'regGE_CNTL', + 'regGE_CNTL_BASE_IDX', 'regGE_GS_FAST_LAUNCH_WG_DIM', + 'regGE_GS_FAST_LAUNCH_WG_DIM_1', + 'regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX', + 'regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX', 'regGE_INDX_OFFSET', + 'regGE_INDX_OFFSET_BASE_IDX', 'regGE_MAX_OUTPUT_PER_SUBGROUP', + 'regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'regGE_MAX_VTX_INDX', + 'regGE_MAX_VTX_INDX_BASE_IDX', 'regGE_MIN_VTX_INDX', + 'regGE_MIN_VTX_INDX_BASE_IDX', 'regGE_MULTI_PRIM_IB_RESET_EN', + 'regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'regGE_NGG_SUBGRP_CNTL', + 'regGE_NGG_SUBGRP_CNTL_BASE_IDX', 'regGE_PA_IF_SAFE_REG', + 'regGE_PA_IF_SAFE_REG_BASE_IDX', 'regGE_PC_ALLOC', + 'regGE_PC_ALLOC_BASE_IDX', 'regGE_PRIV_CONTROL', + 'regGE_PRIV_CONTROL_BASE_IDX', 'regGE_RATE_CNTL_1', + 'regGE_RATE_CNTL_1_BASE_IDX', 'regGE_RATE_CNTL_2', + 'regGE_RATE_CNTL_2_BASE_IDX', 'regGE_SPI_IF_SAFE_REG', + 'regGE_SPI_IF_SAFE_REG_BASE_IDX', 'regGE_STATUS', + 'regGE_STATUS_BASE_IDX', 'regGE_STEREO_CNTL', + 'regGE_STEREO_CNTL_BASE_IDX', 'regGE_USER_VGPR1', + 'regGE_USER_VGPR1_BASE_IDX', 'regGE_USER_VGPR2', + 'regGE_USER_VGPR2_BASE_IDX', 'regGE_USER_VGPR3', + 'regGE_USER_VGPR3_BASE_IDX', 'regGE_USER_VGPR_EN', + 'regGE_USER_VGPR_EN_BASE_IDX', 'regGFX_COPY_STATE', + 'regGFX_COPY_STATE_BASE_IDX', 'regGFX_ICG_GL2C_CTRL', + 'regGFX_ICG_GL2C_CTRL1', 'regGFX_ICG_GL2C_CTRL1_BASE_IDX', + 'regGFX_ICG_GL2C_CTRL_BASE_IDX', 'regGFX_IMU_AEB_OVERRIDE', + 'regGFX_IMU_AEB_OVERRIDE_BASE_IDX', 'regGFX_IMU_C2PMSG_0', + 'regGFX_IMU_C2PMSG_0_BASE_IDX', 'regGFX_IMU_C2PMSG_1', + 'regGFX_IMU_C2PMSG_10', 'regGFX_IMU_C2PMSG_10_BASE_IDX', + 'regGFX_IMU_C2PMSG_11', 'regGFX_IMU_C2PMSG_11_BASE_IDX', + 'regGFX_IMU_C2PMSG_12', 'regGFX_IMU_C2PMSG_12_BASE_IDX', + 'regGFX_IMU_C2PMSG_13', 'regGFX_IMU_C2PMSG_13_BASE_IDX', + 'regGFX_IMU_C2PMSG_14', 'regGFX_IMU_C2PMSG_14_BASE_IDX', + 'regGFX_IMU_C2PMSG_15', 'regGFX_IMU_C2PMSG_15_BASE_IDX', + 'regGFX_IMU_C2PMSG_16', 'regGFX_IMU_C2PMSG_16_BASE_IDX', + 'regGFX_IMU_C2PMSG_17', 'regGFX_IMU_C2PMSG_17_BASE_IDX', + 'regGFX_IMU_C2PMSG_18', 'regGFX_IMU_C2PMSG_18_BASE_IDX', + 'regGFX_IMU_C2PMSG_19', 'regGFX_IMU_C2PMSG_19_BASE_IDX', + 'regGFX_IMU_C2PMSG_1_BASE_IDX', 'regGFX_IMU_C2PMSG_2', + 'regGFX_IMU_C2PMSG_20', 'regGFX_IMU_C2PMSG_20_BASE_IDX', + 'regGFX_IMU_C2PMSG_21', 'regGFX_IMU_C2PMSG_21_BASE_IDX', + 'regGFX_IMU_C2PMSG_22', 'regGFX_IMU_C2PMSG_22_BASE_IDX', + 'regGFX_IMU_C2PMSG_23', 'regGFX_IMU_C2PMSG_23_BASE_IDX', + 'regGFX_IMU_C2PMSG_24', 'regGFX_IMU_C2PMSG_24_BASE_IDX', + 'regGFX_IMU_C2PMSG_25', 'regGFX_IMU_C2PMSG_25_BASE_IDX', + 'regGFX_IMU_C2PMSG_26', 'regGFX_IMU_C2PMSG_26_BASE_IDX', + 'regGFX_IMU_C2PMSG_27', 'regGFX_IMU_C2PMSG_27_BASE_IDX', + 'regGFX_IMU_C2PMSG_28', 'regGFX_IMU_C2PMSG_28_BASE_IDX', + 'regGFX_IMU_C2PMSG_29', 'regGFX_IMU_C2PMSG_29_BASE_IDX', + 'regGFX_IMU_C2PMSG_2_BASE_IDX', 'regGFX_IMU_C2PMSG_3', + 'regGFX_IMU_C2PMSG_30', 'regGFX_IMU_C2PMSG_30_BASE_IDX', + 'regGFX_IMU_C2PMSG_31', 'regGFX_IMU_C2PMSG_31_BASE_IDX', + 'regGFX_IMU_C2PMSG_32', 'regGFX_IMU_C2PMSG_32_BASE_IDX', + 'regGFX_IMU_C2PMSG_33', 'regGFX_IMU_C2PMSG_33_BASE_IDX', + 'regGFX_IMU_C2PMSG_34', 'regGFX_IMU_C2PMSG_34_BASE_IDX', + 'regGFX_IMU_C2PMSG_35', 'regGFX_IMU_C2PMSG_35_BASE_IDX', + 'regGFX_IMU_C2PMSG_36', 'regGFX_IMU_C2PMSG_36_BASE_IDX', + 'regGFX_IMU_C2PMSG_37', 'regGFX_IMU_C2PMSG_37_BASE_IDX', + 'regGFX_IMU_C2PMSG_38', 'regGFX_IMU_C2PMSG_38_BASE_IDX', + 'regGFX_IMU_C2PMSG_39', 'regGFX_IMU_C2PMSG_39_BASE_IDX', + 'regGFX_IMU_C2PMSG_3_BASE_IDX', 'regGFX_IMU_C2PMSG_4', + 'regGFX_IMU_C2PMSG_40', 'regGFX_IMU_C2PMSG_40_BASE_IDX', + 'regGFX_IMU_C2PMSG_41', 'regGFX_IMU_C2PMSG_41_BASE_IDX', + 'regGFX_IMU_C2PMSG_42', 'regGFX_IMU_C2PMSG_42_BASE_IDX', + 'regGFX_IMU_C2PMSG_43', 'regGFX_IMU_C2PMSG_43_BASE_IDX', + 'regGFX_IMU_C2PMSG_44', 'regGFX_IMU_C2PMSG_44_BASE_IDX', + 'regGFX_IMU_C2PMSG_45', 'regGFX_IMU_C2PMSG_45_BASE_IDX', + 'regGFX_IMU_C2PMSG_46', 'regGFX_IMU_C2PMSG_46_BASE_IDX', + 'regGFX_IMU_C2PMSG_47', 'regGFX_IMU_C2PMSG_47_BASE_IDX', + 'regGFX_IMU_C2PMSG_4_BASE_IDX', 'regGFX_IMU_C2PMSG_5', + 'regGFX_IMU_C2PMSG_5_BASE_IDX', 'regGFX_IMU_C2PMSG_6', + 'regGFX_IMU_C2PMSG_6_BASE_IDX', 'regGFX_IMU_C2PMSG_7', + 'regGFX_IMU_C2PMSG_7_BASE_IDX', 'regGFX_IMU_C2PMSG_8', + 'regGFX_IMU_C2PMSG_8_BASE_IDX', 'regGFX_IMU_C2PMSG_9', + 'regGFX_IMU_C2PMSG_9_BASE_IDX', 'regGFX_IMU_C2PMSG_ACCESS_CTRL0', + 'regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX', + 'regGFX_IMU_C2PMSG_ACCESS_CTRL1', + 'regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX', 'regGFX_IMU_CLK_CTRL', + 'regGFX_IMU_CLK_CTRL_BASE_IDX', 'regGFX_IMU_CORE_CTRL', + 'regGFX_IMU_CORE_CTRL_BASE_IDX', 'regGFX_IMU_CORE_INT_STATUS', + 'regGFX_IMU_CORE_INT_STATUS_BASE_IDX', 'regGFX_IMU_CORE_STATUS', + 'regGFX_IMU_CORE_STATUS_BASE_IDX', 'regGFX_IMU_DOORBELL_CONTROL', + 'regGFX_IMU_DOORBELL_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_ACC', + 'regGFX_IMU_DPM_ACC_BASE_IDX', 'regGFX_IMU_DPM_CONTROL', + 'regGFX_IMU_DPM_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_REF_COUNTER', + 'regGFX_IMU_DPM_REF_COUNTER_BASE_IDX', 'regGFX_IMU_D_RAM_ADDR', + 'regGFX_IMU_D_RAM_ADDR_BASE_IDX', 'regGFX_IMU_D_RAM_DATA', + 'regGFX_IMU_D_RAM_DATA_BASE_IDX', 'regGFX_IMU_FENCE_CTRL', + 'regGFX_IMU_FENCE_CTRL_BASE_IDX', 'regGFX_IMU_FENCE_LOG_ADDR', + 'regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX', 'regGFX_IMU_FENCE_LOG_INIT', + 'regGFX_IMU_FENCE_LOG_INIT_BASE_IDX', 'regGFX_IMU_FUSESTRAP', + 'regGFX_IMU_FUSE_CTRL', 'regGFX_IMU_FUSE_CTRL_BASE_IDX', + 'regGFX_IMU_FW_GTS_HI', 'regGFX_IMU_FW_GTS_HI_BASE_IDX', + 'regGFX_IMU_FW_GTS_LO', 'regGFX_IMU_FW_GTS_LO_BASE_IDX', + 'regGFX_IMU_GAP_PWROK', 'regGFX_IMU_GAP_PWROK_BASE_IDX', + 'regGFX_IMU_GFXCLK_BYPASS_CTRL', + 'regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX', + 'regGFX_IMU_GFX_IH_GASKET_CTRL', + 'regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX', + 'regGFX_IMU_GFX_ISO_CTRL', 'regGFX_IMU_GFX_ISO_CTRL_BASE_IDX', + 'regGFX_IMU_GFX_RESET_CTRL', 'regGFX_IMU_GFX_RESET_CTRL_BASE_IDX', + 'regGFX_IMU_GTS_OFFSET_HI', 'regGFX_IMU_GTS_OFFSET_HI_BASE_IDX', + 'regGFX_IMU_GTS_OFFSET_LO', 'regGFX_IMU_GTS_OFFSET_LO_BASE_IDX', + 'regGFX_IMU_IH_CTRL_1', 'regGFX_IMU_IH_CTRL_1_BASE_IDX', + 'regGFX_IMU_IH_CTRL_2', 'regGFX_IMU_IH_CTRL_2_BASE_IDX', + 'regGFX_IMU_IH_CTRL_3', 'regGFX_IMU_IH_CTRL_3_BASE_IDX', + 'regGFX_IMU_IH_STATUS', 'regGFX_IMU_IH_STATUS_BASE_IDX', + 'regGFX_IMU_I_RAM_ADDR', 'regGFX_IMU_I_RAM_ADDR_BASE_IDX', + 'regGFX_IMU_I_RAM_DATA', 'regGFX_IMU_I_RAM_DATA_BASE_IDX', + 'regGFX_IMU_MP1_MUTEX', 'regGFX_IMU_MP1_MUTEX_BASE_IDX', + 'regGFX_IMU_MSG_FLAGS', 'regGFX_IMU_MSG_FLAGS_BASE_IDX', + 'regGFX_IMU_PIC_INTR', 'regGFX_IMU_PIC_INTR_BASE_IDX', + 'regGFX_IMU_PIC_INTR_ID', 'regGFX_IMU_PIC_INTR_ID_BASE_IDX', + 'regGFX_IMU_PIC_INT_EDGE', 'regGFX_IMU_PIC_INT_EDGE_BASE_IDX', + 'regGFX_IMU_PIC_INT_LVL', 'regGFX_IMU_PIC_INT_LVL_BASE_IDX', + 'regGFX_IMU_PIC_INT_MASK', 'regGFX_IMU_PIC_INT_MASK_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_0', 'regGFX_IMU_PIC_INT_PRI_0_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_1', 'regGFX_IMU_PIC_INT_PRI_1_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_2', 'regGFX_IMU_PIC_INT_PRI_2_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_3', 'regGFX_IMU_PIC_INT_PRI_3_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_4', 'regGFX_IMU_PIC_INT_PRI_4_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_5', 'regGFX_IMU_PIC_INT_PRI_5_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_6', 'regGFX_IMU_PIC_INT_PRI_6_BASE_IDX', + 'regGFX_IMU_PIC_INT_PRI_7', 'regGFX_IMU_PIC_INT_PRI_7_BASE_IDX', + 'regGFX_IMU_PIC_INT_STATUS', 'regGFX_IMU_PIC_INT_STATUS_BASE_IDX', + 'regGFX_IMU_PROGRAM_CTR', 'regGFX_IMU_PROGRAM_CTR_BASE_IDX', + 'regGFX_IMU_PWRMGT_IRQ_CTRL', + 'regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX', 'regGFX_IMU_PWROK', + 'regGFX_IMU_PWROKRAW', 'regGFX_IMU_PWROKRAW_BASE_IDX', + 'regGFX_IMU_PWROK_BASE_IDX', 'regGFX_IMU_RESETn', + 'regGFX_IMU_RESETn_BASE_IDX', 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI', + 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX', + 'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO', + 'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX', + 'regGFX_IMU_RLC_BOOTLOADER_SIZE', + 'regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX', + 'regGFX_IMU_RLC_CG_CTRL', 'regGFX_IMU_RLC_CG_CTRL_BASE_IDX', + 'regGFX_IMU_RLC_CMD', 'regGFX_IMU_RLC_CMD_BASE_IDX', + 'regGFX_IMU_RLC_DATA_0', 'regGFX_IMU_RLC_DATA_0_BASE_IDX', + 'regGFX_IMU_RLC_DATA_1', 'regGFX_IMU_RLC_DATA_1_BASE_IDX', + 'regGFX_IMU_RLC_DATA_2', 'regGFX_IMU_RLC_DATA_2_BASE_IDX', + 'regGFX_IMU_RLC_DATA_3', 'regGFX_IMU_RLC_DATA_3_BASE_IDX', + 'regGFX_IMU_RLC_DATA_4', 'regGFX_IMU_RLC_DATA_4_BASE_IDX', + 'regGFX_IMU_RLC_GTS_OFFSET_HI', + 'regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX', + 'regGFX_IMU_RLC_GTS_OFFSET_LO', + 'regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX', + 'regGFX_IMU_RLC_MSG_STATUS', 'regGFX_IMU_RLC_MSG_STATUS_BASE_IDX', + 'regGFX_IMU_RLC_MUTEX', 'regGFX_IMU_RLC_MUTEX_BASE_IDX', + 'regGFX_IMU_RLC_OVERRIDE', 'regGFX_IMU_RLC_OVERRIDE_BASE_IDX', + 'regGFX_IMU_RLC_RAM_ADDR_HIGH', + 'regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX', + 'regGFX_IMU_RLC_RAM_ADDR_LOW', + 'regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX', 'regGFX_IMU_RLC_RAM_DATA', + 'regGFX_IMU_RLC_RAM_DATA_BASE_IDX', 'regGFX_IMU_RLC_RAM_INDEX', + 'regGFX_IMU_RLC_RAM_INDEX_BASE_IDX', + 'regGFX_IMU_RLC_RESET_VECTOR', + 'regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX', 'regGFX_IMU_RLC_STATUS', + 'regGFX_IMU_RLC_STATUS_BASE_IDX', 'regGFX_IMU_RLC_THROTTLE_GFX', + 'regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX', 'regGFX_IMU_SCRATCH_0', + 'regGFX_IMU_SCRATCH_0_BASE_IDX', 'regGFX_IMU_SCRATCH_1', + 'regGFX_IMU_SCRATCH_10', 'regGFX_IMU_SCRATCH_10_BASE_IDX', + 'regGFX_IMU_SCRATCH_11', 'regGFX_IMU_SCRATCH_11_BASE_IDX', + 'regGFX_IMU_SCRATCH_12', 'regGFX_IMU_SCRATCH_12_BASE_IDX', + 'regGFX_IMU_SCRATCH_13', 'regGFX_IMU_SCRATCH_13_BASE_IDX', + 'regGFX_IMU_SCRATCH_14', 'regGFX_IMU_SCRATCH_14_BASE_IDX', + 'regGFX_IMU_SCRATCH_15', 'regGFX_IMU_SCRATCH_15_BASE_IDX', + 'regGFX_IMU_SCRATCH_1_BASE_IDX', 'regGFX_IMU_SCRATCH_2', + 'regGFX_IMU_SCRATCH_2_BASE_IDX', 'regGFX_IMU_SCRATCH_3', + 'regGFX_IMU_SCRATCH_3_BASE_IDX', 'regGFX_IMU_SCRATCH_4', + 'regGFX_IMU_SCRATCH_4_BASE_IDX', 'regGFX_IMU_SCRATCH_5', + 'regGFX_IMU_SCRATCH_5_BASE_IDX', 'regGFX_IMU_SCRATCH_6', + 'regGFX_IMU_SCRATCH_6_BASE_IDX', 'regGFX_IMU_SCRATCH_7', + 'regGFX_IMU_SCRATCH_7_BASE_IDX', 'regGFX_IMU_SCRATCH_8', + 'regGFX_IMU_SCRATCH_8_BASE_IDX', 'regGFX_IMU_SCRATCH_9', + 'regGFX_IMU_SCRATCH_9_BASE_IDX', 'regGFX_IMU_SMUIO_VIDCHG_CTRL', + 'regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX', 'regGFX_IMU_SOC_ADDR', + 'regGFX_IMU_SOC_ADDR_BASE_IDX', 'regGFX_IMU_SOC_DATA', + 'regGFX_IMU_SOC_DATA_BASE_IDX', 'regGFX_IMU_SOC_REQ', + 'regGFX_IMU_SOC_REQ_BASE_IDX', 'regGFX_IMU_STATUS', + 'regGFX_IMU_STATUS_BASE_IDX', 'regGFX_IMU_TELEMETRY', + 'regGFX_IMU_TELEMETRY_BASE_IDX', 'regGFX_IMU_TELEMETRY_DATA', + 'regGFX_IMU_TELEMETRY_DATA_BASE_IDX', + 'regGFX_IMU_TELEMETRY_TEMPERATURE', + 'regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX', + 'regGFX_IMU_TIMER0_CMP0', 'regGFX_IMU_TIMER0_CMP0_BASE_IDX', + 'regGFX_IMU_TIMER0_CMP1', 'regGFX_IMU_TIMER0_CMP1_BASE_IDX', + 'regGFX_IMU_TIMER0_CMP3', 'regGFX_IMU_TIMER0_CMP3_BASE_IDX', + 'regGFX_IMU_TIMER0_CMP_AUTOINC', + 'regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX', + 'regGFX_IMU_TIMER0_CMP_INTEN', + 'regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL0', + 'regGFX_IMU_TIMER0_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL1', + 'regGFX_IMU_TIMER0_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER0_VALUE', + 'regGFX_IMU_TIMER0_VALUE_BASE_IDX', 'regGFX_IMU_TIMER1_CMP0', + 'regGFX_IMU_TIMER1_CMP0_BASE_IDX', 'regGFX_IMU_TIMER1_CMP1', + 'regGFX_IMU_TIMER1_CMP1_BASE_IDX', 'regGFX_IMU_TIMER1_CMP3', + 'regGFX_IMU_TIMER1_CMP3_BASE_IDX', + 'regGFX_IMU_TIMER1_CMP_AUTOINC', + 'regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX', + 'regGFX_IMU_TIMER1_CMP_INTEN', + 'regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL0', + 'regGFX_IMU_TIMER1_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL1', + 'regGFX_IMU_TIMER1_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER1_VALUE', + 'regGFX_IMU_TIMER1_VALUE_BASE_IDX', 'regGFX_IMU_TIMER2_CMP0', + 'regGFX_IMU_TIMER2_CMP0_BASE_IDX', 'regGFX_IMU_TIMER2_CMP1', + 'regGFX_IMU_TIMER2_CMP1_BASE_IDX', 'regGFX_IMU_TIMER2_CMP3', + 'regGFX_IMU_TIMER2_CMP3_BASE_IDX', + 'regGFX_IMU_TIMER2_CMP_AUTOINC', + 'regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX', + 'regGFX_IMU_TIMER2_CMP_INTEN', + 'regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL0', + 'regGFX_IMU_TIMER2_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL1', + 'regGFX_IMU_TIMER2_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER2_VALUE', + 'regGFX_IMU_TIMER2_VALUE_BASE_IDX', 'regGFX_IMU_VDCI_RESET_CTRL', + 'regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX', 'regGFX_IMU_VF_CTRL', + 'regGFX_IMU_VF_CTRL_BASE_IDX', 'regGFX_PIPE_CONTROL', + 'regGFX_PIPE_CONTROL_BASE_IDX', 'regGFX_PIPE_PRIORITY', + 'regGFX_PIPE_PRIORITY_BASE_IDX', 'regGL1A_PERFCOUNTER0_HI', + 'regGL1A_PERFCOUNTER0_HI_BASE_IDX', 'regGL1A_PERFCOUNTER0_LO', + 'regGL1A_PERFCOUNTER0_LO_BASE_IDX', 'regGL1A_PERFCOUNTER0_SELECT', + 'regGL1A_PERFCOUNTER0_SELECT1', + 'regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER1_HI', + 'regGL1A_PERFCOUNTER1_HI_BASE_IDX', 'regGL1A_PERFCOUNTER1_LO', + 'regGL1A_PERFCOUNTER1_LO_BASE_IDX', 'regGL1A_PERFCOUNTER1_SELECT', + 'regGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER2_HI', + 'regGL1A_PERFCOUNTER2_HI_BASE_IDX', 'regGL1A_PERFCOUNTER2_LO', + 'regGL1A_PERFCOUNTER2_LO_BASE_IDX', 'regGL1A_PERFCOUNTER2_SELECT', + 'regGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER3_HI', + 'regGL1A_PERFCOUNTER3_HI_BASE_IDX', 'regGL1A_PERFCOUNTER3_LO', + 'regGL1A_PERFCOUNTER3_LO_BASE_IDX', 'regGL1A_PERFCOUNTER3_SELECT', + 'regGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER0_HI', + 'regGL1C_PERFCOUNTER0_HI_BASE_IDX', 'regGL1C_PERFCOUNTER0_LO', + 'regGL1C_PERFCOUNTER0_LO_BASE_IDX', 'regGL1C_PERFCOUNTER0_SELECT', + 'regGL1C_PERFCOUNTER0_SELECT1', + 'regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER1_HI', + 'regGL1C_PERFCOUNTER1_HI_BASE_IDX', 'regGL1C_PERFCOUNTER1_LO', + 'regGL1C_PERFCOUNTER1_LO_BASE_IDX', 'regGL1C_PERFCOUNTER1_SELECT', + 'regGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER2_HI', + 'regGL1C_PERFCOUNTER2_HI_BASE_IDX', 'regGL1C_PERFCOUNTER2_LO', + 'regGL1C_PERFCOUNTER2_LO_BASE_IDX', 'regGL1C_PERFCOUNTER2_SELECT', + 'regGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER3_HI', + 'regGL1C_PERFCOUNTER3_HI_BASE_IDX', 'regGL1C_PERFCOUNTER3_LO', + 'regGL1C_PERFCOUNTER3_LO_BASE_IDX', 'regGL1C_PERFCOUNTER3_SELECT', + 'regGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_STATUS', + 'regGL1C_STATUS_BASE_IDX', 'regGL1C_UTCL0_CNTL1', + 'regGL1C_UTCL0_CNTL1_BASE_IDX', 'regGL1C_UTCL0_CNTL2', + 'regGL1C_UTCL0_CNTL2_BASE_IDX', 'regGL1C_UTCL0_RETRY', + 'regGL1C_UTCL0_RETRY_BASE_IDX', 'regGL1C_UTCL0_STATUS', + 'regGL1C_UTCL0_STATUS_BASE_IDX', 'regGL1H_ARB_CTRL', + 'regGL1H_ARB_CTRL_BASE_IDX', 'regGL1H_ARB_STATUS', + 'regGL1H_ARB_STATUS_BASE_IDX', 'regGL1H_BURST_CTRL', + 'regGL1H_BURST_CTRL_BASE_IDX', 'regGL1H_BURST_MASK', + 'regGL1H_BURST_MASK_BASE_IDX', 'regGL1H_GL1_CREDITS', + 'regGL1H_GL1_CREDITS_BASE_IDX', 'regGL1H_ICG_CTRL', + 'regGL1H_ICG_CTRL_BASE_IDX', 'regGL1H_PERFCOUNTER0_HI', + 'regGL1H_PERFCOUNTER0_HI_BASE_IDX', 'regGL1H_PERFCOUNTER0_LO', + 'regGL1H_PERFCOUNTER0_LO_BASE_IDX', 'regGL1H_PERFCOUNTER0_SELECT', + 'regGL1H_PERFCOUNTER0_SELECT1', + 'regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGL1H_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER1_HI', + 'regGL1H_PERFCOUNTER1_HI_BASE_IDX', 'regGL1H_PERFCOUNTER1_LO', + 'regGL1H_PERFCOUNTER1_LO_BASE_IDX', 'regGL1H_PERFCOUNTER1_SELECT', + 'regGL1H_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER2_HI', + 'regGL1H_PERFCOUNTER2_HI_BASE_IDX', 'regGL1H_PERFCOUNTER2_LO', + 'regGL1H_PERFCOUNTER2_LO_BASE_IDX', 'regGL1H_PERFCOUNTER2_SELECT', + 'regGL1H_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER3_HI', + 'regGL1H_PERFCOUNTER3_HI_BASE_IDX', 'regGL1H_PERFCOUNTER3_LO', + 'regGL1H_PERFCOUNTER3_LO_BASE_IDX', 'regGL1H_PERFCOUNTER3_SELECT', + 'regGL1H_PERFCOUNTER3_SELECT_BASE_IDX', + 'regGL1I_GL1R_MGCG_OVERRIDE', + 'regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX', + 'regGL1I_GL1R_REP_FGCG_OVERRIDE', + 'regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX', 'regGL1_ARB_STATUS', + 'regGL1_ARB_STATUS_BASE_IDX', 'regGL1_DRAM_BURST_MASK', + 'regGL1_DRAM_BURST_MASK_BASE_IDX', 'regGL1_PIPE_STEER', + 'regGL1_PIPE_STEER_BASE_IDX', 'regGL2A_ADDR_MATCH_CTRL', + 'regGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'regGL2A_ADDR_MATCH_MASK', + 'regGL2A_ADDR_MATCH_MASK_BASE_IDX', 'regGL2A_ADDR_MATCH_SIZE', + 'regGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2A_PERFCOUNTER0_HI', + 'regGL2A_PERFCOUNTER0_HI_BASE_IDX', 'regGL2A_PERFCOUNTER0_LO', + 'regGL2A_PERFCOUNTER0_LO_BASE_IDX', 'regGL2A_PERFCOUNTER0_SELECT', + 'regGL2A_PERFCOUNTER0_SELECT1', + 'regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER1_HI', + 'regGL2A_PERFCOUNTER1_HI_BASE_IDX', 'regGL2A_PERFCOUNTER1_LO', + 'regGL2A_PERFCOUNTER1_LO_BASE_IDX', 'regGL2A_PERFCOUNTER1_SELECT', + 'regGL2A_PERFCOUNTER1_SELECT1', + 'regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER2_HI', + 'regGL2A_PERFCOUNTER2_HI_BASE_IDX', 'regGL2A_PERFCOUNTER2_LO', + 'regGL2A_PERFCOUNTER2_LO_BASE_IDX', 'regGL2A_PERFCOUNTER2_SELECT', + 'regGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER3_HI', + 'regGL2A_PERFCOUNTER3_HI_BASE_IDX', 'regGL2A_PERFCOUNTER3_LO', + 'regGL2A_PERFCOUNTER3_LO_BASE_IDX', 'regGL2A_PERFCOUNTER3_SELECT', + 'regGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2A_PRIORITY_CTRL', + 'regGL2A_PRIORITY_CTRL_BASE_IDX', 'regGL2A_RESP_THROTTLE_CTRL', + 'regGL2A_RESP_THROTTLE_CTRL_BASE_IDX', 'regGL2C_ADDR_MATCH_MASK', + 'regGL2C_ADDR_MATCH_MASK_BASE_IDX', 'regGL2C_ADDR_MATCH_SIZE', + 'regGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2C_CM_CTRL0', + 'regGL2C_CM_CTRL0_BASE_IDX', 'regGL2C_CM_CTRL1', + 'regGL2C_CM_CTRL1_BASE_IDX', 'regGL2C_CM_STALL', + 'regGL2C_CM_STALL_BASE_IDX', 'regGL2C_CTRL', 'regGL2C_CTRL2', + 'regGL2C_CTRL2_BASE_IDX', 'regGL2C_CTRL3', + 'regGL2C_CTRL3_BASE_IDX', 'regGL2C_CTRL4', + 'regGL2C_CTRL4_BASE_IDX', 'regGL2C_CTRL_BASE_IDX', + 'regGL2C_DISCARD_STALL_CTRL', + 'regGL2C_DISCARD_STALL_CTRL_BASE_IDX', 'regGL2C_LB_CTR_CTRL', + 'regGL2C_LB_CTR_CTRL_BASE_IDX', 'regGL2C_LB_CTR_SEL0', + 'regGL2C_LB_CTR_SEL0_BASE_IDX', 'regGL2C_LB_CTR_SEL1', + 'regGL2C_LB_CTR_SEL1_BASE_IDX', 'regGL2C_LB_DATA0', + 'regGL2C_LB_DATA0_BASE_IDX', 'regGL2C_LB_DATA1', + 'regGL2C_LB_DATA1_BASE_IDX', 'regGL2C_LB_DATA2', + 'regGL2C_LB_DATA2_BASE_IDX', 'regGL2C_LB_DATA3', + 'regGL2C_LB_DATA3_BASE_IDX', 'regGL2C_PERFCOUNTER0_HI', + 'regGL2C_PERFCOUNTER0_HI_BASE_IDX', 'regGL2C_PERFCOUNTER0_LO', + 'regGL2C_PERFCOUNTER0_LO_BASE_IDX', 'regGL2C_PERFCOUNTER0_SELECT', + 'regGL2C_PERFCOUNTER0_SELECT1', + 'regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER1_HI', + 'regGL2C_PERFCOUNTER1_HI_BASE_IDX', 'regGL2C_PERFCOUNTER1_LO', + 'regGL2C_PERFCOUNTER1_LO_BASE_IDX', 'regGL2C_PERFCOUNTER1_SELECT', + 'regGL2C_PERFCOUNTER1_SELECT1', + 'regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER2_HI', + 'regGL2C_PERFCOUNTER2_HI_BASE_IDX', 'regGL2C_PERFCOUNTER2_LO', + 'regGL2C_PERFCOUNTER2_LO_BASE_IDX', 'regGL2C_PERFCOUNTER2_SELECT', + 'regGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER3_HI', + 'regGL2C_PERFCOUNTER3_HI_BASE_IDX', 'regGL2C_PERFCOUNTER3_LO', + 'regGL2C_PERFCOUNTER3_LO_BASE_IDX', 'regGL2C_PERFCOUNTER3_SELECT', + 'regGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2C_SOFT_RESET', + 'regGL2C_SOFT_RESET_BASE_IDX', 'regGL2C_WBINVL2', + 'regGL2C_WBINVL2_BASE_IDX', 'regGL2_PIPE_STEER_0', + 'regGL2_PIPE_STEER_0_BASE_IDX', 'regGL2_PIPE_STEER_1', + 'regGL2_PIPE_STEER_1_BASE_IDX', 'regGL2_PIPE_STEER_2', + 'regGL2_PIPE_STEER_2_BASE_IDX', 'regGL2_PIPE_STEER_3', + 'regGL2_PIPE_STEER_3_BASE_IDX', 'regGRBM_CAM_DATA', + 'regGRBM_CAM_DATA_BASE_IDX', 'regGRBM_CAM_DATA_UPPER', + 'regGRBM_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_CAM_INDEX', + 'regGRBM_CAM_INDEX_BASE_IDX', 'regGRBM_CHIP_REVISION', + 'regGRBM_CHIP_REVISION_BASE_IDX', 'regGRBM_CNTL', + 'regGRBM_CNTL_BASE_IDX', 'regGRBM_DSM_BYPASS', + 'regGRBM_DSM_BYPASS_BASE_IDX', 'regGRBM_FENCE_RANGE0', + 'regGRBM_FENCE_RANGE0_BASE_IDX', 'regGRBM_FENCE_RANGE1', + 'regGRBM_FENCE_RANGE1_BASE_IDX', 'regGRBM_GFX_CLKEN_CNTL', + 'regGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL', + 'regGRBM_GFX_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL_SR_DATA', + 'regGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'regGRBM_GFX_CNTL_SR_SELECT', + 'regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'regGRBM_GFX_INDEX', + 'regGRBM_GFX_INDEX_BASE_IDX', 'regGRBM_GFX_INDEX_SR_DATA', + 'regGRBM_GFX_INDEX_SR_DATA_BASE_IDX', + 'regGRBM_GFX_INDEX_SR_SELECT', + 'regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'regGRBM_HYP_CAM_DATA', + 'regGRBM_HYP_CAM_DATA_BASE_IDX', 'regGRBM_HYP_CAM_DATA_UPPER', + 'regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_HYP_CAM_INDEX', + 'regGRBM_HYP_CAM_INDEX_BASE_IDX', 'regGRBM_IH_CREDIT', + 'regGRBM_IH_CREDIT_BASE_IDX', 'regGRBM_INT_CNTL', + 'regGRBM_INT_CNTL_BASE_IDX', 'regGRBM_INVALID_PIPE', + 'regGRBM_INVALID_PIPE_BASE_IDX', 'regGRBM_NOWHERE', + 'regGRBM_NOWHERE_BASE_IDX', 'regGRBM_PERFCOUNTER0_HI', + 'regGRBM_PERFCOUNTER0_HI_BASE_IDX', 'regGRBM_PERFCOUNTER0_LO', + 'regGRBM_PERFCOUNTER0_LO_BASE_IDX', 'regGRBM_PERFCOUNTER0_SELECT', + 'regGRBM_PERFCOUNTER0_SELECT_BASE_IDX', + 'regGRBM_PERFCOUNTER0_SELECT_HI', + 'regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX', + 'regGRBM_PERFCOUNTER1_HI', 'regGRBM_PERFCOUNTER1_HI_BASE_IDX', + 'regGRBM_PERFCOUNTER1_LO', 'regGRBM_PERFCOUNTER1_LO_BASE_IDX', + 'regGRBM_PERFCOUNTER1_SELECT', + 'regGRBM_PERFCOUNTER1_SELECT_BASE_IDX', + 'regGRBM_PERFCOUNTER1_SELECT_HI', + 'regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'regGRBM_PWR_CNTL', + 'regGRBM_PWR_CNTL2', 'regGRBM_PWR_CNTL2_BASE_IDX', + 'regGRBM_PWR_CNTL_BASE_IDX', 'regGRBM_READ_ERROR', + 'regGRBM_READ_ERROR2', 'regGRBM_READ_ERROR2_BASE_IDX', + 'regGRBM_READ_ERROR_BASE_IDX', 'regGRBM_SCRATCH_REG0', + 'regGRBM_SCRATCH_REG0_BASE_IDX', 'regGRBM_SCRATCH_REG1', + 'regGRBM_SCRATCH_REG1_BASE_IDX', 'regGRBM_SCRATCH_REG2', + 'regGRBM_SCRATCH_REG2_BASE_IDX', 'regGRBM_SCRATCH_REG3', + 'regGRBM_SCRATCH_REG3_BASE_IDX', 'regGRBM_SCRATCH_REG4', + 'regGRBM_SCRATCH_REG4_BASE_IDX', 'regGRBM_SCRATCH_REG5', + 'regGRBM_SCRATCH_REG5_BASE_IDX', 'regGRBM_SCRATCH_REG6', + 'regGRBM_SCRATCH_REG6_BASE_IDX', 'regGRBM_SCRATCH_REG7', + 'regGRBM_SCRATCH_REG7_BASE_IDX', 'regGRBM_SE0_PERFCOUNTER_HI', + 'regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE0_PERFCOUNTER_LO', + 'regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE0_PERFCOUNTER_SELECT', + 'regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE1_PERFCOUNTER_HI', + 'regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE1_PERFCOUNTER_LO', + 'regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE1_PERFCOUNTER_SELECT', + 'regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE2_PERFCOUNTER_HI', + 'regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE2_PERFCOUNTER_LO', + 'regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE2_PERFCOUNTER_SELECT', + 'regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE3_PERFCOUNTER_HI', + 'regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE3_PERFCOUNTER_LO', + 'regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE3_PERFCOUNTER_SELECT', + 'regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE4_PERFCOUNTER_HI', + 'regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE4_PERFCOUNTER_LO', + 'regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE4_PERFCOUNTER_SELECT', + 'regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE5_PERFCOUNTER_HI', + 'regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE5_PERFCOUNTER_LO', + 'regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE5_PERFCOUNTER_SELECT', + 'regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE6_PERFCOUNTER_HI', + 'regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE6_PERFCOUNTER_LO', + 'regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE6_PERFCOUNTER_SELECT', + 'regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX', 'regGRBM_SEC_CNTL', + 'regGRBM_SEC_CNTL_BASE_IDX', 'regGRBM_SE_REMAP_CNTL', + 'regGRBM_SE_REMAP_CNTL_BASE_IDX', 'regGRBM_SKEW_CNTL', + 'regGRBM_SKEW_CNTL_BASE_IDX', 'regGRBM_SOFT_RESET', + 'regGRBM_SOFT_RESET_BASE_IDX', 'regGRBM_STATUS', + 'regGRBM_STATUS2', 'regGRBM_STATUS2_BASE_IDX', 'regGRBM_STATUS3', + 'regGRBM_STATUS3_BASE_IDX', 'regGRBM_STATUS_BASE_IDX', + 'regGRBM_STATUS_SE0', 'regGRBM_STATUS_SE0_BASE_IDX', + 'regGRBM_STATUS_SE1', 'regGRBM_STATUS_SE1_BASE_IDX', + 'regGRBM_STATUS_SE2', 'regGRBM_STATUS_SE2_BASE_IDX', + 'regGRBM_STATUS_SE3', 'regGRBM_STATUS_SE3_BASE_IDX', + 'regGRBM_STATUS_SE4', 'regGRBM_STATUS_SE4_BASE_IDX', + 'regGRBM_STATUS_SE5', 'regGRBM_STATUS_SE5_BASE_IDX', + 'regGRBM_TRAP_ADDR', 'regGRBM_TRAP_ADDR_BASE_IDX', + 'regGRBM_TRAP_ADDR_MSK', 'regGRBM_TRAP_ADDR_MSK_BASE_IDX', + 'regGRBM_TRAP_OP', 'regGRBM_TRAP_OP_BASE_IDX', 'regGRBM_TRAP_WD', + 'regGRBM_TRAP_WD_BASE_IDX', 'regGRBM_TRAP_WD_MSK', + 'regGRBM_TRAP_WD_MSK_BASE_IDX', 'regGRBM_UTCL2_INVAL_RANGE_END', + 'regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX', + 'regGRBM_UTCL2_INVAL_RANGE_START', + 'regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX', + 'regGRBM_WAIT_IDLE_CLOCKS', 'regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX', + 'regGRBM_WRITE_ERROR', 'regGRBM_WRITE_ERROR_BASE_IDX', + 'regGRTAVFS_CLK_CNTL', 'regGRTAVFS_CLK_CNTL_BASE_IDX', + 'regGRTAVFS_GENERAL_0', 'regGRTAVFS_GENERAL_0_BASE_IDX', + 'regGRTAVFS_PSM_CNTL', 'regGRTAVFS_PSM_CNTL_BASE_IDX', + 'regGRTAVFS_RTAVFS_RD_DATA', 'regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX', + 'regGRTAVFS_RTAVFS_REG_ADDR', + 'regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', + 'regGRTAVFS_RTAVFS_REG_CTRL', + 'regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX', + 'regGRTAVFS_RTAVFS_REG_STATUS', + 'regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX', + 'regGRTAVFS_RTAVFS_WR_DATA', 'regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX', + 'regGRTAVFS_SE_CLK_CNTL', 'regGRTAVFS_SE_CLK_CNTL_BASE_IDX', + 'regGRTAVFS_SE_GENERAL_0', 'regGRTAVFS_SE_GENERAL_0_BASE_IDX', + 'regGRTAVFS_SE_PSM_CNTL', 'regGRTAVFS_SE_PSM_CNTL_BASE_IDX', + 'regGRTAVFS_SE_RTAVFS_RD_DATA', + 'regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX', + 'regGRTAVFS_SE_RTAVFS_REG_ADDR', + 'regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX', + 'regGRTAVFS_SE_RTAVFS_REG_CTRL', + 'regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX', + 'regGRTAVFS_SE_RTAVFS_REG_STATUS', + 'regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX', + 'regGRTAVFS_SE_RTAVFS_WR_DATA', + 'regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX', + 'regGRTAVFS_SE_SOFT_RESET', 'regGRTAVFS_SE_SOFT_RESET_BASE_IDX', + 'regGRTAVFS_SE_TARG_FREQ', 'regGRTAVFS_SE_TARG_FREQ_BASE_IDX', + 'regGRTAVFS_SE_TARG_VOLT', 'regGRTAVFS_SE_TARG_VOLT_BASE_IDX', + 'regGRTAVFS_SOFT_RESET', 'regGRTAVFS_SOFT_RESET_BASE_IDX', + 'regGRTAVFS_TARG_FREQ', 'regGRTAVFS_TARG_FREQ_BASE_IDX', + 'regGRTAVFS_TARG_VOLT', 'regGRTAVFS_TARG_VOLT_BASE_IDX', + 'regGUS_DRAM_COMBINE_FLUSH', 'regGUS_DRAM_COMBINE_FLUSH_BASE_IDX', + 'regGUS_DRAM_COMBINE_RD_WR_EN', + 'regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX', + 'regGUS_DRAM_GROUP_BURST', 'regGUS_DRAM_GROUP_BURST_BASE_IDX', + 'regGUS_DRAM_PRI_AGE_COEFF', 'regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX', + 'regGUS_DRAM_PRI_AGE_RATE', 'regGUS_DRAM_PRI_AGE_RATE_BASE_IDX', + 'regGUS_DRAM_PRI_FIXED', 'regGUS_DRAM_PRI_FIXED_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT1_PRI1', + 'regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT1_PRI2', + 'regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT1_PRI3', + 'regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT1_PRI4', + 'regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT1_PRI5', + 'regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT_PRI1', + 'regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT_PRI2', + 'regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT_PRI3', + 'regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT_PRI4', + 'regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX', + 'regGUS_DRAM_PRI_QUANT_PRI5', + 'regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX', 'regGUS_DRAM_PRI_QUEUING', + 'regGUS_DRAM_PRI_QUEUING_BASE_IDX', + 'regGUS_DRAM_PRI_URGENCY_COEFF', + 'regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX', + 'regGUS_DRAM_PRI_URGENCY_MODE', + 'regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_ERR_STATUS', + 'regGUS_ERR_STATUS_BASE_IDX', 'regGUS_ICG_CTRL', + 'regGUS_ICG_CTRL_BASE_IDX', 'regGUS_IO_GROUP_BURST', + 'regGUS_IO_GROUP_BURST_BASE_IDX', 'regGUS_IO_RD_COMBINE_FLUSH', + 'regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX', + 'regGUS_IO_RD_PRI_AGE_COEFF', + 'regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX', + 'regGUS_IO_RD_PRI_AGE_RATE', 'regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX', + 'regGUS_IO_RD_PRI_FIXED', 'regGUS_IO_RD_PRI_FIXED_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT1_PRI1', + 'regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT1_PRI2', + 'regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT1_PRI3', + 'regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT1_PRI4', + 'regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT_PRI1', + 'regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT_PRI2', + 'regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT_PRI3', + 'regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX', + 'regGUS_IO_RD_PRI_QUANT_PRI4', + 'regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX', + 'regGUS_IO_RD_PRI_QUEUING', 'regGUS_IO_RD_PRI_QUEUING_BASE_IDX', + 'regGUS_IO_RD_PRI_URGENCY_COEFF', + 'regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX', + 'regGUS_IO_RD_PRI_URGENCY_MODE', + 'regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX', + 'regGUS_IO_WR_COMBINE_FLUSH', + 'regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX', + 'regGUS_IO_WR_PRI_AGE_COEFF', + 'regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX', + 'regGUS_IO_WR_PRI_AGE_RATE', 'regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX', + 'regGUS_IO_WR_PRI_FIXED', 'regGUS_IO_WR_PRI_FIXED_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT1_PRI1', + 'regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT1_PRI2', + 'regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT1_PRI3', + 'regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT1_PRI4', + 'regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT_PRI1', + 'regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT_PRI2', + 'regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT_PRI3', + 'regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX', + 'regGUS_IO_WR_PRI_QUANT_PRI4', + 'regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX', + 'regGUS_IO_WR_PRI_QUEUING', 'regGUS_IO_WR_PRI_QUEUING_BASE_IDX', + 'regGUS_IO_WR_PRI_URGENCY_COEFF', + 'regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX', + 'regGUS_IO_WR_PRI_URGENCY_MODE', + 'regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_L1_CH0_CMD_IN', + 'regGUS_L1_CH0_CMD_IN_BASE_IDX', 'regGUS_L1_CH0_CMD_OUT', + 'regGUS_L1_CH0_CMD_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_IN', + 'regGUS_L1_CH0_DATA_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_OUT', + 'regGUS_L1_CH0_DATA_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_U_IN', + 'regGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_U_OUT', + 'regGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_CH1_CMD_IN', + 'regGUS_L1_CH1_CMD_IN_BASE_IDX', 'regGUS_L1_CH1_CMD_OUT', + 'regGUS_L1_CH1_CMD_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_IN', + 'regGUS_L1_CH1_DATA_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_OUT', + 'regGUS_L1_CH1_DATA_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_U_IN', + 'regGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_U_OUT', + 'regGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA0_CMD_IN', + 'regGUS_L1_SA0_CMD_IN_BASE_IDX', 'regGUS_L1_SA0_CMD_OUT', + 'regGUS_L1_SA0_CMD_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_IN', + 'regGUS_L1_SA0_DATA_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_OUT', + 'regGUS_L1_SA0_DATA_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_U_IN', + 'regGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_U_OUT', + 'regGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA1_CMD_IN', + 'regGUS_L1_SA1_CMD_IN_BASE_IDX', 'regGUS_L1_SA1_CMD_OUT', + 'regGUS_L1_SA1_CMD_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_IN', + 'regGUS_L1_SA1_DATA_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_OUT', + 'regGUS_L1_SA1_DATA_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_U_IN', + 'regGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_U_OUT', + 'regGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA2_CMD_IN', + 'regGUS_L1_SA2_CMD_IN_BASE_IDX', 'regGUS_L1_SA2_CMD_OUT', + 'regGUS_L1_SA2_CMD_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_IN', + 'regGUS_L1_SA2_DATA_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_OUT', + 'regGUS_L1_SA2_DATA_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_U_IN', + 'regGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_U_OUT', + 'regGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA3_CMD_IN', + 'regGUS_L1_SA3_CMD_IN_BASE_IDX', 'regGUS_L1_SA3_CMD_OUT', + 'regGUS_L1_SA3_CMD_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_IN', + 'regGUS_L1_SA3_DATA_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_OUT', + 'regGUS_L1_SA3_DATA_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_U_IN', + 'regGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_U_OUT', + 'regGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'regGUS_LATENCY_SAMPLING', + 'regGUS_LATENCY_SAMPLING_BASE_IDX', 'regGUS_MISC', 'regGUS_MISC2', + 'regGUS_MISC2_BASE_IDX', 'regGUS_MISC3', 'regGUS_MISC3_BASE_IDX', + 'regGUS_MISC_BASE_IDX', 'regGUS_PERFCOUNTER0_CFG', + 'regGUS_PERFCOUNTER0_CFG_BASE_IDX', 'regGUS_PERFCOUNTER1_CFG', + 'regGUS_PERFCOUNTER1_CFG_BASE_IDX', 'regGUS_PERFCOUNTER2_HI', + 'regGUS_PERFCOUNTER2_HI_BASE_IDX', 'regGUS_PERFCOUNTER2_LO', + 'regGUS_PERFCOUNTER2_LO_BASE_IDX', 'regGUS_PERFCOUNTER2_MODE', + 'regGUS_PERFCOUNTER2_MODE_BASE_IDX', 'regGUS_PERFCOUNTER2_SELECT', + 'regGUS_PERFCOUNTER2_SELECT1', + 'regGUS_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGUS_PERFCOUNTER_HI', + 'regGUS_PERFCOUNTER_HI_BASE_IDX', 'regGUS_PERFCOUNTER_LO', + 'regGUS_PERFCOUNTER_LO_BASE_IDX', 'regGUS_PERFCOUNTER_RSLT_CNTL', + 'regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGUS_SDP_ARB_FINAL', + 'regGUS_SDP_ARB_FINAL_BASE_IDX', 'regGUS_SDP_CREDITS', + 'regGUS_SDP_CREDITS_BASE_IDX', 'regGUS_SDP_ENABLE', + 'regGUS_SDP_ENABLE_BASE_IDX', 'regGUS_SDP_QOS_VC_PRIORITY', + 'regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'regGUS_SDP_REQ_CNTL', + 'regGUS_SDP_REQ_CNTL_BASE_IDX', 'regGUS_SDP_TAG_RESERVE0', + 'regGUS_SDP_TAG_RESERVE0_BASE_IDX', 'regGUS_SDP_TAG_RESERVE1', + 'regGUS_SDP_TAG_RESERVE1_BASE_IDX', 'regGUS_SDP_VCC_RESERVE0', + 'regGUS_SDP_VCC_RESERVE0_BASE_IDX', 'regGUS_SDP_VCC_RESERVE1', + 'regGUS_SDP_VCC_RESERVE1_BASE_IDX', 'regGUS_SDP_VCD_RESERVE0', + 'regGUS_SDP_VCD_RESERVE0_BASE_IDX', 'regGUS_SDP_VCD_RESERVE1', + 'regGUS_SDP_VCD_RESERVE1_BASE_IDX', 'regGUS_WRRSP_FIFO_CNTL', + 'regGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'regIA_ENHANCE', + 'regIA_ENHANCE_BASE_IDX', 'regIA_UTCL1_CNTL', + 'regIA_UTCL1_CNTL_BASE_IDX', 'regIA_UTCL1_STATUS', + 'regIA_UTCL1_STATUS_2', 'regIA_UTCL1_STATUS_2_BASE_IDX', + 'regIA_UTCL1_STATUS_BASE_IDX', 'regICG_CHA_CTRL', + 'regICG_CHA_CTRL_BASE_IDX', 'regICG_CHCG_CLK_CTRL', + 'regICG_CHCG_CLK_CTRL_BASE_IDX', 'regICG_CHC_CLK_CTRL', + 'regICG_CHC_CLK_CTRL_BASE_IDX', 'regICG_GL1A_CTRL', + 'regICG_GL1A_CTRL_BASE_IDX', 'regICG_GL1C_CLK_CTRL', + 'regICG_GL1C_CLK_CTRL_BASE_IDX', 'regICG_LDS_CLK_CTRL', + 'regICG_LDS_CLK_CTRL_BASE_IDX', 'regICG_SP_CLK_CTRL', + 'regICG_SP_CLK_CTRL_BASE_IDX', 'regLDS_CONFIG', + 'regLDS_CONFIG_BASE_IDX', 'regPA_CL_CLIP_CNTL', + 'regPA_CL_CLIP_CNTL_BASE_IDX', 'regPA_CL_CNTL_STATUS', + 'regPA_CL_CNTL_STATUS_BASE_IDX', 'regPA_CL_ENHANCE', + 'regPA_CL_ENHANCE_BASE_IDX', 'regPA_CL_GB_HORZ_CLIP_ADJ', + 'regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_HORZ_DISC_ADJ', + 'regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_CLIP_ADJ', + 'regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_DISC_ADJ', + 'regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'regPA_CL_NANINF_CNTL', + 'regPA_CL_NANINF_CNTL_BASE_IDX', 'regPA_CL_NGG_CNTL', + 'regPA_CL_NGG_CNTL_BASE_IDX', 'regPA_CL_POINT_CULL_RAD', + 'regPA_CL_POINT_CULL_RAD_BASE_IDX', 'regPA_CL_POINT_SIZE', + 'regPA_CL_POINT_SIZE_BASE_IDX', 'regPA_CL_POINT_X_RAD', + 'regPA_CL_POINT_X_RAD_BASE_IDX', 'regPA_CL_POINT_Y_RAD', + 'regPA_CL_POINT_Y_RAD_BASE_IDX', 'regPA_CL_PROG_NEAR_CLIP_Z', + 'regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'regPA_CL_UCP_0_W', + 'regPA_CL_UCP_0_W_BASE_IDX', 'regPA_CL_UCP_0_X', + 'regPA_CL_UCP_0_X_BASE_IDX', 'regPA_CL_UCP_0_Y', + 'regPA_CL_UCP_0_Y_BASE_IDX', 'regPA_CL_UCP_0_Z', + 'regPA_CL_UCP_0_Z_BASE_IDX', 'regPA_CL_UCP_1_W', + 'regPA_CL_UCP_1_W_BASE_IDX', 'regPA_CL_UCP_1_X', + 'regPA_CL_UCP_1_X_BASE_IDX', 'regPA_CL_UCP_1_Y', + 'regPA_CL_UCP_1_Y_BASE_IDX', 'regPA_CL_UCP_1_Z', + 'regPA_CL_UCP_1_Z_BASE_IDX', 'regPA_CL_UCP_2_W', + 'regPA_CL_UCP_2_W_BASE_IDX', 'regPA_CL_UCP_2_X', + 'regPA_CL_UCP_2_X_BASE_IDX', 'regPA_CL_UCP_2_Y', + 'regPA_CL_UCP_2_Y_BASE_IDX', 'regPA_CL_UCP_2_Z', + 'regPA_CL_UCP_2_Z_BASE_IDX', 'regPA_CL_UCP_3_W', + 'regPA_CL_UCP_3_W_BASE_IDX', 'regPA_CL_UCP_3_X', + 'regPA_CL_UCP_3_X_BASE_IDX', 'regPA_CL_UCP_3_Y', + 'regPA_CL_UCP_3_Y_BASE_IDX', 'regPA_CL_UCP_3_Z', + 'regPA_CL_UCP_3_Z_BASE_IDX', 'regPA_CL_UCP_4_W', + 'regPA_CL_UCP_4_W_BASE_IDX', 'regPA_CL_UCP_4_X', + 'regPA_CL_UCP_4_X_BASE_IDX', 'regPA_CL_UCP_4_Y', + 'regPA_CL_UCP_4_Y_BASE_IDX', 'regPA_CL_UCP_4_Z', + 'regPA_CL_UCP_4_Z_BASE_IDX', 'regPA_CL_UCP_5_W', + 'regPA_CL_UCP_5_W_BASE_IDX', 'regPA_CL_UCP_5_X', + 'regPA_CL_UCP_5_X_BASE_IDX', 'regPA_CL_UCP_5_Y', + 'regPA_CL_UCP_5_Y_BASE_IDX', 'regPA_CL_UCP_5_Z', + 'regPA_CL_UCP_5_Z_BASE_IDX', 'regPA_CL_VPORT_XOFFSET', + 'regPA_CL_VPORT_XOFFSET_1', 'regPA_CL_VPORT_XOFFSET_10', + 'regPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_11', + 'regPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_12', + 'regPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_13', + 'regPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_14', + 'regPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_15', + 'regPA_CL_VPORT_XOFFSET_15_BASE_IDX', + 'regPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_2', + 'regPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_3', + 'regPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_4', + 'regPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_5', + 'regPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_6', + 'regPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_7', + 'regPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_8', + 'regPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_9', + 'regPA_CL_VPORT_XOFFSET_9_BASE_IDX', + 'regPA_CL_VPORT_XOFFSET_BASE_IDX', 'regPA_CL_VPORT_XSCALE', + 'regPA_CL_VPORT_XSCALE_1', 'regPA_CL_VPORT_XSCALE_10', + 'regPA_CL_VPORT_XSCALE_10_BASE_IDX', 'regPA_CL_VPORT_XSCALE_11', + 'regPA_CL_VPORT_XSCALE_11_BASE_IDX', 'regPA_CL_VPORT_XSCALE_12', + 'regPA_CL_VPORT_XSCALE_12_BASE_IDX', 'regPA_CL_VPORT_XSCALE_13', + 'regPA_CL_VPORT_XSCALE_13_BASE_IDX', 'regPA_CL_VPORT_XSCALE_14', + 'regPA_CL_VPORT_XSCALE_14_BASE_IDX', 'regPA_CL_VPORT_XSCALE_15', + 'regPA_CL_VPORT_XSCALE_15_BASE_IDX', + 'regPA_CL_VPORT_XSCALE_1_BASE_IDX', 'regPA_CL_VPORT_XSCALE_2', + 'regPA_CL_VPORT_XSCALE_2_BASE_IDX', 'regPA_CL_VPORT_XSCALE_3', + 'regPA_CL_VPORT_XSCALE_3_BASE_IDX', 'regPA_CL_VPORT_XSCALE_4', + 'regPA_CL_VPORT_XSCALE_4_BASE_IDX', 'regPA_CL_VPORT_XSCALE_5', + 'regPA_CL_VPORT_XSCALE_5_BASE_IDX', 'regPA_CL_VPORT_XSCALE_6', + 'regPA_CL_VPORT_XSCALE_6_BASE_IDX', 'regPA_CL_VPORT_XSCALE_7', + 'regPA_CL_VPORT_XSCALE_7_BASE_IDX', 'regPA_CL_VPORT_XSCALE_8', + 'regPA_CL_VPORT_XSCALE_8_BASE_IDX', 'regPA_CL_VPORT_XSCALE_9', + 'regPA_CL_VPORT_XSCALE_9_BASE_IDX', + 'regPA_CL_VPORT_XSCALE_BASE_IDX', 'regPA_CL_VPORT_YOFFSET', + 'regPA_CL_VPORT_YOFFSET_1', 'regPA_CL_VPORT_YOFFSET_10', + 'regPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_11', + 'regPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_12', + 'regPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_13', + 'regPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_14', + 'regPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_15', + 'regPA_CL_VPORT_YOFFSET_15_BASE_IDX', + 'regPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_2', + 'regPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_3', + 'regPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_4', + 'regPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_5', + 'regPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_6', + 'regPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_7', + 'regPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_8', + 'regPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_9', + 'regPA_CL_VPORT_YOFFSET_9_BASE_IDX', + 'regPA_CL_VPORT_YOFFSET_BASE_IDX', 'regPA_CL_VPORT_YSCALE', + 'regPA_CL_VPORT_YSCALE_1', 'regPA_CL_VPORT_YSCALE_10', + 'regPA_CL_VPORT_YSCALE_10_BASE_IDX', 'regPA_CL_VPORT_YSCALE_11', + 'regPA_CL_VPORT_YSCALE_11_BASE_IDX', 'regPA_CL_VPORT_YSCALE_12', + 'regPA_CL_VPORT_YSCALE_12_BASE_IDX', 'regPA_CL_VPORT_YSCALE_13', + 'regPA_CL_VPORT_YSCALE_13_BASE_IDX', 'regPA_CL_VPORT_YSCALE_14', + 'regPA_CL_VPORT_YSCALE_14_BASE_IDX', 'regPA_CL_VPORT_YSCALE_15', + 'regPA_CL_VPORT_YSCALE_15_BASE_IDX', + 'regPA_CL_VPORT_YSCALE_1_BASE_IDX', 'regPA_CL_VPORT_YSCALE_2', + 'regPA_CL_VPORT_YSCALE_2_BASE_IDX', 'regPA_CL_VPORT_YSCALE_3', + 'regPA_CL_VPORT_YSCALE_3_BASE_IDX', 'regPA_CL_VPORT_YSCALE_4', + 'regPA_CL_VPORT_YSCALE_4_BASE_IDX', 'regPA_CL_VPORT_YSCALE_5', + 'regPA_CL_VPORT_YSCALE_5_BASE_IDX', 'regPA_CL_VPORT_YSCALE_6', + 'regPA_CL_VPORT_YSCALE_6_BASE_IDX', 'regPA_CL_VPORT_YSCALE_7', + 'regPA_CL_VPORT_YSCALE_7_BASE_IDX', 'regPA_CL_VPORT_YSCALE_8', + 'regPA_CL_VPORT_YSCALE_8_BASE_IDX', 'regPA_CL_VPORT_YSCALE_9', + 'regPA_CL_VPORT_YSCALE_9_BASE_IDX', + 'regPA_CL_VPORT_YSCALE_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET', + 'regPA_CL_VPORT_ZOFFSET_1', 'regPA_CL_VPORT_ZOFFSET_10', + 'regPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_11', + 'regPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_12', + 'regPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_13', + 'regPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_14', + 'regPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_15', + 'regPA_CL_VPORT_ZOFFSET_15_BASE_IDX', + 'regPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_2', + 'regPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_3', + 'regPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_4', + 'regPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_5', + 'regPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_6', + 'regPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_7', + 'regPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_8', + 'regPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_9', + 'regPA_CL_VPORT_ZOFFSET_9_BASE_IDX', + 'regPA_CL_VPORT_ZOFFSET_BASE_IDX', 'regPA_CL_VPORT_ZSCALE', + 'regPA_CL_VPORT_ZSCALE_1', 'regPA_CL_VPORT_ZSCALE_10', + 'regPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_11', + 'regPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_12', + 'regPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_13', + 'regPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_14', + 'regPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_15', + 'regPA_CL_VPORT_ZSCALE_15_BASE_IDX', + 'regPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_2', + 'regPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_3', + 'regPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_4', + 'regPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_5', + 'regPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_6', + 'regPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_7', + 'regPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_8', + 'regPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_9', + 'regPA_CL_VPORT_ZSCALE_9_BASE_IDX', + 'regPA_CL_VPORT_ZSCALE_BASE_IDX', 'regPA_CL_VRS_CNTL', + 'regPA_CL_VRS_CNTL_BASE_IDX', 'regPA_CL_VS_OUT_CNTL', + 'regPA_CL_VS_OUT_CNTL_BASE_IDX', 'regPA_CL_VTE_CNTL', + 'regPA_CL_VTE_CNTL_BASE_IDX', 'regPA_PH_ENHANCE', + 'regPA_PH_ENHANCE_BASE_IDX', 'regPA_PH_INTERFACE_FIFO_SIZE', + 'regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX', + 'regPA_PH_PERFCOUNTER0_HI', 'regPA_PH_PERFCOUNTER0_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER0_LO', 'regPA_PH_PERFCOUNTER0_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER0_SELECT', 'regPA_PH_PERFCOUNTER0_SELECT1', + 'regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX', + 'regPA_PH_PERFCOUNTER1_HI', 'regPA_PH_PERFCOUNTER1_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER1_LO', 'regPA_PH_PERFCOUNTER1_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER1_SELECT', 'regPA_PH_PERFCOUNTER1_SELECT1', + 'regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX', + 'regPA_PH_PERFCOUNTER2_HI', 'regPA_PH_PERFCOUNTER2_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER2_LO', 'regPA_PH_PERFCOUNTER2_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER2_SELECT', 'regPA_PH_PERFCOUNTER2_SELECT1', + 'regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX', + 'regPA_PH_PERFCOUNTER3_HI', 'regPA_PH_PERFCOUNTER3_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER3_LO', 'regPA_PH_PERFCOUNTER3_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER3_SELECT', 'regPA_PH_PERFCOUNTER3_SELECT1', + 'regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX', + 'regPA_PH_PERFCOUNTER4_HI', 'regPA_PH_PERFCOUNTER4_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER4_LO', 'regPA_PH_PERFCOUNTER4_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER4_SELECT', + 'regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX', + 'regPA_PH_PERFCOUNTER5_HI', 'regPA_PH_PERFCOUNTER5_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER5_LO', 'regPA_PH_PERFCOUNTER5_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER5_SELECT', + 'regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX', + 'regPA_PH_PERFCOUNTER6_HI', 'regPA_PH_PERFCOUNTER6_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER6_LO', 'regPA_PH_PERFCOUNTER6_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER6_SELECT', + 'regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX', + 'regPA_PH_PERFCOUNTER7_HI', 'regPA_PH_PERFCOUNTER7_HI_BASE_IDX', + 'regPA_PH_PERFCOUNTER7_LO', 'regPA_PH_PERFCOUNTER7_LO_BASE_IDX', + 'regPA_PH_PERFCOUNTER7_SELECT', + 'regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'regPA_RATE_CNTL', + 'regPA_RATE_CNTL_BASE_IDX', 'regPA_SC_AA_CONFIG', + 'regPA_SC_AA_CONFIG_BASE_IDX', 'regPA_SC_AA_MASK_X0Y0_X1Y0', + 'regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX', + 'regPA_SC_AA_MASK_X0Y1_X1Y1', + 'regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX', + 'regPA_SC_ATM_CNTL', 'regPA_SC_ATM_CNTL_BASE_IDX', + 'regPA_SC_BINNER_CNTL_0', 'regPA_SC_BINNER_CNTL_0_BASE_IDX', + 'regPA_SC_BINNER_CNTL_1', 'regPA_SC_BINNER_CNTL_1_BASE_IDX', + 'regPA_SC_BINNER_CNTL_2', 'regPA_SC_BINNER_CNTL_2_BASE_IDX', + 'regPA_SC_BINNER_CNTL_OVERRIDE', + 'regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_0', + 'regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_1', + 'regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_2', + 'regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_3', + 'regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_0', + 'regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_1', + 'regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_2', + 'regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_3', + 'regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX', + 'regPA_SC_BINNER_TIMEOUT_COUNTER', + 'regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX', + 'regPA_SC_CENTROID_PRIORITY_0', + 'regPA_SC_CENTROID_PRIORITY_0_BASE_IDX', + 'regPA_SC_CENTROID_PRIORITY_1', + 'regPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'regPA_SC_CLIPRECT_0_BR', + 'regPA_SC_CLIPRECT_0_BR_BASE_IDX', 'regPA_SC_CLIPRECT_0_TL', + 'regPA_SC_CLIPRECT_0_TL_BASE_IDX', 'regPA_SC_CLIPRECT_1_BR', + 'regPA_SC_CLIPRECT_1_BR_BASE_IDX', 'regPA_SC_CLIPRECT_1_TL', + 'regPA_SC_CLIPRECT_1_TL_BASE_IDX', 'regPA_SC_CLIPRECT_2_BR', + 'regPA_SC_CLIPRECT_2_BR_BASE_IDX', 'regPA_SC_CLIPRECT_2_TL', + 'regPA_SC_CLIPRECT_2_TL_BASE_IDX', 'regPA_SC_CLIPRECT_3_BR', + 'regPA_SC_CLIPRECT_3_BR_BASE_IDX', 'regPA_SC_CLIPRECT_3_TL', + 'regPA_SC_CLIPRECT_3_TL_BASE_IDX', 'regPA_SC_CLIPRECT_RULE', + 'regPA_SC_CLIPRECT_RULE_BASE_IDX', + 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL', + 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX', + 'regPA_SC_DSM_CNTL', 'regPA_SC_DSM_CNTL_BASE_IDX', + 'regPA_SC_EDGERULE', 'regPA_SC_EDGERULE_BASE_IDX', + 'regPA_SC_ENHANCE', 'regPA_SC_ENHANCE_1', + 'regPA_SC_ENHANCE_1_BASE_IDX', 'regPA_SC_ENHANCE_2', + 'regPA_SC_ENHANCE_2_BASE_IDX', 'regPA_SC_ENHANCE_3', + 'regPA_SC_ENHANCE_3_BASE_IDX', 'regPA_SC_ENHANCE_BASE_IDX', + 'regPA_SC_FIFO_DEPTH_CNTL', 'regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX', + 'regPA_SC_FIFO_SIZE', 'regPA_SC_FIFO_SIZE_BASE_IDX', + 'regPA_SC_FORCE_EOV_MAX_CNTS', + 'regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX', + 'regPA_SC_GENERIC_SCISSOR_BR', + 'regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX', + 'regPA_SC_GENERIC_SCISSOR_TL', + 'regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_COUNT', + 'regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_H', 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN', + 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK', + 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE', + 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_V', + 'regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'regPA_SC_IF_FIFO_SIZE', + 'regPA_SC_IF_FIFO_SIZE_BASE_IDX', 'regPA_SC_LINE_CNTL', + 'regPA_SC_LINE_CNTL_BASE_IDX', 'regPA_SC_LINE_STIPPLE', + 'regPA_SC_LINE_STIPPLE_BASE_IDX', 'regPA_SC_LINE_STIPPLE_STATE', + 'regPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'regPA_SC_MODE_CNTL_0', + 'regPA_SC_MODE_CNTL_0_BASE_IDX', 'regPA_SC_MODE_CNTL_1', + 'regPA_SC_MODE_CNTL_1_BASE_IDX', 'regPA_SC_NGG_MODE_CNTL', + 'regPA_SC_NGG_MODE_CNTL_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_COUNT', + 'regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_H', 'regPA_SC_P3D_TRAP_SCREEN_HV_EN', + 'regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK', + 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE', + 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_V', + 'regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX', + 'regPA_SC_PACKER_WAVE_ID_CNTL', + 'regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX', + 'regPA_SC_PBB_OVERRIDE_FLAG', + 'regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX', 'regPA_SC_PERFCOUNTER0_HI', + 'regPA_SC_PERFCOUNTER0_HI_BASE_IDX', 'regPA_SC_PERFCOUNTER0_LO', + 'regPA_SC_PERFCOUNTER0_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER0_SELECT', 'regPA_SC_PERFCOUNTER0_SELECT1', + 'regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER1_HI', 'regPA_SC_PERFCOUNTER1_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER1_LO', 'regPA_SC_PERFCOUNTER1_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER1_SELECT', + 'regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER2_HI', 'regPA_SC_PERFCOUNTER2_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER2_LO', 'regPA_SC_PERFCOUNTER2_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER2_SELECT', + 'regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER3_HI', 'regPA_SC_PERFCOUNTER3_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER3_LO', 'regPA_SC_PERFCOUNTER3_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER3_SELECT', + 'regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER4_HI', 'regPA_SC_PERFCOUNTER4_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER4_LO', 'regPA_SC_PERFCOUNTER4_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER4_SELECT', + 'regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER5_HI', 'regPA_SC_PERFCOUNTER5_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER5_LO', 'regPA_SC_PERFCOUNTER5_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER5_SELECT', + 'regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER6_HI', 'regPA_SC_PERFCOUNTER6_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER6_LO', 'regPA_SC_PERFCOUNTER6_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER6_SELECT', + 'regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER7_HI', 'regPA_SC_PERFCOUNTER7_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER7_LO', 'regPA_SC_PERFCOUNTER7_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER7_SELECT', + 'regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX', + 'regPA_SC_PKR_WAVE_TABLE_CNTL', + 'regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'regPA_SC_RASTER_CONFIG', + 'regPA_SC_RASTER_CONFIG_1', 'regPA_SC_RASTER_CONFIG_1_BASE_IDX', + 'regPA_SC_RASTER_CONFIG_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_CONTROL', + 'regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MAX_0', + 'regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MAX_1', + 'regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MIN_0', + 'regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MIN_1', + 'regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX', + 'regPA_SC_SCREEN_SCISSOR_BR', + 'regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX', + 'regPA_SC_SCREEN_SCISSOR_TL', + 'regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', 'regPA_SC_SHADER_CONTROL', + 'regPA_SC_SHADER_CONTROL_BASE_IDX', + 'regPA_SC_TILE_STEERING_CREST_OVERRIDE', + 'regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX', + 'regPA_SC_TILE_STEERING_OVERRIDE', + 'regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_COUNT', + 'regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', 'regPA_SC_TRAP_SCREEN_H', + 'regPA_SC_TRAP_SCREEN_HV_EN', + 'regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_HV_LOCK', + 'regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_H_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_OCCURRENCE', + 'regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_V', 'regPA_SC_TRAP_SCREEN_V_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_0_BR', + 'regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_0_TL', + 'regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_10_BR', + 'regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_10_TL', + 'regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_11_BR', + 'regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_11_TL', + 'regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_12_BR', + 'regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_12_TL', + 'regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_13_BR', + 'regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_13_TL', + 'regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_14_BR', + 'regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_14_TL', + 'regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_15_BR', + 'regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_15_TL', + 'regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_1_BR', + 'regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_1_TL', + 'regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_2_BR', + 'regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_2_TL', + 'regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_3_BR', + 'regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_3_TL', + 'regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_4_BR', + 'regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_4_TL', + 'regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_5_BR', + 'regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_5_TL', + 'regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_6_BR', + 'regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_6_TL', + 'regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_7_BR', + 'regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_7_TL', + 'regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_8_BR', + 'regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_8_TL', + 'regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_9_BR', + 'regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_9_TL', + 'regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'regPA_SC_VPORT_ZMAX_0', + 'regPA_SC_VPORT_ZMAX_0_BASE_IDX', 'regPA_SC_VPORT_ZMAX_1', + 'regPA_SC_VPORT_ZMAX_10', 'regPA_SC_VPORT_ZMAX_10_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_11', 'regPA_SC_VPORT_ZMAX_11_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_12', 'regPA_SC_VPORT_ZMAX_12_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_13', 'regPA_SC_VPORT_ZMAX_13_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_14', 'regPA_SC_VPORT_ZMAX_14_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_15', 'regPA_SC_VPORT_ZMAX_15_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_1_BASE_IDX', 'regPA_SC_VPORT_ZMAX_2', + 'regPA_SC_VPORT_ZMAX_2_BASE_IDX', 'regPA_SC_VPORT_ZMAX_3', + 'regPA_SC_VPORT_ZMAX_3_BASE_IDX', 'regPA_SC_VPORT_ZMAX_4', + 'regPA_SC_VPORT_ZMAX_4_BASE_IDX', 'regPA_SC_VPORT_ZMAX_5', + 'regPA_SC_VPORT_ZMAX_5_BASE_IDX', 'regPA_SC_VPORT_ZMAX_6', + 'regPA_SC_VPORT_ZMAX_6_BASE_IDX', 'regPA_SC_VPORT_ZMAX_7', + 'regPA_SC_VPORT_ZMAX_7_BASE_IDX', 'regPA_SC_VPORT_ZMAX_8', + 'regPA_SC_VPORT_ZMAX_8_BASE_IDX', 'regPA_SC_VPORT_ZMAX_9', + 'regPA_SC_VPORT_ZMAX_9_BASE_IDX', 'regPA_SC_VPORT_ZMIN_0', + 'regPA_SC_VPORT_ZMIN_0_BASE_IDX', 'regPA_SC_VPORT_ZMIN_1', + 'regPA_SC_VPORT_ZMIN_10', 'regPA_SC_VPORT_ZMIN_10_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_11', 'regPA_SC_VPORT_ZMIN_11_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_12', 'regPA_SC_VPORT_ZMIN_12_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_13', 'regPA_SC_VPORT_ZMIN_13_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_14', 'regPA_SC_VPORT_ZMIN_14_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_15', 'regPA_SC_VPORT_ZMIN_15_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_1_BASE_IDX', 'regPA_SC_VPORT_ZMIN_2', + 'regPA_SC_VPORT_ZMIN_2_BASE_IDX', 'regPA_SC_VPORT_ZMIN_3', + 'regPA_SC_VPORT_ZMIN_3_BASE_IDX', 'regPA_SC_VPORT_ZMIN_4', + 'regPA_SC_VPORT_ZMIN_4_BASE_IDX', 'regPA_SC_VPORT_ZMIN_5', + 'regPA_SC_VPORT_ZMIN_5_BASE_IDX', 'regPA_SC_VPORT_ZMIN_6', + 'regPA_SC_VPORT_ZMIN_6_BASE_IDX', 'regPA_SC_VPORT_ZMIN_7', + 'regPA_SC_VPORT_ZMIN_7_BASE_IDX', 'regPA_SC_VPORT_ZMIN_8', + 'regPA_SC_VPORT_ZMIN_8_BASE_IDX', 'regPA_SC_VPORT_ZMIN_9', + 'regPA_SC_VPORT_ZMIN_9_BASE_IDX', 'regPA_SC_VRS_OVERRIDE_CNTL', + 'regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX', 'regPA_SC_VRS_RATE_BASE', + 'regPA_SC_VRS_RATE_BASE_BASE_IDX', 'regPA_SC_VRS_RATE_BASE_EXT', + 'regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX', + 'regPA_SC_VRS_RATE_CACHE_CNTL', + 'regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX', + 'regPA_SC_VRS_RATE_FEEDBACK_BASE', + 'regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX', + 'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT', + 'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX', + 'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY', + 'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX', + 'regPA_SC_VRS_RATE_SIZE_XY', 'regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX', + 'regPA_SC_VRS_SURFACE_CNTL', 'regPA_SC_VRS_SURFACE_CNTL_1', + 'regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX', + 'regPA_SC_VRS_SURFACE_CNTL_BASE_IDX', 'regPA_SC_WINDOW_OFFSET', + 'regPA_SC_WINDOW_OFFSET_BASE_IDX', 'regPA_SC_WINDOW_SCISSOR_BR', + 'regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX', + 'regPA_SC_WINDOW_SCISSOR_TL', + 'regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', 'regPA_STATE_STEREO_X', + 'regPA_STATE_STEREO_X_BASE_IDX', 'regPA_STEREO_CNTL', + 'regPA_STEREO_CNTL_BASE_IDX', 'regPA_SU_CNTL_STATUS', + 'regPA_SU_CNTL_STATUS_BASE_IDX', + 'regPA_SU_HARDWARE_SCREEN_OFFSET', + 'regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'regPA_SU_LINE_CNTL', + 'regPA_SU_LINE_CNTL_BASE_IDX', 'regPA_SU_LINE_STIPPLE_CNTL', + 'regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX', + 'regPA_SU_LINE_STIPPLE_SCALE', + 'regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX', + 'regPA_SU_LINE_STIPPLE_VALUE', + 'regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX', + 'regPA_SU_OVER_RASTERIZATION_CNTL', + 'regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_HI', 'regPA_SU_PERFCOUNTER0_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_LO', 'regPA_SU_PERFCOUNTER0_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_SELECT', 'regPA_SU_PERFCOUNTER0_SELECT1', + 'regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_HI', 'regPA_SU_PERFCOUNTER1_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_LO', 'regPA_SU_PERFCOUNTER1_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_SELECT', 'regPA_SU_PERFCOUNTER1_SELECT1', + 'regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX', + 'regPA_SU_PERFCOUNTER2_HI', 'regPA_SU_PERFCOUNTER2_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER2_LO', 'regPA_SU_PERFCOUNTER2_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER2_SELECT', 'regPA_SU_PERFCOUNTER2_SELECT1', + 'regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX', + 'regPA_SU_PERFCOUNTER3_HI', 'regPA_SU_PERFCOUNTER3_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER3_LO', 'regPA_SU_PERFCOUNTER3_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER3_SELECT', 'regPA_SU_PERFCOUNTER3_SELECT1', + 'regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'regPA_SU_POINT_MINMAX', + 'regPA_SU_POINT_MINMAX_BASE_IDX', 'regPA_SU_POINT_SIZE', + 'regPA_SU_POINT_SIZE_BASE_IDX', + 'regPA_SU_POLY_OFFSET_BACK_OFFSET', + 'regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX', + 'regPA_SU_POLY_OFFSET_BACK_SCALE', + 'regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX', + 'regPA_SU_POLY_OFFSET_CLAMP', + 'regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX', + 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL', + 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX', + 'regPA_SU_POLY_OFFSET_FRONT_OFFSET', + 'regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX', + 'regPA_SU_POLY_OFFSET_FRONT_SCALE', + 'regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX', + 'regPA_SU_PRIM_FILTER_CNTL', 'regPA_SU_PRIM_FILTER_CNTL_BASE_IDX', + 'regPA_SU_SC_MODE_CNTL', 'regPA_SU_SC_MODE_CNTL_BASE_IDX', + 'regPA_SU_SMALL_PRIM_FILTER_CNTL', + 'regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'regPA_SU_VTX_CNTL', + 'regPA_SU_VTX_CNTL_BASE_IDX', 'regPCC_PERF_COUNTER', + 'regPCC_PERF_COUNTER_BASE_IDX', 'regPCC_PWRBRK_HYSTERESIS_CTRL', + 'regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX', + 'regPCC_STALL_PATTERN_1_2', 'regPCC_STALL_PATTERN_1_2_BASE_IDX', + 'regPCC_STALL_PATTERN_3_4', 'regPCC_STALL_PATTERN_3_4_BASE_IDX', + 'regPCC_STALL_PATTERN_5_6', 'regPCC_STALL_PATTERN_5_6_BASE_IDX', + 'regPCC_STALL_PATTERN_7', 'regPCC_STALL_PATTERN_7_BASE_IDX', + 'regPCC_STALL_PATTERN_CTRL', 'regPCC_STALL_PATTERN_CTRL_BASE_IDX', + 'regPC_PERFCOUNTER0_HI', 'regPC_PERFCOUNTER0_HI_BASE_IDX', + 'regPC_PERFCOUNTER0_LO', 'regPC_PERFCOUNTER0_LO_BASE_IDX', + 'regPC_PERFCOUNTER0_SELECT', 'regPC_PERFCOUNTER0_SELECT1', + 'regPC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regPC_PERFCOUNTER1_HI', + 'regPC_PERFCOUNTER1_HI_BASE_IDX', 'regPC_PERFCOUNTER1_LO', + 'regPC_PERFCOUNTER1_LO_BASE_IDX', 'regPC_PERFCOUNTER1_SELECT', + 'regPC_PERFCOUNTER1_SELECT1', + 'regPC_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regPC_PERFCOUNTER2_HI', + 'regPC_PERFCOUNTER2_HI_BASE_IDX', 'regPC_PERFCOUNTER2_LO', + 'regPC_PERFCOUNTER2_LO_BASE_IDX', 'regPC_PERFCOUNTER2_SELECT', + 'regPC_PERFCOUNTER2_SELECT1', + 'regPC_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regPC_PERFCOUNTER2_SELECT_BASE_IDX', 'regPC_PERFCOUNTER3_HI', + 'regPC_PERFCOUNTER3_HI_BASE_IDX', 'regPC_PERFCOUNTER3_LO', + 'regPC_PERFCOUNTER3_LO_BASE_IDX', 'regPC_PERFCOUNTER3_SELECT', + 'regPC_PERFCOUNTER3_SELECT1', + 'regPC_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regPC_PERFCOUNTER3_SELECT_BASE_IDX', 'regPMM_CNTL', + 'regPMM_CNTL2', 'regPMM_CNTL2_BASE_IDX', 'regPMM_CNTL_BASE_IDX', + 'regPMM_STATUS', 'regPMM_STATUS_BASE_IDX', + 'regPWRBRK_PERF_COUNTER', 'regPWRBRK_PERF_COUNTER_BASE_IDX', + 'regPWRBRK_STALL_PATTERN_1_2', + 'regPWRBRK_STALL_PATTERN_1_2_BASE_IDX', + 'regPWRBRK_STALL_PATTERN_3_4', + 'regPWRBRK_STALL_PATTERN_3_4_BASE_IDX', + 'regPWRBRK_STALL_PATTERN_5_6', + 'regPWRBRK_STALL_PATTERN_5_6_BASE_IDX', + 'regPWRBRK_STALL_PATTERN_7', 'regPWRBRK_STALL_PATTERN_7_BASE_IDX', + 'regPWRBRK_STALL_PATTERN_CTRL', + 'regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX', 'regRLC_AUTO_PG_CTRL', + 'regRLC_AUTO_PG_CTRL_BASE_IDX', 'regRLC_BUSY_CLK_CNTL', + 'regRLC_BUSY_CLK_CNTL_BASE_IDX', 'regRLC_CAC_MASK_CNTL', + 'regRLC_CAC_MASK_CNTL_BASE_IDX', 'regRLC_CAPTURE_GPU_CLOCK_COUNT', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX', + 'regRLC_CGCG_CGLS_CTRL', 'regRLC_CGCG_CGLS_CTRL_3D', + 'regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX', + 'regRLC_CGCG_CGLS_CTRL_BASE_IDX', 'regRLC_CGCG_RAMP_CTRL', + 'regRLC_CGCG_RAMP_CTRL_3D', 'regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX', + 'regRLC_CGCG_RAMP_CTRL_BASE_IDX', 'regRLC_CGTT_MGCG_OVERRIDE', + 'regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'regRLC_CLK_CNTL', + 'regRLC_CLK_CNTL_BASE_IDX', 'regRLC_CLK_COUNT_CTRL', + 'regRLC_CLK_COUNT_CTRL_BASE_IDX', 'regRLC_CLK_COUNT_GFXCLK_LSB', + 'regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX', + 'regRLC_CLK_COUNT_GFXCLK_MSB', + 'regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX', + 'regRLC_CLK_COUNT_REFCLK_LSB', + 'regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX', + 'regRLC_CLK_COUNT_REFCLK_MSB', + 'regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'regRLC_CLK_COUNT_STAT', + 'regRLC_CLK_COUNT_STAT_BASE_IDX', + 'regRLC_CLK_RESIDENCY_CNTR_CTRL', + 'regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX', + 'regRLC_CLK_RESIDENCY_EVENT_CNTR', + 'regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX', + 'regRLC_CLK_RESIDENCY_REF_CNTR', + 'regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_CNTL', + 'regRLC_CNTL_BASE_IDX', 'regRLC_CP_EOF_INT', + 'regRLC_CP_EOF_INT_BASE_IDX', 'regRLC_CP_EOF_INT_CNT', + 'regRLC_CP_EOF_INT_CNT_BASE_IDX', 'regRLC_CP_SCHEDULERS', + 'regRLC_CP_SCHEDULERS_BASE_IDX', 'regRLC_CP_STAT_INVAL_CTRL', + 'regRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'regRLC_CP_STAT_INVAL_STAT', + 'regRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'regRLC_CSIB_ADDR_HI', + 'regRLC_CSIB_ADDR_HI_BASE_IDX', 'regRLC_CSIB_ADDR_LO', + 'regRLC_CSIB_ADDR_LO_BASE_IDX', 'regRLC_CSIB_LENGTH', + 'regRLC_CSIB_LENGTH_BASE_IDX', 'regRLC_DS_RESIDENCY_CNTR_CTRL', + 'regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX', + 'regRLC_DS_RESIDENCY_EVENT_CNTR', + 'regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX', + 'regRLC_DS_RESIDENCY_REF_CNTR', + 'regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_DYN_PG_REQUEST', + 'regRLC_DYN_PG_REQUEST_BASE_IDX', 'regRLC_DYN_PG_STATUS', + 'regRLC_DYN_PG_STATUS_BASE_IDX', 'regRLC_F32_UCODE_VERSION', + 'regRLC_F32_UCODE_VERSION_BASE_IDX', 'regRLC_FWL_FIRST_VIOL_ADDR', + 'regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX', + 'regRLC_GENERAL_RESIDENCY_CNTR_CTRL', + 'regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX', + 'regRLC_GENERAL_RESIDENCY_EVENT_CNTR', + 'regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX', + 'regRLC_GENERAL_RESIDENCY_REF_CNTR', + 'regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX', + 'regRLC_GFX_IH_ARBITER_STAT', + 'regRLC_GFX_IH_ARBITER_STAT_BASE_IDX', + 'regRLC_GFX_IH_CLIENT_CTRL', 'regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX', + 'regRLC_GFX_IH_CLIENT_OTHER_STAT', + 'regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX', + 'regRLC_GFX_IH_CLIENT_SDMA_STAT', + 'regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX', + 'regRLC_GFX_IH_CLIENT_SE_STAT_H', + 'regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX', + 'regRLC_GFX_IH_CLIENT_SE_STAT_L', + 'regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX', 'regRLC_GFX_IMU_CMD', + 'regRLC_GFX_IMU_CMD_BASE_IDX', 'regRLC_GFX_IMU_DATA_0', + 'regRLC_GFX_IMU_DATA_0_BASE_IDX', 'regRLC_GPM_CP_DMA_COMPLETE_T0', + 'regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX', + 'regRLC_GPM_CP_DMA_COMPLETE_T1', + 'regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'regRLC_GPM_GENERAL_0', + 'regRLC_GPM_GENERAL_0_BASE_IDX', 'regRLC_GPM_GENERAL_1', + 'regRLC_GPM_GENERAL_10', 'regRLC_GPM_GENERAL_10_BASE_IDX', + 'regRLC_GPM_GENERAL_11', 'regRLC_GPM_GENERAL_11_BASE_IDX', + 'regRLC_GPM_GENERAL_12', 'regRLC_GPM_GENERAL_12_BASE_IDX', + 'regRLC_GPM_GENERAL_13', 'regRLC_GPM_GENERAL_13_BASE_IDX', + 'regRLC_GPM_GENERAL_14', 'regRLC_GPM_GENERAL_14_BASE_IDX', + 'regRLC_GPM_GENERAL_15', 'regRLC_GPM_GENERAL_15_BASE_IDX', + 'regRLC_GPM_GENERAL_16', 'regRLC_GPM_GENERAL_16_BASE_IDX', + 'regRLC_GPM_GENERAL_1_BASE_IDX', 'regRLC_GPM_GENERAL_2', + 'regRLC_GPM_GENERAL_2_BASE_IDX', 'regRLC_GPM_GENERAL_3', + 'regRLC_GPM_GENERAL_3_BASE_IDX', 'regRLC_GPM_GENERAL_4', + 'regRLC_GPM_GENERAL_4_BASE_IDX', 'regRLC_GPM_GENERAL_5', + 'regRLC_GPM_GENERAL_5_BASE_IDX', 'regRLC_GPM_GENERAL_6', + 'regRLC_GPM_GENERAL_6_BASE_IDX', 'regRLC_GPM_GENERAL_7', + 'regRLC_GPM_GENERAL_7_BASE_IDX', 'regRLC_GPM_GENERAL_8', + 'regRLC_GPM_GENERAL_8_BASE_IDX', 'regRLC_GPM_GENERAL_9', + 'regRLC_GPM_GENERAL_9_BASE_IDX', 'regRLC_GPM_INT_DISABLE_TH0', + 'regRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'regRLC_GPM_INT_FORCE_TH0', + 'regRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'regRLC_GPM_INT_STAT_TH0', + 'regRLC_GPM_INT_STAT_TH0_BASE_IDX', 'regRLC_GPM_IRAM_ADDR', + 'regRLC_GPM_IRAM_ADDR_BASE_IDX', 'regRLC_GPM_IRAM_DATA', + 'regRLC_GPM_IRAM_DATA_BASE_IDX', 'regRLC_GPM_LEGACY_INT_CLEAR', + 'regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX', + 'regRLC_GPM_LEGACY_INT_DISABLE', + 'regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX', + 'regRLC_GPM_LEGACY_INT_STAT', + 'regRLC_GPM_LEGACY_INT_STAT_BASE_IDX', 'regRLC_GPM_PERF_COUNT_0', + 'regRLC_GPM_PERF_COUNT_0_BASE_IDX', 'regRLC_GPM_PERF_COUNT_1', + 'regRLC_GPM_PERF_COUNT_1_BASE_IDX', 'regRLC_GPM_SCRATCH_ADDR', + 'regRLC_GPM_SCRATCH_ADDR_BASE_IDX', 'regRLC_GPM_SCRATCH_DATA', + 'regRLC_GPM_SCRATCH_DATA_BASE_IDX', 'regRLC_GPM_STAT', + 'regRLC_GPM_STAT_BASE_IDX', 'regRLC_GPM_THREAD_ENABLE', + 'regRLC_GPM_THREAD_ENABLE_BASE_IDX', + 'regRLC_GPM_THREAD_INVALIDATE_CACHE', + 'regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX', + 'regRLC_GPM_THREAD_PRIORITY', + 'regRLC_GPM_THREAD_PRIORITY_BASE_IDX', 'regRLC_GPM_THREAD_RESET', + 'regRLC_GPM_THREAD_RESET_BASE_IDX', 'regRLC_GPM_TIMER_CTRL', + 'regRLC_GPM_TIMER_CTRL_BASE_IDX', 'regRLC_GPM_TIMER_INT_0', + 'regRLC_GPM_TIMER_INT_0_BASE_IDX', 'regRLC_GPM_TIMER_INT_1', + 'regRLC_GPM_TIMER_INT_1_BASE_IDX', 'regRLC_GPM_TIMER_INT_2', + 'regRLC_GPM_TIMER_INT_2_BASE_IDX', 'regRLC_GPM_TIMER_INT_3', + 'regRLC_GPM_TIMER_INT_3_BASE_IDX', 'regRLC_GPM_TIMER_INT_4', + 'regRLC_GPM_TIMER_INT_4_BASE_IDX', 'regRLC_GPM_TIMER_STAT', + 'regRLC_GPM_TIMER_STAT_BASE_IDX', 'regRLC_GPM_UCODE_ADDR', + 'regRLC_GPM_UCODE_ADDR_BASE_IDX', 'regRLC_GPM_UCODE_DATA', + 'regRLC_GPM_UCODE_DATA_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_0', + 'regRLC_GPM_UTCL1_CNTL_0_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_1', + 'regRLC_GPM_UTCL1_CNTL_1_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_2', + 'regRLC_GPM_UTCL1_CNTL_2_BASE_IDX', + 'regRLC_GPM_UTCL1_TH0_ERROR_1', + 'regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX', + 'regRLC_GPM_UTCL1_TH0_ERROR_2', + 'regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX', + 'regRLC_GPM_UTCL1_TH1_ERROR_1', + 'regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX', + 'regRLC_GPM_UTCL1_TH1_ERROR_2', + 'regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX', + 'regRLC_GPM_UTCL1_TH2_ERROR_1', + 'regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX', + 'regRLC_GPM_UTCL1_TH2_ERROR_2', + 'regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'regRLC_GPR_REG1', + 'regRLC_GPR_REG1_BASE_IDX', 'regRLC_GPR_REG2', + 'regRLC_GPR_REG2_BASE_IDX', 'regRLC_GPU_CLOCK_32', + 'regRLC_GPU_CLOCK_32_BASE_IDX', 'regRLC_GPU_CLOCK_32_RES_SEL', + 'regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_LSB', 'regRLC_GPU_CLOCK_COUNT_LSB_1', + 'regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_LSB_2', + 'regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_MSB', 'regRLC_GPU_CLOCK_COUNT_MSB_1', + 'regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_MSB_2', + 'regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_SPM_LSB', + 'regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_SPM_MSB', + 'regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG1', 'regRLC_GPU_IOV_CFG_REG1_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG2', 'regRLC_GPU_IOV_CFG_REG2_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG6', 'regRLC_GPU_IOV_CFG_REG6_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG8', 'regRLC_GPU_IOV_CFG_REG8_BASE_IDX', + 'regRLC_GPU_IOV_F32_CNTL', 'regRLC_GPU_IOV_F32_CNTL_BASE_IDX', + 'regRLC_GPU_IOV_F32_INVALIDATE_CACHE', + 'regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX', + 'regRLC_GPU_IOV_F32_RESET', 'regRLC_GPU_IOV_F32_RESET_BASE_IDX', + 'regRLC_GPU_IOV_INT_DISABLE', + 'regRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'regRLC_GPU_IOV_INT_FORCE', + 'regRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'regRLC_GPU_IOV_INT_STAT', + 'regRLC_GPU_IOV_INT_STAT_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_CNTL', + 'regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR', + 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_RD_DATA', + 'regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR', + 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_WR_DATA', + 'regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX', + 'regRLC_GPU_IOV_RLC_RESPONSE', + 'regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'regRLC_GPU_IOV_SCH_0', + 'regRLC_GPU_IOV_SCH_0_BASE_IDX', 'regRLC_GPU_IOV_SCH_1', + 'regRLC_GPU_IOV_SCH_1_BASE_IDX', 'regRLC_GPU_IOV_SCH_2', + 'regRLC_GPU_IOV_SCH_2_BASE_IDX', 'regRLC_GPU_IOV_SCH_3', + 'regRLC_GPU_IOV_SCH_3_BASE_IDX', 'regRLC_GPU_IOV_SCH_BLOCK', + 'regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX', + 'regRLC_GPU_IOV_SCRATCH_ADDR', + 'regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_SCRATCH_DATA', + 'regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX', + 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA0_STATUS', + 'regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA1_STATUS', + 'regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA2_STATUS', + 'regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA3_STATUS', + 'regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA4_STATUS', + 'regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA5_STATUS', + 'regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA6_STATUS', + 'regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA7_STATUS', + 'regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SMU_RESPONSE', + 'regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX', + 'regRLC_GPU_IOV_UCODE_ADDR', 'regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_UCODE_DATA', 'regRLC_GPU_IOV_UCODE_DATA_BASE_IDX', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX', + 'regRLC_GPU_IOV_VF_ENABLE', 'regRLC_GPU_IOV_VF_ENABLE_BASE_IDX', + 'regRLC_GPU_IOV_VF_MASK', 'regRLC_GPU_IOV_VF_MASK_BASE_IDX', + 'regRLC_GPU_IOV_VM_BUSY_STATUS', + 'regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'regRLC_GTS_OFFSET_LSB', + 'regRLC_GTS_OFFSET_LSB_BASE_IDX', 'regRLC_GTS_OFFSET_MSB', + 'regRLC_GTS_OFFSET_MSB_BASE_IDX', 'regRLC_HYP_RLCG_UCODE_CHKSUM', + 'regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX', + 'regRLC_HYP_RLCP_UCODE_CHKSUM', + 'regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX', + 'regRLC_HYP_RLCV_UCODE_CHKSUM', + 'regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'regRLC_HYP_SEMAPHORE_0', + 'regRLC_HYP_SEMAPHORE_0_BASE_IDX', 'regRLC_HYP_SEMAPHORE_1', + 'regRLC_HYP_SEMAPHORE_1_BASE_IDX', 'regRLC_HYP_SEMAPHORE_2', + 'regRLC_HYP_SEMAPHORE_2_BASE_IDX', 'regRLC_HYP_SEMAPHORE_3', + 'regRLC_HYP_SEMAPHORE_3_BASE_IDX', 'regRLC_IH_COOKIE', + 'regRLC_IH_COOKIE_BASE_IDX', 'regRLC_IH_COOKIE_CNTL', + 'regRLC_IH_COOKIE_CNTL_BASE_IDX', 'regRLC_IMU_BOOTLOAD_ADDR_HI', + 'regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX', + 'regRLC_IMU_BOOTLOAD_ADDR_LO', + 'regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX', + 'regRLC_IMU_BOOTLOAD_SIZE', 'regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX', + 'regRLC_IMU_MISC', 'regRLC_IMU_MISC_BASE_IDX', + 'regRLC_IMU_RESET_VECTOR', 'regRLC_IMU_RESET_VECTOR_BASE_IDX', + 'regRLC_INT_STAT', 'regRLC_INT_STAT_BASE_IDX', + 'regRLC_JUMP_TABLE_RESTORE', 'regRLC_JUMP_TABLE_RESTORE_BASE_IDX', + 'regRLC_LX6_CNTL', 'regRLC_LX6_CNTL_BASE_IDX', + 'regRLC_LX6_DRAM_ADDR', 'regRLC_LX6_DRAM_ADDR_BASE_IDX', + 'regRLC_LX6_DRAM_DATA', 'regRLC_LX6_DRAM_DATA_BASE_IDX', + 'regRLC_LX6_IRAM_ADDR', 'regRLC_LX6_IRAM_ADDR_BASE_IDX', + 'regRLC_LX6_IRAM_DATA', 'regRLC_LX6_IRAM_DATA_BASE_IDX', + 'regRLC_MAX_PG_WGP', 'regRLC_MAX_PG_WGP_BASE_IDX', + 'regRLC_MEM_SLP_CNTL', 'regRLC_MEM_SLP_CNTL_BASE_IDX', + 'regRLC_MGCG_CTRL', 'regRLC_MGCG_CTRL_BASE_IDX', + 'regRLC_PACE_INT_CLEAR', 'regRLC_PACE_INT_CLEAR_BASE_IDX', + 'regRLC_PACE_INT_DISABLE', 'regRLC_PACE_INT_DISABLE_BASE_IDX', + 'regRLC_PACE_INT_FORCE', 'regRLC_PACE_INT_FORCE_BASE_IDX', + 'regRLC_PACE_INT_STAT', 'regRLC_PACE_INT_STAT_BASE_IDX', + 'regRLC_PACE_SCRATCH_ADDR', 'regRLC_PACE_SCRATCH_ADDR_BASE_IDX', + 'regRLC_PACE_SCRATCH_DATA', 'regRLC_PACE_SCRATCH_DATA_BASE_IDX', + 'regRLC_PACE_SPARE_INT', 'regRLC_PACE_SPARE_INT_1', + 'regRLC_PACE_SPARE_INT_1_BASE_IDX', + 'regRLC_PACE_SPARE_INT_BASE_IDX', 'regRLC_PACE_TIMER_CTRL', + 'regRLC_PACE_TIMER_CTRL_BASE_IDX', 'regRLC_PACE_TIMER_INT_0', + 'regRLC_PACE_TIMER_INT_0_BASE_IDX', 'regRLC_PACE_TIMER_INT_1', + 'regRLC_PACE_TIMER_INT_1_BASE_IDX', 'regRLC_PACE_TIMER_STAT', + 'regRLC_PACE_TIMER_STAT_BASE_IDX', 'regRLC_PACE_UCODE_ADDR', + 'regRLC_PACE_UCODE_ADDR_BASE_IDX', 'regRLC_PACE_UCODE_DATA', + 'regRLC_PACE_UCODE_DATA_BASE_IDX', + 'regRLC_PCC_RESIDENCY_CNTR_CTRL', + 'regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX', + 'regRLC_PCC_RESIDENCY_EVENT_CNTR', + 'regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX', + 'regRLC_PCC_RESIDENCY_REF_CNTR', + 'regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX', + 'regRLC_PERFCOUNTER0_HI', 'regRLC_PERFCOUNTER0_HI_BASE_IDX', + 'regRLC_PERFCOUNTER0_LO', 'regRLC_PERFCOUNTER0_LO_BASE_IDX', + 'regRLC_PERFCOUNTER0_SELECT', + 'regRLC_PERFCOUNTER0_SELECT_BASE_IDX', 'regRLC_PERFCOUNTER1_HI', + 'regRLC_PERFCOUNTER1_HI_BASE_IDX', 'regRLC_PERFCOUNTER1_LO', + 'regRLC_PERFCOUNTER1_LO_BASE_IDX', 'regRLC_PERFCOUNTER1_SELECT', + 'regRLC_PERFCOUNTER1_SELECT_BASE_IDX', 'regRLC_PERFMON_CNTL', + 'regRLC_PERFMON_CNTL_BASE_IDX', 'regRLC_PG_ALWAYS_ON_WGP_MASK', + 'regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'regRLC_PG_CNTL', + 'regRLC_PG_CNTL_BASE_IDX', 'regRLC_PG_DELAY', 'regRLC_PG_DELAY_2', + 'regRLC_PG_DELAY_2_BASE_IDX', 'regRLC_PG_DELAY_3', + 'regRLC_PG_DELAY_3_BASE_IDX', 'regRLC_PG_DELAY_BASE_IDX', + 'regRLC_POWER_RESIDENCY_CNTR_CTRL', + 'regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX', + 'regRLC_POWER_RESIDENCY_EVENT_CNTR', + 'regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX', + 'regRLC_POWER_RESIDENCY_REF_CNTR', + 'regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_R2I_CNTL_0', + 'regRLC_R2I_CNTL_0_BASE_IDX', 'regRLC_R2I_CNTL_1', + 'regRLC_R2I_CNTL_1_BASE_IDX', 'regRLC_R2I_CNTL_2', + 'regRLC_R2I_CNTL_2_BASE_IDX', 'regRLC_R2I_CNTL_3', + 'regRLC_R2I_CNTL_3_BASE_IDX', 'regRLC_REFCLOCK_TIMESTAMP_LSB', + 'regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX', + 'regRLC_REFCLOCK_TIMESTAMP_MSB', + 'regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX', + 'regRLC_RLCG_DOORBELL_0_DATA_HI', + 'regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX', + 'regRLC_RLCG_DOORBELL_0_DATA_LO', + 'regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX', + 'regRLC_RLCG_DOORBELL_1_DATA_HI', + 'regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX', + 'regRLC_RLCG_DOORBELL_1_DATA_LO', + 'regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX', + 'regRLC_RLCG_DOORBELL_2_DATA_HI', + 'regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX', + 'regRLC_RLCG_DOORBELL_2_DATA_LO', + 'regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX', + 'regRLC_RLCG_DOORBELL_3_DATA_HI', + 'regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX', + 'regRLC_RLCG_DOORBELL_3_DATA_LO', + 'regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX', + 'regRLC_RLCG_DOORBELL_CNTL', 'regRLC_RLCG_DOORBELL_CNTL_BASE_IDX', + 'regRLC_RLCG_DOORBELL_RANGE', + 'regRLC_RLCG_DOORBELL_RANGE_BASE_IDX', + 'regRLC_RLCG_DOORBELL_STAT', 'regRLC_RLCG_DOORBELL_STAT_BASE_IDX', + 'regRLC_RLCP_DOORBELL_0_DATA_HI', + 'regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX', + 'regRLC_RLCP_DOORBELL_0_DATA_LO', + 'regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX', + 'regRLC_RLCP_DOORBELL_1_DATA_HI', + 'regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX', + 'regRLC_RLCP_DOORBELL_1_DATA_LO', + 'regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX', + 'regRLC_RLCP_DOORBELL_2_DATA_HI', + 'regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX', + 'regRLC_RLCP_DOORBELL_2_DATA_LO', + 'regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX', + 'regRLC_RLCP_DOORBELL_3_DATA_HI', + 'regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX', + 'regRLC_RLCP_DOORBELL_3_DATA_LO', + 'regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX', + 'regRLC_RLCP_DOORBELL_CNTL', 'regRLC_RLCP_DOORBELL_CNTL_BASE_IDX', + 'regRLC_RLCP_DOORBELL_RANGE', + 'regRLC_RLCP_DOORBELL_RANGE_BASE_IDX', + 'regRLC_RLCP_DOORBELL_STAT', 'regRLC_RLCP_DOORBELL_STAT_BASE_IDX', + 'regRLC_RLCP_IRAM_ADDR', 'regRLC_RLCP_IRAM_ADDR_BASE_IDX', + 'regRLC_RLCP_IRAM_DATA', 'regRLC_RLCP_IRAM_DATA_BASE_IDX', + 'regRLC_RLCS_ABORTED_PD_SEQUENCE', + 'regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX', + 'regRLC_RLCS_AUXILIARY_REG_1', + 'regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX', + 'regRLC_RLCS_AUXILIARY_REG_2', + 'regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX', + 'regRLC_RLCS_AUXILIARY_REG_3', + 'regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX', + 'regRLC_RLCS_AUXILIARY_REG_4', + 'regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX', + 'regRLC_RLCS_BOOTLOAD_ID_STATUS1', + 'regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX', + 'regRLC_RLCS_BOOTLOAD_ID_STATUS2', + 'regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX', + 'regRLC_RLCS_BOOTLOAD_STATUS', + 'regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX', + 'regRLC_RLCS_CGCG_REQUEST', 'regRLC_RLCS_CGCG_REQUEST_BASE_IDX', + 'regRLC_RLCS_CGCG_STATUS', 'regRLC_RLCS_CGCG_STATUS_BASE_IDX', + 'regRLC_RLCS_CMP_IDLE_CNTL', 'regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX', + 'regRLC_RLCS_CP_DMA_SRCID_OVER', + 'regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX', + 'regRLC_RLCS_CP_INT_CTRL_1', 'regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX', + 'regRLC_RLCS_CP_INT_CTRL_2', 'regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX', + 'regRLC_RLCS_CP_INT_INFO_1', 'regRLC_RLCS_CP_INT_INFO_1_BASE_IDX', + 'regRLC_RLCS_CP_INT_INFO_2', 'regRLC_RLCS_CP_INT_INFO_2_BASE_IDX', + 'regRLC_RLCS_DEC_DUMP_ADDR', 'regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX', + 'regRLC_RLCS_DEC_END', 'regRLC_RLCS_DEC_END_BASE_IDX', + 'regRLC_RLCS_DEC_START', 'regRLC_RLCS_DEC_START_BASE_IDX', + 'regRLC_RLCS_DIDT_FORCE_STALL', + 'regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'regRLC_RLCS_DSM_TRIG', + 'regRLC_RLCS_DSM_TRIG_BASE_IDX', 'regRLC_RLCS_EDC_INT_CNTL', + 'regRLC_RLCS_EDC_INT_CNTL_BASE_IDX', + 'regRLC_RLCS_EXCEPTION_REG_1', + 'regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX', + 'regRLC_RLCS_EXCEPTION_REG_2', + 'regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX', + 'regRLC_RLCS_EXCEPTION_REG_3', + 'regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX', + 'regRLC_RLCS_EXCEPTION_REG_4', + 'regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'regRLC_RLCS_GCR_DATA_0', + 'regRLC_RLCS_GCR_DATA_0_BASE_IDX', 'regRLC_RLCS_GCR_DATA_1', + 'regRLC_RLCS_GCR_DATA_1_BASE_IDX', 'regRLC_RLCS_GCR_DATA_2', + 'regRLC_RLCS_GCR_DATA_2_BASE_IDX', 'regRLC_RLCS_GCR_DATA_3', + 'regRLC_RLCS_GCR_DATA_3_BASE_IDX', 'regRLC_RLCS_GCR_STATUS', + 'regRLC_RLCS_GCR_STATUS_BASE_IDX', 'regRLC_RLCS_GENERAL_0', + 'regRLC_RLCS_GENERAL_0_BASE_IDX', 'regRLC_RLCS_GENERAL_1', + 'regRLC_RLCS_GENERAL_10', 'regRLC_RLCS_GENERAL_10_BASE_IDX', + 'regRLC_RLCS_GENERAL_11', 'regRLC_RLCS_GENERAL_11_BASE_IDX', + 'regRLC_RLCS_GENERAL_12', 'regRLC_RLCS_GENERAL_12_BASE_IDX', + 'regRLC_RLCS_GENERAL_13', 'regRLC_RLCS_GENERAL_13_BASE_IDX', + 'regRLC_RLCS_GENERAL_14', 'regRLC_RLCS_GENERAL_14_BASE_IDX', + 'regRLC_RLCS_GENERAL_15', 'regRLC_RLCS_GENERAL_15_BASE_IDX', + 'regRLC_RLCS_GENERAL_16', 'regRLC_RLCS_GENERAL_16_BASE_IDX', + 'regRLC_RLCS_GENERAL_1_BASE_IDX', 'regRLC_RLCS_GENERAL_2', + 'regRLC_RLCS_GENERAL_2_BASE_IDX', 'regRLC_RLCS_GENERAL_3', + 'regRLC_RLCS_GENERAL_3_BASE_IDX', 'regRLC_RLCS_GENERAL_4', + 'regRLC_RLCS_GENERAL_4_BASE_IDX', 'regRLC_RLCS_GENERAL_5', + 'regRLC_RLCS_GENERAL_5_BASE_IDX', 'regRLC_RLCS_GENERAL_6', + 'regRLC_RLCS_GENERAL_6_BASE_IDX', 'regRLC_RLCS_GENERAL_7', + 'regRLC_RLCS_GENERAL_7_BASE_IDX', 'regRLC_RLCS_GENERAL_8', + 'regRLC_RLCS_GENERAL_8_BASE_IDX', 'regRLC_RLCS_GENERAL_9', + 'regRLC_RLCS_GENERAL_9_BASE_IDX', + 'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL', + 'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX', + 'regRLC_RLCS_GFX_DS_CNTL', 'regRLC_RLCS_GFX_DS_CNTL_BASE_IDX', + 'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO', + 'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX', + 'regRLC_RLCS_GFX_RM_CNTL', 'regRLC_RLCS_GFX_RM_CNTL_BASE_IDX', + 'regRLC_RLCS_GPM_LEGACY_INT_DISABLE', + 'regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX', + 'regRLC_RLCS_GPM_LEGACY_INT_STAT', + 'regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX', + 'regRLC_RLCS_GPM_STAT', 'regRLC_RLCS_GPM_STAT_2', + 'regRLC_RLCS_GPM_STAT_2_BASE_IDX', + 'regRLC_RLCS_GPM_STAT_BASE_IDX', + 'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL', + 'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX', + 'regRLC_RLCS_GRBM_IDLE_BUSY_STAT', + 'regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX', + 'regRLC_RLCS_GRBM_SOFT_RESET', + 'regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX', + 'regRLC_RLCS_IH_COOKIE_SEMAPHORE', + 'regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX', + 'regRLC_RLCS_IH_SEMAPHORE', 'regRLC_RLCS_IH_SEMAPHORE_BASE_IDX', + 'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE', + 'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX', + 'regRLC_RLCS_IMU_RAM_ADDR_0_LSB', + 'regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX', + 'regRLC_RLCS_IMU_RAM_ADDR_0_MSB', + 'regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX', + 'regRLC_RLCS_IMU_RAM_ADDR_1_LSB', + 'regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX', + 'regRLC_RLCS_IMU_RAM_ADDR_1_MSB', + 'regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX', + 'regRLC_RLCS_IMU_RAM_CNTL', 'regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX', + 'regRLC_RLCS_IMU_RAM_DATA_0', + 'regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX', + 'regRLC_RLCS_IMU_RAM_DATA_1', + 'regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MSG_CNTL', + 'regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MSG_CONTROL', + 'regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MSG_DATA0', + 'regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MSG_DATA1', + 'regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MSG_DATA2', + 'regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MSG_DATA3', + 'regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MSG_DATA4', + 'regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_MUTEX_CNTL', + 'regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_STATUS', + 'regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0', + 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX', + 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1', + 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX', + 'regRLC_RLCS_IMU_VIDCHG_CNTL', + 'regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX', + 'regRLC_RLCS_IOV_CMD_STATUS', + 'regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX', + 'regRLC_RLCS_IOV_CNTX_LOC_SIZE', + 'regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX', + 'regRLC_RLCS_IOV_SCH_BLOCK', 'regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX', + 'regRLC_RLCS_IOV_VM_BUSY_STATUS', + 'regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX', + 'regRLC_RLCS_KMD_LOG_CNTL1', 'regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX', + 'regRLC_RLCS_KMD_LOG_CNTL2', 'regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX', + 'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE', + 'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX', + 'regRLC_RLCS_PG_CHANGE_READ', + 'regRLC_RLCS_PG_CHANGE_READ_BASE_IDX', + 'regRLC_RLCS_PG_CHANGE_STATUS', + 'regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX', + 'regRLC_RLCS_PMM_CGCG_CNTL', 'regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX', + 'regRLC_RLCS_POWER_BRAKE_CNTL', + 'regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX', + 'regRLC_RLCS_POWER_BRAKE_CNTL_TH1', + 'regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX', + 'regRLC_RLCS_RLC_IMU_MSG_CNTL', + 'regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX', + 'regRLC_RLCS_RLC_IMU_MSG_CONTROL', + 'regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX', + 'regRLC_RLCS_RLC_IMU_MSG_DATA0', + 'regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX', + 'regRLC_RLCS_RLC_IMU_STATUS', + 'regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX', + 'regRLC_RLCS_SDMA_INT_CNTL_1', + 'regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX', + 'regRLC_RLCS_SDMA_INT_CNTL_2', + 'regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX', + 'regRLC_RLCS_SDMA_INT_INFO', 'regRLC_RLCS_SDMA_INT_INFO_BASE_IDX', + 'regRLC_RLCS_SDMA_INT_STAT', 'regRLC_RLCS_SDMA_INT_STAT_BASE_IDX', + 'regRLC_RLCS_SOC_DS_CNTL', 'regRLC_RLCS_SOC_DS_CNTL_BASE_IDX', + 'regRLC_RLCS_SPM_INT_CTRL', 'regRLC_RLCS_SPM_INT_CTRL_BASE_IDX', + 'regRLC_RLCS_SPM_INT_INFO_1', + 'regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX', + 'regRLC_RLCS_SPM_INT_INFO_2', + 'regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX', + 'regRLC_RLCS_SPM_SQTT_MODE', 'regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX', + 'regRLC_RLCS_SRM_SRCID_CNTL', + 'regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'regRLC_RLCS_UTCL2_CNTL', + 'regRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'regRLC_RLCS_WGP_READ', + 'regRLC_RLCS_WGP_READ_BASE_IDX', 'regRLC_RLCS_WGP_STATUS', + 'regRLC_RLCS_WGP_STATUS_BASE_IDX', 'regRLC_RLCV_COMMAND', + 'regRLC_RLCV_COMMAND_BASE_IDX', 'regRLC_RLCV_DOORBELL_0_DATA_HI', + 'regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX', + 'regRLC_RLCV_DOORBELL_0_DATA_LO', + 'regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX', + 'regRLC_RLCV_DOORBELL_1_DATA_HI', + 'regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX', + 'regRLC_RLCV_DOORBELL_1_DATA_LO', + 'regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX', + 'regRLC_RLCV_DOORBELL_2_DATA_HI', + 'regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX', + 'regRLC_RLCV_DOORBELL_2_DATA_LO', + 'regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX', + 'regRLC_RLCV_DOORBELL_3_DATA_HI', + 'regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX', + 'regRLC_RLCV_DOORBELL_3_DATA_LO', + 'regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX', + 'regRLC_RLCV_DOORBELL_CNTL', 'regRLC_RLCV_DOORBELL_CNTL_BASE_IDX', + 'regRLC_RLCV_DOORBELL_RANGE', + 'regRLC_RLCV_DOORBELL_RANGE_BASE_IDX', + 'regRLC_RLCV_DOORBELL_STAT', 'regRLC_RLCV_DOORBELL_STAT_BASE_IDX', + 'regRLC_RLCV_IRAM_ADDR', 'regRLC_RLCV_IRAM_ADDR_BASE_IDX', + 'regRLC_RLCV_IRAM_DATA', 'regRLC_RLCV_IRAM_DATA_BASE_IDX', + 'regRLC_RLCV_SAFE_MODE', 'regRLC_RLCV_SAFE_MODE_BASE_IDX', + 'regRLC_RLCV_SPARE_INT', 'regRLC_RLCV_SPARE_INT_1', + 'regRLC_RLCV_SPARE_INT_1_BASE_IDX', + 'regRLC_RLCV_SPARE_INT_BASE_IDX', 'regRLC_RLCV_TIMER_CTRL', + 'regRLC_RLCV_TIMER_CTRL_BASE_IDX', 'regRLC_RLCV_TIMER_INT_0', + 'regRLC_RLCV_TIMER_INT_0_BASE_IDX', 'regRLC_RLCV_TIMER_INT_1', + 'regRLC_RLCV_TIMER_INT_1_BASE_IDX', 'regRLC_RLCV_TIMER_STAT', + 'regRLC_RLCV_TIMER_STAT_BASE_IDX', 'regRLC_SAFE_MODE', + 'regRLC_SAFE_MODE_BASE_IDX', 'regRLC_SDMA0_BUSY_STATUS', + 'regRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA0_STATUS', + 'regRLC_SDMA0_STATUS_BASE_IDX', 'regRLC_SDMA1_BUSY_STATUS', + 'regRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA1_STATUS', + 'regRLC_SDMA1_STATUS_BASE_IDX', 'regRLC_SDMA2_BUSY_STATUS', + 'regRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA2_STATUS', + 'regRLC_SDMA2_STATUS_BASE_IDX', 'regRLC_SDMA3_BUSY_STATUS', + 'regRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA3_STATUS', + 'regRLC_SDMA3_STATUS_BASE_IDX', 'regRLC_SEMAPHORE_0', + 'regRLC_SEMAPHORE_0_BASE_IDX', 'regRLC_SEMAPHORE_1', + 'regRLC_SEMAPHORE_1_BASE_IDX', 'regRLC_SEMAPHORE_2', + 'regRLC_SEMAPHORE_2_BASE_IDX', 'regRLC_SEMAPHORE_3', + 'regRLC_SEMAPHORE_3_BASE_IDX', 'regRLC_SERDES_BUSY', + 'regRLC_SERDES_BUSY_BASE_IDX', 'regRLC_SERDES_CTRL', + 'regRLC_SERDES_CTRL_BASE_IDX', 'regRLC_SERDES_DATA', + 'regRLC_SERDES_DATA_BASE_IDX', 'regRLC_SERDES_MASK', + 'regRLC_SERDES_MASK_BASE_IDX', 'regRLC_SERDES_RD_DATA_0', + 'regRLC_SERDES_RD_DATA_0_BASE_IDX', 'regRLC_SERDES_RD_DATA_1', + 'regRLC_SERDES_RD_DATA_1_BASE_IDX', 'regRLC_SERDES_RD_DATA_2', + 'regRLC_SERDES_RD_DATA_2_BASE_IDX', 'regRLC_SERDES_RD_DATA_3', + 'regRLC_SERDES_RD_DATA_3_BASE_IDX', 'regRLC_SERDES_RD_INDEX', + 'regRLC_SERDES_RD_INDEX_BASE_IDX', 'regRLC_SMU_ARGUMENT_1', + 'regRLC_SMU_ARGUMENT_1_BASE_IDX', 'regRLC_SMU_ARGUMENT_2', + 'regRLC_SMU_ARGUMENT_2_BASE_IDX', 'regRLC_SMU_ARGUMENT_3', + 'regRLC_SMU_ARGUMENT_3_BASE_IDX', 'regRLC_SMU_ARGUMENT_4', + 'regRLC_SMU_ARGUMENT_4_BASE_IDX', 'regRLC_SMU_ARGUMENT_5', + 'regRLC_SMU_ARGUMENT_5_BASE_IDX', 'regRLC_SMU_CLK_REQ', + 'regRLC_SMU_CLK_REQ_BASE_IDX', 'regRLC_SMU_COMMAND', + 'regRLC_SMU_COMMAND_BASE_IDX', 'regRLC_SMU_MESSAGE', + 'regRLC_SMU_MESSAGE_1', 'regRLC_SMU_MESSAGE_1_BASE_IDX', + 'regRLC_SMU_MESSAGE_2', 'regRLC_SMU_MESSAGE_2_BASE_IDX', + 'regRLC_SMU_MESSAGE_BASE_IDX', 'regRLC_SMU_SAFE_MODE', + 'regRLC_SMU_SAFE_MODE_BASE_IDX', 'regRLC_SPARE', + 'regRLC_SPARE_BASE_IDX', 'regRLC_SPARE_INT_0', + 'regRLC_SPARE_INT_0_BASE_IDX', 'regRLC_SPARE_INT_1', + 'regRLC_SPARE_INT_1_BASE_IDX', 'regRLC_SPARE_INT_2', + 'regRLC_SPARE_INT_2_BASE_IDX', 'regRLC_SPM_ACCUM_CTRL', + 'regRLC_SPM_ACCUM_CTRLRAM_ADDR', + 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX', + 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET', + 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX', + 'regRLC_SPM_ACCUM_CTRLRAM_DATA', + 'regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX', + 'regRLC_SPM_ACCUM_CTRL_BASE_IDX', + 'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS', + 'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX', + 'regRLC_SPM_ACCUM_DATARAM_ADDR', + 'regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX', + 'regRLC_SPM_ACCUM_DATARAM_DATA', + 'regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX', + 'regRLC_SPM_ACCUM_DATARAM_WRCOUNT', + 'regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX', + 'regRLC_SPM_ACCUM_MODE', 'regRLC_SPM_ACCUM_MODE_BASE_IDX', + 'regRLC_SPM_ACCUM_SAMPLES_REQUESTED', + 'regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX', + 'regRLC_SPM_ACCUM_STATUS', 'regRLC_SPM_ACCUM_STATUS_BASE_IDX', + 'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR', + 'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX', + 'regRLC_SPM_ACCUM_SWA_DATARAM_DATA', + 'regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX', + 'regRLC_SPM_ACCUM_THRESHOLD', + 'regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX', + 'regRLC_SPM_GFXCLOCK_HIGHCOUNT', + 'regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX', + 'regRLC_SPM_GFXCLOCK_LOWCOUNT', + 'regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX', + 'regRLC_SPM_GLOBAL_DELAY_IND_ADDR', + 'regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX', + 'regRLC_SPM_GLOBAL_DELAY_IND_DATA', + 'regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX', + 'regRLC_SPM_GLOBAL_MUXSEL_ADDR', + 'regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX', + 'regRLC_SPM_GLOBAL_MUXSEL_DATA', + 'regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'regRLC_SPM_INT_CNTL', + 'regRLC_SPM_INT_CNTL_BASE_IDX', 'regRLC_SPM_INT_INFO_1', + 'regRLC_SPM_INT_INFO_1_BASE_IDX', 'regRLC_SPM_INT_INFO_2', + 'regRLC_SPM_INT_INFO_2_BASE_IDX', 'regRLC_SPM_INT_STATUS', + 'regRLC_SPM_INT_STATUS_BASE_IDX', 'regRLC_SPM_MC_CNTL', + 'regRLC_SPM_MC_CNTL_BASE_IDX', 'regRLC_SPM_MODE', + 'regRLC_SPM_MODE_BASE_IDX', 'regRLC_SPM_PAUSE', + 'regRLC_SPM_PAUSE_BASE_IDX', 'regRLC_SPM_PERFMON_CNTL', + 'regRLC_SPM_PERFMON_CNTL_BASE_IDX', + 'regRLC_SPM_PERFMON_RING_BASE_HI', + 'regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX', + 'regRLC_SPM_PERFMON_RING_BASE_LO', + 'regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX', + 'regRLC_SPM_PERFMON_RING_SIZE', + 'regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX', + 'regRLC_SPM_PERFMON_SEGMENT_SIZE', + 'regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX', + 'regRLC_SPM_RING_RDPTR', 'regRLC_SPM_RING_RDPTR_BASE_IDX', + 'regRLC_SPM_RING_WRPTR', 'regRLC_SPM_RING_WRPTR_BASE_IDX', + 'regRLC_SPM_RSPM_CMD', 'regRLC_SPM_RSPM_CMD_ACK', + 'regRLC_SPM_RSPM_CMD_ACK_BASE_IDX', + 'regRLC_SPM_RSPM_CMD_BASE_IDX', 'regRLC_SPM_RSPM_REQ_DATA_HI', + 'regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX', + 'regRLC_SPM_RSPM_REQ_DATA_LO', + 'regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX', 'regRLC_SPM_RSPM_REQ_OP', + 'regRLC_SPM_RSPM_REQ_OP_BASE_IDX', 'regRLC_SPM_RSPM_RET_DATA', + 'regRLC_SPM_RSPM_RET_DATA_BASE_IDX', 'regRLC_SPM_RSPM_RET_OP', + 'regRLC_SPM_RSPM_RET_OP_BASE_IDX', 'regRLC_SPM_SAMPLE_CNT', + 'regRLC_SPM_SAMPLE_CNT_BASE_IDX', 'regRLC_SPM_SEGMENT_THRESHOLD', + 'regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX', + 'regRLC_SPM_SE_DELAY_IND_ADDR', + 'regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX', + 'regRLC_SPM_SE_DELAY_IND_DATA', + 'regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX', + 'regRLC_SPM_SE_MUXSEL_ADDR', 'regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX', + 'regRLC_SPM_SE_MUXSEL_DATA', 'regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX', + 'regRLC_SPM_SE_RSPM_REQ_DATA_HI', + 'regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX', + 'regRLC_SPM_SE_RSPM_REQ_DATA_LO', + 'regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX', + 'regRLC_SPM_SE_RSPM_REQ_OP', 'regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX', + 'regRLC_SPM_SE_RSPM_RET_DATA', + 'regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX', + 'regRLC_SPM_SE_RSPM_RET_OP', 'regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX', + 'regRLC_SPM_SPARE', 'regRLC_SPM_SPARE_BASE_IDX', + 'regRLC_SPM_STATUS', 'regRLC_SPM_STATUS_BASE_IDX', + 'regRLC_SPM_THREAD_TRACE_CTRL', + 'regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'regRLC_SPM_UTCL1_CNTL', + 'regRLC_SPM_UTCL1_CNTL_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_1', + 'regRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_2', + 'regRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'regRLC_SPP_CAM_ADDR', + 'regRLC_SPP_CAM_ADDR_BASE_IDX', 'regRLC_SPP_CAM_DATA', + 'regRLC_SPP_CAM_DATA_BASE_IDX', 'regRLC_SPP_CAM_EXT_ADDR', + 'regRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'regRLC_SPP_CAM_EXT_DATA', + 'regRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'regRLC_SPP_CTRL', + 'regRLC_SPP_CTRL_BASE_IDX', 'regRLC_SPP_GLOBAL_SH_ID', + 'regRLC_SPP_GLOBAL_SH_ID_BASE_IDX', + 'regRLC_SPP_GLOBAL_SH_ID_VALID', + 'regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX', + 'regRLC_SPP_INFLIGHT_RD_ADDR', + 'regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX', + 'regRLC_SPP_INFLIGHT_RD_DATA', + 'regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'regRLC_SPP_PBB_INFO', + 'regRLC_SPP_PBB_INFO_BASE_IDX', 'regRLC_SPP_PROF_INFO_1', + 'regRLC_SPP_PROF_INFO_1_BASE_IDX', 'regRLC_SPP_PROF_INFO_2', + 'regRLC_SPP_PROF_INFO_2_BASE_IDX', 'regRLC_SPP_PVT_LEVEL_MAX', + 'regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'regRLC_SPP_PVT_STAT_0', + 'regRLC_SPP_PVT_STAT_0_BASE_IDX', 'regRLC_SPP_PVT_STAT_1', + 'regRLC_SPP_PVT_STAT_1_BASE_IDX', 'regRLC_SPP_PVT_STAT_2', + 'regRLC_SPP_PVT_STAT_2_BASE_IDX', 'regRLC_SPP_PVT_STAT_3', + 'regRLC_SPP_PVT_STAT_3_BASE_IDX', 'regRLC_SPP_RESET', + 'regRLC_SPP_RESET_BASE_IDX', 'regRLC_SPP_SHADER_PROFILE_EN', + 'regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX', + 'regRLC_SPP_SSF_CAPTURE_EN', 'regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX', + 'regRLC_SPP_SSF_THRESHOLD_0', + 'regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX', + 'regRLC_SPP_SSF_THRESHOLD_1', + 'regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX', + 'regRLC_SPP_SSF_THRESHOLD_2', + 'regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX', + 'regRLC_SPP_STALL_STATE_UPDATE', + 'regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'regRLC_SPP_STATUS', + 'regRLC_SPP_STATUS_BASE_IDX', 'regRLC_SRM_ARAM_ADDR', + 'regRLC_SRM_ARAM_ADDR_BASE_IDX', 'regRLC_SRM_ARAM_DATA', + 'regRLC_SRM_ARAM_DATA_BASE_IDX', 'regRLC_SRM_CNTL', + 'regRLC_SRM_CNTL_BASE_IDX', 'regRLC_SRM_DRAM_ADDR', + 'regRLC_SRM_DRAM_ADDR_BASE_IDX', 'regRLC_SRM_DRAM_DATA', + 'regRLC_SRM_DRAM_DATA_BASE_IDX', 'regRLC_SRM_GPM_ABORT', + 'regRLC_SRM_GPM_ABORT_BASE_IDX', 'regRLC_SRM_GPM_COMMAND', + 'regRLC_SRM_GPM_COMMAND_BASE_IDX', + 'regRLC_SRM_GPM_COMMAND_STATUS', + 'regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_0', + 'regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_1', + 'regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_2', + 'regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_3', + 'regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_4', + 'regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_5', + 'regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_6', + 'regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_7', + 'regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_0', + 'regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_1', + 'regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_2', + 'regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_3', + 'regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_4', + 'regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_5', + 'regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_6', + 'regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_7', + 'regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'regRLC_SRM_STAT', + 'regRLC_SRM_STAT_BASE_IDX', 'regRLC_STAT', + 'regRLC_STATIC_PG_STATUS', 'regRLC_STATIC_PG_STATUS_BASE_IDX', + 'regRLC_STAT_BASE_IDX', 'regRLC_UCODE_CNTL', + 'regRLC_UCODE_CNTL_BASE_IDX', 'regRLC_ULV_RESIDENCY_CNTR_CTRL', + 'regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX', + 'regRLC_ULV_RESIDENCY_EVENT_CNTR', + 'regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX', + 'regRLC_ULV_RESIDENCY_REF_CNTR', + 'regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_UTCL1_STATUS', + 'regRLC_UTCL1_STATUS_2', 'regRLC_UTCL1_STATUS_2_BASE_IDX', + 'regRLC_UTCL1_STATUS_BASE_IDX', 'regRLC_WGP_STATUS', + 'regRLC_WGP_STATUS_BASE_IDX', 'regRLC_XT_CORE_ALT_RESET_VEC', + 'regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX', + 'regRLC_XT_CORE_FAULT_INFO', 'regRLC_XT_CORE_FAULT_INFO_BASE_IDX', + 'regRLC_XT_CORE_INTERRUPT', 'regRLC_XT_CORE_INTERRUPT_BASE_IDX', + 'regRLC_XT_CORE_RESERVED', 'regRLC_XT_CORE_RESERVED_BASE_IDX', + 'regRLC_XT_CORE_STATUS', 'regRLC_XT_CORE_STATUS_BASE_IDX', + 'regRLC_XT_DOORBELL_0_DATA_HI', + 'regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX', + 'regRLC_XT_DOORBELL_0_DATA_LO', + 'regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX', + 'regRLC_XT_DOORBELL_1_DATA_HI', + 'regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX', + 'regRLC_XT_DOORBELL_1_DATA_LO', + 'regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX', + 'regRLC_XT_DOORBELL_2_DATA_HI', + 'regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX', + 'regRLC_XT_DOORBELL_2_DATA_LO', + 'regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX', + 'regRLC_XT_DOORBELL_3_DATA_HI', + 'regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX', + 'regRLC_XT_DOORBELL_3_DATA_LO', + 'regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX', + 'regRLC_XT_DOORBELL_CNTL', 'regRLC_XT_DOORBELL_CNTL_BASE_IDX', + 'regRLC_XT_DOORBELL_RANGE', 'regRLC_XT_DOORBELL_RANGE_BASE_IDX', + 'regRLC_XT_DOORBELL_STAT', 'regRLC_XT_DOORBELL_STAT_BASE_IDX', + 'regRLC_XT_INT_VEC_CLEAR', 'regRLC_XT_INT_VEC_CLEAR_BASE_IDX', + 'regRLC_XT_INT_VEC_FORCE', 'regRLC_XT_INT_VEC_FORCE_BASE_IDX', + 'regRLC_XT_INT_VEC_MUX_INT_SEL', + 'regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX', + 'regRLC_XT_INT_VEC_MUX_SEL', 'regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX', + 'regRMI_CLOCK_CNTRL', 'regRMI_CLOCK_CNTRL_BASE_IDX', + 'regRMI_DEMUX_CNTL', 'regRMI_DEMUX_CNTL_BASE_IDX', + 'regRMI_GENERAL_CNTL', 'regRMI_GENERAL_CNTL1', + 'regRMI_GENERAL_CNTL1_BASE_IDX', 'regRMI_GENERAL_CNTL_BASE_IDX', + 'regRMI_GENERAL_STATUS', 'regRMI_GENERAL_STATUS_BASE_IDX', + 'regRMI_PERFCOUNTER0_HI', 'regRMI_PERFCOUNTER0_HI_BASE_IDX', + 'regRMI_PERFCOUNTER0_LO', 'regRMI_PERFCOUNTER0_LO_BASE_IDX', + 'regRMI_PERFCOUNTER0_SELECT', 'regRMI_PERFCOUNTER0_SELECT1', + 'regRMI_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER1_HI', + 'regRMI_PERFCOUNTER1_HI_BASE_IDX', 'regRMI_PERFCOUNTER1_LO', + 'regRMI_PERFCOUNTER1_LO_BASE_IDX', 'regRMI_PERFCOUNTER1_SELECT', + 'regRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER2_HI', + 'regRMI_PERFCOUNTER2_HI_BASE_IDX', 'regRMI_PERFCOUNTER2_LO', + 'regRMI_PERFCOUNTER2_LO_BASE_IDX', 'regRMI_PERFCOUNTER2_SELECT', + 'regRMI_PERFCOUNTER2_SELECT1', + 'regRMI_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER3_HI', + 'regRMI_PERFCOUNTER3_HI_BASE_IDX', 'regRMI_PERFCOUNTER3_LO', + 'regRMI_PERFCOUNTER3_LO_BASE_IDX', 'regRMI_PERFCOUNTER3_SELECT', + 'regRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'regRMI_PERF_COUNTER_CNTL', + 'regRMI_PERF_COUNTER_CNTL_BASE_IDX', + 'regRMI_PROBE_POP_LOGIC_CNTL', + 'regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'regRMI_RB_GLX_CID_MAP', + 'regRMI_RB_GLX_CID_MAP_BASE_IDX', 'regRMI_SCOREBOARD_CNTL', + 'regRMI_SCOREBOARD_CNTL_BASE_IDX', 'regRMI_SCOREBOARD_STATUS0', + 'regRMI_SCOREBOARD_STATUS0_BASE_IDX', 'regRMI_SCOREBOARD_STATUS1', + 'regRMI_SCOREBOARD_STATUS1_BASE_IDX', 'regRMI_SCOREBOARD_STATUS2', + 'regRMI_SCOREBOARD_STATUS2_BASE_IDX', 'regRMI_SPARE', + 'regRMI_SPARE_1', 'regRMI_SPARE_1_BASE_IDX', 'regRMI_SPARE_2', + 'regRMI_SPARE_2_BASE_IDX', 'regRMI_SPARE_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS0', 'regRMI_SUBBLOCK_STATUS0_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS1', 'regRMI_SUBBLOCK_STATUS1_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS2', 'regRMI_SUBBLOCK_STATUS2_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS3', 'regRMI_SUBBLOCK_STATUS3_BASE_IDX', + 'regRMI_TCIW_FORMATTER0_CNTL', + 'regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX', + 'regRMI_TCIW_FORMATTER1_CNTL', + 'regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'regRMI_UTCL1_CNTL1', + 'regRMI_UTCL1_CNTL1_BASE_IDX', 'regRMI_UTCL1_CNTL2', + 'regRMI_UTCL1_CNTL2_BASE_IDX', 'regRMI_UTCL1_STATUS', + 'regRMI_UTCL1_STATUS_BASE_IDX', 'regRMI_UTC_UNIT_CONFIG', + 'regRMI_UTC_UNIT_CONFIG_BASE_IDX', 'regRMI_UTC_XNACK_N_MISC_CNTL', + 'regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX', + 'regRMI_XBAR_ARBITER_CONFIG', 'regRMI_XBAR_ARBITER_CONFIG_1', + 'regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX', + 'regRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'regRMI_XBAR_CONFIG', + 'regRMI_XBAR_CONFIG_BASE_IDX', 'regRTAVFS_RTAVFS_REG_ADDR', + 'regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'regRTAVFS_RTAVFS_WR_DATA', + 'regRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'regSCRATCH_REG0', + 'regSCRATCH_REG0_BASE_IDX', 'regSCRATCH_REG1', + 'regSCRATCH_REG1_BASE_IDX', 'regSCRATCH_REG2', + 'regSCRATCH_REG2_BASE_IDX', 'regSCRATCH_REG3', + 'regSCRATCH_REG3_BASE_IDX', 'regSCRATCH_REG4', + 'regSCRATCH_REG4_BASE_IDX', 'regSCRATCH_REG5', + 'regSCRATCH_REG5_BASE_IDX', 'regSCRATCH_REG6', + 'regSCRATCH_REG6_BASE_IDX', 'regSCRATCH_REG7', + 'regSCRATCH_REG7_BASE_IDX', 'regSCRATCH_REG_ATOMIC', + 'regSCRATCH_REG_ATOMIC_BASE_IDX', 'regSCRATCH_REG_CMPSWAP_ATOMIC', + 'regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'regSDMA0_AQL_STATUS', + 'regSDMA0_AQL_STATUS_BASE_IDX', 'regSDMA0_ATOMIC_CNTL', + 'regSDMA0_ATOMIC_CNTL_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_HI', + 'regSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_LO', + 'regSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA0_BA_THRESHOLD', + 'regSDMA0_BA_THRESHOLD_BASE_IDX', 'regSDMA0_BROADCAST_UCODE_ADDR', + 'regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX', + 'regSDMA0_BROADCAST_UCODE_DATA', + 'regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA0_CE_CTRL', + 'regSDMA0_CE_CTRL_BASE_IDX', 'regSDMA0_CHICKEN_BITS', + 'regSDMA0_CHICKEN_BITS_2', 'regSDMA0_CHICKEN_BITS_2_BASE_IDX', + 'regSDMA0_CHICKEN_BITS_BASE_IDX', 'regSDMA0_CLOCK_GATING_STATUS', + 'regSDMA0_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA0_CNTL', + 'regSDMA0_CNTL1', 'regSDMA0_CNTL1_BASE_IDX', + 'regSDMA0_CNTL_BASE_IDX', 'regSDMA0_CRD_CNTL', + 'regSDMA0_CRD_CNTL_BASE_IDX', 'regSDMA0_DEC_START', + 'regSDMA0_DEC_START_BASE_IDX', 'regSDMA0_EA_DBIT_ADDR_DATA', + 'regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX', + 'regSDMA0_EA_DBIT_ADDR_INDEX', + 'regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA0_EDC_CONFIG', + 'regSDMA0_EDC_CONFIG_BASE_IDX', 'regSDMA0_EDC_COUNTER', + 'regSDMA0_EDC_COUNTER_BASE_IDX', 'regSDMA0_EDC_COUNTER_CLEAR', + 'regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA0_ERROR_LOG', + 'regSDMA0_ERROR_LOG_BASE_IDX', 'regSDMA0_F32_CNTL', + 'regSDMA0_F32_CNTL_BASE_IDX', 'regSDMA0_F32_COUNTER', + 'regSDMA0_F32_COUNTER_BASE_IDX', 'regSDMA0_F32_MISC_CNTL', + 'regSDMA0_F32_MISC_CNTL_BASE_IDX', 'regSDMA0_FED_STATUS', + 'regSDMA0_FED_STATUS_BASE_IDX', 'regSDMA0_FREEZE', + 'regSDMA0_FREEZE_BASE_IDX', 'regSDMA0_GB_ADDR_CONFIG', + 'regSDMA0_GB_ADDR_CONFIG_BASE_IDX', + 'regSDMA0_GB_ADDR_CONFIG_READ', + 'regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX', + 'regSDMA0_GLOBAL_QUANTUM', 'regSDMA0_GLOBAL_QUANTUM_BASE_IDX', + 'regSDMA0_GLOBAL_TIMESTAMP_HI', + 'regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX', + 'regSDMA0_GLOBAL_TIMESTAMP_LO', + 'regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX', + 'regSDMA0_HBM_PAGE_CONFIG', 'regSDMA0_HBM_PAGE_CONFIG_BASE_IDX', + 'regSDMA0_HOLE_ADDR_HI', 'regSDMA0_HOLE_ADDR_HI_BASE_IDX', + 'regSDMA0_HOLE_ADDR_LO', 'regSDMA0_HOLE_ADDR_LO_BASE_IDX', + 'regSDMA0_IB_OFFSET_FETCH', 'regSDMA0_IB_OFFSET_FETCH_BASE_IDX', + 'regSDMA0_ID', 'regSDMA0_ID_BASE_IDX', 'regSDMA0_INT_STATUS', + 'regSDMA0_INT_STATUS_BASE_IDX', 'regSDMA0_PERFCNT_MISC_CNTL', + 'regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX', + 'regSDMA0_PERFCNT_PERFCOUNTER0_CFG', + 'regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', + 'regSDMA0_PERFCNT_PERFCOUNTER1_CFG', + 'regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', + 'regSDMA0_PERFCNT_PERFCOUNTER_HI', + 'regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX', + 'regSDMA0_PERFCNT_PERFCOUNTER_LO', + 'regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX', + 'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL', + 'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regSDMA0_PERFCOUNTER0_HI', 'regSDMA0_PERFCOUNTER0_HI_BASE_IDX', + 'regSDMA0_PERFCOUNTER0_LO', 'regSDMA0_PERFCOUNTER0_LO_BASE_IDX', + 'regSDMA0_PERFCOUNTER0_SELECT', 'regSDMA0_PERFCOUNTER0_SELECT1', + 'regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX', + 'regSDMA0_PERFCOUNTER1_HI', 'regSDMA0_PERFCOUNTER1_HI_BASE_IDX', + 'regSDMA0_PERFCOUNTER1_LO', 'regSDMA0_PERFCOUNTER1_LO_BASE_IDX', + 'regSDMA0_PERFCOUNTER1_SELECT', 'regSDMA0_PERFCOUNTER1_SELECT1', + 'regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX', + 'regSDMA0_PHYSICAL_ADDR_HI', 'regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX', + 'regSDMA0_PHYSICAL_ADDR_LO', 'regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX', + 'regSDMA0_POWER_CNTL', 'regSDMA0_POWER_CNTL_BASE_IDX', + 'regSDMA0_PROCESS_QUANTUM0', 'regSDMA0_PROCESS_QUANTUM0_BASE_IDX', + 'regSDMA0_PROCESS_QUANTUM1', 'regSDMA0_PROCESS_QUANTUM1_BASE_IDX', + 'regSDMA0_PROGRAM', 'regSDMA0_PROGRAM_BASE_IDX', + 'regSDMA0_PUB_DUMMY_REG0', 'regSDMA0_PUB_DUMMY_REG0_BASE_IDX', + 'regSDMA0_PUB_DUMMY_REG1', 'regSDMA0_PUB_DUMMY_REG1_BASE_IDX', + 'regSDMA0_PUB_DUMMY_REG2', 'regSDMA0_PUB_DUMMY_REG2_BASE_IDX', + 'regSDMA0_PUB_DUMMY_REG3', 'regSDMA0_PUB_DUMMY_REG3_BASE_IDX', + 'regSDMA0_QUEUE0_CONTEXT_STATUS', + 'regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE0_CSA_ADDR_HI', + 'regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE0_CSA_ADDR_LO', + 'regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE0_DOORBELL', 'regSDMA0_QUEUE0_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE0_DOORBELL_LOG', + 'regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE0_DOORBELL_OFFSET', + 'regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE0_DUMMY_REG', 'regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE0_IB_BASE_HI', + 'regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE0_IB_BASE_LO', + 'regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE0_IB_CNTL', + 'regSDMA0_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_IB_OFFSET', + 'regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE0_IB_RPTR', + 'regSDMA0_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_IB_SIZE', + 'regSDMA0_QUEUE0_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE0_IB_SUB_REMAIN', + 'regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_CNTL', + 'regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA0', + 'regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA1', 'regSDMA0_QUEUE0_MIDCMD_DATA10', + 'regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA2', + 'regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA3', + 'regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA4', + 'regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA5', + 'regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA6', + 'regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA7', + 'regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA8', + 'regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE0_MIDCMD_DATA9', + 'regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE0_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE0_PREEMPT', 'regSDMA0_QUEUE0_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE0_RB_AQL_CNTL', + 'regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE', + 'regSDMA0_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE_HI', + 'regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_CNTL', + 'regSDMA0_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_PREEMPT', + 'regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR', + 'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR_HI', + 'regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR', + 'regSDMA0_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR_HI', + 'regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE0_SCHEDULE_CNTL', + 'regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE0_SKIP_CNTL', 'regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE1_CONTEXT_STATUS', + 'regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE1_CSA_ADDR_HI', + 'regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE1_CSA_ADDR_LO', + 'regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE1_DOORBELL', 'regSDMA0_QUEUE1_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE1_DOORBELL_LOG', + 'regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE1_DOORBELL_OFFSET', + 'regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE1_DUMMY_REG', 'regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE1_IB_BASE_HI', + 'regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE1_IB_BASE_LO', + 'regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE1_IB_CNTL', + 'regSDMA0_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_IB_OFFSET', + 'regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE1_IB_RPTR', + 'regSDMA0_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_IB_SIZE', + 'regSDMA0_QUEUE1_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE1_IB_SUB_REMAIN', + 'regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_CNTL', + 'regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA0', + 'regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA1', 'regSDMA0_QUEUE1_MIDCMD_DATA10', + 'regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA2', + 'regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA3', + 'regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA4', + 'regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA5', + 'regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA6', + 'regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA7', + 'regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA8', + 'regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE1_MIDCMD_DATA9', + 'regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE1_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE1_PREEMPT', 'regSDMA0_QUEUE1_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE1_RB_AQL_CNTL', + 'regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE', + 'regSDMA0_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE_HI', + 'regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_CNTL', + 'regSDMA0_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_PREEMPT', + 'regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR', + 'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR_HI', + 'regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR', + 'regSDMA0_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR_HI', + 'regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE1_SCHEDULE_CNTL', + 'regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE1_SKIP_CNTL', 'regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE2_CONTEXT_STATUS', + 'regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE2_CSA_ADDR_HI', + 'regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE2_CSA_ADDR_LO', + 'regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE2_DOORBELL', 'regSDMA0_QUEUE2_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE2_DOORBELL_LOG', + 'regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE2_DOORBELL_OFFSET', + 'regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE2_DUMMY_REG', 'regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE2_IB_BASE_HI', + 'regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE2_IB_BASE_LO', + 'regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE2_IB_CNTL', + 'regSDMA0_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_IB_OFFSET', + 'regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE2_IB_RPTR', + 'regSDMA0_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_IB_SIZE', + 'regSDMA0_QUEUE2_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE2_IB_SUB_REMAIN', + 'regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_CNTL', + 'regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA0', + 'regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA1', 'regSDMA0_QUEUE2_MIDCMD_DATA10', + 'regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA2', + 'regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA3', + 'regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA4', + 'regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA5', + 'regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA6', + 'regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA7', + 'regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA8', + 'regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE2_MIDCMD_DATA9', + 'regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE2_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE2_PREEMPT', 'regSDMA0_QUEUE2_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE2_RB_AQL_CNTL', + 'regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE', + 'regSDMA0_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE_HI', + 'regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_CNTL', + 'regSDMA0_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_PREEMPT', + 'regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR', + 'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR_HI', + 'regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR', + 'regSDMA0_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR_HI', + 'regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE2_SCHEDULE_CNTL', + 'regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE2_SKIP_CNTL', 'regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE3_CONTEXT_STATUS', + 'regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE3_CSA_ADDR_HI', + 'regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE3_CSA_ADDR_LO', + 'regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE3_DOORBELL', 'regSDMA0_QUEUE3_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE3_DOORBELL_LOG', + 'regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE3_DOORBELL_OFFSET', + 'regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE3_DUMMY_REG', 'regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE3_IB_BASE_HI', + 'regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE3_IB_BASE_LO', + 'regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE3_IB_CNTL', + 'regSDMA0_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_IB_OFFSET', + 'regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE3_IB_RPTR', + 'regSDMA0_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_IB_SIZE', + 'regSDMA0_QUEUE3_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE3_IB_SUB_REMAIN', + 'regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_CNTL', + 'regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA0', + 'regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA1', 'regSDMA0_QUEUE3_MIDCMD_DATA10', + 'regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA2', + 'regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA3', + 'regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA4', + 'regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA5', + 'regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA6', + 'regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA7', + 'regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA8', + 'regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE3_MIDCMD_DATA9', + 'regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE3_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE3_PREEMPT', 'regSDMA0_QUEUE3_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE3_RB_AQL_CNTL', + 'regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE', + 'regSDMA0_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE_HI', + 'regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_CNTL', + 'regSDMA0_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_PREEMPT', + 'regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR', + 'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR_HI', + 'regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR', + 'regSDMA0_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR_HI', + 'regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE3_SCHEDULE_CNTL', + 'regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE3_SKIP_CNTL', 'regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE4_CONTEXT_STATUS', + 'regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE4_CSA_ADDR_HI', + 'regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE4_CSA_ADDR_LO', + 'regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE4_DOORBELL', 'regSDMA0_QUEUE4_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE4_DOORBELL_LOG', + 'regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE4_DOORBELL_OFFSET', + 'regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE4_DUMMY_REG', 'regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE4_IB_BASE_HI', + 'regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE4_IB_BASE_LO', + 'regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE4_IB_CNTL', + 'regSDMA0_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_IB_OFFSET', + 'regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE4_IB_RPTR', + 'regSDMA0_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_IB_SIZE', + 'regSDMA0_QUEUE4_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE4_IB_SUB_REMAIN', + 'regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_CNTL', + 'regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA0', + 'regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA1', 'regSDMA0_QUEUE4_MIDCMD_DATA10', + 'regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA2', + 'regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA3', + 'regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA4', + 'regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA5', + 'regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA6', + 'regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA7', + 'regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA8', + 'regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE4_MIDCMD_DATA9', + 'regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE4_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE4_PREEMPT', 'regSDMA0_QUEUE4_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE4_RB_AQL_CNTL', + 'regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE', + 'regSDMA0_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE_HI', + 'regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_CNTL', + 'regSDMA0_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_PREEMPT', + 'regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR', + 'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR_HI', + 'regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR', + 'regSDMA0_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR_HI', + 'regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE4_SCHEDULE_CNTL', + 'regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE4_SKIP_CNTL', 'regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE5_CONTEXT_STATUS', + 'regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE5_CSA_ADDR_HI', + 'regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE5_CSA_ADDR_LO', + 'regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE5_DOORBELL', 'regSDMA0_QUEUE5_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE5_DOORBELL_LOG', + 'regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE5_DOORBELL_OFFSET', + 'regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE5_DUMMY_REG', 'regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE5_IB_BASE_HI', + 'regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE5_IB_BASE_LO', + 'regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE5_IB_CNTL', + 'regSDMA0_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_IB_OFFSET', + 'regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE5_IB_RPTR', + 'regSDMA0_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_IB_SIZE', + 'regSDMA0_QUEUE5_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE5_IB_SUB_REMAIN', + 'regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_CNTL', + 'regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA0', + 'regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA1', 'regSDMA0_QUEUE5_MIDCMD_DATA10', + 'regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA2', + 'regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA3', + 'regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA4', + 'regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA5', + 'regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA6', + 'regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA7', + 'regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA8', + 'regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE5_MIDCMD_DATA9', + 'regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE5_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE5_PREEMPT', 'regSDMA0_QUEUE5_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE5_RB_AQL_CNTL', + 'regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE', + 'regSDMA0_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE_HI', + 'regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_CNTL', + 'regSDMA0_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_PREEMPT', + 'regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR', + 'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR_HI', + 'regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR', + 'regSDMA0_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR_HI', + 'regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE5_SCHEDULE_CNTL', + 'regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE5_SKIP_CNTL', 'regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE6_CONTEXT_STATUS', + 'regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE6_CSA_ADDR_HI', + 'regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE6_CSA_ADDR_LO', + 'regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE6_DOORBELL', 'regSDMA0_QUEUE6_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE6_DOORBELL_LOG', + 'regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE6_DOORBELL_OFFSET', + 'regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE6_DUMMY_REG', 'regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE6_IB_BASE_HI', + 'regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE6_IB_BASE_LO', + 'regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE6_IB_CNTL', + 'regSDMA0_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_IB_OFFSET', + 'regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE6_IB_RPTR', + 'regSDMA0_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_IB_SIZE', + 'regSDMA0_QUEUE6_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE6_IB_SUB_REMAIN', + 'regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_CNTL', + 'regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA0', + 'regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA1', 'regSDMA0_QUEUE6_MIDCMD_DATA10', + 'regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA2', + 'regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA3', + 'regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA4', + 'regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA5', + 'regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA6', + 'regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA7', + 'regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA8', + 'regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE6_MIDCMD_DATA9', + 'regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE6_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE6_PREEMPT', 'regSDMA0_QUEUE6_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE6_RB_AQL_CNTL', + 'regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE', + 'regSDMA0_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE_HI', + 'regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_CNTL', + 'regSDMA0_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_PREEMPT', + 'regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR', + 'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR_HI', + 'regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR', + 'regSDMA0_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR_HI', + 'regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE6_SCHEDULE_CNTL', + 'regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE6_SKIP_CNTL', 'regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE7_CONTEXT_STATUS', + 'regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX', + 'regSDMA0_QUEUE7_CSA_ADDR_HI', + 'regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE7_CSA_ADDR_LO', + 'regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE7_DOORBELL', 'regSDMA0_QUEUE7_DOORBELL_BASE_IDX', + 'regSDMA0_QUEUE7_DOORBELL_LOG', + 'regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX', + 'regSDMA0_QUEUE7_DOORBELL_OFFSET', + 'regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA0_QUEUE7_DUMMY_REG', 'regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX', + 'regSDMA0_QUEUE7_IB_BASE_HI', + 'regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX', + 'regSDMA0_QUEUE7_IB_BASE_LO', + 'regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE7_IB_CNTL', + 'regSDMA0_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_IB_OFFSET', + 'regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE7_IB_RPTR', + 'regSDMA0_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_IB_SIZE', + 'regSDMA0_QUEUE7_IB_SIZE_BASE_IDX', + 'regSDMA0_QUEUE7_IB_SUB_REMAIN', + 'regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_CNTL', + 'regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA0', + 'regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA1', 'regSDMA0_QUEUE7_MIDCMD_DATA10', + 'regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA2', + 'regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA3', + 'regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA4', + 'regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA5', + 'regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA6', + 'regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA7', + 'regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA8', + 'regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX', + 'regSDMA0_QUEUE7_MIDCMD_DATA9', + 'regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX', + 'regSDMA0_QUEUE7_MINOR_PTR_UPDATE', + 'regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA0_QUEUE7_PREEMPT', 'regSDMA0_QUEUE7_PREEMPT_BASE_IDX', + 'regSDMA0_QUEUE7_RB_AQL_CNTL', + 'regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE', + 'regSDMA0_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE_HI', + 'regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_CNTL', + 'regSDMA0_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_PREEMPT', + 'regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR', + 'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI', + 'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO', + 'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR_HI', + 'regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR', + 'regSDMA0_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR_HI', + 'regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX', + 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI', + 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO', + 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA0_QUEUE7_SCHEDULE_CNTL', + 'regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA0_QUEUE7_SKIP_CNTL', 'regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX', + 'regSDMA0_QUEUE_RESET_REQ', 'regSDMA0_QUEUE_RESET_REQ_BASE_IDX', + 'regSDMA0_QUEUE_STATUS0', 'regSDMA0_QUEUE_STATUS0_BASE_IDX', + 'regSDMA0_RB_RPTR_FETCH', 'regSDMA0_RB_RPTR_FETCH_BASE_IDX', + 'regSDMA0_RB_RPTR_FETCH_HI', 'regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX', + 'regSDMA0_RELAX_ORDERING_LUT', + 'regSDMA0_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA0_RLC_CGCG_CTRL', + 'regSDMA0_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA0_SCRATCH_RAM_ADDR', + 'regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA0_SCRATCH_RAM_DATA', + 'regSDMA0_SCRATCH_RAM_DATA_BASE_IDX', + 'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL', + 'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', + 'regSDMA0_STATUS1_REG', 'regSDMA0_STATUS1_REG_BASE_IDX', + 'regSDMA0_STATUS2_REG', 'regSDMA0_STATUS2_REG_BASE_IDX', + 'regSDMA0_STATUS3_REG', 'regSDMA0_STATUS3_REG_BASE_IDX', + 'regSDMA0_STATUS4_REG', 'regSDMA0_STATUS4_REG_BASE_IDX', + 'regSDMA0_STATUS5_REG', 'regSDMA0_STATUS5_REG_BASE_IDX', + 'regSDMA0_STATUS6_REG', 'regSDMA0_STATUS6_REG_BASE_IDX', + 'regSDMA0_STATUS_REG', 'regSDMA0_STATUS_REG_BASE_IDX', + 'regSDMA0_TILING_CONFIG', 'regSDMA0_TILING_CONFIG_BASE_IDX', + 'regSDMA0_TIMESTAMP_CNTL', 'regSDMA0_TIMESTAMP_CNTL_BASE_IDX', + 'regSDMA0_TLBI_GCR_CNTL', 'regSDMA0_TLBI_GCR_CNTL_BASE_IDX', + 'regSDMA0_UCODE1_CHECKSUM', 'regSDMA0_UCODE1_CHECKSUM_BASE_IDX', + 'regSDMA0_UCODE_ADDR', 'regSDMA0_UCODE_ADDR_BASE_IDX', + 'regSDMA0_UCODE_CHECKSUM', 'regSDMA0_UCODE_CHECKSUM_BASE_IDX', + 'regSDMA0_UCODE_DATA', 'regSDMA0_UCODE_DATA_BASE_IDX', + 'regSDMA0_UCODE_SELFLOAD_CONTROL', + 'regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA0_UTCL1_CNTL', + 'regSDMA0_UTCL1_CNTL_BASE_IDX', 'regSDMA0_UTCL1_INV0', + 'regSDMA0_UTCL1_INV0_BASE_IDX', 'regSDMA0_UTCL1_INV1', + 'regSDMA0_UTCL1_INV1_BASE_IDX', 'regSDMA0_UTCL1_INV2', + 'regSDMA0_UTCL1_INV2_BASE_IDX', 'regSDMA0_UTCL1_PAGE', + 'regSDMA0_UTCL1_PAGE_BASE_IDX', 'regSDMA0_UTCL1_RD_STATUS', + 'regSDMA0_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK0', + 'regSDMA0_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK1', + 'regSDMA0_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA0_UTCL1_TIMEOUT', + 'regSDMA0_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA0_UTCL1_WATERMK', + 'regSDMA0_UTCL1_WATERMK_BASE_IDX', 'regSDMA0_UTCL1_WR_STATUS', + 'regSDMA0_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK0', + 'regSDMA0_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK1', + 'regSDMA0_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA0_VERSION', + 'regSDMA0_VERSION_BASE_IDX', 'regSDMA0_WATCHDOG_CNTL', + 'regSDMA0_WATCHDOG_CNTL_BASE_IDX', 'regSDMA1_AQL_STATUS', + 'regSDMA1_AQL_STATUS_BASE_IDX', 'regSDMA1_ATOMIC_CNTL', + 'regSDMA1_ATOMIC_CNTL_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_HI', + 'regSDMA1_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_LO', + 'regSDMA1_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA1_BA_THRESHOLD', + 'regSDMA1_BA_THRESHOLD_BASE_IDX', 'regSDMA1_BROADCAST_UCODE_ADDR', + 'regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX', + 'regSDMA1_BROADCAST_UCODE_DATA', + 'regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA1_CE_CTRL', + 'regSDMA1_CE_CTRL_BASE_IDX', 'regSDMA1_CHICKEN_BITS', + 'regSDMA1_CHICKEN_BITS_2', 'regSDMA1_CHICKEN_BITS_2_BASE_IDX', + 'regSDMA1_CHICKEN_BITS_BASE_IDX', 'regSDMA1_CLOCK_GATING_STATUS', + 'regSDMA1_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA1_CNTL', + 'regSDMA1_CNTL1', 'regSDMA1_CNTL1_BASE_IDX', + 'regSDMA1_CNTL_BASE_IDX', 'regSDMA1_CRD_CNTL', + 'regSDMA1_CRD_CNTL_BASE_IDX', 'regSDMA1_DEC_START', + 'regSDMA1_DEC_START_BASE_IDX', 'regSDMA1_EA_DBIT_ADDR_DATA', + 'regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX', + 'regSDMA1_EA_DBIT_ADDR_INDEX', + 'regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA1_EDC_CONFIG', + 'regSDMA1_EDC_CONFIG_BASE_IDX', 'regSDMA1_EDC_COUNTER', + 'regSDMA1_EDC_COUNTER_BASE_IDX', 'regSDMA1_EDC_COUNTER_CLEAR', + 'regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA1_ERROR_LOG', + 'regSDMA1_ERROR_LOG_BASE_IDX', 'regSDMA1_F32_CNTL', + 'regSDMA1_F32_CNTL_BASE_IDX', 'regSDMA1_F32_COUNTER', + 'regSDMA1_F32_COUNTER_BASE_IDX', 'regSDMA1_F32_MISC_CNTL', + 'regSDMA1_F32_MISC_CNTL_BASE_IDX', 'regSDMA1_FED_STATUS', + 'regSDMA1_FED_STATUS_BASE_IDX', 'regSDMA1_FREEZE', + 'regSDMA1_FREEZE_BASE_IDX', 'regSDMA1_GB_ADDR_CONFIG', + 'regSDMA1_GB_ADDR_CONFIG_BASE_IDX', + 'regSDMA1_GB_ADDR_CONFIG_READ', + 'regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX', + 'regSDMA1_GLOBAL_QUANTUM', 'regSDMA1_GLOBAL_QUANTUM_BASE_IDX', + 'regSDMA1_GLOBAL_TIMESTAMP_HI', + 'regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX', + 'regSDMA1_GLOBAL_TIMESTAMP_LO', + 'regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX', + 'regSDMA1_HBM_PAGE_CONFIG', 'regSDMA1_HBM_PAGE_CONFIG_BASE_IDX', + 'regSDMA1_HOLE_ADDR_HI', 'regSDMA1_HOLE_ADDR_HI_BASE_IDX', + 'regSDMA1_HOLE_ADDR_LO', 'regSDMA1_HOLE_ADDR_LO_BASE_IDX', + 'regSDMA1_IB_OFFSET_FETCH', 'regSDMA1_IB_OFFSET_FETCH_BASE_IDX', + 'regSDMA1_ID', 'regSDMA1_ID_BASE_IDX', 'regSDMA1_INT_STATUS', + 'regSDMA1_INT_STATUS_BASE_IDX', 'regSDMA1_PERFCNT_MISC_CNTL', + 'regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX', + 'regSDMA1_PERFCNT_PERFCOUNTER0_CFG', + 'regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', + 'regSDMA1_PERFCNT_PERFCOUNTER1_CFG', + 'regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', + 'regSDMA1_PERFCNT_PERFCOUNTER_HI', + 'regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX', + 'regSDMA1_PERFCNT_PERFCOUNTER_LO', + 'regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX', + 'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL', + 'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regSDMA1_PERFCOUNTER0_HI', 'regSDMA1_PERFCOUNTER0_HI_BASE_IDX', + 'regSDMA1_PERFCOUNTER0_LO', 'regSDMA1_PERFCOUNTER0_LO_BASE_IDX', + 'regSDMA1_PERFCOUNTER0_SELECT', 'regSDMA1_PERFCOUNTER0_SELECT1', + 'regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX', + 'regSDMA1_PERFCOUNTER1_HI', 'regSDMA1_PERFCOUNTER1_HI_BASE_IDX', + 'regSDMA1_PERFCOUNTER1_LO', 'regSDMA1_PERFCOUNTER1_LO_BASE_IDX', + 'regSDMA1_PERFCOUNTER1_SELECT', 'regSDMA1_PERFCOUNTER1_SELECT1', + 'regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX', + 'regSDMA1_PHYSICAL_ADDR_HI', 'regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX', + 'regSDMA1_PHYSICAL_ADDR_LO', 'regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX', + 'regSDMA1_POWER_CNTL', 'regSDMA1_POWER_CNTL_BASE_IDX', + 'regSDMA1_PROCESS_QUANTUM0', 'regSDMA1_PROCESS_QUANTUM0_BASE_IDX', + 'regSDMA1_PROCESS_QUANTUM1', 'regSDMA1_PROCESS_QUANTUM1_BASE_IDX', + 'regSDMA1_PROGRAM', 'regSDMA1_PROGRAM_BASE_IDX', + 'regSDMA1_PUB_DUMMY_REG0', 'regSDMA1_PUB_DUMMY_REG0_BASE_IDX', + 'regSDMA1_PUB_DUMMY_REG1', 'regSDMA1_PUB_DUMMY_REG1_BASE_IDX', + 'regSDMA1_PUB_DUMMY_REG2', 'regSDMA1_PUB_DUMMY_REG2_BASE_IDX', + 'regSDMA1_PUB_DUMMY_REG3', 'regSDMA1_PUB_DUMMY_REG3_BASE_IDX', + 'regSDMA1_QUEUE0_CONTEXT_STATUS', + 'regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE0_CSA_ADDR_HI', + 'regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE0_CSA_ADDR_LO', + 'regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE0_DOORBELL', 'regSDMA1_QUEUE0_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE0_DOORBELL_LOG', + 'regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE0_DOORBELL_OFFSET', + 'regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE0_DUMMY_REG', 'regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE0_IB_BASE_HI', + 'regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE0_IB_BASE_LO', + 'regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE0_IB_CNTL', + 'regSDMA1_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_IB_OFFSET', + 'regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE0_IB_RPTR', + 'regSDMA1_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_IB_SIZE', + 'regSDMA1_QUEUE0_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE0_IB_SUB_REMAIN', + 'regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_CNTL', + 'regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA0', + 'regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA1', 'regSDMA1_QUEUE0_MIDCMD_DATA10', + 'regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA2', + 'regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA3', + 'regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA4', + 'regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA5', + 'regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA6', + 'regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA7', + 'regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA8', + 'regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE0_MIDCMD_DATA9', + 'regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE0_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE0_PREEMPT', 'regSDMA1_QUEUE0_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE0_RB_AQL_CNTL', + 'regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE', + 'regSDMA1_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE_HI', + 'regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_CNTL', + 'regSDMA1_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_PREEMPT', + 'regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR', + 'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR_HI', + 'regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR', + 'regSDMA1_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR_HI', + 'regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE0_SCHEDULE_CNTL', + 'regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE0_SKIP_CNTL', 'regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE1_CONTEXT_STATUS', + 'regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE1_CSA_ADDR_HI', + 'regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE1_CSA_ADDR_LO', + 'regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE1_DOORBELL', 'regSDMA1_QUEUE1_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE1_DOORBELL_LOG', + 'regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE1_DOORBELL_OFFSET', + 'regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE1_DUMMY_REG', 'regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE1_IB_BASE_HI', + 'regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE1_IB_BASE_LO', + 'regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE1_IB_CNTL', + 'regSDMA1_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_IB_OFFSET', + 'regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE1_IB_RPTR', + 'regSDMA1_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_IB_SIZE', + 'regSDMA1_QUEUE1_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE1_IB_SUB_REMAIN', + 'regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_CNTL', + 'regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA0', + 'regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA1', 'regSDMA1_QUEUE1_MIDCMD_DATA10', + 'regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA2', + 'regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA3', + 'regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA4', + 'regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA5', + 'regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA6', + 'regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA7', + 'regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA8', + 'regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE1_MIDCMD_DATA9', + 'regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE1_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE1_PREEMPT', 'regSDMA1_QUEUE1_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE1_RB_AQL_CNTL', + 'regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE', + 'regSDMA1_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE_HI', + 'regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_CNTL', + 'regSDMA1_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_PREEMPT', + 'regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR', + 'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR_HI', + 'regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR', + 'regSDMA1_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR_HI', + 'regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE1_SCHEDULE_CNTL', + 'regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE1_SKIP_CNTL', 'regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE2_CONTEXT_STATUS', + 'regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE2_CSA_ADDR_HI', + 'regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE2_CSA_ADDR_LO', + 'regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE2_DOORBELL', 'regSDMA1_QUEUE2_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE2_DOORBELL_LOG', + 'regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE2_DOORBELL_OFFSET', + 'regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE2_DUMMY_REG', 'regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE2_IB_BASE_HI', + 'regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE2_IB_BASE_LO', + 'regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE2_IB_CNTL', + 'regSDMA1_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_IB_OFFSET', + 'regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE2_IB_RPTR', + 'regSDMA1_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_IB_SIZE', + 'regSDMA1_QUEUE2_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE2_IB_SUB_REMAIN', + 'regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_CNTL', + 'regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA0', + 'regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA1', 'regSDMA1_QUEUE2_MIDCMD_DATA10', + 'regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA2', + 'regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA3', + 'regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA4', + 'regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA5', + 'regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA6', + 'regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA7', + 'regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA8', + 'regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE2_MIDCMD_DATA9', + 'regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE2_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE2_PREEMPT', 'regSDMA1_QUEUE2_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE2_RB_AQL_CNTL', + 'regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE', + 'regSDMA1_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE_HI', + 'regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_CNTL', + 'regSDMA1_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_PREEMPT', + 'regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR', + 'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR_HI', + 'regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR', + 'regSDMA1_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR_HI', + 'regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE2_SCHEDULE_CNTL', + 'regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE2_SKIP_CNTL', 'regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE3_CONTEXT_STATUS', + 'regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE3_CSA_ADDR_HI', + 'regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE3_CSA_ADDR_LO', + 'regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE3_DOORBELL', 'regSDMA1_QUEUE3_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE3_DOORBELL_LOG', + 'regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE3_DOORBELL_OFFSET', + 'regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE3_DUMMY_REG', 'regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE3_IB_BASE_HI', + 'regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE3_IB_BASE_LO', + 'regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE3_IB_CNTL', + 'regSDMA1_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_IB_OFFSET', + 'regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE3_IB_RPTR', + 'regSDMA1_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_IB_SIZE', + 'regSDMA1_QUEUE3_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE3_IB_SUB_REMAIN', + 'regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_CNTL', + 'regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA0', + 'regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA1', 'regSDMA1_QUEUE3_MIDCMD_DATA10', + 'regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA2', + 'regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA3', + 'regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA4', + 'regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA5', + 'regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA6', + 'regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA7', + 'regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA8', + 'regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE3_MIDCMD_DATA9', + 'regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE3_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE3_PREEMPT', 'regSDMA1_QUEUE3_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE3_RB_AQL_CNTL', + 'regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE', + 'regSDMA1_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE_HI', + 'regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_CNTL', + 'regSDMA1_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_PREEMPT', + 'regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR', + 'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR_HI', + 'regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR', + 'regSDMA1_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR_HI', + 'regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE3_SCHEDULE_CNTL', + 'regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE3_SKIP_CNTL', 'regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE4_CONTEXT_STATUS', + 'regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE4_CSA_ADDR_HI', + 'regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE4_CSA_ADDR_LO', + 'regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE4_DOORBELL', 'regSDMA1_QUEUE4_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE4_DOORBELL_LOG', + 'regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE4_DOORBELL_OFFSET', + 'regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE4_DUMMY_REG', 'regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE4_IB_BASE_HI', + 'regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE4_IB_BASE_LO', + 'regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE4_IB_CNTL', + 'regSDMA1_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_IB_OFFSET', + 'regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE4_IB_RPTR', + 'regSDMA1_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_IB_SIZE', + 'regSDMA1_QUEUE4_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE4_IB_SUB_REMAIN', + 'regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_CNTL', + 'regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA0', + 'regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA1', 'regSDMA1_QUEUE4_MIDCMD_DATA10', + 'regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA2', + 'regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA3', + 'regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA4', + 'regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA5', + 'regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA6', + 'regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA7', + 'regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA8', + 'regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE4_MIDCMD_DATA9', + 'regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE4_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE4_PREEMPT', 'regSDMA1_QUEUE4_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE4_RB_AQL_CNTL', + 'regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE', + 'regSDMA1_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE_HI', + 'regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_CNTL', + 'regSDMA1_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_PREEMPT', + 'regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR', + 'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR_HI', + 'regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR', + 'regSDMA1_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR_HI', + 'regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE4_SCHEDULE_CNTL', + 'regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE4_SKIP_CNTL', 'regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE5_CONTEXT_STATUS', + 'regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE5_CSA_ADDR_HI', + 'regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE5_CSA_ADDR_LO', + 'regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE5_DOORBELL', 'regSDMA1_QUEUE5_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE5_DOORBELL_LOG', + 'regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE5_DOORBELL_OFFSET', + 'regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE5_DUMMY_REG', 'regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE5_IB_BASE_HI', + 'regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE5_IB_BASE_LO', + 'regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE5_IB_CNTL', + 'regSDMA1_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_IB_OFFSET', + 'regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE5_IB_RPTR', + 'regSDMA1_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_IB_SIZE', + 'regSDMA1_QUEUE5_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE5_IB_SUB_REMAIN', + 'regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_CNTL', + 'regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA0', + 'regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA1', 'regSDMA1_QUEUE5_MIDCMD_DATA10', + 'regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA2', + 'regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA3', + 'regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA4', + 'regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA5', + 'regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA6', + 'regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA7', + 'regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA8', + 'regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE5_MIDCMD_DATA9', + 'regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE5_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE5_PREEMPT', 'regSDMA1_QUEUE5_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE5_RB_AQL_CNTL', + 'regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE', + 'regSDMA1_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE_HI', + 'regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_CNTL', + 'regSDMA1_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_PREEMPT', + 'regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR', + 'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR_HI', + 'regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR', + 'regSDMA1_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR_HI', + 'regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE5_SCHEDULE_CNTL', + 'regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE5_SKIP_CNTL', 'regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE6_CONTEXT_STATUS', + 'regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE6_CSA_ADDR_HI', + 'regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE6_CSA_ADDR_LO', + 'regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE6_DOORBELL', 'regSDMA1_QUEUE6_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE6_DOORBELL_LOG', + 'regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE6_DOORBELL_OFFSET', + 'regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE6_DUMMY_REG', 'regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE6_IB_BASE_HI', + 'regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE6_IB_BASE_LO', + 'regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE6_IB_CNTL', + 'regSDMA1_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_IB_OFFSET', + 'regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE6_IB_RPTR', + 'regSDMA1_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_IB_SIZE', + 'regSDMA1_QUEUE6_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE6_IB_SUB_REMAIN', + 'regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_CNTL', + 'regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA0', + 'regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA1', 'regSDMA1_QUEUE6_MIDCMD_DATA10', + 'regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA2', + 'regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA3', + 'regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA4', + 'regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA5', + 'regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA6', + 'regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA7', + 'regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA8', + 'regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE6_MIDCMD_DATA9', + 'regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE6_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE6_PREEMPT', 'regSDMA1_QUEUE6_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE6_RB_AQL_CNTL', + 'regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE', + 'regSDMA1_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE_HI', + 'regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_CNTL', + 'regSDMA1_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_PREEMPT', + 'regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR', + 'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR_HI', + 'regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR', + 'regSDMA1_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR_HI', + 'regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE6_SCHEDULE_CNTL', + 'regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE6_SKIP_CNTL', 'regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE7_CONTEXT_STATUS', + 'regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX', + 'regSDMA1_QUEUE7_CSA_ADDR_HI', + 'regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE7_CSA_ADDR_LO', + 'regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE7_DOORBELL', 'regSDMA1_QUEUE7_DOORBELL_BASE_IDX', + 'regSDMA1_QUEUE7_DOORBELL_LOG', + 'regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX', + 'regSDMA1_QUEUE7_DOORBELL_OFFSET', + 'regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX', + 'regSDMA1_QUEUE7_DUMMY_REG', 'regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX', + 'regSDMA1_QUEUE7_IB_BASE_HI', + 'regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX', + 'regSDMA1_QUEUE7_IB_BASE_LO', + 'regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE7_IB_CNTL', + 'regSDMA1_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_IB_OFFSET', + 'regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE7_IB_RPTR', + 'regSDMA1_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_IB_SIZE', + 'regSDMA1_QUEUE7_IB_SIZE_BASE_IDX', + 'regSDMA1_QUEUE7_IB_SUB_REMAIN', + 'regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_CNTL', + 'regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA0', + 'regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA1', 'regSDMA1_QUEUE7_MIDCMD_DATA10', + 'regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA2', + 'regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA3', + 'regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA4', + 'regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA5', + 'regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA6', + 'regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA7', + 'regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA8', + 'regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX', + 'regSDMA1_QUEUE7_MIDCMD_DATA9', + 'regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX', + 'regSDMA1_QUEUE7_MINOR_PTR_UPDATE', + 'regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX', + 'regSDMA1_QUEUE7_PREEMPT', 'regSDMA1_QUEUE7_PREEMPT_BASE_IDX', + 'regSDMA1_QUEUE7_RB_AQL_CNTL', + 'regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE', + 'regSDMA1_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE_HI', + 'regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_CNTL', + 'regSDMA1_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_PREEMPT', + 'regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR', + 'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI', + 'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO', + 'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR_HI', + 'regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR', + 'regSDMA1_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR_HI', + 'regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX', + 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI', + 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO', + 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'regSDMA1_QUEUE7_SCHEDULE_CNTL', + 'regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX', + 'regSDMA1_QUEUE7_SKIP_CNTL', 'regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX', + 'regSDMA1_QUEUE_RESET_REQ', 'regSDMA1_QUEUE_RESET_REQ_BASE_IDX', + 'regSDMA1_QUEUE_STATUS0', 'regSDMA1_QUEUE_STATUS0_BASE_IDX', + 'regSDMA1_RB_RPTR_FETCH', 'regSDMA1_RB_RPTR_FETCH_BASE_IDX', + 'regSDMA1_RB_RPTR_FETCH_HI', 'regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX', + 'regSDMA1_RELAX_ORDERING_LUT', + 'regSDMA1_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA1_RLC_CGCG_CTRL', + 'regSDMA1_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA1_SCRATCH_RAM_ADDR', + 'regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA1_SCRATCH_RAM_DATA', + 'regSDMA1_SCRATCH_RAM_DATA_BASE_IDX', + 'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL', + 'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', + 'regSDMA1_STATUS1_REG', 'regSDMA1_STATUS1_REG_BASE_IDX', + 'regSDMA1_STATUS2_REG', 'regSDMA1_STATUS2_REG_BASE_IDX', + 'regSDMA1_STATUS3_REG', 'regSDMA1_STATUS3_REG_BASE_IDX', + 'regSDMA1_STATUS4_REG', 'regSDMA1_STATUS4_REG_BASE_IDX', + 'regSDMA1_STATUS5_REG', 'regSDMA1_STATUS5_REG_BASE_IDX', + 'regSDMA1_STATUS6_REG', 'regSDMA1_STATUS6_REG_BASE_IDX', + 'regSDMA1_STATUS_REG', 'regSDMA1_STATUS_REG_BASE_IDX', + 'regSDMA1_TILING_CONFIG', 'regSDMA1_TILING_CONFIG_BASE_IDX', + 'regSDMA1_TIMESTAMP_CNTL', 'regSDMA1_TIMESTAMP_CNTL_BASE_IDX', + 'regSDMA1_TLBI_GCR_CNTL', 'regSDMA1_TLBI_GCR_CNTL_BASE_IDX', + 'regSDMA1_UCODE1_CHECKSUM', 'regSDMA1_UCODE1_CHECKSUM_BASE_IDX', + 'regSDMA1_UCODE_ADDR', 'regSDMA1_UCODE_ADDR_BASE_IDX', + 'regSDMA1_UCODE_CHECKSUM', 'regSDMA1_UCODE_CHECKSUM_BASE_IDX', + 'regSDMA1_UCODE_DATA', 'regSDMA1_UCODE_DATA_BASE_IDX', + 'regSDMA1_UCODE_SELFLOAD_CONTROL', + 'regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA1_UTCL1_CNTL', + 'regSDMA1_UTCL1_CNTL_BASE_IDX', 'regSDMA1_UTCL1_INV0', + 'regSDMA1_UTCL1_INV0_BASE_IDX', 'regSDMA1_UTCL1_INV1', + 'regSDMA1_UTCL1_INV1_BASE_IDX', 'regSDMA1_UTCL1_INV2', + 'regSDMA1_UTCL1_INV2_BASE_IDX', 'regSDMA1_UTCL1_PAGE', + 'regSDMA1_UTCL1_PAGE_BASE_IDX', 'regSDMA1_UTCL1_RD_STATUS', + 'regSDMA1_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK0', + 'regSDMA1_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK1', + 'regSDMA1_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA1_UTCL1_TIMEOUT', + 'regSDMA1_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA1_UTCL1_WATERMK', + 'regSDMA1_UTCL1_WATERMK_BASE_IDX', 'regSDMA1_UTCL1_WR_STATUS', + 'regSDMA1_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK0', + 'regSDMA1_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK1', + 'regSDMA1_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA1_VERSION', + 'regSDMA1_VERSION_BASE_IDX', 'regSDMA1_WATCHDOG_CNTL', + 'regSDMA1_WATCHDOG_CNTL_BASE_IDX', 'regSE0_CAC_AGGR_GFXCLK_CYCLE', + 'regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE0_CAC_AGGR_LOWER', + 'regSE0_CAC_AGGR_LOWER_BASE_IDX', 'regSE0_CAC_AGGR_UPPER', + 'regSE0_CAC_AGGR_UPPER_BASE_IDX', 'regSE1_CAC_AGGR_GFXCLK_CYCLE', + 'regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE1_CAC_AGGR_LOWER', + 'regSE1_CAC_AGGR_LOWER_BASE_IDX', 'regSE1_CAC_AGGR_UPPER', + 'regSE1_CAC_AGGR_UPPER_BASE_IDX', 'regSE2_CAC_AGGR_GFXCLK_CYCLE', + 'regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE2_CAC_AGGR_LOWER', + 'regSE2_CAC_AGGR_LOWER_BASE_IDX', 'regSE2_CAC_AGGR_UPPER', + 'regSE2_CAC_AGGR_UPPER_BASE_IDX', 'regSE3_CAC_AGGR_GFXCLK_CYCLE', + 'regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE3_CAC_AGGR_LOWER', + 'regSE3_CAC_AGGR_LOWER_BASE_IDX', 'regSE3_CAC_AGGR_UPPER', + 'regSE3_CAC_AGGR_UPPER_BASE_IDX', 'regSE4_CAC_AGGR_GFXCLK_CYCLE', + 'regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE4_CAC_AGGR_LOWER', + 'regSE4_CAC_AGGR_LOWER_BASE_IDX', 'regSE4_CAC_AGGR_UPPER', + 'regSE4_CAC_AGGR_UPPER_BASE_IDX', 'regSE5_CAC_AGGR_GFXCLK_CYCLE', + 'regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE5_CAC_AGGR_LOWER', + 'regSE5_CAC_AGGR_LOWER_BASE_IDX', 'regSE5_CAC_AGGR_UPPER', + 'regSE5_CAC_AGGR_UPPER_BASE_IDX', 'regSEDC_GL1_GL2_OVERRIDES', + 'regSEDC_GL1_GL2_OVERRIDES_BASE_IDX', 'regSE_CAC_CTRL_1', + 'regSE_CAC_CTRL_1_BASE_IDX', 'regSE_CAC_CTRL_2', + 'regSE_CAC_CTRL_2_BASE_IDX', 'regSE_CAC_IND_DATA', + 'regSE_CAC_IND_DATA_BASE_IDX', 'regSE_CAC_IND_INDEX', + 'regSE_CAC_IND_INDEX_BASE_IDX', 'regSE_CAC_WEIGHT_BCI_0', + 'regSE_CAC_WEIGHT_BCI_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_0', + 'regSE_CAC_WEIGHT_CB_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_1', + 'regSE_CAC_WEIGHT_CB_10', 'regSE_CAC_WEIGHT_CB_10_BASE_IDX', + 'regSE_CAC_WEIGHT_CB_11', 'regSE_CAC_WEIGHT_CB_11_BASE_IDX', + 'regSE_CAC_WEIGHT_CB_1_BASE_IDX', 'regSE_CAC_WEIGHT_CB_2', + 'regSE_CAC_WEIGHT_CB_2_BASE_IDX', 'regSE_CAC_WEIGHT_CB_3', + 'regSE_CAC_WEIGHT_CB_3_BASE_IDX', 'regSE_CAC_WEIGHT_CB_4', + 'regSE_CAC_WEIGHT_CB_4_BASE_IDX', 'regSE_CAC_WEIGHT_CB_5', + 'regSE_CAC_WEIGHT_CB_5_BASE_IDX', 'regSE_CAC_WEIGHT_CB_6', + 'regSE_CAC_WEIGHT_CB_6_BASE_IDX', 'regSE_CAC_WEIGHT_CB_7', + 'regSE_CAC_WEIGHT_CB_7_BASE_IDX', 'regSE_CAC_WEIGHT_CB_8', + 'regSE_CAC_WEIGHT_CB_8_BASE_IDX', 'regSE_CAC_WEIGHT_CB_9', + 'regSE_CAC_WEIGHT_CB_9_BASE_IDX', 'regSE_CAC_WEIGHT_CU_0', + 'regSE_CAC_WEIGHT_CU_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_0', + 'regSE_CAC_WEIGHT_DB_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_1', + 'regSE_CAC_WEIGHT_DB_1_BASE_IDX', 'regSE_CAC_WEIGHT_DB_2', + 'regSE_CAC_WEIGHT_DB_2_BASE_IDX', 'regSE_CAC_WEIGHT_DB_3', + 'regSE_CAC_WEIGHT_DB_3_BASE_IDX', 'regSE_CAC_WEIGHT_DB_4', + 'regSE_CAC_WEIGHT_DB_4_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_0', + 'regSE_CAC_WEIGHT_GL1C_0_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_1', + 'regSE_CAC_WEIGHT_GL1C_1_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_2', + 'regSE_CAC_WEIGHT_GL1C_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_0', + 'regSE_CAC_WEIGHT_LDS_0_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_1', + 'regSE_CAC_WEIGHT_LDS_1_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_2', + 'regSE_CAC_WEIGHT_LDS_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_3', + 'regSE_CAC_WEIGHT_LDS_3_BASE_IDX', 'regSE_CAC_WEIGHT_PA_0', + 'regSE_CAC_WEIGHT_PA_0_BASE_IDX', 'regSE_CAC_WEIGHT_PA_1', + 'regSE_CAC_WEIGHT_PA_1_BASE_IDX', 'regSE_CAC_WEIGHT_PA_2', + 'regSE_CAC_WEIGHT_PA_2_BASE_IDX', 'regSE_CAC_WEIGHT_PA_3', + 'regSE_CAC_WEIGHT_PA_3_BASE_IDX', 'regSE_CAC_WEIGHT_PC_0', + 'regSE_CAC_WEIGHT_PC_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_0', + 'regSE_CAC_WEIGHT_RMI_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_1', + 'regSE_CAC_WEIGHT_RMI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_0', + 'regSE_CAC_WEIGHT_SC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SC_1', + 'regSE_CAC_WEIGHT_SC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_2', + 'regSE_CAC_WEIGHT_SC_2_BASE_IDX', 'regSE_CAC_WEIGHT_SC_3', + 'regSE_CAC_WEIGHT_SC_3_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_0', + 'regSE_CAC_WEIGHT_SPI_0_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_1', + 'regSE_CAC_WEIGHT_SPI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_2', + 'regSE_CAC_WEIGHT_SPI_2_BASE_IDX', 'regSE_CAC_WEIGHT_SP_0', + 'regSE_CAC_WEIGHT_SP_0_BASE_IDX', 'regSE_CAC_WEIGHT_SP_1', + 'regSE_CAC_WEIGHT_SP_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_0', + 'regSE_CAC_WEIGHT_SQC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_1', + 'regSE_CAC_WEIGHT_SQC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_0', + 'regSE_CAC_WEIGHT_SQ_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_1', + 'regSE_CAC_WEIGHT_SQ_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_2', + 'regSE_CAC_WEIGHT_SQ_2_BASE_IDX', 'regSE_CAC_WEIGHT_SXRB_0', + 'regSE_CAC_WEIGHT_SXRB_0_BASE_IDX', 'regSE_CAC_WEIGHT_SX_0', + 'regSE_CAC_WEIGHT_SX_0_BASE_IDX', 'regSE_CAC_WEIGHT_TA_0', + 'regSE_CAC_WEIGHT_TA_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_0', + 'regSE_CAC_WEIGHT_TCP_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_1', + 'regSE_CAC_WEIGHT_TCP_1_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_2', + 'regSE_CAC_WEIGHT_TCP_2_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_3', + 'regSE_CAC_WEIGHT_TCP_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_0', + 'regSE_CAC_WEIGHT_TD_0_BASE_IDX', 'regSE_CAC_WEIGHT_TD_1', + 'regSE_CAC_WEIGHT_TD_1_BASE_IDX', 'regSE_CAC_WEIGHT_TD_2', + 'regSE_CAC_WEIGHT_TD_2_BASE_IDX', 'regSE_CAC_WEIGHT_TD_3', + 'regSE_CAC_WEIGHT_TD_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_4', + 'regSE_CAC_WEIGHT_TD_4_BASE_IDX', 'regSE_CAC_WEIGHT_TD_5', + 'regSE_CAC_WEIGHT_TD_5_BASE_IDX', 'regSE_CAC_WEIGHT_UTCL1_0', + 'regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX', + 'regSE_CAC_WINDOW_AGGR_VALUE', + 'regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX', + 'regSE_CAC_WINDOW_GFXCLK_CYCLE', + 'regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX', 'regSH_MEM_BASES', + 'regSH_MEM_BASES_BASE_IDX', 'regSH_MEM_CONFIG', + 'regSH_MEM_CONFIG_BASE_IDX', 'regSH_RESERVED_REG0', + 'regSH_RESERVED_REG0_BASE_IDX', 'regSH_RESERVED_REG1', + 'regSH_RESERVED_REG1_BASE_IDX', 'regSMU_RLC_RESPONSE', + 'regSMU_RLC_RESPONSE_BASE_IDX', 'regSPI_ARB_CNTL_0', + 'regSPI_ARB_CNTL_0_BASE_IDX', 'regSPI_ARB_CYCLES_0', + 'regSPI_ARB_CYCLES_0_BASE_IDX', 'regSPI_ARB_CYCLES_1', + 'regSPI_ARB_CYCLES_1_BASE_IDX', 'regSPI_ARB_PRIORITY', + 'regSPI_ARB_PRIORITY_BASE_IDX', 'regSPI_ATTRIBUTE_RING_BASE', + 'regSPI_ATTRIBUTE_RING_BASE_BASE_IDX', + 'regSPI_ATTRIBUTE_RING_SIZE', + 'regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX', 'regSPI_BARYC_CNTL', + 'regSPI_BARYC_CNTL_BASE_IDX', 'regSPI_COMPUTE_QUEUE_RESET', + 'regSPI_COMPUTE_QUEUE_RESET_BASE_IDX', + 'regSPI_COMPUTE_WF_CTX_SAVE', + 'regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX', + 'regSPI_COMPUTE_WF_CTX_SAVE_STATUS', + 'regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX', + 'regSPI_CONFIG_CNTL', 'regSPI_CONFIG_CNTL_1', + 'regSPI_CONFIG_CNTL_1_BASE_IDX', 'regSPI_CONFIG_CNTL_2', + 'regSPI_CONFIG_CNTL_2_BASE_IDX', 'regSPI_CONFIG_CNTL_BASE_IDX', + 'regSPI_CONFIG_PS_CU_EN', 'regSPI_CONFIG_PS_CU_EN_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_0', + 'regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_1', + 'regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_2', + 'regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_3', + 'regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_STATUS', + 'regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'regSPI_DSM_CNTL', + 'regSPI_DSM_CNTL2', 'regSPI_DSM_CNTL2_BASE_IDX', + 'regSPI_DSM_CNTL_BASE_IDX', 'regSPI_EDC_CNT', + 'regSPI_EDC_CNT_BASE_IDX', 'regSPI_EXP_THROTTLE_CTRL', + 'regSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'regSPI_FEATURE_CTRL', + 'regSPI_FEATURE_CTRL_BASE_IDX', 'regSPI_GDBG_PER_VMID_CNTL', + 'regSPI_GDBG_PER_VMID_CNTL_BASE_IDX', 'regSPI_GDBG_TRAP_CONFIG', + 'regSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'regSPI_GDBG_WAVE_CNTL', + 'regSPI_GDBG_WAVE_CNTL3', 'regSPI_GDBG_WAVE_CNTL3_BASE_IDX', + 'regSPI_GDBG_WAVE_CNTL_BASE_IDX', 'regSPI_GDS_CREDITS', + 'regSPI_GDS_CREDITS_BASE_IDX', 'regSPI_GFX_CNTL', + 'regSPI_GFX_CNTL_BASE_IDX', 'regSPI_GFX_SCRATCH_BASE_HI', + 'regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX', + 'regSPI_GFX_SCRATCH_BASE_LO', + 'regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL1', + 'regSPI_GS_THROTTLE_CNTL1_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL2', + 'regSPI_GS_THROTTLE_CNTL2_BASE_IDX', 'regSPI_INTERP_CONTROL_0', + 'regSPI_INTERP_CONTROL_0_BASE_IDX', 'regSPI_LB_CTR_CTRL', + 'regSPI_LB_CTR_CTRL_BASE_IDX', 'regSPI_LB_DATA_REG', + 'regSPI_LB_DATA_REG_BASE_IDX', 'regSPI_LB_DATA_WAVES', + 'regSPI_LB_DATA_WAVES_BASE_IDX', 'regSPI_LB_WGP_MASK', + 'regSPI_LB_WGP_MASK_BASE_IDX', 'regSPI_P0_TRAP_SCREEN_GPR_MIN', + 'regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSBA_HI', + 'regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSBA_LO', + 'regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSMA_HI', + 'regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSMA_LO', + 'regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_GPR_MIN', + 'regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSBA_HI', + 'regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSBA_LO', + 'regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSMA_HI', + 'regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSMA_LO', + 'regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX', + 'regSPI_PERFCOUNTER0_HI', 'regSPI_PERFCOUNTER0_HI_BASE_IDX', + 'regSPI_PERFCOUNTER0_LO', 'regSPI_PERFCOUNTER0_LO_BASE_IDX', + 'regSPI_PERFCOUNTER0_SELECT', 'regSPI_PERFCOUNTER0_SELECT1', + 'regSPI_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER1_HI', + 'regSPI_PERFCOUNTER1_HI_BASE_IDX', 'regSPI_PERFCOUNTER1_LO', + 'regSPI_PERFCOUNTER1_LO_BASE_IDX', 'regSPI_PERFCOUNTER1_SELECT', + 'regSPI_PERFCOUNTER1_SELECT1', + 'regSPI_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER2_HI', + 'regSPI_PERFCOUNTER2_HI_BASE_IDX', 'regSPI_PERFCOUNTER2_LO', + 'regSPI_PERFCOUNTER2_LO_BASE_IDX', 'regSPI_PERFCOUNTER2_SELECT', + 'regSPI_PERFCOUNTER2_SELECT1', + 'regSPI_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER3_HI', + 'regSPI_PERFCOUNTER3_HI_BASE_IDX', 'regSPI_PERFCOUNTER3_LO', + 'regSPI_PERFCOUNTER3_LO_BASE_IDX', 'regSPI_PERFCOUNTER3_SELECT', + 'regSPI_PERFCOUNTER3_SELECT1', + 'regSPI_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER4_HI', + 'regSPI_PERFCOUNTER4_HI_BASE_IDX', 'regSPI_PERFCOUNTER4_LO', + 'regSPI_PERFCOUNTER4_LO_BASE_IDX', 'regSPI_PERFCOUNTER4_SELECT', + 'regSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER5_HI', + 'regSPI_PERFCOUNTER5_HI_BASE_IDX', 'regSPI_PERFCOUNTER5_LO', + 'regSPI_PERFCOUNTER5_LO_BASE_IDX', 'regSPI_PERFCOUNTER5_SELECT', + 'regSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER_BINS', + 'regSPI_PERFCOUNTER_BINS_BASE_IDX', + 'regSPI_PG_ENABLE_STATIC_WGP_MASK', + 'regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'regSPI_PQEV_CTRL', + 'regSPI_PQEV_CTRL_BASE_IDX', 'regSPI_PS_INPUT_ADDR', + 'regSPI_PS_INPUT_ADDR_BASE_IDX', 'regSPI_PS_INPUT_CNTL_0', + 'regSPI_PS_INPUT_CNTL_0_BASE_IDX', 'regSPI_PS_INPUT_CNTL_1', + 'regSPI_PS_INPUT_CNTL_10', 'regSPI_PS_INPUT_CNTL_10_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_11', 'regSPI_PS_INPUT_CNTL_11_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_12', 'regSPI_PS_INPUT_CNTL_12_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_13', 'regSPI_PS_INPUT_CNTL_13_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_14', 'regSPI_PS_INPUT_CNTL_14_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_15', 'regSPI_PS_INPUT_CNTL_15_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_16', 'regSPI_PS_INPUT_CNTL_16_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_17', 'regSPI_PS_INPUT_CNTL_17_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_18', 'regSPI_PS_INPUT_CNTL_18_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_19', 'regSPI_PS_INPUT_CNTL_19_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_1_BASE_IDX', 'regSPI_PS_INPUT_CNTL_2', + 'regSPI_PS_INPUT_CNTL_20', 'regSPI_PS_INPUT_CNTL_20_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_21', 'regSPI_PS_INPUT_CNTL_21_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_22', 'regSPI_PS_INPUT_CNTL_22_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_23', 'regSPI_PS_INPUT_CNTL_23_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_24', 'regSPI_PS_INPUT_CNTL_24_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_25', 'regSPI_PS_INPUT_CNTL_25_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_26', 'regSPI_PS_INPUT_CNTL_26_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_27', 'regSPI_PS_INPUT_CNTL_27_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_28', 'regSPI_PS_INPUT_CNTL_28_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_29', 'regSPI_PS_INPUT_CNTL_29_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_2_BASE_IDX', 'regSPI_PS_INPUT_CNTL_3', + 'regSPI_PS_INPUT_CNTL_30', 'regSPI_PS_INPUT_CNTL_30_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_31', 'regSPI_PS_INPUT_CNTL_31_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_3_BASE_IDX', 'regSPI_PS_INPUT_CNTL_4', + 'regSPI_PS_INPUT_CNTL_4_BASE_IDX', 'regSPI_PS_INPUT_CNTL_5', + 'regSPI_PS_INPUT_CNTL_5_BASE_IDX', 'regSPI_PS_INPUT_CNTL_6', + 'regSPI_PS_INPUT_CNTL_6_BASE_IDX', 'regSPI_PS_INPUT_CNTL_7', + 'regSPI_PS_INPUT_CNTL_7_BASE_IDX', 'regSPI_PS_INPUT_CNTL_8', + 'regSPI_PS_INPUT_CNTL_8_BASE_IDX', 'regSPI_PS_INPUT_CNTL_9', + 'regSPI_PS_INPUT_CNTL_9_BASE_IDX', 'regSPI_PS_INPUT_ENA', + 'regSPI_PS_INPUT_ENA_BASE_IDX', 'regSPI_PS_IN_CONTROL', + 'regSPI_PS_IN_CONTROL_BASE_IDX', 'regSPI_PS_MAX_WAVE_ID', + 'regSPI_PS_MAX_WAVE_ID_BASE_IDX', 'regSPI_RESOURCE_RESERVE_CU_0', + 'regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_1', 'regSPI_RESOURCE_RESERVE_CU_10', + 'regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_11', + 'regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_12', + 'regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_13', + 'regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_14', + 'regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_15', + 'regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_2', + 'regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_3', + 'regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_4', + 'regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_5', + 'regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_6', + 'regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_7', + 'regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_8', + 'regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_9', + 'regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_0', + 'regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_1', + 'regSPI_RESOURCE_RESERVE_EN_CU_10', + 'regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_11', + 'regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_12', + 'regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_13', + 'regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_14', + 'regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_15', + 'regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_2', + 'regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_3', + 'regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_4', + 'regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_5', + 'regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_6', + 'regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_7', + 'regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_8', + 'regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_9', + 'regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX', + 'regSPI_SHADER_COL_FORMAT', 'regSPI_SHADER_COL_FORMAT_BASE_IDX', + 'regSPI_SHADER_GS_MESHLET_DIM', + 'regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX', + 'regSPI_SHADER_GS_MESHLET_EXP_ALLOC', + 'regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX', + 'regSPI_SHADER_IDX_FORMAT', 'regSPI_SHADER_IDX_FORMAT_BASE_IDX', + 'regSPI_SHADER_PGM_CHKSUM_GS', + 'regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX', + 'regSPI_SHADER_PGM_CHKSUM_HS', + 'regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX', + 'regSPI_SHADER_PGM_CHKSUM_PS', + 'regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES', + 'regSPI_SHADER_PGM_HI_ES_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES_GS', + 'regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_GS', + 'regSPI_SHADER_PGM_HI_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_HS', + 'regSPI_SHADER_PGM_HI_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS', + 'regSPI_SHADER_PGM_HI_LS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS_HS', + 'regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_PS', + 'regSPI_SHADER_PGM_HI_PS_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES', + 'regSPI_SHADER_PGM_LO_ES_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES_GS', + 'regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_GS', + 'regSPI_SHADER_PGM_LO_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_HS', + 'regSPI_SHADER_PGM_LO_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS', + 'regSPI_SHADER_PGM_LO_LS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS_HS', + 'regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_PS', + 'regSPI_SHADER_PGM_LO_PS_BASE_IDX', 'regSPI_SHADER_PGM_RSRC1_GS', + 'regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC1_HS', + 'regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC1_PS', + 'regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_GS', + 'regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_HS', + 'regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_PS', + 'regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC3_GS', + 'regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC3_HS', + 'regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC3_PS', + 'regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC4_GS', + 'regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC4_HS', + 'regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC4_PS', + 'regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX', 'regSPI_SHADER_POS_FORMAT', + 'regSPI_SHADER_POS_FORMAT_BASE_IDX', + 'regSPI_SHADER_REQ_CTRL_ESGS', + 'regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX', + 'regSPI_SHADER_REQ_CTRL_LSHS', + 'regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX', + 'regSPI_SHADER_REQ_CTRL_PS', 'regSPI_SHADER_REQ_CTRL_PS_BASE_IDX', + 'regSPI_SHADER_RSRC_LIMIT_CTRL', + 'regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_ESGS_0', + 'regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_ESGS_1', + 'regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_ESGS_2', + 'regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_ESGS_3', + 'regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_LSHS_0', + 'regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_LSHS_1', + 'regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_LSHS_2', + 'regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_LSHS_3', + 'regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_PS_0', + 'regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_PS_1', + 'regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_PS_2', + 'regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX', + 'regSPI_SHADER_USER_ACCUM_PS_3', + 'regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_HI_GS', + 'regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_HI_HS', + 'regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_LO_GS', + 'regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_LO_HS', + 'regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_0', + 'regSPI_SHADER_USER_DATA_GS_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_1', 'regSPI_SHADER_USER_DATA_GS_10', + 'regSPI_SHADER_USER_DATA_GS_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_11', + 'regSPI_SHADER_USER_DATA_GS_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_12', + 'regSPI_SHADER_USER_DATA_GS_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_13', + 'regSPI_SHADER_USER_DATA_GS_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_14', + 'regSPI_SHADER_USER_DATA_GS_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_15', + 'regSPI_SHADER_USER_DATA_GS_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_16', + 'regSPI_SHADER_USER_DATA_GS_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_17', + 'regSPI_SHADER_USER_DATA_GS_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_18', + 'regSPI_SHADER_USER_DATA_GS_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_19', + 'regSPI_SHADER_USER_DATA_GS_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_2', 'regSPI_SHADER_USER_DATA_GS_20', + 'regSPI_SHADER_USER_DATA_GS_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_21', + 'regSPI_SHADER_USER_DATA_GS_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_22', + 'regSPI_SHADER_USER_DATA_GS_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_23', + 'regSPI_SHADER_USER_DATA_GS_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_24', + 'regSPI_SHADER_USER_DATA_GS_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_25', + 'regSPI_SHADER_USER_DATA_GS_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_26', + 'regSPI_SHADER_USER_DATA_GS_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_27', + 'regSPI_SHADER_USER_DATA_GS_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_28', + 'regSPI_SHADER_USER_DATA_GS_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_29', + 'regSPI_SHADER_USER_DATA_GS_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_3', 'regSPI_SHADER_USER_DATA_GS_30', + 'regSPI_SHADER_USER_DATA_GS_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_31', + 'regSPI_SHADER_USER_DATA_GS_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_4', + 'regSPI_SHADER_USER_DATA_GS_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_5', + 'regSPI_SHADER_USER_DATA_GS_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_6', + 'regSPI_SHADER_USER_DATA_GS_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_7', + 'regSPI_SHADER_USER_DATA_GS_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_8', + 'regSPI_SHADER_USER_DATA_GS_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_GS_9', + 'regSPI_SHADER_USER_DATA_GS_9_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_0', + 'regSPI_SHADER_USER_DATA_HS_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_1', 'regSPI_SHADER_USER_DATA_HS_10', + 'regSPI_SHADER_USER_DATA_HS_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_11', + 'regSPI_SHADER_USER_DATA_HS_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_12', + 'regSPI_SHADER_USER_DATA_HS_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_13', + 'regSPI_SHADER_USER_DATA_HS_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_14', + 'regSPI_SHADER_USER_DATA_HS_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_15', + 'regSPI_SHADER_USER_DATA_HS_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_16', + 'regSPI_SHADER_USER_DATA_HS_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_17', + 'regSPI_SHADER_USER_DATA_HS_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_18', + 'regSPI_SHADER_USER_DATA_HS_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_19', + 'regSPI_SHADER_USER_DATA_HS_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_2', 'regSPI_SHADER_USER_DATA_HS_20', + 'regSPI_SHADER_USER_DATA_HS_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_21', + 'regSPI_SHADER_USER_DATA_HS_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_22', + 'regSPI_SHADER_USER_DATA_HS_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_23', + 'regSPI_SHADER_USER_DATA_HS_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_24', + 'regSPI_SHADER_USER_DATA_HS_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_25', + 'regSPI_SHADER_USER_DATA_HS_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_26', + 'regSPI_SHADER_USER_DATA_HS_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_27', + 'regSPI_SHADER_USER_DATA_HS_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_28', + 'regSPI_SHADER_USER_DATA_HS_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_29', + 'regSPI_SHADER_USER_DATA_HS_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_3', 'regSPI_SHADER_USER_DATA_HS_30', + 'regSPI_SHADER_USER_DATA_HS_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_31', + 'regSPI_SHADER_USER_DATA_HS_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_4', + 'regSPI_SHADER_USER_DATA_HS_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_5', + 'regSPI_SHADER_USER_DATA_HS_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_6', + 'regSPI_SHADER_USER_DATA_HS_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_7', + 'regSPI_SHADER_USER_DATA_HS_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_8', + 'regSPI_SHADER_USER_DATA_HS_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_HS_9', + 'regSPI_SHADER_USER_DATA_HS_9_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_0', + 'regSPI_SHADER_USER_DATA_PS_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_1', 'regSPI_SHADER_USER_DATA_PS_10', + 'regSPI_SHADER_USER_DATA_PS_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_11', + 'regSPI_SHADER_USER_DATA_PS_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_12', + 'regSPI_SHADER_USER_DATA_PS_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_13', + 'regSPI_SHADER_USER_DATA_PS_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_14', + 'regSPI_SHADER_USER_DATA_PS_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_15', + 'regSPI_SHADER_USER_DATA_PS_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_16', + 'regSPI_SHADER_USER_DATA_PS_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_17', + 'regSPI_SHADER_USER_DATA_PS_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_18', + 'regSPI_SHADER_USER_DATA_PS_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_19', + 'regSPI_SHADER_USER_DATA_PS_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_2', 'regSPI_SHADER_USER_DATA_PS_20', + 'regSPI_SHADER_USER_DATA_PS_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_21', + 'regSPI_SHADER_USER_DATA_PS_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_22', + 'regSPI_SHADER_USER_DATA_PS_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_23', + 'regSPI_SHADER_USER_DATA_PS_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_24', + 'regSPI_SHADER_USER_DATA_PS_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_25', + 'regSPI_SHADER_USER_DATA_PS_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_26', + 'regSPI_SHADER_USER_DATA_PS_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_27', + 'regSPI_SHADER_USER_DATA_PS_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_28', + 'regSPI_SHADER_USER_DATA_PS_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_29', + 'regSPI_SHADER_USER_DATA_PS_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_3', 'regSPI_SHADER_USER_DATA_PS_30', + 'regSPI_SHADER_USER_DATA_PS_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_31', + 'regSPI_SHADER_USER_DATA_PS_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_4', + 'regSPI_SHADER_USER_DATA_PS_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_5', + 'regSPI_SHADER_USER_DATA_PS_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_6', + 'regSPI_SHADER_USER_DATA_PS_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_7', + 'regSPI_SHADER_USER_DATA_PS_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_8', + 'regSPI_SHADER_USER_DATA_PS_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_9', + 'regSPI_SHADER_USER_DATA_PS_9_BASE_IDX', 'regSPI_SHADER_Z_FORMAT', + 'regSPI_SHADER_Z_FORMAT_BASE_IDX', + 'regSPI_SX_EXPORT_BUFFER_SIZES', + 'regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX', + 'regSPI_SX_SCOREBOARD_BUFFER_SIZES', + 'regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX', + 'regSPI_TMPRING_SIZE', 'regSPI_TMPRING_SIZE_BASE_IDX', + 'regSPI_USER_ACCUM_VMID_CNTL', + 'regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'regSPI_VS_OUT_CONFIG', + 'regSPI_VS_OUT_CONFIG_BASE_IDX', 'regSPI_WAVE_LIMIT_CNTL', + 'regSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'regSPI_WCL_PIPE_PERCENT_CS0', + 'regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS1', + 'regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS2', + 'regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS3', + 'regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS4', + 'regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS5', + 'regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS6', + 'regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS7', + 'regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_GFX', + 'regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_HP3D', + 'regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX', + 'regSPI_WF_LIFETIME_CNTL', 'regSPI_WF_LIFETIME_CNTL_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_0', + 'regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_1', + 'regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_2', + 'regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_3', + 'regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_4', + 'regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_5', + 'regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_0', + 'regSPI_WF_LIFETIME_STATUS_0_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_11', + 'regSPI_WF_LIFETIME_STATUS_11_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_13', + 'regSPI_WF_LIFETIME_STATUS_13_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_14', + 'regSPI_WF_LIFETIME_STATUS_14_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_15', + 'regSPI_WF_LIFETIME_STATUS_15_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_16', + 'regSPI_WF_LIFETIME_STATUS_16_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_17', + 'regSPI_WF_LIFETIME_STATUS_17_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_18', + 'regSPI_WF_LIFETIME_STATUS_18_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_19', + 'regSPI_WF_LIFETIME_STATUS_19_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_2', 'regSPI_WF_LIFETIME_STATUS_20', + 'regSPI_WF_LIFETIME_STATUS_20_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_21', + 'regSPI_WF_LIFETIME_STATUS_21_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_2_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_4', + 'regSPI_WF_LIFETIME_STATUS_4_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_6', + 'regSPI_WF_LIFETIME_STATUS_6_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_7', + 'regSPI_WF_LIFETIME_STATUS_7_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_9', + 'regSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'regSP_CONFIG', + 'regSP_CONFIG_BASE_IDX', 'regSQC_CACHES', + 'regSQC_CACHES_BASE_IDX', 'regSQC_CONFIG', + 'regSQC_CONFIG_BASE_IDX', 'regSQG_CONFIG', + 'regSQG_CONFIG_BASE_IDX', 'regSQG_GL1H_STATUS', + 'regSQG_GL1H_STATUS_BASE_IDX', 'regSQG_PERFCOUNTER0_HI', + 'regSQG_PERFCOUNTER0_HI_BASE_IDX', 'regSQG_PERFCOUNTER0_LO', + 'regSQG_PERFCOUNTER0_LO_BASE_IDX', 'regSQG_PERFCOUNTER0_SELECT', + 'regSQG_PERFCOUNTER0_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER1_HI', + 'regSQG_PERFCOUNTER1_HI_BASE_IDX', 'regSQG_PERFCOUNTER1_LO', + 'regSQG_PERFCOUNTER1_LO_BASE_IDX', 'regSQG_PERFCOUNTER1_SELECT', + 'regSQG_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER2_HI', + 'regSQG_PERFCOUNTER2_HI_BASE_IDX', 'regSQG_PERFCOUNTER2_LO', + 'regSQG_PERFCOUNTER2_LO_BASE_IDX', 'regSQG_PERFCOUNTER2_SELECT', + 'regSQG_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER3_HI', + 'regSQG_PERFCOUNTER3_HI_BASE_IDX', 'regSQG_PERFCOUNTER3_LO', + 'regSQG_PERFCOUNTER3_LO_BASE_IDX', 'regSQG_PERFCOUNTER3_SELECT', + 'regSQG_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER4_HI', + 'regSQG_PERFCOUNTER4_HI_BASE_IDX', 'regSQG_PERFCOUNTER4_LO', + 'regSQG_PERFCOUNTER4_LO_BASE_IDX', 'regSQG_PERFCOUNTER4_SELECT', + 'regSQG_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER5_HI', + 'regSQG_PERFCOUNTER5_HI_BASE_IDX', 'regSQG_PERFCOUNTER5_LO', + 'regSQG_PERFCOUNTER5_LO_BASE_IDX', 'regSQG_PERFCOUNTER5_SELECT', + 'regSQG_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER6_HI', + 'regSQG_PERFCOUNTER6_HI_BASE_IDX', 'regSQG_PERFCOUNTER6_LO', + 'regSQG_PERFCOUNTER6_LO_BASE_IDX', 'regSQG_PERFCOUNTER6_SELECT', + 'regSQG_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER7_HI', + 'regSQG_PERFCOUNTER7_HI_BASE_IDX', 'regSQG_PERFCOUNTER7_LO', + 'regSQG_PERFCOUNTER7_LO_BASE_IDX', 'regSQG_PERFCOUNTER7_SELECT', + 'regSQG_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER_CTRL', + 'regSQG_PERFCOUNTER_CTRL2', 'regSQG_PERFCOUNTER_CTRL2_BASE_IDX', + 'regSQG_PERFCOUNTER_CTRL_BASE_IDX', 'regSQG_PERF_SAMPLE_FINISH', + 'regSQG_PERF_SAMPLE_FINISH_BASE_IDX', 'regSQG_STATUS', + 'regSQG_STATUS_BASE_IDX', 'regSQ_ALU_CLK_CTRL', + 'regSQ_ALU_CLK_CTRL_BASE_IDX', 'regSQ_ARB_CONFIG', + 'regSQ_ARB_CONFIG_BASE_IDX', 'regSQ_CMD', 'regSQ_CMD_BASE_IDX', + 'regSQ_CONFIG', 'regSQ_CONFIG_BASE_IDX', 'regSQ_DEBUG', + 'regSQ_DEBUG_BASE_IDX', 'regSQ_DEBUG_HOST_TRAP_STATUS', + 'regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX', 'regSQ_DEBUG_STS_GLOBAL', + 'regSQ_DEBUG_STS_GLOBAL2', 'regSQ_DEBUG_STS_GLOBAL2_BASE_IDX', + 'regSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'regSQ_DSM_CNTL', + 'regSQ_DSM_CNTL2', 'regSQ_DSM_CNTL2_BASE_IDX', + 'regSQ_DSM_CNTL_BASE_IDX', 'regSQ_FIFO_SIZES', + 'regSQ_FIFO_SIZES_BASE_IDX', 'regSQ_IND_DATA', + 'regSQ_IND_DATA_BASE_IDX', 'regSQ_IND_INDEX', + 'regSQ_IND_INDEX_BASE_IDX', 'regSQ_INTERRUPT_AUTO_MASK', + 'regSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'regSQ_INTERRUPT_MSG_CTRL', + 'regSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'regSQ_LDS_CLK_CTRL', + 'regSQ_LDS_CLK_CTRL_BASE_IDX', 'regSQ_PERFCOUNTER0_LO', + 'regSQ_PERFCOUNTER0_LO_BASE_IDX', 'regSQ_PERFCOUNTER0_SELECT', + 'regSQ_PERFCOUNTER0_SELECT_BASE_IDX', + 'regSQ_PERFCOUNTER10_SELECT', + 'regSQ_PERFCOUNTER10_SELECT_BASE_IDX', + 'regSQ_PERFCOUNTER11_SELECT', + 'regSQ_PERFCOUNTER11_SELECT_BASE_IDX', + 'regSQ_PERFCOUNTER12_SELECT', + 'regSQ_PERFCOUNTER12_SELECT_BASE_IDX', + 'regSQ_PERFCOUNTER13_SELECT', + 'regSQ_PERFCOUNTER13_SELECT_BASE_IDX', + 'regSQ_PERFCOUNTER14_SELECT', + 'regSQ_PERFCOUNTER14_SELECT_BASE_IDX', + 'regSQ_PERFCOUNTER15_SELECT', + 'regSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER1_LO', + 'regSQ_PERFCOUNTER1_LO_BASE_IDX', 'regSQ_PERFCOUNTER1_SELECT', + 'regSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER2_LO', + 'regSQ_PERFCOUNTER2_LO_BASE_IDX', 'regSQ_PERFCOUNTER2_SELECT', + 'regSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER3_LO', + 'regSQ_PERFCOUNTER3_LO_BASE_IDX', 'regSQ_PERFCOUNTER3_SELECT', + 'regSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER4_LO', + 'regSQ_PERFCOUNTER4_LO_BASE_IDX', 'regSQ_PERFCOUNTER4_SELECT', + 'regSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER5_LO', + 'regSQ_PERFCOUNTER5_LO_BASE_IDX', 'regSQ_PERFCOUNTER5_SELECT', + 'regSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER6_LO', + 'regSQ_PERFCOUNTER6_LO_BASE_IDX', 'regSQ_PERFCOUNTER6_SELECT', + 'regSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER7_LO', + 'regSQ_PERFCOUNTER7_LO_BASE_IDX', 'regSQ_PERFCOUNTER7_SELECT', + 'regSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER8_SELECT', + 'regSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER9_SELECT', + 'regSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER_CTRL', + 'regSQ_PERFCOUNTER_CTRL2', 'regSQ_PERFCOUNTER_CTRL2_BASE_IDX', + 'regSQ_PERFCOUNTER_CTRL_BASE_IDX', 'regSQ_PERF_SNAPSHOT_CTRL', + 'regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX', 'regSQ_RANDOM_WAVE_PRI', + 'regSQ_RANDOM_WAVE_PRI_BASE_IDX', 'regSQ_RUNTIME_CONFIG', + 'regSQ_RUNTIME_CONFIG_BASE_IDX', 'regSQ_SHADER_TBA_HI', + 'regSQ_SHADER_TBA_HI_BASE_IDX', 'regSQ_SHADER_TBA_LO', + 'regSQ_SHADER_TBA_LO_BASE_IDX', 'regSQ_SHADER_TMA_HI', + 'regSQ_SHADER_TMA_HI_BASE_IDX', 'regSQ_SHADER_TMA_LO', + 'regSQ_SHADER_TMA_LO_BASE_IDX', 'regSQ_TEX_CLK_CTRL', + 'regSQ_TEX_CLK_CTRL_BASE_IDX', 'regSQ_THREAD_TRACE_BUF0_BASE', + 'regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX', + 'regSQ_THREAD_TRACE_BUF0_SIZE', + 'regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX', + 'regSQ_THREAD_TRACE_BUF1_BASE', + 'regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX', + 'regSQ_THREAD_TRACE_BUF1_SIZE', + 'regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX', + 'regSQ_THREAD_TRACE_CTRL', 'regSQ_THREAD_TRACE_CTRL_BASE_IDX', + 'regSQ_THREAD_TRACE_DROPPED_CNTR', + 'regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX', + 'regSQ_THREAD_TRACE_GFX_DRAW_CNTR', + 'regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX', + 'regSQ_THREAD_TRACE_GFX_MARKER_CNTR', + 'regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX', + 'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR', + 'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX', + 'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR', + 'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX', + 'regSQ_THREAD_TRACE_MASK', 'regSQ_THREAD_TRACE_MASK_BASE_IDX', + 'regSQ_THREAD_TRACE_STATUS', 'regSQ_THREAD_TRACE_STATUS2', + 'regSQ_THREAD_TRACE_STATUS2_BASE_IDX', + 'regSQ_THREAD_TRACE_STATUS_BASE_IDX', + 'regSQ_THREAD_TRACE_TOKEN_MASK', + 'regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_0', + 'regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_1', + 'regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_2', + 'regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_3', + 'regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_4', + 'regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_5', + 'regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_6', + 'regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_7', + 'regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX', + 'regSQ_THREAD_TRACE_WPTR', 'regSQ_THREAD_TRACE_WPTR_BASE_IDX', + 'regSQ_WATCH0_ADDR_H', 'regSQ_WATCH0_ADDR_H_BASE_IDX', + 'regSQ_WATCH0_ADDR_L', 'regSQ_WATCH0_ADDR_L_BASE_IDX', + 'regSQ_WATCH0_CNTL', 'regSQ_WATCH0_CNTL_BASE_IDX', + 'regSQ_WATCH1_ADDR_H', 'regSQ_WATCH1_ADDR_H_BASE_IDX', + 'regSQ_WATCH1_ADDR_L', 'regSQ_WATCH1_ADDR_L_BASE_IDX', + 'regSQ_WATCH1_CNTL', 'regSQ_WATCH1_CNTL_BASE_IDX', + 'regSQ_WATCH2_ADDR_H', 'regSQ_WATCH2_ADDR_H_BASE_IDX', + 'regSQ_WATCH2_ADDR_L', 'regSQ_WATCH2_ADDR_L_BASE_IDX', + 'regSQ_WATCH2_CNTL', 'regSQ_WATCH2_CNTL_BASE_IDX', + 'regSQ_WATCH3_ADDR_H', 'regSQ_WATCH3_ADDR_H_BASE_IDX', + 'regSQ_WATCH3_ADDR_L', 'regSQ_WATCH3_ADDR_L_BASE_IDX', + 'regSQ_WATCH3_CNTL', 'regSQ_WATCH3_CNTL_BASE_IDX', + 'regSX_BLEND_OPT_CONTROL', 'regSX_BLEND_OPT_CONTROL_BASE_IDX', + 'regSX_BLEND_OPT_EPSILON', 'regSX_BLEND_OPT_EPSILON_BASE_IDX', + 'regSX_DEBUG_1', 'regSX_DEBUG_1_BASE_IDX', 'regSX_MRT0_BLEND_OPT', + 'regSX_MRT0_BLEND_OPT_BASE_IDX', 'regSX_MRT1_BLEND_OPT', + 'regSX_MRT1_BLEND_OPT_BASE_IDX', 'regSX_MRT2_BLEND_OPT', + 'regSX_MRT2_BLEND_OPT_BASE_IDX', 'regSX_MRT3_BLEND_OPT', + 'regSX_MRT3_BLEND_OPT_BASE_IDX', 'regSX_MRT4_BLEND_OPT', + 'regSX_MRT4_BLEND_OPT_BASE_IDX', 'regSX_MRT5_BLEND_OPT', + 'regSX_MRT5_BLEND_OPT_BASE_IDX', 'regSX_MRT6_BLEND_OPT', + 'regSX_MRT6_BLEND_OPT_BASE_IDX', 'regSX_MRT7_BLEND_OPT', + 'regSX_MRT7_BLEND_OPT_BASE_IDX', 'regSX_PERFCOUNTER0_HI', + 'regSX_PERFCOUNTER0_HI_BASE_IDX', 'regSX_PERFCOUNTER0_LO', + 'regSX_PERFCOUNTER0_LO_BASE_IDX', 'regSX_PERFCOUNTER0_SELECT', + 'regSX_PERFCOUNTER0_SELECT1', + 'regSX_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regSX_PERFCOUNTER0_SELECT_BASE_IDX', 'regSX_PERFCOUNTER1_HI', + 'regSX_PERFCOUNTER1_HI_BASE_IDX', 'regSX_PERFCOUNTER1_LO', + 'regSX_PERFCOUNTER1_LO_BASE_IDX', 'regSX_PERFCOUNTER1_SELECT', + 'regSX_PERFCOUNTER1_SELECT1', + 'regSX_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regSX_PERFCOUNTER1_SELECT_BASE_IDX', 'regSX_PERFCOUNTER2_HI', + 'regSX_PERFCOUNTER2_HI_BASE_IDX', 'regSX_PERFCOUNTER2_LO', + 'regSX_PERFCOUNTER2_LO_BASE_IDX', 'regSX_PERFCOUNTER2_SELECT', + 'regSX_PERFCOUNTER2_SELECT_BASE_IDX', 'regSX_PERFCOUNTER3_HI', + 'regSX_PERFCOUNTER3_HI_BASE_IDX', 'regSX_PERFCOUNTER3_LO', + 'regSX_PERFCOUNTER3_LO_BASE_IDX', 'regSX_PERFCOUNTER3_SELECT', + 'regSX_PERFCOUNTER3_SELECT_BASE_IDX', 'regSX_PS_DOWNCONVERT', + 'regSX_PS_DOWNCONVERT_BASE_IDX', 'regSX_PS_DOWNCONVERT_CONTROL', + 'regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'regTA_BC_BASE_ADDR', + 'regTA_BC_BASE_ADDR_BASE_IDX', 'regTA_BC_BASE_ADDR_HI', + 'regTA_BC_BASE_ADDR_HI_BASE_IDX', 'regTA_CGTT_CTRL', + 'regTA_CGTT_CTRL_BASE_IDX', 'regTA_CNTL', 'regTA_CNTL2', + 'regTA_CNTL2_BASE_IDX', 'regTA_CNTL_AUX', + 'regTA_CNTL_AUX_BASE_IDX', 'regTA_CNTL_BASE_IDX', + 'regTA_CS_BC_BASE_ADDR', 'regTA_CS_BC_BASE_ADDR_BASE_IDX', + 'regTA_CS_BC_BASE_ADDR_HI', 'regTA_CS_BC_BASE_ADDR_HI_BASE_IDX', + 'regTA_PERFCOUNTER0_HI', 'regTA_PERFCOUNTER0_HI_BASE_IDX', + 'regTA_PERFCOUNTER0_LO', 'regTA_PERFCOUNTER0_LO_BASE_IDX', + 'regTA_PERFCOUNTER0_SELECT', 'regTA_PERFCOUNTER0_SELECT1', + 'regTA_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTA_PERFCOUNTER0_SELECT_BASE_IDX', 'regTA_PERFCOUNTER1_HI', + 'regTA_PERFCOUNTER1_HI_BASE_IDX', 'regTA_PERFCOUNTER1_LO', + 'regTA_PERFCOUNTER1_LO_BASE_IDX', 'regTA_PERFCOUNTER1_SELECT', + 'regTA_PERFCOUNTER1_SELECT_BASE_IDX', 'regTA_SCRATCH', + 'regTA_SCRATCH_BASE_IDX', 'regTA_STATUS', 'regTA_STATUS_BASE_IDX', + 'regTCP_CNTL', 'regTCP_CNTL2', 'regTCP_CNTL2_BASE_IDX', + 'regTCP_CNTL_BASE_IDX', 'regTCP_DEBUG_DATA', + 'regTCP_DEBUG_DATA_BASE_IDX', 'regTCP_DEBUG_INDEX', + 'regTCP_DEBUG_INDEX_BASE_IDX', 'regTCP_INVALIDATE', + 'regTCP_INVALIDATE_BASE_IDX', 'regTCP_PERFCOUNTER0_HI', + 'regTCP_PERFCOUNTER0_HI_BASE_IDX', 'regTCP_PERFCOUNTER0_LO', + 'regTCP_PERFCOUNTER0_LO_BASE_IDX', 'regTCP_PERFCOUNTER0_SELECT', + 'regTCP_PERFCOUNTER0_SELECT1', + 'regTCP_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER1_HI', + 'regTCP_PERFCOUNTER1_HI_BASE_IDX', 'regTCP_PERFCOUNTER1_LO', + 'regTCP_PERFCOUNTER1_LO_BASE_IDX', 'regTCP_PERFCOUNTER1_SELECT', + 'regTCP_PERFCOUNTER1_SELECT1', + 'regTCP_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER2_HI', + 'regTCP_PERFCOUNTER2_HI_BASE_IDX', 'regTCP_PERFCOUNTER2_LO', + 'regTCP_PERFCOUNTER2_LO_BASE_IDX', 'regTCP_PERFCOUNTER2_SELECT', + 'regTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER3_HI', + 'regTCP_PERFCOUNTER3_HI_BASE_IDX', 'regTCP_PERFCOUNTER3_LO', + 'regTCP_PERFCOUNTER3_LO_BASE_IDX', 'regTCP_PERFCOUNTER3_SELECT', + 'regTCP_PERFCOUNTER3_SELECT_BASE_IDX', + 'regTCP_PERFCOUNTER_FILTER', 'regTCP_PERFCOUNTER_FILTER2', + 'regTCP_PERFCOUNTER_FILTER2_BASE_IDX', + 'regTCP_PERFCOUNTER_FILTER_BASE_IDX', + 'regTCP_PERFCOUNTER_FILTER_EN', + 'regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'regTCP_STATUS', + 'regTCP_STATUS_BASE_IDX', 'regTCP_WATCH0_ADDR_H', + 'regTCP_WATCH0_ADDR_H_BASE_IDX', 'regTCP_WATCH0_ADDR_L', + 'regTCP_WATCH0_ADDR_L_BASE_IDX', 'regTCP_WATCH0_CNTL', + 'regTCP_WATCH0_CNTL_BASE_IDX', 'regTCP_WATCH1_ADDR_H', + 'regTCP_WATCH1_ADDR_H_BASE_IDX', 'regTCP_WATCH1_ADDR_L', + 'regTCP_WATCH1_ADDR_L_BASE_IDX', 'regTCP_WATCH1_CNTL', + 'regTCP_WATCH1_CNTL_BASE_IDX', 'regTCP_WATCH2_ADDR_H', + 'regTCP_WATCH2_ADDR_H_BASE_IDX', 'regTCP_WATCH2_ADDR_L', + 'regTCP_WATCH2_ADDR_L_BASE_IDX', 'regTCP_WATCH2_CNTL', + 'regTCP_WATCH2_CNTL_BASE_IDX', 'regTCP_WATCH3_ADDR_H', + 'regTCP_WATCH3_ADDR_H_BASE_IDX', 'regTCP_WATCH3_ADDR_L', + 'regTCP_WATCH3_ADDR_L_BASE_IDX', 'regTCP_WATCH3_CNTL', + 'regTCP_WATCH3_CNTL_BASE_IDX', 'regTD_DSM_CNTL', + 'regTD_DSM_CNTL2', 'regTD_DSM_CNTL2_BASE_IDX', + 'regTD_DSM_CNTL_BASE_IDX', 'regTD_PERFCOUNTER0_HI', + 'regTD_PERFCOUNTER0_HI_BASE_IDX', 'regTD_PERFCOUNTER0_LO', + 'regTD_PERFCOUNTER0_LO_BASE_IDX', 'regTD_PERFCOUNTER0_SELECT', + 'regTD_PERFCOUNTER0_SELECT1', + 'regTD_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTD_PERFCOUNTER0_SELECT_BASE_IDX', 'regTD_PERFCOUNTER1_HI', + 'regTD_PERFCOUNTER1_HI_BASE_IDX', 'regTD_PERFCOUNTER1_LO', + 'regTD_PERFCOUNTER1_LO_BASE_IDX', 'regTD_PERFCOUNTER1_SELECT', + 'regTD_PERFCOUNTER1_SELECT_BASE_IDX', 'regTD_SCRATCH', + 'regTD_SCRATCH_BASE_IDX', 'regTD_STATUS', 'regTD_STATUS_BASE_IDX', + 'regUCONFIG_RESERVED_REG0', 'regUCONFIG_RESERVED_REG0_BASE_IDX', + 'regUCONFIG_RESERVED_REG1', 'regUCONFIG_RESERVED_REG1_BASE_IDX', + 'regUTCL1_ALOG', 'regUTCL1_ALOG_BASE_IDX', 'regUTCL1_CTRL_0', + 'regUTCL1_CTRL_0_BASE_IDX', 'regUTCL1_CTRL_1', + 'regUTCL1_CTRL_1_BASE_IDX', 'regUTCL1_CTRL_2', + 'regUTCL1_CTRL_2_BASE_IDX', 'regUTCL1_FIFO_SIZING', + 'regUTCL1_FIFO_SIZING_BASE_IDX', 'regUTCL1_PERFCOUNTER0_HI', + 'regUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'regUTCL1_PERFCOUNTER0_LO', + 'regUTCL1_PERFCOUNTER0_LO_BASE_IDX', + 'regUTCL1_PERFCOUNTER0_SELECT', + 'regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX', + 'regUTCL1_PERFCOUNTER1_HI', 'regUTCL1_PERFCOUNTER1_HI_BASE_IDX', + 'regUTCL1_PERFCOUNTER1_LO', 'regUTCL1_PERFCOUNTER1_LO_BASE_IDX', + 'regUTCL1_PERFCOUNTER1_SELECT', + 'regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX', + 'regUTCL1_PERFCOUNTER2_HI', 'regUTCL1_PERFCOUNTER2_HI_BASE_IDX', + 'regUTCL1_PERFCOUNTER2_LO', 'regUTCL1_PERFCOUNTER2_LO_BASE_IDX', + 'regUTCL1_PERFCOUNTER2_SELECT', + 'regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX', + 'regUTCL1_PERFCOUNTER3_HI', 'regUTCL1_PERFCOUNTER3_HI_BASE_IDX', + 'regUTCL1_PERFCOUNTER3_LO', 'regUTCL1_PERFCOUNTER3_LO_BASE_IDX', + 'regUTCL1_PERFCOUNTER3_SELECT', + 'regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX', 'regUTCL1_STATUS', + 'regUTCL1_STATUS_BASE_IDX', 'regUTCL1_UTCL0_INVREQ_DISABLE', + 'regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX', 'regVGT_DMA_BASE', + 'regVGT_DMA_BASE_BASE_IDX', 'regVGT_DMA_BASE_HI', + 'regVGT_DMA_BASE_HI_BASE_IDX', 'regVGT_DMA_DATA_FIFO_DEPTH', + 'regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_INDEX_TYPE', + 'regVGT_DMA_INDEX_TYPE_BASE_IDX', 'regVGT_DMA_MAX_SIZE', + 'regVGT_DMA_MAX_SIZE_BASE_IDX', 'regVGT_DMA_NUM_INSTANCES', + 'regVGT_DMA_NUM_INSTANCES_BASE_IDX', 'regVGT_DMA_REQ_FIFO_DEPTH', + 'regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_SIZE', + 'regVGT_DMA_SIZE_BASE_IDX', 'regVGT_DRAW_INITIATOR', + 'regVGT_DRAW_INITIATOR_BASE_IDX', 'regVGT_DRAW_INIT_FIFO_DEPTH', + 'regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX', + 'regVGT_DRAW_PAYLOAD_CNTL', 'regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX', + 'regVGT_ENHANCE', 'regVGT_ENHANCE_BASE_IDX', + 'regVGT_ESGS_RING_ITEMSIZE', 'regVGT_ESGS_RING_ITEMSIZE_BASE_IDX', + 'regVGT_EVENT_ADDRESS_REG', 'regVGT_EVENT_ADDRESS_REG_BASE_IDX', + 'regVGT_EVENT_INITIATOR', 'regVGT_EVENT_INITIATOR_BASE_IDX', + 'regVGT_GS_INSTANCE_CNT', 'regVGT_GS_INSTANCE_CNT_BASE_IDX', + 'regVGT_GS_MAX_VERT_OUT', 'regVGT_GS_MAX_VERT_OUT_BASE_IDX', + 'regVGT_GS_MAX_WAVE_ID', 'regVGT_GS_MAX_WAVE_ID_BASE_IDX', + 'regVGT_GS_OUT_PRIM_TYPE', 'regVGT_GS_OUT_PRIM_TYPE_BASE_IDX', + 'regVGT_HOS_MAX_TESS_LEVEL', 'regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX', + 'regVGT_HOS_MIN_TESS_LEVEL', 'regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX', + 'regVGT_HS_OFFCHIP_PARAM', 'regVGT_HS_OFFCHIP_PARAM_BASE_IDX', + 'regVGT_INDEX_TYPE', 'regVGT_INDEX_TYPE_BASE_IDX', + 'regVGT_INSTANCE_BASE_ID', 'regVGT_INSTANCE_BASE_ID_BASE_IDX', + 'regVGT_LS_HS_CONFIG', 'regVGT_LS_HS_CONFIG_BASE_IDX', + 'regVGT_MC_LAT_CNTL', 'regVGT_MC_LAT_CNTL_BASE_IDX', + 'regVGT_MULTI_PRIM_IB_RESET_INDX', + 'regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'regVGT_NUM_INDICES', + 'regVGT_NUM_INDICES_BASE_IDX', 'regVGT_NUM_INSTANCES', + 'regVGT_NUM_INSTANCES_BASE_IDX', 'regVGT_PRIMITIVEID_EN', + 'regVGT_PRIMITIVEID_EN_BASE_IDX', 'regVGT_PRIMITIVEID_RESET', + 'regVGT_PRIMITIVEID_RESET_BASE_IDX', 'regVGT_PRIMITIVE_TYPE', + 'regVGT_PRIMITIVE_TYPE_BASE_IDX', 'regVGT_REUSE_OFF', + 'regVGT_REUSE_OFF_BASE_IDX', 'regVGT_SHADER_STAGES_EN', + 'regVGT_SHADER_STAGES_EN_BASE_IDX', + 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE', + 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX', + 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET', + 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX', + 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE', + 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX', + 'regVGT_SYS_CONFIG', 'regVGT_SYS_CONFIG_BASE_IDX', + 'regVGT_TESS_DISTRIBUTION', 'regVGT_TESS_DISTRIBUTION_BASE_IDX', + 'regVGT_TF_MEMORY_BASE', 'regVGT_TF_MEMORY_BASE_BASE_IDX', + 'regVGT_TF_MEMORY_BASE_HI', 'regVGT_TF_MEMORY_BASE_HI_BASE_IDX', + 'regVGT_TF_PARAM', 'regVGT_TF_PARAM_BASE_IDX', + 'regVGT_TF_RING_SIZE', 'regVGT_TF_RING_SIZE_BASE_IDX', + 'regVIOLATION_DATA_ASYNC_VF_PROG', + 'regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'regWD_CNTL_STATUS', + 'regWD_CNTL_STATUS_BASE_IDX', 'regWD_ENHANCE', + 'regWD_ENHANCE_BASE_IDX', 'regWD_QOS', 'regWD_QOS_BASE_IDX', + 'regWD_UTCL1_CNTL', 'regWD_UTCL1_CNTL_BASE_IDX', + 'regWD_UTCL1_STATUS', 'regWD_UTCL1_STATUS_BASE_IDX'] diff --git a/tinygrad/runtime/autogen/am/mmhub_3_0_0.py b/tinygrad/runtime/autogen/am/mmhub_3_0_0.py new file mode 100644 index 0000000000..a1435858e7 --- /dev/null +++ b/tinygrad/runtime/autogen/am/mmhub_3_0_0.py @@ -0,0 +1,15475 @@ +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_mmhub_3_0_0_OFFSET_HEADER = True # macro +regDAGB0_RDCLI0 = 0x0000 # macro +regDAGB0_RDCLI0_BASE_IDX = 0 # macro +regDAGB0_RDCLI1 = 0x0001 # macro +regDAGB0_RDCLI1_BASE_IDX = 0 # macro +regDAGB0_RDCLI2 = 0x0002 # macro +regDAGB0_RDCLI2_BASE_IDX = 0 # macro +regDAGB0_RDCLI3 = 0x0003 # macro +regDAGB0_RDCLI3_BASE_IDX = 0 # macro +regDAGB0_RDCLI4 = 0x0004 # macro +regDAGB0_RDCLI4_BASE_IDX = 0 # macro +regDAGB0_RDCLI5 = 0x0005 # macro +regDAGB0_RDCLI5_BASE_IDX = 0 # macro +regDAGB0_RDCLI6 = 0x0006 # macro +regDAGB0_RDCLI6_BASE_IDX = 0 # macro +regDAGB0_RDCLI7 = 0x0007 # macro +regDAGB0_RDCLI7_BASE_IDX = 0 # macro +regDAGB0_RDCLI8 = 0x0008 # macro +regDAGB0_RDCLI8_BASE_IDX = 0 # macro +regDAGB0_RDCLI9 = 0x0009 # macro +regDAGB0_RDCLI9_BASE_IDX = 0 # macro +regDAGB0_RDCLI10 = 0x000a # macro +regDAGB0_RDCLI10_BASE_IDX = 0 # macro +regDAGB0_RDCLI11 = 0x000b # macro +regDAGB0_RDCLI11_BASE_IDX = 0 # macro +regDAGB0_RDCLI12 = 0x000c # macro +regDAGB0_RDCLI12_BASE_IDX = 0 # macro +regDAGB0_RDCLI13 = 0x000d # macro +regDAGB0_RDCLI13_BASE_IDX = 0 # macro +regDAGB0_RDCLI14 = 0x000e # macro +regDAGB0_RDCLI14_BASE_IDX = 0 # macro +regDAGB0_RDCLI15 = 0x000f # macro +regDAGB0_RDCLI15_BASE_IDX = 0 # macro +regDAGB0_RDCLI16 = 0x0010 # macro +regDAGB0_RDCLI16_BASE_IDX = 0 # macro +regDAGB0_RDCLI17 = 0x0011 # macro +regDAGB0_RDCLI17_BASE_IDX = 0 # macro +regDAGB0_RDCLI18 = 0x0012 # macro +regDAGB0_RDCLI18_BASE_IDX = 0 # macro +regDAGB0_RDCLI19 = 0x0013 # macro +regDAGB0_RDCLI19_BASE_IDX = 0 # macro +regDAGB0_RDCLI20 = 0x0014 # macro +regDAGB0_RDCLI20_BASE_IDX = 0 # macro +regDAGB0_RDCLI21 = 0x0015 # macro +regDAGB0_RDCLI21_BASE_IDX = 0 # macro +regDAGB0_RDCLI22 = 0x0016 # macro +regDAGB0_RDCLI22_BASE_IDX = 0 # macro +regDAGB0_RDCLI23 = 0x0017 # macro +regDAGB0_RDCLI23_BASE_IDX = 0 # macro +regDAGB0_RD_CNTL = 0x0018 # macro +regDAGB0_RD_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_IO_CNTL = 0x0019 # macro +regDAGB0_RD_IO_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_GMI_CNTL = 0x001a # macro +regDAGB0_RD_GMI_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB = 0x001b # macro +regDAGB0_RD_ADDR_DAGB_BASE_IDX = 0 # macro +regDAGB0_RD_CGTT_CLK_CTRL = 0x001c # macro +regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_L1TLB_RD_CGTT_CLK_CTRL = 0x001d # macro +regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST0 = 0x001e # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 = 0x001f # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST1 = 0x0020 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 = 0x0021 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST2 = 0x0022 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 = 0x0023 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB0_RD_VC0_CNTL = 0x0024 # macro +regDAGB0_RD_VC0_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC1_CNTL = 0x0025 # macro +regDAGB0_RD_VC1_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC2_CNTL = 0x0026 # macro +regDAGB0_RD_VC2_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC3_CNTL = 0x0027 # macro +regDAGB0_RD_VC3_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC4_CNTL = 0x0028 # macro +regDAGB0_RD_VC4_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC5_CNTL = 0x0029 # macro +regDAGB0_RD_VC5_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_IO_VC_CNTL = 0x002a # macro +regDAGB0_RD_IO_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_GMI_VC_CNTL = 0x002b # macro +regDAGB0_RD_GMI_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_CNTL_MISC = 0x002c # macro +regDAGB0_RD_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB0_RD_TLB_CREDIT = 0x002d # macro +regDAGB0_RD_TLB_CREDIT_BASE_IDX = 0 # macro +regDAGB0_RD_RDRET_CREDIT_CNTL = 0x002e # macro +regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_RDRET_CREDIT_CNTL2 = 0x002f # macro +regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK_PENDING = 0x0030 # macro +regDAGB0_RDCLI_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_GO_PENDING = 0x0031 # macro +regDAGB0_RDCLI_GO_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_GBLSEND_PENDING = 0x0032 # macro +regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_TLB_PENDING = 0x0033 # macro +regDAGB0_RDCLI_TLB_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_OARB_PENDING = 0x0034 # macro +regDAGB0_RDCLI_OARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK2ARB_PENDING = 0x0035 # macro +regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK2DF_PENDING = 0x0036 # macro +regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_OSD_PENDING = 0x0037 # macro +regDAGB0_RDCLI_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK_OSD_PENDING = 0x0038 # macro +regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE = 0x0039 # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE = 0x003a # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB0_WRCLI0 = 0x003b # macro +regDAGB0_WRCLI0_BASE_IDX = 0 # macro +regDAGB0_WRCLI1 = 0x003c # macro +regDAGB0_WRCLI1_BASE_IDX = 0 # macro +regDAGB0_WRCLI2 = 0x003d # macro +regDAGB0_WRCLI2_BASE_IDX = 0 # macro +regDAGB0_WRCLI3 = 0x003e # macro +regDAGB0_WRCLI3_BASE_IDX = 0 # macro +regDAGB0_WRCLI4 = 0x003f # macro +regDAGB0_WRCLI4_BASE_IDX = 0 # macro +regDAGB0_WRCLI5 = 0x0040 # macro +regDAGB0_WRCLI5_BASE_IDX = 0 # macro +regDAGB0_WRCLI6 = 0x0041 # macro +regDAGB0_WRCLI6_BASE_IDX = 0 # macro +regDAGB0_WRCLI7 = 0x0042 # macro +regDAGB0_WRCLI7_BASE_IDX = 0 # macro +regDAGB0_WRCLI8 = 0x0043 # macro +regDAGB0_WRCLI8_BASE_IDX = 0 # macro +regDAGB0_WRCLI9 = 0x0044 # macro +regDAGB0_WRCLI9_BASE_IDX = 0 # macro +regDAGB0_WRCLI10 = 0x0045 # macro +regDAGB0_WRCLI10_BASE_IDX = 0 # macro +regDAGB0_WRCLI11 = 0x0046 # macro +regDAGB0_WRCLI11_BASE_IDX = 0 # macro +regDAGB0_WRCLI12 = 0x0047 # macro +regDAGB0_WRCLI12_BASE_IDX = 0 # macro +regDAGB0_WRCLI13 = 0x0048 # macro +regDAGB0_WRCLI13_BASE_IDX = 0 # macro +regDAGB0_WRCLI14 = 0x0049 # macro +regDAGB0_WRCLI14_BASE_IDX = 0 # macro +regDAGB0_WRCLI15 = 0x004a # macro +regDAGB0_WRCLI15_BASE_IDX = 0 # macro +regDAGB0_WRCLI16 = 0x004b # macro +regDAGB0_WRCLI16_BASE_IDX = 0 # macro +regDAGB0_WRCLI17 = 0x004c # macro +regDAGB0_WRCLI17_BASE_IDX = 0 # macro +regDAGB0_WRCLI18 = 0x004d # macro +regDAGB0_WRCLI18_BASE_IDX = 0 # macro +regDAGB0_WRCLI19 = 0x004e # macro +regDAGB0_WRCLI19_BASE_IDX = 0 # macro +regDAGB0_WRCLI20 = 0x004f # macro +regDAGB0_WRCLI20_BASE_IDX = 0 # macro +regDAGB0_WRCLI21 = 0x0050 # macro +regDAGB0_WRCLI21_BASE_IDX = 0 # macro +regDAGB0_WRCLI22 = 0x0051 # macro +regDAGB0_WRCLI22_BASE_IDX = 0 # macro +regDAGB0_WRCLI23 = 0x0052 # macro +regDAGB0_WRCLI23_BASE_IDX = 0 # macro +regDAGB0_WR_CNTL = 0x0053 # macro +regDAGB0_WR_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_IO_CNTL = 0x0054 # macro +regDAGB0_WR_IO_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_GMI_CNTL = 0x0055 # macro +regDAGB0_WR_GMI_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB = 0x0056 # macro +regDAGB0_WR_ADDR_DAGB_BASE_IDX = 0 # macro +regDAGB0_WR_CGTT_CLK_CTRL = 0x0057 # macro +regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_L1TLB_WR_CGTT_CLK_CTRL = 0x0058 # macro +regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST0 = 0x0059 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 = 0x005a # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST1 = 0x005b # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 = 0x005c # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST2 = 0x005d # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 = 0x005e # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB = 0x005f # macro +regDAGB0_WR_DATA_DAGB_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST0 = 0x0060 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 = 0x0061 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST1 = 0x0062 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 = 0x0063 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST2 = 0x0064 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 = 0x0065 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB0_WR_VC0_CNTL = 0x0066 # macro +regDAGB0_WR_VC0_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC1_CNTL = 0x0067 # macro +regDAGB0_WR_VC1_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC2_CNTL = 0x0068 # macro +regDAGB0_WR_VC2_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC3_CNTL = 0x0069 # macro +regDAGB0_WR_VC3_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC4_CNTL = 0x006a # macro +regDAGB0_WR_VC4_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC5_CNTL = 0x006b # macro +regDAGB0_WR_VC5_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_IO_VC_CNTL = 0x006c # macro +regDAGB0_WR_IO_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_GMI_VC_CNTL = 0x006d # macro +regDAGB0_WR_GMI_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_CNTL_MISC = 0x006e # macro +regDAGB0_WR_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB0_WR_TLB_CREDIT = 0x006f # macro +regDAGB0_WR_TLB_CREDIT_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_CREDIT = 0x0070 # macro +regDAGB0_WR_DATA_CREDIT_BASE_IDX = 0 # macro +regDAGB0_WR_MISC_CREDIT = 0x0071 # macro +regDAGB0_WR_MISC_CREDIT_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 = 0x0072 # macro +regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX = 0 # macro +regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 = 0x0073 # macro +regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK_PENDING = 0x0074 # macro +regDAGB0_WRCLI_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GO_PENDING = 0x0075 # macro +regDAGB0_WRCLI_GO_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GBLSEND_PENDING = 0x0076 # macro +regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_TLB_PENDING = 0x0077 # macro +regDAGB0_WRCLI_TLB_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_OARB_PENDING = 0x0078 # macro +regDAGB0_WRCLI_OARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK2ARB_PENDING = 0x0079 # macro +regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK2DF_PENDING = 0x007a # macro +regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_OSD_PENDING = 0x007b # macro +regDAGB0_WRCLI_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK_OSD_PENDING = 0x007c # macro +regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_DBUS_ASK_PENDING = 0x007d # macro +regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_DBUS_GO_PENDING = 0x007e # macro +regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE = 0x007f # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE = 0x0080 # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE = 0x0081 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE = 0x0082 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB0_DAGB_DLY = 0x0083 # macro +regDAGB0_DAGB_DLY_BASE_IDX = 0 # macro +regDAGB0_CNTL_MISC = 0x0084 # macro +regDAGB0_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB0_CNTL_MISC2 = 0x0085 # macro +regDAGB0_CNTL_MISC2_BASE_IDX = 0 # macro +regDAGB0_FIFO_EMPTY = 0x0086 # macro +regDAGB0_FIFO_EMPTY_BASE_IDX = 0 # macro +regDAGB0_FIFO_FULL = 0x0087 # macro +regDAGB0_FIFO_FULL_BASE_IDX = 0 # macro +regDAGB0_RD_CREDITS_FULL = 0x0088 # macro +regDAGB0_RD_CREDITS_FULL_BASE_IDX = 0 # macro +regDAGB0_WR_CREDITS_FULL = 0x0089 # macro +regDAGB0_WR_CREDITS_FULL_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER_LO = 0x008a # macro +regDAGB0_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER_HI = 0x008b # macro +regDAGB0_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER0_CFG = 0x008c # macro +regDAGB0_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER1_CFG = 0x008d # macro +regDAGB0_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER2_CFG = 0x008e # macro +regDAGB0_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER_RSLT_CNTL = 0x008f # macro +regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regDAGB0_L1TLB_REG_RW = 0x0090 # macro +regDAGB0_L1TLB_REG_RW_BASE_IDX = 0 # macro +regDAGB0_RESERVE1 = 0x0091 # macro +regDAGB0_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_RESERVE2 = 0x0092 # macro +regDAGB0_RESERVE2_BASE_IDX = 0 # macro +regDAGB0_RESERVE3 = 0x0093 # macro +regDAGB0_RESERVE3_BASE_IDX = 0 # macro +regDAGB0_RESERVE4 = 0x0094 # macro +regDAGB0_RESERVE4_BASE_IDX = 0 # macro +regDAGB0_SDP_RD_BW_CNTL = 0x0095 # macro +regDAGB0_SDP_RD_BW_CNTL_BASE_IDX = 0 # macro +regDAGB0_SDP_PRIORITY_OVERRIDE = 0x0096 # macro +regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_SDP_RD_PRIORITY = 0x0097 # macro +regDAGB0_SDP_RD_PRIORITY_BASE_IDX = 0 # macro +regDAGB0_SDP_WR_PRIORITY = 0x0098 # macro +regDAGB0_SDP_WR_PRIORITY_BASE_IDX = 0 # macro +regDAGB0_SDP_RD_CLI2SDP_VC_MAP = 0x0099 # macro +regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX = 0 # macro +regDAGB0_SDP_WR_CLI2SDP_VC_MAP = 0x009a # macro +regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX = 0 # macro +regDAGB0_SDP_ENABLE = 0x009b # macro +regDAGB0_SDP_ENABLE_BASE_IDX = 0 # macro +regDAGB0_SDP_CREDITS = 0x009c # macro +regDAGB0_SDP_CREDITS_BASE_IDX = 0 # macro +regDAGB0_SDP_TAG_RESERVE0 = 0x009d # macro +regDAGB0_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro +regDAGB0_SDP_TAG_RESERVE1 = 0x009e # macro +regDAGB0_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_SDP_VCC_RESERVE0 = 0x009f # macro +regDAGB0_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro +regDAGB0_SDP_VCC_RESERVE1 = 0x00a0 # macro +regDAGB0_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_SDP_ERR_STATUS = 0x00a1 # macro +regDAGB0_SDP_ERR_STATUS_BASE_IDX = 0 # macro +regDAGB0_SDP_REQ_CNTL = 0x00a2 # macro +regDAGB0_SDP_REQ_CNTL_BASE_IDX = 0 # macro +regDAGB0_SDP_MISC = 0x00a4 # macro +regDAGB0_SDP_MISC_BASE_IDX = 0 # macro +regDAGB0_SDP_MISC2 = 0x00a5 # macro +regDAGB0_SDP_MISC2_BASE_IDX = 0 # macro +regDAGB0_SDP_VCD_RESERVE0 = 0x00a7 # macro +regDAGB0_SDP_VCD_RESERVE0_BASE_IDX = 0 # macro +regDAGB0_SDP_VCD_RESERVE1 = 0x00a8 # macro +regDAGB0_SDP_VCD_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_SDP_ARB_CNTL0 = 0x00a9 # macro +regDAGB0_SDP_ARB_CNTL0_BASE_IDX = 0 # macro +regDAGB0_SDP_ARB_CNTL1 = 0x00aa # macro +regDAGB0_SDP_ARB_CNTL1_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_CNTL = 0x00ab # macro +regDAGB0_FATAL_ERROR_CNTL_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_CLEAR = 0x00ac # macro +regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS0 = 0x00ad # macro +regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS1 = 0x00ae # macro +regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS2 = 0x00af # macro +regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS3 = 0x00b0 # macro +regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS4 = 0x00b1 # macro +regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX = 0 # macro +regDAGB0_SDP_CGTT_CLK_CTRL = 0x00b6 # macro +regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_SDP_LATENCY_SAMPLING = 0x00b7 # macro +regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX = 0 # macro +regDAGB1_RDCLI0 = 0x00b8 # macro +regDAGB1_RDCLI0_BASE_IDX = 0 # macro +regDAGB1_RDCLI1 = 0x00b9 # macro +regDAGB1_RDCLI1_BASE_IDX = 0 # macro +regDAGB1_RDCLI2 = 0x00ba # macro +regDAGB1_RDCLI2_BASE_IDX = 0 # macro +regDAGB1_RDCLI3 = 0x00bb # macro +regDAGB1_RDCLI3_BASE_IDX = 0 # macro +regDAGB1_RDCLI4 = 0x00bc # macro +regDAGB1_RDCLI4_BASE_IDX = 0 # macro +regDAGB1_RDCLI5 = 0x00bd # macro +regDAGB1_RDCLI5_BASE_IDX = 0 # macro +regDAGB1_RDCLI6 = 0x00be # macro +regDAGB1_RDCLI6_BASE_IDX = 0 # macro +regDAGB1_RDCLI7 = 0x00bf # macro +regDAGB1_RDCLI7_BASE_IDX = 0 # macro +regDAGB1_RDCLI8 = 0x00c0 # macro +regDAGB1_RDCLI8_BASE_IDX = 0 # macro +regDAGB1_RDCLI9 = 0x00c1 # macro +regDAGB1_RDCLI9_BASE_IDX = 0 # macro +regDAGB1_RDCLI10 = 0x00c2 # macro +regDAGB1_RDCLI10_BASE_IDX = 0 # macro +regDAGB1_RDCLI11 = 0x00c3 # macro +regDAGB1_RDCLI11_BASE_IDX = 0 # macro +regDAGB1_RDCLI12 = 0x00c4 # macro +regDAGB1_RDCLI12_BASE_IDX = 0 # macro +regDAGB1_RDCLI13 = 0x00c5 # macro +regDAGB1_RDCLI13_BASE_IDX = 0 # macro +regDAGB1_RDCLI14 = 0x00c6 # macro +regDAGB1_RDCLI14_BASE_IDX = 0 # macro +regDAGB1_RDCLI15 = 0x00c7 # macro +regDAGB1_RDCLI15_BASE_IDX = 0 # macro +regDAGB1_RDCLI16 = 0x00c8 # macro +regDAGB1_RDCLI16_BASE_IDX = 0 # macro +regDAGB1_RDCLI17 = 0x00c9 # macro +regDAGB1_RDCLI17_BASE_IDX = 0 # macro +regDAGB1_RDCLI18 = 0x00ca # macro +regDAGB1_RDCLI18_BASE_IDX = 0 # macro +regDAGB1_RDCLI19 = 0x00cb # macro +regDAGB1_RDCLI19_BASE_IDX = 0 # macro +regDAGB1_RDCLI20 = 0x00cc # macro +regDAGB1_RDCLI20_BASE_IDX = 0 # macro +regDAGB1_RDCLI21 = 0x00cd # macro +regDAGB1_RDCLI21_BASE_IDX = 0 # macro +regDAGB1_RDCLI22 = 0x00ce # macro +regDAGB1_RDCLI22_BASE_IDX = 0 # macro +regDAGB1_RDCLI23 = 0x00cf # macro +regDAGB1_RDCLI23_BASE_IDX = 0 # macro +regDAGB1_RD_CNTL = 0x00d0 # macro +regDAGB1_RD_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_IO_CNTL = 0x00d1 # macro +regDAGB1_RD_IO_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_GMI_CNTL = 0x00d2 # macro +regDAGB1_RD_GMI_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB = 0x00d3 # macro +regDAGB1_RD_ADDR_DAGB_BASE_IDX = 0 # macro +regDAGB1_RD_CGTT_CLK_CTRL = 0x00d4 # macro +regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB1_L1TLB_RD_CGTT_CLK_CTRL = 0x00d5 # macro +regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST0 = 0x00d6 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 = 0x00d7 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST1 = 0x00d8 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 = 0x00d9 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST2 = 0x00da # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 = 0x00db # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB1_RD_VC0_CNTL = 0x00dc # macro +regDAGB1_RD_VC0_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC1_CNTL = 0x00dd # macro +regDAGB1_RD_VC1_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC2_CNTL = 0x00de # macro +regDAGB1_RD_VC2_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC3_CNTL = 0x00df # macro +regDAGB1_RD_VC3_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC4_CNTL = 0x00e0 # macro +regDAGB1_RD_VC4_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC5_CNTL = 0x00e1 # macro +regDAGB1_RD_VC5_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_IO_VC_CNTL = 0x00e2 # macro +regDAGB1_RD_IO_VC_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_GMI_VC_CNTL = 0x00e3 # macro +regDAGB1_RD_GMI_VC_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_CNTL_MISC = 0x00e4 # macro +regDAGB1_RD_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB1_RD_TLB_CREDIT = 0x00e5 # macro +regDAGB1_RD_TLB_CREDIT_BASE_IDX = 0 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL = 0x00e6 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL2 = 0x00e7 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK_PENDING = 0x00e8 # macro +regDAGB1_RDCLI_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_GO_PENDING = 0x00e9 # macro +regDAGB1_RDCLI_GO_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_GBLSEND_PENDING = 0x00ea # macro +regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_TLB_PENDING = 0x00eb # macro +regDAGB1_RDCLI_TLB_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_OARB_PENDING = 0x00ec # macro +regDAGB1_RDCLI_OARB_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK2ARB_PENDING = 0x00ed # macro +regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK2DF_PENDING = 0x00ee # macro +regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_OSD_PENDING = 0x00ef # macro +regDAGB1_RDCLI_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK_OSD_PENDING = 0x00f0 # macro +regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE = 0x00f1 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX = 0 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE = 0x00f2 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB1_DAGB_DLY = 0x00f3 # macro +regDAGB1_DAGB_DLY_BASE_IDX = 0 # macro +regDAGB1_CNTL_MISC = 0x00f4 # macro +regDAGB1_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB1_CNTL_MISC2 = 0x00f5 # macro +regDAGB1_CNTL_MISC2_BASE_IDX = 0 # macro +regDAGB1_FIFO_EMPTY = 0x00f6 # macro +regDAGB1_FIFO_EMPTY_BASE_IDX = 0 # macro +regDAGB1_FIFO_FULL = 0x00f7 # macro +regDAGB1_FIFO_FULL_BASE_IDX = 0 # macro +regDAGB1_RD_CREDITS_FULL = 0x00f8 # macro +regDAGB1_RD_CREDITS_FULL_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER_LO = 0x00f9 # macro +regDAGB1_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER_HI = 0x00fa # macro +regDAGB1_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER0_CFG = 0x00fb # macro +regDAGB1_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER1_CFG = 0x00fc # macro +regDAGB1_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER2_CFG = 0x00fd # macro +regDAGB1_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER_RSLT_CNTL = 0x00fe # macro +regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regDAGB1_L1TLB_REG_RW = 0x00ff # macro +regDAGB1_L1TLB_REG_RW_BASE_IDX = 0 # macro +regDAGB1_RESERVE1 = 0x0100 # macro +regDAGB1_RESERVE1_BASE_IDX = 0 # macro +regDAGB1_RESERVE2 = 0x0101 # macro +regDAGB1_RESERVE2_BASE_IDX = 0 # macro +regDAGB1_RESERVE3 = 0x0102 # macro +regDAGB1_RESERVE3_BASE_IDX = 0 # macro +regDAGB1_RESERVE4 = 0x0103 # macro +regDAGB1_RESERVE4_BASE_IDX = 0 # macro +regDAGB1_SDP_RD_BW_CNTL = 0x0104 # macro +regDAGB1_SDP_RD_BW_CNTL_BASE_IDX = 0 # macro +regDAGB1_SDP_PRIORITY_OVERRIDE = 0x0105 # macro +regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX = 0 # macro +regDAGB1_SDP_RD_PRIORITY = 0x0106 # macro +regDAGB1_SDP_RD_PRIORITY_BASE_IDX = 0 # macro +regDAGB1_SDP_RD_CLI2SDP_VC_MAP = 0x0107 # macro +regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX = 0 # macro +regDAGB1_SDP_ENABLE = 0x0108 # macro +regDAGB1_SDP_ENABLE_BASE_IDX = 0 # macro +regDAGB1_SDP_CREDITS = 0x0109 # macro +regDAGB1_SDP_CREDITS_BASE_IDX = 0 # macro +regDAGB1_SDP_TAG_RESERVE0 = 0x010a # macro +regDAGB1_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro +regDAGB1_SDP_TAG_RESERVE1 = 0x010b # macro +regDAGB1_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro +regDAGB1_SDP_VCC_RESERVE0 = 0x010c # macro +regDAGB1_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro +regDAGB1_SDP_VCC_RESERVE1 = 0x010d # macro +regDAGB1_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro +regDAGB1_SDP_ERR_STATUS = 0x010e # macro +regDAGB1_SDP_ERR_STATUS_BASE_IDX = 0 # macro +regDAGB1_SDP_REQ_CNTL = 0x010f # macro +regDAGB1_SDP_REQ_CNTL_BASE_IDX = 0 # macro +regDAGB1_SDP_MISC = 0x0111 # macro +regDAGB1_SDP_MISC_BASE_IDX = 0 # macro +regDAGB1_SDP_MISC2 = 0x0112 # macro +regDAGB1_SDP_MISC2_BASE_IDX = 0 # macro +regDAGB1_SDP_ARB_CNTL0 = 0x0114 # macro +regDAGB1_SDP_ARB_CNTL0_BASE_IDX = 0 # macro +regDAGB1_SDP_ARB_CNTL1 = 0x0115 # macro +regDAGB1_SDP_ARB_CNTL1_BASE_IDX = 0 # macro +regDAGB1_SDP_CGTT_CLK_CTRL = 0x0116 # macro +regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB1_SDP_LATENCY_SAMPLING = 0x0117 # macro +regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX = 0 # macro +regPCTL_CTRL = 0x0380 # macro +regPCTL_CTRL_BASE_IDX = 0 # macro +regPCTL_MMHUB_DEEPSLEEP_IB = 0x0381 # macro +regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX = 0 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE = 0x0382 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX = 0 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB = 0x0383 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX = 0 # macro +regPCTL_PG_IGNORE_DEEPSLEEP = 0x0384 # macro +regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX = 0 # macro +regPCTL_PG_IGNORE_DEEPSLEEP_IB = 0x0385 # macro +regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DAGB_WRBUSY = 0x0386 # macro +regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DAGB_RDBUSY = 0x0387 # macro +regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DS_ALLOW = 0x0388 # macro +regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DS_ALLOW_IB = 0x0389 # macro +regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DAGB_WRBUSY = 0x038a # macro +regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DAGB_RDBUSY = 0x038b # macro +regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DS_ALLOW = 0x038c # macro +regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DS_ALLOW_IB = 0x038d # macro +regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX = 0 # macro +regPCTL_UTCL2_MISC = 0x038e # macro +regPCTL_UTCL2_MISC_BASE_IDX = 0 # macro +regPCTL_SLICE0_MISC = 0x038f # macro +regPCTL_SLICE0_MISC_BASE_IDX = 0 # macro +regPCTL_SLICE1_MISC = 0x0390 # macro +regPCTL_SLICE1_MISC_BASE_IDX = 0 # macro +regPCTL_RENG_CTRL = 0x0391 # macro +regPCTL_RENG_CTRL_BASE_IDX = 0 # macro +regPCTL_UTCL2_RENG_EXECUTE = 0x0392 # macro +regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX = 0 # macro +regPCTL_SLICE0_RENG_EXECUTE = 0x0393 # macro +regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX = 0 # macro +regPCTL_SLICE1_RENG_EXECUTE = 0x0394 # macro +regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX = 0 # macro +regPCTL_UTCL2_RENG_RAM_INDEX = 0x0395 # macro +regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX = 0 # macro +regPCTL_UTCL2_RENG_RAM_DATA = 0x0396 # macro +regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX = 0 # macro +regPCTL_SLICE0_RENG_RAM_INDEX = 0x0397 # macro +regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX = 0 # macro +regPCTL_SLICE0_RENG_RAM_DATA = 0x0398 # macro +regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX = 0 # macro +regPCTL_SLICE1_RENG_RAM_INDEX = 0x0399 # macro +regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX = 0 # macro +regPCTL_SLICE1_RENG_RAM_DATA = 0x039a # macro +regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 = 0x039b # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 = 0x039c # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 = 0x039d # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 = 0x039e # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 = 0x039f # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 = 0x03a0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 = 0x03a1 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 = 0x03a2 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 = 0x03a3 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 = 0x03a4 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 = 0x03a5 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 = 0x03a6 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 = 0x03a7 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 = 0x03a8 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 = 0x03a9 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 = 0x03aa # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 = 0x03ab # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 = 0x03ac # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 = 0x03ad # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 = 0x03ae # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 = 0x03af # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX = 0 # macro +regPCTL_STATUS = 0x03b0 # macro +regPCTL_STATUS_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER_LO = 0x03b1 # macro +regPCTL_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER_HI = 0x03b2 # macro +regPCTL_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER0_CFG = 0x03b3 # macro +regPCTL_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER1_CFG = 0x03b4 # macro +regPCTL_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER_RSLT_CNTL = 0x03b5 # macro +regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regPCTL_RESERVED_0 = 0x03b6 # macro +regPCTL_RESERVED_0_BASE_IDX = 0 # macro +regPCTL_RESERVED_1 = 0x03b7 # macro +regPCTL_RESERVED_1_BASE_IDX = 0 # macro +regPCTL_RESERVED_2 = 0x03b8 # macro +regPCTL_RESERVED_2_BASE_IDX = 0 # macro +regPCTL_RESERVED_3 = 0x03b9 # macro +regPCTL_RESERVED_3_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB0_STATUS = 0x0586 # macro +regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB1_STATUS = 0x0587 # macro +regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB2_STATUS = 0x0588 # macro +regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB3_STATUS = 0x0589 # macro +regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB4_STATUS = 0x058a # macro +regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB5_STATUS = 0x058b # macro +regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER0_CFG = 0x059c # macro +regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER1_CFG = 0x059d # macro +regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER2_CFG = 0x059e # macro +regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER3_CFG = 0x059f # macro +regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL = 0x05a0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_LO = 0x05a4 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_HI = 0x05a5 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regMM_ATC_L2_CNTL = 0x06c0 # macro +regMM_ATC_L2_CNTL_BASE_IDX = 0 # macro +regMM_ATC_L2_CNTL2 = 0x06c1 # macro +regMM_ATC_L2_CNTL2_BASE_IDX = 0 # macro +regMM_ATC_L2_CACHE_DATA0 = 0x06c4 # macro +regMM_ATC_L2_CACHE_DATA0_BASE_IDX = 0 # macro +regMM_ATC_L2_CACHE_DATA1 = 0x06c5 # macro +regMM_ATC_L2_CACHE_DATA1_BASE_IDX = 0 # macro +regMM_ATC_L2_CACHE_DATA2 = 0x06c6 # macro +regMM_ATC_L2_CACHE_DATA2_BASE_IDX = 0 # macro +regMM_ATC_L2_CNTL3 = 0x06c7 # macro +regMM_ATC_L2_CNTL3_BASE_IDX = 0 # macro +regMM_ATC_L2_CNTL4 = 0x06c8 # macro +regMM_ATC_L2_CNTL4_BASE_IDX = 0 # macro +regMM_ATC_L2_CNTL5 = 0x06c9 # macro +regMM_ATC_L2_CNTL5_BASE_IDX = 0 # macro +regMM_ATC_L2_MM_GROUP_RT_CLASSES = 0x06ca # macro +regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro +regMM_ATC_L2_STATUS = 0x06cb # macro +regMM_ATC_L2_STATUS_BASE_IDX = 0 # macro +regMM_ATC_L2_STATUS2 = 0x06cc # macro +regMM_ATC_L2_STATUS2_BASE_IDX = 0 # macro +regMM_ATC_L2_MISC_CG = 0x06cd # macro +regMM_ATC_L2_MISC_CG_BASE_IDX = 0 # macro +regMM_ATC_L2_MEM_POWER_LS = 0x06ce # macro +regMM_ATC_L2_MEM_POWER_LS_BASE_IDX = 0 # macro +regMM_ATC_L2_CGTT_CLK_CTRL = 0x06cf # macro +regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regMM_ATC_L2_SDPPORT_CTRL = 0x06d2 # macro +regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX = 0 # macro +regMMUTCL2_FFBM_CONFIG = 0x06d4 # macro +regMMUTCL2_FFBM_CONFIG_BASE_IDX = 0 # macro +regMMUTCL2_FFBM_ACCESS_CNTL = 0x06d5 # macro +regMMUTCL2_FFBM_ACCESS_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_FFBM_ADDRESS = 0x06d6 # macro +regMMUTCL2_FFBM_ADDRESS_BASE_IDX = 0 # macro +regMMUTCL2_FFBM_DATA = 0x06d7 # macro +regMMUTCL2_FFBM_DATA_BASE_IDX = 0 # macro +regMMUTCL2_FFBM_INVALIDATE_REQUEST = 0x06d8 # macro +regMMUTCL2_FFBM_INVALIDATE_REQUEST_BASE_IDX = 0 # macro +regMMUTCL2_FFBM_INVALIDATE_RESPONSE = 0x06d9 # macro +regMMUTCL2_FFBM_INVALIDATE_RESPONSE_BASE_IDX = 0 # macro +regMMVM_L2_CNTL = 0x0700 # macro +regMMVM_L2_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_CNTL2 = 0x0701 # macro +regMMVM_L2_CNTL2_BASE_IDX = 0 # macro +regMMVM_L2_CNTL3 = 0x0702 # macro +regMMVM_L2_CNTL3_BASE_IDX = 0 # macro +regMMVM_L2_STATUS = 0x0703 # macro +regMMVM_L2_STATUS_BASE_IDX = 0 # macro +regMMVM_DUMMY_PAGE_FAULT_CNTL = 0x0704 # macro +regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x0705 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x0706 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_CNTL = 0x0707 # macro +regMMVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL = 0x0708 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL2 = 0x0709 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x070a # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x070b # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_STATUS = 0x070c # macro +regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x070d # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x070e # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x070f # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x0710 # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x0712 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x0713 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x0714 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x0715 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x0716 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x0717 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CNTL4 = 0x0718 # macro +regMMVM_L2_CNTL4_BASE_IDX = 0 # macro +regMMVM_L2_MM_GROUP_RT_CLASSES = 0x0719 # macro +regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID = 0x071a # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID2 = 0x071b # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro +regMMVM_L2_CACHE_PARITY_CNTL = 0x071c # macro +regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_CGTT_CLK_CTRL = 0x071d # macro +regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regMMVM_L2_CNTL5 = 0x071e # macro +regMMVM_L2_CNTL5_BASE_IDX = 0 # macro +regMMVM_L2_GCR_CNTL = 0x071f # macro +regMMVM_L2_GCR_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_CGTT_BUSY_CTRL = 0x0720 # macro +regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro +regMMVM_L2_PTE_CACHE_DUMP_CNTL = 0x0721 # macro +regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_PTE_CACHE_DUMP_READ = 0x0722 # macro +regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro +regMMVM_L2_BANK_SELECT_MASKS = 0x0725 # macro +regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x0726 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x0727 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x0728 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 # macro +regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x0729 # macro +regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 # macro +regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x072a # macro +regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_CNTL = 0x0740 # macro +regMMVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_CNTL = 0x0741 # macro +regMMVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_CNTL = 0x0742 # macro +regMMVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_CNTL = 0x0743 # macro +regMMVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_CNTL = 0x0744 # macro +regMMVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_CNTL = 0x0745 # macro +regMMVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_CNTL = 0x0746 # macro +regMMVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_CNTL = 0x0747 # macro +regMMVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_CNTL = 0x0748 # macro +regMMVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_CNTL = 0x0749 # macro +regMMVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_CNTL = 0x074a # macro +regMMVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_CNTL = 0x074b # macro +regMMVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_CNTL = 0x074c # macro +regMMVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_CNTL = 0x074d # macro +regMMVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_CNTL = 0x074e # macro +regMMVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_CNTL = 0x074f # macro +regMMVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXTS_DISABLE = 0x0750 # macro +regMMVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_SEM = 0x0751 # macro +regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_SEM = 0x0752 # macro +regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_SEM = 0x0753 # macro +regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_SEM = 0x0754 # macro +regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_SEM = 0x0755 # macro +regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_SEM = 0x0756 # macro +regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_SEM = 0x0757 # macro +regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_SEM = 0x0758 # macro +regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_SEM = 0x0759 # macro +regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_SEM = 0x075a # macro +regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_SEM = 0x075b # macro +regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_SEM = 0x075c # macro +regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_SEM = 0x075d # macro +regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_SEM = 0x075e # macro +regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_SEM = 0x075f # macro +regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_SEM = 0x0760 # macro +regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_SEM = 0x0761 # macro +regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_SEM = 0x0762 # macro +regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_REQ = 0x0763 # macro +regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_REQ = 0x0764 # macro +regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_REQ = 0x0765 # macro +regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_REQ = 0x0766 # macro +regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_REQ = 0x0767 # macro +regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_REQ = 0x0768 # macro +regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_REQ = 0x0769 # macro +regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_REQ = 0x076a # macro +regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_REQ = 0x076b # macro +regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_REQ = 0x076c # macro +regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_REQ = 0x076d # macro +regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_REQ = 0x076e # macro +regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_REQ = 0x076f # macro +regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_REQ = 0x0770 # macro +regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_REQ = 0x0771 # macro +regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_REQ = 0x0772 # macro +regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_REQ = 0x0773 # macro +regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_REQ = 0x0774 # macro +regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_ACK = 0x0775 # macro +regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_ACK = 0x0776 # macro +regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_ACK = 0x0777 # macro +regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_ACK = 0x0778 # macro +regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_ACK = 0x0779 # macro +regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_ACK = 0x077a # macro +regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_ACK = 0x077b # macro +regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_ACK = 0x077c # macro +regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_ACK = 0x077d # macro +regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_ACK = 0x077e # macro +regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_ACK = 0x077f # macro +regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_ACK = 0x0780 # macro +regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_ACK = 0x0781 # macro +regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_ACK = 0x0782 # macro +regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_ACK = 0x0783 # macro +regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_ACK = 0x0784 # macro +regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_ACK = 0x0785 # macro +regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_ACK = 0x0786 # macro +regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x0787 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x0788 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x0789 # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x078a # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x078b # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x078c # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x078d # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x078e # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x078f # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x0790 # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x0791 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x0792 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x0793 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x0794 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x0795 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x0796 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x0797 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x0798 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x0799 # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x079a # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x079b # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x079c # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x079d # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x079e # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x079f # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x07a0 # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x07a1 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x07a2 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x07a3 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x07a4 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x07a5 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x07a6 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x07a7 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x07a8 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x07a9 # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x07aa # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x07ab # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x07ac # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x07ad # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x07ae # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x07af # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x07b0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x07b1 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x07b2 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x07b3 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x07b4 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x07b5 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x07b6 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x07b7 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x07b8 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x07b9 # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x07ba # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x07bb # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x07bc # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x07bd # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x07be # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x07bf # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x07c0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x07c1 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x07c2 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x07c3 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x07c4 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x07c5 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x07c6 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x07c7 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x07c8 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x07c9 # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x07ca # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x07cb # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x07cc # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x07cd # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x07ce # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x07cf # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x07d0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x07d1 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x07d2 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x07d3 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x07d4 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x07d5 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x07d6 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x07d7 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x07d8 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x07d9 # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x07da # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x07db # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x07dc # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x07dd # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x07de # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x07df # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x07e0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x07e1 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x07e2 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x07e3 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x07e4 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x07e5 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x07e6 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x07e7 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x07e8 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x07e9 # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x07ea # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x07eb # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x07ec # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x07ed # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x07ee # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x07ef # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x07f0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x07f1 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x07f2 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x07f3 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x07f4 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x07f5 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x07f6 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x07f7 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x07f8 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x07f9 # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x07fa # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x07fb # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x07fc # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x07fd # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x07fe # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x07ff # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x0800 # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x0801 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x0802 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x0803 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x0804 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x0805 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x0806 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x0807 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x0808 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x0809 # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x080a # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x080b # macro +regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x080c # macro +regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x080d # macro +regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x080e # macro +regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x080f # macro +regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0810 # macro +regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0811 # macro +regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0812 # macro +regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0813 # macro +regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0814 # macro +regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0815 # macro +regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0816 # macro +regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0817 # macro +regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0818 # macro +regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0819 # macro +regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x081a # macro +regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x081b # macro +regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER0_CFG = 0x0824 # macro +regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER1_CFG = 0x0825 # macro +regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER2_CFG = 0x0826 # macro +regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER3_CFG = 0x0827 # macro +regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER4_CFG = 0x0828 # macro +regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER5_CFG = 0x0829 # macro +regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER6_CFG = 0x082a # macro +regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER7_CFG = 0x082b # macro +regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x082c # macro +regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER0_CFG = 0x082d # macro +regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER1_CFG = 0x082e # macro +regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER2_CFG = 0x082f # macro +regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER3_CFG = 0x0830 # macro +regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER_RSLT_CNTL = 0x0831 # macro +regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER_LO = 0x0838 # macro +regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER_HI = 0x0839 # macro +regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER_LO = 0x083a # macro +regMMUTCL2_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER_HI = 0x083b # macro +regMMUTCL2_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF0 = 0x084c # macro +regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF1 = 0x084d # macro +regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF2 = 0x084e # macro +regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF3 = 0x084f # macro +regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF4 = 0x0850 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF5 = 0x0851 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF6 = 0x0852 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF7 = 0x0853 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF8 = 0x0854 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF9 = 0x0855 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF10 = 0x0856 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF11 = 0x0857 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF12 = 0x0858 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF13 = 0x0859 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF14 = 0x085a # macro +regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF15 = 0x085b # macro +regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 0 # macro +regMMMC_VM_FB_OFFSET = 0x08d7 # macro +regMMMC_VM_FB_OFFSET_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x08d8 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x08d9 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro +regMMMC_VM_STEERING = 0x08da # macro +regMMMC_VM_STEERING_BASE_IDX = 0 # macro +regMMMC_MEM_POWER_LS = 0x08dc # macro +regMMMC_MEM_POWER_LS_BASE_IDX = 0 # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x08dd # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x08de # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x08df # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x08e0 # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 # macro +regMMMC_VM_APT_CNTL = 0x08e1 # macro +regMMMC_VM_APT_CNTL_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_START = 0x08e2 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_END = 0x08e3 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x08e4 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_CGTT_CLK_CTRL = 0x08e5 # macro +regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regMMUTCL2_CGTT_BUSY_CTRL = 0x08e7 # macro +regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro +regMMMC_VM_FB_NOALLOC_CNTL = 0x08e8 # macro +regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_HARVEST_BYPASS_GROUPS = 0x08e9 # macro +regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro +regMMUTCL2_GROUP_RET_FAULT_STATUS = 0x08eb # macro +regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_FB_LOCATION_BASE = 0x08ec # macro +regMMMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro +regMMMC_VM_FB_LOCATION_TOP = 0x08ed # macro +regMMMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro +regMMMC_VM_AGP_TOP = 0x08ee # macro +regMMMC_VM_AGP_TOP_BASE_IDX = 0 # macro +regMMMC_VM_AGP_BOT = 0x08ef # macro +regMMMC_VM_AGP_BOT_BASE_IDX = 0 # macro +regMMMC_VM_AGP_BASE = 0x08f0 # macro +regMMMC_VM_AGP_BASE_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x08f1 # macro +regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x08f2 # macro +regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB_CNTL = 0x08f3 # macro +regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro +regMM_ATC_L2_PERFCOUNTER_LO = 0x0900 # macro +regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMM_ATC_L2_PERFCOUNTER_HI = 0x0901 # macro +regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regMM_ATC_L2_PERFCOUNTER0_CFG = 0x0908 # macro +regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMM_ATC_L2_PERFCOUNTER1_CFG = 0x0909 # macro +regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL = 0x090a # macro +regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x0a94 # macro +regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 0 # macro +regMMUTC_TRANSLATION_FAULT_CNTL0 = 0x0a99 # macro +regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 0 # macro +regMMUTC_TRANSLATION_FAULT_CNTL1 = 0x0a9a # macro +regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 0 # macro +regMMUTCL2_FFBM_ENABLE_CNTL = 0x0a9b # macro +regMMUTCL2_FFBM_ENABLE_CNTL_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x0aa0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 0 # macro +regMM_ATC_L2_IOV_MODE_CNTL = 0x0aa4 # macro +regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX = 0 # macro +regMML2TLB_TLB0_STATUS = 0x0ab1 # macro +regMML2TLB_TLB0_STATUS_BASE_IDX = 0 # macro +regMML2TLB_TMZ_CNTL = 0x0ab2 # macro +regMML2TLB_TMZ_CNTL_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x0ab3 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x0ab4 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x0ab5 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x0ab6 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro +regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ = 0x0ab7 # macro +regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro +regMML2TLB_PERFCOUNTER0_CFG = 0x0ac0 # macro +regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMML2TLB_PERFCOUNTER1_CFG = 0x0ac1 # macro +regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMML2TLB_PERFCOUNTER2_CFG = 0x0ac2 # macro +regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regMML2TLB_PERFCOUNTER3_CFG = 0x0ac3 # macro +regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX = 0 # macro +regMML2TLB_PERFCOUNTER_RSLT_CNTL = 0x0ac4 # macro +regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMML2TLB_PERFCOUNTER_LO = 0x0ac8 # macro +regMML2TLB_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMML2TLB_PERFCOUNTER_HI = 0x0ac9 # macro +regMML2TLB_PERFCOUNTER_HI_BASE_IDX = 0 # macro +_mmhub_3_0_0_SH_MASK_HEADER = True # macro +DAGB0_RDCLI0__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI0__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI0__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI0__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI0__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI0__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI0__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI0__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI0__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI0__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI0__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI0__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI0__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI0__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI1__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI1__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI1__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI1__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI1__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI1__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI1__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI1__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI1__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI1__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI1__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI1__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI1__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI1__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI2__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI2__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI2__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI2__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI2__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI2__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI2__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI2__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI2__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI2__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI2__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI2__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI2__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI2__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI3__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI3__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI3__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI3__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI3__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI3__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI3__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI3__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI3__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI3__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI3__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI3__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI3__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI3__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI4__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI4__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI4__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI4__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI4__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI4__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI4__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI4__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI4__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI4__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI4__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI4__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI4__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI4__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI5__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI5__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI5__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI5__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI5__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI5__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI5__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI5__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI5__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI5__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI5__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI5__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI5__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI5__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI6__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI6__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI6__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI6__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI6__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI6__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI6__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI6__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI6__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI6__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI6__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI6__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI6__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI6__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI7__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI7__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI7__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI7__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI7__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI7__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI7__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI7__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI7__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI7__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI7__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI7__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI7__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI7__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI8__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI8__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI8__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI8__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI8__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI8__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI8__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI8__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI8__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI8__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI8__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI8__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI8__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI8__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI9__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI9__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI9__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI9__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI9__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI9__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI9__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI9__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI9__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI9__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI9__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI9__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI9__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI9__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI10__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI10__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI10__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI10__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI10__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI10__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI10__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI10__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI10__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI10__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI10__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI10__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI10__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI10__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI11__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI11__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI11__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI11__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI11__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI11__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI11__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI11__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI11__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI11__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI11__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI11__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI11__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI11__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI12__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI12__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI12__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI12__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI12__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI12__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI12__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI12__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI12__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI12__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI12__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI12__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI12__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI12__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI13__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI13__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI13__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI13__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI13__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI13__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI13__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI13__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI13__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI13__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI13__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI13__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI13__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI13__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI14__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI14__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI14__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI14__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI14__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI14__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI14__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI14__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI14__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI14__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI14__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI14__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI14__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI14__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI15__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI15__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI15__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI15__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI15__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI15__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI15__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI15__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI15__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI15__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI15__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI15__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI15__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI15__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI16__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI16__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI16__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI16__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI16__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI16__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI16__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI16__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI16__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI16__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI16__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI16__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI16__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI16__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI17__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI17__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI17__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI17__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI17__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI17__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI17__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI17__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI17__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI17__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI17__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI17__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI17__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI17__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI18__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI18__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI18__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI18__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI18__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI18__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI18__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI18__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI18__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI18__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI18__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI18__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI18__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI18__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI19__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI19__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI19__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI19__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI19__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI19__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI19__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI19__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI19__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI19__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI19__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI19__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI19__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI19__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI20__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI20__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI20__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI20__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI20__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI20__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI20__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI20__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI20__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI20__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI20__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI20__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI20__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI20__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI21__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI21__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI21__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI21__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI21__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI21__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI21__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI21__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI21__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI21__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI21__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI21__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI21__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI21__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI22__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI22__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI22__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI22__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI22__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI22__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI22__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI22__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI22__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI22__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI22__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI22__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI22__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI22__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI23__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI23__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI23__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI23__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI23__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI23__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI23__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI23__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI23__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI23__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI23__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI23__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI23__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI23__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT = 0x0 # macro +DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT = 0x6 # macro +DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT = 0xc # macro +DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT = 0xf # macro +DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK = 0x0000003F # macro +DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK = 0x00000FC0 # macro +DAGB0_RD_CNTL__SHARE_VC_NUM_MASK = 0x00007000 # macro +DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK = 0x00008000 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT = 0xd # macro +DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB0_RD_ADDR_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK = 0x00002000 # macro +DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC0_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC0_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC0_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC1_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC1_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC1_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC2_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC2_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC2_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC3_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC3_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC3_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC4_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC4_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC4_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC5_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC5_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC5_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT = 0x6 # macro +DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT = 0x9 # macro +DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK = 0x0000003F # macro +DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK = 0x000001C0 # macro +DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK = 0x00000200 # macro +DAGB0_RD_TLB_CREDIT__TLB0__SHIFT = 0x0 # macro +DAGB0_RD_TLB_CREDIT__TLB1__SHIFT = 0x5 # macro +DAGB0_RD_TLB_CREDIT__TLB2__SHIFT = 0xa # macro +DAGB0_RD_TLB_CREDIT__TLB3__SHIFT = 0xf # macro +DAGB0_RD_TLB_CREDIT__TLB4__SHIFT = 0x14 # macro +DAGB0_RD_TLB_CREDIT__TLB5__SHIFT = 0x19 # macro +DAGB0_RD_TLB_CREDIT__TLB0_MASK = 0x0000001F # macro +DAGB0_RD_TLB_CREDIT__TLB1_MASK = 0x000003E0 # macro +DAGB0_RD_TLB_CREDIT__TLB2_MASK = 0x00007C00 # macro +DAGB0_RD_TLB_CREDIT__TLB3_MASK = 0x000F8000 # macro +DAGB0_RD_TLB_CREDIT__TLB4_MASK = 0x01F00000 # macro +DAGB0_RD_TLB_CREDIT__TLB5_MASK = 0x3E000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT = 0xa # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT = 0xf # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT = 0x14 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT = 0x19 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT = 0x1e # macro +DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT = 0x1f # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK = 0x01F00000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK = 0x3E000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK = 0x40000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK = 0x80000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK = 0x0000003F # macro +DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_TLB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_OARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT = 0x0 # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI0__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI0__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI0__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI0__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI0__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI0__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI0__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI0__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI0__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI0__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI0__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI0__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI0__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI0__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI1__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI1__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI1__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI1__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI1__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI1__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI1__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI1__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI1__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI1__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI1__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI1__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI1__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI1__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI2__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI2__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI2__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI2__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI2__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI2__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI2__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI2__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI2__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI2__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI2__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI2__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI2__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI2__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI3__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI3__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI3__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI3__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI3__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI3__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI3__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI3__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI3__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI3__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI3__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI3__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI3__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI3__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI4__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI4__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI4__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI4__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI4__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI4__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI4__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI4__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI4__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI4__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI4__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI4__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI4__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI4__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI5__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI5__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI5__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI5__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI5__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI5__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI5__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI5__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI5__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI5__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI5__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI5__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI5__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI5__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI6__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI6__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI6__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI6__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI6__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI6__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI6__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI6__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI6__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI6__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI6__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI6__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI6__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI6__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI7__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI7__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI7__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI7__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI7__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI7__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI7__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI7__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI7__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI7__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI7__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI7__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI7__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI7__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI8__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI8__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI8__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI8__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI8__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI8__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI8__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI8__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI8__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI8__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI8__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI8__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI8__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI8__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI9__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI9__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI9__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI9__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI9__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI9__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI9__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI9__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI9__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI9__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI9__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI9__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI9__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI9__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI10__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI10__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI10__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI10__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI10__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI10__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI10__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI10__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI10__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI10__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI10__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI10__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI10__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI10__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI11__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI11__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI11__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI11__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI11__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI11__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI11__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI11__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI11__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI11__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI11__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI11__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI11__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI11__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI12__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI12__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI12__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI12__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI12__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI12__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI12__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI12__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI12__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI12__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI12__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI12__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI12__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI12__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI13__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI13__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI13__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI13__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI13__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI13__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI13__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI13__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI13__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI13__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI13__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI13__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI13__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI13__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI14__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI14__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI14__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI14__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI14__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI14__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI14__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI14__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI14__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI14__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI14__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI14__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI14__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI14__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI15__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI15__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI15__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI15__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI15__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI15__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI15__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI15__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI15__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI15__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI15__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI15__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI15__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI15__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI16__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI16__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI16__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI16__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI16__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI16__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI16__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI16__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI16__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI16__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI16__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI16__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI16__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI16__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI17__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI17__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI17__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI17__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI17__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI17__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI17__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI17__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI17__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI17__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI17__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI17__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI17__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI17__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI18__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI18__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI18__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI18__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI18__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI18__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI18__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI18__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI18__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI18__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI18__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI18__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI18__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI18__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI19__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI19__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI19__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI19__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI19__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI19__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI19__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI19__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI19__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI19__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI19__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI19__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI19__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI19__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI20__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI20__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI20__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI20__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI20__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI20__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI20__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI20__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI20__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI20__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI20__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI20__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI20__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI20__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI21__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI21__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI21__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI21__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI21__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI21__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI21__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI21__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI21__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI21__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI21__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI21__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI21__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI21__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI22__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI22__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI22__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI22__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI22__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI22__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI22__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI22__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI22__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI22__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI22__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI22__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI22__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI22__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI23__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI23__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI23__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI23__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI23__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI23__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI23__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI23__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI23__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI23__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI23__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI23__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI23__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI23__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT = 0x0 # macro +DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT = 0x6 # macro +DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT = 0xc # macro +DAGB0_WR_CNTL__UPDATE_FED__SHIFT = 0xd # macro +DAGB0_WR_CNTL__UPDATE_NACK__SHIFT = 0xe # macro +DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK = 0x0000003F # macro +DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK = 0x00000FC0 # macro +DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK = 0x00001000 # macro +DAGB0_WR_CNTL__UPDATE_FED_MASK = 0x00002000 # macro +DAGB0_WR_CNTL__UPDATE_NACK_MASK = 0x00004000 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT = 0xd # macro +DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB0_WR_ADDR_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK = 0x00002000 # macro +DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB0_WR_DATA_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC0_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC0_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC0_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC1_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC1_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC1_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC2_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC2_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC2_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC3_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC3_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC3_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC4_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC4_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC4_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC5_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC5_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC5_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT = 0x6 # macro +DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK = 0x0000003F # macro +DAGB0_WR_CNTL_MISC__HDP_CID_MASK = 0x000007C0 # macro +DAGB0_WR_TLB_CREDIT__TLB0__SHIFT = 0x0 # macro +DAGB0_WR_TLB_CREDIT__TLB1__SHIFT = 0x5 # macro +DAGB0_WR_TLB_CREDIT__TLB2__SHIFT = 0xa # macro +DAGB0_WR_TLB_CREDIT__TLB3__SHIFT = 0xf # macro +DAGB0_WR_TLB_CREDIT__TLB4__SHIFT = 0x14 # macro +DAGB0_WR_TLB_CREDIT__TLB5__SHIFT = 0x19 # macro +DAGB0_WR_TLB_CREDIT__TLB0_MASK = 0x0000001F # macro +DAGB0_WR_TLB_CREDIT__TLB1_MASK = 0x000003E0 # macro +DAGB0_WR_TLB_CREDIT__TLB2_MASK = 0x00007C00 # macro +DAGB0_WR_TLB_CREDIT__TLB3_MASK = 0x000F8000 # macro +DAGB0_WR_TLB_CREDIT__TLB4_MASK = 0x01F00000 # macro +DAGB0_WR_TLB_CREDIT__TLB5_MASK = 0x3E000000 # macro +DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT = 0x0 # macro +DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT = 0x8 # macro +DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT = 0x10 # macro +DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT = 0x18 # macro +DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK = 0x000000FF # macro +DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK = 0x0000FF00 # macro +DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK = 0x00FF0000 # macro +DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK = 0xFF000000 # macro +DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT = 0x6 # macro +DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK = 0x0000003F # macro +DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK = 0x000001C0 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT = 0xa # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT = 0xf # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT = 0x14 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT = 0x19 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT = 0x1a # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT = 0x1b # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK = 0x01F00000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK = 0x02000000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK = 0x04000000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK = 0x08000000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT = 0xa # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT = 0xf # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT = 0x14 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT = 0x1a # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT = 0x1b # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT = 0x1c # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK = 0x03F00000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK = 0x04000000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK = 0x08000000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK = 0x10000000 # macro +DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_TLB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_OARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT = 0x0 # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT = 0x0 # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +DAGB0_DAGB_DLY__DLY__SHIFT = 0x0 # macro +DAGB0_DAGB_DLY__CLI__SHIFT = 0x8 # macro +DAGB0_DAGB_DLY__POS__SHIFT = 0x10 # macro +DAGB0_DAGB_DLY__DLY_MASK = 0x000000FF # macro +DAGB0_DAGB_DLY__CLI_MASK = 0x0000FF00 # macro +DAGB0_DAGB_DLY__POS_MASK = 0x000F0000 # macro +DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT = 0x0 # macro +DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK = 0x0000003F # macro +DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT = 0x0 # macro +DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT = 0x1 # macro +DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT = 0x2 # macro +DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT = 0x3 # macro +DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT = 0x4 # macro +DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT = 0x5 # macro +DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT = 0x6 # macro +DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT = 0x7 # macro +DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT = 0x8 # macro +DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT = 0x9 # macro +DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT = 0xa # macro +DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT = 0xb # macro +DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK = 0x00000001 # macro +DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK = 0x00000002 # macro +DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK = 0x00000004 # macro +DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK = 0x00000008 # macro +DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK = 0x00000010 # macro +DAGB0_CNTL_MISC2__SWAP_CTL_MASK = 0x00000020 # macro +DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK = 0x00000040 # macro +DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK = 0x00000080 # macro +DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK = 0x00000100 # macro +DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK = 0x00000200 # macro +DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK = 0x00000400 # macro +DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK = 0x00000800 # macro +DAGB0_FIFO_EMPTY__EMPTY__SHIFT = 0x0 # macro +DAGB0_FIFO_EMPTY__EMPTY_MASK = 0x0001FFFF # macro +DAGB0_FIFO_FULL__FULL__SHIFT = 0x0 # macro +DAGB0_FIFO_FULL__FULL_MASK = 0x0000FFFF # macro +DAGB0_RD_CREDITS_FULL__FULL__SHIFT = 0x0 # macro +DAGB0_RD_CREDITS_FULL__FULL_MASK = 0x0000007F # macro +DAGB0_WR_CREDITS_FULL__FULL__SHIFT = 0x0 # macro +DAGB0_WR_CREDITS_FULL__FULL_MASK = 0x0001FFFF # macro +DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x00000003 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT = 0x0 # macro +DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT = 0x1 # macro +DAGB0_L1TLB_REG_RW__RESERVE__SHIFT = 0x2 # macro +DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK = 0x00000001 # macro +DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK = 0x00000002 # macro +DAGB0_L1TLB_REG_RW__RESERVE_MASK = 0x3FFFFFFC # macro +DAGB0_RESERVE1__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE1__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_RESERVE2__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE2__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_RESERVE3__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE3__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_RESERVE4__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE4__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT = 0x1 # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT = 0x9 # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT = 0xa # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT = 0xd # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK = 0x000001FE # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK = 0x00000200 # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK = 0x00001C00 # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK = 0x0007E000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT = 0x0 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT = 0x9 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT = 0xa # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT = 0xb # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT = 0xc # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT = 0xd # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT = 0xe # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT = 0x10 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT = 0x14 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT = 0x19 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT = 0x1a # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT = 0x1b # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT = 0x1c # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT = 0x1d # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT = 0x1e # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK = 0x0000000F # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK = 0x00000200 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK = 0x00000400 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK = 0x00000800 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK = 0x00001000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK = 0x00002000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK = 0x00004000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK = 0x000F0000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK = 0x01F00000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK = 0x02000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK = 0x04000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK = 0x08000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK = 0x10000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK = 0x20000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK = 0x40000000 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT = 0x0 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT = 0x4 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT = 0x8 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT = 0xc # macro +DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT = 0x10 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT = 0x14 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK = 0x0000000F # macro +DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK = 0x000000F0 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK = 0x00000F00 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK = 0x0000F000 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK = 0x000F0000 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK = 0x00F00000 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT = 0x0 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT = 0x4 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT = 0x8 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT = 0xc # macro +DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT = 0x10 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT = 0x14 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK = 0x0000000F # macro +DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK = 0x000000F0 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK = 0x00000F00 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK = 0x0000F000 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK = 0x000F0000 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK = 0x00F00000 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT = 0x0 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT = 0x3 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT = 0x6 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT = 0x9 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT = 0xc # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT = 0xf # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK = 0x00000007 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK = 0x00000038 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK = 0x000001C0 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK = 0x00000E00 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK = 0x00007000 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK = 0x00038000 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT = 0x0 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT = 0x3 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT = 0x6 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT = 0x9 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT = 0xc # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT = 0xf # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK = 0x00000007 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK = 0x00000038 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK = 0x000001C0 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK = 0x00000E00 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK = 0x00007000 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK = 0x00038000 # macro +DAGB0_SDP_ENABLE__ENABLE__SHIFT = 0x0 # macro +DAGB0_SDP_ENABLE__ENABLE_MASK = 0x00000001 # macro +DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT = 0x0 # macro +DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT = 0x8 # macro +DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT = 0x10 # macro +DAGB0_SDP_CREDITS__TAG_LIMIT_MASK = 0x000000FF # macro +DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK = 0x00007F00 # macro +DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK = 0x01FF0000 # macro +DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT = 0x0 # macro +DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT = 0x8 # macro +DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT = 0x10 # macro +DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT = 0x18 # macro +DAGB0_SDP_TAG_RESERVE0__VC0_MASK = 0x000000FF # macro +DAGB0_SDP_TAG_RESERVE0__VC1_MASK = 0x0000FF00 # macro +DAGB0_SDP_TAG_RESERVE0__VC2_MASK = 0x00FF0000 # macro +DAGB0_SDP_TAG_RESERVE0__VC3_MASK = 0xFF000000 # macro +DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT = 0x0 # macro +DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT = 0x8 # macro +DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT = 0x10 # macro +DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT = 0x18 # macro +DAGB0_SDP_TAG_RESERVE1__VC4_MASK = 0x000000FF # macro +DAGB0_SDP_TAG_RESERVE1__VC5_MASK = 0x0000FF00 # macro +DAGB0_SDP_TAG_RESERVE1__VC6_MASK = 0x00FF0000 # macro +DAGB0_SDP_TAG_RESERVE1__VC7_MASK = 0xFF000000 # macro +DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT = 0x0 # macro +DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT = 0x4 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xb # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xc # macro +DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT = 0xd # macro +DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT = 0xe # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT = 0xf # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT = 0x10 # macro +DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT = 0x11 # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT = 0x12 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK = 0x0000000F # macro +DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK = 0x000000F0 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00000800 # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00001000 # macro +DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK = 0x00002000 # macro +DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK = 0x00004000 # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK = 0x00008000 # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK = 0x00010000 # macro +DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK = 0x00020000 # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK = 0x00040000 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT = 0x0 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT = 0x1 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT = 0x2 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT = 0x3 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT = 0x4 # macro +DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT = 0x5 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT = 0x6 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT = 0x8 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT = 0xa # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK = 0x00000001 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK = 0x00000002 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK = 0x00000004 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK = 0x00000008 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK = 0x00000010 # macro +DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK = 0x00000020 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK = 0x000000C0 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK = 0x00000300 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK = 0x00000C00 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT = 0x0 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT = 0x1 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT = 0x2 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT = 0x3 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT = 0x4 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT = 0x5 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT = 0x6 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT = 0x7 # macro +DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT = 0x8 # macro +DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT = 0x9 # macro +DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT = 0xb # macro +DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT = 0xd # macro +DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT = 0xf # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT = 0x14 # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT = 0x15 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK = 0x00000001 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK = 0x00000002 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK = 0x00000004 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK = 0x00000008 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK = 0x00000010 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK = 0x00000020 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK = 0x00000040 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK = 0x00000080 # macro +DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK = 0x00000100 # macro +DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK = 0x00000600 # macro +DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK = 0x00001800 # macro +DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK = 0x00006000 # macro +DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK = 0x000F8000 # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK = 0x00100000 # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK = 0x00200000 # macro +DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT = 0x0 # macro +DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT = 0x1 # macro +DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT = 0x2 # macro +DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT = 0x3 # macro +DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK = 0x00000001 # macro +DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK = 0x00000002 # macro +DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK = 0x00000004 # macro +DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK = 0x00000008 # macro +DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x12 # macro +DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK = 0x00040000 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT = 0x0 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT = 0x1 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT = 0x2 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT = 0x3 # macro +DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT = 0x4 # macro +DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT = 0x5 # macro +DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT = 0x6 # macro +DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT = 0x7 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK = 0x00000001 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK = 0x00000002 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK = 0x00000004 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK = 0x00000008 # macro +DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK = 0x00000010 # macro +DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK = 0x00000020 # macro +DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK = 0x00000040 # macro +DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK = 0x00000080 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT = 0x0 # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT = 0x8 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT = 0x10 # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT = 0x18 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK = 0x0000007F # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK = 0x00007F00 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK = 0x007F0000 # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK = 0x7F000000 # macro +DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK = 0x000003FF # macro +DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK = 0x00000001 # macro +DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT = 0x1 # macro +DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT = 0x6 # macro +DAGB0_FATAL_ERROR_STATUS0__VALID_MASK = 0x00000001 # macro +DAGB0_FATAL_ERROR_STATUS0__CID_MASK = 0x0000003E # macro +DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK = 0xFFFFFFC0 # macro +DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK = 0x0001FFFF # macro +DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT = 0x10 # macro +DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT = 0x18 # macro +DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT = 0x1c # macro +DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT = 0x1d # macro +DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT = 0x1e # macro +DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT = 0x1f # macro +DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK = 0x0000FFFF # macro +DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK = 0x00FF0000 # macro +DAGB0_FATAL_ERROR_STATUS2__VFID_MASK = 0x0F000000 # macro +DAGB0_FATAL_ERROR_STATUS2__VF_MASK = 0x10000000 # macro +DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK = 0x20000000 # macro +DAGB0_FATAL_ERROR_STATUS2__IO_MASK = 0x40000000 # macro +DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK = 0x80000000 # macro +DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT = 0x6 # macro +DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT = 0x10 # macro +DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT = 0x11 # macro +DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT = 0x12 # macro +DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT = 0x13 # macro +DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT = 0x14 # macro +DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT = 0x16 # macro +DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT = 0x17 # macro +DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT = 0x18 # macro +DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT = 0x19 # macro +DAGB0_FATAL_ERROR_STATUS3__OP_MASK = 0x00001FC0 # macro +DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK = 0x00010000 # macro +DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK = 0x00020000 # macro +DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK = 0x00040000 # macro +DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK = 0x00080000 # macro +DAGB0_FATAL_ERROR_STATUS3__NACK_MASK = 0x00300000 # macro +DAGB0_FATAL_ERROR_STATUS3__RO_MASK = 0x00400000 # macro +DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK = 0x00800000 # macro +DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK = 0x01000000 # macro +DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK = 0x02000000 # macro +DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT = 0x4 # macro +DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT = 0x5 # macro +DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT = 0x6 # macro +DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT = 0x7 # macro +DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT = 0x8 # macro +DAGB0_FATAL_ERROR_STATUS4__PRI_MASK = 0x0000000F # macro +DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK = 0x00000010 # macro +DAGB0_FATAL_ERROR_STATUS4__FULL_MASK = 0x00000020 # macro +DAGB0_FATAL_ERROR_STATUS4__DROP_MASK = 0x00000040 # macro +DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK = 0x00000080 # macro +DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK = 0x00000100 # macro +DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT = 0x0 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT = 0x1 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT = 0x2 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT = 0x3 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT = 0x4 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT = 0x5 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT = 0x6 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT = 0x7 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT = 0x8 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT = 0x9 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT = 0xa # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT = 0xb # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT = 0xc # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT = 0xd # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT = 0xe # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT = 0x16 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK = 0x00000001 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK = 0x00000002 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK = 0x00000004 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK = 0x00000008 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK = 0x00000010 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK = 0x00000020 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK = 0x00000040 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK = 0x00000080 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK = 0x00000100 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK = 0x00000200 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK = 0x00000400 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK = 0x00000800 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK = 0x00001000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK = 0x00002000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK = 0x003FC000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK = 0x3FC00000 # macro +DAGB1_RDCLI0__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI0__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI0__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI0__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI0__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI0__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI0__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI0__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI0__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI0__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI0__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI0__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI0__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI0__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI1__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI1__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI1__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI1__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI1__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI1__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI1__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI1__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI1__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI1__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI1__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI1__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI1__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI1__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI2__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI2__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI2__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI2__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI2__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI2__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI2__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI2__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI2__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI2__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI2__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI2__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI2__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI2__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI3__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI3__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI3__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI3__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI3__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI3__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI3__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI3__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI3__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI3__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI3__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI3__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI3__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI3__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI4__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI4__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI4__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI4__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI4__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI4__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI4__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI4__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI4__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI4__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI4__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI4__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI4__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI4__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI5__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI5__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI5__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI5__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI5__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI5__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI5__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI5__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI5__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI5__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI5__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI5__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI5__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI5__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI6__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI6__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI6__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI6__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI6__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI6__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI6__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI6__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI6__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI6__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI6__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI6__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI6__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI6__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI7__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI7__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI7__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI7__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI7__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI7__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI7__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI7__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI7__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI7__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI7__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI7__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI7__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI7__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI8__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI8__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI8__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI8__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI8__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI8__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI8__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI8__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI8__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI8__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI8__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI8__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI8__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI8__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI9__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI9__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI9__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI9__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI9__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI9__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI9__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI9__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI9__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI9__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI9__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI9__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI9__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI9__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI10__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI10__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI10__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI10__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI10__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI10__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI10__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI10__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI10__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI10__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI10__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI10__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI10__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI10__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI11__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI11__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI11__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI11__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI11__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI11__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI11__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI11__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI11__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI11__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI11__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI11__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI11__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI11__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI12__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI12__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI12__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI12__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI12__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI12__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI12__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI12__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI12__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI12__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI12__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI12__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI12__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI12__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI13__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI13__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI13__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI13__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI13__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI13__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI13__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI13__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI13__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI13__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI13__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI13__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI13__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI13__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI14__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI14__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI14__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI14__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI14__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI14__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI14__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI14__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI14__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI14__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI14__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI14__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI14__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI14__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI15__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI15__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI15__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI15__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI15__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI15__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI15__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI15__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI15__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI15__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI15__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI15__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI15__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI15__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI16__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI16__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI16__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI16__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI16__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI16__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI16__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI16__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI16__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI16__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI16__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI16__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI16__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI16__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI17__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI17__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI17__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI17__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI17__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI17__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI17__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI17__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI17__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI17__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI17__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI17__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI17__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI17__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI18__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI18__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI18__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI18__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI18__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI18__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI18__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI18__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI18__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI18__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI18__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI18__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI18__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI18__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI19__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI19__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI19__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI19__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI19__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI19__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI19__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI19__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI19__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI19__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI19__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI19__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI19__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI19__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI20__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI20__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI20__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI20__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI20__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI20__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI20__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI20__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI20__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI20__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI20__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI20__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI20__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI20__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI21__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI21__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI21__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI21__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI21__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI21__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI21__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI21__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI21__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI21__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI21__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI21__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI21__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI21__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI22__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI22__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI22__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI22__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI22__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI22__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI22__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI22__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI22__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI22__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI22__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI22__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI22__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI22__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI23__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI23__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI23__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI23__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI23__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI23__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI23__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI23__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI23__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI23__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI23__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI23__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI23__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI23__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT = 0x0 # macro +DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT = 0x6 # macro +DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT = 0xc # macro +DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT = 0xf # macro +DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK = 0x0000003F # macro +DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK = 0x00000FC0 # macro +DAGB1_RD_CNTL__SHARE_VC_NUM_MASK = 0x00007000 # macro +DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK = 0x00008000 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT = 0xd # macro +DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB1_RD_ADDR_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK = 0x00002000 # macro +DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC0_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC0_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC0_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC1_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC1_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC1_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC2_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC2_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC2_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC3_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC3_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC3_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC4_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC4_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC4_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC5_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC5_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC5_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT = 0x6 # macro +DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT = 0x9 # macro +DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK = 0x0000003F # macro +DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK = 0x000001C0 # macro +DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK = 0x00000200 # macro +DAGB1_RD_TLB_CREDIT__TLB0__SHIFT = 0x0 # macro +DAGB1_RD_TLB_CREDIT__TLB1__SHIFT = 0x5 # macro +DAGB1_RD_TLB_CREDIT__TLB2__SHIFT = 0xa # macro +DAGB1_RD_TLB_CREDIT__TLB3__SHIFT = 0xf # macro +DAGB1_RD_TLB_CREDIT__TLB4__SHIFT = 0x14 # macro +DAGB1_RD_TLB_CREDIT__TLB5__SHIFT = 0x19 # macro +DAGB1_RD_TLB_CREDIT__TLB0_MASK = 0x0000001F # macro +DAGB1_RD_TLB_CREDIT__TLB1_MASK = 0x000003E0 # macro +DAGB1_RD_TLB_CREDIT__TLB2_MASK = 0x00007C00 # macro +DAGB1_RD_TLB_CREDIT__TLB3_MASK = 0x000F8000 # macro +DAGB1_RD_TLB_CREDIT__TLB4_MASK = 0x01F00000 # macro +DAGB1_RD_TLB_CREDIT__TLB5_MASK = 0x3E000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT = 0xa # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT = 0xf # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT = 0x14 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT = 0x19 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT = 0x1e # macro +DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT = 0x1f # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK = 0x01F00000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK = 0x3E000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK = 0x40000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK = 0x80000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK = 0x0000003F # macro +DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_TLB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_OARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT = 0x0 # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +DAGB1_DAGB_DLY__DLY__SHIFT = 0x0 # macro +DAGB1_DAGB_DLY__CLI__SHIFT = 0x8 # macro +DAGB1_DAGB_DLY__POS__SHIFT = 0x10 # macro +DAGB1_DAGB_DLY__DLY_MASK = 0x000000FF # macro +DAGB1_DAGB_DLY__CLI_MASK = 0x0000FF00 # macro +DAGB1_DAGB_DLY__POS_MASK = 0x000F0000 # macro +DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT = 0x0 # macro +DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK = 0x0000003F # macro +DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT = 0x0 # macro +DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT = 0x1 # macro +DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT = 0x2 # macro +DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT = 0x3 # macro +DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT = 0x4 # macro +DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT = 0x5 # macro +DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT = 0x6 # macro +DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT = 0x7 # macro +DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT = 0x8 # macro +DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT = 0x9 # macro +DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT = 0xa # macro +DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT = 0xb # macro +DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK = 0x00000001 # macro +DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK = 0x00000002 # macro +DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK = 0x00000004 # macro +DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK = 0x00000008 # macro +DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK = 0x00000010 # macro +DAGB1_CNTL_MISC2__SWAP_CTL_MASK = 0x00000020 # macro +DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK = 0x00000040 # macro +DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK = 0x00000080 # macro +DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK = 0x00000100 # macro +DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK = 0x00000200 # macro +DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK = 0x00000400 # macro +DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK = 0x00000800 # macro +DAGB1_FIFO_EMPTY__EMPTY__SHIFT = 0x0 # macro +DAGB1_FIFO_EMPTY__EMPTY_MASK = 0x0000007F # macro +DAGB1_FIFO_FULL__FULL__SHIFT = 0x0 # macro +DAGB1_FIFO_FULL__FULL_MASK = 0x0000007F # macro +DAGB1_RD_CREDITS_FULL__FULL__SHIFT = 0x0 # macro +DAGB1_RD_CREDITS_FULL__FULL_MASK = 0x0000007F # macro +DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x00000003 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT = 0x0 # macro +DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT = 0x1 # macro +DAGB1_L1TLB_REG_RW__RESERVE__SHIFT = 0x2 # macro +DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK = 0x00000001 # macro +DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK = 0x00000002 # macro +DAGB1_L1TLB_REG_RW__RESERVE_MASK = 0x3FFFFFFC # macro +DAGB1_RESERVE1__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE1__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_RESERVE2__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE2__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_RESERVE3__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE3__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_RESERVE4__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE4__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT = 0x1 # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT = 0x9 # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT = 0xa # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT = 0xd # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK = 0x000001FE # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK = 0x00000200 # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK = 0x00001C00 # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK = 0x0007E000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT = 0x0 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT = 0x9 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT = 0xa # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT = 0xb # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT = 0xc # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT = 0xd # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT = 0xe # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT = 0x10 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT = 0x14 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT = 0x19 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT = 0x1a # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT = 0x1b # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT = 0x1c # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT = 0x1d # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT = 0x1e # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK = 0x0000000F # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK = 0x00000200 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK = 0x00000400 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK = 0x00000800 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK = 0x00001000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK = 0x00002000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK = 0x00004000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK = 0x000F0000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK = 0x01F00000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK = 0x02000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK = 0x04000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK = 0x08000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK = 0x10000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK = 0x20000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK = 0x40000000 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT = 0x0 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT = 0x4 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT = 0x8 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT = 0xc # macro +DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT = 0x10 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT = 0x14 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK = 0x0000000F # macro +DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK = 0x000000F0 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK = 0x00000F00 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK = 0x0000F000 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK = 0x000F0000 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK = 0x00F00000 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT = 0x0 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT = 0x3 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT = 0x6 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT = 0x9 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT = 0xc # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT = 0xf # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK = 0x00000007 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK = 0x00000038 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK = 0x000001C0 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK = 0x00000E00 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK = 0x00007000 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK = 0x00038000 # macro +DAGB1_SDP_ENABLE__ENABLE__SHIFT = 0x0 # macro +DAGB1_SDP_ENABLE__ENABLE_MASK = 0x00000001 # macro +DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT = 0x0 # macro +DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT = 0x8 # macro +DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT = 0x10 # macro +DAGB1_SDP_CREDITS__TAG_LIMIT_MASK = 0x000000FF # macro +DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK = 0x00007F00 # macro +DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK = 0x01FF0000 # macro +DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT = 0x0 # macro +DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT = 0x8 # macro +DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT = 0x10 # macro +DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT = 0x18 # macro +DAGB1_SDP_TAG_RESERVE0__VC0_MASK = 0x000000FF # macro +DAGB1_SDP_TAG_RESERVE0__VC1_MASK = 0x0000FF00 # macro +DAGB1_SDP_TAG_RESERVE0__VC2_MASK = 0x00FF0000 # macro +DAGB1_SDP_TAG_RESERVE0__VC3_MASK = 0xFF000000 # macro +DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT = 0x0 # macro +DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT = 0x8 # macro +DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT = 0x10 # macro +DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT = 0x18 # macro +DAGB1_SDP_TAG_RESERVE1__VC4_MASK = 0x000000FF # macro +DAGB1_SDP_TAG_RESERVE1__VC5_MASK = 0x0000FF00 # macro +DAGB1_SDP_TAG_RESERVE1__VC6_MASK = 0x00FF0000 # macro +DAGB1_SDP_TAG_RESERVE1__VC7_MASK = 0xFF000000 # macro +DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT = 0x0 # macro +DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT = 0x4 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xb # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xc # macro +DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT = 0xd # macro +DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT = 0xe # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT = 0xf # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT = 0x10 # macro +DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT = 0x11 # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT = 0x12 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK = 0x0000000F # macro +DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK = 0x000000F0 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00000800 # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00001000 # macro +DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK = 0x00002000 # macro +DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK = 0x00004000 # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK = 0x00008000 # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK = 0x00010000 # macro +DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK = 0x00020000 # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK = 0x00040000 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT = 0x0 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT = 0x1 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT = 0x2 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT = 0x3 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT = 0x4 # macro +DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT = 0x5 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT = 0x6 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT = 0x8 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT = 0xa # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK = 0x00000001 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK = 0x00000002 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK = 0x00000004 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK = 0x00000008 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK = 0x00000010 # macro +DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK = 0x00000020 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK = 0x000000C0 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK = 0x00000300 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK = 0x00000C00 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT = 0x0 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT = 0x1 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT = 0x2 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT = 0x3 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT = 0x4 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT = 0x5 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT = 0x6 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT = 0x7 # macro +DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT = 0x8 # macro +DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT = 0x9 # macro +DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT = 0xb # macro +DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT = 0xd # macro +DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT = 0xf # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT = 0x14 # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT = 0x15 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK = 0x00000001 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK = 0x00000002 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK = 0x00000004 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK = 0x00000008 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK = 0x00000010 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK = 0x00000020 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK = 0x00000040 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK = 0x00000080 # macro +DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK = 0x00000100 # macro +DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK = 0x00000600 # macro +DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK = 0x00001800 # macro +DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK = 0x00006000 # macro +DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK = 0x000F8000 # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK = 0x00100000 # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK = 0x00200000 # macro +DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT = 0x0 # macro +DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT = 0x1 # macro +DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT = 0x2 # macro +DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT = 0x3 # macro +DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK = 0x00000001 # macro +DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK = 0x00000002 # macro +DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK = 0x00000004 # macro +DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK = 0x00000008 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT = 0x0 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT = 0x1 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT = 0x2 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT = 0x3 # macro +DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT = 0x4 # macro +DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT = 0x5 # macro +DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT = 0x6 # macro +DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT = 0x7 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK = 0x00000001 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK = 0x00000002 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK = 0x00000004 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK = 0x00000008 # macro +DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK = 0x00000010 # macro +DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK = 0x00000020 # macro +DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK = 0x00000040 # macro +DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK = 0x00000080 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT = 0x0 # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT = 0x8 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT = 0x10 # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT = 0x18 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK = 0x0000007F # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK = 0x00007F00 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK = 0x007F0000 # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK = 0x7F000000 # macro +DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT = 0x0 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT = 0x1 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT = 0x2 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT = 0x3 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT = 0x4 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT = 0x5 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT = 0x6 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT = 0x7 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT = 0x8 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT = 0x9 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT = 0xa # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT = 0xb # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT = 0xc # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT = 0xd # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT = 0xe # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT = 0x16 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK = 0x00000001 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK = 0x00000002 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK = 0x00000004 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK = 0x00000008 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK = 0x00000010 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK = 0x00000020 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK = 0x00000040 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK = 0x00000080 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK = 0x00000100 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK = 0x00000200 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK = 0x00000400 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK = 0x00000800 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK = 0x00001000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK = 0x00002000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK = 0x003FC000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK = 0x3FC00000 # macro +PCTL_CTRL__PG_ENABLE__SHIFT = 0x0 # macro +PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT = 0x1 # macro +PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT = 0xe # macro +PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT = 0x13 # macro +PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT = 0x14 # macro +PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT = 0x15 # macro +PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT = 0x16 # macro +PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT = 0x1b # macro +PCTL_CTRL__Z9_PWRDOWN__SHIFT = 0x1c # macro +PCTL_CTRL__Z9_PWRUP__SHIFT = 0x1d # macro +PCTL_CTRL__SNR_DISABLE__SHIFT = 0x1e # macro +PCTL_CTRL__WRACK_GUARD__SHIFT = 0x1f # macro +PCTL_CTRL__PG_ENABLE_MASK = 0x00000001 # macro +PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK = 0x0000000E # macro +PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK = 0x0007C000 # macro +PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK = 0x00080000 # macro +PCTL_CTRL__UTCL2_LEGACY_MODE_MASK = 0x00100000 # macro +PCTL_CTRL__SDP_DISCONNECT_MODE_MASK = 0x00200000 # macro +PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK = 0x07C00000 # macro +PCTL_CTRL__ZSC_TIMER_ENABLE_MASK = 0x08000000 # macro +PCTL_CTRL__Z9_PWRDOWN_MASK = 0x10000000 # macro +PCTL_CTRL__Z9_PWRUP_MASK = 0x20000000 # macro +PCTL_CTRL__SNR_DISABLE_MASK = 0x40000000 # macro +PCTL_CTRL__WRACK_GUARD_MASK = 0x80000000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT = 0x0 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT = 0x1 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT = 0x2 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT = 0x3 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT = 0x4 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT = 0x5 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT = 0x6 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT = 0x7 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT = 0x8 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT = 0x9 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT = 0xa # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT = 0xb # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT = 0xc # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT = 0xd # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT = 0xe # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT = 0xf # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT = 0x10 # macro +PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT = 0x1f # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK = 0x00000001 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK = 0x00000002 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK = 0x00000004 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK = 0x00000008 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK = 0x00000010 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK = 0x00000020 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK = 0x00000040 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK = 0x00000080 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK = 0x00000100 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK = 0x00000200 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK = 0x00000400 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK = 0x00000800 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK = 0x00001000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK = 0x00002000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK = 0x00004000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK = 0x00008000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK = 0x00010000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK = 0x80000000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT = 0x0 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT = 0x1 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT = 0x2 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT = 0x3 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT = 0x4 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT = 0x5 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT = 0x6 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT = 0x7 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT = 0x8 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT = 0x9 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT = 0xa # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT = 0xb # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT = 0xc # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT = 0xd # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT = 0xe # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT = 0xf # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT = 0x10 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT = 0x11 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK = 0x00000001 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK = 0x00000002 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK = 0x00000004 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK = 0x00000008 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK = 0x00000010 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK = 0x00000020 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK = 0x00000040 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK = 0x00000080 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK = 0x00000100 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK = 0x00000200 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK = 0x00000400 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK = 0x00000800 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK = 0x00001000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK = 0x00002000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK = 0x00004000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK = 0x00008000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK = 0x00010000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK = 0x00020000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT = 0x0 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT = 0x1 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT = 0x2 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT = 0x3 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT = 0x4 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT = 0x5 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT = 0x6 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT = 0x7 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT = 0x8 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT = 0x9 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT = 0xa # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT = 0xb # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT = 0xc # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT = 0xd # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT = 0xe # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT = 0xf # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT = 0x10 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK = 0x00000001 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK = 0x00000002 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK = 0x00000004 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK = 0x00000008 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK = 0x00000010 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK = 0x00000020 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK = 0x00000040 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK = 0x00000080 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK = 0x00000100 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK = 0x00000200 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK = 0x00000400 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK = 0x00000800 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK = 0x00001000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK = 0x00002000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK = 0x00004000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK = 0x00008000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK = 0x00010000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT = 0x0 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT = 0x1 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT = 0x2 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT = 0x3 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT = 0x4 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT = 0x5 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT = 0x6 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT = 0x7 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT = 0x8 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT = 0x9 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT = 0xa # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT = 0xb # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT = 0xc # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT = 0xd # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT = 0xe # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT = 0xf # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT = 0x10 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT = 0x11 # macro +PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT = 0x12 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK = 0x00000001 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK = 0x00000002 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK = 0x00000004 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK = 0x00000008 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK = 0x00000010 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK = 0x00000020 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK = 0x00000040 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK = 0x00000080 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK = 0x00000100 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK = 0x00000200 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK = 0x00000400 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK = 0x00000800 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK = 0x00001000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK = 0x00002000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK = 0x00004000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK = 0x00008000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK = 0x00010000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK = 0x00020000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK = 0x00040000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT = 0x0 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT = 0x1 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT = 0x2 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT = 0x3 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT = 0x4 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT = 0x5 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT = 0x6 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT = 0x7 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT = 0x8 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT = 0x9 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT = 0xa # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT = 0xb # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT = 0xc # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT = 0xd # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT = 0xe # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT = 0xf # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT = 0x10 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT = 0x11 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK = 0x00000001 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK = 0x00000002 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK = 0x00000004 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK = 0x00000008 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK = 0x00000010 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK = 0x00000020 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK = 0x00000040 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK = 0x00000080 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK = 0x00000100 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK = 0x00000200 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK = 0x00000400 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK = 0x00000800 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK = 0x00001000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK = 0x00002000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK = 0x00004000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK = 0x00008000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK = 0x00010000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK = 0x00020000 # macro +PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT = 0x1 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT = 0x2 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT = 0x3 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT = 0x4 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT = 0x5 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT = 0x6 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT = 0x7 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT = 0x8 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT = 0x9 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT = 0xa # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT = 0xb # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT = 0xc # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT = 0xd # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT = 0xe # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT = 0xf # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT = 0x10 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK = 0x00000001 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK = 0x00000002 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK = 0x00000004 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK = 0x00000008 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK = 0x00000010 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK = 0x00000020 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK = 0x00000040 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK = 0x00000080 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK = 0x00000100 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK = 0x00000200 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK = 0x00000400 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK = 0x00000800 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK = 0x00001000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK = 0x00002000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK = 0x00004000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK = 0x00008000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK = 0x00010000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT = 0x1 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT = 0x2 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT = 0x3 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT = 0x4 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT = 0x5 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT = 0x6 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT = 0x7 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT = 0x8 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT = 0x9 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT = 0xa # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT = 0xb # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT = 0xc # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT = 0xd # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT = 0xe # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT = 0xf # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT = 0x10 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK = 0x00000001 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK = 0x00000002 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK = 0x00000004 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK = 0x00000008 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK = 0x00000010 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK = 0x00000020 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK = 0x00000040 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK = 0x00000080 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK = 0x00000100 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK = 0x00000200 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK = 0x00000400 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK = 0x00000800 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK = 0x00001000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK = 0x00002000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK = 0x00004000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK = 0x00008000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK = 0x00010000 # macro +PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT = 0x1 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT = 0x2 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT = 0x3 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT = 0x4 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT = 0x5 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT = 0x6 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT = 0x7 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT = 0x8 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT = 0x9 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT = 0xa # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT = 0xb # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT = 0xc # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT = 0xd # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT = 0xe # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT = 0xf # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT = 0x10 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK = 0x00000001 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK = 0x00000002 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK = 0x00000004 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK = 0x00000008 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK = 0x00000010 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK = 0x00000020 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK = 0x00000040 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK = 0x00000080 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK = 0x00000100 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK = 0x00000200 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK = 0x00000400 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK = 0x00000800 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK = 0x00001000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK = 0x00002000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK = 0x00004000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK = 0x00008000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK = 0x00010000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT = 0x1 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT = 0x2 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT = 0x3 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT = 0x4 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT = 0x5 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT = 0x6 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT = 0x7 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT = 0x8 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT = 0x9 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT = 0xa # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT = 0xb # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT = 0xc # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT = 0xd # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT = 0xe # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT = 0xf # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT = 0x10 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK = 0x00000001 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK = 0x00000002 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK = 0x00000004 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK = 0x00000008 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK = 0x00000010 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK = 0x00000020 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK = 0x00000040 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK = 0x00000080 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK = 0x00000100 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK = 0x00000200 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK = 0x00000400 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK = 0x00000800 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK = 0x00001000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK = 0x00002000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK = 0x00004000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK = 0x00008000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK = 0x00010000 # macro +PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT = 0xb # macro +PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT = 0xc # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT = 0xf # macro +PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT = 0x10 # macro +PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT = 0x11 # macro +PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT = 0x12 # macro +PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT = 0x13 # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT = 0x14 # macro +PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT = 0x1a # macro +PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK = 0x00000800 # macro +PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK = 0x00007000 # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK = 0x00008000 # macro +PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK = 0x00010000 # macro +PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK = 0x00020000 # macro +PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK = 0x00040000 # macro +PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK = 0x00080000 # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK = 0x03F00000 # macro +PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK = 0x3C000000 # macro +PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT = 0xa # macro +PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT = 0xb # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT = 0xe # macro +PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT = 0xf # macro +PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT = 0x10 # macro +PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT = 0x11 # macro +PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT = 0x12 # macro +PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT = 0x13 # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT = 0x14 # macro +PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT = 0x1a # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT = 0x1e # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT = 0x1f # macro +PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK = 0x00000400 # macro +PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK = 0x00003800 # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK = 0x00004000 # macro +PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK = 0x00008000 # macro +PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK = 0x00010000 # macro +PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK = 0x00020000 # macro +PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK = 0x00040000 # macro +PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK = 0x00080000 # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK = 0x03F00000 # macro +PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK = 0x3C000000 # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK = 0x40000000 # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK = 0x80000000 # macro +PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT = 0xa # macro +PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT = 0xb # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT = 0xe # macro +PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT = 0xf # macro +PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT = 0x10 # macro +PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT = 0x11 # macro +PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT = 0x12 # macro +PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT = 0x13 # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT = 0x14 # macro +PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT = 0x1a # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT = 0x1e # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT = 0x1f # macro +PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK = 0x00000400 # macro +PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK = 0x00003800 # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK = 0x00004000 # macro +PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK = 0x00008000 # macro +PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK = 0x00010000 # macro +PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK = 0x00020000 # macro +PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK = 0x00040000 # macro +PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK = 0x00080000 # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK = 0x03F00000 # macro +PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK = 0x3C000000 # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK = 0x40000000 # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK = 0x80000000 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT = 0x2 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT = 0xd # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK = 0x00001FFC # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK = 0x00FFE000 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT = 0x2 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT = 0xc # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK = 0x00000FFC # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK = 0x003FF000 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT = 0x2 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT = 0xc # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK = 0x00000FFC # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK = 0x003FF000 # macro +PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT = 0x0 # macro +PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK = 0x000007FF # macro +PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT = 0x0 # macro +PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK = 0xFFFFFFFF # macro +PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT = 0x0 # macro +PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK = 0x000003FF # macro +PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT = 0x0 # macro +PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK = 0xFFFFFFFF # macro +PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT = 0x0 # macro +PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK = 0x000003FF # macro +PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT = 0x0 # macro +PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK = 0xFFFFFFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK = 0xFFFF0000 # macro +PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT = 0x0 # macro +PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT = 0x1 # macro +PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT = 0x2 # macro +PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT = 0x3 # macro +PCTL_STATUS__MMHUB_IDLE__SHIFT = 0x4 # macro +PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT = 0x5 # macro +PCTL_STATUS__MMHUB_POWER__SHIFT = 0x10 # macro +PCTL_STATUS__RENG_RAM_STALE__SHIFT = 0x11 # macro +PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT = 0x12 # macro +PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT = 0x13 # macro +PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT = 0x14 # macro +PCTL_STATUS__MMHUB_CONFIG_DONE_MASK = 0x00000001 # macro +PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK = 0x00000002 # macro +PCTL_STATUS__MMHUB_FENCE_REQ_MASK = 0x00000004 # macro +PCTL_STATUS__MMHUB_FENCE_ACK_MASK = 0x00000008 # macro +PCTL_STATUS__MMHUB_IDLE_MASK = 0x00000010 # macro +PCTL_STATUS__PGFSM_CMD_STATUS_MASK = 0x00000060 # macro +PCTL_STATUS__MMHUB_POWER_MASK = 0x00010000 # macro +PCTL_STATUS__RENG_RAM_STALE_MASK = 0x00020000 # macro +PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK = 0x00040000 # macro +PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK = 0x00080000 # macro +PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK = 0x00100000 # macro +PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +PCTL_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +PCTL_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +PCTL_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +PCTL_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +PCTL_RESERVED_0__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_0__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_0__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_0__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_0__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_0__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_0__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_0__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_0__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_0__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_0__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_0__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_0__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_0__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_0__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_0__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_0__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_0__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_0__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_0__BIT0_MASK = 0x80000000 # macro +PCTL_RESERVED_1__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_1__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_1__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_1__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_1__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_1__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_1__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_1__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_1__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_1__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_1__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_1__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_1__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_1__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_1__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_1__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_1__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_1__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_1__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_1__BIT0_MASK = 0x80000000 # macro +PCTL_RESERVED_2__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_2__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_2__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_2__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_2__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_2__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_2__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_2__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_2__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_2__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_2__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_2__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_2__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_2__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_2__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_2__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_2__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_2__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_2__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_2__BIT0_MASK = 0x80000000 # macro +PCTL_RESERVED_3__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_3__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_3__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_3__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_3__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_3__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_3__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_3__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_3__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_3__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_3__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_3__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_3__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_3__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_3__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_3__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_3__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_3__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_3__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_3__BIT0_MASK = 0x80000000 # macro +MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT = 0x2 # macro +MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK = 0x00000004 # macro +MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT = 0x2 # macro +MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK = 0x00000004 # macro +MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT = 0x2 # macro +MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK = 0x00000004 # macro +MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT = 0x2 # macro +MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK = 0x00000004 # macro +MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT = 0x2 # macro +MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK = 0x00000004 # macro +MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT = 0x2 # macro +MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK = 0x00000004 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT = 0x0 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT = 0x3 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT = 0x6 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT = 0x7 # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT = 0x8 # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT = 0xb # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT = 0xe # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT = 0xf # macro +MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT = 0x10 # macro +MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT = 0x13 # macro +MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT = 0x14 # macro +MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT = 0x16 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK = 0x00000003 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK = 0x00000018 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK = 0x00000040 # macro +MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK = 0x00000080 # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK = 0x00000300 # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK = 0x00001800 # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK = 0x00004000 # macro +MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK = 0x00008000 # macro +MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK = 0x00070000 # macro +MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK = 0x00080000 # macro +MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK = 0x00300000 # macro +MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK = 0x0FC00000 # macro +MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT = 0x0 # macro +MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT = 0x6 # macro +MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT = 0x9 # macro +MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0xb # macro +MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT = 0xc # macro +MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT = 0xf # macro +MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT = 0x12 # macro +MM_ATC_L2_CNTL2__BANK_SELECT_MASK = 0x0000003F # macro +MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK = 0x000001C0 # macro +MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK = 0x00000600 # macro +MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000800 # macro +MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK = 0x00007000 # macro +MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK = 0x00038000 # macro +MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK = 0x00FC0000 # macro +MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT = 0x0 # macro +MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT = 0x1 # macro +MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT = 0x2 # macro +MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT = 0x18 # macro +MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK = 0x00000001 # macro +MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK = 0x00000002 # macro +MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK = 0x00FFFFFC # macro +MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK = 0x0F000000 # macro +MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT = 0x0 # macro +MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK = 0xFFFFFFFF # macro +MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT = 0x0 # macro +MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK = 0xFFFFFFFF # macro +MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT = 0x6 # macro +MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT = 0xc # macro +MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT = 0x12 # macro +MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT = 0x15 # macro +MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT = 0x1b # macro +MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT = 0x1e # macro +MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK = 0x0000003F # macro +MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK = 0x00000FC0 # macro +MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK = 0x0003F000 # macro +MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK = 0x001C0000 # macro +MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK = 0x07E00000 # macro +MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK = 0x38000000 # macro +MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK = 0x40000000 # macro +MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT = 0x6 # macro +MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT = 0xc # macro +MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK = 0x0000003F # macro +MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK = 0x00000FC0 # macro +MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK = 0x0003F000 # macro +MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x0 # macro +MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0xa # macro +MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x000003FF # macro +MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x000FFC00 # macro +MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT = 0x0 # macro +MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK = 0xFFFFFFFF # macro +MM_ATC_L2_STATUS__BUSY__SHIFT = 0x0 # macro +MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT = 0x1 # macro +MM_ATC_L2_STATUS__BUSY_MASK = 0x00000001 # macro +MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK = 0x00000002 # macro +MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT = 0x0 # macro +MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT = 0x8 # macro +MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK = 0x000000FF # macro +MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK = 0x0000FF00 # macro +MM_ATC_L2_MISC_CG__OFFDLY__SHIFT = 0x6 # macro +MM_ATC_L2_MISC_CG__ENABLE__SHIFT = 0x12 # macro +MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT = 0x13 # macro +MM_ATC_L2_MISC_CG__OFFDLY_MASK = 0x00000FC0 # macro +MM_ATC_L2_MISC_CG__ENABLE_MASK = 0x00040000 # macro +MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK = 0x00080000 # macro +MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT = 0x0 # macro +MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT = 0x6 # macro +MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK = 0x0000003F # macro +MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK = 0x00000FC0 # macro +MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT = 0x0 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT = 0x1 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT = 0x2 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT = 0x3 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT = 0x4 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT = 0x5 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT = 0x6 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT = 0x7 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT = 0x8 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT = 0x9 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK = 0x00000001 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK = 0x00000002 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK = 0x00000004 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK = 0x00000008 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK = 0x00000010 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK = 0x00000020 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK = 0x00000040 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK = 0x00000080 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK = 0x00000100 # macro +MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK = 0x00000200 # macro +MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE__SHIFT = 0x0 # macro +MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE_MASK = 0x0000001F # macro +MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST__SHIFT = 0x0 # macro +MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT__SHIFT = 0x1 # macro +MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST_MASK = 0x00000001 # macro +MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT_MASK = 0x00000002 # macro +MMUTCL2_FFBM_ADDRESS__VFID__SHIFT = 0x0 # macro +MMUTCL2_FFBM_ADDRESS__ADDRESS__SHIFT = 0x4 # macro +MMUTCL2_FFBM_ADDRESS__VFID_MASK = 0x0000000F # macro +MMUTCL2_FFBM_ADDRESS__ADDRESS_MASK = 0x07FFFFF0 # macro +MMUTCL2_FFBM_DATA__VALID__SHIFT = 0x0 # macro +MMUTCL2_FFBM_DATA__READ_PERMISSION__SHIFT = 0x1 # macro +MMUTCL2_FFBM_DATA__WRITE_PERMISSION__SHIFT = 0x2 # macro +MMUTCL2_FFBM_DATA__FRAGMENT__SHIFT = 0x3 # macro +MMUTCL2_FFBM_DATA__FB_SPA__SHIFT = 0x8 # macro +MMUTCL2_FFBM_DATA__VALID_MASK = 0x00000001 # macro +MMUTCL2_FFBM_DATA__READ_PERMISSION_MASK = 0x00000002 # macro +MMUTCL2_FFBM_DATA__WRITE_PERMISSION_MASK = 0x00000004 # macro +MMUTCL2_FFBM_DATA__FRAGMENT_MASK = 0x000000F8 # macro +MMUTCL2_FFBM_DATA__FB_SPA_MASK = 0x7FFFFF00 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ__SHIFT = 0x0 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID__SHIFT = 0x1 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE__SHIFT = 0x6 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE__SHIFT = 0x7 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS__SHIFT = 0x8 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ_MASK = 0x00000001 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID_MASK = 0x0000001E # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE_MASK = 0x00000040 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE_MASK = 0x00000080 # macro +MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS_MASK = 0x7FFFFF00 # macro +MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK__SHIFT = 0x1 # macro +MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK_MASK = 0x00000001 # macro +MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK_MASK = 0x00000002 # macro +MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT = 0x0 # macro +MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT = 0x1 # macro +MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT = 0x2 # macro +MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT = 0x4 # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT = 0x8 # macro +MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0x9 # macro +MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0xa # macro +MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT = 0xb # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT = 0xc # macro +MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT = 0xf # macro +MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT = 0x12 # macro +MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT = 0x13 # macro +MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT = 0x15 # macro +MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT = 0x1a # macro +MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK = 0x00000001 # macro +MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK = 0x00000002 # macro +MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK = 0x0000000C # macro +MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK = 0x00000030 # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK = 0x00000100 # macro +MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000200 # macro +MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000400 # macro +MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK = 0x00000800 # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK = 0x00007000 # macro +MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK = 0x00038000 # macro +MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK = 0x00040000 # macro +MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK = 0x00180000 # macro +MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK = 0x03E00000 # macro +MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK = 0x0C000000 # macro +MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT = 0x0 # macro +MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT = 0x1 # macro +MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT = 0x15 # macro +MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT = 0x16 # macro +MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT = 0x17 # macro +MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT = 0x1a # macro +MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT = 0x1c # macro +MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK = 0x00000001 # macro +MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK = 0x00000002 # macro +MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK = 0x00200000 # macro +MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK = 0x00400000 # macro +MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK = 0x03800000 # macro +MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK = 0x0C000000 # macro +MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK = 0x70000000 # macro +MMVM_L2_CNTL3__BANK_SELECT__SHIFT = 0x0 # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT = 0x6 # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT = 0x8 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0xf # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT = 0x14 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT = 0x15 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT = 0x18 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT = 0x1c # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT = 0x1d # macro +MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT = 0x1e # macro +MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT = 0x1f # macro +MMVM_L2_CNTL3__BANK_SELECT_MASK = 0x0000003F # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK = 0x000000C0 # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK = 0x00001F00 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000F8000 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK = 0x00100000 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK = 0x00E00000 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK = 0x0F000000 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK = 0x10000000 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK = 0x20000000 # macro +MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK = 0x40000000 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK = 0x80000000 # macro +MMVM_L2_STATUS__L2_BUSY__SHIFT = 0x0 # macro +MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT = 0x1 # macro +MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x11 # macro +MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x12 # macro +MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT = 0x13 # macro +MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT = 0x14 # macro +MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT = 0x15 # macro +MMVM_L2_STATUS__L2_BUSY_MASK = 0x00000001 # macro +MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK = 0x0001FFFE # macro +MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK = 0x00020000 # macro +MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK = 0x00040000 # macro +MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK = 0x00080000 # macro +MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK = 0x00100000 # macro +MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK = 0x00200000 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT = 0x0 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT = 0x1 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT = 0x2 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK = 0x00000001 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK = 0x00000002 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK = 0x000000FC # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT = 0x0 # macro +MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT = 0x8 # macro +MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK = 0x000000FF # macro +MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK = 0x0000FF00 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT = 0x1 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x2 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x3 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x4 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x5 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x6 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x7 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x8 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x9 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xb # macro +MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0xd # macro +MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x1d # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT = 0x1e # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT = 0x1f # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00000001 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK = 0x00000002 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000004 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000008 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000010 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000020 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000040 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000080 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000100 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000200 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000800 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x1FFFE000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x20000000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK = 0x40000000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK = 0x80000000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x10 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT = 0x11 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT = 0x12 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT = 0x13 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x0000FFFF # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x00010000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK = 0x00020000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK = 0x00040000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK = 0x00080000 # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT = 0x1 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT = 0x4 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT = 0x8 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT = 0x9 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT = 0x12 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT = 0x13 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT = 0x14 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT = 0x18 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT = 0x19 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT = 0x1d # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK = 0x00000001 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK = 0x0000000E # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK = 0x000000F0 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK = 0x00000100 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK = 0x0003FE00 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK = 0x00040000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK = 0x00080000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK = 0x00F00000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK = 0x01000000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK = 0x1E000000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK = 0x20000000 # macro +MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK = 0x0000000F # macro +MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT = 0x0 # macro +MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT = 0x6 # macro +MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT = 0x7 # macro +MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x8 # macro +MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x12 # macro +MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT = 0x1c # macro +MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT = 0x1d # macro +MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT = 0x1e # macro +MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT = 0x1f # macro +MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK = 0x0000003F # macro +MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK = 0x00000040 # macro +MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK = 0x00000080 # macro +MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0003FF00 # macro +MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0FFC0000 # macro +MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK = 0x10000000 # macro +MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK = 0x20000000 # macro +MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK = 0x40000000 # macro +MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK = 0x80000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT = 0x0 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT = 0x1 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT = 0x2 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT = 0x3 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT = 0x4 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT = 0x5 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT = 0x6 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT = 0x7 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT = 0x8 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT = 0x9 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT = 0xa # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT = 0xb # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT = 0xc # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT = 0xd # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT = 0xe # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT = 0xf # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT = 0x10 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT = 0x11 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT = 0x12 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT = 0x13 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT = 0x14 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT = 0x15 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT = 0x16 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT = 0x17 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT = 0x18 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT = 0x19 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT = 0x1a # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT = 0x1b # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT = 0x1c # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT = 0x1d # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT = 0x1e # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT = 0x1f # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK = 0x00000001 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK = 0x00000002 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK = 0x00000004 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK = 0x00000008 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK = 0x00000010 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK = 0x00000020 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK = 0x00000040 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK = 0x00000080 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK = 0x00000100 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK = 0x00000200 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK = 0x00000400 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK = 0x00000800 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK = 0x00001000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK = 0x00002000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK = 0x00004000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK = 0x00008000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK = 0x00010000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK = 0x00020000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK = 0x00040000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK = 0x00080000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK = 0x00100000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK = 0x00200000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK = 0x00400000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK = 0x00800000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK = 0x01000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK = 0x02000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK = 0x04000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK = 0x08000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK = 0x10000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK = 0x20000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK = 0x40000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK = 0x80000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT = 0x14 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT = 0x1a # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK = 0x00100000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK = 0x7C000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT = 0x14 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT = 0x1a # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK = 0x00100000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK = 0x7C000000 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT = 0x0 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT = 0x1 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT = 0x2 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT = 0x3 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT = 0x4 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT = 0x5 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT = 0x6 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT = 0x9 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT = 0xc # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK = 0x00000001 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK = 0x00000002 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK = 0x00000004 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK = 0x00000008 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK = 0x00000010 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK = 0x00000020 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK = 0x000001C0 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK = 0x00000E00 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK = 0x0000F000 # macro +MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT = 0x5 # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT = 0xe # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT = 0xf # macro +MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT = 0x10 # macro +MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT = 0x11 # macro +MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK = 0x00003FE0 # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK = 0x00004000 # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK = 0x00008000 # macro +MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK = 0x00010000 # macro +MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK = 0x00020000 # macro +MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT = 0x0 # macro +MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT = 0x1 # macro +MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK = 0x00000001 # macro +MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK = 0x000003FE # macro +MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT = 0x0 # macro +MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT = 0x5 # macro +MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK = 0x0000001F # macro +MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK = 0x00000020 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT = 0x0 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT = 0x1 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT = 0x4 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT = 0x8 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT = 0xc # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT = 0x10 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK = 0x00000001 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK = 0x00000002 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK = 0x000000F0 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK = 0x00000F00 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK = 0x0000F000 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK = 0xFFFF0000 # macro +MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT = 0x0 # macro +MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK = 0xFFFFFFFF # macro +MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT = 0x0 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT = 0x4 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT = 0x8 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT = 0xc # macro +MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK = 0x0000000F # macro +MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK = 0x000000F0 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK = 0x00000F00 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK = 0x0000F000 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT = 0x0 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT = 0xa # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK = 0x000003FF # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK = 0x00000400 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT = 0x0 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT = 0xa # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK = 0x000003FF # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK = 0x00000400 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT = 0x0 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT = 0xa # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK = 0x000003FF # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK = 0x00000400 # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT = 0x0 # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT = 0xa # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK = 0x000003FF # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK = 0x00000400 # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT = 0x0 # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT = 0xa # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK = 0x000003FF # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK = 0x00000400 # macro +MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT = 0x0 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT = 0x1 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT = 0x2 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT = 0x3 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT = 0x4 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT = 0x5 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT = 0x6 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT = 0x7 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT = 0x8 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT = 0x9 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT = 0xa # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT = 0xb # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT = 0xc # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT = 0xd # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT = 0xe # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT = 0xf # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK = 0x00000001 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK = 0x00000002 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK = 0x00000004 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK = 0x00000008 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK = 0x00000010 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK = 0x00000020 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK = 0x00000040 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK = 0x00000080 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK = 0x00000100 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK = 0x00000200 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK = 0x00000400 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK = 0x00000800 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK = 0x00001000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK = 0x00002000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK = 0x00004000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK = 0x00008000 # macro +MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT = 0x0 # macro +MMMC_VM_FB_OFFSET__FB_OFFSET_MASK = 0x00FFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK = 0xFFFFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK = 0x0000000F # macro +MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT = 0x0 # macro +MMMC_VM_STEERING__DEFAULT_STEERING_MASK = 0x00000003 # macro +MMMC_MEM_POWER_LS__LS_SETUP__SHIFT = 0x0 # macro +MMMC_MEM_POWER_LS__LS_HOLD__SHIFT = 0x6 # macro +MMMC_MEM_POWER_LS__LS_SETUP_MASK = 0x0000003F # macro +MMMC_MEM_POWER_LS__LS_HOLD_MASK = 0x00000FC0 # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT = 0x0 # macro +MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT = 0x1 # macro +MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT = 0x2 # macro +MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT = 0x4 # macro +MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT = 0x5 # macro +MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT = 0x6 # macro +MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK = 0x00000001 # macro +MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK = 0x00000002 # macro +MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK = 0x0000000C # macro +MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK = 0x00000010 # macro +MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK = 0x00000020 # macro +MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK = 0x000000C0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK = 0x00000001 # macro +MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT = 0x0 # macro +MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT = 0x5 # macro +MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK = 0x0000001F # macro +MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK = 0x00000020 # macro +MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT = 0x0 # macro +MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT = 0x1 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT = 0x2 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT = 0x3 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT = 0x4 # macro +MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK = 0x00000001 # macro +MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK = 0x00000002 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK = 0x00000004 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK = 0x00000008 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK = 0x00000010 # macro +MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT = 0x0 # macro +MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK = 0xFFFFFFFF # macro +MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT = 0x0 # macro +MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK = 0xFFFFFFFF # macro +MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT = 0x0 # macro +MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK = 0x00FFFFFF # macro +MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT = 0x0 # macro +MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK = 0x00FFFFFF # macro +MMMC_VM_AGP_TOP__AGP_TOP__SHIFT = 0x0 # macro +MMMC_VM_AGP_TOP__AGP_TOP_MASK = 0x00FFFFFF # macro +MMMC_VM_AGP_BOT__AGP_BOT__SHIFT = 0x0 # macro +MMMC_VM_AGP_BOT__AGP_BOT_MASK = 0x00FFFFFF # macro +MMMC_VM_AGP_BASE__AGP_BASE__SHIFT = 0x0 # macro +MMMC_VM_AGP_BASE__AGP_BASE_MASK = 0x00FFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT = 0x3 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT = 0x5 # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT = 0x6 # macro +MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT = 0x7 # macro +MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT = 0xb # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK = 0x00000018 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK = 0x00000020 # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK = 0x00000040 # macro +MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK = 0x00000780 # macro +MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK = 0x00003800 # macro +MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT = 0x0 # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT = 0x10 # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK = 0x0000FFFF # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK = 0xFFFF0000 # macro +MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT = 0x0 # macro +MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK = 0xFFFFFFFF # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT = 0x0 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT = 0x4 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT = 0x5 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT = 0x6 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK = 0x0000000F # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK = 0x00000010 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK = 0x00000020 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK = 0x00000040 # macro +MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM__SHIFT = 0x0 # macro +MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM_MASK = 0x00000001 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK = 0x00000001 # macro +MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT = 0x0 # macro +MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK = 0x00000001 # macro +MML2TLB_TLB0_STATUS__BUSY__SHIFT = 0x0 # macro +MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT = 0x2 # macro +MML2TLB_TLB0_STATUS__BUSY_MASK = 0x00000001 # macro +MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK = 0x00000004 # macro +MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT = 0x0 # macro +MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK = 0x00000001 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK = 0xFFFFFFFF # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT = 0x4 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT = 0x8 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT = 0xc # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT = 0xd # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT = 0xf # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT = 0x10 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT = 0x11 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT = 0x12 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT = 0x1e # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK = 0x0000000F # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK = 0x000000F0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK = 0x00000F00 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK = 0x00001000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK = 0x00006000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK = 0x00008000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK = 0x00010000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK = 0x00020000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK = 0x07FC0000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK = 0x40000000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK = 0xFFFFFFFF # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT = 0x4 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT = 0x7 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT = 0xd # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT = 0xe # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT = 0xf # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT = 0x10 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT = 0x11 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT = 0x12 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT = 0x15 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT = 0x16 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT = 0x18 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT = 0x1f # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK = 0x0000000F # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK = 0x00000070 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK = 0x00001F80 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK = 0x00002000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK = 0x00004000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK = 0x00008000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK = 0x00010000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK = 0x00020000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK = 0x001C0000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK = 0x00200000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK = 0x00C00000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK = 0x01000000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK = 0x80000000 # macro +MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT = 0x0 # macro +MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT = 0xa # macro +MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK = 0x000003FF # macro +MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK = 0x00000400 # macro +MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +__all__ = \ + ['DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK', + 'DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK', + 'DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK', + 'DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT', + 'DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK', + 'DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT', + 'DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK', + 'DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT', + 'DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__SWAP_CTL_MASK', + 'DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT', + 'DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK', + 'DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT', + 'DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK', + 'DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT', + 'DAGB0_DAGB_DLY__CLI_MASK', 'DAGB0_DAGB_DLY__CLI__SHIFT', + 'DAGB0_DAGB_DLY__DLY_MASK', 'DAGB0_DAGB_DLY__DLY__SHIFT', + 'DAGB0_DAGB_DLY__POS_MASK', 'DAGB0_DAGB_DLY__POS__SHIFT', + 'DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK', + 'DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT', + 'DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK', + 'DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK', + 'DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS0__CID_MASK', + 'DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS0__VALID_MASK', + 'DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK', + 'DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__IO_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__VFID_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__VF_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__NACK_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__OP_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__RO_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__DROP_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__FULL_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__PRI_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT', + 'DAGB0_FIFO_EMPTY__EMPTY_MASK', 'DAGB0_FIFO_EMPTY__EMPTY__SHIFT', + 'DAGB0_FIFO_FULL__FULL_MASK', 'DAGB0_FIFO_FULL__FULL__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK', + 'DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT', + 'DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK', + 'DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT', + 'DAGB0_L1TLB_REG_RW__RESERVE_MASK', + 'DAGB0_L1TLB_REG_RW__RESERVE__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK', + 'DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK', + 'DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK', + 'DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK', + 'DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK', + 'DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK', + 'DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI0__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI0__MAX_BW_MASK', + 'DAGB0_RDCLI0__MAX_BW__SHIFT', 'DAGB0_RDCLI0__MAX_OSD_MASK', + 'DAGB0_RDCLI0__MAX_OSD__SHIFT', + 'DAGB0_RDCLI0__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI0__MIN_BW_MASK', + 'DAGB0_RDCLI0__MIN_BW__SHIFT', + 'DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI0__URG_HIGH_MASK', 'DAGB0_RDCLI0__URG_HIGH__SHIFT', + 'DAGB0_RDCLI0__URG_LOW_MASK', 'DAGB0_RDCLI0__URG_LOW__SHIFT', + 'DAGB0_RDCLI0__VIRT_CHAN_MASK', 'DAGB0_RDCLI0__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI10__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI10__MAX_BW_MASK', 'DAGB0_RDCLI10__MAX_BW__SHIFT', + 'DAGB0_RDCLI10__MAX_OSD_MASK', 'DAGB0_RDCLI10__MAX_OSD__SHIFT', + 'DAGB0_RDCLI10__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI10__MIN_BW_MASK', 'DAGB0_RDCLI10__MIN_BW__SHIFT', + 'DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI10__URG_HIGH_MASK', 'DAGB0_RDCLI10__URG_HIGH__SHIFT', + 'DAGB0_RDCLI10__URG_LOW_MASK', 'DAGB0_RDCLI10__URG_LOW__SHIFT', + 'DAGB0_RDCLI10__VIRT_CHAN_MASK', + 'DAGB0_RDCLI10__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI11__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI11__MAX_BW_MASK', 'DAGB0_RDCLI11__MAX_BW__SHIFT', + 'DAGB0_RDCLI11__MAX_OSD_MASK', 'DAGB0_RDCLI11__MAX_OSD__SHIFT', + 'DAGB0_RDCLI11__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI11__MIN_BW_MASK', 'DAGB0_RDCLI11__MIN_BW__SHIFT', + 'DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI11__URG_HIGH_MASK', 'DAGB0_RDCLI11__URG_HIGH__SHIFT', + 'DAGB0_RDCLI11__URG_LOW_MASK', 'DAGB0_RDCLI11__URG_LOW__SHIFT', + 'DAGB0_RDCLI11__VIRT_CHAN_MASK', + 'DAGB0_RDCLI11__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI12__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI12__MAX_BW_MASK', 'DAGB0_RDCLI12__MAX_BW__SHIFT', + 'DAGB0_RDCLI12__MAX_OSD_MASK', 'DAGB0_RDCLI12__MAX_OSD__SHIFT', + 'DAGB0_RDCLI12__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI12__MIN_BW_MASK', 'DAGB0_RDCLI12__MIN_BW__SHIFT', + 'DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI12__URG_HIGH_MASK', 'DAGB0_RDCLI12__URG_HIGH__SHIFT', + 'DAGB0_RDCLI12__URG_LOW_MASK', 'DAGB0_RDCLI12__URG_LOW__SHIFT', + 'DAGB0_RDCLI12__VIRT_CHAN_MASK', + 'DAGB0_RDCLI12__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI13__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI13__MAX_BW_MASK', 'DAGB0_RDCLI13__MAX_BW__SHIFT', + 'DAGB0_RDCLI13__MAX_OSD_MASK', 'DAGB0_RDCLI13__MAX_OSD__SHIFT', + 'DAGB0_RDCLI13__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI13__MIN_BW_MASK', 'DAGB0_RDCLI13__MIN_BW__SHIFT', + 'DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI13__URG_HIGH_MASK', 'DAGB0_RDCLI13__URG_HIGH__SHIFT', + 'DAGB0_RDCLI13__URG_LOW_MASK', 'DAGB0_RDCLI13__URG_LOW__SHIFT', + 'DAGB0_RDCLI13__VIRT_CHAN_MASK', + 'DAGB0_RDCLI13__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI14__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI14__MAX_BW_MASK', 'DAGB0_RDCLI14__MAX_BW__SHIFT', + 'DAGB0_RDCLI14__MAX_OSD_MASK', 'DAGB0_RDCLI14__MAX_OSD__SHIFT', + 'DAGB0_RDCLI14__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI14__MIN_BW_MASK', 'DAGB0_RDCLI14__MIN_BW__SHIFT', + 'DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI14__URG_HIGH_MASK', 'DAGB0_RDCLI14__URG_HIGH__SHIFT', + 'DAGB0_RDCLI14__URG_LOW_MASK', 'DAGB0_RDCLI14__URG_LOW__SHIFT', + 'DAGB0_RDCLI14__VIRT_CHAN_MASK', + 'DAGB0_RDCLI14__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI15__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI15__MAX_BW_MASK', 'DAGB0_RDCLI15__MAX_BW__SHIFT', + 'DAGB0_RDCLI15__MAX_OSD_MASK', 'DAGB0_RDCLI15__MAX_OSD__SHIFT', + 'DAGB0_RDCLI15__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI15__MIN_BW_MASK', 'DAGB0_RDCLI15__MIN_BW__SHIFT', + 'DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI15__URG_HIGH_MASK', 'DAGB0_RDCLI15__URG_HIGH__SHIFT', + 'DAGB0_RDCLI15__URG_LOW_MASK', 'DAGB0_RDCLI15__URG_LOW__SHIFT', + 'DAGB0_RDCLI15__VIRT_CHAN_MASK', + 'DAGB0_RDCLI15__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI16__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI16__MAX_BW_MASK', 'DAGB0_RDCLI16__MAX_BW__SHIFT', + 'DAGB0_RDCLI16__MAX_OSD_MASK', 'DAGB0_RDCLI16__MAX_OSD__SHIFT', + 'DAGB0_RDCLI16__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI16__MIN_BW_MASK', 'DAGB0_RDCLI16__MIN_BW__SHIFT', + 'DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI16__URG_HIGH_MASK', 'DAGB0_RDCLI16__URG_HIGH__SHIFT', + 'DAGB0_RDCLI16__URG_LOW_MASK', 'DAGB0_RDCLI16__URG_LOW__SHIFT', + 'DAGB0_RDCLI16__VIRT_CHAN_MASK', + 'DAGB0_RDCLI16__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI17__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI17__MAX_BW_MASK', 'DAGB0_RDCLI17__MAX_BW__SHIFT', + 'DAGB0_RDCLI17__MAX_OSD_MASK', 'DAGB0_RDCLI17__MAX_OSD__SHIFT', + 'DAGB0_RDCLI17__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI17__MIN_BW_MASK', 'DAGB0_RDCLI17__MIN_BW__SHIFT', + 'DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI17__URG_HIGH_MASK', 'DAGB0_RDCLI17__URG_HIGH__SHIFT', + 'DAGB0_RDCLI17__URG_LOW_MASK', 'DAGB0_RDCLI17__URG_LOW__SHIFT', + 'DAGB0_RDCLI17__VIRT_CHAN_MASK', + 'DAGB0_RDCLI17__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI18__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI18__MAX_BW_MASK', 'DAGB0_RDCLI18__MAX_BW__SHIFT', + 'DAGB0_RDCLI18__MAX_OSD_MASK', 'DAGB0_RDCLI18__MAX_OSD__SHIFT', + 'DAGB0_RDCLI18__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI18__MIN_BW_MASK', 'DAGB0_RDCLI18__MIN_BW__SHIFT', + 'DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI18__URG_HIGH_MASK', 'DAGB0_RDCLI18__URG_HIGH__SHIFT', + 'DAGB0_RDCLI18__URG_LOW_MASK', 'DAGB0_RDCLI18__URG_LOW__SHIFT', + 'DAGB0_RDCLI18__VIRT_CHAN_MASK', + 'DAGB0_RDCLI18__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI19__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI19__MAX_BW_MASK', 'DAGB0_RDCLI19__MAX_BW__SHIFT', + 'DAGB0_RDCLI19__MAX_OSD_MASK', 'DAGB0_RDCLI19__MAX_OSD__SHIFT', + 'DAGB0_RDCLI19__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI19__MIN_BW_MASK', 'DAGB0_RDCLI19__MIN_BW__SHIFT', + 'DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI19__URG_HIGH_MASK', 'DAGB0_RDCLI19__URG_HIGH__SHIFT', + 'DAGB0_RDCLI19__URG_LOW_MASK', 'DAGB0_RDCLI19__URG_LOW__SHIFT', + 'DAGB0_RDCLI19__VIRT_CHAN_MASK', + 'DAGB0_RDCLI19__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI1__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI1__MAX_BW_MASK', + 'DAGB0_RDCLI1__MAX_BW__SHIFT', 'DAGB0_RDCLI1__MAX_OSD_MASK', + 'DAGB0_RDCLI1__MAX_OSD__SHIFT', + 'DAGB0_RDCLI1__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI1__MIN_BW_MASK', + 'DAGB0_RDCLI1__MIN_BW__SHIFT', + 'DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI1__URG_HIGH_MASK', 'DAGB0_RDCLI1__URG_HIGH__SHIFT', + 'DAGB0_RDCLI1__URG_LOW_MASK', 'DAGB0_RDCLI1__URG_LOW__SHIFT', + 'DAGB0_RDCLI1__VIRT_CHAN_MASK', 'DAGB0_RDCLI1__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI20__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI20__MAX_BW_MASK', 'DAGB0_RDCLI20__MAX_BW__SHIFT', + 'DAGB0_RDCLI20__MAX_OSD_MASK', 'DAGB0_RDCLI20__MAX_OSD__SHIFT', + 'DAGB0_RDCLI20__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI20__MIN_BW_MASK', 'DAGB0_RDCLI20__MIN_BW__SHIFT', + 'DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI20__URG_HIGH_MASK', 'DAGB0_RDCLI20__URG_HIGH__SHIFT', + 'DAGB0_RDCLI20__URG_LOW_MASK', 'DAGB0_RDCLI20__URG_LOW__SHIFT', + 'DAGB0_RDCLI20__VIRT_CHAN_MASK', + 'DAGB0_RDCLI20__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI21__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI21__MAX_BW_MASK', 'DAGB0_RDCLI21__MAX_BW__SHIFT', + 'DAGB0_RDCLI21__MAX_OSD_MASK', 'DAGB0_RDCLI21__MAX_OSD__SHIFT', + 'DAGB0_RDCLI21__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI21__MIN_BW_MASK', 'DAGB0_RDCLI21__MIN_BW__SHIFT', + 'DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI21__URG_HIGH_MASK', 'DAGB0_RDCLI21__URG_HIGH__SHIFT', + 'DAGB0_RDCLI21__URG_LOW_MASK', 'DAGB0_RDCLI21__URG_LOW__SHIFT', + 'DAGB0_RDCLI21__VIRT_CHAN_MASK', + 'DAGB0_RDCLI21__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI22__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI22__MAX_BW_MASK', 'DAGB0_RDCLI22__MAX_BW__SHIFT', + 'DAGB0_RDCLI22__MAX_OSD_MASK', 'DAGB0_RDCLI22__MAX_OSD__SHIFT', + 'DAGB0_RDCLI22__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI22__MIN_BW_MASK', 'DAGB0_RDCLI22__MIN_BW__SHIFT', + 'DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI22__URG_HIGH_MASK', 'DAGB0_RDCLI22__URG_HIGH__SHIFT', + 'DAGB0_RDCLI22__URG_LOW_MASK', 'DAGB0_RDCLI22__URG_LOW__SHIFT', + 'DAGB0_RDCLI22__VIRT_CHAN_MASK', + 'DAGB0_RDCLI22__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI23__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI23__MAX_BW_MASK', 'DAGB0_RDCLI23__MAX_BW__SHIFT', + 'DAGB0_RDCLI23__MAX_OSD_MASK', 'DAGB0_RDCLI23__MAX_OSD__SHIFT', + 'DAGB0_RDCLI23__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI23__MIN_BW_MASK', 'DAGB0_RDCLI23__MIN_BW__SHIFT', + 'DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI23__URG_HIGH_MASK', 'DAGB0_RDCLI23__URG_HIGH__SHIFT', + 'DAGB0_RDCLI23__URG_LOW_MASK', 'DAGB0_RDCLI23__URG_LOW__SHIFT', + 'DAGB0_RDCLI23__VIRT_CHAN_MASK', + 'DAGB0_RDCLI23__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI2__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI2__MAX_BW_MASK', + 'DAGB0_RDCLI2__MAX_BW__SHIFT', 'DAGB0_RDCLI2__MAX_OSD_MASK', + 'DAGB0_RDCLI2__MAX_OSD__SHIFT', + 'DAGB0_RDCLI2__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI2__MIN_BW_MASK', + 'DAGB0_RDCLI2__MIN_BW__SHIFT', + 'DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI2__URG_HIGH_MASK', 'DAGB0_RDCLI2__URG_HIGH__SHIFT', + 'DAGB0_RDCLI2__URG_LOW_MASK', 'DAGB0_RDCLI2__URG_LOW__SHIFT', + 'DAGB0_RDCLI2__VIRT_CHAN_MASK', 'DAGB0_RDCLI2__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI3__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI3__MAX_BW_MASK', + 'DAGB0_RDCLI3__MAX_BW__SHIFT', 'DAGB0_RDCLI3__MAX_OSD_MASK', + 'DAGB0_RDCLI3__MAX_OSD__SHIFT', + 'DAGB0_RDCLI3__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI3__MIN_BW_MASK', + 'DAGB0_RDCLI3__MIN_BW__SHIFT', + 'DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI3__URG_HIGH_MASK', 'DAGB0_RDCLI3__URG_HIGH__SHIFT', + 'DAGB0_RDCLI3__URG_LOW_MASK', 'DAGB0_RDCLI3__URG_LOW__SHIFT', + 'DAGB0_RDCLI3__VIRT_CHAN_MASK', 'DAGB0_RDCLI3__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI4__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI4__MAX_BW_MASK', + 'DAGB0_RDCLI4__MAX_BW__SHIFT', 'DAGB0_RDCLI4__MAX_OSD_MASK', + 'DAGB0_RDCLI4__MAX_OSD__SHIFT', + 'DAGB0_RDCLI4__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI4__MIN_BW_MASK', + 'DAGB0_RDCLI4__MIN_BW__SHIFT', + 'DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI4__URG_HIGH_MASK', 'DAGB0_RDCLI4__URG_HIGH__SHIFT', + 'DAGB0_RDCLI4__URG_LOW_MASK', 'DAGB0_RDCLI4__URG_LOW__SHIFT', + 'DAGB0_RDCLI4__VIRT_CHAN_MASK', 'DAGB0_RDCLI4__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI5__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI5__MAX_BW_MASK', + 'DAGB0_RDCLI5__MAX_BW__SHIFT', 'DAGB0_RDCLI5__MAX_OSD_MASK', + 'DAGB0_RDCLI5__MAX_OSD__SHIFT', + 'DAGB0_RDCLI5__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI5__MIN_BW_MASK', + 'DAGB0_RDCLI5__MIN_BW__SHIFT', + 'DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI5__URG_HIGH_MASK', 'DAGB0_RDCLI5__URG_HIGH__SHIFT', + 'DAGB0_RDCLI5__URG_LOW_MASK', 'DAGB0_RDCLI5__URG_LOW__SHIFT', + 'DAGB0_RDCLI5__VIRT_CHAN_MASK', 'DAGB0_RDCLI5__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI6__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI6__MAX_BW_MASK', + 'DAGB0_RDCLI6__MAX_BW__SHIFT', 'DAGB0_RDCLI6__MAX_OSD_MASK', + 'DAGB0_RDCLI6__MAX_OSD__SHIFT', + 'DAGB0_RDCLI6__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI6__MIN_BW_MASK', + 'DAGB0_RDCLI6__MIN_BW__SHIFT', + 'DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI6__URG_HIGH_MASK', 'DAGB0_RDCLI6__URG_HIGH__SHIFT', + 'DAGB0_RDCLI6__URG_LOW_MASK', 'DAGB0_RDCLI6__URG_LOW__SHIFT', + 'DAGB0_RDCLI6__VIRT_CHAN_MASK', 'DAGB0_RDCLI6__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI7__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI7__MAX_BW_MASK', + 'DAGB0_RDCLI7__MAX_BW__SHIFT', 'DAGB0_RDCLI7__MAX_OSD_MASK', + 'DAGB0_RDCLI7__MAX_OSD__SHIFT', + 'DAGB0_RDCLI7__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI7__MIN_BW_MASK', + 'DAGB0_RDCLI7__MIN_BW__SHIFT', + 'DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI7__URG_HIGH_MASK', 'DAGB0_RDCLI7__URG_HIGH__SHIFT', + 'DAGB0_RDCLI7__URG_LOW_MASK', 'DAGB0_RDCLI7__URG_LOW__SHIFT', + 'DAGB0_RDCLI7__VIRT_CHAN_MASK', 'DAGB0_RDCLI7__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI8__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI8__MAX_BW_MASK', + 'DAGB0_RDCLI8__MAX_BW__SHIFT', 'DAGB0_RDCLI8__MAX_OSD_MASK', + 'DAGB0_RDCLI8__MAX_OSD__SHIFT', + 'DAGB0_RDCLI8__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI8__MIN_BW_MASK', + 'DAGB0_RDCLI8__MIN_BW__SHIFT', + 'DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI8__URG_HIGH_MASK', 'DAGB0_RDCLI8__URG_HIGH__SHIFT', + 'DAGB0_RDCLI8__URG_LOW_MASK', 'DAGB0_RDCLI8__URG_LOW__SHIFT', + 'DAGB0_RDCLI8__VIRT_CHAN_MASK', 'DAGB0_RDCLI8__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI9__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI9__MAX_BW_MASK', + 'DAGB0_RDCLI9__MAX_BW__SHIFT', 'DAGB0_RDCLI9__MAX_OSD_MASK', + 'DAGB0_RDCLI9__MAX_OSD__SHIFT', + 'DAGB0_RDCLI9__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI9__MIN_BW_MASK', + 'DAGB0_RDCLI9__MIN_BW__SHIFT', + 'DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI9__URG_HIGH_MASK', 'DAGB0_RDCLI9__URG_HIGH__SHIFT', + 'DAGB0_RDCLI9__URG_LOW_MASK', 'DAGB0_RDCLI9__URG_LOW__SHIFT', + 'DAGB0_RDCLI9__VIRT_CHAN_MASK', 'DAGB0_RDCLI9__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_ASK_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_GO_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT', + 'DAGB0_RDCLI_OARB_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_OSD_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_TLB_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK', + 'DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK', + 'DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT', + 'DAGB0_RD_ADDR_DAGB__WHOAMI_MASK', + 'DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK', + 'DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT', + 'DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK', + 'DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT', + 'DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK', + 'DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT', + 'DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK', + 'DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT', + 'DAGB0_RD_CNTL__SHARE_VC_NUM_MASK', + 'DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT', + 'DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK', + 'DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT', + 'DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK', + 'DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT', + 'DAGB0_RD_CREDITS_FULL__FULL_MASK', + 'DAGB0_RD_CREDITS_FULL__FULL__SHIFT', + 'DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB0_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB0__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB1_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB1__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB2_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB2__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB3_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB3__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB4_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB4__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB5_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB5__SHIFT', + 'DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC0_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC0_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC0_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC1_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC1_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC1_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC2_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC2_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC2_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC3_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC3_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC3_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC4_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC4_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC4_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC5_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC5_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC5_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RESERVE1__RESERVE_MASK', 'DAGB0_RESERVE1__RESERVE__SHIFT', + 'DAGB0_RESERVE2__RESERVE_MASK', 'DAGB0_RESERVE2__RESERVE__SHIFT', + 'DAGB0_RESERVE3__RESERVE_MASK', 'DAGB0_RESERVE3__RESERVE__SHIFT', + 'DAGB0_RESERVE4__RESERVE_MASK', 'DAGB0_RESERVE4__RESERVE__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK', + 'DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK', + 'DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK', + 'DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK', + 'DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK', + 'DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT', + 'DAGB0_SDP_CREDITS__TAG_LIMIT_MASK', + 'DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT', + 'DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK', + 'DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT', + 'DAGB0_SDP_ENABLE__ENABLE_MASK', + 'DAGB0_SDP_ENABLE__ENABLE__SHIFT', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK', + 'DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT', + 'DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK', + 'DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT', + 'DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK', + 'DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT', + 'DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK', + 'DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT', + 'DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK', + 'DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT', + 'DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK', + 'DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT', + 'DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK', + 'DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT', + 'DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK', + 'DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK', + 'DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK', + 'DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK', + 'DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK', + 'DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT', + 'DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK', + 'DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC0_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC1_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC2_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC3_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC4_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC5_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC6_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC7_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK', + 'DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK', + 'DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT', + 'DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI0__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI0__MAX_BW_MASK', + 'DAGB0_WRCLI0__MAX_BW__SHIFT', 'DAGB0_WRCLI0__MAX_OSD_MASK', + 'DAGB0_WRCLI0__MAX_OSD__SHIFT', + 'DAGB0_WRCLI0__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI0__MIN_BW_MASK', + 'DAGB0_WRCLI0__MIN_BW__SHIFT', + 'DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI0__URG_HIGH_MASK', 'DAGB0_WRCLI0__URG_HIGH__SHIFT', + 'DAGB0_WRCLI0__URG_LOW_MASK', 'DAGB0_WRCLI0__URG_LOW__SHIFT', + 'DAGB0_WRCLI0__VIRT_CHAN_MASK', 'DAGB0_WRCLI0__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI10__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI10__MAX_BW_MASK', 'DAGB0_WRCLI10__MAX_BW__SHIFT', + 'DAGB0_WRCLI10__MAX_OSD_MASK', 'DAGB0_WRCLI10__MAX_OSD__SHIFT', + 'DAGB0_WRCLI10__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI10__MIN_BW_MASK', 'DAGB0_WRCLI10__MIN_BW__SHIFT', + 'DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI10__URG_HIGH_MASK', 'DAGB0_WRCLI10__URG_HIGH__SHIFT', + 'DAGB0_WRCLI10__URG_LOW_MASK', 'DAGB0_WRCLI10__URG_LOW__SHIFT', + 'DAGB0_WRCLI10__VIRT_CHAN_MASK', + 'DAGB0_WRCLI10__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI11__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI11__MAX_BW_MASK', 'DAGB0_WRCLI11__MAX_BW__SHIFT', + 'DAGB0_WRCLI11__MAX_OSD_MASK', 'DAGB0_WRCLI11__MAX_OSD__SHIFT', + 'DAGB0_WRCLI11__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI11__MIN_BW_MASK', 'DAGB0_WRCLI11__MIN_BW__SHIFT', + 'DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI11__URG_HIGH_MASK', 'DAGB0_WRCLI11__URG_HIGH__SHIFT', + 'DAGB0_WRCLI11__URG_LOW_MASK', 'DAGB0_WRCLI11__URG_LOW__SHIFT', + 'DAGB0_WRCLI11__VIRT_CHAN_MASK', + 'DAGB0_WRCLI11__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI12__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI12__MAX_BW_MASK', 'DAGB0_WRCLI12__MAX_BW__SHIFT', + 'DAGB0_WRCLI12__MAX_OSD_MASK', 'DAGB0_WRCLI12__MAX_OSD__SHIFT', + 'DAGB0_WRCLI12__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI12__MIN_BW_MASK', 'DAGB0_WRCLI12__MIN_BW__SHIFT', + 'DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI12__URG_HIGH_MASK', 'DAGB0_WRCLI12__URG_HIGH__SHIFT', + 'DAGB0_WRCLI12__URG_LOW_MASK', 'DAGB0_WRCLI12__URG_LOW__SHIFT', + 'DAGB0_WRCLI12__VIRT_CHAN_MASK', + 'DAGB0_WRCLI12__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI13__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI13__MAX_BW_MASK', 'DAGB0_WRCLI13__MAX_BW__SHIFT', + 'DAGB0_WRCLI13__MAX_OSD_MASK', 'DAGB0_WRCLI13__MAX_OSD__SHIFT', + 'DAGB0_WRCLI13__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI13__MIN_BW_MASK', 'DAGB0_WRCLI13__MIN_BW__SHIFT', + 'DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI13__URG_HIGH_MASK', 'DAGB0_WRCLI13__URG_HIGH__SHIFT', + 'DAGB0_WRCLI13__URG_LOW_MASK', 'DAGB0_WRCLI13__URG_LOW__SHIFT', + 'DAGB0_WRCLI13__VIRT_CHAN_MASK', + 'DAGB0_WRCLI13__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI14__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI14__MAX_BW_MASK', 'DAGB0_WRCLI14__MAX_BW__SHIFT', + 'DAGB0_WRCLI14__MAX_OSD_MASK', 'DAGB0_WRCLI14__MAX_OSD__SHIFT', + 'DAGB0_WRCLI14__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI14__MIN_BW_MASK', 'DAGB0_WRCLI14__MIN_BW__SHIFT', + 'DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI14__URG_HIGH_MASK', 'DAGB0_WRCLI14__URG_HIGH__SHIFT', + 'DAGB0_WRCLI14__URG_LOW_MASK', 'DAGB0_WRCLI14__URG_LOW__SHIFT', + 'DAGB0_WRCLI14__VIRT_CHAN_MASK', + 'DAGB0_WRCLI14__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI15__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI15__MAX_BW_MASK', 'DAGB0_WRCLI15__MAX_BW__SHIFT', + 'DAGB0_WRCLI15__MAX_OSD_MASK', 'DAGB0_WRCLI15__MAX_OSD__SHIFT', + 'DAGB0_WRCLI15__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI15__MIN_BW_MASK', 'DAGB0_WRCLI15__MIN_BW__SHIFT', + 'DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI15__URG_HIGH_MASK', 'DAGB0_WRCLI15__URG_HIGH__SHIFT', + 'DAGB0_WRCLI15__URG_LOW_MASK', 'DAGB0_WRCLI15__URG_LOW__SHIFT', + 'DAGB0_WRCLI15__VIRT_CHAN_MASK', + 'DAGB0_WRCLI15__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI16__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI16__MAX_BW_MASK', 'DAGB0_WRCLI16__MAX_BW__SHIFT', + 'DAGB0_WRCLI16__MAX_OSD_MASK', 'DAGB0_WRCLI16__MAX_OSD__SHIFT', + 'DAGB0_WRCLI16__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI16__MIN_BW_MASK', 'DAGB0_WRCLI16__MIN_BW__SHIFT', + 'DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI16__URG_HIGH_MASK', 'DAGB0_WRCLI16__URG_HIGH__SHIFT', + 'DAGB0_WRCLI16__URG_LOW_MASK', 'DAGB0_WRCLI16__URG_LOW__SHIFT', + 'DAGB0_WRCLI16__VIRT_CHAN_MASK', + 'DAGB0_WRCLI16__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI17__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI17__MAX_BW_MASK', 'DAGB0_WRCLI17__MAX_BW__SHIFT', + 'DAGB0_WRCLI17__MAX_OSD_MASK', 'DAGB0_WRCLI17__MAX_OSD__SHIFT', + 'DAGB0_WRCLI17__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI17__MIN_BW_MASK', 'DAGB0_WRCLI17__MIN_BW__SHIFT', + 'DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI17__URG_HIGH_MASK', 'DAGB0_WRCLI17__URG_HIGH__SHIFT', + 'DAGB0_WRCLI17__URG_LOW_MASK', 'DAGB0_WRCLI17__URG_LOW__SHIFT', + 'DAGB0_WRCLI17__VIRT_CHAN_MASK', + 'DAGB0_WRCLI17__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI18__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI18__MAX_BW_MASK', 'DAGB0_WRCLI18__MAX_BW__SHIFT', + 'DAGB0_WRCLI18__MAX_OSD_MASK', 'DAGB0_WRCLI18__MAX_OSD__SHIFT', + 'DAGB0_WRCLI18__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI18__MIN_BW_MASK', 'DAGB0_WRCLI18__MIN_BW__SHIFT', + 'DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI18__URG_HIGH_MASK', 'DAGB0_WRCLI18__URG_HIGH__SHIFT', + 'DAGB0_WRCLI18__URG_LOW_MASK', 'DAGB0_WRCLI18__URG_LOW__SHIFT', + 'DAGB0_WRCLI18__VIRT_CHAN_MASK', + 'DAGB0_WRCLI18__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI19__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI19__MAX_BW_MASK', 'DAGB0_WRCLI19__MAX_BW__SHIFT', + 'DAGB0_WRCLI19__MAX_OSD_MASK', 'DAGB0_WRCLI19__MAX_OSD__SHIFT', + 'DAGB0_WRCLI19__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI19__MIN_BW_MASK', 'DAGB0_WRCLI19__MIN_BW__SHIFT', + 'DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI19__URG_HIGH_MASK', 'DAGB0_WRCLI19__URG_HIGH__SHIFT', + 'DAGB0_WRCLI19__URG_LOW_MASK', 'DAGB0_WRCLI19__URG_LOW__SHIFT', + 'DAGB0_WRCLI19__VIRT_CHAN_MASK', + 'DAGB0_WRCLI19__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI1__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI1__MAX_BW_MASK', + 'DAGB0_WRCLI1__MAX_BW__SHIFT', 'DAGB0_WRCLI1__MAX_OSD_MASK', + 'DAGB0_WRCLI1__MAX_OSD__SHIFT', + 'DAGB0_WRCLI1__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI1__MIN_BW_MASK', + 'DAGB0_WRCLI1__MIN_BW__SHIFT', + 'DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI1__URG_HIGH_MASK', 'DAGB0_WRCLI1__URG_HIGH__SHIFT', + 'DAGB0_WRCLI1__URG_LOW_MASK', 'DAGB0_WRCLI1__URG_LOW__SHIFT', + 'DAGB0_WRCLI1__VIRT_CHAN_MASK', 'DAGB0_WRCLI1__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI20__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI20__MAX_BW_MASK', 'DAGB0_WRCLI20__MAX_BW__SHIFT', + 'DAGB0_WRCLI20__MAX_OSD_MASK', 'DAGB0_WRCLI20__MAX_OSD__SHIFT', + 'DAGB0_WRCLI20__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI20__MIN_BW_MASK', 'DAGB0_WRCLI20__MIN_BW__SHIFT', + 'DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI20__URG_HIGH_MASK', 'DAGB0_WRCLI20__URG_HIGH__SHIFT', + 'DAGB0_WRCLI20__URG_LOW_MASK', 'DAGB0_WRCLI20__URG_LOW__SHIFT', + 'DAGB0_WRCLI20__VIRT_CHAN_MASK', + 'DAGB0_WRCLI20__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI21__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI21__MAX_BW_MASK', 'DAGB0_WRCLI21__MAX_BW__SHIFT', + 'DAGB0_WRCLI21__MAX_OSD_MASK', 'DAGB0_WRCLI21__MAX_OSD__SHIFT', + 'DAGB0_WRCLI21__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI21__MIN_BW_MASK', 'DAGB0_WRCLI21__MIN_BW__SHIFT', + 'DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI21__URG_HIGH_MASK', 'DAGB0_WRCLI21__URG_HIGH__SHIFT', + 'DAGB0_WRCLI21__URG_LOW_MASK', 'DAGB0_WRCLI21__URG_LOW__SHIFT', + 'DAGB0_WRCLI21__VIRT_CHAN_MASK', + 'DAGB0_WRCLI21__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI22__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI22__MAX_BW_MASK', 'DAGB0_WRCLI22__MAX_BW__SHIFT', + 'DAGB0_WRCLI22__MAX_OSD_MASK', 'DAGB0_WRCLI22__MAX_OSD__SHIFT', + 'DAGB0_WRCLI22__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI22__MIN_BW_MASK', 'DAGB0_WRCLI22__MIN_BW__SHIFT', + 'DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI22__URG_HIGH_MASK', 'DAGB0_WRCLI22__URG_HIGH__SHIFT', + 'DAGB0_WRCLI22__URG_LOW_MASK', 'DAGB0_WRCLI22__URG_LOW__SHIFT', + 'DAGB0_WRCLI22__VIRT_CHAN_MASK', + 'DAGB0_WRCLI22__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI23__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI23__MAX_BW_MASK', 'DAGB0_WRCLI23__MAX_BW__SHIFT', + 'DAGB0_WRCLI23__MAX_OSD_MASK', 'DAGB0_WRCLI23__MAX_OSD__SHIFT', + 'DAGB0_WRCLI23__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI23__MIN_BW_MASK', 'DAGB0_WRCLI23__MIN_BW__SHIFT', + 'DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI23__URG_HIGH_MASK', 'DAGB0_WRCLI23__URG_HIGH__SHIFT', + 'DAGB0_WRCLI23__URG_LOW_MASK', 'DAGB0_WRCLI23__URG_LOW__SHIFT', + 'DAGB0_WRCLI23__VIRT_CHAN_MASK', + 'DAGB0_WRCLI23__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI2__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI2__MAX_BW_MASK', + 'DAGB0_WRCLI2__MAX_BW__SHIFT', 'DAGB0_WRCLI2__MAX_OSD_MASK', + 'DAGB0_WRCLI2__MAX_OSD__SHIFT', + 'DAGB0_WRCLI2__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI2__MIN_BW_MASK', + 'DAGB0_WRCLI2__MIN_BW__SHIFT', + 'DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI2__URG_HIGH_MASK', 'DAGB0_WRCLI2__URG_HIGH__SHIFT', + 'DAGB0_WRCLI2__URG_LOW_MASK', 'DAGB0_WRCLI2__URG_LOW__SHIFT', + 'DAGB0_WRCLI2__VIRT_CHAN_MASK', 'DAGB0_WRCLI2__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI3__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI3__MAX_BW_MASK', + 'DAGB0_WRCLI3__MAX_BW__SHIFT', 'DAGB0_WRCLI3__MAX_OSD_MASK', + 'DAGB0_WRCLI3__MAX_OSD__SHIFT', + 'DAGB0_WRCLI3__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI3__MIN_BW_MASK', + 'DAGB0_WRCLI3__MIN_BW__SHIFT', + 'DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI3__URG_HIGH_MASK', 'DAGB0_WRCLI3__URG_HIGH__SHIFT', + 'DAGB0_WRCLI3__URG_LOW_MASK', 'DAGB0_WRCLI3__URG_LOW__SHIFT', + 'DAGB0_WRCLI3__VIRT_CHAN_MASK', 'DAGB0_WRCLI3__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI4__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI4__MAX_BW_MASK', + 'DAGB0_WRCLI4__MAX_BW__SHIFT', 'DAGB0_WRCLI4__MAX_OSD_MASK', + 'DAGB0_WRCLI4__MAX_OSD__SHIFT', + 'DAGB0_WRCLI4__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI4__MIN_BW_MASK', + 'DAGB0_WRCLI4__MIN_BW__SHIFT', + 'DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI4__URG_HIGH_MASK', 'DAGB0_WRCLI4__URG_HIGH__SHIFT', + 'DAGB0_WRCLI4__URG_LOW_MASK', 'DAGB0_WRCLI4__URG_LOW__SHIFT', + 'DAGB0_WRCLI4__VIRT_CHAN_MASK', 'DAGB0_WRCLI4__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI5__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI5__MAX_BW_MASK', + 'DAGB0_WRCLI5__MAX_BW__SHIFT', 'DAGB0_WRCLI5__MAX_OSD_MASK', + 'DAGB0_WRCLI5__MAX_OSD__SHIFT', + 'DAGB0_WRCLI5__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI5__MIN_BW_MASK', + 'DAGB0_WRCLI5__MIN_BW__SHIFT', + 'DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI5__URG_HIGH_MASK', 'DAGB0_WRCLI5__URG_HIGH__SHIFT', + 'DAGB0_WRCLI5__URG_LOW_MASK', 'DAGB0_WRCLI5__URG_LOW__SHIFT', + 'DAGB0_WRCLI5__VIRT_CHAN_MASK', 'DAGB0_WRCLI5__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI6__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI6__MAX_BW_MASK', + 'DAGB0_WRCLI6__MAX_BW__SHIFT', 'DAGB0_WRCLI6__MAX_OSD_MASK', + 'DAGB0_WRCLI6__MAX_OSD__SHIFT', + 'DAGB0_WRCLI6__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI6__MIN_BW_MASK', + 'DAGB0_WRCLI6__MIN_BW__SHIFT', + 'DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI6__URG_HIGH_MASK', 'DAGB0_WRCLI6__URG_HIGH__SHIFT', + 'DAGB0_WRCLI6__URG_LOW_MASK', 'DAGB0_WRCLI6__URG_LOW__SHIFT', + 'DAGB0_WRCLI6__VIRT_CHAN_MASK', 'DAGB0_WRCLI6__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI7__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI7__MAX_BW_MASK', + 'DAGB0_WRCLI7__MAX_BW__SHIFT', 'DAGB0_WRCLI7__MAX_OSD_MASK', + 'DAGB0_WRCLI7__MAX_OSD__SHIFT', + 'DAGB0_WRCLI7__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI7__MIN_BW_MASK', + 'DAGB0_WRCLI7__MIN_BW__SHIFT', + 'DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI7__URG_HIGH_MASK', 'DAGB0_WRCLI7__URG_HIGH__SHIFT', + 'DAGB0_WRCLI7__URG_LOW_MASK', 'DAGB0_WRCLI7__URG_LOW__SHIFT', + 'DAGB0_WRCLI7__VIRT_CHAN_MASK', 'DAGB0_WRCLI7__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI8__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI8__MAX_BW_MASK', + 'DAGB0_WRCLI8__MAX_BW__SHIFT', 'DAGB0_WRCLI8__MAX_OSD_MASK', + 'DAGB0_WRCLI8__MAX_OSD__SHIFT', + 'DAGB0_WRCLI8__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI8__MIN_BW_MASK', + 'DAGB0_WRCLI8__MIN_BW__SHIFT', + 'DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI8__URG_HIGH_MASK', 'DAGB0_WRCLI8__URG_HIGH__SHIFT', + 'DAGB0_WRCLI8__URG_LOW_MASK', 'DAGB0_WRCLI8__URG_LOW__SHIFT', + 'DAGB0_WRCLI8__VIRT_CHAN_MASK', 'DAGB0_WRCLI8__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI9__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI9__MAX_BW_MASK', + 'DAGB0_WRCLI9__MAX_BW__SHIFT', 'DAGB0_WRCLI9__MAX_OSD_MASK', + 'DAGB0_WRCLI9__MAX_OSD__SHIFT', + 'DAGB0_WRCLI9__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI9__MIN_BW_MASK', + 'DAGB0_WRCLI9__MIN_BW__SHIFT', + 'DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI9__URG_HIGH_MASK', 'DAGB0_WRCLI9__URG_HIGH__SHIFT', + 'DAGB0_WRCLI9__URG_LOW_MASK', 'DAGB0_WRCLI9__URG_LOW__SHIFT', + 'DAGB0_WRCLI9__VIRT_CHAN_MASK', 'DAGB0_WRCLI9__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_ASK_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_GO_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT', + 'DAGB0_WRCLI_OARB_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_OSD_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_TLB_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK', + 'DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK', + 'DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT', + 'DAGB0_WR_ADDR_DAGB__WHOAMI_MASK', + 'DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_WR_CNTL_MISC__HDP_CID_MASK', + 'DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT', + 'DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK', + 'DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT', + 'DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK', + 'DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT', + 'DAGB0_WR_CNTL__UPDATE_FED_MASK', + 'DAGB0_WR_CNTL__UPDATE_FED__SHIFT', + 'DAGB0_WR_CNTL__UPDATE_NACK_MASK', + 'DAGB0_WR_CNTL__UPDATE_NACK__SHIFT', + 'DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK', + 'DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT', + 'DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK', + 'DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT', + 'DAGB0_WR_CREDITS_FULL__FULL_MASK', + 'DAGB0_WR_CREDITS_FULL__FULL__SHIFT', + 'DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT', + 'DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT', + 'DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT', + 'DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK', + 'DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB0_WR_DATA_DAGB__WHOAMI_MASK', + 'DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT', + 'DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK', + 'DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT', + 'DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK', + 'DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB0_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB0__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB1_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB1__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB2_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB2__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB3_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB3__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB4_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB4__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB5_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB5__SHIFT', + 'DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC0_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC0_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC0_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC1_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC1_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC1_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC2_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC2_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC2_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC3_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC3_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC3_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC4_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC4_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC4_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC5_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC5_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC5_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK', + 'DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK', + 'DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK', + 'DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT', + 'DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK', + 'DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT', + 'DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK', + 'DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT', + 'DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__SWAP_CTL_MASK', + 'DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT', + 'DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK', + 'DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT', + 'DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK', + 'DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT', + 'DAGB1_DAGB_DLY__CLI_MASK', 'DAGB1_DAGB_DLY__CLI__SHIFT', + 'DAGB1_DAGB_DLY__DLY_MASK', 'DAGB1_DAGB_DLY__DLY__SHIFT', + 'DAGB1_DAGB_DLY__POS_MASK', 'DAGB1_DAGB_DLY__POS__SHIFT', + 'DAGB1_FIFO_EMPTY__EMPTY_MASK', 'DAGB1_FIFO_EMPTY__EMPTY__SHIFT', + 'DAGB1_FIFO_FULL__FULL_MASK', 'DAGB1_FIFO_FULL__FULL__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK', + 'DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT', + 'DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK', + 'DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT', + 'DAGB1_L1TLB_REG_RW__RESERVE_MASK', + 'DAGB1_L1TLB_REG_RW__RESERVE__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK', + 'DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK', + 'DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK', + 'DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK', + 'DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK', + 'DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK', + 'DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI0__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI0__MAX_BW_MASK', + 'DAGB1_RDCLI0__MAX_BW__SHIFT', 'DAGB1_RDCLI0__MAX_OSD_MASK', + 'DAGB1_RDCLI0__MAX_OSD__SHIFT', + 'DAGB1_RDCLI0__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI0__MIN_BW_MASK', + 'DAGB1_RDCLI0__MIN_BW__SHIFT', + 'DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI0__URG_HIGH_MASK', 'DAGB1_RDCLI0__URG_HIGH__SHIFT', + 'DAGB1_RDCLI0__URG_LOW_MASK', 'DAGB1_RDCLI0__URG_LOW__SHIFT', + 'DAGB1_RDCLI0__VIRT_CHAN_MASK', 'DAGB1_RDCLI0__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI10__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI10__MAX_BW_MASK', 'DAGB1_RDCLI10__MAX_BW__SHIFT', + 'DAGB1_RDCLI10__MAX_OSD_MASK', 'DAGB1_RDCLI10__MAX_OSD__SHIFT', + 'DAGB1_RDCLI10__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI10__MIN_BW_MASK', 'DAGB1_RDCLI10__MIN_BW__SHIFT', + 'DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI10__URG_HIGH_MASK', 'DAGB1_RDCLI10__URG_HIGH__SHIFT', + 'DAGB1_RDCLI10__URG_LOW_MASK', 'DAGB1_RDCLI10__URG_LOW__SHIFT', + 'DAGB1_RDCLI10__VIRT_CHAN_MASK', + 'DAGB1_RDCLI10__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI11__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI11__MAX_BW_MASK', 'DAGB1_RDCLI11__MAX_BW__SHIFT', + 'DAGB1_RDCLI11__MAX_OSD_MASK', 'DAGB1_RDCLI11__MAX_OSD__SHIFT', + 'DAGB1_RDCLI11__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI11__MIN_BW_MASK', 'DAGB1_RDCLI11__MIN_BW__SHIFT', + 'DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI11__URG_HIGH_MASK', 'DAGB1_RDCLI11__URG_HIGH__SHIFT', + 'DAGB1_RDCLI11__URG_LOW_MASK', 'DAGB1_RDCLI11__URG_LOW__SHIFT', + 'DAGB1_RDCLI11__VIRT_CHAN_MASK', + 'DAGB1_RDCLI11__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI12__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI12__MAX_BW_MASK', 'DAGB1_RDCLI12__MAX_BW__SHIFT', + 'DAGB1_RDCLI12__MAX_OSD_MASK', 'DAGB1_RDCLI12__MAX_OSD__SHIFT', + 'DAGB1_RDCLI12__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI12__MIN_BW_MASK', 'DAGB1_RDCLI12__MIN_BW__SHIFT', + 'DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI12__URG_HIGH_MASK', 'DAGB1_RDCLI12__URG_HIGH__SHIFT', + 'DAGB1_RDCLI12__URG_LOW_MASK', 'DAGB1_RDCLI12__URG_LOW__SHIFT', + 'DAGB1_RDCLI12__VIRT_CHAN_MASK', + 'DAGB1_RDCLI12__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI13__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI13__MAX_BW_MASK', 'DAGB1_RDCLI13__MAX_BW__SHIFT', + 'DAGB1_RDCLI13__MAX_OSD_MASK', 'DAGB1_RDCLI13__MAX_OSD__SHIFT', + 'DAGB1_RDCLI13__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI13__MIN_BW_MASK', 'DAGB1_RDCLI13__MIN_BW__SHIFT', + 'DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI13__URG_HIGH_MASK', 'DAGB1_RDCLI13__URG_HIGH__SHIFT', + 'DAGB1_RDCLI13__URG_LOW_MASK', 'DAGB1_RDCLI13__URG_LOW__SHIFT', + 'DAGB1_RDCLI13__VIRT_CHAN_MASK', + 'DAGB1_RDCLI13__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI14__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI14__MAX_BW_MASK', 'DAGB1_RDCLI14__MAX_BW__SHIFT', + 'DAGB1_RDCLI14__MAX_OSD_MASK', 'DAGB1_RDCLI14__MAX_OSD__SHIFT', + 'DAGB1_RDCLI14__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI14__MIN_BW_MASK', 'DAGB1_RDCLI14__MIN_BW__SHIFT', + 'DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI14__URG_HIGH_MASK', 'DAGB1_RDCLI14__URG_HIGH__SHIFT', + 'DAGB1_RDCLI14__URG_LOW_MASK', 'DAGB1_RDCLI14__URG_LOW__SHIFT', + 'DAGB1_RDCLI14__VIRT_CHAN_MASK', + 'DAGB1_RDCLI14__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI15__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI15__MAX_BW_MASK', 'DAGB1_RDCLI15__MAX_BW__SHIFT', + 'DAGB1_RDCLI15__MAX_OSD_MASK', 'DAGB1_RDCLI15__MAX_OSD__SHIFT', + 'DAGB1_RDCLI15__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI15__MIN_BW_MASK', 'DAGB1_RDCLI15__MIN_BW__SHIFT', + 'DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI15__URG_HIGH_MASK', 'DAGB1_RDCLI15__URG_HIGH__SHIFT', + 'DAGB1_RDCLI15__URG_LOW_MASK', 'DAGB1_RDCLI15__URG_LOW__SHIFT', + 'DAGB1_RDCLI15__VIRT_CHAN_MASK', + 'DAGB1_RDCLI15__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI16__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI16__MAX_BW_MASK', 'DAGB1_RDCLI16__MAX_BW__SHIFT', + 'DAGB1_RDCLI16__MAX_OSD_MASK', 'DAGB1_RDCLI16__MAX_OSD__SHIFT', + 'DAGB1_RDCLI16__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI16__MIN_BW_MASK', 'DAGB1_RDCLI16__MIN_BW__SHIFT', + 'DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI16__URG_HIGH_MASK', 'DAGB1_RDCLI16__URG_HIGH__SHIFT', + 'DAGB1_RDCLI16__URG_LOW_MASK', 'DAGB1_RDCLI16__URG_LOW__SHIFT', + 'DAGB1_RDCLI16__VIRT_CHAN_MASK', + 'DAGB1_RDCLI16__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI17__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI17__MAX_BW_MASK', 'DAGB1_RDCLI17__MAX_BW__SHIFT', + 'DAGB1_RDCLI17__MAX_OSD_MASK', 'DAGB1_RDCLI17__MAX_OSD__SHIFT', + 'DAGB1_RDCLI17__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI17__MIN_BW_MASK', 'DAGB1_RDCLI17__MIN_BW__SHIFT', + 'DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI17__URG_HIGH_MASK', 'DAGB1_RDCLI17__URG_HIGH__SHIFT', + 'DAGB1_RDCLI17__URG_LOW_MASK', 'DAGB1_RDCLI17__URG_LOW__SHIFT', + 'DAGB1_RDCLI17__VIRT_CHAN_MASK', + 'DAGB1_RDCLI17__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI18__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI18__MAX_BW_MASK', 'DAGB1_RDCLI18__MAX_BW__SHIFT', + 'DAGB1_RDCLI18__MAX_OSD_MASK', 'DAGB1_RDCLI18__MAX_OSD__SHIFT', + 'DAGB1_RDCLI18__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI18__MIN_BW_MASK', 'DAGB1_RDCLI18__MIN_BW__SHIFT', + 'DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI18__URG_HIGH_MASK', 'DAGB1_RDCLI18__URG_HIGH__SHIFT', + 'DAGB1_RDCLI18__URG_LOW_MASK', 'DAGB1_RDCLI18__URG_LOW__SHIFT', + 'DAGB1_RDCLI18__VIRT_CHAN_MASK', + 'DAGB1_RDCLI18__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI19__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI19__MAX_BW_MASK', 'DAGB1_RDCLI19__MAX_BW__SHIFT', + 'DAGB1_RDCLI19__MAX_OSD_MASK', 'DAGB1_RDCLI19__MAX_OSD__SHIFT', + 'DAGB1_RDCLI19__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI19__MIN_BW_MASK', 'DAGB1_RDCLI19__MIN_BW__SHIFT', + 'DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI19__URG_HIGH_MASK', 'DAGB1_RDCLI19__URG_HIGH__SHIFT', + 'DAGB1_RDCLI19__URG_LOW_MASK', 'DAGB1_RDCLI19__URG_LOW__SHIFT', + 'DAGB1_RDCLI19__VIRT_CHAN_MASK', + 'DAGB1_RDCLI19__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI1__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI1__MAX_BW_MASK', + 'DAGB1_RDCLI1__MAX_BW__SHIFT', 'DAGB1_RDCLI1__MAX_OSD_MASK', + 'DAGB1_RDCLI1__MAX_OSD__SHIFT', + 'DAGB1_RDCLI1__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI1__MIN_BW_MASK', + 'DAGB1_RDCLI1__MIN_BW__SHIFT', + 'DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI1__URG_HIGH_MASK', 'DAGB1_RDCLI1__URG_HIGH__SHIFT', + 'DAGB1_RDCLI1__URG_LOW_MASK', 'DAGB1_RDCLI1__URG_LOW__SHIFT', + 'DAGB1_RDCLI1__VIRT_CHAN_MASK', 'DAGB1_RDCLI1__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI20__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI20__MAX_BW_MASK', 'DAGB1_RDCLI20__MAX_BW__SHIFT', + 'DAGB1_RDCLI20__MAX_OSD_MASK', 'DAGB1_RDCLI20__MAX_OSD__SHIFT', + 'DAGB1_RDCLI20__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI20__MIN_BW_MASK', 'DAGB1_RDCLI20__MIN_BW__SHIFT', + 'DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI20__URG_HIGH_MASK', 'DAGB1_RDCLI20__URG_HIGH__SHIFT', + 'DAGB1_RDCLI20__URG_LOW_MASK', 'DAGB1_RDCLI20__URG_LOW__SHIFT', + 'DAGB1_RDCLI20__VIRT_CHAN_MASK', + 'DAGB1_RDCLI20__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI21__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI21__MAX_BW_MASK', 'DAGB1_RDCLI21__MAX_BW__SHIFT', + 'DAGB1_RDCLI21__MAX_OSD_MASK', 'DAGB1_RDCLI21__MAX_OSD__SHIFT', + 'DAGB1_RDCLI21__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI21__MIN_BW_MASK', 'DAGB1_RDCLI21__MIN_BW__SHIFT', + 'DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI21__URG_HIGH_MASK', 'DAGB1_RDCLI21__URG_HIGH__SHIFT', + 'DAGB1_RDCLI21__URG_LOW_MASK', 'DAGB1_RDCLI21__URG_LOW__SHIFT', + 'DAGB1_RDCLI21__VIRT_CHAN_MASK', + 'DAGB1_RDCLI21__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI22__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI22__MAX_BW_MASK', 'DAGB1_RDCLI22__MAX_BW__SHIFT', + 'DAGB1_RDCLI22__MAX_OSD_MASK', 'DAGB1_RDCLI22__MAX_OSD__SHIFT', + 'DAGB1_RDCLI22__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI22__MIN_BW_MASK', 'DAGB1_RDCLI22__MIN_BW__SHIFT', + 'DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI22__URG_HIGH_MASK', 'DAGB1_RDCLI22__URG_HIGH__SHIFT', + 'DAGB1_RDCLI22__URG_LOW_MASK', 'DAGB1_RDCLI22__URG_LOW__SHIFT', + 'DAGB1_RDCLI22__VIRT_CHAN_MASK', + 'DAGB1_RDCLI22__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI23__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI23__MAX_BW_MASK', 'DAGB1_RDCLI23__MAX_BW__SHIFT', + 'DAGB1_RDCLI23__MAX_OSD_MASK', 'DAGB1_RDCLI23__MAX_OSD__SHIFT', + 'DAGB1_RDCLI23__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI23__MIN_BW_MASK', 'DAGB1_RDCLI23__MIN_BW__SHIFT', + 'DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI23__URG_HIGH_MASK', 'DAGB1_RDCLI23__URG_HIGH__SHIFT', + 'DAGB1_RDCLI23__URG_LOW_MASK', 'DAGB1_RDCLI23__URG_LOW__SHIFT', + 'DAGB1_RDCLI23__VIRT_CHAN_MASK', + 'DAGB1_RDCLI23__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI2__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI2__MAX_BW_MASK', + 'DAGB1_RDCLI2__MAX_BW__SHIFT', 'DAGB1_RDCLI2__MAX_OSD_MASK', + 'DAGB1_RDCLI2__MAX_OSD__SHIFT', + 'DAGB1_RDCLI2__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI2__MIN_BW_MASK', + 'DAGB1_RDCLI2__MIN_BW__SHIFT', + 'DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI2__URG_HIGH_MASK', 'DAGB1_RDCLI2__URG_HIGH__SHIFT', + 'DAGB1_RDCLI2__URG_LOW_MASK', 'DAGB1_RDCLI2__URG_LOW__SHIFT', + 'DAGB1_RDCLI2__VIRT_CHAN_MASK', 'DAGB1_RDCLI2__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI3__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI3__MAX_BW_MASK', + 'DAGB1_RDCLI3__MAX_BW__SHIFT', 'DAGB1_RDCLI3__MAX_OSD_MASK', + 'DAGB1_RDCLI3__MAX_OSD__SHIFT', + 'DAGB1_RDCLI3__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI3__MIN_BW_MASK', + 'DAGB1_RDCLI3__MIN_BW__SHIFT', + 'DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI3__URG_HIGH_MASK', 'DAGB1_RDCLI3__URG_HIGH__SHIFT', + 'DAGB1_RDCLI3__URG_LOW_MASK', 'DAGB1_RDCLI3__URG_LOW__SHIFT', + 'DAGB1_RDCLI3__VIRT_CHAN_MASK', 'DAGB1_RDCLI3__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI4__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI4__MAX_BW_MASK', + 'DAGB1_RDCLI4__MAX_BW__SHIFT', 'DAGB1_RDCLI4__MAX_OSD_MASK', + 'DAGB1_RDCLI4__MAX_OSD__SHIFT', + 'DAGB1_RDCLI4__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI4__MIN_BW_MASK', + 'DAGB1_RDCLI4__MIN_BW__SHIFT', + 'DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI4__URG_HIGH_MASK', 'DAGB1_RDCLI4__URG_HIGH__SHIFT', + 'DAGB1_RDCLI4__URG_LOW_MASK', 'DAGB1_RDCLI4__URG_LOW__SHIFT', + 'DAGB1_RDCLI4__VIRT_CHAN_MASK', 'DAGB1_RDCLI4__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI5__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI5__MAX_BW_MASK', + 'DAGB1_RDCLI5__MAX_BW__SHIFT', 'DAGB1_RDCLI5__MAX_OSD_MASK', + 'DAGB1_RDCLI5__MAX_OSD__SHIFT', + 'DAGB1_RDCLI5__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI5__MIN_BW_MASK', + 'DAGB1_RDCLI5__MIN_BW__SHIFT', + 'DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI5__URG_HIGH_MASK', 'DAGB1_RDCLI5__URG_HIGH__SHIFT', + 'DAGB1_RDCLI5__URG_LOW_MASK', 'DAGB1_RDCLI5__URG_LOW__SHIFT', + 'DAGB1_RDCLI5__VIRT_CHAN_MASK', 'DAGB1_RDCLI5__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI6__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI6__MAX_BW_MASK', + 'DAGB1_RDCLI6__MAX_BW__SHIFT', 'DAGB1_RDCLI6__MAX_OSD_MASK', + 'DAGB1_RDCLI6__MAX_OSD__SHIFT', + 'DAGB1_RDCLI6__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI6__MIN_BW_MASK', + 'DAGB1_RDCLI6__MIN_BW__SHIFT', + 'DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI6__URG_HIGH_MASK', 'DAGB1_RDCLI6__URG_HIGH__SHIFT', + 'DAGB1_RDCLI6__URG_LOW_MASK', 'DAGB1_RDCLI6__URG_LOW__SHIFT', + 'DAGB1_RDCLI6__VIRT_CHAN_MASK', 'DAGB1_RDCLI6__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI7__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI7__MAX_BW_MASK', + 'DAGB1_RDCLI7__MAX_BW__SHIFT', 'DAGB1_RDCLI7__MAX_OSD_MASK', + 'DAGB1_RDCLI7__MAX_OSD__SHIFT', + 'DAGB1_RDCLI7__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI7__MIN_BW_MASK', + 'DAGB1_RDCLI7__MIN_BW__SHIFT', + 'DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI7__URG_HIGH_MASK', 'DAGB1_RDCLI7__URG_HIGH__SHIFT', + 'DAGB1_RDCLI7__URG_LOW_MASK', 'DAGB1_RDCLI7__URG_LOW__SHIFT', + 'DAGB1_RDCLI7__VIRT_CHAN_MASK', 'DAGB1_RDCLI7__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI8__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI8__MAX_BW_MASK', + 'DAGB1_RDCLI8__MAX_BW__SHIFT', 'DAGB1_RDCLI8__MAX_OSD_MASK', + 'DAGB1_RDCLI8__MAX_OSD__SHIFT', + 'DAGB1_RDCLI8__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI8__MIN_BW_MASK', + 'DAGB1_RDCLI8__MIN_BW__SHIFT', + 'DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI8__URG_HIGH_MASK', 'DAGB1_RDCLI8__URG_HIGH__SHIFT', + 'DAGB1_RDCLI8__URG_LOW_MASK', 'DAGB1_RDCLI8__URG_LOW__SHIFT', + 'DAGB1_RDCLI8__VIRT_CHAN_MASK', 'DAGB1_RDCLI8__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI9__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI9__MAX_BW_MASK', + 'DAGB1_RDCLI9__MAX_BW__SHIFT', 'DAGB1_RDCLI9__MAX_OSD_MASK', + 'DAGB1_RDCLI9__MAX_OSD__SHIFT', + 'DAGB1_RDCLI9__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI9__MIN_BW_MASK', + 'DAGB1_RDCLI9__MIN_BW__SHIFT', + 'DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI9__URG_HIGH_MASK', 'DAGB1_RDCLI9__URG_HIGH__SHIFT', + 'DAGB1_RDCLI9__URG_LOW_MASK', 'DAGB1_RDCLI9__URG_LOW__SHIFT', + 'DAGB1_RDCLI9__VIRT_CHAN_MASK', 'DAGB1_RDCLI9__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_ASK_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_GO_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT', + 'DAGB1_RDCLI_OARB_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_OSD_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_TLB_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK', + 'DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK', + 'DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT', + 'DAGB1_RD_ADDR_DAGB__WHOAMI_MASK', + 'DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK', + 'DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT', + 'DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK', + 'DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT', + 'DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK', + 'DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT', + 'DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK', + 'DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT', + 'DAGB1_RD_CNTL__SHARE_VC_NUM_MASK', + 'DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT', + 'DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK', + 'DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT', + 'DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK', + 'DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT', + 'DAGB1_RD_CREDITS_FULL__FULL_MASK', + 'DAGB1_RD_CREDITS_FULL__FULL__SHIFT', + 'DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK', + 'DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK', + 'DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB0_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB0__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB1_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB1__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB2_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB2__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB3_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB3__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB4_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB4__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB5_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB5__SHIFT', + 'DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC0_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC0_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC0_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC1_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC1_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC1_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC2_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC2_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC2_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC3_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC3_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC3_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC4_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC4_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC4_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC5_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC5_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC5_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RESERVE1__RESERVE_MASK', 'DAGB1_RESERVE1__RESERVE__SHIFT', + 'DAGB1_RESERVE2__RESERVE_MASK', 'DAGB1_RESERVE2__RESERVE__SHIFT', + 'DAGB1_RESERVE3__RESERVE_MASK', 'DAGB1_RESERVE3__RESERVE__SHIFT', + 'DAGB1_RESERVE4__RESERVE_MASK', 'DAGB1_RESERVE4__RESERVE__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK', + 'DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK', + 'DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK', + 'DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK', + 'DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK', + 'DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT', + 'DAGB1_SDP_CREDITS__TAG_LIMIT_MASK', + 'DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT', + 'DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK', + 'DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT', + 'DAGB1_SDP_ENABLE__ENABLE_MASK', + 'DAGB1_SDP_ENABLE__ENABLE__SHIFT', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK', + 'DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT', + 'DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK', + 'DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT', + 'DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK', + 'DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT', + 'DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK', + 'DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT', + 'DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK', + 'DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT', + 'DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK', + 'DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT', + 'DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK', + 'DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT', + 'DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK', + 'DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK', + 'DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK', + 'DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK', + 'DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK', + 'DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT', + 'DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK', + 'DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC0_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC1_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC2_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC3_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC4_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC5_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC6_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC7_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK', + 'DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT', + 'MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MML2TLB_TLB0_STATUS__BUSY_MASK', + 'MML2TLB_TLB0_STATUS__BUSY__SHIFT', + 'MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK', + 'MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT', + 'MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK', + 'MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT', + 'MMMC_MEM_POWER_LS__LS_HOLD_MASK', + 'MMMC_MEM_POWER_LS__LS_HOLD__SHIFT', + 'MMMC_MEM_POWER_LS__LS_SETUP_MASK', + 'MMMC_MEM_POWER_LS__LS_SETUP__SHIFT', + 'MMMC_VM_AGP_BASE__AGP_BASE_MASK', + 'MMMC_VM_AGP_BASE__AGP_BASE__SHIFT', + 'MMMC_VM_AGP_BOT__AGP_BOT_MASK', + 'MMMC_VM_AGP_BOT__AGP_BOT__SHIFT', + 'MMMC_VM_AGP_TOP__AGP_TOP_MASK', + 'MMMC_VM_AGP_TOP__AGP_TOP__SHIFT', + 'MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK', + 'MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT', + 'MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK', + 'MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT', + 'MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK', + 'MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT', + 'MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK', + 'MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT', + 'MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK', + 'MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT', + 'MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK', + 'MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT', + 'MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK', + 'MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT', + 'MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK', + 'MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT', + 'MMMC_VM_FB_OFFSET__FB_OFFSET_MASK', + 'MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK', + 'MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT', + 'MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK', + 'MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT', + 'MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK', + 'MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK', + 'MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT', + 'MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK', + 'MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT', + 'MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK', + 'MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT', + 'MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK', + 'MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT', + 'MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK', + 'MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT', + 'MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK', + 'MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT', + 'MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT', + 'MMMC_VM_STEERING__DEFAULT_STEERING_MASK', + 'MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK', + 'MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK', + 'MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT', + 'MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK', + 'MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT', + 'MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK', + 'MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT', + 'MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT_MASK', + 'MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT__SHIFT', + 'MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST_MASK', + 'MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST__SHIFT', + 'MMUTCL2_FFBM_ADDRESS__ADDRESS_MASK', + 'MMUTCL2_FFBM_ADDRESS__ADDRESS__SHIFT', + 'MMUTCL2_FFBM_ADDRESS__VFID_MASK', + 'MMUTCL2_FFBM_ADDRESS__VFID__SHIFT', + 'MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE_MASK', + 'MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE__SHIFT', + 'MMUTCL2_FFBM_DATA__FB_SPA_MASK', + 'MMUTCL2_FFBM_DATA__FB_SPA__SHIFT', + 'MMUTCL2_FFBM_DATA__FRAGMENT_MASK', + 'MMUTCL2_FFBM_DATA__FRAGMENT__SHIFT', + 'MMUTCL2_FFBM_DATA__READ_PERMISSION_MASK', + 'MMUTCL2_FFBM_DATA__READ_PERMISSION__SHIFT', + 'MMUTCL2_FFBM_DATA__VALID_MASK', + 'MMUTCL2_FFBM_DATA__VALID__SHIFT', + 'MMUTCL2_FFBM_DATA__WRITE_PERMISSION_MASK', + 'MMUTCL2_FFBM_DATA__WRITE_PERMISSION__SHIFT', + 'MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM_MASK', + 'MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM__SHIFT', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS_MASK', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS__SHIFT', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE_MASK', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE__SHIFT', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ_MASK', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ__SHIFT', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE_MASK', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE__SHIFT', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID_MASK', + 'MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID__SHIFT', + 'MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK_MASK', + 'MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK__SHIFT', + 'MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK_MASK', + 'MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK__SHIFT', + 'MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK', + 'MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT', + 'MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK', + 'MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT', + 'MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK', + 'MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT', + 'MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK', + 'MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT', + 'MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK', + 'MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT', + 'MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK', + 'MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT', + 'MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT', + 'MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK', + 'MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT', + 'MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK', + 'MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK', + 'MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT', + 'MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK', + 'MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT', + 'MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK', + 'MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT', + 'MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK', + 'MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT', + 'MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK', + 'MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT', + 'MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK', + 'MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT', + 'MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK', + 'MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT', + 'MMVM_L2_CNTL3__BANK_SELECT_MASK', + 'MMVM_L2_CNTL3__BANK_SELECT__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT', + 'MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK', + 'MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT', + 'MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK', + 'MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT', + 'MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK', + 'MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT', + 'MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK', + 'MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT', + 'MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK', + 'MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT', + 'MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK', + 'MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT', + 'MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK', + 'MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT', + 'MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK', + 'MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT', + 'MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK', + 'MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT', + 'MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK', + 'MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT', + 'MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK', + 'MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT', + 'MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK', + 'MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT', + 'MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK', + 'MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT', + 'MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK', + 'MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK', + 'MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK', + 'MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK', + 'MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT', + 'MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK', + 'MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT', + 'MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK', + 'MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT', + 'MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK', + 'MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK', + 'MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK', + 'MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT', + 'MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK', + 'MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT', + 'MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__L2_BUSY_MASK', 'MMVM_L2_STATUS__L2_BUSY__SHIFT', + 'MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK', + 'MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT', + 'MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK', + 'MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT', + 'MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK', + 'MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT', + 'MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK', + 'MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT', + 'MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK', + 'MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT', + 'MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK', + 'MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT', + 'MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'MM_ATC_L2_CNTL2__BANK_SELECT_MASK', + 'MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT', + 'MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK', + 'MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT', + 'MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK', + 'MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT', + 'MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK', + 'MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT', + 'MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK', + 'MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT', + 'MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK', + 'MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT', + 'MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK', + 'MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT', + 'MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK', + 'MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT', + 'MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK', + 'MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT', + 'MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK', + 'MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT', + 'MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK', + 'MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT', + 'MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK', + 'MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT', + 'MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK', + 'MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT', + 'MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK', + 'MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT', + 'MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK', + 'MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT', + 'MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK', + 'MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT', + 'MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK', + 'MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT', + 'MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK', + 'MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT', + 'MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK', + 'MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT', + 'MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK', + 'MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK', + 'MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT', + 'MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK', + 'MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT', + 'MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK', + 'MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT', + 'MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK', + 'MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT', + 'MM_ATC_L2_MISC_CG__ENABLE_MASK', + 'MM_ATC_L2_MISC_CG__ENABLE__SHIFT', + 'MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK', + 'MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT', + 'MM_ATC_L2_MISC_CG__OFFDLY_MASK', + 'MM_ATC_L2_MISC_CG__OFFDLY__SHIFT', + 'MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK', + 'MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT', + 'MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK', + 'MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT', + 'MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK', + 'MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT', + 'MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK', + 'MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT', + 'MM_ATC_L2_STATUS__BUSY_MASK', 'MM_ATC_L2_STATUS__BUSY__SHIFT', + 'MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK', + 'MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT', + 'PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK', + 'PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT', + 'PCTL_CTRL__PG_ENABLE_MASK', 'PCTL_CTRL__PG_ENABLE__SHIFT', + 'PCTL_CTRL__SDP_DISCONNECT_MODE_MASK', + 'PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT', + 'PCTL_CTRL__SNR_DISABLE_MASK', 'PCTL_CTRL__SNR_DISABLE__SHIFT', + 'PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK', + 'PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT', + 'PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK', + 'PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT', + 'PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK', + 'PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT', + 'PCTL_CTRL__UTCL2_LEGACY_MODE_MASK', + 'PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT', + 'PCTL_CTRL__WRACK_GUARD_MASK', 'PCTL_CTRL__WRACK_GUARD__SHIFT', + 'PCTL_CTRL__Z9_PWRDOWN_MASK', 'PCTL_CTRL__Z9_PWRDOWN__SHIFT', + 'PCTL_CTRL__Z9_PWRUP_MASK', 'PCTL_CTRL__Z9_PWRUP__SHIFT', + 'PCTL_CTRL__ZSC_TIMER_ENABLE_MASK', + 'PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__CLEAR_MASK', + 'PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__ENABLE_MASK', + 'PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__CLEAR_MASK', + 'PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__ENABLE_MASK', + 'PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_RESERVED_0__BIT0_MASK', 'PCTL_RESERVED_0__BIT0__SHIFT', + 'PCTL_RESERVED_0__BIT1_MASK', 'PCTL_RESERVED_0__BIT1__SHIFT', + 'PCTL_RESERVED_0__BIT2_MASK', 'PCTL_RESERVED_0__BIT2__SHIFT', + 'PCTL_RESERVED_0__BIT3_MASK', 'PCTL_RESERVED_0__BIT3__SHIFT', + 'PCTL_RESERVED_0__BIT4_MASK', 'PCTL_RESERVED_0__BIT4__SHIFT', + 'PCTL_RESERVED_0__BIT5_MASK', 'PCTL_RESERVED_0__BIT5__SHIFT', + 'PCTL_RESERVED_0__BIT6_MASK', 'PCTL_RESERVED_0__BIT6__SHIFT', + 'PCTL_RESERVED_0__BIT7_MASK', 'PCTL_RESERVED_0__BIT7__SHIFT', + 'PCTL_RESERVED_0__BYTE_MASK', 'PCTL_RESERVED_0__BYTE__SHIFT', + 'PCTL_RESERVED_0__WORD_MASK', 'PCTL_RESERVED_0__WORD__SHIFT', + 'PCTL_RESERVED_1__BIT0_MASK', 'PCTL_RESERVED_1__BIT0__SHIFT', + 'PCTL_RESERVED_1__BIT1_MASK', 'PCTL_RESERVED_1__BIT1__SHIFT', + 'PCTL_RESERVED_1__BIT2_MASK', 'PCTL_RESERVED_1__BIT2__SHIFT', + 'PCTL_RESERVED_1__BIT3_MASK', 'PCTL_RESERVED_1__BIT3__SHIFT', + 'PCTL_RESERVED_1__BIT4_MASK', 'PCTL_RESERVED_1__BIT4__SHIFT', + 'PCTL_RESERVED_1__BIT5_MASK', 'PCTL_RESERVED_1__BIT5__SHIFT', + 'PCTL_RESERVED_1__BIT6_MASK', 'PCTL_RESERVED_1__BIT6__SHIFT', + 'PCTL_RESERVED_1__BIT7_MASK', 'PCTL_RESERVED_1__BIT7__SHIFT', + 'PCTL_RESERVED_1__BYTE_MASK', 'PCTL_RESERVED_1__BYTE__SHIFT', + 'PCTL_RESERVED_1__WORD_MASK', 'PCTL_RESERVED_1__WORD__SHIFT', + 'PCTL_RESERVED_2__BIT0_MASK', 'PCTL_RESERVED_2__BIT0__SHIFT', + 'PCTL_RESERVED_2__BIT1_MASK', 'PCTL_RESERVED_2__BIT1__SHIFT', + 'PCTL_RESERVED_2__BIT2_MASK', 'PCTL_RESERVED_2__BIT2__SHIFT', + 'PCTL_RESERVED_2__BIT3_MASK', 'PCTL_RESERVED_2__BIT3__SHIFT', + 'PCTL_RESERVED_2__BIT4_MASK', 'PCTL_RESERVED_2__BIT4__SHIFT', + 'PCTL_RESERVED_2__BIT5_MASK', 'PCTL_RESERVED_2__BIT5__SHIFT', + 'PCTL_RESERVED_2__BIT6_MASK', 'PCTL_RESERVED_2__BIT6__SHIFT', + 'PCTL_RESERVED_2__BIT7_MASK', 'PCTL_RESERVED_2__BIT7__SHIFT', + 'PCTL_RESERVED_2__BYTE_MASK', 'PCTL_RESERVED_2__BYTE__SHIFT', + 'PCTL_RESERVED_2__WORD_MASK', 'PCTL_RESERVED_2__WORD__SHIFT', + 'PCTL_RESERVED_3__BIT0_MASK', 'PCTL_RESERVED_3__BIT0__SHIFT', + 'PCTL_RESERVED_3__BIT1_MASK', 'PCTL_RESERVED_3__BIT1__SHIFT', + 'PCTL_RESERVED_3__BIT2_MASK', 'PCTL_RESERVED_3__BIT2__SHIFT', + 'PCTL_RESERVED_3__BIT3_MASK', 'PCTL_RESERVED_3__BIT3__SHIFT', + 'PCTL_RESERVED_3__BIT4_MASK', 'PCTL_RESERVED_3__BIT4__SHIFT', + 'PCTL_RESERVED_3__BIT5_MASK', 'PCTL_RESERVED_3__BIT5__SHIFT', + 'PCTL_RESERVED_3__BIT6_MASK', 'PCTL_RESERVED_3__BIT6__SHIFT', + 'PCTL_RESERVED_3__BIT7_MASK', 'PCTL_RESERVED_3__BIT7__SHIFT', + 'PCTL_RESERVED_3__BYTE_MASK', 'PCTL_RESERVED_3__BYTE__SHIFT', + 'PCTL_RESERVED_3__WORD_MASK', 'PCTL_RESERVED_3__WORD__SHIFT', + 'PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT', + 'PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK', + 'PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT', + 'PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK', + 'PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT', + 'PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK', + 'PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK', + 'PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT', + 'PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK', + 'PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT', + 'PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK', + 'PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK', + 'PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT', + 'PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK', + 'PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT', + 'PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK', + 'PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT', + 'PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK', + 'PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT', + 'PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK', + 'PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK', + 'PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT', + 'PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK', + 'PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT', + 'PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK', + 'PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK', + 'PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT', + 'PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK', + 'PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_STATUS__MMHUB_CONFIG_DONE_MASK', + 'PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT', + 'PCTL_STATUS__MMHUB_FENCE_ACK_MASK', + 'PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT', + 'PCTL_STATUS__MMHUB_FENCE_REQ_MASK', + 'PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT', + 'PCTL_STATUS__MMHUB_IDLE_MASK', 'PCTL_STATUS__MMHUB_IDLE__SHIFT', + 'PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK', + 'PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT', + 'PCTL_STATUS__MMHUB_POWER_MASK', + 'PCTL_STATUS__MMHUB_POWER__SHIFT', + 'PCTL_STATUS__PGFSM_CMD_STATUS_MASK', + 'PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT', + 'PCTL_STATUS__RENG_RAM_STALE_MASK', + 'PCTL_STATUS__RENG_RAM_STALE__SHIFT', + 'PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK', + 'PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT', + 'PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK', + 'PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT', + 'PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK', + 'PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT', + 'PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK', + 'PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT', + 'PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK', + 'PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK', + 'PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT', + 'PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK', + 'PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT', + 'PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK', + 'PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK', + 'PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT', + 'PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK', + 'PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + '_mmhub_3_0_0_OFFSET_HEADER', '_mmhub_3_0_0_SH_MASK_HEADER', + 'regDAGB0_CNTL_MISC', 'regDAGB0_CNTL_MISC2', + 'regDAGB0_CNTL_MISC2_BASE_IDX', 'regDAGB0_CNTL_MISC_BASE_IDX', + 'regDAGB0_DAGB_DLY', 'regDAGB0_DAGB_DLY_BASE_IDX', + 'regDAGB0_FATAL_ERROR_CLEAR', + 'regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX', + 'regDAGB0_FATAL_ERROR_CNTL', 'regDAGB0_FATAL_ERROR_CNTL_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS0', + 'regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS1', + 'regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS2', + 'regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS3', + 'regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS4', + 'regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX', 'regDAGB0_FIFO_EMPTY', + 'regDAGB0_FIFO_EMPTY_BASE_IDX', 'regDAGB0_FIFO_FULL', + 'regDAGB0_FIFO_FULL_BASE_IDX', 'regDAGB0_L1TLB_RD_CGTT_CLK_CTRL', + 'regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_L1TLB_REG_RW', 'regDAGB0_L1TLB_REG_RW_BASE_IDX', + 'regDAGB0_L1TLB_WR_CGTT_CLK_CTRL', + 'regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_PERFCOUNTER0_CFG', 'regDAGB0_PERFCOUNTER0_CFG_BASE_IDX', + 'regDAGB0_PERFCOUNTER1_CFG', 'regDAGB0_PERFCOUNTER1_CFG_BASE_IDX', + 'regDAGB0_PERFCOUNTER2_CFG', 'regDAGB0_PERFCOUNTER2_CFG_BASE_IDX', + 'regDAGB0_PERFCOUNTER_HI', 'regDAGB0_PERFCOUNTER_HI_BASE_IDX', + 'regDAGB0_PERFCOUNTER_LO', 'regDAGB0_PERFCOUNTER_LO_BASE_IDX', + 'regDAGB0_PERFCOUNTER_RSLT_CNTL', + 'regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regDAGB0_RDCLI0', + 'regDAGB0_RDCLI0_BASE_IDX', 'regDAGB0_RDCLI1', 'regDAGB0_RDCLI10', + 'regDAGB0_RDCLI10_BASE_IDX', 'regDAGB0_RDCLI11', + 'regDAGB0_RDCLI11_BASE_IDX', 'regDAGB0_RDCLI12', + 'regDAGB0_RDCLI12_BASE_IDX', 'regDAGB0_RDCLI13', + 'regDAGB0_RDCLI13_BASE_IDX', 'regDAGB0_RDCLI14', + 'regDAGB0_RDCLI14_BASE_IDX', 'regDAGB0_RDCLI15', + 'regDAGB0_RDCLI15_BASE_IDX', 'regDAGB0_RDCLI16', + 'regDAGB0_RDCLI16_BASE_IDX', 'regDAGB0_RDCLI17', + 'regDAGB0_RDCLI17_BASE_IDX', 'regDAGB0_RDCLI18', + 'regDAGB0_RDCLI18_BASE_IDX', 'regDAGB0_RDCLI19', + 'regDAGB0_RDCLI19_BASE_IDX', 'regDAGB0_RDCLI1_BASE_IDX', + 'regDAGB0_RDCLI2', 'regDAGB0_RDCLI20', + 'regDAGB0_RDCLI20_BASE_IDX', 'regDAGB0_RDCLI21', + 'regDAGB0_RDCLI21_BASE_IDX', 'regDAGB0_RDCLI22', + 'regDAGB0_RDCLI22_BASE_IDX', 'regDAGB0_RDCLI23', + 'regDAGB0_RDCLI23_BASE_IDX', 'regDAGB0_RDCLI2_BASE_IDX', + 'regDAGB0_RDCLI3', 'regDAGB0_RDCLI3_BASE_IDX', 'regDAGB0_RDCLI4', + 'regDAGB0_RDCLI4_BASE_IDX', 'regDAGB0_RDCLI5', + 'regDAGB0_RDCLI5_BASE_IDX', 'regDAGB0_RDCLI6', + 'regDAGB0_RDCLI6_BASE_IDX', 'regDAGB0_RDCLI7', + 'regDAGB0_RDCLI7_BASE_IDX', 'regDAGB0_RDCLI8', + 'regDAGB0_RDCLI8_BASE_IDX', 'regDAGB0_RDCLI9', + 'regDAGB0_RDCLI9_BASE_IDX', 'regDAGB0_RDCLI_ASK2ARB_PENDING', + 'regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_ASK2DF_PENDING', + 'regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_ASK_OSD_PENDING', + 'regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_ASK_PENDING', + 'regDAGB0_RDCLI_ASK_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_GBLSEND_PENDING', + 'regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_GO_PENDING', 'regDAGB0_RDCLI_GO_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB0_RDCLI_OARB_PENDING', + 'regDAGB0_RDCLI_OARB_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_OSD_PENDING', + 'regDAGB0_RDCLI_OSD_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_TLB_PENDING', + 'regDAGB0_RDCLI_TLB_PENDING_BASE_IDX', 'regDAGB0_RD_ADDR_DAGB', + 'regDAGB0_RD_ADDR_DAGB_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST0', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST1', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST2', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB0_RD_CGTT_CLK_CTRL', 'regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_RD_CNTL', 'regDAGB0_RD_CNTL_BASE_IDX', + 'regDAGB0_RD_CNTL_MISC', 'regDAGB0_RD_CNTL_MISC_BASE_IDX', + 'regDAGB0_RD_CREDITS_FULL', 'regDAGB0_RD_CREDITS_FULL_BASE_IDX', + 'regDAGB0_RD_GMI_CNTL', 'regDAGB0_RD_GMI_CNTL_BASE_IDX', + 'regDAGB0_RD_GMI_VC_CNTL', 'regDAGB0_RD_GMI_VC_CNTL_BASE_IDX', + 'regDAGB0_RD_IO_CNTL', 'regDAGB0_RD_IO_CNTL_BASE_IDX', + 'regDAGB0_RD_IO_VC_CNTL', 'regDAGB0_RD_IO_VC_CNTL_BASE_IDX', + 'regDAGB0_RD_RDRET_CREDIT_CNTL', 'regDAGB0_RD_RDRET_CREDIT_CNTL2', + 'regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX', + 'regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX', + 'regDAGB0_RD_TLB_CREDIT', 'regDAGB0_RD_TLB_CREDIT_BASE_IDX', + 'regDAGB0_RD_VC0_CNTL', 'regDAGB0_RD_VC0_CNTL_BASE_IDX', + 'regDAGB0_RD_VC1_CNTL', 'regDAGB0_RD_VC1_CNTL_BASE_IDX', + 'regDAGB0_RD_VC2_CNTL', 'regDAGB0_RD_VC2_CNTL_BASE_IDX', + 'regDAGB0_RD_VC3_CNTL', 'regDAGB0_RD_VC3_CNTL_BASE_IDX', + 'regDAGB0_RD_VC4_CNTL', 'regDAGB0_RD_VC4_CNTL_BASE_IDX', + 'regDAGB0_RD_VC5_CNTL', 'regDAGB0_RD_VC5_CNTL_BASE_IDX', + 'regDAGB0_RESERVE1', 'regDAGB0_RESERVE1_BASE_IDX', + 'regDAGB0_RESERVE2', 'regDAGB0_RESERVE2_BASE_IDX', + 'regDAGB0_RESERVE3', 'regDAGB0_RESERVE3_BASE_IDX', + 'regDAGB0_RESERVE4', 'regDAGB0_RESERVE4_BASE_IDX', + 'regDAGB0_SDP_ARB_CNTL0', 'regDAGB0_SDP_ARB_CNTL0_BASE_IDX', + 'regDAGB0_SDP_ARB_CNTL1', 'regDAGB0_SDP_ARB_CNTL1_BASE_IDX', + 'regDAGB0_SDP_CGTT_CLK_CTRL', + 'regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX', 'regDAGB0_SDP_CREDITS', + 'regDAGB0_SDP_CREDITS_BASE_IDX', 'regDAGB0_SDP_ENABLE', + 'regDAGB0_SDP_ENABLE_BASE_IDX', 'regDAGB0_SDP_ERR_STATUS', + 'regDAGB0_SDP_ERR_STATUS_BASE_IDX', + 'regDAGB0_SDP_LATENCY_SAMPLING', + 'regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX', 'regDAGB0_SDP_MISC', + 'regDAGB0_SDP_MISC2', 'regDAGB0_SDP_MISC2_BASE_IDX', + 'regDAGB0_SDP_MISC_BASE_IDX', 'regDAGB0_SDP_PRIORITY_OVERRIDE', + 'regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX', + 'regDAGB0_SDP_RD_BW_CNTL', 'regDAGB0_SDP_RD_BW_CNTL_BASE_IDX', + 'regDAGB0_SDP_RD_CLI2SDP_VC_MAP', + 'regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX', + 'regDAGB0_SDP_RD_PRIORITY', 'regDAGB0_SDP_RD_PRIORITY_BASE_IDX', + 'regDAGB0_SDP_REQ_CNTL', 'regDAGB0_SDP_REQ_CNTL_BASE_IDX', + 'regDAGB0_SDP_TAG_RESERVE0', 'regDAGB0_SDP_TAG_RESERVE0_BASE_IDX', + 'regDAGB0_SDP_TAG_RESERVE1', 'regDAGB0_SDP_TAG_RESERVE1_BASE_IDX', + 'regDAGB0_SDP_VCC_RESERVE0', 'regDAGB0_SDP_VCC_RESERVE0_BASE_IDX', + 'regDAGB0_SDP_VCC_RESERVE1', 'regDAGB0_SDP_VCC_RESERVE1_BASE_IDX', + 'regDAGB0_SDP_VCD_RESERVE0', 'regDAGB0_SDP_VCD_RESERVE0_BASE_IDX', + 'regDAGB0_SDP_VCD_RESERVE1', 'regDAGB0_SDP_VCD_RESERVE1_BASE_IDX', + 'regDAGB0_SDP_WR_CLI2SDP_VC_MAP', + 'regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX', + 'regDAGB0_SDP_WR_PRIORITY', 'regDAGB0_SDP_WR_PRIORITY_BASE_IDX', + 'regDAGB0_WRCLI0', 'regDAGB0_WRCLI0_BASE_IDX', 'regDAGB0_WRCLI1', + 'regDAGB0_WRCLI10', 'regDAGB0_WRCLI10_BASE_IDX', + 'regDAGB0_WRCLI11', 'regDAGB0_WRCLI11_BASE_IDX', + 'regDAGB0_WRCLI12', 'regDAGB0_WRCLI12_BASE_IDX', + 'regDAGB0_WRCLI13', 'regDAGB0_WRCLI13_BASE_IDX', + 'regDAGB0_WRCLI14', 'regDAGB0_WRCLI14_BASE_IDX', + 'regDAGB0_WRCLI15', 'regDAGB0_WRCLI15_BASE_IDX', + 'regDAGB0_WRCLI16', 'regDAGB0_WRCLI16_BASE_IDX', + 'regDAGB0_WRCLI17', 'regDAGB0_WRCLI17_BASE_IDX', + 'regDAGB0_WRCLI18', 'regDAGB0_WRCLI18_BASE_IDX', + 'regDAGB0_WRCLI19', 'regDAGB0_WRCLI19_BASE_IDX', + 'regDAGB0_WRCLI1_BASE_IDX', 'regDAGB0_WRCLI2', 'regDAGB0_WRCLI20', + 'regDAGB0_WRCLI20_BASE_IDX', 'regDAGB0_WRCLI21', + 'regDAGB0_WRCLI21_BASE_IDX', 'regDAGB0_WRCLI22', + 'regDAGB0_WRCLI22_BASE_IDX', 'regDAGB0_WRCLI23', + 'regDAGB0_WRCLI23_BASE_IDX', 'regDAGB0_WRCLI2_BASE_IDX', + 'regDAGB0_WRCLI3', 'regDAGB0_WRCLI3_BASE_IDX', 'regDAGB0_WRCLI4', + 'regDAGB0_WRCLI4_BASE_IDX', 'regDAGB0_WRCLI5', + 'regDAGB0_WRCLI5_BASE_IDX', 'regDAGB0_WRCLI6', + 'regDAGB0_WRCLI6_BASE_IDX', 'regDAGB0_WRCLI7', + 'regDAGB0_WRCLI7_BASE_IDX', 'regDAGB0_WRCLI8', + 'regDAGB0_WRCLI8_BASE_IDX', 'regDAGB0_WRCLI9', + 'regDAGB0_WRCLI9_BASE_IDX', 'regDAGB0_WRCLI_ASK2ARB_PENDING', + 'regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_ASK2DF_PENDING', + 'regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_ASK_OSD_PENDING', + 'regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_ASK_PENDING', + 'regDAGB0_WRCLI_ASK_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_DBUS_ASK_PENDING', + 'regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_DBUS_GO_PENDING', + 'regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_GBLSEND_PENDING', + 'regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_GO_PENDING', 'regDAGB0_WRCLI_GO_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB0_WRCLI_OARB_PENDING', + 'regDAGB0_WRCLI_OARB_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_OSD_PENDING', + 'regDAGB0_WRCLI_OSD_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_TLB_PENDING', + 'regDAGB0_WRCLI_TLB_PENDING_BASE_IDX', 'regDAGB0_WR_ADDR_DAGB', + 'regDAGB0_WR_ADDR_DAGB_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST0', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST1', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST2', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1', + 'regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX', + 'regDAGB0_WR_CGTT_CLK_CTRL', 'regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_WR_CNTL', 'regDAGB0_WR_CNTL_BASE_IDX', + 'regDAGB0_WR_CNTL_MISC', 'regDAGB0_WR_CNTL_MISC_BASE_IDX', + 'regDAGB0_WR_CREDITS_FULL', 'regDAGB0_WR_CREDITS_FULL_BASE_IDX', + 'regDAGB0_WR_DATA_CREDIT', 'regDAGB0_WR_DATA_CREDIT_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB', 'regDAGB0_WR_DATA_DAGB_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER0', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER1', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER2', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST0', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST1', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST2', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1', + 'regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX', + 'regDAGB0_WR_GMI_CNTL', 'regDAGB0_WR_GMI_CNTL_BASE_IDX', + 'regDAGB0_WR_GMI_VC_CNTL', 'regDAGB0_WR_GMI_VC_CNTL_BASE_IDX', + 'regDAGB0_WR_IO_CNTL', 'regDAGB0_WR_IO_CNTL_BASE_IDX', + 'regDAGB0_WR_IO_VC_CNTL', 'regDAGB0_WR_IO_VC_CNTL_BASE_IDX', + 'regDAGB0_WR_MISC_CREDIT', 'regDAGB0_WR_MISC_CREDIT_BASE_IDX', + 'regDAGB0_WR_TLB_CREDIT', 'regDAGB0_WR_TLB_CREDIT_BASE_IDX', + 'regDAGB0_WR_VC0_CNTL', 'regDAGB0_WR_VC0_CNTL_BASE_IDX', + 'regDAGB0_WR_VC1_CNTL', 'regDAGB0_WR_VC1_CNTL_BASE_IDX', + 'regDAGB0_WR_VC2_CNTL', 'regDAGB0_WR_VC2_CNTL_BASE_IDX', + 'regDAGB0_WR_VC3_CNTL', 'regDAGB0_WR_VC3_CNTL_BASE_IDX', + 'regDAGB0_WR_VC4_CNTL', 'regDAGB0_WR_VC4_CNTL_BASE_IDX', + 'regDAGB0_WR_VC5_CNTL', 'regDAGB0_WR_VC5_CNTL_BASE_IDX', + 'regDAGB1_CNTL_MISC', 'regDAGB1_CNTL_MISC2', + 'regDAGB1_CNTL_MISC2_BASE_IDX', 'regDAGB1_CNTL_MISC_BASE_IDX', + 'regDAGB1_DAGB_DLY', 'regDAGB1_DAGB_DLY_BASE_IDX', + 'regDAGB1_FIFO_EMPTY', 'regDAGB1_FIFO_EMPTY_BASE_IDX', + 'regDAGB1_FIFO_FULL', 'regDAGB1_FIFO_FULL_BASE_IDX', + 'regDAGB1_L1TLB_RD_CGTT_CLK_CTRL', + 'regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB1_L1TLB_REG_RW', 'regDAGB1_L1TLB_REG_RW_BASE_IDX', + 'regDAGB1_PERFCOUNTER0_CFG', 'regDAGB1_PERFCOUNTER0_CFG_BASE_IDX', + 'regDAGB1_PERFCOUNTER1_CFG', 'regDAGB1_PERFCOUNTER1_CFG_BASE_IDX', + 'regDAGB1_PERFCOUNTER2_CFG', 'regDAGB1_PERFCOUNTER2_CFG_BASE_IDX', + 'regDAGB1_PERFCOUNTER_HI', 'regDAGB1_PERFCOUNTER_HI_BASE_IDX', + 'regDAGB1_PERFCOUNTER_LO', 'regDAGB1_PERFCOUNTER_LO_BASE_IDX', + 'regDAGB1_PERFCOUNTER_RSLT_CNTL', + 'regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regDAGB1_RDCLI0', + 'regDAGB1_RDCLI0_BASE_IDX', 'regDAGB1_RDCLI1', 'regDAGB1_RDCLI10', + 'regDAGB1_RDCLI10_BASE_IDX', 'regDAGB1_RDCLI11', + 'regDAGB1_RDCLI11_BASE_IDX', 'regDAGB1_RDCLI12', + 'regDAGB1_RDCLI12_BASE_IDX', 'regDAGB1_RDCLI13', + 'regDAGB1_RDCLI13_BASE_IDX', 'regDAGB1_RDCLI14', + 'regDAGB1_RDCLI14_BASE_IDX', 'regDAGB1_RDCLI15', + 'regDAGB1_RDCLI15_BASE_IDX', 'regDAGB1_RDCLI16', + 'regDAGB1_RDCLI16_BASE_IDX', 'regDAGB1_RDCLI17', + 'regDAGB1_RDCLI17_BASE_IDX', 'regDAGB1_RDCLI18', + 'regDAGB1_RDCLI18_BASE_IDX', 'regDAGB1_RDCLI19', + 'regDAGB1_RDCLI19_BASE_IDX', 'regDAGB1_RDCLI1_BASE_IDX', + 'regDAGB1_RDCLI2', 'regDAGB1_RDCLI20', + 'regDAGB1_RDCLI20_BASE_IDX', 'regDAGB1_RDCLI21', + 'regDAGB1_RDCLI21_BASE_IDX', 'regDAGB1_RDCLI22', + 'regDAGB1_RDCLI22_BASE_IDX', 'regDAGB1_RDCLI23', + 'regDAGB1_RDCLI23_BASE_IDX', 'regDAGB1_RDCLI2_BASE_IDX', + 'regDAGB1_RDCLI3', 'regDAGB1_RDCLI3_BASE_IDX', 'regDAGB1_RDCLI4', + 'regDAGB1_RDCLI4_BASE_IDX', 'regDAGB1_RDCLI5', + 'regDAGB1_RDCLI5_BASE_IDX', 'regDAGB1_RDCLI6', + 'regDAGB1_RDCLI6_BASE_IDX', 'regDAGB1_RDCLI7', + 'regDAGB1_RDCLI7_BASE_IDX', 'regDAGB1_RDCLI8', + 'regDAGB1_RDCLI8_BASE_IDX', 'regDAGB1_RDCLI9', + 'regDAGB1_RDCLI9_BASE_IDX', 'regDAGB1_RDCLI_ASK2ARB_PENDING', + 'regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_ASK2DF_PENDING', + 'regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_ASK_OSD_PENDING', + 'regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_ASK_PENDING', + 'regDAGB1_RDCLI_ASK_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_GBLSEND_PENDING', + 'regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_GO_PENDING', 'regDAGB1_RDCLI_GO_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB1_RDCLI_OARB_PENDING', + 'regDAGB1_RDCLI_OARB_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_OSD_PENDING', + 'regDAGB1_RDCLI_OSD_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_TLB_PENDING', + 'regDAGB1_RDCLI_TLB_PENDING_BASE_IDX', 'regDAGB1_RD_ADDR_DAGB', + 'regDAGB1_RD_ADDR_DAGB_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST0', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST1', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST2', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB1_RD_CGTT_CLK_CTRL', 'regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB1_RD_CNTL', 'regDAGB1_RD_CNTL_BASE_IDX', + 'regDAGB1_RD_CNTL_MISC', 'regDAGB1_RD_CNTL_MISC_BASE_IDX', + 'regDAGB1_RD_CREDITS_FULL', 'regDAGB1_RD_CREDITS_FULL_BASE_IDX', + 'regDAGB1_RD_GMI_CNTL', 'regDAGB1_RD_GMI_CNTL_BASE_IDX', + 'regDAGB1_RD_GMI_VC_CNTL', 'regDAGB1_RD_GMI_VC_CNTL_BASE_IDX', + 'regDAGB1_RD_IO_CNTL', 'regDAGB1_RD_IO_CNTL_BASE_IDX', + 'regDAGB1_RD_IO_VC_CNTL', 'regDAGB1_RD_IO_VC_CNTL_BASE_IDX', + 'regDAGB1_RD_RDRET_CREDIT_CNTL', 'regDAGB1_RD_RDRET_CREDIT_CNTL2', + 'regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX', + 'regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX', + 'regDAGB1_RD_TLB_CREDIT', 'regDAGB1_RD_TLB_CREDIT_BASE_IDX', + 'regDAGB1_RD_VC0_CNTL', 'regDAGB1_RD_VC0_CNTL_BASE_IDX', + 'regDAGB1_RD_VC1_CNTL', 'regDAGB1_RD_VC1_CNTL_BASE_IDX', + 'regDAGB1_RD_VC2_CNTL', 'regDAGB1_RD_VC2_CNTL_BASE_IDX', + 'regDAGB1_RD_VC3_CNTL', 'regDAGB1_RD_VC3_CNTL_BASE_IDX', + 'regDAGB1_RD_VC4_CNTL', 'regDAGB1_RD_VC4_CNTL_BASE_IDX', + 'regDAGB1_RD_VC5_CNTL', 'regDAGB1_RD_VC5_CNTL_BASE_IDX', + 'regDAGB1_RESERVE1', 'regDAGB1_RESERVE1_BASE_IDX', + 'regDAGB1_RESERVE2', 'regDAGB1_RESERVE2_BASE_IDX', + 'regDAGB1_RESERVE3', 'regDAGB1_RESERVE3_BASE_IDX', + 'regDAGB1_RESERVE4', 'regDAGB1_RESERVE4_BASE_IDX', + 'regDAGB1_SDP_ARB_CNTL0', 'regDAGB1_SDP_ARB_CNTL0_BASE_IDX', + 'regDAGB1_SDP_ARB_CNTL1', 'regDAGB1_SDP_ARB_CNTL1_BASE_IDX', + 'regDAGB1_SDP_CGTT_CLK_CTRL', + 'regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX', 'regDAGB1_SDP_CREDITS', + 'regDAGB1_SDP_CREDITS_BASE_IDX', 'regDAGB1_SDP_ENABLE', + 'regDAGB1_SDP_ENABLE_BASE_IDX', 'regDAGB1_SDP_ERR_STATUS', + 'regDAGB1_SDP_ERR_STATUS_BASE_IDX', + 'regDAGB1_SDP_LATENCY_SAMPLING', + 'regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX', 'regDAGB1_SDP_MISC', + 'regDAGB1_SDP_MISC2', 'regDAGB1_SDP_MISC2_BASE_IDX', + 'regDAGB1_SDP_MISC_BASE_IDX', 'regDAGB1_SDP_PRIORITY_OVERRIDE', + 'regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX', + 'regDAGB1_SDP_RD_BW_CNTL', 'regDAGB1_SDP_RD_BW_CNTL_BASE_IDX', + 'regDAGB1_SDP_RD_CLI2SDP_VC_MAP', + 'regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX', + 'regDAGB1_SDP_RD_PRIORITY', 'regDAGB1_SDP_RD_PRIORITY_BASE_IDX', + 'regDAGB1_SDP_REQ_CNTL', 'regDAGB1_SDP_REQ_CNTL_BASE_IDX', + 'regDAGB1_SDP_TAG_RESERVE0', 'regDAGB1_SDP_TAG_RESERVE0_BASE_IDX', + 'regDAGB1_SDP_TAG_RESERVE1', 'regDAGB1_SDP_TAG_RESERVE1_BASE_IDX', + 'regDAGB1_SDP_VCC_RESERVE0', 'regDAGB1_SDP_VCC_RESERVE0_BASE_IDX', + 'regDAGB1_SDP_VCC_RESERVE1', 'regDAGB1_SDP_VCC_RESERVE1_BASE_IDX', + 'regMML2TLB_PERFCOUNTER0_CFG', + 'regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX', + 'regMML2TLB_PERFCOUNTER1_CFG', + 'regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX', + 'regMML2TLB_PERFCOUNTER2_CFG', + 'regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX', + 'regMML2TLB_PERFCOUNTER3_CFG', + 'regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX', + 'regMML2TLB_PERFCOUNTER_HI', 'regMML2TLB_PERFCOUNTER_HI_BASE_IDX', + 'regMML2TLB_PERFCOUNTER_LO', 'regMML2TLB_PERFCOUNTER_LO_BASE_IDX', + 'regMML2TLB_PERFCOUNTER_RSLT_CNTL', + 'regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMML2TLB_TLB0_STATUS', 'regMML2TLB_TLB0_STATUS_BASE_IDX', + 'regMML2TLB_TMZ_CNTL', 'regMML2TLB_TMZ_CNTL_BASE_IDX', + 'regMMMC_MEM_POWER_LS', 'regMMMC_MEM_POWER_LS_BASE_IDX', + 'regMMMC_VM_AGP_BASE', 'regMMMC_VM_AGP_BASE_BASE_IDX', + 'regMMMC_VM_AGP_BOT', 'regMMMC_VM_AGP_BOT_BASE_IDX', + 'regMMMC_VM_AGP_TOP', 'regMMMC_VM_AGP_TOP_BASE_IDX', + 'regMMMC_VM_APT_CNTL', 'regMMMC_VM_APT_CNTL_BASE_IDX', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', + 'regMMMC_VM_FB_LOCATION_BASE', + 'regMMMC_VM_FB_LOCATION_BASE_BASE_IDX', + 'regMMMC_VM_FB_LOCATION_TOP', + 'regMMMC_VM_FB_LOCATION_TOP_BASE_IDX', + 'regMMMC_VM_FB_NOALLOC_CNTL', + 'regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX', 'regMMMC_VM_FB_OFFSET', + 'regMMMC_VM_FB_OFFSET_BASE_IDX', 'regMMMC_VM_FB_SIZE_OFFSET_VF0', + 'regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF1', 'regMMMC_VM_FB_SIZE_OFFSET_VF10', + 'regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF11', + 'regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF12', + 'regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF13', + 'regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF14', + 'regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF15', + 'regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF2', + 'regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF3', + 'regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF4', + 'regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF5', + 'regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF6', + 'regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF7', + 'regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF8', + 'regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF9', + 'regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER0_CFG', + 'regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER1_CFG', + 'regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER2_CFG', + 'regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER3_CFG', + 'regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER4_CFG', + 'regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER5_CFG', + 'regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER6_CFG', + 'regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER7_CFG', + 'regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER_HI', + 'regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER_LO', + 'regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL', + 'regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMMMC_VM_LOCAL_FB_ADDRESS_END', + 'regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX', + 'regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL', + 'regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX', + 'regMMMC_VM_LOCAL_FB_ADDRESS_START', + 'regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER0_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER1_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER2_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER3_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER_HI', + 'regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER_LO', + 'regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL', + 'regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB0_STATUS', + 'regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB1_STATUS', + 'regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB2_STATUS', + 'regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB3_STATUS', + 'regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB4_STATUS', + 'regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB5_STATUS', + 'regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB_CNTL', 'regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX', + 'regMMMC_VM_STEERING', 'regMMMC_VM_STEERING_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR', + 'regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR', + 'regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', + 'regMMUTCL2_CGTT_BUSY_CTRL', 'regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX', + 'regMMUTCL2_CGTT_CLK_CTRL', 'regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX', + 'regMMUTCL2_FFBM_ACCESS_CNTL', + 'regMMUTCL2_FFBM_ACCESS_CNTL_BASE_IDX', 'regMMUTCL2_FFBM_ADDRESS', + 'regMMUTCL2_FFBM_ADDRESS_BASE_IDX', 'regMMUTCL2_FFBM_CONFIG', + 'regMMUTCL2_FFBM_CONFIG_BASE_IDX', 'regMMUTCL2_FFBM_DATA', + 'regMMUTCL2_FFBM_DATA_BASE_IDX', 'regMMUTCL2_FFBM_ENABLE_CNTL', + 'regMMUTCL2_FFBM_ENABLE_CNTL_BASE_IDX', + 'regMMUTCL2_FFBM_INVALIDATE_REQUEST', + 'regMMUTCL2_FFBM_INVALIDATE_REQUEST_BASE_IDX', + 'regMMUTCL2_FFBM_INVALIDATE_RESPONSE', + 'regMMUTCL2_FFBM_INVALIDATE_RESPONSE_BASE_IDX', + 'regMMUTCL2_GROUP_RET_FAULT_STATUS', + 'regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX', + 'regMMUTCL2_HARVEST_BYPASS_GROUPS', + 'regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX', + 'regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ', + 'regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER0_CFG', + 'regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER1_CFG', + 'regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER2_CFG', + 'regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER3_CFG', + 'regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER_HI', 'regMMUTCL2_PERFCOUNTER_HI_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER_LO', 'regMMUTCL2_PERFCOUNTER_LO_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER_RSLT_CNTL', + 'regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMMUTCL2_TRANSLATION_BYPASS_BY_VMID', + 'regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', + 'regMMUTC_TRANSLATION_FAULT_CNTL0', + 'regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX', + 'regMMUTC_TRANSLATION_FAULT_CNTL1', + 'regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX', + 'regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT', + 'regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX', + 'regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ', + 'regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX', + 'regMMVM_CONTEXT0_CNTL', 'regMMVM_CONTEXT0_CNTL_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT10_CNTL', 'regMMVM_CONTEXT10_CNTL_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT11_CNTL', 'regMMVM_CONTEXT11_CNTL_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT12_CNTL', 'regMMVM_CONTEXT12_CNTL_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT13_CNTL', 'regMMVM_CONTEXT13_CNTL_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT14_CNTL', 'regMMVM_CONTEXT14_CNTL_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT15_CNTL', 'regMMVM_CONTEXT15_CNTL_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT1_CNTL', 'regMMVM_CONTEXT1_CNTL_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT2_CNTL', 'regMMVM_CONTEXT2_CNTL_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT3_CNTL', 'regMMVM_CONTEXT3_CNTL_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT4_CNTL', 'regMMVM_CONTEXT4_CNTL_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT5_CNTL', 'regMMVM_CONTEXT5_CNTL_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT6_CNTL', 'regMMVM_CONTEXT6_CNTL_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT7_CNTL', 'regMMVM_CONTEXT7_CNTL_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT8_CNTL', 'regMMVM_CONTEXT8_CNTL_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT9_CNTL', 'regMMVM_CONTEXT9_CNTL_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXTS_DISABLE', 'regMMVM_CONTEXTS_DISABLE_BASE_IDX', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', + 'regMMVM_DUMMY_PAGE_FAULT_CNTL', + 'regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', + 'regMMVM_INVALIDATE_CNTL', 'regMMVM_INVALIDATE_CNTL_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_ACK', + 'regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_REQ', + 'regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_SEM', + 'regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_ACK', + 'regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_REQ', + 'regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_SEM', + 'regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_ACK', + 'regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_REQ', + 'regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_SEM', + 'regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_ACK', + 'regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_REQ', + 'regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_SEM', + 'regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_ACK', + 'regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_REQ', + 'regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_SEM', + 'regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_ACK', + 'regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_REQ', + 'regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_SEM', + 'regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_ACK', + 'regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_REQ', + 'regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_SEM', + 'regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_ACK', + 'regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_REQ', + 'regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_SEM', + 'regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_ACK', + 'regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_REQ', + 'regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_SEM', + 'regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_ACK', + 'regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_REQ', + 'regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_SEM', + 'regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_ACK', + 'regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_REQ', + 'regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_SEM', + 'regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_ACK', + 'regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_REQ', + 'regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_SEM', + 'regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_ACK', + 'regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_REQ', + 'regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_SEM', + 'regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_ACK', + 'regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_REQ', + 'regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_SEM', + 'regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_ACK', + 'regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_REQ', + 'regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_SEM', + 'regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_ACK', + 'regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_REQ', + 'regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_SEM', + 'regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_ACK', + 'regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_REQ', + 'regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_SEM', + 'regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_ACK', + 'regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_REQ', + 'regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_SEM', + 'regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX', + 'regMMVM_L2_BANK_SELECT_MASKS', + 'regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID2', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', + 'regMMVM_L2_CACHE_PARITY_CNTL', + 'regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX', + 'regMMVM_L2_CGTT_BUSY_CTRL', 'regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX', + 'regMMVM_L2_CGTT_CLK_CTRL', 'regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX', + 'regMMVM_L2_CNTL', 'regMMVM_L2_CNTL2', + 'regMMVM_L2_CNTL2_BASE_IDX', 'regMMVM_L2_CNTL3', + 'regMMVM_L2_CNTL3_BASE_IDX', 'regMMVM_L2_CNTL4', + 'regMMVM_L2_CNTL4_BASE_IDX', 'regMMVM_L2_CNTL5', + 'regMMVM_L2_CNTL5_BASE_IDX', 'regMMVM_L2_CNTL_BASE_IDX', + 'regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', + 'regMMVM_L2_GCR_CNTL', 'regMMVM_L2_GCR_CNTL_BASE_IDX', + 'regMMVM_L2_MM_GROUP_RT_CLASSES', + 'regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', + 'regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_HI32', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_LO32', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_CNTL', + 'regMMVM_L2_PROTECTION_FAULT_CNTL2', + 'regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL3', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL4', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_STATUS', + 'regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', + 'regMMVM_L2_PTE_CACHE_DUMP_CNTL', + 'regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX', + 'regMMVM_L2_PTE_CACHE_DUMP_READ', + 'regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'regMMVM_L2_STATUS', + 'regMMVM_L2_STATUS_BASE_IDX', 'regMM_ATC_L2_CACHE_DATA0', + 'regMM_ATC_L2_CACHE_DATA0_BASE_IDX', 'regMM_ATC_L2_CACHE_DATA1', + 'regMM_ATC_L2_CACHE_DATA1_BASE_IDX', 'regMM_ATC_L2_CACHE_DATA2', + 'regMM_ATC_L2_CACHE_DATA2_BASE_IDX', 'regMM_ATC_L2_CGTT_CLK_CTRL', + 'regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX', 'regMM_ATC_L2_CNTL', + 'regMM_ATC_L2_CNTL2', 'regMM_ATC_L2_CNTL2_BASE_IDX', + 'regMM_ATC_L2_CNTL3', 'regMM_ATC_L2_CNTL3_BASE_IDX', + 'regMM_ATC_L2_CNTL4', 'regMM_ATC_L2_CNTL4_BASE_IDX', + 'regMM_ATC_L2_CNTL5', 'regMM_ATC_L2_CNTL5_BASE_IDX', + 'regMM_ATC_L2_CNTL_BASE_IDX', 'regMM_ATC_L2_IOV_MODE_CNTL', + 'regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX', + 'regMM_ATC_L2_MEM_POWER_LS', 'regMM_ATC_L2_MEM_POWER_LS_BASE_IDX', + 'regMM_ATC_L2_MISC_CG', 'regMM_ATC_L2_MISC_CG_BASE_IDX', + 'regMM_ATC_L2_MM_GROUP_RT_CLASSES', + 'regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX', + 'regMM_ATC_L2_PERFCOUNTER0_CFG', + 'regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX', + 'regMM_ATC_L2_PERFCOUNTER1_CFG', + 'regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX', + 'regMM_ATC_L2_PERFCOUNTER_HI', + 'regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX', + 'regMM_ATC_L2_PERFCOUNTER_LO', + 'regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX', + 'regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL', + 'regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMM_ATC_L2_SDPPORT_CTRL', 'regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX', + 'regMM_ATC_L2_STATUS', 'regMM_ATC_L2_STATUS2', + 'regMM_ATC_L2_STATUS2_BASE_IDX', 'regMM_ATC_L2_STATUS_BASE_IDX', + 'regPCTL_CTRL', 'regPCTL_CTRL_BASE_IDX', + 'regPCTL_MMHUB_DEEPSLEEP_IB', + 'regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX', + 'regPCTL_PERFCOUNTER0_CFG', 'regPCTL_PERFCOUNTER0_CFG_BASE_IDX', + 'regPCTL_PERFCOUNTER1_CFG', 'regPCTL_PERFCOUNTER1_CFG_BASE_IDX', + 'regPCTL_PERFCOUNTER_HI', 'regPCTL_PERFCOUNTER_HI_BASE_IDX', + 'regPCTL_PERFCOUNTER_LO', 'regPCTL_PERFCOUNTER_LO_BASE_IDX', + 'regPCTL_PERFCOUNTER_RSLT_CNTL', + 'regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regPCTL_PG_IGNORE_DEEPSLEEP', + 'regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX', + 'regPCTL_PG_IGNORE_DEEPSLEEP_IB', + 'regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX', 'regPCTL_RENG_CTRL', + 'regPCTL_RENG_CTRL_BASE_IDX', 'regPCTL_RESERVED_0', + 'regPCTL_RESERVED_0_BASE_IDX', 'regPCTL_RESERVED_1', + 'regPCTL_RESERVED_1_BASE_IDX', 'regPCTL_RESERVED_2', + 'regPCTL_RESERVED_2_BASE_IDX', 'regPCTL_RESERVED_3', + 'regPCTL_RESERVED_3_BASE_IDX', 'regPCTL_SLICE0_CFG_DAGB_RDBUSY', + 'regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX', + 'regPCTL_SLICE0_CFG_DAGB_WRBUSY', + 'regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX', + 'regPCTL_SLICE0_CFG_DS_ALLOW', + 'regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX', + 'regPCTL_SLICE0_CFG_DS_ALLOW_IB', + 'regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX', 'regPCTL_SLICE0_MISC', + 'regPCTL_SLICE0_MISC_BASE_IDX', 'regPCTL_SLICE0_RENG_EXECUTE', + 'regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX', + 'regPCTL_SLICE0_RENG_RAM_DATA', + 'regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX', + 'regPCTL_SLICE0_RENG_RAM_INDEX', + 'regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX', + 'regPCTL_SLICE1_CFG_DAGB_RDBUSY', + 'regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX', + 'regPCTL_SLICE1_CFG_DAGB_WRBUSY', + 'regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX', + 'regPCTL_SLICE1_CFG_DS_ALLOW', + 'regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX', + 'regPCTL_SLICE1_CFG_DS_ALLOW_IB', + 'regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX', 'regPCTL_SLICE1_MISC', + 'regPCTL_SLICE1_MISC_BASE_IDX', 'regPCTL_SLICE1_RENG_EXECUTE', + 'regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX', + 'regPCTL_SLICE1_RENG_RAM_DATA', + 'regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX', + 'regPCTL_SLICE1_RENG_RAM_INDEX', + 'regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX', + 'regPCTL_STATUS', 'regPCTL_STATUS_BASE_IDX', 'regPCTL_UTCL2_MISC', + 'regPCTL_UTCL2_MISC_BASE_IDX', 'regPCTL_UTCL2_RENG_EXECUTE', + 'regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX', + 'regPCTL_UTCL2_RENG_RAM_DATA', + 'regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX', + 'regPCTL_UTCL2_RENG_RAM_INDEX', + 'regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX'] diff --git a/tinygrad/runtime/autogen/am/mp_11_0.py b/tinygrad/runtime/autogen/am/mp_11_0.py new file mode 100644 index 0000000000..48cd61a9bd --- /dev/null +++ b/tinygrad/runtime/autogen/am/mp_11_0.py @@ -0,0 +1,1638 @@ +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_mp_11_0_2_OFFSET_HEADER = True # macro +mmMP0_SMN_C2PMSG_32 = 0x0060 # macro +mmMP0_SMN_C2PMSG_32_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_33 = 0x0061 # macro +mmMP0_SMN_C2PMSG_33_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_34 = 0x0062 # macro +mmMP0_SMN_C2PMSG_34_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_35 = 0x0063 # macro +mmMP0_SMN_C2PMSG_35_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_36 = 0x0064 # macro +mmMP0_SMN_C2PMSG_36_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_37 = 0x0065 # macro +mmMP0_SMN_C2PMSG_37_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_38 = 0x0066 # macro +mmMP0_SMN_C2PMSG_38_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_39 = 0x0067 # macro +mmMP0_SMN_C2PMSG_39_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_40 = 0x0068 # macro +mmMP0_SMN_C2PMSG_40_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_41 = 0x0069 # macro +mmMP0_SMN_C2PMSG_41_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_42 = 0x006a # macro +mmMP0_SMN_C2PMSG_42_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_43 = 0x006b # macro +mmMP0_SMN_C2PMSG_43_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_44 = 0x006c # macro +mmMP0_SMN_C2PMSG_44_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_45 = 0x006d # macro +mmMP0_SMN_C2PMSG_45_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_46 = 0x006e # macro +mmMP0_SMN_C2PMSG_46_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_47 = 0x006f # macro +mmMP0_SMN_C2PMSG_47_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_48 = 0x0070 # macro +mmMP0_SMN_C2PMSG_48_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_49 = 0x0071 # macro +mmMP0_SMN_C2PMSG_49_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_50 = 0x0072 # macro +mmMP0_SMN_C2PMSG_50_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_51 = 0x0073 # macro +mmMP0_SMN_C2PMSG_51_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_52 = 0x0074 # macro +mmMP0_SMN_C2PMSG_52_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_53 = 0x0075 # macro +mmMP0_SMN_C2PMSG_53_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_54 = 0x0076 # macro +mmMP0_SMN_C2PMSG_54_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_55 = 0x0077 # macro +mmMP0_SMN_C2PMSG_55_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_56 = 0x0078 # macro +mmMP0_SMN_C2PMSG_56_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_57 = 0x0079 # macro +mmMP0_SMN_C2PMSG_57_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_58 = 0x007a # macro +mmMP0_SMN_C2PMSG_58_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_59 = 0x007b # macro +mmMP0_SMN_C2PMSG_59_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_60 = 0x007c # macro +mmMP0_SMN_C2PMSG_60_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_61 = 0x007d # macro +mmMP0_SMN_C2PMSG_61_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_62 = 0x007e # macro +mmMP0_SMN_C2PMSG_62_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_63 = 0x007f # macro +mmMP0_SMN_C2PMSG_63_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_64 = 0x0080 # macro +mmMP0_SMN_C2PMSG_64_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_65 = 0x0081 # macro +mmMP0_SMN_C2PMSG_65_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_66 = 0x0082 # macro +mmMP0_SMN_C2PMSG_66_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_67 = 0x0083 # macro +mmMP0_SMN_C2PMSG_67_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_68 = 0x0084 # macro +mmMP0_SMN_C2PMSG_68_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_69 = 0x0085 # macro +mmMP0_SMN_C2PMSG_69_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_70 = 0x0086 # macro +mmMP0_SMN_C2PMSG_70_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_71 = 0x0087 # macro +mmMP0_SMN_C2PMSG_71_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_72 = 0x0088 # macro +mmMP0_SMN_C2PMSG_72_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_73 = 0x0089 # macro +mmMP0_SMN_C2PMSG_73_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_74 = 0x008a # macro +mmMP0_SMN_C2PMSG_74_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_75 = 0x008b # macro +mmMP0_SMN_C2PMSG_75_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_76 = 0x008c # macro +mmMP0_SMN_C2PMSG_76_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_77 = 0x008d # macro +mmMP0_SMN_C2PMSG_77_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_78 = 0x008e # macro +mmMP0_SMN_C2PMSG_78_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_79 = 0x008f # macro +mmMP0_SMN_C2PMSG_79_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_80 = 0x0090 # macro +mmMP0_SMN_C2PMSG_80_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_81 = 0x0091 # macro +mmMP0_SMN_C2PMSG_81_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_82 = 0x0092 # macro +mmMP0_SMN_C2PMSG_82_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_83 = 0x0093 # macro +mmMP0_SMN_C2PMSG_83_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_84 = 0x0094 # macro +mmMP0_SMN_C2PMSG_84_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_85 = 0x0095 # macro +mmMP0_SMN_C2PMSG_85_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_86 = 0x0096 # macro +mmMP0_SMN_C2PMSG_86_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_87 = 0x0097 # macro +mmMP0_SMN_C2PMSG_87_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_88 = 0x0098 # macro +mmMP0_SMN_C2PMSG_88_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_89 = 0x0099 # macro +mmMP0_SMN_C2PMSG_89_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_90 = 0x009a # macro +mmMP0_SMN_C2PMSG_90_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_91 = 0x009b # macro +mmMP0_SMN_C2PMSG_91_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_92 = 0x009c # macro +mmMP0_SMN_C2PMSG_92_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_93 = 0x009d # macro +mmMP0_SMN_C2PMSG_93_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_94 = 0x009e # macro +mmMP0_SMN_C2PMSG_94_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_95 = 0x009f # macro +mmMP0_SMN_C2PMSG_95_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_96 = 0x00a0 # macro +mmMP0_SMN_C2PMSG_96_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_97 = 0x00a1 # macro +mmMP0_SMN_C2PMSG_97_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_98 = 0x00a2 # macro +mmMP0_SMN_C2PMSG_98_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_99 = 0x00a3 # macro +mmMP0_SMN_C2PMSG_99_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_100 = 0x00a4 # macro +mmMP0_SMN_C2PMSG_100_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_101 = 0x00a5 # macro +mmMP0_SMN_C2PMSG_101_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_102 = 0x00a6 # macro +mmMP0_SMN_C2PMSG_102_BASE_IDX = 0 # macro +mmMP0_SMN_C2PMSG_103 = 0x00a7 # macro +mmMP0_SMN_C2PMSG_103_BASE_IDX = 0 # macro +mmMP0_SMN_ACTIVE_FCN_ID = 0x00c0 # macro +mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX = 0 # macro +mmMP0_SMN_IH_CREDIT = 0x00c1 # macro +mmMP0_SMN_IH_CREDIT_BASE_IDX = 0 # macro +mmMP0_SMN_IH_SW_INT = 0x00c2 # macro +mmMP0_SMN_IH_SW_INT_BASE_IDX = 0 # macro +mmMP0_SMN_IH_SW_INT_CTRL = 0x00c3 # macro +mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_32 = 0x0260 # macro +mmMP1_SMN_C2PMSG_32_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_33 = 0x0261 # macro +mmMP1_SMN_C2PMSG_33_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_34 = 0x0262 # macro +mmMP1_SMN_C2PMSG_34_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_35 = 0x0263 # macro +mmMP1_SMN_C2PMSG_35_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_36 = 0x0264 # macro +mmMP1_SMN_C2PMSG_36_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_37 = 0x0265 # macro +mmMP1_SMN_C2PMSG_37_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_38 = 0x0266 # macro +mmMP1_SMN_C2PMSG_38_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_39 = 0x0267 # macro +mmMP1_SMN_C2PMSG_39_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_40 = 0x0268 # macro +mmMP1_SMN_C2PMSG_40_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_41 = 0x0269 # macro +mmMP1_SMN_C2PMSG_41_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_42 = 0x026a # macro +mmMP1_SMN_C2PMSG_42_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_43 = 0x026b # macro +mmMP1_SMN_C2PMSG_43_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_44 = 0x026c # macro +mmMP1_SMN_C2PMSG_44_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_45 = 0x026d # macro +mmMP1_SMN_C2PMSG_45_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_46 = 0x026e # macro +mmMP1_SMN_C2PMSG_46_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_47 = 0x026f # macro +mmMP1_SMN_C2PMSG_47_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_48 = 0x0270 # macro +mmMP1_SMN_C2PMSG_48_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_49 = 0x0271 # macro +mmMP1_SMN_C2PMSG_49_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_50 = 0x0272 # macro +mmMP1_SMN_C2PMSG_50_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_51 = 0x0273 # macro +mmMP1_SMN_C2PMSG_51_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_52 = 0x0274 # macro +mmMP1_SMN_C2PMSG_52_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_53 = 0x0275 # macro +mmMP1_SMN_C2PMSG_53_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_54 = 0x0276 # macro +mmMP1_SMN_C2PMSG_54_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_55 = 0x0277 # macro +mmMP1_SMN_C2PMSG_55_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_56 = 0x0278 # macro +mmMP1_SMN_C2PMSG_56_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_57 = 0x0279 # macro +mmMP1_SMN_C2PMSG_57_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_58 = 0x027a # macro +mmMP1_SMN_C2PMSG_58_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_59 = 0x027b # macro +mmMP1_SMN_C2PMSG_59_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_60 = 0x027c # macro +mmMP1_SMN_C2PMSG_60_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_61 = 0x027d # macro +mmMP1_SMN_C2PMSG_61_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_62 = 0x027e # macro +mmMP1_SMN_C2PMSG_62_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_63 = 0x027f # macro +mmMP1_SMN_C2PMSG_63_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_64 = 0x0280 # macro +mmMP1_SMN_C2PMSG_64_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_65 = 0x0281 # macro +mmMP1_SMN_C2PMSG_65_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_66 = 0x0282 # macro +mmMP1_SMN_C2PMSG_66_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_67 = 0x0283 # macro +mmMP1_SMN_C2PMSG_67_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_68 = 0x0284 # macro +mmMP1_SMN_C2PMSG_68_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_69 = 0x0285 # macro +mmMP1_SMN_C2PMSG_69_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_70 = 0x0286 # macro +mmMP1_SMN_C2PMSG_70_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_71 = 0x0287 # macro +mmMP1_SMN_C2PMSG_71_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_72 = 0x0288 # macro +mmMP1_SMN_C2PMSG_72_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_73 = 0x0289 # macro +mmMP1_SMN_C2PMSG_73_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_74 = 0x028a # macro +mmMP1_SMN_C2PMSG_74_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_75 = 0x028b # macro +mmMP1_SMN_C2PMSG_75_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_76 = 0x028c # macro +mmMP1_SMN_C2PMSG_76_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_77 = 0x028d # macro +mmMP1_SMN_C2PMSG_77_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_78 = 0x028e # macro +mmMP1_SMN_C2PMSG_78_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_79 = 0x028f # macro +mmMP1_SMN_C2PMSG_79_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_80 = 0x0290 # macro +mmMP1_SMN_C2PMSG_80_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_81 = 0x0291 # macro +mmMP1_SMN_C2PMSG_81_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_82 = 0x0292 # macro +mmMP1_SMN_C2PMSG_82_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_83 = 0x0293 # macro +mmMP1_SMN_C2PMSG_83_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_84 = 0x0294 # macro +mmMP1_SMN_C2PMSG_84_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_85 = 0x0295 # macro +mmMP1_SMN_C2PMSG_85_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_86 = 0x0296 # macro +mmMP1_SMN_C2PMSG_86_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_87 = 0x0297 # macro +mmMP1_SMN_C2PMSG_87_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_88 = 0x0298 # macro +mmMP1_SMN_C2PMSG_88_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_89 = 0x0299 # macro +mmMP1_SMN_C2PMSG_89_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_90 = 0x029a # macro +mmMP1_SMN_C2PMSG_90_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_91 = 0x029b # macro +mmMP1_SMN_C2PMSG_91_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_92 = 0x029c # macro +mmMP1_SMN_C2PMSG_92_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_93 = 0x029d # macro +mmMP1_SMN_C2PMSG_93_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_94 = 0x029e # macro +mmMP1_SMN_C2PMSG_94_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_95 = 0x029f # macro +mmMP1_SMN_C2PMSG_95_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_96 = 0x02a0 # macro +mmMP1_SMN_C2PMSG_96_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_97 = 0x02a1 # macro +mmMP1_SMN_C2PMSG_97_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_98 = 0x02a2 # macro +mmMP1_SMN_C2PMSG_98_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_99 = 0x02a3 # macro +mmMP1_SMN_C2PMSG_99_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_100 = 0x02a4 # macro +mmMP1_SMN_C2PMSG_100_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_101 = 0x02a5 # macro +mmMP1_SMN_C2PMSG_101_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_102 = 0x02a6 # macro +mmMP1_SMN_C2PMSG_102_BASE_IDX = 0 # macro +mmMP1_SMN_C2PMSG_103 = 0x02a7 # macro +mmMP1_SMN_C2PMSG_103_BASE_IDX = 0 # macro +mmMP1_SMN_ACTIVE_FCN_ID = 0x02c0 # macro +mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX = 0 # macro +mmMP1_SMN_IH_CREDIT = 0x02c1 # macro +mmMP1_SMN_IH_CREDIT_BASE_IDX = 0 # macro +mmMP1_SMN_IH_SW_INT = 0x02c2 # macro +mmMP1_SMN_IH_SW_INT_BASE_IDX = 0 # macro +mmMP1_SMN_IH_SW_INT_CTRL = 0x02c3 # macro +mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro +mmMP1_SMN_FPS_CNT = 0x02c4 # macro +mmMP1_SMN_FPS_CNT_BASE_IDX = 0 # macro +mmMP1_SMN_PUB_CTRL = 0x02c5 # macro +mmMP1_SMN_PUB_CTRL_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH0 = 0x03c0 # macro +mmMP1_SMN_EXT_SCRATCH0_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH1 = 0x03c1 # macro +mmMP1_SMN_EXT_SCRATCH1_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH2 = 0x03c2 # macro +mmMP1_SMN_EXT_SCRATCH2_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH3 = 0x03c3 # macro +mmMP1_SMN_EXT_SCRATCH3_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH4 = 0x03c4 # macro +mmMP1_SMN_EXT_SCRATCH4_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH5 = 0x03c5 # macro +mmMP1_SMN_EXT_SCRATCH5_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH6 = 0x03c6 # macro +mmMP1_SMN_EXT_SCRATCH6_BASE_IDX = 0 # macro +mmMP1_SMN_EXT_SCRATCH7 = 0x03c7 # macro +mmMP1_SMN_EXT_SCRATCH7_BASE_IDX = 0 # macro +smnMP1_PMI_3_START = 0x3030204 # macro +smnMP1_PMI_3_FIFO = 0x3030208 # macro +smnMP1_PMI_3 = 0x3030600 # macro +_mp_11_0_2_SH_MASK_HEADER = True # macro +MP0_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT = 0x0 # macro +MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT = 0x1f # macro +MP0_SMN_ACTIVE_FCN_ID__VFID_MASK = 0x0000001F # macro +MP0_SMN_ACTIVE_FCN_ID__VF_MASK = 0x80000000 # macro +MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro +MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro +MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro +MP0_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro +MP0_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro +MP0_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro +MP0_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro +MP0_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro +MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT = 0x0 # macro +MP1_FIRMWARE_FLAGS__RESERVED__SHIFT = 0x1 # macro +MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK = 0x00000001 # macro +MP1_FIRMWARE_FLAGS__RESERVED_MASK = 0xFFFFFFFE # macro +MP1_PUB_SCRATCH0__DATA__SHIFT = 0x0 # macro +MP1_PUB_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro +MP1_PUB_SCRATCH1__DATA__SHIFT = 0x0 # macro +MP1_PUB_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro +MP1_PUB_SCRATCH2__DATA__SHIFT = 0x0 # macro +MP1_PUB_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro +MP1_PUB_SCRATCH3__DATA__SHIFT = 0x0 # macro +MP1_PUB_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_0__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_1__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_1__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_2__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_2__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_3__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_3__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_4__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_4__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_5__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_5__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_6__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_6__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_7__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_7__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_8__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_8__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_9__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_9__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_10__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_10__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_11__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_11__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_12__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_12__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_13__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_13__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_14__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_14__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_15__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_15__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_16__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_16__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_17__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_17__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_18__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_18__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_19__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_19__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_20__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_20__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_21__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_21__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_22__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_22__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_23__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_23__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_24__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_24__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_25__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_25__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_26__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_26__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_27__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_27__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_28__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_28__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_29__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_29__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_30__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_30__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_31__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_31__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2CMSG_0__CONTENT__SHIFT = 0x0 # macro +MP1_P2CMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2CMSG_1__CONTENT__SHIFT = 0x0 # macro +MP1_P2CMSG_1__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2CMSG_2__CONTENT__SHIFT = 0x0 # macro +MP1_P2CMSG_2__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2CMSG_3__CONTENT__SHIFT = 0x0 # macro +MP1_P2CMSG_3__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2CMSG_INTEN__INTEN__SHIFT = 0x0 # macro +MP1_P2CMSG_INTEN__INTEN_MASK = 0x0000000F # macro +MP1_P2CMSG_INTSTS__INTSTS0__SHIFT = 0x0 # macro +MP1_P2CMSG_INTSTS__INTSTS1__SHIFT = 0x1 # macro +MP1_P2CMSG_INTSTS__INTSTS2__SHIFT = 0x2 # macro +MP1_P2CMSG_INTSTS__INTSTS3__SHIFT = 0x3 # macro +MP1_P2CMSG_INTSTS__INTSTS0_MASK = 0x00000001 # macro +MP1_P2CMSG_INTSTS__INTSTS1_MASK = 0x00000002 # macro +MP1_P2CMSG_INTSTS__INTSTS2_MASK = 0x00000004 # macro +MP1_P2CMSG_INTSTS__INTSTS3_MASK = 0x00000008 # macro +MP1_P2SMSG_0__CONTENT__SHIFT = 0x0 # macro +MP1_P2SMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2SMSG_1__CONTENT__SHIFT = 0x0 # macro +MP1_P2SMSG_1__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2SMSG_2__CONTENT__SHIFT = 0x0 # macro +MP1_P2SMSG_2__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2SMSG_3__CONTENT__SHIFT = 0x0 # macro +MP1_P2SMSG_3__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_P2SMSG_INTSTS__INTSTS0__SHIFT = 0x0 # macro +MP1_P2SMSG_INTSTS__INTSTS1__SHIFT = 0x1 # macro +MP1_P2SMSG_INTSTS__INTSTS2__SHIFT = 0x2 # macro +MP1_P2SMSG_INTSTS__INTSTS3__SHIFT = 0x3 # macro +MP1_P2SMSG_INTSTS__INTSTS0_MASK = 0x00000001 # macro +MP1_P2SMSG_INTSTS__INTSTS1_MASK = 0x00000002 # macro +MP1_P2SMSG_INTSTS__INTSTS2_MASK = 0x00000004 # macro +MP1_P2SMSG_INTSTS__INTSTS3_MASK = 0x00000008 # macro +MP1_S2PMSG_0__CONTENT__SHIFT = 0x0 # macro +MP1_S2PMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro +MP1_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_ACTIVE_FCN_ID__VFID__SHIFT = 0x0 # macro +MP1_ACTIVE_FCN_ID__VF__SHIFT = 0x1f # macro +MP1_ACTIVE_FCN_ID__VFID_MASK = 0x0000001F # macro +MP1_ACTIVE_FCN_ID__VF_MASK = 0x80000000 # macro +MP1_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro +MP1_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro +MP1_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro +MP1_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro +MP1_IH_SW_INT__ID__SHIFT = 0x0 # macro +MP1_IH_SW_INT__VALID__SHIFT = 0x8 # macro +MP1_IH_SW_INT__ID_MASK = 0x000000FF # macro +MP1_IH_SW_INT__VALID_MASK = 0x00000100 # macro +MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro +MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro +MP1_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro +MP1_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro +MP1_FPS_CNT__COUNT__SHIFT = 0x0 # macro +MP1_FPS_CNT__COUNT_MASK = 0xFFFFFFFF # macro +MP1_PUB_CTRL__RESET__SHIFT = 0x0 # macro +MP1_PUB_CTRL__RESET_MASK = 0x00000001 # macro +MP1_EXT_SCRATCH0__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro +MP1_EXT_SCRATCH1__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro +MP1_EXT_SCRATCH2__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro +MP1_EXT_SCRATCH3__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro +MP1_EXT_SCRATCH4__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH4__DATA_MASK = 0xFFFFFFFF # macro +MP1_EXT_SCRATCH5__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH5__DATA_MASK = 0xFFFFFFFF # macro +MP1_EXT_SCRATCH6__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH6__DATA_MASK = 0xFFFFFFFF # macro +MP1_EXT_SCRATCH7__DATA__SHIFT = 0x0 # macro +MP1_EXT_SCRATCH7__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT = 0x0 # macro +MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT = 0x1f # macro +MP1_SMN_ACTIVE_FCN_ID__VFID_MASK = 0x0000001F # macro +MP1_SMN_ACTIVE_FCN_ID__VF_MASK = 0x80000000 # macro +MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro +MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro +MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro +MP1_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro +MP1_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro +MP1_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro +MP1_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro +MP1_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro +MP1_SMN_FPS_CNT__COUNT__SHIFT = 0x0 # macro +MP1_SMN_FPS_CNT__COUNT_MASK = 0xFFFFFFFF # macro +MP1_SMN_PUB_CTRL__RESET__SHIFT = 0x0 # macro +MP1_SMN_PUB_CTRL__RESET_MASK = 0x00000001 # macro +MP1_SMN_EXT_SCRATCH0__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH1__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH2__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH3__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH4__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH4__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH5__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH5__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH6__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH6__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH7__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH7__DATA_MASK = 0xFFFFFFFF # macro +MP1_PMI_3_START__ENABLE_MASK = 0x80000000 # macro +MP1_PMI_3_FIFO__DEPTH_MASK = 0x00000fff # macro +MP1_PMI_3_START__ENABLE__SHIFT = 0x0000001f # macro +MP1_PMI_3_FIFO__DEPTH__SHIFT = 0x00000000 # macro +__all__ = \ + ['MP0_SMN_ACTIVE_FCN_ID__VFID_MASK', + 'MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT', + 'MP0_SMN_ACTIVE_FCN_ID__VF_MASK', + 'MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT', + 'MP0_SMN_C2PMSG_100__CONTENT_MASK', + 'MP0_SMN_C2PMSG_100__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_101__CONTENT_MASK', + 'MP0_SMN_C2PMSG_101__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_102__CONTENT_MASK', + 'MP0_SMN_C2PMSG_102__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_103__CONTENT_MASK', + 'MP0_SMN_C2PMSG_103__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_32__CONTENT_MASK', + 'MP0_SMN_C2PMSG_32__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_33__CONTENT_MASK', + 'MP0_SMN_C2PMSG_33__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_34__CONTENT_MASK', + 'MP0_SMN_C2PMSG_34__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_35__CONTENT_MASK', + 'MP0_SMN_C2PMSG_35__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_36__CONTENT_MASK', + 'MP0_SMN_C2PMSG_36__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_37__CONTENT_MASK', + 'MP0_SMN_C2PMSG_37__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_38__CONTENT_MASK', + 'MP0_SMN_C2PMSG_38__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_39__CONTENT_MASK', + 'MP0_SMN_C2PMSG_39__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_40__CONTENT_MASK', + 'MP0_SMN_C2PMSG_40__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_41__CONTENT_MASK', + 'MP0_SMN_C2PMSG_41__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_42__CONTENT_MASK', + 'MP0_SMN_C2PMSG_42__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_43__CONTENT_MASK', + 'MP0_SMN_C2PMSG_43__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_44__CONTENT_MASK', + 'MP0_SMN_C2PMSG_44__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_45__CONTENT_MASK', + 'MP0_SMN_C2PMSG_45__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_46__CONTENT_MASK', + 'MP0_SMN_C2PMSG_46__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_47__CONTENT_MASK', + 'MP0_SMN_C2PMSG_47__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_48__CONTENT_MASK', + 'MP0_SMN_C2PMSG_48__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_49__CONTENT_MASK', + 'MP0_SMN_C2PMSG_49__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_50__CONTENT_MASK', + 'MP0_SMN_C2PMSG_50__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_51__CONTENT_MASK', + 'MP0_SMN_C2PMSG_51__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_52__CONTENT_MASK', + 'MP0_SMN_C2PMSG_52__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_53__CONTENT_MASK', + 'MP0_SMN_C2PMSG_53__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_54__CONTENT_MASK', + 'MP0_SMN_C2PMSG_54__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_55__CONTENT_MASK', + 'MP0_SMN_C2PMSG_55__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_56__CONTENT_MASK', + 'MP0_SMN_C2PMSG_56__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_57__CONTENT_MASK', + 'MP0_SMN_C2PMSG_57__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_58__CONTENT_MASK', + 'MP0_SMN_C2PMSG_58__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_59__CONTENT_MASK', + 'MP0_SMN_C2PMSG_59__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_60__CONTENT_MASK', + 'MP0_SMN_C2PMSG_60__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_61__CONTENT_MASK', + 'MP0_SMN_C2PMSG_61__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_62__CONTENT_MASK', + 'MP0_SMN_C2PMSG_62__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_63__CONTENT_MASK', + 'MP0_SMN_C2PMSG_63__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_64__CONTENT_MASK', + 'MP0_SMN_C2PMSG_64__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_65__CONTENT_MASK', + 'MP0_SMN_C2PMSG_65__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_66__CONTENT_MASK', + 'MP0_SMN_C2PMSG_66__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_67__CONTENT_MASK', + 'MP0_SMN_C2PMSG_67__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_68__CONTENT_MASK', + 'MP0_SMN_C2PMSG_68__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_69__CONTENT_MASK', + 'MP0_SMN_C2PMSG_69__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_70__CONTENT_MASK', + 'MP0_SMN_C2PMSG_70__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_71__CONTENT_MASK', + 'MP0_SMN_C2PMSG_71__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_72__CONTENT_MASK', + 'MP0_SMN_C2PMSG_72__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_73__CONTENT_MASK', + 'MP0_SMN_C2PMSG_73__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_74__CONTENT_MASK', + 'MP0_SMN_C2PMSG_74__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_75__CONTENT_MASK', + 'MP0_SMN_C2PMSG_75__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_76__CONTENT_MASK', + 'MP0_SMN_C2PMSG_76__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_77__CONTENT_MASK', + 'MP0_SMN_C2PMSG_77__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_78__CONTENT_MASK', + 'MP0_SMN_C2PMSG_78__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_79__CONTENT_MASK', + 'MP0_SMN_C2PMSG_79__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_80__CONTENT_MASK', + 'MP0_SMN_C2PMSG_80__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_81__CONTENT_MASK', + 'MP0_SMN_C2PMSG_81__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_82__CONTENT_MASK', + 'MP0_SMN_C2PMSG_82__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_83__CONTENT_MASK', + 'MP0_SMN_C2PMSG_83__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_84__CONTENT_MASK', + 'MP0_SMN_C2PMSG_84__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_85__CONTENT_MASK', + 'MP0_SMN_C2PMSG_85__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_86__CONTENT_MASK', + 'MP0_SMN_C2PMSG_86__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_87__CONTENT_MASK', + 'MP0_SMN_C2PMSG_87__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_88__CONTENT_MASK', + 'MP0_SMN_C2PMSG_88__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_89__CONTENT_MASK', + 'MP0_SMN_C2PMSG_89__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_90__CONTENT_MASK', + 'MP0_SMN_C2PMSG_90__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_91__CONTENT_MASK', + 'MP0_SMN_C2PMSG_91__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_92__CONTENT_MASK', + 'MP0_SMN_C2PMSG_92__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_93__CONTENT_MASK', + 'MP0_SMN_C2PMSG_93__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_94__CONTENT_MASK', + 'MP0_SMN_C2PMSG_94__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_95__CONTENT_MASK', + 'MP0_SMN_C2PMSG_95__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_96__CONTENT_MASK', + 'MP0_SMN_C2PMSG_96__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_97__CONTENT_MASK', + 'MP0_SMN_C2PMSG_97__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_98__CONTENT_MASK', + 'MP0_SMN_C2PMSG_98__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_99__CONTENT_MASK', + 'MP0_SMN_C2PMSG_99__CONTENT__SHIFT', + 'MP0_SMN_IH_CREDIT__CLIENT_ID_MASK', + 'MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT', + 'MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK', + 'MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT', + 'MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK', + 'MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT', + 'MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK', + 'MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT', + 'MP0_SMN_IH_SW_INT__ID_MASK', 'MP0_SMN_IH_SW_INT__ID__SHIFT', + 'MP0_SMN_IH_SW_INT__VALID_MASK', + 'MP0_SMN_IH_SW_INT__VALID__SHIFT', 'MP1_ACTIVE_FCN_ID__VFID_MASK', + 'MP1_ACTIVE_FCN_ID__VFID__SHIFT', 'MP1_ACTIVE_FCN_ID__VF_MASK', + 'MP1_ACTIVE_FCN_ID__VF__SHIFT', 'MP1_C2PMSG_0__CONTENT_MASK', + 'MP1_C2PMSG_0__CONTENT__SHIFT', 'MP1_C2PMSG_100__CONTENT_MASK', + 'MP1_C2PMSG_100__CONTENT__SHIFT', 'MP1_C2PMSG_101__CONTENT_MASK', + 'MP1_C2PMSG_101__CONTENT__SHIFT', 'MP1_C2PMSG_102__CONTENT_MASK', + 'MP1_C2PMSG_102__CONTENT__SHIFT', 'MP1_C2PMSG_103__CONTENT_MASK', + 'MP1_C2PMSG_103__CONTENT__SHIFT', 'MP1_C2PMSG_10__CONTENT_MASK', + 'MP1_C2PMSG_10__CONTENT__SHIFT', 'MP1_C2PMSG_11__CONTENT_MASK', + 'MP1_C2PMSG_11__CONTENT__SHIFT', 'MP1_C2PMSG_12__CONTENT_MASK', + 'MP1_C2PMSG_12__CONTENT__SHIFT', 'MP1_C2PMSG_13__CONTENT_MASK', + 'MP1_C2PMSG_13__CONTENT__SHIFT', 'MP1_C2PMSG_14__CONTENT_MASK', + 'MP1_C2PMSG_14__CONTENT__SHIFT', 'MP1_C2PMSG_15__CONTENT_MASK', + 'MP1_C2PMSG_15__CONTENT__SHIFT', 'MP1_C2PMSG_16__CONTENT_MASK', + 'MP1_C2PMSG_16__CONTENT__SHIFT', 'MP1_C2PMSG_17__CONTENT_MASK', + 'MP1_C2PMSG_17__CONTENT__SHIFT', 'MP1_C2PMSG_18__CONTENT_MASK', + 'MP1_C2PMSG_18__CONTENT__SHIFT', 'MP1_C2PMSG_19__CONTENT_MASK', + 'MP1_C2PMSG_19__CONTENT__SHIFT', 'MP1_C2PMSG_1__CONTENT_MASK', + 'MP1_C2PMSG_1__CONTENT__SHIFT', 'MP1_C2PMSG_20__CONTENT_MASK', + 'MP1_C2PMSG_20__CONTENT__SHIFT', 'MP1_C2PMSG_21__CONTENT_MASK', + 'MP1_C2PMSG_21__CONTENT__SHIFT', 'MP1_C2PMSG_22__CONTENT_MASK', + 'MP1_C2PMSG_22__CONTENT__SHIFT', 'MP1_C2PMSG_23__CONTENT_MASK', + 'MP1_C2PMSG_23__CONTENT__SHIFT', 'MP1_C2PMSG_24__CONTENT_MASK', + 'MP1_C2PMSG_24__CONTENT__SHIFT', 'MP1_C2PMSG_25__CONTENT_MASK', + 'MP1_C2PMSG_25__CONTENT__SHIFT', 'MP1_C2PMSG_26__CONTENT_MASK', + 'MP1_C2PMSG_26__CONTENT__SHIFT', 'MP1_C2PMSG_27__CONTENT_MASK', + 'MP1_C2PMSG_27__CONTENT__SHIFT', 'MP1_C2PMSG_28__CONTENT_MASK', + 'MP1_C2PMSG_28__CONTENT__SHIFT', 'MP1_C2PMSG_29__CONTENT_MASK', + 'MP1_C2PMSG_29__CONTENT__SHIFT', 'MP1_C2PMSG_2__CONTENT_MASK', + 'MP1_C2PMSG_2__CONTENT__SHIFT', 'MP1_C2PMSG_30__CONTENT_MASK', + 'MP1_C2PMSG_30__CONTENT__SHIFT', 'MP1_C2PMSG_31__CONTENT_MASK', + 'MP1_C2PMSG_31__CONTENT__SHIFT', 'MP1_C2PMSG_32__CONTENT_MASK', + 'MP1_C2PMSG_32__CONTENT__SHIFT', 'MP1_C2PMSG_33__CONTENT_MASK', + 'MP1_C2PMSG_33__CONTENT__SHIFT', 'MP1_C2PMSG_34__CONTENT_MASK', + 'MP1_C2PMSG_34__CONTENT__SHIFT', 'MP1_C2PMSG_35__CONTENT_MASK', + 'MP1_C2PMSG_35__CONTENT__SHIFT', 'MP1_C2PMSG_36__CONTENT_MASK', + 'MP1_C2PMSG_36__CONTENT__SHIFT', 'MP1_C2PMSG_37__CONTENT_MASK', + 'MP1_C2PMSG_37__CONTENT__SHIFT', 'MP1_C2PMSG_38__CONTENT_MASK', + 'MP1_C2PMSG_38__CONTENT__SHIFT', 'MP1_C2PMSG_39__CONTENT_MASK', + 'MP1_C2PMSG_39__CONTENT__SHIFT', 'MP1_C2PMSG_3__CONTENT_MASK', + 'MP1_C2PMSG_3__CONTENT__SHIFT', 'MP1_C2PMSG_40__CONTENT_MASK', + 'MP1_C2PMSG_40__CONTENT__SHIFT', 'MP1_C2PMSG_41__CONTENT_MASK', + 'MP1_C2PMSG_41__CONTENT__SHIFT', 'MP1_C2PMSG_42__CONTENT_MASK', + 'MP1_C2PMSG_42__CONTENT__SHIFT', 'MP1_C2PMSG_43__CONTENT_MASK', + 'MP1_C2PMSG_43__CONTENT__SHIFT', 'MP1_C2PMSG_44__CONTENT_MASK', + 'MP1_C2PMSG_44__CONTENT__SHIFT', 'MP1_C2PMSG_45__CONTENT_MASK', + 'MP1_C2PMSG_45__CONTENT__SHIFT', 'MP1_C2PMSG_46__CONTENT_MASK', + 'MP1_C2PMSG_46__CONTENT__SHIFT', 'MP1_C2PMSG_47__CONTENT_MASK', + 'MP1_C2PMSG_47__CONTENT__SHIFT', 'MP1_C2PMSG_48__CONTENT_MASK', + 'MP1_C2PMSG_48__CONTENT__SHIFT', 'MP1_C2PMSG_49__CONTENT_MASK', + 'MP1_C2PMSG_49__CONTENT__SHIFT', 'MP1_C2PMSG_4__CONTENT_MASK', + 'MP1_C2PMSG_4__CONTENT__SHIFT', 'MP1_C2PMSG_50__CONTENT_MASK', + 'MP1_C2PMSG_50__CONTENT__SHIFT', 'MP1_C2PMSG_51__CONTENT_MASK', + 'MP1_C2PMSG_51__CONTENT__SHIFT', 'MP1_C2PMSG_52__CONTENT_MASK', + 'MP1_C2PMSG_52__CONTENT__SHIFT', 'MP1_C2PMSG_53__CONTENT_MASK', + 'MP1_C2PMSG_53__CONTENT__SHIFT', 'MP1_C2PMSG_54__CONTENT_MASK', + 'MP1_C2PMSG_54__CONTENT__SHIFT', 'MP1_C2PMSG_55__CONTENT_MASK', + 'MP1_C2PMSG_55__CONTENT__SHIFT', 'MP1_C2PMSG_56__CONTENT_MASK', + 'MP1_C2PMSG_56__CONTENT__SHIFT', 'MP1_C2PMSG_57__CONTENT_MASK', + 'MP1_C2PMSG_57__CONTENT__SHIFT', 'MP1_C2PMSG_58__CONTENT_MASK', + 'MP1_C2PMSG_58__CONTENT__SHIFT', 'MP1_C2PMSG_59__CONTENT_MASK', + 'MP1_C2PMSG_59__CONTENT__SHIFT', 'MP1_C2PMSG_5__CONTENT_MASK', + 'MP1_C2PMSG_5__CONTENT__SHIFT', 'MP1_C2PMSG_60__CONTENT_MASK', + 'MP1_C2PMSG_60__CONTENT__SHIFT', 'MP1_C2PMSG_61__CONTENT_MASK', + 'MP1_C2PMSG_61__CONTENT__SHIFT', 'MP1_C2PMSG_62__CONTENT_MASK', + 'MP1_C2PMSG_62__CONTENT__SHIFT', 'MP1_C2PMSG_63__CONTENT_MASK', + 'MP1_C2PMSG_63__CONTENT__SHIFT', 'MP1_C2PMSG_64__CONTENT_MASK', + 'MP1_C2PMSG_64__CONTENT__SHIFT', 'MP1_C2PMSG_65__CONTENT_MASK', + 'MP1_C2PMSG_65__CONTENT__SHIFT', 'MP1_C2PMSG_66__CONTENT_MASK', + 'MP1_C2PMSG_66__CONTENT__SHIFT', 'MP1_C2PMSG_67__CONTENT_MASK', + 'MP1_C2PMSG_67__CONTENT__SHIFT', 'MP1_C2PMSG_68__CONTENT_MASK', + 'MP1_C2PMSG_68__CONTENT__SHIFT', 'MP1_C2PMSG_69__CONTENT_MASK', + 'MP1_C2PMSG_69__CONTENT__SHIFT', 'MP1_C2PMSG_6__CONTENT_MASK', + 'MP1_C2PMSG_6__CONTENT__SHIFT', 'MP1_C2PMSG_70__CONTENT_MASK', + 'MP1_C2PMSG_70__CONTENT__SHIFT', 'MP1_C2PMSG_71__CONTENT_MASK', + 'MP1_C2PMSG_71__CONTENT__SHIFT', 'MP1_C2PMSG_72__CONTENT_MASK', + 'MP1_C2PMSG_72__CONTENT__SHIFT', 'MP1_C2PMSG_73__CONTENT_MASK', + 'MP1_C2PMSG_73__CONTENT__SHIFT', 'MP1_C2PMSG_74__CONTENT_MASK', + 'MP1_C2PMSG_74__CONTENT__SHIFT', 'MP1_C2PMSG_75__CONTENT_MASK', + 'MP1_C2PMSG_75__CONTENT__SHIFT', 'MP1_C2PMSG_76__CONTENT_MASK', + 'MP1_C2PMSG_76__CONTENT__SHIFT', 'MP1_C2PMSG_77__CONTENT_MASK', + 'MP1_C2PMSG_77__CONTENT__SHIFT', 'MP1_C2PMSG_78__CONTENT_MASK', + 'MP1_C2PMSG_78__CONTENT__SHIFT', 'MP1_C2PMSG_79__CONTENT_MASK', + 'MP1_C2PMSG_79__CONTENT__SHIFT', 'MP1_C2PMSG_7__CONTENT_MASK', + 'MP1_C2PMSG_7__CONTENT__SHIFT', 'MP1_C2PMSG_80__CONTENT_MASK', + 'MP1_C2PMSG_80__CONTENT__SHIFT', 'MP1_C2PMSG_81__CONTENT_MASK', + 'MP1_C2PMSG_81__CONTENT__SHIFT', 'MP1_C2PMSG_82__CONTENT_MASK', + 'MP1_C2PMSG_82__CONTENT__SHIFT', 'MP1_C2PMSG_83__CONTENT_MASK', + 'MP1_C2PMSG_83__CONTENT__SHIFT', 'MP1_C2PMSG_84__CONTENT_MASK', + 'MP1_C2PMSG_84__CONTENT__SHIFT', 'MP1_C2PMSG_85__CONTENT_MASK', + 'MP1_C2PMSG_85__CONTENT__SHIFT', 'MP1_C2PMSG_86__CONTENT_MASK', + 'MP1_C2PMSG_86__CONTENT__SHIFT', 'MP1_C2PMSG_87__CONTENT_MASK', + 'MP1_C2PMSG_87__CONTENT__SHIFT', 'MP1_C2PMSG_88__CONTENT_MASK', + 'MP1_C2PMSG_88__CONTENT__SHIFT', 'MP1_C2PMSG_89__CONTENT_MASK', + 'MP1_C2PMSG_89__CONTENT__SHIFT', 'MP1_C2PMSG_8__CONTENT_MASK', + 'MP1_C2PMSG_8__CONTENT__SHIFT', 'MP1_C2PMSG_90__CONTENT_MASK', + 'MP1_C2PMSG_90__CONTENT__SHIFT', 'MP1_C2PMSG_91__CONTENT_MASK', + 'MP1_C2PMSG_91__CONTENT__SHIFT', 'MP1_C2PMSG_92__CONTENT_MASK', + 'MP1_C2PMSG_92__CONTENT__SHIFT', 'MP1_C2PMSG_93__CONTENT_MASK', + 'MP1_C2PMSG_93__CONTENT__SHIFT', 'MP1_C2PMSG_94__CONTENT_MASK', + 'MP1_C2PMSG_94__CONTENT__SHIFT', 'MP1_C2PMSG_95__CONTENT_MASK', + 'MP1_C2PMSG_95__CONTENT__SHIFT', 'MP1_C2PMSG_96__CONTENT_MASK', + 'MP1_C2PMSG_96__CONTENT__SHIFT', 'MP1_C2PMSG_97__CONTENT_MASK', + 'MP1_C2PMSG_97__CONTENT__SHIFT', 'MP1_C2PMSG_98__CONTENT_MASK', + 'MP1_C2PMSG_98__CONTENT__SHIFT', 'MP1_C2PMSG_99__CONTENT_MASK', + 'MP1_C2PMSG_99__CONTENT__SHIFT', 'MP1_C2PMSG_9__CONTENT_MASK', + 'MP1_C2PMSG_9__CONTENT__SHIFT', 'MP1_EXT_SCRATCH0__DATA_MASK', + 'MP1_EXT_SCRATCH0__DATA__SHIFT', 'MP1_EXT_SCRATCH1__DATA_MASK', + 'MP1_EXT_SCRATCH1__DATA__SHIFT', 'MP1_EXT_SCRATCH2__DATA_MASK', + 'MP1_EXT_SCRATCH2__DATA__SHIFT', 'MP1_EXT_SCRATCH3__DATA_MASK', + 'MP1_EXT_SCRATCH3__DATA__SHIFT', 'MP1_EXT_SCRATCH4__DATA_MASK', + 'MP1_EXT_SCRATCH4__DATA__SHIFT', 'MP1_EXT_SCRATCH5__DATA_MASK', + 'MP1_EXT_SCRATCH5__DATA__SHIFT', 'MP1_EXT_SCRATCH6__DATA_MASK', + 'MP1_EXT_SCRATCH6__DATA__SHIFT', 'MP1_EXT_SCRATCH7__DATA_MASK', + 'MP1_EXT_SCRATCH7__DATA__SHIFT', + 'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK', + 'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT', + 'MP1_FIRMWARE_FLAGS__RESERVED_MASK', + 'MP1_FIRMWARE_FLAGS__RESERVED__SHIFT', 'MP1_FPS_CNT__COUNT_MASK', + 'MP1_FPS_CNT__COUNT__SHIFT', 'MP1_IH_CREDIT__CLIENT_ID_MASK', + 'MP1_IH_CREDIT__CLIENT_ID__SHIFT', + 'MP1_IH_CREDIT__CREDIT_VALUE_MASK', + 'MP1_IH_CREDIT__CREDIT_VALUE__SHIFT', + 'MP1_IH_SW_INT_CTRL__INT_ACK_MASK', + 'MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT', + 'MP1_IH_SW_INT_CTRL__INT_MASK_MASK', + 'MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT', 'MP1_IH_SW_INT__ID_MASK', + 'MP1_IH_SW_INT__ID__SHIFT', 'MP1_IH_SW_INT__VALID_MASK', + 'MP1_IH_SW_INT__VALID__SHIFT', 'MP1_P2CMSG_0__CONTENT_MASK', + 'MP1_P2CMSG_0__CONTENT__SHIFT', 'MP1_P2CMSG_1__CONTENT_MASK', + 'MP1_P2CMSG_1__CONTENT__SHIFT', 'MP1_P2CMSG_2__CONTENT_MASK', + 'MP1_P2CMSG_2__CONTENT__SHIFT', 'MP1_P2CMSG_3__CONTENT_MASK', + 'MP1_P2CMSG_3__CONTENT__SHIFT', 'MP1_P2CMSG_INTEN__INTEN_MASK', + 'MP1_P2CMSG_INTEN__INTEN__SHIFT', + 'MP1_P2CMSG_INTSTS__INTSTS0_MASK', + 'MP1_P2CMSG_INTSTS__INTSTS0__SHIFT', + 'MP1_P2CMSG_INTSTS__INTSTS1_MASK', + 'MP1_P2CMSG_INTSTS__INTSTS1__SHIFT', + 'MP1_P2CMSG_INTSTS__INTSTS2_MASK', + 'MP1_P2CMSG_INTSTS__INTSTS2__SHIFT', + 'MP1_P2CMSG_INTSTS__INTSTS3_MASK', + 'MP1_P2CMSG_INTSTS__INTSTS3__SHIFT', 'MP1_P2SMSG_0__CONTENT_MASK', + 'MP1_P2SMSG_0__CONTENT__SHIFT', 'MP1_P2SMSG_1__CONTENT_MASK', + 'MP1_P2SMSG_1__CONTENT__SHIFT', 'MP1_P2SMSG_2__CONTENT_MASK', + 'MP1_P2SMSG_2__CONTENT__SHIFT', 'MP1_P2SMSG_3__CONTENT_MASK', + 'MP1_P2SMSG_3__CONTENT__SHIFT', 'MP1_P2SMSG_INTSTS__INTSTS0_MASK', + 'MP1_P2SMSG_INTSTS__INTSTS0__SHIFT', + 'MP1_P2SMSG_INTSTS__INTSTS1_MASK', + 'MP1_P2SMSG_INTSTS__INTSTS1__SHIFT', + 'MP1_P2SMSG_INTSTS__INTSTS2_MASK', + 'MP1_P2SMSG_INTSTS__INTSTS2__SHIFT', + 'MP1_P2SMSG_INTSTS__INTSTS3_MASK', + 'MP1_P2SMSG_INTSTS__INTSTS3__SHIFT', 'MP1_PMI_3_FIFO__DEPTH_MASK', + 'MP1_PMI_3_FIFO__DEPTH__SHIFT', 'MP1_PMI_3_START__ENABLE_MASK', + 'MP1_PMI_3_START__ENABLE__SHIFT', 'MP1_PUB_CTRL__RESET_MASK', + 'MP1_PUB_CTRL__RESET__SHIFT', 'MP1_PUB_SCRATCH0__DATA_MASK', + 'MP1_PUB_SCRATCH0__DATA__SHIFT', 'MP1_PUB_SCRATCH1__DATA_MASK', + 'MP1_PUB_SCRATCH1__DATA__SHIFT', 'MP1_PUB_SCRATCH2__DATA_MASK', + 'MP1_PUB_SCRATCH2__DATA__SHIFT', 'MP1_PUB_SCRATCH3__DATA_MASK', + 'MP1_PUB_SCRATCH3__DATA__SHIFT', 'MP1_S2PMSG_0__CONTENT_MASK', + 'MP1_S2PMSG_0__CONTENT__SHIFT', + 'MP1_SMN_ACTIVE_FCN_ID__VFID_MASK', + 'MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT', + 'MP1_SMN_ACTIVE_FCN_ID__VF_MASK', + 'MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT', + 'MP1_SMN_C2PMSG_100__CONTENT_MASK', + 'MP1_SMN_C2PMSG_100__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_101__CONTENT_MASK', + 'MP1_SMN_C2PMSG_101__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_102__CONTENT_MASK', + 'MP1_SMN_C2PMSG_102__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_103__CONTENT_MASK', + 'MP1_SMN_C2PMSG_103__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_32__CONTENT_MASK', + 'MP1_SMN_C2PMSG_32__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_33__CONTENT_MASK', + 'MP1_SMN_C2PMSG_33__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_34__CONTENT_MASK', + 'MP1_SMN_C2PMSG_34__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_35__CONTENT_MASK', + 'MP1_SMN_C2PMSG_35__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_36__CONTENT_MASK', + 'MP1_SMN_C2PMSG_36__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_37__CONTENT_MASK', + 'MP1_SMN_C2PMSG_37__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_38__CONTENT_MASK', + 'MP1_SMN_C2PMSG_38__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_39__CONTENT_MASK', + 'MP1_SMN_C2PMSG_39__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_40__CONTENT_MASK', + 'MP1_SMN_C2PMSG_40__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_41__CONTENT_MASK', + 'MP1_SMN_C2PMSG_41__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_42__CONTENT_MASK', + 'MP1_SMN_C2PMSG_42__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_43__CONTENT_MASK', + 'MP1_SMN_C2PMSG_43__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_44__CONTENT_MASK', + 'MP1_SMN_C2PMSG_44__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_45__CONTENT_MASK', + 'MP1_SMN_C2PMSG_45__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_46__CONTENT_MASK', + 'MP1_SMN_C2PMSG_46__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_47__CONTENT_MASK', + 'MP1_SMN_C2PMSG_47__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_48__CONTENT_MASK', + 'MP1_SMN_C2PMSG_48__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_49__CONTENT_MASK', + 'MP1_SMN_C2PMSG_49__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_50__CONTENT_MASK', + 'MP1_SMN_C2PMSG_50__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_51__CONTENT_MASK', + 'MP1_SMN_C2PMSG_51__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_52__CONTENT_MASK', + 'MP1_SMN_C2PMSG_52__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_53__CONTENT_MASK', + 'MP1_SMN_C2PMSG_53__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_54__CONTENT_MASK', + 'MP1_SMN_C2PMSG_54__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_55__CONTENT_MASK', + 'MP1_SMN_C2PMSG_55__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_56__CONTENT_MASK', + 'MP1_SMN_C2PMSG_56__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_57__CONTENT_MASK', + 'MP1_SMN_C2PMSG_57__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_58__CONTENT_MASK', + 'MP1_SMN_C2PMSG_58__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_59__CONTENT_MASK', + 'MP1_SMN_C2PMSG_59__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_60__CONTENT_MASK', + 'MP1_SMN_C2PMSG_60__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_61__CONTENT_MASK', + 'MP1_SMN_C2PMSG_61__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_62__CONTENT_MASK', + 'MP1_SMN_C2PMSG_62__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_63__CONTENT_MASK', + 'MP1_SMN_C2PMSG_63__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_64__CONTENT_MASK', + 'MP1_SMN_C2PMSG_64__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_65__CONTENT_MASK', + 'MP1_SMN_C2PMSG_65__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_66__CONTENT_MASK', + 'MP1_SMN_C2PMSG_66__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_67__CONTENT_MASK', + 'MP1_SMN_C2PMSG_67__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_68__CONTENT_MASK', + 'MP1_SMN_C2PMSG_68__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_69__CONTENT_MASK', + 'MP1_SMN_C2PMSG_69__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_70__CONTENT_MASK', + 'MP1_SMN_C2PMSG_70__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_71__CONTENT_MASK', + 'MP1_SMN_C2PMSG_71__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_72__CONTENT_MASK', + 'MP1_SMN_C2PMSG_72__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_73__CONTENT_MASK', + 'MP1_SMN_C2PMSG_73__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_74__CONTENT_MASK', + 'MP1_SMN_C2PMSG_74__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_75__CONTENT_MASK', + 'MP1_SMN_C2PMSG_75__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_76__CONTENT_MASK', + 'MP1_SMN_C2PMSG_76__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_77__CONTENT_MASK', + 'MP1_SMN_C2PMSG_77__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_78__CONTENT_MASK', + 'MP1_SMN_C2PMSG_78__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_79__CONTENT_MASK', + 'MP1_SMN_C2PMSG_79__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_80__CONTENT_MASK', + 'MP1_SMN_C2PMSG_80__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_81__CONTENT_MASK', + 'MP1_SMN_C2PMSG_81__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_82__CONTENT_MASK', + 'MP1_SMN_C2PMSG_82__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_83__CONTENT_MASK', + 'MP1_SMN_C2PMSG_83__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_84__CONTENT_MASK', + 'MP1_SMN_C2PMSG_84__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_85__CONTENT_MASK', + 'MP1_SMN_C2PMSG_85__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_86__CONTENT_MASK', + 'MP1_SMN_C2PMSG_86__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_87__CONTENT_MASK', + 'MP1_SMN_C2PMSG_87__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_88__CONTENT_MASK', + 'MP1_SMN_C2PMSG_88__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_89__CONTENT_MASK', + 'MP1_SMN_C2PMSG_89__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_90__CONTENT_MASK', + 'MP1_SMN_C2PMSG_90__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_91__CONTENT_MASK', + 'MP1_SMN_C2PMSG_91__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_92__CONTENT_MASK', + 'MP1_SMN_C2PMSG_92__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_93__CONTENT_MASK', + 'MP1_SMN_C2PMSG_93__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_94__CONTENT_MASK', + 'MP1_SMN_C2PMSG_94__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_95__CONTENT_MASK', + 'MP1_SMN_C2PMSG_95__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_96__CONTENT_MASK', + 'MP1_SMN_C2PMSG_96__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_97__CONTENT_MASK', + 'MP1_SMN_C2PMSG_97__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_98__CONTENT_MASK', + 'MP1_SMN_C2PMSG_98__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_99__CONTENT_MASK', + 'MP1_SMN_C2PMSG_99__CONTENT__SHIFT', + 'MP1_SMN_EXT_SCRATCH0__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH0__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH1__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH1__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH2__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH2__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH3__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH3__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH4__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH4__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH5__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH5__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH6__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH6__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH7__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH7__DATA__SHIFT', + 'MP1_SMN_FPS_CNT__COUNT_MASK', 'MP1_SMN_FPS_CNT__COUNT__SHIFT', + 'MP1_SMN_IH_CREDIT__CLIENT_ID_MASK', + 'MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT', + 'MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK', + 'MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT', + 'MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK', + 'MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT', + 'MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK', + 'MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT', + 'MP1_SMN_IH_SW_INT__ID_MASK', 'MP1_SMN_IH_SW_INT__ID__SHIFT', + 'MP1_SMN_IH_SW_INT__VALID_MASK', + 'MP1_SMN_IH_SW_INT__VALID__SHIFT', 'MP1_SMN_PUB_CTRL__RESET_MASK', + 'MP1_SMN_PUB_CTRL__RESET__SHIFT', '_mp_11_0_2_OFFSET_HEADER', + '_mp_11_0_2_SH_MASK_HEADER', 'mmMP0_SMN_ACTIVE_FCN_ID', + 'mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX', 'mmMP0_SMN_C2PMSG_100', + 'mmMP0_SMN_C2PMSG_100_BASE_IDX', 'mmMP0_SMN_C2PMSG_101', + 'mmMP0_SMN_C2PMSG_101_BASE_IDX', 'mmMP0_SMN_C2PMSG_102', + 'mmMP0_SMN_C2PMSG_102_BASE_IDX', 'mmMP0_SMN_C2PMSG_103', + 'mmMP0_SMN_C2PMSG_103_BASE_IDX', 'mmMP0_SMN_C2PMSG_32', + 'mmMP0_SMN_C2PMSG_32_BASE_IDX', 'mmMP0_SMN_C2PMSG_33', + 'mmMP0_SMN_C2PMSG_33_BASE_IDX', 'mmMP0_SMN_C2PMSG_34', + 'mmMP0_SMN_C2PMSG_34_BASE_IDX', 'mmMP0_SMN_C2PMSG_35', + 'mmMP0_SMN_C2PMSG_35_BASE_IDX', 'mmMP0_SMN_C2PMSG_36', + 'mmMP0_SMN_C2PMSG_36_BASE_IDX', 'mmMP0_SMN_C2PMSG_37', + 'mmMP0_SMN_C2PMSG_37_BASE_IDX', 'mmMP0_SMN_C2PMSG_38', + 'mmMP0_SMN_C2PMSG_38_BASE_IDX', 'mmMP0_SMN_C2PMSG_39', + 'mmMP0_SMN_C2PMSG_39_BASE_IDX', 'mmMP0_SMN_C2PMSG_40', + 'mmMP0_SMN_C2PMSG_40_BASE_IDX', 'mmMP0_SMN_C2PMSG_41', + 'mmMP0_SMN_C2PMSG_41_BASE_IDX', 'mmMP0_SMN_C2PMSG_42', + 'mmMP0_SMN_C2PMSG_42_BASE_IDX', 'mmMP0_SMN_C2PMSG_43', + 'mmMP0_SMN_C2PMSG_43_BASE_IDX', 'mmMP0_SMN_C2PMSG_44', + 'mmMP0_SMN_C2PMSG_44_BASE_IDX', 'mmMP0_SMN_C2PMSG_45', + 'mmMP0_SMN_C2PMSG_45_BASE_IDX', 'mmMP0_SMN_C2PMSG_46', + 'mmMP0_SMN_C2PMSG_46_BASE_IDX', 'mmMP0_SMN_C2PMSG_47', + 'mmMP0_SMN_C2PMSG_47_BASE_IDX', 'mmMP0_SMN_C2PMSG_48', + 'mmMP0_SMN_C2PMSG_48_BASE_IDX', 'mmMP0_SMN_C2PMSG_49', + 'mmMP0_SMN_C2PMSG_49_BASE_IDX', 'mmMP0_SMN_C2PMSG_50', + 'mmMP0_SMN_C2PMSG_50_BASE_IDX', 'mmMP0_SMN_C2PMSG_51', + 'mmMP0_SMN_C2PMSG_51_BASE_IDX', 'mmMP0_SMN_C2PMSG_52', + 'mmMP0_SMN_C2PMSG_52_BASE_IDX', 'mmMP0_SMN_C2PMSG_53', + 'mmMP0_SMN_C2PMSG_53_BASE_IDX', 'mmMP0_SMN_C2PMSG_54', + 'mmMP0_SMN_C2PMSG_54_BASE_IDX', 'mmMP0_SMN_C2PMSG_55', + 'mmMP0_SMN_C2PMSG_55_BASE_IDX', 'mmMP0_SMN_C2PMSG_56', + 'mmMP0_SMN_C2PMSG_56_BASE_IDX', 'mmMP0_SMN_C2PMSG_57', + 'mmMP0_SMN_C2PMSG_57_BASE_IDX', 'mmMP0_SMN_C2PMSG_58', + 'mmMP0_SMN_C2PMSG_58_BASE_IDX', 'mmMP0_SMN_C2PMSG_59', + 'mmMP0_SMN_C2PMSG_59_BASE_IDX', 'mmMP0_SMN_C2PMSG_60', + 'mmMP0_SMN_C2PMSG_60_BASE_IDX', 'mmMP0_SMN_C2PMSG_61', + 'mmMP0_SMN_C2PMSG_61_BASE_IDX', 'mmMP0_SMN_C2PMSG_62', + 'mmMP0_SMN_C2PMSG_62_BASE_IDX', 'mmMP0_SMN_C2PMSG_63', + 'mmMP0_SMN_C2PMSG_63_BASE_IDX', 'mmMP0_SMN_C2PMSG_64', + 'mmMP0_SMN_C2PMSG_64_BASE_IDX', 'mmMP0_SMN_C2PMSG_65', + 'mmMP0_SMN_C2PMSG_65_BASE_IDX', 'mmMP0_SMN_C2PMSG_66', + 'mmMP0_SMN_C2PMSG_66_BASE_IDX', 'mmMP0_SMN_C2PMSG_67', + 'mmMP0_SMN_C2PMSG_67_BASE_IDX', 'mmMP0_SMN_C2PMSG_68', + 'mmMP0_SMN_C2PMSG_68_BASE_IDX', 'mmMP0_SMN_C2PMSG_69', + 'mmMP0_SMN_C2PMSG_69_BASE_IDX', 'mmMP0_SMN_C2PMSG_70', + 'mmMP0_SMN_C2PMSG_70_BASE_IDX', 'mmMP0_SMN_C2PMSG_71', + 'mmMP0_SMN_C2PMSG_71_BASE_IDX', 'mmMP0_SMN_C2PMSG_72', + 'mmMP0_SMN_C2PMSG_72_BASE_IDX', 'mmMP0_SMN_C2PMSG_73', + 'mmMP0_SMN_C2PMSG_73_BASE_IDX', 'mmMP0_SMN_C2PMSG_74', + 'mmMP0_SMN_C2PMSG_74_BASE_IDX', 'mmMP0_SMN_C2PMSG_75', + 'mmMP0_SMN_C2PMSG_75_BASE_IDX', 'mmMP0_SMN_C2PMSG_76', + 'mmMP0_SMN_C2PMSG_76_BASE_IDX', 'mmMP0_SMN_C2PMSG_77', + 'mmMP0_SMN_C2PMSG_77_BASE_IDX', 'mmMP0_SMN_C2PMSG_78', + 'mmMP0_SMN_C2PMSG_78_BASE_IDX', 'mmMP0_SMN_C2PMSG_79', + 'mmMP0_SMN_C2PMSG_79_BASE_IDX', 'mmMP0_SMN_C2PMSG_80', + 'mmMP0_SMN_C2PMSG_80_BASE_IDX', 'mmMP0_SMN_C2PMSG_81', + 'mmMP0_SMN_C2PMSG_81_BASE_IDX', 'mmMP0_SMN_C2PMSG_82', + 'mmMP0_SMN_C2PMSG_82_BASE_IDX', 'mmMP0_SMN_C2PMSG_83', + 'mmMP0_SMN_C2PMSG_83_BASE_IDX', 'mmMP0_SMN_C2PMSG_84', + 'mmMP0_SMN_C2PMSG_84_BASE_IDX', 'mmMP0_SMN_C2PMSG_85', + 'mmMP0_SMN_C2PMSG_85_BASE_IDX', 'mmMP0_SMN_C2PMSG_86', + 'mmMP0_SMN_C2PMSG_86_BASE_IDX', 'mmMP0_SMN_C2PMSG_87', + 'mmMP0_SMN_C2PMSG_87_BASE_IDX', 'mmMP0_SMN_C2PMSG_88', + 'mmMP0_SMN_C2PMSG_88_BASE_IDX', 'mmMP0_SMN_C2PMSG_89', + 'mmMP0_SMN_C2PMSG_89_BASE_IDX', 'mmMP0_SMN_C2PMSG_90', + 'mmMP0_SMN_C2PMSG_90_BASE_IDX', 'mmMP0_SMN_C2PMSG_91', + 'mmMP0_SMN_C2PMSG_91_BASE_IDX', 'mmMP0_SMN_C2PMSG_92', + 'mmMP0_SMN_C2PMSG_92_BASE_IDX', 'mmMP0_SMN_C2PMSG_93', + 'mmMP0_SMN_C2PMSG_93_BASE_IDX', 'mmMP0_SMN_C2PMSG_94', + 'mmMP0_SMN_C2PMSG_94_BASE_IDX', 'mmMP0_SMN_C2PMSG_95', + 'mmMP0_SMN_C2PMSG_95_BASE_IDX', 'mmMP0_SMN_C2PMSG_96', + 'mmMP0_SMN_C2PMSG_96_BASE_IDX', 'mmMP0_SMN_C2PMSG_97', + 'mmMP0_SMN_C2PMSG_97_BASE_IDX', 'mmMP0_SMN_C2PMSG_98', + 'mmMP0_SMN_C2PMSG_98_BASE_IDX', 'mmMP0_SMN_C2PMSG_99', + 'mmMP0_SMN_C2PMSG_99_BASE_IDX', 'mmMP0_SMN_IH_CREDIT', + 'mmMP0_SMN_IH_CREDIT_BASE_IDX', 'mmMP0_SMN_IH_SW_INT', + 'mmMP0_SMN_IH_SW_INT_BASE_IDX', 'mmMP0_SMN_IH_SW_INT_CTRL', + 'mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX', 'mmMP1_SMN_ACTIVE_FCN_ID', + 'mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX', 'mmMP1_SMN_C2PMSG_100', + 'mmMP1_SMN_C2PMSG_100_BASE_IDX', 'mmMP1_SMN_C2PMSG_101', + 'mmMP1_SMN_C2PMSG_101_BASE_IDX', 'mmMP1_SMN_C2PMSG_102', + 'mmMP1_SMN_C2PMSG_102_BASE_IDX', 'mmMP1_SMN_C2PMSG_103', + 'mmMP1_SMN_C2PMSG_103_BASE_IDX', 'mmMP1_SMN_C2PMSG_32', + 'mmMP1_SMN_C2PMSG_32_BASE_IDX', 'mmMP1_SMN_C2PMSG_33', + 'mmMP1_SMN_C2PMSG_33_BASE_IDX', 'mmMP1_SMN_C2PMSG_34', + 'mmMP1_SMN_C2PMSG_34_BASE_IDX', 'mmMP1_SMN_C2PMSG_35', + 'mmMP1_SMN_C2PMSG_35_BASE_IDX', 'mmMP1_SMN_C2PMSG_36', + 'mmMP1_SMN_C2PMSG_36_BASE_IDX', 'mmMP1_SMN_C2PMSG_37', + 'mmMP1_SMN_C2PMSG_37_BASE_IDX', 'mmMP1_SMN_C2PMSG_38', + 'mmMP1_SMN_C2PMSG_38_BASE_IDX', 'mmMP1_SMN_C2PMSG_39', + 'mmMP1_SMN_C2PMSG_39_BASE_IDX', 'mmMP1_SMN_C2PMSG_40', + 'mmMP1_SMN_C2PMSG_40_BASE_IDX', 'mmMP1_SMN_C2PMSG_41', + 'mmMP1_SMN_C2PMSG_41_BASE_IDX', 'mmMP1_SMN_C2PMSG_42', + 'mmMP1_SMN_C2PMSG_42_BASE_IDX', 'mmMP1_SMN_C2PMSG_43', + 'mmMP1_SMN_C2PMSG_43_BASE_IDX', 'mmMP1_SMN_C2PMSG_44', + 'mmMP1_SMN_C2PMSG_44_BASE_IDX', 'mmMP1_SMN_C2PMSG_45', + 'mmMP1_SMN_C2PMSG_45_BASE_IDX', 'mmMP1_SMN_C2PMSG_46', + 'mmMP1_SMN_C2PMSG_46_BASE_IDX', 'mmMP1_SMN_C2PMSG_47', + 'mmMP1_SMN_C2PMSG_47_BASE_IDX', 'mmMP1_SMN_C2PMSG_48', + 'mmMP1_SMN_C2PMSG_48_BASE_IDX', 'mmMP1_SMN_C2PMSG_49', + 'mmMP1_SMN_C2PMSG_49_BASE_IDX', 'mmMP1_SMN_C2PMSG_50', + 'mmMP1_SMN_C2PMSG_50_BASE_IDX', 'mmMP1_SMN_C2PMSG_51', + 'mmMP1_SMN_C2PMSG_51_BASE_IDX', 'mmMP1_SMN_C2PMSG_52', + 'mmMP1_SMN_C2PMSG_52_BASE_IDX', 'mmMP1_SMN_C2PMSG_53', + 'mmMP1_SMN_C2PMSG_53_BASE_IDX', 'mmMP1_SMN_C2PMSG_54', + 'mmMP1_SMN_C2PMSG_54_BASE_IDX', 'mmMP1_SMN_C2PMSG_55', + 'mmMP1_SMN_C2PMSG_55_BASE_IDX', 'mmMP1_SMN_C2PMSG_56', + 'mmMP1_SMN_C2PMSG_56_BASE_IDX', 'mmMP1_SMN_C2PMSG_57', + 'mmMP1_SMN_C2PMSG_57_BASE_IDX', 'mmMP1_SMN_C2PMSG_58', + 'mmMP1_SMN_C2PMSG_58_BASE_IDX', 'mmMP1_SMN_C2PMSG_59', + 'mmMP1_SMN_C2PMSG_59_BASE_IDX', 'mmMP1_SMN_C2PMSG_60', + 'mmMP1_SMN_C2PMSG_60_BASE_IDX', 'mmMP1_SMN_C2PMSG_61', + 'mmMP1_SMN_C2PMSG_61_BASE_IDX', 'mmMP1_SMN_C2PMSG_62', + 'mmMP1_SMN_C2PMSG_62_BASE_IDX', 'mmMP1_SMN_C2PMSG_63', + 'mmMP1_SMN_C2PMSG_63_BASE_IDX', 'mmMP1_SMN_C2PMSG_64', + 'mmMP1_SMN_C2PMSG_64_BASE_IDX', 'mmMP1_SMN_C2PMSG_65', + 'mmMP1_SMN_C2PMSG_65_BASE_IDX', 'mmMP1_SMN_C2PMSG_66', + 'mmMP1_SMN_C2PMSG_66_BASE_IDX', 'mmMP1_SMN_C2PMSG_67', + 'mmMP1_SMN_C2PMSG_67_BASE_IDX', 'mmMP1_SMN_C2PMSG_68', + 'mmMP1_SMN_C2PMSG_68_BASE_IDX', 'mmMP1_SMN_C2PMSG_69', + 'mmMP1_SMN_C2PMSG_69_BASE_IDX', 'mmMP1_SMN_C2PMSG_70', + 'mmMP1_SMN_C2PMSG_70_BASE_IDX', 'mmMP1_SMN_C2PMSG_71', + 'mmMP1_SMN_C2PMSG_71_BASE_IDX', 'mmMP1_SMN_C2PMSG_72', + 'mmMP1_SMN_C2PMSG_72_BASE_IDX', 'mmMP1_SMN_C2PMSG_73', + 'mmMP1_SMN_C2PMSG_73_BASE_IDX', 'mmMP1_SMN_C2PMSG_74', + 'mmMP1_SMN_C2PMSG_74_BASE_IDX', 'mmMP1_SMN_C2PMSG_75', + 'mmMP1_SMN_C2PMSG_75_BASE_IDX', 'mmMP1_SMN_C2PMSG_76', + 'mmMP1_SMN_C2PMSG_76_BASE_IDX', 'mmMP1_SMN_C2PMSG_77', + 'mmMP1_SMN_C2PMSG_77_BASE_IDX', 'mmMP1_SMN_C2PMSG_78', + 'mmMP1_SMN_C2PMSG_78_BASE_IDX', 'mmMP1_SMN_C2PMSG_79', + 'mmMP1_SMN_C2PMSG_79_BASE_IDX', 'mmMP1_SMN_C2PMSG_80', + 'mmMP1_SMN_C2PMSG_80_BASE_IDX', 'mmMP1_SMN_C2PMSG_81', + 'mmMP1_SMN_C2PMSG_81_BASE_IDX', 'mmMP1_SMN_C2PMSG_82', + 'mmMP1_SMN_C2PMSG_82_BASE_IDX', 'mmMP1_SMN_C2PMSG_83', + 'mmMP1_SMN_C2PMSG_83_BASE_IDX', 'mmMP1_SMN_C2PMSG_84', + 'mmMP1_SMN_C2PMSG_84_BASE_IDX', 'mmMP1_SMN_C2PMSG_85', + 'mmMP1_SMN_C2PMSG_85_BASE_IDX', 'mmMP1_SMN_C2PMSG_86', + 'mmMP1_SMN_C2PMSG_86_BASE_IDX', 'mmMP1_SMN_C2PMSG_87', + 'mmMP1_SMN_C2PMSG_87_BASE_IDX', 'mmMP1_SMN_C2PMSG_88', + 'mmMP1_SMN_C2PMSG_88_BASE_IDX', 'mmMP1_SMN_C2PMSG_89', + 'mmMP1_SMN_C2PMSG_89_BASE_IDX', 'mmMP1_SMN_C2PMSG_90', + 'mmMP1_SMN_C2PMSG_90_BASE_IDX', 'mmMP1_SMN_C2PMSG_91', + 'mmMP1_SMN_C2PMSG_91_BASE_IDX', 'mmMP1_SMN_C2PMSG_92', + 'mmMP1_SMN_C2PMSG_92_BASE_IDX', 'mmMP1_SMN_C2PMSG_93', + 'mmMP1_SMN_C2PMSG_93_BASE_IDX', 'mmMP1_SMN_C2PMSG_94', + 'mmMP1_SMN_C2PMSG_94_BASE_IDX', 'mmMP1_SMN_C2PMSG_95', + 'mmMP1_SMN_C2PMSG_95_BASE_IDX', 'mmMP1_SMN_C2PMSG_96', + 'mmMP1_SMN_C2PMSG_96_BASE_IDX', 'mmMP1_SMN_C2PMSG_97', + 'mmMP1_SMN_C2PMSG_97_BASE_IDX', 'mmMP1_SMN_C2PMSG_98', + 'mmMP1_SMN_C2PMSG_98_BASE_IDX', 'mmMP1_SMN_C2PMSG_99', + 'mmMP1_SMN_C2PMSG_99_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH0', + 'mmMP1_SMN_EXT_SCRATCH0_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH1', + 'mmMP1_SMN_EXT_SCRATCH1_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH2', + 'mmMP1_SMN_EXT_SCRATCH2_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH3', + 'mmMP1_SMN_EXT_SCRATCH3_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH4', + 'mmMP1_SMN_EXT_SCRATCH4_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH5', + 'mmMP1_SMN_EXT_SCRATCH5_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH6', + 'mmMP1_SMN_EXT_SCRATCH6_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH7', + 'mmMP1_SMN_EXT_SCRATCH7_BASE_IDX', 'mmMP1_SMN_FPS_CNT', + 'mmMP1_SMN_FPS_CNT_BASE_IDX', 'mmMP1_SMN_IH_CREDIT', + 'mmMP1_SMN_IH_CREDIT_BASE_IDX', 'mmMP1_SMN_IH_SW_INT', + 'mmMP1_SMN_IH_SW_INT_BASE_IDX', 'mmMP1_SMN_IH_SW_INT_CTRL', + 'mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX', 'mmMP1_SMN_PUB_CTRL', + 'mmMP1_SMN_PUB_CTRL_BASE_IDX', 'smnMP1_PMI_3', + 'smnMP1_PMI_3_FIFO', 'smnMP1_PMI_3_START'] diff --git a/tinygrad/runtime/autogen/am/mp_13_0_0.py b/tinygrad/runtime/autogen/am/mp_13_0_0.py new file mode 100644 index 0000000000..57494c2f10 --- /dev/null +++ b/tinygrad/runtime/autogen/am/mp_13_0_0.py @@ -0,0 +1,1509 @@ +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_mp_13_0_0_OFFSET_HEADER = True # macro +regMP0_SMN_C2PMSG_32 = 0x0060 # macro +regMP0_SMN_C2PMSG_32_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_33 = 0x0061 # macro +regMP0_SMN_C2PMSG_33_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_34 = 0x0062 # macro +regMP0_SMN_C2PMSG_34_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_35 = 0x0063 # macro +regMP0_SMN_C2PMSG_35_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_36 = 0x0064 # macro +regMP0_SMN_C2PMSG_36_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_37 = 0x0065 # macro +regMP0_SMN_C2PMSG_37_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_38 = 0x0066 # macro +regMP0_SMN_C2PMSG_38_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_39 = 0x0067 # macro +regMP0_SMN_C2PMSG_39_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_40 = 0x0068 # macro +regMP0_SMN_C2PMSG_40_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_41 = 0x0069 # macro +regMP0_SMN_C2PMSG_41_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_42 = 0x006a # macro +regMP0_SMN_C2PMSG_42_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_43 = 0x006b # macro +regMP0_SMN_C2PMSG_43_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_44 = 0x006c # macro +regMP0_SMN_C2PMSG_44_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_45 = 0x006d # macro +regMP0_SMN_C2PMSG_45_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_46 = 0x006e # macro +regMP0_SMN_C2PMSG_46_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_47 = 0x006f # macro +regMP0_SMN_C2PMSG_47_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_48 = 0x0070 # macro +regMP0_SMN_C2PMSG_48_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_49 = 0x0071 # macro +regMP0_SMN_C2PMSG_49_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_50 = 0x0072 # macro +regMP0_SMN_C2PMSG_50_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_51 = 0x0073 # macro +regMP0_SMN_C2PMSG_51_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_52 = 0x0074 # macro +regMP0_SMN_C2PMSG_52_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_53 = 0x0075 # macro +regMP0_SMN_C2PMSG_53_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_54 = 0x0076 # macro +regMP0_SMN_C2PMSG_54_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_55 = 0x0077 # macro +regMP0_SMN_C2PMSG_55_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_56 = 0x0078 # macro +regMP0_SMN_C2PMSG_56_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_57 = 0x0079 # macro +regMP0_SMN_C2PMSG_57_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_58 = 0x007a # macro +regMP0_SMN_C2PMSG_58_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_59 = 0x007b # macro +regMP0_SMN_C2PMSG_59_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_60 = 0x007c # macro +regMP0_SMN_C2PMSG_60_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_61 = 0x007d # macro +regMP0_SMN_C2PMSG_61_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_62 = 0x007e # macro +regMP0_SMN_C2PMSG_62_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_63 = 0x007f # macro +regMP0_SMN_C2PMSG_63_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_64 = 0x0080 # macro +regMP0_SMN_C2PMSG_64_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_65 = 0x0081 # macro +regMP0_SMN_C2PMSG_65_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_66 = 0x0082 # macro +regMP0_SMN_C2PMSG_66_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_67 = 0x0083 # macro +regMP0_SMN_C2PMSG_67_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_68 = 0x0084 # macro +regMP0_SMN_C2PMSG_68_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_69 = 0x0085 # macro +regMP0_SMN_C2PMSG_69_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_70 = 0x0086 # macro +regMP0_SMN_C2PMSG_70_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_71 = 0x0087 # macro +regMP0_SMN_C2PMSG_71_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_72 = 0x0088 # macro +regMP0_SMN_C2PMSG_72_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_73 = 0x0089 # macro +regMP0_SMN_C2PMSG_73_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_74 = 0x008a # macro +regMP0_SMN_C2PMSG_74_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_75 = 0x008b # macro +regMP0_SMN_C2PMSG_75_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_76 = 0x008c # macro +regMP0_SMN_C2PMSG_76_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_77 = 0x008d # macro +regMP0_SMN_C2PMSG_77_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_78 = 0x008e # macro +regMP0_SMN_C2PMSG_78_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_79 = 0x008f # macro +regMP0_SMN_C2PMSG_79_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_80 = 0x0090 # macro +regMP0_SMN_C2PMSG_80_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_81 = 0x0091 # macro +regMP0_SMN_C2PMSG_81_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_82 = 0x0092 # macro +regMP0_SMN_C2PMSG_82_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_83 = 0x0093 # macro +regMP0_SMN_C2PMSG_83_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_84 = 0x0094 # macro +regMP0_SMN_C2PMSG_84_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_85 = 0x0095 # macro +regMP0_SMN_C2PMSG_85_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_86 = 0x0096 # macro +regMP0_SMN_C2PMSG_86_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_87 = 0x0097 # macro +regMP0_SMN_C2PMSG_87_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_88 = 0x0098 # macro +regMP0_SMN_C2PMSG_88_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_89 = 0x0099 # macro +regMP0_SMN_C2PMSG_89_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_90 = 0x009a # macro +regMP0_SMN_C2PMSG_90_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_91 = 0x009b # macro +regMP0_SMN_C2PMSG_91_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_92 = 0x009c # macro +regMP0_SMN_C2PMSG_92_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_93 = 0x009d # macro +regMP0_SMN_C2PMSG_93_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_94 = 0x009e # macro +regMP0_SMN_C2PMSG_94_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_95 = 0x009f # macro +regMP0_SMN_C2PMSG_95_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_96 = 0x00a0 # macro +regMP0_SMN_C2PMSG_96_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_97 = 0x00a1 # macro +regMP0_SMN_C2PMSG_97_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_98 = 0x00a2 # macro +regMP0_SMN_C2PMSG_98_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_99 = 0x00a3 # macro +regMP0_SMN_C2PMSG_99_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_100 = 0x00a4 # macro +regMP0_SMN_C2PMSG_100_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_101 = 0x00a5 # macro +regMP0_SMN_C2PMSG_101_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_102 = 0x00a6 # macro +regMP0_SMN_C2PMSG_102_BASE_IDX = 0 # macro +regMP0_SMN_C2PMSG_103 = 0x00a7 # macro +regMP0_SMN_C2PMSG_103_BASE_IDX = 0 # macro +regMP0_SMN_IH_CREDIT = 0x00c1 # macro +regMP0_SMN_IH_CREDIT_BASE_IDX = 0 # macro +regMP0_SMN_IH_SW_INT = 0x00c2 # macro +regMP0_SMN_IH_SW_INT_BASE_IDX = 0 # macro +regMP0_SMN_IH_SW_INT_CTRL = 0x00c3 # macro +regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_32 = 0x0260 # macro +regMP1_SMN_C2PMSG_32_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_33 = 0x0261 # macro +regMP1_SMN_C2PMSG_33_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_34 = 0x0262 # macro +regMP1_SMN_C2PMSG_34_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_35 = 0x0263 # macro +regMP1_SMN_C2PMSG_35_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_36 = 0x0264 # macro +regMP1_SMN_C2PMSG_36_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_37 = 0x0265 # macro +regMP1_SMN_C2PMSG_37_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_38 = 0x0266 # macro +regMP1_SMN_C2PMSG_38_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_39 = 0x0267 # macro +regMP1_SMN_C2PMSG_39_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_40 = 0x0268 # macro +regMP1_SMN_C2PMSG_40_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_41 = 0x0269 # macro +regMP1_SMN_C2PMSG_41_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_42 = 0x026a # macro +regMP1_SMN_C2PMSG_42_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_43 = 0x026b # macro +regMP1_SMN_C2PMSG_43_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_44 = 0x026c # macro +regMP1_SMN_C2PMSG_44_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_45 = 0x026d # macro +regMP1_SMN_C2PMSG_45_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_46 = 0x026e # macro +regMP1_SMN_C2PMSG_46_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_47 = 0x026f # macro +regMP1_SMN_C2PMSG_47_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_48 = 0x0270 # macro +regMP1_SMN_C2PMSG_48_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_49 = 0x0271 # macro +regMP1_SMN_C2PMSG_49_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_50 = 0x0272 # macro +regMP1_SMN_C2PMSG_50_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_51 = 0x0273 # macro +regMP1_SMN_C2PMSG_51_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_52 = 0x0274 # macro +regMP1_SMN_C2PMSG_52_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_53 = 0x0275 # macro +regMP1_SMN_C2PMSG_53_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_54 = 0x0276 # macro +regMP1_SMN_C2PMSG_54_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_55 = 0x0277 # macro +regMP1_SMN_C2PMSG_55_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_56 = 0x0278 # macro +regMP1_SMN_C2PMSG_56_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_57 = 0x0279 # macro +regMP1_SMN_C2PMSG_57_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_58 = 0x027a # macro +regMP1_SMN_C2PMSG_58_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_59 = 0x027b # macro +regMP1_SMN_C2PMSG_59_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_60 = 0x027c # macro +regMP1_SMN_C2PMSG_60_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_61 = 0x027d # macro +regMP1_SMN_C2PMSG_61_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_62 = 0x027e # macro +regMP1_SMN_C2PMSG_62_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_63 = 0x027f # macro +regMP1_SMN_C2PMSG_63_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_64 = 0x0280 # macro +regMP1_SMN_C2PMSG_64_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_65 = 0x0281 # macro +regMP1_SMN_C2PMSG_65_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_66 = 0x0282 # macro +regMP1_SMN_C2PMSG_66_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_67 = 0x0283 # macro +regMP1_SMN_C2PMSG_67_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_68 = 0x0284 # macro +regMP1_SMN_C2PMSG_68_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_69 = 0x0285 # macro +regMP1_SMN_C2PMSG_69_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_70 = 0x0286 # macro +regMP1_SMN_C2PMSG_70_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_71 = 0x0287 # macro +regMP1_SMN_C2PMSG_71_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_72 = 0x0288 # macro +regMP1_SMN_C2PMSG_72_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_73 = 0x0289 # macro +regMP1_SMN_C2PMSG_73_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_74 = 0x028a # macro +regMP1_SMN_C2PMSG_74_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_75 = 0x028b # macro +regMP1_SMN_C2PMSG_75_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_76 = 0x028c # macro +regMP1_SMN_C2PMSG_76_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_77 = 0x028d # macro +regMP1_SMN_C2PMSG_77_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_78 = 0x028e # macro +regMP1_SMN_C2PMSG_78_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_79 = 0x028f # macro +regMP1_SMN_C2PMSG_79_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_80 = 0x0290 # macro +regMP1_SMN_C2PMSG_80_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_81 = 0x0291 # macro +regMP1_SMN_C2PMSG_81_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_82 = 0x0292 # macro +regMP1_SMN_C2PMSG_82_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_83 = 0x0293 # macro +regMP1_SMN_C2PMSG_83_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_84 = 0x0294 # macro +regMP1_SMN_C2PMSG_84_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_85 = 0x0295 # macro +regMP1_SMN_C2PMSG_85_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_86 = 0x0296 # macro +regMP1_SMN_C2PMSG_86_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_87 = 0x0297 # macro +regMP1_SMN_C2PMSG_87_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_88 = 0x0298 # macro +regMP1_SMN_C2PMSG_88_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_89 = 0x0299 # macro +regMP1_SMN_C2PMSG_89_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_90 = 0x029a # macro +regMP1_SMN_C2PMSG_90_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_91 = 0x029b # macro +regMP1_SMN_C2PMSG_91_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_92 = 0x029c # macro +regMP1_SMN_C2PMSG_92_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_93 = 0x029d # macro +regMP1_SMN_C2PMSG_93_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_94 = 0x029e # macro +regMP1_SMN_C2PMSG_94_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_95 = 0x029f # macro +regMP1_SMN_C2PMSG_95_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_96 = 0x02a0 # macro +regMP1_SMN_C2PMSG_96_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_97 = 0x02a1 # macro +regMP1_SMN_C2PMSG_97_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_98 = 0x02a2 # macro +regMP1_SMN_C2PMSG_98_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_99 = 0x02a3 # macro +regMP1_SMN_C2PMSG_99_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_100 = 0x02a4 # macro +regMP1_SMN_C2PMSG_100_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_101 = 0x02a5 # macro +regMP1_SMN_C2PMSG_101_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_102 = 0x02a6 # macro +regMP1_SMN_C2PMSG_102_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_103 = 0x02a7 # macro +regMP1_SMN_C2PMSG_103_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_104 = 0x02a8 # macro +regMP1_SMN_C2PMSG_104_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_105 = 0x02a9 # macro +regMP1_SMN_C2PMSG_105_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_106 = 0x02aa # macro +regMP1_SMN_C2PMSG_106_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_107 = 0x02ab # macro +regMP1_SMN_C2PMSG_107_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_108 = 0x02ac # macro +regMP1_SMN_C2PMSG_108_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_109 = 0x02ad # macro +regMP1_SMN_C2PMSG_109_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_110 = 0x02ae # macro +regMP1_SMN_C2PMSG_110_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_111 = 0x02af # macro +regMP1_SMN_C2PMSG_111_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_112 = 0x02b0 # macro +regMP1_SMN_C2PMSG_112_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_113 = 0x02b1 # macro +regMP1_SMN_C2PMSG_113_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_114 = 0x02b2 # macro +regMP1_SMN_C2PMSG_114_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_115 = 0x02b3 # macro +regMP1_SMN_C2PMSG_115_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_116 = 0x02b4 # macro +regMP1_SMN_C2PMSG_116_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_117 = 0x02b5 # macro +regMP1_SMN_C2PMSG_117_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_118 = 0x02b6 # macro +regMP1_SMN_C2PMSG_118_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_119 = 0x02b7 # macro +regMP1_SMN_C2PMSG_119_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_120 = 0x02b8 # macro +regMP1_SMN_C2PMSG_120_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_121 = 0x02b9 # macro +regMP1_SMN_C2PMSG_121_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_122 = 0x02ba # macro +regMP1_SMN_C2PMSG_122_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_123 = 0x02bb # macro +regMP1_SMN_C2PMSG_123_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_124 = 0x02bc # macro +regMP1_SMN_C2PMSG_124_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_125 = 0x02bd # macro +regMP1_SMN_C2PMSG_125_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_126 = 0x02be # macro +regMP1_SMN_C2PMSG_126_BASE_IDX = 0 # macro +regMP1_SMN_C2PMSG_127 = 0x02bf # macro +regMP1_SMN_C2PMSG_127_BASE_IDX = 0 # macro +regMP1_SMN_IH_CREDIT = 0x02c1 # macro +regMP1_SMN_IH_CREDIT_BASE_IDX = 0 # macro +regMP1_SMN_IH_SW_INT = 0x02c2 # macro +regMP1_SMN_IH_SW_INT_BASE_IDX = 0 # macro +regMP1_SMN_IH_SW_INT_CTRL = 0x02c3 # macro +regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro +regMP1_SMN_FPS_CNT = 0x02c4 # macro +regMP1_SMN_FPS_CNT_BASE_IDX = 0 # macro +regMP1_SMN_PUB_CTRL = 0x02c5 # macro +regMP1_SMN_PUB_CTRL_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH0 = 0x0340 # macro +regMP1_SMN_EXT_SCRATCH0_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH1 = 0x0341 # macro +regMP1_SMN_EXT_SCRATCH1_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH2 = 0x0342 # macro +regMP1_SMN_EXT_SCRATCH2_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH3 = 0x0343 # macro +regMP1_SMN_EXT_SCRATCH3_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH4 = 0x0344 # macro +regMP1_SMN_EXT_SCRATCH4_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH5 = 0x0345 # macro +regMP1_SMN_EXT_SCRATCH5_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH6 = 0x0346 # macro +regMP1_SMN_EXT_SCRATCH6_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH7 = 0x0347 # macro +regMP1_SMN_EXT_SCRATCH7_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH8 = 0x0348 # macro +regMP1_SMN_EXT_SCRATCH8_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH10 = 0x034a # macro +regMP1_SMN_EXT_SCRATCH10_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH11 = 0x034b # macro +regMP1_SMN_EXT_SCRATCH11_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH12 = 0x034c # macro +regMP1_SMN_EXT_SCRATCH12_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH13 = 0x034d # macro +regMP1_SMN_EXT_SCRATCH13_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH14 = 0x034e # macro +regMP1_SMN_EXT_SCRATCH14_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH15 = 0x034f # macro +regMP1_SMN_EXT_SCRATCH15_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH16 = 0x0350 # macro +regMP1_SMN_EXT_SCRATCH16_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH17 = 0x0351 # macro +regMP1_SMN_EXT_SCRATCH17_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH18 = 0x0352 # macro +regMP1_SMN_EXT_SCRATCH18_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH19 = 0x0353 # macro +regMP1_SMN_EXT_SCRATCH19_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH20 = 0x0354 # macro +regMP1_SMN_EXT_SCRATCH20_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH21 = 0x0355 # macro +regMP1_SMN_EXT_SCRATCH21_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH22 = 0x0356 # macro +regMP1_SMN_EXT_SCRATCH22_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH23 = 0x0357 # macro +regMP1_SMN_EXT_SCRATCH23_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH24 = 0x0358 # macro +regMP1_SMN_EXT_SCRATCH24_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH25 = 0x0359 # macro +regMP1_SMN_EXT_SCRATCH25_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH26 = 0x035a # macro +regMP1_SMN_EXT_SCRATCH26_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH27 = 0x035b # macro +regMP1_SMN_EXT_SCRATCH27_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH28 = 0x035c # macro +regMP1_SMN_EXT_SCRATCH28_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH29 = 0x035d # macro +regMP1_SMN_EXT_SCRATCH29_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH30 = 0x035e # macro +regMP1_SMN_EXT_SCRATCH30_BASE_IDX = 0 # macro +regMP1_SMN_EXT_SCRATCH31 = 0x035f # macro +regMP1_SMN_EXT_SCRATCH31_BASE_IDX = 0 # macro +regMP1_FIRMWARE_FLAGS = 0xbee009 # macro +regMP1_FIRMWARE_FLAGS_BASE_IDX = 0 # macro +regMPIO_FIRMWARE_FLAGS = 0xbee009 # macro +regMPIO_FIRMWARE_FLAGS_BASE_IDX = 0 # macro +_mp_13_0_0_SH_MASK_HEADER = True # macro +MP0_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro +MP0_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro +MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro +MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro +MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro +MP0_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro +MP0_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro +MP0_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro +MP0_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro +MP0_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro +MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro +MP1_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_104__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_104__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_105__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_105__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_106__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_106__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_107__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_107__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_108__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_108__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_109__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_109__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_110__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_110__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_111__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_111__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_112__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_112__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_113__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_113__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_114__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_114__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_115__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_115__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_116__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_116__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_117__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_117__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_118__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_118__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_119__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_119__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_120__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_120__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_121__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_121__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_122__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_122__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_123__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_123__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_124__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_124__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_125__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_125__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_126__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_126__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_C2PMSG_127__CONTENT__SHIFT = 0x0 # macro +MP1_SMN_C2PMSG_127__CONTENT_MASK = 0xFFFFFFFF # macro +MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro +MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro +MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro +MP1_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro +MP1_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro +MP1_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro +MP1_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro +MP1_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro +MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro +MP1_SMN_FPS_CNT__COUNT__SHIFT = 0x0 # macro +MP1_SMN_FPS_CNT__COUNT_MASK = 0xFFFFFFFF # macro +MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT = 0x0 # macro +MP1_SMN_PUB_CTRL__LX3_RESET_MASK = 0x00000001 # macro +MP1_SMN_EXT_SCRATCH0__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH1__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH2__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH3__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH4__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH4__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH5__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH5__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH6__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH6__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH7__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH7__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH8__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH8__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH10__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH10__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH11__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH11__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH12__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH12__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH13__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH13__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH14__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH14__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH15__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH15__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH16__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH16__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH17__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH17__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH18__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH18__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH19__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH19__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH20__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH20__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH21__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH21__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH22__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH22__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH23__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH23__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH24__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH24__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH25__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH25__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH26__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH26__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH27__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH27__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH28__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH28__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH29__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH29__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH30__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH30__DATA_MASK = 0xFFFFFFFF # macro +MP1_SMN_EXT_SCRATCH31__DATA__SHIFT = 0x0 # macro +MP1_SMN_EXT_SCRATCH31__DATA_MASK = 0xFFFFFFFF # macro +MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT = 0x0 # macro +MP1_FIRMWARE_FLAGS__RESERVED__SHIFT = 0x1 # macro +MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK = 0x00000001 # macro +MP1_FIRMWARE_FLAGS__RESERVED_MASK = 0xFFFFFFFE # macro +MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT = 0x0 # macro +MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT = 0x1 # macro +MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK = 0x00000001 # macro +MPIO_FIRMWARE_FLAGS__RESERVED_MASK = 0xFFFFFFFE # macro +__all__ = \ + ['MP0_SMN_C2PMSG_100__CONTENT_MASK', + 'MP0_SMN_C2PMSG_100__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_101__CONTENT_MASK', + 'MP0_SMN_C2PMSG_101__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_102__CONTENT_MASK', + 'MP0_SMN_C2PMSG_102__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_103__CONTENT_MASK', + 'MP0_SMN_C2PMSG_103__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_32__CONTENT_MASK', + 'MP0_SMN_C2PMSG_32__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_33__CONTENT_MASK', + 'MP0_SMN_C2PMSG_33__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_34__CONTENT_MASK', + 'MP0_SMN_C2PMSG_34__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_35__CONTENT_MASK', + 'MP0_SMN_C2PMSG_35__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_36__CONTENT_MASK', + 'MP0_SMN_C2PMSG_36__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_37__CONTENT_MASK', + 'MP0_SMN_C2PMSG_37__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_38__CONTENT_MASK', + 'MP0_SMN_C2PMSG_38__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_39__CONTENT_MASK', + 'MP0_SMN_C2PMSG_39__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_40__CONTENT_MASK', + 'MP0_SMN_C2PMSG_40__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_41__CONTENT_MASK', + 'MP0_SMN_C2PMSG_41__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_42__CONTENT_MASK', + 'MP0_SMN_C2PMSG_42__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_43__CONTENT_MASK', + 'MP0_SMN_C2PMSG_43__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_44__CONTENT_MASK', + 'MP0_SMN_C2PMSG_44__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_45__CONTENT_MASK', + 'MP0_SMN_C2PMSG_45__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_46__CONTENT_MASK', + 'MP0_SMN_C2PMSG_46__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_47__CONTENT_MASK', + 'MP0_SMN_C2PMSG_47__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_48__CONTENT_MASK', + 'MP0_SMN_C2PMSG_48__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_49__CONTENT_MASK', + 'MP0_SMN_C2PMSG_49__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_50__CONTENT_MASK', + 'MP0_SMN_C2PMSG_50__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_51__CONTENT_MASK', + 'MP0_SMN_C2PMSG_51__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_52__CONTENT_MASK', + 'MP0_SMN_C2PMSG_52__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_53__CONTENT_MASK', + 'MP0_SMN_C2PMSG_53__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_54__CONTENT_MASK', + 'MP0_SMN_C2PMSG_54__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_55__CONTENT_MASK', + 'MP0_SMN_C2PMSG_55__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_56__CONTENT_MASK', + 'MP0_SMN_C2PMSG_56__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_57__CONTENT_MASK', + 'MP0_SMN_C2PMSG_57__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_58__CONTENT_MASK', + 'MP0_SMN_C2PMSG_58__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_59__CONTENT_MASK', + 'MP0_SMN_C2PMSG_59__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_60__CONTENT_MASK', + 'MP0_SMN_C2PMSG_60__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_61__CONTENT_MASK', + 'MP0_SMN_C2PMSG_61__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_62__CONTENT_MASK', + 'MP0_SMN_C2PMSG_62__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_63__CONTENT_MASK', + 'MP0_SMN_C2PMSG_63__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_64__CONTENT_MASK', + 'MP0_SMN_C2PMSG_64__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_65__CONTENT_MASK', + 'MP0_SMN_C2PMSG_65__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_66__CONTENT_MASK', + 'MP0_SMN_C2PMSG_66__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_67__CONTENT_MASK', + 'MP0_SMN_C2PMSG_67__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_68__CONTENT_MASK', + 'MP0_SMN_C2PMSG_68__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_69__CONTENT_MASK', + 'MP0_SMN_C2PMSG_69__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_70__CONTENT_MASK', + 'MP0_SMN_C2PMSG_70__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_71__CONTENT_MASK', + 'MP0_SMN_C2PMSG_71__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_72__CONTENT_MASK', + 'MP0_SMN_C2PMSG_72__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_73__CONTENT_MASK', + 'MP0_SMN_C2PMSG_73__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_74__CONTENT_MASK', + 'MP0_SMN_C2PMSG_74__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_75__CONTENT_MASK', + 'MP0_SMN_C2PMSG_75__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_76__CONTENT_MASK', + 'MP0_SMN_C2PMSG_76__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_77__CONTENT_MASK', + 'MP0_SMN_C2PMSG_77__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_78__CONTENT_MASK', + 'MP0_SMN_C2PMSG_78__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_79__CONTENT_MASK', + 'MP0_SMN_C2PMSG_79__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_80__CONTENT_MASK', + 'MP0_SMN_C2PMSG_80__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_81__CONTENT_MASK', + 'MP0_SMN_C2PMSG_81__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_82__CONTENT_MASK', + 'MP0_SMN_C2PMSG_82__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_83__CONTENT_MASK', + 'MP0_SMN_C2PMSG_83__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_84__CONTENT_MASK', + 'MP0_SMN_C2PMSG_84__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_85__CONTENT_MASK', + 'MP0_SMN_C2PMSG_85__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_86__CONTENT_MASK', + 'MP0_SMN_C2PMSG_86__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_87__CONTENT_MASK', + 'MP0_SMN_C2PMSG_87__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_88__CONTENT_MASK', + 'MP0_SMN_C2PMSG_88__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_89__CONTENT_MASK', + 'MP0_SMN_C2PMSG_89__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_90__CONTENT_MASK', + 'MP0_SMN_C2PMSG_90__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_91__CONTENT_MASK', + 'MP0_SMN_C2PMSG_91__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_92__CONTENT_MASK', + 'MP0_SMN_C2PMSG_92__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_93__CONTENT_MASK', + 'MP0_SMN_C2PMSG_93__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_94__CONTENT_MASK', + 'MP0_SMN_C2PMSG_94__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_95__CONTENT_MASK', + 'MP0_SMN_C2PMSG_95__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_96__CONTENT_MASK', + 'MP0_SMN_C2PMSG_96__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_97__CONTENT_MASK', + 'MP0_SMN_C2PMSG_97__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_98__CONTENT_MASK', + 'MP0_SMN_C2PMSG_98__CONTENT__SHIFT', + 'MP0_SMN_C2PMSG_99__CONTENT_MASK', + 'MP0_SMN_C2PMSG_99__CONTENT__SHIFT', + 'MP0_SMN_IH_CREDIT__CLIENT_ID_MASK', + 'MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT', + 'MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK', + 'MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT', + 'MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK', + 'MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT', + 'MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK', + 'MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT', + 'MP0_SMN_IH_SW_INT__ID_MASK', 'MP0_SMN_IH_SW_INT__ID__SHIFT', + 'MP0_SMN_IH_SW_INT__VALID_MASK', + 'MP0_SMN_IH_SW_INT__VALID__SHIFT', + 'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK', + 'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT', + 'MP1_FIRMWARE_FLAGS__RESERVED_MASK', + 'MP1_FIRMWARE_FLAGS__RESERVED__SHIFT', + 'MP1_SMN_C2PMSG_100__CONTENT_MASK', + 'MP1_SMN_C2PMSG_100__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_101__CONTENT_MASK', + 'MP1_SMN_C2PMSG_101__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_102__CONTENT_MASK', + 'MP1_SMN_C2PMSG_102__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_103__CONTENT_MASK', + 'MP1_SMN_C2PMSG_103__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_104__CONTENT_MASK', + 'MP1_SMN_C2PMSG_104__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_105__CONTENT_MASK', + 'MP1_SMN_C2PMSG_105__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_106__CONTENT_MASK', + 'MP1_SMN_C2PMSG_106__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_107__CONTENT_MASK', + 'MP1_SMN_C2PMSG_107__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_108__CONTENT_MASK', + 'MP1_SMN_C2PMSG_108__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_109__CONTENT_MASK', + 'MP1_SMN_C2PMSG_109__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_110__CONTENT_MASK', + 'MP1_SMN_C2PMSG_110__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_111__CONTENT_MASK', + 'MP1_SMN_C2PMSG_111__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_112__CONTENT_MASK', + 'MP1_SMN_C2PMSG_112__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_113__CONTENT_MASK', + 'MP1_SMN_C2PMSG_113__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_114__CONTENT_MASK', + 'MP1_SMN_C2PMSG_114__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_115__CONTENT_MASK', + 'MP1_SMN_C2PMSG_115__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_116__CONTENT_MASK', + 'MP1_SMN_C2PMSG_116__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_117__CONTENT_MASK', + 'MP1_SMN_C2PMSG_117__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_118__CONTENT_MASK', + 'MP1_SMN_C2PMSG_118__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_119__CONTENT_MASK', + 'MP1_SMN_C2PMSG_119__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_120__CONTENT_MASK', + 'MP1_SMN_C2PMSG_120__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_121__CONTENT_MASK', + 'MP1_SMN_C2PMSG_121__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_122__CONTENT_MASK', + 'MP1_SMN_C2PMSG_122__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_123__CONTENT_MASK', + 'MP1_SMN_C2PMSG_123__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_124__CONTENT_MASK', + 'MP1_SMN_C2PMSG_124__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_125__CONTENT_MASK', + 'MP1_SMN_C2PMSG_125__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_126__CONTENT_MASK', + 'MP1_SMN_C2PMSG_126__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_127__CONTENT_MASK', + 'MP1_SMN_C2PMSG_127__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_32__CONTENT_MASK', + 'MP1_SMN_C2PMSG_32__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_33__CONTENT_MASK', + 'MP1_SMN_C2PMSG_33__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_34__CONTENT_MASK', + 'MP1_SMN_C2PMSG_34__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_35__CONTENT_MASK', + 'MP1_SMN_C2PMSG_35__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_36__CONTENT_MASK', + 'MP1_SMN_C2PMSG_36__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_37__CONTENT_MASK', + 'MP1_SMN_C2PMSG_37__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_38__CONTENT_MASK', + 'MP1_SMN_C2PMSG_38__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_39__CONTENT_MASK', + 'MP1_SMN_C2PMSG_39__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_40__CONTENT_MASK', + 'MP1_SMN_C2PMSG_40__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_41__CONTENT_MASK', + 'MP1_SMN_C2PMSG_41__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_42__CONTENT_MASK', + 'MP1_SMN_C2PMSG_42__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_43__CONTENT_MASK', + 'MP1_SMN_C2PMSG_43__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_44__CONTENT_MASK', + 'MP1_SMN_C2PMSG_44__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_45__CONTENT_MASK', + 'MP1_SMN_C2PMSG_45__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_46__CONTENT_MASK', + 'MP1_SMN_C2PMSG_46__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_47__CONTENT_MASK', + 'MP1_SMN_C2PMSG_47__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_48__CONTENT_MASK', + 'MP1_SMN_C2PMSG_48__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_49__CONTENT_MASK', + 'MP1_SMN_C2PMSG_49__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_50__CONTENT_MASK', + 'MP1_SMN_C2PMSG_50__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_51__CONTENT_MASK', + 'MP1_SMN_C2PMSG_51__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_52__CONTENT_MASK', + 'MP1_SMN_C2PMSG_52__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_53__CONTENT_MASK', + 'MP1_SMN_C2PMSG_53__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_54__CONTENT_MASK', + 'MP1_SMN_C2PMSG_54__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_55__CONTENT_MASK', + 'MP1_SMN_C2PMSG_55__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_56__CONTENT_MASK', + 'MP1_SMN_C2PMSG_56__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_57__CONTENT_MASK', + 'MP1_SMN_C2PMSG_57__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_58__CONTENT_MASK', + 'MP1_SMN_C2PMSG_58__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_59__CONTENT_MASK', + 'MP1_SMN_C2PMSG_59__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_60__CONTENT_MASK', + 'MP1_SMN_C2PMSG_60__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_61__CONTENT_MASK', + 'MP1_SMN_C2PMSG_61__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_62__CONTENT_MASK', + 'MP1_SMN_C2PMSG_62__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_63__CONTENT_MASK', + 'MP1_SMN_C2PMSG_63__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_64__CONTENT_MASK', + 'MP1_SMN_C2PMSG_64__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_65__CONTENT_MASK', + 'MP1_SMN_C2PMSG_65__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_66__CONTENT_MASK', + 'MP1_SMN_C2PMSG_66__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_67__CONTENT_MASK', + 'MP1_SMN_C2PMSG_67__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_68__CONTENT_MASK', + 'MP1_SMN_C2PMSG_68__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_69__CONTENT_MASK', + 'MP1_SMN_C2PMSG_69__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_70__CONTENT_MASK', + 'MP1_SMN_C2PMSG_70__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_71__CONTENT_MASK', + 'MP1_SMN_C2PMSG_71__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_72__CONTENT_MASK', + 'MP1_SMN_C2PMSG_72__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_73__CONTENT_MASK', + 'MP1_SMN_C2PMSG_73__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_74__CONTENT_MASK', + 'MP1_SMN_C2PMSG_74__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_75__CONTENT_MASK', + 'MP1_SMN_C2PMSG_75__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_76__CONTENT_MASK', + 'MP1_SMN_C2PMSG_76__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_77__CONTENT_MASK', + 'MP1_SMN_C2PMSG_77__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_78__CONTENT_MASK', + 'MP1_SMN_C2PMSG_78__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_79__CONTENT_MASK', + 'MP1_SMN_C2PMSG_79__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_80__CONTENT_MASK', + 'MP1_SMN_C2PMSG_80__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_81__CONTENT_MASK', + 'MP1_SMN_C2PMSG_81__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_82__CONTENT_MASK', + 'MP1_SMN_C2PMSG_82__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_83__CONTENT_MASK', + 'MP1_SMN_C2PMSG_83__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_84__CONTENT_MASK', + 'MP1_SMN_C2PMSG_84__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_85__CONTENT_MASK', + 'MP1_SMN_C2PMSG_85__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_86__CONTENT_MASK', + 'MP1_SMN_C2PMSG_86__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_87__CONTENT_MASK', + 'MP1_SMN_C2PMSG_87__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_88__CONTENT_MASK', + 'MP1_SMN_C2PMSG_88__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_89__CONTENT_MASK', + 'MP1_SMN_C2PMSG_89__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_90__CONTENT_MASK', + 'MP1_SMN_C2PMSG_90__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_91__CONTENT_MASK', + 'MP1_SMN_C2PMSG_91__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_92__CONTENT_MASK', + 'MP1_SMN_C2PMSG_92__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_93__CONTENT_MASK', + 'MP1_SMN_C2PMSG_93__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_94__CONTENT_MASK', + 'MP1_SMN_C2PMSG_94__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_95__CONTENT_MASK', + 'MP1_SMN_C2PMSG_95__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_96__CONTENT_MASK', + 'MP1_SMN_C2PMSG_96__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_97__CONTENT_MASK', + 'MP1_SMN_C2PMSG_97__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_98__CONTENT_MASK', + 'MP1_SMN_C2PMSG_98__CONTENT__SHIFT', + 'MP1_SMN_C2PMSG_99__CONTENT_MASK', + 'MP1_SMN_C2PMSG_99__CONTENT__SHIFT', + 'MP1_SMN_EXT_SCRATCH0__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH0__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH10__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH10__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH11__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH11__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH12__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH12__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH13__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH13__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH14__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH14__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH15__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH15__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH16__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH16__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH17__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH17__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH18__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH18__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH19__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH19__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH1__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH1__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH20__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH20__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH21__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH21__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH22__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH22__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH23__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH23__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH24__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH24__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH25__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH25__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH26__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH26__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH27__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH27__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH28__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH28__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH29__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH29__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH2__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH2__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH30__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH30__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH31__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH31__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH3__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH3__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH4__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH4__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH5__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH5__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH6__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH6__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH7__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH7__DATA__SHIFT', + 'MP1_SMN_EXT_SCRATCH8__DATA_MASK', + 'MP1_SMN_EXT_SCRATCH8__DATA__SHIFT', + 'MP1_SMN_FPS_CNT__COUNT_MASK', 'MP1_SMN_FPS_CNT__COUNT__SHIFT', + 'MP1_SMN_IH_CREDIT__CLIENT_ID_MASK', + 'MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT', + 'MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK', + 'MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT', + 'MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK', + 'MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT', + 'MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK', + 'MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT', + 'MP1_SMN_IH_SW_INT__ID_MASK', 'MP1_SMN_IH_SW_INT__ID__SHIFT', + 'MP1_SMN_IH_SW_INT__VALID_MASK', + 'MP1_SMN_IH_SW_INT__VALID__SHIFT', + 'MP1_SMN_PUB_CTRL__LX3_RESET_MASK', + 'MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT', + 'MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK', + 'MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT', + 'MPIO_FIRMWARE_FLAGS__RESERVED_MASK', + 'MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT', + '_mp_13_0_0_OFFSET_HEADER', '_mp_13_0_0_SH_MASK_HEADER', + 'regMP0_SMN_C2PMSG_100', 'regMP0_SMN_C2PMSG_100_BASE_IDX', + 'regMP0_SMN_C2PMSG_101', 'regMP0_SMN_C2PMSG_101_BASE_IDX', + 'regMP0_SMN_C2PMSG_102', 'regMP0_SMN_C2PMSG_102_BASE_IDX', + 'regMP0_SMN_C2PMSG_103', 'regMP0_SMN_C2PMSG_103_BASE_IDX', + 'regMP0_SMN_C2PMSG_32', 'regMP0_SMN_C2PMSG_32_BASE_IDX', + 'regMP0_SMN_C2PMSG_33', 'regMP0_SMN_C2PMSG_33_BASE_IDX', + 'regMP0_SMN_C2PMSG_34', 'regMP0_SMN_C2PMSG_34_BASE_IDX', + 'regMP0_SMN_C2PMSG_35', 'regMP0_SMN_C2PMSG_35_BASE_IDX', + 'regMP0_SMN_C2PMSG_36', 'regMP0_SMN_C2PMSG_36_BASE_IDX', + 'regMP0_SMN_C2PMSG_37', 'regMP0_SMN_C2PMSG_37_BASE_IDX', + 'regMP0_SMN_C2PMSG_38', 'regMP0_SMN_C2PMSG_38_BASE_IDX', + 'regMP0_SMN_C2PMSG_39', 'regMP0_SMN_C2PMSG_39_BASE_IDX', + 'regMP0_SMN_C2PMSG_40', 'regMP0_SMN_C2PMSG_40_BASE_IDX', + 'regMP0_SMN_C2PMSG_41', 'regMP0_SMN_C2PMSG_41_BASE_IDX', + 'regMP0_SMN_C2PMSG_42', 'regMP0_SMN_C2PMSG_42_BASE_IDX', + 'regMP0_SMN_C2PMSG_43', 'regMP0_SMN_C2PMSG_43_BASE_IDX', + 'regMP0_SMN_C2PMSG_44', 'regMP0_SMN_C2PMSG_44_BASE_IDX', + 'regMP0_SMN_C2PMSG_45', 'regMP0_SMN_C2PMSG_45_BASE_IDX', + 'regMP0_SMN_C2PMSG_46', 'regMP0_SMN_C2PMSG_46_BASE_IDX', + 'regMP0_SMN_C2PMSG_47', 'regMP0_SMN_C2PMSG_47_BASE_IDX', + 'regMP0_SMN_C2PMSG_48', 'regMP0_SMN_C2PMSG_48_BASE_IDX', + 'regMP0_SMN_C2PMSG_49', 'regMP0_SMN_C2PMSG_49_BASE_IDX', + 'regMP0_SMN_C2PMSG_50', 'regMP0_SMN_C2PMSG_50_BASE_IDX', + 'regMP0_SMN_C2PMSG_51', 'regMP0_SMN_C2PMSG_51_BASE_IDX', + 'regMP0_SMN_C2PMSG_52', 'regMP0_SMN_C2PMSG_52_BASE_IDX', + 'regMP0_SMN_C2PMSG_53', 'regMP0_SMN_C2PMSG_53_BASE_IDX', + 'regMP0_SMN_C2PMSG_54', 'regMP0_SMN_C2PMSG_54_BASE_IDX', + 'regMP0_SMN_C2PMSG_55', 'regMP0_SMN_C2PMSG_55_BASE_IDX', + 'regMP0_SMN_C2PMSG_56', 'regMP0_SMN_C2PMSG_56_BASE_IDX', + 'regMP0_SMN_C2PMSG_57', 'regMP0_SMN_C2PMSG_57_BASE_IDX', + 'regMP0_SMN_C2PMSG_58', 'regMP0_SMN_C2PMSG_58_BASE_IDX', + 'regMP0_SMN_C2PMSG_59', 'regMP0_SMN_C2PMSG_59_BASE_IDX', + 'regMP0_SMN_C2PMSG_60', 'regMP0_SMN_C2PMSG_60_BASE_IDX', + 'regMP0_SMN_C2PMSG_61', 'regMP0_SMN_C2PMSG_61_BASE_IDX', + 'regMP0_SMN_C2PMSG_62', 'regMP0_SMN_C2PMSG_62_BASE_IDX', + 'regMP0_SMN_C2PMSG_63', 'regMP0_SMN_C2PMSG_63_BASE_IDX', + 'regMP0_SMN_C2PMSG_64', 'regMP0_SMN_C2PMSG_64_BASE_IDX', + 'regMP0_SMN_C2PMSG_65', 'regMP0_SMN_C2PMSG_65_BASE_IDX', + 'regMP0_SMN_C2PMSG_66', 'regMP0_SMN_C2PMSG_66_BASE_IDX', + 'regMP0_SMN_C2PMSG_67', 'regMP0_SMN_C2PMSG_67_BASE_IDX', + 'regMP0_SMN_C2PMSG_68', 'regMP0_SMN_C2PMSG_68_BASE_IDX', + 'regMP0_SMN_C2PMSG_69', 'regMP0_SMN_C2PMSG_69_BASE_IDX', + 'regMP0_SMN_C2PMSG_70', 'regMP0_SMN_C2PMSG_70_BASE_IDX', + 'regMP0_SMN_C2PMSG_71', 'regMP0_SMN_C2PMSG_71_BASE_IDX', + 'regMP0_SMN_C2PMSG_72', 'regMP0_SMN_C2PMSG_72_BASE_IDX', + 'regMP0_SMN_C2PMSG_73', 'regMP0_SMN_C2PMSG_73_BASE_IDX', + 'regMP0_SMN_C2PMSG_74', 'regMP0_SMN_C2PMSG_74_BASE_IDX', + 'regMP0_SMN_C2PMSG_75', 'regMP0_SMN_C2PMSG_75_BASE_IDX', + 'regMP0_SMN_C2PMSG_76', 'regMP0_SMN_C2PMSG_76_BASE_IDX', + 'regMP0_SMN_C2PMSG_77', 'regMP0_SMN_C2PMSG_77_BASE_IDX', + 'regMP0_SMN_C2PMSG_78', 'regMP0_SMN_C2PMSG_78_BASE_IDX', + 'regMP0_SMN_C2PMSG_79', 'regMP0_SMN_C2PMSG_79_BASE_IDX', + 'regMP0_SMN_C2PMSG_80', 'regMP0_SMN_C2PMSG_80_BASE_IDX', + 'regMP0_SMN_C2PMSG_81', 'regMP0_SMN_C2PMSG_81_BASE_IDX', + 'regMP0_SMN_C2PMSG_82', 'regMP0_SMN_C2PMSG_82_BASE_IDX', + 'regMP0_SMN_C2PMSG_83', 'regMP0_SMN_C2PMSG_83_BASE_IDX', + 'regMP0_SMN_C2PMSG_84', 'regMP0_SMN_C2PMSG_84_BASE_IDX', + 'regMP0_SMN_C2PMSG_85', 'regMP0_SMN_C2PMSG_85_BASE_IDX', + 'regMP0_SMN_C2PMSG_86', 'regMP0_SMN_C2PMSG_86_BASE_IDX', + 'regMP0_SMN_C2PMSG_87', 'regMP0_SMN_C2PMSG_87_BASE_IDX', + 'regMP0_SMN_C2PMSG_88', 'regMP0_SMN_C2PMSG_88_BASE_IDX', + 'regMP0_SMN_C2PMSG_89', 'regMP0_SMN_C2PMSG_89_BASE_IDX', + 'regMP0_SMN_C2PMSG_90', 'regMP0_SMN_C2PMSG_90_BASE_IDX', + 'regMP0_SMN_C2PMSG_91', 'regMP0_SMN_C2PMSG_91_BASE_IDX', + 'regMP0_SMN_C2PMSG_92', 'regMP0_SMN_C2PMSG_92_BASE_IDX', + 'regMP0_SMN_C2PMSG_93', 'regMP0_SMN_C2PMSG_93_BASE_IDX', + 'regMP0_SMN_C2PMSG_94', 'regMP0_SMN_C2PMSG_94_BASE_IDX', + 'regMP0_SMN_C2PMSG_95', 'regMP0_SMN_C2PMSG_95_BASE_IDX', + 'regMP0_SMN_C2PMSG_96', 'regMP0_SMN_C2PMSG_96_BASE_IDX', + 'regMP0_SMN_C2PMSG_97', 'regMP0_SMN_C2PMSG_97_BASE_IDX', + 'regMP0_SMN_C2PMSG_98', 'regMP0_SMN_C2PMSG_98_BASE_IDX', + 'regMP0_SMN_C2PMSG_99', 'regMP0_SMN_C2PMSG_99_BASE_IDX', + 'regMP0_SMN_IH_CREDIT', 'regMP0_SMN_IH_CREDIT_BASE_IDX', + 'regMP0_SMN_IH_SW_INT', 'regMP0_SMN_IH_SW_INT_BASE_IDX', + 'regMP0_SMN_IH_SW_INT_CTRL', 'regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX', + 'regMP1_FIRMWARE_FLAGS', 'regMP1_FIRMWARE_FLAGS_BASE_IDX', + 'regMP1_SMN_C2PMSG_100', 'regMP1_SMN_C2PMSG_100_BASE_IDX', + 'regMP1_SMN_C2PMSG_101', 'regMP1_SMN_C2PMSG_101_BASE_IDX', + 'regMP1_SMN_C2PMSG_102', 'regMP1_SMN_C2PMSG_102_BASE_IDX', + 'regMP1_SMN_C2PMSG_103', 'regMP1_SMN_C2PMSG_103_BASE_IDX', + 'regMP1_SMN_C2PMSG_104', 'regMP1_SMN_C2PMSG_104_BASE_IDX', + 'regMP1_SMN_C2PMSG_105', 'regMP1_SMN_C2PMSG_105_BASE_IDX', + 'regMP1_SMN_C2PMSG_106', 'regMP1_SMN_C2PMSG_106_BASE_IDX', + 'regMP1_SMN_C2PMSG_107', 'regMP1_SMN_C2PMSG_107_BASE_IDX', + 'regMP1_SMN_C2PMSG_108', 'regMP1_SMN_C2PMSG_108_BASE_IDX', + 'regMP1_SMN_C2PMSG_109', 'regMP1_SMN_C2PMSG_109_BASE_IDX', + 'regMP1_SMN_C2PMSG_110', 'regMP1_SMN_C2PMSG_110_BASE_IDX', + 'regMP1_SMN_C2PMSG_111', 'regMP1_SMN_C2PMSG_111_BASE_IDX', + 'regMP1_SMN_C2PMSG_112', 'regMP1_SMN_C2PMSG_112_BASE_IDX', + 'regMP1_SMN_C2PMSG_113', 'regMP1_SMN_C2PMSG_113_BASE_IDX', + 'regMP1_SMN_C2PMSG_114', 'regMP1_SMN_C2PMSG_114_BASE_IDX', + 'regMP1_SMN_C2PMSG_115', 'regMP1_SMN_C2PMSG_115_BASE_IDX', + 'regMP1_SMN_C2PMSG_116', 'regMP1_SMN_C2PMSG_116_BASE_IDX', + 'regMP1_SMN_C2PMSG_117', 'regMP1_SMN_C2PMSG_117_BASE_IDX', + 'regMP1_SMN_C2PMSG_118', 'regMP1_SMN_C2PMSG_118_BASE_IDX', + 'regMP1_SMN_C2PMSG_119', 'regMP1_SMN_C2PMSG_119_BASE_IDX', + 'regMP1_SMN_C2PMSG_120', 'regMP1_SMN_C2PMSG_120_BASE_IDX', + 'regMP1_SMN_C2PMSG_121', 'regMP1_SMN_C2PMSG_121_BASE_IDX', + 'regMP1_SMN_C2PMSG_122', 'regMP1_SMN_C2PMSG_122_BASE_IDX', + 'regMP1_SMN_C2PMSG_123', 'regMP1_SMN_C2PMSG_123_BASE_IDX', + 'regMP1_SMN_C2PMSG_124', 'regMP1_SMN_C2PMSG_124_BASE_IDX', + 'regMP1_SMN_C2PMSG_125', 'regMP1_SMN_C2PMSG_125_BASE_IDX', + 'regMP1_SMN_C2PMSG_126', 'regMP1_SMN_C2PMSG_126_BASE_IDX', + 'regMP1_SMN_C2PMSG_127', 'regMP1_SMN_C2PMSG_127_BASE_IDX', + 'regMP1_SMN_C2PMSG_32', 'regMP1_SMN_C2PMSG_32_BASE_IDX', + 'regMP1_SMN_C2PMSG_33', 'regMP1_SMN_C2PMSG_33_BASE_IDX', + 'regMP1_SMN_C2PMSG_34', 'regMP1_SMN_C2PMSG_34_BASE_IDX', + 'regMP1_SMN_C2PMSG_35', 'regMP1_SMN_C2PMSG_35_BASE_IDX', + 'regMP1_SMN_C2PMSG_36', 'regMP1_SMN_C2PMSG_36_BASE_IDX', + 'regMP1_SMN_C2PMSG_37', 'regMP1_SMN_C2PMSG_37_BASE_IDX', + 'regMP1_SMN_C2PMSG_38', 'regMP1_SMN_C2PMSG_38_BASE_IDX', + 'regMP1_SMN_C2PMSG_39', 'regMP1_SMN_C2PMSG_39_BASE_IDX', + 'regMP1_SMN_C2PMSG_40', 'regMP1_SMN_C2PMSG_40_BASE_IDX', + 'regMP1_SMN_C2PMSG_41', 'regMP1_SMN_C2PMSG_41_BASE_IDX', + 'regMP1_SMN_C2PMSG_42', 'regMP1_SMN_C2PMSG_42_BASE_IDX', + 'regMP1_SMN_C2PMSG_43', 'regMP1_SMN_C2PMSG_43_BASE_IDX', + 'regMP1_SMN_C2PMSG_44', 'regMP1_SMN_C2PMSG_44_BASE_IDX', + 'regMP1_SMN_C2PMSG_45', 'regMP1_SMN_C2PMSG_45_BASE_IDX', + 'regMP1_SMN_C2PMSG_46', 'regMP1_SMN_C2PMSG_46_BASE_IDX', + 'regMP1_SMN_C2PMSG_47', 'regMP1_SMN_C2PMSG_47_BASE_IDX', + 'regMP1_SMN_C2PMSG_48', 'regMP1_SMN_C2PMSG_48_BASE_IDX', + 'regMP1_SMN_C2PMSG_49', 'regMP1_SMN_C2PMSG_49_BASE_IDX', + 'regMP1_SMN_C2PMSG_50', 'regMP1_SMN_C2PMSG_50_BASE_IDX', + 'regMP1_SMN_C2PMSG_51', 'regMP1_SMN_C2PMSG_51_BASE_IDX', + 'regMP1_SMN_C2PMSG_52', 'regMP1_SMN_C2PMSG_52_BASE_IDX', + 'regMP1_SMN_C2PMSG_53', 'regMP1_SMN_C2PMSG_53_BASE_IDX', + 'regMP1_SMN_C2PMSG_54', 'regMP1_SMN_C2PMSG_54_BASE_IDX', + 'regMP1_SMN_C2PMSG_55', 'regMP1_SMN_C2PMSG_55_BASE_IDX', + 'regMP1_SMN_C2PMSG_56', 'regMP1_SMN_C2PMSG_56_BASE_IDX', + 'regMP1_SMN_C2PMSG_57', 'regMP1_SMN_C2PMSG_57_BASE_IDX', + 'regMP1_SMN_C2PMSG_58', 'regMP1_SMN_C2PMSG_58_BASE_IDX', + 'regMP1_SMN_C2PMSG_59', 'regMP1_SMN_C2PMSG_59_BASE_IDX', + 'regMP1_SMN_C2PMSG_60', 'regMP1_SMN_C2PMSG_60_BASE_IDX', + 'regMP1_SMN_C2PMSG_61', 'regMP1_SMN_C2PMSG_61_BASE_IDX', + 'regMP1_SMN_C2PMSG_62', 'regMP1_SMN_C2PMSG_62_BASE_IDX', + 'regMP1_SMN_C2PMSG_63', 'regMP1_SMN_C2PMSG_63_BASE_IDX', + 'regMP1_SMN_C2PMSG_64', 'regMP1_SMN_C2PMSG_64_BASE_IDX', + 'regMP1_SMN_C2PMSG_65', 'regMP1_SMN_C2PMSG_65_BASE_IDX', + 'regMP1_SMN_C2PMSG_66', 'regMP1_SMN_C2PMSG_66_BASE_IDX', + 'regMP1_SMN_C2PMSG_67', 'regMP1_SMN_C2PMSG_67_BASE_IDX', + 'regMP1_SMN_C2PMSG_68', 'regMP1_SMN_C2PMSG_68_BASE_IDX', + 'regMP1_SMN_C2PMSG_69', 'regMP1_SMN_C2PMSG_69_BASE_IDX', + 'regMP1_SMN_C2PMSG_70', 'regMP1_SMN_C2PMSG_70_BASE_IDX', + 'regMP1_SMN_C2PMSG_71', 'regMP1_SMN_C2PMSG_71_BASE_IDX', + 'regMP1_SMN_C2PMSG_72', 'regMP1_SMN_C2PMSG_72_BASE_IDX', + 'regMP1_SMN_C2PMSG_73', 'regMP1_SMN_C2PMSG_73_BASE_IDX', + 'regMP1_SMN_C2PMSG_74', 'regMP1_SMN_C2PMSG_74_BASE_IDX', + 'regMP1_SMN_C2PMSG_75', 'regMP1_SMN_C2PMSG_75_BASE_IDX', + 'regMP1_SMN_C2PMSG_76', 'regMP1_SMN_C2PMSG_76_BASE_IDX', + 'regMP1_SMN_C2PMSG_77', 'regMP1_SMN_C2PMSG_77_BASE_IDX', + 'regMP1_SMN_C2PMSG_78', 'regMP1_SMN_C2PMSG_78_BASE_IDX', + 'regMP1_SMN_C2PMSG_79', 'regMP1_SMN_C2PMSG_79_BASE_IDX', + 'regMP1_SMN_C2PMSG_80', 'regMP1_SMN_C2PMSG_80_BASE_IDX', + 'regMP1_SMN_C2PMSG_81', 'regMP1_SMN_C2PMSG_81_BASE_IDX', + 'regMP1_SMN_C2PMSG_82', 'regMP1_SMN_C2PMSG_82_BASE_IDX', + 'regMP1_SMN_C2PMSG_83', 'regMP1_SMN_C2PMSG_83_BASE_IDX', + 'regMP1_SMN_C2PMSG_84', 'regMP1_SMN_C2PMSG_84_BASE_IDX', + 'regMP1_SMN_C2PMSG_85', 'regMP1_SMN_C2PMSG_85_BASE_IDX', + 'regMP1_SMN_C2PMSG_86', 'regMP1_SMN_C2PMSG_86_BASE_IDX', + 'regMP1_SMN_C2PMSG_87', 'regMP1_SMN_C2PMSG_87_BASE_IDX', + 'regMP1_SMN_C2PMSG_88', 'regMP1_SMN_C2PMSG_88_BASE_IDX', + 'regMP1_SMN_C2PMSG_89', 'regMP1_SMN_C2PMSG_89_BASE_IDX', + 'regMP1_SMN_C2PMSG_90', 'regMP1_SMN_C2PMSG_90_BASE_IDX', + 'regMP1_SMN_C2PMSG_91', 'regMP1_SMN_C2PMSG_91_BASE_IDX', + 'regMP1_SMN_C2PMSG_92', 'regMP1_SMN_C2PMSG_92_BASE_IDX', + 'regMP1_SMN_C2PMSG_93', 'regMP1_SMN_C2PMSG_93_BASE_IDX', + 'regMP1_SMN_C2PMSG_94', 'regMP1_SMN_C2PMSG_94_BASE_IDX', + 'regMP1_SMN_C2PMSG_95', 'regMP1_SMN_C2PMSG_95_BASE_IDX', + 'regMP1_SMN_C2PMSG_96', 'regMP1_SMN_C2PMSG_96_BASE_IDX', + 'regMP1_SMN_C2PMSG_97', 'regMP1_SMN_C2PMSG_97_BASE_IDX', + 'regMP1_SMN_C2PMSG_98', 'regMP1_SMN_C2PMSG_98_BASE_IDX', + 'regMP1_SMN_C2PMSG_99', 'regMP1_SMN_C2PMSG_99_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH0', 'regMP1_SMN_EXT_SCRATCH0_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH1', 'regMP1_SMN_EXT_SCRATCH10', + 'regMP1_SMN_EXT_SCRATCH10_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH11', + 'regMP1_SMN_EXT_SCRATCH11_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH12', + 'regMP1_SMN_EXT_SCRATCH12_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH13', + 'regMP1_SMN_EXT_SCRATCH13_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH14', + 'regMP1_SMN_EXT_SCRATCH14_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH15', + 'regMP1_SMN_EXT_SCRATCH15_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH16', + 'regMP1_SMN_EXT_SCRATCH16_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH17', + 'regMP1_SMN_EXT_SCRATCH17_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH18', + 'regMP1_SMN_EXT_SCRATCH18_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH19', + 'regMP1_SMN_EXT_SCRATCH19_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH1_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH2', + 'regMP1_SMN_EXT_SCRATCH20', 'regMP1_SMN_EXT_SCRATCH20_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH21', 'regMP1_SMN_EXT_SCRATCH21_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH22', 'regMP1_SMN_EXT_SCRATCH22_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH23', 'regMP1_SMN_EXT_SCRATCH23_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH24', 'regMP1_SMN_EXT_SCRATCH24_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH25', 'regMP1_SMN_EXT_SCRATCH25_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH26', 'regMP1_SMN_EXT_SCRATCH26_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH27', 'regMP1_SMN_EXT_SCRATCH27_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH28', 'regMP1_SMN_EXT_SCRATCH28_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH29', 'regMP1_SMN_EXT_SCRATCH29_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH2_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH3', + 'regMP1_SMN_EXT_SCRATCH30', 'regMP1_SMN_EXT_SCRATCH30_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH31', 'regMP1_SMN_EXT_SCRATCH31_BASE_IDX', + 'regMP1_SMN_EXT_SCRATCH3_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH4', + 'regMP1_SMN_EXT_SCRATCH4_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH5', + 'regMP1_SMN_EXT_SCRATCH5_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH6', + 'regMP1_SMN_EXT_SCRATCH6_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH7', + 'regMP1_SMN_EXT_SCRATCH7_BASE_IDX', 'regMP1_SMN_EXT_SCRATCH8', + 'regMP1_SMN_EXT_SCRATCH8_BASE_IDX', 'regMP1_SMN_FPS_CNT', + 'regMP1_SMN_FPS_CNT_BASE_IDX', 'regMP1_SMN_IH_CREDIT', + 'regMP1_SMN_IH_CREDIT_BASE_IDX', 'regMP1_SMN_IH_SW_INT', + 'regMP1_SMN_IH_SW_INT_BASE_IDX', 'regMP1_SMN_IH_SW_INT_CTRL', + 'regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX', 'regMP1_SMN_PUB_CTRL', + 'regMP1_SMN_PUB_CTRL_BASE_IDX', 'regMPIO_FIRMWARE_FLAGS', + 'regMPIO_FIRMWARE_FLAGS_BASE_IDX'] diff --git a/tinygrad/runtime/autogen/am/nbio_4_3_0.py b/tinygrad/runtime/autogen/am/nbio_4_3_0.py new file mode 100644 index 0000000000..003e7ae60c --- /dev/null +++ b/tinygrad/runtime/autogen/am/nbio_4_3_0.py @@ -0,0 +1,173551 @@ +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_nbio_4_3_0_OFFSET_HEADER = True # macro +regBIF_BX0_PCIE_INDEX = 0x000c # macro +regBIF_BX0_PCIE_INDEX_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_DATA = 0x000d # macro +regBIF_BX0_PCIE_DATA_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_INDEX2 = 0x000e # macro +regBIF_BX0_PCIE_INDEX2_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_DATA2 = 0x000f # macro +regBIF_BX0_PCIE_DATA2_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_INDEX_HI = 0x0010 # macro +regBIF_BX0_PCIE_INDEX_HI_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_INDEX2_HI = 0x0011 # macro +regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX = 0 # macro +regBIF_BX0_SBIOS_SCRATCH_0 = 0x0034 # macro +regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_1 = 0x0035 # macro +regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_2 = 0x0036 # macro +regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_3 = 0x0037 # macro +regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_0 = 0x0038 # macro +regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_1 = 0x0039 # macro +regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_2 = 0x003a # macro +regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_3 = 0x003b # macro +regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_4 = 0x003c # macro +regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_5 = 0x003d # macro +regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_6 = 0x003e # macro +regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_7 = 0x003f # macro +regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_8 = 0x0040 # macro +regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_9 = 0x0041 # macro +regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_10 = 0x0042 # macro +regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_11 = 0x0043 # macro +regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_12 = 0x0044 # macro +regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_13 = 0x0045 # macro +regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_14 = 0x0046 # macro +regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_15 = 0x0047 # macro +regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX = 1 # macro +regBIF_BX0_BIF_RLC_INTR_CNTL = 0x004c # macro +regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_BIF_VCE_INTR_CNTL = 0x004d # macro +regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_BIF_UVD_INTR_CNTL = 0x004e # macro +regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 = 0x006c # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 = 0x006d # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 = 0x006e # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 = 0x006f # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 = 0x0070 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 = 0x0071 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 = 0x0072 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 = 0x0073 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 = 0x0074 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 = 0x0075 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 = 0x0076 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 = 0x0077 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 = 0x0078 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 = 0x0079 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 = 0x007a # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 = 0x007b # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_CNTL = 0x007c # macro +regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL = 0x007d # macro +regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL = 0x007e # macro +regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL = 0x007f # macro +regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_0 = 0x0080 # macro +regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_1 = 0x0081 # macro +regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_2 = 0x0082 # macro +regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_3 = 0x0083 # macro +regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_4 = 0x0084 # macro +regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_5 = 0x0085 # macro +regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_6 = 0x0086 # macro +regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_7 = 0x0087 # macro +regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_8 = 0x0088 # macro +regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_9 = 0x0089 # macro +regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_10 = 0x008a # macro +regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_11 = 0x008b # macro +regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_12 = 0x008c # macro +regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_13 = 0x008d # macro +regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_14 = 0x008e # macro +regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_15 = 0x008f # macro +regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_0 = 0x0090 # macro +regBIF_BX0_FW_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_1 = 0x0091 # macro +regBIF_BX0_FW_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_2 = 0x0092 # macro +regBIF_BX0_FW_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_3 = 0x0093 # macro +regBIF_BX0_FW_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_4 = 0x0094 # macro +regBIF_BX0_FW_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_5 = 0x0095 # macro +regBIF_BX0_FW_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_6 = 0x0096 # macro +regBIF_BX0_FW_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_7 = 0x0097 # macro +regBIF_BX0_FW_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_8 = 0x0098 # macro +regBIF_BX0_FW_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_9 = 0x0099 # macro +regBIF_BX0_FW_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_10 = 0x009a # macro +regBIF_BX0_FW_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_11 = 0x009b # macro +regBIF_BX0_FW_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_12 = 0x009c # macro +regBIF_BX0_FW_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_13 = 0x009d # macro +regBIF_BX0_FW_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_14 = 0x009e # macro +regBIF_BX0_FW_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_15 = 0x009f # macro +regBIF_BX0_FW_SCRATCH_15_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_4 = 0x00a0 # macro +regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_5 = 0x00a1 # macro +regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_6 = 0x00a2 # macro +regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_7 = 0x00a3 # macro +regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_8 = 0x00a4 # macro +regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_9 = 0x00a5 # macro +regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_10 = 0x00a6 # macro +regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_11 = 0x00a7 # macro +regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_12 = 0x00a8 # macro +regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_13 = 0x00a9 # macro +regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_14 = 0x00aa # macro +regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_15 = 0x00ab # macro +regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX = 1 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RESERVED = 0x0060 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH = 0x0061 # macro +regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CNTL = 0x0063 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL = 0x0064 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 = 0x0065 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL = 0x0066 # macro +regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL = 0x0067 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 = 0x0068 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC = 0x0069 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 = 0x006a # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL = 0x006c # macro +regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_RX_CNTL = 0x006d # macro +regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL = 0x006e # macro +regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 = 0x006f # macro +regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC = 0x0070 # macro +regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP = 0x0071 # macro +regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_SCRATCH = 0x0040 # macro +regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_CNTL = 0x0042 # macro +regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL = 0x0043 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS = 0x0044 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 = 0x0045 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL = 0x0046 # macro +regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL = 0x0047 # macro +regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL = 0x0049 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC = 0x004c # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 = 0x004d # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP = 0x004f # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR = 0x0050 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL = 0x0050 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0050 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0052 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0052 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0052 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL = 0x0052 # macro +regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIEP_RESERVED = 0x0053 # macro +regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL = 0x0055 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID = 0x0056 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL = 0x0057 # macro +regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL = 0x0058 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL = 0x0059 # macro +regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_MM_INDEX = 0x0000 # macro +regBIF_BX_PF0_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_PF0_MM_DATA = 0x0001 # macro +regBIF_BX_PF0_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_PF0_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX = 0 # macro +regBIF_BX_PF0_RSMU_INDEX = 0x0000 # macro +regBIF_BX_PF0_RSMU_INDEX_BASE_IDX = 1 # macro +regBIF_BX_PF0_RSMU_DATA = 0x0001 # macro +regBIF_BX_PF0_RSMU_DATA_BASE_IDX = 1 # macro +regBIF_BX_PF0_RSMU_INDEX_HI = 0x0002 # macro +regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX = 1 # macro +regBIF_BX0_CC_BIF_BX_STRAP0 = 0x00e2 # macro +regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX = 2 # macro +regBIF_BX0_CC_BIF_BX_PINSTRAP0 = 0x00e4 # macro +regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX = 2 # macro +regBIF_BX0_BIF_MM_INDACCESS_CNTL = 0x00e6 # macro +regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BUS_CNTL = 0x00e7 # macro +regBIF_BX0_BUS_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_SCRATCH0 = 0x00e8 # macro +regBIF_BX0_BIF_SCRATCH0_BASE_IDX = 2 # macro +regBIF_BX0_BIF_SCRATCH1 = 0x00e9 # macro +regBIF_BX0_BIF_SCRATCH1_BASE_IDX = 2 # macro +regBIF_BX0_BX_RESET_EN = 0x00ed # macro +regBIF_BX0_BX_RESET_EN_BASE_IDX = 2 # macro +regBIF_BX0_MM_CFGREGS_CNTL = 0x00ee # macro +regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BX_RESET_CNTL = 0x00f0 # macro +regBIF_BX0_BX_RESET_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_INTERRUPT_CNTL = 0x00f1 # macro +regBIF_BX0_INTERRUPT_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_INTERRUPT_CNTL2 = 0x00f2 # macro +regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX = 2 # macro +regBIF_BX0_CLKREQB_PAD_CNTL = 0x00f8 # macro +regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_FEATURES_CONTROL_MISC = 0x00fb # macro +regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX = 2 # macro +regBIF_BX0_HDP_ATOMIC_CONTROL_MISC = 0x00fc # macro +regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX = 2 # macro +regBIF_BX0_BIF_DOORBELL_CNTL = 0x00fd # macro +regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_DOORBELL_INT_CNTL = 0x00fe # macro +regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_FB_EN = 0x0100 # macro +regBIF_BX0_BIF_FB_EN_BASE_IDX = 2 # macro +regBIF_BX0_BIF_INTR_CNTL = 0x0101 # macro +regBIF_BX0_BIF_INTR_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_MST_TRANS_PENDING_VF = 0x0109 # macro +regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX = 2 # macro +regBIF_BX0_BIF_SLV_TRANS_PENDING_VF = 0x010a # macro +regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX = 2 # macro +regBIF_BX0_MEM_TYPE_CNTL = 0x0111 # macro +regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL = 0x0113 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_0 = 0x0114 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_1 = 0x0115 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_2 = 0x0116 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_3 = 0x0117 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_4 = 0x0118 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_5 = 0x0119 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_6 = 0x011a # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_7 = 0x011b # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_8 = 0x011c # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_9 = 0x011d # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_10 = 0x011e # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_11 = 0x011f # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_12 = 0x0120 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_13 = 0x0121 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_14 = 0x0122 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_15 = 0x0123 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX = 2 # macro +regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL = 0x012d # macro +regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL = 0x012e # macro +regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_CNTL = 0x012f # macro +regBIF_BX0_BIF_RB_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_BASE = 0x0130 # macro +regBIF_BX0_BIF_RB_BASE_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_RPTR = 0x0131 # macro +regBIF_BX0_BIF_RB_RPTR_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_WPTR = 0x0132 # macro +regBIF_BX0_BIF_RB_WPTR_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_HI = 0x0133 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_LO = 0x0134 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX = 2 # macro +regBIF_BX0_BIF_MP1_INTR_CTRL = 0x0142 # macro +regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_ERR_INT_CNTL = 0x0086 # macro +regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BACO_CNTL_MISC = 0x0087 # macro +regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_RESET_EN = 0x0088 # macro +regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_VDM_SUPPORT = 0x0089 # macro +regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 = 0x008a # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 = 0x008b # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_GPUIOV_REGION = 0x008c # macro +regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_GPU_HOSTVM_EN = 0x008d # macro +regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL = 0x008e # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET = 0x008f # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE = 0x008f # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE0 = 0x00be # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE1 = 0x00bf # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUS_CNTL = 0x00c1 # macro +regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_CNTL = 0x00c2 # macro +regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_F0_BASE = 0x00c6 # macro +regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_APER_SIZE = 0x00c7 # macro +regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE = 0x00c8 # macro +regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_XDMA_LO = 0x00c9 # macro +regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_XDMA_HI = 0x00ca # macro +regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC = 0x00cb # macro +regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL1 = 0x00cc # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST0 = 0x00cd # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST1 = 0x00ce # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL2 = 0x00cf # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM = 0x00d0 # macro +regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_HOST_BUSNUM = 0x00d1 # macro +regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI = 0x00d2 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO = 0x00d3 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI = 0x00d4 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO = 0x00d5 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI = 0x00d6 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO = 0x00d7 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI = 0x00d8 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO = 0x00d9 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 = 0x00da # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 = 0x00db # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_DEV0_LINK_CNTL = 0x00dd # macro +regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CMN_LINK_CNTL = 0x00de # macro +regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE = 0x00df # macro +regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL = 0x00e0 # macro +regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_MH_ARB_CNTL = 0x00e1 # macro +regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX = 3 # macro +regRCC_STRAP0_RCC_BIF_STRAP0 = 0x0000 # macro +regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP1 = 0x0001 # macro +regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP2 = 0x0002 # macro +regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP3 = 0x0003 # macro +regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP4 = 0x0004 # macro +regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP5 = 0x0005 # macro +regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP6 = 0x0006 # macro +regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 = 0x0007 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 = 0x0008 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 = 0x0009 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 = 0x000a # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 = 0x000b # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 = 0x000c # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 = 0x000d # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 = 0x000e # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 = 0x000f # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 = 0x0010 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 = 0x0011 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 = 0x0012 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 = 0x0013 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 = 0x0014 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 = 0x0015 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 = 0x0016 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 = 0x0017 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 = 0x0018 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 = 0x0019 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 = 0x001a # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 = 0x001b # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 = 0x001c # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 = 0x001d # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 = 0x001e # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 = 0x001f # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 = 0x0020 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 = 0x0021 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 = 0x0022 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 = 0x0023 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 = 0x0024 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 = 0x0025 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 = 0x0031 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 = 0x0032 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 = 0x0033 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 = 0x0034 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 = 0x0035 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 = 0x0036 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 = 0x0037 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 = 0x0038 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 = 0x0039 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 = 0x003a # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 = 0x003b # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 = 0x003c # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX = 2 # macro +regBIF_BX_PF0_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_PF0_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regGDC0_SHUB_REGS_IF_CTL = 0x01c3 # macro +regGDC0_SHUB_REGS_IF_CTL_BASE_IDX = 2 # macro +regGDC0_NBIF_GFX_DOORBELL_STATUS = 0x01cf # macro +regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX = 2 # macro +regGDC0_ATDMA_MISC_CNTL = 0x01dd # macro +regGDC0_ATDMA_MISC_CNTL_BASE_IDX = 2 # macro +regGDC0_S2A_MISC_CNTL = 0x01df # macro +regGDC0_S2A_MISC_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF8_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF8_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF9_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF9_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF10_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF10_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF11_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF11_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF12_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF12_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF13_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF13_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF14_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF14_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX = 3 # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF15_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF15_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX = 3 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX = 3 # macro +cfgPSWUSCFG0_0_VENDOR_ID = 0xfffe00000000 # macro +cfgPSWUSCFG0_0_DEVICE_ID = 0xfffe00000002 # macro +cfgPSWUSCFG0_0_COMMAND = 0xfffe00000004 # macro +cfgPSWUSCFG0_0_STATUS = 0xfffe00000006 # macro +cfgPSWUSCFG0_0_REVISION_ID = 0xfffe00000008 # macro +cfgPSWUSCFG0_0_PROG_INTERFACE = 0xfffe00000009 # macro +cfgPSWUSCFG0_0_SUB_CLASS = 0xfffe0000000a # macro +cfgPSWUSCFG0_0_BASE_CLASS = 0xfffe0000000b # macro +cfgPSWUSCFG0_0_CACHE_LINE = 0xfffe0000000c # macro +cfgPSWUSCFG0_0_LATENCY = 0xfffe0000000d # macro +cfgPSWUSCFG0_0_HEADER = 0xfffe0000000e # macro +cfgPSWUSCFG0_0_BIST = 0xfffe0000000f # macro +cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY = 0xfffe00000018 # macro +cfgPSWUSCFG0_0_IO_BASE_LIMIT = 0xfffe0000001c # macro +cfgPSWUSCFG0_0_SECONDARY_STATUS = 0xfffe0000001e # macro +cfgPSWUSCFG0_0_MEM_BASE_LIMIT = 0xfffe00000020 # macro +cfgPSWUSCFG0_0_PREF_BASE_LIMIT = 0xfffe00000024 # macro +cfgPSWUSCFG0_0_PREF_BASE_UPPER = 0xfffe00000028 # macro +cfgPSWUSCFG0_0_PREF_LIMIT_UPPER = 0xfffe0000002c # macro +cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI = 0xfffe00000030 # macro +cfgPSWUSCFG0_0_CAP_PTR = 0xfffe00000034 # macro +cfgPSWUSCFG0_0_ROM_BASE_ADDR = 0xfffe00000038 # macro +cfgPSWUSCFG0_0_INTERRUPT_LINE = 0xfffe0000003c # macro +cfgPSWUSCFG0_0_INTERRUPT_PIN = 0xfffe0000003d # macro +cfgPSWUSCFG0_0_VENDOR_CAP_LIST = 0xfffe00000048 # macro +cfgPSWUSCFG0_0_ADAPTER_ID_W = 0xfffe0000004c # macro +cfgPSWUSCFG0_0_PMI_CAP_LIST = 0xfffe00000050 # macro +cfgPSWUSCFG0_0_PMI_CAP = 0xfffe00000052 # macro +cfgPSWUSCFG0_0_PMI_STATUS_CNTL = 0xfffe00000054 # macro +cfgPSWUSCFG0_0_PCIE_CAP_LIST = 0xfffe00000058 # macro +cfgPSWUSCFG0_0_PCIE_CAP = 0xfffe0000005a # macro +cfgPSWUSCFG0_0_DEVICE_CAP = 0xfffe0000005c # macro +cfgPSWUSCFG0_0_DEVICE_CNTL = 0xfffe00000060 # macro +cfgPSWUSCFG0_0_DEVICE_STATUS = 0xfffe00000062 # macro +cfgPSWUSCFG0_0_LINK_CAP = 0xfffe00000064 # macro +cfgPSWUSCFG0_0_LINK_CNTL = 0xfffe00000068 # macro +cfgPSWUSCFG0_0_LINK_STATUS = 0xfffe0000006a # macro +cfgPSWUSCFG0_0_DEVICE_CAP2 = 0xfffe0000007c # macro +cfgPSWUSCFG0_0_DEVICE_CNTL2 = 0xfffe00000080 # macro +cfgPSWUSCFG0_0_DEVICE_STATUS2 = 0xfffe00000082 # macro +cfgPSWUSCFG0_0_LINK_CAP2 = 0xfffe00000084 # macro +cfgPSWUSCFG0_0_LINK_CNTL2 = 0xfffe00000088 # macro +cfgPSWUSCFG0_0_LINK_STATUS2 = 0xfffe0000008a # macro +cfgPSWUSCFG0_0_MSI_CAP_LIST = 0xfffe000000a0 # macro +cfgPSWUSCFG0_0_MSI_MSG_CNTL = 0xfffe000000a2 # macro +cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO = 0xfffe000000a4 # macro +cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI = 0xfffe000000a8 # macro +cfgPSWUSCFG0_0_MSI_MSG_DATA = 0xfffe000000a8 # macro +cfgPSWUSCFG0_0_MSI_MSG_DATA_64 = 0xfffe000000ac # macro +cfgPSWUSCFG0_0_SSID_CAP_LIST = 0xfffe000000c0 # macro +cfgPSWUSCFG0_0_SSID_CAP = 0xfffe000000c4 # macro +cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe00000100 # macro +cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe00000104 # macro +cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe00000108 # macro +cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe0000010c # macro +cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST = 0xfffe00000110 # macro +cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 = 0xfffe00000114 # macro +cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 = 0xfffe00000118 # macro +cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL = 0xfffe0000011c # macro +cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS = 0xfffe0000011e # macro +cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP = 0xfffe00000120 # macro +cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL = 0xfffe00000124 # macro +cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS = 0xfffe0000012a # macro +cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP = 0xfffe0000012c # macro +cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL = 0xfffe00000130 # macro +cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS = 0xfffe00000136 # macro +cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0xfffe00000140 # macro +cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 = 0xfffe00000144 # macro +cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 = 0xfffe00000148 # macro +cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe00000150 # macro +cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS = 0xfffe00000154 # macro +cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK = 0xfffe00000158 # macro +cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe0000015c # macro +cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS = 0xfffe00000160 # macro +cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK = 0xfffe00000164 # macro +cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe00000168 # macro +cfgPSWUSCFG0_0_PCIE_HDR_LOG0 = 0xfffe0000016c # macro +cfgPSWUSCFG0_0_PCIE_HDR_LOG1 = 0xfffe00000170 # macro +cfgPSWUSCFG0_0_PCIE_HDR_LOG2 = 0xfffe00000174 # macro +cfgPSWUSCFG0_0_PCIE_HDR_LOG3 = 0xfffe00000178 # macro +cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe00000188 # macro +cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe0000018c # macro +cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe00000190 # macro +cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe00000194 # macro +cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST = 0xfffe00000270 # macro +cfgPSWUSCFG0_0_PCIE_LINK_CNTL3 = 0xfffe00000274 # macro +cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS = 0xfffe00000278 # macro +cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL = 0xfffe0000027c # macro +cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL = 0xfffe0000027e # macro +cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL = 0xfffe00000280 # macro +cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL = 0xfffe00000282 # macro +cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL = 0xfffe00000284 # macro +cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL = 0xfffe00000286 # macro +cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL = 0xfffe00000288 # macro +cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL = 0xfffe0000028a # macro +cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL = 0xfffe0000028c # macro +cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL = 0xfffe0000028e # macro +cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL = 0xfffe00000290 # macro +cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL = 0xfffe00000292 # macro +cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL = 0xfffe00000294 # macro +cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL = 0xfffe00000296 # macro +cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL = 0xfffe00000298 # macro +cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL = 0xfffe0000029a # macro +cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST = 0xfffe000002a0 # macro +cfgPSWUSCFG0_0_PCIE_ACS_CAP = 0xfffe000002a4 # macro +cfgPSWUSCFG0_0_PCIE_ACS_CNTL = 0xfffe000002a6 # macro +cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST = 0xfffe000002f0 # macro +cfgPSWUSCFG0_0_PCIE_MC_CAP = 0xfffe000002f4 # macro +cfgPSWUSCFG0_0_PCIE_MC_CNTL = 0xfffe000002f6 # macro +cfgPSWUSCFG0_0_PCIE_MC_ADDR0 = 0xfffe000002f8 # macro +cfgPSWUSCFG0_0_PCIE_MC_ADDR1 = 0xfffe000002fc # macro +cfgPSWUSCFG0_0_PCIE_MC_RCV0 = 0xfffe00000300 # macro +cfgPSWUSCFG0_0_PCIE_MC_RCV1 = 0xfffe00000304 # macro +cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 = 0xfffe00000308 # macro +cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 = 0xfffe0000030c # macro +cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0xfffe00000310 # macro +cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0xfffe00000314 # macro +cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST = 0xfffe00000320 # macro +cfgPSWUSCFG0_0_PCIE_LTR_CAP = 0xfffe00000324 # macro +cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe00000328 # macro +cfgPSWUSCFG0_0_PCIE_ARI_CAP = 0xfffe0000032c # macro +cfgPSWUSCFG0_0_PCIE_ARI_CNTL = 0xfffe0000032e # macro +cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST = 0xfffe00000400 # macro +cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP = 0xfffe00000404 # macro +cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS = 0xfffe00000408 # macro +cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST = 0xfffe00000410 # macro +cfgPSWUSCFG0_0_LINK_CAP_16GT = 0xfffe00000414 # macro +cfgPSWUSCFG0_0_LINK_CNTL_16GT = 0xfffe00000418 # macro +cfgPSWUSCFG0_0_LINK_STATUS_16GT = 0xfffe0000041c # macro +cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0xfffe00000420 # macro +cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT = 0xfffe00000424 # macro +cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT = 0xfffe00000428 # macro +cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT = 0xfffe00000430 # macro +cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT = 0xfffe00000431 # macro +cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT = 0xfffe00000432 # macro +cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT = 0xfffe00000433 # macro +cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT = 0xfffe00000434 # macro +cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT = 0xfffe00000435 # macro +cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT = 0xfffe00000436 # macro +cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT = 0xfffe00000437 # macro +cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT = 0xfffe00000438 # macro +cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT = 0xfffe00000439 # macro +cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT = 0xfffe0000043a # macro +cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT = 0xfffe0000043b # macro +cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT = 0xfffe0000043c # macro +cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT = 0xfffe0000043d # macro +cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT = 0xfffe0000043e # macro +cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT = 0xfffe0000043f # macro +cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST = 0xfffe00000440 # macro +cfgPSWUSCFG0_0_MARGINING_PORT_CAP = 0xfffe00000444 # macro +cfgPSWUSCFG0_0_MARGINING_PORT_STATUS = 0xfffe00000446 # macro +cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL = 0xfffe00000448 # macro +cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS = 0xfffe0000044a # macro +cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL = 0xfffe0000044c # macro +cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS = 0xfffe0000044e # macro +cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL = 0xfffe00000450 # macro +cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS = 0xfffe00000452 # macro +cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL = 0xfffe00000454 # macro +cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS = 0xfffe00000456 # macro +cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL = 0xfffe00000458 # macro +cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS = 0xfffe0000045a # macro +cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL = 0xfffe0000045c # macro +cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS = 0xfffe0000045e # macro +cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL = 0xfffe00000460 # macro +cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS = 0xfffe00000462 # macro +cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL = 0xfffe00000464 # macro +cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS = 0xfffe00000466 # macro +cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL = 0xfffe00000468 # macro +cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS = 0xfffe0000046a # macro +cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL = 0xfffe0000046c # macro +cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS = 0xfffe0000046e # macro +cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL = 0xfffe00000470 # macro +cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS = 0xfffe00000472 # macro +cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL = 0xfffe00000474 # macro +cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS = 0xfffe00000476 # macro +cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL = 0xfffe00000478 # macro +cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS = 0xfffe0000047a # macro +cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL = 0xfffe0000047c # macro +cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS = 0xfffe0000047e # macro +cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL = 0xfffe00000480 # macro +cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS = 0xfffe00000482 # macro +cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL = 0xfffe00000484 # macro +cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS = 0xfffe00000486 # macro +cfgPSWUSCFG0_0_LINK_CAP_32GT = 0xfffe00000504 # macro +cfgPSWUSCFG0_0_LINK_CNTL_32GT = 0xfffe00000508 # macro +cfgPSWUSCFG0_0_LINK_STATUS_32GT = 0xfffe0000050c # macro +cfgBIF_CFG_DEV0_RC0_VENDOR_ID = 0xfffe10100000 # macro +cfgBIF_CFG_DEV0_RC0_DEVICE_ID = 0xfffe10100002 # macro +cfgBIF_CFG_DEV0_RC0_COMMAND = 0xfffe10100004 # macro +cfgBIF_CFG_DEV0_RC0_STATUS = 0xfffe10100006 # macro +cfgBIF_CFG_DEV0_RC0_REVISION_ID = 0xfffe10100008 # macro +cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE = 0xfffe10100009 # macro +cfgBIF_CFG_DEV0_RC0_SUB_CLASS = 0xfffe1010000a # macro +cfgBIF_CFG_DEV0_RC0_BASE_CLASS = 0xfffe1010000b # macro +cfgBIF_CFG_DEV0_RC0_CACHE_LINE = 0xfffe1010000c # macro +cfgBIF_CFG_DEV0_RC0_LATENCY = 0xfffe1010000d # macro +cfgBIF_CFG_DEV0_RC0_HEADER = 0xfffe1010000e # macro +cfgBIF_CFG_DEV0_RC0_BIST = 0xfffe1010000f # macro +cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1 = 0xfffe10100010 # macro +cfgBIF_CFG_DEV0_RC0_BASE_ADDR_2 = 0xfffe10100014 # macro +cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY = 0xfffe10100018 # macro +cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT = 0xfffe1010001c # macro +cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS = 0xfffe1010001e # macro +cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT = 0xfffe10100020 # macro +cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT = 0xfffe10100024 # macro +cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER = 0xfffe10100028 # macro +cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER = 0xfffe1010002c # macro +cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI = 0xfffe10100030 # macro +cfgBIF_CFG_DEV0_RC0_CAP_PTR = 0xfffe10100034 # macro +cfgBIF_CFG_DEV0_RC0_ROM_BASE_ADDR = 0xfffe10100038 # macro +cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE = 0xfffe1010003c # macro +cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN = 0xfffe1010003d # macro +cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST = 0xfffe10100050 # macro +cfgBIF_CFG_DEV0_RC0_PMI_CAP = 0xfffe10100052 # macro +cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL = 0xfffe10100054 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST = 0xfffe10100058 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_CAP = 0xfffe1010005a # macro +cfgBIF_CFG_DEV0_RC0_DEVICE_CAP = 0xfffe1010005c # macro +cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL = 0xfffe10100060 # macro +cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS = 0xfffe10100062 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CAP = 0xfffe10100064 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CNTL = 0xfffe10100068 # macro +cfgBIF_CFG_DEV0_RC0_LINK_STATUS = 0xfffe1010006a # macro +cfgBIF_CFG_DEV0_RC0_SLOT_CAP = 0xfffe1010006c # macro +cfgBIF_CFG_DEV0_RC0_SLOT_CNTL = 0xfffe10100070 # macro +cfgBIF_CFG_DEV0_RC0_SLOT_STATUS = 0xfffe10100072 # macro +cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2 = 0xfffe1010007c # macro +cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2 = 0xfffe10100080 # macro +cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2 = 0xfffe10100082 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CAP2 = 0xfffe10100084 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CNTL2 = 0xfffe10100088 # macro +cfgBIF_CFG_DEV0_RC0_LINK_STATUS2 = 0xfffe1010008a # macro +cfgBIF_CFG_DEV0_RC0_SLOT_CAP2 = 0xfffe1010008c # macro +cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2 = 0xfffe10100090 # macro +cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2 = 0xfffe10100092 # macro +cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST = 0xfffe101000a0 # macro +cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL = 0xfffe101000a2 # macro +cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO = 0xfffe101000a4 # macro +cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI = 0xfffe101000a8 # macro +cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA = 0xfffe101000a8 # macro +cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA = 0xfffe101000aa # macro +cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 = 0xfffe101000ac # macro +cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 = 0xfffe101000ae # macro +cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST = 0xfffe101000c0 # macro +cfgBIF_CFG_DEV0_RC0_SSID_CAP = 0xfffe101000c4 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10100100 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10100104 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10100108 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1010010c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST = 0xfffe10100110 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 = 0xfffe10100114 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 = 0xfffe10100118 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL = 0xfffe1010011c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS = 0xfffe1010011e # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP = 0xfffe10100120 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL = 0xfffe10100124 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS = 0xfffe1010012a # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP = 0xfffe1010012c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL = 0xfffe10100130 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS = 0xfffe10100136 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0xfffe10100140 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 = 0xfffe10100144 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 = 0xfffe10100148 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10100150 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS = 0xfffe10100154 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK = 0xfffe10100158 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1010015c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS = 0xfffe10100160 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK = 0xfffe10100164 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10100168 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 = 0xfffe1010016c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 = 0xfffe10100170 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 = 0xfffe10100174 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 = 0xfffe10100178 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10100188 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1010018c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10100190 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10100194 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST = 0xfffe10100270 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 = 0xfffe10100274 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS = 0xfffe10100278 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL = 0xfffe1010027c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL = 0xfffe1010027e # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL = 0xfffe10100280 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL = 0xfffe10100282 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL = 0xfffe10100284 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL = 0xfffe10100286 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL = 0xfffe10100288 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL = 0xfffe1010028a # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL = 0xfffe1010028c # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL = 0xfffe1010028e # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL = 0xfffe10100290 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL = 0xfffe10100292 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL = 0xfffe10100294 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL = 0xfffe10100296 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL = 0xfffe10100298 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL = 0xfffe1010029a # macro +cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST = 0xfffe101002a0 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP = 0xfffe101002a4 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL = 0xfffe101002a6 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST = 0xfffe10100400 # macro +cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP = 0xfffe10100404 # macro +cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS = 0xfffe10100408 # macro +cfgBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST = 0xfffe10100410 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CAP_16GT = 0xfffe10100414 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CNTL_16GT = 0xfffe10100418 # macro +cfgBIF_CFG_DEV0_RC0_LINK_STATUS_16GT = 0xfffe1010041c # macro +cfgBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0xfffe10100420 # macro +cfgBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT = 0xfffe10100424 # macro +cfgBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT = 0xfffe10100428 # macro +cfgBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT = 0xfffe10100430 # macro +cfgBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT = 0xfffe10100431 # macro +cfgBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT = 0xfffe10100432 # macro +cfgBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT = 0xfffe10100433 # macro +cfgBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT = 0xfffe10100434 # macro +cfgBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT = 0xfffe10100435 # macro +cfgBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT = 0xfffe10100436 # macro +cfgBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT = 0xfffe10100437 # macro +cfgBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT = 0xfffe10100438 # macro +cfgBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT = 0xfffe10100439 # macro +cfgBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT = 0xfffe1010043a # macro +cfgBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT = 0xfffe1010043b # macro +cfgBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT = 0xfffe1010043c # macro +cfgBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT = 0xfffe1010043d # macro +cfgBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT = 0xfffe1010043e # macro +cfgBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT = 0xfffe1010043f # macro +cfgBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST = 0xfffe10100450 # macro +cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP = 0xfffe10100454 # macro +cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS = 0xfffe10100456 # macro +cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL = 0xfffe10100458 # macro +cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS = 0xfffe1010045a # macro +cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL = 0xfffe1010045c # macro +cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS = 0xfffe1010045e # macro +cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL = 0xfffe10100460 # macro +cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS = 0xfffe10100462 # macro +cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL = 0xfffe10100464 # macro +cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS = 0xfffe10100466 # macro +cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL = 0xfffe10100468 # macro +cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS = 0xfffe1010046a # macro +cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL = 0xfffe1010046c # macro +cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS = 0xfffe1010046e # macro +cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL = 0xfffe10100470 # macro +cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS = 0xfffe10100472 # macro +cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL = 0xfffe10100474 # macro +cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS = 0xfffe10100476 # macro +cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL = 0xfffe10100478 # macro +cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS = 0xfffe1010047a # macro +cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL = 0xfffe1010047c # macro +cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS = 0xfffe1010047e # macro +cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL = 0xfffe10100480 # macro +cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS = 0xfffe10100482 # macro +cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL = 0xfffe10100484 # macro +cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS = 0xfffe10100486 # macro +cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL = 0xfffe10100488 # macro +cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS = 0xfffe1010048a # macro +cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL = 0xfffe1010048c # macro +cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS = 0xfffe1010048e # macro +cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL = 0xfffe10100490 # macro +cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS = 0xfffe10100492 # macro +cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL = 0xfffe10100494 # macro +cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS = 0xfffe10100496 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CAP_32GT = 0xfffe10100504 # macro +cfgBIF_CFG_DEV0_RC0_LINK_CNTL_32GT = 0xfffe10100508 # macro +cfgBIF_CFG_DEV0_RC0_LINK_STATUS_32GT = 0xfffe1010050c # macro +cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID = 0xfffe10200000 # macro +cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID = 0xfffe10200002 # macro +cfgBIF_CFG_DEV0_EPF0_0_COMMAND = 0xfffe10200004 # macro +cfgBIF_CFG_DEV0_EPF0_0_STATUS = 0xfffe10200006 # macro +cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID = 0xfffe10200008 # macro +cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE = 0xfffe10200009 # macro +cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS = 0xfffe1020000a # macro +cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS = 0xfffe1020000b # macro +cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE = 0xfffe1020000c # macro +cfgBIF_CFG_DEV0_EPF0_0_LATENCY = 0xfffe1020000d # macro +cfgBIF_CFG_DEV0_EPF0_0_HEADER = 0xfffe1020000e # macro +cfgBIF_CFG_DEV0_EPF0_0_BIST = 0xfffe1020000f # macro +cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 = 0xfffe10200010 # macro +cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 = 0xfffe10200014 # macro +cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 = 0xfffe10200018 # macro +cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 = 0xfffe1020001c # macro +cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 = 0xfffe10200020 # macro +cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 = 0xfffe10200024 # macro +cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR = 0xfffe10200028 # macro +cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID = 0xfffe1020002c # macro +cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR = 0xfffe10200030 # macro +cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR = 0xfffe10200034 # macro +cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE = 0xfffe1020003c # macro +cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN = 0xfffe1020003d # macro +cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT = 0xfffe1020003e # macro +cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY = 0xfffe1020003f # macro +cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST = 0xfffe10200048 # macro +cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W = 0xfffe1020004c # macro +cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST = 0xfffe10200050 # macro +cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP = 0xfffe10200052 # macro +cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL = 0xfffe10200054 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST = 0xfffe10200064 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP = 0xfffe10200066 # macro +cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP = 0xfffe10200068 # macro +cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL = 0xfffe1020006c # macro +cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS = 0xfffe1020006e # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP = 0xfffe10200070 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL = 0xfffe10200074 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS = 0xfffe10200076 # macro +cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 = 0xfffe10200088 # macro +cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 = 0xfffe1020008c # macro +cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 = 0xfffe1020008e # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 = 0xfffe10200090 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 = 0xfffe10200094 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 = 0xfffe10200096 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST = 0xfffe102000a0 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL = 0xfffe102000a2 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO = 0xfffe102000a4 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI = 0xfffe102000a8 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA = 0xfffe102000a8 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA = 0xfffe102000aa # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK = 0xfffe102000ac # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 = 0xfffe102000ac # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 = 0xfffe102000ae # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 = 0xfffe102000b0 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING = 0xfffe102000b0 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 = 0xfffe102000b4 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST = 0xfffe102000c0 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL = 0xfffe102000c2 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE = 0xfffe102000c4 # macro +cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA = 0xfffe102000c8 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10200100 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10200104 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10200108 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1020010c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST = 0xfffe10200110 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 = 0xfffe10200114 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 = 0xfffe10200118 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL = 0xfffe1020011c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS = 0xfffe1020011e # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP = 0xfffe10200120 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL = 0xfffe10200124 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS = 0xfffe1020012a # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP = 0xfffe1020012c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL = 0xfffe10200130 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS = 0xfffe10200136 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0xfffe10200140 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 = 0xfffe10200144 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 = 0xfffe10200148 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10200150 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10200154 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK = 0xfffe10200158 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1020015c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS = 0xfffe10200160 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK = 0xfffe10200164 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10200168 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 = 0xfffe1020016c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 = 0xfffe10200170 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 = 0xfffe10200174 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 = 0xfffe10200178 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10200188 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1020018c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10200190 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10200194 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST = 0xfffe10200200 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP = 0xfffe10200204 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL = 0xfffe10200208 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP = 0xfffe1020020c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL = 0xfffe10200210 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP = 0xfffe10200214 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL = 0xfffe10200218 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP = 0xfffe1020021c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL = 0xfffe10200220 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP = 0xfffe10200224 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL = 0xfffe10200228 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP = 0xfffe1020022c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL = 0xfffe10200230 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0xfffe10200240 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT = 0xfffe10200244 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA = 0xfffe10200248 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP = 0xfffe1020024c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST = 0xfffe10200250 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP = 0xfffe10200254 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR = 0xfffe10200258 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS = 0xfffe1020025c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL = 0xfffe1020025e # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0xfffe10200260 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0xfffe10200261 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0xfffe10200262 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0xfffe10200263 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0xfffe10200264 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0xfffe10200265 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0xfffe10200266 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0xfffe10200267 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST = 0xfffe10200270 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 = 0xfffe10200274 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS = 0xfffe10200278 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL = 0xfffe1020027c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL = 0xfffe1020027e # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL = 0xfffe10200280 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL = 0xfffe10200282 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL = 0xfffe10200284 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL = 0xfffe10200286 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL = 0xfffe10200288 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL = 0xfffe1020028a # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL = 0xfffe1020028c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL = 0xfffe1020028e # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL = 0xfffe10200290 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL = 0xfffe10200292 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL = 0xfffe10200294 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL = 0xfffe10200296 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL = 0xfffe10200298 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL = 0xfffe1020029a # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST = 0xfffe102002a0 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP = 0xfffe102002a4 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL = 0xfffe102002a6 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST = 0xfffe102002d0 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP = 0xfffe102002d4 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL = 0xfffe102002d6 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST = 0xfffe102002f0 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP = 0xfffe102002f4 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL = 0xfffe102002f6 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 = 0xfffe102002f8 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 = 0xfffe102002fc # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 = 0xfffe10200300 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 = 0xfffe10200304 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 = 0xfffe10200308 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 = 0xfffe1020030c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0xfffe10200310 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0xfffe10200314 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST = 0xfffe10200320 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP = 0xfffe10200324 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10200328 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP = 0xfffe1020032c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL = 0xfffe1020032e # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST = 0xfffe10200330 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP = 0xfffe10200334 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL = 0xfffe10200338 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS = 0xfffe1020033a # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS = 0xfffe1020033c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS = 0xfffe1020033e # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS = 0xfffe10200340 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK = 0xfffe10200342 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET = 0xfffe10200344 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE = 0xfffe10200346 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID = 0xfffe1020034a # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0xfffe1020034c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE = 0xfffe10200350 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 = 0xfffe10200354 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 = 0xfffe10200358 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 = 0xfffe1020035c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 = 0xfffe10200360 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 = 0xfffe10200364 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 = 0xfffe10200368 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0xfffe1020036c # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST = 0xfffe10200400 # macro +cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP = 0xfffe10200404 # macro +cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS = 0xfffe10200408 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST = 0xfffe10200410 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT = 0xfffe10200414 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT = 0xfffe10200418 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT = 0xfffe1020041c # macro +cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0xfffe10200420 # macro +cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT = 0xfffe10200424 # macro +cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT = 0xfffe10200428 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT = 0xfffe10200430 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT = 0xfffe10200431 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT = 0xfffe10200432 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT = 0xfffe10200433 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT = 0xfffe10200434 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT = 0xfffe10200435 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT = 0xfffe10200436 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT = 0xfffe10200437 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT = 0xfffe10200438 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT = 0xfffe10200439 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT = 0xfffe1020043a # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT = 0xfffe1020043b # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT = 0xfffe1020043c # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT = 0xfffe1020043d # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT = 0xfffe1020043e # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT = 0xfffe1020043f # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST = 0xfffe10200450 # macro +cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP = 0xfffe10200454 # macro +cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS = 0xfffe10200456 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL = 0xfffe10200458 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS = 0xfffe1020045a # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL = 0xfffe1020045c # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS = 0xfffe1020045e # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL = 0xfffe10200460 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS = 0xfffe10200462 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL = 0xfffe10200464 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS = 0xfffe10200466 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL = 0xfffe10200468 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS = 0xfffe1020046a # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL = 0xfffe1020046c # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS = 0xfffe1020046e # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL = 0xfffe10200470 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS = 0xfffe10200472 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL = 0xfffe10200474 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS = 0xfffe10200476 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL = 0xfffe10200478 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS = 0xfffe1020047a # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL = 0xfffe1020047c # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS = 0xfffe1020047e # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL = 0xfffe10200480 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS = 0xfffe10200482 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL = 0xfffe10200484 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS = 0xfffe10200486 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL = 0xfffe10200488 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS = 0xfffe1020048a # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL = 0xfffe1020048c # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS = 0xfffe1020048e # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL = 0xfffe10200490 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS = 0xfffe10200492 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL = 0xfffe10200494 # macro +cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS = 0xfffe10200496 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST = 0xfffe102004c0 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP = 0xfffe102004c4 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL = 0xfffe102004c8 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP = 0xfffe102004cc # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL = 0xfffe102004d0 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP = 0xfffe102004d4 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL = 0xfffe102004d8 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP = 0xfffe102004dc # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL = 0xfffe102004e0 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP = 0xfffe102004e4 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL = 0xfffe102004e8 # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP = 0xfffe102004ec # macro +cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL = 0xfffe102004f0 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT = 0xfffe10200504 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT = 0xfffe10200508 # macro +cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT = 0xfffe1020050c # macro +cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID = 0xfffe10201000 # macro +cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID = 0xfffe10201002 # macro +cfgBIF_CFG_DEV0_EPF1_0_COMMAND = 0xfffe10201004 # macro +cfgBIF_CFG_DEV0_EPF1_0_STATUS = 0xfffe10201006 # macro +cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID = 0xfffe10201008 # macro +cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE = 0xfffe10201009 # macro +cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS = 0xfffe1020100a # macro +cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS = 0xfffe1020100b # macro +cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE = 0xfffe1020100c # macro +cfgBIF_CFG_DEV0_EPF1_0_LATENCY = 0xfffe1020100d # macro +cfgBIF_CFG_DEV0_EPF1_0_HEADER = 0xfffe1020100e # macro +cfgBIF_CFG_DEV0_EPF1_0_BIST = 0xfffe1020100f # macro +cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 = 0xfffe10201010 # macro +cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 = 0xfffe10201014 # macro +cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 = 0xfffe10201018 # macro +cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 = 0xfffe1020101c # macro +cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 = 0xfffe10201020 # macro +cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 = 0xfffe10201024 # macro +cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR = 0xfffe10201028 # macro +cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID = 0xfffe1020102c # macro +cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR = 0xfffe10201030 # macro +cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR = 0xfffe10201034 # macro +cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE = 0xfffe1020103c # macro +cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN = 0xfffe1020103d # macro +cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT = 0xfffe1020103e # macro +cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY = 0xfffe1020103f # macro +cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST = 0xfffe10201048 # macro +cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W = 0xfffe1020104c # macro +cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST = 0xfffe10201050 # macro +cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP = 0xfffe10201052 # macro +cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL = 0xfffe10201054 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST = 0xfffe10201064 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP = 0xfffe10201066 # macro +cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP = 0xfffe10201068 # macro +cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL = 0xfffe1020106c # macro +cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS = 0xfffe1020106e # macro +cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP = 0xfffe10201070 # macro +cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL = 0xfffe10201074 # macro +cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS = 0xfffe10201076 # macro +cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 = 0xfffe10201088 # macro +cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 = 0xfffe1020108c # macro +cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 = 0xfffe1020108e # macro +cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 = 0xfffe10201090 # macro +cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 = 0xfffe10201094 # macro +cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 = 0xfffe10201096 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST = 0xfffe102010a0 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL = 0xfffe102010a2 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO = 0xfffe102010a4 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI = 0xfffe102010a8 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA = 0xfffe102010a8 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA = 0xfffe102010aa # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK = 0xfffe102010ac # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 = 0xfffe102010ac # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 = 0xfffe102010ae # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 = 0xfffe102010b0 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING = 0xfffe102010b0 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 = 0xfffe102010b4 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST = 0xfffe102010c0 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL = 0xfffe102010c2 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE = 0xfffe102010c4 # macro +cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA = 0xfffe102010c8 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10201100 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10201104 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10201108 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1020110c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0xfffe10201140 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 = 0xfffe10201144 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 = 0xfffe10201148 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10201150 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10201154 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK = 0xfffe10201158 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1020115c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS = 0xfffe10201160 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK = 0xfffe10201164 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10201168 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 = 0xfffe1020116c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 = 0xfffe10201170 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 = 0xfffe10201174 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 = 0xfffe10201178 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10201188 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1020118c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10201190 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10201194 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST = 0xfffe10201200 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP = 0xfffe10201204 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL = 0xfffe10201208 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP = 0xfffe1020120c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL = 0xfffe10201210 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP = 0xfffe10201214 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL = 0xfffe10201218 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP = 0xfffe1020121c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL = 0xfffe10201220 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP = 0xfffe10201224 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL = 0xfffe10201228 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP = 0xfffe1020122c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL = 0xfffe10201230 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0xfffe10201240 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT = 0xfffe10201244 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA = 0xfffe10201248 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP = 0xfffe1020124c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST = 0xfffe10201250 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP = 0xfffe10201254 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR = 0xfffe10201258 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS = 0xfffe1020125c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL = 0xfffe1020125e # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0xfffe10201260 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0xfffe10201261 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0xfffe10201262 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0xfffe10201263 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0xfffe10201264 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0xfffe10201265 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0xfffe10201266 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0xfffe10201267 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST = 0xfffe10201270 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 = 0xfffe10201274 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS = 0xfffe10201278 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL = 0xfffe1020127c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL = 0xfffe1020127e # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL = 0xfffe10201280 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL = 0xfffe10201282 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL = 0xfffe10201284 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL = 0xfffe10201286 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL = 0xfffe10201288 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL = 0xfffe1020128a # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL = 0xfffe1020128c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL = 0xfffe1020128e # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL = 0xfffe10201290 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL = 0xfffe10201292 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL = 0xfffe10201294 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL = 0xfffe10201296 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL = 0xfffe10201298 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL = 0xfffe1020129a # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST = 0xfffe102012a0 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP = 0xfffe102012a4 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL = 0xfffe102012a6 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST = 0xfffe102012d0 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP = 0xfffe102012d4 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL = 0xfffe102012d6 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST = 0xfffe102012f0 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP = 0xfffe102012f4 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL = 0xfffe102012f6 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 = 0xfffe102012f8 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 = 0xfffe102012fc # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 = 0xfffe10201300 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 = 0xfffe10201304 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 = 0xfffe10201308 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 = 0xfffe1020130c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0xfffe10201310 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0xfffe10201314 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST = 0xfffe10201320 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP = 0xfffe10201324 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10201328 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP = 0xfffe1020132c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL = 0xfffe1020132e # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST = 0xfffe10201330 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP = 0xfffe10201334 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL = 0xfffe10201338 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS = 0xfffe1020133a # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS = 0xfffe1020133c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS = 0xfffe1020133e # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS = 0xfffe10201340 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK = 0xfffe10201342 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET = 0xfffe10201344 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE = 0xfffe10201346 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID = 0xfffe1020134a # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0xfffe1020134c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE = 0xfffe10201350 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 = 0xfffe10201354 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 = 0xfffe10201358 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 = 0xfffe1020135c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 = 0xfffe10201360 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 = 0xfffe10201364 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 = 0xfffe10201368 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0xfffe1020136c # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST = 0xfffe102014c0 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP = 0xfffe102014c4 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL = 0xfffe102014c8 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP = 0xfffe102014cc # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL = 0xfffe102014d0 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP = 0xfffe102014d4 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL = 0xfffe102014d8 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP = 0xfffe102014dc # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL = 0xfffe102014e0 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP = 0xfffe102014e4 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL = 0xfffe102014e8 # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP = 0xfffe102014ec # macro +cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL = 0xfffe102014f0 # macro +cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID = 0xfffe10202000 # macro +cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID = 0xfffe10202002 # macro +cfgBIF_CFG_DEV0_EPF2_0_COMMAND = 0xfffe10202004 # macro +cfgBIF_CFG_DEV0_EPF2_0_STATUS = 0xfffe10202006 # macro +cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID = 0xfffe10202008 # macro +cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE = 0xfffe10202009 # macro +cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS = 0xfffe1020200a # macro +cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS = 0xfffe1020200b # macro +cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE = 0xfffe1020200c # macro +cfgBIF_CFG_DEV0_EPF2_0_LATENCY = 0xfffe1020200d # macro +cfgBIF_CFG_DEV0_EPF2_0_HEADER = 0xfffe1020200e # macro +cfgBIF_CFG_DEV0_EPF2_0_BIST = 0xfffe1020200f # macro +cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 = 0xfffe10202010 # macro +cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 = 0xfffe10202014 # macro +cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 = 0xfffe10202018 # macro +cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 = 0xfffe1020201c # macro +cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 = 0xfffe10202020 # macro +cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 = 0xfffe10202024 # macro +cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR = 0xfffe10202028 # macro +cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID = 0xfffe1020202c # macro +cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR = 0xfffe10202030 # macro +cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR = 0xfffe10202034 # macro +cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE = 0xfffe1020203c # macro +cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN = 0xfffe1020203d # macro +cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT = 0xfffe1020203e # macro +cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY = 0xfffe1020203f # macro +cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST = 0xfffe10202048 # macro +cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W = 0xfffe1020204c # macro +cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST = 0xfffe10202050 # macro +cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP = 0xfffe10202052 # macro +cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL = 0xfffe10202054 # macro +cfgBIF_CFG_DEV0_EPF2_0_SBRN = 0xfffe10202060 # macro +cfgBIF_CFG_DEV0_EPF2_0_FLADJ = 0xfffe10202061 # macro +cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD = 0xfffe10202062 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST = 0xfffe10202064 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP = 0xfffe10202066 # macro +cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP = 0xfffe10202068 # macro +cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL = 0xfffe1020206c # macro +cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS = 0xfffe1020206e # macro +cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP = 0xfffe10202070 # macro +cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL = 0xfffe10202074 # macro +cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS = 0xfffe10202076 # macro +cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 = 0xfffe10202088 # macro +cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 = 0xfffe1020208c # macro +cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 = 0xfffe1020208e # macro +cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 = 0xfffe10202090 # macro +cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 = 0xfffe10202094 # macro +cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 = 0xfffe10202096 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST = 0xfffe102020a0 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL = 0xfffe102020a2 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO = 0xfffe102020a4 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI = 0xfffe102020a8 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA = 0xfffe102020a8 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA = 0xfffe102020aa # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK = 0xfffe102020ac # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 = 0xfffe102020ac # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 = 0xfffe102020ae # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 = 0xfffe102020b0 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING = 0xfffe102020b0 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 = 0xfffe102020b4 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST = 0xfffe102020c0 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL = 0xfffe102020c2 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE = 0xfffe102020c4 # macro +cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA = 0xfffe102020c8 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10202100 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10202104 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10202108 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1020210c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10202150 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10202154 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK = 0xfffe10202158 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1020215c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS = 0xfffe10202160 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK = 0xfffe10202164 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10202168 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 = 0xfffe1020216c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 = 0xfffe10202170 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 = 0xfffe10202174 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 = 0xfffe10202178 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10202188 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1020218c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10202190 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10202194 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST = 0xfffe10202200 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP = 0xfffe10202204 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL = 0xfffe10202208 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP = 0xfffe1020220c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL = 0xfffe10202210 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP = 0xfffe10202214 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL = 0xfffe10202218 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP = 0xfffe1020221c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL = 0xfffe10202220 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP = 0xfffe10202224 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL = 0xfffe10202228 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP = 0xfffe1020222c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL = 0xfffe10202230 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0xfffe10202240 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT = 0xfffe10202244 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA = 0xfffe10202248 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP = 0xfffe1020224c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST = 0xfffe10202250 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP = 0xfffe10202254 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR = 0xfffe10202258 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS = 0xfffe1020225c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL = 0xfffe1020225e # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0xfffe10202260 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0xfffe10202261 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0xfffe10202262 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0xfffe10202263 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0xfffe10202264 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0xfffe10202265 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0xfffe10202266 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0xfffe10202267 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST = 0xfffe102022a0 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP = 0xfffe102022a4 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL = 0xfffe102022a6 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST = 0xfffe102022d0 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP = 0xfffe102022d4 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL = 0xfffe102022d6 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10202328 # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP = 0xfffe1020232c # macro +cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL = 0xfffe1020232e # macro +cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID = 0xfffe10203000 # macro +cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID = 0xfffe10203002 # macro +cfgBIF_CFG_DEV0_EPF3_0_COMMAND = 0xfffe10203004 # macro +cfgBIF_CFG_DEV0_EPF3_0_STATUS = 0xfffe10203006 # macro +cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID = 0xfffe10203008 # macro +cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE = 0xfffe10203009 # macro +cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS = 0xfffe1020300a # macro +cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS = 0xfffe1020300b # macro +cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE = 0xfffe1020300c # macro +cfgBIF_CFG_DEV0_EPF3_0_LATENCY = 0xfffe1020300d # macro +cfgBIF_CFG_DEV0_EPF3_0_HEADER = 0xfffe1020300e # macro +cfgBIF_CFG_DEV0_EPF3_0_BIST = 0xfffe1020300f # macro +cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 = 0xfffe10203010 # macro +cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 = 0xfffe10203014 # macro +cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 = 0xfffe10203018 # macro +cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 = 0xfffe1020301c # macro +cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 = 0xfffe10203020 # macro +cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 = 0xfffe10203024 # macro +cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR = 0xfffe10203028 # macro +cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID = 0xfffe1020302c # macro +cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR = 0xfffe10203030 # macro +cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR = 0xfffe10203034 # macro +cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE = 0xfffe1020303c # macro +cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN = 0xfffe1020303d # macro +cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT = 0xfffe1020303e # macro +cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY = 0xfffe1020303f # macro +cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST = 0xfffe10203048 # macro +cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W = 0xfffe1020304c # macro +cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST = 0xfffe10203050 # macro +cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP = 0xfffe10203052 # macro +cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL = 0xfffe10203054 # macro +cfgBIF_CFG_DEV0_EPF3_0_SBRN = 0xfffe10203060 # macro +cfgBIF_CFG_DEV0_EPF3_0_FLADJ = 0xfffe10203061 # macro +cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD = 0xfffe10203062 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST = 0xfffe10203064 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP = 0xfffe10203066 # macro +cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP = 0xfffe10203068 # macro +cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL = 0xfffe1020306c # macro +cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS = 0xfffe1020306e # macro +cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP = 0xfffe10203070 # macro +cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL = 0xfffe10203074 # macro +cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS = 0xfffe10203076 # macro +cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 = 0xfffe10203088 # macro +cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 = 0xfffe1020308c # macro +cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 = 0xfffe1020308e # macro +cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 = 0xfffe10203090 # macro +cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 = 0xfffe10203094 # macro +cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 = 0xfffe10203096 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST = 0xfffe102030a0 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL = 0xfffe102030a2 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO = 0xfffe102030a4 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI = 0xfffe102030a8 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA = 0xfffe102030a8 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA = 0xfffe102030aa # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK = 0xfffe102030ac # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 = 0xfffe102030ac # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 = 0xfffe102030ae # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 = 0xfffe102030b0 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING = 0xfffe102030b0 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 = 0xfffe102030b4 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST = 0xfffe102030c0 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL = 0xfffe102030c2 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE = 0xfffe102030c4 # macro +cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA = 0xfffe102030c8 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10203100 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10203104 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10203108 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1020310c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10203150 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10203154 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK = 0xfffe10203158 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1020315c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS = 0xfffe10203160 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK = 0xfffe10203164 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10203168 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 = 0xfffe1020316c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 = 0xfffe10203170 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 = 0xfffe10203174 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 = 0xfffe10203178 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10203188 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1020318c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10203190 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10203194 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST = 0xfffe10203200 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP = 0xfffe10203204 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL = 0xfffe10203208 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP = 0xfffe1020320c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL = 0xfffe10203210 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP = 0xfffe10203214 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL = 0xfffe10203218 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP = 0xfffe1020321c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL = 0xfffe10203220 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP = 0xfffe10203224 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL = 0xfffe10203228 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP = 0xfffe1020322c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL = 0xfffe10203230 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0xfffe10203240 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT = 0xfffe10203244 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA = 0xfffe10203248 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP = 0xfffe1020324c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST = 0xfffe10203250 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP = 0xfffe10203254 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR = 0xfffe10203258 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS = 0xfffe1020325c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL = 0xfffe1020325e # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0xfffe10203260 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0xfffe10203261 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0xfffe10203262 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0xfffe10203263 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0xfffe10203264 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0xfffe10203265 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0xfffe10203266 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0xfffe10203267 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST = 0xfffe102032a0 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP = 0xfffe102032a4 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL = 0xfffe102032a6 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST = 0xfffe102032d0 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP = 0xfffe102032d4 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL = 0xfffe102032d6 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10203328 # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP = 0xfffe1020332c # macro +cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL = 0xfffe1020332e # macro +cfgPCIE_INDEX = 0x30200030 # macro +cfgPCIE_DATA = 0x30200034 # macro +cfgPCIE_INDEX2 = 0x30200038 # macro +cfgPCIE_DATA2 = 0x3020003c # macro +cfgPCIE_INDEX_HI = 0x30200040 # macro +cfgPCIE_INDEX2_HI = 0x30200044 # macro +cfgSBIOS_SCRATCH_0 = 0x30200120 # macro +cfgSBIOS_SCRATCH_1 = 0x30200124 # macro +cfgSBIOS_SCRATCH_2 = 0x30200128 # macro +cfgSBIOS_SCRATCH_3 = 0x3020012c # macro +cfgBIOS_SCRATCH_0 = 0x30200130 # macro +cfgBIOS_SCRATCH_1 = 0x30200134 # macro +cfgBIOS_SCRATCH_2 = 0x30200138 # macro +cfgBIOS_SCRATCH_3 = 0x3020013c # macro +cfgBIOS_SCRATCH_4 = 0x30200140 # macro +cfgBIOS_SCRATCH_5 = 0x30200144 # macro +cfgBIOS_SCRATCH_6 = 0x30200148 # macro +cfgBIOS_SCRATCH_7 = 0x3020014c # macro +cfgBIOS_SCRATCH_8 = 0x30200150 # macro +cfgBIOS_SCRATCH_9 = 0x30200154 # macro +cfgBIOS_SCRATCH_10 = 0x30200158 # macro +cfgBIOS_SCRATCH_11 = 0x3020015c # macro +cfgBIOS_SCRATCH_12 = 0x30200160 # macro +cfgBIOS_SCRATCH_13 = 0x30200164 # macro +cfgBIOS_SCRATCH_14 = 0x30200168 # macro +cfgBIOS_SCRATCH_15 = 0x3020016c # macro +cfgBIF_RLC_INTR_CNTL = 0x30200180 # macro +cfgBIF_VCE_INTR_CNTL = 0x30200184 # macro +cfgBIF_UVD_INTR_CNTL = 0x30200188 # macro +cfgGFX_MMIOREG_CAM_ADDR0 = 0x30200200 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR0 = 0x30200204 # macro +cfgGFX_MMIOREG_CAM_ADDR1 = 0x30200208 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR1 = 0x3020020c # macro +cfgGFX_MMIOREG_CAM_ADDR2 = 0x30200210 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR2 = 0x30200214 # macro +cfgGFX_MMIOREG_CAM_ADDR3 = 0x30200218 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR3 = 0x3020021c # macro +cfgGFX_MMIOREG_CAM_ADDR4 = 0x30200220 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR4 = 0x30200224 # macro +cfgGFX_MMIOREG_CAM_ADDR5 = 0x30200228 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR5 = 0x3020022c # macro +cfgGFX_MMIOREG_CAM_ADDR6 = 0x30200230 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR6 = 0x30200234 # macro +cfgGFX_MMIOREG_CAM_ADDR7 = 0x30200238 # macro +cfgGFX_MMIOREG_CAM_REMAP_ADDR7 = 0x3020023c # macro +cfgGFX_MMIOREG_CAM_CNTL = 0x30200240 # macro +cfgGFX_MMIOREG_CAM_ZERO_CPL = 0x30200244 # macro +cfgGFX_MMIOREG_CAM_ONE_CPL = 0x30200248 # macro +cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL = 0x3020024c # macro +cfgDRIVER_SCRATCH_0 = 0x30200250 # macro +cfgDRIVER_SCRATCH_1 = 0x30200254 # macro +cfgDRIVER_SCRATCH_2 = 0x30200258 # macro +cfgDRIVER_SCRATCH_3 = 0x3020025c # macro +cfgDRIVER_SCRATCH_4 = 0x30200260 # macro +cfgDRIVER_SCRATCH_5 = 0x30200264 # macro +cfgDRIVER_SCRATCH_6 = 0x30200268 # macro +cfgDRIVER_SCRATCH_7 = 0x3020026c # macro +cfgDRIVER_SCRATCH_8 = 0x30200270 # macro +cfgDRIVER_SCRATCH_9 = 0x30200274 # macro +cfgDRIVER_SCRATCH_10 = 0x30200278 # macro +cfgDRIVER_SCRATCH_11 = 0x3020027c # macro +cfgDRIVER_SCRATCH_12 = 0x30200280 # macro +cfgDRIVER_SCRATCH_13 = 0x30200284 # macro +cfgDRIVER_SCRATCH_14 = 0x30200288 # macro +cfgDRIVER_SCRATCH_15 = 0x3020028c # macro +cfgFW_SCRATCH_0 = 0x30200290 # macro +cfgFW_SCRATCH_1 = 0x30200294 # macro +cfgFW_SCRATCH_2 = 0x30200298 # macro +cfgFW_SCRATCH_3 = 0x3020029c # macro +cfgFW_SCRATCH_4 = 0x302002a0 # macro +cfgFW_SCRATCH_5 = 0x302002a4 # macro +cfgFW_SCRATCH_6 = 0x302002a8 # macro +cfgFW_SCRATCH_7 = 0x302002ac # macro +cfgFW_SCRATCH_8 = 0x302002b0 # macro +cfgFW_SCRATCH_9 = 0x302002b4 # macro +cfgFW_SCRATCH_10 = 0x302002b8 # macro +cfgFW_SCRATCH_11 = 0x302002bc # macro +cfgFW_SCRATCH_12 = 0x302002c0 # macro +cfgFW_SCRATCH_13 = 0x302002c4 # macro +cfgFW_SCRATCH_14 = 0x302002c8 # macro +cfgFW_SCRATCH_15 = 0x302002cc # macro +cfgSBIOS_SCRATCH_4 = 0x302002d0 # macro +cfgSBIOS_SCRATCH_5 = 0x302002d4 # macro +cfgSBIOS_SCRATCH_6 = 0x302002d8 # macro +cfgSBIOS_SCRATCH_7 = 0x302002dc # macro +cfgSBIOS_SCRATCH_8 = 0x302002e0 # macro +cfgSBIOS_SCRATCH_9 = 0x302002e4 # macro +cfgSBIOS_SCRATCH_10 = 0x302002e8 # macro +cfgSBIOS_SCRATCH_11 = 0x302002ec # macro +cfgSBIOS_SCRATCH_12 = 0x302002f0 # macro +cfgSBIOS_SCRATCH_13 = 0x302002f4 # macro +cfgSBIOS_SCRATCH_14 = 0x302002f8 # macro +cfgSBIOS_SCRATCH_15 = 0x302002fc # macro +cfgDN_PCIE_RESERVED = 0x30203600 # macro +cfgDN_PCIE_SCRATCH = 0x30203604 # macro +cfgDN_PCIE_CNTL = 0x3020360c # macro +cfgDN_PCIE_CONFIG_CNTL = 0x30203610 # macro +cfgDN_PCIE_RX_CNTL2 = 0x30203614 # macro +cfgDN_PCIE_BUS_CNTL = 0x30203618 # macro +cfgDN_PCIE_CFG_CNTL = 0x3020361c # macro +cfgDN_PCIE_STRAP_F0 = 0x30203620 # macro +cfgDN_PCIE_STRAP_MISC = 0x30203624 # macro +cfgDN_PCIE_STRAP_MISC2 = 0x30203628 # macro +cfgPCIE_ERR_CNTL = 0x30203630 # macro +cfgPCIE_RX_CNTL = 0x30203634 # macro +cfgPCIE_LC_SPEED_CNTL = 0x30203638 # macro +cfgPCIE_LC_CNTL2 = 0x3020363c # macro +cfgPCIEP_STRAP_MISC = 0x30203640 # macro +cfgLTR_MSG_INFO_FROM_EP = 0x30203644 # macro +cfgEP_PCIE_SCRATCH = 0x30203580 # macro +cfgEP_PCIE_CNTL = 0x30203588 # macro +cfgEP_PCIE_INT_CNTL = 0x3020358c # macro +cfgEP_PCIE_INT_STATUS = 0x30203590 # macro +cfgEP_PCIE_RX_CNTL2 = 0x30203594 # macro +cfgEP_PCIE_BUS_CNTL = 0x30203598 # macro +cfgEP_PCIE_CFG_CNTL = 0x3020359c # macro +cfgEP_PCIE_TX_LTR_CNTL = 0x302035a4 # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 = 0x302035a8 # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 = 0x302035a9 # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 = 0x302035aa # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 = 0x302035ab # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 = 0x302035ac # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 = 0x302035ad # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 = 0x302035ae # macro +cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 = 0x302035af # macro +cfgEP_PCIE_STRAP_MISC = 0x302035b0 # macro +cfgEP_PCIE_STRAP_MISC2 = 0x302035b4 # macro +cfgEP_PCIE_F0_DPA_CAP = 0x302035bc # macro +cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR = 0x302035c0 # macro +cfgEP_PCIE_F0_DPA_CNTL = 0x302035c1 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 = 0x302035c3 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 = 0x302035c4 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 = 0x302035c5 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 = 0x302035c6 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 = 0x302035c7 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 = 0x302035c8 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 = 0x302035c9 # macro +cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 = 0x302035ca # macro +cfgEP_PCIE_PME_CONTROL = 0x302035cb # macro +cfgEP_PCIEP_RESERVED = 0x302035cc # macro +cfgEP_PCIE_TX_CNTL = 0x302035d4 # macro +cfgEP_PCIE_TX_REQUESTER_ID = 0x302035d8 # macro +cfgEP_PCIE_ERR_CNTL = 0x302035dc # macro +cfgEP_PCIE_RX_CNTL = 0x302035e0 # macro +cfgEP_PCIE_LC_SPEED_CNTL = 0x302035e4 # macro +cfgBIF_BX_PF0_MM_INDEX = 0x30200000 # macro +cfgBIF_BX_PF0_MM_DATA = 0x30200004 # macro +cfgBIF_BX_PF0_MM_INDEX_HI = 0x30200018 # macro +cfgCC_BIF_BX_STRAP0 = 0x30203808 # macro +cfgCC_BIF_BX_PINSTRAP0 = 0x30203810 # macro +cfgBIF_MM_INDACCESS_CNTL = 0x30203818 # macro +cfgBUS_CNTL = 0x3020381c # macro +cfgBIF_SCRATCH0 = 0x30203820 # macro +cfgBIF_SCRATCH1 = 0x30203824 # macro +cfgBX_RESET_EN = 0x30203834 # macro +cfgMM_CFGREGS_CNTL = 0x30203838 # macro +cfgBX_RESET_CNTL = 0x30203840 # macro +cfgINTERRUPT_CNTL = 0x30203844 # macro +cfgINTERRUPT_CNTL2 = 0x30203848 # macro +cfgCLKREQB_PAD_CNTL = 0x30203860 # macro +cfgBIF_FEATURES_CONTROL_MISC = 0x3020386c # macro +cfgHDP_ATOMIC_CONTROL_MISC = 0x30203870 # macro +cfgBIF_DOORBELL_CNTL = 0x30203874 # macro +cfgBIF_DOORBELL_INT_CNTL = 0x30203878 # macro +cfgBIF_FB_EN = 0x30203880 # macro +cfgBIF_INTR_CNTL = 0x30203884 # macro +cfgBIF_MST_TRANS_PENDING_VF = 0x302038a4 # macro +cfgBIF_SLV_TRANS_PENDING_VF = 0x302038a8 # macro +cfgBACO_CNTL = 0x302038ac # macro +cfgBIF_BACO_EXIT_TIME0 = 0x302038b0 # macro +cfgBIF_BACO_EXIT_TIMER1 = 0x302038b4 # macro +cfgBIF_BACO_EXIT_TIMER2 = 0x302038b8 # macro +cfgBIF_BACO_EXIT_TIMER3 = 0x302038bc # macro +cfgBIF_BACO_EXIT_TIMER4 = 0x302038c0 # macro +cfgMEM_TYPE_CNTL = 0x302038c4 # macro +cfgNBIF_GFX_ADDR_LUT_CNTL = 0x302038cc # macro +cfgNBIF_GFX_ADDR_LUT_0 = 0x302038d0 # macro +cfgNBIF_GFX_ADDR_LUT_1 = 0x302038d4 # macro +cfgNBIF_GFX_ADDR_LUT_2 = 0x302038d8 # macro +cfgNBIF_GFX_ADDR_LUT_3 = 0x302038dc # macro +cfgNBIF_GFX_ADDR_LUT_4 = 0x302038e0 # macro +cfgNBIF_GFX_ADDR_LUT_5 = 0x302038e4 # macro +cfgNBIF_GFX_ADDR_LUT_6 = 0x302038e8 # macro +cfgNBIF_GFX_ADDR_LUT_7 = 0x302038ec # macro +cfgNBIF_GFX_ADDR_LUT_8 = 0x302038f0 # macro +cfgNBIF_GFX_ADDR_LUT_9 = 0x302038f4 # macro +cfgNBIF_GFX_ADDR_LUT_10 = 0x302038f8 # macro +cfgNBIF_GFX_ADDR_LUT_11 = 0x302038fc # macro +cfgNBIF_GFX_ADDR_LUT_12 = 0x30203900 # macro +cfgNBIF_GFX_ADDR_LUT_13 = 0x30203904 # macro +cfgNBIF_GFX_ADDR_LUT_14 = 0x30203908 # macro +cfgNBIF_GFX_ADDR_LUT_15 = 0x3020390c # macro +cfgREMAP_HDP_MEM_FLUSH_CNTL = 0x30203934 # macro +cfgREMAP_HDP_REG_FLUSH_CNTL = 0x30203938 # macro +cfgBIF_RB_CNTL = 0x3020393c # macro +cfgBIF_RB_BASE = 0x30203940 # macro +cfgBIF_RB_RPTR = 0x30203944 # macro +cfgBIF_RB_WPTR = 0x30203948 # macro +cfgBIF_RB_WPTR_ADDR_HI = 0x3020394c # macro +cfgBIF_RB_WPTR_ADDR_LO = 0x30203950 # macro +cfgMAILBOX_INDEX = 0x30203954 # macro +cfgBIF_MP1_INTR_CTRL = 0x30203988 # macro +cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE = 0x30203994 # macro +cfgBIF_PERSTB_PAD_CNTL = 0x302039a0 # macro +cfgBIF_PX_EN_PAD_CNTL = 0x302039a4 # macro +cfgBIF_REFPADKIN_PAD_CNTL = 0x302039a8 # macro +cfgBIF_CLKREQB_PAD_CNTL = 0x302039ac # macro +cfgBIF_PWRBRK_PAD_CNTL = 0x302039b0 # macro +cfgBIF_WAKEB_PAD_CNTL = 0x302039b4 # macro +cfgBIF_VAUX_PRESENT_PAD_CNTL = 0x302039b8 # macro +cfgRCC_ERR_INT_CNTL = 0x30203698 # macro +cfgRCC_BACO_CNTL_MISC = 0x3020369c # macro +cfgRCC_RESET_EN = 0x302036a0 # macro +cfgRCC_VDM_SUPPORT = 0x302036a4 # macro +cfgRCC_MARGIN_PARAM_CNTL0 = 0x302036a8 # macro +cfgRCC_MARGIN_PARAM_CNTL1 = 0x302036ac # macro +cfgRCC_GPUIOV_REGION = 0x302036b0 # macro +cfgRCC_PEER_REG_RANGE0 = 0x30203778 # macro +cfgRCC_PEER_REG_RANGE1 = 0x3020377c # macro +cfgRCC_BUS_CNTL = 0x30203784 # macro +cfgRCC_CONFIG_CNTL = 0x30203788 # macro +cfgRCC_CONFIG_F0_BASE = 0x30203798 # macro +cfgRCC_CONFIG_APER_SIZE = 0x3020379c # macro +cfgRCC_CONFIG_REG_APER_SIZE = 0x302037a0 # macro +cfgRCC_XDMA_LO = 0x302037a4 # macro +cfgRCC_XDMA_HI = 0x302037a8 # macro +cfgRCC_FEATURES_CONTROL_MISC = 0x302037ac # macro +cfgRCC_BUSNUM_CNTL1 = 0x302037b0 # macro +cfgRCC_BUSNUM_LIST0 = 0x302037b4 # macro +cfgRCC_BUSNUM_LIST1 = 0x302037b8 # macro +cfgRCC_BUSNUM_CNTL2 = 0x302037bc # macro +cfgRCC_CAPTURE_HOST_BUSNUM = 0x302037c0 # macro +cfgRCC_HOST_BUSNUM = 0x302037c4 # macro +cfgRCC_PEER0_FB_OFFSET_HI = 0x302037c8 # macro +cfgRCC_PEER0_FB_OFFSET_LO = 0x302037cc # macro +cfgRCC_PEER1_FB_OFFSET_HI = 0x302037d0 # macro +cfgRCC_PEER1_FB_OFFSET_LO = 0x302037d4 # macro +cfgRCC_PEER2_FB_OFFSET_HI = 0x302037d8 # macro +cfgRCC_PEER2_FB_OFFSET_LO = 0x302037dc # macro +cfgRCC_PEER3_FB_OFFSET_HI = 0x302037e0 # macro +cfgRCC_PEER3_FB_OFFSET_LO = 0x302037e4 # macro +cfgRCC_DEVFUNCNUM_LIST0 = 0x302037e8 # macro +cfgRCC_DEVFUNCNUM_LIST1 = 0x302037ec # macro +cfgRCC_DEV0_LINK_CNTL = 0x302037f4 # macro +cfgRCC_CMN_LINK_CNTL = 0x302037f8 # macro +cfgRCC_EP_REQUESTERID_RESTORE = 0x302037fc # macro +cfgRCC_LTR_LSWITCH_CNTL = 0x30203800 # macro +cfgRCC_MH_ARB_CNTL = 0x30203804 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO = 0x30242000 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI = 0x30242004 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA = 0x30242008 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL = 0x3024200c # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO = 0x30242010 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI = 0x30242014 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA = 0x30242018 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL = 0x3024201c # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO = 0x30242020 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI = 0x30242024 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA = 0x30242028 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL = 0x3024202c # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO = 0x30242030 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI = 0x30242034 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA = 0x30242038 # macro +cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL = 0x3024203c # macro +cfgRCC_DEV0_EPF0_GFXMSIX_PBA = 0x30243000 # macro +cfgRCC_BIF_STRAP0 = 0x30203480 # macro +cfgRCC_BIF_STRAP1 = 0x30203484 # macro +cfgRCC_BIF_STRAP2 = 0x30203488 # macro +cfgRCC_BIF_STRAP3 = 0x3020348c # macro +cfgRCC_BIF_STRAP4 = 0x30203490 # macro +cfgRCC_BIF_STRAP5 = 0x30203494 # macro +cfgRCC_BIF_STRAP6 = 0x30203498 # macro +cfgRCC_DEV0_PORT_STRAP0 = 0x3020349c # macro +cfgRCC_DEV0_PORT_STRAP1 = 0x302034a0 # macro +cfgRCC_DEV0_PORT_STRAP10 = 0x302034a4 # macro +cfgRCC_DEV0_PORT_STRAP11 = 0x302034a8 # macro +cfgRCC_DEV0_PORT_STRAP12 = 0x302034ac # macro +cfgRCC_DEV0_PORT_STRAP13 = 0x302034b0 # macro +cfgRCC_DEV0_PORT_STRAP14 = 0x302034b4 # macro +cfgRCC_DEV0_PORT_STRAP2 = 0x302034b8 # macro +cfgRCC_DEV0_PORT_STRAP3 = 0x302034bc # macro +cfgRCC_DEV0_PORT_STRAP4 = 0x302034c0 # macro +cfgRCC_DEV0_PORT_STRAP5 = 0x302034c4 # macro +cfgRCC_DEV0_PORT_STRAP6 = 0x302034c8 # macro +cfgRCC_DEV0_PORT_STRAP7 = 0x302034cc # macro +cfgRCC_DEV0_PORT_STRAP8 = 0x302034d0 # macro +cfgRCC_DEV0_PORT_STRAP9 = 0x302034d4 # macro +cfgRCC_DEV0_EPF0_STRAP0 = 0x302034d8 # macro +cfgRCC_DEV0_EPF0_STRAP1 = 0x302034dc # macro +cfgRCC_DEV0_EPF0_STRAP13 = 0x302034e0 # macro +cfgRCC_DEV0_EPF0_STRAP14 = 0x302034e4 # macro +cfgRCC_DEV0_EPF0_STRAP15 = 0x302034e8 # macro +cfgRCC_DEV0_EPF0_STRAP16 = 0x302034ec # macro +cfgRCC_DEV0_EPF0_STRAP17 = 0x302034f0 # macro +cfgRCC_DEV0_EPF0_STRAP18 = 0x302034f4 # macro +cfgRCC_DEV0_EPF0_STRAP2 = 0x302034f8 # macro +cfgRCC_DEV0_EPF0_STRAP26 = 0x302034fc # macro +cfgRCC_DEV0_EPF0_STRAP3 = 0x30203500 # macro +cfgRCC_DEV0_EPF0_STRAP4 = 0x30203504 # macro +cfgRCC_DEV0_EPF0_STRAP5 = 0x30203508 # macro +cfgRCC_DEV0_EPF0_STRAP8 = 0x3020350c # macro +cfgRCC_DEV0_EPF0_STRAP9 = 0x30203510 # macro +cfgRCC_DEV0_EPF1_STRAP0 = 0x30203514 # macro +cfgRCC_DEV0_EPF1_STRAP2 = 0x30203544 # macro +cfgRCC_DEV0_EPF1_STRAP20 = 0x30203548 # macro +cfgRCC_DEV0_EPF1_STRAP21 = 0x3020354c # macro +cfgRCC_DEV0_EPF1_STRAP22 = 0x30203550 # macro +cfgRCC_DEV0_EPF1_STRAP23 = 0x30203554 # macro +cfgRCC_DEV0_EPF1_STRAP24 = 0x30203558 # macro +cfgRCC_DEV0_EPF1_STRAP25 = 0x3020355c # macro +cfgRCC_DEV0_EPF1_STRAP3 = 0x30203560 # macro +cfgRCC_DEV0_EPF1_STRAP4 = 0x30203564 # macro +cfgRCC_DEV0_EPF1_STRAP5 = 0x30203568 # macro +cfgRCC_DEV0_EPF1_STRAP6 = 0x3020356c # macro +cfgRCC_DEV0_EPF1_STRAP7 = 0x30203570 # macro +cfgBIF_BX_PF_BIF_BME_STATUS = 0x3020382c # macro +cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG = 0x30203830 # macro +cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x3020384c # macro +cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x30203850 # macro +cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL = 0x30203854 # macro +cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL = 0x30203858 # macro +cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x3020385c # macro +cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x30203864 # macro +cfgBIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x30203868 # macro +cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ = 0x30203898 # macro +cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE = 0x3020389c # macro +cfgBIF_BX_PF_BIF_TRANS_PENDING = 0x302038a0 # macro +cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS = 0x302038c8 # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 = 0x30203958 # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 = 0x3020395c # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 = 0x30203960 # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 = 0x30203964 # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 = 0x30203968 # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 = 0x3020396c # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 = 0x30203970 # macro +cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 = 0x30203974 # macro +cfgBIF_BX_PF_MAILBOX_CONTROL = 0x30203978 # macro +cfgBIF_BX_PF_MAILBOX_INT_CNTL = 0x3020397c # macro +cfgBIF_BX_PF_BIF_VMHV_MAILBOX = 0x30203980 # macro +cfgRCC_DEV0_EPF0_RCC_ERR_LOG = 0x30203694 # macro +cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN = 0x30203780 # macro +cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE = 0x3020378c # macro +cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED = 0x30203790 # macro +cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER = 0x30203794 # macro +cfgSHUB_REGS_IF_CTL = 0x30203b8c # macro +cfgNGDC_MGCG_CTRL = 0x30203ba8 # macro +cfgNGDC_RESERVED_0 = 0x30203bac # macro +cfgNGDC_RESERVED_1 = 0x30203bb0 # macro +cfgATDMA_MISC_CNTL = 0x30203bf4 # macro +cfgS2A_MISC_CNTL = 0x30203bfc # macro +cfgNGDC_PG_MISC_CTRL = 0x30203c60 # macro +cfgNGDC_PGMST_CTRL = 0x30203c64 # macro +cfgNGDC_PGSLV_CTRL = 0x30203c68 # macro +cfgSUM_INDEX = 0x1000e0 # macro +cfgSUM_DATA = 0x1000e4 # macro +cfgSUM_INDEX_HI = 0x1000ec # macro +cfgSHADOW_COMMAND = 0xfffe30000004 # macro +cfgSHADOW_BASE_ADDR_1 = 0xfffe30000010 # macro +cfgSHADOW_BASE_ADDR_2 = 0xfffe30000014 # macro +cfgSHADOW_SUB_BUS_NUMBER_LATENCY = 0xfffe30000018 # macro +cfgSHADOW_IO_BASE_LIMIT = 0xfffe3000001c # macro +cfgSHADOW_MEM_BASE_LIMIT = 0xfffe30000020 # macro +cfgSHADOW_PREF_BASE_LIMIT = 0xfffe30000024 # macro +cfgSHADOW_PREF_BASE_UPPER = 0xfffe30000028 # macro +cfgSHADOW_PREF_LIMIT_UPPER = 0xfffe3000002c # macro +cfgSHADOW_IO_BASE_LIMIT_HI = 0xfffe30000030 # macro +cfgSUC_INDEX = 0xfffe300000e0 # macro +cfgSUC_DATA = 0xfffe300000e4 # macro +cfgBIF_BX_PF1_MM_INDEX = 0x0000 # macro +cfgBIF_BX_PF1_MM_DATA = 0x0004 # macro +cfgBIF_BX_PF1_MM_INDEX_HI = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID = 0xfffe10300000 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID = 0xfffe10300002 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND = 0xfffe10300004 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS = 0xfffe10300006 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID = 0xfffe10300008 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE = 0xfffe10300009 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS = 0xfffe1030000a # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS = 0xfffe1030000b # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE = 0xfffe1030000c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY = 0xfffe1030000d # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER = 0xfffe1030000e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST = 0xfffe1030000f # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 = 0xfffe10300010 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 = 0xfffe10300014 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 = 0xfffe10300018 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 = 0xfffe1030001c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 = 0xfffe10300020 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 = 0xfffe10300024 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR = 0xfffe10300028 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID = 0xfffe1030002c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR = 0xfffe10300030 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR = 0xfffe10300034 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE = 0xfffe1030003c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN = 0xfffe1030003d # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT = 0xfffe1030003e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY = 0xfffe1030003f # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST = 0xfffe10300064 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP = 0xfffe10300066 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP = 0xfffe10300068 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL = 0xfffe1030006c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS = 0xfffe1030006e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP = 0xfffe10300070 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL = 0xfffe10300074 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS = 0xfffe10300076 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 = 0xfffe10300088 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 = 0xfffe1030008c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 = 0xfffe1030008e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 = 0xfffe10300090 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 = 0xfffe10300094 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 = 0xfffe10300096 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST = 0xfffe103000a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL = 0xfffe103000a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO = 0xfffe103000a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI = 0xfffe103000a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA = 0xfffe103000a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA = 0xfffe103000aa # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK = 0xfffe103000ac # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 = 0xfffe103000ac # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64 = 0xfffe103000ae # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 = 0xfffe103000b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING = 0xfffe103000b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 = 0xfffe103000b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST = 0xfffe103000c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL = 0xfffe103000c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE = 0xfffe103000c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA = 0xfffe103000c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10300100 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10300104 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10300108 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030010c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10300150 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10300154 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK = 0xfffe10300158 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030015c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS = 0xfffe10300160 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK = 0xfffe10300164 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10300168 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 = 0xfffe1030016c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 = 0xfffe10300170 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 = 0xfffe10300174 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 = 0xfffe10300178 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10300188 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030018c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10300190 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10300194 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10300328 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP = 0xfffe1030032c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL = 0xfffe1030032e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID = 0xfffe10301000 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID = 0xfffe10301002 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND = 0xfffe10301004 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS = 0xfffe10301006 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID = 0xfffe10301008 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE = 0xfffe10301009 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS = 0xfffe1030100a # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS = 0xfffe1030100b # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE = 0xfffe1030100c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY = 0xfffe1030100d # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER = 0xfffe1030100e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST = 0xfffe1030100f # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 = 0xfffe10301010 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 = 0xfffe10301014 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 = 0xfffe10301018 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 = 0xfffe1030101c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 = 0xfffe10301020 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 = 0xfffe10301024 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR = 0xfffe10301028 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID = 0xfffe1030102c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR = 0xfffe10301030 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR = 0xfffe10301034 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE = 0xfffe1030103c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN = 0xfffe1030103d # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT = 0xfffe1030103e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY = 0xfffe1030103f # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST = 0xfffe10301064 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP = 0xfffe10301066 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP = 0xfffe10301068 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL = 0xfffe1030106c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS = 0xfffe1030106e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP = 0xfffe10301070 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL = 0xfffe10301074 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS = 0xfffe10301076 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 = 0xfffe10301088 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 = 0xfffe1030108c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 = 0xfffe1030108e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 = 0xfffe10301090 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 = 0xfffe10301094 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 = 0xfffe10301096 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST = 0xfffe103010a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL = 0xfffe103010a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO = 0xfffe103010a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI = 0xfffe103010a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA = 0xfffe103010a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA = 0xfffe103010aa # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK = 0xfffe103010ac # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 = 0xfffe103010ac # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64 = 0xfffe103010ae # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 = 0xfffe103010b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING = 0xfffe103010b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 = 0xfffe103010b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST = 0xfffe103010c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL = 0xfffe103010c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE = 0xfffe103010c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA = 0xfffe103010c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10301100 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10301104 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10301108 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030110c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10301150 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10301154 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK = 0xfffe10301158 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030115c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS = 0xfffe10301160 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK = 0xfffe10301164 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10301168 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 = 0xfffe1030116c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 = 0xfffe10301170 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 = 0xfffe10301174 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 = 0xfffe10301178 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10301188 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030118c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10301190 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10301194 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10301328 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP = 0xfffe1030132c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL = 0xfffe1030132e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID = 0xfffe10302000 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID = 0xfffe10302002 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND = 0xfffe10302004 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS = 0xfffe10302006 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID = 0xfffe10302008 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE = 0xfffe10302009 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS = 0xfffe1030200a # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS = 0xfffe1030200b # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE = 0xfffe1030200c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY = 0xfffe1030200d # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER = 0xfffe1030200e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST = 0xfffe1030200f # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 = 0xfffe10302010 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 = 0xfffe10302014 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 = 0xfffe10302018 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 = 0xfffe1030201c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 = 0xfffe10302020 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 = 0xfffe10302024 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR = 0xfffe10302028 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID = 0xfffe1030202c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR = 0xfffe10302030 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR = 0xfffe10302034 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE = 0xfffe1030203c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN = 0xfffe1030203d # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT = 0xfffe1030203e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY = 0xfffe1030203f # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST = 0xfffe10302064 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP = 0xfffe10302066 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP = 0xfffe10302068 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL = 0xfffe1030206c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS = 0xfffe1030206e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP = 0xfffe10302070 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL = 0xfffe10302074 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS = 0xfffe10302076 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 = 0xfffe10302088 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 = 0xfffe1030208c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 = 0xfffe1030208e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 = 0xfffe10302090 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 = 0xfffe10302094 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 = 0xfffe10302096 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST = 0xfffe103020a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL = 0xfffe103020a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO = 0xfffe103020a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI = 0xfffe103020a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA = 0xfffe103020a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA = 0xfffe103020aa # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK = 0xfffe103020ac # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 = 0xfffe103020ac # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64 = 0xfffe103020ae # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 = 0xfffe103020b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING = 0xfffe103020b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 = 0xfffe103020b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST = 0xfffe103020c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL = 0xfffe103020c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE = 0xfffe103020c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA = 0xfffe103020c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10302100 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10302104 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10302108 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030210c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10302150 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10302154 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK = 0xfffe10302158 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030215c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS = 0xfffe10302160 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK = 0xfffe10302164 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10302168 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 = 0xfffe1030216c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 = 0xfffe10302170 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 = 0xfffe10302174 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 = 0xfffe10302178 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10302188 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030218c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10302190 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10302194 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10302328 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP = 0xfffe1030232c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL = 0xfffe1030232e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID = 0xfffe10303000 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID = 0xfffe10303002 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND = 0xfffe10303004 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS = 0xfffe10303006 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID = 0xfffe10303008 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE = 0xfffe10303009 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS = 0xfffe1030300a # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS = 0xfffe1030300b # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE = 0xfffe1030300c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY = 0xfffe1030300d # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER = 0xfffe1030300e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST = 0xfffe1030300f # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 = 0xfffe10303010 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 = 0xfffe10303014 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 = 0xfffe10303018 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 = 0xfffe1030301c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 = 0xfffe10303020 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 = 0xfffe10303024 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR = 0xfffe10303028 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID = 0xfffe1030302c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR = 0xfffe10303030 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR = 0xfffe10303034 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE = 0xfffe1030303c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN = 0xfffe1030303d # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT = 0xfffe1030303e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY = 0xfffe1030303f # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST = 0xfffe10303064 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP = 0xfffe10303066 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP = 0xfffe10303068 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL = 0xfffe1030306c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS = 0xfffe1030306e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP = 0xfffe10303070 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL = 0xfffe10303074 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS = 0xfffe10303076 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 = 0xfffe10303088 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 = 0xfffe1030308c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 = 0xfffe1030308e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 = 0xfffe10303090 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 = 0xfffe10303094 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 = 0xfffe10303096 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST = 0xfffe103030a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL = 0xfffe103030a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO = 0xfffe103030a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI = 0xfffe103030a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA = 0xfffe103030a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA = 0xfffe103030aa # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK = 0xfffe103030ac # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 = 0xfffe103030ac # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64 = 0xfffe103030ae # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 = 0xfffe103030b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING = 0xfffe103030b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 = 0xfffe103030b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST = 0xfffe103030c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL = 0xfffe103030c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE = 0xfffe103030c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA = 0xfffe103030c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10303100 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10303104 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10303108 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030310c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10303150 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10303154 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK = 0xfffe10303158 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030315c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS = 0xfffe10303160 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK = 0xfffe10303164 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10303168 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 = 0xfffe1030316c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 = 0xfffe10303170 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 = 0xfffe10303174 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 = 0xfffe10303178 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10303188 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030318c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10303190 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10303194 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10303328 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP = 0xfffe1030332c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL = 0xfffe1030332e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID = 0xfffe10304000 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID = 0xfffe10304002 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND = 0xfffe10304004 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS = 0xfffe10304006 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID = 0xfffe10304008 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE = 0xfffe10304009 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS = 0xfffe1030400a # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS = 0xfffe1030400b # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE = 0xfffe1030400c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY = 0xfffe1030400d # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER = 0xfffe1030400e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST = 0xfffe1030400f # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 = 0xfffe10304010 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 = 0xfffe10304014 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 = 0xfffe10304018 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 = 0xfffe1030401c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 = 0xfffe10304020 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 = 0xfffe10304024 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR = 0xfffe10304028 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID = 0xfffe1030402c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR = 0xfffe10304030 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR = 0xfffe10304034 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE = 0xfffe1030403c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN = 0xfffe1030403d # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT = 0xfffe1030403e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY = 0xfffe1030403f # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST = 0xfffe10304064 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP = 0xfffe10304066 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP = 0xfffe10304068 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL = 0xfffe1030406c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS = 0xfffe1030406e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP = 0xfffe10304070 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL = 0xfffe10304074 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS = 0xfffe10304076 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 = 0xfffe10304088 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 = 0xfffe1030408c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 = 0xfffe1030408e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 = 0xfffe10304090 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 = 0xfffe10304094 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 = 0xfffe10304096 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST = 0xfffe103040a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL = 0xfffe103040a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO = 0xfffe103040a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI = 0xfffe103040a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA = 0xfffe103040a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA = 0xfffe103040aa # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK = 0xfffe103040ac # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 = 0xfffe103040ac # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64 = 0xfffe103040ae # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 = 0xfffe103040b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING = 0xfffe103040b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 = 0xfffe103040b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST = 0xfffe103040c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL = 0xfffe103040c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE = 0xfffe103040c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA = 0xfffe103040c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10304100 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10304104 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10304108 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030410c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10304150 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10304154 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK = 0xfffe10304158 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030415c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS = 0xfffe10304160 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK = 0xfffe10304164 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10304168 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 = 0xfffe1030416c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 = 0xfffe10304170 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 = 0xfffe10304174 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 = 0xfffe10304178 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10304188 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030418c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10304190 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10304194 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10304328 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP = 0xfffe1030432c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL = 0xfffe1030432e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID = 0xfffe10305000 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID = 0xfffe10305002 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND = 0xfffe10305004 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS = 0xfffe10305006 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID = 0xfffe10305008 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE = 0xfffe10305009 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS = 0xfffe1030500a # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS = 0xfffe1030500b # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE = 0xfffe1030500c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY = 0xfffe1030500d # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER = 0xfffe1030500e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST = 0xfffe1030500f # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 = 0xfffe10305010 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 = 0xfffe10305014 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 = 0xfffe10305018 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 = 0xfffe1030501c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 = 0xfffe10305020 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 = 0xfffe10305024 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR = 0xfffe10305028 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID = 0xfffe1030502c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR = 0xfffe10305030 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR = 0xfffe10305034 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE = 0xfffe1030503c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN = 0xfffe1030503d # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT = 0xfffe1030503e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY = 0xfffe1030503f # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST = 0xfffe10305064 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP = 0xfffe10305066 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP = 0xfffe10305068 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL = 0xfffe1030506c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS = 0xfffe1030506e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP = 0xfffe10305070 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL = 0xfffe10305074 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS = 0xfffe10305076 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 = 0xfffe10305088 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 = 0xfffe1030508c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 = 0xfffe1030508e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 = 0xfffe10305090 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 = 0xfffe10305094 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 = 0xfffe10305096 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST = 0xfffe103050a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL = 0xfffe103050a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO = 0xfffe103050a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI = 0xfffe103050a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA = 0xfffe103050a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA = 0xfffe103050aa # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK = 0xfffe103050ac # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 = 0xfffe103050ac # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64 = 0xfffe103050ae # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 = 0xfffe103050b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING = 0xfffe103050b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 = 0xfffe103050b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST = 0xfffe103050c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL = 0xfffe103050c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE = 0xfffe103050c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA = 0xfffe103050c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10305100 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10305104 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10305108 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030510c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10305150 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10305154 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK = 0xfffe10305158 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030515c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS = 0xfffe10305160 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK = 0xfffe10305164 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10305168 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 = 0xfffe1030516c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 = 0xfffe10305170 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 = 0xfffe10305174 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 = 0xfffe10305178 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10305188 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030518c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10305190 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10305194 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10305328 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP = 0xfffe1030532c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL = 0xfffe1030532e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID = 0xfffe10306000 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID = 0xfffe10306002 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND = 0xfffe10306004 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS = 0xfffe10306006 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID = 0xfffe10306008 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE = 0xfffe10306009 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS = 0xfffe1030600a # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS = 0xfffe1030600b # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE = 0xfffe1030600c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY = 0xfffe1030600d # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER = 0xfffe1030600e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST = 0xfffe1030600f # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 = 0xfffe10306010 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 = 0xfffe10306014 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 = 0xfffe10306018 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 = 0xfffe1030601c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 = 0xfffe10306020 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 = 0xfffe10306024 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR = 0xfffe10306028 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID = 0xfffe1030602c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR = 0xfffe10306030 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR = 0xfffe10306034 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE = 0xfffe1030603c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN = 0xfffe1030603d # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT = 0xfffe1030603e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY = 0xfffe1030603f # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST = 0xfffe10306064 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP = 0xfffe10306066 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP = 0xfffe10306068 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL = 0xfffe1030606c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS = 0xfffe1030606e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP = 0xfffe10306070 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL = 0xfffe10306074 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS = 0xfffe10306076 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 = 0xfffe10306088 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 = 0xfffe1030608c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 = 0xfffe1030608e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 = 0xfffe10306090 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 = 0xfffe10306094 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 = 0xfffe10306096 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST = 0xfffe103060a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL = 0xfffe103060a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO = 0xfffe103060a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI = 0xfffe103060a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA = 0xfffe103060a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA = 0xfffe103060aa # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK = 0xfffe103060ac # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 = 0xfffe103060ac # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64 = 0xfffe103060ae # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 = 0xfffe103060b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING = 0xfffe103060b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 = 0xfffe103060b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST = 0xfffe103060c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL = 0xfffe103060c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE = 0xfffe103060c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA = 0xfffe103060c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10306100 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10306104 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10306108 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030610c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10306150 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10306154 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK = 0xfffe10306158 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030615c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS = 0xfffe10306160 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK = 0xfffe10306164 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10306168 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 = 0xfffe1030616c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 = 0xfffe10306170 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 = 0xfffe10306174 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 = 0xfffe10306178 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10306188 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030618c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10306190 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10306194 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10306328 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP = 0xfffe1030632c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL = 0xfffe1030632e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID = 0xfffe10307000 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID = 0xfffe10307002 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND = 0xfffe10307004 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS = 0xfffe10307006 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID = 0xfffe10307008 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE = 0xfffe10307009 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS = 0xfffe1030700a # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS = 0xfffe1030700b # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE = 0xfffe1030700c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY = 0xfffe1030700d # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER = 0xfffe1030700e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST = 0xfffe1030700f # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 = 0xfffe10307010 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 = 0xfffe10307014 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 = 0xfffe10307018 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 = 0xfffe1030701c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 = 0xfffe10307020 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 = 0xfffe10307024 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR = 0xfffe10307028 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID = 0xfffe1030702c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR = 0xfffe10307030 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR = 0xfffe10307034 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE = 0xfffe1030703c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN = 0xfffe1030703d # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT = 0xfffe1030703e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY = 0xfffe1030703f # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST = 0xfffe10307064 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP = 0xfffe10307066 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP = 0xfffe10307068 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL = 0xfffe1030706c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS = 0xfffe1030706e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP = 0xfffe10307070 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL = 0xfffe10307074 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS = 0xfffe10307076 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 = 0xfffe10307088 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 = 0xfffe1030708c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 = 0xfffe1030708e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 = 0xfffe10307090 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 = 0xfffe10307094 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 = 0xfffe10307096 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST = 0xfffe103070a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL = 0xfffe103070a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO = 0xfffe103070a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI = 0xfffe103070a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA = 0xfffe103070a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA = 0xfffe103070aa # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK = 0xfffe103070ac # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 = 0xfffe103070ac # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64 = 0xfffe103070ae # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 = 0xfffe103070b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING = 0xfffe103070b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 = 0xfffe103070b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST = 0xfffe103070c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL = 0xfffe103070c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE = 0xfffe103070c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA = 0xfffe103070c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10307100 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10307104 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10307108 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030710c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10307150 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10307154 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK = 0xfffe10307158 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030715c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS = 0xfffe10307160 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK = 0xfffe10307164 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10307168 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 = 0xfffe1030716c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 = 0xfffe10307170 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 = 0xfffe10307174 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 = 0xfffe10307178 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10307188 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030718c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10307190 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10307194 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10307328 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP = 0xfffe1030732c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL = 0xfffe1030732e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID = 0xfffe10308000 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID = 0xfffe10308002 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND = 0xfffe10308004 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS = 0xfffe10308006 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID = 0xfffe10308008 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE = 0xfffe10308009 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS = 0xfffe1030800a # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS = 0xfffe1030800b # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE = 0xfffe1030800c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY = 0xfffe1030800d # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER = 0xfffe1030800e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST = 0xfffe1030800f # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 = 0xfffe10308010 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 = 0xfffe10308014 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 = 0xfffe10308018 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 = 0xfffe1030801c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 = 0xfffe10308020 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 = 0xfffe10308024 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR = 0xfffe10308028 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID = 0xfffe1030802c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR = 0xfffe10308030 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR = 0xfffe10308034 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE = 0xfffe1030803c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN = 0xfffe1030803d # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT = 0xfffe1030803e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY = 0xfffe1030803f # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST = 0xfffe10308064 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP = 0xfffe10308066 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP = 0xfffe10308068 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL = 0xfffe1030806c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS = 0xfffe1030806e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP = 0xfffe10308070 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL = 0xfffe10308074 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS = 0xfffe10308076 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 = 0xfffe10308088 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 = 0xfffe1030808c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 = 0xfffe1030808e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 = 0xfffe10308090 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 = 0xfffe10308094 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 = 0xfffe10308096 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST = 0xfffe103080a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL = 0xfffe103080a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO = 0xfffe103080a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI = 0xfffe103080a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA = 0xfffe103080a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA = 0xfffe103080aa # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK = 0xfffe103080ac # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 = 0xfffe103080ac # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64 = 0xfffe103080ae # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 = 0xfffe103080b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING = 0xfffe103080b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 = 0xfffe103080b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST = 0xfffe103080c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL = 0xfffe103080c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE = 0xfffe103080c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA = 0xfffe103080c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10308100 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10308104 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10308108 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030810c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10308150 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10308154 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK = 0xfffe10308158 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030815c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS = 0xfffe10308160 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK = 0xfffe10308164 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10308168 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 = 0xfffe1030816c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 = 0xfffe10308170 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 = 0xfffe10308174 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 = 0xfffe10308178 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10308188 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030818c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10308190 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10308194 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10308328 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP = 0xfffe1030832c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL = 0xfffe1030832e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID = 0xfffe10309000 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID = 0xfffe10309002 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND = 0xfffe10309004 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS = 0xfffe10309006 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID = 0xfffe10309008 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE = 0xfffe10309009 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS = 0xfffe1030900a # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS = 0xfffe1030900b # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE = 0xfffe1030900c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY = 0xfffe1030900d # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER = 0xfffe1030900e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST = 0xfffe1030900f # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 = 0xfffe10309010 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 = 0xfffe10309014 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 = 0xfffe10309018 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 = 0xfffe1030901c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 = 0xfffe10309020 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 = 0xfffe10309024 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR = 0xfffe10309028 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID = 0xfffe1030902c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR = 0xfffe10309030 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR = 0xfffe10309034 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE = 0xfffe1030903c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN = 0xfffe1030903d # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT = 0xfffe1030903e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY = 0xfffe1030903f # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST = 0xfffe10309064 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP = 0xfffe10309066 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP = 0xfffe10309068 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL = 0xfffe1030906c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS = 0xfffe1030906e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP = 0xfffe10309070 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL = 0xfffe10309074 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS = 0xfffe10309076 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 = 0xfffe10309088 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 = 0xfffe1030908c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 = 0xfffe1030908e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 = 0xfffe10309090 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 = 0xfffe10309094 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 = 0xfffe10309096 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST = 0xfffe103090a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL = 0xfffe103090a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO = 0xfffe103090a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI = 0xfffe103090a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA = 0xfffe103090a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA = 0xfffe103090aa # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK = 0xfffe103090ac # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 = 0xfffe103090ac # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64 = 0xfffe103090ae # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 = 0xfffe103090b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING = 0xfffe103090b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 = 0xfffe103090b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST = 0xfffe103090c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL = 0xfffe103090c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE = 0xfffe103090c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA = 0xfffe103090c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe10309100 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe10309104 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe10309108 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030910c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe10309150 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS = 0xfffe10309154 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK = 0xfffe10309158 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030915c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS = 0xfffe10309160 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK = 0xfffe10309164 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe10309168 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 = 0xfffe1030916c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 = 0xfffe10309170 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 = 0xfffe10309174 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 = 0xfffe10309178 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe10309188 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030918c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe10309190 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe10309194 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe10309328 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP = 0xfffe1030932c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL = 0xfffe1030932e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID = 0xfffe1030a000 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID = 0xfffe1030a002 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND = 0xfffe1030a004 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS = 0xfffe1030a006 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID = 0xfffe1030a008 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE = 0xfffe1030a009 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS = 0xfffe1030a00a # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS = 0xfffe1030a00b # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE = 0xfffe1030a00c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY = 0xfffe1030a00d # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER = 0xfffe1030a00e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST = 0xfffe1030a00f # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 = 0xfffe1030a010 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 = 0xfffe1030a014 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 = 0xfffe1030a018 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 = 0xfffe1030a01c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 = 0xfffe1030a020 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 = 0xfffe1030a024 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR = 0xfffe1030a028 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID = 0xfffe1030a02c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR = 0xfffe1030a030 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR = 0xfffe1030a034 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE = 0xfffe1030a03c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN = 0xfffe1030a03d # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT = 0xfffe1030a03e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY = 0xfffe1030a03f # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST = 0xfffe1030a064 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP = 0xfffe1030a066 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP = 0xfffe1030a068 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL = 0xfffe1030a06c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS = 0xfffe1030a06e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP = 0xfffe1030a070 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL = 0xfffe1030a074 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS = 0xfffe1030a076 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 = 0xfffe1030a088 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 = 0xfffe1030a08c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 = 0xfffe1030a08e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 = 0xfffe1030a090 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 = 0xfffe1030a094 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 = 0xfffe1030a096 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST = 0xfffe1030a0a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL = 0xfffe1030a0a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO = 0xfffe1030a0a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI = 0xfffe1030a0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA = 0xfffe1030a0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA = 0xfffe1030a0aa # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK = 0xfffe1030a0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 = 0xfffe1030a0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64 = 0xfffe1030a0ae # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 = 0xfffe1030a0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING = 0xfffe1030a0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 = 0xfffe1030a0b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST = 0xfffe1030a0c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL = 0xfffe1030a0c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE = 0xfffe1030a0c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA = 0xfffe1030a0c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe1030a100 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe1030a104 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe1030a108 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030a10c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe1030a150 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS = 0xfffe1030a154 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK = 0xfffe1030a158 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030a15c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS = 0xfffe1030a160 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK = 0xfffe1030a164 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe1030a168 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 = 0xfffe1030a16c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 = 0xfffe1030a170 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 = 0xfffe1030a174 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 = 0xfffe1030a178 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe1030a188 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030a18c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe1030a190 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe1030a194 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe1030a328 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP = 0xfffe1030a32c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL = 0xfffe1030a32e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID = 0xfffe1030b000 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID = 0xfffe1030b002 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND = 0xfffe1030b004 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS = 0xfffe1030b006 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID = 0xfffe1030b008 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE = 0xfffe1030b009 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS = 0xfffe1030b00a # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS = 0xfffe1030b00b # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE = 0xfffe1030b00c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY = 0xfffe1030b00d # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER = 0xfffe1030b00e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST = 0xfffe1030b00f # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 = 0xfffe1030b010 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 = 0xfffe1030b014 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 = 0xfffe1030b018 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 = 0xfffe1030b01c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 = 0xfffe1030b020 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 = 0xfffe1030b024 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR = 0xfffe1030b028 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID = 0xfffe1030b02c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR = 0xfffe1030b030 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR = 0xfffe1030b034 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE = 0xfffe1030b03c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN = 0xfffe1030b03d # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT = 0xfffe1030b03e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY = 0xfffe1030b03f # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST = 0xfffe1030b064 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP = 0xfffe1030b066 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP = 0xfffe1030b068 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL = 0xfffe1030b06c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS = 0xfffe1030b06e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP = 0xfffe1030b070 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL = 0xfffe1030b074 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS = 0xfffe1030b076 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 = 0xfffe1030b088 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 = 0xfffe1030b08c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 = 0xfffe1030b08e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 = 0xfffe1030b090 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 = 0xfffe1030b094 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 = 0xfffe1030b096 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST = 0xfffe1030b0a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL = 0xfffe1030b0a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO = 0xfffe1030b0a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI = 0xfffe1030b0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA = 0xfffe1030b0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA = 0xfffe1030b0aa # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK = 0xfffe1030b0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 = 0xfffe1030b0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64 = 0xfffe1030b0ae # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 = 0xfffe1030b0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING = 0xfffe1030b0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 = 0xfffe1030b0b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST = 0xfffe1030b0c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL = 0xfffe1030b0c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE = 0xfffe1030b0c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA = 0xfffe1030b0c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe1030b100 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe1030b104 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe1030b108 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030b10c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe1030b150 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS = 0xfffe1030b154 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK = 0xfffe1030b158 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030b15c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS = 0xfffe1030b160 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK = 0xfffe1030b164 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe1030b168 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 = 0xfffe1030b16c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 = 0xfffe1030b170 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 = 0xfffe1030b174 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 = 0xfffe1030b178 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe1030b188 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030b18c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe1030b190 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe1030b194 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe1030b328 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP = 0xfffe1030b32c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL = 0xfffe1030b32e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID = 0xfffe1030c000 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID = 0xfffe1030c002 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND = 0xfffe1030c004 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS = 0xfffe1030c006 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID = 0xfffe1030c008 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE = 0xfffe1030c009 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS = 0xfffe1030c00a # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS = 0xfffe1030c00b # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE = 0xfffe1030c00c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY = 0xfffe1030c00d # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER = 0xfffe1030c00e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST = 0xfffe1030c00f # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 = 0xfffe1030c010 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 = 0xfffe1030c014 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 = 0xfffe1030c018 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 = 0xfffe1030c01c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 = 0xfffe1030c020 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 = 0xfffe1030c024 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR = 0xfffe1030c028 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID = 0xfffe1030c02c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR = 0xfffe1030c030 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR = 0xfffe1030c034 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE = 0xfffe1030c03c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN = 0xfffe1030c03d # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT = 0xfffe1030c03e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY = 0xfffe1030c03f # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST = 0xfffe1030c064 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP = 0xfffe1030c066 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP = 0xfffe1030c068 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL = 0xfffe1030c06c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS = 0xfffe1030c06e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP = 0xfffe1030c070 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL = 0xfffe1030c074 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS = 0xfffe1030c076 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 = 0xfffe1030c088 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 = 0xfffe1030c08c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 = 0xfffe1030c08e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 = 0xfffe1030c090 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 = 0xfffe1030c094 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 = 0xfffe1030c096 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST = 0xfffe1030c0a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL = 0xfffe1030c0a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO = 0xfffe1030c0a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI = 0xfffe1030c0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA = 0xfffe1030c0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA = 0xfffe1030c0aa # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK = 0xfffe1030c0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 = 0xfffe1030c0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64 = 0xfffe1030c0ae # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 = 0xfffe1030c0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING = 0xfffe1030c0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 = 0xfffe1030c0b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST = 0xfffe1030c0c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL = 0xfffe1030c0c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE = 0xfffe1030c0c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA = 0xfffe1030c0c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe1030c100 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe1030c104 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe1030c108 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030c10c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe1030c150 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS = 0xfffe1030c154 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK = 0xfffe1030c158 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030c15c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS = 0xfffe1030c160 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK = 0xfffe1030c164 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe1030c168 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 = 0xfffe1030c16c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 = 0xfffe1030c170 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 = 0xfffe1030c174 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 = 0xfffe1030c178 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe1030c188 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030c18c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe1030c190 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe1030c194 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe1030c328 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP = 0xfffe1030c32c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL = 0xfffe1030c32e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID = 0xfffe1030d000 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID = 0xfffe1030d002 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND = 0xfffe1030d004 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS = 0xfffe1030d006 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID = 0xfffe1030d008 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE = 0xfffe1030d009 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS = 0xfffe1030d00a # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS = 0xfffe1030d00b # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE = 0xfffe1030d00c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY = 0xfffe1030d00d # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER = 0xfffe1030d00e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST = 0xfffe1030d00f # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 = 0xfffe1030d010 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 = 0xfffe1030d014 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 = 0xfffe1030d018 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 = 0xfffe1030d01c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 = 0xfffe1030d020 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 = 0xfffe1030d024 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR = 0xfffe1030d028 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID = 0xfffe1030d02c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR = 0xfffe1030d030 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR = 0xfffe1030d034 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE = 0xfffe1030d03c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN = 0xfffe1030d03d # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT = 0xfffe1030d03e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY = 0xfffe1030d03f # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST = 0xfffe1030d064 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP = 0xfffe1030d066 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP = 0xfffe1030d068 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL = 0xfffe1030d06c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS = 0xfffe1030d06e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP = 0xfffe1030d070 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL = 0xfffe1030d074 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS = 0xfffe1030d076 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 = 0xfffe1030d088 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 = 0xfffe1030d08c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 = 0xfffe1030d08e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 = 0xfffe1030d090 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 = 0xfffe1030d094 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 = 0xfffe1030d096 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST = 0xfffe1030d0a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL = 0xfffe1030d0a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO = 0xfffe1030d0a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI = 0xfffe1030d0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA = 0xfffe1030d0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA = 0xfffe1030d0aa # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK = 0xfffe1030d0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 = 0xfffe1030d0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64 = 0xfffe1030d0ae # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 = 0xfffe1030d0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING = 0xfffe1030d0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 = 0xfffe1030d0b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST = 0xfffe1030d0c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL = 0xfffe1030d0c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE = 0xfffe1030d0c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA = 0xfffe1030d0c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe1030d100 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe1030d104 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe1030d108 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030d10c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe1030d150 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS = 0xfffe1030d154 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK = 0xfffe1030d158 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030d15c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS = 0xfffe1030d160 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK = 0xfffe1030d164 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe1030d168 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 = 0xfffe1030d16c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 = 0xfffe1030d170 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 = 0xfffe1030d174 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 = 0xfffe1030d178 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe1030d188 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030d18c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe1030d190 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe1030d194 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe1030d328 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP = 0xfffe1030d32c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL = 0xfffe1030d32e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID = 0xfffe1030e000 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID = 0xfffe1030e002 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND = 0xfffe1030e004 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS = 0xfffe1030e006 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID = 0xfffe1030e008 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE = 0xfffe1030e009 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS = 0xfffe1030e00a # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS = 0xfffe1030e00b # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE = 0xfffe1030e00c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY = 0xfffe1030e00d # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER = 0xfffe1030e00e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST = 0xfffe1030e00f # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 = 0xfffe1030e010 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 = 0xfffe1030e014 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 = 0xfffe1030e018 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 = 0xfffe1030e01c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 = 0xfffe1030e020 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 = 0xfffe1030e024 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR = 0xfffe1030e028 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID = 0xfffe1030e02c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR = 0xfffe1030e030 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR = 0xfffe1030e034 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE = 0xfffe1030e03c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN = 0xfffe1030e03d # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT = 0xfffe1030e03e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY = 0xfffe1030e03f # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST = 0xfffe1030e064 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP = 0xfffe1030e066 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP = 0xfffe1030e068 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL = 0xfffe1030e06c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS = 0xfffe1030e06e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP = 0xfffe1030e070 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL = 0xfffe1030e074 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS = 0xfffe1030e076 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 = 0xfffe1030e088 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 = 0xfffe1030e08c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 = 0xfffe1030e08e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 = 0xfffe1030e090 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 = 0xfffe1030e094 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 = 0xfffe1030e096 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST = 0xfffe1030e0a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL = 0xfffe1030e0a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO = 0xfffe1030e0a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI = 0xfffe1030e0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA = 0xfffe1030e0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA = 0xfffe1030e0aa # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK = 0xfffe1030e0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 = 0xfffe1030e0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64 = 0xfffe1030e0ae # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 = 0xfffe1030e0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING = 0xfffe1030e0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 = 0xfffe1030e0b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST = 0xfffe1030e0c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL = 0xfffe1030e0c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE = 0xfffe1030e0c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA = 0xfffe1030e0c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe1030e100 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe1030e104 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe1030e108 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030e10c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe1030e150 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS = 0xfffe1030e154 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK = 0xfffe1030e158 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030e15c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS = 0xfffe1030e160 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK = 0xfffe1030e164 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe1030e168 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 = 0xfffe1030e16c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 = 0xfffe1030e170 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 = 0xfffe1030e174 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 = 0xfffe1030e178 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe1030e188 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030e18c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe1030e190 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe1030e194 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe1030e328 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP = 0xfffe1030e32c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL = 0xfffe1030e32e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID = 0xfffe1030f000 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID = 0xfffe1030f002 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND = 0xfffe1030f004 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS = 0xfffe1030f006 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID = 0xfffe1030f008 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE = 0xfffe1030f009 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS = 0xfffe1030f00a # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS = 0xfffe1030f00b # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE = 0xfffe1030f00c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY = 0xfffe1030f00d # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER = 0xfffe1030f00e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST = 0xfffe1030f00f # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 = 0xfffe1030f010 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 = 0xfffe1030f014 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 = 0xfffe1030f018 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 = 0xfffe1030f01c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 = 0xfffe1030f020 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 = 0xfffe1030f024 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR = 0xfffe1030f028 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID = 0xfffe1030f02c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR = 0xfffe1030f030 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR = 0xfffe1030f034 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE = 0xfffe1030f03c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN = 0xfffe1030f03d # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT = 0xfffe1030f03e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY = 0xfffe1030f03f # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST = 0xfffe1030f064 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP = 0xfffe1030f066 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP = 0xfffe1030f068 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL = 0xfffe1030f06c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS = 0xfffe1030f06e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP = 0xfffe1030f070 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL = 0xfffe1030f074 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS = 0xfffe1030f076 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 = 0xfffe1030f088 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 = 0xfffe1030f08c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 = 0xfffe1030f08e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 = 0xfffe1030f090 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 = 0xfffe1030f094 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 = 0xfffe1030f096 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST = 0xfffe1030f0a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL = 0xfffe1030f0a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO = 0xfffe1030f0a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI = 0xfffe1030f0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA = 0xfffe1030f0a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA = 0xfffe1030f0aa # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK = 0xfffe1030f0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 = 0xfffe1030f0ac # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64 = 0xfffe1030f0ae # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 = 0xfffe1030f0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING = 0xfffe1030f0b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 = 0xfffe1030f0b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST = 0xfffe1030f0c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL = 0xfffe1030f0c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE = 0xfffe1030f0c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA = 0xfffe1030f0c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0xfffe1030f100 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR = 0xfffe1030f104 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 = 0xfffe1030f108 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 = 0xfffe1030f10c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0xfffe1030f150 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS = 0xfffe1030f154 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK = 0xfffe1030f158 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY = 0xfffe1030f15c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS = 0xfffe1030f160 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK = 0xfffe1030f164 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL = 0xfffe1030f168 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 = 0xfffe1030f16c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 = 0xfffe1030f170 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 = 0xfffe1030f174 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 = 0xfffe1030f178 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 = 0xfffe1030f188 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 = 0xfffe1030f18c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 = 0xfffe1030f190 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 = 0xfffe1030f194 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST = 0xfffe1030f328 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP = 0xfffe1030f32c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL = 0xfffe1030f32e # macro +cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS = 0xd000382c # macro +cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG = 0xd0003830 # macro +cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd000384c # macro +cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0003850 # macro +cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0003854 # macro +cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0003858 # macro +cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd000385c # macro +cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0003864 # macro +cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0003868 # macro +cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ = 0xd0003898 # macro +cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE = 0xd000389c # macro +cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING = 0xd00038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS = 0xd00038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 = 0xd0003958 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 = 0xd000395c # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 = 0xd0003960 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 = 0xd0003964 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 = 0xd0003968 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 = 0xd000396c # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 = 0xd0003970 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 = 0xd0003974 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL = 0xd0003978 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL = 0xd000397c # macro +cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX = 0xd0003980 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX = 0xd0000000 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA = 0xd0000004 # macro +cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI = 0xd0000018 # macro +cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG = 0xd0003694 # macro +cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN = 0xd0003780 # macro +cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE = 0xd000378c # macro +cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED = 0xd0003790 # macro +cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER = 0xd0003794 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO = 0xd0042000 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI = 0xd0042004 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA = 0xd0042008 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL = 0xd004200c # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO = 0xd0042010 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI = 0xd0042014 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA = 0xd0042018 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL = 0xd004201c # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO = 0xd0042020 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI = 0xd0042024 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA = 0xd0042028 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL = 0xd004202c # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO = 0xd0042030 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI = 0xd0042034 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA = 0xd0042038 # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL = 0xd004203c # macro +cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA = 0xd0043000 # macro +cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS = 0xd008382c # macro +cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG = 0xd0083830 # macro +cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd008384c # macro +cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0083850 # macro +cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0083854 # macro +cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0083858 # macro +cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd008385c # macro +cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0083864 # macro +cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0083868 # macro +cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ = 0xd0083898 # macro +cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE = 0xd008389c # macro +cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING = 0xd00838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS = 0xd00838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 = 0xd0083958 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 = 0xd008395c # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 = 0xd0083960 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 = 0xd0083964 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 = 0xd0083968 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 = 0xd008396c # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 = 0xd0083970 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 = 0xd0083974 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL = 0xd0083978 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL = 0xd008397c # macro +cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX = 0xd0083980 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX = 0xd0080000 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA = 0xd0080004 # macro +cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI = 0xd0080018 # macro +cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG = 0xd0083694 # macro +cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN = 0xd0083780 # macro +cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE = 0xd008378c # macro +cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED = 0xd0083790 # macro +cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER = 0xd0083794 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO = 0xd00c2000 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI = 0xd00c2004 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA = 0xd00c2008 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL = 0xd00c200c # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO = 0xd00c2010 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI = 0xd00c2014 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA = 0xd00c2018 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL = 0xd00c201c # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO = 0xd00c2020 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI = 0xd00c2024 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA = 0xd00c2028 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL = 0xd00c202c # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO = 0xd00c2030 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI = 0xd00c2034 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA = 0xd00c2038 # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL = 0xd00c203c # macro +cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA = 0xd00c3000 # macro +cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS = 0xd010382c # macro +cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG = 0xd0103830 # macro +cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd010384c # macro +cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0103850 # macro +cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0103854 # macro +cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0103858 # macro +cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd010385c # macro +cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0103864 # macro +cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0103868 # macro +cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ = 0xd0103898 # macro +cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE = 0xd010389c # macro +cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING = 0xd01038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS = 0xd01038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 = 0xd0103958 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 = 0xd010395c # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 = 0xd0103960 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 = 0xd0103964 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 = 0xd0103968 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 = 0xd010396c # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 = 0xd0103970 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 = 0xd0103974 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL = 0xd0103978 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL = 0xd010397c # macro +cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX = 0xd0103980 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX = 0xd0100000 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA = 0xd0100004 # macro +cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI = 0xd0100018 # macro +cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG = 0xd0103694 # macro +cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN = 0xd0103780 # macro +cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE = 0xd010378c # macro +cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED = 0xd0103790 # macro +cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER = 0xd0103794 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO = 0xd0142000 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI = 0xd0142004 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA = 0xd0142008 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL = 0xd014200c # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO = 0xd0142010 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI = 0xd0142014 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA = 0xd0142018 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL = 0xd014201c # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO = 0xd0142020 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI = 0xd0142024 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA = 0xd0142028 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL = 0xd014202c # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO = 0xd0142030 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI = 0xd0142034 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA = 0xd0142038 # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL = 0xd014203c # macro +cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA = 0xd0143000 # macro +cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS = 0xd018382c # macro +cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG = 0xd0183830 # macro +cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd018384c # macro +cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0183850 # macro +cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0183854 # macro +cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0183858 # macro +cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd018385c # macro +cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0183864 # macro +cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0183868 # macro +cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ = 0xd0183898 # macro +cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE = 0xd018389c # macro +cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING = 0xd01838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS = 0xd01838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 = 0xd0183958 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 = 0xd018395c # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 = 0xd0183960 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 = 0xd0183964 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 = 0xd0183968 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 = 0xd018396c # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 = 0xd0183970 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 = 0xd0183974 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL = 0xd0183978 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL = 0xd018397c # macro +cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX = 0xd0183980 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX = 0xd0180000 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA = 0xd0180004 # macro +cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI = 0xd0180018 # macro +cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG = 0xd0183694 # macro +cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN = 0xd0183780 # macro +cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE = 0xd018378c # macro +cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED = 0xd0183790 # macro +cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER = 0xd0183794 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO = 0xd01c2000 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI = 0xd01c2004 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA = 0xd01c2008 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL = 0xd01c200c # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO = 0xd01c2010 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI = 0xd01c2014 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA = 0xd01c2018 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL = 0xd01c201c # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO = 0xd01c2020 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI = 0xd01c2024 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA = 0xd01c2028 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL = 0xd01c202c # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO = 0xd01c2030 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI = 0xd01c2034 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA = 0xd01c2038 # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL = 0xd01c203c # macro +cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA = 0xd01c3000 # macro +cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS = 0xd020382c # macro +cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG = 0xd0203830 # macro +cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd020384c # macro +cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0203850 # macro +cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0203854 # macro +cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0203858 # macro +cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd020385c # macro +cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0203864 # macro +cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0203868 # macro +cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ = 0xd0203898 # macro +cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE = 0xd020389c # macro +cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING = 0xd02038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS = 0xd02038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 = 0xd0203958 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 = 0xd020395c # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 = 0xd0203960 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 = 0xd0203964 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 = 0xd0203968 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 = 0xd020396c # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 = 0xd0203970 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 = 0xd0203974 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL = 0xd0203978 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL = 0xd020397c # macro +cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX = 0xd0203980 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX = 0xd0200000 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA = 0xd0200004 # macro +cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI = 0xd0200018 # macro +cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG = 0xd0203694 # macro +cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN = 0xd0203780 # macro +cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE = 0xd020378c # macro +cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED = 0xd0203790 # macro +cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER = 0xd0203794 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO = 0xd0242000 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI = 0xd0242004 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA = 0xd0242008 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL = 0xd024200c # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO = 0xd0242010 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI = 0xd0242014 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA = 0xd0242018 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL = 0xd024201c # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO = 0xd0242020 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI = 0xd0242024 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA = 0xd0242028 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL = 0xd024202c # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO = 0xd0242030 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI = 0xd0242034 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA = 0xd0242038 # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL = 0xd024203c # macro +cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA = 0xd0243000 # macro +cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS = 0xd028382c # macro +cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG = 0xd0283830 # macro +cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd028384c # macro +cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0283850 # macro +cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0283854 # macro +cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0283858 # macro +cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd028385c # macro +cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0283864 # macro +cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0283868 # macro +cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ = 0xd0283898 # macro +cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE = 0xd028389c # macro +cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING = 0xd02838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS = 0xd02838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 = 0xd0283958 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 = 0xd028395c # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 = 0xd0283960 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 = 0xd0283964 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 = 0xd0283968 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 = 0xd028396c # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 = 0xd0283970 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 = 0xd0283974 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL = 0xd0283978 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL = 0xd028397c # macro +cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX = 0xd0283980 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX = 0xd0280000 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA = 0xd0280004 # macro +cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI = 0xd0280018 # macro +cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG = 0xd0283694 # macro +cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN = 0xd0283780 # macro +cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE = 0xd028378c # macro +cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED = 0xd0283790 # macro +cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER = 0xd0283794 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO = 0xd02c2000 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI = 0xd02c2004 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA = 0xd02c2008 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL = 0xd02c200c # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO = 0xd02c2010 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI = 0xd02c2014 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA = 0xd02c2018 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL = 0xd02c201c # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO = 0xd02c2020 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI = 0xd02c2024 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA = 0xd02c2028 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL = 0xd02c202c # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO = 0xd02c2030 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI = 0xd02c2034 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA = 0xd02c2038 # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL = 0xd02c203c # macro +cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA = 0xd02c3000 # macro +cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS = 0xd030382c # macro +cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG = 0xd0303830 # macro +cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd030384c # macro +cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0303850 # macro +cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0303854 # macro +cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0303858 # macro +cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd030385c # macro +cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0303864 # macro +cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0303868 # macro +cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ = 0xd0303898 # macro +cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE = 0xd030389c # macro +cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING = 0xd03038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS = 0xd03038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 = 0xd0303958 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 = 0xd030395c # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 = 0xd0303960 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 = 0xd0303964 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 = 0xd0303968 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 = 0xd030396c # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 = 0xd0303970 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 = 0xd0303974 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL = 0xd0303978 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL = 0xd030397c # macro +cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX = 0xd0303980 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX = 0xd0300000 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA = 0xd0300004 # macro +cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI = 0xd0300018 # macro +cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG = 0xd0303694 # macro +cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN = 0xd0303780 # macro +cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE = 0xd030378c # macro +cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED = 0xd0303790 # macro +cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER = 0xd0303794 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO = 0xd0342000 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI = 0xd0342004 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA = 0xd0342008 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL = 0xd034200c # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO = 0xd0342010 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI = 0xd0342014 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA = 0xd0342018 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL = 0xd034201c # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO = 0xd0342020 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI = 0xd0342024 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA = 0xd0342028 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL = 0xd034202c # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO = 0xd0342030 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI = 0xd0342034 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA = 0xd0342038 # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL = 0xd034203c # macro +cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA = 0xd0343000 # macro +cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS = 0xd038382c # macro +cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG = 0xd0383830 # macro +cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd038384c # macro +cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0383850 # macro +cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0383854 # macro +cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0383858 # macro +cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd038385c # macro +cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0383864 # macro +cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0383868 # macro +cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ = 0xd0383898 # macro +cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE = 0xd038389c # macro +cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING = 0xd03838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS = 0xd03838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 = 0xd0383958 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 = 0xd038395c # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 = 0xd0383960 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 = 0xd0383964 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 = 0xd0383968 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 = 0xd038396c # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 = 0xd0383970 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 = 0xd0383974 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL = 0xd0383978 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL = 0xd038397c # macro +cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX = 0xd0383980 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX = 0xd0380000 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA = 0xd0380004 # macro +cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI = 0xd0380018 # macro +cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG = 0xd0383694 # macro +cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN = 0xd0383780 # macro +cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE = 0xd038378c # macro +cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED = 0xd0383790 # macro +cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER = 0xd0383794 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO = 0xd03c2000 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI = 0xd03c2004 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA = 0xd03c2008 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL = 0xd03c200c # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO = 0xd03c2010 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI = 0xd03c2014 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA = 0xd03c2018 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL = 0xd03c201c # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO = 0xd03c2020 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI = 0xd03c2024 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA = 0xd03c2028 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL = 0xd03c202c # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO = 0xd03c2030 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI = 0xd03c2034 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA = 0xd03c2038 # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL = 0xd03c203c # macro +cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA = 0xd03c3000 # macro +cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS = 0xd040382c # macro +cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG = 0xd0403830 # macro +cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd040384c # macro +cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0403850 # macro +cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0403854 # macro +cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0403858 # macro +cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd040385c # macro +cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0403864 # macro +cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0403868 # macro +cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ = 0xd0403898 # macro +cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE = 0xd040389c # macro +cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING = 0xd04038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS = 0xd04038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 = 0xd0403958 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 = 0xd040395c # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 = 0xd0403960 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 = 0xd0403964 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 = 0xd0403968 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 = 0xd040396c # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 = 0xd0403970 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 = 0xd0403974 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL = 0xd0403978 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL = 0xd040397c # macro +cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX = 0xd0403980 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX = 0xd0400000 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA = 0xd0400004 # macro +cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI = 0xd0400018 # macro +cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG = 0xd0403694 # macro +cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN = 0xd0403780 # macro +cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE = 0xd040378c # macro +cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED = 0xd0403790 # macro +cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER = 0xd0403794 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO = 0xd0442000 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI = 0xd0442004 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA = 0xd0442008 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL = 0xd044200c # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO = 0xd0442010 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI = 0xd0442014 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA = 0xd0442018 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL = 0xd044201c # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO = 0xd0442020 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI = 0xd0442024 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA = 0xd0442028 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL = 0xd044202c # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO = 0xd0442030 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI = 0xd0442034 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA = 0xd0442038 # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL = 0xd044203c # macro +cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA = 0xd0443000 # macro +cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS = 0xd048382c # macro +cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG = 0xd0483830 # macro +cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd048384c # macro +cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0483850 # macro +cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0483854 # macro +cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0483858 # macro +cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd048385c # macro +cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0483864 # macro +cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0483868 # macro +cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ = 0xd0483898 # macro +cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE = 0xd048389c # macro +cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING = 0xd04838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS = 0xd04838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 = 0xd0483958 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 = 0xd048395c # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 = 0xd0483960 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 = 0xd0483964 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 = 0xd0483968 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 = 0xd048396c # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 = 0xd0483970 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 = 0xd0483974 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL = 0xd0483978 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL = 0xd048397c # macro +cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX = 0xd0483980 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX = 0xd0480000 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA = 0xd0480004 # macro +cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI = 0xd0480018 # macro +cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG = 0xd0483694 # macro +cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN = 0xd0483780 # macro +cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE = 0xd048378c # macro +cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED = 0xd0483790 # macro +cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER = 0xd0483794 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO = 0xd04c2000 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI = 0xd04c2004 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA = 0xd04c2008 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL = 0xd04c200c # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO = 0xd04c2010 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI = 0xd04c2014 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA = 0xd04c2018 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL = 0xd04c201c # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO = 0xd04c2020 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI = 0xd04c2024 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA = 0xd04c2028 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL = 0xd04c202c # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO = 0xd04c2030 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI = 0xd04c2034 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA = 0xd04c2038 # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL = 0xd04c203c # macro +cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA = 0xd04c3000 # macro +cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS = 0xd050382c # macro +cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG = 0xd0503830 # macro +cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd050384c # macro +cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0503850 # macro +cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0503854 # macro +cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0503858 # macro +cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd050385c # macro +cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0503864 # macro +cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0503868 # macro +cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ = 0xd0503898 # macro +cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE = 0xd050389c # macro +cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING = 0xd05038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS = 0xd05038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 = 0xd0503958 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 = 0xd050395c # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 = 0xd0503960 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 = 0xd0503964 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 = 0xd0503968 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 = 0xd050396c # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 = 0xd0503970 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 = 0xd0503974 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL = 0xd0503978 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL = 0xd050397c # macro +cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX = 0xd0503980 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX = 0xd0500000 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA = 0xd0500004 # macro +cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI = 0xd0500018 # macro +cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG = 0xd0503694 # macro +cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN = 0xd0503780 # macro +cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE = 0xd050378c # macro +cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED = 0xd0503790 # macro +cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER = 0xd0503794 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO = 0xd0542000 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI = 0xd0542004 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA = 0xd0542008 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL = 0xd054200c # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO = 0xd0542010 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI = 0xd0542014 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA = 0xd0542018 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL = 0xd054201c # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO = 0xd0542020 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI = 0xd0542024 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA = 0xd0542028 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL = 0xd054202c # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO = 0xd0542030 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI = 0xd0542034 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA = 0xd0542038 # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL = 0xd054203c # macro +cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA = 0xd0543000 # macro +cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS = 0xd058382c # macro +cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG = 0xd0583830 # macro +cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd058384c # macro +cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0583850 # macro +cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0583854 # macro +cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0583858 # macro +cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd058385c # macro +cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0583864 # macro +cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0583868 # macro +cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ = 0xd0583898 # macro +cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE = 0xd058389c # macro +cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING = 0xd05838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS = 0xd05838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 = 0xd0583958 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 = 0xd058395c # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 = 0xd0583960 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 = 0xd0583964 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 = 0xd0583968 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 = 0xd058396c # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 = 0xd0583970 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 = 0xd0583974 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL = 0xd0583978 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL = 0xd058397c # macro +cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX = 0xd0583980 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX = 0xd0580000 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA = 0xd0580004 # macro +cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI = 0xd0580018 # macro +cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG = 0xd0583694 # macro +cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN = 0xd0583780 # macro +cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE = 0xd058378c # macro +cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED = 0xd0583790 # macro +cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER = 0xd0583794 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO = 0xd05c2000 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI = 0xd05c2004 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA = 0xd05c2008 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL = 0xd05c200c # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO = 0xd05c2010 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI = 0xd05c2014 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA = 0xd05c2018 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL = 0xd05c201c # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO = 0xd05c2020 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI = 0xd05c2024 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA = 0xd05c2028 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL = 0xd05c202c # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO = 0xd05c2030 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI = 0xd05c2034 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA = 0xd05c2038 # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL = 0xd05c203c # macro +cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA = 0xd05c3000 # macro +cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS = 0xd060382c # macro +cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG = 0xd0603830 # macro +cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd060384c # macro +cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0603850 # macro +cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0603854 # macro +cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0603858 # macro +cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd060385c # macro +cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0603864 # macro +cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0603868 # macro +cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ = 0xd0603898 # macro +cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE = 0xd060389c # macro +cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING = 0xd06038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS = 0xd06038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 = 0xd0603958 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 = 0xd060395c # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 = 0xd0603960 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 = 0xd0603964 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 = 0xd0603968 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 = 0xd060396c # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 = 0xd0603970 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 = 0xd0603974 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL = 0xd0603978 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL = 0xd060397c # macro +cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX = 0xd0603980 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX = 0xd0600000 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA = 0xd0600004 # macro +cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI = 0xd0600018 # macro +cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG = 0xd0603694 # macro +cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN = 0xd0603780 # macro +cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE = 0xd060378c # macro +cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED = 0xd0603790 # macro +cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER = 0xd0603794 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO = 0xd0642000 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI = 0xd0642004 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA = 0xd0642008 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL = 0xd064200c # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO = 0xd0642010 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI = 0xd0642014 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA = 0xd0642018 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL = 0xd064201c # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO = 0xd0642020 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI = 0xd0642024 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA = 0xd0642028 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL = 0xd064202c # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO = 0xd0642030 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI = 0xd0642034 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA = 0xd0642038 # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL = 0xd064203c # macro +cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA = 0xd0643000 # macro +cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS = 0xd068382c # macro +cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG = 0xd0683830 # macro +cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd068384c # macro +cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0683850 # macro +cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0683854 # macro +cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0683858 # macro +cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd068385c # macro +cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0683864 # macro +cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0683868 # macro +cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ = 0xd0683898 # macro +cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE = 0xd068389c # macro +cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING = 0xd06838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS = 0xd06838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 = 0xd0683958 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 = 0xd068395c # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 = 0xd0683960 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 = 0xd0683964 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 = 0xd0683968 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 = 0xd068396c # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 = 0xd0683970 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 = 0xd0683974 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL = 0xd0683978 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL = 0xd068397c # macro +cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX = 0xd0683980 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX = 0xd0680000 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA = 0xd0680004 # macro +cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI = 0xd0680018 # macro +cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG = 0xd0683694 # macro +cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN = 0xd0683780 # macro +cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE = 0xd068378c # macro +cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED = 0xd0683790 # macro +cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER = 0xd0683794 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO = 0xd06c2000 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI = 0xd06c2004 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA = 0xd06c2008 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL = 0xd06c200c # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO = 0xd06c2010 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI = 0xd06c2014 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA = 0xd06c2018 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL = 0xd06c201c # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO = 0xd06c2020 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI = 0xd06c2024 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA = 0xd06c2028 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL = 0xd06c202c # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO = 0xd06c2030 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI = 0xd06c2034 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA = 0xd06c2038 # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL = 0xd06c203c # macro +cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA = 0xd06c3000 # macro +cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS = 0xd070382c # macro +cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG = 0xd0703830 # macro +cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd070384c # macro +cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0703850 # macro +cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0703854 # macro +cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0703858 # macro +cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd070385c # macro +cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0703864 # macro +cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0703868 # macro +cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ = 0xd0703898 # macro +cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE = 0xd070389c # macro +cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING = 0xd07038a0 # macro +cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS = 0xd07038c8 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 = 0xd0703958 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 = 0xd070395c # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 = 0xd0703960 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 = 0xd0703964 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 = 0xd0703968 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 = 0xd070396c # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 = 0xd0703970 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 = 0xd0703974 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL = 0xd0703978 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL = 0xd070397c # macro +cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX = 0xd0703980 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX = 0xd0700000 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA = 0xd0700004 # macro +cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI = 0xd0700018 # macro +cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG = 0xd0703694 # macro +cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN = 0xd0703780 # macro +cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE = 0xd070378c # macro +cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED = 0xd0703790 # macro +cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER = 0xd0703794 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO = 0xd0742000 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI = 0xd0742004 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA = 0xd0742008 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL = 0xd074200c # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO = 0xd0742010 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI = 0xd0742014 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA = 0xd0742018 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL = 0xd074201c # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO = 0xd0742020 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI = 0xd0742024 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA = 0xd0742028 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL = 0xd074202c # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO = 0xd0742030 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI = 0xd0742034 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA = 0xd0742038 # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL = 0xd074203c # macro +cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA = 0xd0743000 # macro +cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS = 0xd078382c # macro +cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG = 0xd0783830 # macro +cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0xd078384c # macro +cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0xd0783850 # macro +cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL = 0xd0783854 # macro +cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL = 0xd0783858 # macro +cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL = 0xd078385c # macro +cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0xd0783864 # macro +cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0xd0783868 # macro +cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ = 0xd0783898 # macro +cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE = 0xd078389c # macro +cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING = 0xd07838a0 # macro +cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS = 0xd07838c8 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 = 0xd0783958 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 = 0xd078395c # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 = 0xd0783960 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 = 0xd0783964 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 = 0xd0783968 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 = 0xd078396c # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 = 0xd0783970 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 = 0xd0783974 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL = 0xd0783978 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL = 0xd078397c # macro +cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX = 0xd0783980 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX = 0xd0780000 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA = 0xd0780004 # macro +cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI = 0xd0780018 # macro +cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG = 0xd0783694 # macro +cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN = 0xd0783780 # macro +cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE = 0xd078378c # macro +cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED = 0xd0783790 # macro +cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER = 0xd0783794 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO = 0xd07c2000 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI = 0xd07c2004 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA = 0xd07c2008 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL = 0xd07c200c # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO = 0xd07c2010 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI = 0xd07c2014 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA = 0xd07c2018 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL = 0xd07c201c # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO = 0xd07c2020 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI = 0xd07c2024 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA = 0xd07c2028 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL = 0xd07c202c # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO = 0xd07c2030 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI = 0xd07c2034 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA = 0xd07c2038 # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL = 0xd07c203c # macro +cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA = 0xd07c3000 # macro +regPCIEP_RESERVED = 0x2890000 # macro +regPCIEP_RESERVED_BASE_IDX = 5 # macro +regPCIEP_SCRATCH = 0x2890001 # macro +regPCIEP_SCRATCH_BASE_IDX = 5 # macro +regPCIEP_PORT_CNTL = 0x2890010 # macro +regPCIEP_PORT_CNTL_BASE_IDX = 5 # macro +regPCIE_TX_REQUESTER_ID = 0x2890021 # macro +regPCIE_TX_REQUESTER_ID_BASE_IDX = 5 # macro +regPCIE_P_PORT_LANE_STATUS = 0x2890050 # macro +regPCIE_P_PORT_LANE_STATUS_BASE_IDX = 5 # macro +regPSWUSP0_PCIE_ERR_CNTL = 0x289006a # macro +regPSWUSP0_PCIE_ERR_CNTL_BASE_IDX = 5 # macro +regPSWUSP0_PCIE_RX_CNTL = 0x2890070 # macro +regPSWUSP0_PCIE_RX_CNTL_BASE_IDX = 5 # macro +regPCIE_RX_EXPECTED_SEQNUM = 0x2890071 # macro +regPCIE_RX_EXPECTED_SEQNUM_BASE_IDX = 5 # macro +regPCIE_RX_VENDOR_SPECIFIC = 0x2890072 # macro +regPCIE_RX_VENDOR_SPECIFIC_BASE_IDX = 5 # macro +regPCIE_RX_CNTL3 = 0x2890074 # macro +regPCIE_RX_CNTL3_BASE_IDX = 5 # macro +regPCIE_RX_CREDITS_ALLOCATED_P = 0x2890080 # macro +regPCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX = 5 # macro +regPCIE_RX_CREDITS_ALLOCATED_NP = 0x2890081 # macro +regPCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX = 5 # macro +regPCIE_RX_CREDITS_ALLOCATED_CPL = 0x2890082 # macro +regPCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX = 5 # macro +regPCIEP_ERROR_INJECT_PHYSICAL = 0x2890083 # macro +regPCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX = 5 # macro +regPCIEP_ERROR_INJECT_TRANSACTION = 0x2890084 # macro +regPCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX = 5 # macro +regPCIEP_NAK_COUNTER = 0x2890086 # macro +regPCIEP_NAK_COUNTER_BASE_IDX = 5 # macro +regPCIE_LC_CNTL = 0x28900a0 # macro +regPCIE_LC_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_TRAINING_CNTL = 0x28900a1 # macro +regPCIE_LC_TRAINING_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_LINK_WIDTH_CNTL = 0x28900a2 # macro +regPCIE_LC_LINK_WIDTH_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_N_FTS_CNTL = 0x28900a3 # macro +regPCIE_LC_N_FTS_CNTL_BASE_IDX = 5 # macro +regPSWUSP0_PCIE_LC_SPEED_CNTL = 0x28900a4 # macro +regPSWUSP0_PCIE_LC_SPEED_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_STATE0 = 0x28900a5 # macro +regPCIE_LC_STATE0_BASE_IDX = 5 # macro +regPCIE_LC_STATE1 = 0x28900a6 # macro +regPCIE_LC_STATE1_BASE_IDX = 5 # macro +regPCIE_LC_STATE2 = 0x28900a7 # macro +regPCIE_LC_STATE2_BASE_IDX = 5 # macro +regPCIE_LC_STATE3 = 0x28900a8 # macro +regPCIE_LC_STATE3_BASE_IDX = 5 # macro +regPCIE_LC_STATE4 = 0x28900a9 # macro +regPCIE_LC_STATE4_BASE_IDX = 5 # macro +regPCIE_LC_STATE5 = 0x28900aa # macro +regPCIE_LC_STATE5_BASE_IDX = 5 # macro +regPSWUSP0_PCIE_LC_CNTL2 = 0x28900b1 # macro +regPSWUSP0_PCIE_LC_CNTL2_BASE_IDX = 5 # macro +regPCIE_LC_BW_CHANGE_CNTL = 0x28900b2 # macro +regPCIE_LC_BW_CHANGE_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_CDR_CNTL = 0x28900b3 # macro +regPCIE_LC_CDR_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_LANE_CNTL = 0x28900b4 # macro +regPCIE_LC_LANE_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_CNTL3 = 0x28900b5 # macro +regPCIE_LC_CNTL3_BASE_IDX = 5 # macro +regPCIE_LC_CNTL4 = 0x28900b6 # macro +regPCIE_LC_CNTL4_BASE_IDX = 5 # macro +regPCIE_LC_CNTL5 = 0x28900b7 # macro +regPCIE_LC_CNTL5_BASE_IDX = 5 # macro +regPCIE_LC_FORCE_COEFF = 0x28900b8 # macro +regPCIE_LC_FORCE_COEFF_BASE_IDX = 5 # macro +regPCIE_LC_BEST_EQ_SETTINGS = 0x28900b9 # macro +regPCIE_LC_BEST_EQ_SETTINGS_BASE_IDX = 5 # macro +regPCIE_LC_FORCE_EQ_REQ_COEFF = 0x28900ba # macro +regPCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX = 5 # macro +regPCIE_LC_CNTL6 = 0x28900bb # macro +regPCIE_LC_CNTL6_BASE_IDX = 5 # macro +regPCIE_LC_CNTL7 = 0x28900bc # macro +regPCIE_LC_CNTL7_BASE_IDX = 5 # macro +regPCIEP_STRAP_LC = 0x28900c0 # macro +regPCIEP_STRAP_LC_BASE_IDX = 5 # macro +regPSWUSP0_PCIEP_STRAP_MISC = 0x28900c1 # macro +regPSWUSP0_PCIEP_STRAP_MISC_BASE_IDX = 5 # macro +regPCIEP_STRAP_LC2 = 0x28900c2 # macro +regPCIEP_STRAP_LC2_BASE_IDX = 5 # macro +regPCIE_LC_L1_PM_SUBSTATE = 0x28900c6 # macro +regPCIE_LC_L1_PM_SUBSTATE_BASE_IDX = 5 # macro +regPCIE_LC_L1_PM_SUBSTATE2 = 0x28900c7 # macro +regPCIE_LC_L1_PM_SUBSTATE2_BASE_IDX = 5 # macro +regPCIE_LC_L1_PM_SUBSTATE3 = 0x28900c8 # macro +regPCIE_LC_L1_PM_SUBSTATE3_BASE_IDX = 5 # macro +regPCIE_LC_L1_PM_SUBSTATE4 = 0x28900c9 # macro +regPCIE_LC_L1_PM_SUBSTATE4_BASE_IDX = 5 # macro +regPCIE_LC_L1_PM_SUBSTATE5 = 0x28900ca # macro +regPCIE_LC_L1_PM_SUBSTATE5_BASE_IDX = 5 # macro +regPCIEP_BCH_ECC_CNTL = 0x28900d0 # macro +regPCIEP_BCH_ECC_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_CNTL8 = 0x28900dd # macro +regPCIE_LC_CNTL8_BASE_IDX = 5 # macro +regPCIE_LC_CNTL9 = 0x28900de # macro +regPCIE_LC_CNTL9_BASE_IDX = 5 # macro +regPCIE_LC_FORCE_COEFF2 = 0x28900df # macro +regPCIE_LC_FORCE_COEFF2_BASE_IDX = 5 # macro +regPCIE_LC_FORCE_EQ_REQ_COEFF2 = 0x28900e0 # macro +regPCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX = 5 # macro +regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES = 0x28900e2 # macro +regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX = 5 # macro +regPCIE_LC_CNTL10 = 0x28900e3 # macro +regPCIE_LC_CNTL10_BASE_IDX = 5 # macro +regPCIE_LC_SAVE_RESTORE_1 = 0x28900e6 # macro +regPCIE_LC_SAVE_RESTORE_1_BASE_IDX = 5 # macro +regPCIE_LC_SAVE_RESTORE_2 = 0x28900e7 # macro +regPCIE_LC_SAVE_RESTORE_2_BASE_IDX = 5 # macro +regPCIE_LC_CNTL11 = 0x2890103 # macro +regPCIE_LC_CNTL11_BASE_IDX = 5 # macro +regPCIE_LC_CNTL12 = 0x2890104 # macro +regPCIE_LC_CNTL12_BASE_IDX = 5 # macro +regPCIE_LC_SPEED_CNTL2 = 0x2890105 # macro +regPCIE_LC_SPEED_CNTL2_BASE_IDX = 5 # macro +regPCIE_LC_FORCE_COEFF3 = 0x2890106 # macro +regPCIE_LC_FORCE_COEFF3_BASE_IDX = 5 # macro +regPCIE_LC_FORCE_EQ_REQ_COEFF3 = 0x2890107 # macro +regPCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX = 5 # macro +regPCIE_TX_SEQ = 0x2890188 # macro +regPCIE_TX_SEQ_BASE_IDX = 5 # macro +regPCIE_TX_REPLAY = 0x2890189 # macro +regPCIE_TX_REPLAY_BASE_IDX = 5 # macro +regPCIE_TX_ACK_LATENCY_LIMIT = 0x289018c # macro +regPCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_FCU_THRESHOLD = 0x2890190 # macro +regPCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX = 5 # macro +regPCIE_TX_VENDOR_SPECIFIC = 0x2890194 # macro +regPCIE_TX_VENDOR_SPECIFIC_BASE_IDX = 5 # macro +regPCIE_TX_NOP_DLLP = 0x2890195 # macro +regPCIE_TX_NOP_DLLP_BASE_IDX = 5 # macro +regPCIE_TX_REQUEST_NUM_CNTL = 0x2890198 # macro +regPCIE_TX_REQUEST_NUM_CNTL_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_ADVT_P = 0x28901a0 # macro +regPCIE_TX_CREDITS_ADVT_P_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_ADVT_NP = 0x28901a1 # macro +regPCIE_TX_CREDITS_ADVT_NP_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_ADVT_CPL = 0x28901a2 # macro +regPCIE_TX_CREDITS_ADVT_CPL_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_INIT_P = 0x28901a3 # macro +regPCIE_TX_CREDITS_INIT_P_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_INIT_NP = 0x28901a4 # macro +regPCIE_TX_CREDITS_INIT_NP_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_INIT_CPL = 0x28901a5 # macro +regPCIE_TX_CREDITS_INIT_CPL_BASE_IDX = 5 # macro +regPCIE_TX_CREDITS_STATUS = 0x28901a6 # macro +regPCIE_TX_CREDITS_STATUS_BASE_IDX = 5 # macro +regPCIE_FC_P = 0x28901a8 # macro +regPCIE_FC_P_BASE_IDX = 5 # macro +regPCIE_FC_NP = 0x28901a9 # macro +regPCIE_FC_NP_BASE_IDX = 5 # macro +regPCIE_FC_CPL = 0x28901aa # macro +regPCIE_FC_CPL_BASE_IDX = 5 # macro +regPCIE_FC_P_VC1 = 0x28901ab # macro +regPCIE_FC_P_VC1_BASE_IDX = 5 # macro +regPCIE_FC_NP_VC1 = 0x28901ac # macro +regPCIE_FC_NP_VC1_BASE_IDX = 5 # macro +regPCIE_FC_CPL_VC1 = 0x28901ad # macro +regPCIE_FC_CPL_VC1_BASE_IDX = 5 # macro +regPCIE_RESERVED = 0x28a0000 # macro +regPCIE_RESERVED_BASE_IDX = 5 # macro +regPCIE_SCRATCH = 0x28a0001 # macro +regPCIE_SCRATCH_BASE_IDX = 5 # macro +regPCIE_RX_NUM_NAK = 0x28a000e # macro +regPCIE_RX_NUM_NAK_BASE_IDX = 5 # macro +regPCIE_RX_NUM_NAK_GENERATED = 0x28a000f # macro +regPCIE_RX_NUM_NAK_GENERATED_BASE_IDX = 5 # macro +regPCIE_CNTL = 0x28a0010 # macro +regPCIE_CNTL_BASE_IDX = 5 # macro +regPCIE_CONFIG_CNTL = 0x28a0011 # macro +regPCIE_CONFIG_CNTL_BASE_IDX = 5 # macro +regPCIE_RX_CNTL5 = 0x28a0018 # macro +regPCIE_RX_CNTL5_BASE_IDX = 5 # macro +regPCIE_RX_CNTL4 = 0x28a0019 # macro +regPCIE_RX_CNTL4_BASE_IDX = 5 # macro +regPCIE_COMMON_AER_MASK = 0x28a001a # macro +regPCIE_COMMON_AER_MASK_BASE_IDX = 5 # macro +regPCIE_CNTL2 = 0x28a001c # macro +regPCIE_CNTL2_BASE_IDX = 5 # macro +regPCIE_RX_CNTL2 = 0x28a001d # macro +regPCIE_RX_CNTL2_BASE_IDX = 5 # macro +regPCIE_CI_CNTL = 0x28a0020 # macro +regPCIE_CI_CNTL_BASE_IDX = 5 # macro +regPCIE_BUS_CNTL = 0x28a0021 # macro +regPCIE_BUS_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_STATE6 = 0x28a0022 # macro +regPCIE_LC_STATE6_BASE_IDX = 5 # macro +regPCIE_LC_STATE7 = 0x28a0023 # macro +regPCIE_LC_STATE7_BASE_IDX = 5 # macro +regPCIE_LC_STATE8 = 0x28a0024 # macro +regPCIE_LC_STATE8_BASE_IDX = 5 # macro +regPCIE_LC_STATE9 = 0x28a0025 # macro +regPCIE_LC_STATE9_BASE_IDX = 5 # macro +regPCIE_LC_STATE10 = 0x28a0026 # macro +regPCIE_LC_STATE10_BASE_IDX = 5 # macro +regPCIE_LC_STATE11 = 0x28a0027 # macro +regPCIE_LC_STATE11_BASE_IDX = 5 # macro +regPCIE_LC_STATUS1 = 0x28a0028 # macro +regPCIE_LC_STATUS1_BASE_IDX = 5 # macro +regPCIE_LC_STATUS2 = 0x28a0029 # macro +regPCIE_LC_STATUS2_BASE_IDX = 5 # macro +regPCIE_WPR_CNTL = 0x28a0030 # macro +regPCIE_WPR_CNTL_BASE_IDX = 5 # macro +regPCIE_RX_LAST_TLP0 = 0x28a0031 # macro +regPCIE_RX_LAST_TLP0_BASE_IDX = 5 # macro +regPCIE_RX_LAST_TLP1 = 0x28a0032 # macro +regPCIE_RX_LAST_TLP1_BASE_IDX = 5 # macro +regPCIE_RX_LAST_TLP2 = 0x28a0033 # macro +regPCIE_RX_LAST_TLP2_BASE_IDX = 5 # macro +regPCIE_RX_LAST_TLP3 = 0x28a0034 # macro +regPCIE_RX_LAST_TLP3_BASE_IDX = 5 # macro +regPCIE_I2C_REG_ADDR_EXPAND = 0x28a003a # macro +regPCIE_I2C_REG_ADDR_EXPAND_BASE_IDX = 5 # macro +regPCIE_I2C_REG_DATA = 0x28a003b # macro +regPCIE_I2C_REG_DATA_BASE_IDX = 5 # macro +regPCIE_CFG_CNTL = 0x28a003c # macro +regPCIE_CFG_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_PM_CNTL = 0x28a003d # macro +regPCIE_LC_PM_CNTL_BASE_IDX = 5 # macro +regPCIE_LC_PM_CNTL2 = 0x28a003e # macro +regPCIE_LC_PM_CNTL2_BASE_IDX = 5 # macro +regPCIE_P_CNTL = 0x28a0040 # macro +regPCIE_P_CNTL_BASE_IDX = 5 # macro +regPCIE_P_BUF_STATUS = 0x28a0041 # macro +regPCIE_P_BUF_STATUS_BASE_IDX = 5 # macro +regPCIE_P_DECODER_STATUS = 0x28a0042 # macro +regPCIE_P_DECODER_STATUS_BASE_IDX = 5 # macro +regPCIE_P_MISC_STATUS = 0x28a0043 # macro +regPCIE_P_MISC_STATUS_BASE_IDX = 5 # macro +regPCIE_P_RCV_L0S_FTS_DET = 0x28a0050 # macro +regPCIE_P_RCV_L0S_FTS_DET_BASE_IDX = 5 # macro +regPCIE_RX_AD = 0x28a0062 # macro +regPCIE_RX_AD_BASE_IDX = 5 # macro +regPCIE_SDP_CTRL = 0x28a0063 # macro +regPCIE_SDP_CTRL_BASE_IDX = 5 # macro +regPCIE_SDP_SWUS_SLV_ATTR_CTRL = 0x28a0065 # macro +regPCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX = 5 # macro +regPCIE_SDP_CTRL2 = 0x28a0068 # macro +regPCIE_SDP_CTRL2_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT_CNTL = 0x28a0080 # macro +regPCIE_PERF_COUNT_CNTL_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK1 = 0x28a0081 # macro +regPCIE_PERF_CNTL_TXCLK1_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK1 = 0x28a0082 # macro +regPCIE_PERF_COUNT0_TXCLK1_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK1 = 0x28a0083 # macro +regPCIE_PERF_COUNT1_TXCLK1_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK2 = 0x28a0084 # macro +regPCIE_PERF_CNTL_TXCLK2_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK2 = 0x28a0085 # macro +regPCIE_PERF_COUNT0_TXCLK2_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK2 = 0x28a0086 # macro +regPCIE_PERF_COUNT1_TXCLK2_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK3 = 0x28a0087 # macro +regPCIE_PERF_CNTL_TXCLK3_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK3 = 0x28a0088 # macro +regPCIE_PERF_COUNT0_TXCLK3_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK3 = 0x28a0089 # macro +regPCIE_PERF_COUNT1_TXCLK3_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK4 = 0x28a008a # macro +regPCIE_PERF_CNTL_TXCLK4_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK4 = 0x28a008b # macro +regPCIE_PERF_COUNT0_TXCLK4_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK4 = 0x28a008c # macro +regPCIE_PERF_COUNT1_TXCLK4_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL = 0x28a0093 # macro +regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL = 0x28a0094 # macro +regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK5 = 0x28a0096 # macro +regPCIE_PERF_CNTL_TXCLK5_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK5 = 0x28a0097 # macro +regPCIE_PERF_COUNT0_TXCLK5_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK5 = 0x28a0098 # macro +regPCIE_PERF_COUNT1_TXCLK5_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK6 = 0x28a0099 # macro +regPCIE_PERF_CNTL_TXCLK6_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK6 = 0x28a009a # macro +regPCIE_PERF_COUNT0_TXCLK6_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK6 = 0x28a009b # macro +regPCIE_PERF_COUNT1_TXCLK6_BASE_IDX = 5 # macro +regPCIE_STRAP_F0 = 0x28a00b0 # macro +regPCIE_STRAP_F0_BASE_IDX = 5 # macro +regPCIE_STRAP_MISC = 0x28a00c0 # macro +regPCIE_STRAP_MISC_BASE_IDX = 5 # macro +regPCIE_STRAP_MISC2 = 0x28a00c1 # macro +regPCIE_STRAP_MISC2_BASE_IDX = 5 # macro +regPCIE_STRAP_PI = 0x28a00c2 # macro +regPCIE_STRAP_PI_BASE_IDX = 5 # macro +regPCIE_STRAP_I2C_BD = 0x28a00c4 # macro +regPCIE_STRAP_I2C_BD_BASE_IDX = 5 # macro +regPCIE_PRBS_CLR = 0x28a00c8 # macro +regPCIE_PRBS_CLR_BASE_IDX = 5 # macro +regPCIE_PRBS_STATUS1 = 0x28a00c9 # macro +regPCIE_PRBS_STATUS1_BASE_IDX = 5 # macro +regPCIE_PRBS_STATUS2 = 0x28a00ca # macro +regPCIE_PRBS_STATUS2_BASE_IDX = 5 # macro +regPCIE_PRBS_FREERUN = 0x28a00cb # macro +regPCIE_PRBS_FREERUN_BASE_IDX = 5 # macro +regPCIE_PRBS_MISC = 0x28a00cc # macro +regPCIE_PRBS_MISC_BASE_IDX = 5 # macro +regPCIE_PRBS_USER_PATTERN = 0x28a00cd # macro +regPCIE_PRBS_USER_PATTERN_BASE_IDX = 5 # macro +regPCIE_PRBS_LO_BITCNT = 0x28a00ce # macro +regPCIE_PRBS_LO_BITCNT_BASE_IDX = 5 # macro +regPCIE_PRBS_HI_BITCNT = 0x28a00cf # macro +regPCIE_PRBS_HI_BITCNT_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_0 = 0x28a00d0 # macro +regPCIE_PRBS_ERRCNT_0_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_1 = 0x28a00d1 # macro +regPCIE_PRBS_ERRCNT_1_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_2 = 0x28a00d2 # macro +regPCIE_PRBS_ERRCNT_2_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_3 = 0x28a00d3 # macro +regPCIE_PRBS_ERRCNT_3_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_4 = 0x28a00d4 # macro +regPCIE_PRBS_ERRCNT_4_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_5 = 0x28a00d5 # macro +regPCIE_PRBS_ERRCNT_5_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_6 = 0x28a00d6 # macro +regPCIE_PRBS_ERRCNT_6_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_7 = 0x28a00d7 # macro +regPCIE_PRBS_ERRCNT_7_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_8 = 0x28a00d8 # macro +regPCIE_PRBS_ERRCNT_8_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_9 = 0x28a00d9 # macro +regPCIE_PRBS_ERRCNT_9_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_10 = 0x28a00da # macro +regPCIE_PRBS_ERRCNT_10_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_11 = 0x28a00db # macro +regPCIE_PRBS_ERRCNT_11_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_12 = 0x28a00dc # macro +regPCIE_PRBS_ERRCNT_12_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_13 = 0x28a00dd # macro +regPCIE_PRBS_ERRCNT_13_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_14 = 0x28a00de # macro +regPCIE_PRBS_ERRCNT_14_BASE_IDX = 5 # macro +regPCIE_PRBS_ERRCNT_15 = 0x28a00df # macro +regPCIE_PRBS_ERRCNT_15_BASE_IDX = 5 # macro +regSWRST_COMMAND_STATUS = 0x28a0100 # macro +regSWRST_COMMAND_STATUS_BASE_IDX = 5 # macro +regSWRST_GENERAL_CONTROL = 0x28a0101 # macro +regSWRST_GENERAL_CONTROL_BASE_IDX = 5 # macro +regSWRST_COMMAND_0 = 0x28a0102 # macro +regSWRST_COMMAND_0_BASE_IDX = 5 # macro +regSWRST_COMMAND_1 = 0x28a0103 # macro +regSWRST_COMMAND_1_BASE_IDX = 5 # macro +regSWRST_CONTROL_0 = 0x28a0104 # macro +regSWRST_CONTROL_0_BASE_IDX = 5 # macro +regSWRST_CONTROL_1 = 0x28a0105 # macro +regSWRST_CONTROL_1_BASE_IDX = 5 # macro +regSWRST_CONTROL_2 = 0x28a0106 # macro +regSWRST_CONTROL_2_BASE_IDX = 5 # macro +regSWRST_CONTROL_3 = 0x28a0107 # macro +regSWRST_CONTROL_3_BASE_IDX = 5 # macro +regSWRST_CONTROL_4 = 0x28a0108 # macro +regSWRST_CONTROL_4_BASE_IDX = 5 # macro +regSWRST_CONTROL_5 = 0x28a0109 # macro +regSWRST_CONTROL_5_BASE_IDX = 5 # macro +regSWRST_CONTROL_6 = 0x28a010a # macro +regSWRST_CONTROL_6_BASE_IDX = 5 # macro +regSWRST_EP_COMMAND_0 = 0x28a010b # macro +regSWRST_EP_COMMAND_0_BASE_IDX = 5 # macro +regSWRST_EP_CONTROL_0 = 0x28a010c # macro +regSWRST_EP_CONTROL_0_BASE_IDX = 5 # macro +regCPM_CONTROL = 0x28a0118 # macro +regCPM_CONTROL_BASE_IDX = 5 # macro +regCPM_SPLIT_CONTROL = 0x28a0119 # macro +regCPM_SPLIT_CONTROL_BASE_IDX = 5 # macro +regCPM_CONTROL_EXT = 0x28a011a # macro +regCPM_CONTROL_EXT_BASE_IDX = 5 # macro +regSMN_APERTURE_ID_A = 0x28a011d # macro +regSMN_APERTURE_ID_A_BASE_IDX = 5 # macro +regSMN_APERTURE_ID_B = 0x28a011e # macro +regSMN_APERTURE_ID_B_BASE_IDX = 5 # macro +regLNCNT_CONTROL = 0x28a0125 # macro +regLNCNT_CONTROL_BASE_IDX = 5 # macro +regSMU_INT_PIN_SHARING_PORT_INDICATOR = 0x28a012f # macro +regSMU_INT_PIN_SHARING_PORT_INDICATOR_BASE_IDX = 5 # macro +regPCIE_PGMST_CNTL = 0x28a0130 # macro +regPCIE_PGMST_CNTL_BASE_IDX = 5 # macro +regPCIE_PGSLV_CNTL = 0x28a0131 # macro +regPCIE_PGSLV_CNTL_BASE_IDX = 5 # macro +regLC_CPM_CONTROL_0 = 0x28a0133 # macro +regLC_CPM_CONTROL_0_BASE_IDX = 5 # macro +regLC_CPM_CONTROL_1 = 0x28a0134 # macro +regLC_CPM_CONTROL_1_BASE_IDX = 5 # macro +regPCIE_RXMARGIN_CONTROL_CAPABILITIES = 0x28a0135 # macro +regPCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX = 5 # macro +regPCIE_RXMARGIN_1_SETTINGS = 0x28a0136 # macro +regPCIE_RXMARGIN_1_SETTINGS_BASE_IDX = 5 # macro +regPCIE_RXMARGIN_2_SETTINGS = 0x28a0137 # macro +regPCIE_RXMARGIN_2_SETTINGS_BASE_IDX = 5 # macro +regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO = 0x28a013a # macro +regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO_BASE_IDX = 5 # macro +regPCIE_TX_LAST_TLP0 = 0x28a0180 # macro +regPCIE_TX_LAST_TLP0_BASE_IDX = 5 # macro +regPCIE_TX_LAST_TLP1 = 0x28a0181 # macro +regPCIE_TX_LAST_TLP1_BASE_IDX = 5 # macro +regPCIE_TX_LAST_TLP2 = 0x28a0182 # macro +regPCIE_TX_LAST_TLP2_BASE_IDX = 5 # macro +regPCIE_TX_LAST_TLP3 = 0x28a0183 # macro +regPCIE_TX_LAST_TLP3_BASE_IDX = 5 # macro +regPCIE_TX_TRACKING_ADDR_LO = 0x28a0184 # macro +regPCIE_TX_TRACKING_ADDR_LO_BASE_IDX = 5 # macro +regPCIE_TX_TRACKING_ADDR_HI = 0x28a0185 # macro +regPCIE_TX_TRACKING_ADDR_HI_BASE_IDX = 5 # macro +regPCIE_TX_TRACKING_CTRL_STATUS = 0x28a0186 # macro +regPCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX = 5 # macro +regPCIE_TX_CTRL_4 = 0x28a018b # macro +regPCIE_TX_CTRL_4_BASE_IDX = 5 # macro +regPCIE_TX_STATUS = 0x28a0194 # macro +regPCIE_TX_STATUS_BASE_IDX = 5 # macro +regPCIE_TX_F0_ATTR_CNTL = 0x28a019c # macro +regPCIE_TX_F0_ATTR_CNTL_BASE_IDX = 5 # macro +regPCIE_TX_SWUS_ATTR_CNTL = 0x28a019d # macro +regPCIE_TX_SWUS_ATTR_CNTL_BASE_IDX = 5 # macro +regPCIE_MST_CTRL_1 = 0x28a01c4 # macro +regPCIE_MST_CTRL_1_BASE_IDX = 5 # macro +regPCIE_HIP_REG0 = 0x28a01e0 # macro +regPCIE_HIP_REG0_BASE_IDX = 5 # macro +regPCIE_HIP_REG1 = 0x28a01e1 # macro +regPCIE_HIP_REG1_BASE_IDX = 5 # macro +regPCIE_HIP_REG2 = 0x28a01e2 # macro +regPCIE_HIP_REG2_BASE_IDX = 5 # macro +regPCIE_HIP_REG3 = 0x28a01e3 # macro +regPCIE_HIP_REG3_BASE_IDX = 5 # macro +regPCIE_HIP_REG4 = 0x28a01e4 # macro +regPCIE_HIP_REG4_BASE_IDX = 5 # macro +regPCIE_HIP_REG5 = 0x28a01e5 # macro +regPCIE_HIP_REG5_BASE_IDX = 5 # macro +regPCIE_HIP_REG6 = 0x28a01e6 # macro +regPCIE_HIP_REG6_BASE_IDX = 5 # macro +regPCIE_HIP_REG7 = 0x28a01e7 # macro +regPCIE_HIP_REG7_BASE_IDX = 5 # macro +regPCIE_HIP_REG8 = 0x28a01e8 # macro +regPCIE_HIP_REG8_BASE_IDX = 5 # macro +regSMU_PCIE_FENCED1_REG = 0x28a0200 # macro +regSMU_PCIE_FENCED1_REG_BASE_IDX = 5 # macro +regSMU_PCIE_FENCED2_REG = 0x28a0201 # macro +regSMU_PCIE_FENCED2_REG_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK7 = 0x28a0222 # macro +regPCIE_PERF_CNTL_TXCLK7_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK7 = 0x28a0223 # macro +regPCIE_PERF_COUNT0_TXCLK7_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK7 = 0x28a0224 # macro +regPCIE_PERF_COUNT1_TXCLK7_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK8 = 0x28a0225 # macro +regPCIE_PERF_CNTL_TXCLK8_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK8 = 0x28a0226 # macro +regPCIE_PERF_COUNT0_TXCLK8_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK8 = 0x28a0227 # macro +regPCIE_PERF_COUNT1_TXCLK8_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK9 = 0x28a0228 # macro +regPCIE_PERF_CNTL_TXCLK9_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK9 = 0x28a0229 # macro +regPCIE_PERF_COUNT0_TXCLK9_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK9 = 0x28a022a # macro +regPCIE_PERF_COUNT1_TXCLK9_BASE_IDX = 5 # macro +regPCIE_PERF_CNTL_TXCLK10 = 0x28a022b # macro +regPCIE_PERF_CNTL_TXCLK10_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT0_TXCLK10 = 0x28a022c # macro +regPCIE_PERF_COUNT0_TXCLK10_BASE_IDX = 5 # macro +regPCIE_PERF_COUNT1_TXCLK10 = 0x28a022d # macro +regPCIE_PERF_COUNT1_TXCLK10_BASE_IDX = 5 # macro +regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY = 0x2880006 # macro +regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_BASE_IDX = 5 # macro +regPSWUSCFG0_IO_BASE_LIMIT = 0x2880007 # macro +regPSWUSCFG0_IO_BASE_LIMIT_BASE_IDX = 5 # macro +regPSWUSCFG0_SECONDARY_STATUS = 0x2880007 # macro +regPSWUSCFG0_SECONDARY_STATUS_BASE_IDX = 5 # macro +regPSWUSCFG0_MEM_BASE_LIMIT = 0x2880008 # macro +regPSWUSCFG0_MEM_BASE_LIMIT_BASE_IDX = 5 # macro +regPSWUSCFG0_PREF_BASE_LIMIT = 0x2880009 # macro +regPSWUSCFG0_PREF_BASE_LIMIT_BASE_IDX = 5 # macro +regPSWUSCFG0_PREF_BASE_UPPER = 0x288000a # macro +regPSWUSCFG0_PREF_BASE_UPPER_BASE_IDX = 5 # macro +regPSWUSCFG0_PREF_LIMIT_UPPER = 0x288000b # macro +regPSWUSCFG0_PREF_LIMIT_UPPER_BASE_IDX = 5 # macro +regPSWUSCFG0_IO_BASE_LIMIT_HI = 0x288000c # macro +regPSWUSCFG0_IO_BASE_LIMIT_HI_BASE_IDX = 5 # macro +regPSWUSCFG0_SSID_CAP_LIST = 0x2880030 # macro +regPSWUSCFG0_SSID_CAP_LIST_BASE_IDX = 5 # macro +regPSWUSCFG0_SSID_CAP = 0x2880031 # macro +regPSWUSCFG0_SSID_CAP_BASE_IDX = 5 # macro +regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL = 0x2890102 # macro +regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY = 0x0006 # macro +regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_IO_BASE_LIMIT = 0x0007 # macro +regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_SECONDARY_STATUS = 0x0007 # macro +regBIF_CFG_DEV0_RC_SECONDARY_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT = 0x0008 # macro +regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT = 0x0009 # macro +regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_PREF_BASE_UPPER = 0x000a # macro +regBIF_CFG_DEV0_RC_PREF_BASE_UPPER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER = 0x000b # macro +regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI = 0x000c # macro +regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI_BASE_IDX = 5 # macro +regSLOT_CAP = 0x001b # macro +regSLOT_CAP_BASE_IDX = 5 # macro +regSLOT_CNTL = 0x001c # macro +regSLOT_CNTL_BASE_IDX = 5 # macro +regSLOT_STATUS = 0x001c # macro +regSLOT_STATUS_BASE_IDX = 5 # macro +regSLOT_CAP2 = 0x0023 # macro +regSLOT_CAP2_BASE_IDX = 5 # macro +regSLOT_CNTL2 = 0x0024 # macro +regSLOT_CNTL2_BASE_IDX = 5 # macro +regSLOT_STATUS2 = 0x0024 # macro +regSLOT_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_SSID_CAP_LIST = 0x0030 # macro +regBIF_CFG_DEV0_RC_SSID_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_RC_SSID_CAP = 0x0031 # macro +regBIF_CFG_DEV0_RC_SSID_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VENDOR_ID = 0x10000 # macro +regBIF_CFG_DEV0_EPF0_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_ID = 0x10000 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_COMMAND = 0x10001 # macro +regBIF_CFG_DEV0_EPF0_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_STATUS = 0x10001 # macro +regBIF_CFG_DEV0_EPF0_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_REVISION_ID = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PROG_INTERFACE = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_SUB_CLASS = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BASE_CLASS = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_CACHE_LINE = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LATENCY = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_HEADER = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BIST = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_1 = 0x10004 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_2 = 0x10005 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_3 = 0x10006 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_4 = 0x10007 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_5 = 0x10008 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_6 = 0x10009 # macro +regBIF_CFG_DEV0_EPF0_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR = 0x1000a # macro +regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_ADAPTER_ID = 0x1000b # macro +regBIF_CFG_DEV0_EPF0_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR = 0x1000c # macro +regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_CAP_PTR = 0x1000d # macro +regBIF_CFG_DEV0_EPF0_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MIN_GRANT = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MAX_LATENCY = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST = 0x10012 # macro +regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W = 0x10013 # macro +regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST = 0x10014 # macro +regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PMI_CAP = 0x10014 # macro +regBIF_CFG_DEV0_EPF0_PMI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL = 0x10015 # macro +regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST = 0x10019 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CAP = 0x10019 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CAP = 0x1001a # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CNTL = 0x1001b # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_STATUS = 0x1001b # macro +regBIF_CFG_DEV0_EPF0_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP = 0x1001c # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL = 0x1001d # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS = 0x1001d # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CAP2 = 0x10022 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 = 0x10023 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 = 0x10023 # macro +regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP2 = 0x10024 # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL2 = 0x10025 # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS2 = 0x10025 # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST = 0x10028 # macro +regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL = 0x10028 # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO = 0x10029 # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI = 0x1002a # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA = 0x1002a # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA = 0x1002a # macro +regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_MASK = 0x1002b # macro +regBIF_CFG_DEV0_EPF0_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 = 0x1002b # macro +regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 = 0x1002b # macro +regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_MASK_64 = 0x1002c # macro +regBIF_CFG_DEV0_EPF0_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_PENDING = 0x1002c # macro +regBIF_CFG_DEV0_EPF0_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSI_PENDING_64 = 0x1002d # macro +regBIF_CFG_DEV0_EPF0_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST = 0x10030 # macro +regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL = 0x10030 # macro +regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSIX_TABLE = 0x10031 # macro +regBIF_CFG_DEV0_EPF0_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MSIX_PBA = 0x10032 # macro +regBIF_CFG_DEV0_EPF0_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x10040 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR = 0x10041 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 = 0x10042 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 = 0x10043 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST = 0x10044 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 = 0x10045 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 = 0x10046 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL = 0x10047 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS = 0x10047 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP = 0x10048 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL = 0x10049 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS = 0x1004a # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP = 0x1004b # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL = 0x1004c # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS = 0x1004d # macro +regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x10050 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 = 0x10051 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 = 0x10052 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x10054 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS = 0x10055 # macro +regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK = 0x10056 # macro +regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY = 0x10057 # macro +regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS = 0x10058 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK = 0x10059 # macro +regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL = 0x1005a # macro +regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 = 0x1005b # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 = 0x1005c # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 = 0x1005d # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 = 0x1005e # macro +regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 = 0x10062 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 = 0x10063 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 = 0x10064 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 = 0x10065 # macro +regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST = 0x10080 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP = 0x10081 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL = 0x10082 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP = 0x10083 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL = 0x10084 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP = 0x10085 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL = 0x10086 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP = 0x10087 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL = 0x10088 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP = 0x10089 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL = 0x1008a # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP = 0x1008b # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL = 0x1008c # macro +regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x10090 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT = 0x10091 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA = 0x10092 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP = 0x10093 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST = 0x10094 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP = 0x10095 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR = 0x10096 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS = 0x10097 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL = 0x10097 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST = 0x1009c # macro +regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 = 0x1009d # macro +regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS = 0x1009e # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL = 0x1009f # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL = 0x1009f # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL = 0x100a0 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL = 0x100a0 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL = 0x100a1 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL = 0x100a1 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL = 0x100a2 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL = 0x100a2 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL = 0x100a3 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL = 0x100a3 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL = 0x100a4 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL = 0x100a4 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL = 0x100a5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL = 0x100a5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL = 0x100a6 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL = 0x100a6 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST = 0x100a8 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP = 0x100a9 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL = 0x100a9 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST = 0x100b4 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP = 0x100b5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL = 0x100b5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST = 0x100bc # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP = 0x100bd # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL = 0x100bd # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 = 0x100be # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 = 0x100bf # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 = 0x100c0 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 = 0x100c1 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 = 0x100c2 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 = 0x100c3 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0x100c4 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0x100c5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST = 0x100c8 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP = 0x100c9 # macro +regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST = 0x100ca # macro +regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP = 0x100cb # macro +regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL = 0x100cb # macro +regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST = 0x100cc # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP = 0x100cd # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL = 0x100ce # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS = 0x100ce # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS = 0x100cf # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS = 0x100cf # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS = 0x100d0 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK = 0x100d0 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET = 0x100d1 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE = 0x100d1 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID = 0x100d2 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0x100d3 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE = 0x100d4 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 = 0x100d5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 = 0x100d6 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 = 0x100d7 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 = 0x100d8 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 = 0x100d9 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 = 0x100da # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0x100db # macro +regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST = 0x10100 # macro +regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP = 0x10101 # macro +regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS = 0x10102 # macro +regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST = 0x10104 # macro +regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT = 0x10105 # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT = 0x10106 # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT = 0x10107 # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x10108 # macro +regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x10109 # macro +regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x1010a # macro +regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST = 0x10114 # macro +regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP = 0x10115 # macro +regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS = 0x10115 # macro +regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL = 0x10116 # macro +regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS = 0x10116 # macro +regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL = 0x10117 # macro +regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS = 0x10117 # macro +regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL = 0x10118 # macro +regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS = 0x10118 # macro +regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL = 0x10119 # macro +regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS = 0x10119 # macro +regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL = 0x1011a # macro +regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS = 0x1011a # macro +regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL = 0x1011b # macro +regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS = 0x1011b # macro +regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL = 0x1011c # macro +regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS = 0x1011c # macro +regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL = 0x1011d # macro +regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS = 0x1011d # macro +regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL = 0x1011e # macro +regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS = 0x1011e # macro +regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL = 0x1011f # macro +regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS = 0x1011f # macro +regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL = 0x10120 # macro +regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS = 0x10120 # macro +regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL = 0x10121 # macro +regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS = 0x10121 # macro +regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL = 0x10122 # macro +regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS = 0x10122 # macro +regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL = 0x10123 # macro +regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS = 0x10123 # macro +regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL = 0x10124 # macro +regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS = 0x10124 # macro +regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL = 0x10125 # macro +regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS = 0x10125 # macro +regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST = 0x10130 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP = 0x10131 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL = 0x10132 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP = 0x10133 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL = 0x10134 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP = 0x10135 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL = 0x10136 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP = 0x10137 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL = 0x10138 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP = 0x10139 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL = 0x1013a # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP = 0x1013b # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL = 0x1013c # macro +regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT = 0x10141 # macro +regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT = 0x10142 # macro +regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT = 0x10143 # macro +regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID = 0x18000 # macro +regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID = 0x18000 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_COMMAND = 0x18001 # macro +regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_STATUS = 0x18001 # macro +regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID = 0x18002 # macro +regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE = 0x18002 # macro +regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS = 0x18002 # macro +regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS = 0x18002 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE = 0x18003 # macro +regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_LATENCY = 0x18003 # macro +regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_HEADER = 0x18003 # macro +regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BIST = 0x18003 # macro +regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 = 0x18004 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 = 0x18005 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 = 0x18006 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 = 0x18007 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 = 0x18008 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 = 0x18009 # macro +regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR = 0x1800a # macro +regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID = 0x1800b # macro +regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR = 0x1800c # macro +regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR = 0x1800d # macro +regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE = 0x1800f # macro +regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN = 0x1800f # macro +regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT = 0x1800f # macro +regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY = 0x1800f # macro +regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST = 0x18019 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP = 0x18019 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP = 0x1801a # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL = 0x1801b # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS = 0x1801b # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP = 0x1801c # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL = 0x1801d # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS = 0x1801d # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 = 0x18022 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 = 0x18023 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 = 0x18023 # macro +regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 = 0x18024 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 = 0x18025 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 = 0x18025 # macro +regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST = 0x18028 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL = 0x18028 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO = 0x18029 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI = 0x1802a # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA = 0x1802a # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA = 0x1802a # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK = 0x1802b # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 = 0x1802b # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 = 0x1802b # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 = 0x1802c # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING = 0x1802c # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 = 0x1802d # macro +regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST = 0x18030 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL = 0x18030 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE = 0x18031 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA = 0x18032 # macro +regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x18040 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR = 0x18041 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 = 0x18042 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 = 0x18043 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x18054 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS = 0x18055 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK = 0x18056 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY = 0x18057 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS = 0x18058 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK = 0x18059 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL = 0x1805a # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 = 0x1805b # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 = 0x1805c # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 = 0x1805d # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 = 0x1805e # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 = 0x18062 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 = 0x18063 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 = 0x18064 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 = 0x18065 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST = 0x180ca # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP = 0x180cb # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL = 0x180cb # macro +regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID = 0x18400 # macro +regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID = 0x18400 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_COMMAND = 0x18401 # macro +regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_STATUS = 0x18401 # macro +regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID = 0x18402 # macro +regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE = 0x18402 # macro +regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS = 0x18402 # macro +regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS = 0x18402 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE = 0x18403 # macro +regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_LATENCY = 0x18403 # macro +regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_HEADER = 0x18403 # macro +regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BIST = 0x18403 # macro +regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 = 0x18404 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 = 0x18405 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 = 0x18406 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 = 0x18407 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 = 0x18408 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 = 0x18409 # macro +regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR = 0x1840a # macro +regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID = 0x1840b # macro +regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR = 0x1840c # macro +regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR = 0x1840d # macro +regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE = 0x1840f # macro +regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN = 0x1840f # macro +regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT = 0x1840f # macro +regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY = 0x1840f # macro +regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST = 0x18419 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP = 0x18419 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP = 0x1841a # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL = 0x1841b # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS = 0x1841b # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP = 0x1841c # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL = 0x1841d # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS = 0x1841d # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 = 0x18422 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 = 0x18423 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 = 0x18423 # macro +regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 = 0x18424 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 = 0x18425 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 = 0x18425 # macro +regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST = 0x18428 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL = 0x18428 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO = 0x18429 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI = 0x1842a # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA = 0x1842a # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA = 0x1842a # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK = 0x1842b # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 = 0x1842b # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 = 0x1842b # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 = 0x1842c # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING = 0x1842c # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 = 0x1842d # macro +regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST = 0x18430 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL = 0x18430 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE = 0x18431 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA = 0x18432 # macro +regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x18440 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR = 0x18441 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 = 0x18442 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 = 0x18443 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x18454 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS = 0x18455 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK = 0x18456 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY = 0x18457 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS = 0x18458 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK = 0x18459 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL = 0x1845a # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 = 0x1845b # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 = 0x1845c # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 = 0x1845d # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 = 0x1845e # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 = 0x18462 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 = 0x18463 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 = 0x18464 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 = 0x18465 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST = 0x184ca # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP = 0x184cb # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL = 0x184cb # macro +regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID = 0x18800 # macro +regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID = 0x18800 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_COMMAND = 0x18801 # macro +regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_STATUS = 0x18801 # macro +regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID = 0x18802 # macro +regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE = 0x18802 # macro +regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS = 0x18802 # macro +regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS = 0x18802 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE = 0x18803 # macro +regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_LATENCY = 0x18803 # macro +regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_HEADER = 0x18803 # macro +regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BIST = 0x18803 # macro +regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 = 0x18804 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 = 0x18805 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 = 0x18806 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 = 0x18807 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 = 0x18808 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 = 0x18809 # macro +regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR = 0x1880a # macro +regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID = 0x1880b # macro +regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR = 0x1880c # macro +regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR = 0x1880d # macro +regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE = 0x1880f # macro +regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN = 0x1880f # macro +regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT = 0x1880f # macro +regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY = 0x1880f # macro +regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST = 0x18819 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP = 0x18819 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP = 0x1881a # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL = 0x1881b # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS = 0x1881b # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP = 0x1881c # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL = 0x1881d # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS = 0x1881d # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 = 0x18822 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 = 0x18823 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 = 0x18823 # macro +regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 = 0x18824 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 = 0x18825 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 = 0x18825 # macro +regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST = 0x18828 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL = 0x18828 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO = 0x18829 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI = 0x1882a # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA = 0x1882a # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA = 0x1882a # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK = 0x1882b # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 = 0x1882b # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 = 0x1882b # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 = 0x1882c # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING = 0x1882c # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 = 0x1882d # macro +regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST = 0x18830 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL = 0x18830 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE = 0x18831 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA = 0x18832 # macro +regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x18840 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR = 0x18841 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 = 0x18842 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 = 0x18843 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x18854 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS = 0x18855 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK = 0x18856 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY = 0x18857 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS = 0x18858 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK = 0x18859 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL = 0x1885a # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 = 0x1885b # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 = 0x1885c # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 = 0x1885d # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 = 0x1885e # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 = 0x18862 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 = 0x18863 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 = 0x18864 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 = 0x18865 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST = 0x188ca # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP = 0x188cb # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL = 0x188cb # macro +regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID = 0x18c00 # macro +regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID = 0x18c00 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_COMMAND = 0x18c01 # macro +regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_STATUS = 0x18c01 # macro +regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID = 0x18c02 # macro +regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE = 0x18c02 # macro +regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS = 0x18c02 # macro +regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS = 0x18c02 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE = 0x18c03 # macro +regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_LATENCY = 0x18c03 # macro +regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_HEADER = 0x18c03 # macro +regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BIST = 0x18c03 # macro +regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 = 0x18c04 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 = 0x18c05 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 = 0x18c06 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 = 0x18c07 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 = 0x18c08 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 = 0x18c09 # macro +regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR = 0x18c0a # macro +regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID = 0x18c0b # macro +regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR = 0x18c0c # macro +regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR = 0x18c0d # macro +regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE = 0x18c0f # macro +regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN = 0x18c0f # macro +regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT = 0x18c0f # macro +regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY = 0x18c0f # macro +regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST = 0x18c19 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP = 0x18c19 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP = 0x18c1a # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL = 0x18c1b # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS = 0x18c1b # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP = 0x18c1c # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL = 0x18c1d # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS = 0x18c1d # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 = 0x18c22 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 = 0x18c23 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 = 0x18c23 # macro +regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 = 0x18c24 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 = 0x18c25 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 = 0x18c25 # macro +regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST = 0x18c28 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL = 0x18c28 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO = 0x18c29 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI = 0x18c2a # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA = 0x18c2a # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA = 0x18c2a # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK = 0x18c2b # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 = 0x18c2b # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 = 0x18c2b # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 = 0x18c2c # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING = 0x18c2c # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 = 0x18c2d # macro +regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST = 0x18c30 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL = 0x18c30 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE = 0x18c31 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA = 0x18c32 # macro +regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x18c40 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR = 0x18c41 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 = 0x18c42 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 = 0x18c43 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x18c54 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS = 0x18c55 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK = 0x18c56 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY = 0x18c57 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS = 0x18c58 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK = 0x18c59 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL = 0x18c5a # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 = 0x18c5b # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 = 0x18c5c # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 = 0x18c5d # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 = 0x18c5e # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 = 0x18c62 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 = 0x18c63 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 = 0x18c64 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 = 0x18c65 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST = 0x18cca # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP = 0x18ccb # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL = 0x18ccb # macro +regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID = 0x19000 # macro +regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID = 0x19000 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_COMMAND = 0x19001 # macro +regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_STATUS = 0x19001 # macro +regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID = 0x19002 # macro +regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE = 0x19002 # macro +regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS = 0x19002 # macro +regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS = 0x19002 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE = 0x19003 # macro +regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_LATENCY = 0x19003 # macro +regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_HEADER = 0x19003 # macro +regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BIST = 0x19003 # macro +regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 = 0x19004 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 = 0x19005 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 = 0x19006 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 = 0x19007 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 = 0x19008 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 = 0x19009 # macro +regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR = 0x1900a # macro +regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID = 0x1900b # macro +regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR = 0x1900c # macro +regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR = 0x1900d # macro +regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE = 0x1900f # macro +regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN = 0x1900f # macro +regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT = 0x1900f # macro +regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY = 0x1900f # macro +regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST = 0x19019 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP = 0x19019 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP = 0x1901a # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL = 0x1901b # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS = 0x1901b # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP = 0x1901c # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL = 0x1901d # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS = 0x1901d # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 = 0x19022 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 = 0x19023 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 = 0x19023 # macro +regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 = 0x19024 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 = 0x19025 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 = 0x19025 # macro +regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST = 0x19028 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL = 0x19028 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO = 0x19029 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI = 0x1902a # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA = 0x1902a # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA = 0x1902a # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK = 0x1902b # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 = 0x1902b # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 = 0x1902b # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 = 0x1902c # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING = 0x1902c # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 = 0x1902d # macro +regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST = 0x19030 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL = 0x19030 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE = 0x19031 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA = 0x19032 # macro +regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x19040 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR = 0x19041 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 = 0x19042 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 = 0x19043 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x19054 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS = 0x19055 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK = 0x19056 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY = 0x19057 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS = 0x19058 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK = 0x19059 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL = 0x1905a # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 = 0x1905b # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 = 0x1905c # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 = 0x1905d # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 = 0x1905e # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 = 0x19062 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 = 0x19063 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 = 0x19064 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 = 0x19065 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST = 0x190ca # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP = 0x190cb # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL = 0x190cb # macro +regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID = 0x19400 # macro +regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID = 0x19400 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_COMMAND = 0x19401 # macro +regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_STATUS = 0x19401 # macro +regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID = 0x19402 # macro +regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE = 0x19402 # macro +regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS = 0x19402 # macro +regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS = 0x19402 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE = 0x19403 # macro +regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_LATENCY = 0x19403 # macro +regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_HEADER = 0x19403 # macro +regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BIST = 0x19403 # macro +regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 = 0x19404 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 = 0x19405 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 = 0x19406 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 = 0x19407 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 = 0x19408 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 = 0x19409 # macro +regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR = 0x1940a # macro +regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID = 0x1940b # macro +regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR = 0x1940c # macro +regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR = 0x1940d # macro +regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE = 0x1940f # macro +regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN = 0x1940f # macro +regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT = 0x1940f # macro +regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY = 0x1940f # macro +regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST = 0x19419 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP = 0x19419 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP = 0x1941a # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL = 0x1941b # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS = 0x1941b # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP = 0x1941c # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL = 0x1941d # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS = 0x1941d # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 = 0x19422 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 = 0x19423 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 = 0x19423 # macro +regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 = 0x19424 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 = 0x19425 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 = 0x19425 # macro +regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST = 0x19428 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL = 0x19428 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO = 0x19429 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI = 0x1942a # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA = 0x1942a # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA = 0x1942a # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK = 0x1942b # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 = 0x1942b # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 = 0x1942b # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 = 0x1942c # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING = 0x1942c # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 = 0x1942d # macro +regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST = 0x19430 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL = 0x19430 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE = 0x19431 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA = 0x19432 # macro +regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x19440 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR = 0x19441 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 = 0x19442 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 = 0x19443 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x19454 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS = 0x19455 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK = 0x19456 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY = 0x19457 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS = 0x19458 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK = 0x19459 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL = 0x1945a # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 = 0x1945b # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 = 0x1945c # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 = 0x1945d # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 = 0x1945e # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 = 0x19462 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 = 0x19463 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 = 0x19464 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 = 0x19465 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST = 0x194ca # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP = 0x194cb # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL = 0x194cb # macro +regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID = 0x19800 # macro +regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID = 0x19800 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_COMMAND = 0x19801 # macro +regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_STATUS = 0x19801 # macro +regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID = 0x19802 # macro +regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE = 0x19802 # macro +regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS = 0x19802 # macro +regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS = 0x19802 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE = 0x19803 # macro +regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_LATENCY = 0x19803 # macro +regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_HEADER = 0x19803 # macro +regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BIST = 0x19803 # macro +regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 = 0x19804 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 = 0x19805 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 = 0x19806 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 = 0x19807 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 = 0x19808 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 = 0x19809 # macro +regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR = 0x1980a # macro +regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID = 0x1980b # macro +regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR = 0x1980c # macro +regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR = 0x1980d # macro +regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE = 0x1980f # macro +regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN = 0x1980f # macro +regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT = 0x1980f # macro +regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY = 0x1980f # macro +regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST = 0x19819 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP = 0x19819 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP = 0x1981a # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL = 0x1981b # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS = 0x1981b # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP = 0x1981c # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL = 0x1981d # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS = 0x1981d # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 = 0x19822 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 = 0x19823 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 = 0x19823 # macro +regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 = 0x19824 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 = 0x19825 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 = 0x19825 # macro +regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST = 0x19828 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL = 0x19828 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO = 0x19829 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI = 0x1982a # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA = 0x1982a # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA = 0x1982a # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK = 0x1982b # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 = 0x1982b # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 = 0x1982b # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 = 0x1982c # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING = 0x1982c # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 = 0x1982d # macro +regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST = 0x19830 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL = 0x19830 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE = 0x19831 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA = 0x19832 # macro +regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x19840 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR = 0x19841 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 = 0x19842 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 = 0x19843 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x19854 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS = 0x19855 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK = 0x19856 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY = 0x19857 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS = 0x19858 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK = 0x19859 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL = 0x1985a # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 = 0x1985b # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 = 0x1985c # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 = 0x1985d # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 = 0x1985e # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 = 0x19862 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 = 0x19863 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 = 0x19864 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 = 0x19865 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST = 0x198ca # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP = 0x198cb # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL = 0x198cb # macro +regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID = 0x19c00 # macro +regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID = 0x19c00 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_COMMAND = 0x19c01 # macro +regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_STATUS = 0x19c01 # macro +regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID = 0x19c02 # macro +regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE = 0x19c02 # macro +regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS = 0x19c02 # macro +regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS = 0x19c02 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE = 0x19c03 # macro +regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_LATENCY = 0x19c03 # macro +regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_HEADER = 0x19c03 # macro +regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BIST = 0x19c03 # macro +regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 = 0x19c04 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 = 0x19c05 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 = 0x19c06 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 = 0x19c07 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 = 0x19c08 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 = 0x19c09 # macro +regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR = 0x19c0a # macro +regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID = 0x19c0b # macro +regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR = 0x19c0c # macro +regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR = 0x19c0d # macro +regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE = 0x19c0f # macro +regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN = 0x19c0f # macro +regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT = 0x19c0f # macro +regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY = 0x19c0f # macro +regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST = 0x19c19 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP = 0x19c19 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP = 0x19c1a # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL = 0x19c1b # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS = 0x19c1b # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP = 0x19c1c # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL = 0x19c1d # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS = 0x19c1d # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 = 0x19c22 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 = 0x19c23 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 = 0x19c23 # macro +regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 = 0x19c24 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 = 0x19c25 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 = 0x19c25 # macro +regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST = 0x19c28 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL = 0x19c28 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO = 0x19c29 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI = 0x19c2a # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA = 0x19c2a # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA = 0x19c2a # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK = 0x19c2b # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 = 0x19c2b # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 = 0x19c2b # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 = 0x19c2c # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING = 0x19c2c # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 = 0x19c2d # macro +regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST = 0x19c30 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL = 0x19c30 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE = 0x19c31 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA = 0x19c32 # macro +regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x19c40 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR = 0x19c41 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 = 0x19c42 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 = 0x19c43 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x19c54 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS = 0x19c55 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK = 0x19c56 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY = 0x19c57 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS = 0x19c58 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK = 0x19c59 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL = 0x19c5a # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 = 0x19c5b # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 = 0x19c5c # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 = 0x19c5d # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 = 0x19c5e # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 = 0x19c62 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 = 0x19c63 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 = 0x19c64 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 = 0x19c65 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST = 0x19cca # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP = 0x19ccb # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL = 0x19ccb # macro +regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID = 0x1a000 # macro +regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID = 0x1a000 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_COMMAND = 0x1a001 # macro +regBIF_CFG_DEV0_EPF0_VF8_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_STATUS = 0x1a001 # macro +regBIF_CFG_DEV0_EPF0_VF8_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID = 0x1a002 # macro +regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE = 0x1a002 # macro +regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS = 0x1a002 # macro +regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS = 0x1a002 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE = 0x1a003 # macro +regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_LATENCY = 0x1a003 # macro +regBIF_CFG_DEV0_EPF0_VF8_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_HEADER = 0x1a003 # macro +regBIF_CFG_DEV0_EPF0_VF8_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BIST = 0x1a003 # macro +regBIF_CFG_DEV0_EPF0_VF8_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1 = 0x1a004 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2 = 0x1a005 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3 = 0x1a006 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4 = 0x1a007 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5 = 0x1a008 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6 = 0x1a009 # macro +regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR = 0x1a00a # macro +regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID = 0x1a00b # macro +regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR = 0x1a00c # macro +regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR = 0x1a00d # macro +regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE = 0x1a00f # macro +regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN = 0x1a00f # macro +regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT = 0x1a00f # macro +regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY = 0x1a00f # macro +regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST = 0x1a019 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP = 0x1a019 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP = 0x1a01a # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL = 0x1a01b # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS = 0x1a01b # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP = 0x1a01c # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL = 0x1a01d # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS = 0x1a01d # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2 = 0x1a022 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2 = 0x1a023 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2 = 0x1a023 # macro +regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2 = 0x1a024 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2 = 0x1a025 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2 = 0x1a025 # macro +regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST = 0x1a028 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL = 0x1a028 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO = 0x1a029 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI = 0x1a02a # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA = 0x1a02a # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA = 0x1a02a # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK = 0x1a02b # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64 = 0x1a02b # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64 = 0x1a02b # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64 = 0x1a02c # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING = 0x1a02c # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64 = 0x1a02d # macro +regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST = 0x1a030 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL = 0x1a030 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE = 0x1a031 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA = 0x1a032 # macro +regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1a040 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR = 0x1a041 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1 = 0x1a042 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2 = 0x1a043 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1a054 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS = 0x1a055 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK = 0x1a056 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY = 0x1a057 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS = 0x1a058 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK = 0x1a059 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL = 0x1a05a # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0 = 0x1a05b # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1 = 0x1a05c # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2 = 0x1a05d # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3 = 0x1a05e # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0 = 0x1a062 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1 = 0x1a063 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2 = 0x1a064 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3 = 0x1a065 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST = 0x1a0ca # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP = 0x1a0cb # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL = 0x1a0cb # macro +regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID = 0x1a400 # macro +regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID = 0x1a400 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_COMMAND = 0x1a401 # macro +regBIF_CFG_DEV0_EPF0_VF9_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_STATUS = 0x1a401 # macro +regBIF_CFG_DEV0_EPF0_VF9_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID = 0x1a402 # macro +regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE = 0x1a402 # macro +regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS = 0x1a402 # macro +regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS = 0x1a402 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE = 0x1a403 # macro +regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_LATENCY = 0x1a403 # macro +regBIF_CFG_DEV0_EPF0_VF9_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_HEADER = 0x1a403 # macro +regBIF_CFG_DEV0_EPF0_VF9_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BIST = 0x1a403 # macro +regBIF_CFG_DEV0_EPF0_VF9_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1 = 0x1a404 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2 = 0x1a405 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3 = 0x1a406 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4 = 0x1a407 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5 = 0x1a408 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6 = 0x1a409 # macro +regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR = 0x1a40a # macro +regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID = 0x1a40b # macro +regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR = 0x1a40c # macro +regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR = 0x1a40d # macro +regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE = 0x1a40f # macro +regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN = 0x1a40f # macro +regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT = 0x1a40f # macro +regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY = 0x1a40f # macro +regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST = 0x1a419 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP = 0x1a419 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP = 0x1a41a # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL = 0x1a41b # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS = 0x1a41b # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP = 0x1a41c # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL = 0x1a41d # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS = 0x1a41d # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2 = 0x1a422 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2 = 0x1a423 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2 = 0x1a423 # macro +regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2 = 0x1a424 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2 = 0x1a425 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2 = 0x1a425 # macro +regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST = 0x1a428 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL = 0x1a428 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO = 0x1a429 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI = 0x1a42a # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA = 0x1a42a # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA = 0x1a42a # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK = 0x1a42b # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64 = 0x1a42b # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64 = 0x1a42b # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64 = 0x1a42c # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING = 0x1a42c # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64 = 0x1a42d # macro +regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST = 0x1a430 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL = 0x1a430 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE = 0x1a431 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA = 0x1a432 # macro +regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1a440 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR = 0x1a441 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1 = 0x1a442 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2 = 0x1a443 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1a454 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS = 0x1a455 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK = 0x1a456 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY = 0x1a457 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS = 0x1a458 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK = 0x1a459 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL = 0x1a45a # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0 = 0x1a45b # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1 = 0x1a45c # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2 = 0x1a45d # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3 = 0x1a45e # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0 = 0x1a462 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1 = 0x1a463 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2 = 0x1a464 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3 = 0x1a465 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST = 0x1a4ca # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP = 0x1a4cb # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL = 0x1a4cb # macro +regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID = 0x1a800 # macro +regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID = 0x1a800 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_COMMAND = 0x1a801 # macro +regBIF_CFG_DEV0_EPF0_VF10_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_STATUS = 0x1a801 # macro +regBIF_CFG_DEV0_EPF0_VF10_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID = 0x1a802 # macro +regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE = 0x1a802 # macro +regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS = 0x1a802 # macro +regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS = 0x1a802 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE = 0x1a803 # macro +regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_LATENCY = 0x1a803 # macro +regBIF_CFG_DEV0_EPF0_VF10_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_HEADER = 0x1a803 # macro +regBIF_CFG_DEV0_EPF0_VF10_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BIST = 0x1a803 # macro +regBIF_CFG_DEV0_EPF0_VF10_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1 = 0x1a804 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2 = 0x1a805 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3 = 0x1a806 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4 = 0x1a807 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5 = 0x1a808 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6 = 0x1a809 # macro +regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR = 0x1a80a # macro +regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID = 0x1a80b # macro +regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR = 0x1a80c # macro +regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR = 0x1a80d # macro +regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE = 0x1a80f # macro +regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN = 0x1a80f # macro +regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT = 0x1a80f # macro +regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY = 0x1a80f # macro +regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST = 0x1a819 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP = 0x1a819 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP = 0x1a81a # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL = 0x1a81b # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS = 0x1a81b # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP = 0x1a81c # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL = 0x1a81d # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS = 0x1a81d # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2 = 0x1a822 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2 = 0x1a823 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2 = 0x1a823 # macro +regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2 = 0x1a824 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2 = 0x1a825 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2 = 0x1a825 # macro +regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST = 0x1a828 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL = 0x1a828 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO = 0x1a829 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI = 0x1a82a # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA = 0x1a82a # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA = 0x1a82a # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK = 0x1a82b # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64 = 0x1a82b # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64 = 0x1a82b # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64 = 0x1a82c # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING = 0x1a82c # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64 = 0x1a82d # macro +regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST = 0x1a830 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL = 0x1a830 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE = 0x1a831 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA = 0x1a832 # macro +regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1a840 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR = 0x1a841 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1 = 0x1a842 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2 = 0x1a843 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1a854 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS = 0x1a855 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK = 0x1a856 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY = 0x1a857 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS = 0x1a858 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK = 0x1a859 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL = 0x1a85a # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0 = 0x1a85b # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1 = 0x1a85c # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2 = 0x1a85d # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3 = 0x1a85e # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0 = 0x1a862 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1 = 0x1a863 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2 = 0x1a864 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3 = 0x1a865 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST = 0x1a8ca # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP = 0x1a8cb # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL = 0x1a8cb # macro +regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID = 0x1ac00 # macro +regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID = 0x1ac00 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_COMMAND = 0x1ac01 # macro +regBIF_CFG_DEV0_EPF0_VF11_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_STATUS = 0x1ac01 # macro +regBIF_CFG_DEV0_EPF0_VF11_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID = 0x1ac02 # macro +regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE = 0x1ac02 # macro +regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS = 0x1ac02 # macro +regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS = 0x1ac02 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE = 0x1ac03 # macro +regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_LATENCY = 0x1ac03 # macro +regBIF_CFG_DEV0_EPF0_VF11_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_HEADER = 0x1ac03 # macro +regBIF_CFG_DEV0_EPF0_VF11_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BIST = 0x1ac03 # macro +regBIF_CFG_DEV0_EPF0_VF11_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1 = 0x1ac04 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2 = 0x1ac05 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3 = 0x1ac06 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4 = 0x1ac07 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5 = 0x1ac08 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6 = 0x1ac09 # macro +regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR = 0x1ac0a # macro +regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID = 0x1ac0b # macro +regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR = 0x1ac0c # macro +regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR = 0x1ac0d # macro +regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE = 0x1ac0f # macro +regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN = 0x1ac0f # macro +regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT = 0x1ac0f # macro +regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY = 0x1ac0f # macro +regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST = 0x1ac19 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP = 0x1ac19 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP = 0x1ac1a # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL = 0x1ac1b # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS = 0x1ac1b # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP = 0x1ac1c # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL = 0x1ac1d # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS = 0x1ac1d # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2 = 0x1ac22 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2 = 0x1ac23 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2 = 0x1ac23 # macro +regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2 = 0x1ac24 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2 = 0x1ac25 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2 = 0x1ac25 # macro +regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST = 0x1ac28 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL = 0x1ac28 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO = 0x1ac29 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI = 0x1ac2a # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA = 0x1ac2a # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA = 0x1ac2a # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK = 0x1ac2b # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64 = 0x1ac2b # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64 = 0x1ac2b # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64 = 0x1ac2c # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING = 0x1ac2c # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64 = 0x1ac2d # macro +regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST = 0x1ac30 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL = 0x1ac30 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE = 0x1ac31 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA = 0x1ac32 # macro +regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1ac40 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR = 0x1ac41 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1 = 0x1ac42 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2 = 0x1ac43 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1ac54 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS = 0x1ac55 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK = 0x1ac56 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY = 0x1ac57 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS = 0x1ac58 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK = 0x1ac59 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL = 0x1ac5a # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0 = 0x1ac5b # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1 = 0x1ac5c # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2 = 0x1ac5d # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3 = 0x1ac5e # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0 = 0x1ac62 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1 = 0x1ac63 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2 = 0x1ac64 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3 = 0x1ac65 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST = 0x1acca # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP = 0x1accb # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL = 0x1accb # macro +regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID = 0x1b000 # macro +regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID = 0x1b000 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_COMMAND = 0x1b001 # macro +regBIF_CFG_DEV0_EPF0_VF12_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_STATUS = 0x1b001 # macro +regBIF_CFG_DEV0_EPF0_VF12_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID = 0x1b002 # macro +regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE = 0x1b002 # macro +regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS = 0x1b002 # macro +regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS = 0x1b002 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE = 0x1b003 # macro +regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_LATENCY = 0x1b003 # macro +regBIF_CFG_DEV0_EPF0_VF12_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_HEADER = 0x1b003 # macro +regBIF_CFG_DEV0_EPF0_VF12_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BIST = 0x1b003 # macro +regBIF_CFG_DEV0_EPF0_VF12_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1 = 0x1b004 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2 = 0x1b005 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3 = 0x1b006 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4 = 0x1b007 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5 = 0x1b008 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6 = 0x1b009 # macro +regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR = 0x1b00a # macro +regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID = 0x1b00b # macro +regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR = 0x1b00c # macro +regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR = 0x1b00d # macro +regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE = 0x1b00f # macro +regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN = 0x1b00f # macro +regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT = 0x1b00f # macro +regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY = 0x1b00f # macro +regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST = 0x1b019 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP = 0x1b019 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP = 0x1b01a # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL = 0x1b01b # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS = 0x1b01b # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP = 0x1b01c # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL = 0x1b01d # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS = 0x1b01d # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2 = 0x1b022 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2 = 0x1b023 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2 = 0x1b023 # macro +regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2 = 0x1b024 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2 = 0x1b025 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2 = 0x1b025 # macro +regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST = 0x1b028 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL = 0x1b028 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO = 0x1b029 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI = 0x1b02a # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA = 0x1b02a # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA = 0x1b02a # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK = 0x1b02b # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64 = 0x1b02b # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64 = 0x1b02b # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64 = 0x1b02c # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING = 0x1b02c # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64 = 0x1b02d # macro +regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST = 0x1b030 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL = 0x1b030 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE = 0x1b031 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA = 0x1b032 # macro +regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1b040 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR = 0x1b041 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1 = 0x1b042 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2 = 0x1b043 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1b054 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS = 0x1b055 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK = 0x1b056 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY = 0x1b057 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS = 0x1b058 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK = 0x1b059 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL = 0x1b05a # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0 = 0x1b05b # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1 = 0x1b05c # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2 = 0x1b05d # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3 = 0x1b05e # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0 = 0x1b062 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1 = 0x1b063 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2 = 0x1b064 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3 = 0x1b065 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST = 0x1b0ca # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP = 0x1b0cb # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL = 0x1b0cb # macro +regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID = 0x1b400 # macro +regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID = 0x1b400 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_COMMAND = 0x1b401 # macro +regBIF_CFG_DEV0_EPF0_VF13_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_STATUS = 0x1b401 # macro +regBIF_CFG_DEV0_EPF0_VF13_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID = 0x1b402 # macro +regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE = 0x1b402 # macro +regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS = 0x1b402 # macro +regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS = 0x1b402 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE = 0x1b403 # macro +regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_LATENCY = 0x1b403 # macro +regBIF_CFG_DEV0_EPF0_VF13_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_HEADER = 0x1b403 # macro +regBIF_CFG_DEV0_EPF0_VF13_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BIST = 0x1b403 # macro +regBIF_CFG_DEV0_EPF0_VF13_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1 = 0x1b404 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2 = 0x1b405 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3 = 0x1b406 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4 = 0x1b407 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5 = 0x1b408 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6 = 0x1b409 # macro +regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR = 0x1b40a # macro +regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID = 0x1b40b # macro +regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR = 0x1b40c # macro +regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR = 0x1b40d # macro +regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE = 0x1b40f # macro +regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN = 0x1b40f # macro +regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT = 0x1b40f # macro +regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY = 0x1b40f # macro +regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST = 0x1b419 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP = 0x1b419 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP = 0x1b41a # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL = 0x1b41b # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS = 0x1b41b # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP = 0x1b41c # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL = 0x1b41d # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS = 0x1b41d # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2 = 0x1b422 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2 = 0x1b423 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2 = 0x1b423 # macro +regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2 = 0x1b424 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2 = 0x1b425 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2 = 0x1b425 # macro +regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST = 0x1b428 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL = 0x1b428 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO = 0x1b429 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI = 0x1b42a # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA = 0x1b42a # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA = 0x1b42a # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK = 0x1b42b # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64 = 0x1b42b # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64 = 0x1b42b # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64 = 0x1b42c # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING = 0x1b42c # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64 = 0x1b42d # macro +regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST = 0x1b430 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL = 0x1b430 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE = 0x1b431 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA = 0x1b432 # macro +regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1b440 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR = 0x1b441 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1 = 0x1b442 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2 = 0x1b443 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1b454 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS = 0x1b455 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK = 0x1b456 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY = 0x1b457 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS = 0x1b458 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK = 0x1b459 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL = 0x1b45a # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0 = 0x1b45b # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1 = 0x1b45c # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2 = 0x1b45d # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3 = 0x1b45e # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0 = 0x1b462 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1 = 0x1b463 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2 = 0x1b464 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3 = 0x1b465 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST = 0x1b4ca # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP = 0x1b4cb # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL = 0x1b4cb # macro +regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID = 0x1b800 # macro +regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID = 0x1b800 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_COMMAND = 0x1b801 # macro +regBIF_CFG_DEV0_EPF0_VF14_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_STATUS = 0x1b801 # macro +regBIF_CFG_DEV0_EPF0_VF14_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID = 0x1b802 # macro +regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE = 0x1b802 # macro +regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS = 0x1b802 # macro +regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS = 0x1b802 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE = 0x1b803 # macro +regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_LATENCY = 0x1b803 # macro +regBIF_CFG_DEV0_EPF0_VF14_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_HEADER = 0x1b803 # macro +regBIF_CFG_DEV0_EPF0_VF14_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BIST = 0x1b803 # macro +regBIF_CFG_DEV0_EPF0_VF14_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1 = 0x1b804 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2 = 0x1b805 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3 = 0x1b806 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4 = 0x1b807 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5 = 0x1b808 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6 = 0x1b809 # macro +regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR = 0x1b80a # macro +regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID = 0x1b80b # macro +regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR = 0x1b80c # macro +regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR = 0x1b80d # macro +regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE = 0x1b80f # macro +regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN = 0x1b80f # macro +regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT = 0x1b80f # macro +regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY = 0x1b80f # macro +regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST = 0x1b819 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP = 0x1b819 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP = 0x1b81a # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL = 0x1b81b # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS = 0x1b81b # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP = 0x1b81c # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL = 0x1b81d # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS = 0x1b81d # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2 = 0x1b822 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2 = 0x1b823 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2 = 0x1b823 # macro +regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2 = 0x1b824 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2 = 0x1b825 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2 = 0x1b825 # macro +regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST = 0x1b828 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL = 0x1b828 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO = 0x1b829 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI = 0x1b82a # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA = 0x1b82a # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA = 0x1b82a # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK = 0x1b82b # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64 = 0x1b82b # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64 = 0x1b82b # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64 = 0x1b82c # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING = 0x1b82c # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64 = 0x1b82d # macro +regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST = 0x1b830 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL = 0x1b830 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE = 0x1b831 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA = 0x1b832 # macro +regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1b840 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR = 0x1b841 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1 = 0x1b842 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2 = 0x1b843 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1b854 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS = 0x1b855 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK = 0x1b856 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY = 0x1b857 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS = 0x1b858 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK = 0x1b859 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL = 0x1b85a # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0 = 0x1b85b # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1 = 0x1b85c # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2 = 0x1b85d # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3 = 0x1b85e # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0 = 0x1b862 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1 = 0x1b863 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2 = 0x1b864 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3 = 0x1b865 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST = 0x1b8ca # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP = 0x1b8cb # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL = 0x1b8cb # macro +regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID = 0x1bc00 # macro +regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID = 0x1bc00 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_COMMAND = 0x1bc01 # macro +regBIF_CFG_DEV0_EPF0_VF15_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_STATUS = 0x1bc01 # macro +regBIF_CFG_DEV0_EPF0_VF15_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID = 0x1bc02 # macro +regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE = 0x1bc02 # macro +regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS = 0x1bc02 # macro +regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS = 0x1bc02 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE = 0x1bc03 # macro +regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_LATENCY = 0x1bc03 # macro +regBIF_CFG_DEV0_EPF0_VF15_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_HEADER = 0x1bc03 # macro +regBIF_CFG_DEV0_EPF0_VF15_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BIST = 0x1bc03 # macro +regBIF_CFG_DEV0_EPF0_VF15_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1 = 0x1bc04 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2 = 0x1bc05 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3 = 0x1bc06 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4 = 0x1bc07 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5 = 0x1bc08 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6 = 0x1bc09 # macro +regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR = 0x1bc0a # macro +regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID = 0x1bc0b # macro +regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR = 0x1bc0c # macro +regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR = 0x1bc0d # macro +regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE = 0x1bc0f # macro +regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN = 0x1bc0f # macro +regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT = 0x1bc0f # macro +regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY = 0x1bc0f # macro +regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST = 0x1bc19 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP = 0x1bc19 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP = 0x1bc1a # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL = 0x1bc1b # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS = 0x1bc1b # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP = 0x1bc1c # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL = 0x1bc1d # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS = 0x1bc1d # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2 = 0x1bc22 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2 = 0x1bc23 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2 = 0x1bc23 # macro +regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2 = 0x1bc24 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2 = 0x1bc25 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2 = 0x1bc25 # macro +regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST = 0x1bc28 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL = 0x1bc28 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO = 0x1bc29 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI = 0x1bc2a # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA = 0x1bc2a # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA = 0x1bc2a # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK = 0x1bc2b # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64 = 0x1bc2b # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64 = 0x1bc2b # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64 = 0x1bc2c # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING = 0x1bc2c # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64 = 0x1bc2d # macro +regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST = 0x1bc30 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL = 0x1bc30 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE = 0x1bc31 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA = 0x1bc32 # macro +regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x1bc40 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR = 0x1bc41 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1 = 0x1bc42 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2 = 0x1bc43 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x1bc54 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS = 0x1bc55 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK = 0x1bc56 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY = 0x1bc57 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS = 0x1bc58 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK = 0x1bc59 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL = 0x1bc5a # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0 = 0x1bc5b # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1 = 0x1bc5c # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2 = 0x1bc5d # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3 = 0x1bc5e # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0 = 0x1bc62 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1 = 0x1bc63 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2 = 0x1bc64 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3 = 0x1bc65 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST = 0x1bcca # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP = 0x1bccb # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL = 0x1bccb # macro +regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_VENDOR_ID = 0x10400 # macro +regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_ID = 0x10400 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_COMMAND = 0x10401 # macro +regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_STATUS = 0x10401 # macro +regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_REVISION_ID = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PROG_INTERFACE = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_SUB_CLASS = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BASE_CLASS = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_CACHE_LINE = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_LATENCY = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_HEADER = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BIST = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 = 0x10404 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 = 0x10405 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 = 0x10406 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 = 0x10407 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 = 0x10408 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 = 0x10409 # macro +regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR = 0x1040a # macro +regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_ADAPTER_ID = 0x1040b # macro +regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR = 0x1040c # macro +regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_CAP_PTR = 0x1040d # macro +regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MIN_GRANT = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MAX_LATENCY = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST = 0x10412 # macro +regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W = 0x10413 # macro +regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST = 0x10414 # macro +regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PMI_CAP = 0x10414 # macro +regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL = 0x10415 # macro +regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST = 0x10419 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CAP = 0x10419 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CAP = 0x1041a # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CNTL = 0x1041b # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_STATUS = 0x1041b # macro +regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_LINK_CAP = 0x1041c # macro +regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_LINK_CNTL = 0x1041d # macro +regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_LINK_STATUS = 0x1041d # macro +regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 = 0x10422 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 = 0x10423 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 = 0x10423 # macro +regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_LINK_CAP2 = 0x10424 # macro +regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_LINK_CNTL2 = 0x10425 # macro +regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_LINK_STATUS2 = 0x10425 # macro +regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST = 0x10428 # macro +regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL = 0x10428 # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO = 0x10429 # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI = 0x1042a # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA = 0x1042a # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA = 0x1042a # macro +regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_MASK = 0x1042b # macro +regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 = 0x1042b # macro +regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 = 0x1042b # macro +regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_MASK_64 = 0x1042c # macro +regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_PENDING = 0x1042c # macro +regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 = 0x1042d # macro +regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST = 0x10430 # macro +regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL = 0x10430 # macro +regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSIX_TABLE = 0x10431 # macro +regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_MSIX_PBA = 0x10432 # macro +regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x10440 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR = 0x10441 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 = 0x10442 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 = 0x10443 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x10450 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 = 0x10451 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 = 0x10452 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x10454 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS = 0x10455 # macro +regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK = 0x10456 # macro +regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY = 0x10457 # macro +regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS = 0x10458 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK = 0x10459 # macro +regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL = 0x1045a # macro +regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 = 0x1045b # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 = 0x1045c # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 = 0x1045d # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 = 0x1045e # macro +regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 = 0x10462 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 = 0x10463 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 = 0x10464 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 = 0x10465 # macro +regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST = 0x10480 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP = 0x10481 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL = 0x10482 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP = 0x10483 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL = 0x10484 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP = 0x10485 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL = 0x10486 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP = 0x10487 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL = 0x10488 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP = 0x10489 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL = 0x1048a # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP = 0x1048b # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL = 0x1048c # macro +regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x10490 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT = 0x10491 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA = 0x10492 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP = 0x10493 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST = 0x10494 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP = 0x10495 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR = 0x10496 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS = 0x10497 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL = 0x10497 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST = 0x1049c # macro +regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 = 0x1049d # macro +regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS = 0x1049e # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL = 0x1049f # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL = 0x1049f # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL = 0x104a0 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL = 0x104a0 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL = 0x104a1 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL = 0x104a1 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL = 0x104a2 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL = 0x104a2 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL = 0x104a3 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL = 0x104a3 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL = 0x104a4 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL = 0x104a4 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL = 0x104a5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL = 0x104a5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL = 0x104a6 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL = 0x104a6 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST = 0x104a8 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP = 0x104a9 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL = 0x104a9 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST = 0x104b4 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP = 0x104b5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL = 0x104b5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST = 0x104bc # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP = 0x104bd # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL = 0x104bd # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 = 0x104be # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 = 0x104bf # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 = 0x104c0 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 = 0x104c1 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 = 0x104c2 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 = 0x104c3 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0x104c4 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0x104c5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST = 0x104c8 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP = 0x104c9 # macro +regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST = 0x104ca # macro +regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP = 0x104cb # macro +regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL = 0x104cb # macro +regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST = 0x104cc # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP = 0x104cd # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL = 0x104ce # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS = 0x104ce # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS = 0x104cf # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS = 0x104cf # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS = 0x104d0 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK = 0x104d0 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET = 0x104d1 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE = 0x104d1 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID = 0x104d2 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0x104d3 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE = 0x104d4 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 = 0x104d5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 = 0x104d6 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 = 0x104d7 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 = 0x104d8 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 = 0x104d9 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 = 0x104da # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0x104db # macro +regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST = 0x10530 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP = 0x10531 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL = 0x10532 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP = 0x10533 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL = 0x10534 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP = 0x10535 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL = 0x10536 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP = 0x10537 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL = 0x10538 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP = 0x10539 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL = 0x1053a # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP = 0x1053b # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL = 0x1053c # macro +regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_VENDOR_ID = 0x10800 # macro +regBIF_CFG_DEV0_EPF2_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_ID = 0x10800 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_COMMAND = 0x10801 # macro +regBIF_CFG_DEV0_EPF2_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_STATUS = 0x10801 # macro +regBIF_CFG_DEV0_EPF2_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_REVISION_ID = 0x10802 # macro +regBIF_CFG_DEV0_EPF2_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PROG_INTERFACE = 0x10802 # macro +regBIF_CFG_DEV0_EPF2_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_SUB_CLASS = 0x10802 # macro +regBIF_CFG_DEV0_EPF2_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BASE_CLASS = 0x10802 # macro +regBIF_CFG_DEV0_EPF2_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_CACHE_LINE = 0x10803 # macro +regBIF_CFG_DEV0_EPF2_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_LATENCY = 0x10803 # macro +regBIF_CFG_DEV0_EPF2_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_HEADER = 0x10803 # macro +regBIF_CFG_DEV0_EPF2_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BIST = 0x10803 # macro +regBIF_CFG_DEV0_EPF2_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_1 = 0x10804 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_2 = 0x10805 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_3 = 0x10806 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_4 = 0x10807 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_5 = 0x10808 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_6 = 0x10809 # macro +regBIF_CFG_DEV0_EPF2_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR = 0x1080a # macro +regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_ADAPTER_ID = 0x1080b # macro +regBIF_CFG_DEV0_EPF2_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR = 0x1080c # macro +regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_CAP_PTR = 0x1080d # macro +regBIF_CFG_DEV0_EPF2_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE = 0x1080f # macro +regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN = 0x1080f # macro +regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MIN_GRANT = 0x1080f # macro +regBIF_CFG_DEV0_EPF2_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MAX_LATENCY = 0x1080f # macro +regBIF_CFG_DEV0_EPF2_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST = 0x10812 # macro +regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W = 0x10813 # macro +regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST = 0x10814 # macro +regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PMI_CAP = 0x10814 # macro +regBIF_CFG_DEV0_EPF2_PMI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL = 0x10815 # macro +regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_SBRN = 0x10818 # macro +regBIF_CFG_DEV0_EPF2_SBRN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_FLADJ = 0x10818 # macro +regBIF_CFG_DEV0_EPF2_FLADJ_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DBESL_DBESLD = 0x10818 # macro +regBIF_CFG_DEV0_EPF2_DBESL_DBESLD_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST = 0x10819 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CAP = 0x10819 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CAP = 0x1081a # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CNTL = 0x1081b # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_STATUS = 0x1081b # macro +regBIF_CFG_DEV0_EPF2_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_LINK_CAP = 0x1081c # macro +regBIF_CFG_DEV0_EPF2_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_LINK_CNTL = 0x1081d # macro +regBIF_CFG_DEV0_EPF2_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_LINK_STATUS = 0x1081d # macro +regBIF_CFG_DEV0_EPF2_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CAP2 = 0x10822 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 = 0x10823 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 = 0x10823 # macro +regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_LINK_CAP2 = 0x10824 # macro +regBIF_CFG_DEV0_EPF2_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_LINK_CNTL2 = 0x10825 # macro +regBIF_CFG_DEV0_EPF2_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_LINK_STATUS2 = 0x10825 # macro +regBIF_CFG_DEV0_EPF2_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST = 0x10828 # macro +regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL = 0x10828 # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO = 0x10829 # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI = 0x1082a # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA = 0x1082a # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA = 0x1082a # macro +regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_MASK = 0x1082b # macro +regBIF_CFG_DEV0_EPF2_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 = 0x1082b # macro +regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 = 0x1082b # macro +regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_MASK_64 = 0x1082c # macro +regBIF_CFG_DEV0_EPF2_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_PENDING = 0x1082c # macro +regBIF_CFG_DEV0_EPF2_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSI_PENDING_64 = 0x1082d # macro +regBIF_CFG_DEV0_EPF2_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST = 0x10830 # macro +regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL = 0x10830 # macro +regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSIX_TABLE = 0x10831 # macro +regBIF_CFG_DEV0_EPF2_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_MSIX_PBA = 0x10832 # macro +regBIF_CFG_DEV0_EPF2_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x10840 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR = 0x10841 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 = 0x10842 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 = 0x10843 # macro +regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x10854 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS = 0x10855 # macro +regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK = 0x10856 # macro +regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY = 0x10857 # macro +regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS = 0x10858 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK = 0x10859 # macro +regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL = 0x1085a # macro +regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 = 0x1085b # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 = 0x1085c # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 = 0x1085d # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 = 0x1085e # macro +regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 = 0x10862 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 = 0x10863 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 = 0x10864 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 = 0x10865 # macro +regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST = 0x10880 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP = 0x10881 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL = 0x10882 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP = 0x10883 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL = 0x10884 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP = 0x10885 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL = 0x10886 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP = 0x10887 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL = 0x10888 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP = 0x10889 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL = 0x1088a # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP = 0x1088b # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL = 0x1088c # macro +regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x10890 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT = 0x10891 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA = 0x10892 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP = 0x10893 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST = 0x10894 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP = 0x10895 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR = 0x10896 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS = 0x10897 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL = 0x10897 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x10898 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x10898 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x10898 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x10898 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x10899 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x10899 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x10899 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x10899 # macro +regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST = 0x108a8 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP = 0x108a9 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL = 0x108a9 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST = 0x108b4 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP = 0x108b5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL = 0x108b5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST = 0x108ca # macro +regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP = 0x108cb # macro +regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL = 0x108cb # macro +regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_VENDOR_ID = 0x10c00 # macro +regBIF_CFG_DEV0_EPF3_VENDOR_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_ID = 0x10c00 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_COMMAND = 0x10c01 # macro +regBIF_CFG_DEV0_EPF3_COMMAND_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_STATUS = 0x10c01 # macro +regBIF_CFG_DEV0_EPF3_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_REVISION_ID = 0x10c02 # macro +regBIF_CFG_DEV0_EPF3_REVISION_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PROG_INTERFACE = 0x10c02 # macro +regBIF_CFG_DEV0_EPF3_PROG_INTERFACE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_SUB_CLASS = 0x10c02 # macro +regBIF_CFG_DEV0_EPF3_SUB_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BASE_CLASS = 0x10c02 # macro +regBIF_CFG_DEV0_EPF3_BASE_CLASS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_CACHE_LINE = 0x10c03 # macro +regBIF_CFG_DEV0_EPF3_CACHE_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_LATENCY = 0x10c03 # macro +regBIF_CFG_DEV0_EPF3_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_HEADER = 0x10c03 # macro +regBIF_CFG_DEV0_EPF3_HEADER_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BIST = 0x10c03 # macro +regBIF_CFG_DEV0_EPF3_BIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_1 = 0x10c04 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_2 = 0x10c05 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_3 = 0x10c06 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_4 = 0x10c07 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_5 = 0x10c08 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_6 = 0x10c09 # macro +regBIF_CFG_DEV0_EPF3_BASE_ADDR_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR = 0x10c0a # macro +regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_ADAPTER_ID = 0x10c0b # macro +regBIF_CFG_DEV0_EPF3_ADAPTER_ID_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR = 0x10c0c # macro +regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_CAP_PTR = 0x10c0d # macro +regBIF_CFG_DEV0_EPF3_CAP_PTR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE = 0x10c0f # macro +regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN = 0x10c0f # macro +regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MIN_GRANT = 0x10c0f # macro +regBIF_CFG_DEV0_EPF3_MIN_GRANT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MAX_LATENCY = 0x10c0f # macro +regBIF_CFG_DEV0_EPF3_MAX_LATENCY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST = 0x10c12 # macro +regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W = 0x10c13 # macro +regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST = 0x10c14 # macro +regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PMI_CAP = 0x10c14 # macro +regBIF_CFG_DEV0_EPF3_PMI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL = 0x10c15 # macro +regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_SBRN = 0x10c18 # macro +regBIF_CFG_DEV0_EPF3_SBRN_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_FLADJ = 0x10c18 # macro +regBIF_CFG_DEV0_EPF3_FLADJ_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DBESL_DBESLD = 0x10c18 # macro +regBIF_CFG_DEV0_EPF3_DBESL_DBESLD_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST = 0x10c19 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CAP = 0x10c19 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CAP = 0x10c1a # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CNTL = 0x10c1b # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_STATUS = 0x10c1b # macro +regBIF_CFG_DEV0_EPF3_DEVICE_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_LINK_CAP = 0x10c1c # macro +regBIF_CFG_DEV0_EPF3_LINK_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_LINK_CNTL = 0x10c1d # macro +regBIF_CFG_DEV0_EPF3_LINK_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_LINK_STATUS = 0x10c1d # macro +regBIF_CFG_DEV0_EPF3_LINK_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CAP2 = 0x10c22 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 = 0x10c23 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 = 0x10c23 # macro +regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_LINK_CAP2 = 0x10c24 # macro +regBIF_CFG_DEV0_EPF3_LINK_CAP2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_LINK_CNTL2 = 0x10c25 # macro +regBIF_CFG_DEV0_EPF3_LINK_CNTL2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_LINK_STATUS2 = 0x10c25 # macro +regBIF_CFG_DEV0_EPF3_LINK_STATUS2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST = 0x10c28 # macro +regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL = 0x10c28 # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO = 0x10c29 # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI = 0x10c2a # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA = 0x10c2a # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA = 0x10c2a # macro +regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_MASK = 0x10c2b # macro +regBIF_CFG_DEV0_EPF3_MSI_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 = 0x10c2b # macro +regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 = 0x10c2b # macro +regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_MASK_64 = 0x10c2c # macro +regBIF_CFG_DEV0_EPF3_MSI_MASK_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_PENDING = 0x10c2c # macro +regBIF_CFG_DEV0_EPF3_MSI_PENDING_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSI_PENDING_64 = 0x10c2d # macro +regBIF_CFG_DEV0_EPF3_MSI_PENDING_64_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST = 0x10c30 # macro +regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL = 0x10c30 # macro +regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSIX_TABLE = 0x10c31 # macro +regBIF_CFG_DEV0_EPF3_MSIX_TABLE_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_MSIX_PBA = 0x10c32 # macro +regBIF_CFG_DEV0_EPF3_MSIX_PBA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x10c40 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR = 0x10c41 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 = 0x10c42 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 = 0x10c43 # macro +regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x10c54 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS = 0x10c55 # macro +regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK = 0x10c56 # macro +regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY = 0x10c57 # macro +regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS = 0x10c58 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK = 0x10c59 # macro +regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL = 0x10c5a # macro +regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 = 0x10c5b # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 = 0x10c5c # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 = 0x10c5d # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 = 0x10c5e # macro +regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 = 0x10c62 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 = 0x10c63 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 = 0x10c64 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 = 0x10c65 # macro +regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST = 0x10c80 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP = 0x10c81 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL = 0x10c82 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP = 0x10c83 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL = 0x10c84 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP = 0x10c85 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL = 0x10c86 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP = 0x10c87 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL = 0x10c88 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP = 0x10c89 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL = 0x10c8a # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP = 0x10c8b # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL = 0x10c8c # macro +regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x10c90 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT = 0x10c91 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA = 0x10c92 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP = 0x10c93 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST = 0x10c94 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP = 0x10c95 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR = 0x10c96 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS = 0x10c97 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL = 0x10c97 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x10c98 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x10c98 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x10c98 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x10c98 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x10c99 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x10c99 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x10c99 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x10c99 # macro +regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST = 0x10ca8 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP = 0x10ca9 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL = 0x10ca9 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST = 0x10cb4 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP = 0x10cb5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL = 0x10cb5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST = 0x10cca # macro +regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP = 0x10ccb # macro +regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_BASE_IDX = 5 # macro +regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL = 0x10ccb # macro +regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_VDM_SUPPORT = 0xc440 # macro +regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_BUS_CNTL = 0xc441 # macro +regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC = 0xc442 # macro +regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_DEV0_LINK_CNTL = 0xc443 # macro +regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CMN_LINK_CNTL = 0xc444 # macro +regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE = 0xc445 # macro +regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL = 0xc446 # macro +regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_MH_ARB_CNTL = 0xc447 # macro +regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 = 0xc448 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 = 0xc449 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_SCRATCH = 0xc44c # macro +regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_CNTL = 0xc44e # macro +regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL = 0xc44f # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS = 0xc450 # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 = 0xc451 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL = 0xc452 # macro +regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL = 0xc453 # macro +regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL = 0xc454 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC = 0xc455 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 = 0xc456 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP = 0xc457 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR = 0xc458 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL = 0xc458 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 = 0xc458 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 = 0xc45a # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 = 0xc45a # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 = 0xc45a # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL = 0xc45c # macro +regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIEP_RESERVED = 0xc45d # macro +regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL = 0xc45f # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID = 0xc460 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL = 0xc461 # macro +regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL = 0xc462 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL = 0xc463 # macro +regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_RESERVED = 0xc468 # macro +regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH = 0xc469 # macro +regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_CNTL = 0xc46b # macro +regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL = 0xc46c # macro +regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 = 0xc46d # macro +regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL = 0xc46e # macro +regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL = 0xc46f # macro +regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 = 0xc470 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC = 0xc471 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 = 0xc472 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL = 0xc475 # macro +regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_1_PCIE_RX_CNTL = 0xc476 # macro +regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL = 0xc477 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 = 0xc478 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC = 0xc479 # macro +regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP = 0xc47a # macro +regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX = 5 # macro +regPCIEMSIX_VECT0_ADDR_LO = 0x1c000 # macro +regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT0_ADDR_HI = 0x1c001 # macro +regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT0_MSG_DATA = 0x1c002 # macro +regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT0_CONTROL = 0x1c003 # macro +regPCIEMSIX_VECT0_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT1_ADDR_LO = 0x1c004 # macro +regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT1_ADDR_HI = 0x1c005 # macro +regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT1_MSG_DATA = 0x1c006 # macro +regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT1_CONTROL = 0x1c007 # macro +regPCIEMSIX_VECT1_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT2_ADDR_LO = 0x1c008 # macro +regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT2_ADDR_HI = 0x1c009 # macro +regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT2_MSG_DATA = 0x1c00a # macro +regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT2_CONTROL = 0x1c00b # macro +regPCIEMSIX_VECT2_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT3_ADDR_LO = 0x1c00c # macro +regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT3_ADDR_HI = 0x1c00d # macro +regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT3_MSG_DATA = 0x1c00e # macro +regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT3_CONTROL = 0x1c00f # macro +regPCIEMSIX_VECT3_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT4_ADDR_LO = 0x1c010 # macro +regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT4_ADDR_HI = 0x1c011 # macro +regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT4_MSG_DATA = 0x1c012 # macro +regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT4_CONTROL = 0x1c013 # macro +regPCIEMSIX_VECT4_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT5_ADDR_LO = 0x1c014 # macro +regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT5_ADDR_HI = 0x1c015 # macro +regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT5_MSG_DATA = 0x1c016 # macro +regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT5_CONTROL = 0x1c017 # macro +regPCIEMSIX_VECT5_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT6_ADDR_LO = 0x1c018 # macro +regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT6_ADDR_HI = 0x1c019 # macro +regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT6_MSG_DATA = 0x1c01a # macro +regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT6_CONTROL = 0x1c01b # macro +regPCIEMSIX_VECT6_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT7_ADDR_LO = 0x1c01c # macro +regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT7_ADDR_HI = 0x1c01d # macro +regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT7_MSG_DATA = 0x1c01e # macro +regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT7_CONTROL = 0x1c01f # macro +regPCIEMSIX_VECT7_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT8_ADDR_LO = 0x1c020 # macro +regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT8_ADDR_HI = 0x1c021 # macro +regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT8_MSG_DATA = 0x1c022 # macro +regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT8_CONTROL = 0x1c023 # macro +regPCIEMSIX_VECT8_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT9_ADDR_LO = 0x1c024 # macro +regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT9_ADDR_HI = 0x1c025 # macro +regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT9_MSG_DATA = 0x1c026 # macro +regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT9_CONTROL = 0x1c027 # macro +regPCIEMSIX_VECT9_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT10_ADDR_LO = 0x1c028 # macro +regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT10_ADDR_HI = 0x1c029 # macro +regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT10_MSG_DATA = 0x1c02a # macro +regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT10_CONTROL = 0x1c02b # macro +regPCIEMSIX_VECT10_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT11_ADDR_LO = 0x1c02c # macro +regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT11_ADDR_HI = 0x1c02d # macro +regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT11_MSG_DATA = 0x1c02e # macro +regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT11_CONTROL = 0x1c02f # macro +regPCIEMSIX_VECT11_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT12_ADDR_LO = 0x1c030 # macro +regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT12_ADDR_HI = 0x1c031 # macro +regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT12_MSG_DATA = 0x1c032 # macro +regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT12_CONTROL = 0x1c033 # macro +regPCIEMSIX_VECT12_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT13_ADDR_LO = 0x1c034 # macro +regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT13_ADDR_HI = 0x1c035 # macro +regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT13_MSG_DATA = 0x1c036 # macro +regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT13_CONTROL = 0x1c037 # macro +regPCIEMSIX_VECT13_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT14_ADDR_LO = 0x1c038 # macro +regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT14_ADDR_HI = 0x1c039 # macro +regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT14_MSG_DATA = 0x1c03a # macro +regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT14_CONTROL = 0x1c03b # macro +regPCIEMSIX_VECT14_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT15_ADDR_LO = 0x1c03c # macro +regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT15_ADDR_HI = 0x1c03d # macro +regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT15_MSG_DATA = 0x1c03e # macro +regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT15_CONTROL = 0x1c03f # macro +regPCIEMSIX_VECT15_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT16_ADDR_LO = 0x1c040 # macro +regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT16_ADDR_HI = 0x1c041 # macro +regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT16_MSG_DATA = 0x1c042 # macro +regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT16_CONTROL = 0x1c043 # macro +regPCIEMSIX_VECT16_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT17_ADDR_LO = 0x1c044 # macro +regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT17_ADDR_HI = 0x1c045 # macro +regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT17_MSG_DATA = 0x1c046 # macro +regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT17_CONTROL = 0x1c047 # macro +regPCIEMSIX_VECT17_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT18_ADDR_LO = 0x1c048 # macro +regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT18_ADDR_HI = 0x1c049 # macro +regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT18_MSG_DATA = 0x1c04a # macro +regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT18_CONTROL = 0x1c04b # macro +regPCIEMSIX_VECT18_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT19_ADDR_LO = 0x1c04c # macro +regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT19_ADDR_HI = 0x1c04d # macro +regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT19_MSG_DATA = 0x1c04e # macro +regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT19_CONTROL = 0x1c04f # macro +regPCIEMSIX_VECT19_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT20_ADDR_LO = 0x1c050 # macro +regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT20_ADDR_HI = 0x1c051 # macro +regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT20_MSG_DATA = 0x1c052 # macro +regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT20_CONTROL = 0x1c053 # macro +regPCIEMSIX_VECT20_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT21_ADDR_LO = 0x1c054 # macro +regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT21_ADDR_HI = 0x1c055 # macro +regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT21_MSG_DATA = 0x1c056 # macro +regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT21_CONTROL = 0x1c057 # macro +regPCIEMSIX_VECT21_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT22_ADDR_LO = 0x1c058 # macro +regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT22_ADDR_HI = 0x1c059 # macro +regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT22_MSG_DATA = 0x1c05a # macro +regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT22_CONTROL = 0x1c05b # macro +regPCIEMSIX_VECT22_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT23_ADDR_LO = 0x1c05c # macro +regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT23_ADDR_HI = 0x1c05d # macro +regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT23_MSG_DATA = 0x1c05e # macro +regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT23_CONTROL = 0x1c05f # macro +regPCIEMSIX_VECT23_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT24_ADDR_LO = 0x1c060 # macro +regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT24_ADDR_HI = 0x1c061 # macro +regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT24_MSG_DATA = 0x1c062 # macro +regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT24_CONTROL = 0x1c063 # macro +regPCIEMSIX_VECT24_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT25_ADDR_LO = 0x1c064 # macro +regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT25_ADDR_HI = 0x1c065 # macro +regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT25_MSG_DATA = 0x1c066 # macro +regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT25_CONTROL = 0x1c067 # macro +regPCIEMSIX_VECT25_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT26_ADDR_LO = 0x1c068 # macro +regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT26_ADDR_HI = 0x1c069 # macro +regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT26_MSG_DATA = 0x1c06a # macro +regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT26_CONTROL = 0x1c06b # macro +regPCIEMSIX_VECT26_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT27_ADDR_LO = 0x1c06c # macro +regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT27_ADDR_HI = 0x1c06d # macro +regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT27_MSG_DATA = 0x1c06e # macro +regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT27_CONTROL = 0x1c06f # macro +regPCIEMSIX_VECT27_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT28_ADDR_LO = 0x1c070 # macro +regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT28_ADDR_HI = 0x1c071 # macro +regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT28_MSG_DATA = 0x1c072 # macro +regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT28_CONTROL = 0x1c073 # macro +regPCIEMSIX_VECT28_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT29_ADDR_LO = 0x1c074 # macro +regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT29_ADDR_HI = 0x1c075 # macro +regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT29_MSG_DATA = 0x1c076 # macro +regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT29_CONTROL = 0x1c077 # macro +regPCIEMSIX_VECT29_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT30_ADDR_LO = 0x1c078 # macro +regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT30_ADDR_HI = 0x1c079 # macro +regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT30_MSG_DATA = 0x1c07a # macro +regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT30_CONTROL = 0x1c07b # macro +regPCIEMSIX_VECT30_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT31_ADDR_LO = 0x1c07c # macro +regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT31_ADDR_HI = 0x1c07d # macro +regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT31_MSG_DATA = 0x1c07e # macro +regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT31_CONTROL = 0x1c07f # macro +regPCIEMSIX_VECT31_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT32_ADDR_LO = 0x1c080 # macro +regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT32_ADDR_HI = 0x1c081 # macro +regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT32_MSG_DATA = 0x1c082 # macro +regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT32_CONTROL = 0x1c083 # macro +regPCIEMSIX_VECT32_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT33_ADDR_LO = 0x1c084 # macro +regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT33_ADDR_HI = 0x1c085 # macro +regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT33_MSG_DATA = 0x1c086 # macro +regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT33_CONTROL = 0x1c087 # macro +regPCIEMSIX_VECT33_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT34_ADDR_LO = 0x1c088 # macro +regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT34_ADDR_HI = 0x1c089 # macro +regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT34_MSG_DATA = 0x1c08a # macro +regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT34_CONTROL = 0x1c08b # macro +regPCIEMSIX_VECT34_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT35_ADDR_LO = 0x1c08c # macro +regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT35_ADDR_HI = 0x1c08d # macro +regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT35_MSG_DATA = 0x1c08e # macro +regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT35_CONTROL = 0x1c08f # macro +regPCIEMSIX_VECT35_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT36_ADDR_LO = 0x1c090 # macro +regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT36_ADDR_HI = 0x1c091 # macro +regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT36_MSG_DATA = 0x1c092 # macro +regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT36_CONTROL = 0x1c093 # macro +regPCIEMSIX_VECT36_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT37_ADDR_LO = 0x1c094 # macro +regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT37_ADDR_HI = 0x1c095 # macro +regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT37_MSG_DATA = 0x1c096 # macro +regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT37_CONTROL = 0x1c097 # macro +regPCIEMSIX_VECT37_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT38_ADDR_LO = 0x1c098 # macro +regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT38_ADDR_HI = 0x1c099 # macro +regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT38_MSG_DATA = 0x1c09a # macro +regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT38_CONTROL = 0x1c09b # macro +regPCIEMSIX_VECT38_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT39_ADDR_LO = 0x1c09c # macro +regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT39_ADDR_HI = 0x1c09d # macro +regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT39_MSG_DATA = 0x1c09e # macro +regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT39_CONTROL = 0x1c09f # macro +regPCIEMSIX_VECT39_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT40_ADDR_LO = 0x1c0a0 # macro +regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT40_ADDR_HI = 0x1c0a1 # macro +regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT40_MSG_DATA = 0x1c0a2 # macro +regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT40_CONTROL = 0x1c0a3 # macro +regPCIEMSIX_VECT40_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT41_ADDR_LO = 0x1c0a4 # macro +regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT41_ADDR_HI = 0x1c0a5 # macro +regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT41_MSG_DATA = 0x1c0a6 # macro +regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT41_CONTROL = 0x1c0a7 # macro +regPCIEMSIX_VECT41_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT42_ADDR_LO = 0x1c0a8 # macro +regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT42_ADDR_HI = 0x1c0a9 # macro +regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT42_MSG_DATA = 0x1c0aa # macro +regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT42_CONTROL = 0x1c0ab # macro +regPCIEMSIX_VECT42_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT43_ADDR_LO = 0x1c0ac # macro +regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT43_ADDR_HI = 0x1c0ad # macro +regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT43_MSG_DATA = 0x1c0ae # macro +regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT43_CONTROL = 0x1c0af # macro +regPCIEMSIX_VECT43_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT44_ADDR_LO = 0x1c0b0 # macro +regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT44_ADDR_HI = 0x1c0b1 # macro +regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT44_MSG_DATA = 0x1c0b2 # macro +regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT44_CONTROL = 0x1c0b3 # macro +regPCIEMSIX_VECT44_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT45_ADDR_LO = 0x1c0b4 # macro +regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT45_ADDR_HI = 0x1c0b5 # macro +regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT45_MSG_DATA = 0x1c0b6 # macro +regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT45_CONTROL = 0x1c0b7 # macro +regPCIEMSIX_VECT45_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT46_ADDR_LO = 0x1c0b8 # macro +regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT46_ADDR_HI = 0x1c0b9 # macro +regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT46_MSG_DATA = 0x1c0ba # macro +regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT46_CONTROL = 0x1c0bb # macro +regPCIEMSIX_VECT46_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT47_ADDR_LO = 0x1c0bc # macro +regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT47_ADDR_HI = 0x1c0bd # macro +regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT47_MSG_DATA = 0x1c0be # macro +regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT47_CONTROL = 0x1c0bf # macro +regPCIEMSIX_VECT47_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT48_ADDR_LO = 0x1c0c0 # macro +regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT48_ADDR_HI = 0x1c0c1 # macro +regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT48_MSG_DATA = 0x1c0c2 # macro +regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT48_CONTROL = 0x1c0c3 # macro +regPCIEMSIX_VECT48_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT49_ADDR_LO = 0x1c0c4 # macro +regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT49_ADDR_HI = 0x1c0c5 # macro +regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT49_MSG_DATA = 0x1c0c6 # macro +regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT49_CONTROL = 0x1c0c7 # macro +regPCIEMSIX_VECT49_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT50_ADDR_LO = 0x1c0c8 # macro +regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT50_ADDR_HI = 0x1c0c9 # macro +regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT50_MSG_DATA = 0x1c0ca # macro +regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT50_CONTROL = 0x1c0cb # macro +regPCIEMSIX_VECT50_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT51_ADDR_LO = 0x1c0cc # macro +regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT51_ADDR_HI = 0x1c0cd # macro +regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT51_MSG_DATA = 0x1c0ce # macro +regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT51_CONTROL = 0x1c0cf # macro +regPCIEMSIX_VECT51_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT52_ADDR_LO = 0x1c0d0 # macro +regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT52_ADDR_HI = 0x1c0d1 # macro +regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT52_MSG_DATA = 0x1c0d2 # macro +regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT52_CONTROL = 0x1c0d3 # macro +regPCIEMSIX_VECT52_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT53_ADDR_LO = 0x1c0d4 # macro +regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT53_ADDR_HI = 0x1c0d5 # macro +regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT53_MSG_DATA = 0x1c0d6 # macro +regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT53_CONTROL = 0x1c0d7 # macro +regPCIEMSIX_VECT53_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT54_ADDR_LO = 0x1c0d8 # macro +regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT54_ADDR_HI = 0x1c0d9 # macro +regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT54_MSG_DATA = 0x1c0da # macro +regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT54_CONTROL = 0x1c0db # macro +regPCIEMSIX_VECT54_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT55_ADDR_LO = 0x1c0dc # macro +regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT55_ADDR_HI = 0x1c0dd # macro +regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT55_MSG_DATA = 0x1c0de # macro +regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT55_CONTROL = 0x1c0df # macro +regPCIEMSIX_VECT55_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT56_ADDR_LO = 0x1c0e0 # macro +regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT56_ADDR_HI = 0x1c0e1 # macro +regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT56_MSG_DATA = 0x1c0e2 # macro +regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT56_CONTROL = 0x1c0e3 # macro +regPCIEMSIX_VECT56_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT57_ADDR_LO = 0x1c0e4 # macro +regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT57_ADDR_HI = 0x1c0e5 # macro +regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT57_MSG_DATA = 0x1c0e6 # macro +regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT57_CONTROL = 0x1c0e7 # macro +regPCIEMSIX_VECT57_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT58_ADDR_LO = 0x1c0e8 # macro +regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT58_ADDR_HI = 0x1c0e9 # macro +regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT58_MSG_DATA = 0x1c0ea # macro +regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT58_CONTROL = 0x1c0eb # macro +regPCIEMSIX_VECT58_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT59_ADDR_LO = 0x1c0ec # macro +regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT59_ADDR_HI = 0x1c0ed # macro +regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT59_MSG_DATA = 0x1c0ee # macro +regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT59_CONTROL = 0x1c0ef # macro +regPCIEMSIX_VECT59_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT60_ADDR_LO = 0x1c0f0 # macro +regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT60_ADDR_HI = 0x1c0f1 # macro +regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT60_MSG_DATA = 0x1c0f2 # macro +regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT60_CONTROL = 0x1c0f3 # macro +regPCIEMSIX_VECT60_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT61_ADDR_LO = 0x1c0f4 # macro +regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT61_ADDR_HI = 0x1c0f5 # macro +regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT61_MSG_DATA = 0x1c0f6 # macro +regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT61_CONTROL = 0x1c0f7 # macro +regPCIEMSIX_VECT61_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT62_ADDR_LO = 0x1c0f8 # macro +regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT62_ADDR_HI = 0x1c0f9 # macro +regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT62_MSG_DATA = 0x1c0fa # macro +regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT62_CONTROL = 0x1c0fb # macro +regPCIEMSIX_VECT62_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT63_ADDR_LO = 0x1c0fc # macro +regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT63_ADDR_HI = 0x1c0fd # macro +regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT63_MSG_DATA = 0x1c0fe # macro +regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT63_CONTROL = 0x1c0ff # macro +regPCIEMSIX_VECT63_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT64_ADDR_LO = 0x1c100 # macro +regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT64_ADDR_HI = 0x1c101 # macro +regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT64_MSG_DATA = 0x1c102 # macro +regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT64_CONTROL = 0x1c103 # macro +regPCIEMSIX_VECT64_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT65_ADDR_LO = 0x1c104 # macro +regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT65_ADDR_HI = 0x1c105 # macro +regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT65_MSG_DATA = 0x1c106 # macro +regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT65_CONTROL = 0x1c107 # macro +regPCIEMSIX_VECT65_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT66_ADDR_LO = 0x1c108 # macro +regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT66_ADDR_HI = 0x1c109 # macro +regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT66_MSG_DATA = 0x1c10a # macro +regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT66_CONTROL = 0x1c10b # macro +regPCIEMSIX_VECT66_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT67_ADDR_LO = 0x1c10c # macro +regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT67_ADDR_HI = 0x1c10d # macro +regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT67_MSG_DATA = 0x1c10e # macro +regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT67_CONTROL = 0x1c10f # macro +regPCIEMSIX_VECT67_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT68_ADDR_LO = 0x1c110 # macro +regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT68_ADDR_HI = 0x1c111 # macro +regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT68_MSG_DATA = 0x1c112 # macro +regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT68_CONTROL = 0x1c113 # macro +regPCIEMSIX_VECT68_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT69_ADDR_LO = 0x1c114 # macro +regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT69_ADDR_HI = 0x1c115 # macro +regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT69_MSG_DATA = 0x1c116 # macro +regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT69_CONTROL = 0x1c117 # macro +regPCIEMSIX_VECT69_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT70_ADDR_LO = 0x1c118 # macro +regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT70_ADDR_HI = 0x1c119 # macro +regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT70_MSG_DATA = 0x1c11a # macro +regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT70_CONTROL = 0x1c11b # macro +regPCIEMSIX_VECT70_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT71_ADDR_LO = 0x1c11c # macro +regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT71_ADDR_HI = 0x1c11d # macro +regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT71_MSG_DATA = 0x1c11e # macro +regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT71_CONTROL = 0x1c11f # macro +regPCIEMSIX_VECT71_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT72_ADDR_LO = 0x1c120 # macro +regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT72_ADDR_HI = 0x1c121 # macro +regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT72_MSG_DATA = 0x1c122 # macro +regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT72_CONTROL = 0x1c123 # macro +regPCIEMSIX_VECT72_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT73_ADDR_LO = 0x1c124 # macro +regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT73_ADDR_HI = 0x1c125 # macro +regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT73_MSG_DATA = 0x1c126 # macro +regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT73_CONTROL = 0x1c127 # macro +regPCIEMSIX_VECT73_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT74_ADDR_LO = 0x1c128 # macro +regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT74_ADDR_HI = 0x1c129 # macro +regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT74_MSG_DATA = 0x1c12a # macro +regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT74_CONTROL = 0x1c12b # macro +regPCIEMSIX_VECT74_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT75_ADDR_LO = 0x1c12c # macro +regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT75_ADDR_HI = 0x1c12d # macro +regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT75_MSG_DATA = 0x1c12e # macro +regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT75_CONTROL = 0x1c12f # macro +regPCIEMSIX_VECT75_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT76_ADDR_LO = 0x1c130 # macro +regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT76_ADDR_HI = 0x1c131 # macro +regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT76_MSG_DATA = 0x1c132 # macro +regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT76_CONTROL = 0x1c133 # macro +regPCIEMSIX_VECT76_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT77_ADDR_LO = 0x1c134 # macro +regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT77_ADDR_HI = 0x1c135 # macro +regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT77_MSG_DATA = 0x1c136 # macro +regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT77_CONTROL = 0x1c137 # macro +regPCIEMSIX_VECT77_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT78_ADDR_LO = 0x1c138 # macro +regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT78_ADDR_HI = 0x1c139 # macro +regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT78_MSG_DATA = 0x1c13a # macro +regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT78_CONTROL = 0x1c13b # macro +regPCIEMSIX_VECT78_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT79_ADDR_LO = 0x1c13c # macro +regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT79_ADDR_HI = 0x1c13d # macro +regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT79_MSG_DATA = 0x1c13e # macro +regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT79_CONTROL = 0x1c13f # macro +regPCIEMSIX_VECT79_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT80_ADDR_LO = 0x1c140 # macro +regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT80_ADDR_HI = 0x1c141 # macro +regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT80_MSG_DATA = 0x1c142 # macro +regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT80_CONTROL = 0x1c143 # macro +regPCIEMSIX_VECT80_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT81_ADDR_LO = 0x1c144 # macro +regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT81_ADDR_HI = 0x1c145 # macro +regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT81_MSG_DATA = 0x1c146 # macro +regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT81_CONTROL = 0x1c147 # macro +regPCIEMSIX_VECT81_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT82_ADDR_LO = 0x1c148 # macro +regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT82_ADDR_HI = 0x1c149 # macro +regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT82_MSG_DATA = 0x1c14a # macro +regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT82_CONTROL = 0x1c14b # macro +regPCIEMSIX_VECT82_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT83_ADDR_LO = 0x1c14c # macro +regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT83_ADDR_HI = 0x1c14d # macro +regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT83_MSG_DATA = 0x1c14e # macro +regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT83_CONTROL = 0x1c14f # macro +regPCIEMSIX_VECT83_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT84_ADDR_LO = 0x1c150 # macro +regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT84_ADDR_HI = 0x1c151 # macro +regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT84_MSG_DATA = 0x1c152 # macro +regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT84_CONTROL = 0x1c153 # macro +regPCIEMSIX_VECT84_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT85_ADDR_LO = 0x1c154 # macro +regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT85_ADDR_HI = 0x1c155 # macro +regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT85_MSG_DATA = 0x1c156 # macro +regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT85_CONTROL = 0x1c157 # macro +regPCIEMSIX_VECT85_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT86_ADDR_LO = 0x1c158 # macro +regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT86_ADDR_HI = 0x1c159 # macro +regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT86_MSG_DATA = 0x1c15a # macro +regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT86_CONTROL = 0x1c15b # macro +regPCIEMSIX_VECT86_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT87_ADDR_LO = 0x1c15c # macro +regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT87_ADDR_HI = 0x1c15d # macro +regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT87_MSG_DATA = 0x1c15e # macro +regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT87_CONTROL = 0x1c15f # macro +regPCIEMSIX_VECT87_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT88_ADDR_LO = 0x1c160 # macro +regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT88_ADDR_HI = 0x1c161 # macro +regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT88_MSG_DATA = 0x1c162 # macro +regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT88_CONTROL = 0x1c163 # macro +regPCIEMSIX_VECT88_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT89_ADDR_LO = 0x1c164 # macro +regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT89_ADDR_HI = 0x1c165 # macro +regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT89_MSG_DATA = 0x1c166 # macro +regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT89_CONTROL = 0x1c167 # macro +regPCIEMSIX_VECT89_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT90_ADDR_LO = 0x1c168 # macro +regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT90_ADDR_HI = 0x1c169 # macro +regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT90_MSG_DATA = 0x1c16a # macro +regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT90_CONTROL = 0x1c16b # macro +regPCIEMSIX_VECT90_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT91_ADDR_LO = 0x1c16c # macro +regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT91_ADDR_HI = 0x1c16d # macro +regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT91_MSG_DATA = 0x1c16e # macro +regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT91_CONTROL = 0x1c16f # macro +regPCIEMSIX_VECT91_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT92_ADDR_LO = 0x1c170 # macro +regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT92_ADDR_HI = 0x1c171 # macro +regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT92_MSG_DATA = 0x1c172 # macro +regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT92_CONTROL = 0x1c173 # macro +regPCIEMSIX_VECT92_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT93_ADDR_LO = 0x1c174 # macro +regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT93_ADDR_HI = 0x1c175 # macro +regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT93_MSG_DATA = 0x1c176 # macro +regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT93_CONTROL = 0x1c177 # macro +regPCIEMSIX_VECT93_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT94_ADDR_LO = 0x1c178 # macro +regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT94_ADDR_HI = 0x1c179 # macro +regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT94_MSG_DATA = 0x1c17a # macro +regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT94_CONTROL = 0x1c17b # macro +regPCIEMSIX_VECT94_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT95_ADDR_LO = 0x1c17c # macro +regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT95_ADDR_HI = 0x1c17d # macro +regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT95_MSG_DATA = 0x1c17e # macro +regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT95_CONTROL = 0x1c17f # macro +regPCIEMSIX_VECT95_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT96_ADDR_LO = 0x1c180 # macro +regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT96_ADDR_HI = 0x1c181 # macro +regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT96_MSG_DATA = 0x1c182 # macro +regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT96_CONTROL = 0x1c183 # macro +regPCIEMSIX_VECT96_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT97_ADDR_LO = 0x1c184 # macro +regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT97_ADDR_HI = 0x1c185 # macro +regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT97_MSG_DATA = 0x1c186 # macro +regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT97_CONTROL = 0x1c187 # macro +regPCIEMSIX_VECT97_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT98_ADDR_LO = 0x1c188 # macro +regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT98_ADDR_HI = 0x1c189 # macro +regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT98_MSG_DATA = 0x1c18a # macro +regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT98_CONTROL = 0x1c18b # macro +regPCIEMSIX_VECT98_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT99_ADDR_LO = 0x1c18c # macro +regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT99_ADDR_HI = 0x1c18d # macro +regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT99_MSG_DATA = 0x1c18e # macro +regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT99_CONTROL = 0x1c18f # macro +regPCIEMSIX_VECT99_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT100_ADDR_LO = 0x1c190 # macro +regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT100_ADDR_HI = 0x1c191 # macro +regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT100_MSG_DATA = 0x1c192 # macro +regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT100_CONTROL = 0x1c193 # macro +regPCIEMSIX_VECT100_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT101_ADDR_LO = 0x1c194 # macro +regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT101_ADDR_HI = 0x1c195 # macro +regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT101_MSG_DATA = 0x1c196 # macro +regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT101_CONTROL = 0x1c197 # macro +regPCIEMSIX_VECT101_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT102_ADDR_LO = 0x1c198 # macro +regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT102_ADDR_HI = 0x1c199 # macro +regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT102_MSG_DATA = 0x1c19a # macro +regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT102_CONTROL = 0x1c19b # macro +regPCIEMSIX_VECT102_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT103_ADDR_LO = 0x1c19c # macro +regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT103_ADDR_HI = 0x1c19d # macro +regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT103_MSG_DATA = 0x1c19e # macro +regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT103_CONTROL = 0x1c19f # macro +regPCIEMSIX_VECT103_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT104_ADDR_LO = 0x1c1a0 # macro +regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT104_ADDR_HI = 0x1c1a1 # macro +regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT104_MSG_DATA = 0x1c1a2 # macro +regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT104_CONTROL = 0x1c1a3 # macro +regPCIEMSIX_VECT104_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT105_ADDR_LO = 0x1c1a4 # macro +regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT105_ADDR_HI = 0x1c1a5 # macro +regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT105_MSG_DATA = 0x1c1a6 # macro +regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT105_CONTROL = 0x1c1a7 # macro +regPCIEMSIX_VECT105_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT106_ADDR_LO = 0x1c1a8 # macro +regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT106_ADDR_HI = 0x1c1a9 # macro +regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT106_MSG_DATA = 0x1c1aa # macro +regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT106_CONTROL = 0x1c1ab # macro +regPCIEMSIX_VECT106_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT107_ADDR_LO = 0x1c1ac # macro +regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT107_ADDR_HI = 0x1c1ad # macro +regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT107_MSG_DATA = 0x1c1ae # macro +regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT107_CONTROL = 0x1c1af # macro +regPCIEMSIX_VECT107_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT108_ADDR_LO = 0x1c1b0 # macro +regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT108_ADDR_HI = 0x1c1b1 # macro +regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT108_MSG_DATA = 0x1c1b2 # macro +regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT108_CONTROL = 0x1c1b3 # macro +regPCIEMSIX_VECT108_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT109_ADDR_LO = 0x1c1b4 # macro +regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT109_ADDR_HI = 0x1c1b5 # macro +regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT109_MSG_DATA = 0x1c1b6 # macro +regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT109_CONTROL = 0x1c1b7 # macro +regPCIEMSIX_VECT109_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT110_ADDR_LO = 0x1c1b8 # macro +regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT110_ADDR_HI = 0x1c1b9 # macro +regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT110_MSG_DATA = 0x1c1ba # macro +regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT110_CONTROL = 0x1c1bb # macro +regPCIEMSIX_VECT110_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT111_ADDR_LO = 0x1c1bc # macro +regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT111_ADDR_HI = 0x1c1bd # macro +regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT111_MSG_DATA = 0x1c1be # macro +regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT111_CONTROL = 0x1c1bf # macro +regPCIEMSIX_VECT111_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT112_ADDR_LO = 0x1c1c0 # macro +regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT112_ADDR_HI = 0x1c1c1 # macro +regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT112_MSG_DATA = 0x1c1c2 # macro +regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT112_CONTROL = 0x1c1c3 # macro +regPCIEMSIX_VECT112_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT113_ADDR_LO = 0x1c1c4 # macro +regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT113_ADDR_HI = 0x1c1c5 # macro +regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT113_MSG_DATA = 0x1c1c6 # macro +regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT113_CONTROL = 0x1c1c7 # macro +regPCIEMSIX_VECT113_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT114_ADDR_LO = 0x1c1c8 # macro +regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT114_ADDR_HI = 0x1c1c9 # macro +regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT114_MSG_DATA = 0x1c1ca # macro +regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT114_CONTROL = 0x1c1cb # macro +regPCIEMSIX_VECT114_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT115_ADDR_LO = 0x1c1cc # macro +regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT115_ADDR_HI = 0x1c1cd # macro +regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT115_MSG_DATA = 0x1c1ce # macro +regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT115_CONTROL = 0x1c1cf # macro +regPCIEMSIX_VECT115_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT116_ADDR_LO = 0x1c1d0 # macro +regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT116_ADDR_HI = 0x1c1d1 # macro +regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT116_MSG_DATA = 0x1c1d2 # macro +regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT116_CONTROL = 0x1c1d3 # macro +regPCIEMSIX_VECT116_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT117_ADDR_LO = 0x1c1d4 # macro +regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT117_ADDR_HI = 0x1c1d5 # macro +regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT117_MSG_DATA = 0x1c1d6 # macro +regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT117_CONTROL = 0x1c1d7 # macro +regPCIEMSIX_VECT117_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT118_ADDR_LO = 0x1c1d8 # macro +regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT118_ADDR_HI = 0x1c1d9 # macro +regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT118_MSG_DATA = 0x1c1da # macro +regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT118_CONTROL = 0x1c1db # macro +regPCIEMSIX_VECT118_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT119_ADDR_LO = 0x1c1dc # macro +regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT119_ADDR_HI = 0x1c1dd # macro +regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT119_MSG_DATA = 0x1c1de # macro +regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT119_CONTROL = 0x1c1df # macro +regPCIEMSIX_VECT119_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT120_ADDR_LO = 0x1c1e0 # macro +regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT120_ADDR_HI = 0x1c1e1 # macro +regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT120_MSG_DATA = 0x1c1e2 # macro +regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT120_CONTROL = 0x1c1e3 # macro +regPCIEMSIX_VECT120_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT121_ADDR_LO = 0x1c1e4 # macro +regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT121_ADDR_HI = 0x1c1e5 # macro +regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT121_MSG_DATA = 0x1c1e6 # macro +regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT121_CONTROL = 0x1c1e7 # macro +regPCIEMSIX_VECT121_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT122_ADDR_LO = 0x1c1e8 # macro +regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT122_ADDR_HI = 0x1c1e9 # macro +regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT122_MSG_DATA = 0x1c1ea # macro +regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT122_CONTROL = 0x1c1eb # macro +regPCIEMSIX_VECT122_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT123_ADDR_LO = 0x1c1ec # macro +regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT123_ADDR_HI = 0x1c1ed # macro +regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT123_MSG_DATA = 0x1c1ee # macro +regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT123_CONTROL = 0x1c1ef # macro +regPCIEMSIX_VECT123_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT124_ADDR_LO = 0x1c1f0 # macro +regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT124_ADDR_HI = 0x1c1f1 # macro +regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT124_MSG_DATA = 0x1c1f2 # macro +regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT124_CONTROL = 0x1c1f3 # macro +regPCIEMSIX_VECT124_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT125_ADDR_LO = 0x1c1f4 # macro +regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT125_ADDR_HI = 0x1c1f5 # macro +regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT125_MSG_DATA = 0x1c1f6 # macro +regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT125_CONTROL = 0x1c1f7 # macro +regPCIEMSIX_VECT125_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT126_ADDR_LO = 0x1c1f8 # macro +regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT126_ADDR_HI = 0x1c1f9 # macro +regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT126_MSG_DATA = 0x1c1fa # macro +regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT126_CONTROL = 0x1c1fb # macro +regPCIEMSIX_VECT126_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT127_ADDR_LO = 0x1c1fc # macro +regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT127_ADDR_HI = 0x1c1fd # macro +regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT127_MSG_DATA = 0x1c1fe # macro +regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT127_CONTROL = 0x1c1ff # macro +regPCIEMSIX_VECT127_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT128_ADDR_LO = 0x1c200 # macro +regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT128_ADDR_HI = 0x1c201 # macro +regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT128_MSG_DATA = 0x1c202 # macro +regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT128_CONTROL = 0x1c203 # macro +regPCIEMSIX_VECT128_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT129_ADDR_LO = 0x1c204 # macro +regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT129_ADDR_HI = 0x1c205 # macro +regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT129_MSG_DATA = 0x1c206 # macro +regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT129_CONTROL = 0x1c207 # macro +regPCIEMSIX_VECT129_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT130_ADDR_LO = 0x1c208 # macro +regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT130_ADDR_HI = 0x1c209 # macro +regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT130_MSG_DATA = 0x1c20a # macro +regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT130_CONTROL = 0x1c20b # macro +regPCIEMSIX_VECT130_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT131_ADDR_LO = 0x1c20c # macro +regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT131_ADDR_HI = 0x1c20d # macro +regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT131_MSG_DATA = 0x1c20e # macro +regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT131_CONTROL = 0x1c20f # macro +regPCIEMSIX_VECT131_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT132_ADDR_LO = 0x1c210 # macro +regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT132_ADDR_HI = 0x1c211 # macro +regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT132_MSG_DATA = 0x1c212 # macro +regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT132_CONTROL = 0x1c213 # macro +regPCIEMSIX_VECT132_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT133_ADDR_LO = 0x1c214 # macro +regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT133_ADDR_HI = 0x1c215 # macro +regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT133_MSG_DATA = 0x1c216 # macro +regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT133_CONTROL = 0x1c217 # macro +regPCIEMSIX_VECT133_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT134_ADDR_LO = 0x1c218 # macro +regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT134_ADDR_HI = 0x1c219 # macro +regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT134_MSG_DATA = 0x1c21a # macro +regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT134_CONTROL = 0x1c21b # macro +regPCIEMSIX_VECT134_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT135_ADDR_LO = 0x1c21c # macro +regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT135_ADDR_HI = 0x1c21d # macro +regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT135_MSG_DATA = 0x1c21e # macro +regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT135_CONTROL = 0x1c21f # macro +regPCIEMSIX_VECT135_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT136_ADDR_LO = 0x1c220 # macro +regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT136_ADDR_HI = 0x1c221 # macro +regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT136_MSG_DATA = 0x1c222 # macro +regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT136_CONTROL = 0x1c223 # macro +regPCIEMSIX_VECT136_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT137_ADDR_LO = 0x1c224 # macro +regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT137_ADDR_HI = 0x1c225 # macro +regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT137_MSG_DATA = 0x1c226 # macro +regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT137_CONTROL = 0x1c227 # macro +regPCIEMSIX_VECT137_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT138_ADDR_LO = 0x1c228 # macro +regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT138_ADDR_HI = 0x1c229 # macro +regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT138_MSG_DATA = 0x1c22a # macro +regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT138_CONTROL = 0x1c22b # macro +regPCIEMSIX_VECT138_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT139_ADDR_LO = 0x1c22c # macro +regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT139_ADDR_HI = 0x1c22d # macro +regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT139_MSG_DATA = 0x1c22e # macro +regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT139_CONTROL = 0x1c22f # macro +regPCIEMSIX_VECT139_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT140_ADDR_LO = 0x1c230 # macro +regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT140_ADDR_HI = 0x1c231 # macro +regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT140_MSG_DATA = 0x1c232 # macro +regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT140_CONTROL = 0x1c233 # macro +regPCIEMSIX_VECT140_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT141_ADDR_LO = 0x1c234 # macro +regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT141_ADDR_HI = 0x1c235 # macro +regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT141_MSG_DATA = 0x1c236 # macro +regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT141_CONTROL = 0x1c237 # macro +regPCIEMSIX_VECT141_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT142_ADDR_LO = 0x1c238 # macro +regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT142_ADDR_HI = 0x1c239 # macro +regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT142_MSG_DATA = 0x1c23a # macro +regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT142_CONTROL = 0x1c23b # macro +regPCIEMSIX_VECT142_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT143_ADDR_LO = 0x1c23c # macro +regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT143_ADDR_HI = 0x1c23d # macro +regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT143_MSG_DATA = 0x1c23e # macro +regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT143_CONTROL = 0x1c23f # macro +regPCIEMSIX_VECT143_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT144_ADDR_LO = 0x1c240 # macro +regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT144_ADDR_HI = 0x1c241 # macro +regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT144_MSG_DATA = 0x1c242 # macro +regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT144_CONTROL = 0x1c243 # macro +regPCIEMSIX_VECT144_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT145_ADDR_LO = 0x1c244 # macro +regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT145_ADDR_HI = 0x1c245 # macro +regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT145_MSG_DATA = 0x1c246 # macro +regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT145_CONTROL = 0x1c247 # macro +regPCIEMSIX_VECT145_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT146_ADDR_LO = 0x1c248 # macro +regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT146_ADDR_HI = 0x1c249 # macro +regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT146_MSG_DATA = 0x1c24a # macro +regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT146_CONTROL = 0x1c24b # macro +regPCIEMSIX_VECT146_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT147_ADDR_LO = 0x1c24c # macro +regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT147_ADDR_HI = 0x1c24d # macro +regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT147_MSG_DATA = 0x1c24e # macro +regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT147_CONTROL = 0x1c24f # macro +regPCIEMSIX_VECT147_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT148_ADDR_LO = 0x1c250 # macro +regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT148_ADDR_HI = 0x1c251 # macro +regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT148_MSG_DATA = 0x1c252 # macro +regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT148_CONTROL = 0x1c253 # macro +regPCIEMSIX_VECT148_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT149_ADDR_LO = 0x1c254 # macro +regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT149_ADDR_HI = 0x1c255 # macro +regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT149_MSG_DATA = 0x1c256 # macro +regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT149_CONTROL = 0x1c257 # macro +regPCIEMSIX_VECT149_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT150_ADDR_LO = 0x1c258 # macro +regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT150_ADDR_HI = 0x1c259 # macro +regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT150_MSG_DATA = 0x1c25a # macro +regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT150_CONTROL = 0x1c25b # macro +regPCIEMSIX_VECT150_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT151_ADDR_LO = 0x1c25c # macro +regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT151_ADDR_HI = 0x1c25d # macro +regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT151_MSG_DATA = 0x1c25e # macro +regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT151_CONTROL = 0x1c25f # macro +regPCIEMSIX_VECT151_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT152_ADDR_LO = 0x1c260 # macro +regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT152_ADDR_HI = 0x1c261 # macro +regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT152_MSG_DATA = 0x1c262 # macro +regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT152_CONTROL = 0x1c263 # macro +regPCIEMSIX_VECT152_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT153_ADDR_LO = 0x1c264 # macro +regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT153_ADDR_HI = 0x1c265 # macro +regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT153_MSG_DATA = 0x1c266 # macro +regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT153_CONTROL = 0x1c267 # macro +regPCIEMSIX_VECT153_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT154_ADDR_LO = 0x1c268 # macro +regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT154_ADDR_HI = 0x1c269 # macro +regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT154_MSG_DATA = 0x1c26a # macro +regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT154_CONTROL = 0x1c26b # macro +regPCIEMSIX_VECT154_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT155_ADDR_LO = 0x1c26c # macro +regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT155_ADDR_HI = 0x1c26d # macro +regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT155_MSG_DATA = 0x1c26e # macro +regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT155_CONTROL = 0x1c26f # macro +regPCIEMSIX_VECT155_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT156_ADDR_LO = 0x1c270 # macro +regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT156_ADDR_HI = 0x1c271 # macro +regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT156_MSG_DATA = 0x1c272 # macro +regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT156_CONTROL = 0x1c273 # macro +regPCIEMSIX_VECT156_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT157_ADDR_LO = 0x1c274 # macro +regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT157_ADDR_HI = 0x1c275 # macro +regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT157_MSG_DATA = 0x1c276 # macro +regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT157_CONTROL = 0x1c277 # macro +regPCIEMSIX_VECT157_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT158_ADDR_LO = 0x1c278 # macro +regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT158_ADDR_HI = 0x1c279 # macro +regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT158_MSG_DATA = 0x1c27a # macro +regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT158_CONTROL = 0x1c27b # macro +regPCIEMSIX_VECT158_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT159_ADDR_LO = 0x1c27c # macro +regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT159_ADDR_HI = 0x1c27d # macro +regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT159_MSG_DATA = 0x1c27e # macro +regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT159_CONTROL = 0x1c27f # macro +regPCIEMSIX_VECT159_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT160_ADDR_LO = 0x1c280 # macro +regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT160_ADDR_HI = 0x1c281 # macro +regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT160_MSG_DATA = 0x1c282 # macro +regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT160_CONTROL = 0x1c283 # macro +regPCIEMSIX_VECT160_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT161_ADDR_LO = 0x1c284 # macro +regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT161_ADDR_HI = 0x1c285 # macro +regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT161_MSG_DATA = 0x1c286 # macro +regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT161_CONTROL = 0x1c287 # macro +regPCIEMSIX_VECT161_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT162_ADDR_LO = 0x1c288 # macro +regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT162_ADDR_HI = 0x1c289 # macro +regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT162_MSG_DATA = 0x1c28a # macro +regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT162_CONTROL = 0x1c28b # macro +regPCIEMSIX_VECT162_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT163_ADDR_LO = 0x1c28c # macro +regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT163_ADDR_HI = 0x1c28d # macro +regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT163_MSG_DATA = 0x1c28e # macro +regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT163_CONTROL = 0x1c28f # macro +regPCIEMSIX_VECT163_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT164_ADDR_LO = 0x1c290 # macro +regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT164_ADDR_HI = 0x1c291 # macro +regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT164_MSG_DATA = 0x1c292 # macro +regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT164_CONTROL = 0x1c293 # macro +regPCIEMSIX_VECT164_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT165_ADDR_LO = 0x1c294 # macro +regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT165_ADDR_HI = 0x1c295 # macro +regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT165_MSG_DATA = 0x1c296 # macro +regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT165_CONTROL = 0x1c297 # macro +regPCIEMSIX_VECT165_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT166_ADDR_LO = 0x1c298 # macro +regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT166_ADDR_HI = 0x1c299 # macro +regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT166_MSG_DATA = 0x1c29a # macro +regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT166_CONTROL = 0x1c29b # macro +regPCIEMSIX_VECT166_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT167_ADDR_LO = 0x1c29c # macro +regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT167_ADDR_HI = 0x1c29d # macro +regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT167_MSG_DATA = 0x1c29e # macro +regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT167_CONTROL = 0x1c29f # macro +regPCIEMSIX_VECT167_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT168_ADDR_LO = 0x1c2a0 # macro +regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT168_ADDR_HI = 0x1c2a1 # macro +regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT168_MSG_DATA = 0x1c2a2 # macro +regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT168_CONTROL = 0x1c2a3 # macro +regPCIEMSIX_VECT168_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT169_ADDR_LO = 0x1c2a4 # macro +regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT169_ADDR_HI = 0x1c2a5 # macro +regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT169_MSG_DATA = 0x1c2a6 # macro +regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT169_CONTROL = 0x1c2a7 # macro +regPCIEMSIX_VECT169_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT170_ADDR_LO = 0x1c2a8 # macro +regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT170_ADDR_HI = 0x1c2a9 # macro +regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT170_MSG_DATA = 0x1c2aa # macro +regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT170_CONTROL = 0x1c2ab # macro +regPCIEMSIX_VECT170_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT171_ADDR_LO = 0x1c2ac # macro +regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT171_ADDR_HI = 0x1c2ad # macro +regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT171_MSG_DATA = 0x1c2ae # macro +regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT171_CONTROL = 0x1c2af # macro +regPCIEMSIX_VECT171_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT172_ADDR_LO = 0x1c2b0 # macro +regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT172_ADDR_HI = 0x1c2b1 # macro +regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT172_MSG_DATA = 0x1c2b2 # macro +regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT172_CONTROL = 0x1c2b3 # macro +regPCIEMSIX_VECT172_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT173_ADDR_LO = 0x1c2b4 # macro +regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT173_ADDR_HI = 0x1c2b5 # macro +regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT173_MSG_DATA = 0x1c2b6 # macro +regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT173_CONTROL = 0x1c2b7 # macro +regPCIEMSIX_VECT173_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT174_ADDR_LO = 0x1c2b8 # macro +regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT174_ADDR_HI = 0x1c2b9 # macro +regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT174_MSG_DATA = 0x1c2ba # macro +regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT174_CONTROL = 0x1c2bb # macro +regPCIEMSIX_VECT174_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT175_ADDR_LO = 0x1c2bc # macro +regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT175_ADDR_HI = 0x1c2bd # macro +regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT175_MSG_DATA = 0x1c2be # macro +regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT175_CONTROL = 0x1c2bf # macro +regPCIEMSIX_VECT175_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT176_ADDR_LO = 0x1c2c0 # macro +regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT176_ADDR_HI = 0x1c2c1 # macro +regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT176_MSG_DATA = 0x1c2c2 # macro +regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT176_CONTROL = 0x1c2c3 # macro +regPCIEMSIX_VECT176_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT177_ADDR_LO = 0x1c2c4 # macro +regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT177_ADDR_HI = 0x1c2c5 # macro +regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT177_MSG_DATA = 0x1c2c6 # macro +regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT177_CONTROL = 0x1c2c7 # macro +regPCIEMSIX_VECT177_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT178_ADDR_LO = 0x1c2c8 # macro +regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT178_ADDR_HI = 0x1c2c9 # macro +regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT178_MSG_DATA = 0x1c2ca # macro +regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT178_CONTROL = 0x1c2cb # macro +regPCIEMSIX_VECT178_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT179_ADDR_LO = 0x1c2cc # macro +regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT179_ADDR_HI = 0x1c2cd # macro +regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT179_MSG_DATA = 0x1c2ce # macro +regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT179_CONTROL = 0x1c2cf # macro +regPCIEMSIX_VECT179_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT180_ADDR_LO = 0x1c2d0 # macro +regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT180_ADDR_HI = 0x1c2d1 # macro +regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT180_MSG_DATA = 0x1c2d2 # macro +regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT180_CONTROL = 0x1c2d3 # macro +regPCIEMSIX_VECT180_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT181_ADDR_LO = 0x1c2d4 # macro +regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT181_ADDR_HI = 0x1c2d5 # macro +regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT181_MSG_DATA = 0x1c2d6 # macro +regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT181_CONTROL = 0x1c2d7 # macro +regPCIEMSIX_VECT181_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT182_ADDR_LO = 0x1c2d8 # macro +regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT182_ADDR_HI = 0x1c2d9 # macro +regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT182_MSG_DATA = 0x1c2da # macro +regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT182_CONTROL = 0x1c2db # macro +regPCIEMSIX_VECT182_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT183_ADDR_LO = 0x1c2dc # macro +regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT183_ADDR_HI = 0x1c2dd # macro +regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT183_MSG_DATA = 0x1c2de # macro +regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT183_CONTROL = 0x1c2df # macro +regPCIEMSIX_VECT183_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT184_ADDR_LO = 0x1c2e0 # macro +regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT184_ADDR_HI = 0x1c2e1 # macro +regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT184_MSG_DATA = 0x1c2e2 # macro +regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT184_CONTROL = 0x1c2e3 # macro +regPCIEMSIX_VECT184_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT185_ADDR_LO = 0x1c2e4 # macro +regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT185_ADDR_HI = 0x1c2e5 # macro +regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT185_MSG_DATA = 0x1c2e6 # macro +regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT185_CONTROL = 0x1c2e7 # macro +regPCIEMSIX_VECT185_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT186_ADDR_LO = 0x1c2e8 # macro +regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT186_ADDR_HI = 0x1c2e9 # macro +regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT186_MSG_DATA = 0x1c2ea # macro +regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT186_CONTROL = 0x1c2eb # macro +regPCIEMSIX_VECT186_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT187_ADDR_LO = 0x1c2ec # macro +regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT187_ADDR_HI = 0x1c2ed # macro +regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT187_MSG_DATA = 0x1c2ee # macro +regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT187_CONTROL = 0x1c2ef # macro +regPCIEMSIX_VECT187_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT188_ADDR_LO = 0x1c2f0 # macro +regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT188_ADDR_HI = 0x1c2f1 # macro +regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT188_MSG_DATA = 0x1c2f2 # macro +regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT188_CONTROL = 0x1c2f3 # macro +regPCIEMSIX_VECT188_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT189_ADDR_LO = 0x1c2f4 # macro +regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT189_ADDR_HI = 0x1c2f5 # macro +regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT189_MSG_DATA = 0x1c2f6 # macro +regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT189_CONTROL = 0x1c2f7 # macro +regPCIEMSIX_VECT189_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT190_ADDR_LO = 0x1c2f8 # macro +regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT190_ADDR_HI = 0x1c2f9 # macro +regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT190_MSG_DATA = 0x1c2fa # macro +regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT190_CONTROL = 0x1c2fb # macro +regPCIEMSIX_VECT190_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT191_ADDR_LO = 0x1c2fc # macro +regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT191_ADDR_HI = 0x1c2fd # macro +regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT191_MSG_DATA = 0x1c2fe # macro +regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT191_CONTROL = 0x1c2ff # macro +regPCIEMSIX_VECT191_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT192_ADDR_LO = 0x1c300 # macro +regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT192_ADDR_HI = 0x1c301 # macro +regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT192_MSG_DATA = 0x1c302 # macro +regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT192_CONTROL = 0x1c303 # macro +regPCIEMSIX_VECT192_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT193_ADDR_LO = 0x1c304 # macro +regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT193_ADDR_HI = 0x1c305 # macro +regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT193_MSG_DATA = 0x1c306 # macro +regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT193_CONTROL = 0x1c307 # macro +regPCIEMSIX_VECT193_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT194_ADDR_LO = 0x1c308 # macro +regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT194_ADDR_HI = 0x1c309 # macro +regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT194_MSG_DATA = 0x1c30a # macro +regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT194_CONTROL = 0x1c30b # macro +regPCIEMSIX_VECT194_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT195_ADDR_LO = 0x1c30c # macro +regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT195_ADDR_HI = 0x1c30d # macro +regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT195_MSG_DATA = 0x1c30e # macro +regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT195_CONTROL = 0x1c30f # macro +regPCIEMSIX_VECT195_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT196_ADDR_LO = 0x1c310 # macro +regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT196_ADDR_HI = 0x1c311 # macro +regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT196_MSG_DATA = 0x1c312 # macro +regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT196_CONTROL = 0x1c313 # macro +regPCIEMSIX_VECT196_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT197_ADDR_LO = 0x1c314 # macro +regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT197_ADDR_HI = 0x1c315 # macro +regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT197_MSG_DATA = 0x1c316 # macro +regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT197_CONTROL = 0x1c317 # macro +regPCIEMSIX_VECT197_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT198_ADDR_LO = 0x1c318 # macro +regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT198_ADDR_HI = 0x1c319 # macro +regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT198_MSG_DATA = 0x1c31a # macro +regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT198_CONTROL = 0x1c31b # macro +regPCIEMSIX_VECT198_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT199_ADDR_LO = 0x1c31c # macro +regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT199_ADDR_HI = 0x1c31d # macro +regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT199_MSG_DATA = 0x1c31e # macro +regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT199_CONTROL = 0x1c31f # macro +regPCIEMSIX_VECT199_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT200_ADDR_LO = 0x1c320 # macro +regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT200_ADDR_HI = 0x1c321 # macro +regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT200_MSG_DATA = 0x1c322 # macro +regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT200_CONTROL = 0x1c323 # macro +regPCIEMSIX_VECT200_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT201_ADDR_LO = 0x1c324 # macro +regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT201_ADDR_HI = 0x1c325 # macro +regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT201_MSG_DATA = 0x1c326 # macro +regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT201_CONTROL = 0x1c327 # macro +regPCIEMSIX_VECT201_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT202_ADDR_LO = 0x1c328 # macro +regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT202_ADDR_HI = 0x1c329 # macro +regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT202_MSG_DATA = 0x1c32a # macro +regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT202_CONTROL = 0x1c32b # macro +regPCIEMSIX_VECT202_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT203_ADDR_LO = 0x1c32c # macro +regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT203_ADDR_HI = 0x1c32d # macro +regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT203_MSG_DATA = 0x1c32e # macro +regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT203_CONTROL = 0x1c32f # macro +regPCIEMSIX_VECT203_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT204_ADDR_LO = 0x1c330 # macro +regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT204_ADDR_HI = 0x1c331 # macro +regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT204_MSG_DATA = 0x1c332 # macro +regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT204_CONTROL = 0x1c333 # macro +regPCIEMSIX_VECT204_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT205_ADDR_LO = 0x1c334 # macro +regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT205_ADDR_HI = 0x1c335 # macro +regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT205_MSG_DATA = 0x1c336 # macro +regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT205_CONTROL = 0x1c337 # macro +regPCIEMSIX_VECT205_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT206_ADDR_LO = 0x1c338 # macro +regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT206_ADDR_HI = 0x1c339 # macro +regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT206_MSG_DATA = 0x1c33a # macro +regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT206_CONTROL = 0x1c33b # macro +regPCIEMSIX_VECT206_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT207_ADDR_LO = 0x1c33c # macro +regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT207_ADDR_HI = 0x1c33d # macro +regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT207_MSG_DATA = 0x1c33e # macro +regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT207_CONTROL = 0x1c33f # macro +regPCIEMSIX_VECT207_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT208_ADDR_LO = 0x1c340 # macro +regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT208_ADDR_HI = 0x1c341 # macro +regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT208_MSG_DATA = 0x1c342 # macro +regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT208_CONTROL = 0x1c343 # macro +regPCIEMSIX_VECT208_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT209_ADDR_LO = 0x1c344 # macro +regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT209_ADDR_HI = 0x1c345 # macro +regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT209_MSG_DATA = 0x1c346 # macro +regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT209_CONTROL = 0x1c347 # macro +regPCIEMSIX_VECT209_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT210_ADDR_LO = 0x1c348 # macro +regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT210_ADDR_HI = 0x1c349 # macro +regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT210_MSG_DATA = 0x1c34a # macro +regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT210_CONTROL = 0x1c34b # macro +regPCIEMSIX_VECT210_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT211_ADDR_LO = 0x1c34c # macro +regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT211_ADDR_HI = 0x1c34d # macro +regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT211_MSG_DATA = 0x1c34e # macro +regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT211_CONTROL = 0x1c34f # macro +regPCIEMSIX_VECT211_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT212_ADDR_LO = 0x1c350 # macro +regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT212_ADDR_HI = 0x1c351 # macro +regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT212_MSG_DATA = 0x1c352 # macro +regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT212_CONTROL = 0x1c353 # macro +regPCIEMSIX_VECT212_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT213_ADDR_LO = 0x1c354 # macro +regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT213_ADDR_HI = 0x1c355 # macro +regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT213_MSG_DATA = 0x1c356 # macro +regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT213_CONTROL = 0x1c357 # macro +regPCIEMSIX_VECT213_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT214_ADDR_LO = 0x1c358 # macro +regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT214_ADDR_HI = 0x1c359 # macro +regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT214_MSG_DATA = 0x1c35a # macro +regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT214_CONTROL = 0x1c35b # macro +regPCIEMSIX_VECT214_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT215_ADDR_LO = 0x1c35c # macro +regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT215_ADDR_HI = 0x1c35d # macro +regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT215_MSG_DATA = 0x1c35e # macro +regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT215_CONTROL = 0x1c35f # macro +regPCIEMSIX_VECT215_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT216_ADDR_LO = 0x1c360 # macro +regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT216_ADDR_HI = 0x1c361 # macro +regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT216_MSG_DATA = 0x1c362 # macro +regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT216_CONTROL = 0x1c363 # macro +regPCIEMSIX_VECT216_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT217_ADDR_LO = 0x1c364 # macro +regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT217_ADDR_HI = 0x1c365 # macro +regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT217_MSG_DATA = 0x1c366 # macro +regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT217_CONTROL = 0x1c367 # macro +regPCIEMSIX_VECT217_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT218_ADDR_LO = 0x1c368 # macro +regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT218_ADDR_HI = 0x1c369 # macro +regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT218_MSG_DATA = 0x1c36a # macro +regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT218_CONTROL = 0x1c36b # macro +regPCIEMSIX_VECT218_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT219_ADDR_LO = 0x1c36c # macro +regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT219_ADDR_HI = 0x1c36d # macro +regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT219_MSG_DATA = 0x1c36e # macro +regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT219_CONTROL = 0x1c36f # macro +regPCIEMSIX_VECT219_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT220_ADDR_LO = 0x1c370 # macro +regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT220_ADDR_HI = 0x1c371 # macro +regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT220_MSG_DATA = 0x1c372 # macro +regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT220_CONTROL = 0x1c373 # macro +regPCIEMSIX_VECT220_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT221_ADDR_LO = 0x1c374 # macro +regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT221_ADDR_HI = 0x1c375 # macro +regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT221_MSG_DATA = 0x1c376 # macro +regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT221_CONTROL = 0x1c377 # macro +regPCIEMSIX_VECT221_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT222_ADDR_LO = 0x1c378 # macro +regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT222_ADDR_HI = 0x1c379 # macro +regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT222_MSG_DATA = 0x1c37a # macro +regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT222_CONTROL = 0x1c37b # macro +regPCIEMSIX_VECT222_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT223_ADDR_LO = 0x1c37c # macro +regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT223_ADDR_HI = 0x1c37d # macro +regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT223_MSG_DATA = 0x1c37e # macro +regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT223_CONTROL = 0x1c37f # macro +regPCIEMSIX_VECT223_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT224_ADDR_LO = 0x1c380 # macro +regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT224_ADDR_HI = 0x1c381 # macro +regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT224_MSG_DATA = 0x1c382 # macro +regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT224_CONTROL = 0x1c383 # macro +regPCIEMSIX_VECT224_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT225_ADDR_LO = 0x1c384 # macro +regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT225_ADDR_HI = 0x1c385 # macro +regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT225_MSG_DATA = 0x1c386 # macro +regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT225_CONTROL = 0x1c387 # macro +regPCIEMSIX_VECT225_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT226_ADDR_LO = 0x1c388 # macro +regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT226_ADDR_HI = 0x1c389 # macro +regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT226_MSG_DATA = 0x1c38a # macro +regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT226_CONTROL = 0x1c38b # macro +regPCIEMSIX_VECT226_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT227_ADDR_LO = 0x1c38c # macro +regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT227_ADDR_HI = 0x1c38d # macro +regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT227_MSG_DATA = 0x1c38e # macro +regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT227_CONTROL = 0x1c38f # macro +regPCIEMSIX_VECT227_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT228_ADDR_LO = 0x1c390 # macro +regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT228_ADDR_HI = 0x1c391 # macro +regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT228_MSG_DATA = 0x1c392 # macro +regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT228_CONTROL = 0x1c393 # macro +regPCIEMSIX_VECT228_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT229_ADDR_LO = 0x1c394 # macro +regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT229_ADDR_HI = 0x1c395 # macro +regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT229_MSG_DATA = 0x1c396 # macro +regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT229_CONTROL = 0x1c397 # macro +regPCIEMSIX_VECT229_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT230_ADDR_LO = 0x1c398 # macro +regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT230_ADDR_HI = 0x1c399 # macro +regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT230_MSG_DATA = 0x1c39a # macro +regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT230_CONTROL = 0x1c39b # macro +regPCIEMSIX_VECT230_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT231_ADDR_LO = 0x1c39c # macro +regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT231_ADDR_HI = 0x1c39d # macro +regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT231_MSG_DATA = 0x1c39e # macro +regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT231_CONTROL = 0x1c39f # macro +regPCIEMSIX_VECT231_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT232_ADDR_LO = 0x1c3a0 # macro +regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT232_ADDR_HI = 0x1c3a1 # macro +regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT232_MSG_DATA = 0x1c3a2 # macro +regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT232_CONTROL = 0x1c3a3 # macro +regPCIEMSIX_VECT232_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT233_ADDR_LO = 0x1c3a4 # macro +regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT233_ADDR_HI = 0x1c3a5 # macro +regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT233_MSG_DATA = 0x1c3a6 # macro +regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT233_CONTROL = 0x1c3a7 # macro +regPCIEMSIX_VECT233_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT234_ADDR_LO = 0x1c3a8 # macro +regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT234_ADDR_HI = 0x1c3a9 # macro +regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT234_MSG_DATA = 0x1c3aa # macro +regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT234_CONTROL = 0x1c3ab # macro +regPCIEMSIX_VECT234_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT235_ADDR_LO = 0x1c3ac # macro +regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT235_ADDR_HI = 0x1c3ad # macro +regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT235_MSG_DATA = 0x1c3ae # macro +regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT235_CONTROL = 0x1c3af # macro +regPCIEMSIX_VECT235_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT236_ADDR_LO = 0x1c3b0 # macro +regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT236_ADDR_HI = 0x1c3b1 # macro +regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT236_MSG_DATA = 0x1c3b2 # macro +regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT236_CONTROL = 0x1c3b3 # macro +regPCIEMSIX_VECT236_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT237_ADDR_LO = 0x1c3b4 # macro +regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT237_ADDR_HI = 0x1c3b5 # macro +regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT237_MSG_DATA = 0x1c3b6 # macro +regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT237_CONTROL = 0x1c3b7 # macro +regPCIEMSIX_VECT237_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT238_ADDR_LO = 0x1c3b8 # macro +regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT238_ADDR_HI = 0x1c3b9 # macro +regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT238_MSG_DATA = 0x1c3ba # macro +regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT238_CONTROL = 0x1c3bb # macro +regPCIEMSIX_VECT238_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT239_ADDR_LO = 0x1c3bc # macro +regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT239_ADDR_HI = 0x1c3bd # macro +regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT239_MSG_DATA = 0x1c3be # macro +regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT239_CONTROL = 0x1c3bf # macro +regPCIEMSIX_VECT239_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT240_ADDR_LO = 0x1c3c0 # macro +regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT240_ADDR_HI = 0x1c3c1 # macro +regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT240_MSG_DATA = 0x1c3c2 # macro +regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT240_CONTROL = 0x1c3c3 # macro +regPCIEMSIX_VECT240_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT241_ADDR_LO = 0x1c3c4 # macro +regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT241_ADDR_HI = 0x1c3c5 # macro +regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT241_MSG_DATA = 0x1c3c6 # macro +regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT241_CONTROL = 0x1c3c7 # macro +regPCIEMSIX_VECT241_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT242_ADDR_LO = 0x1c3c8 # macro +regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT242_ADDR_HI = 0x1c3c9 # macro +regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT242_MSG_DATA = 0x1c3ca # macro +regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT242_CONTROL = 0x1c3cb # macro +regPCIEMSIX_VECT242_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT243_ADDR_LO = 0x1c3cc # macro +regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT243_ADDR_HI = 0x1c3cd # macro +regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT243_MSG_DATA = 0x1c3ce # macro +regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT243_CONTROL = 0x1c3cf # macro +regPCIEMSIX_VECT243_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT244_ADDR_LO = 0x1c3d0 # macro +regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT244_ADDR_HI = 0x1c3d1 # macro +regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT244_MSG_DATA = 0x1c3d2 # macro +regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT244_CONTROL = 0x1c3d3 # macro +regPCIEMSIX_VECT244_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT245_ADDR_LO = 0x1c3d4 # macro +regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT245_ADDR_HI = 0x1c3d5 # macro +regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT245_MSG_DATA = 0x1c3d6 # macro +regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT245_CONTROL = 0x1c3d7 # macro +regPCIEMSIX_VECT245_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT246_ADDR_LO = 0x1c3d8 # macro +regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT246_ADDR_HI = 0x1c3d9 # macro +regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT246_MSG_DATA = 0x1c3da # macro +regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT246_CONTROL = 0x1c3db # macro +regPCIEMSIX_VECT246_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT247_ADDR_LO = 0x1c3dc # macro +regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT247_ADDR_HI = 0x1c3dd # macro +regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT247_MSG_DATA = 0x1c3de # macro +regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT247_CONTROL = 0x1c3df # macro +regPCIEMSIX_VECT247_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT248_ADDR_LO = 0x1c3e0 # macro +regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT248_ADDR_HI = 0x1c3e1 # macro +regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT248_MSG_DATA = 0x1c3e2 # macro +regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT248_CONTROL = 0x1c3e3 # macro +regPCIEMSIX_VECT248_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT249_ADDR_LO = 0x1c3e4 # macro +regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT249_ADDR_HI = 0x1c3e5 # macro +regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT249_MSG_DATA = 0x1c3e6 # macro +regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT249_CONTROL = 0x1c3e7 # macro +regPCIEMSIX_VECT249_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT250_ADDR_LO = 0x1c3e8 # macro +regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT250_ADDR_HI = 0x1c3e9 # macro +regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT250_MSG_DATA = 0x1c3ea # macro +regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT250_CONTROL = 0x1c3eb # macro +regPCIEMSIX_VECT250_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT251_ADDR_LO = 0x1c3ec # macro +regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT251_ADDR_HI = 0x1c3ed # macro +regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT251_MSG_DATA = 0x1c3ee # macro +regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT251_CONTROL = 0x1c3ef # macro +regPCIEMSIX_VECT251_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT252_ADDR_LO = 0x1c3f0 # macro +regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT252_ADDR_HI = 0x1c3f1 # macro +regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT252_MSG_DATA = 0x1c3f2 # macro +regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT252_CONTROL = 0x1c3f3 # macro +regPCIEMSIX_VECT252_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT253_ADDR_LO = 0x1c3f4 # macro +regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT253_ADDR_HI = 0x1c3f5 # macro +regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT253_MSG_DATA = 0x1c3f6 # macro +regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT253_CONTROL = 0x1c3f7 # macro +regPCIEMSIX_VECT253_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT254_ADDR_LO = 0x1c3f8 # macro +regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT254_ADDR_HI = 0x1c3f9 # macro +regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT254_MSG_DATA = 0x1c3fa # macro +regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT254_CONTROL = 0x1c3fb # macro +regPCIEMSIX_VECT254_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_VECT255_ADDR_LO = 0x1c3fc # macro +regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX = 5 # macro +regPCIEMSIX_VECT255_ADDR_HI = 0x1c3fd # macro +regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX = 5 # macro +regPCIEMSIX_VECT255_MSG_DATA = 0x1c3fe # macro +regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX = 5 # macro +regPCIEMSIX_VECT255_CONTROL = 0x1c3ff # macro +regPCIEMSIX_VECT255_CONTROL_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_0 = 0x1c400 # macro +regPCIEMSIX_PBA_0_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_1 = 0x1c401 # macro +regPCIEMSIX_PBA_1_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_2 = 0x1c402 # macro +regPCIEMSIX_PBA_2_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_3 = 0x1c403 # macro +regPCIEMSIX_PBA_3_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_4 = 0x1c404 # macro +regPCIEMSIX_PBA_4_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_5 = 0x1c405 # macro +regPCIEMSIX_PBA_5_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_6 = 0x1c406 # macro +regPCIEMSIX_PBA_6_BASE_IDX = 5 # macro +regPCIEMSIX_PBA_7 = 0x1c407 # macro +regPCIEMSIX_PBA_7_BASE_IDX = 5 # macro +regSHADOW_COMMAND = 0xc001 # macro +regSHADOW_COMMAND_BASE_IDX = 5 # macro +regSHADOW_BASE_ADDR_1 = 0xc004 # macro +regSHADOW_BASE_ADDR_1_BASE_IDX = 5 # macro +regSHADOW_BASE_ADDR_2 = 0xc005 # macro +regSHADOW_BASE_ADDR_2_BASE_IDX = 5 # macro +regSHADOW_SUB_BUS_NUMBER_LATENCY = 0xc006 # macro +regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX = 5 # macro +regSHADOW_IO_BASE_LIMIT = 0xc007 # macro +regSHADOW_IO_BASE_LIMIT_BASE_IDX = 5 # macro +regSHADOW_MEM_BASE_LIMIT = 0xc008 # macro +regSHADOW_MEM_BASE_LIMIT_BASE_IDX = 5 # macro +regSHADOW_PREF_BASE_LIMIT = 0xc009 # macro +regSHADOW_PREF_BASE_LIMIT_BASE_IDX = 5 # macro +regSHADOW_PREF_BASE_UPPER = 0xc00a # macro +regSHADOW_PREF_BASE_UPPER_BASE_IDX = 5 # macro +regSHADOW_PREF_LIMIT_UPPER = 0xc00b # macro +regSHADOW_PREF_LIMIT_UPPER_BASE_IDX = 5 # macro +regSHADOW_IO_BASE_LIMIT_HI = 0xc00c # macro +regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX = 5 # macro +regSUC_INDEX = 0xc038 # macro +regSUC_INDEX_BASE_IDX = 5 # macro +regSUC_DATA = 0xc039 # macro +regSUC_DATA_BASE_IDX = 5 # macro +regSUM_INDEX = 0xec38 # macro +regSUM_INDEX_BASE_IDX = 5 # macro +regSUM_DATA = 0xec39 # macro +regSUM_DATA_BASE_IDX = 5 # macro +regSUM_INDEX_HI = 0xec3b # macro +regSUM_INDEX_HI_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 = 0xc400 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 = 0xc401 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 = 0xc402 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 = 0xc403 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 = 0xc404 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 = 0xc405 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 = 0xc406 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 = 0xc407 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 = 0xc408 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 = 0xc409 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 = 0xc40a # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 = 0xc40b # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 = 0xc40c # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 = 0xc40d # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 = 0xc40e # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP0 = 0xc480 # macro +regRCC_DEV1_PORT_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP1 = 0xc481 # macro +regRCC_DEV1_PORT_STRAP1_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP2 = 0xc482 # macro +regRCC_DEV1_PORT_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP3 = 0xc483 # macro +regRCC_DEV1_PORT_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP4 = 0xc484 # macro +regRCC_DEV1_PORT_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP5 = 0xc485 # macro +regRCC_DEV1_PORT_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP6 = 0xc486 # macro +regRCC_DEV1_PORT_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP7 = 0xc487 # macro +regRCC_DEV1_PORT_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP8 = 0xc488 # macro +regRCC_DEV1_PORT_STRAP8_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP9 = 0xc489 # macro +regRCC_DEV1_PORT_STRAP9_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP10 = 0xc48a # macro +regRCC_DEV1_PORT_STRAP10_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP11 = 0xc48b # macro +regRCC_DEV1_PORT_STRAP11_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP12 = 0xc48c # macro +regRCC_DEV1_PORT_STRAP12_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP13 = 0xc48d # macro +regRCC_DEV1_PORT_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV1_PORT_STRAP14 = 0xc48e # macro +regRCC_DEV1_PORT_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP0 = 0xc500 # macro +regRCC_DEV2_PORT_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP1 = 0xc501 # macro +regRCC_DEV2_PORT_STRAP1_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP2 = 0xc502 # macro +regRCC_DEV2_PORT_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP3 = 0xc503 # macro +regRCC_DEV2_PORT_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP4 = 0xc504 # macro +regRCC_DEV2_PORT_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP5 = 0xc505 # macro +regRCC_DEV2_PORT_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP6 = 0xc506 # macro +regRCC_DEV2_PORT_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP7 = 0xc507 # macro +regRCC_DEV2_PORT_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP8 = 0xc508 # macro +regRCC_DEV2_PORT_STRAP8_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP9 = 0xc509 # macro +regRCC_DEV2_PORT_STRAP9_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP10 = 0xc50a # macro +regRCC_DEV2_PORT_STRAP10_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP11 = 0xc50b # macro +regRCC_DEV2_PORT_STRAP11_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP12 = 0xc50c # macro +regRCC_DEV2_PORT_STRAP12_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP13 = 0xc50d # macro +regRCC_DEV2_PORT_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV2_PORT_STRAP14 = 0xc50e # macro +regRCC_DEV2_PORT_STRAP14_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_BIF_STRAP0 = 0xc600 # macro +regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_BIF_STRAP1 = 0xc601 # macro +regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_BIF_STRAP2 = 0xc602 # macro +regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_BIF_STRAP3 = 0xc603 # macro +regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_BIF_STRAP4 = 0xc604 # macro +regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_BIF_STRAP5 = 0xc605 # macro +regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_BIF_STRAP6 = 0xc606 # macro +regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 = 0xd000 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 = 0xd001 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 = 0xd002 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 = 0xd003 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 = 0xd004 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 = 0xd005 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 = 0xd008 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 = 0xd009 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 = 0xd00d # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 = 0xd00e # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 = 0xd00f # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 = 0xd010 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 = 0xd011 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 = 0xd012 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 = 0xd01a # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 = 0xd080 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 = 0xd082 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 = 0xd083 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 = 0xd084 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 = 0xd085 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 = 0xd086 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 = 0xd087 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 = 0xd094 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 = 0xd095 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 = 0xd096 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 = 0xd097 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 = 0xd098 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX = 5 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 = 0xd099 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP0 = 0xd100 # macro +regRCC_DEV0_EPF2_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP2 = 0xd102 # macro +regRCC_DEV0_EPF2_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP3 = 0xd103 # macro +regRCC_DEV0_EPF2_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP4 = 0xd104 # macro +regRCC_DEV0_EPF2_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP5 = 0xd105 # macro +regRCC_DEV0_EPF2_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP6 = 0xd106 # macro +regRCC_DEV0_EPF2_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP7 = 0xd107 # macro +regRCC_DEV0_EPF2_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP10 = 0xd10a # macro +regRCC_DEV0_EPF2_STRAP10_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP11 = 0xd10b # macro +regRCC_DEV0_EPF2_STRAP11_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP12 = 0xd10c # macro +regRCC_DEV0_EPF2_STRAP12_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP13 = 0xd10d # macro +regRCC_DEV0_EPF2_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP14 = 0xd10e # macro +regRCC_DEV0_EPF2_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV0_EPF2_STRAP20 = 0xd114 # macro +regRCC_DEV0_EPF2_STRAP20_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP0 = 0xd180 # macro +regRCC_DEV0_EPF3_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP2 = 0xd182 # macro +regRCC_DEV0_EPF3_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP3 = 0xd183 # macro +regRCC_DEV0_EPF3_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP4 = 0xd184 # macro +regRCC_DEV0_EPF3_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP5 = 0xd185 # macro +regRCC_DEV0_EPF3_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP6 = 0xd186 # macro +regRCC_DEV0_EPF3_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP7 = 0xd187 # macro +regRCC_DEV0_EPF3_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP10 = 0xd18a # macro +regRCC_DEV0_EPF3_STRAP10_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP11 = 0xd18b # macro +regRCC_DEV0_EPF3_STRAP11_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP12 = 0xd18c # macro +regRCC_DEV0_EPF3_STRAP12_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP13 = 0xd18d # macro +regRCC_DEV0_EPF3_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP14 = 0xd18e # macro +regRCC_DEV0_EPF3_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV0_EPF3_STRAP20 = 0xd194 # macro +regRCC_DEV0_EPF3_STRAP20_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP0 = 0xd200 # macro +regRCC_DEV0_EPF4_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP2 = 0xd202 # macro +regRCC_DEV0_EPF4_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP3 = 0xd203 # macro +regRCC_DEV0_EPF4_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP4 = 0xd204 # macro +regRCC_DEV0_EPF4_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP5 = 0xd205 # macro +regRCC_DEV0_EPF4_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP6 = 0xd206 # macro +regRCC_DEV0_EPF4_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP7 = 0xd207 # macro +regRCC_DEV0_EPF4_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP13 = 0xd20d # macro +regRCC_DEV0_EPF4_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV0_EPF4_STRAP14 = 0xd20e # macro +regRCC_DEV0_EPF4_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP0 = 0xd280 # macro +regRCC_DEV0_EPF5_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP2 = 0xd282 # macro +regRCC_DEV0_EPF5_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP3 = 0xd283 # macro +regRCC_DEV0_EPF5_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP4 = 0xd284 # macro +regRCC_DEV0_EPF5_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP5 = 0xd285 # macro +regRCC_DEV0_EPF5_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP6 = 0xd286 # macro +regRCC_DEV0_EPF5_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP7 = 0xd287 # macro +regRCC_DEV0_EPF5_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP13 = 0xd28d # macro +regRCC_DEV0_EPF5_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV0_EPF5_STRAP14 = 0xd28e # macro +regRCC_DEV0_EPF5_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP0 = 0xd300 # macro +regRCC_DEV0_EPF6_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP2 = 0xd302 # macro +regRCC_DEV0_EPF6_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP3 = 0xd303 # macro +regRCC_DEV0_EPF6_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP4 = 0xd304 # macro +regRCC_DEV0_EPF6_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP5 = 0xd305 # macro +regRCC_DEV0_EPF6_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP6 = 0xd306 # macro +regRCC_DEV0_EPF6_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP13 = 0xd30d # macro +regRCC_DEV0_EPF6_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV0_EPF6_STRAP14 = 0xd30e # macro +regRCC_DEV0_EPF6_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP0 = 0xd380 # macro +regRCC_DEV0_EPF7_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP2 = 0xd382 # macro +regRCC_DEV0_EPF7_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP3 = 0xd383 # macro +regRCC_DEV0_EPF7_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP4 = 0xd384 # macro +regRCC_DEV0_EPF7_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP5 = 0xd385 # macro +regRCC_DEV0_EPF7_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP6 = 0xd386 # macro +regRCC_DEV0_EPF7_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP7 = 0xd387 # macro +regRCC_DEV0_EPF7_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP13 = 0xd38d # macro +regRCC_DEV0_EPF7_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV0_EPF7_STRAP14 = 0xd38e # macro +regRCC_DEV0_EPF7_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP0 = 0xd400 # macro +regRCC_DEV1_EPF0_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP2 = 0xd402 # macro +regRCC_DEV1_EPF0_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP3 = 0xd403 # macro +regRCC_DEV1_EPF0_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP4 = 0xd404 # macro +regRCC_DEV1_EPF0_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP5 = 0xd405 # macro +regRCC_DEV1_EPF0_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP6 = 0xd406 # macro +regRCC_DEV1_EPF0_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP7 = 0xd407 # macro +regRCC_DEV1_EPF0_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP13 = 0xd40d # macro +regRCC_DEV1_EPF0_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV1_EPF0_STRAP14 = 0xd40e # macro +regRCC_DEV1_EPF0_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP0 = 0xd480 # macro +regRCC_DEV1_EPF1_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP2 = 0xd482 # macro +regRCC_DEV1_EPF1_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP3 = 0xd483 # macro +regRCC_DEV1_EPF1_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP4 = 0xd484 # macro +regRCC_DEV1_EPF1_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP5 = 0xd485 # macro +regRCC_DEV1_EPF1_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP6 = 0xd486 # macro +regRCC_DEV1_EPF1_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP7 = 0xd487 # macro +regRCC_DEV1_EPF1_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP13 = 0xd48d # macro +regRCC_DEV1_EPF1_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV1_EPF1_STRAP14 = 0xd48e # macro +regRCC_DEV1_EPF1_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP0 = 0xd500 # macro +regRCC_DEV1_EPF2_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP2 = 0xd502 # macro +regRCC_DEV1_EPF2_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP3 = 0xd503 # macro +regRCC_DEV1_EPF2_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP4 = 0xd504 # macro +regRCC_DEV1_EPF2_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP5 = 0xd505 # macro +regRCC_DEV1_EPF2_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP6 = 0xd506 # macro +regRCC_DEV1_EPF2_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP13 = 0xd50d # macro +regRCC_DEV1_EPF2_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV1_EPF2_STRAP14 = 0xd50e # macro +regRCC_DEV1_EPF2_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP0 = 0xd580 # macro +regRCC_DEV1_EPF3_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP2 = 0xd582 # macro +regRCC_DEV1_EPF3_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP3 = 0xd583 # macro +regRCC_DEV1_EPF3_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP4 = 0xd584 # macro +regRCC_DEV1_EPF3_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP5 = 0xd585 # macro +regRCC_DEV1_EPF3_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP6 = 0xd586 # macro +regRCC_DEV1_EPF3_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP13 = 0xd58d # macro +regRCC_DEV1_EPF3_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV1_EPF3_STRAP14 = 0xd58e # macro +regRCC_DEV1_EPF3_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP0 = 0xd600 # macro +regRCC_DEV1_EPF4_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP2 = 0xd602 # macro +regRCC_DEV1_EPF4_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP3 = 0xd603 # macro +regRCC_DEV1_EPF4_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP4 = 0xd604 # macro +regRCC_DEV1_EPF4_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP5 = 0xd605 # macro +regRCC_DEV1_EPF4_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP6 = 0xd606 # macro +regRCC_DEV1_EPF4_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP13 = 0xd60d # macro +regRCC_DEV1_EPF4_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV1_EPF4_STRAP14 = 0xd60e # macro +regRCC_DEV1_EPF4_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP0 = 0xd680 # macro +regRCC_DEV1_EPF5_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP2 = 0xd682 # macro +regRCC_DEV1_EPF5_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP3 = 0xd683 # macro +regRCC_DEV1_EPF5_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP4 = 0xd684 # macro +regRCC_DEV1_EPF5_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP5 = 0xd685 # macro +regRCC_DEV1_EPF5_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP6 = 0xd686 # macro +regRCC_DEV1_EPF5_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP13 = 0xd68d # macro +regRCC_DEV1_EPF5_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV1_EPF5_STRAP14 = 0xd68e # macro +regRCC_DEV1_EPF5_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP0 = 0xd800 # macro +regRCC_DEV2_EPF0_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP2 = 0xd802 # macro +regRCC_DEV2_EPF0_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP3 = 0xd803 # macro +regRCC_DEV2_EPF0_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP4 = 0xd804 # macro +regRCC_DEV2_EPF0_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP5 = 0xd805 # macro +regRCC_DEV2_EPF0_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP6 = 0xd806 # macro +regRCC_DEV2_EPF0_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP7 = 0xd807 # macro +regRCC_DEV2_EPF0_STRAP7_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP13 = 0xd80d # macro +regRCC_DEV2_EPF0_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV2_EPF0_STRAP14 = 0xd80e # macro +regRCC_DEV2_EPF0_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP0 = 0xd880 # macro +regRCC_DEV2_EPF1_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP2 = 0xd882 # macro +regRCC_DEV2_EPF1_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP3 = 0xd883 # macro +regRCC_DEV2_EPF1_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP4 = 0xd884 # macro +regRCC_DEV2_EPF1_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP5 = 0xd885 # macro +regRCC_DEV2_EPF1_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP6 = 0xd886 # macro +regRCC_DEV2_EPF1_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP13 = 0xd88d # macro +regRCC_DEV2_EPF1_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV2_EPF1_STRAP14 = 0xd88e # macro +regRCC_DEV2_EPF1_STRAP14_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP0 = 0xd900 # macro +regRCC_DEV2_EPF2_STRAP0_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP2 = 0xd902 # macro +regRCC_DEV2_EPF2_STRAP2_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP3 = 0xd903 # macro +regRCC_DEV2_EPF2_STRAP3_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP4 = 0xd904 # macro +regRCC_DEV2_EPF2_STRAP4_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP5 = 0xd905 # macro +regRCC_DEV2_EPF2_STRAP5_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP6 = 0xd906 # macro +regRCC_DEV2_EPF2_STRAP6_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP13 = 0xd90d # macro +regRCC_DEV2_EPF2_STRAP13_BASE_IDX = 5 # macro +regRCC_DEV2_EPF2_STRAP14 = 0xd90e # macro +regRCC_DEV2_EPF2_STRAP14_BASE_IDX = 5 # macro +regHARD_RST_CTRL = 0xe000 # macro +regHARD_RST_CTRL_BASE_IDX = 5 # macro +regSELF_SOFT_RST = 0xe002 # macro +regSELF_SOFT_RST_BASE_IDX = 5 # macro +regBIF_GFX_DRV_VPU_RST = 0xe003 # macro +regBIF_GFX_DRV_VPU_RST_BASE_IDX = 5 # macro +regBIF_RST_MISC_CTRL = 0xe004 # macro +regBIF_RST_MISC_CTRL_BASE_IDX = 5 # macro +regBIF_RST_MISC_CTRL2 = 0xe005 # macro +regBIF_RST_MISC_CTRL2_BASE_IDX = 5 # macro +regBIF_RST_MISC_CTRL3 = 0xe006 # macro +regBIF_RST_MISC_CTRL3_BASE_IDX = 5 # macro +regDEV0_PF0_FLR_RST_CTRL = 0xe008 # macro +regDEV0_PF0_FLR_RST_CTRL_BASE_IDX = 5 # macro +regDEV0_PF1_FLR_RST_CTRL = 0xe009 # macro +regDEV0_PF1_FLR_RST_CTRL_BASE_IDX = 5 # macro +regDEV0_PF2_FLR_RST_CTRL = 0xe00a # macro +regDEV0_PF2_FLR_RST_CTRL_BASE_IDX = 5 # macro +regDEV0_PF3_FLR_RST_CTRL = 0xe00b # macro +regDEV0_PF3_FLR_RST_CTRL_BASE_IDX = 5 # macro +regBIF_INST_RESET_INTR_STS = 0xe010 # macro +regBIF_INST_RESET_INTR_STS_BASE_IDX = 5 # macro +regBIF_PF_FLR_INTR_STS = 0xe011 # macro +regBIF_PF_FLR_INTR_STS_BASE_IDX = 5 # macro +regBIF_D3HOTD0_INTR_STS = 0xe012 # macro +regBIF_D3HOTD0_INTR_STS_BASE_IDX = 5 # macro +regBIF_POWER_INTR_STS = 0xe014 # macro +regBIF_POWER_INTR_STS_BASE_IDX = 5 # macro +regBIF_PF_DSTATE_INTR_STS = 0xe015 # macro +regBIF_PF_DSTATE_INTR_STS_BASE_IDX = 5 # macro +regSELF_SOFT_RST_2 = 0xe016 # macro +regSELF_SOFT_RST_2_BASE_IDX = 5 # macro +regBIF_INST_RESET_INTR_MASK = 0xe020 # macro +regBIF_INST_RESET_INTR_MASK_BASE_IDX = 5 # macro +regBIF_PF_FLR_INTR_MASK = 0xe021 # macro +regBIF_PF_FLR_INTR_MASK_BASE_IDX = 5 # macro +regBIF_D3HOTD0_INTR_MASK = 0xe022 # macro +regBIF_D3HOTD0_INTR_MASK_BASE_IDX = 5 # macro +regBIF_POWER_INTR_MASK = 0xe024 # macro +regBIF_POWER_INTR_MASK_BASE_IDX = 5 # macro +regBIF_PF_DSTATE_INTR_MASK = 0xe025 # macro +regBIF_PF_DSTATE_INTR_MASK_BASE_IDX = 5 # macro +regBIF_PF_FLR_RST = 0xe040 # macro +regBIF_PF_FLR_RST_BASE_IDX = 5 # macro +regBIF_DEV0_PF0_DSTATE_VALUE = 0xe050 # macro +regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX = 5 # macro +regBIF_DEV0_PF1_DSTATE_VALUE = 0xe051 # macro +regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX = 5 # macro +regBIF_DEV0_PF2_DSTATE_VALUE = 0xe052 # macro +regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX = 5 # macro +regBIF_DEV0_PF3_DSTATE_VALUE = 0xe053 # macro +regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX = 5 # macro +regDEV0_PF0_D3HOTD0_RST_CTRL = 0xe078 # macro +regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX = 5 # macro +regDEV0_PF1_D3HOTD0_RST_CTRL = 0xe079 # macro +regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX = 5 # macro +regDEV0_PF2_D3HOTD0_RST_CTRL = 0xe07a # macro +regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX = 5 # macro +regDEV0_PF3_D3HOTD0_RST_CTRL = 0xe07b # macro +regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX = 5 # macro +regBIF_PORT0_DSTATE_VALUE = 0xe230 # macro +regBIF_PORT0_DSTATE_VALUE_BASE_IDX = 5 # macro +regREGS_ROM_OFFSET_CTRL = 0xcc23 # macro +regREGS_ROM_OFFSET_CTRL_BASE_IDX = 5 # macro +regNBIF_STRAP_BIOS_CNTL = 0xcc81 # macro +regNBIF_STRAP_BIOS_CNTL_BASE_IDX = 5 # macro +regMISC_SCRATCH = 0xe800 # macro +regMISC_SCRATCH_BASE_IDX = 5 # macro +regINTR_LINE_POLARITY = 0xe801 # macro +regINTR_LINE_POLARITY_BASE_IDX = 5 # macro +regINTR_LINE_ENABLE = 0xe802 # macro +regINTR_LINE_ENABLE_BASE_IDX = 5 # macro +regOUTSTANDING_VC_ALLOC = 0xe803 # macro +regOUTSTANDING_VC_ALLOC_BASE_IDX = 5 # macro +regBIFC_MISC_CTRL0 = 0xe804 # macro +regBIFC_MISC_CTRL0_BASE_IDX = 5 # macro +regBIFC_MISC_CTRL1 = 0xe805 # macro +regBIFC_MISC_CTRL1_BASE_IDX = 5 # macro +regBIFC_BME_ERR_LOG_LB = 0xe806 # macro +regBIFC_BME_ERR_LOG_LB_BASE_IDX = 5 # macro +regBIFC_LC_TIMER_CTRL = 0xe807 # macro +regBIFC_LC_TIMER_CTRL_BASE_IDX = 5 # macro +regBIFC_RCCBIH_BME_ERR_LOG0 = 0xe808 # macro +regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX = 5 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 = 0xe80a # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX = 5 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 = 0xe80b # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX = 5 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 = 0xe80c # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX = 5 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 = 0xe80d # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX = 5 # macro +regBIFC_DMA_ATTR_CNTL2_DEV0 = 0xe81a # macro +regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX = 5 # macro +regBME_DUMMY_CNTL_0 = 0xe825 # macro +regBME_DUMMY_CNTL_0_BASE_IDX = 5 # macro +regBIFC_HSTARB_CNTL = 0xe828 # macro +regBIFC_HSTARB_CNTL_BASE_IDX = 5 # macro +regBIFC_GSI_CNTL = 0xe829 # macro +regBIFC_GSI_CNTL_BASE_IDX = 5 # macro +regBIFC_PCIEFUNC_CNTL = 0xe82a # macro +regBIFC_PCIEFUNC_CNTL_BASE_IDX = 5 # macro +regBIFC_PASID_CHECK_DIS = 0xe82b # macro +regBIFC_PASID_CHECK_DIS_BASE_IDX = 5 # macro +regBIFC_SDP_CNTL_0 = 0xe82c # macro +regBIFC_SDP_CNTL_0_BASE_IDX = 5 # macro +regBIFC_SDP_CNTL_1 = 0xe82d # macro +regBIFC_SDP_CNTL_1_BASE_IDX = 5 # macro +regBIFC_PASID_STS = 0xe82e # macro +regBIFC_PASID_STS_BASE_IDX = 5 # macro +regBIFC_ATHUB_ACT_CNTL = 0xe82f # macro +regBIFC_ATHUB_ACT_CNTL_BASE_IDX = 5 # macro +regBIFC_PERF_CNTL_0 = 0xe830 # macro +regBIFC_PERF_CNTL_0_BASE_IDX = 5 # macro +regBIFC_PERF_CNTL_1 = 0xe831 # macro +regBIFC_PERF_CNTL_1_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_MMIO_RD_L32BIT = 0xe832 # macro +regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_MMIO_WR_L32BIT = 0xe833 # macro +regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_DMA_RD_L32BIT = 0xe834 # macro +regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_DMA_WR_L32BIT = 0xe835 # macro +regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX = 5 # macro +regNBIF_REGIF_ERRSET_CTRL = 0xe836 # macro +regNBIF_REGIF_ERRSET_CTRL_BASE_IDX = 5 # macro +regBIFC_SDP_CNTL_2 = 0xe837 # macro +regBIFC_SDP_CNTL_2_BASE_IDX = 5 # macro +regNBIF_PGMST_CTRL = 0xe838 # macro +regNBIF_PGMST_CTRL_BASE_IDX = 5 # macro +regNBIF_PGSLV_CTRL = 0xe839 # macro +regNBIF_PGSLV_CTRL_BASE_IDX = 5 # macro +regNBIF_PG_MISC_CTRL = 0xe83a # macro +regNBIF_PG_MISC_CTRL_BASE_IDX = 5 # macro +regSMN_MST_EP_CNTL3 = 0xe83c # macro +regSMN_MST_EP_CNTL3_BASE_IDX = 5 # macro +regSMN_MST_EP_CNTL4 = 0xe83d # macro +regSMN_MST_EP_CNTL4_BASE_IDX = 5 # macro +regSMN_MST_CNTL1 = 0xe83e # macro +regSMN_MST_CNTL1_BASE_IDX = 5 # macro +regSMN_MST_EP_CNTL5 = 0xe83f # macro +regSMN_MST_EP_CNTL5_BASE_IDX = 5 # macro +regBIF_SELFRING_BUFFER_VID = 0xe840 # macro +regBIF_SELFRING_BUFFER_VID_BASE_IDX = 5 # macro +regBIF_SELFRING_VECTOR_CNTL = 0xe841 # macro +regBIF_SELFRING_VECTOR_CNTL_BASE_IDX = 5 # macro +regNBIF_STRAP_WRITE_CTRL = 0xe845 # macro +regNBIF_STRAP_WRITE_CTRL_BASE_IDX = 5 # macro +regNBIF_INTX_DSTATE_MISC_CNTL = 0xe846 # macro +regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX = 5 # macro +regNBIF_PENDING_MISC_CNTL = 0xe847 # macro +regNBIF_PENDING_MISC_CNTL_BASE_IDX = 5 # macro +regBIF_GMI_WRR_WEIGHT = 0xe848 # macro +regBIF_GMI_WRR_WEIGHT_BASE_IDX = 5 # macro +regBIF_GMI_WRR_WEIGHT2 = 0xe849 # macro +regBIF_GMI_WRR_WEIGHT2_BASE_IDX = 5 # macro +regBIF_GMI_WRR_WEIGHT3 = 0xe84a # macro +regBIF_GMI_WRR_WEIGHT3_BASE_IDX = 5 # macro +regNBIF_PWRBRK_REQUEST = 0xe84c # macro +regNBIF_PWRBRK_REQUEST_BASE_IDX = 5 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F0 = 0xe850 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX = 5 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F1 = 0xe851 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX = 5 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F2 = 0xe852 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX = 5 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F3 = 0xe853 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX = 5 # macro +regBIF_DMA_MP4_ERR_LOG = 0xe870 # macro +regBIF_DMA_MP4_ERR_LOG_BASE_IDX = 5 # macro +regBIF_PASID_ERR_LOG = 0xe871 # macro +regBIF_PASID_ERR_LOG_BASE_IDX = 5 # macro +regBIF_PASID_ERR_CLR = 0xe872 # macro +regBIF_PASID_ERR_CLR_BASE_IDX = 5 # macro +regNBIF_VWIRE_CTRL = 0xe880 # macro +regNBIF_VWIRE_CTRL_BASE_IDX = 5 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL = 0xe881 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX = 5 # macro +regNBIF_SMN_VWR_VCHG_RST_CTRL0 = 0xe882 # macro +regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX = 5 # macro +regNBIF_SMN_VWR_VCHG_TRIG = 0xe884 # macro +regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX = 5 # macro +regNBIF_SMN_VWR_WTRIG_CNTL = 0xe885 # macro +regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX = 5 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 = 0xe886 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX = 5 # macro +regNBIF_MGCG_CTRL_LCLK = 0xe887 # macro +regNBIF_MGCG_CTRL_LCLK_BASE_IDX = 5 # macro +regNBIF_DS_CTRL_LCLK = 0xe888 # macro +regNBIF_DS_CTRL_LCLK_BASE_IDX = 5 # macro +regSMN_MST_CNTL0 = 0xe889 # macro +regSMN_MST_CNTL0_BASE_IDX = 5 # macro +regSMN_MST_EP_CNTL1 = 0xe88a # macro +regSMN_MST_EP_CNTL1_BASE_IDX = 5 # macro +regSMN_MST_EP_CNTL2 = 0xe88b # macro +regSMN_MST_EP_CNTL2_BASE_IDX = 5 # macro +regNBIF_SDP_VWR_VCHG_DIS_CTRL = 0xe88c # macro +regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX = 5 # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL0 = 0xe88d # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX = 5 # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL1 = 0xe88e # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX = 5 # macro +regNBIF_SDP_VWR_VCHG_TRIG = 0xe88f # macro +regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX = 5 # macro +regNBIF_SHUB_TODET_CTRL = 0xe898 # macro +regNBIF_SHUB_TODET_CTRL_BASE_IDX = 5 # macro +regNBIF_SHUB_TODET_CLIENT_CTRL = 0xe899 # macro +regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX = 5 # macro +regNBIF_SHUB_TODET_CLIENT_STATUS = 0xe89a # macro +regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX = 5 # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL = 0xe89b # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX = 5 # macro +regNBIF_SHUB_TODET_CLIENT_CTRL2 = 0xe89c # macro +regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX = 5 # macro +regNBIF_SHUB_TODET_CLIENT_STATUS2 = 0xe89d # macro +regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX = 5 # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 = 0xe89e # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX = 5 # macro +regBIFC_BME_ERR_LOG_HB = 0xe8ab # macro +regBIFC_BME_ERR_LOG_HB_BASE_IDX = 5 # macro +regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC = 0xe8c0 # macro +regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX = 5 # macro +regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC = 0xe8c1 # macro +regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX = 5 # macro +regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC = 0xe8c2 # macro +regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX = 5 # macro +regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC = 0xe8c3 # macro +regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX = 5 # macro +regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC = 0xe8c4 # macro +regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX = 5 # macro +regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC = 0xe8c5 # macro +regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX = 5 # macro +regDISCON_HYSTERESIS_HEAD_CTRL = 0xe8c6 # macro +regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX = 5 # macro +regBIFC_EARLY_WAKEUP_CNTL = 0xe8d2 # macro +regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_MMIO_RD_H16BIT = 0xe8f0 # macro +regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_MMIO_WR_H16BIT = 0xe8f1 # macro +regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_DMA_RD_H16BIT = 0xe8f2 # macro +regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX = 5 # macro +regBIFC_PERF_CNT_DMA_WR_H16BIT = 0xe8f3 # macro +regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX = 5 # macro +regBIFL_RAS_CENTRAL_CNTL = 0xe400 # macro +regBIFL_RAS_CENTRAL_CNTL_BASE_IDX = 5 # macro +regBIFL_RAS_CENTRAL_STATUS = 0xe410 # macro +regBIFL_RAS_CENTRAL_STATUS_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF0_CTRL = 0xe420 # macro +regBIFL_RAS_LEAF0_CTRL_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF1_CTRL = 0xe421 # macro +regBIFL_RAS_LEAF1_CTRL_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF2_CTRL = 0xe422 # macro +regBIFL_RAS_LEAF2_CTRL_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF3_CTRL = 0xe423 # macro +regBIFL_RAS_LEAF3_CTRL_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF0_STATUS = 0xe430 # macro +regBIFL_RAS_LEAF0_STATUS_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF1_STATUS = 0xe431 # macro +regBIFL_RAS_LEAF1_STATUS_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF2_STATUS = 0xe432 # macro +regBIFL_RAS_LEAF2_STATUS_BASE_IDX = 5 # macro +regBIFL_RAS_LEAF3_STATUS = 0xe433 # macro +regBIFL_RAS_LEAF3_STATUS_BASE_IDX = 5 # macro +regBIFL_IOHUB_RAS_IH_CNTL = 0xe7fe # macro +regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX = 5 # macro +regBIFL_RAS_VWR_FROM_IOHUB = 0xe7ff # macro +regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RESERVED = 0x8d80 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH = 0x8d81 # macro +regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CNTL = 0x8d83 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL = 0x8d84 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 = 0x8d85 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL = 0x8d86 # macro +regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL = 0x8d87 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 = 0x8d88 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC = 0x8d89 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX = 5 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 = 0x8d8a # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL = 0x8d8c # macro +regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_2_PCIE_RX_CNTL = 0x8d8d # macro +regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL = 0x8d8e # macro +regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 = 0x8d8f # macro +regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC = 0x8d90 # macro +regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX = 5 # macro +regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP = 0x8d91 # macro +regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_SCRATCH = 0x8d60 # macro +regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_CNTL = 0x8d62 # macro +regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL = 0x8d63 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS = 0x8d64 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 = 0x8d65 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL = 0x8d66 # macro +regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL = 0x8d67 # macro +regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL = 0x8d69 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 5 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC = 0x8d6c # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 = 0x8d6d # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP = 0x8d6f # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR = 0x8d70 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL = 0x8d70 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 = 0x8d70 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 = 0x8d72 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 = 0x8d72 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 = 0x8d72 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL = 0x8d72 # macro +regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIEP_RESERVED = 0x8d73 # macro +regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL = 0x8d75 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID = 0x8d76 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL = 0x8d77 # macro +regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL = 0x8d78 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX = 5 # macro +regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL = 0x8d79 # macro +regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_ERR_INT_CNTL = 0x8da6 # macro +regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_BACO_CNTL_MISC = 0x8da7 # macro +regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_RESET_EN = 0x8da8 # macro +regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_VDM_SUPPORT = 0x8da9 # macro +regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 = 0x8daa # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 = 0x8dab # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_GPUIOV_REGION = 0x8dac # macro +regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_GPU_HOSTVM_EN = 0x8dad # macro +regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL = 0x8dae # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET = 0x8daf # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE = 0x8daf # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE0 = 0x8dde # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE1 = 0x8ddf # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_BUS_CNTL = 0x8de1 # macro +regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CONFIG_CNTL = 0x8de2 # macro +regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CONFIG_F0_BASE = 0x8de6 # macro +regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CONFIG_APER_SIZE = 0x8de7 # macro +regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE = 0x8de8 # macro +regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_XDMA_LO = 0x8de9 # macro +regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_XDMA_HI = 0x8dea # macro +regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC = 0x8deb # macro +regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL1 = 0x8dec # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST0 = 0x8ded # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST1 = 0x8dee # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL2 = 0x8def # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM = 0x8df0 # macro +regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_HOST_BUSNUM = 0x8df1 # macro +regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI = 0x8df2 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO = 0x8df3 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI = 0x8df4 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO = 0x8df5 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI = 0x8df6 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO = 0x8df7 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI = 0x8df8 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO = 0x8df9 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 = 0x8dfa # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX = 5 # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 = 0x8dfb # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_DEV0_LINK_CNTL = 0x8dfd # macro +regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_CMN_LINK_CNTL = 0x8dfe # macro +regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE = 0x8dff # macro +regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL = 0x8e00 # macro +regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX = 5 # macro +regRCC_DEV0_2_RCC_MH_ARB_CNTL = 0x8e01 # macro +regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_PCIE_INDEX = 0x800c # macro +regBIF_BX1_PCIE_INDEX_BASE_IDX = 5 # macro +regBIF_BX1_PCIE_DATA = 0x800d # macro +regBIF_BX1_PCIE_DATA_BASE_IDX = 5 # macro +regBIF_BX1_PCIE_INDEX2 = 0x800e # macro +regBIF_BX1_PCIE_INDEX2_BASE_IDX = 5 # macro +regBIF_BX1_PCIE_DATA2 = 0x800f # macro +regBIF_BX1_PCIE_DATA2_BASE_IDX = 5 # macro +regBIF_BX1_PCIE_INDEX_HI = 0x8010 # macro +regBIF_BX1_PCIE_INDEX_HI_BASE_IDX = 5 # macro +regBIF_BX1_PCIE_INDEX2_HI = 0x8011 # macro +regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_0 = 0x8048 # macro +regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_1 = 0x8049 # macro +regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_2 = 0x804a # macro +regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_3 = 0x804b # macro +regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_0 = 0x804c # macro +regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_1 = 0x804d # macro +regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_2 = 0x804e # macro +regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_3 = 0x804f # macro +regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_4 = 0x8050 # macro +regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_5 = 0x8051 # macro +regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_6 = 0x8052 # macro +regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_7 = 0x8053 # macro +regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_8 = 0x8054 # macro +regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_9 = 0x8055 # macro +regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_10 = 0x8056 # macro +regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_11 = 0x8057 # macro +regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_12 = 0x8058 # macro +regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_13 = 0x8059 # macro +regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_14 = 0x805a # macro +regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX = 5 # macro +regBIF_BX1_BIOS_SCRATCH_15 = 0x805b # macro +regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX = 5 # macro +regBIF_BX1_BIF_RLC_INTR_CNTL = 0x8060 # macro +regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_VCE_INTR_CNTL = 0x8061 # macro +regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_UVD_INTR_CNTL = 0x8062 # macro +regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 = 0x8080 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 = 0x8081 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 = 0x8082 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 = 0x8083 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 = 0x8084 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 = 0x8085 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 = 0x8086 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 = 0x8087 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 = 0x8088 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 = 0x8089 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 = 0x808a # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 = 0x808b # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 = 0x808c # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 = 0x808d # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 = 0x808e # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 = 0x808f # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_CNTL = 0x8090 # macro +regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL = 0x8091 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL = 0x8092 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX = 5 # macro +regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL = 0x8093 # macro +regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_0 = 0x8094 # macro +regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_1 = 0x8095 # macro +regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_2 = 0x8096 # macro +regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_3 = 0x8097 # macro +regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_4 = 0x8098 # macro +regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_5 = 0x8099 # macro +regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_6 = 0x809a # macro +regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_7 = 0x809b # macro +regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_8 = 0x809c # macro +regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_9 = 0x809d # macro +regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_10 = 0x809e # macro +regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_11 = 0x809f # macro +regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_12 = 0x80a0 # macro +regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_13 = 0x80a1 # macro +regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_14 = 0x80a2 # macro +regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX = 5 # macro +regBIF_BX1_DRIVER_SCRATCH_15 = 0x80a3 # macro +regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_0 = 0x80a4 # macro +regBIF_BX1_FW_SCRATCH_0_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_1 = 0x80a5 # macro +regBIF_BX1_FW_SCRATCH_1_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_2 = 0x80a6 # macro +regBIF_BX1_FW_SCRATCH_2_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_3 = 0x80a7 # macro +regBIF_BX1_FW_SCRATCH_3_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_4 = 0x80a8 # macro +regBIF_BX1_FW_SCRATCH_4_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_5 = 0x80a9 # macro +regBIF_BX1_FW_SCRATCH_5_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_6 = 0x80aa # macro +regBIF_BX1_FW_SCRATCH_6_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_7 = 0x80ab # macro +regBIF_BX1_FW_SCRATCH_7_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_8 = 0x80ac # macro +regBIF_BX1_FW_SCRATCH_8_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_9 = 0x80ad # macro +regBIF_BX1_FW_SCRATCH_9_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_10 = 0x80ae # macro +regBIF_BX1_FW_SCRATCH_10_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_11 = 0x80af # macro +regBIF_BX1_FW_SCRATCH_11_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_12 = 0x80b0 # macro +regBIF_BX1_FW_SCRATCH_12_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_13 = 0x80b1 # macro +regBIF_BX1_FW_SCRATCH_13_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_14 = 0x80b2 # macro +regBIF_BX1_FW_SCRATCH_14_BASE_IDX = 5 # macro +regBIF_BX1_FW_SCRATCH_15 = 0x80b3 # macro +regBIF_BX1_FW_SCRATCH_15_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_4 = 0x80b4 # macro +regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_5 = 0x80b5 # macro +regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_6 = 0x80b6 # macro +regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_7 = 0x80b7 # macro +regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_8 = 0x80b8 # macro +regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_9 = 0x80b9 # macro +regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_10 = 0x80ba # macro +regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_11 = 0x80bb # macro +regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_12 = 0x80bc # macro +regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_13 = 0x80bd # macro +regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_14 = 0x80be # macro +regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX = 5 # macro +regBIF_BX1_SBIOS_SCRATCH_15 = 0x80bf # macro +regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX = 5 # macro +regBIF_BX_PF1_MM_INDEX = 0x8000 # macro +regBIF_BX_PF1_MM_INDEX_BASE_IDX = 5 # macro +regBIF_BX_PF1_MM_DATA = 0x8001 # macro +regBIF_BX_PF1_MM_DATA_BASE_IDX = 5 # macro +regBIF_BX_PF1_MM_INDEX_HI = 0x8006 # macro +regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX = 5 # macro +regBIF_BX1_CC_BIF_BX_STRAP0 = 0x8e02 # macro +regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX = 5 # macro +regBIF_BX1_CC_BIF_BX_PINSTRAP0 = 0x8e04 # macro +regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX = 5 # macro +regBIF_BX1_BIF_MM_INDACCESS_CNTL = 0x8e06 # macro +regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BUS_CNTL = 0x8e07 # macro +regBIF_BX1_BUS_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_SCRATCH0 = 0x8e08 # macro +regBIF_BX1_BIF_SCRATCH0_BASE_IDX = 5 # macro +regBIF_BX1_BIF_SCRATCH1 = 0x8e09 # macro +regBIF_BX1_BIF_SCRATCH1_BASE_IDX = 5 # macro +regBIF_BX1_BX_RESET_EN = 0x8e0d # macro +regBIF_BX1_BX_RESET_EN_BASE_IDX = 5 # macro +regBIF_BX1_MM_CFGREGS_CNTL = 0x8e0e # macro +regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BX_RESET_CNTL = 0x8e10 # macro +regBIF_BX1_BX_RESET_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_INTERRUPT_CNTL = 0x8e11 # macro +regBIF_BX1_INTERRUPT_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_INTERRUPT_CNTL2 = 0x8e12 # macro +regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX = 5 # macro +regBIF_BX1_CLKREQB_PAD_CNTL = 0x8e18 # macro +regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_FEATURES_CONTROL_MISC = 0x8e1b # macro +regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX = 5 # macro +regBIF_BX1_HDP_ATOMIC_CONTROL_MISC = 0x8e1c # macro +regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX = 5 # macro +regBIF_BX1_BIF_DOORBELL_CNTL = 0x8e1d # macro +regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_DOORBELL_INT_CNTL = 0x8e1e # macro +regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_FB_EN = 0x8e20 # macro +regBIF_BX1_BIF_FB_EN_BASE_IDX = 5 # macro +regBIF_BX1_BIF_INTR_CNTL = 0x8e21 # macro +regBIF_BX1_BIF_INTR_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_MST_TRANS_PENDING_VF = 0x8e29 # macro +regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX = 5 # macro +regBIF_BX1_BIF_SLV_TRANS_PENDING_VF = 0x8e2a # macro +regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX = 5 # macro +regBIF_BX1_MEM_TYPE_CNTL = 0x8e31 # macro +regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL = 0x8e33 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_0 = 0x8e34 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_1 = 0x8e35 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_2 = 0x8e36 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_3 = 0x8e37 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_4 = 0x8e38 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_5 = 0x8e39 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_6 = 0x8e3a # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_7 = 0x8e3b # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_8 = 0x8e3c # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_9 = 0x8e3d # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_10 = 0x8e3e # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_11 = 0x8e3f # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_12 = 0x8e40 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_13 = 0x8e41 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_14 = 0x8e42 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX = 5 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_15 = 0x8e43 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX = 5 # macro +regBIF_BX1_VF_REGWR_EN = 0x8e44 # macro +regBIF_BX1_VF_REGWR_EN_BASE_IDX = 5 # macro +regBIF_BX1_VF_DOORBELL_EN = 0x8e45 # macro +regBIF_BX1_VF_DOORBELL_EN_BASE_IDX = 5 # macro +regBIF_BX1_VF_FB_EN = 0x8e46 # macro +regBIF_BX1_VF_FB_EN_BASE_IDX = 5 # macro +regBIF_BX1_VF_REGWR_STATUS = 0x8e47 # macro +regBIF_BX1_VF_REGWR_STATUS_BASE_IDX = 5 # macro +regBIF_BX1_VF_DOORBELL_STATUS = 0x8e48 # macro +regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX = 5 # macro +regBIF_BX1_VF_FB_STATUS = 0x8e49 # macro +regBIF_BX1_VF_FB_STATUS_BASE_IDX = 5 # macro +regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL = 0x8e4d # macro +regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL = 0x8e4e # macro +regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_RB_CNTL = 0x8e4f # macro +regBIF_BX1_BIF_RB_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_RB_BASE = 0x8e50 # macro +regBIF_BX1_BIF_RB_BASE_BASE_IDX = 5 # macro +regBIF_BX1_BIF_RB_RPTR = 0x8e51 # macro +regBIF_BX1_BIF_RB_RPTR_BASE_IDX = 5 # macro +regBIF_BX1_BIF_RB_WPTR = 0x8e52 # macro +regBIF_BX1_BIF_RB_WPTR_BASE_IDX = 5 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_HI = 0x8e53 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX = 5 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_LO = 0x8e54 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX = 5 # macro +regBIF_BX1_MAILBOX_INDEX = 0x8e55 # macro +regBIF_BX1_MAILBOX_INDEX_BASE_IDX = 5 # macro +regBIF_BX1_BIF_MP1_INTR_CTRL = 0x8e62 # macro +regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE = 0x8e63 # macro +regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX = 5 # macro +regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE = 0x8e64 # macro +regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX = 5 # macro +regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE = 0x8e65 # macro +regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX = 5 # macro +regBIF_BX1_BIF_PERSTB_PAD_CNTL = 0x8e68 # macro +regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_PX_EN_PAD_CNTL = 0x8e69 # macro +regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_REFPADKIN_PAD_CNTL = 0x8e6a # macro +regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_CLKREQB_PAD_CNTL = 0x8e6b # macro +regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_PWRBRK_PAD_CNTL = 0x8e6c # macro +regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_WAKEB_PAD_CNTL = 0x8e6d # macro +regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL = 0x8e6e # macro +regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL = 0x8e70 # macro +regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX = 5 # macro +regBIF_BX1_BIF_S5_MEM_POWER_CTRL0 = 0x8e71 # macro +regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX = 5 # macro +regBIF_BX1_BIF_S5_MEM_POWER_CTRL1 = 0x8e72 # macro +regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX = 5 # macro +regBIF_BX1_BIF_S5_DUMMY_REGS = 0x8e73 # macro +regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX = 5 # macro +regBIF_BX_PF1_BIF_BME_STATUS = 0x8e0b # macro +regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX = 5 # macro +regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG = 0x8e0c # macro +regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX = 5 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x8e13 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 5 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x8e14 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 5 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL = 0x8e15 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 5 # macro +regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL = 0x8e16 # macro +regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 5 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x8e17 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 5 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x8e19 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 5 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x8e1a # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 5 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_REQ = 0x8e26 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX = 5 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_DONE = 0x8e27 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX = 5 # macro +regBIF_BX_PF1_BIF_TRANS_PENDING = 0x8e28 # macro +regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX = 5 # macro +regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS = 0x8e32 # macro +regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 = 0x8e56 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 = 0x8e57 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 = 0x8e58 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 = 0x8e59 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 = 0x8e5a # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 = 0x8e5b # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 = 0x8e5c # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 = 0x8e5d # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_CONTROL = 0x8e5e # macro +regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX = 5 # macro +regBIF_BX_PF1_MAILBOX_INT_CNTL = 0x8e5f # macro +regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX = 5 # macro +regBIF_BX_PF1_BIF_VMHV_MAILBOX = 0x8e60 # macro +regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_BIF_STRAP0 = 0x8d20 # macro +regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_BIF_STRAP1 = 0x8d21 # macro +regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_BIF_STRAP2 = 0x8d22 # macro +regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_BIF_STRAP3 = 0x8d23 # macro +regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_BIF_STRAP4 = 0x8d24 # macro +regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_BIF_STRAP5 = 0x8d25 # macro +regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_BIF_STRAP6 = 0x8d26 # macro +regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 = 0x8d27 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 = 0x8d28 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 = 0x8d29 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 = 0x8d2a # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 = 0x8d2b # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 = 0x8d2c # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 = 0x8d2d # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 = 0x8d2e # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 = 0x8d2f # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 = 0x8d30 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 = 0x8d31 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 = 0x8d32 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 = 0x8d33 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 = 0x8d34 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 = 0x8d35 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 = 0x8d36 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 = 0x8d37 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 = 0x8d38 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 = 0x8d39 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 = 0x8d3a # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 = 0x8d3b # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 = 0x8d3c # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 = 0x8d3d # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 = 0x8d3e # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 = 0x8d3f # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 = 0x8d40 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 = 0x8d41 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 = 0x8d42 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 = 0x8d43 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 = 0x8d44 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 = 0x8d45 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 = 0x8d51 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 = 0x8d52 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 = 0x8d53 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 = 0x8d54 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 = 0x8d55 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 = 0x8d56 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 = 0x8d57 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 = 0x8d58 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 = 0x8d59 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 = 0x8d5a # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 = 0x8d5b # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX = 5 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 = 0x8d5c # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX = 5 # macro +regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 = 0x4f7400 # macro +regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 = 0x4f7401 # macro +regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 = 0x4f7402 # macro +regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 = 0x4f7403 # macro +regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 = 0x4f7404 # macro +regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 = 0x4f7405 # macro +regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 = 0x4f7406 # macro +regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 = 0x4f7407 # macro +regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 = 0x4f7408 # macro +regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 = 0x4f7409 # macro +regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 = 0x4f740a # macro +regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 = 0x4f740b # macro +regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 = 0x4f740c # macro +regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 = 0x4f740d # macro +regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 = 0x4f740e # macro +regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 = 0x4f740f # macro +regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 = 0x4f7410 # macro +regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 = 0x4f7411 # macro +regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 = 0x4f7412 # macro +regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 = 0x4f7413 # macro +regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 = 0x4f7414 # macro +regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 = 0x4f7415 # macro +regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 = 0x4f7416 # macro +regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 = 0x4f7417 # macro +regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 = 0x4f7418 # macro +regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 = 0x4f7419 # macro +regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 = 0x4f741a # macro +regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 = 0x4f741b # macro +regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 = 0x4f741c # macro +regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 = 0x4f741d # macro +regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 = 0x4f741e # macro +regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 = 0x4f741f # macro +regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 = 0x4f7420 # macro +regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 = 0x4f7421 # macro +regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 = 0x4f7422 # macro +regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 = 0x4f7423 # macro +regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 = 0x4f7424 # macro +regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 = 0x4f7425 # macro +regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 = 0x4f7426 # macro +regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 = 0x4f7427 # macro +regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 = 0x4f7428 # macro +regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 = 0x4f7429 # macro +regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 = 0x4f742a # macro +regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 = 0x4f742b # macro +regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 = 0x4f742c # macro +regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 = 0x4f742d # macro +regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 = 0x4f742e # macro +regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 = 0x4f742f # macro +regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 = 0x4f7430 # macro +regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 = 0x4f7431 # macro +regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 = 0x4f7432 # macro +regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 = 0x4f7433 # macro +regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 = 0x4f7434 # macro +regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 = 0x4f7435 # macro +regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 = 0x4f7436 # macro +regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 = 0x4f7437 # macro +regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 = 0x4f7438 # macro +regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 = 0x4f7439 # macro +regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 = 0x4f743a # macro +regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 = 0x4f743b # macro +regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0 = 0x4f743c # macro +regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1 = 0x4f743d # macro +regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0 = 0x4f743e # macro +regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1 = 0x4f743f # macro +regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0 = 0x4f7440 # macro +regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1 = 0x4f7441 # macro +regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0 = 0x4f7442 # macro +regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1 = 0x4f7443 # macro +regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_Req_BurstTarget_REG0 = 0x4f7444 # macro +regGDC_DMA_SION_CL3_Req_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_Req_BurstTarget_REG1 = 0x4f7445 # macro +regGDC_DMA_SION_CL3_Req_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_Req_TimeSlot_REG0 = 0x4f7446 # macro +regGDC_DMA_SION_CL3_Req_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_Req_TimeSlot_REG1 = 0x4f7447 # macro +regGDC_DMA_SION_CL3_Req_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0 = 0x4f7448 # macro +regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1 = 0x4f7449 # macro +regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0 = 0x4f744a # macro +regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1 = 0x4f744b # macro +regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0 = 0x4f744c # macro +regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1 = 0x4f744d # macro +regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0 = 0x4f744e # macro +regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1 = 0x4f744f # macro +regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_DMA_SION_CNTL_REG0 = 0x4f7450 # macro +regGDC_DMA_SION_CNTL_REG0_BASE_IDX = 3 # macro +regGDC_DMA_SION_CNTL_REG1 = 0x4f7451 # macro +regGDC_DMA_SION_CNTL_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 = 0x4f7600 # macro +regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 = 0x4f7601 # macro +regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 = 0x4f7602 # macro +regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 = 0x4f7603 # macro +regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 = 0x4f7604 # macro +regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 = 0x4f7605 # macro +regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 = 0x4f7606 # macro +regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 = 0x4f7607 # macro +regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_Req_BurstTarget_REG0 = 0x4f7608 # macro +regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_Req_BurstTarget_REG1 = 0x4f7609 # macro +regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_Req_TimeSlot_REG0 = 0x4f760a # macro +regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_Req_TimeSlot_REG1 = 0x4f760b # macro +regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 = 0x4f760c # macro +regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 = 0x4f760d # macro +regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 = 0x4f760e # macro +regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 = 0x4f760f # macro +regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 = 0x4f7610 # macro +regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 = 0x4f7611 # macro +regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 = 0x4f7612 # macro +regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 = 0x4f7613 # macro +regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 = 0x4f7614 # macro +regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 = 0x4f7615 # macro +regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 = 0x4f7616 # macro +regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 = 0x4f7617 # macro +regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 = 0x4f7618 # macro +regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 = 0x4f7619 # macro +regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 = 0x4f761a # macro +regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 = 0x4f761b # macro +regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_Req_BurstTarget_REG0 = 0x4f761c # macro +regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_Req_BurstTarget_REG1 = 0x4f761d # macro +regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_Req_TimeSlot_REG0 = 0x4f761e # macro +regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_Req_TimeSlot_REG1 = 0x4f761f # macro +regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 = 0x4f7620 # macro +regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 = 0x4f7621 # macro +regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 = 0x4f7622 # macro +regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 = 0x4f7623 # macro +regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 = 0x4f7624 # macro +regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 = 0x4f7625 # macro +regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 = 0x4f7626 # macro +regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 = 0x4f7627 # macro +regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0 = 0x4f7628 # macro +regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1 = 0x4f7629 # macro +regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0 = 0x4f762a # macro +regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1 = 0x4f762b # macro +regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0 = 0x4f762c # macro +regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1 = 0x4f762d # macro +regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0 = 0x4f762e # macro +regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1 = 0x4f762f # macro +regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_Req_BurstTarget_REG0 = 0x4f7630 # macro +regGDC_HST_SION_CL2_Req_BurstTarget_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_Req_BurstTarget_REG1 = 0x4f7631 # macro +regGDC_HST_SION_CL2_Req_BurstTarget_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_Req_TimeSlot_REG0 = 0x4f7632 # macro +regGDC_HST_SION_CL2_Req_TimeSlot_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_Req_TimeSlot_REG1 = 0x4f7633 # macro +regGDC_HST_SION_CL2_Req_TimeSlot_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0 = 0x4f7634 # macro +regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1 = 0x4f7635 # macro +regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0 = 0x4f7636 # macro +regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1 = 0x4f7637 # macro +regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0 = 0x4f7638 # macro +regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1 = 0x4f7639 # macro +regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0 = 0x4f763a # macro +regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1 = 0x4f763b # macro +regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX = 3 # macro +regGDC_HST_SION_CNTL_REG0 = 0x4f763c # macro +regGDC_HST_SION_CNTL_REG0_BASE_IDX = 3 # macro +regGDC_HST_SION_CNTL_REG1 = 0x4f763d # macro +regGDC_HST_SION_CNTL_REG1_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_0_CTRL = 0x4f7640 # macro +regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_1_CTRL = 0x4f7641 # macro +regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_2_CTRL = 0x4f7642 # macro +regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_3_CTRL = 0x4f7643 # macro +regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_4_CTRL = 0x4f7644 # macro +regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_5_CTRL = 0x4f7645 # macro +regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_6_CTRL = 0x4f7646 # macro +regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_7_CTRL = 0x4f7647 # macro +regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_8_CTRL = 0x4f7648 # macro +regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_9_CTRL = 0x4f7649 # macro +regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_10_CTRL = 0x4f764a # macro +regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_11_CTRL = 0x4f764b # macro +regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_12_CTRL = 0x4f764c # macro +regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_13_CTRL = 0x4f764d # macro +regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_14_CTRL = 0x4f764e # macro +regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_ENTRY_15_CTRL = 0x4f764f # macro +regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX = 3 # macro +regS2A_DOORBELL_COMMON_CTRL_REG = 0x4f7650 # macro +regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX = 3 # macro +regGDC1_SHUB_REGS_IF_CTL = 0x4f0ae3 # macro +regGDC1_SHUB_REGS_IF_CTL_BASE_IDX = 3 # macro +regGDC1_NGDC_MGCG_CTRL = 0x4f0aea # macro +regGDC1_NGDC_MGCG_CTRL_BASE_IDX = 3 # macro +regGDC1_NGDC_RESERVED_0 = 0x4f0aeb # macro +regGDC1_NGDC_RESERVED_0_BASE_IDX = 3 # macro +regGDC1_NGDC_RESERVED_1 = 0x4f0aec # macro +regGDC1_NGDC_RESERVED_1_BASE_IDX = 3 # macro +regGDC1_NBIF_GFX_DOORBELL_STATUS = 0x4f0aef # macro +regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX = 3 # macro +regGDC1_ATDMA_MISC_CNTL = 0x4f0afd # macro +regGDC1_ATDMA_MISC_CNTL_BASE_IDX = 3 # macro +regGDC1_S2A_MISC_CNTL = 0x4f0aff # macro +regGDC1_S2A_MISC_CNTL_BASE_IDX = 3 # macro +regGDC1_NGDC_EARLY_WAKEUP_CTRL = 0x4f0b01 # macro +regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX = 3 # macro +regGDC1_NGDC_PG_MISC_CTRL = 0x4f0b18 # macro +regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX = 3 # macro +regGDC1_NGDC_PGMST_CTRL = 0x4f0b19 # macro +regGDC1_NGDC_PGMST_CTRL_BASE_IDX = 3 # macro +regGDC1_NGDC_PGSLV_CTRL = 0x4f0b1a # macro +regGDC1_NGDC_PGSLV_CTRL_BASE_IDX = 3 # macro +regGDCSOC_ERR_RSP_CNTL = 0x4f5c00 # macro +regGDCSOC_ERR_RSP_CNTL_BASE_IDX = 3 # macro +regGDCSOC_RAS_CENTRAL_STATUS = 0x4f5c10 # macro +regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF0_CTRL = 0x4f5c20 # macro +regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF1_CTRL = 0x4f5c21 # macro +regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF2_CTRL = 0x4f5c22 # macro +regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF3_CTRL = 0x4f5c23 # macro +regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF4_CTRL = 0x4f5c24 # macro +regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF2_MISC_CTRL = 0x4f5c2e # macro +regGDCSOC_RAS_LEAF2_MISC_CTRL_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF2_MISC_CTRL2 = 0x4f5c2f # macro +regGDCSOC_RAS_LEAF2_MISC_CTRL2_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF0_STATUS = 0x4f5c30 # macro +regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF1_STATUS = 0x4f5c31 # macro +regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF2_STATUS = 0x4f5c32 # macro +regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF3_STATUS = 0x4f5c33 # macro +regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX = 3 # macro +regGDCSOC_RAS_LEAF4_STATUS = 0x4f5c34 # macro +regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX = 3 # macro +regSHUB_PF_FLR_RST = 0x4f7800 # macro +regSHUB_PF_FLR_RST_BASE_IDX = 3 # macro +regSHUB_GFX_DRV_VPU_RST = 0x4f7801 # macro +regSHUB_GFX_DRV_VPU_RST_BASE_IDX = 3 # macro +regSHUB_LINK_RESET = 0x4f7802 # macro +regSHUB_LINK_RESET_BASE_IDX = 3 # macro +regSHUB_HARD_RST_CTRL = 0x4f7810 # macro +regSHUB_HARD_RST_CTRL_BASE_IDX = 3 # macro +regSHUB_SOFT_RST_CTRL = 0x4f7811 # macro +regSHUB_SOFT_RST_CTRL_BASE_IDX = 3 # macro +regSHUB_SDP_PORT_RST = 0x4f7812 # macro +regSHUB_SDP_PORT_RST_BASE_IDX = 3 # macro +regSHUB_RST_MISC_TRL = 0x4f7813 # macro +regSHUB_RST_MISC_TRL_BASE_IDX = 3 # macro +regHST_CLK0_SW0_CL0_CNTL = 0x4f3d40 # macro +regHST_CLK0_SW0_CL0_CNTL_BASE_IDX = 3 # macro +regHST_CLK0_SW1_CL0_CNTL = 0x4f3d60 # macro +regHST_CLK0_SW1_CL0_CNTL_BASE_IDX = 3 # macro +cfgPSWUSCFG0_1_VENDOR_ID = 0x0000 # macro +cfgPSWUSCFG0_1_DEVICE_ID = 0x0002 # macro +cfgPSWUSCFG0_1_COMMAND = 0x0004 # macro +cfgPSWUSCFG0_1_STATUS = 0x0006 # macro +cfgPSWUSCFG0_1_REVISION_ID = 0x0008 # macro +cfgPSWUSCFG0_1_PROG_INTERFACE = 0x0009 # macro +cfgPSWUSCFG0_1_SUB_CLASS = 0x000a # macro +cfgPSWUSCFG0_1_BASE_CLASS = 0x000b # macro +cfgPSWUSCFG0_1_CACHE_LINE = 0x000c # macro +cfgPSWUSCFG0_1_LATENCY = 0x000d # macro +cfgPSWUSCFG0_1_HEADER = 0x000e # macro +cfgPSWUSCFG0_1_BIST = 0x000f # macro +cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY = 0x0018 # macro +cfgPSWUSCFG0_1_IO_BASE_LIMIT = 0x001c # macro +cfgPSWUSCFG0_1_SECONDARY_STATUS = 0x001e # macro +cfgPSWUSCFG0_1_MEM_BASE_LIMIT = 0x0020 # macro +cfgPSWUSCFG0_1_PREF_BASE_LIMIT = 0x0024 # macro +cfgPSWUSCFG0_1_PREF_BASE_UPPER = 0x0028 # macro +cfgPSWUSCFG0_1_PREF_LIMIT_UPPER = 0x002c # macro +cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI = 0x0030 # macro +cfgPSWUSCFG0_1_CAP_PTR = 0x0034 # macro +cfgPSWUSCFG0_1_ROM_BASE_ADDR = 0x0038 # macro +cfgPSWUSCFG0_1_INTERRUPT_LINE = 0x003c # macro +cfgPSWUSCFG0_1_INTERRUPT_PIN = 0x003d # macro +cfgPSWUSCFG0_1_VENDOR_CAP_LIST = 0x0048 # macro +cfgPSWUSCFG0_1_ADAPTER_ID_W = 0x004c # macro +cfgPSWUSCFG0_1_PMI_CAP_LIST = 0x0050 # macro +cfgPSWUSCFG0_1_PMI_CAP = 0x0052 # macro +cfgPSWUSCFG0_1_PMI_STATUS_CNTL = 0x0054 # macro +cfgPSWUSCFG0_1_PCIE_CAP_LIST = 0x0058 # macro +cfgPSWUSCFG0_1_PCIE_CAP = 0x005a # macro +cfgPSWUSCFG0_1_DEVICE_CAP = 0x005c # macro +cfgPSWUSCFG0_1_DEVICE_CNTL = 0x0060 # macro +cfgPSWUSCFG0_1_DEVICE_STATUS = 0x0062 # macro +cfgPSWUSCFG0_1_LINK_CAP = 0x0064 # macro +cfgPSWUSCFG0_1_LINK_CNTL = 0x0068 # macro +cfgPSWUSCFG0_1_LINK_STATUS = 0x006a # macro +cfgPSWUSCFG0_1_DEVICE_CAP2 = 0x007c # macro +cfgPSWUSCFG0_1_DEVICE_CNTL2 = 0x0080 # macro +cfgPSWUSCFG0_1_DEVICE_STATUS2 = 0x0082 # macro +cfgPSWUSCFG0_1_LINK_CAP2 = 0x0084 # macro +cfgPSWUSCFG0_1_LINK_CNTL2 = 0x0088 # macro +cfgPSWUSCFG0_1_LINK_STATUS2 = 0x008a # macro +cfgPSWUSCFG0_1_MSI_CAP_LIST = 0x00a0 # macro +cfgPSWUSCFG0_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgPSWUSCFG0_1_MSI_MSG_DATA = 0x00a8 # macro +cfgPSWUSCFG0_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgPSWUSCFG0_1_SSID_CAP_LIST = 0x00c0 # macro +cfgPSWUSCFG0_1_SSID_CAP = 0x00c4 # macro +cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST = 0x0110 # macro +cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 = 0x0114 # macro +cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 = 0x0118 # macro +cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL = 0x011c # macro +cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS = 0x011e # macro +cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP = 0x0120 # macro +cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL = 0x0124 # macro +cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS = 0x012a # macro +cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP = 0x012c # macro +cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL = 0x0130 # macro +cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS = 0x0136 # macro +cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0140 # macro +cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 = 0x0144 # macro +cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 = 0x0148 # macro +cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgPSWUSCFG0_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgPSWUSCFG0_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgPSWUSCFG0_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgPSWUSCFG0_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST = 0x0270 # macro +cfgPSWUSCFG0_1_PCIE_LINK_CNTL3 = 0x0274 # macro +cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS = 0x0278 # macro +cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL = 0x027c # macro +cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL = 0x027e # macro +cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL = 0x0280 # macro +cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL = 0x0282 # macro +cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL = 0x0284 # macro +cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL = 0x0286 # macro +cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL = 0x0288 # macro +cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL = 0x028a # macro +cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL = 0x028c # macro +cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL = 0x028e # macro +cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL = 0x0290 # macro +cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL = 0x0292 # macro +cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL = 0x0294 # macro +cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL = 0x0296 # macro +cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL = 0x0298 # macro +cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL = 0x029a # macro +cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgPSWUSCFG0_1_PCIE_ACS_CAP = 0x02a4 # macro +cfgPSWUSCFG0_1_PCIE_ACS_CNTL = 0x02a6 # macro +cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST = 0x02f0 # macro +cfgPSWUSCFG0_1_PCIE_MC_CAP = 0x02f4 # macro +cfgPSWUSCFG0_1_PCIE_MC_CNTL = 0x02f6 # macro +cfgPSWUSCFG0_1_PCIE_MC_ADDR0 = 0x02f8 # macro +cfgPSWUSCFG0_1_PCIE_MC_ADDR1 = 0x02fc # macro +cfgPSWUSCFG0_1_PCIE_MC_RCV0 = 0x0300 # macro +cfgPSWUSCFG0_1_PCIE_MC_RCV1 = 0x0304 # macro +cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 = 0x0308 # macro +cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 = 0x030c # macro +cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0x0310 # macro +cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0x0314 # macro +cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST = 0x0320 # macro +cfgPSWUSCFG0_1_PCIE_LTR_CAP = 0x0324 # macro +cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgPSWUSCFG0_1_PCIE_ARI_CAP = 0x032c # macro +cfgPSWUSCFG0_1_PCIE_ARI_CNTL = 0x032e # macro +cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST = 0x0400 # macro +cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP = 0x0404 # macro +cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS = 0x0408 # macro +cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST = 0x0410 # macro +cfgPSWUSCFG0_1_LINK_CAP_16GT = 0x0414 # macro +cfgPSWUSCFG0_1_LINK_CNTL_16GT = 0x0418 # macro +cfgPSWUSCFG0_1_LINK_STATUS_16GT = 0x041c # macro +cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x0420 # macro +cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x0424 # macro +cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x0428 # macro +cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT = 0x0430 # macro +cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT = 0x0431 # macro +cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT = 0x0432 # macro +cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT = 0x0433 # macro +cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT = 0x0434 # macro +cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT = 0x0435 # macro +cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT = 0x0436 # macro +cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT = 0x0437 # macro +cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT = 0x0438 # macro +cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT = 0x0439 # macro +cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT = 0x043a # macro +cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT = 0x043b # macro +cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT = 0x043c # macro +cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT = 0x043d # macro +cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT = 0x043e # macro +cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT = 0x043f # macro +cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST = 0x0440 # macro +cfgPSWUSCFG0_1_MARGINING_PORT_CAP = 0x0444 # macro +cfgPSWUSCFG0_1_MARGINING_PORT_STATUS = 0x0446 # macro +cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL = 0x0448 # macro +cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS = 0x044a # macro +cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL = 0x044c # macro +cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS = 0x044e # macro +cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL = 0x0450 # macro +cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS = 0x0452 # macro +cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL = 0x0454 # macro +cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS = 0x0456 # macro +cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL = 0x0458 # macro +cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS = 0x045a # macro +cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL = 0x045c # macro +cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS = 0x045e # macro +cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL = 0x0460 # macro +cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS = 0x0462 # macro +cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL = 0x0464 # macro +cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS = 0x0466 # macro +cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL = 0x0468 # macro +cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS = 0x046a # macro +cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL = 0x046c # macro +cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS = 0x046e # macro +cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL = 0x0470 # macro +cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS = 0x0472 # macro +cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL = 0x0474 # macro +cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS = 0x0476 # macro +cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL = 0x0478 # macro +cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS = 0x047a # macro +cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL = 0x047c # macro +cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS = 0x047e # macro +cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL = 0x0480 # macro +cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS = 0x0482 # macro +cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL = 0x0484 # macro +cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS = 0x0486 # macro +cfgPSWUSCFG0_1_LINK_CAP_32GT = 0x0504 # macro +cfgPSWUSCFG0_1_LINK_CNTL_32GT = 0x0508 # macro +cfgPSWUSCFG0_1_LINK_STATUS_32GT = 0x050c # macro +cfgBIF_CFG_DEV0_RC1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_RC1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_RC1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_RC1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_RC1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_RC1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_RC1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_RC1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_RC1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_RC1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_RC1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_RC1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_RC1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_RC1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY = 0x0018 # macro +cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT = 0x001c # macro +cfgBIF_CFG_DEV0_RC1_SECONDARY_STATUS = 0x001e # macro +cfgBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT = 0x0020 # macro +cfgBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT = 0x0024 # macro +cfgBIF_CFG_DEV0_RC1_PREF_BASE_UPPER = 0x0028 # macro +cfgBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER = 0x002c # macro +cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI = 0x0030 # macro +cfgBIF_CFG_DEV0_RC1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_RC1_ROM_BASE_ADDR = 0x0038 # macro +cfgBIF_CFG_DEV0_RC1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_RC1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_RC1_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_RC1_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_CAP_LIST = 0x0058 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_CAP = 0x005a # macro +cfgBIF_CFG_DEV0_RC1_DEVICE_CAP = 0x005c # macro +cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL = 0x0060 # macro +cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS = 0x0062 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CAP = 0x0064 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CNTL = 0x0068 # macro +cfgBIF_CFG_DEV0_RC1_LINK_STATUS = 0x006a # macro +cfgBIF_CFG_DEV0_RC1_SLOT_CAP = 0x006c # macro +cfgBIF_CFG_DEV0_RC1_SLOT_CNTL = 0x0070 # macro +cfgBIF_CFG_DEV0_RC1_SLOT_STATUS = 0x0072 # macro +cfgBIF_CFG_DEV0_RC1_DEVICE_CAP2 = 0x007c # macro +cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL2 = 0x0080 # macro +cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS2 = 0x0082 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CAP2 = 0x0084 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CNTL2 = 0x0088 # macro +cfgBIF_CFG_DEV0_RC1_LINK_STATUS2 = 0x008a # macro +cfgBIF_CFG_DEV0_RC1_SLOT_CAP2 = 0x008c # macro +cfgBIF_CFG_DEV0_RC1_SLOT_CNTL2 = 0x0090 # macro +cfgBIF_CFG_DEV0_RC1_SLOT_STATUS2 = 0x0092 # macro +cfgBIF_CFG_DEV0_RC1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_RC1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_RC1_SSID_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_RC1_SSID_CAP = 0x00c4 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST = 0x0110 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 = 0x0114 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 = 0x0118 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL = 0x011c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS = 0x011e # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP = 0x0120 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL = 0x0124 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS = 0x012a # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP = 0x012c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL = 0x0130 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS = 0x0136 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0140 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 = 0x0144 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 = 0x0148 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST = 0x0270 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 = 0x0274 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS = 0x0278 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL = 0x027c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL = 0x027e # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL = 0x0280 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL = 0x0282 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL = 0x0284 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL = 0x0286 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL = 0x0288 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL = 0x028a # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL = 0x028c # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL = 0x028e # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL = 0x0290 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL = 0x0292 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL = 0x0294 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL = 0x0296 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL = 0x0298 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL = 0x029a # macro +cfgBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST = 0x0400 # macro +cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP = 0x0404 # macro +cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS = 0x0408 # macro +cfgBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST = 0x0410 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CAP_16GT = 0x0414 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CNTL_16GT = 0x0418 # macro +cfgBIF_CFG_DEV0_RC1_LINK_STATUS_16GT = 0x041c # macro +cfgBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x0420 # macro +cfgBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x0424 # macro +cfgBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x0428 # macro +cfgBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT = 0x0430 # macro +cfgBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT = 0x0431 # macro +cfgBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT = 0x0432 # macro +cfgBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT = 0x0433 # macro +cfgBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT = 0x0434 # macro +cfgBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT = 0x0435 # macro +cfgBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT = 0x0436 # macro +cfgBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT = 0x0437 # macro +cfgBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT = 0x0438 # macro +cfgBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT = 0x0439 # macro +cfgBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT = 0x043a # macro +cfgBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT = 0x043b # macro +cfgBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT = 0x043c # macro +cfgBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT = 0x043d # macro +cfgBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT = 0x043e # macro +cfgBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT = 0x043f # macro +cfgBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST = 0x0450 # macro +cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP = 0x0454 # macro +cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS = 0x0456 # macro +cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL = 0x0458 # macro +cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS = 0x045a # macro +cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL = 0x045c # macro +cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS = 0x045e # macro +cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL = 0x0460 # macro +cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS = 0x0462 # macro +cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL = 0x0464 # macro +cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS = 0x0466 # macro +cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL = 0x0468 # macro +cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS = 0x046a # macro +cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL = 0x046c # macro +cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS = 0x046e # macro +cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL = 0x0470 # macro +cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS = 0x0472 # macro +cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL = 0x0474 # macro +cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS = 0x0476 # macro +cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL = 0x0478 # macro +cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS = 0x047a # macro +cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL = 0x047c # macro +cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS = 0x047e # macro +cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL = 0x0480 # macro +cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS = 0x0482 # macro +cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL = 0x0484 # macro +cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS = 0x0486 # macro +cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL = 0x0488 # macro +cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS = 0x048a # macro +cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL = 0x048c # macro +cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS = 0x048e # macro +cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL = 0x0490 # macro +cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS = 0x0492 # macro +cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL = 0x0494 # macro +cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS = 0x0496 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CAP_32GT = 0x0504 # macro +cfgBIF_CFG_DEV0_RC1_LINK_CNTL_32GT = 0x0508 # macro +cfgBIF_CFG_DEV0_RC1_LINK_STATUS_32GT = 0x050c # macro +cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST = 0x0048 # macro +cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W = 0x004c # macro +cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST = 0x0110 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 = 0x0114 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 = 0x0118 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL = 0x011c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS = 0x011e # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP = 0x0120 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL = 0x0124 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS = 0x012a # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP = 0x012c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL = 0x0130 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS = 0x0136 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0140 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 = 0x0144 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 = 0x0148 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST = 0x0200 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP = 0x0204 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL = 0x0208 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP = 0x020c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL = 0x0210 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP = 0x0214 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL = 0x0218 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP = 0x021c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL = 0x0220 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP = 0x0224 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL = 0x0228 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP = 0x022c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL = 0x0230 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x0240 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT = 0x0244 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA = 0x0248 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP = 0x024c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST = 0x0250 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP = 0x0254 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR = 0x0258 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS = 0x025c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL = 0x025e # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0260 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0261 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0262 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0263 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0264 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0265 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0266 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0267 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST = 0x0270 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 = 0x0274 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS = 0x0278 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL = 0x027c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL = 0x027e # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL = 0x0280 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL = 0x0282 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL = 0x0284 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL = 0x0286 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL = 0x0288 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL = 0x028a # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL = 0x028c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL = 0x028e # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL = 0x0290 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL = 0x0292 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL = 0x0294 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL = 0x0296 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL = 0x0298 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL = 0x029a # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST = 0x02d0 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP = 0x02d4 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL = 0x02d6 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST = 0x02f0 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP = 0x02f4 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL = 0x02f6 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 = 0x02f8 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 = 0x02fc # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 = 0x0300 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 = 0x0304 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 = 0x0308 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 = 0x030c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0x0310 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0x0314 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST = 0x0320 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP = 0x0324 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST = 0x0330 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP = 0x0334 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL = 0x0338 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS = 0x033a # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS = 0x033c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS = 0x033e # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS = 0x0340 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK = 0x0342 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET = 0x0344 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE = 0x0346 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID = 0x034a # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0x034c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE = 0x0350 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 = 0x0354 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 = 0x0358 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 = 0x035c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 = 0x0360 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 = 0x0364 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 = 0x0368 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0x036c # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST = 0x0400 # macro +cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP = 0x0404 # macro +cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS = 0x0408 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST = 0x0410 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT = 0x0414 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT = 0x0418 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT = 0x041c # macro +cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x0420 # macro +cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x0424 # macro +cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x0428 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT = 0x0430 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT = 0x0431 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT = 0x0432 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT = 0x0433 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT = 0x0434 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT = 0x0435 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT = 0x0436 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT = 0x0437 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT = 0x0438 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT = 0x0439 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT = 0x043a # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT = 0x043b # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT = 0x043c # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT = 0x043d # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT = 0x043e # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT = 0x043f # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST = 0x0450 # macro +cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP = 0x0454 # macro +cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS = 0x0456 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL = 0x0458 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS = 0x045a # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL = 0x045c # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS = 0x045e # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL = 0x0460 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS = 0x0462 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL = 0x0464 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS = 0x0466 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL = 0x0468 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS = 0x046a # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL = 0x046c # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS = 0x046e # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL = 0x0470 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS = 0x0472 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL = 0x0474 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS = 0x0476 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL = 0x0478 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS = 0x047a # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL = 0x047c # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS = 0x047e # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL = 0x0480 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS = 0x0482 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL = 0x0484 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS = 0x0486 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL = 0x0488 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS = 0x048a # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL = 0x048c # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS = 0x048e # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL = 0x0490 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS = 0x0492 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL = 0x0494 # macro +cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS = 0x0496 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST = 0x04c0 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP = 0x04c4 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL = 0x04c8 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP = 0x04cc # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL = 0x04d0 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP = 0x04d4 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL = 0x04d8 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP = 0x04dc # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL = 0x04e0 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP = 0x04e4 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL = 0x04e8 # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP = 0x04ec # macro +cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL = 0x04f0 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT = 0x0504 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT = 0x0508 # macro +cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT = 0x050c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF1_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF1_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF1_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF1_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF1_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST = 0x0048 # macro +cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W = 0x004c # macro +cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0140 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 = 0x0144 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 = 0x0148 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST = 0x0200 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP = 0x0204 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL = 0x0208 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP = 0x020c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL = 0x0210 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP = 0x0214 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL = 0x0218 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP = 0x021c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL = 0x0220 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP = 0x0224 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL = 0x0228 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP = 0x022c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL = 0x0230 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x0240 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT = 0x0244 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA = 0x0248 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP = 0x024c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST = 0x0250 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP = 0x0254 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR = 0x0258 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS = 0x025c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL = 0x025e # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0260 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0261 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0262 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0263 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0264 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0265 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0266 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0267 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST = 0x0270 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 = 0x0274 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS = 0x0278 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL = 0x027c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL = 0x027e # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL = 0x0280 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL = 0x0282 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL = 0x0284 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL = 0x0286 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL = 0x0288 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL = 0x028a # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL = 0x028c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL = 0x028e # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL = 0x0290 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL = 0x0292 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL = 0x0294 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL = 0x0296 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL = 0x0298 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL = 0x029a # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST = 0x02d0 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP = 0x02d4 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL = 0x02d6 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST = 0x02f0 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP = 0x02f4 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL = 0x02f6 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 = 0x02f8 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 = 0x02fc # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 = 0x0300 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 = 0x0304 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 = 0x0308 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 = 0x030c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0x0310 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0x0314 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST = 0x0320 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP = 0x0324 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST = 0x0330 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP = 0x0334 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL = 0x0338 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS = 0x033a # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS = 0x033c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS = 0x033e # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS = 0x0340 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK = 0x0342 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET = 0x0344 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE = 0x0346 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID = 0x034a # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0x034c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE = 0x0350 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 = 0x0354 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 = 0x0358 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 = 0x035c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 = 0x0360 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 = 0x0364 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 = 0x0368 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0x036c # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST = 0x04c0 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP = 0x04c4 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL = 0x04c8 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP = 0x04cc # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL = 0x04d0 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP = 0x04d4 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL = 0x04d8 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP = 0x04dc # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL = 0x04e0 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP = 0x04e4 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL = 0x04e8 # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP = 0x04ec # macro +cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL = 0x04f0 # macro +cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF2_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF2_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF2_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF2_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF2_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST = 0x0048 # macro +cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W = 0x004c # macro +cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_EPF2_1_SBRN = 0x0060 # macro +cfgBIF_CFG_DEV0_EPF2_1_FLADJ = 0x0061 # macro +cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD = 0x0062 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST = 0x0200 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP = 0x0204 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL = 0x0208 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP = 0x020c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL = 0x0210 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP = 0x0214 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL = 0x0218 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP = 0x021c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL = 0x0220 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP = 0x0224 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL = 0x0228 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP = 0x022c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL = 0x0230 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x0240 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT = 0x0244 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA = 0x0248 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP = 0x024c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST = 0x0250 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP = 0x0254 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR = 0x0258 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS = 0x025c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL = 0x025e # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0260 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0261 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0262 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0263 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0264 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0265 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0266 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0267 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST = 0x02d0 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP = 0x02d4 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL = 0x02d6 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF3_1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF3_1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF3_1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF3_1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF3_1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST = 0x0048 # macro +cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W = 0x004c # macro +cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_EPF3_1_SBRN = 0x0060 # macro +cfgBIF_CFG_DEV0_EPF3_1_FLADJ = 0x0061 # macro +cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD = 0x0062 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST = 0x0200 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP = 0x0204 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL = 0x0208 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP = 0x020c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL = 0x0210 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP = 0x0214 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL = 0x0218 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP = 0x021c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL = 0x0220 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP = 0x0224 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL = 0x0228 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP = 0x022c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL = 0x0230 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x0240 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT = 0x0244 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA = 0x0248 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP = 0x024c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST = 0x0250 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP = 0x0254 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR = 0x0258 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS = 0x025c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL = 0x025e # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0260 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0261 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0262 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0263 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0264 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0265 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0266 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0267 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST = 0x02d0 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP = 0x02d4 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL = 0x02d6 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL = 0x032e # macro +_nbio_4_3_0_SH_MASK_HEADER = True # macro +BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT = 0x0 # macro +BIF_BX0_PCIE_DATA__PCIE_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT = 0x0 # macro +BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK = 0x000000FF # macro +BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK = 0x000000FF # macro +BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK = 0x000000FF # macro +BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT = 0x7 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK = 0x00000080 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT = 0x19 # macro +RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK = 0x06000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT = 0x8 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK = 0x00000100 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT = 0x12 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT = 0x13 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK = 0x00040000 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK = 0x00080000 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT = 0x9 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0x15 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK = 0x00000200 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00200000 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT = 0xa # macro +RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK = 0x00000400 # macro +RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT = 0x6 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK = 0x00000008 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK = 0x00000040 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT = 0x6 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK = 0x00000008 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK = 0x00000040 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK = 0x00000080 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT = 0x6 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT = 0xa # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT = 0xd # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT = 0xe # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT = 0xf # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT = 0x10 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT = 0x11 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK = 0x00000007 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK = 0x00000038 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK = 0x00000040 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK = 0x00000380 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK = 0x00001C00 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK = 0x00002000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK = 0x00004000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK = 0x00008000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK = 0x00010000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK = 0x00020000 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0xFF # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK = 0x001F # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK = 0x0100 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK = 0x1F # macro +RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT = 0xa # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT = 0xc # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT = 0x19 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK = 0x00000C00 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK = 0x00003000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK = 0x01000000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK = 0x02000000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK = 0x00000007 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK = 0x000000F8 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK = 0x0000FF00 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0x19 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0x1a # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT = 0x1b # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT = 0x1c # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT = 0x1d # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT = 0x1e # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT = 0x1f # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x01000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x02000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x04000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK = 0x08000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK = 0x10000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK = 0x20000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK = 0x40000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK = 0x80000000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_PF0_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT = 0x19 # macro +BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK = 0xFE000000 # macro +BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT = 0x1 # macro +BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK = 0x00000002 # macro +BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT = 0x6 # macro +BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT = 0x7 # macro +BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT = 0xa # macro +BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT = 0xd # macro +BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT = 0x10 # macro +BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT = 0x11 # macro +BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT = 0x12 # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT = 0x18 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT = 0x19 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT = 0x1a # macro +BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT = 0x1b # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT = 0x1c # macro +BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT = 0x1d # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT = 0x1e # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT = 0x1f # macro +BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK = 0x00000040 # macro +BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK = 0x00000080 # macro +BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK = 0x00001C00 # macro +BIF_BX0_BUS_CNTL__SET_MC_TC_MASK = 0x0000E000 # macro +BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK = 0x00010000 # macro +BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK = 0x00020000 # macro +BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK = 0x00040000 # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK = 0x01000000 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK = 0x02000000 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK = 0x04000000 # macro +BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK = 0x08000000 # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK = 0x10000000 # macro +BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK = 0x20000000 # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK = 0x40000000 # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK = 0x80000000 # macro +BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT = 0x0 # macro +BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT = 0x0 # macro +BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK = 0xFFFFFFFF # macro +BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT = 0x10 # macro +BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK = 0x00010000 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT = 0x0 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT = 0x6 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT = 0x1f # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK = 0x00000007 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK = 0x000000C0 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK = 0x80000000 # macro +BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT = 0x0 # macro +BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK = 0x00000001 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT = 0x0 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT = 0x1 # macro +BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT = 0x3 # macro +BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT = 0x4 # macro +BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT = 0x8 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT = 0xf # macro +BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT = 0x10 # macro +BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT = 0x11 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT = 0x12 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK = 0x00000001 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK = 0x00000002 # macro +BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK = 0x00000008 # macro +BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK = 0x000000F0 # macro +BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK = 0x00000100 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK = 0x00008000 # macro +BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK = 0x00010000 # macro +BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK = 0x00020000 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK = 0x00040000 # macro +BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT = 0x0 # macro +BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT = 0x0 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT = 0x1 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT = 0x2 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT = 0x3 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT = 0x5 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT = 0x6 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT = 0x7 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT = 0x8 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT = 0x9 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT = 0xa # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT = 0xb # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT = 0xc # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT = 0xd # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK = 0x00000001 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK = 0x00000002 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK = 0x00000004 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK = 0x00000018 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK = 0x00000020 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK = 0x00000040 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK = 0x00000080 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK = 0x00000100 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK = 0x00000200 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK = 0x00000400 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK = 0x00000800 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK = 0x00001000 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK = 0x00002000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT = 0x0 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT = 0x1 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT = 0x2 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT = 0x3 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT = 0xb # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT = 0xc # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT = 0xd # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT = 0xf # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT = 0x10 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT = 0x19 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK = 0x00000001 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK = 0x00000002 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK = 0x00000004 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK = 0x00000008 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK = 0x00000800 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK = 0x00001000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK = 0x00002000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK = 0x00008000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK = 0x01FF0000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK = 0x02000000 # macro +BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT = 0x0 # macro +BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK = 0x000000FF # macro +BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT = 0x0 # macro +BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT = 0x1 # macro +BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT = 0x2 # macro +BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT = 0x3 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT = 0x4 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT = 0x18 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT = 0x19 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT = 0x1a # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT = 0x1b # macro +BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK = 0x00000001 # macro +BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK = 0x00000002 # macro +BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK = 0x00000004 # macro +BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK = 0x00000008 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK = 0x00000010 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK = 0x01000000 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK = 0x02000000 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK = 0x04000000 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK = 0x08000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT = 0x0 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT = 0x1 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT = 0x2 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT = 0x10 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT = 0x11 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT = 0x12 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x17 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT = 0x18 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT = 0x19 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT = 0x1a # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1c # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1d # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1e # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x1f # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK = 0x00000001 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK = 0x00000002 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK = 0x00000004 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK = 0x00010000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK = 0x00020000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK = 0x00040000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x00800000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK = 0x01000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK = 0x02000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK = 0x04000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x10000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x20000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x40000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x80000000 # macro +BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT = 0x0 # macro +BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT = 0x1 # macro +BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK = 0x00000001 # macro +BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK = 0x00000002 # macro +BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT = 0x0 # macro +BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK = 0x00000001 # macro +BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT = 0x0 # macro +BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK = 0x00000001 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT = 0x1 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT = 0x8 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK = 0x00000001 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK = 0x00000002 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK = 0x00000100 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT = 0x8 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT = 0x9 # macro +BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT = 0x11 # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT = 0x1a # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT = 0x1d # macro +BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT = 0x1e # macro +BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT = 0x1f # macro +BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK = 0x00000100 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK = 0x00003E00 # macro +BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK = 0x00020000 # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK = 0x1C000000 # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK = 0x20000000 # macro +BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK = 0x40000000 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK = 0x80000000 # macro +BIF_BX0_BIF_RB_BASE__ADDR__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX0_BIF_RB_RPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK = 0x00000001 # macro +BIF_BX0_BIF_RB_WPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK = 0x000000FF # macro +BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT = 0x0 # macro +BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT = 0xf # macro +RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK = 0x00008000 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK = 0x00000010 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT = 0x5 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT = 0xb # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT = 0x12 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT = 0x19 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK = 0x00000010 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK = 0x000007E0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK = 0x0003F800 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK = 0x01FC0000 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK = 0xFE000000 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT = 0x6 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT = 0xc # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK = 0x0000003F # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK = 0x00000FC0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK = 0x0001F000 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK = 0x00FE0000 # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK = 0x0000000F # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK = 0x000000F0 # macro +RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK = 0xFFFF # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT = 0x5 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT = 0x6 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT = 0x7 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT = 0xc # macro +RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT = 0xd # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x12 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x13 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x14 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x15 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT = 0x19 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT = 0x1c # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT = 0x1d # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK = 0x00000010 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK = 0x00000020 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK = 0x00000040 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK = 0x00000080 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK = 0x00001000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK = 0x00002000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00040000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00080000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00100000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00200000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK = 0x01000000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK = 0x0E000000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK = 0x10000000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK = 0xE0000000 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK = 0x00000018 # macro +RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK = 0x07FFFFFF # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT = 0x7 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT = 0x9 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT = 0xa # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT = 0xb # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT = 0xc # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT = 0xd # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT = 0xe # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT = 0xf # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT = 0x12 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT = 0x13 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK = 0x00000080 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK = 0x00000200 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK = 0x00000400 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK = 0x00000800 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK = 0x00001000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK = 0x00002000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK = 0x00004000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK = 0x00008000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK = 0x00040000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK = 0x00080000 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK = 0x0000FFFF # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK = 0xFFFF0000 # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK = 0x00001F00 # macro +RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK = 0x00007FFE # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT = 0x3 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK = 0x00000004 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT = 0xa # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT = 0xb # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT = 0xc # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT = 0xd # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0xe # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0xf # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK = 0x00000038 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK = 0x00000200 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK = 0x00000400 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK = 0x00000800 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK = 0x00002000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK = 0x000C0000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK = 0x02000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT = 0xa # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT = 0xc # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT = 0xd # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT = 0xf # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK = 0x00000200 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK = 0x00000C00 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK = 0x00006000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK = 0x00018000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK = 0x02000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK = 0x18000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT = 0xa # macro +RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT = 0xd # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT = 0xe # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT = 0xf # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK = 0x00000200 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK = 0x00000C00 # macro +RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK = 0x00002000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK = 0x00C00000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x06000000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK = 0x0E000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK = 0x0007FFC0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK = 0x0FFF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK = 0x00FFFFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK = 0x000FFE00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK = 0xFFF00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT = 0xd # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT = 0xf # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK = 0x00000E00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK = 0x00002000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK = 0x00700000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK = 0x03800000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK = 0x1C000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0xb # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK = 0x00000038 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK = 0x00000600 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x00003800 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x0003C000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x001C0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x01E00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK = 0x06000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK = 0x18000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK = 0x02000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK = 0x00030000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x0F000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0xF0000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK = 0x1F000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK = 0x000F0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK = 0x00F00000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK = 0xFF000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK = 0x3E000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK = 0x01FFE000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT = 0xf # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK = 0x00003E00 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK = 0x07000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK = 0x00E00000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT = 0xa # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK = 0x000003FF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK = 0x00000400 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK = 0x0F800000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00000007 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK = 0x00000070 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK = 0x00001E00 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK = 0x0000E000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00070000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK = 0x00780000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK = 0x03800000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK = 0x38000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK = 0xC0000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK = 0x00C00000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK = 0x000F0000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK = 0x00F00000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK = 0x00003E00 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK = 0x07000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK = 0x0F800000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK = 0x00000004 # macro +BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT = 0x0 # macro +GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK = 0x00000001 # macro +GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT = 0x0 # macro +GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK = 0x0000FFFF # macro +GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT = 0x0 # macro +GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0x1 # macro +GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT = 0x2 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT = 0x8 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT = 0x10 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT = 0x18 # macro +GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK = 0x00000001 # macro +GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000002 # macro +GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK = 0x0000000C # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK = 0x0000FF00 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK = 0x00FF0000 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK = 0xFF000000 # macro +GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT = 0x8 # macro +GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT = 0xa # macro +GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT = 0xc # macro +GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT = 0xf # macro +GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT = 0x10 # macro +GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK = 0x00000300 # macro +GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK = 0x00000C00 # macro +GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK = 0x00003000 # macro +GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK = 0x00008000 # macro +GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +PSWUSCFG0_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +PSWUSCFG0_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +PSWUSCFG0_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +PSWUSCFG0_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +PSWUSCFG0_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +PSWUSCFG0_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +PSWUSCFG0_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +PSWUSCFG0_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +PSWUSCFG0_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +PSWUSCFG0_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +PSWUSCFG0_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +PSWUSCFG0_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +PSWUSCFG0_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +PSWUSCFG0_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +PSWUSCFG0_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +PSWUSCFG0_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +PSWUSCFG0_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +PSWUSCFG0_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +PSWUSCFG0_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +PSWUSCFG0_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +PSWUSCFG0_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +PSWUSCFG0_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +PSWUSCFG0_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +PSWUSCFG0_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +PSWUSCFG0_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +PSWUSCFG0_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +PSWUSCFG0_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +PSWUSCFG0_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +PSWUSCFG0_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +PSWUSCFG0_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +PSWUSCFG0_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +PSWUSCFG0_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +PSWUSCFG0_0_BIST__BIST_COMP_MASK = 0x0F # macro +PSWUSCFG0_0_BIST__BIST_STRT_MASK = 0x40 # macro +PSWUSCFG0_0_BIST__BIST_CAP_MASK = 0x80 # macro +PSWUSCFG0_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +PSWUSCFG0_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +PSWUSCFG0_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +PSWUSCFG0_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +PSWUSCFG0_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +PSWUSCFG0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +PSWUSCFG0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +PSWUSCFG0_0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +PSWUSCFG0_0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +PSWUSCFG0_0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +PSWUSCFG0_0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +PSWUSCFG0_0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +PSWUSCFG0_0_PMI_CAP__VERSION_MASK = 0x0007 # macro +PSWUSCFG0_0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +PSWUSCFG0_0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +PSWUSCFG0_0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +PSWUSCFG0_0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +PSWUSCFG0_0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +PSWUSCFG0_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +PSWUSCFG0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +PSWUSCFG0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT = 0xf # macro +PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK = 0x8000 # macro +PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +PSWUSCFG0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +PSWUSCFG0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +PSWUSCFG0_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +PSWUSCFG0_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +PSWUSCFG0_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +PSWUSCFG0_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +PSWUSCFG0_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +PSWUSCFG0_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +PSWUSCFG0_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +PSWUSCFG0_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +PSWUSCFG0_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +PSWUSCFG0_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +PSWUSCFG0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +PSWUSCFG0_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +PSWUSCFG0_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +PSWUSCFG0_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +PSWUSCFG0_0_MSI_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x10 # macro +PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_MSI_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF0000 # macro +PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x10 # macro +PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF0000 # macro +PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +PSWUSCFG0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT = 0x1 # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK = 0x00000001 # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK = 0x007FFFFE # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_0_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED__SHIFT = 0x8 # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED__SHIFT = 0x9 # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED__SHIFT = 0xa # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +PSWUSCFG0_0_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +PSWUSCFG0_0_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED_MASK = 0x00000100 # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED_MASK = 0x00000200 # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED_MASK = 0x00000400 # macro +PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +PSWUSCFG0_0_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE__SHIFT = 0x1 # macro +PSWUSCFG0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED__SHIFT = 0x8 # macro +PSWUSCFG0_0_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE_MASK = 0x00000001 # macro +PSWUSCFG0_0_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE_MASK = 0x00000002 # macro +PSWUSCFG0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED_MASK = 0x00000700 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL__SHIFT = 0x6 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED__SHIFT = 0xa # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL_MASK = 0x000000C0 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +PSWUSCFG0_0_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED_MASK = 0x00000400 # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK = 0x00007F80 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK = 0x00018000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK = 0xFFF80000 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK = 0x00C0 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_AP_CAP__COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_AP_CAP__COUNT_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS_MASK = 0x0000FFE0 # macro +BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS_MASK = 0xFFFFFFFE # macro +BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_RC0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS_MASK = 0x0000FFE0 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS_MASK = 0xFFFFFFFE # macro +BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK = 0x3F # macro +BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK = 0x3F # macro +BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +PCIE_INDEX__PCIE_INDEX__SHIFT = 0x0 # macro +PCIE_INDEX__PCIE_INDEX_MASK = 0xFFFFFFFF # macro +PCIE_DATA__PCIE_DATA__SHIFT = 0x0 # macro +PCIE_DATA__PCIE_DATA_MASK = 0xFFFFFFFF # macro +PCIE_INDEX2__PCIE_INDEX2__SHIFT = 0x0 # macro +PCIE_INDEX2__PCIE_INDEX2_MASK = 0xFFFFFFFF # macro +PCIE_DATA2__PCIE_DATA2__SHIFT = 0x0 # macro +PCIE_DATA2__PCIE_DATA2_MASK = 0xFFFFFFFF # macro +PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT = 0x0 # macro +PCIE_INDEX_HI__PCIE_INDEX_HI_MASK = 0x000000FF # macro +PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT = 0x0 # macro +PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK = 0x000000FF # macro +SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT = 0x0 # macro +SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT = 0x0 # macro +SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT = 0x0 # macro +SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT = 0x0 # macro +SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_EngineA_INTR_CNTL__EngineA_CMD_COMPLETE__SHIFT = 0x0 # macro +BIF_EngineA_INTR_CNTL__EngineA_HANG_SELF_RECOVERED__SHIFT = 0x1 # macro +BIF_EngineA_INTR_CNTL__EngineA_HANG_NEED_FLR__SHIFT = 0x2 # macro +BIF_EngineA_INTR_CNTL__EngineA_VM_BUSY_TRANSITION__SHIFT = 0x3 # macro +BIF_EngineA_INTR_CNTL__EngineA_INST_SEL__SHIFT = 0x1c # macro +BIF_EngineA_INTR_CNTL__EngineA_CMD_COMPLETE_MASK = 0x00000001 # macro +BIF_EngineA_INTR_CNTL__EngineA_HANG_SELF_RECOVERED_MASK = 0x00000002 # macro +BIF_EngineA_INTR_CNTL__EngineA_HANG_NEED_FLR_MASK = 0x00000004 # macro +BIF_EngineA_INTR_CNTL__EngineA_VM_BUSY_TRANSITION_MASK = 0x00000008 # macro +BIF_EngineA_INTR_CNTL__EngineA_INST_SEL_MASK = 0xF0000000 # macro +BIF_EngineB_INTR_CNTL__EngineB_CMD_COMPLETE__SHIFT = 0x0 # macro +BIF_EngineB_INTR_CNTL__EngineB_HANG_SELF_RECOVERED__SHIFT = 0x1 # macro +BIF_EngineB_INTR_CNTL__EngineB_HANG_NEED_FLR__SHIFT = 0x2 # macro +BIF_EngineB_INTR_CNTL__EngineB_VM_BUSY_TRANSITION__SHIFT = 0x3 # macro +BIF_EngineB_INTR_CNTL__EngineB_INST_SEL__SHIFT = 0x1c # macro +BIF_EngineB_INTR_CNTL__EngineB_CMD_COMPLETE_MASK = 0x00000001 # macro +BIF_EngineB_INTR_CNTL__EngineB_HANG_SELF_RECOVERED_MASK = 0x00000002 # macro +BIF_EngineB_INTR_CNTL__EngineB_HANG_NEED_FLR_MASK = 0x00000004 # macro +BIF_EngineB_INTR_CNTL__EngineB_VM_BUSY_TRANSITION_MASK = 0x00000008 # macro +BIF_EngineB_INTR_CNTL__EngineB_INST_SEL_MASK = 0xF0000000 # macro +GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK = 0x000FFFFF # macro +GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK = 0x000000FF # macro +GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK = 0xFFFFFFFF # macro +GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK = 0xFFFFFFFF # macro +GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT = 0x0 # macro +GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT = 0x0 # macro +DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT = 0x0 # macro +DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT = 0x0 # macro +DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT = 0x0 # macro +DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT = 0x0 # macro +DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT = 0x0 # macro +DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT = 0x0 # macro +DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT = 0x0 # macro +DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT = 0x0 # macro +DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT = 0x0 # macro +DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT = 0x0 # macro +DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT = 0x0 # macro +DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT = 0x0 # macro +DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT = 0x0 # macro +DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT = 0x0 # macro +DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK = 0xFFFFFFFF # macro +DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT = 0x0 # macro +DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_0__FW_SCRATCH_0__SHIFT = 0x0 # macro +FW_SCRATCH_0__FW_SCRATCH_0_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_1__FW_SCRATCH_1__SHIFT = 0x0 # macro +FW_SCRATCH_1__FW_SCRATCH_1_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_2__FW_SCRATCH_2__SHIFT = 0x0 # macro +FW_SCRATCH_2__FW_SCRATCH_2_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_3__FW_SCRATCH_3__SHIFT = 0x0 # macro +FW_SCRATCH_3__FW_SCRATCH_3_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_4__FW_SCRATCH_4__SHIFT = 0x0 # macro +FW_SCRATCH_4__FW_SCRATCH_4_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_5__FW_SCRATCH_5__SHIFT = 0x0 # macro +FW_SCRATCH_5__FW_SCRATCH_5_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_6__FW_SCRATCH_6__SHIFT = 0x0 # macro +FW_SCRATCH_6__FW_SCRATCH_6_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_7__FW_SCRATCH_7__SHIFT = 0x0 # macro +FW_SCRATCH_7__FW_SCRATCH_7_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_8__FW_SCRATCH_8__SHIFT = 0x0 # macro +FW_SCRATCH_8__FW_SCRATCH_8_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_9__FW_SCRATCH_9__SHIFT = 0x0 # macro +FW_SCRATCH_9__FW_SCRATCH_9_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_10__FW_SCRATCH_10__SHIFT = 0x0 # macro +FW_SCRATCH_10__FW_SCRATCH_10_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_11__FW_SCRATCH_11__SHIFT = 0x0 # macro +FW_SCRATCH_11__FW_SCRATCH_11_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_12__FW_SCRATCH_12__SHIFT = 0x0 # macro +FW_SCRATCH_12__FW_SCRATCH_12_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_13__FW_SCRATCH_13__SHIFT = 0x0 # macro +FW_SCRATCH_13__FW_SCRATCH_13_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_14__FW_SCRATCH_14__SHIFT = 0x0 # macro +FW_SCRATCH_14__FW_SCRATCH_14_MASK = 0xFFFFFFFF # macro +FW_SCRATCH_15__FW_SCRATCH_15__SHIFT = 0x0 # macro +FW_SCRATCH_15__FW_SCRATCH_15_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT = 0x0 # macro +SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT = 0x0 # macro +SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT = 0x0 # macro +SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT = 0x0 # macro +SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT = 0x0 # macro +SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT = 0x0 # macro +SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT = 0x0 # macro +SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT = 0x0 # macro +SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT = 0x0 # macro +SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT = 0x0 # macro +SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT = 0x0 # macro +SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT = 0x0 # macro +SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT = 0x0 # macro +DN_PCIE_RESERVED__PCIE_RESERVED_MASK = 0xFFFFFFFF # macro +DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT = 0x7 # macro +DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK = 0x00000080 # macro +DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT = 0x19 # macro +DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK = 0x06000000 # macro +DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT = 0x8 # macro +DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK = 0x00000100 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT = 0x12 # macro +PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT = 0x13 # macro +PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT = 0x14 # macro +PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK = 0x00040000 # macro +PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK = 0x00080000 # macro +PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK = 0x00100000 # macro +PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT = 0x9 # macro +PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0x15 # macro +PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK = 0x00000200 # macro +PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00200000 # macro +PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT = 0x0 # macro +PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK = 0x00000001 # macro +PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT = 0xa # macro +PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK = 0x00000400 # macro +LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT = 0x0 # macro +LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK = 0xFFFFFFFF # macro +EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT = 0x0 # macro +EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT = 0x1 # macro +EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT = 0x2 # macro +EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT = 0x3 # macro +EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT = 0x4 # macro +EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT = 0x6 # macro +EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK = 0x00000001 # macro +EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK = 0x00000002 # macro +EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK = 0x00000004 # macro +EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK = 0x00000008 # macro +EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK = 0x00000010 # macro +EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK = 0x00000040 # macro +EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT = 0x0 # macro +EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT = 0x1 # macro +EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT = 0x2 # macro +EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT = 0x3 # macro +EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT = 0x4 # macro +EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT = 0x6 # macro +EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT = 0x7 # macro +EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK = 0x00000001 # macro +EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK = 0x00000002 # macro +EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK = 0x00000004 # macro +EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK = 0x00000008 # macro +EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK = 0x00000010 # macro +EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK = 0x00000040 # macro +EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK = 0x00000080 # macro +EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT = 0x0 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT = 0x3 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT = 0x6 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT = 0x7 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT = 0xa # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT = 0xd # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT = 0xe # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT = 0xf # macro +EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT = 0x10 # macro +EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT = 0x11 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK = 0x00000007 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK = 0x00000038 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK = 0x00000040 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK = 0x00000380 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK = 0x00001C00 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK = 0x00002000 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK = 0x00004000 # macro +EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK = 0x00008000 # macro +EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK = 0x00010000 # macro +EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK = 0x00020000 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0xFF # macro +EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT = 0x0 # macro +EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT = 0x8 # macro +EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK = 0x001F # macro +EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK = 0x0100 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT = 0x0 # macro +EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK = 0x1F # macro +EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT = 0x0 # macro +EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK = 0xFFFFFFFF # macro +EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT = 0xa # macro +EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT = 0xc # macro +EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT = 0x18 # macro +EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT = 0x19 # macro +EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT = 0x1a # macro +EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK = 0x00000C00 # macro +EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK = 0x00003000 # macro +EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK = 0x01000000 # macro +EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK = 0x02000000 # macro +EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK = 0x04000000 # macro +EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT = 0x0 # macro +EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT = 0x3 # macro +EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT = 0x8 # macro +EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK = 0x00000007 # macro +EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK = 0x000000F8 # macro +EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK = 0x0000FF00 # macro +EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0x18 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0x19 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0x1a # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT = 0x1b # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT = 0x1c # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT = 0x1d # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT = 0x1e # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT = 0x1f # macro +EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x01000000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x02000000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x04000000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK = 0x08000000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK = 0x10000000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK = 0x20000000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK = 0x40000000 # macro +EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK = 0x80000000 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +DVSEC_PRIV_CNTL__DVSEC_PRIV_REG__SHIFT = 0x0 # macro +DVSEC_PRIV_CNTL__DVSEC_PRIV_REG_MASK = 0xFFFFFFFF # macro +DVSEC_PRIV_CNTL2__DVSEC_PRIV_REG2__SHIFT = 0x0 # macro +DVSEC_PRIV_CNTL2__DVSEC_PRIV_REG2_MASK = 0xFFFFFFFF # macro +DVSEC_VF_PRIV_CNTL__DVSEC_VF_PRIV_REG__SHIFT = 0x0 # macro +DVSEC_VF_PRIV_CNTL__DVSEC_VF_PRIV_REG_MASK = 0xFFFFFFFF # macro +DVSEC_VF_PRIV_CNTL2__DVSEC_VF_PRIV_REG2__SHIFT = 0x0 # macro +DVSEC_VF_PRIV_CNTL2__DVSEC_VF_PRIV_REG2_MASK = 0xFFFFFFFF # macro +CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT = 0x19 # macro +CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK = 0xFE000000 # macro +BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT = 0x1 # macro +BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK = 0x00000002 # macro +BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT = 0x6 # macro +BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT = 0x7 # macro +BUS_CNTL__SET_AZ_TC__SHIFT = 0xa # macro +BUS_CNTL__SET_MC_TC__SHIFT = 0xd # macro +BUS_CNTL__ZERO_BE_WR_EN__SHIFT = 0x10 # macro +BUS_CNTL__ZERO_BE_RD_EN__SHIFT = 0x11 # macro +BUS_CNTL__RD_STALL_IO_WR__SHIFT = 0x12 # macro +BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT = 0x18 # macro +BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT = 0x19 # macro +BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT = 0x1a # macro +BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT = 0x1b # macro +BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT = 0x1c # macro +BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT = 0x1d # macro +BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT = 0x1e # macro +BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT = 0x1f # macro +BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK = 0x00000040 # macro +BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK = 0x00000080 # macro +BUS_CNTL__SET_AZ_TC_MASK = 0x00001C00 # macro +BUS_CNTL__SET_MC_TC_MASK = 0x0000E000 # macro +BUS_CNTL__ZERO_BE_WR_EN_MASK = 0x00010000 # macro +BUS_CNTL__ZERO_BE_RD_EN_MASK = 0x00020000 # macro +BUS_CNTL__RD_STALL_IO_WR_MASK = 0x00040000 # macro +BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK = 0x01000000 # macro +BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK = 0x02000000 # macro +BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK = 0x04000000 # macro +BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK = 0x08000000 # macro +BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK = 0x10000000 # macro +BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK = 0x20000000 # macro +BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK = 0x40000000 # macro +BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK = 0x80000000 # macro +BIF_SCRATCH0__BIF_SCRATCH0__SHIFT = 0x0 # macro +BIF_SCRATCH0__BIF_SCRATCH0_MASK = 0xFFFFFFFF # macro +BIF_SCRATCH1__BIF_SCRATCH1__SHIFT = 0x0 # macro +BIF_SCRATCH1__BIF_SCRATCH1_MASK = 0xFFFFFFFF # macro +BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT = 0x10 # macro +BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK = 0x00010000 # macro +MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT = 0x0 # macro +MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT = 0x6 # macro +MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT = 0x1f # macro +MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK = 0x00000007 # macro +MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK = 0x000000C0 # macro +MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK = 0x80000000 # macro +BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT = 0x0 # macro +BX_RESET_CNTL__LINK_TRAIN_EN_MASK = 0x00000001 # macro +INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT = 0x0 # macro +INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT = 0x1 # macro +INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT = 0x3 # macro +INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT = 0x4 # macro +INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT = 0x8 # macro +INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT = 0xf # macro +INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT = 0x10 # macro +INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT = 0x11 # macro +INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT = 0x12 # macro +INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK = 0x00000001 # macro +INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK = 0x00000002 # macro +INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK = 0x00000008 # macro +INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK = 0x000000F0 # macro +INTERRUPT_CNTL__GEN_IH_INT_EN_MASK = 0x00000100 # macro +INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK = 0x00008000 # macro +INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK = 0x00010000 # macro +INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK = 0x00020000 # macro +INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK = 0x00040000 # macro +INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT = 0x0 # macro +INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK = 0xFFFFFFFF # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT = 0x0 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT = 0x1 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT = 0x2 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT = 0x3 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT = 0x5 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT = 0x6 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT = 0x7 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT = 0x8 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT = 0x9 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT = 0xa # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT = 0xb # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT = 0xc # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT = 0xd # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK = 0x00000001 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK = 0x00000002 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK = 0x00000004 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK = 0x00000018 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK = 0x00000020 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK = 0x00000040 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK = 0x00000080 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK = 0x00000100 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK = 0x00000200 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK = 0x00000400 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK = 0x00000800 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK = 0x00001000 # macro +CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK = 0x00002000 # macro +BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT = 0x0 # macro +BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT = 0x1 # macro +BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT = 0x2 # macro +BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT = 0x3 # macro +BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT = 0xb # macro +BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT = 0xc # macro +BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT = 0xd # macro +BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT = 0xf # macro +BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT = 0x10 # macro +BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT = 0x19 # macro +BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK = 0x00000001 # macro +BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK = 0x00000002 # macro +BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK = 0x00000004 # macro +BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK = 0x00000008 # macro +BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK = 0x00000800 # macro +BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK = 0x00001000 # macro +BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK = 0x00002000 # macro +BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK = 0x00008000 # macro +BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK = 0x01FF0000 # macro +BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK = 0x02000000 # macro +HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT = 0x0 # macro +HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK = 0x000000FF # macro +BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT = 0x0 # macro +BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT = 0x1 # macro +BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT = 0x2 # macro +BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT = 0x3 # macro +BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT = 0x4 # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT = 0x18 # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT = 0x19 # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT = 0x1a # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT = 0x1b # macro +BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK = 0x00000001 # macro +BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK = 0x00000002 # macro +BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK = 0x00000004 # macro +BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK = 0x00000008 # macro +BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK = 0x00000010 # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK = 0x01000000 # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK = 0x02000000 # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK = 0x04000000 # macro +BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK = 0x08000000 # macro +BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT = 0x0 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT = 0x1 # macro +BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT = 0x2 # macro +BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT = 0x10 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT = 0x11 # macro +BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT = 0x12 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x17 # macro +BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT = 0x18 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT = 0x19 # macro +BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT = 0x1a # macro +BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1c # macro +BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1d # macro +BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1e # macro +BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x1f # macro +BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK = 0x00000001 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK = 0x00000002 # macro +BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK = 0x00000004 # macro +BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK = 0x00010000 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK = 0x00020000 # macro +BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK = 0x00040000 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x00800000 # macro +BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK = 0x01000000 # macro +BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK = 0x02000000 # macro +BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK = 0x04000000 # macro +BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x10000000 # macro +BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x20000000 # macro +BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x40000000 # macro +BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x80000000 # macro +BIF_FB_EN__FB_READ_EN__SHIFT = 0x0 # macro +BIF_FB_EN__FB_WRITE_EN__SHIFT = 0x1 # macro +BIF_FB_EN__FB_READ_EN_MASK = 0x00000001 # macro +BIF_FB_EN__FB_WRITE_EN_MASK = 0x00000002 # macro +BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT = 0x0 # macro +BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK = 0x00000001 # macro +BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BACO_CNTL__BACO_EN__SHIFT = 0x0 # macro +BACO_CNTL__BACO_DUMMY_EN__SHIFT = 0x2 # macro +BACO_CNTL__BACO_POWER_OFF__SHIFT = 0x3 # macro +BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT = 0x5 # macro +BACO_CNTL__BACO_RST_INTR_MASK__SHIFT = 0x6 # macro +BACO_CNTL__BACO_MODE__SHIFT = 0x8 # macro +BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT = 0x9 # macro +BACO_CNTL__PWRGOOD_VDDSOC__SHIFT = 0x10 # macro +BACO_CNTL__BACO_AUTO_EXIT__SHIFT = 0x1f # macro +BACO_CNTL__BACO_EN_MASK = 0x00000001 # macro +BACO_CNTL__BACO_DUMMY_EN_MASK = 0x00000004 # macro +BACO_CNTL__BACO_POWER_OFF_MASK = 0x00000008 # macro +BACO_CNTL__BACO_DSTATE_BYPASS_MASK = 0x00000020 # macro +BACO_CNTL__BACO_RST_INTR_MASK_MASK = 0x00000040 # macro +BACO_CNTL__BACO_MODE_MASK = 0x00000100 # macro +BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK = 0x00000200 # macro +BACO_CNTL__PWRGOOD_VDDSOC_MASK = 0x00010000 # macro +BACO_CNTL__BACO_AUTO_EXIT_MASK = 0x80000000 # macro +BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT = 0x0 # macro +BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT = 0x18 # macro +BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT = 0x1a # macro +BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT = 0x1b # macro +BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT = 0x1c # macro +BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT = 0x1d # macro +BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT = 0x1f # macro +BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK = 0x000FFFFF # macro +BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK = 0x01000000 # macro +BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK = 0x04000000 # macro +BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK = 0x08000000 # macro +BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK = 0x10000000 # macro +BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK = 0x60000000 # macro +BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK = 0x80000000 # macro +BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT = 0x0 # macro +BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK = 0x000FFFFF # macro +BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK = 0x000FFFFF # macro +MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT = 0x0 # macro +MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK = 0x00000001 # macro +NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT = 0x1 # macro +NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT = 0x8 # macro +NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK = 0x00000001 # macro +NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK = 0x00000002 # macro +NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK = 0x00000100 # macro +NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_0__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_1__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_2__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_3__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_4__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_5__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_6__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_7__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_8__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_9__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_10__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_11__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_12__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_13__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_14__ADDR_MASK = 0x00FFFFFF # macro +NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT = 0x0 # macro +NBIF_GFX_ADDR_LUT_15__ADDR_MASK = 0x00FFFFFF # macro +VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT = 0x0 # macro +VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT = 0x1 # macro +VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT = 0x2 # macro +VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT = 0x3 # macro +VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT = 0x4 # macro +VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT = 0x5 # macro +VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT = 0x6 # macro +VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT = 0x7 # macro +VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT = 0x8 # macro +VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT = 0x9 # macro +VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT = 0xa # macro +VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT = 0xb # macro +VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT = 0xc # macro +VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT = 0xd # macro +VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT = 0xe # macro +VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT = 0xf # macro +VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT = 0x10 # macro +VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT = 0x11 # macro +VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT = 0x12 # macro +VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT = 0x13 # macro +VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT = 0x14 # macro +VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT = 0x15 # macro +VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT = 0x16 # macro +VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT = 0x17 # macro +VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT = 0x18 # macro +VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT = 0x19 # macro +VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT = 0x1a # macro +VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT = 0x1b # macro +VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT = 0x1c # macro +VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT = 0x1d # macro +VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT = 0x1e # macro +VF_REGWR_EN__VF_REGWR_EN_VF0_MASK = 0x00000001 # macro +VF_REGWR_EN__VF_REGWR_EN_VF1_MASK = 0x00000002 # macro +VF_REGWR_EN__VF_REGWR_EN_VF2_MASK = 0x00000004 # macro +VF_REGWR_EN__VF_REGWR_EN_VF3_MASK = 0x00000008 # macro +VF_REGWR_EN__VF_REGWR_EN_VF4_MASK = 0x00000010 # macro +VF_REGWR_EN__VF_REGWR_EN_VF5_MASK = 0x00000020 # macro +VF_REGWR_EN__VF_REGWR_EN_VF6_MASK = 0x00000040 # macro +VF_REGWR_EN__VF_REGWR_EN_VF7_MASK = 0x00000080 # macro +VF_REGWR_EN__VF_REGWR_EN_VF8_MASK = 0x00000100 # macro +VF_REGWR_EN__VF_REGWR_EN_VF9_MASK = 0x00000200 # macro +VF_REGWR_EN__VF_REGWR_EN_VF10_MASK = 0x00000400 # macro +VF_REGWR_EN__VF_REGWR_EN_VF11_MASK = 0x00000800 # macro +VF_REGWR_EN__VF_REGWR_EN_VF12_MASK = 0x00001000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF13_MASK = 0x00002000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF14_MASK = 0x00004000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF15_MASK = 0x00008000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF16_MASK = 0x00010000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF17_MASK = 0x00020000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF18_MASK = 0x00040000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF19_MASK = 0x00080000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF20_MASK = 0x00100000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF21_MASK = 0x00200000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF22_MASK = 0x00400000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF23_MASK = 0x00800000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF24_MASK = 0x01000000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF25_MASK = 0x02000000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF26_MASK = 0x04000000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF27_MASK = 0x08000000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF28_MASK = 0x10000000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF29_MASK = 0x20000000 # macro +VF_REGWR_EN__VF_REGWR_EN_VF30_MASK = 0x40000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT = 0x0 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT = 0x1 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT = 0x2 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT = 0x3 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT = 0x4 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT = 0x5 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT = 0x6 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT = 0x7 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT = 0x8 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT = 0x9 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT = 0xa # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT = 0xb # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT = 0xc # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT = 0xd # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT = 0xe # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT = 0xf # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT = 0x10 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT = 0x11 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT = 0x12 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT = 0x13 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT = 0x14 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT = 0x15 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT = 0x16 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT = 0x17 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT = 0x18 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT = 0x19 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT = 0x1a # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT = 0x1b # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT = 0x1c # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT = 0x1d # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT = 0x1e # macro +VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT = 0x1f # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK = 0x00000001 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK = 0x00000002 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK = 0x00000004 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK = 0x00000008 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK = 0x00000010 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK = 0x00000020 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK = 0x00000040 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK = 0x00000080 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK = 0x00000100 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK = 0x00000200 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK = 0x00000400 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK = 0x00000800 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK = 0x00001000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK = 0x00002000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK = 0x00004000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK = 0x00008000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK = 0x00010000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK = 0x00020000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK = 0x00040000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK = 0x00080000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK = 0x00100000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK = 0x00200000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK = 0x00400000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK = 0x00800000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK = 0x01000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK = 0x02000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK = 0x04000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK = 0x08000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK = 0x10000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK = 0x20000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK = 0x40000000 # macro +VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK = 0x80000000 # macro +VF_FB_EN__VF_FB_EN_VF0__SHIFT = 0x0 # macro +VF_FB_EN__VF_FB_EN_VF1__SHIFT = 0x1 # macro +VF_FB_EN__VF_FB_EN_VF2__SHIFT = 0x2 # macro +VF_FB_EN__VF_FB_EN_VF3__SHIFT = 0x3 # macro +VF_FB_EN__VF_FB_EN_VF4__SHIFT = 0x4 # macro +VF_FB_EN__VF_FB_EN_VF5__SHIFT = 0x5 # macro +VF_FB_EN__VF_FB_EN_VF6__SHIFT = 0x6 # macro +VF_FB_EN__VF_FB_EN_VF7__SHIFT = 0x7 # macro +VF_FB_EN__VF_FB_EN_VF8__SHIFT = 0x8 # macro +VF_FB_EN__VF_FB_EN_VF9__SHIFT = 0x9 # macro +VF_FB_EN__VF_FB_EN_VF10__SHIFT = 0xa # macro +VF_FB_EN__VF_FB_EN_VF11__SHIFT = 0xb # macro +VF_FB_EN__VF_FB_EN_VF12__SHIFT = 0xc # macro +VF_FB_EN__VF_FB_EN_VF13__SHIFT = 0xd # macro +VF_FB_EN__VF_FB_EN_VF14__SHIFT = 0xe # macro +VF_FB_EN__VF_FB_EN_VF15__SHIFT = 0xf # macro +VF_FB_EN__VF_FB_EN_VF16__SHIFT = 0x10 # macro +VF_FB_EN__VF_FB_EN_VF17__SHIFT = 0x11 # macro +VF_FB_EN__VF_FB_EN_VF18__SHIFT = 0x12 # macro +VF_FB_EN__VF_FB_EN_VF19__SHIFT = 0x13 # macro +VF_FB_EN__VF_FB_EN_VF20__SHIFT = 0x14 # macro +VF_FB_EN__VF_FB_EN_VF21__SHIFT = 0x15 # macro +VF_FB_EN__VF_FB_EN_VF22__SHIFT = 0x16 # macro +VF_FB_EN__VF_FB_EN_VF23__SHIFT = 0x17 # macro +VF_FB_EN__VF_FB_EN_VF24__SHIFT = 0x18 # macro +VF_FB_EN__VF_FB_EN_VF25__SHIFT = 0x19 # macro +VF_FB_EN__VF_FB_EN_VF26__SHIFT = 0x1a # macro +VF_FB_EN__VF_FB_EN_VF27__SHIFT = 0x1b # macro +VF_FB_EN__VF_FB_EN_VF28__SHIFT = 0x1c # macro +VF_FB_EN__VF_FB_EN_VF29__SHIFT = 0x1d # macro +VF_FB_EN__VF_FB_EN_VF30__SHIFT = 0x1e # macro +VF_FB_EN__VF_FB_EN_VF0_MASK = 0x00000001 # macro +VF_FB_EN__VF_FB_EN_VF1_MASK = 0x00000002 # macro +VF_FB_EN__VF_FB_EN_VF2_MASK = 0x00000004 # macro +VF_FB_EN__VF_FB_EN_VF3_MASK = 0x00000008 # macro +VF_FB_EN__VF_FB_EN_VF4_MASK = 0x00000010 # macro +VF_FB_EN__VF_FB_EN_VF5_MASK = 0x00000020 # macro +VF_FB_EN__VF_FB_EN_VF6_MASK = 0x00000040 # macro +VF_FB_EN__VF_FB_EN_VF7_MASK = 0x00000080 # macro +VF_FB_EN__VF_FB_EN_VF8_MASK = 0x00000100 # macro +VF_FB_EN__VF_FB_EN_VF9_MASK = 0x00000200 # macro +VF_FB_EN__VF_FB_EN_VF10_MASK = 0x00000400 # macro +VF_FB_EN__VF_FB_EN_VF11_MASK = 0x00000800 # macro +VF_FB_EN__VF_FB_EN_VF12_MASK = 0x00001000 # macro +VF_FB_EN__VF_FB_EN_VF13_MASK = 0x00002000 # macro +VF_FB_EN__VF_FB_EN_VF14_MASK = 0x00004000 # macro +VF_FB_EN__VF_FB_EN_VF15_MASK = 0x00008000 # macro +VF_FB_EN__VF_FB_EN_VF16_MASK = 0x00010000 # macro +VF_FB_EN__VF_FB_EN_VF17_MASK = 0x00020000 # macro +VF_FB_EN__VF_FB_EN_VF18_MASK = 0x00040000 # macro +VF_FB_EN__VF_FB_EN_VF19_MASK = 0x00080000 # macro +VF_FB_EN__VF_FB_EN_VF20_MASK = 0x00100000 # macro +VF_FB_EN__VF_FB_EN_VF21_MASK = 0x00200000 # macro +VF_FB_EN__VF_FB_EN_VF22_MASK = 0x00400000 # macro +VF_FB_EN__VF_FB_EN_VF23_MASK = 0x00800000 # macro +VF_FB_EN__VF_FB_EN_VF24_MASK = 0x01000000 # macro +VF_FB_EN__VF_FB_EN_VF25_MASK = 0x02000000 # macro +VF_FB_EN__VF_FB_EN_VF26_MASK = 0x04000000 # macro +VF_FB_EN__VF_FB_EN_VF27_MASK = 0x08000000 # macro +VF_FB_EN__VF_FB_EN_VF28_MASK = 0x10000000 # macro +VF_FB_EN__VF_FB_EN_VF29_MASK = 0x20000000 # macro +VF_FB_EN__VF_FB_EN_VF30_MASK = 0x40000000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT = 0x0 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT = 0x1 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT = 0x2 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT = 0x3 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT = 0x4 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT = 0x5 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT = 0x6 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT = 0x7 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT = 0x8 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT = 0x9 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT = 0xa # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT = 0xb # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT = 0xc # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT = 0xd # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT = 0xe # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT = 0xf # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT = 0x10 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT = 0x11 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT = 0x12 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT = 0x13 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT = 0x14 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT = 0x15 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT = 0x16 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT = 0x17 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT = 0x18 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT = 0x19 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT = 0x1a # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT = 0x1b # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT = 0x1c # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT = 0x1d # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT = 0x1e # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK = 0x00000001 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK = 0x00000002 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK = 0x00000004 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK = 0x00000008 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK = 0x00000010 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK = 0x00000020 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK = 0x00000040 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK = 0x00000080 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK = 0x00000100 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK = 0x00000200 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK = 0x00000400 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK = 0x00000800 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK = 0x00001000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK = 0x00002000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK = 0x00004000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK = 0x00008000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK = 0x00010000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK = 0x00020000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK = 0x00040000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK = 0x00080000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK = 0x00100000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK = 0x00200000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK = 0x00400000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK = 0x00800000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK = 0x01000000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK = 0x02000000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK = 0x04000000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK = 0x08000000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK = 0x10000000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK = 0x20000000 # macro +VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK = 0x40000000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT = 0x0 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT = 0x1 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT = 0x2 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT = 0x3 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT = 0x4 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT = 0x5 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT = 0x6 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT = 0x7 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT = 0x8 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT = 0x9 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT = 0xa # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT = 0xb # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT = 0xc # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT = 0xd # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT = 0xe # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT = 0xf # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT = 0x10 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT = 0x11 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT = 0x12 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT = 0x13 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT = 0x14 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT = 0x15 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT = 0x16 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT = 0x17 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT = 0x18 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT = 0x19 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT = 0x1a # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT = 0x1b # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT = 0x1c # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT = 0x1d # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT = 0x1e # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK = 0x00000001 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK = 0x00000002 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK = 0x00000004 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK = 0x00000008 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK = 0x00000010 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK = 0x00000020 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK = 0x00000040 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK = 0x00000080 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK = 0x00000100 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK = 0x00000200 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK = 0x00000400 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK = 0x00000800 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK = 0x00001000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK = 0x00002000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK = 0x00004000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK = 0x00008000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK = 0x00010000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK = 0x00020000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK = 0x00040000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK = 0x00080000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK = 0x00100000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK = 0x00200000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK = 0x00400000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK = 0x00800000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK = 0x01000000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK = 0x02000000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK = 0x04000000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK = 0x08000000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK = 0x10000000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK = 0x20000000 # macro +VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK = 0x40000000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT = 0x0 # macro +VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT = 0x1 # macro +VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT = 0x2 # macro +VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT = 0x3 # macro +VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT = 0x4 # macro +VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT = 0x5 # macro +VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT = 0x6 # macro +VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT = 0x7 # macro +VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT = 0x8 # macro +VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT = 0x9 # macro +VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT = 0xa # macro +VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT = 0xb # macro +VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT = 0xc # macro +VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT = 0xd # macro +VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT = 0xe # macro +VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT = 0xf # macro +VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT = 0x10 # macro +VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT = 0x11 # macro +VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT = 0x12 # macro +VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT = 0x13 # macro +VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT = 0x14 # macro +VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT = 0x15 # macro +VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT = 0x16 # macro +VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT = 0x17 # macro +VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT = 0x18 # macro +VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT = 0x19 # macro +VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT = 0x1a # macro +VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT = 0x1b # macro +VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT = 0x1c # macro +VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT = 0x1d # macro +VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT = 0x1e # macro +VF_FB_STATUS__VF_FB_STATUS_VF0_MASK = 0x00000001 # macro +VF_FB_STATUS__VF_FB_STATUS_VF1_MASK = 0x00000002 # macro +VF_FB_STATUS__VF_FB_STATUS_VF2_MASK = 0x00000004 # macro +VF_FB_STATUS__VF_FB_STATUS_VF3_MASK = 0x00000008 # macro +VF_FB_STATUS__VF_FB_STATUS_VF4_MASK = 0x00000010 # macro +VF_FB_STATUS__VF_FB_STATUS_VF5_MASK = 0x00000020 # macro +VF_FB_STATUS__VF_FB_STATUS_VF6_MASK = 0x00000040 # macro +VF_FB_STATUS__VF_FB_STATUS_VF7_MASK = 0x00000080 # macro +VF_FB_STATUS__VF_FB_STATUS_VF8_MASK = 0x00000100 # macro +VF_FB_STATUS__VF_FB_STATUS_VF9_MASK = 0x00000200 # macro +VF_FB_STATUS__VF_FB_STATUS_VF10_MASK = 0x00000400 # macro +VF_FB_STATUS__VF_FB_STATUS_VF11_MASK = 0x00000800 # macro +VF_FB_STATUS__VF_FB_STATUS_VF12_MASK = 0x00001000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF13_MASK = 0x00002000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF14_MASK = 0x00004000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF15_MASK = 0x00008000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF16_MASK = 0x00010000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF17_MASK = 0x00020000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF18_MASK = 0x00040000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF19_MASK = 0x00080000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF20_MASK = 0x00100000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF21_MASK = 0x00200000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF22_MASK = 0x00400000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF23_MASK = 0x00800000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF24_MASK = 0x01000000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF25_MASK = 0x02000000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF26_MASK = 0x04000000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF27_MASK = 0x08000000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF28_MASK = 0x10000000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF29_MASK = 0x20000000 # macro +VF_FB_STATUS__VF_FB_STATUS_VF30_MASK = 0x40000000 # macro +GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT = 0x0 # macro +GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK = 0x00000001 # macro +REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +BIF_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT = 0x8 # macro +BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT = 0x9 # macro +BIF_RB_CNTL__BIF_RB_TRAN__SHIFT = 0x11 # macro +BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT = 0x1a # macro +BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT = 0x1d # macro +BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT = 0x1e # macro +BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT = 0x1f # macro +BIF_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +BIF_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK = 0x00000100 # macro +BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK = 0x00003E00 # macro +BIF_RB_CNTL__BIF_RB_TRAN_MASK = 0x00020000 # macro +BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK = 0x1C000000 # macro +BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK = 0x20000000 # macro +BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK = 0x40000000 # macro +BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK = 0x80000000 # macro +BIF_RB_BASE__ADDR__SHIFT = 0x0 # macro +BIF_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +BIF_RB_RPTR__OFFSET__SHIFT = 0x2 # macro +BIF_RB_RPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT = 0x0 # macro +BIF_RB_WPTR__OFFSET__SHIFT = 0x2 # macro +BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK = 0x00000001 # macro +BIF_RB_WPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +BIF_RB_WPTR_ADDR_HI__ADDR_MASK = 0x000000FF # macro +BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +BIF_RB_WPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +MAILBOX_INDEX__MAILBOX_INDEX__SHIFT = 0x0 # macro +MAILBOX_INDEX__MAILBOX_INDEX_MASK = 0x0000001F # macro +BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT = 0x2 # macro +BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT = 0x10 # macro +BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT = 0x11 # macro +BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT = 0x1f # macro +BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK = 0x00003FFC # macro +BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK = 0x00010000 # macro +BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK = 0x00020000 # macro +BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK = 0x80000000 # macro +BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT = 0x0 # macro +BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK = 0x00000001 # macro +BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK = 0x0000FFFF # macro +BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK = 0x00000FFF # macro +BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK = 0x000000FF # macro +BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK = 0x7FFFFFFF # macro +BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT = 0x0 # macro +BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK = 0x000000FF # macro +BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT = 0x0 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT = 0x1 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT = 0x2 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT = 0x3 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT = 0x4 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT = 0x5 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT = 0x6 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT = 0x7 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK = 0x00000001 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK = 0x00000002 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK = 0x00000004 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK = 0x00000008 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK = 0x00000010 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK = 0x00000020 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK = 0x00000040 # macro +BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK = 0x00000080 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT = 0x0 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT = 0x1 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT = 0x2 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT = 0x3 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT = 0x4 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT = 0x5 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK = 0x00000001 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK = 0x00000002 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK = 0x00000004 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK = 0x00000008 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK = 0x00000010 # macro +BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK = 0x00000020 # macro +PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT = 0x0 # macro +PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT = 0x1 # macro +PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK = 0x00000001 # macro +PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK = 0xFFFFFFFE # macro +BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT = 0x0 # macro +BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK = 0xFFFFFFFF # macro +BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT = 0x0 # macro +BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT = 0xa # macro +BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK = 0x000003FF # macro +BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK = 0x00000400 # macro +BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT = 0x0 # macro +BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK = 0xFFFFFFFF # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iTXIMPSEL__SHIFT = 0x0 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iCTFEN__SHIFT = 0x1 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iPD__SHIFT = 0x2 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iPU__SHIFT = 0x3 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXEN__SHIFT = 0x4 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL0__SHIFT = 0x5 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL1__SHIFT = 0x6 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_Reserved__SHIFT = 0x7 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iA__SHIFT = 0x8 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iOE__SHIFT = 0x9 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_Y__SHIFT = 0xa # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iTXIMPSEL_MASK = 0x00000001 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iCTFEN_MASK = 0x00000002 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iPD_MASK = 0x00000004 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iPU_MASK = 0x00000008 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXEN_MASK = 0x00000010 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL0_MASK = 0x00000020 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL1_MASK = 0x00000040 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_Reserved_MASK = 0x00000080 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iA_MASK = 0x00000100 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_iOE_MASK = 0x00000200 # macro +GPIO_CNTL_0_REG__GPIO_CNTL_0_Y_MASK = 0x00000400 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iTXIMPSEL__SHIFT = 0x0 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iCTFEN__SHIFT = 0x1 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iPD__SHIFT = 0x2 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iPU__SHIFT = 0x3 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXEN__SHIFT = 0x4 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL0__SHIFT = 0x5 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL1__SHIFT = 0x6 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_Reserved__SHIFT = 0x7 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iA__SHIFT = 0x8 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iOE__SHIFT = 0x9 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_Y__SHIFT = 0xa # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iTXIMPSEL_MASK = 0x00000001 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iCTFEN_MASK = 0x00000002 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iPD_MASK = 0x00000004 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iPU_MASK = 0x00000008 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXEN_MASK = 0x00000010 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL0_MASK = 0x00000020 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL1_MASK = 0x00000040 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_Reserved_MASK = 0x00000080 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iA_MASK = 0x00000100 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_iOE_MASK = 0x00000200 # macro +GPIO_CNTL_1_REG__GPIO_CNTL_1_Y_MASK = 0x00000400 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iTXIMPSEL__SHIFT = 0x0 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iCTFEN__SHIFT = 0x1 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iPD__SHIFT = 0x2 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iPU__SHIFT = 0x3 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXEN__SHIFT = 0x4 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL0__SHIFT = 0x5 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL1__SHIFT = 0x6 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_Reserved__SHIFT = 0x7 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iA__SHIFT = 0x8 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iOE__SHIFT = 0x9 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_Y__SHIFT = 0xa # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iTXIMPSEL_MASK = 0x00000001 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iCTFEN_MASK = 0x00000002 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iPD_MASK = 0x00000004 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iPU_MASK = 0x00000008 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXEN_MASK = 0x00000010 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL0_MASK = 0x00000020 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL1_MASK = 0x00000040 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_Reserved_MASK = 0x00000080 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iA_MASK = 0x00000100 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_iOE_MASK = 0x00000200 # macro +GPIO_CNTL_2_REG__GPIO_CNTL_2_Y_MASK = 0x00000400 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iTXIMPSEL__SHIFT = 0x0 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iCTFEN__SHIFT = 0x1 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iPD__SHIFT = 0x2 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iPU__SHIFT = 0x3 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXEN__SHIFT = 0x4 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL0__SHIFT = 0x5 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL1__SHIFT = 0x6 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_Reserved__SHIFT = 0x7 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iA__SHIFT = 0x8 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iOE__SHIFT = 0x9 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_Y__SHIFT = 0xa # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iTXIMPSEL_MASK = 0x00000001 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iCTFEN_MASK = 0x00000002 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iPD_MASK = 0x00000004 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iPU_MASK = 0x00000008 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXEN_MASK = 0x00000010 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL0_MASK = 0x00000020 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL1_MASK = 0x00000040 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_Reserved_MASK = 0x00000080 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iA_MASK = 0x00000100 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_iOE_MASK = 0x00000200 # macro +GPIO_CNTL_3_REG__GPIO_CNTL_3_Y_MASK = 0x00000400 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iTXIMPSEL__SHIFT = 0x0 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iCTFEN__SHIFT = 0x1 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iPD__SHIFT = 0x2 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iPU__SHIFT = 0x3 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXEN__SHIFT = 0x4 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL0__SHIFT = 0x5 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL1__SHIFT = 0x6 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_Reserved__SHIFT = 0x7 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iA__SHIFT = 0x8 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iOE__SHIFT = 0x9 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_Y__SHIFT = 0xa # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iTXIMPSEL_MASK = 0x00000001 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iCTFEN_MASK = 0x00000002 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iPD_MASK = 0x00000004 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iPU_MASK = 0x00000008 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXEN_MASK = 0x00000010 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL0_MASK = 0x00000020 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL1_MASK = 0x00000040 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_Reserved_MASK = 0x00000080 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iA_MASK = 0x00000100 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_iOE_MASK = 0x00000200 # macro +GPIO_CNTL_4_REG__GPIO_CNTL_4_Y_MASK = 0x00000400 # macro +CLDO_075_S5_CTRL__SPARE__SHIFT = 0x0 # macro +CLDO_075_S5_CTRL__LDO_VOLTAGE_OUT__SHIFT = 0x3 # macro +CLDO_075_S5_CTRL__SELECTS0__SHIFT = 0x6 # macro +CLDO_075_S5_CTRL__CONFIG_EN__SHIFT = 0x7 # macro +CLDO_075_S5_CTRL__SPARE_MASK = 0x00000007 # macro +CLDO_075_S5_CTRL__LDO_VOLTAGE_OUT_MASK = 0x00000038 # macro +CLDO_075_S5_CTRL__SELECTS0_MASK = 0x00000040 # macro +CLDO_075_S5_CTRL__CONFIG_EN_MASK = 0x00000080 # macro +CLDO_12_PCIE_CTRL__SPARE__SHIFT = 0x0 # macro +CLDO_12_PCIE_CTRL__LDO_VOLTAGE_OUT__SHIFT = 0x3 # macro +CLDO_12_PCIE_CTRL__SELECTS0__SHIFT = 0x6 # macro +CLDO_12_PCIE_CTRL__CONFIG_EN__SHIFT = 0x7 # macro +CLDO_12_PCIE_CTRL__SPARE_MASK = 0x00000007 # macro +CLDO_12_PCIE_CTRL__LDO_VOLTAGE_OUT_MASK = 0x00000038 # macro +CLDO_12_PCIE_CTRL__SELECTS0_MASK = 0x00000040 # macro +CLDO_12_PCIE_CTRL__CONFIG_EN_MASK = 0x00000080 # macro +SMNCLK_SEL__S5_SMN_CLK_SEL__SHIFT = 0x0 # macro +SMNCLK_SEL__S5_SMN_CLK_SEL_MASK = 0x00000001 # macro +RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT = 0x0 # macro +RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK = 0x00000001 # macro +RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT = 0x0 # macro +RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT = 0x1 # macro +RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK = 0x00000001 # macro +RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK = 0x00000002 # macro +RCC_RESET_EN__DB_APER_RESET_EN__SHIFT = 0xf # macro +RCC_RESET_EN__DB_APER_RESET_EN_MASK = 0x00008000 # macro +RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT = 0x0 # macro +RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT = 0x1 # macro +RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT = 0x2 # macro +RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT = 0x3 # macro +RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT = 0x4 # macro +RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK = 0x00000001 # macro +RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK = 0x00000002 # macro +RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK = 0x00000004 # macro +RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK = 0x00000008 # macro +RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK = 0x00000010 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT = 0x0 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT = 0x1 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT = 0x2 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT = 0x3 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT = 0x4 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT = 0x5 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT = 0xb # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT = 0x12 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT = 0x19 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK = 0x00000001 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK = 0x00000002 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK = 0x00000004 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK = 0x00000008 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK = 0x00000010 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK = 0x000007E0 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK = 0x0003F800 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK = 0x01FC0000 # macro +RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK = 0xFE000000 # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT = 0x0 # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT = 0x6 # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT = 0xc # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT = 0x11 # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK = 0x0000003F # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK = 0x00000FC0 # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK = 0x0001F000 # macro +RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK = 0x00FE0000 # macro +RCC_GPUIOV_REGION__LFB_REGION__SHIFT = 0x0 # macro +RCC_GPUIOV_REGION__MAX_REGION__SHIFT = 0x4 # macro +RCC_GPUIOV_REGION__LFB_REGION_MASK = 0x0000000F # macro +RCC_GPUIOV_REGION__MAX_REGION_MASK = 0x000000F0 # macro +RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT = 0x0 # macro +RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK = 0x00000001 # macro +RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT = 0x0 # macro +RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT = 0x1 # macro +RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK = 0x00000001 # macro +RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK = 0x00000002 # macro +RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT = 0x0 # macro +RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK = 0xFFFF # macro +RCC_PEER_REG_RANGE0__START_ADDR__SHIFT = 0x0 # macro +RCC_PEER_REG_RANGE0__END_ADDR__SHIFT = 0x10 # macro +RCC_PEER_REG_RANGE0__START_ADDR_MASK = 0x0000FFFF # macro +RCC_PEER_REG_RANGE0__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_PEER_REG_RANGE1__START_ADDR__SHIFT = 0x0 # macro +RCC_PEER_REG_RANGE1__END_ADDR__SHIFT = 0x10 # macro +RCC_PEER_REG_RANGE1__START_ADDR_MASK = 0x0000FFFF # macro +RCC_PEER_REG_RANGE1__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_BUS_CNTL__PMI_IO_DIS__SHIFT = 0x2 # macro +RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT = 0x3 # macro +RCC_BUS_CNTL__PMI_BM_DIS__SHIFT = 0x4 # macro +RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT = 0x5 # macro +RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT = 0x6 # macro +RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT = 0x7 # macro +RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT = 0x8 # macro +RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT = 0xc # macro +RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT = 0xd # macro +RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x10 # macro +RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x11 # macro +RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x12 # macro +RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x13 # macro +RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x14 # macro +RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x15 # macro +RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT = 0x18 # macro +RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT = 0x19 # macro +RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT = 0x1c # macro +RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT = 0x1d # macro +RCC_BUS_CNTL__PMI_IO_DIS_MASK = 0x00000004 # macro +RCC_BUS_CNTL__PMI_MEM_DIS_MASK = 0x00000008 # macro +RCC_BUS_CNTL__PMI_BM_DIS_MASK = 0x00000010 # macro +RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK = 0x00000020 # macro +RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK = 0x00000040 # macro +RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK = 0x00000080 # macro +RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK = 0x00000100 # macro +RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK = 0x00001000 # macro +RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK = 0x00002000 # macro +RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00010000 # macro +RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00020000 # macro +RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00040000 # macro +RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00080000 # macro +RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00100000 # macro +RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00200000 # macro +RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK = 0x01000000 # macro +RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK = 0x0E000000 # macro +RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK = 0x10000000 # macro +RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK = 0xE0000000 # macro +RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT = 0x0 # macro +RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT = 0x2 # macro +RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT = 0x3 # macro +RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK = 0x00000001 # macro +RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK = 0x00000004 # macro +RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK = 0x00000018 # macro +RCC_CONFIG_F0_BASE__F0_BASE__SHIFT = 0x0 # macro +RCC_CONFIG_F0_BASE__F0_BASE_MASK = 0xFFFFFFFF # macro +RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT = 0x0 # macro +RCC_CONFIG_APER_SIZE__APER_SIZE_MASK = 0xFFFFFFFF # macro +RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT = 0x0 # macro +RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK = 0x07FFFFFF # macro +RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT = 0x0 # macro +RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT = 0x1f # macro +RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK = 0x80000000 # macro +RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT = 0x0 # macro +RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT = 0x7 # macro +RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT = 0x8 # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT = 0x9 # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT = 0xa # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT = 0xb # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT = 0xc # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT = 0xd # macro +RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT = 0xe # macro +RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT = 0xf # macro +RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT = 0x10 # macro +RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT = 0x11 # macro +RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT = 0x12 # macro +RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT = 0x13 # macro +RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK = 0x00000080 # macro +RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK = 0x00000100 # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK = 0x00000200 # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK = 0x00000400 # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK = 0x00000800 # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK = 0x00001000 # macro +RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK = 0x00002000 # macro +RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK = 0x00004000 # macro +RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK = 0x00008000 # macro +RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK = 0x00010000 # macro +RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK = 0x00020000 # macro +RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK = 0x00040000 # macro +RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK = 0x00080000 # macro +RCC_BUSNUM_CNTL1__ID_MASK__SHIFT = 0x0 # macro +RCC_BUSNUM_CNTL1__ID_MASK_MASK = 0x000000FF # macro +RCC_BUSNUM_LIST0__ID0__SHIFT = 0x0 # macro +RCC_BUSNUM_LIST0__ID1__SHIFT = 0x8 # macro +RCC_BUSNUM_LIST0__ID2__SHIFT = 0x10 # macro +RCC_BUSNUM_LIST0__ID3__SHIFT = 0x18 # macro +RCC_BUSNUM_LIST0__ID0_MASK = 0x000000FF # macro +RCC_BUSNUM_LIST0__ID1_MASK = 0x0000FF00 # macro +RCC_BUSNUM_LIST0__ID2_MASK = 0x00FF0000 # macro +RCC_BUSNUM_LIST0__ID3_MASK = 0xFF000000 # macro +RCC_BUSNUM_LIST1__ID4__SHIFT = 0x0 # macro +RCC_BUSNUM_LIST1__ID5__SHIFT = 0x8 # macro +RCC_BUSNUM_LIST1__ID6__SHIFT = 0x10 # macro +RCC_BUSNUM_LIST1__ID7__SHIFT = 0x18 # macro +RCC_BUSNUM_LIST1__ID4_MASK = 0x000000FF # macro +RCC_BUSNUM_LIST1__ID5_MASK = 0x0000FF00 # macro +RCC_BUSNUM_LIST1__ID6_MASK = 0x00FF0000 # macro +RCC_BUSNUM_LIST1__ID7_MASK = 0xFF000000 # macro +RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT = 0x0 # macro +RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT = 0x8 # macro +RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT = 0x10 # macro +RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT = 0x11 # macro +RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK = 0x000000FF # macro +RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK = 0x00000100 # macro +RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK = 0x00010000 # macro +RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK = 0x00020000 # macro +RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT = 0x0 # macro +RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK = 0x00000001 # macro +RCC_HOST_BUSNUM__HOST_ID__SHIFT = 0x0 # macro +RCC_HOST_BUSNUM__HOST_ID_MASK = 0x0000FFFF # macro +RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT = 0x1f # macro +RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK = 0x80000000 # macro +RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT = 0x1f # macro +RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK = 0x80000000 # macro +RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT = 0x1f # macro +RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK = 0x80000000 # macro +RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT = 0x1f # macro +RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK = 0x80000000 # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT = 0x0 # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT = 0x8 # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT = 0x10 # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT = 0x18 # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK = 0x000000FF # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK = 0x0000FF00 # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK = 0x00FF0000 # macro +RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK = 0xFF000000 # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT = 0x0 # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT = 0x8 # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT = 0x10 # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT = 0x18 # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK = 0x000000FF # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK = 0x0000FF00 # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK = 0x00FF0000 # macro +RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK = 0xFF000000 # macro +RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT = 0x0 # macro +RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT = 0x8 # macro +RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT = 0x10 # macro +RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT = 0x11 # macro +RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK = 0x00000001 # macro +RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK = 0x00000100 # macro +RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK = 0x00010000 # macro +RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK = 0x00020000 # macro +RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT = 0x0 # macro +RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT = 0x1 # macro +RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT = 0x2 # macro +RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT = 0x3 # macro +RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT = 0x10 # macro +RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK = 0x00000001 # macro +RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK = 0x00000002 # macro +RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK = 0x00000004 # macro +RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK = 0x00000008 # macro +RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK = 0xFFFF0000 # macro +RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT = 0x0 # macro +RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT = 0x8 # macro +RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK = 0x000000FF # macro +RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK = 0x00001F00 # macro +RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT = 0x0 # macro +RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT = 0x1 # macro +RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK = 0x00000001 # macro +RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK = 0x00007FFE # macro +RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT = 0x0 # macro +RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT = 0x1 # macro +RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT = 0x2 # macro +RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT = 0x3 # macro +RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT = 0x6 # macro +RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT = 0x7 # macro +RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT = 0x8 # macro +RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT = 0x9 # macro +RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT = 0xa # macro +RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT = 0xb # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT = 0xc # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT = 0xd # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0xe # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0xf # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT = 0x10 # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT = 0x11 # macro +RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT = 0x12 # macro +RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT = 0x18 # macro +RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT = 0x19 # macro +RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT = 0x1a # macro +RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1b # macro +RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT = 0x1c # macro +RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT = 0x1d # macro +RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT = 0x1e # macro +RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT = 0x1f # macro +RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK = 0x00000001 # macro +RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK = 0x00000002 # macro +RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK = 0x00000004 # macro +RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK = 0x00000038 # macro +RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK = 0x00000040 # macro +RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK = 0x00000080 # macro +RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK = 0x00000100 # macro +RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK = 0x00000200 # macro +RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK = 0x00000400 # macro +RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK = 0x00000800 # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK = 0x00001000 # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK = 0x00002000 # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00004000 # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00008000 # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK = 0x00010000 # macro +RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK = 0x00020000 # macro +RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK = 0x000C0000 # macro +RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK = 0x01000000 # macro +RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK = 0x02000000 # macro +RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK = 0x04000000 # macro +RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK = 0x08000000 # macro +RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK = 0x10000000 # macro +RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK = 0x20000000 # macro +RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK = 0x40000000 # macro +RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK = 0x80000000 # macro +RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT = 0x1 # macro +RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT = 0x3 # macro +RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT = 0x5 # macro +RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x6 # macro +RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT = 0x7 # macro +RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT = 0x8 # macro +RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT = 0x9 # macro +RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT = 0xa # macro +RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT = 0xc # macro +RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT = 0xd # macro +RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT = 0xf # macro +RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT = 0x11 # macro +RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT = 0x12 # macro +RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT = 0x13 # macro +RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT = 0x14 # macro +RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT = 0x15 # macro +RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT = 0x16 # macro +RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT = 0x17 # macro +RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT = 0x18 # macro +RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT = 0x19 # macro +RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT = 0x1a # macro +RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT = 0x1b # macro +RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT = 0x1d # macro +RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT = 0x1e # macro +RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT = 0x1f # macro +RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK = 0x00000002 # macro +RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK = 0x00000008 # macro +RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK = 0x00000020 # macro +RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00000040 # macro +RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK = 0x00000080 # macro +RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK = 0x00000100 # macro +RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK = 0x00000200 # macro +RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK = 0x00000C00 # macro +RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK = 0x00001000 # macro +RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK = 0x00006000 # macro +RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK = 0x00018000 # macro +RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK = 0x00020000 # macro +RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK = 0x00040000 # macro +RCC_BIF_STRAP1__STRAP_DLF_EN_MASK = 0x00080000 # macro +RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK = 0x00100000 # macro +RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK = 0x00200000 # macro +RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK = 0x00400000 # macro +RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK = 0x00800000 # macro +RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK = 0x01000000 # macro +RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK = 0x02000000 # macro +RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK = 0x04000000 # macro +RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK = 0x18000000 # macro +RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK = 0x20000000 # macro +RCC_BIF_STRAP1__STRAP_AP_EN_MASK = 0x40000000 # macro +RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK = 0x80000000 # macro +RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT = 0x0 # macro +RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT = 0x3 # macro +RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT = 0x4 # macro +RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT = 0x5 # macro +RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT = 0x6 # macro +RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT = 0x8 # macro +RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT = 0x9 # macro +RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT = 0xa # macro +RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT = 0xd # macro +RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT = 0xe # macro +RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT = 0xf # macro +RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT = 0x10 # macro +RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT = 0x18 # macro +RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT = 0x1f # macro +RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK = 0x00000001 # macro +RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK = 0x00000008 # macro +RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK = 0x00000010 # macro +RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK = 0x00000020 # macro +RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK = 0x00000040 # macro +RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK = 0x00000100 # macro +RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK = 0x00000200 # macro +RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK = 0x00000C00 # macro +RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK = 0x00002000 # macro +RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK = 0x00004000 # macro +RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK = 0x00008000 # macro +RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK = 0x00FF0000 # macro +RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK = 0x01000000 # macro +RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK = 0x80000000 # macro +RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT = 0x0 # macro +RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT = 0x10 # macro +RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK = 0x0000FFFF # macro +RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK = 0xFFFF0000 # macro +RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT = 0x0 # macro +RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT = 0x10 # macro +RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK = 0x0000FFFF # macro +RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK = 0xFFFF0000 # macro +RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT = 0x0 # macro +RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT = 0x10 # macro +RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT = 0x11 # macro +RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT = 0x12 # macro +RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT = 0x13 # macro +RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT = 0x14 # macro +RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT = 0x16 # macro +RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT = 0x18 # macro +RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x19 # macro +RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1b # macro +RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT = 0x1c # macro +RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK = 0x0000FFFF # macro +RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK = 0x00010000 # macro +RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK = 0x00020000 # macro +RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK = 0x00040000 # macro +RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK = 0x00080000 # macro +RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK = 0x00100000 # macro +RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK = 0x00C00000 # macro +RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK = 0x01000000 # macro +RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x06000000 # macro +RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x08000000 # macro +RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK = 0x70000000 # macro +RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT = 0x0 # macro +RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT = 0x1 # macro +RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT = 0x2 # macro +RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK = 0x00000001 # macro +RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK = 0x00000002 # macro +RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK = 0x00000004 # macro +RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT = 0x12 # macro +RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT = 0x15 # macro +RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT = 0x18 # macro +RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT = 0x19 # macro +RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT = 0x1c # macro +RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT = 0x1f # macro +RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK = 0x00010000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK = 0x00040000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK = 0x00E00000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK = 0x01000000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK = 0x0E000000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK = 0x70000000 # macro +RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK = 0x80000000 # macro +RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT = 0x1 # macro +RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT = 0x2 # macro +RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT = 0x3 # macro +RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT = 0x4 # macro +RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT = 0x5 # macro +RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT = 0x6 # macro +RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK = 0x00000001 # macro +RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK = 0x00000002 # macro +RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK = 0x00000004 # macro +RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK = 0x00000008 # macro +RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK = 0x00000010 # macro +RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK = 0x00000020 # macro +RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK = 0x0007FFC0 # macro +RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT = 0x1c # macro +RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT = 0x1e # macro +RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK = 0x0000FFFF # macro +RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK = 0x0FFF0000 # macro +RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK = 0x10000000 # macro +RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK = 0x40000000 # macro +RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK = 0x00FFFFFF # macro +RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT = 0x9 # macro +RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT = 0x14 # macro +RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK = 0x000000FF # macro +RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK = 0x00000100 # macro +RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK = 0x000FFE00 # macro +RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK = 0xFFF00000 # macro +RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT = 0x1 # macro +RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT = 0x2 # macro +RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT = 0x3 # macro +RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT = 0x4 # macro +RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK = 0x00000001 # macro +RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK = 0x00000002 # macro +RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK = 0x00000004 # macro +RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK = 0x00000008 # macro +RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK = 0x00000010 # macro +RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT = 0x1 # macro +RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT = 0x2 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT = 0x3 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT = 0x4 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT = 0x5 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT = 0x6 # macro +RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT = 0x9 # macro +RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT = 0xc # macro +RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT = 0xd # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT = 0xe # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT = 0xf # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT = 0x11 # macro +RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x14 # macro +RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT = 0x17 # macro +RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x1a # macro +RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT = 0x1d # macro +RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK = 0x00000001 # macro +RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK = 0x00000002 # macro +RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK = 0x00000004 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK = 0x00000008 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK = 0x00000010 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK = 0x00000020 # macro +RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK = 0x00000040 # macro +RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK = 0x00000100 # macro +RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK = 0x00000E00 # macro +RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK = 0x00001000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK = 0x00002000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK = 0x00004000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK = 0x00008000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK = 0x00010000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK = 0x00020000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK = 0x00700000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK = 0x03800000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK = 0x1C000000 # macro +RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK = 0xE0000000 # macro +RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT = 0x1 # macro +RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT = 0x2 # macro +RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT = 0x6 # macro +RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT = 0x7 # macro +RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT = 0x9 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0xb # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0xe # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0x12 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0x15 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT = 0x19 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT = 0x1b # macro +RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT = 0x1f # macro +RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK = 0x00000001 # macro +RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK = 0x00000002 # macro +RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK = 0x00000004 # macro +RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK = 0x00000038 # macro +RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK = 0x00000040 # macro +RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK = 0x00000080 # macro +RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK = 0x00000100 # macro +RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK = 0x00000600 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x00003800 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x0003C000 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x001C0000 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x01E00000 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK = 0x06000000 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK = 0x18000000 # macro +RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK = 0x80000000 # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT = 0x18 # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK = 0x000000FF # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK = 0x0000FF00 # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK = 0x00FF0000 # macro +RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK = 0xFF000000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT = 0x12 # macro +RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT = 0x14 # macro +RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT = 0x15 # macro +RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT = 0x16 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT = 0x17 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT = 0x18 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT = 0x19 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT = 0x1a # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT = 0x1b # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT = 0x1c # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT = 0x1d # macro +RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT = 0x1f # macro +RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK = 0x000000FF # macro +RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK = 0x0000FF00 # macro +RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK = 0x00010000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK = 0x00040000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK = 0x00100000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK = 0x00200000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK = 0x00400000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK = 0x00800000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK = 0x01000000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK = 0x02000000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK = 0x04000000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK = 0x08000000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK = 0x10000000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK = 0x20000000 # macro +RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK = 0x80000000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT = 0x1 # macro +RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT = 0x2 # macro +RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x4 # macro +RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT = 0x5 # macro +RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x6 # macro +RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0xc # macro +RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT = 0x12 # macro +RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT = 0x13 # macro +RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT = 0x14 # macro +RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT = 0x15 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x18 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0x1c # macro +RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK = 0x00000001 # macro +RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK = 0x00000002 # macro +RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK = 0x00000004 # macro +RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000008 # macro +RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000010 # macro +RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK = 0x00000020 # macro +RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000040 # macro +RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x00000F00 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0x0000F000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK = 0x00030000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK = 0x00040000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK = 0x00080000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK = 0x00100000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK = 0x00E00000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x0F000000 # macro +RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0xF0000000 # macro +RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT = 0xc # macro +RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT = 0x18 # macro +RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT = 0x1d # macro +RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK = 0x000000FF # macro +RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK = 0x00000F00 # macro +RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK = 0x0000F000 # macro +RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK = 0x00FF0000 # macro +RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK = 0x1F000000 # macro +RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK = 0xE0000000 # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT = 0x18 # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK = 0x000000FF # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK = 0x0000FF00 # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK = 0x00FF0000 # macro +RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK = 0xFF000000 # macro +RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT = 0x0 # macro +RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT = 0x8 # macro +RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK = 0x000000FF # macro +RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK = 0x0000FF00 # macro +RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT = 0x10 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT = 0x14 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT = 0x18 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT = 0x1e # macro +RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK = 0x000F0000 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK = 0x00F00000 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK = 0x0F000000 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK = 0x40000000 # macro +RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK = 0xFFFF0000 # macro +RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT = 0x8 # macro +RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT = 0x10 # macro +RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT = 0x18 # macro +RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK = 0x000000FF # macro +RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK = 0x0000FF00 # macro +RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK = 0x00FF0000 # macro +RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK = 0xFF000000 # macro +RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT = 0x18 # macro +RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT = 0x19 # macro +RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT = 0x1e # macro +RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK = 0x01000000 # macro +RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK = 0x3E000000 # macro +RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK = 0x40000000 # macro +RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT = 0xc # macro +RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT = 0xd # macro +RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK = 0x00001000 # macro +RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK = 0x01FFE000 # macro +RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT = 0x6 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT = 0x7 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT = 0x9 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT = 0xe # macro +RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT = 0xf # macro +RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT = 0x10 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT = 0x17 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x18 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT = 0x1b # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT = 0x1d # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT = 0x1e # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK = 0x00000040 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK = 0x00000080 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK = 0x00003E00 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK = 0x00004000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK = 0x00008000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK = 0x00010000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK = 0x00800000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK = 0x07000000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK = 0x08000000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK = 0x20000000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK = 0x40000000 # macro +RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK = 0x00000FFF # macro +RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT = 0x10 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT = 0x13 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT = 0x15 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT = 0x18 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT = 0x1a # macro +RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT = 0x1b # macro +RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT = 0x1e # macro +RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK = 0x00010000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK = 0x00080000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK = 0x00E00000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK = 0x01000000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK = 0x04000000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK = 0x08000000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK = 0x40000000 # macro +RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT = 0xa # macro +RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT = 0x17 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT = 0x1c # macro +RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK = 0x000003FF # macro +RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK = 0x00000400 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK = 0x0F800000 # macro +RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK = 0x70000000 # macro +RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT = 0x1e # macro +RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK = 0x40000000 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT = 0x3 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT = 0x4 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT = 0x7 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x9 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT = 0xd # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x13 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT = 0x17 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT = 0x1a # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x1b # macro +RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT = 0x1e # macro +RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00000007 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK = 0x00000008 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK = 0x00000070 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK = 0x00000080 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK = 0x00001E00 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK = 0x0000E000 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00070000 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK = 0x00780000 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK = 0x03800000 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK = 0x04000000 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK = 0x38000000 # macro +RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK = 0xC0000000 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT = 0x13 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT = 0x14 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT = 0x15 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT = 0x16 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT = 0x18 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK = 0x00080000 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK = 0x00100000 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK = 0x00200000 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK = 0x00C00000 # macro +RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK = 0x0F000000 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT = 0x10 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT = 0x14 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT = 0x1e # macro +RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK = 0x000F0000 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK = 0x00F00000 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK = 0x40000000 # macro +RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT = 0x8 # macro +RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT = 0x10 # macro +RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK = 0x000000FF # macro +RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK = 0x0000FF00 # macro +RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK = 0x00FF0000 # macro +RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT = 0xc # macro +RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT = 0x18 # macro +RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK = 0x00000FFF # macro +RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK = 0x00FFF000 # macro +RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK = 0x01000000 # macro +RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT = 0xc # macro +RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK = 0x00000FFF # macro +RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK = 0x00FFF000 # macro +RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT = 0xc # macro +RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT = 0xd # macro +RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK = 0x00000FFF # macro +RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK = 0x00001000 # macro +RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK = 0x01FFE000 # macro +RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK = 0x00000FFF # macro +RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT = 0x7 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT = 0x8 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT = 0x9 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT = 0xe # macro +RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT = 0x10 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT = 0x17 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT = 0x18 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT = 0x1d # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT = 0x1e # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT = 0x1f # macro +RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK = 0x00000080 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK = 0x00000100 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK = 0x00003E00 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK = 0x00004000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK = 0x00010000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK = 0x00800000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK = 0x07000000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK = 0x20000000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK = 0x40000000 # macro +RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK = 0x80000000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT = 0x10 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT = 0x13 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT = 0x18 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT = 0x1a # macro +RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT = 0x1b # macro +RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT = 0x1e # macro +RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT = 0x1f # macro +RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK = 0x00010000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK = 0x00080000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK = 0x01000000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK = 0x04000000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK = 0x08000000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK = 0x40000000 # macro +RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK = 0x80000000 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT = 0x17 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT = 0x1c # macro +RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK = 0x0F800000 # macro +RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK = 0x70000000 # macro +RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT = 0x1e # macro +RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK = 0x40000000 # macro +RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT = 0x2 # macro +RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK = 0x00000004 # macro +BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT = 0x0 # macro +SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK = 0x00000001 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT = 0x0 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT = 0x1 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT = 0x2 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT = 0xa # macro +NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT = 0xb # macro +NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT = 0xc # macro +NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT = 0xd # macro +NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK = 0x00000001 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK = 0x00000002 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK = 0x000003FC # macro +NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK = 0x00000400 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK = 0x00000800 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK = 0x00001000 # macro +NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK = 0x00002000 # macro +NGDC_RESERVED_0__RESERVED__SHIFT = 0x0 # macro +NGDC_RESERVED_0__RESERVED_MASK = 0xFFFFFFFF # macro +NGDC_RESERVED_1__RESERVED__SHIFT = 0x0 # macro +NGDC_RESERVED_1__RESERVED_MASK = 0xFFFFFFFF # macro +NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT = 0x0 # macro +NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK = 0x0000FFFF # macro +ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT = 0x0 # macro +ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0x1 # macro +ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT = 0x2 # macro +ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT = 0x8 # macro +ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT = 0x10 # macro +ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT = 0x18 # macro +ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK = 0x00000001 # macro +ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000002 # macro +ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK = 0x0000000C # macro +ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK = 0x0000FF00 # macro +ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK = 0x00FF0000 # macro +ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK = 0xFF000000 # macro +S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT = 0x8 # macro +S2A_MISC_CNTL__RB_ARB_MODE__SHIFT = 0xa # macro +S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT = 0xc # macro +S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT = 0xf # macro +S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT = 0x10 # macro +S2A_MISC_CNTL__ATM_ARB_MODE_MASK = 0x00000300 # macro +S2A_MISC_CNTL__RB_ARB_MODE_MASK = 0x00000C00 # macro +S2A_MISC_CNTL__HSTR_ARB_MODE_MASK = 0x00003000 # macro +S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK = 0x00008000 # macro +S2A_MISC_CNTL__WRSP_ARB_MODE_MASK = 0x000F0000 # macro +NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT = 0x0 # macro +NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT = 0x1 # macro +NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT = 0x2 # macro +NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK = 0x00000001 # macro +NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK = 0x00000002 # macro +NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK = 0x00000004 # macro +NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT = 0x0 # macro +NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK = 0x00000001 # macro +NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT = 0xa # macro +NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT = 0xd # macro +NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT = 0xe # macro +NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT = 0x10 # macro +NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT = 0x18 # macro +NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT = 0x1f # macro +NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK = 0x00000400 # macro +NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK = 0x00002000 # macro +NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK = 0x00004000 # macro +NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK = 0x00010000 # macro +NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK = 0x3F000000 # macro +NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK = 0x80000000 # macro +NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT = 0x0 # macro +NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT = 0x8 # macro +NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT = 0xa # macro +NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT = 0xe # macro +NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK = 0x000000FF # macro +NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK = 0x00000100 # macro +NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK = 0x00003C00 # macro +NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK = 0x0000C000 # macro +NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT = 0x5 # macro +NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT = 0xa # macro +NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK = 0x000003E0 # macro +NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK = 0x00007C00 # macro +SUM_INDEX__SUM_INDEX__SHIFT = 0x0 # macro +SUM_INDEX__SUM_INDEX_MASK = 0xFFFFFFFF # macro +SUM_DATA__SUM_DATA__SHIFT = 0x0 # macro +SUM_DATA__SUM_DATA_MASK = 0xFFFFFFFF # macro +SUM_INDEX_HI__SUM_INDEX_HI__SHIFT = 0x0 # macro +SUM_INDEX_HI__SUM_INDEX_HI_MASK = 0x000000FF # macro +SHADOW_COMMAND__IOEN_UP__SHIFT = 0x0 # macro +SHADOW_COMMAND__MEMEN_UP__SHIFT = 0x1 # macro +SHADOW_COMMAND__IOEN_UP_MASK = 0x0001 # macro +SHADOW_COMMAND__MEMEN_UP_MASK = 0x0002 # macro +SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT = 0x0 # macro +SHADOW_BASE_ADDR_1__BAR1_UP_MASK = 0xFFFFFFFF # macro +SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT = 0x0 # macro +SHADOW_BASE_ADDR_2__BAR2_UP_MASK = 0xFFFFFFFF # macro +SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT = 0x8 # macro +SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT = 0x10 # macro +SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK = 0x0000FF00 # macro +SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK = 0x00FF0000 # macro +SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT = 0x4 # macro +SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT = 0xc # macro +SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK = 0x00F0 # macro +SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK = 0xF000 # macro +SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT = 0x4 # macro +SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT = 0x14 # macro +SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK = 0x0000FFF0 # macro +SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK = 0xFFF00000 # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT = 0x4 # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT = 0x14 # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK = 0x0000FFF0 # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK = 0xFFF00000 # macro +SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT = 0x0 # macro +SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK = 0xFFFFFFFF # macro +SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT = 0x0 # macro +SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK = 0xFFFFFFFF # macro +SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT = 0x0 # macro +SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT = 0x10 # macro +SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK = 0x0000FFFF # macro +SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK = 0xFFFF0000 # macro +SUC_INDEX__SUC_INDEX__SHIFT = 0x0 # macro +SUC_INDEX__SUC_INDEX_MASK = 0xFFFFFFFF # macro +SUC_DATA__SUC_DATA__SHIFT = 0x0 # macro +SUC_DATA__SUC_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_PF1_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +PCIEP_RESERVED__RESERVED__SHIFT = 0x0 # macro +PCIEP_RESERVED__RESERVED_MASK = 0xFFFFFFFF # macro +PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT = 0x0 # macro +PCIEP_SCRATCH__PCIEP_SCRATCH_MASK = 0xFFFFFFFF # macro +PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT = 0x0 # macro +PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT = 0x1 # macro +PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT = 0x2 # macro +PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT = 0x3 # macro +PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT = 0x4 # macro +PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT = 0x5 # macro +PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT = 0x8 # macro +PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT = 0x12 # macro +PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT = 0x18 # macro +PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT = 0x1a # macro +PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK = 0x00000001 # macro +PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK = 0x00000002 # macro +PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK = 0x00000004 # macro +PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK = 0x00000008 # macro +PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK = 0x00000010 # macro +PCIEP_PORT_CNTL__PMI_BM_DIS_MASK = 0x00000020 # macro +PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK = 0x0003FF00 # macro +PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK = 0x001C0000 # macro +PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK = 0x03000000 # macro +PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK = 0x0C000000 # macro +PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_FUNCTION__SHIFT = 0x10 # macro +PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_DEVICE__SHIFT = 0x13 # macro +PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_BUS__SHIFT = 0x18 # macro +PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_FUNCTION_MASK = 0x00070000 # macro +PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_DEVICE_MASK = 0x00F80000 # macro +PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_BUS_MASK = 0xFF000000 # macro +PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT = 0x0 # macro +PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT = 0x1 # macro +PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK = 0x00000001 # macro +PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK = 0x0000007E # macro +PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT = 0x1 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT = 0x2 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT = 0x5 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_POIS_TLP__SHIFT = 0x6 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT = 0x7 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0xc # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0xd # macro +PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT = 0xe # macro +PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT = 0xf # macro +PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT = 0x10 # macro +PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT = 0x13 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT = 0x14 # macro +PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK = 0x00000002 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK = 0x00000004 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK = 0x00000020 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_POIS_TLP_MASK = 0x00000040 # macro +PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK = 0x00000080 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x00001000 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x00002000 # macro +PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK = 0x00004000 # macro +PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK = 0x00008000 # macro +PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK = 0x00010000 # macro +PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK = 0x00080000 # macro +PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK = 0x00100000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT = 0x0 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT = 0x1 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT = 0x2 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT = 0x3 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT = 0x4 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT = 0x5 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT = 0x6 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT = 0x7 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT = 0xa # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT = 0xb # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT = 0xc # macro +PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT = 0xd # macro +PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT = 0xe # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_L23_MODE__SHIFT = 0xf # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT = 0x10 # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT = 0x13 # macro +PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT = 0x17 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT = 0x1c # macro +PSWUSP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT = 0x1d # macro +PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_ON_SURPDN_EN__SHIFT = 0x1e # macro +PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_3_EN__SHIFT = 0x1f # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK = 0x00000001 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK = 0x00000002 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK = 0x00000004 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK = 0x00000008 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK = 0x00000010 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK = 0x00000020 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK = 0x00000040 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK = 0x00000080 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK = 0x00000400 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK = 0x00000800 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK = 0x00001000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK = 0x00002000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK = 0x00004000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_L23_MODE_MASK = 0x00008000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK = 0x00070000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK = 0x00080000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK = 0x00800000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK = 0x10000000 # macro +PSWUSP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK = 0x20000000 # macro +PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_ON_SURPDN_EN_MASK = 0x40000000 # macro +PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_3_EN_MASK = 0x80000000 # macro +PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT = 0x0 # macro +PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK = 0x00000FFF # macro +PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT = 0x0 # macro +PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT = 0x18 # macro +PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK = 0x00FFFFFF # macro +PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK = 0x01000000 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT = 0x0 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT = 0x1 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT = 0x2 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT = 0x3 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT = 0x4 # macro +PCIE_RX_CNTL3__RX_ENH_ATOMIC_EN__SHIFT = 0x8 # macro +PCIE_RX_CNTL3__RX_INGRESS_POISONED_BLOCKING_EN__SHIFT = 0x9 # macro +PCIE_RX_CNTL3__RX_SWAP_RTRC_TO_BFRC_HDR_ONLY_ENABLE__SHIFT = 0xa # macro +PCIE_RX_CNTL3__RX_PRIV_POISON_EGRESS_BLOCK_EN__SHIFT = 0xb # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK = 0x00000001 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK = 0x00000002 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK = 0x00000004 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK = 0x00000008 # macro +PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK = 0x00000010 # macro +PCIE_RX_CNTL3__RX_ENH_ATOMIC_EN_MASK = 0x00000100 # macro +PCIE_RX_CNTL3__RX_INGRESS_POISONED_BLOCKING_EN_MASK = 0x00000200 # macro +PCIE_RX_CNTL3__RX_SWAP_RTRC_TO_BFRC_HDR_ONLY_ENABLE_MASK = 0x00000400 # macro +PCIE_RX_CNTL3__RX_PRIV_POISON_EGRESS_BLOCK_EN_MASK = 0x00000800 # macro +PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT = 0x0 # macro +PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT = 0x10 # macro +PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK = 0x00000FFF # macro +PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK = 0x00FF0000 # macro +PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT = 0x0 # macro +PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT = 0x10 # macro +PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK = 0x00000FFF # macro +PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK = 0x00FF0000 # macro +PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT = 0x0 # macro +PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT = 0x10 # macro +PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK = 0x00000FFF # macro +PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK = 0x00FF0000 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT = 0x0 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT = 0x2 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT = 0x4 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT = 0x6 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT = 0x8 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT = 0xa # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT = 0xc # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT = 0xe # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT = 0x10 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT = 0x12 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT = 0x14 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT = 0x16 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK = 0x00000003 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK = 0x0000000C # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK = 0x00000030 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK = 0x000000C0 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK = 0x00000300 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK = 0x00000C00 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK = 0x00003000 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK = 0x0000C000 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK = 0x00030000 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK = 0x000C0000 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK = 0x00300000 # macro +PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK = 0x00C00000 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT = 0x0 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT = 0x2 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT = 0x4 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT = 0x6 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT = 0x8 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT = 0xa # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT = 0xc # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT = 0xe # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT = 0x10 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT = 0x12 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK = 0x00000003 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK = 0x0000000C # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK = 0x00000030 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK = 0x000000C0 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK = 0x00000300 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK = 0x00000C00 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK = 0x00003000 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK = 0x0000C000 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK = 0x00030000 # macro +PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK = 0x000C0000 # macro +PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT = 0x0 # macro +PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT = 0x10 # macro +PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK = 0x0000FFFF # macro +PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK = 0xFFFF0000 # macro +PCIE_LC_CNTL__LC_ADVANCE_SPEED_COMPL_ON_EVERY_COMPL_ENTRY__SHIFT = 0x0 # macro +PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT = 0x1 # macro +PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT = 0x2 # macro +PCIE_LC_CNTL__LC_RESET_LINK__SHIFT = 0x3 # macro +PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT = 0x4 # macro +PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT = 0x8 # macro +PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT = 0xc # macro +PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT = 0x10 # macro +PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT = 0x11 # macro +PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT = 0x12 # macro +PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT = 0x14 # macro +PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT = 0x15 # macro +PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT = 0x16 # macro +PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT = 0x17 # macro +PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT = 0x18 # macro +PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT = 0x19 # macro +PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT = 0x1b # macro +PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT = 0x1c # macro +PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT = 0x1d # macro +PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT = 0x1e # macro +PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT = 0x1f # macro +PCIE_LC_CNTL__LC_ADVANCE_SPEED_COMPL_ON_EVERY_COMPL_ENTRY_MASK = 0x00000001 # macro +PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK = 0x00000002 # macro +PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK = 0x00000004 # macro +PCIE_LC_CNTL__LC_RESET_LINK_MASK = 0x00000008 # macro +PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK = 0x000000F0 # macro +PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK = 0x00000F00 # macro +PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK = 0x0000F000 # macro +PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK = 0x00010000 # macro +PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK = 0x00020000 # macro +PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK = 0x000C0000 # macro +PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK = 0x00100000 # macro +PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK = 0x00200000 # macro +PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK = 0x00400000 # macro +PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK = 0x00800000 # macro +PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK = 0x01000000 # macro +PCIE_LC_CNTL__LC_DELAY_COUNT_MASK = 0x06000000 # macro +PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK = 0x08000000 # macro +PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK = 0x10000000 # macro +PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK = 0x20000000 # macro +PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK = 0x40000000 # macro +PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK = 0x80000000 # macro +PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT = 0x0 # macro +PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT = 0x4 # macro +PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT = 0x5 # macro +PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT = 0x6 # macro +PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT = 0x7 # macro +PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT = 0x8 # macro +PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT = 0xb # macro +PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT = 0xc # macro +PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT = 0xd # macro +PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT = 0xe # macro +PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT = 0xf # macro +PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT = 0x10 # macro +PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT = 0x11 # macro +PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT = 0x12 # macro +PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT = 0x13 # macro +PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT = 0x14 # macro +PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT = 0x15 # macro +PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT = 0x16 # macro +PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT = 0x18 # macro +PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT = 0x19 # macro +PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT = 0x1a # macro +PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT = 0x1b # macro +PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT = 0x1c # macro +PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT = 0x1d # macro +PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK = 0x0000000F # macro +PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK = 0x00000010 # macro +PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK = 0x00000020 # macro +PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK = 0x00000040 # macro +PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK = 0x00000080 # macro +PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK = 0x00000700 # macro +PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK = 0x00000800 # macro +PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK = 0x00001000 # macro +PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK = 0x00002000 # macro +PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK = 0x00004000 # macro +PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK = 0x00008000 # macro +PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK = 0x00010000 # macro +PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK = 0x00020000 # macro +PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK = 0x00040000 # macro +PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK = 0x00080000 # macro +PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK = 0x00100000 # macro +PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK = 0x00200000 # macro +PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK = 0x00C00000 # macro +PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK = 0x01000000 # macro +PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK = 0x02000000 # macro +PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK = 0x04000000 # macro +PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK = 0x08000000 # macro +PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK = 0x10000000 # macro +PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK = 0xE0000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT = 0x0 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT = 0x4 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT = 0x7 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT = 0x8 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT = 0x9 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT = 0xa # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT = 0xb # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT = 0xc # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT = 0xd # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT = 0xe # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT = 0xf # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT = 0x11 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT = 0x12 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT = 0x13 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT = 0x14 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT = 0x15 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT = 0x18 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT = 0x19 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT = 0x1a # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT = 0x1b # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT = 0x1c # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT = 0x1d # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT = 0x1e # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT = 0x1f # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK = 0x00000007 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK = 0x00000070 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK = 0x00000080 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK = 0x00000100 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK = 0x00000200 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK = 0x00000400 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK = 0x00000800 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK = 0x00001000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK = 0x00002000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK = 0x00004000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK = 0x00008000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK = 0x00020000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK = 0x00040000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK = 0x00080000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK = 0x00100000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK = 0x00600000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK = 0x01000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK = 0x02000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK = 0x04000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK = 0x08000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK = 0x10000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK = 0x20000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK = 0x40000000 # macro +PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK = 0x80000000 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT = 0x0 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT = 0x8 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT = 0x9 # macro +PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT = 0xa # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT = 0xc # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT = 0xd # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_32GT_CNTL__SHIFT = 0xe # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT = 0x10 # macro +PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT = 0x18 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK = 0x000000FF # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK = 0x00000100 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK = 0x00000200 # macro +PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK = 0x00000400 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK = 0x00001000 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK = 0x00002000 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_32GT_CNTL_MASK = 0x00004000 # macro +PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK = 0x00FF0000 # macro +PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK = 0xFF000000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT = 0x5 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT = 0x8 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT = 0xb # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT = 0xc # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT = 0x15 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT = 0x16 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT = 0x17 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT = 0x18 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT = 0x19 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT = 0x1a # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT = 0x1b # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN5__SHIFT = 0x1c # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN5__SHIFT = 0x1d # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK = 0x000000E0 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK = 0x00000700 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK = 0x00000800 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK = 0x00007000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK = 0x00200000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK = 0x00400000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK = 0x00800000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK = 0x01000000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK = 0x02000000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK = 0x04000000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK = 0x08000000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN5_MASK = 0x10000000 # macro +PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN5_MASK = 0x20000000 # macro +PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT = 0x0 # macro +PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT = 0x8 # macro +PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT = 0x10 # macro +PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT = 0x18 # macro +PCIE_LC_STATE0__LC_CURRENT_STATE_MASK = 0x0000003F # macro +PCIE_LC_STATE0__LC_PREV_STATE1_MASK = 0x00003F00 # macro +PCIE_LC_STATE0__LC_PREV_STATE2_MASK = 0x003F0000 # macro +PCIE_LC_STATE0__LC_PREV_STATE3_MASK = 0x3F000000 # macro +PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT = 0x0 # macro +PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT = 0x8 # macro +PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT = 0x10 # macro +PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT = 0x18 # macro +PCIE_LC_STATE1__LC_PREV_STATE4_MASK = 0x0000003F # macro +PCIE_LC_STATE1__LC_PREV_STATE5_MASK = 0x00003F00 # macro +PCIE_LC_STATE1__LC_PREV_STATE6_MASK = 0x003F0000 # macro +PCIE_LC_STATE1__LC_PREV_STATE7_MASK = 0x3F000000 # macro +PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT = 0x0 # macro +PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT = 0x8 # macro +PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT = 0x10 # macro +PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT = 0x18 # macro +PCIE_LC_STATE2__LC_PREV_STATE8_MASK = 0x0000003F # macro +PCIE_LC_STATE2__LC_PREV_STATE9_MASK = 0x00003F00 # macro +PCIE_LC_STATE2__LC_PREV_STATE10_MASK = 0x003F0000 # macro +PCIE_LC_STATE2__LC_PREV_STATE11_MASK = 0x3F000000 # macro +PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT = 0x0 # macro +PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT = 0x8 # macro +PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT = 0x10 # macro +PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT = 0x18 # macro +PCIE_LC_STATE3__LC_PREV_STATE12_MASK = 0x0000003F # macro +PCIE_LC_STATE3__LC_PREV_STATE13_MASK = 0x00003F00 # macro +PCIE_LC_STATE3__LC_PREV_STATE14_MASK = 0x003F0000 # macro +PCIE_LC_STATE3__LC_PREV_STATE15_MASK = 0x3F000000 # macro +PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT = 0x0 # macro +PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT = 0x8 # macro +PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT = 0x10 # macro +PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT = 0x18 # macro +PCIE_LC_STATE4__LC_PREV_STATE16_MASK = 0x0000003F # macro +PCIE_LC_STATE4__LC_PREV_STATE17_MASK = 0x00003F00 # macro +PCIE_LC_STATE4__LC_PREV_STATE18_MASK = 0x003F0000 # macro +PCIE_LC_STATE4__LC_PREV_STATE19_MASK = 0x3F000000 # macro +PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT = 0x0 # macro +PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT = 0x8 # macro +PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT = 0x10 # macro +PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT = 0x18 # macro +PCIE_LC_STATE5__LC_PREV_STATE20_MASK = 0x0000003F # macro +PCIE_LC_STATE5__LC_PREV_STATE21_MASK = 0x00003F00 # macro +PCIE_LC_STATE5__LC_PREV_STATE22_MASK = 0x003F0000 # macro +PCIE_LC_STATE5__LC_PREV_STATE23_MASK = 0x3F000000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT = 0x0 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT = 0x6 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT = 0x7 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT = 0x8 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT = 0x9 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT = 0xa # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT = 0xb # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT = 0xc # macro +PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT = 0xd # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT = 0xe # macro +PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT = 0x10 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT = 0x11 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT = 0x12 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT = 0x13 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT = 0x14 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT = 0x15 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT = 0x16 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT = 0x17 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT = 0x19 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT = 0x1a # macro +PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT = 0x1c # macro +PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT = 0x1d # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT = 0x1f # macro +PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK = 0x0000003F # macro +PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK = 0x00000040 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK = 0x00000080 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK = 0x00000100 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK = 0x00000200 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK = 0x00000400 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK = 0x00000800 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK = 0x00001000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK = 0x00002000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK = 0x0000C000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK = 0x00010000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK = 0x00020000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK = 0x00040000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK = 0x00080000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK = 0x00100000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK = 0x00200000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK = 0x00400000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK = 0x01800000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK = 0x02000000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK = 0x04000000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK = 0x10000000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK = 0x60000000 # macro +PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK = 0x80000000 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT = 0x0 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT = 0x1 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT = 0x2 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT = 0x3 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT = 0x4 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT = 0x5 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT = 0x6 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT = 0x7 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT = 0x8 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT = 0x9 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT = 0xa # macro +PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT = 0xb # macro +PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK = 0x00000001 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK = 0x00000002 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK = 0x00000004 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK = 0x00000008 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK = 0x00000010 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK = 0x00000020 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK = 0x00000040 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK = 0x00000080 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK = 0x00000100 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK = 0x00000200 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK = 0x00000400 # macro +PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK = 0x00000800 # macro +PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT = 0x0 # macro +PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT = 0xc # macro +PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT = 0x18 # macro +PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK = 0x00000FFF # macro +PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK = 0x00FFF000 # macro +PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK = 0x03000000 # macro +PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT = 0x0 # macro +PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK = 0x0000FFFF # macro +PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT = 0x0 # macro +PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT = 0x1 # macro +PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT = 0x3 # macro +PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT = 0x4 # macro +PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT = 0x5 # macro +PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT = 0x6 # macro +PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT = 0x8 # macro +PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT = 0x9 # macro +PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT = 0xa # macro +PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT = 0xb # macro +PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT = 0xc # macro +PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT = 0xd # macro +PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT = 0xe # macro +PCIE_LC_CNTL3__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT = 0xf # macro +PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT = 0x11 # macro +PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT = 0x12 # macro +PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT = 0x13 # macro +PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT = 0x15 # macro +PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT = 0x16 # macro +PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT = 0x17 # macro +PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT = 0x18 # macro +PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT = 0x1a # macro +PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT = 0x1e # macro +PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT = 0x1f # macro +PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK = 0x00000001 # macro +PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK = 0x00000006 # macro +PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK = 0x00000008 # macro +PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK = 0x00000010 # macro +PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK = 0x00000020 # macro +PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK = 0x000000C0 # macro +PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK = 0x00000100 # macro +PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK = 0x00000200 # macro +PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK = 0x00000400 # macro +PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK = 0x00000800 # macro +PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK = 0x00001000 # macro +PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK = 0x00002000 # macro +PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK = 0x00004000 # macro +PCIE_LC_CNTL3__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK = 0x00008000 # macro +PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK = 0x00020000 # macro +PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK = 0x00040000 # macro +PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK = 0x00180000 # macro +PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK = 0x00200000 # macro +PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK = 0x00400000 # macro +PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK = 0x00800000 # macro +PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK = 0x03000000 # macro +PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK = 0x3C000000 # macro +PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK = 0x40000000 # macro +PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK = 0x80000000 # macro +PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT = 0x0 # macro +PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT = 0x2 # macro +PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT = 0x3 # macro +PCIE_LC_CNTL4__LC_L1_POWERDOWN__SHIFT = 0x4 # macro +PCIE_LC_CNTL4__LC_P2_ENTRY__SHIFT = 0x5 # macro +PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT = 0x6 # macro +PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MODE__SHIFT = 0x7 # macro +PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT = 0x8 # macro +PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT = 0xa # macro +PCIE_LC_CNTL4__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT = 0xb # macro +PCIE_LC_CNTL4__LC_SEND_EIEOS_IN_RCFG__SHIFT = 0xc # macro +PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT = 0xd # macro +PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT = 0xe # macro +PCIE_LC_CNTL4__LC_WAIT_FOR_TWO_EIEOS_SEQUENCE__SHIFT = 0xf # macro +PCIE_LC_CNTL4__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT = 0x10 # macro +PCIE_LC_CNTL4__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT = 0x11 # macro +PCIE_LC_CNTL4__LC_DELAY_COEFF_UPDATE_DIS__SHIFT = 0x12 # macro +PCIE_LC_CNTL4__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT = 0x13 # macro +PCIE_LC_CNTL4__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT = 0x15 # macro +PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT = 0x16 # macro +PCIE_LC_CNTL4__LC_TX_SWING__SHIFT = 0x17 # macro +PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT = 0x18 # macro +PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT = 0x19 # macro +PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT = 0x1a # macro +PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK = 0x00000003 # macro +PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK = 0x00000004 # macro +PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK = 0x00000008 # macro +PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK = 0x00000010 # macro +PCIE_LC_CNTL4__LC_P2_ENTRY_MASK = 0x00000020 # macro +PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK = 0x00000040 # macro +PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MODE_MASK = 0x00000080 # macro +PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK = 0x00000100 # macro +PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK = 0x00000400 # macro +PCIE_LC_CNTL4__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK = 0x00000800 # macro +PCIE_LC_CNTL4__LC_SEND_EIEOS_IN_RCFG_MASK = 0x00001000 # macro +PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK = 0x00002000 # macro +PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK = 0x00004000 # macro +PCIE_LC_CNTL4__LC_WAIT_FOR_TWO_EIEOS_SEQUENCE_MASK = 0x00008000 # macro +PCIE_LC_CNTL4__LC_DELAY_DETECTED_TSX_RCV_EN_MASK = 0x00010000 # macro +PCIE_LC_CNTL4__LC_DONT_CHECK_EQTS_IN_RCFG_MASK = 0x00020000 # macro +PCIE_LC_CNTL4__LC_DELAY_COEFF_UPDATE_DIS_MASK = 0x00040000 # macro +PCIE_LC_CNTL4__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK = 0x00180000 # macro +PCIE_LC_CNTL4__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK = 0x00200000 # macro +PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK = 0x00400000 # macro +PCIE_LC_CNTL4__LC_TX_SWING_MASK = 0x00800000 # macro +PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK = 0x01000000 # macro +PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK = 0x02000000 # macro +PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK = 0xFC000000 # macro +PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT = 0x0 # macro +PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT = 0x2 # macro +PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT = 0x6 # macro +PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT = 0xa # macro +PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT = 0x10 # macro +PCIE_LC_CNTL5__LC_LOCAL_USE_PRESET__SHIFT = 0x15 # macro +PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT = 0x16 # macro +PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT = 0x18 # macro +PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT = 0x19 # macro +PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT = 0x1a # macro +PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT = 0x1b # macro +PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT = 0x1c # macro +PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT = 0x1d # macro +PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK = 0x00000003 # macro +PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK = 0x0000003C # macro +PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK = 0x000003C0 # macro +PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK = 0x0000FC00 # macro +PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK = 0x001F0000 # macro +PCIE_LC_CNTL5__LC_LOCAL_USE_PRESET_MASK = 0x00200000 # macro +PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK = 0x00C00000 # macro +PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK = 0x01000000 # macro +PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK = 0x02000000 # macro +PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK = 0x04000000 # macro +PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK = 0x08000000 # macro +PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK = 0x10000000 # macro +PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK = 0xE0000000 # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT = 0x0 # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT = 0x1 # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT = 0x7 # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT = 0xd # macro +PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT = 0x13 # macro +PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT = 0x14 # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK = 0x00000001 # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK = 0x0000007E # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK = 0x00001F80 # macro +PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK = 0x0007E000 # macro +PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK = 0x00080000 # macro +PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK = 0x00100000 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT = 0x0 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT = 0x4 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT = 0xa # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT = 0x10 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT = 0x16 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT = 0x1e # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK = 0x0000000F # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK = 0x000003F0 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK = 0x0000FC00 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK = 0x003F0000 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK = 0x3FC00000 # macro +PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK = 0xC0000000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT = 0x0 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT = 0x1 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT = 0x7 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT = 0xd # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT = 0x13 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT = 0x19 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK = 0x00000001 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK = 0x0000007E # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK = 0x00001F80 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK = 0x0007E000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK = 0x01F80000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK = 0x7E000000 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT = 0x0 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT = 0x2 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT = 0x4 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT = 0x6 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_32GT__SHIFT = 0x8 # macro +PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT = 0xc # macro +PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT = 0xd # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT = 0x14 # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT = 0x15 # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT = 0x17 # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT = 0x19 # macro +PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT = 0x1a # macro +PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT = 0x1b # macro +PCIE_LC_CNTL6__LC_IGNORE_RETIMER_PRESENCE__SHIFT = 0x1d # macro +PCIE_LC_CNTL6__LC_RETIMER_PRESENCE__SHIFT = 0x1e # macro +PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK = 0x00000003 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK = 0x0000000C # macro +PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK = 0x00000030 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK = 0x000000C0 # macro +PCIE_LC_CNTL6__LC_SPC_MODE_32GT_MASK = 0x00000300 # macro +PCIE_LC_CNTL6__LC_SRIS_EN_MASK = 0x00001000 # macro +PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK = 0x0003E000 # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK = 0x00100000 # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK = 0x00600000 # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK = 0x01800000 # macro +PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK = 0x02000000 # macro +PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK = 0x04000000 # macro +PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_MASK = 0x18000000 # macro +PCIE_LC_CNTL6__LC_IGNORE_RETIMER_PRESENCE_MASK = 0x20000000 # macro +PCIE_LC_CNTL6__LC_RETIMER_PRESENCE_MASK = 0xC0000000 # macro +PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT = 0x0 # macro +PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT = 0x1 # macro +PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT = 0x2 # macro +PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT = 0x3 # macro +PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT = 0x4 # macro +PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT = 0x5 # macro +PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT = 0x6 # macro +PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT = 0x7 # macro +PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT = 0x8 # macro +PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT = 0x9 # macro +PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT = 0xa # macro +PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT = 0xb # macro +PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT = 0xc # macro +PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT = 0xd # macro +PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT = 0x15 # macro +PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT = 0x16 # macro +PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT = 0x17 # macro +PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT = 0x18 # macro +PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT = 0x19 # macro +PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT = 0x1b # macro +PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT = 0x1c # macro +PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT = 0x1d # macro +PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT = 0x1e # macro +PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT = 0x1f # macro +PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK = 0x00000001 # macro +PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK = 0x00000002 # macro +PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK = 0x00000004 # macro +PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK = 0x00000008 # macro +PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK = 0x00000010 # macro +PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK = 0x00000020 # macro +PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK = 0x00000040 # macro +PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK = 0x00000080 # macro +PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK = 0x00000100 # macro +PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK = 0x00000200 # macro +PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK = 0x00000400 # macro +PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK = 0x00000800 # macro +PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK = 0x00001000 # macro +PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK = 0x001FE000 # macro +PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK = 0x00200000 # macro +PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK = 0x00400000 # macro +PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK = 0x00800000 # macro +PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK = 0x01000000 # macro +PCIE_LC_CNTL7__LC_ESM_RATES_MASK = 0x06000000 # macro +PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK = 0x08000000 # macro +PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK = 0x10000000 # macro +PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK = 0x20000000 # macro +PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK = 0x40000000 # macro +PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK = 0x80000000 # macro +PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT = 0x0 # macro +PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT = 0x2 # macro +PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT = 0x4 # macro +PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT = 0x6 # macro +PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT = 0x8 # macro +PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT = 0xb # macro +PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT = 0xc # macro +PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT = 0xd # macro +PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT = 0xe # macro +PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT = 0xf # macro +PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT = 0x10 # macro +PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x13 # macro +PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT = 0x14 # macro +PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT = 0x15 # macro +PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_16GT_DIS__SHIFT = 0x16 # macro +PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_32GT_DIS__SHIFT = 0x17 # macro +PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK = 0x00000003 # macro +PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK = 0x0000000C # macro +PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK = 0x00000030 # macro +PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK = 0x000000C0 # macro +PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK = 0x00000700 # macro +PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK = 0x00000800 # macro +PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK = 0x00001000 # macro +PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK = 0x00002000 # macro +PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK = 0x00004000 # macro +PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK = 0x00008000 # macro +PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK = 0x00070000 # macro +PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00080000 # macro +PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK = 0x00100000 # macro +PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK = 0x00200000 # macro +PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_16GT_DIS_MASK = 0x00400000 # macro +PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_32GT_DIS_MASK = 0x00800000 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT = 0x0 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT = 0x1 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT = 0x2 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT = 0x3 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT = 0x5 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT = 0x6 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT = 0x7 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK = 0x00000001 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK = 0x00000002 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK = 0x00000004 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK = 0x00000018 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK = 0x00000020 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK = 0x00000040 # macro +PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK = 0x00000080 # macro +PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT = 0x0 # macro +PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT = 0x1 # macro +PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT = 0x3 # macro +PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT = 0x4 # macro +PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT = 0x7 # macro +PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK = 0x00000001 # macro +PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK = 0x00000006 # macro +PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK = 0x00000008 # macro +PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK = 0x00000070 # macro +PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK = 0x00000380 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT = 0x0 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT = 0x1 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT = 0x2 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT = 0x3 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT = 0x4 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT = 0x5 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT = 0x6 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT = 0x8 # macro +PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_EN__SHIFT = 0xd # macro +PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_TRIGGER__SHIFT = 0xe # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_BLOCK_EXIT_PG_COMMIT__SHIFT = 0xf # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT = 0x10 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT = 0x14 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT = 0x17 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_WAKE_FROM_ASPM_L1_ON_PM_CONTROL_CLEAR__SHIFT = 0x1a # macro +PCIE_LC_L1_PM_SUBSTATE__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT = 0x1b # macro +PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT = 0x1c # macro +PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT = 0x1d # macro +PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT = 0x1e # macro +PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_USE_PCS_SIDEBAND__SHIFT = 0x1f # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK = 0x00000001 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK = 0x00000002 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK = 0x00000004 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK = 0x00000008 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK = 0x00000010 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK = 0x00000020 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK = 0x000000C0 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK = 0x00001F00 # macro +PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_EN_MASK = 0x00002000 # macro +PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_TRIGGER_MASK = 0x00004000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_BLOCK_EXIT_PG_COMMIT_MASK = 0x00008000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK = 0x00070000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK = 0x00700000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK = 0x03800000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_WAKE_FROM_ASPM_L1_ON_PM_CONTROL_CLEAR_MASK = 0x04000000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK = 0x08000000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_1_ABORT_IN_L1_MASK = 0x10000000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_2_ABORT_IN_L1_MASK = 0x20000000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK = 0x40000000 # macro +PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_USE_PCS_SIDEBAND_MASK = 0x80000000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT = 0x0 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT = 0x8 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_POWERDOWN__SHIFT = 0xe # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_P2_EDGE__SHIFT = 0xf # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT = 0x10 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_POWERDOWN_P2_L1_2_EXIT__SHIFT = 0x1b # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_REFCLK_L1_2_T_POWERON__SHIFT = 0x1c # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT = 0x1d # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT = 0x1e # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT = 0x1f # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK = 0x000000FF # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK = 0x00000700 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_POWERDOWN_MASK = 0x00004000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_P2_EDGE_MASK = 0x00008000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK = 0x03FF0000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_POWERDOWN_P2_L1_2_EXIT_MASK = 0x08000000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_REFCLK_L1_2_T_POWERON_MASK = 0x10000000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK = 0x20000000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK = 0x40000000 # macro +PCIE_LC_L1_PM_SUBSTATE2__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK = 0x80000000 # macro +PCIE_LC_L1_PM_SUBSTATE3__T_POWER_ON_FCH_TARGET_ADDRESS_LO__SHIFT = 0x0 # macro +PCIE_LC_L1_PM_SUBSTATE3__T_POWER_ON_FCH_TARGET_ADDRESS_LO_MASK = 0xFFFFFFFF # macro +PCIE_LC_L1_PM_SUBSTATE4__T_POWER_ON_FCH_TARGET_ADDRESS_HI__SHIFT = 0x0 # macro +PCIE_LC_L1_PM_SUBSTATE4__T_POWER_ON_FCH_TARGET_ADDRESS_HI_MASK = 0xFFFFFFFF # macro +PCIE_LC_L1_PM_SUBSTATE5__T_POWER_ON_FCH_L12_CLKREQ_DELAY__SHIFT = 0x0 # macro +PCIE_LC_L1_PM_SUBSTATE5__LC_BLOCK_EI_L1_REFCLK_OFF__SHIFT = 0x1e # macro +PCIE_LC_L1_PM_SUBSTATE5__LC_IGNORE_ALL_RX_ELEC_IDLE_IN_L1SS__SHIFT = 0x1f # macro +PCIE_LC_L1_PM_SUBSTATE5__T_POWER_ON_FCH_L12_CLKREQ_DELAY_MASK = 0x000000FF # macro +PCIE_LC_L1_PM_SUBSTATE5__LC_BLOCK_EI_L1_REFCLK_OFF_MASK = 0x40000000 # macro +PCIE_LC_L1_PM_SUBSTATE5__LC_IGNORE_ALL_RX_ELEC_IDLE_IN_L1SS_MASK = 0x80000000 # macro +PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT = 0x0 # macro +PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT = 0x8 # macro +PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT = 0x10 # macro +PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK = 0x00000001 # macro +PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK = 0x0000FF00 # macro +PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK = 0xFFFF0000 # macro +PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT = 0x0 # macro +PCIE_LC_CNTL8__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT = 0x2 # macro +PCIE_LC_CNTL8__LC_LOCK_IN_EQ_RESPONSE__SHIFT = 0x3 # macro +PCIE_LC_CNTL8__LC_ESM_RATE0_TIMER_FACTOR__SHIFT = 0x4 # macro +PCIE_LC_CNTL8__LC_ESM_RATE1_TIMER_FACTOR__SHIFT = 0x6 # macro +PCIE_LC_CNTL8__LC_ESM_RATE2_TIMER_FACTOR__SHIFT = 0x8 # macro +PCIE_LC_CNTL8__LC_USC_ACCEPTABLE_PRESETS__SHIFT = 0xa # macro +PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_ON__SHIFT = 0x14 # macro +PCIE_LC_CNTL8__LC_LOOPBACK_EQ_IN_PROGRESS__SHIFT = 0x15 # macro +PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN__SHIFT = 0x16 # macro +PCIE_LC_CNTL8__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN__SHIFT = 0x17 # macro +PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_LANE_UNDER_TEST__SHIFT = 0x18 # macro +PCIE_LC_CNTL8__LC_LOOPBACK_EQ_LANE_UNDER_TEST__SHIFT = 0x1c # macro +PCIE_LC_CNTL8__LC_FOM_TIME_MASK = 0x00000003 # macro +PCIE_LC_CNTL8__LC_EX_SEARCH_TRAVERSAL_MODE_MASK = 0x00000004 # macro +PCIE_LC_CNTL8__LC_LOCK_IN_EQ_RESPONSE_MASK = 0x00000008 # macro +PCIE_LC_CNTL8__LC_ESM_RATE0_TIMER_FACTOR_MASK = 0x00000030 # macro +PCIE_LC_CNTL8__LC_ESM_RATE1_TIMER_FACTOR_MASK = 0x000000C0 # macro +PCIE_LC_CNTL8__LC_ESM_RATE2_TIMER_FACTOR_MASK = 0x00000300 # macro +PCIE_LC_CNTL8__LC_USC_ACCEPTABLE_PRESETS_MASK = 0x000FFC00 # macro +PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_ON_MASK = 0x00100000 # macro +PCIE_LC_CNTL8__LC_LOOPBACK_EQ_IN_PROGRESS_MASK = 0x00200000 # macro +PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_MASK = 0x00400000 # macro +PCIE_LC_CNTL8__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_MASK = 0x00800000 # macro +PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_LANE_UNDER_TEST_MASK = 0x0F000000 # macro +PCIE_LC_CNTL8__LC_LOOPBACK_EQ_LANE_UNDER_TEST_MASK = 0xF0000000 # macro +PCIE_LC_CNTL9__LC_RESET_RCVR_DETECTED_ALL_ARCS__SHIFT = 0x0 # macro +PCIE_LC_CNTL9__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT = 0x1 # macro +PCIE_LC_CNTL9__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT = 0x2 # macro +PCIE_LC_CNTL9__LC_LOOPBACK_EQ_ARC_EN__SHIFT = 0x3 # macro +PCIE_LC_CNTL9__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_EN__SHIFT = 0x4 # macro +PCIE_LC_CNTL9__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT = 0x5 # macro +PCIE_LC_CNTL9__LC_EXT_ASPM_L12_COMMONMODE_COUNT_METHOD__SHIFT = 0x6 # macro +PCIE_LC_CNTL9__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT = 0x7 # macro +PCIE_LC_CNTL9__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT = 0x8 # macro +PCIE_LC_CNTL9__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT = 0x9 # macro +PCIE_LC_CNTL9__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT = 0xa # macro +PCIE_LC_CNTL9__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT = 0xb # macro +PCIE_LC_CNTL9__LC_TRAINING_BITS_REQUIRED__SHIFT = 0xc # macro +PCIE_LC_CNTL9__LC_REPEAT_RXEQEVAL_AFTER_TIMEOUT__SHIFT = 0xe # macro +PCIE_LC_CNTL9__LC_CPM_IDLE_REFCLKREQ_CHECK__SHIFT = 0xf # macro +PCIE_LC_CNTL9__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT = 0x10 # macro +PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT = 0x11 # macro +PCIE_LC_CNTL9__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT = 0x12 # macro +PCIE_LC_CNTL9__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT = 0x13 # macro +PCIE_LC_CNTL9__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT = 0x14 # macro +PCIE_LC_CNTL9__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT = 0x15 # macro +PCIE_LC_CNTL9__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT = 0x16 # macro +PCIE_LC_CNTL9__LC_USE_OLD_PHYSTATUS_FOR_POWERDOWN_INACTIVE__SHIFT = 0x17 # macro +PCIE_LC_CNTL9__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT = 0x18 # macro +PCIE_LC_CNTL9__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT = 0x19 # macro +PCIE_LC_CNTL9__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT = 0x1a # macro +PCIE_LC_CNTL9__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT = 0x1b # macro +PCIE_LC_CNTL9__LC_USE_NEW_EQ_SYMBOL_6_EN__SHIFT = 0x1c # macro +PCIE_LC_CNTL9__LC_DEC_FAILED_SPEED_CHANGE_COUNT_ABORT_BYPASS_TO_HIGH_RATE__SHIFT = 0x1d # macro +PCIE_LC_CNTL9__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT = 0x1e # macro +PCIE_LC_CNTL9__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT = 0x1f # macro +PCIE_LC_CNTL9__LC_RESET_RCVR_DETECTED_ALL_ARCS_MASK = 0x00000001 # macro +PCIE_LC_CNTL9__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK = 0x00000002 # macro +PCIE_LC_CNTL9__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK = 0x00000004 # macro +PCIE_LC_CNTL9__LC_LOOPBACK_EQ_ARC_EN_MASK = 0x00000008 # macro +PCIE_LC_CNTL9__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_EN_MASK = 0x00000010 # macro +PCIE_LC_CNTL9__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK = 0x00000020 # macro +PCIE_LC_CNTL9__LC_EXT_ASPM_L12_COMMONMODE_COUNT_METHOD_MASK = 0x00000040 # macro +PCIE_LC_CNTL9__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK = 0x00000080 # macro +PCIE_LC_CNTL9__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK = 0x00000100 # macro +PCIE_LC_CNTL9__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK = 0x00000200 # macro +PCIE_LC_CNTL9__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK = 0x00000400 # macro +PCIE_LC_CNTL9__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK = 0x00000800 # macro +PCIE_LC_CNTL9__LC_TRAINING_BITS_REQUIRED_MASK = 0x00003000 # macro +PCIE_LC_CNTL9__LC_REPEAT_RXEQEVAL_AFTER_TIMEOUT_MASK = 0x00004000 # macro +PCIE_LC_CNTL9__LC_CPM_IDLE_REFCLKREQ_CHECK_MASK = 0x00008000 # macro +PCIE_LC_CNTL9__LC_REFCLK_OFF_NO_RCVR_LANES_MASK = 0x00010000 # macro +PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK = 0x00020000 # macro +PCIE_LC_CNTL9__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK = 0x00040000 # macro +PCIE_LC_CNTL9__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK = 0x00080000 # macro +PCIE_LC_CNTL9__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK = 0x00100000 # macro +PCIE_LC_CNTL9__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK = 0x00200000 # macro +PCIE_LC_CNTL9__LC_DYN_LANES_L1_SS_POWERDOWN_MASK = 0x00400000 # macro +PCIE_LC_CNTL9__LC_USE_OLD_PHYSTATUS_FOR_POWERDOWN_INACTIVE_MASK = 0x00800000 # macro +PCIE_LC_CNTL9__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK = 0x01000000 # macro +PCIE_LC_CNTL9__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK = 0x02000000 # macro +PCIE_LC_CNTL9__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK = 0x04000000 # macro +PCIE_LC_CNTL9__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK = 0x08000000 # macro +PCIE_LC_CNTL9__LC_USE_NEW_EQ_SYMBOL_6_EN_MASK = 0x10000000 # macro +PCIE_LC_CNTL9__LC_DEC_FAILED_SPEED_CHANGE_COUNT_ABORT_BYPASS_TO_HIGH_RATE_MASK = 0x20000000 # macro +PCIE_LC_CNTL9__LC_CONFIG_WAIT_FOR_EIEOS_MASK = 0x40000000 # macro +PCIE_LC_CNTL9__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK = 0x80000000 # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT = 0x0 # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT = 0x1 # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT = 0x7 # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT = 0xd # macro +PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT = 0x13 # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK = 0x00000001 # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK = 0x0000007E # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK = 0x00001F80 # macro +PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK = 0x0007E000 # macro +PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK = 0x00080000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT = 0x0 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT = 0x1 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT = 0x7 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT = 0xd # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT = 0x13 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT = 0x19 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK = 0x00000001 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK = 0x0000007E # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK = 0x00001F80 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK = 0x0007E000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK = 0x01F80000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK = 0x7E000000 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT = 0x0 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT = 0x1 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LC_PKT_GEN_DYN_CLK_GATING__SHIFT = 0x2 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_DYN_CLK_GATING__SHIFT = 0x3 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LTSSM_DYN_CLK_GATING__SHIFT = 0x4 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK = 0x00000001 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK = 0x00000002 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LC_PKT_GEN_DYN_CLK_GATING_MASK = 0x00000004 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_DYN_CLK_GATING_MASK = 0x00000008 # macro +PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LTSSM_DYN_CLK_GATING_MASK = 0x00000010 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT = 0x0 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT = 0x1 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT = 0x2 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT = 0x3 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT = 0x5 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT = 0x9 # macro +PCIE_LC_CNTL10__LC_USE_PENDING_FOM_SKIP_SECOND_RXEQEVAL__SHIFT = 0xd # macro +PCIE_LC_CNTL10__LC_TIEOFF_PORTS_IGNORE_PHYSTATUS__SHIFT = 0xf # macro +PCIE_LC_CNTL10__LC_CLEAR_CNTL_SKP_SELECT_DATASTREAM_EXIT__SHIFT = 0x10 # macro +PCIE_LC_CNTL10__LC_DEASSERT_REFCLKREQ_IN_L23__SHIFT = 0x11 # macro +PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_L23__SHIFT = 0x12 # macro +PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_NON_SS_L1__SHIFT = 0x13 # macro +PCIE_LC_CNTL10__LC_LSLD_EN__SHIFT = 0x17 # macro +PCIE_LC_CNTL10__LC_LSLD_RATE_REQD__SHIFT = 0x18 # macro +PCIE_LC_CNTL10__LC_LSLD_MODE__SHIFT = 0x1a # macro +PCIE_LC_CNTL10__LC_LSLD_DONE__SHIFT = 0x1b # macro +PCIE_LC_CNTL10__LC_LSLD_TLS_ADVERTISED__SHIFT = 0x1c # macro +PCIE_LC_CNTL10__LC_LSLD_CURRENT_RATE__SHIFT = 0x1e # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK = 0x00000001 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK = 0x00000002 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK = 0x00000004 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK = 0x00000018 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK = 0x000001E0 # macro +PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK = 0x00001E00 # macro +PCIE_LC_CNTL10__LC_USE_PENDING_FOM_SKIP_SECOND_RXEQEVAL_MASK = 0x00002000 # macro +PCIE_LC_CNTL10__LC_TIEOFF_PORTS_IGNORE_PHYSTATUS_MASK = 0x00008000 # macro +PCIE_LC_CNTL10__LC_CLEAR_CNTL_SKP_SELECT_DATASTREAM_EXIT_MASK = 0x00010000 # macro +PCIE_LC_CNTL10__LC_DEASSERT_REFCLKREQ_IN_L23_MASK = 0x00020000 # macro +PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_L23_MASK = 0x00040000 # macro +PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_NON_SS_L1_MASK = 0x00080000 # macro +PCIE_LC_CNTL10__LC_LSLD_EN_MASK = 0x00800000 # macro +PCIE_LC_CNTL10__LC_LSLD_RATE_REQD_MASK = 0x03000000 # macro +PCIE_LC_CNTL10__LC_LSLD_MODE_MASK = 0x04000000 # macro +PCIE_LC_CNTL10__LC_LSLD_DONE_MASK = 0x08000000 # macro +PCIE_LC_CNTL10__LC_LSLD_TLS_ADVERTISED_MASK = 0x30000000 # macro +PCIE_LC_CNTL10__LC_LSLD_CURRENT_RATE_MASK = 0xC0000000 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT = 0x0 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT = 0x1 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT = 0x2 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT = 0xa # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT = 0xb # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT = 0xc # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EQ_SETTINGS_RESTORED__SHIFT = 0xd # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT = 0xe # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT = 0x10 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK = 0x00000001 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK = 0x00000002 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK = 0x000003FC # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK = 0x00000400 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK = 0x00000800 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK = 0x00001000 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EQ_SETTINGS_RESTORED_MASK = 0x00002000 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK = 0x0000C000 # macro +PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK = 0xFFFF0000 # macro +PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT = 0x0 # macro +PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK = 0xFFFFFFFF # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_SUPPORT__SHIFT = 0x0 # macro +PCIE_LC_CNTL11__LC_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT__SHIFT = 0x1 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RESERVED__SHIFT = 0x2 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RCVD__SHIFT = 0x3 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_NEGOTIATED__SHIFT = 0x4 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_FAILURE__SHIFT = 0x5 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_SUPPORT__SHIFT = 0x8 # macro +PCIE_LC_CNTL11__LC_ADVERTISE_NO_EQ_NEEDED_SUPPORT__SHIFT = 0x9 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RESERVED__SHIFT = 0xa # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RCVD__SHIFT = 0xb # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_NEGOTIATED__SHIFT = 0xc # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_FAILURE__SHIFT = 0xd # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_PRESET_SEL__SHIFT = 0xe # macro +PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_SENT__SHIFT = 0xf # macro +PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_RCVD__SHIFT = 0x11 # macro +PCIE_LC_CNTL11__LC_DISABLE_TRAINING_BIT_ARCH_IND__SHIFT = 0x13 # macro +PCIE_LC_CNTL11__LC_SET_TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x18 # macro +PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_REQUEST_RCVD__SHIFT = 0x19 # macro +PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON__SHIFT = 0x1a # macro +PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_RCVD__SHIFT = 0x1b # macro +PCIE_LC_CNTL11__LC_LAST_TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x1c # macro +PCIE_LC_CNTL11__LC_CHECK_TS1_EC_ON_EQ_EXIT__SHIFT = 0x1d # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_SUPPORT_MASK = 0x00000001 # macro +PCIE_LC_CNTL11__LC_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT_MASK = 0x00000002 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RESERVED_MASK = 0x00000004 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RCVD_MASK = 0x00000008 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_NEGOTIATED_MASK = 0x00000010 # macro +PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_FAILURE_MASK = 0x00000020 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_SUPPORT_MASK = 0x00000100 # macro +PCIE_LC_CNTL11__LC_ADVERTISE_NO_EQ_NEEDED_SUPPORT_MASK = 0x00000200 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RESERVED_MASK = 0x00000400 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RCVD_MASK = 0x00000800 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_NEGOTIATED_MASK = 0x00001000 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_FAILURE_MASK = 0x00002000 # macro +PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_PRESET_SEL_MASK = 0x00004000 # macro +PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_SENT_MASK = 0x00018000 # macro +PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_RCVD_MASK = 0x00060000 # macro +PCIE_LC_CNTL11__LC_DISABLE_TRAINING_BIT_ARCH_IND_MASK = 0x00F80000 # macro +PCIE_LC_CNTL11__LC_SET_TRANSMITTER_PRECODE_REQUEST_MASK = 0x01000000 # macro +PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_REQUEST_RCVD_MASK = 0x02000000 # macro +PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_MASK = 0x04000000 # macro +PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_RCVD_MASK = 0x08000000 # macro +PCIE_LC_CNTL11__LC_LAST_TRANSMITTER_PRECODE_REQUEST_MASK = 0x10000000 # macro +PCIE_LC_CNTL11__LC_CHECK_TS1_EC_ON_EQ_EXIT_MASK = 0x20000000 # macro +PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT = 0x0 # macro +PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT = 0x1 # macro +PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT = 0x2 # macro +PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT = 0x3 # macro +PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT = 0x4 # macro +PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT = 0x5 # macro +PCIE_LC_CNTL12__LC_DELAY_PHASE1__SHIFT = 0x6 # macro +PCIE_LC_CNTL12__LC_BLOCKALIGN_IN_L1_ENTRY__SHIFT = 0x8 # macro +PCIE_LC_CNTL12__LC_USE_LEGACY_RXSB1_SPDCHG_ELECIDLE__SHIFT = 0x9 # macro +PCIE_LC_CNTL12__LC_LOCK_REVERSAL_EARLY_CONFIG_COMPLETE__SHIFT = 0xa # macro +PCIE_LC_CNTL12__LC_LOCK_REVERSAL_IMMEDIATE_CONFIG_COMPLETE__SHIFT = 0xb # macro +PCIE_LC_CNTL12__LC_USE_LOOPBACK_INACTIVE_LANES__SHIFT = 0xc # macro +PCIE_LC_CNTL12__LC_LOOPBACK_TEST_MODE_RCVRDET__SHIFT = 0xd # macro +PCIE_LC_CNTL12__LC_LOOPBACK_EQ_LOCK_REVERSAL__SHIFT = 0xe # macro +PCIE_LC_CNTL12__LC_LIVE_DESKEW_MASK_EN__SHIFT = 0x10 # macro +PCIE_LC_CNTL12__LC_LIVE_DESKEW_8B10B_EN__SHIFT = 0x11 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_DATA_UNLOCK__SHIFT = 0x12 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_RECOVER__SHIFT = 0x13 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_ADAPT__SHIFT = 0x14 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_INIT__SHIFT = 0x15 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_EVENT_SEL__SHIFT = 0x16 # macro +PCIE_LC_CNTL12__LC_DEFER_SKIP_INTERVAL_MODE__SHIFT = 0x18 # macro +PCIE_LC_CNTL12__LC_RECOVERY_EQ_WAIT_FOR_PIPE_STOPPED__SHIFT = 0x19 # macro +PCIE_LC_CNTL12__LC_HOLD_TX_STOP_SENDING_PKTS_REPLAY_RETRAIN__SHIFT = 0x1a # macro +PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_SAFERECOVER__SHIFT = 0x1b # macro +PCIE_LC_CNTL12__LC_DSC_INITIATE_EQUALIZATION_OS_BOUNDARY__SHIFT = 0x1c # macro +PCIE_LC_CNTL12__LC_EQ_REQ_PHASE_WAIT_FOR_FINAL_TS1__SHIFT = 0x1d # macro +PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_RXEQEVAL__SHIFT = 0x1e # macro +PCIE_LC_CNTL12__LC_TRACK_RX_WAIT_FOR_TS1__SHIFT = 0x1f # macro +PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK = 0x00000001 # macro +PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK = 0x00000002 # macro +PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK = 0x00000004 # macro +PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK = 0x00000008 # macro +PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK = 0x00000010 # macro +PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK = 0x00000020 # macro +PCIE_LC_CNTL12__LC_DELAY_PHASE1_MASK = 0x000000C0 # macro +PCIE_LC_CNTL12__LC_BLOCKALIGN_IN_L1_ENTRY_MASK = 0x00000100 # macro +PCIE_LC_CNTL12__LC_USE_LEGACY_RXSB1_SPDCHG_ELECIDLE_MASK = 0x00000200 # macro +PCIE_LC_CNTL12__LC_LOCK_REVERSAL_EARLY_CONFIG_COMPLETE_MASK = 0x00000400 # macro +PCIE_LC_CNTL12__LC_LOCK_REVERSAL_IMMEDIATE_CONFIG_COMPLETE_MASK = 0x00000800 # macro +PCIE_LC_CNTL12__LC_USE_LOOPBACK_INACTIVE_LANES_MASK = 0x00001000 # macro +PCIE_LC_CNTL12__LC_LOOPBACK_TEST_MODE_RCVRDET_MASK = 0x00002000 # macro +PCIE_LC_CNTL12__LC_LOOPBACK_EQ_LOCK_REVERSAL_MASK = 0x00004000 # macro +PCIE_LC_CNTL12__LC_LIVE_DESKEW_MASK_EN_MASK = 0x00010000 # macro +PCIE_LC_CNTL12__LC_LIVE_DESKEW_8B10B_EN_MASK = 0x00020000 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_DATA_UNLOCK_MASK = 0x00040000 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_RECOVER_MASK = 0x00080000 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_ADAPT_MASK = 0x00100000 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_INIT_MASK = 0x00200000 # macro +PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_EVENT_SEL_MASK = 0x00C00000 # macro +PCIE_LC_CNTL12__LC_DEFER_SKIP_INTERVAL_MODE_MASK = 0x01000000 # macro +PCIE_LC_CNTL12__LC_RECOVERY_EQ_WAIT_FOR_PIPE_STOPPED_MASK = 0x02000000 # macro +PCIE_LC_CNTL12__LC_HOLD_TX_STOP_SENDING_PKTS_REPLAY_RETRAIN_MASK = 0x04000000 # macro +PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_SAFERECOVER_MASK = 0x08000000 # macro +PCIE_LC_CNTL12__LC_DSC_INITIATE_EQUALIZATION_OS_BOUNDARY_MASK = 0x10000000 # macro +PCIE_LC_CNTL12__LC_EQ_REQ_PHASE_WAIT_FOR_FINAL_TS1_MASK = 0x20000000 # macro +PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_RXEQEVAL_MASK = 0x40000000 # macro +PCIE_LC_CNTL12__LC_TRACK_RX_WAIT_FOR_TS1_MASK = 0x80000000 # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT = 0x0 # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT = 0x1 # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT = 0x2 # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT = 0x3 # macro +PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT = 0x4 # macro +PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT = 0x5 # macro +PCIE_LC_SPEED_CNTL2__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT = 0x6 # macro +PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_STATUS__SHIFT = 0x7 # macro +PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT = 0x8 # macro +PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT = 0xa # macro +PCIE_LC_SPEED_CNTL2__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT = 0xb # macro +PCIE_LC_SPEED_CNTL2__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT = 0xc # macro +PCIE_LC_SPEED_CNTL2__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT = 0xd # macro +PCIE_LC_SPEED_CNTL2__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT = 0xe # macro +PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_AFTER_FAILED_EQ__SHIFT = 0xf # macro +PCIE_LC_SPEED_CNTL2__LC_ENFORCE_CORRECT_SPEED_FOR_EQ__SHIFT = 0x10 # macro +PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SOFTWARE_PERFORM_EQ__SHIFT = 0x11 # macro +PCIE_LC_SPEED_CNTL2__LC_SEND_EQ_TS2_IF_OTHER_SIDE_EVER_ADVERTISED_SPEED__SHIFT = 0x12 # macro +PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SINGLE_EQ_PER_RECOVERY__SHIFT = 0x13 # macro +PCIE_LC_SPEED_CNTL2__LC_USE_LEGACY_CLEAR_DELAY_DLLPs__SHIFT = 0x14 # macro +PCIE_LC_SPEED_CNTL2__LC_DEFER_RETRAIN_LINK_UNTIL_EXIT_RECOVERY__SHIFT = 0x15 # macro +PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_ON_FAIL_SPEED_CHANGE_LIMIT__SHIFT = 0x16 # macro +PCIE_LC_SPEED_CNTL2__LC_DEFER_PRIVATE_SPEED_CHANGE_UNTIL_EXIT_RECOVERY__SHIFT = 0x17 # macro +PCIE_LC_SPEED_CNTL2__LC_DONT_UPDATE_GEN_SUPPORT_MID_RECOVERY__SHIFT = 0x19 # macro +PCIE_LC_SPEED_CNTL2__LC_ALLOW_SET_INITIATE_SPEED_CHANGE_IN_RECOVERY_LOCK__SHIFT = 0x1a # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_SW_SPEED_CHANGE_MASK = 0x00000001 # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK = 0x00000002 # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_HW_SPEED_CHANGE_MASK = 0x00000004 # macro +PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK = 0x00000008 # macro +PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK = 0x00000010 # macro +PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L1_EN_MASK = 0x00000020 # macro +PCIE_LC_SPEED_CNTL2__LC_INITIATE_LINK_SPEED_CHANGE_MASK = 0x00000040 # macro +PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_STATUS_MASK = 0x00000080 # macro +PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK = 0x00000300 # macro +PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK = 0x00000400 # macro +PCIE_LC_SPEED_CNTL2__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK = 0x00000800 # macro +PCIE_LC_SPEED_CNTL2__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK = 0x00001000 # macro +PCIE_LC_SPEED_CNTL2__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK = 0x00002000 # macro +PCIE_LC_SPEED_CNTL2__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK = 0x00004000 # macro +PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_AFTER_FAILED_EQ_MASK = 0x00008000 # macro +PCIE_LC_SPEED_CNTL2__LC_ENFORCE_CORRECT_SPEED_FOR_EQ_MASK = 0x00010000 # macro +PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SOFTWARE_PERFORM_EQ_MASK = 0x00020000 # macro +PCIE_LC_SPEED_CNTL2__LC_SEND_EQ_TS2_IF_OTHER_SIDE_EVER_ADVERTISED_SPEED_MASK = 0x00040000 # macro +PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SINGLE_EQ_PER_RECOVERY_MASK = 0x00080000 # macro +PCIE_LC_SPEED_CNTL2__LC_USE_LEGACY_CLEAR_DELAY_DLLPs_MASK = 0x00100000 # macro +PCIE_LC_SPEED_CNTL2__LC_DEFER_RETRAIN_LINK_UNTIL_EXIT_RECOVERY_MASK = 0x00200000 # macro +PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_ON_FAIL_SPEED_CHANGE_LIMIT_MASK = 0x00400000 # macro +PCIE_LC_SPEED_CNTL2__LC_DEFER_PRIVATE_SPEED_CHANGE_UNTIL_EXIT_RECOVERY_MASK = 0x01800000 # macro +PCIE_LC_SPEED_CNTL2__LC_DONT_UPDATE_GEN_SUPPORT_MID_RECOVERY_MASK = 0x02000000 # macro +PCIE_LC_SPEED_CNTL2__LC_ALLOW_SET_INITIATE_SPEED_CHANGE_IN_RECOVERY_LOCK_MASK = 0x04000000 # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_COEFF_32GT__SHIFT = 0x0 # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_PRE_CURSOR_32GT__SHIFT = 0x1 # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_CURSOR_32GT__SHIFT = 0x7 # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_POST_CURSOR_32GT__SHIFT = 0xd # macro +PCIE_LC_FORCE_COEFF3__LC_3X3_COEFF_SEARCH_EN_32GT__SHIFT = 0x13 # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_COEFF_32GT_MASK = 0x00000001 # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_PRE_CURSOR_32GT_MASK = 0x0000007E # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_CURSOR_32GT_MASK = 0x00001F80 # macro +PCIE_LC_FORCE_COEFF3__LC_FORCE_POST_CURSOR_32GT_MASK = 0x0007E000 # macro +PCIE_LC_FORCE_COEFF3__LC_3X3_COEFF_SEARCH_EN_32GT_MASK = 0x00080000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_32GT__SHIFT = 0x0 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_PRE_CURSOR_REQ_32GT__SHIFT = 0x1 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_CURSOR_REQ_32GT__SHIFT = 0x7 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_POST_CURSOR_REQ_32GT__SHIFT = 0xd # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FS_OTHER_END_32GT__SHIFT = 0x13 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_LF_OTHER_END_32GT__SHIFT = 0x19 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_32GT_MASK = 0x00000001 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_PRE_CURSOR_REQ_32GT_MASK = 0x0000007E # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_CURSOR_REQ_32GT_MASK = 0x00001F80 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_POST_CURSOR_REQ_32GT_MASK = 0x0007E000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FS_OTHER_END_32GT_MASK = 0x01F80000 # macro +PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_LF_OTHER_END_32GT_MASK = 0x7E000000 # macro +PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT = 0x0 # macro +PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT = 0x10 # macro +PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK = 0x00000FFF # macro +PCIE_TX_SEQ__TX_ACKD_SEQ_MASK = 0x0FFF0000 # macro +PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT = 0x0 # macro +PCIE_TX_REPLAY__TX_REPLAY_ROLLOVER_EN__SHIFT = 0x5 # macro +PCIE_TX_REPLAY__TX_REPLAY_STALL__SHIFT = 0xa # macro +PCIE_TX_REPLAY__TX_REPLAY_DISABLE__SHIFT = 0xb # macro +PCIE_TX_REPLAY__TX_REPLAY_ALL__SHIFT = 0xc # macro +PCIE_TX_REPLAY__TX_REPLAY_FORCE_WRSCH_ACK__SHIFT = 0xd # macro +PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT = 0xe # macro +PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT = 0xf # macro +PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT = 0x10 # macro +PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK = 0x0000001F # macro +PCIE_TX_REPLAY__TX_REPLAY_ROLLOVER_EN_MASK = 0x00000020 # macro +PCIE_TX_REPLAY__TX_REPLAY_STALL_MASK = 0x00000400 # macro +PCIE_TX_REPLAY__TX_REPLAY_DISABLE_MASK = 0x00000800 # macro +PCIE_TX_REPLAY__TX_REPLAY_ALL_MASK = 0x00001000 # macro +PCIE_TX_REPLAY__TX_REPLAY_FORCE_WRSCH_ACK_MASK = 0x00002000 # macro +PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK = 0x00004000 # macro +PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK = 0x00008000 # macro +PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK = 0xFFFF0000 # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT = 0x0 # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT = 0xc # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_FC_ARB_ENABLE__SHIFT = 0xd # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_SCALE__SHIFT = 0x14 # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_ADJUSTMENT__SHIFT = 0x18 # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK = 0x00000FFF # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK = 0x00001000 # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_FC_ARB_ENABLE_MASK = 0x00002000 # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_SCALE_MASK = 0x00F00000 # macro +PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_ADJUSTMENT_MASK = 0xFF000000 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT = 0x4 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT = 0x8 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT = 0x14 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT = 0x18 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK = 0x00000007 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK = 0x00000070 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK = 0x00000700 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK = 0x00070000 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK = 0x00700000 # macro +PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK = 0x07000000 # macro +PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT = 0x0 # macro +PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT = 0x18 # macro +PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK = 0x00FFFFFF # macro +PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK = 0x01000000 # macro +PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT = 0x0 # macro +PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT = 0x18 # macro +PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK = 0x00FFFFFF # macro +PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK = 0x01000000 # macro +PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT = 0x18 # macro +PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT = 0x1e # macro +PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT = 0x1f # macro +PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK = 0x3F000000 # macro +PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK = 0x40000000 # macro +PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK = 0x80000000 # macro +PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK = 0x00003FFF # macro +PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK = 0x03FF0000 # macro +PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK = 0x00003FFF # macro +PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK = 0x03FF0000 # macro +PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK = 0x00003FFF # macro +PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK = 0x03FF0000 # macro +PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK = 0x00000FFF # macro +PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK = 0x00FF0000 # macro +PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK = 0x00000FFF # macro +PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK = 0x00FF0000 # macro +PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK = 0x00000FFF # macro +PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK = 0x00FF0000 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT = 0x0 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT = 0x1 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT = 0x2 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT = 0x3 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT = 0x4 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT = 0x5 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT = 0x10 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT = 0x11 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT = 0x12 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT = 0x13 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT = 0x14 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT = 0x15 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK = 0x00000001 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK = 0x00000002 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK = 0x00000004 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK = 0x00000008 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK = 0x00000010 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK = 0x00000020 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK = 0x00010000 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK = 0x00020000 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK = 0x00040000 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK = 0x00080000 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK = 0x00100000 # macro +PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK = 0x00200000 # macro +PCIE_FC_P__PD_CREDITS__SHIFT = 0x0 # macro +PCIE_FC_P__PH_CREDITS__SHIFT = 0x10 # macro +PCIE_FC_P__PD_CREDITS_MASK = 0x0000FFFF # macro +PCIE_FC_P__PH_CREDITS_MASK = 0x0FFF0000 # macro +PCIE_FC_NP__NPD_CREDITS__SHIFT = 0x0 # macro +PCIE_FC_NP__NPH_CREDITS__SHIFT = 0x10 # macro +PCIE_FC_NP__NPD_CREDITS_MASK = 0x0000FFFF # macro +PCIE_FC_NP__NPH_CREDITS_MASK = 0x0FFF0000 # macro +PCIE_FC_CPL__CPLD_CREDITS__SHIFT = 0x0 # macro +PCIE_FC_CPL__CPLH_CREDITS__SHIFT = 0x10 # macro +PCIE_FC_CPL__CPLD_CREDITS_MASK = 0x0000FFFF # macro +PCIE_FC_CPL__CPLH_CREDITS_MASK = 0x0FFF0000 # macro +PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT = 0x0 # macro +PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT = 0x10 # macro +PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK = 0x0000FFFF # macro +PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK = 0x0FFF0000 # macro +PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT = 0x0 # macro +PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT = 0x10 # macro +PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK = 0x0000FFFF # macro +PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK = 0x0FFF0000 # macro +PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT = 0x0 # macro +PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT = 0x10 # macro +PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK = 0x0000FFFF # macro +PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK = 0x0FFF0000 # macro +PCIE_RESERVED__RESERVED__SHIFT = 0x0 # macro +PCIE_RESERVED__RESERVED_MASK = 0xFFFFFFFF # macro +PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT = 0x0 # macro +PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK = 0xFFFFFFFF # macro +PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT = 0x0 # macro +PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK = 0xFFFFFFFF # macro +PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT = 0x1 # macro +PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT = 0x9 # macro +PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT = 0xa # macro +PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT = 0xf # macro +PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT = 0x10 # macro +PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT = 0x11 # macro +PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT = 0x12 # macro +PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT = 0x13 # macro +PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT = 0x14 # macro +PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT = 0x15 # macro +PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT = 0x16 # macro +PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT = 0x17 # macro +PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT = 0x1f # macro +PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK = 0x0000000E # macro +PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK = 0x00000200 # macro +PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK = 0x00001C00 # macro +PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK = 0x00008000 # macro +PCIE_CNTL__RX_RCB_REORDER_EN_MASK = 0x00010000 # macro +PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK = 0x00020000 # macro +PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK = 0x00040000 # macro +PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK = 0x00080000 # macro +PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK = 0x00100000 # macro +PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK = 0x00200000 # macro +PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK = 0x00400000 # macro +PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK = 0x00800000 # macro +PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK = 0x80000000 # macro +PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT = 0x0 # macro +PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK = 0x0000000F # macro +PCIE_RX_CNTL5__RX_SB_ARB_MODE__SHIFT = 0x0 # macro +PCIE_RX_CNTL5__RX_SB_ARB_LOWER_LIMIT__SHIFT = 0x8 # macro +PCIE_RX_CNTL5__RX_SB_ARB_UPPER_LIMIT__SHIFT = 0x10 # macro +PCIE_RX_CNTL5__RX_SB_ARB_MODE_MASK = 0x00000003 # macro +PCIE_RX_CNTL5__RX_SB_ARB_LOWER_LIMIT_MASK = 0x00003F00 # macro +PCIE_RX_CNTL5__RX_SB_ARB_UPPER_LIMIT_MASK = 0x003F0000 # macro +PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_TPH_DIS__SHIFT = 0x0 # macro +PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE4_DIS__SHIFT = 0x1 # macro +PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE1_E_F_DIS__SHIFT = 0x2 # macro +PCIE_RX_CNTL4__CI_ATS_RO_DIS__SHIFT = 0x3 # macro +PCIE_RX_CNTL4__RX_CTO_CPL_REFCLK_SPEED__SHIFT = 0x8 # macro +PCIE_RX_CNTL4__RX_OVERFLOW_PRIV_MASK__SHIFT = 0xa # macro +PCIE_RX_CNTL4__RX_PD_OVERFLOW_FIX_DISABLE__SHIFT = 0x10 # macro +PCIE_RX_CNTL4__RX_NAK_COUNTER_MODE__SHIFT = 0x11 # macro +PCIE_RX_CNTL4__RX_SF_FILTERING_END_FROM_DLLP_DIS__SHIFT = 0x12 # macro +PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_TPH_DIS_MASK = 0x00000001 # macro +PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE4_DIS_MASK = 0x00000002 # macro +PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE1_E_F_DIS_MASK = 0x00000004 # macro +PCIE_RX_CNTL4__CI_ATS_RO_DIS_MASK = 0x00000008 # macro +PCIE_RX_CNTL4__RX_CTO_CPL_REFCLK_SPEED_MASK = 0x00000300 # macro +PCIE_RX_CNTL4__RX_OVERFLOW_PRIV_MASK_MASK = 0x0000FC00 # macro +PCIE_RX_CNTL4__RX_PD_OVERFLOW_FIX_DISABLE_MASK = 0x00010000 # macro +PCIE_RX_CNTL4__RX_NAK_COUNTER_MODE_MASK = 0x00020000 # macro +PCIE_RX_CNTL4__RX_SF_FILTERING_END_FROM_DLLP_DIS_MASK = 0x00040000 # macro +PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC__SHIFT = 0x0 # macro +PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC_MASK = 0x000000FF # macro +PCIE_CNTL2__RCB_LS_EN__SHIFT = 0x0 # macro +PCIE_CNTL2__MST_CPL_LS_EN__SHIFT = 0x1 # macro +PCIE_CNTL2__SLVAER_LS_EN__SHIFT = 0x2 # macro +PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT = 0x10 # macro +PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT = 0x11 # macro +PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT = 0x14 # macro +PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT = 0x15 # macro +PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT = 0x18 # macro +PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT = 0x1d # macro +PCIE_CNTL2__RCB_LS_EN_MASK = 0x00000001 # macro +PCIE_CNTL2__MST_CPL_LS_EN_MASK = 0x00000002 # macro +PCIE_CNTL2__SLVAER_LS_EN_MASK = 0x00000004 # macro +PCIE_CNTL2__SLV_MEM_LS_EN_MASK = 0x00010000 # macro +PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK = 0x00020000 # macro +PCIE_CNTL2__SLV_MEM_SD_EN_MASK = 0x00100000 # macro +PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK = 0x00200000 # macro +PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK = 0x1F000000 # macro +PCIE_CNTL2__SLV_MEM_DS_EN_MASK = 0x20000000 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT = 0x1 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT = 0x2 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT = 0x3 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT = 0x4 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT = 0x5 # macro +PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT = 0x8 # macro +PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT = 0x9 # macro +PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT = 0xc # macro +PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT = 0xd # macro +PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT = 0xe # macro +PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT = 0x10 # macro +PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK = 0x00000002 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK = 0x00000004 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK = 0x00000008 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK = 0x00000010 # macro +PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK = 0x00000020 # macro +PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK = 0x00000100 # macro +PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK = 0x00000E00 # macro +PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK = 0x00001000 # macro +PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK = 0x00002000 # macro +PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK = 0x00004000 # macro +PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK = 0x03FF0000 # macro +PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +PCIE_CI_CNTL__CI_SLV_SDP_CHAIN_DIS__SHIFT = 0x0 # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT = 0x3 # macro +PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT = 0x6 # macro +PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT = 0x8 # macro +PCIE_CI_CNTL__CI_SLV_SDP_MEM_WR_FULL_DIS__SHIFT = 0x9 # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT = 0xa # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT = 0xb # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT = 0xc # macro +PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT = 0x10 # macro +PCIE_CI_CNTL__TX_PGMEM_CTRL_PGATE_DIS__SHIFT = 0x15 # macro +PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT = 0x16 # macro +PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT = 0x17 # macro +PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT = 0x18 # macro +PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT = 0x1d # macro +PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT = 0x1e # macro +PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT = 0x1f # macro +PCIE_CI_CNTL__CI_SLV_SDP_CHAIN_DIS_MASK = 0x00000001 # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK = 0x00000038 # macro +PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK = 0x000000C0 # macro +PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK = 0x00000100 # macro +PCIE_CI_CNTL__CI_SLV_SDP_MEM_WR_FULL_DIS_MASK = 0x00000200 # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK = 0x00000400 # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK = 0x00000800 # macro +PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK = 0x00001000 # macro +PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK = 0x00010000 # macro +PCIE_CI_CNTL__TX_PGMEM_CTRL_PGATE_DIS_MASK = 0x00200000 # macro +PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK = 0x00400000 # macro +PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK = 0x00800000 # macro +PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK = 0x01000000 # macro +PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK = 0x20000000 # macro +PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK = 0x40000000 # macro +PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK = 0x80000000 # macro +PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT = 0x6 # macro +PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT = 0xc # macro +PCIE_BUS_CNTL__PMI_INT_DIS_MASK = 0x00000040 # macro +PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK = 0x00001000 # macro +PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT = 0x0 # macro +PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT = 0x8 # macro +PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT = 0x10 # macro +PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT = 0x18 # macro +PCIE_LC_STATE6__LC_PREV_STATE24_MASK = 0x0000003F # macro +PCIE_LC_STATE6__LC_PREV_STATE25_MASK = 0x00003F00 # macro +PCIE_LC_STATE6__LC_PREV_STATE26_MASK = 0x003F0000 # macro +PCIE_LC_STATE6__LC_PREV_STATE27_MASK = 0x3F000000 # macro +PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT = 0x0 # macro +PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT = 0x8 # macro +PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT = 0x10 # macro +PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT = 0x18 # macro +PCIE_LC_STATE7__LC_PREV_STATE28_MASK = 0x0000003F # macro +PCIE_LC_STATE7__LC_PREV_STATE29_MASK = 0x00003F00 # macro +PCIE_LC_STATE7__LC_PREV_STATE30_MASK = 0x003F0000 # macro +PCIE_LC_STATE7__LC_PREV_STATE31_MASK = 0x3F000000 # macro +PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT = 0x0 # macro +PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT = 0x8 # macro +PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT = 0x10 # macro +PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT = 0x18 # macro +PCIE_LC_STATE8__LC_PREV_STATE32_MASK = 0x0000003F # macro +PCIE_LC_STATE8__LC_PREV_STATE33_MASK = 0x00003F00 # macro +PCIE_LC_STATE8__LC_PREV_STATE34_MASK = 0x003F0000 # macro +PCIE_LC_STATE8__LC_PREV_STATE35_MASK = 0x3F000000 # macro +PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT = 0x0 # macro +PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT = 0x8 # macro +PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT = 0x10 # macro +PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT = 0x18 # macro +PCIE_LC_STATE9__LC_PREV_STATE36_MASK = 0x0000003F # macro +PCIE_LC_STATE9__LC_PREV_STATE37_MASK = 0x00003F00 # macro +PCIE_LC_STATE9__LC_PREV_STATE38_MASK = 0x003F0000 # macro +PCIE_LC_STATE9__LC_PREV_STATE39_MASK = 0x3F000000 # macro +PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT = 0x0 # macro +PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT = 0x8 # macro +PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT = 0x10 # macro +PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT = 0x18 # macro +PCIE_LC_STATE10__LC_PREV_STATE40_MASK = 0x0000003F # macro +PCIE_LC_STATE10__LC_PREV_STATE41_MASK = 0x00003F00 # macro +PCIE_LC_STATE10__LC_PREV_STATE42_MASK = 0x003F0000 # macro +PCIE_LC_STATE10__LC_PREV_STATE43_MASK = 0x3F000000 # macro +PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT = 0x0 # macro +PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT = 0x8 # macro +PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT = 0x10 # macro +PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT = 0x18 # macro +PCIE_LC_STATE11__LC_PREV_STATE44_MASK = 0x0000003F # macro +PCIE_LC_STATE11__LC_PREV_STATE45_MASK = 0x00003F00 # macro +PCIE_LC_STATE11__LC_PREV_STATE46_MASK = 0x003F0000 # macro +PCIE_LC_STATE11__LC_PREV_STATE47_MASK = 0x3F000000 # macro +PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT = 0x0 # macro +PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT = 0x1 # macro +PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT = 0x2 # macro +PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT = 0x5 # macro +PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK = 0x00000001 # macro +PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK = 0x00000002 # macro +PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK = 0x0000001C # macro +PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK = 0x000000E0 # macro +PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT = 0x0 # macro +PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT = 0x10 # macro +PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK = 0x0000FFFF # macro +PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK = 0xFFFF0000 # macro +PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT = 0x0 # macro +PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT = 0x1 # macro +PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT = 0x2 # macro +PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT = 0x3 # macro +PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT = 0x4 # macro +PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT = 0x5 # macro +PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT = 0x6 # macro +PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK = 0x00000001 # macro +PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK = 0x00000002 # macro +PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK = 0x00000004 # macro +PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK = 0x00000008 # macro +PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK = 0x00000010 # macro +PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK = 0x00000020 # macro +PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK = 0x00000040 # macro +PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT = 0x0 # macro +PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK = 0xFFFFFFFF # macro +PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT = 0x0 # macro +PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK = 0xFFFFFFFF # macro +PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT = 0x0 # macro +PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK = 0xFFFFFFFF # macro +PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT = 0x0 # macro +PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK = 0xFFFFFFFF # macro +PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT = 0x0 # macro +PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK = 0x0001FFFF # macro +PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT = 0x0 # macro +PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK = 0xFFFFFFFF # macro +PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT = 0x0 # macro +PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT = 0x4 # macro +PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT = 0x8 # macro +PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT = 0xc # macro +PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT = 0x10 # macro +PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT = 0x14 # macro +PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT = 0x18 # macro +PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT = 0x1c # macro +PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK = 0x0000000F # macro +PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK = 0x000000F0 # macro +PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK = 0x00000F00 # macro +PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK = 0x0000F000 # macro +PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK = 0x000F0000 # macro +PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK = 0x00F00000 # macro +PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK = 0x0F000000 # macro +PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK = 0xF0000000 # macro +PCIE_LC_PM_CNTL2__LC_PORT_8_CLKREQB_MAP__SHIFT = 0x0 # macro +PCIE_LC_PM_CNTL2__LC_PORT_8_CLKREQB_MAP_MASK = 0x0000000F # macro +PCIE_P_CNTL__P_PWRDN_EN__SHIFT = 0x0 # macro +PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT = 0x1 # macro +PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT = 0x4 # macro +PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT = 0x5 # macro +PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT = 0x6 # macro +PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT = 0x7 # macro +PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT = 0x8 # macro +PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT = 0xc # macro +PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT = 0xd # macro +PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT = 0xe # macro +PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT = 0x11 # macro +PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT = 0x12 # macro +PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT = 0x13 # macro +PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT = 0x17 # macro +PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT = 0x18 # macro +PCIE_P_CNTL__LC_FILTER_SKP_FROM_L_IDLE__SHIFT = 0x19 # macro +PCIE_P_CNTL__LC_TIEOFF_LANES_IGNORE_REFCLKACK__SHIFT = 0x1a # macro +PCIE_P_CNTL__LC_MISSING_COM_RESET_SET_TRACK__SHIFT = 0x1b # macro +PCIE_P_CNTL__LC_RESET_TRACK_TSX_COUNTER_NO_DATA_VLD__SHIFT = 0x1c # macro +PCIE_P_CNTL__P_PWRDN_EN_MASK = 0x00000001 # macro +PCIE_P_CNTL__P_SYMALIGN_MODE_MASK = 0x00000002 # macro +PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK = 0x00000010 # macro +PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK = 0x00000020 # macro +PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK = 0x00000040 # macro +PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK = 0x00000080 # macro +PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK = 0x00000100 # macro +PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK = 0x00001000 # macro +PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK = 0x00002000 # macro +PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK = 0x0000C000 # macro +PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK = 0x00020000 # macro +PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK = 0x00040000 # macro +PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK = 0x00780000 # macro +PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK = 0x00800000 # macro +PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK = 0x01000000 # macro +PCIE_P_CNTL__LC_FILTER_SKP_FROM_L_IDLE_MASK = 0x02000000 # macro +PCIE_P_CNTL__LC_TIEOFF_LANES_IGNORE_REFCLKACK_MASK = 0x04000000 # macro +PCIE_P_CNTL__LC_MISSING_COM_RESET_SET_TRACK_MASK = 0x08000000 # macro +PCIE_P_CNTL__LC_RESET_TRACK_TSX_COUNTER_NO_DATA_VLD_MASK = 0x70000000 # macro +PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT = 0x0 # macro +PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT = 0x10 # macro +PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK = 0x0000FFFF # macro +PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK = 0xFFFF0000 # macro +PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT = 0x0 # macro +PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK = 0x0000FFFF # macro +PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT = 0x0 # macro +PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT = 0x10 # macro +PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK = 0x000001FF # macro +PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK = 0xFFFF0000 # macro +PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT = 0x0 # macro +PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT = 0x8 # macro +PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK = 0x000000FF # macro +PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK = 0x0000FF00 # macro +PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT = 0x0 # macro +PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT = 0x1 # macro +PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT = 0x2 # macro +PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT = 0x3 # macro +PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT = 0x4 # macro +PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT = 0x5 # macro +PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT = 0x8 # macro +PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT = 0x9 # macro +PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT = 0xa # macro +PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT = 0xb # macro +PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT = 0xc # macro +PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT = 0xd # macro +PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT = 0xe # macro +PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT = 0xf # macro +PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT = 0x10 # macro +PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT = 0x11 # macro +PCIE_RX_AD__RX_RC_LARGE_VDM_BFRC_EN__SHIFT = 0x12 # macro +PCIE_RX_AD__RC_IGNORE_ACS_ERR_ON_DRS_DIS__SHIFT = 0x13 # macro +PCIE_RX_AD__RX_SWUS_IGNORE_ROUTING_ON_VDM_EN__SHIFT = 0x14 # macro +PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK = 0x00000001 # macro +PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK = 0x00000002 # macro +PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK = 0x00000004 # macro +PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK = 0x00000008 # macro +PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK = 0x00000010 # macro +PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK = 0x00000020 # macro +PCIE_RX_AD__RX_RC_DROP_VDM0_MASK = 0x00000100 # macro +PCIE_RX_AD__RX_RC_UR_VDM0_MASK = 0x00000200 # macro +PCIE_RX_AD__RX_RC_DROP_VDM1_MASK = 0x00000400 # macro +PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK = 0x00000800 # macro +PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK = 0x00001000 # macro +PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK = 0x00002000 # macro +PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK = 0x00004000 # macro +PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK = 0x00008000 # macro +PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK = 0x00010000 # macro +PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK = 0x00020000 # macro +PCIE_RX_AD__RX_RC_LARGE_VDM_BFRC_EN_MASK = 0x00040000 # macro +PCIE_RX_AD__RC_IGNORE_ACS_ERR_ON_DRS_DIS_MASK = 0x00080000 # macro +PCIE_RX_AD__RX_SWUS_IGNORE_ROUTING_ON_VDM_EN_MASK = 0x00100000 # macro +PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT = 0x0 # macro +PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT = 0x4 # macro +PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT = 0x5 # macro +PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT = 0x9 # macro +PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT = 0xa # macro +PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT = 0xb # macro +PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT = 0xc # macro +PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT = 0xf # macro +PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT = 0x10 # macro +PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT = 0x11 # macro +PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT = 0x12 # macro +PCIE_SDP_CTRL__CI_SLV_SDP_PARITY_CHECK_EN__SHIFT = 0x13 # macro +PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT = 0x19 # macro +PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT = 0x1a # macro +PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN__SHIFT = 0x1d # macro +PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_BIT46_EN__SHIFT = 0x1e # macro +PCIE_SDP_CTRL__SDP_UNIT_ID_MASK = 0x0000000F # macro +PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK = 0x00000010 # macro +PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK = 0x00000020 # macro +PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK = 0x00000200 # macro +PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK = 0x00000400 # macro +PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK = 0x00000800 # macro +PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK = 0x00001000 # macro +PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK = 0x00008000 # macro +PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK = 0x00010000 # macro +PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK = 0x00020000 # macro +PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK = 0x00040000 # macro +PCIE_SDP_CTRL__CI_SLV_SDP_PARITY_CHECK_EN_MASK = 0x00080000 # macro +PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK = 0x02000000 # macro +PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK = 0x1C000000 # macro +PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN_MASK = 0x20000000 # macro +PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_BIT46_EN_MASK = 0x40000000 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT = 0x0 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT = 0x2 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT = 0x4 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT = 0x6 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT = 0x8 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT = 0xa # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT = 0xc # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT = 0xe # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT = 0x10 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK = 0x00000003 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK = 0x0000000C # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK = 0x00000030 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK = 0x000000C0 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK = 0x00000300 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK = 0x00000C00 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK = 0x00003000 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK = 0x0000C000 # macro +PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK = 0x00030000 # macro +PCIE_SDP_CTRL2__CI_VIRTUAL_WIRE_DIS__SHIFT = 0x0 # macro +PCIE_SDP_CTRL2__CI_VIRTUAL_WIRE_DIS_MASK = 0x00000001 # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT = 0x0 # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT = 0x1 # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT = 0x2 # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_LCLK_STATUS__SHIFT = 0x1f # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK = 0x00000001 # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK = 0x00000002 # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK = 0x00000004 # macro +PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_LCLK_STATUS_MASK = 0x80000000 # macro +PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK1__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK1__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK1__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK1__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK2__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK2__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK2__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK2__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK3__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK3__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK3__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK3__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK4__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK4__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK4__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK4__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT = 0x4 # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT = 0xc # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK = 0x0000000F # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK = 0x000000F0 # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK = 0x00000F00 # macro +PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK = 0x0000F000 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT = 0x4 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT = 0xc # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK1__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK1__SHIFT = 0x14 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK2__SHIFT = 0x18 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK2__SHIFT = 0x1c # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK = 0x0000000F # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK = 0x000000F0 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK = 0x00000F00 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK = 0x0000F000 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK1_MASK = 0x000F0000 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK1_MASK = 0x00F00000 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK2_MASK = 0x0F000000 # macro +PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK2_MASK = 0xF0000000 # macro +PCIE_PERF_CNTL_TXCLK5__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK5__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK5__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK5__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK5__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK5__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK5__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK5__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK5__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK5__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK5__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK5__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_TXCLK6__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK6__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK6__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK6__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK6__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK6__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK6__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK6__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK6__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK6__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK6__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK6__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT = 0x1 # macro +PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT = 0x2 # macro +PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT = 0x3 # macro +PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT = 0x4 # macro +PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT = 0x5 # macro +PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT = 0x6 # macro +PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT = 0x7 # macro +PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT = 0x8 # macro +PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT = 0x9 # macro +PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT = 0xa # macro +PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT = 0xb # macro +PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT = 0xc # macro +PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT = 0xd # macro +PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT = 0xe # macro +PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT = 0xf # macro +PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT = 0x10 # macro +PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT = 0x12 # macro +PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT = 0x13 # macro +PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT = 0x14 # macro +PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT = 0x18 # macro +PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT = 0x1b # macro +PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1c # macro +PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT = 0x1d # macro +PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT = 0x1e # macro +PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT = 0x1f # macro +PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK = 0x00000002 # macro +PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK = 0x00000004 # macro +PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK = 0x00000008 # macro +PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK = 0x00000010 # macro +PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK = 0x00000020 # macro +PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK = 0x00000040 # macro +PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK = 0x00000080 # macro +PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK = 0x00000100 # macro +PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK = 0x00000200 # macro +PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK = 0x00000400 # macro +PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK = 0x00000800 # macro +PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK = 0x00001000 # macro +PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK = 0x00002000 # macro +PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK = 0x00004000 # macro +PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK = 0x00008000 # macro +PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK = 0x00010000 # macro +PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK = 0x00040000 # macro +PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK = 0x00080000 # macro +PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK = 0x00100000 # macro +PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK = 0x07000000 # macro +PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK = 0x08000000 # macro +PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK = 0x10000000 # macro +PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK = 0x20000000 # macro +PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK = 0x40000000 # macro +PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK = 0x80000000 # macro +PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT = 0x0 # macro +PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT = 0x1 # macro +PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT = 0x2 # macro +PCIE_STRAP_MISC__STRAP_NPEM_EN__SHIFT = 0x3 # macro +PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT = 0x4 # macro +PCIE_STRAP_MISC__STRAP_32GT_EN__SHIFT = 0x5 # macro +PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT = 0x6 # macro +PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT = 0x1a # macro +PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT = 0x1c # macro +PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT = 0x1f # macro +PCIE_STRAP_MISC__STRAP_DLF_EN_MASK = 0x00000001 # macro +PCIE_STRAP_MISC__STRAP_16GT_EN_MASK = 0x00000002 # macro +PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK = 0x00000004 # macro +PCIE_STRAP_MISC__STRAP_NPEM_EN_MASK = 0x00000008 # macro +PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK = 0x00000010 # macro +PCIE_STRAP_MISC__STRAP_32GT_EN_MASK = 0x00000020 # macro +PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK = 0x00000040 # macro +PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK = 0x04000000 # macro +PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK = 0x10000000 # macro +PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK = 0x80000000 # macro +PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT = 0x0 # macro +PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT = 0x1 # macro +PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT = 0x3 # macro +PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT = 0x5 # macro +PCIE_STRAP_MISC2__STRAP_GEN5_COMPLIANCE__SHIFT = 0x7 # macro +PCIE_STRAP_MISC2__STRAP_DRS_SUPPORTED__SHIFT = 0x8 # macro +PCIE_STRAP_MISC2__STRAP_FRS_SUPPORTED__SHIFT = 0x9 # macro +PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_EN__SHIFT = 0xa # macro +PCIE_STRAP_MISC2__STRAP_RTR_EN__SHIFT = 0xb # macro +PCIE_STRAP_MISC2__STRAP_IMMEDIATE_READINESS_EN__SHIFT = 0xc # macro +PCIE_STRAP_MISC2__STRAP_RTR_RESET_TIME__SHIFT = 0xd # macro +PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_MAX_DEPTH__SHIFT = 0x10 # macro +PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK = 0x00000001 # macro +PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK = 0x00000002 # macro +PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK = 0x00000008 # macro +PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK = 0x00000020 # macro +PCIE_STRAP_MISC2__STRAP_GEN5_COMPLIANCE_MASK = 0x00000080 # macro +PCIE_STRAP_MISC2__STRAP_DRS_SUPPORTED_MASK = 0x00000100 # macro +PCIE_STRAP_MISC2__STRAP_FRS_SUPPORTED_MASK = 0x00000200 # macro +PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_EN_MASK = 0x00000400 # macro +PCIE_STRAP_MISC2__STRAP_RTR_EN_MASK = 0x00000800 # macro +PCIE_STRAP_MISC2__STRAP_IMMEDIATE_READINESS_EN_MASK = 0x00001000 # macro +PCIE_STRAP_MISC2__STRAP_RTR_RESET_TIME_MASK = 0x00006000 # macro +PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_MAX_DEPTH_MASK = 0x00030000 # macro +PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT = 0x0 # macro +PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT = 0x1c # macro +PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT = 0x1d # macro +PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK = 0x00000001 # macro +PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK = 0x10000000 # macro +PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK = 0x20000000 # macro +PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT = 0x0 # macro +PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK = 0x0000007F # macro +PCIE_PRBS_CLR__PRBS_CLR__SHIFT = 0x0 # macro +PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT = 0x18 # macro +PCIE_PRBS_CLR__PRBS_CLR_MASK = 0x0000FFFF # macro +PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK = 0x01000000 # macro +PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT = 0x0 # macro +PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT = 0x10 # macro +PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK = 0x0000FFFF # macro +PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK = 0xFFFF0000 # macro +PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT = 0x0 # macro +PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK = 0x0000FFFF # macro +PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT = 0x0 # macro +PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK = 0x0000FFFF # macro +PCIE_PRBS_MISC__PRBS_EN__SHIFT = 0x0 # macro +PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT = 0x1 # macro +PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT = 0x4 # macro +PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT = 0x5 # macro +PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT = 0x6 # macro +PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT = 0x8 # macro +PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT = 0xe # macro +PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT = 0x10 # macro +PCIE_PRBS_MISC__PRBS_EN_MASK = 0x00000001 # macro +PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK = 0x0000000E # macro +PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK = 0x00000010 # macro +PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK = 0x00000020 # macro +PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK = 0x000000C0 # macro +PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK = 0x00001F00 # macro +PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK = 0x0000C000 # macro +PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK = 0xFFFF0000 # macro +PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT = 0x0 # macro +PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK = 0x3FFFFFFF # macro +PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT = 0x0 # macro +PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT = 0x0 # macro +PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK = 0x000000FF # macro +PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK = 0xFFFFFFFF # macro +PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT = 0x0 # macro +PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK = 0xFFFFFFFF # macro +SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT = 0x0 # macro +SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT = 0x1 # macro +SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT = 0x10 # macro +SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT = 0x11 # macro +SWRST_COMMAND_STATUS__PERST_ASRT__SHIFT = 0x12 # macro +SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT = 0x18 # macro +SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT = 0x19 # macro +SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT = 0x1a # macro +SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT = 0x1b # macro +SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT = 0x1c # macro +SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT = 0x1d # macro +SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT = 0x1e # macro +SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT = 0x1f # macro +SWRST_COMMAND_STATUS__RECONFIGURE_MASK = 0x00000001 # macro +SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK = 0x00000002 # macro +SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK = 0x00010000 # macro +SWRST_COMMAND_STATUS__WAIT_STATE_MASK = 0x00020000 # macro +SWRST_COMMAND_STATUS__PERST_ASRT_MASK = 0x00040000 # macro +SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK = 0x01000000 # macro +SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK = 0x02000000 # macro +SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK = 0x04000000 # macro +SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK = 0x08000000 # macro +SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK = 0x10000000 # macro +SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK = 0x20000000 # macro +SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK = 0x40000000 # macro +SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK = 0x80000000 # macro +SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT = 0x0 # macro +SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT = 0x1 # macro +SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT = 0x2 # macro +SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT = 0x8 # macro +SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT = 0x9 # macro +SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT = 0xa # macro +SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT = 0xc # macro +SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT = 0x11 # macro +SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT = 0x18 # macro +SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT = 0x19 # macro +SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS__SHIFT = 0x1a # macro +SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK = 0x00000001 # macro +SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK = 0x00000002 # macro +SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK = 0x0000001C # macro +SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK = 0x00000100 # macro +SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK = 0x00000200 # macro +SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK = 0x00000400 # macro +SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK = 0x00001000 # macro +SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK = 0x00020000 # macro +SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK = 0x01000000 # macro +SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK = 0x02000000 # macro +SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS_MASK = 0x04000000 # macro +SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT = 0x0 # macro +SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT = 0x8 # macro +SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT = 0x9 # macro +SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT = 0xa # macro +SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT = 0xb # macro +SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT = 0xc # macro +SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT = 0xd # macro +SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT = 0xe # macro +SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT = 0xf # macro +SWRST_COMMAND_0__PORT8_CFG_RESET__SHIFT = 0x10 # macro +SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT = 0x18 # macro +SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT = 0x19 # macro +SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT = 0x1a # macro +SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT = 0x1b # macro +SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT = 0x1c # macro +SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT = 0x1d # macro +SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT = 0x1e # macro +SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET__SHIFT = 0x1f # macro +SWRST_COMMAND_0__PORT0_COR_RESET_MASK = 0x00000001 # macro +SWRST_COMMAND_0__PORT0_CFG_RESET_MASK = 0x00000100 # macro +SWRST_COMMAND_0__PORT1_CFG_RESET_MASK = 0x00000200 # macro +SWRST_COMMAND_0__PORT2_CFG_RESET_MASK = 0x00000400 # macro +SWRST_COMMAND_0__PORT3_CFG_RESET_MASK = 0x00000800 # macro +SWRST_COMMAND_0__PORT4_CFG_RESET_MASK = 0x00001000 # macro +SWRST_COMMAND_0__PORT5_CFG_RESET_MASK = 0x00002000 # macro +SWRST_COMMAND_0__PORT6_CFG_RESET_MASK = 0x00004000 # macro +SWRST_COMMAND_0__PORT7_CFG_RESET_MASK = 0x00008000 # macro +SWRST_COMMAND_0__PORT8_CFG_RESET_MASK = 0x00010000 # macro +SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK = 0x01000000 # macro +SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK = 0x02000000 # macro +SWRST_COMMAND_0__BIF0_CORE_RESET_MASK = 0x04000000 # macro +SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK = 0x08000000 # macro +SWRST_COMMAND_0__BIF0_PHY_RESET_MASK = 0x10000000 # macro +SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK = 0x20000000 # macro +SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK = 0x40000000 # macro +SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET_MASK = 0x80000000 # macro +SWRST_COMMAND_1__RESETPCS0__SHIFT = 0x0 # macro +SWRST_COMMAND_1__RESETPCS1__SHIFT = 0x1 # macro +SWRST_COMMAND_1__RESETPCS2__SHIFT = 0x2 # macro +SWRST_COMMAND_1__RESETPCS3__SHIFT = 0x3 # macro +SWRST_COMMAND_1__RESETPCS4__SHIFT = 0x4 # macro +SWRST_COMMAND_1__RESETPCS5__SHIFT = 0x5 # macro +SWRST_COMMAND_1__RESETPCS6__SHIFT = 0x6 # macro +SWRST_COMMAND_1__RESETPCS7__SHIFT = 0x7 # macro +SWRST_COMMAND_1__RESETPCS8__SHIFT = 0x8 # macro +SWRST_COMMAND_1__RESETPCS9__SHIFT = 0x9 # macro +SWRST_COMMAND_1__RESETPCS10__SHIFT = 0xa # macro +SWRST_COMMAND_1__RESETPCS11__SHIFT = 0xb # macro +SWRST_COMMAND_1__RESETPCS12__SHIFT = 0xc # macro +SWRST_COMMAND_1__RESETPCS13__SHIFT = 0xd # macro +SWRST_COMMAND_1__RESETPCS14__SHIFT = 0xe # macro +SWRST_COMMAND_1__RESETPCS15__SHIFT = 0xf # macro +SWRST_COMMAND_1__SWITCHCLK__SHIFT = 0x15 # macro +SWRST_COMMAND_1__RESETPCFG__SHIFT = 0x19 # macro +SWRST_COMMAND_1__RESETLNCT__SHIFT = 0x1a # macro +SWRST_COMMAND_1__RESETMNTR__SHIFT = 0x1b # macro +SWRST_COMMAND_1__RESETHLTR__SHIFT = 0x1c # macro +SWRST_COMMAND_1__RESETCPM__SHIFT = 0x1d # macro +SWRST_COMMAND_1__RESETPHY0__SHIFT = 0x1e # macro +SWRST_COMMAND_1__TOGGLESTRAP__SHIFT = 0x1f # macro +SWRST_COMMAND_1__RESETPCS0_MASK = 0x00000001 # macro +SWRST_COMMAND_1__RESETPCS1_MASK = 0x00000002 # macro +SWRST_COMMAND_1__RESETPCS2_MASK = 0x00000004 # macro +SWRST_COMMAND_1__RESETPCS3_MASK = 0x00000008 # macro +SWRST_COMMAND_1__RESETPCS4_MASK = 0x00000010 # macro +SWRST_COMMAND_1__RESETPCS5_MASK = 0x00000020 # macro +SWRST_COMMAND_1__RESETPCS6_MASK = 0x00000040 # macro +SWRST_COMMAND_1__RESETPCS7_MASK = 0x00000080 # macro +SWRST_COMMAND_1__RESETPCS8_MASK = 0x00000100 # macro +SWRST_COMMAND_1__RESETPCS9_MASK = 0x00000200 # macro +SWRST_COMMAND_1__RESETPCS10_MASK = 0x00000400 # macro +SWRST_COMMAND_1__RESETPCS11_MASK = 0x00000800 # macro +SWRST_COMMAND_1__RESETPCS12_MASK = 0x00001000 # macro +SWRST_COMMAND_1__RESETPCS13_MASK = 0x00002000 # macro +SWRST_COMMAND_1__RESETPCS14_MASK = 0x00004000 # macro +SWRST_COMMAND_1__RESETPCS15_MASK = 0x00008000 # macro +SWRST_COMMAND_1__SWITCHCLK_MASK = 0x00200000 # macro +SWRST_COMMAND_1__RESETPCFG_MASK = 0x02000000 # macro +SWRST_COMMAND_1__RESETLNCT_MASK = 0x04000000 # macro +SWRST_COMMAND_1__RESETMNTR_MASK = 0x08000000 # macro +SWRST_COMMAND_1__RESETHLTR_MASK = 0x10000000 # macro +SWRST_COMMAND_1__RESETCPM_MASK = 0x20000000 # macro +SWRST_COMMAND_1__RESETPHY0_MASK = 0x40000000 # macro +SWRST_COMMAND_1__TOGGLESTRAP_MASK = 0x80000000 # macro +SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT = 0x0 # macro +SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT = 0x8 # macro +SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT = 0x9 # macro +SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT = 0xa # macro +SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT = 0xb # macro +SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT = 0xc # macro +SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT = 0xd # macro +SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT = 0xe # macro +SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT = 0xf # macro +SWRST_CONTROL_0__PORT8_CFG_RCEN__SHIFT = 0x10 # macro +SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT = 0x18 # macro +SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT = 0x19 # macro +SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT = 0x1a # macro +SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT = 0x1b # macro +SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT = 0x1c # macro +SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT = 0x1d # macro +SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT = 0x1e # macro +SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN__SHIFT = 0x1f # macro +SWRST_CONTROL_0__PORT0_COR_RCEN_MASK = 0x00000001 # macro +SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK = 0x00000100 # macro +SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK = 0x00000200 # macro +SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK = 0x00000400 # macro +SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK = 0x00000800 # macro +SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK = 0x00001000 # macro +SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK = 0x00002000 # macro +SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK = 0x00004000 # macro +SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK = 0x00008000 # macro +SWRST_CONTROL_0__PORT8_CFG_RCEN_MASK = 0x00010000 # macro +SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK = 0x01000000 # macro +SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK = 0x02000000 # macro +SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK = 0x04000000 # macro +SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK = 0x08000000 # macro +SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK = 0x10000000 # macro +SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK = 0x20000000 # macro +SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK = 0x40000000 # macro +SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN_MASK = 0x80000000 # macro +SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT = 0x0 # macro +SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT = 0x1 # macro +SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT = 0x2 # macro +SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT = 0x3 # macro +SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT = 0x4 # macro +SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT = 0x5 # macro +SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT = 0x6 # macro +SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT = 0x7 # macro +SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT = 0x8 # macro +SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT = 0x9 # macro +SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT = 0xa # macro +SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT = 0xb # macro +SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT = 0xc # macro +SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT = 0xd # macro +SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT = 0xe # macro +SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT = 0xf # macro +SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT = 0x15 # macro +SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT = 0x19 # macro +SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT = 0x1a # macro +SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT = 0x1b # macro +SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT = 0x1c # macro +SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT = 0x1d # macro +SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT = 0x1e # macro +SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT = 0x1f # macro +SWRST_CONTROL_1__PCSRESET0_RCEN_MASK = 0x00000001 # macro +SWRST_CONTROL_1__PCSRESET1_RCEN_MASK = 0x00000002 # macro +SWRST_CONTROL_1__PCSRESET2_RCEN_MASK = 0x00000004 # macro +SWRST_CONTROL_1__PCSRESET3_RCEN_MASK = 0x00000008 # macro +SWRST_CONTROL_1__PCSRESET4_RCEN_MASK = 0x00000010 # macro +SWRST_CONTROL_1__PCSRESET5_RCEN_MASK = 0x00000020 # macro +SWRST_CONTROL_1__PCSRESET6_RCEN_MASK = 0x00000040 # macro +SWRST_CONTROL_1__PCSRESET7_RCEN_MASK = 0x00000080 # macro +SWRST_CONTROL_1__PCSRESET8_RCEN_MASK = 0x00000100 # macro +SWRST_CONTROL_1__PCSRESET9_RCEN_MASK = 0x00000200 # macro +SWRST_CONTROL_1__PCSRESET10_RCEN_MASK = 0x00000400 # macro +SWRST_CONTROL_1__PCSRESET11_RCEN_MASK = 0x00000800 # macro +SWRST_CONTROL_1__PCSRESET12_RCEN_MASK = 0x00001000 # macro +SWRST_CONTROL_1__PCSRESET13_RCEN_MASK = 0x00002000 # macro +SWRST_CONTROL_1__PCSRESET14_RCEN_MASK = 0x00004000 # macro +SWRST_CONTROL_1__PCSRESET15_RCEN_MASK = 0x00008000 # macro +SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK = 0x00200000 # macro +SWRST_CONTROL_1__RESETPCFG_RCEN_MASK = 0x02000000 # macro +SWRST_CONTROL_1__RESETLNCT_RCEN_MASK = 0x04000000 # macro +SWRST_CONTROL_1__RESETMNTR_RCEN_MASK = 0x08000000 # macro +SWRST_CONTROL_1__RESETHLTR_RCEN_MASK = 0x10000000 # macro +SWRST_CONTROL_1__RESETCPM_RCEN_MASK = 0x20000000 # macro +SWRST_CONTROL_1__RESETPHY0_RCEN_MASK = 0x40000000 # macro +SWRST_CONTROL_1__STRAPVLD_RCEN_MASK = 0x80000000 # macro +SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT = 0x0 # macro +SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT = 0x8 # macro +SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT = 0x9 # macro +SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT = 0xa # macro +SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT = 0xb # macro +SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT = 0xc # macro +SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT = 0xd # macro +SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT = 0xe # macro +SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT = 0xf # macro +SWRST_CONTROL_2__PORT8_CFG_ATEN__SHIFT = 0x10 # macro +SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT = 0x18 # macro +SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT = 0x19 # macro +SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT = 0x1a # macro +SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT = 0x1b # macro +SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT = 0x1c # macro +SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT = 0x1d # macro +SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT = 0x1e # macro +SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN__SHIFT = 0x1f # macro +SWRST_CONTROL_2__PORT0_COR_ATEN_MASK = 0x00000001 # macro +SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK = 0x00000100 # macro +SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK = 0x00000200 # macro +SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK = 0x00000400 # macro +SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK = 0x00000800 # macro +SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK = 0x00001000 # macro +SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK = 0x00002000 # macro +SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK = 0x00004000 # macro +SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK = 0x00008000 # macro +SWRST_CONTROL_2__PORT8_CFG_ATEN_MASK = 0x00010000 # macro +SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK = 0x01000000 # macro +SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK = 0x02000000 # macro +SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK = 0x04000000 # macro +SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK = 0x08000000 # macro +SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK = 0x10000000 # macro +SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK = 0x20000000 # macro +SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK = 0x40000000 # macro +SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN_MASK = 0x80000000 # macro +SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT = 0x0 # macro +SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT = 0x1 # macro +SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT = 0x2 # macro +SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT = 0x3 # macro +SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT = 0x4 # macro +SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT = 0x5 # macro +SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT = 0x6 # macro +SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT = 0x7 # macro +SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT = 0x8 # macro +SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT = 0x9 # macro +SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT = 0xa # macro +SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT = 0xb # macro +SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT = 0xc # macro +SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT = 0xd # macro +SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT = 0xe # macro +SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT = 0xf # macro +SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT = 0x15 # macro +SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT = 0x19 # macro +SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT = 0x1a # macro +SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT = 0x1b # macro +SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT = 0x1c # macro +SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT = 0x1d # macro +SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT = 0x1e # macro +SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT = 0x1f # macro +SWRST_CONTROL_3__PCSRESET0_ATEN_MASK = 0x00000001 # macro +SWRST_CONTROL_3__PCSRESET1_ATEN_MASK = 0x00000002 # macro +SWRST_CONTROL_3__PCSRESET2_ATEN_MASK = 0x00000004 # macro +SWRST_CONTROL_3__PCSRESET3_ATEN_MASK = 0x00000008 # macro +SWRST_CONTROL_3__PCSRESET4_ATEN_MASK = 0x00000010 # macro +SWRST_CONTROL_3__PCSRESET5_ATEN_MASK = 0x00000020 # macro +SWRST_CONTROL_3__PCSRESET6_ATEN_MASK = 0x00000040 # macro +SWRST_CONTROL_3__PCSRESET7_ATEN_MASK = 0x00000080 # macro +SWRST_CONTROL_3__PCSRESET8_ATEN_MASK = 0x00000100 # macro +SWRST_CONTROL_3__PCSRESET9_ATEN_MASK = 0x00000200 # macro +SWRST_CONTROL_3__PCSRESET10_ATEN_MASK = 0x00000400 # macro +SWRST_CONTROL_3__PCSRESET11_ATEN_MASK = 0x00000800 # macro +SWRST_CONTROL_3__PCSRESET12_ATEN_MASK = 0x00001000 # macro +SWRST_CONTROL_3__PCSRESET13_ATEN_MASK = 0x00002000 # macro +SWRST_CONTROL_3__PCSRESET14_ATEN_MASK = 0x00004000 # macro +SWRST_CONTROL_3__PCSRESET15_ATEN_MASK = 0x00008000 # macro +SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK = 0x00200000 # macro +SWRST_CONTROL_3__RESETPCFG_ATEN_MASK = 0x02000000 # macro +SWRST_CONTROL_3__RESETLNCT_ATEN_MASK = 0x04000000 # macro +SWRST_CONTROL_3__RESETMNTR_ATEN_MASK = 0x08000000 # macro +SWRST_CONTROL_3__RESETHLTR_ATEN_MASK = 0x10000000 # macro +SWRST_CONTROL_3__RESETCPM_ATEN_MASK = 0x20000000 # macro +SWRST_CONTROL_3__RESETPHY0_ATEN_MASK = 0x40000000 # macro +SWRST_CONTROL_3__STRAPVLD_ATEN_MASK = 0x80000000 # macro +SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT = 0x0 # macro +SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT = 0x8 # macro +SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT = 0x9 # macro +SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT = 0xa # macro +SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT = 0xb # macro +SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT = 0xc # macro +SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT = 0xd # macro +SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT = 0xe # macro +SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT = 0xf # macro +SWRST_CONTROL_4__PORT8_CFG_WREN__SHIFT = 0x10 # macro +SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT = 0x18 # macro +SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT = 0x19 # macro +SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT = 0x1a # macro +SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT = 0x1b # macro +SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT = 0x1c # macro +SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT = 0x1d # macro +SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT = 0x1e # macro +SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN__SHIFT = 0x1f # macro +SWRST_CONTROL_4__PORT0_COR_WREN_MASK = 0x00000001 # macro +SWRST_CONTROL_4__PORT0_CFG_WREN_MASK = 0x00000100 # macro +SWRST_CONTROL_4__PORT1_CFG_WREN_MASK = 0x00000200 # macro +SWRST_CONTROL_4__PORT2_CFG_WREN_MASK = 0x00000400 # macro +SWRST_CONTROL_4__PORT3_CFG_WREN_MASK = 0x00000800 # macro +SWRST_CONTROL_4__PORT4_CFG_WREN_MASK = 0x00001000 # macro +SWRST_CONTROL_4__PORT5_CFG_WREN_MASK = 0x00002000 # macro +SWRST_CONTROL_4__PORT6_CFG_WREN_MASK = 0x00004000 # macro +SWRST_CONTROL_4__PORT7_CFG_WREN_MASK = 0x00008000 # macro +SWRST_CONTROL_4__PORT8_CFG_WREN_MASK = 0x00010000 # macro +SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK = 0x01000000 # macro +SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK = 0x02000000 # macro +SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK = 0x04000000 # macro +SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK = 0x08000000 # macro +SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK = 0x10000000 # macro +SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK = 0x20000000 # macro +SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK = 0x40000000 # macro +SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN_MASK = 0x80000000 # macro +SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT = 0x0 # macro +SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT = 0x1 # macro +SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT = 0x2 # macro +SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT = 0x3 # macro +SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT = 0x4 # macro +SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT = 0x5 # macro +SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT = 0x6 # macro +SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT = 0x7 # macro +SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT = 0x8 # macro +SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT = 0x9 # macro +SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT = 0xa # macro +SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT = 0xb # macro +SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT = 0xc # macro +SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT = 0xd # macro +SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT = 0xe # macro +SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT = 0xf # macro +SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT = 0x15 # macro +SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT = 0x19 # macro +SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT = 0x1a # macro +SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT = 0x1b # macro +SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT = 0x1c # macro +SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT = 0x1d # macro +SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT = 0x1e # macro +SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT = 0x1f # macro +SWRST_CONTROL_5__PCSRESET0_WREN_MASK = 0x00000001 # macro +SWRST_CONTROL_5__PCSRESET1_WREN_MASK = 0x00000002 # macro +SWRST_CONTROL_5__PCSRESET2_WREN_MASK = 0x00000004 # macro +SWRST_CONTROL_5__PCSRESET3_WREN_MASK = 0x00000008 # macro +SWRST_CONTROL_5__PCSRESET4_WREN_MASK = 0x00000010 # macro +SWRST_CONTROL_5__PCSRESET5_WREN_MASK = 0x00000020 # macro +SWRST_CONTROL_5__PCSRESET6_WREN_MASK = 0x00000040 # macro +SWRST_CONTROL_5__PCSRESET7_WREN_MASK = 0x00000080 # macro +SWRST_CONTROL_5__PCSRESET8_WREN_MASK = 0x00000100 # macro +SWRST_CONTROL_5__PCSRESET9_WREN_MASK = 0x00000200 # macro +SWRST_CONTROL_5__PCSRESET10_WREN_MASK = 0x00000400 # macro +SWRST_CONTROL_5__PCSRESET11_WREN_MASK = 0x00000800 # macro +SWRST_CONTROL_5__PCSRESET12_WREN_MASK = 0x00001000 # macro +SWRST_CONTROL_5__PCSRESET13_WREN_MASK = 0x00002000 # macro +SWRST_CONTROL_5__PCSRESET14_WREN_MASK = 0x00004000 # macro +SWRST_CONTROL_5__PCSRESET15_WREN_MASK = 0x00008000 # macro +SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK = 0x00200000 # macro +SWRST_CONTROL_5__WRRESETPCFG_EN_MASK = 0x02000000 # macro +SWRST_CONTROL_5__WRRESETLNCT_EN_MASK = 0x04000000 # macro +SWRST_CONTROL_5__WRRESETMNTR_EN_MASK = 0x08000000 # macro +SWRST_CONTROL_5__WRRESETHLTR_EN_MASK = 0x10000000 # macro +SWRST_CONTROL_5__WRRESETCPM_EN_MASK = 0x20000000 # macro +SWRST_CONTROL_5__WRRESETPHY0_EN_MASK = 0x40000000 # macro +SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK = 0x80000000 # macro +SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT = 0x0 # macro +SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT = 0x1 # macro +SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT = 0x2 # macro +SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT = 0x3 # macro +SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT = 0x4 # macro +SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT = 0x5 # macro +SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT = 0x6 # macro +SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT = 0x7 # macro +SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT = 0x8 # macro +SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT = 0x9 # macro +SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT = 0xa # macro +SWRST_CONTROL_6__HOLD_TRAINING_A_MASK = 0x00000001 # macro +SWRST_CONTROL_6__HOLD_TRAINING_B_MASK = 0x00000002 # macro +SWRST_CONTROL_6__HOLD_TRAINING_C_MASK = 0x00000004 # macro +SWRST_CONTROL_6__HOLD_TRAINING_D_MASK = 0x00000008 # macro +SWRST_CONTROL_6__HOLD_TRAINING_E_MASK = 0x00000010 # macro +SWRST_CONTROL_6__HOLD_TRAINING_F_MASK = 0x00000020 # macro +SWRST_CONTROL_6__HOLD_TRAINING_G_MASK = 0x00000040 # macro +SWRST_CONTROL_6__HOLD_TRAINING_H_MASK = 0x00000080 # macro +SWRST_CONTROL_6__HOLD_TRAINING_I_MASK = 0x00000100 # macro +SWRST_CONTROL_6__HOLD_TRAINING_J_MASK = 0x00000200 # macro +SWRST_CONTROL_6__HOLD_TRAINING_K_MASK = 0x00000400 # macro +SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT = 0x0 # macro +SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT = 0x8 # macro +SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT = 0x9 # macro +SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT = 0xa # macro +SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK = 0x00000001 # macro +SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK = 0x00000100 # macro +SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK = 0x00000200 # macro +SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK = 0x00000400 # macro +SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT = 0x0 # macro +SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT = 0x8 # macro +SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT = 0x9 # macro +SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT = 0xa # macro +SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK = 0x00000001 # macro +SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK = 0x00000100 # macro +SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK = 0x00000200 # macro +SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK = 0x00000400 # macro +CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT = 0x0 # macro +CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT = 0x1 # macro +CPM_CONTROL__L1_PWR_GATE_ENABLE__SHIFT = 0x2 # macro +CPM_CONTROL__L1_1_PWR_GATE_ENABLE__SHIFT = 0x3 # macro +CPM_CONTROL__L1_2_PWR_GATE_ENABLE__SHIFT = 0x4 # macro +CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT = 0x5 # macro +CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT = 0x6 # macro +CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT = 0x7 # macro +CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT = 0x8 # macro +CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT = 0x9 # macro +CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT = 0xb # macro +CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE__SHIFT = 0xd # macro +CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT = 0xe # macro +CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT = 0xf # macro +CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT = 0x10 # macro +CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT = 0x11 # macro +CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT = 0x12 # macro +CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG__SHIFT = 0x15 # macro +CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT = 0x16 # macro +CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT = 0x17 # macro +CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT = 0x18 # macro +CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT = 0x19 # macro +CPM_CONTROL__PG_EARLY_WAKE_ENABLE__SHIFT = 0x1a # macro +CPM_CONTROL__PCIE_CORE_IDLE__SHIFT = 0x1b # macro +CPM_CONTROL__PCIE_LINK_IDLE__SHIFT = 0x1c # macro +CPM_CONTROL__PCIE_BUFFER_EMPTY__SHIFT = 0x1d # macro +CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY__SHIFT = 0x1e # macro +CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK = 0x00000001 # macro +CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK = 0x00000002 # macro +CPM_CONTROL__L1_PWR_GATE_ENABLE_MASK = 0x00000004 # macro +CPM_CONTROL__L1_1_PWR_GATE_ENABLE_MASK = 0x00000008 # macro +CPM_CONTROL__L1_2_PWR_GATE_ENABLE_MASK = 0x00000010 # macro +CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK = 0x00000020 # macro +CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK = 0x00000040 # macro +CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK = 0x00000080 # macro +CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK = 0x00000100 # macro +CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK = 0x00000600 # macro +CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK = 0x00001800 # macro +CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE_MASK = 0x00002000 # macro +CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK = 0x00004000 # macro +CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK = 0x00008000 # macro +CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK = 0x00010000 # macro +CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK = 0x00020000 # macro +CPM_CONTROL__FAST_TXCLK_LATENCY_MASK = 0x001C0000 # macro +CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG_MASK = 0x00200000 # macro +CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK = 0x00400000 # macro +CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK = 0x00800000 # macro +CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK = 0x01000000 # macro +CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK = 0x02000000 # macro +CPM_CONTROL__PG_EARLY_WAKE_ENABLE_MASK = 0x04000000 # macro +CPM_CONTROL__PCIE_CORE_IDLE_MASK = 0x08000000 # macro +CPM_CONTROL__PCIE_LINK_IDLE_MASK = 0x10000000 # macro +CPM_CONTROL__PCIE_BUFFER_EMPTY_MASK = 0x20000000 # macro +CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY_MASK = 0xC0000000 # macro +CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE__SHIFT = 0x0 # macro +CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE_MASK = 0x00000001 # macro +CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE__SHIFT = 0x0 # macro +CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE__SHIFT = 0x1 # macro +CPM_CONTROL_EXT__LCLK_DS_MODE__SHIFT = 0x2 # macro +CPM_CONTROL_EXT__LCLK_DS_ENABLE__SHIFT = 0x3 # macro +CPM_CONTROL_EXT__PG_STATE__SHIFT = 0x4 # macro +CPM_CONTROL_EXT__HOTPLUG_ALLOW_LCLK_GATING_EN__SHIFT = 0x7 # macro +CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE_MASK = 0x00000001 # macro +CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE_MASK = 0x00000002 # macro +CPM_CONTROL_EXT__LCLK_DS_MODE_MASK = 0x00000004 # macro +CPM_CONTROL_EXT__LCLK_DS_ENABLE_MASK = 0x00000008 # macro +CPM_CONTROL_EXT__PG_STATE_MASK = 0x00000070 # macro +CPM_CONTROL_EXT__HOTPLUG_ALLOW_LCLK_GATING_EN_MASK = 0x00000080 # macro +SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT = 0x0 # macro +SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT = 0xc # macro +SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK = 0x00000FFF # macro +SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK = 0x00FFF000 # macro +SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT = 0x0 # macro +SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT = 0xc # macro +SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK = 0x00000FFF # macro +SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK = 0x00FFF000 # macro +LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT = 0x0 # macro +LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT = 0x1 # macro +LNCNT_CONTROL__CFG_LNC_BW_QUAN_THRD__SHIFT = 0x2 # macro +LNCNT_CONTROL__CFG_LNC_CMN_QUAN_THRD__SHIFT = 0x5 # macro +LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK = 0x00000001 # macro +LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK = 0x00000002 # macro +LNCNT_CONTROL__CFG_LNC_BW_QUAN_THRD_MASK = 0x0000001C # macro +LNCNT_CONTROL__CFG_LNC_CMN_QUAN_THRD_MASK = 0x000000E0 # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT = 0x0 # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT = 0x10 # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK = 0x0000FFFF # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK = 0xFFFF0000 # macro +PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT = 0x0 # macro +PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT = 0x8 # macro +PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT = 0xa # macro +PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT = 0xe # macro +PCIE_PGMST_CNTL__PG_EXIT_TIMER__SHIFT = 0x10 # macro +PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK = 0x000000FF # macro +PCIE_PGMST_CNTL__CFG_PG_EN_MASK = 0x00000100 # macro +PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK = 0x00003C00 # macro +PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK = 0x0000C000 # macro +PCIE_PGMST_CNTL__PG_EXIT_TIMER_MASK = 0x00FF0000 # macro +PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE__SHIFT = 0x0 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE__SHIFT = 0x1 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE__SHIFT = 0x2 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE__SHIFT = 0x3 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE__SHIFT = 0x4 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE__SHIFT = 0x5 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE__SHIFT = 0x6 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE__SHIFT = 0x7 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE__SHIFT = 0x8 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE__SHIFT = 0x9 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE__SHIFT = 0xa # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE__SHIFT = 0xb # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE__SHIFT = 0xc # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE__SHIFT = 0xd # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE__SHIFT = 0xe # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE__SHIFT = 0xf # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE__SHIFT = 0x10 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE__SHIFT = 0x11 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE__SHIFT = 0x12 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE__SHIFT = 0x13 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE__SHIFT = 0x14 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE__SHIFT = 0x15 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE__SHIFT = 0x16 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE__SHIFT = 0x17 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE__SHIFT = 0x18 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE__SHIFT = 0x19 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE__SHIFT = 0x1a # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE__SHIFT = 0x1b # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE__SHIFT = 0x1c # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE__SHIFT = 0x1d # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE__SHIFT = 0x1e # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE__SHIFT = 0x1f # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE_MASK = 0x00000001 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE_MASK = 0x00000002 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE_MASK = 0x00000004 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE_MASK = 0x00000008 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE_MASK = 0x00000010 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE_MASK = 0x00000020 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE_MASK = 0x00000040 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE_MASK = 0x00000080 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE_MASK = 0x00000100 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE_MASK = 0x00000200 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE_MASK = 0x00000400 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE_MASK = 0x00000800 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE_MASK = 0x00001000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE_MASK = 0x00002000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE_MASK = 0x00004000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE_MASK = 0x00008000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE_MASK = 0x00010000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE_MASK = 0x00020000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE_MASK = 0x00040000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE_MASK = 0x00080000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE_MASK = 0x00100000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE_MASK = 0x00200000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE_MASK = 0x00400000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE_MASK = 0x00800000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE_MASK = 0x01000000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE_MASK = 0x02000000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE_MASK = 0x04000000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE_MASK = 0x08000000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE_MASK = 0x10000000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE_MASK = 0x20000000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE_MASK = 0x40000000 # macro +LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE_MASK = 0x80000000 # macro +LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY__SHIFT = 0x0 # macro +LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE__SHIFT = 0xf # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE__SHIFT = 0x10 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE__SHIFT = 0x11 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE__SHIFT = 0x12 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE__SHIFT = 0x13 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE__SHIFT = 0x14 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE__SHIFT = 0x15 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE__SHIFT = 0x16 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE__SHIFT = 0x17 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE__SHIFT = 0x18 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE__SHIFT = 0x19 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE__SHIFT = 0x1a # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE__SHIFT = 0x1b # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE__SHIFT = 0x1c # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE__SHIFT = 0x1d # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE__SHIFT = 0x1e # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE__SHIFT = 0x1f # macro +LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY_MASK = 0x00000007 # macro +LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE_MASK = 0x00008000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE_MASK = 0x00010000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE_MASK = 0x00020000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE_MASK = 0x00040000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE_MASK = 0x00080000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE_MASK = 0x00100000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE_MASK = 0x00200000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE_MASK = 0x00400000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE_MASK = 0x00800000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE_MASK = 0x01000000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE_MASK = 0x02000000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE_MASK = 0x04000000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE_MASK = 0x08000000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE_MASK = 0x10000000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE_MASK = 0x20000000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE_MASK = 0x40000000 # macro +LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE_MASK = 0x80000000 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT = 0x0 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT = 0x1 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT = 0x2 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT = 0x3 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT = 0x4 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK = 0x00000001 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK = 0x00000002 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK = 0x00000004 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK = 0x00000008 # macro +PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK = 0x00000010 # macro +PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT = 0x0 # macro +PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT = 0x7 # macro +PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT = 0xd # macro +PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT = 0x14 # macro +PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK = 0x0000007F # macro +PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK = 0x00001F80 # macro +PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK = 0x000FE000 # macro +PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK = 0x07F00000 # macro +PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT = 0x0 # macro +PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT = 0x6 # macro +PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT = 0xc # macro +PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT = 0x13 # macro +PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT = 0x18 # macro +PCIE_RXMARGIN_2_SETTINGS__ENABLE_PRECODING__SHIFT = 0x1e # macro +PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK = 0x0000003F # macro +PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK = 0x00000FC0 # macro +PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK = 0x0007F000 # macro +PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK = 0x00F80000 # macro +PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK = 0x3F000000 # macro +PCIE_RXMARGIN_2_SETTINGS__ENABLE_PRECODING_MASK = 0x40000000 # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__DPC_INT_STATUS__SHIFT = 0x0 # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__PD_INT_STATUS__SHIFT = 0x10 # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__DPC_INT_STATUS_MASK = 0x0000FFFF # macro +SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__PD_INT_STATUS_MASK = 0xFFFF0000 # macro +PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT = 0x0 # macro +PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK = 0xFFFFFFFF # macro +PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT = 0x0 # macro +PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK = 0xFFFFFFFF # macro +PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT = 0x0 # macro +PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK = 0xFFFFFFFF # macro +PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT = 0x0 # macro +PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK = 0xFFFFFFFF # macro +PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT = 0x2 # macro +PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT = 0x0 # macro +PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT = 0x0 # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT = 0x1 # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT = 0x8 # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT = 0xf # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK = 0x00000001 # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK = 0x0000000E # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK = 0x00007F00 # macro +PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK = 0x00008000 # macro +PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW__SHIFT = 0x0 # macro +PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW_MASK = 0x0000000F # macro +PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT = 0x0 # macro +PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT = 0x1 # macro +PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT = 0x2 # macro +PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT = 0x3 # macro +PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT = 0x4 # macro +PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT = 0x5 # macro +PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT = 0x6 # macro +PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT = 0x7 # macro +PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT = 0x8 # macro +PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT = 0x9 # macro +PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT = 0xa # macro +PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT = 0xb # macro +PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT = 0xc # macro +PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT = 0xd # macro +PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT = 0xe # macro +PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT = 0xf # macro +PCIE_TX_STATUS__TX_MST_MEM_READY_MASK = 0x00000001 # macro +PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK = 0x00000002 # macro +PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK = 0x00000004 # macro +PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK = 0x00000008 # macro +PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK = 0x00000010 # macro +PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK = 0x00000020 # macro +PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK = 0x00000040 # macro +PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK = 0x00000080 # macro +PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK = 0x00000100 # macro +PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK = 0x00000200 # macro +PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK = 0x00000400 # macro +PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK = 0x00000800 # macro +PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK = 0x00001000 # macro +PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK = 0x00002000 # macro +PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK = 0x00004000 # macro +PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK = 0x00008000 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT = 0x0 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT = 0x2 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT = 0x4 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT = 0x6 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT = 0x8 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT = 0xa # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT = 0xc # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK = 0x00000003 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK = 0x0000000C # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK = 0x00000030 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK = 0x000000C0 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK = 0x00000300 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK = 0x00000C00 # macro +PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK = 0x00003000 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT = 0x0 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT = 0x2 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT = 0x4 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT = 0x6 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT = 0x8 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT = 0xa # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT = 0xc # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK = 0x00000003 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK = 0x0000000C # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK = 0x00000030 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK = 0x000000C0 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK = 0x00000300 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK = 0x00000C00 # macro +PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK = 0x00003000 # macro +PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT__SHIFT = 0x0 # macro +PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN__SHIFT = 0x8 # macro +PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS__SHIFT = 0x9 # macro +PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS__SHIFT = 0xa # macro +PCIE_MST_CTRL_1__MST_SDP_CREDITS_LIVE_OVERRIDE_DIS__SHIFT = 0xe # macro +PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN__SHIFT = 0xf # macro +PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT__SHIFT = 0x10 # macro +PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS__SHIFT = 0x18 # macro +PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT_MASK = 0x000000FF # macro +PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN_MASK = 0x00000100 # macro +PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS_MASK = 0x00000200 # macro +PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS_MASK = 0x00000400 # macro +PCIE_MST_CTRL_1__MST_SDP_CREDITS_LIVE_OVERRIDE_DIS_MASK = 0x00004000 # macro +PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN_MASK = 0x00008000 # macro +PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT_MASK = 0x00FF0000 # macro +PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS_MASK = 0xFF000000 # macro +PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI__SHIFT = 0x0 # macro +PCIE_HIP_REG0__CI_HIP_APT0_ENABLE__SHIFT = 0x18 # macro +PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE__SHIFT = 0x19 # macro +PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE__SHIFT = 0x1a # macro +PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE__SHIFT = 0x1d # macro +PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI_MASK = 0x000FFFFF # macro +PCIE_HIP_REG0__CI_HIP_APT0_ENABLE_MASK = 0x01000000 # macro +PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE_MASK = 0x02000000 # macro +PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE_MASK = 0x1C000000 # macro +PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE_MASK = 0x60000000 # macro +PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO__SHIFT = 0x0 # macro +PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO_MASK = 0xFFFFFFFF # macro +PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI__SHIFT = 0x0 # macro +PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI_MASK = 0x000FFFFF # macro +PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO__SHIFT = 0x0 # macro +PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO_MASK = 0xFFFFFFFF # macro +PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI__SHIFT = 0x0 # macro +PCIE_HIP_REG4__CI_HIP_APT1_ENABLE__SHIFT = 0x18 # macro +PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE__SHIFT = 0x19 # macro +PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE__SHIFT = 0x1a # macro +PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE__SHIFT = 0x1d # macro +PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI_MASK = 0x000FFFFF # macro +PCIE_HIP_REG4__CI_HIP_APT1_ENABLE_MASK = 0x01000000 # macro +PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE_MASK = 0x02000000 # macro +PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE_MASK = 0x1C000000 # macro +PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE_MASK = 0x60000000 # macro +PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO__SHIFT = 0x0 # macro +PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO_MASK = 0xFFFFFFFF # macro +PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI__SHIFT = 0x0 # macro +PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI_MASK = 0x000FFFFF # macro +PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO__SHIFT = 0x0 # macro +PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO_MASK = 0xFFFFFFFF # macro +PCIE_HIP_REG8__CI_HIP_MASK__SHIFT = 0x0 # macro +PCIE_HIP_REG8__CI_HIP_MASK_MASK = 0x000FFFFF # macro +SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT = 0x0 # macro +SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK = 0x00000001 # macro +SMU_PCIE_FENCED2_REG__MP0_PCIE_OVERCLOCKING_EN__SHIFT = 0x0 # macro +SMU_PCIE_FENCED2_REG__MP0_PCIE_OVERCLOCKING_EN_MASK = 0x00000001 # macro +PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK7__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK7__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK7__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK7__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK7__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK7__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK7__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK7__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK7__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK7__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_TXCLK8__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK8__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK8__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK8__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK8__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK8__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK8__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK8__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK8__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK8__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK8__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK8__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_TXCLK9__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK9__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK9__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK9__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK9__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK9__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK9__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK9__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK9__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK9__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK9__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK9__COUNTER1_MASK = 0xFFFFFFFF # macro +PCIE_PERF_CNTL_TXCLK10__EVENT0_SEL__SHIFT = 0x0 # macro +PCIE_PERF_CNTL_TXCLK10__EVENT1_SEL__SHIFT = 0x8 # macro +PCIE_PERF_CNTL_TXCLK10__COUNTER0_FULL__SHIFT = 0x10 # macro +PCIE_PERF_CNTL_TXCLK10__COUNTER1_FULL__SHIFT = 0x11 # macro +PCIE_PERF_CNTL_TXCLK10__EVENT0_SEL_MASK = 0x000000FF # macro +PCIE_PERF_CNTL_TXCLK10__EVENT1_SEL_MASK = 0x0000FF00 # macro +PCIE_PERF_CNTL_TXCLK10__COUNTER0_FULL_MASK = 0x00010000 # macro +PCIE_PERF_CNTL_TXCLK10__COUNTER1_FULL_MASK = 0x00020000 # macro +PCIE_PERF_COUNT0_TXCLK10__COUNTER0__SHIFT = 0x0 # macro +PCIE_PERF_COUNT0_TXCLK10__COUNTER0_MASK = 0xFFFFFFFF # macro +PCIE_PERF_COUNT1_TXCLK10__COUNTER1__SHIFT = 0x0 # macro +PCIE_PERF_COUNT1_TXCLK10__COUNTER1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +PSWUSCFG0_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT = 0x0 # macro +SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT = 0x1 # macro +SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT = 0x2 # macro +SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT = 0x3 # macro +SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT = 0x4 # macro +SLOT_CAP__HOTPLUG_SURPRISE__SHIFT = 0x5 # macro +SLOT_CAP__HOTPLUG_CAPABLE__SHIFT = 0x6 # macro +SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT = 0x7 # macro +SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT = 0xf # macro +SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT = 0x11 # macro +SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT = 0x12 # macro +SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT = 0x13 # macro +SLOT_CAP__ATTN_BUTTON_PRESENT_MASK = 0x00000001 # macro +SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK = 0x00000002 # macro +SLOT_CAP__MRL_SENSOR_PRESENT_MASK = 0x00000004 # macro +SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK = 0x00000008 # macro +SLOT_CAP__PWR_INDICATOR_PRESENT_MASK = 0x00000010 # macro +SLOT_CAP__HOTPLUG_SURPRISE_MASK = 0x00000020 # macro +SLOT_CAP__HOTPLUG_CAPABLE_MASK = 0x00000040 # macro +SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK = 0x00007F80 # macro +SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK = 0x00018000 # macro +SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK = 0x00020000 # macro +SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK = 0x00040000 # macro +SLOT_CAP__PHYSICAL_SLOT_NUM_MASK = 0xFFF80000 # macro +SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT = 0x0 # macro +SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT = 0x1 # macro +SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT = 0x2 # macro +SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT = 0x3 # macro +SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT = 0x4 # macro +SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT = 0x5 # macro +SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT = 0x6 # macro +SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT = 0x8 # macro +SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT = 0xa # macro +SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT = 0xb # macro +SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT = 0xc # macro +SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT = 0xd # macro +SLOT_CNTL__INBAND_PD_DISABLE__SHIFT = 0xe # macro +SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK = 0x0001 # macro +SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK = 0x0002 # macro +SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK = 0x0004 # macro +SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK = 0x0008 # macro +SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK = 0x0010 # macro +SLOT_CNTL__HOTPLUG_INTR_EN_MASK = 0x0020 # macro +SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK = 0x00C0 # macro +SLOT_CNTL__PWR_INDICATOR_CNTL_MASK = 0x0300 # macro +SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK = 0x0400 # macro +SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK = 0x0800 # macro +SLOT_CNTL__DL_STATE_CHANGED_EN_MASK = 0x1000 # macro +SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK = 0x2000 # macro +SLOT_CNTL__INBAND_PD_DISABLE_MASK = 0x4000 # macro +SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT = 0x0 # macro +SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT = 0x1 # macro +SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT = 0x2 # macro +SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT = 0x3 # macro +SLOT_STATUS__COMMAND_COMPLETED__SHIFT = 0x4 # macro +SLOT_STATUS__MRL_SENSOR_STATE__SHIFT = 0x5 # macro +SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT = 0x6 # macro +SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT = 0x7 # macro +SLOT_STATUS__DL_STATE_CHANGED__SHIFT = 0x8 # macro +SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK = 0x0001 # macro +SLOT_STATUS__PWR_FAULT_DETECTED_MASK = 0x0002 # macro +SLOT_STATUS__MRL_SENSOR_CHANGED_MASK = 0x0004 # macro +SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK = 0x0008 # macro +SLOT_STATUS__COMMAND_COMPLETED_MASK = 0x0010 # macro +SLOT_STATUS__MRL_SENSOR_STATE_MASK = 0x0020 # macro +SLOT_STATUS__PRESENCE_DETECT_STATE_MASK = 0x0040 # macro +SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK = 0x0080 # macro +SLOT_STATUS__DL_STATE_CHANGED_MASK = 0x0100 # macro +SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT = 0x0 # macro +SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK = 0x00000001 # macro +SLOT_CNTL2__RESERVED__SHIFT = 0x0 # macro +SLOT_CNTL2__RESERVED_MASK = 0xFFFF # macro +SLOT_STATUS2__RESERVED__SHIFT = 0x0 # macro +SLOT_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK = 0x3F # macro +BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK = 0x3F # macro +BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK = 0x00000010 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT = 0x5 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT = 0x6 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT = 0x7 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT = 0xc # macro +RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT = 0xd # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x12 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x13 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x14 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x15 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT = 0x19 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT = 0x1c # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT = 0x1d # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK = 0x00000010 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK = 0x00000020 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK = 0x00000040 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK = 0x00000080 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK = 0x00001000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK = 0x00002000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00040000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00080000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00100000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00200000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK = 0x01000000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK = 0x0E000000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK = 0x10000000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK = 0xE0000000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT = 0x7 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT = 0x9 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT = 0xa # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT = 0xb # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT = 0xc # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT = 0xd # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT = 0xe # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT = 0xf # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT = 0x12 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT = 0x13 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK = 0x00000080 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK = 0x00000200 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK = 0x00000400 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK = 0x00000800 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK = 0x00001000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK = 0x00002000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK = 0x00004000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK = 0x00008000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK = 0x00040000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK = 0x00080000 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK = 0xFFFF0000 # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK = 0x00001F00 # macro +RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK = 0x00007FFE # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT = 0x5 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT = 0xb # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT = 0x12 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT = 0x19 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK = 0x00000010 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK = 0x000007E0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK = 0x0003F800 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK = 0x01FC0000 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK = 0xFE000000 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT = 0x6 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT = 0xc # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK = 0x0000003F # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK = 0x00000FC0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK = 0x0001F000 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK = 0x00FE0000 # macro +RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT = 0x6 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK = 0x00000008 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK = 0x00000040 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT = 0x6 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK = 0x00000008 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK = 0x00000040 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK = 0x00000080 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT = 0x6 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT = 0xa # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT = 0xd # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT = 0xe # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT = 0xf # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT = 0x10 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT = 0x11 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK = 0x00000007 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK = 0x00000038 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK = 0x00000040 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK = 0x00000380 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK = 0x00001C00 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK = 0x00002000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK = 0x00004000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK = 0x00008000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK = 0x00010000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK = 0x00020000 # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0xFF # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK = 0x001F # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK = 0x0100 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK = 0x1F # macro +RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT = 0xa # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT = 0xc # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT = 0x19 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK = 0x00000C00 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK = 0x00003000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK = 0x01000000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK = 0x02000000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK = 0x00000007 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK = 0x000000F8 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK = 0x0000FF00 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0x19 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0x1a # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT = 0x1b # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT = 0x1c # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT = 0x1d # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT = 0x1e # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT = 0x1f # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x01000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x02000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x04000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK = 0x08000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK = 0x10000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK = 0x20000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK = 0x40000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK = 0x80000000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT = 0x7 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK = 0x00000080 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT = 0x19 # macro +RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK = 0x06000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT = 0x8 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK = 0x00000100 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT = 0x12 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT = 0x13 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK = 0x00040000 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK = 0x00080000 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT = 0x9 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0x15 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK = 0x00000200 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00200000 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT = 0xa # macro +RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK = 0x00000400 # macro +RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK = 0x0E000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT = 0xd # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT = 0xf # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK = 0x00000E00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK = 0x00002000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK = 0x00700000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK = 0x03800000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK = 0x1C000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0xb # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK = 0x00000038 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK = 0x00000600 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x00003800 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x0003C000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x001C0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x01E00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK = 0x06000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK = 0x18000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK = 0x02000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK = 0x00030000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x0F000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0xF0000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK = 0x1F000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK = 0x0007FFC0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK = 0x0FFF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK = 0x00FFFFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK = 0x000FFE00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK = 0xFFF00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT = 0xa # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT = 0xb # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT = 0xc # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT = 0xd # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0xe # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0xf # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK = 0x00000038 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK = 0x00000200 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK = 0x00000400 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK = 0x00000800 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK = 0x00002000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK = 0x000C0000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK = 0x02000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT = 0xa # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT = 0xc # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT = 0xd # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT = 0xf # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK = 0x00000200 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK = 0x00000C00 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK = 0x00006000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK = 0x00018000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK = 0x02000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK = 0x18000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT = 0xa # macro +RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT = 0xd # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT = 0xe # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT = 0xf # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK = 0x00000200 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK = 0x00000C00 # macro +RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK = 0x00002000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK = 0x00C00000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x06000000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK = 0x000F0000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK = 0x00F00000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT = 0xf # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK = 0x00003E00 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK = 0x07000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK = 0x00E00000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT = 0xa # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK = 0x000003FF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK = 0x00000400 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK = 0x0F800000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00000007 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK = 0x00000070 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK = 0x00001E00 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK = 0x0000E000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00070000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK = 0x00780000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK = 0x03800000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK = 0x38000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK = 0xC0000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK = 0x00C00000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK = 0xFF000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK = 0x3E000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK = 0x01FFE000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK = 0x000F0000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK = 0x00F00000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK = 0x00003E00 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK = 0x07000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK = 0x0F800000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK = 0x00000004 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT = 0x0 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT = 0x10 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT = 0x14 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT = 0x1c # macro +RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT = 0x1d # macro +RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT = 0x1e # macro +RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT = 0x1f # macro +RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK = 0x000F0000 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK = 0x00F00000 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK = 0x10000000 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK = 0x20000000 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK = 0x40000000 # macro +RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK = 0x80000000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT = 0x7 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT = 0x8 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT = 0x9 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT = 0xe # macro +RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT = 0x10 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT = 0x11 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT = 0x14 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT = 0x15 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT = 0x17 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT = 0x18 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT = 0x1c # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT = 0x1d # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT = 0x1e # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT = 0x1f # macro +RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK = 0x00000080 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK = 0x00000100 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK = 0x00003E00 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK = 0x00004000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK = 0x00010000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK = 0x00020000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK = 0x00100000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK = 0x00200000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK = 0x00800000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK = 0x07000000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK = 0x10000000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK = 0x20000000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK = 0x40000000 # macro +RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK = 0x80000000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT = 0x0 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT = 0x10 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT = 0x11 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT = 0x12 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT = 0x13 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT = 0x14 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT = 0x18 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT = 0x1a # macro +RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT = 0x1b # macro +RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2__SHIFT = 0x1d # macro +RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2__SHIFT = 0x1e # macro +RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2__SHIFT = 0x1f # macro +RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK = 0x00010000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK = 0x00020000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK = 0x00040000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK = 0x00080000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK = 0x00100000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK = 0x01000000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK = 0x04000000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK = 0x08000000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2_MASK = 0x20000000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2_MASK = 0x40000000 # macro +RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2_MASK = 0x80000000 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT = 0x14 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT = 0x15 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT = 0x16 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT = 0x17 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT = 0x1c # macro +RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT = 0x1f # macro +RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK = 0x00100000 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK = 0x00200000 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK = 0x00400000 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK = 0x0F800000 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK = 0x70000000 # macro +RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK = 0x80000000 # macro +RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT = 0x0 # macro +RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2__SHIFT = 0x1b # macro +RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2__SHIFT = 0x1e # macro +RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2_MASK = 0x38000000 # macro +RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2_MASK = 0x40000000 # macro +RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT = 0x0 # macro +RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK = 0x00000001 # macro +RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT = 0x0 # macro +RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT = 0x8 # macro +RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT = 0x10 # macro +RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK = 0x000000FF # macro +RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK = 0x0000FF00 # macro +RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK = 0x00FF0000 # macro +RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2__SHIFT = 0x0 # macro +RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT = 0x0 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT = 0x10 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT = 0x14 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT = 0x1c # macro +RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT = 0x1d # macro +RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT = 0x1e # macro +RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT = 0x1f # macro +RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK = 0x000F0000 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK = 0x00F00000 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK = 0x10000000 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK = 0x20000000 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK = 0x40000000 # macro +RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK = 0x80000000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT = 0x7 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT = 0x8 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT = 0x9 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT = 0xe # macro +RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT = 0x10 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT = 0x11 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT = 0x14 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT = 0x15 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT = 0x17 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT = 0x18 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT = 0x1c # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT = 0x1d # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT = 0x1e # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT = 0x1f # macro +RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK = 0x00000080 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK = 0x00000100 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK = 0x00003E00 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK = 0x00004000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK = 0x00010000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK = 0x00020000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK = 0x00100000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK = 0x00200000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK = 0x00800000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK = 0x07000000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK = 0x10000000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK = 0x20000000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK = 0x40000000 # macro +RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK = 0x80000000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT = 0x0 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT = 0x10 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT = 0x11 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT = 0x12 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT = 0x13 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT = 0x14 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT = 0x18 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT = 0x1a # macro +RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT = 0x1b # macro +RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3__SHIFT = 0x1d # macro +RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3__SHIFT = 0x1e # macro +RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3__SHIFT = 0x1f # macro +RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK = 0x00010000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK = 0x00020000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK = 0x00040000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK = 0x00080000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK = 0x00100000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK = 0x01000000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK = 0x04000000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK = 0x08000000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3_MASK = 0x20000000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3_MASK = 0x40000000 # macro +RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3_MASK = 0x80000000 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT = 0x14 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT = 0x15 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT = 0x16 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT = 0x17 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT = 0x1c # macro +RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK = 0x00100000 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK = 0x00200000 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK = 0x00400000 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK = 0x0F800000 # macro +RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK = 0x70000000 # macro +RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT = 0x0 # macro +RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3__SHIFT = 0x1b # macro +RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3__SHIFT = 0x1e # macro +RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK = 0x0000FFFF # macro +RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3_MASK = 0x38000000 # macro +RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3_MASK = 0x40000000 # macro +RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT = 0x0 # macro +RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK = 0x00000001 # macro +RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT = 0x0 # macro +RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT = 0x8 # macro +RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT = 0x10 # macro +RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK = 0x000000FF # macro +RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK = 0x0000FF00 # macro +RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK = 0x00FF0000 # macro +RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3__SHIFT = 0x0 # macro +RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3_MASK = 0x0000FFFF # macro +HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT = 0x0 # macro +HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT = 0x1 # macro +HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT = 0x2 # macro +HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT = 0x3 # macro +HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT = 0x4 # macro +HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT = 0x5 # macro +HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT = 0x6 # macro +HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT = 0x7 # macro +HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT = 0x9 # macro +HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT = 0xa # macro +HARD_RST_CTRL__STRAP_RST_EN__SHIFT = 0x17 # macro +HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT = 0x1c # macro +HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT = 0x1d # macro +HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT = 0x1e # macro +HARD_RST_CTRL__CORE_RST_EN__SHIFT = 0x1f # macro +HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK = 0x00000001 # macro +HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK = 0x00000002 # macro +HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK = 0x00000004 # macro +HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK = 0x00000008 # macro +HARD_RST_CTRL__EP_CFG_RST_EN_MASK = 0x00000010 # macro +HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK = 0x00000020 # macro +HARD_RST_CTRL__EP_PRV_RST_EN_MASK = 0x00000040 # macro +HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK = 0x00000080 # macro +HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK = 0x00000200 # macro +HARD_RST_CTRL__SION_AON_RESET_EN_MASK = 0x00000400 # macro +HARD_RST_CTRL__STRAP_RST_EN_MASK = 0x00800000 # macro +HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK = 0x10000000 # macro +HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK = 0x20000000 # macro +HARD_RST_CTRL__RELOAD_STRAP_EN_MASK = 0x40000000 # macro +HARD_RST_CTRL__CORE_RST_EN_MASK = 0x80000000 # macro +SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT = 0x0 # macro +SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT = 0x1 # macro +SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT = 0x2 # macro +SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT = 0x3 # macro +SELF_SOFT_RST__EP0_CFG_RST__SHIFT = 0x4 # macro +SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT = 0x5 # macro +SELF_SOFT_RST__EP0_PRV_RST__SHIFT = 0x6 # macro +SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT = 0x7 # macro +SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT = 0x18 # macro +SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT = 0x19 # macro +SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT = 0x1a # macro +SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT = 0x1b # macro +SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT = 0x1c # macro +SELF_SOFT_RST__CORE_STICKY_RST__SHIFT = 0x1d # macro +SELF_SOFT_RST__RELOAD_STRAP__SHIFT = 0x1e # macro +SELF_SOFT_RST__CORE_RST__SHIFT = 0x1f # macro +SELF_SOFT_RST__DSPT0_CFG_RST_MASK = 0x00000001 # macro +SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK = 0x00000002 # macro +SELF_SOFT_RST__DSPT0_PRV_RST_MASK = 0x00000004 # macro +SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK = 0x00000008 # macro +SELF_SOFT_RST__EP0_CFG_RST_MASK = 0x00000010 # macro +SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK = 0x00000020 # macro +SELF_SOFT_RST__EP0_PRV_RST_MASK = 0x00000040 # macro +SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK = 0x00000080 # macro +SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK = 0x01000000 # macro +SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK = 0x02000000 # macro +SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK = 0x04000000 # macro +SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK = 0x08000000 # macro +SELF_SOFT_RST__SWUS_SHADOW_RST_MASK = 0x10000000 # macro +SELF_SOFT_RST__CORE_STICKY_RST_MASK = 0x20000000 # macro +SELF_SOFT_RST__RELOAD_STRAP_MASK = 0x40000000 # macro +SELF_SOFT_RST__CORE_RST_MASK = 0x80000000 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT = 0x0 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT = 0x1 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT = 0x2 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT = 0x3 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT = 0x4 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT = 0x5 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT = 0x6 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT = 0x7 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK = 0x00000001 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK = 0x00000002 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK = 0x00000004 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK = 0x00000008 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK = 0x00000010 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK = 0x00000020 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK = 0x00000040 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK = 0x00000080 # macro +BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT = 0x0 # macro +BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT = 0x2 # macro +BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT = 0x4 # macro +BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT = 0x5 # macro +BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT = 0x6 # macro +BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT = 0x8 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT = 0x9 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT = 0xa # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT = 0xd # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT = 0xf # macro +BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT = 0x11 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT = 0x17 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT = 0x18 # macro +BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK = 0x00000001 # macro +BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK = 0x0000000C # macro +BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK = 0x00000010 # macro +BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK = 0x00000020 # macro +BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK = 0x00000040 # macro +BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK = 0x00000100 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK = 0x00000200 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK = 0x00001C00 # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK = 0x00006000 # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK = 0x00018000 # macro +BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK = 0x000E0000 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK = 0x00800000 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK = 0x03000000 # macro +BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT = 0x10 # macro +BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT = 0x11 # macro +BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT = 0x12 # macro +BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT = 0x1f # macro +BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK = 0x00010000 # macro +BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK = 0x00020000 # macro +BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK = 0x00040000 # macro +BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK = 0x80000000 # macro +BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT = 0x0 # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT = 0x4 # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT = 0x6 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT = 0x7 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT = 0xa # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT = 0xd # macro +BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK = 0x0000000F # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK = 0x00000030 # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK = 0x00000040 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK = 0x00000380 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK = 0x00001C00 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK = 0x0000E000 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT = 0x5 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT = 0x6 # macro +DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT = 0x7 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT = 0x8 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT = 0x9 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT = 0xa # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT = 0xb # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT = 0xc # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT = 0xd # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT = 0xe # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT = 0xf # macro +DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT = 0x10 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT = 0x11 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT = 0x12 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT = 0x17 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT = 0x19 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT = 0x1f # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK = 0x00000020 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK = 0x00000040 # macro +DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK = 0x00000080 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK = 0x00000100 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK = 0x00000200 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK = 0x00000400 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK = 0x00000800 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK = 0x00001000 # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK = 0x00002000 # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK = 0x00004000 # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK = 0x00008000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK = 0x00010000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK = 0x00020000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK = 0x001C0000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK = 0x01800000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK = 0x06000000 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK = 0x80000000 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT = 0x11 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT = 0x12 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT = 0x17 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT = 0x19 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK = 0x00020000 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK = 0x001C0000 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK = 0x01800000 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK = 0x06000000 # macro +DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT = 0x11 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT = 0x12 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT = 0x17 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT = 0x19 # macro +DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK = 0x00020000 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK = 0x001C0000 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK = 0x01800000 # macro +DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK = 0x06000000 # macro +DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT = 0x11 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT = 0x12 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT = 0x17 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT = 0x19 # macro +DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK = 0x00020000 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK = 0x001C0000 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK = 0x01800000 # macro +DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK = 0x06000000 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT = 0x0 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT = 0x1 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT = 0x2 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT = 0x3 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT = 0x4 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK = 0x00000001 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK = 0x00000002 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK = 0x00000004 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK = 0x00000008 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK = 0x00000010 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT = 0x0 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT = 0x1 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT = 0x2 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT = 0x3 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK = 0x00000001 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK = 0x00000002 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK = 0x00000004 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK = 0x00000008 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT = 0x0 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT = 0x1 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT = 0x2 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT = 0x3 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK = 0x00000001 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK = 0x00000002 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK = 0x00000004 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK = 0x00000008 # macro +BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT = 0x0 # macro +BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT = 0x10 # macro +BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK = 0x00000001 # macro +BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK = 0x00010000 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT = 0x0 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT = 0x1 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT = 0x2 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT = 0x3 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT = 0x4 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT = 0x5 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT = 0x6 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT = 0x7 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK = 0x00000001 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK = 0x00000002 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK = 0x00000004 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK = 0x00000008 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK = 0x00000010 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK = 0x00000020 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK = 0x00000040 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK = 0x00000080 # macro +SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT = 0x0 # macro +SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT = 0x1 # macro +SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT = 0x2 # macro +SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT = 0x3 # macro +SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT = 0x4 # macro +SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT = 0x5 # macro +SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT = 0x6 # macro +SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT = 0x7 # macro +SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT = 0x18 # macro +SELF_SOFT_RST_2__STRAP_RST__SHIFT = 0x19 # macro +SELF_SOFT_RST_2__NBIF_S5_RST__SHIFT = 0x1e # macro +SELF_SOFT_RST_2__NBIF_S5_CDC_RST__SHIFT = 0x1f # macro +SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK = 0x00000001 # macro +SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK = 0x00000002 # macro +SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK = 0x00000004 # macro +SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK = 0x00000008 # macro +SELF_SOFT_RST_2__EP3_CFG_RST_MASK = 0x00000010 # macro +SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK = 0x00000020 # macro +SELF_SOFT_RST_2__EP3_PRV_RST_MASK = 0x00000040 # macro +SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK = 0x00000080 # macro +SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK = 0x01000000 # macro +SELF_SOFT_RST_2__STRAP_RST_MASK = 0x02000000 # macro +SELF_SOFT_RST_2__NBIF_S5_RST_MASK = 0x40000000 # macro +SELF_SOFT_RST_2__NBIF_S5_CDC_RST_MASK = 0x80000000 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT = 0x0 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT = 0x1 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT = 0x2 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT = 0x3 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT = 0x4 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK = 0x00000001 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK = 0x00000002 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK = 0x00000004 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK = 0x00000008 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK = 0x00000010 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT = 0x0 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT = 0x1 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT = 0x2 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT = 0x3 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK = 0x00000001 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK = 0x00000002 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK = 0x00000004 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK = 0x00000008 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT = 0x0 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT = 0x1 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT = 0x2 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT = 0x3 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK = 0x00000001 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK = 0x00000002 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK = 0x00000004 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK = 0x00000008 # macro +BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT = 0x0 # macro +BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT = 0x10 # macro +BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK = 0x00000001 # macro +BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK = 0x00010000 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT = 0x0 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT = 0x1 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT = 0x2 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT = 0x3 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT = 0x4 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT = 0x5 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT = 0x6 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT = 0x7 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK = 0x00000001 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK = 0x00000002 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK = 0x00000004 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK = 0x00000008 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK = 0x00000010 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK = 0x00000020 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK = 0x00000040 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK = 0x00000080 # macro +BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT = 0x0 # macro +BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT = 0x1 # macro +BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT = 0x2 # macro +BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT = 0x3 # macro +BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK = 0x00000001 # macro +BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK = 0x00000002 # macro +BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK = 0x00000004 # macro +BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK = 0x00000008 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT = 0x2 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK = 0x00000004 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT = 0x2 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK = 0x00000004 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT = 0x2 # macro +BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK = 0x00000004 # macro +BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT = 0x2 # macro +BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK = 0x00000004 # macro +BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT = 0x0 # macro +REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK = 0x7F # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT = 0x0 # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT = 0x1 # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK = 0x00000001 # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK = 0x00000002 # macro +MISC_SCRATCH__MISC_SCRATCH0__SHIFT = 0x0 # macro +MISC_SCRATCH__MISC_SCRATCH0_MASK = 0xFFFFFFFF # macro +INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT = 0x0 # macro +INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK = 0x000000FF # macro +INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT = 0x0 # macro +INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK = 0x000000FF # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT = 0x0 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT = 0x2 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT = 0x4 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT = 0x6 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT = 0x8 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT = 0xa # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT = 0xc # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT = 0xe # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT = 0x10 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT = 0x18 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT = 0x1a # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT = 0x1c # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK = 0x00000003 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK = 0x0000000C # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK = 0x00000030 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK = 0x000000C0 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK = 0x00000300 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK = 0x00000C00 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK = 0x00003000 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK = 0x0000C000 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK = 0x000F0000 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK = 0x03000000 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK = 0x0C000000 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK = 0xF0000000 # macro +BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT = 0x4 # macro +BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT = 0x8 # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT = 0x9 # macro +BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT = 0xa # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT = 0xb # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT = 0xc # macro +BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT = 0xd # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT = 0xe # macro +BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT = 0xf # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT = 0x10 # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT = 0x11 # macro +BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT = 0x12 # macro +BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT = 0x13 # macro +BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT = 0x14 # macro +BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT = 0x15 # macro +BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT = 0x16 # macro +BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT = 0x17 # macro +BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT = 0x18 # macro +BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT = 0x19 # macro +BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT = 0x1a # macro +BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT = 0x1b # macro +BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT = 0x1c # macro +BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT = 0x1e # macro +BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT = 0x1f # macro +BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK = 0x000000F0 # macro +BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK = 0x00000100 # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK = 0x00000200 # macro +BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK = 0x00000400 # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK = 0x00000800 # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK = 0x00001000 # macro +BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK = 0x00002000 # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK = 0x00004000 # macro +BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK = 0x00008000 # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK = 0x00010000 # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK = 0x00020000 # macro +BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK = 0x00040000 # macro +BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK = 0x00080000 # macro +BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK = 0x00100000 # macro +BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK = 0x00200000 # macro +BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK = 0x00400000 # macro +BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK = 0x00800000 # macro +BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK = 0x01000000 # macro +BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK = 0x02000000 # macro +BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK = 0x04000000 # macro +BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK = 0x08000000 # macro +BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK = 0x10000000 # macro +BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK = 0x40000000 # macro +BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK = 0x80000000 # macro +BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT = 0x0 # macro +BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT = 0x1 # macro +BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT = 0x2 # macro +BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT = 0x3 # macro +BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT = 0x4 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT = 0x5 # macro +BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT = 0x6 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT = 0x7 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT = 0x8 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT = 0xa # macro +BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT = 0xc # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT = 0xd # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT = 0xe # macro +BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT = 0xf # macro +BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT = 0x10 # macro +BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT = 0x11 # macro +BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT = 0x12 # macro +BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT = 0x13 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT = 0x14 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT = 0x15 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT = 0x16 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT = 0x17 # macro +BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT = 0x18 # macro +BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT = 0x19 # macro +BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT = 0x1a # macro +BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT = 0x1b # macro +BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT = 0x1c # macro +BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT = 0x1d # macro +BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT = 0x1e # macro +BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK = 0x00000001 # macro +BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK = 0x00000002 # macro +BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK = 0x00000004 # macro +BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK = 0x00000008 # macro +BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK = 0x00000010 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK = 0x00000020 # macro +BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK = 0x00000040 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK = 0x00000080 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK = 0x00000300 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK = 0x00000C00 # macro +BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK = 0x00001000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK = 0x00002000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK = 0x00004000 # macro +BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK = 0x00008000 # macro +BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK = 0x00010000 # macro +BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK = 0x00020000 # macro +BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK = 0x00040000 # macro +BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK = 0x00080000 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK = 0x00100000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK = 0x00200000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK = 0x00400000 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK = 0x00800000 # macro +BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK = 0x01000000 # macro +BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK = 0x02000000 # macro +BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK = 0x04000000 # macro +BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK = 0x08000000 # macro +BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK = 0x10000000 # macro +BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK = 0x20000000 # macro +BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK = 0xC0000000 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT = 0x0 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT = 0x1 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2__SHIFT = 0x2 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3__SHIFT = 0x3 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT = 0x10 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT = 0x11 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT = 0x12 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT = 0x13 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK = 0x00000001 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK = 0x00000002 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2_MASK = 0x00000004 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3_MASK = 0x00000008 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK = 0x00010000 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK = 0x00020000 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK = 0x00040000 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK = 0x00080000 # macro +BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT = 0x0 # macro +BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT = 0x10 # macro +BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK = 0x0000FFFF # macro +BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK = 0xFFFF0000 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT = 0x0 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT = 0x1 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT = 0x2 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT = 0x3 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT = 0x10 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT = 0x11 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT = 0x12 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT = 0x13 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK = 0x00000001 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK = 0x00000002 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK = 0x00000004 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK = 0x00000008 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK = 0x00010000 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK = 0x00020000 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK = 0x00040000 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK = 0x00080000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT = 0xc # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK = 0x00000001 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK = 0x00000010 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK = 0x00000100 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK = 0x00001000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK = 0x00010000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK = 0x00100000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK = 0x01000000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK = 0x10000000 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT = 0x0 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT = 0x2 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT = 0x4 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT = 0x6 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT = 0x8 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT = 0xa # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT = 0xc # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT = 0xe # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK = 0x00000003 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK = 0x0000000C # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK = 0x00000030 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK = 0x000000C0 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK = 0x00000300 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK = 0x00000C00 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK = 0x00003000 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK = 0x0000C000 # macro +BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT = 0x0 # macro +BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT = 0x8 # macro +BIFC_HSTARB_CNTL__SLVARB_MODE_MASK = 0x00000003 # macro +BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK = 0x00000100 # macro +BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT = 0x0 # macro +BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT = 0x2 # macro +BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT = 0x5 # macro +BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT = 0x6 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT = 0x7 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT = 0x8 # macro +BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT = 0x9 # macro +BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT = 0xa # macro +BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT = 0xc # macro +BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT = 0xe # macro +BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT = 0xf # macro +BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT = 0x10 # macro +BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT = 0x11 # macro +BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT = 0x1b # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT = 0x1c # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT = 0x1d # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT = 0x1e # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT = 0x1f # macro +BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK = 0x00000003 # macro +BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK = 0x0000001C # macro +BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK = 0x00000020 # macro +BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK = 0x00000040 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK = 0x00000080 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK = 0x00000100 # macro +BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK = 0x00000200 # macro +BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK = 0x00000C00 # macro +BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK = 0x00003000 # macro +BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK = 0x00004000 # macro +BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK = 0x00008000 # macro +BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK = 0x00010000 # macro +BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK = 0x00020000 # macro +BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK = 0x08000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK = 0x10000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK = 0x20000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK = 0x40000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK = 0x80000000 # macro +BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT = 0x0 # macro +BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT = 0x10 # macro +BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK = 0x0000FFFF # macro +BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK = 0x00010000 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT = 0x0 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT = 0x1 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT = 0x2 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT = 0x3 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK = 0x00000001 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK = 0x00000002 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK = 0x00000004 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK = 0x00000008 # macro +BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT = 0x0 # macro +BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT = 0x8 # macro +BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT = 0x10 # macro +BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT = 0x18 # macro +BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK = 0x000000FF # macro +BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK = 0x0000FF00 # macro +BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK = 0x00FF0000 # macro +BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK = 0xFF000000 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT = 0x0 # macro +BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT = 0x1 # macro +BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT = 0x2 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT = 0x3 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT = 0x4 # macro +BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT = 0x5 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT = 0x7 # macro +BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT = 0x8 # macro +BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT = 0x9 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK = 0x00000001 # macro +BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK = 0x00000002 # macro +BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK = 0x00000004 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK = 0x00000008 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK = 0x00000010 # macro +BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK = 0x00000020 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK = 0x00000080 # macro +BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK = 0x00000100 # macro +BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK = 0x00000200 # macro +BIFC_PASID_STS__PASID_STS__SHIFT = 0x0 # macro +BIFC_PASID_STS__PASID_STS_MASK = 0x0000000F # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT = 0x0 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT = 0x3 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT = 0x8 # macro +BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT = 0x9 # macro +BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT = 0xa # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT = 0xb # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK = 0x00000007 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK = 0x00000038 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK = 0x00000100 # macro +BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK = 0x00000200 # macro +BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK = 0x00000400 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK = 0x00000800 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT = 0x0 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT = 0x1 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT = 0x8 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT = 0x9 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT = 0x10 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT = 0x18 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK = 0x00000001 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK = 0x00000002 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK = 0x00000100 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK = 0x00000200 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK = 0x007F0000 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK = 0x7F000000 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT = 0x0 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT = 0x1 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT = 0x4 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT = 0x5 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT = 0x8 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT = 0x10 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK = 0x00000001 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK = 0x00000002 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK = 0x00000010 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK = 0x00000020 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK = 0x0000FF00 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK = 0x01FF0000 # macro +BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT = 0x0 # macro +NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK = 0x00000001 # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT = 0x0 # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT = 0x8 # macro +BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x10 # macro +BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x18 # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK = 0x000000FF # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK = 0x00000F00 # macro +BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK = 0x000F0000 # macro +BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK = 0x0F000000 # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT = 0x0 # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT = 0x8 # macro +NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT = 0xa # macro +NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT = 0xe # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK = 0x000000FF # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK = 0x00000100 # macro +NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK = 0x00003C00 # macro +NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK = 0x0000C000 # macro +NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT = 0x5 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT = 0xa # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT = 0xd # macro +NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT = 0xe # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT = 0x10 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT = 0x18 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT = 0x1e # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT = 0x1f # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK = 0x000003E0 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK = 0x00000400 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK = 0x00002000 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK = 0x00004000 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK = 0x00010000 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK = 0x3F000000 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK = 0x40000000 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK = 0x80000000 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK = 0x00000080 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK = 0x00000080 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT = 0x0 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT = 0x10 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK = 0x00000001 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK = 0x00010000 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK = 0x00000080 # macro +BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT = 0x0 # macro +BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT = 0x8 # macro +BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT = 0x10 # macro +BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK = 0x000000FF # macro +BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK = 0x0000FF00 # macro +BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK = 0x00FF0000 # macro +BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT = 0x0 # macro +BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT = 0x1 # macro +BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK = 0x00000001 # macro +BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK = 0x00000002 # macro +NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT = 0x0 # macro +NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK = 0x00000001 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT = 0x0 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT = 0x1 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT = 0x2 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT = 0x3 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT = 0x4 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT = 0x5 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT = 0x6 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT = 0x7 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK = 0x00000001 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK = 0x00000002 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK = 0x00000004 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK = 0x00000008 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK = 0x00000010 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK = 0x00000020 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK = 0x00000040 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK = 0x00000080 # macro +NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT = 0x0 # macro +NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT = 0x1 # macro +NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK = 0x00000001 # macro +NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK = 0x00000002 # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT = 0x1d # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT = 0x1e # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT = 0x1f # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK = 0x20000000 # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK = 0x40000000 # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK = 0x80000000 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT = 0x0 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT = 0x8 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT = 0x10 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT = 0x18 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK = 0x000000FF # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK = 0x0000FF00 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK = 0x00FF0000 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK = 0xFF000000 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT = 0x0 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT = 0x8 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT = 0x10 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT = 0x18 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK = 0x000000FF # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK = 0x0000FF00 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK = 0x00FF0000 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK = 0xFF000000 # macro +NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT = 0x0 # macro +NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT = 0x0 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT = 0x1 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT = 0x2 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT = 0x3 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT = 0x10 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT = 0x11 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT = 0x12 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT = 0x13 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK = 0x00000002 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK = 0x00000004 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK = 0x00000008 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK = 0x00010000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK = 0x00020000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK = 0x00040000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK = 0x00080000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT = 0x0 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT = 0x1 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT = 0x2 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT = 0x3 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT = 0x10 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT = 0x11 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT = 0x12 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT = 0x13 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK = 0x00000002 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK = 0x00000004 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK = 0x00000008 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK = 0x00010000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK = 0x00020000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK = 0x00040000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK = 0x00080000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT = 0x0 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT = 0x1 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT = 0x2 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT = 0x3 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT = 0x10 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT = 0x11 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT = 0x12 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT = 0x13 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK = 0x00000002 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK = 0x00000004 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK = 0x00000008 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK = 0x00010000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK = 0x00020000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK = 0x00040000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK = 0x00080000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT = 0x0 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT = 0x1 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT = 0x2 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT = 0x3 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT = 0x10 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT = 0x11 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT = 0x12 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT = 0x13 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK = 0x00000002 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK = 0x00000004 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK = 0x00000008 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK = 0x00010000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK = 0x00020000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK = 0x00040000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK = 0x00080000 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT = 0x0 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT = 0x1 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT = 0x10 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT = 0x11 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK = 0x00000001 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK = 0x00000002 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK = 0x00010000 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK = 0x00020000 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT = 0x0 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT = 0x1 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT = 0x2 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT = 0x3 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK = 0x00000001 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK = 0x00000002 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK = 0x00000004 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK = 0x00000008 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT = 0x0 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT = 0x1 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT = 0x2 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT = 0x3 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK = 0x00000001 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK = 0x00000002 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK = 0x00000004 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK = 0x00000008 # macro +NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT = 0x0 # macro +NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT = 0x4 # macro +NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT = 0x8 # macro +NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT = 0x10 # macro +NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT = 0x14 # macro +NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT = 0x1a # macro +NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK = 0x00000001 # macro +NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK = 0x000000F0 # macro +NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK = 0x00000100 # macro +NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK = 0x00010000 # macro +NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK = 0x00F00000 # macro +NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK = 0x0C000000 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT = 0x7 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT = 0x8 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT = 0x9 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK = 0x00000040 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK = 0x00000080 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK = 0x00000100 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK = 0x00000200 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT = 0x7 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT = 0x8 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT = 0x9 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK = 0x00000040 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK = 0x00000080 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK = 0x00000100 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK = 0x00000200 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT = 0x7 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT = 0x8 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT = 0x9 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK = 0x00000040 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK = 0x00000080 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK = 0x00000100 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK = 0x00000200 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT = 0x0 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT = 0x1 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT = 0x2 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT = 0x3 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT = 0x4 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT = 0x5 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT = 0x6 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT = 0x7 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT = 0x8 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT = 0x9 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK = 0x00000001 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK = 0x00000002 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK = 0x00000004 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK = 0x00000008 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK = 0x00000010 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK = 0x00000020 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK = 0x00000040 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK = 0x00000080 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK = 0x00000100 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK = 0x00000200 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT = 0x7 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT = 0x8 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT = 0x9 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK = 0x00000040 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK = 0x00000080 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK = 0x00000100 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK = 0x00000200 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT = 0x0 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT = 0x1 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT = 0x2 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT = 0xa # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT = 0xb # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT = 0xc # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT = 0xd # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK = 0x00000001 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK = 0x00000002 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK = 0x000003FC # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK = 0x00000400 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK = 0x00000800 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK = 0x00001000 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK = 0x00002000 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT = 0x0 # macro +NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT = 0x1 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT = 0x10 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK = 0x00000001 # macro +NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK = 0x00000002 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK = 0xFFFF0000 # macro +SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT = 0x0 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT = 0x8 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT = 0x9 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT = 0xa # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT = 0xb # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT = 0x10 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT = 0x14 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT = 0x18 # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT = 0x1c # macro +SMN_MST_CNTL0__SMN_ARB_MODE_MASK = 0x00000003 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK = 0x00000100 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK = 0x00000200 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK = 0x00000400 # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK = 0x00000800 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK = 0x00010000 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK = 0x00100000 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK = 0x01000000 # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK = 0x10000000 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK = 0x00000080 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK = 0x01000000 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK = 0x01000000 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK = 0x01000000 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK = 0x01000000 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT = 0x1 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT = 0x8 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT = 0x10 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK = 0x00000001 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK = 0x00000002 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK = 0x00000700 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK = 0xFFFF0000 # macro +NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK = 0xFFFFFFFF # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT = 0x8 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT = 0xc # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT = 0x10 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT = 0x14 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT = 0x18 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT = 0x1c # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK = 0x00000F00 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK = 0x0000F000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK = 0x000F0000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK = 0x00F00000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK = 0x0F000000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK = 0xF0000000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT = 0x8 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT = 0xc # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT = 0x10 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT = 0x14 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT = 0x18 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT = 0x1c # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK = 0x00000F00 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK = 0x0000F000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK = 0x000F0000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK = 0x00F00000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK = 0x0F000000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK = 0xF0000000 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT = 0x8 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT = 0xc # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT = 0x10 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT = 0x14 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT = 0x18 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT = 0x1c # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK = 0x00000F00 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK = 0x0000F000 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK = 0x000F0000 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK = 0x00F00000 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK = 0x0F000000 # macro +BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK = 0xF0000000 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT = 0x8 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT = 0xc # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT = 0x10 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT = 0x14 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT = 0x18 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT = 0x1c # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK = 0x00000F00 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK = 0x0000F000 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK = 0x000F0000 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK = 0x00F00000 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK = 0x0F000000 # macro +BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK = 0xF0000000 # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x0 # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x8 # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK = 0x0000000F # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK = 0x00000F00 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT = 0x0 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT = 0x1 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT = 0x2 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK = 0x00000001 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK = 0x00000002 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK = 0x00000004 # macro +BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS__SHIFT = 0x1b # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS__SHIFT = 0x1c # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT = 0x1d # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT = 0x1e # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT = 0x1f # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS_MASK = 0x08000000 # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS_MASK = 0x10000000 # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK = 0x20000000 # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK = 0x40000000 # macro +BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK = 0x80000000 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT = 0x0 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT = 0x1 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT = 0x2 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT = 0x3 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT = 0x1d # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT = 0x1e # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT = 0x1f # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK = 0x00000001 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK = 0x00000002 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK = 0x00000004 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK = 0x00000008 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK = 0x20000000 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK = 0x40000000 # macro +BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK = 0x80000000 # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT = 0x1 # macro +BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT = 0x2 # macro +BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT = 0x4 # macro +BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT = 0x10 # macro +BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK = 0x00000002 # macro +BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK = 0x00000004 # macro +BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK = 0x00000010 # macro +BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK = 0x00010000 # macro +BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT = 0x1 # macro +BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT = 0x2 # macro +BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT = 0x4 # macro +BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT = 0x10 # macro +BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK = 0x00000002 # macro +BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK = 0x00000004 # macro +BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK = 0x00000010 # macro +BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK = 0x00010000 # macro +BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT = 0x1 # macro +BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT = 0x2 # macro +BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT = 0x4 # macro +BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT = 0x10 # macro +BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK = 0x00000002 # macro +BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK = 0x00000004 # macro +BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK = 0x00000010 # macro +BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK = 0x00010000 # macro +BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT = 0x1 # macro +BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT = 0x2 # macro +BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT = 0x4 # macro +BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT = 0x10 # macro +BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK = 0x00000002 # macro +BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK = 0x00000004 # macro +BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK = 0x00000010 # macro +BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK = 0x00010000 # macro +BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT = 0x0 # macro +BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT = 0x1 # macro +BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT = 0x2 # macro +BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK = 0x00000001 # macro +BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK = 0x00000002 # macro +BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK = 0x00000004 # macro +BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT = 0x0 # macro +BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT = 0x1 # macro +BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT = 0x2 # macro +BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK = 0x00000001 # macro +BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK = 0x00000002 # macro +BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK = 0x00000004 # macro +BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT = 0x0 # macro +BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT = 0x1 # macro +BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT = 0x2 # macro +BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK = 0x00000001 # macro +BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK = 0x00000002 # macro +BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK = 0x00000004 # macro +BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT = 0x0 # macro +BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT = 0x1 # macro +BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT = 0x2 # macro +BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK = 0x00000001 # macro +BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK = 0x00000002 # macro +BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK = 0x00000004 # macro +BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT = 0x0 # macro +BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK = 0x00000001 # macro +BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT = 0x0 # macro +BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK = 0x00000001 # macro +RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT = 0x7 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK = 0x00000080 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT = 0x19 # macro +RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK = 0x06000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT = 0x8 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK = 0x00000100 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT = 0x12 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT = 0x13 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK = 0x00040000 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK = 0x00080000 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT = 0x9 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0x15 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK = 0x00000200 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00200000 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT = 0xa # macro +RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK = 0x00000400 # macro +RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT = 0x6 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK = 0x00000008 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK = 0x00000040 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT = 0x6 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK = 0x00000008 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK = 0x00000040 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK = 0x00000080 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT = 0x6 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT = 0xa # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT = 0xd # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT = 0xe # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT = 0xf # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT = 0x10 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT = 0x11 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK = 0x00000007 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK = 0x00000038 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK = 0x00000040 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK = 0x00000380 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK = 0x00001C00 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK = 0x00002000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK = 0x00004000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK = 0x00008000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK = 0x00010000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK = 0x00020000 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0xFF # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK = 0x001F # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK = 0x0100 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK = 0x1F # macro +RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT = 0xa # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT = 0xc # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT = 0x19 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK = 0x00000C00 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK = 0x00003000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK = 0x01000000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK = 0x02000000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK = 0x00000007 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK = 0x000000F8 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK = 0x0000FF00 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0x19 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0x1a # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT = 0x1b # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT = 0x1c # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT = 0x1d # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT = 0x1e # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT = 0x1f # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x01000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x02000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x04000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK = 0x08000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK = 0x10000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK = 0x20000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK = 0x40000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK = 0x80000000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT = 0xf # macro +RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK = 0x00008000 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT = 0x4 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK = 0x00000002 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK = 0x00000010 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT = 0x4 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT = 0x5 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT = 0xb # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT = 0x12 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT = 0x19 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK = 0x00000002 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK = 0x00000010 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK = 0x000007E0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK = 0x0003F800 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK = 0x01FC0000 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK = 0xFE000000 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT = 0x6 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT = 0xc # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK = 0x0000003F # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK = 0x00000FC0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK = 0x0001F000 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK = 0x00FE0000 # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK = 0x0000000F # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK = 0x000000F0 # macro +RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK = 0xFFFF # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT = 0x4 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT = 0x5 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT = 0x6 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT = 0x7 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT = 0xc # macro +RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT = 0xd # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x12 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x13 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x14 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x15 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT = 0x18 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT = 0x19 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT = 0x1c # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT = 0x1d # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK = 0x00000010 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK = 0x00000020 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK = 0x00000040 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK = 0x00000080 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK = 0x00000100 # macro +RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK = 0x00001000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK = 0x00002000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00010000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00020000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00040000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00080000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00100000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00200000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK = 0x01000000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK = 0x0E000000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK = 0x10000000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK = 0xE0000000 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK = 0x00000018 # macro +RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK = 0x07FFFFFF # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT = 0x7 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT = 0x9 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT = 0xa # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT = 0xb # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT = 0xc # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT = 0xd # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT = 0xe # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT = 0xf # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT = 0x12 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT = 0x13 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK = 0x00000080 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK = 0x00000100 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK = 0x00000200 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK = 0x00000400 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK = 0x00000800 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK = 0x00001000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK = 0x00002000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK = 0x00004000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK = 0x00008000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK = 0x00010000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK = 0x00020000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK = 0x00040000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK = 0x00080000 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK = 0xFF000000 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK = 0xFF000000 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK = 0x0000FFFF # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK = 0xFF000000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK = 0xFF000000 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK = 0x00000100 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK = 0x00010000 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK = 0x00020000 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK = 0x00000002 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK = 0xFFFF0000 # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK = 0x000000FF # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK = 0x00001F00 # macro +RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK = 0x00007FFE # macro +BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT = 0x0 # macro +BIF_BX1_PCIE_DATA__PCIE_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT = 0x0 # macro +BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK = 0x000000FF # macro +BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK = 0x000000FF # macro +BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK = 0x000000FF # macro +BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT = 0x19 # macro +BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK = 0xFE000000 # macro +BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT = 0x1 # macro +BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK = 0x00000002 # macro +BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT = 0x6 # macro +BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT = 0x7 # macro +BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT = 0xa # macro +BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT = 0xd # macro +BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT = 0x10 # macro +BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT = 0x11 # macro +BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT = 0x12 # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT = 0x18 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT = 0x19 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT = 0x1a # macro +BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT = 0x1b # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT = 0x1c # macro +BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT = 0x1d # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT = 0x1e # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT = 0x1f # macro +BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK = 0x00000040 # macro +BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK = 0x00000080 # macro +BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK = 0x00001C00 # macro +BIF_BX1_BUS_CNTL__SET_MC_TC_MASK = 0x0000E000 # macro +BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK = 0x00010000 # macro +BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK = 0x00020000 # macro +BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK = 0x00040000 # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK = 0x01000000 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK = 0x02000000 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK = 0x04000000 # macro +BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK = 0x08000000 # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK = 0x10000000 # macro +BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK = 0x20000000 # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK = 0x40000000 # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK = 0x80000000 # macro +BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT = 0x0 # macro +BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT = 0x0 # macro +BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK = 0xFFFFFFFF # macro +BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT = 0x10 # macro +BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK = 0x00010000 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT = 0x0 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT = 0x6 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT = 0x1f # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK = 0x00000007 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK = 0x000000C0 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK = 0x80000000 # macro +BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT = 0x0 # macro +BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK = 0x00000001 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT = 0x0 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT = 0x1 # macro +BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT = 0x3 # macro +BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT = 0x4 # macro +BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT = 0x8 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT = 0xf # macro +BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT = 0x10 # macro +BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT = 0x11 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT = 0x12 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK = 0x00000001 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK = 0x00000002 # macro +BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK = 0x00000008 # macro +BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK = 0x000000F0 # macro +BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK = 0x00000100 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK = 0x00008000 # macro +BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK = 0x00010000 # macro +BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK = 0x00020000 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK = 0x00040000 # macro +BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT = 0x0 # macro +BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT = 0x0 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT = 0x1 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT = 0x2 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT = 0x3 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT = 0x5 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT = 0x6 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT = 0x7 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT = 0x8 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT = 0x9 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT = 0xa # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT = 0xb # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT = 0xc # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT = 0xd # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK = 0x00000001 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK = 0x00000002 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK = 0x00000004 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK = 0x00000018 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK = 0x00000020 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK = 0x00000040 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK = 0x00000080 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK = 0x00000100 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK = 0x00000200 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK = 0x00000400 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK = 0x00000800 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK = 0x00001000 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK = 0x00002000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT = 0x0 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT = 0x1 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT = 0x2 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT = 0x3 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT = 0xb # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT = 0xc # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT = 0xd # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT = 0xf # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT = 0x10 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT = 0x19 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK = 0x00000001 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK = 0x00000002 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK = 0x00000004 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK = 0x00000008 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK = 0x00000800 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK = 0x00001000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK = 0x00002000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK = 0x00008000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK = 0x01FF0000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK = 0x02000000 # macro +BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT = 0x0 # macro +BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK = 0x000000FF # macro +BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT = 0x0 # macro +BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT = 0x1 # macro +BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT = 0x2 # macro +BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT = 0x3 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT = 0x4 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT = 0x18 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT = 0x19 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT = 0x1a # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT = 0x1b # macro +BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK = 0x00000001 # macro +BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK = 0x00000002 # macro +BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK = 0x00000004 # macro +BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK = 0x00000008 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK = 0x00000010 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK = 0x01000000 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK = 0x02000000 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK = 0x04000000 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK = 0x08000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT = 0x0 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT = 0x1 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT = 0x2 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT = 0x10 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT = 0x11 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT = 0x12 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x17 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT = 0x18 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT = 0x19 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT = 0x1a # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1c # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1d # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1e # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x1f # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK = 0x00000001 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK = 0x00000002 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK = 0x00000004 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK = 0x00010000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK = 0x00020000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK = 0x00040000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x00800000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK = 0x01000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK = 0x02000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK = 0x04000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x10000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x20000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x40000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x80000000 # macro +BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT = 0x0 # macro +BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT = 0x1 # macro +BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK = 0x00000001 # macro +BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK = 0x00000002 # macro +BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT = 0x0 # macro +BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK = 0x00000001 # macro +BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT = 0x0 # macro +BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK = 0x00000001 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT = 0x1 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT = 0x8 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK = 0x00000001 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK = 0x00000002 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK = 0x00000100 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT = 0x1f # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK = 0x80000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK = 0x40000000 # macro +BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT = 0x8 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT = 0x9 # macro +BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT = 0x11 # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT = 0x1a # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT = 0x1d # macro +BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT = 0x1e # macro +BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT = 0x1f # macro +BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK = 0x00000100 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK = 0x00003E00 # macro +BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK = 0x00020000 # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK = 0x1C000000 # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK = 0x20000000 # macro +BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK = 0x40000000 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK = 0x80000000 # macro +BIF_BX1_BIF_RB_BASE__ADDR__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX1_BIF_RB_RPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK = 0x00000001 # macro +BIF_BX1_BIF_RB_WPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK = 0x000000FF # macro +BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT = 0x0 # macro +BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK = 0x0000001F # macro +BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT = 0x0 # macro +BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK = 0x00000001 # macro +BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK = 0x0000FFFF # macro +BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK = 0x00000FFF # macro +BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK = 0x000000FF # macro +BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK = 0x7FFFFFFF # macro +BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK = 0x000000FF # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT = 0x0 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT = 0x1 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT = 0x2 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT = 0x3 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT = 0x4 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT = 0x5 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT = 0x6 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT = 0x7 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK = 0x00000001 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK = 0x00000002 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK = 0x00000004 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK = 0x00000008 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK = 0x00000010 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK = 0x00000020 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK = 0x00000040 # macro +BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK = 0x00000080 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT = 0x0 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT = 0x1 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT = 0x2 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT = 0x3 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT = 0x4 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT = 0x5 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK = 0x00000001 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK = 0x00000002 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK = 0x00000004 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK = 0x00000008 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK = 0x00000010 # macro +BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK = 0x00000020 # macro +BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT = 0x0 # macro +BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT = 0x1 # macro +BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK = 0x00000001 # macro +BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK = 0xFFFFFFFE # macro +BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT = 0x0 # macro +BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT = 0x0 # macro +BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT = 0xa # macro +BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK = 0x000003FF # macro +BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK = 0x00000400 # macro +BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT = 0x0 # macro +BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT = 0xa # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT = 0xb # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT = 0xc # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT = 0xd # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0xe # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0xf # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK = 0x00000038 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK = 0x00000200 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK = 0x00000400 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK = 0x00000800 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK = 0x00002000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK = 0x000C0000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK = 0x02000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT = 0xa # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT = 0xc # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT = 0xd # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT = 0xf # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK = 0x00000200 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK = 0x00000C00 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK = 0x00006000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK = 0x00018000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK = 0x02000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK = 0x18000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT = 0xa # macro +RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT = 0xd # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT = 0xe # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT = 0xf # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK = 0x00000200 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK = 0x00000C00 # macro +RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK = 0x00002000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK = 0x00C00000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x06000000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK = 0x0E000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK = 0x0007FFC0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK = 0x0FFF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK = 0x00FFFFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK = 0x000FFE00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK = 0xFFF00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT = 0xd # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT = 0xf # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK = 0x00000E00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK = 0x00002000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK = 0x00700000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK = 0x03800000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK = 0x1C000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0xb # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK = 0x00000038 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK = 0x00000600 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x00003800 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x0003C000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x001C0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x01E00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK = 0x06000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK = 0x18000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK = 0x02000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK = 0x00030000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x0F000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0xF0000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK = 0x1F000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK = 0x000F0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK = 0x00F00000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK = 0xFF000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK = 0x3E000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK = 0x01FFE000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT = 0xf # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK = 0x00003E00 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK = 0x07000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK = 0x00E00000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT = 0xa # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK = 0x000003FF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK = 0x00000400 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK = 0x0F800000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00000007 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK = 0x00000070 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK = 0x00001E00 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK = 0x0000E000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00070000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK = 0x00780000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK = 0x03800000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK = 0x38000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK = 0xC0000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK = 0x00C00000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK = 0x000F0000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK = 0x00F00000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK = 0x00003E00 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK = 0x07000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK = 0x0F800000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK = 0x00000004 # macro +GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT = 0x0 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT = 0x1 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT = 0x2 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT = 0x3 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT = 0x4 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT = 0x5 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT = 0x6 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT = 0x7 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT = 0x8 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT = 0x9 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT = 0xa # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT = 0xb # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT = 0xc # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT = 0xd # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT = 0xe # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT = 0xf # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT = 0x10 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT = 0x11 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT = 0x12 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT = 0x13 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK = 0x00000001 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK = 0x00000002 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK = 0x00000004 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK = 0x00000008 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK = 0x00000010 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK = 0x00000020 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK = 0x00000040 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK = 0x00000080 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK = 0x00000100 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK = 0x00000200 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK = 0x00000400 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK = 0x00000800 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK = 0x00001000 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK = 0x00002000 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK = 0x00004000 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK = 0x00008000 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK = 0x00010000 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK = 0x00020000 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK = 0x00040000 # macro +GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK = 0x00080000 # macro +GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT = 0x0 # macro +GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS__SHIFT = 0x8 # macro +GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD_MASK = 0x000000FF # macro +GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS_MASK = 0x0000FF00 # macro +GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT = 0x0 # macro +GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK = 0xFFFFFFFF # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT = 0x0 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT = 0x1 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT = 0x2 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT = 0x3 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT = 0x4 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT = 0x5 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT = 0x6 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT = 0x7 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT = 0x8 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT = 0x9 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT = 0xa # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT = 0xb # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT = 0xc # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT = 0xd # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT = 0xe # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT = 0xf # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT = 0x10 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT = 0x11 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT = 0x12 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT = 0x13 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK = 0x00000001 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK = 0x00000002 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK = 0x00000004 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK = 0x00000008 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK = 0x00000010 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK = 0x00000020 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK = 0x00000040 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK = 0x00000080 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK = 0x00000100 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK = 0x00000200 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK = 0x00000400 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK = 0x00000800 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK = 0x00001000 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK = 0x00002000 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK = 0x00004000 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK = 0x00008000 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK = 0x00010000 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK = 0x00020000 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK = 0x00040000 # macro +GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK = 0x00080000 # macro +GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT = 0x0 # macro +GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS__SHIFT = 0x8 # macro +GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD_MASK = 0x000000FF # macro +GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS_MASK = 0x0000FF00 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT = 0x0 # macro +S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK = 0x00000001 # macro +GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT = 0x0 # macro +GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK = 0x00000001 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT = 0x0 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT = 0x1 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT = 0x2 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT = 0xa # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT = 0xb # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT = 0xc # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT = 0xd # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK = 0x00000001 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK = 0x00000002 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK = 0x000003FC # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK = 0x00000400 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK = 0x00000800 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK = 0x00001000 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK = 0x00002000 # macro +GDC1_NGDC_RESERVED_0__RESERVED__SHIFT = 0x0 # macro +GDC1_NGDC_RESERVED_0__RESERVED_MASK = 0xFFFFFFFF # macro +GDC1_NGDC_RESERVED_1__RESERVED__SHIFT = 0x0 # macro +GDC1_NGDC_RESERVED_1__RESERVED_MASK = 0xFFFFFFFF # macro +GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT = 0x0 # macro +GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK = 0x0000FFFF # macro +GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT = 0x0 # macro +GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0x1 # macro +GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT = 0x2 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT = 0x8 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT = 0x10 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT = 0x18 # macro +GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK = 0x00000001 # macro +GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000002 # macro +GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK = 0x0000000C # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK = 0x0000FF00 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK = 0x00FF0000 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK = 0xFF000000 # macro +GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT = 0x8 # macro +GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT = 0xa # macro +GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT = 0xc # macro +GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT = 0xf # macro +GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT = 0x10 # macro +GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK = 0x00000300 # macro +GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK = 0x00000C00 # macro +GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK = 0x00003000 # macro +GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK = 0x00008000 # macro +GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK = 0x000F0000 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT = 0x0 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT = 0x1 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT = 0x2 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK = 0x00000001 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK = 0x00000002 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK = 0x00000004 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT = 0xa # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT = 0xd # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT = 0xe # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT = 0x10 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT = 0x18 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT = 0x1f # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK = 0x00000400 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK = 0x00002000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK = 0x00004000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK = 0x00010000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK = 0x3F000000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK = 0x80000000 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT = 0x0 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT = 0x8 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT = 0xa # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT = 0xe # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK = 0x000000FF # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK = 0x00000100 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK = 0x00003C00 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK = 0x0000C000 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT = 0x5 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT = 0xa # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK = 0x000003E0 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK = 0x00007C00 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT = 0x0 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT = 0x1 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT = 0x2 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT = 0x3 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT = 0x4 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT = 0x5 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK = 0x00000001 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK = 0x00000002 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK = 0x00000004 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK = 0x00000008 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK = 0x00000010 # macro +GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK = 0x00000020 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT = 0x0 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT = 0x1 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT = 0x2 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT = 0x3 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK = 0x00000001 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK = 0x00000002 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK = 0x00000004 # macro +GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK = 0x00000008 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT = 0x4 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK = 0x00000010 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT = 0x4 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK = 0x00000010 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT = 0x4 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT = 0x10 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK = 0x00000010 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK = 0x00010000 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT = 0x4 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK = 0x00000010 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT = 0x3 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT = 0x4 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT = 0x5 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT = 0x6 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT = 0x11 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT = 0x12 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT = 0x13 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT = 0x14 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK = 0x00000008 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK = 0x00000010 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK = 0x00000020 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK = 0x00000040 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA_MASK = 0x00020000 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA_MASK = 0x00040000 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK = 0x00080000 # macro +GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK = 0x00100000 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK__SHIFT = 0xc # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP__SHIFT = 0xd # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT = 0x11 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK_MASK = 0x00001000 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP_MASK = 0x00002000 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK = 0x00020000 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT = 0x15 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK = 0x001FF800 # macro +GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK = 0x7FE00000 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT = 0x0 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT = 0x1 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT = 0x2 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT = 0x8 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT = 0x9 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT = 0xa # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT = 0xb # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK = 0x00000001 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK = 0x00000002 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK = 0x00000004 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK = 0x00000100 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK = 0x00000200 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK = 0x00000400 # macro +GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK = 0x00000800 # macro +SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT = 0x0 # macro +SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT = 0x1 # macro +SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT = 0x2 # macro +SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT = 0x3 # macro +SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK = 0x00000001 # macro +SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK = 0x00000002 # macro +SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK = 0x00000004 # macro +SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK = 0x00000008 # macro +SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT = 0x0 # macro +SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK = 0x00000001 # macro +SHUB_LINK_RESET__LINK_P0_RESET__SHIFT = 0x0 # macro +SHUB_LINK_RESET__LINK_P1_RESET__SHIFT = 0x1 # macro +SHUB_LINK_RESET__LINK_P2_RESET__SHIFT = 0x2 # macro +SHUB_LINK_RESET__LINK_P3_RESET__SHIFT = 0x3 # macro +SHUB_LINK_RESET__LINK_P0_RESET_MASK = 0x00000001 # macro +SHUB_LINK_RESET__LINK_P1_RESET_MASK = 0x00000002 # macro +SHUB_LINK_RESET__LINK_P2_RESET_MASK = 0x00000004 # macro +SHUB_LINK_RESET__LINK_P3_RESET_MASK = 0x00000008 # macro +SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT = 0x0 # macro +SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT = 0x1 # macro +SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT = 0x2 # macro +SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT = 0x4 # macro +SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT = 0x5 # macro +SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK = 0x00000001 # macro +SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK = 0x00000002 # macro +SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK = 0x00000004 # macro +SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK = 0x00000010 # macro +SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK = 0x00000020 # macro +SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT = 0x0 # macro +SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT = 0x1 # macro +SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT = 0x2 # macro +SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT = 0x4 # macro +SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT = 0x5 # macro +SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK = 0x00000001 # macro +SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK = 0x00000002 # macro +SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK = 0x00000004 # macro +SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK = 0x00000010 # macro +SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK = 0x00000020 # macro +SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT = 0x1 # macro +SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT = 0x2 # macro +SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT = 0x3 # macro +SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT = 0x4 # macro +SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT = 0x6 # macro +SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT = 0x7 # macro +SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT = 0x8 # macro +SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT = 0x9 # macro +SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT = 0xa # macro +SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT = 0xb # macro +SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT = 0xc # macro +SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT = 0xd # macro +SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT = 0x18 # macro +SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK = 0x00000002 # macro +SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK = 0x00000004 # macro +SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK = 0x00000008 # macro +SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK = 0x00000010 # macro +SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK = 0x00000040 # macro +SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK = 0x00000080 # macro +SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK = 0x00000100 # macro +SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK = 0x00000200 # macro +SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK = 0x00000400 # macro +SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK = 0x00000800 # macro +SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK = 0x00001000 # macro +SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK = 0x00002000 # macro +SHUB_SDP_PORT_RST__SION_AON_RST_MASK = 0x01000000 # macro +HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +PSWUSCFG0_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +PSWUSCFG0_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +PSWUSCFG0_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +PSWUSCFG0_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +PSWUSCFG0_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +PSWUSCFG0_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +PSWUSCFG0_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +PSWUSCFG0_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +PSWUSCFG0_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +PSWUSCFG0_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +PSWUSCFG0_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +PSWUSCFG0_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +PSWUSCFG0_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +PSWUSCFG0_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +PSWUSCFG0_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +PSWUSCFG0_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +PSWUSCFG0_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +PSWUSCFG0_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +PSWUSCFG0_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +PSWUSCFG0_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +PSWUSCFG0_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +PSWUSCFG0_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +PSWUSCFG0_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +PSWUSCFG0_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +PSWUSCFG0_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +PSWUSCFG0_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +PSWUSCFG0_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +PSWUSCFG0_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +PSWUSCFG0_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +PSWUSCFG0_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +PSWUSCFG0_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +PSWUSCFG0_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +PSWUSCFG0_1_BIST__BIST_COMP_MASK = 0x0F # macro +PSWUSCFG0_1_BIST__BIST_STRT_MASK = 0x40 # macro +PSWUSCFG0_1_BIST__BIST_CAP_MASK = 0x80 # macro +PSWUSCFG0_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +PSWUSCFG0_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +PSWUSCFG0_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +PSWUSCFG0_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +PSWUSCFG0_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +PSWUSCFG0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +PSWUSCFG0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +PSWUSCFG0_1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +PSWUSCFG0_1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +PSWUSCFG0_1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +PSWUSCFG0_1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +PSWUSCFG0_1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +PSWUSCFG0_1_PMI_CAP__VERSION_MASK = 0x0007 # macro +PSWUSCFG0_1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +PSWUSCFG0_1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +PSWUSCFG0_1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +PSWUSCFG0_1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +PSWUSCFG0_1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +PSWUSCFG0_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +PSWUSCFG0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +PSWUSCFG0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT = 0xf # macro +PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK = 0x8000 # macro +PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +PSWUSCFG0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +PSWUSCFG0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +PSWUSCFG0_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +PSWUSCFG0_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +PSWUSCFG0_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +PSWUSCFG0_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +PSWUSCFG0_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +PSWUSCFG0_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +PSWUSCFG0_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +PSWUSCFG0_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +PSWUSCFG0_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +PSWUSCFG0_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +PSWUSCFG0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +PSWUSCFG0_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +PSWUSCFG0_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +PSWUSCFG0_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +PSWUSCFG0_1_MSI_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x10 # macro +PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_MSI_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF0000 # macro +PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x10 # macro +PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF0000 # macro +PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK = 0x000F # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK = 0x0F00 # macro +PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK = 0x7000 # macro +PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +PSWUSCFG0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT = 0x1 # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK = 0x00000001 # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK = 0x007FFFFE # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PSWUSCFG0_1_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED__SHIFT = 0x8 # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED__SHIFT = 0x9 # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED__SHIFT = 0xa # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +PSWUSCFG0_1_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +PSWUSCFG0_1_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED_MASK = 0x00000100 # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED_MASK = 0x00000200 # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED_MASK = 0x00000400 # macro +PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +PSWUSCFG0_1_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE__SHIFT = 0x1 # macro +PSWUSCFG0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED__SHIFT = 0x8 # macro +PSWUSCFG0_1_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE_MASK = 0x00000001 # macro +PSWUSCFG0_1_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE_MASK = 0x00000002 # macro +PSWUSCFG0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED_MASK = 0x00000700 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL__SHIFT = 0x6 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED__SHIFT = 0xa # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL_MASK = 0x000000C0 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +PSWUSCFG0_1_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED_MASK = 0x00000400 # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK = 0x00007F80 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK = 0x00018000 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK = 0xFFF80000 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK = 0x00C0 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL__INBAND_PD_DISABLE_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_AP_CAP__COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_AP_CAP__SEL_EN_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_AP_CAP__COUNT_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC1_AP_CAP__SEL_EN_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_AP_CNTL__INX_SEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_AP_CNTL__NEGO_GLOBAL_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC1_AP_CNTL__INX_SEL_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC1_AP_CNTL__NEGO_GLOBAL_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC1_AP_DATA1__USAGE_INFOR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_AP_DATA1__DETAILS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC1_AP_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_AP_DATA1__USAGE_INFOR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC1_AP_DATA1__DETAILS_MASK = 0x0000FFE0 # macro +BIF_CFG_DEV0_RC1_AP_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC1_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_AP_DATA2__MODIFIED_TS_INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__PCIE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__OTHERS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__PCIE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__OTHERS_MASK = 0xFFFFFFFE # macro +BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_RC1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_RC1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_RC1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK = 0x0000FFF8 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_AP_CAP__COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_AP_CAP__SEL_EN_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_AP_CAP__COUNT_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_AP_CAP__SEL_EN_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_AP_CNTL__INX_SEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_AP_CNTL__NEGO_GLOBAL_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_1_AP_CNTL__INX_SEL_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_1_AP_CNTL__NEGO_GLOBAL_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA1__USAGE_INFOR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA1__DETAILS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA1__VENDORID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA1__USAGE_INFOR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA1__DETAILS_MASK = 0x0000FFE0 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA1__VENDORID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_AP_DATA2__MODIFIED_TS_INFOR2_MASK = 0x00FFFFFF # macro +BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__PCIE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__OTHERS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__PCIE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__OTHERS_MASK = 0xFFFFFFFE # macro +BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF1_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK = 0x3F # macro +BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF2_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK = 0x3F # macro +BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA1__RESET_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA1__DLUP_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA1__VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA1__RESET_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA1__DLUP_TIME_MASK = 0x00FFF000 # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA1__VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME_MASK = 0x00000FFF # macro +BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME_MASK = 0x00FFF000 # macro +PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK = 0x00010000 # macro +__all__ = \ + ['ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK', + 'ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT', + 'ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK', + 'ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT', + 'ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK', + 'ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT', + 'ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK', + 'ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT', + 'ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK', + 'ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT', + 'BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK', + 'BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT', + 'BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK', + 'BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT', + 'BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK', + 'BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT', + 'BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK', + 'BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT', + 'BACO_CNTL__BACO_AUTO_EXIT_MASK', + 'BACO_CNTL__BACO_AUTO_EXIT__SHIFT', + 'BACO_CNTL__BACO_DSTATE_BYPASS_MASK', + 'BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT', + 'BACO_CNTL__BACO_DUMMY_EN_MASK', + 'BACO_CNTL__BACO_DUMMY_EN__SHIFT', 'BACO_CNTL__BACO_EN_MASK', + 'BACO_CNTL__BACO_EN__SHIFT', 'BACO_CNTL__BACO_MODE_MASK', + 'BACO_CNTL__BACO_MODE__SHIFT', 'BACO_CNTL__BACO_POWER_OFF_MASK', + 'BACO_CNTL__BACO_POWER_OFF__SHIFT', + 'BACO_CNTL__BACO_RST_INTR_MASK_MASK', + 'BACO_CNTL__BACO_RST_INTR_MASK__SHIFT', + 'BACO_CNTL__PWRGOOD_VDDSOC_MASK', + 'BACO_CNTL__PWRGOOD_VDDSOC__SHIFT', + 'BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK', + 'BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK', + 'BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK', + 'BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2_MASK', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2__SHIFT', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3_MASK', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK', + 'BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK', + 'BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT', + 'BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK', + 'BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK', + 'BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT', + 'BIFC_HSTARB_CNTL__SLVARB_MODE_MASK', + 'BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT', + 'BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK', + 'BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT', + 'BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK', + 'BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT', + 'BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK', + 'BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT', + 'BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK', + 'BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT', + 'BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK', + 'BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT', + 'BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK', + 'BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT', + 'BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK', + 'BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT', + 'BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK', + 'BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT', + 'BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK', + 'BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT', + 'BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK', + 'BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT', + 'BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK', + 'BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT', + 'BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK', + 'BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT', + 'BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK', + 'BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT', + 'BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK', + 'BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT', + 'BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK', + 'BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT', + 'BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK', + 'BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT', + 'BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK', + 'BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT', + 'BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK', + 'BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT', + 'BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK', + 'BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT', + 'BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK', + 'BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT', + 'BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK', + 'BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK', + 'BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK', + 'BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK', + 'BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT', + 'BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK', + 'BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT', + 'BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK', + 'BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT', + 'BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK', + 'BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK', + 'BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT', + 'BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK', + 'BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT', + 'BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK', + 'BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK', + 'BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT', + 'BIFC_PASID_STS__PASID_STS_MASK', + 'BIFC_PASID_STS__PASID_STS__SHIFT', + 'BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK', + 'BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT', + 'BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK', + 'BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT', + 'BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT', + 'BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT', + 'BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK', + 'BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT', + 'BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT', + 'BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT', + 'BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK', + 'BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT', + 'BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK', + 'BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT', + 'BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK', + 'BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK', + 'BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT', + 'BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK', + 'BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS_MASK', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS__SHIFT', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS_MASK', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS__SHIFT', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK', + 'BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK', + 'BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK', + 'BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK', + 'BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK', + 'BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK', + 'BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK', + 'BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK', + 'BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT', + 'BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK', + 'BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT', + 'BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK', + 'BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK', + 'BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK', + 'BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK', + 'BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK', + 'BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK', + 'BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK', + 'BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT', + 'BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK', + 'BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT', + 'BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK', + 'BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK', + 'BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK', + 'BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK', + 'BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK', + 'BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK', + 'BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK', + 'BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT', + 'BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK', + 'BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT', + 'BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK', + 'BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK', + 'BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT', + 'BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK', + 'BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK', + 'BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK', + 'BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT', + 'BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK', + 'BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT', + 'BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK', + 'BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT', + 'BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK', + 'BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT', + 'BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK', + 'BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT', + 'BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK', + 'BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT', + 'BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK', + 'BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT', + 'BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK', + 'BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT', + 'BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK', + 'BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT', + 'BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK', + 'BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT', + 'BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK', + 'BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT', + 'BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK', + 'BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT', + 'BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK', + 'BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT', + 'BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK', + 'BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT', + 'BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK', + 'BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT', + 'BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK', + 'BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT', + 'BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK', + 'BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK', + 'BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT', + 'BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK', + 'BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT', + 'BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK', + 'BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT', + 'BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK', + 'BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT', + 'BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK', + 'BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT', + 'BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX0_BIF_RB_BASE__ADDR_MASK', + 'BIF_BX0_BIF_RB_BASE__ADDR__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK', + 'BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK', + 'BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT', + 'BIF_BX0_BIF_RB_RPTR__OFFSET_MASK', + 'BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT', + 'BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK', + 'BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT', + 'BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK', + 'BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT', + 'BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK', + 'BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT', + 'BIF_BX0_BIF_RB_WPTR__OFFSET_MASK', + 'BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT', + 'BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK', + 'BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT', + 'BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK', + 'BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT', + 'BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK', + 'BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK', + 'BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK', + 'BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK', + 'BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK', + 'BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK', + 'BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK', + 'BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK', + 'BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK', + 'BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK', + 'BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK', + 'BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK', + 'BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK', + 'BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK', + 'BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK', + 'BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK', + 'BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK', + 'BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK', + 'BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK', + 'BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT', + 'BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK', + 'BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT', + 'BIF_BX0_BUS_CNTL__SET_MC_TC_MASK', + 'BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK', + 'BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK', + 'BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK', + 'BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK', + 'BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT', + 'BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK', + 'BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT', + 'BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK', + 'BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT', + 'BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK', + 'BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK', + 'BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK', + 'BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK', + 'BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK', + 'BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK', + 'BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK', + 'BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK', + 'BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK', + 'BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK', + 'BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK', + 'BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK', + 'BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK', + 'BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK', + 'BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK', + 'BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK', + 'BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK', + 'BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT', + 'BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK', + 'BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT', + 'BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK', + 'BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT', + 'BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK', + 'BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT', + 'BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK', + 'BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT', + 'BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK', + 'BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT', + 'BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK', + 'BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT', + 'BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK', + 'BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT', + 'BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK', + 'BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT', + 'BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK', + 'BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT', + 'BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK', + 'BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT', + 'BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK', + 'BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT', + 'BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK', + 'BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT', + 'BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK', + 'BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT', + 'BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK', + 'BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT', + 'BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK', + 'BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT', + 'BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK', + 'BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT', + 'BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK', + 'BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK', + 'BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK', + 'BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK', + 'BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT', + 'BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK', + 'BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT', + 'BIF_BX0_PCIE_DATA__PCIE_DATA_MASK', + 'BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT', + 'BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK', + 'BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT', + 'BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK', + 'BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT', + 'BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK', + 'BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT', + 'BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK', + 'BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT', + 'BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK', + 'BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK', + 'BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK', + 'BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK', + 'BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK', + 'BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK', + 'BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK', + 'BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK', + 'BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK', + 'BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK', + 'BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK', + 'BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK', + 'BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK', + 'BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK', + 'BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK', + 'BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK', + 'BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT', + 'BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK', + 'BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK', + 'BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT', + 'BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK', + 'BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT', + 'BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK', + 'BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK', + 'BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT', + 'BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK', + 'BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT', + 'BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK', + 'BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT', + 'BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK', + 'BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK', + 'BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK', + 'BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_RB_BASE__ADDR_MASK', + 'BIF_BX1_BIF_RB_BASE__ADDR__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK', + 'BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK', + 'BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT', + 'BIF_BX1_BIF_RB_RPTR__OFFSET_MASK', + 'BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT', + 'BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK', + 'BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT', + 'BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK', + 'BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT', + 'BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK', + 'BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT', + 'BIF_BX1_BIF_RB_WPTR__OFFSET_MASK', + 'BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT', + 'BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK', + 'BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK', + 'BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT', + 'BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK', + 'BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT', + 'BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK', + 'BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT', + 'BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK', + 'BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT', + 'BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK', + 'BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT', + 'BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK', + 'BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT', + 'BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK', + 'BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT', + 'BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK', + 'BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK', + 'BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK', + 'BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK', + 'BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK', + 'BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK', + 'BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK', + 'BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK', + 'BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK', + 'BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK', + 'BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK', + 'BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK', + 'BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK', + 'BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK', + 'BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK', + 'BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK', + 'BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK', + 'BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK', + 'BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK', + 'BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK', + 'BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK', + 'BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK', + 'BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT', + 'BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK', + 'BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT', + 'BIF_BX1_BUS_CNTL__SET_MC_TC_MASK', + 'BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK', + 'BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK', + 'BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK', + 'BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK', + 'BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT', + 'BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK', + 'BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT', + 'BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK', + 'BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT', + 'BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK', + 'BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK', + 'BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK', + 'BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK', + 'BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK', + 'BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK', + 'BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK', + 'BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK', + 'BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK', + 'BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK', + 'BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK', + 'BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK', + 'BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK', + 'BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK', + 'BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK', + 'BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK', + 'BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK', + 'BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT', + 'BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK', + 'BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT', + 'BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK', + 'BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT', + 'BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK', + 'BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT', + 'BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK', + 'BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT', + 'BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK', + 'BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT', + 'BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK', + 'BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT', + 'BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK', + 'BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT', + 'BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK', + 'BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT', + 'BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK', + 'BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT', + 'BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK', + 'BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT', + 'BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK', + 'BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT', + 'BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK', + 'BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT', + 'BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK', + 'BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT', + 'BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK', + 'BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT', + 'BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK', + 'BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT', + 'BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK', + 'BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT', + 'BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK', + 'BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK', + 'BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK', + 'BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK', + 'BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT', + 'BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK', + 'BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT', + 'BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK', + 'BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT', + 'BIF_BX1_PCIE_DATA__PCIE_DATA_MASK', + 'BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT', + 'BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK', + 'BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT', + 'BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK', + 'BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT', + 'BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK', + 'BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT', + 'BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK', + 'BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT', + 'BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK', + 'BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT', + 'BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK', + 'BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT', + 'BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK', + 'BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK', + 'BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK', + 'BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK', + 'BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK', + 'BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK', + 'BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK', + 'BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK', + 'BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK', + 'BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK', + 'BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK', + 'BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK', + 'BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK', + 'BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK', + 'BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK', + 'BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK', + 'BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF0_MM_DATA__MM_DATA_MASK', + 'BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_PF0_MM_INDEX__MM_APER_MASK', + 'BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MM_DATA__MM_DATA_MASK', + 'BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_PF1_MM_INDEX__MM_APER_MASK', + 'BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE_MASK', + 'BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_CAP__COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_CAP__COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_CAP__SEL_EN_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_CAP__SEL_EN_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_CNTL__INX_SEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_CNTL__INX_SEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_CNTL__NEGO_GLOBAL_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_CNTL__NEGO_GLOBAL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA1__DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA1__DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA1__USAGE_INFOR_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA1__USAGE_INFOR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA2__MODIFIED_TS_INFOR2_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__OTHERS_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__OTHERS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__PCIE_MASK', + 'BIF_CFG_DEV0_EPF0_1_AP_SEL_EN_MASK__PCIE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_EPF0_1_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_EPF0_1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF1_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK', + 'BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK', + 'BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK', + 'BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK', + 'BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK', + 'BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK', + 'BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK', + 'BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK', + 'BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK', + 'BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF2_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK', + 'BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK', + 'BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT', + 'BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK', + 'BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK', + 'BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT', + 'BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK', + 'BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT', + 'BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK', + 'BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK', + 'BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK', + 'BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK', + 'BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK', + 'BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK', + 'BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK', + 'BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK', + 'BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK', + 'BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK', + 'BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK', + 'BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK', + 'BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT', + 'BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK', + 'BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK', + 'BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT', + 'BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK', + 'BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT', + 'BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK', + 'BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_CAP__COUNT_MASK', + 'BIF_CFG_DEV0_RC0_AP_CAP__COUNT__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL_MASK', + 'BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN_MASK', + 'BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS_MASK', + 'BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR_MASK', + 'BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2_MASK', + 'BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS_MASK', + 'BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS__SHIFT', + 'BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE_MASK', + 'BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE__SHIFT', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_RC0_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_RC0_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_CAP__COUNT_MASK', + 'BIF_CFG_DEV0_RC1_AP_CAP__COUNT__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_CAP__SEL_EN_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_AP_CAP__SEL_EN_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_CNTL__INX_SEL_MASK', + 'BIF_CFG_DEV0_RC1_AP_CNTL__INX_SEL__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_CNTL__NEGO_GLOBAL_EN_MASK', + 'BIF_CFG_DEV0_RC1_AP_CNTL__NEGO_GLOBAL_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_DATA1__DETAILS_MASK', + 'BIF_CFG_DEV0_RC1_AP_DATA1__DETAILS__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_DATA1__USAGE_INFOR_MASK', + 'BIF_CFG_DEV0_RC1_AP_DATA1__USAGE_INFOR__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_RC1_AP_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_DATA2__MODIFIED_TS_INFOR2_MASK', + 'BIF_CFG_DEV0_RC1_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__OTHERS_MASK', + 'BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__OTHERS__SHIFT', + 'BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__PCIE_MASK', + 'BIF_CFG_DEV0_RC1_AP_SEL_EN_MASK__PCIE__SHIFT', + 'BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_RC1_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC1_RTR_DATA1__DLUP_TIME_MASK', + 'BIF_CFG_DEV0_RC1_RTR_DATA1__DLUP_TIME__SHIFT', + 'BIF_CFG_DEV0_RC1_RTR_DATA1__RESET_TIME_MASK', + 'BIF_CFG_DEV0_RC1_RTR_DATA1__RESET_TIME__SHIFT', + 'BIF_CFG_DEV0_RC1_RTR_DATA1__VALID_MASK', + 'BIF_CFG_DEV0_RC1_RTR_DATA1__VALID__SHIFT', + 'BIF_CFG_DEV0_RC1_RTR_DATA2__D3HOTD0_TIME_MASK', + 'BIF_CFG_DEV0_RC1_RTR_DATA2__D3HOTD0_TIME__SHIFT', + 'BIF_CFG_DEV0_RC1_RTR_DATA2__FLR_TIME_MASK', + 'BIF_CFG_DEV0_RC1_RTR_DATA2__FLR_TIME__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__INBAND_PD_DISABLE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK', + 'BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK', + 'BIF_CFG_DEV0_RC1_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT', + 'BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK', + 'BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT', + 'BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK', + 'BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT', + 'BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK', + 'BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT', + 'BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK', + 'BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT', + 'BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK', + 'BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT', + 'BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK', + 'BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT', + 'BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK', + 'BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK', + 'BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT', + 'BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK', + 'BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT', + 'BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK', + 'BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT', + 'BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK', + 'BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT', + 'BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK', + 'BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT', + 'BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK', + 'BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT', + 'BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK', + 'BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT', + 'BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT', + 'BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK', + 'BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT', + 'BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK', + 'BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT', + 'BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT', + 'BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK', + 'BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK', + 'BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT', + 'BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_EngineA_INTR_CNTL__EngineA_CMD_COMPLETE_MASK', + 'BIF_EngineA_INTR_CNTL__EngineA_CMD_COMPLETE__SHIFT', + 'BIF_EngineA_INTR_CNTL__EngineA_HANG_NEED_FLR_MASK', + 'BIF_EngineA_INTR_CNTL__EngineA_HANG_NEED_FLR__SHIFT', + 'BIF_EngineA_INTR_CNTL__EngineA_HANG_SELF_RECOVERED_MASK', + 'BIF_EngineA_INTR_CNTL__EngineA_HANG_SELF_RECOVERED__SHIFT', + 'BIF_EngineA_INTR_CNTL__EngineA_INST_SEL_MASK', + 'BIF_EngineA_INTR_CNTL__EngineA_INST_SEL__SHIFT', + 'BIF_EngineA_INTR_CNTL__EngineA_VM_BUSY_TRANSITION_MASK', + 'BIF_EngineA_INTR_CNTL__EngineA_VM_BUSY_TRANSITION__SHIFT', + 'BIF_EngineB_INTR_CNTL__EngineB_CMD_COMPLETE_MASK', + 'BIF_EngineB_INTR_CNTL__EngineB_CMD_COMPLETE__SHIFT', + 'BIF_EngineB_INTR_CNTL__EngineB_HANG_NEED_FLR_MASK', + 'BIF_EngineB_INTR_CNTL__EngineB_HANG_NEED_FLR__SHIFT', + 'BIF_EngineB_INTR_CNTL__EngineB_HANG_SELF_RECOVERED_MASK', + 'BIF_EngineB_INTR_CNTL__EngineB_HANG_SELF_RECOVERED__SHIFT', + 'BIF_EngineB_INTR_CNTL__EngineB_INST_SEL_MASK', + 'BIF_EngineB_INTR_CNTL__EngineB_INST_SEL__SHIFT', + 'BIF_EngineB_INTR_CNTL__EngineB_VM_BUSY_TRANSITION_MASK', + 'BIF_EngineB_INTR_CNTL__EngineB_VM_BUSY_TRANSITION__SHIFT', + 'BIF_FB_EN__FB_READ_EN_MASK', 'BIF_FB_EN__FB_READ_EN__SHIFT', + 'BIF_FB_EN__FB_WRITE_EN_MASK', 'BIF_FB_EN__FB_WRITE_EN__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK', + 'BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK', + 'BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK', + 'BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK', + 'BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK', + 'BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK', + 'BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK', + 'BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK', + 'BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK', + 'BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT', + 'BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK', + 'BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT', + 'BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK', + 'BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT', + 'BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK', + 'BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT', + 'BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK', + 'BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT', + 'BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK', + 'BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT', + 'BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK', + 'BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT', + 'BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK', + 'BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT', + 'BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK', + 'BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT', + 'BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK', + 'BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT', + 'BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK', + 'BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT', + 'BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK', + 'BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT', + 'BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK', + 'BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT', + 'BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK', + 'BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT', + 'BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK', + 'BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT', + 'BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK', + 'BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT', + 'BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK', + 'BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT', + 'BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK', + 'BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT', + 'BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK', + 'BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT', + 'BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK', + 'BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT', + 'BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK', + 'BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT', + 'BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK', + 'BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT', + 'BIF_RB_BASE__ADDR_MASK', 'BIF_RB_BASE__ADDR__SHIFT', + 'BIF_RB_CNTL__BIF_RB_TRAN_MASK', + 'BIF_RB_CNTL__BIF_RB_TRAN__SHIFT', 'BIF_RB_CNTL__RB_ENABLE_MASK', + 'BIF_RB_CNTL__RB_ENABLE__SHIFT', + 'BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK', + 'BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT', + 'BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK', + 'BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT', + 'BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK', + 'BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT', + 'BIF_RB_CNTL__RB_SIZE_MASK', 'BIF_RB_CNTL__RB_SIZE__SHIFT', + 'BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK', + 'BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT', + 'BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK', + 'BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT', + 'BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK', + 'BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT', + 'BIF_RB_RPTR__OFFSET_MASK', 'BIF_RB_RPTR__OFFSET__SHIFT', + 'BIF_RB_WPTR_ADDR_HI__ADDR_MASK', + 'BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT', + 'BIF_RB_WPTR_ADDR_LO__ADDR_MASK', + 'BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT', + 'BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK', + 'BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT', 'BIF_RB_WPTR__OFFSET_MASK', + 'BIF_RB_WPTR__OFFSET__SHIFT', + 'BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK', + 'BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT', + 'BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT', + 'BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK', + 'BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT', + 'BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK', + 'BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT', + 'BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK', + 'BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT', + 'BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK', + 'BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT', + 'BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK', + 'BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT', + 'BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK', + 'BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT', + 'BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK', + 'BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT', + 'BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK', + 'BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT', + 'BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK', + 'BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT', + 'BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK', + 'BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT', + 'BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK', + 'BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT', + 'BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK', + 'BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT', + 'BIF_SCRATCH0__BIF_SCRATCH0_MASK', + 'BIF_SCRATCH0__BIF_SCRATCH0__SHIFT', + 'BIF_SCRATCH1__BIF_SCRATCH1_MASK', + 'BIF_SCRATCH1__BIF_SCRATCH1__SHIFT', + 'BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK', + 'BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT', + 'BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK', + 'BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT', + 'BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK', + 'BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT', + 'BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK', + 'BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT', + 'BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK', + 'BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT', + 'BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK', + 'BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT', + 'BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK', + 'BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK', + 'BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT', + 'BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK', + 'BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT', + 'BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK', + 'BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT', + 'BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK', + 'BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT', + 'BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK', + 'BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT', + 'BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK', + 'BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT', + 'BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK', + 'BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT', + 'BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK', + 'BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT', + 'BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK', + 'BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT', + 'BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK', + 'BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT', + 'BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK', + 'BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT', + 'BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK', + 'BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT', + 'BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK', + 'BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT', + 'BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK', + 'BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT', + 'BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK', + 'BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT', + 'BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK', + 'BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT', + 'BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK', + 'BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT', + 'BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK', + 'BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT', + 'BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK', + 'BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT', + 'BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK', + 'BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT', + 'BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK', + 'BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT', + 'BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK', + 'BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT', + 'BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK', + 'BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT', + 'BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK', + 'BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT', + 'BUS_CNTL__RD_STALL_IO_WR_MASK', + 'BUS_CNTL__RD_STALL_IO_WR__SHIFT', 'BUS_CNTL__SET_AZ_TC_MASK', + 'BUS_CNTL__SET_AZ_TC__SHIFT', 'BUS_CNTL__SET_MC_TC_MASK', + 'BUS_CNTL__SET_MC_TC__SHIFT', + 'BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK', + 'BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT', + 'BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK', + 'BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT', + 'BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK', + 'BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT', + 'BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK', + 'BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT', + 'BUS_CNTL__ZERO_BE_RD_EN_MASK', 'BUS_CNTL__ZERO_BE_RD_EN__SHIFT', + 'BUS_CNTL__ZERO_BE_WR_EN_MASK', 'BUS_CNTL__ZERO_BE_WR_EN__SHIFT', + 'BX_RESET_CNTL__LINK_TRAIN_EN_MASK', + 'BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT', + 'BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK', + 'BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT', + 'CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK', + 'CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT', + 'CLDO_075_S5_CTRL__CONFIG_EN_MASK', + 'CLDO_075_S5_CTRL__CONFIG_EN__SHIFT', + 'CLDO_075_S5_CTRL__LDO_VOLTAGE_OUT_MASK', + 'CLDO_075_S5_CTRL__LDO_VOLTAGE_OUT__SHIFT', + 'CLDO_075_S5_CTRL__SELECTS0_MASK', + 'CLDO_075_S5_CTRL__SELECTS0__SHIFT', + 'CLDO_075_S5_CTRL__SPARE_MASK', 'CLDO_075_S5_CTRL__SPARE__SHIFT', + 'CLDO_12_PCIE_CTRL__CONFIG_EN_MASK', + 'CLDO_12_PCIE_CTRL__CONFIG_EN__SHIFT', + 'CLDO_12_PCIE_CTRL__LDO_VOLTAGE_OUT_MASK', + 'CLDO_12_PCIE_CTRL__LDO_VOLTAGE_OUT__SHIFT', + 'CLDO_12_PCIE_CTRL__SELECTS0_MASK', + 'CLDO_12_PCIE_CTRL__SELECTS0__SHIFT', + 'CLDO_12_PCIE_CTRL__SPARE_MASK', + 'CLDO_12_PCIE_CTRL__SPARE__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK', + 'CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT', + 'CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE_MASK', + 'CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE__SHIFT', + 'CPM_CONTROL_EXT__HOTPLUG_ALLOW_LCLK_GATING_EN_MASK', + 'CPM_CONTROL_EXT__HOTPLUG_ALLOW_LCLK_GATING_EN__SHIFT', + 'CPM_CONTROL_EXT__LCLK_DS_ENABLE_MASK', + 'CPM_CONTROL_EXT__LCLK_DS_ENABLE__SHIFT', + 'CPM_CONTROL_EXT__LCLK_DS_MODE_MASK', + 'CPM_CONTROL_EXT__LCLK_DS_MODE__SHIFT', + 'CPM_CONTROL_EXT__PG_STATE_MASK', + 'CPM_CONTROL_EXT__PG_STATE__SHIFT', + 'CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE_MASK', + 'CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE__SHIFT', + 'CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK', + 'CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT', + 'CPM_CONTROL__FAST_TXCLK_LATENCY_MASK', + 'CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT', + 'CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG_MASK', + 'CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG__SHIFT', + 'CPM_CONTROL__L1_1_PWR_GATE_ENABLE_MASK', + 'CPM_CONTROL__L1_1_PWR_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__L1_2_PWR_GATE_ENABLE_MASK', + 'CPM_CONTROL__L1_2_PWR_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__L1_PWR_GATE_ENABLE_MASK', + 'CPM_CONTROL__L1_PWR_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK', + 'CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK', + 'CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT', + 'CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK', + 'CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT', + 'CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK', + 'CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT', + 'CPM_CONTROL__PCIE_BUFFER_EMPTY_MASK', + 'CPM_CONTROL__PCIE_BUFFER_EMPTY__SHIFT', + 'CPM_CONTROL__PCIE_CORE_IDLE_MASK', + 'CPM_CONTROL__PCIE_CORE_IDLE__SHIFT', + 'CPM_CONTROL__PCIE_LINK_IDLE_MASK', + 'CPM_CONTROL__PCIE_LINK_IDLE__SHIFT', + 'CPM_CONTROL__PG_EARLY_WAKE_ENABLE_MASK', + 'CPM_CONTROL__PG_EARLY_WAKE_ENABLE__SHIFT', + 'CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK', + 'CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT', + 'CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE_MASK', + 'CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE__SHIFT', + 'CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK', + 'CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK', + 'CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT', + 'CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK', + 'CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT', + 'CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK', + 'CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT', + 'CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY_MASK', + 'CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY__SHIFT', + 'CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK', + 'CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK', + 'CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT', + 'CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK', + 'CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK', + 'CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK', + 'CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT', + 'CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK', + 'CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT', + 'CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE_MASK', + 'CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK', + 'DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK', + 'DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK', + 'DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK', + 'DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK', + 'DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK', + 'DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK', + 'DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK', + 'DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK', + 'DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT', + 'DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK', + 'DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT', + 'DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK', + 'DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT', + 'DN_PCIE_RESERVED__PCIE_RESERVED_MASK', + 'DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT', + 'DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK', + 'DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT', + 'DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK', + 'DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT', + 'DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK', + 'DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT', + 'DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK', + 'DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT', + 'DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK', + 'DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT', + 'DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK', + 'DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT', + 'DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK', + 'DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT', + 'DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK', + 'DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT', + 'DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK', + 'DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT', + 'DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK', + 'DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT', + 'DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK', + 'DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT', + 'DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK', + 'DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT', + 'DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK', + 'DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT', + 'DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK', + 'DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT', + 'DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK', + 'DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT', + 'DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK', + 'DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT', + 'DVSEC_PRIV_CNTL2__DVSEC_PRIV_REG2_MASK', + 'DVSEC_PRIV_CNTL2__DVSEC_PRIV_REG2__SHIFT', + 'DVSEC_PRIV_CNTL__DVSEC_PRIV_REG_MASK', + 'DVSEC_PRIV_CNTL__DVSEC_PRIV_REG__SHIFT', + 'DVSEC_VF_PRIV_CNTL2__DVSEC_VF_PRIV_REG2_MASK', + 'DVSEC_VF_PRIV_CNTL2__DVSEC_VF_PRIV_REG2__SHIFT', + 'DVSEC_VF_PRIV_CNTL__DVSEC_VF_PRIV_REG_MASK', + 'DVSEC_VF_PRIV_CNTL__DVSEC_VF_PRIV_REG__SHIFT', + 'EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK', + 'EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT', + 'EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK', + 'EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT', + 'EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK', + 'EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT', + 'EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK', + 'EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT', + 'EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK', + 'EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT', + 'EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK', + 'EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT', + 'EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK', + 'EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT', + 'EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK', + 'EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT', + 'EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK', + 'EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT', + 'EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK', + 'EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT', + 'EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK', + 'EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT', + 'EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK', + 'EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT', + 'EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK', + 'EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT', + 'EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK', + 'EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT', + 'EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK', + 'EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT', + 'EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK', + 'EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK', + 'EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT', + 'EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK', + 'EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT', + 'EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK', + 'EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT', + 'EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK', + 'EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT', + 'EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK', + 'EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT', + 'EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK', + 'EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK', + 'EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT', + 'EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK', + 'EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT', + 'EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK', + 'EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT', + 'EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK', + 'EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT', + 'EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK', + 'EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT', + 'FW_SCRATCH_0__FW_SCRATCH_0_MASK', + 'FW_SCRATCH_0__FW_SCRATCH_0__SHIFT', + 'FW_SCRATCH_10__FW_SCRATCH_10_MASK', + 'FW_SCRATCH_10__FW_SCRATCH_10__SHIFT', + 'FW_SCRATCH_11__FW_SCRATCH_11_MASK', + 'FW_SCRATCH_11__FW_SCRATCH_11__SHIFT', + 'FW_SCRATCH_12__FW_SCRATCH_12_MASK', + 'FW_SCRATCH_12__FW_SCRATCH_12__SHIFT', + 'FW_SCRATCH_13__FW_SCRATCH_13_MASK', + 'FW_SCRATCH_13__FW_SCRATCH_13__SHIFT', + 'FW_SCRATCH_14__FW_SCRATCH_14_MASK', + 'FW_SCRATCH_14__FW_SCRATCH_14__SHIFT', + 'FW_SCRATCH_15__FW_SCRATCH_15_MASK', + 'FW_SCRATCH_15__FW_SCRATCH_15__SHIFT', + 'FW_SCRATCH_1__FW_SCRATCH_1_MASK', + 'FW_SCRATCH_1__FW_SCRATCH_1__SHIFT', + 'FW_SCRATCH_2__FW_SCRATCH_2_MASK', + 'FW_SCRATCH_2__FW_SCRATCH_2__SHIFT', + 'FW_SCRATCH_3__FW_SCRATCH_3_MASK', + 'FW_SCRATCH_3__FW_SCRATCH_3__SHIFT', + 'FW_SCRATCH_4__FW_SCRATCH_4_MASK', + 'FW_SCRATCH_4__FW_SCRATCH_4__SHIFT', + 'FW_SCRATCH_5__FW_SCRATCH_5_MASK', + 'FW_SCRATCH_5__FW_SCRATCH_5__SHIFT', + 'FW_SCRATCH_6__FW_SCRATCH_6_MASK', + 'FW_SCRATCH_6__FW_SCRATCH_6__SHIFT', + 'FW_SCRATCH_7__FW_SCRATCH_7_MASK', + 'FW_SCRATCH_7__FW_SCRATCH_7__SHIFT', + 'FW_SCRATCH_8__FW_SCRATCH_8_MASK', + 'FW_SCRATCH_8__FW_SCRATCH_8__SHIFT', + 'FW_SCRATCH_9__FW_SCRATCH_9_MASK', + 'FW_SCRATCH_9__FW_SCRATCH_9__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK', + 'GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT', + 'GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK', + 'GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT', + 'GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT', + 'GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK', + 'GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT', + 'GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT', + 'GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT', + 'GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT', + 'GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK', + 'GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK', + 'GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT', + 'GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK', + 'GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT', + 'GDC1_NGDC_RESERVED_0__RESERVED_MASK', + 'GDC1_NGDC_RESERVED_0__RESERVED__SHIFT', + 'GDC1_NGDC_RESERVED_1__RESERVED_MASK', + 'GDC1_NGDC_RESERVED_1__RESERVED__SHIFT', + 'GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT', + 'GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK', + 'GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT', + 'GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT', + 'GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT', + 'GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT', + 'GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK', + 'GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK', + 'GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK', + 'GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK', + 'GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK', + 'GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK', + 'GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT', + 'GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK', + 'GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK', + 'GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK', + 'GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT', + 'GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK', + 'GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT', + 'GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK', + 'GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT', + 'GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK', + 'GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK', + 'GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT', + 'GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS_MASK', + 'GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS__SHIFT', + 'GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD_MASK', + 'GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT', + 'GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK', + 'GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT', + 'GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK', + 'GDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT', + 'GDC_HST_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK', + 'GDC_HST_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT', + 'GDC_HST_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK', + 'GDC_HST_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT', + 'GDC_HST_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK', + 'GDC_HST_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT', + 'GDC_HST_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK', + 'GDC_HST_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK', + 'GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT', + 'GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS_MASK', + 'GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS__SHIFT', + 'GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD_MASK', + 'GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT', + 'GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK', + 'GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT', + 'GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK', + 'GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT', + 'GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK', + 'GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT', + 'GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK', + 'GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT', + 'GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK', + 'GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT', + 'GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK', + 'GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT', + 'GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK', + 'GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT', + 'GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK', + 'GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT', + 'GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK', + 'GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT', + 'GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK', + 'GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT', + 'GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK', + 'GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT', + 'GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK', + 'GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT', + 'GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK', + 'GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT', + 'GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK', + 'GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_Reserved_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_Reserved__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_Y_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_Y__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iA_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iA__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iCTFEN_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iCTFEN__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iOE_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iOE__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iPD_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iPD__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iPU_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iPU__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXEN_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXEN__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL0_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL0__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL1_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iRXSEL1__SHIFT', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iTXIMPSEL_MASK', + 'GPIO_CNTL_0_REG__GPIO_CNTL_0_iTXIMPSEL__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_Reserved_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_Reserved__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_Y_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_Y__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iA_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iA__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iCTFEN_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iCTFEN__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iOE_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iOE__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iPD_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iPD__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iPU_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iPU__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXEN_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXEN__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL0_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL0__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL1_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iRXSEL1__SHIFT', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iTXIMPSEL_MASK', + 'GPIO_CNTL_1_REG__GPIO_CNTL_1_iTXIMPSEL__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_Reserved_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_Reserved__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_Y_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_Y__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iA_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iA__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iCTFEN_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iCTFEN__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iOE_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iOE__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iPD_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iPD__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iPU_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iPU__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXEN_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXEN__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL0_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL0__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL1_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iRXSEL1__SHIFT', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iTXIMPSEL_MASK', + 'GPIO_CNTL_2_REG__GPIO_CNTL_2_iTXIMPSEL__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_Reserved_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_Reserved__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_Y_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_Y__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iA_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iA__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iCTFEN_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iCTFEN__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iOE_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iOE__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iPD_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iPD__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iPU_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iPU__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXEN_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXEN__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL0_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL0__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL1_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iRXSEL1__SHIFT', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iTXIMPSEL_MASK', + 'GPIO_CNTL_3_REG__GPIO_CNTL_3_iTXIMPSEL__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_Reserved_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_Reserved__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_Y_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_Y__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iA_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iA__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iCTFEN_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iCTFEN__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iOE_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iOE__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iPD_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iPD__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iPU_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iPU__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXEN_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXEN__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL0_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL0__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL1_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iRXSEL1__SHIFT', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iTXIMPSEL_MASK', + 'GPIO_CNTL_4_REG__GPIO_CNTL_4_iTXIMPSEL__SHIFT', + 'HARD_RST_CTRL__CORE_RST_EN_MASK', + 'HARD_RST_CTRL__CORE_RST_EN__SHIFT', + 'HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_CFG_RST_EN_MASK', + 'HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_PRV_RST_EN_MASK', + 'HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__RELOAD_STRAP_EN_MASK', + 'HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT', + 'HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK', + 'HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT', + 'HARD_RST_CTRL__SION_AON_RESET_EN_MASK', + 'HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT', + 'HARD_RST_CTRL__STRAP_RST_EN_MASK', + 'HARD_RST_CTRL__STRAP_RST_EN__SHIFT', + 'HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK', + 'HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT', + 'HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK', + 'HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT', + 'HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK', + 'INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT', + 'INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK', + 'INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT', + 'INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK', + 'INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT', + 'INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK', + 'INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT', + 'INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK', + 'INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT', + 'INTERRUPT_CNTL__GEN_IH_INT_EN_MASK', + 'INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT', + 'INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK', + 'INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT', + 'INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK', + 'INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT', + 'INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK', + 'INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT', + 'INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK', + 'INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT', + 'INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK', + 'INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT', + 'INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK', + 'INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY_MASK', + 'LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE__SHIFT', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE_MASK', + 'LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE__SHIFT', + 'LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK', + 'LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT', + 'LNCNT_CONTROL__CFG_LNC_BW_QUAN_THRD_MASK', + 'LNCNT_CONTROL__CFG_LNC_BW_QUAN_THRD__SHIFT', + 'LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK', + 'LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT', + 'LNCNT_CONTROL__CFG_LNC_CMN_QUAN_THRD_MASK', + 'LNCNT_CONTROL__CFG_LNC_CMN_QUAN_THRD__SHIFT', + 'LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK', + 'LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT', + 'MAILBOX_INDEX__MAILBOX_INDEX_MASK', + 'MAILBOX_INDEX__MAILBOX_INDEX__SHIFT', + 'MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK', + 'MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT', + 'MISC_SCRATCH__MISC_SCRATCH0_MASK', + 'MISC_SCRATCH__MISC_SCRATCH0__SHIFT', + 'MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK', + 'MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT', + 'MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK', + 'MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT', + 'MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK', + 'MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT', + 'NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK', + 'NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT', + 'NBIF_GFX_ADDR_LUT_0__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_10__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_11__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_12__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_13__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_14__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_15__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_1__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_2__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_3__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_4__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_5__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_6__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_7__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_8__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_9__ADDR_MASK', + 'NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT', + 'NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK', + 'NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT', + 'NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK', + 'NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT', + 'NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK', + 'NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT', + 'NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK', + 'NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT', + 'NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK', + 'NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT', + 'NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK', + 'NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT', + 'NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK', + 'NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT', + 'NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK', + 'NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT', + 'NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK', + 'NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK', + 'NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK', + 'NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK', + 'NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK', + 'NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT', + 'NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK', + 'NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT', + 'NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK', + 'NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT', + 'NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK', + 'NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT', + 'NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK', + 'NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT', + 'NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK', + 'NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT', + 'NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK', + 'NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT', + 'NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK', + 'NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT', + 'NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK', + 'NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT', + 'NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK', + 'NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT', + 'NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK', + 'NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT', + 'NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK', + 'NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT', + 'NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK', + 'NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT', + 'NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK', + 'NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT', + 'NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK', + 'NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT', + 'NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK', + 'NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT', + 'NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK', + 'NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT', + 'NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK', + 'NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT', + 'NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK', + 'NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT', + 'NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK', + 'NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT', + 'NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK', + 'NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT', + 'NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK', + 'NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT', + 'NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK', + 'NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT', + 'NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK', + 'NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT', + 'NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK', + 'NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT', + 'NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK', + 'NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT', + 'NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK', + 'NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT', + 'NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK', + 'NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT', + 'NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK', + 'NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT', + 'NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK', + 'NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT', + 'NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK', + 'NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT', + 'NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK', + 'NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT', + 'NGDC_RESERVED_0__RESERVED_MASK', + 'NGDC_RESERVED_0__RESERVED__SHIFT', + 'NGDC_RESERVED_1__RESERVED_MASK', + 'NGDC_RESERVED_1__RESERVED__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT', + 'PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK', + 'PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT', + 'PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK', + 'PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT', + 'PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK', + 'PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK', + 'PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK', + 'PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT', + 'PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK', + 'PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT', + 'PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK', + 'PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT', + 'PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK', + 'PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT', + 'PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK', + 'PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT', + 'PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK', + 'PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT', + 'PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK', + 'PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT', + 'PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK', + 'PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT', + 'PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK', + 'PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT', + 'PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK', + 'PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT', + 'PCIEP_PORT_CNTL__PMI_BM_DIS_MASK', + 'PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT', + 'PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK', + 'PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT', + 'PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK', + 'PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT', + 'PCIEP_RESERVED__RESERVED_MASK', + 'PCIEP_RESERVED__RESERVED__SHIFT', + 'PCIEP_SCRATCH__PCIEP_SCRATCH_MASK', + 'PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT', + 'PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK', + 'PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT', + 'PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK', + 'PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT', + 'PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK', + 'PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT', + 'PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK', + 'PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT', + 'PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK', + 'PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT', + 'PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_16GT_DIS_MASK', + 'PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_16GT_DIS__SHIFT', + 'PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_32GT_DIS_MASK', + 'PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_32GT_DIS__SHIFT', + 'PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK', + 'PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT', + 'PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK', + 'PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT', + 'PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK', + 'PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT', + 'PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK', + 'PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT', + 'PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK', + 'PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT', + 'PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK', + 'PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT', + 'PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK', + 'PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT', + 'PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK', + 'PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT', + 'PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK', + 'PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT', + 'PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK', + 'PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT', + 'PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK', + 'PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT', + 'PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK', + 'PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT', + 'PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK', + 'PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT', + 'PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK', + 'PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT', + 'PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'PCIE_BUS_CNTL__PMI_INT_DIS_MASK', + 'PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT', + 'PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK', + 'PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT', + 'PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK', + 'PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK', + 'PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK', + 'PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_SDP_CHAIN_DIS_MASK', + 'PCIE_CI_CNTL__CI_SLV_SDP_CHAIN_DIS__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK', + 'PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT', + 'PCIE_CI_CNTL__CI_SLV_SDP_MEM_WR_FULL_DIS_MASK', + 'PCIE_CI_CNTL__CI_SLV_SDP_MEM_WR_FULL_DIS__SHIFT', + 'PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK', + 'PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT', + 'PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK', + 'PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT', + 'PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK', + 'PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT', + 'PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK', + 'PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT', + 'PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK', + 'PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT', + 'PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK', + 'PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT', + 'PCIE_CI_CNTL__TX_PGMEM_CTRL_PGATE_DIS_MASK', + 'PCIE_CI_CNTL__TX_PGMEM_CTRL_PGATE_DIS__SHIFT', + 'PCIE_CNTL2__MST_CPL_LS_EN_MASK', + 'PCIE_CNTL2__MST_CPL_LS_EN__SHIFT', 'PCIE_CNTL2__RCB_LS_EN_MASK', + 'PCIE_CNTL2__RCB_LS_EN__SHIFT', + 'PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK', + 'PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT', + 'PCIE_CNTL2__SLVAER_LS_EN_MASK', + 'PCIE_CNTL2__SLVAER_LS_EN__SHIFT', + 'PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK', + 'PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT', + 'PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK', + 'PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT', + 'PCIE_CNTL2__SLV_MEM_DS_EN_MASK', + 'PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT', + 'PCIE_CNTL2__SLV_MEM_LS_EN_MASK', + 'PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT', + 'PCIE_CNTL2__SLV_MEM_SD_EN_MASK', + 'PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT', + 'PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK', + 'PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT', + 'PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK', + 'PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT', + 'PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK', + 'PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT', + 'PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK', + 'PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT', + 'PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK', + 'PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT', + 'PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK', + 'PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT', + 'PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK', + 'PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT', + 'PCIE_CNTL__RX_RCB_REORDER_EN_MASK', + 'PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT', + 'PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK', + 'PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT', + 'PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK', + 'PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT', + 'PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK', + 'PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT', + 'PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK', + 'PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT', + 'PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK', + 'PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT', + 'PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC_MASK', + 'PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC__SHIFT', + 'PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK', + 'PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT', + 'PCIE_DATA2__PCIE_DATA2_MASK', 'PCIE_DATA2__PCIE_DATA2__SHIFT', + 'PCIE_DATA__PCIE_DATA_MASK', 'PCIE_DATA__PCIE_DATA__SHIFT', + 'PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK', + 'PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT', + 'PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK', + 'PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT', + 'PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK', + 'PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT', + 'PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK', + 'PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT', + 'PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK', + 'PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT', + 'PCIE_FC_CPL__CPLD_CREDITS_MASK', + 'PCIE_FC_CPL__CPLD_CREDITS__SHIFT', + 'PCIE_FC_CPL__CPLH_CREDITS_MASK', + 'PCIE_FC_CPL__CPLH_CREDITS__SHIFT', + 'PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK', + 'PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT', + 'PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK', + 'PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT', + 'PCIE_FC_NP__NPD_CREDITS_MASK', 'PCIE_FC_NP__NPD_CREDITS__SHIFT', + 'PCIE_FC_NP__NPH_CREDITS_MASK', 'PCIE_FC_NP__NPH_CREDITS__SHIFT', + 'PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK', + 'PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT', + 'PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK', + 'PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT', + 'PCIE_FC_P__PD_CREDITS_MASK', 'PCIE_FC_P__PD_CREDITS__SHIFT', + 'PCIE_FC_P__PH_CREDITS_MASK', 'PCIE_FC_P__PH_CREDITS__SHIFT', + 'PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI_MASK', + 'PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI__SHIFT', + 'PCIE_HIP_REG0__CI_HIP_APT0_ENABLE_MASK', + 'PCIE_HIP_REG0__CI_HIP_APT0_ENABLE__SHIFT', + 'PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE_MASK', + 'PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE__SHIFT', + 'PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE_MASK', + 'PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE__SHIFT', + 'PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE_MASK', + 'PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE__SHIFT', + 'PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO_MASK', + 'PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO__SHIFT', + 'PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI_MASK', + 'PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI__SHIFT', + 'PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO_MASK', + 'PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO__SHIFT', + 'PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI_MASK', + 'PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI__SHIFT', + 'PCIE_HIP_REG4__CI_HIP_APT1_ENABLE_MASK', + 'PCIE_HIP_REG4__CI_HIP_APT1_ENABLE__SHIFT', + 'PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE_MASK', + 'PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE__SHIFT', + 'PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE_MASK', + 'PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE__SHIFT', + 'PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE_MASK', + 'PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE__SHIFT', + 'PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO_MASK', + 'PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO__SHIFT', + 'PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI_MASK', + 'PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI__SHIFT', + 'PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO_MASK', + 'PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO__SHIFT', + 'PCIE_HIP_REG8__CI_HIP_MASK_MASK', + 'PCIE_HIP_REG8__CI_HIP_MASK__SHIFT', + 'PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK', + 'PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT', + 'PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK', + 'PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT', + 'PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK', + 'PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT', + 'PCIE_INDEX2__PCIE_INDEX2_MASK', + 'PCIE_INDEX2__PCIE_INDEX2__SHIFT', + 'PCIE_INDEX_HI__PCIE_INDEX_HI_MASK', + 'PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT', + 'PCIE_INDEX__PCIE_INDEX_MASK', 'PCIE_INDEX__PCIE_INDEX__SHIFT', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK', + 'PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT', + 'PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK', + 'PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT', + 'PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK', + 'PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT', + 'PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK', + 'PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT', + 'PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK', + 'PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT', + 'PCIE_LC_CNTL10__LC_CLEAR_CNTL_SKP_SELECT_DATASTREAM_EXIT_MASK', + 'PCIE_LC_CNTL10__LC_CLEAR_CNTL_SKP_SELECT_DATASTREAM_EXIT__SHIFT', + 'PCIE_LC_CNTL10__LC_DEASSERT_REFCLKREQ_IN_L23_MASK', + 'PCIE_LC_CNTL10__LC_DEASSERT_REFCLKREQ_IN_L23__SHIFT', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK', + 'PCIE_LC_CNTL10__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT', + 'PCIE_LC_CNTL10__LC_LSLD_CURRENT_RATE_MASK', + 'PCIE_LC_CNTL10__LC_LSLD_CURRENT_RATE__SHIFT', + 'PCIE_LC_CNTL10__LC_LSLD_DONE_MASK', + 'PCIE_LC_CNTL10__LC_LSLD_DONE__SHIFT', + 'PCIE_LC_CNTL10__LC_LSLD_EN_MASK', + 'PCIE_LC_CNTL10__LC_LSLD_EN__SHIFT', + 'PCIE_LC_CNTL10__LC_LSLD_MODE_MASK', + 'PCIE_LC_CNTL10__LC_LSLD_MODE__SHIFT', + 'PCIE_LC_CNTL10__LC_LSLD_RATE_REQD_MASK', + 'PCIE_LC_CNTL10__LC_LSLD_RATE_REQD__SHIFT', + 'PCIE_LC_CNTL10__LC_LSLD_TLS_ADVERTISED_MASK', + 'PCIE_LC_CNTL10__LC_LSLD_TLS_ADVERTISED__SHIFT', + 'PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_L23_MASK', + 'PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_L23__SHIFT', + 'PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_NON_SS_L1_MASK', + 'PCIE_LC_CNTL10__LC_RELEASE_CLKREQ_IN_NON_SS_L1__SHIFT', + 'PCIE_LC_CNTL10__LC_TIEOFF_PORTS_IGNORE_PHYSTATUS_MASK', + 'PCIE_LC_CNTL10__LC_TIEOFF_PORTS_IGNORE_PHYSTATUS__SHIFT', + 'PCIE_LC_CNTL10__LC_USE_PENDING_FOM_SKIP_SECOND_RXEQEVAL_MASK', + 'PCIE_LC_CNTL10__LC_USE_PENDING_FOM_SKIP_SECOND_RXEQEVAL__SHIFT', + 'PCIE_LC_CNTL11__LC_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT_MASK', + 'PCIE_LC_CNTL11__LC_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT__SHIFT', + 'PCIE_LC_CNTL11__LC_ADVERTISE_NO_EQ_NEEDED_SUPPORT_MASK', + 'PCIE_LC_CNTL11__LC_ADVERTISE_NO_EQ_NEEDED_SUPPORT__SHIFT', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_FAILURE_MASK', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_FAILURE__SHIFT', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_NEGOTIATED_MASK', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_NEGOTIATED__SHIFT', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RCVD_MASK', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RCVD__SHIFT', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RESERVED_MASK', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_RESERVED__SHIFT', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_SUPPORT_MASK', + 'PCIE_LC_CNTL11__LC_BYPASS_EQ_TO_HIGH_RATE_SUPPORT__SHIFT', + 'PCIE_LC_CNTL11__LC_CHECK_TS1_EC_ON_EQ_EXIT_MASK', + 'PCIE_LC_CNTL11__LC_CHECK_TS1_EC_ON_EQ_EXIT__SHIFT', + 'PCIE_LC_CNTL11__LC_DISABLE_TRAINING_BIT_ARCH_IND_MASK', + 'PCIE_LC_CNTL11__LC_DISABLE_TRAINING_BIT_ARCH_IND__SHIFT', + 'PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_RCVD_MASK', + 'PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_RCVD__SHIFT', + 'PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_SENT_MASK', + 'PCIE_LC_CNTL11__LC_ENHANCED_LINK_BEHAVIOR_CNTL_SENT__SHIFT', + 'PCIE_LC_CNTL11__LC_LAST_TRANSMITTER_PRECODE_REQUEST_MASK', + 'PCIE_LC_CNTL11__LC_LAST_TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_FAILURE_MASK', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_FAILURE__SHIFT', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_NEGOTIATED_MASK', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_NEGOTIATED__SHIFT', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_PRESET_SEL_MASK', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_PRESET_SEL__SHIFT', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RCVD_MASK', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RCVD__SHIFT', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RESERVED_MASK', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_RESERVED__SHIFT', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_SUPPORT_MASK', + 'PCIE_LC_CNTL11__LC_NO_EQ_NEEDED_SUPPORT__SHIFT', + 'PCIE_LC_CNTL11__LC_SET_TRANSMITTER_PRECODE_REQUEST_MASK', + 'PCIE_LC_CNTL11__LC_SET_TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_MASK', + 'PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_RCVD_MASK', + 'PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON_RCVD__SHIFT', + 'PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_ON__SHIFT', + 'PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_REQUEST_RCVD_MASK', + 'PCIE_LC_CNTL11__LC_TRANSMITTER_PRECODE_REQUEST_RCVD__SHIFT', + 'PCIE_LC_CNTL12__LC_BLOCKALIGN_IN_L1_ENTRY_MASK', + 'PCIE_LC_CNTL12__LC_BLOCKALIGN_IN_L1_ENTRY__SHIFT', + 'PCIE_LC_CNTL12__LC_DEFER_SKIP_INTERVAL_MODE_MASK', + 'PCIE_LC_CNTL12__LC_DEFER_SKIP_INTERVAL_MODE__SHIFT', + 'PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK', + 'PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT', + 'PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK', + 'PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT', + 'PCIE_LC_CNTL12__LC_DELAY_PHASE1_MASK', + 'PCIE_LC_CNTL12__LC_DELAY_PHASE1__SHIFT', + 'PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK', + 'PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT', + 'PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK', + 'PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT', + 'PCIE_LC_CNTL12__LC_DSC_INITIATE_EQUALIZATION_OS_BOUNDARY_MASK', + 'PCIE_LC_CNTL12__LC_DSC_INITIATE_EQUALIZATION_OS_BOUNDARY__SHIFT', + 'PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK', + 'PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT', + 'PCIE_LC_CNTL12__LC_EQ_REQ_PHASE_WAIT_FOR_FINAL_TS1_MASK', + 'PCIE_LC_CNTL12__LC_EQ_REQ_PHASE_WAIT_FOR_FINAL_TS1__SHIFT', + 'PCIE_LC_CNTL12__LC_HOLD_TX_STOP_SENDING_PKTS_REPLAY_RETRAIN_MASK', + 'PCIE_LC_CNTL12__LC_HOLD_TX_STOP_SENDING_PKTS_REPLAY_RETRAIN__SHIFT', + 'PCIE_LC_CNTL12__LC_LIVE_DESKEW_8B10B_EN_MASK', + 'PCIE_LC_CNTL12__LC_LIVE_DESKEW_8B10B_EN__SHIFT', + 'PCIE_LC_CNTL12__LC_LIVE_DESKEW_MASK_EN_MASK', + 'PCIE_LC_CNTL12__LC_LIVE_DESKEW_MASK_EN__SHIFT', + 'PCIE_LC_CNTL12__LC_LOCK_REVERSAL_EARLY_CONFIG_COMPLETE_MASK', + 'PCIE_LC_CNTL12__LC_LOCK_REVERSAL_EARLY_CONFIG_COMPLETE__SHIFT', + 'PCIE_LC_CNTL12__LC_LOCK_REVERSAL_IMMEDIATE_CONFIG_COMPLETE_MASK', + 'PCIE_LC_CNTL12__LC_LOCK_REVERSAL_IMMEDIATE_CONFIG_COMPLETE__SHIFT', + 'PCIE_LC_CNTL12__LC_LOOPBACK_EQ_LOCK_REVERSAL_MASK', + 'PCIE_LC_CNTL12__LC_LOOPBACK_EQ_LOCK_REVERSAL__SHIFT', + 'PCIE_LC_CNTL12__LC_LOOPBACK_TEST_MODE_RCVRDET_MASK', + 'PCIE_LC_CNTL12__LC_LOOPBACK_TEST_MODE_RCVRDET__SHIFT', + 'PCIE_LC_CNTL12__LC_RECOVERY_EQ_WAIT_FOR_PIPE_STOPPED_MASK', + 'PCIE_LC_CNTL12__LC_RECOVERY_EQ_WAIT_FOR_PIPE_STOPPED__SHIFT', + 'PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_RXEQEVAL_MASK', + 'PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_RXEQEVAL__SHIFT', + 'PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_SAFERECOVER_MASK', + 'PCIE_LC_CNTL12__LC_RESET_TSX_CNT_ON_SAFERECOVER__SHIFT', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_DATA_UNLOCK_MASK', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_DATA_UNLOCK__SHIFT', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_ADAPT_MASK', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_ADAPT__SHIFT', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_RECOVER_MASK', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_RX_RECOVER__SHIFT', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_EVENT_SEL_MASK', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_EVENT_SEL__SHIFT', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_INIT_MASK', + 'PCIE_LC_CNTL12__LC_SAFE_RECOVER_SW_INIT__SHIFT', + 'PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK', + 'PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT', + 'PCIE_LC_CNTL12__LC_TRACK_RX_WAIT_FOR_TS1_MASK', + 'PCIE_LC_CNTL12__LC_TRACK_RX_WAIT_FOR_TS1__SHIFT', + 'PCIE_LC_CNTL12__LC_USE_LEGACY_RXSB1_SPDCHG_ELECIDLE_MASK', + 'PCIE_LC_CNTL12__LC_USE_LEGACY_RXSB1_SPDCHG_ELECIDLE__SHIFT', + 'PCIE_LC_CNTL12__LC_USE_LOOPBACK_INACTIVE_LANES_MASK', + 'PCIE_LC_CNTL12__LC_USE_LOOPBACK_INACTIVE_LANES__SHIFT', + 'PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK', + 'PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT', + 'PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK', + 'PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT', + 'PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK', + 'PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT', + 'PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK', + 'PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT', + 'PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK', + 'PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT', + 'PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK', + 'PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT', + 'PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK', + 'PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT', + 'PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK', + 'PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT', + 'PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK', + 'PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT', + 'PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK', + 'PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT', + 'PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK', + 'PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT', + 'PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK', + 'PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT', + 'PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK', + 'PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT', + 'PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK', + 'PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT', + 'PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK', + 'PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT', + 'PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK', + 'PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT', + 'PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK', + 'PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT', + 'PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK', + 'PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT', + 'PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK', + 'PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT', + 'PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK', + 'PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT', + 'PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK', + 'PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT', + 'PCIE_LC_CNTL3__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK', + 'PCIE_LC_CNTL3__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT', + 'PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK', + 'PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT', + 'PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK', + 'PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT', + 'PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK', + 'PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT', + 'PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK', + 'PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT', + 'PCIE_LC_CNTL4__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK', + 'PCIE_LC_CNTL4__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT', + 'PCIE_LC_CNTL4__LC_DELAY_COEFF_UPDATE_DIS_MASK', + 'PCIE_LC_CNTL4__LC_DELAY_COEFF_UPDATE_DIS__SHIFT', + 'PCIE_LC_CNTL4__LC_DELAY_DETECTED_TSX_RCV_EN_MASK', + 'PCIE_LC_CNTL4__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT', + 'PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK', + 'PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT', + 'PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK', + 'PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT', + 'PCIE_LC_CNTL4__LC_DONT_CHECK_EQTS_IN_RCFG_MASK', + 'PCIE_LC_CNTL4__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT', + 'PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK', + 'PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT', + 'PCIE_LC_CNTL4__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK', + 'PCIE_LC_CNTL4__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT', + 'PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK', + 'PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT', + 'PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK', + 'PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MODE_MASK', + 'PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MODE__SHIFT', + 'PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT', + 'PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK', + 'PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT', + 'PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK', + 'PCIE_LC_CNTL4__LC_L1_POWERDOWN__SHIFT', + 'PCIE_LC_CNTL4__LC_P2_ENTRY_MASK', + 'PCIE_LC_CNTL4__LC_P2_ENTRY__SHIFT', + 'PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK', + 'PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT', + 'PCIE_LC_CNTL4__LC_SEND_EIEOS_IN_RCFG_MASK', + 'PCIE_LC_CNTL4__LC_SEND_EIEOS_IN_RCFG__SHIFT', + 'PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK', + 'PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT', + 'PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK', + 'PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT', + 'PCIE_LC_CNTL4__LC_TX_SWING_MASK', + 'PCIE_LC_CNTL4__LC_TX_SWING__SHIFT', + 'PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK', + 'PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT', + 'PCIE_LC_CNTL4__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK', + 'PCIE_LC_CNTL4__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT', + 'PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK', + 'PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT', + 'PCIE_LC_CNTL4__LC_WAIT_FOR_TWO_EIEOS_SEQUENCE_MASK', + 'PCIE_LC_CNTL4__LC_WAIT_FOR_TWO_EIEOS_SEQUENCE__SHIFT', + 'PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK', + 'PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK', + 'PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT', + 'PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT', + 'PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK', + 'PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT', + 'PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK', + 'PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT', + 'PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK', + 'PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT', + 'PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK', + 'PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT', + 'PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK', + 'PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT', + 'PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK', + 'PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT', + 'PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK', + 'PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT', + 'PCIE_LC_CNTL5__LC_LOCAL_USE_PRESET_MASK', + 'PCIE_LC_CNTL5__LC_LOCAL_USE_PRESET__SHIFT', + 'PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK', + 'PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT', + 'PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK', + 'PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT', + 'PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK', + 'PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT', + 'PCIE_LC_CNTL6__LC_IGNORE_RETIMER_PRESENCE_MASK', + 'PCIE_LC_CNTL6__LC_IGNORE_RETIMER_PRESENCE__SHIFT', + 'PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK', + 'PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT', + 'PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE_MASK', + 'PCIE_LC_CNTL6__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT', + 'PCIE_LC_CNTL6__LC_RETIMER_PRESENCE_MASK', + 'PCIE_LC_CNTL6__LC_RETIMER_PRESENCE__SHIFT', + 'PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK', + 'PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT', + 'PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK', + 'PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT', + 'PCIE_LC_CNTL6__LC_SPC_MODE_32GT_MASK', + 'PCIE_LC_CNTL6__LC_SPC_MODE_32GT__SHIFT', + 'PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK', + 'PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT', + 'PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK', + 'PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK', + 'PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT', + 'PCIE_LC_CNTL6__LC_SRIS_EN_MASK', + 'PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT', + 'PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK', + 'PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT', + 'PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK', + 'PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT', + 'PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK', + 'PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT', + 'PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK', + 'PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT', + 'PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK', + 'PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT', + 'PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK', + 'PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT', + 'PCIE_LC_CNTL7__LC_ESM_RATES_MASK', + 'PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT', + 'PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK', + 'PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT', + 'PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK', + 'PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT', + 'PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK', + 'PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT', + 'PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK', + 'PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT', + 'PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK', + 'PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT', + 'PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK', + 'PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT', + 'PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK', + 'PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT', + 'PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK', + 'PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT', + 'PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK', + 'PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT', + 'PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK', + 'PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT', + 'PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK', + 'PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT', + 'PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK', + 'PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT', + 'PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK', + 'PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT', + 'PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK', + 'PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT', + 'PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK', + 'PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT', + 'PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK', + 'PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT', + 'PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK', + 'PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT', + 'PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK', + 'PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT', + 'PCIE_LC_CNTL8__LC_ESM_RATE0_TIMER_FACTOR_MASK', + 'PCIE_LC_CNTL8__LC_ESM_RATE0_TIMER_FACTOR__SHIFT', + 'PCIE_LC_CNTL8__LC_ESM_RATE1_TIMER_FACTOR_MASK', + 'PCIE_LC_CNTL8__LC_ESM_RATE1_TIMER_FACTOR__SHIFT', + 'PCIE_LC_CNTL8__LC_ESM_RATE2_TIMER_FACTOR_MASK', + 'PCIE_LC_CNTL8__LC_ESM_RATE2_TIMER_FACTOR__SHIFT', + 'PCIE_LC_CNTL8__LC_EX_SEARCH_TRAVERSAL_MODE_MASK', + 'PCIE_LC_CNTL8__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT', + 'PCIE_LC_CNTL8__LC_FOM_TIME_MASK', + 'PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT', + 'PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_LANE_UNDER_TEST_MASK', + 'PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_LANE_UNDER_TEST__SHIFT', + 'PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_ON_MASK', + 'PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_ON__SHIFT', + 'PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_MASK', + 'PCIE_LC_CNTL8__LC_FORCE_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN__SHIFT', + 'PCIE_LC_CNTL8__LC_LOCK_IN_EQ_RESPONSE_MASK', + 'PCIE_LC_CNTL8__LC_LOCK_IN_EQ_RESPONSE__SHIFT', + 'PCIE_LC_CNTL8__LC_LOOPBACK_EQ_IN_PROGRESS_MASK', + 'PCIE_LC_CNTL8__LC_LOOPBACK_EQ_IN_PROGRESS__SHIFT', + 'PCIE_LC_CNTL8__LC_LOOPBACK_EQ_LANE_UNDER_TEST_MASK', + 'PCIE_LC_CNTL8__LC_LOOPBACK_EQ_LANE_UNDER_TEST__SHIFT', + 'PCIE_LC_CNTL8__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_MASK', + 'PCIE_LC_CNTL8__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN__SHIFT', + 'PCIE_LC_CNTL8__LC_USC_ACCEPTABLE_PRESETS_MASK', + 'PCIE_LC_CNTL8__LC_USC_ACCEPTABLE_PRESETS__SHIFT', + 'PCIE_LC_CNTL9__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK', + 'PCIE_LC_CNTL9__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT', + 'PCIE_LC_CNTL9__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK', + 'PCIE_LC_CNTL9__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT', + 'PCIE_LC_CNTL9__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK', + 'PCIE_LC_CNTL9__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT', + 'PCIE_LC_CNTL9__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK', + 'PCIE_LC_CNTL9__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT', + 'PCIE_LC_CNTL9__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK', + 'PCIE_LC_CNTL9__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT', + 'PCIE_LC_CNTL9__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK', + 'PCIE_LC_CNTL9__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT', + 'PCIE_LC_CNTL9__LC_CONFIG_WAIT_FOR_EIEOS_MASK', + 'PCIE_LC_CNTL9__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT', + 'PCIE_LC_CNTL9__LC_CPM_IDLE_REFCLKREQ_CHECK_MASK', + 'PCIE_LC_CNTL9__LC_CPM_IDLE_REFCLKREQ_CHECK__SHIFT', + 'PCIE_LC_CNTL9__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK', + 'PCIE_LC_CNTL9__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT', + 'PCIE_LC_CNTL9__LC_DEC_FAILED_SPEED_CHANGE_COUNT_ABORT_BYPASS_TO_HIGH_RATE_MASK', + 'PCIE_LC_CNTL9__LC_DEC_FAILED_SPEED_CHANGE_COUNT_ABORT_BYPASS_TO_HIGH_RATE__SHIFT', + 'PCIE_LC_CNTL9__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK', + 'PCIE_LC_CNTL9__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT', + 'PCIE_LC_CNTL9__LC_DYN_LANES_L1_SS_POWERDOWN_MASK', + 'PCIE_LC_CNTL9__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT', + 'PCIE_LC_CNTL9__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK', + 'PCIE_LC_CNTL9__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT', + 'PCIE_LC_CNTL9__LC_EXT_ASPM_L12_COMMONMODE_COUNT_METHOD_MASK', + 'PCIE_LC_CNTL9__LC_EXT_ASPM_L12_COMMONMODE_COUNT_METHOD__SHIFT', + 'PCIE_LC_CNTL9__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK', + 'PCIE_LC_CNTL9__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT', + 'PCIE_LC_CNTL9__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK', + 'PCIE_LC_CNTL9__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT', + 'PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK', + 'PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT', + 'PCIE_LC_CNTL9__LC_LOOPBACK_EQ_ARC_EN_MASK', + 'PCIE_LC_CNTL9__LC_LOOPBACK_EQ_ARC_EN__SHIFT', + 'PCIE_LC_CNTL9__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_EN_MASK', + 'PCIE_LC_CNTL9__LC_LOOPBACK_EQ_TRANSMIT_MOD_COMP_PATTERN_EN__SHIFT', + 'PCIE_LC_CNTL9__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK', + 'PCIE_LC_CNTL9__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT', + 'PCIE_LC_CNTL9__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK', + 'PCIE_LC_CNTL9__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT', + 'PCIE_LC_CNTL9__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK', + 'PCIE_LC_CNTL9__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT', + 'PCIE_LC_CNTL9__LC_REFCLK_OFF_NO_RCVR_LANES_MASK', + 'PCIE_LC_CNTL9__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT', + 'PCIE_LC_CNTL9__LC_REPEAT_RXEQEVAL_AFTER_TIMEOUT_MASK', + 'PCIE_LC_CNTL9__LC_REPEAT_RXEQEVAL_AFTER_TIMEOUT__SHIFT', + 'PCIE_LC_CNTL9__LC_RESET_RCVR_DETECTED_ALL_ARCS_MASK', + 'PCIE_LC_CNTL9__LC_RESET_RCVR_DETECTED_ALL_ARCS__SHIFT', + 'PCIE_LC_CNTL9__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK', + 'PCIE_LC_CNTL9__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT', + 'PCIE_LC_CNTL9__LC_TRAINING_BITS_REQUIRED_MASK', + 'PCIE_LC_CNTL9__LC_TRAINING_BITS_REQUIRED__SHIFT', + 'PCIE_LC_CNTL9__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK', + 'PCIE_LC_CNTL9__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT', + 'PCIE_LC_CNTL9__LC_USE_NEW_EQ_SYMBOL_6_EN_MASK', + 'PCIE_LC_CNTL9__LC_USE_NEW_EQ_SYMBOL_6_EN__SHIFT', + 'PCIE_LC_CNTL9__LC_USE_OLD_PHYSTATUS_FOR_POWERDOWN_INACTIVE_MASK', + 'PCIE_LC_CNTL9__LC_USE_OLD_PHYSTATUS_FOR_POWERDOWN_INACTIVE__SHIFT', + 'PCIE_LC_CNTL9__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK', + 'PCIE_LC_CNTL9__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT', + 'PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK', + 'PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT', + 'PCIE_LC_CNTL__LC_ADVANCE_SPEED_COMPL_ON_EVERY_COMPL_ENTRY_MASK', + 'PCIE_LC_CNTL__LC_ADVANCE_SPEED_COMPL_ON_EVERY_COMPL_ENTRY__SHIFT', + 'PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK', + 'PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT', + 'PCIE_LC_CNTL__LC_DELAY_COUNT_MASK', + 'PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT', + 'PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK', + 'PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT', + 'PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK', + 'PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT', + 'PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK', + 'PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT', + 'PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK', + 'PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT', + 'PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK', + 'PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT', + 'PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK', + 'PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT', + 'PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK', + 'PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT', + 'PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK', + 'PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT', + 'PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK', + 'PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT', + 'PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK', + 'PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT', + 'PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK', + 'PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT', + 'PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK', + 'PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT', + 'PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK', + 'PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT', + 'PCIE_LC_CNTL__LC_RESET_LINK_MASK', + 'PCIE_LC_CNTL__LC_RESET_LINK__SHIFT', + 'PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK', + 'PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT', + 'PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK', + 'PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT', + 'PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK', + 'PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LC_PKT_GEN_DYN_CLK_GATING_MASK', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LC_PKT_GEN_DYN_CLK_GATING__SHIFT', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LTSSM_DYN_CLK_GATING_MASK', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_LTSSM_DYN_CLK_GATING__SHIFT', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_DYN_CLK_GATING_MASK', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_DYN_CLK_GATING__SHIFT', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK', + 'PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT', + 'PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK', + 'PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK', + 'PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT', + 'PCIE_LC_FORCE_COEFF3__LC_3X3_COEFF_SEARCH_EN_32GT_MASK', + 'PCIE_LC_FORCE_COEFF3__LC_3X3_COEFF_SEARCH_EN_32GT__SHIFT', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_COEFF_32GT_MASK', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_COEFF_32GT__SHIFT', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_CURSOR_32GT_MASK', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_CURSOR_32GT__SHIFT', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_POST_CURSOR_32GT_MASK', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_POST_CURSOR_32GT__SHIFT', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_PRE_CURSOR_32GT_MASK', + 'PCIE_LC_FORCE_COEFF3__LC_FORCE_PRE_CURSOR_32GT__SHIFT', + 'PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK', + 'PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK', + 'PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT', + 'PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK', + 'PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_32GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_32GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_CURSOR_REQ_32GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_CURSOR_REQ_32GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_POST_CURSOR_REQ_32GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_POST_CURSOR_REQ_32GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_PRE_CURSOR_REQ_32GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FORCE_PRE_CURSOR_REQ_32GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FS_OTHER_END_32GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_FS_OTHER_END_32GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_LF_OTHER_END_32GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF3__LC_LF_OTHER_END_32GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK', + 'PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_P2_EDGE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_P2_EDGE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_POWERDOWN_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_AUX_COUNT_REFCLK_INCREMENT_INTERNAL_POWERDOWN__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_POWERDOWN_P2_L1_2_EXIT_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_POWERDOWN_P2_L1_2_EXIT__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_REFCLK_L1_2_T_POWERON_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_DELAY_REFCLK_L1_2_T_POWERON__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK', + 'PCIE_LC_L1_PM_SUBSTATE2__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE3__T_POWER_ON_FCH_TARGET_ADDRESS_LO_MASK', + 'PCIE_LC_L1_PM_SUBSTATE3__T_POWER_ON_FCH_TARGET_ADDRESS_LO__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE4__T_POWER_ON_FCH_TARGET_ADDRESS_HI_MASK', + 'PCIE_LC_L1_PM_SUBSTATE4__T_POWER_ON_FCH_TARGET_ADDRESS_HI__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE5__LC_BLOCK_EI_L1_REFCLK_OFF_MASK', + 'PCIE_LC_L1_PM_SUBSTATE5__LC_BLOCK_EI_L1_REFCLK_OFF__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE5__LC_IGNORE_ALL_RX_ELEC_IDLE_IN_L1SS_MASK', + 'PCIE_LC_L1_PM_SUBSTATE5__LC_IGNORE_ALL_RX_ELEC_IDLE_IN_L1SS__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE5__T_POWER_ON_FCH_L12_CLKREQ_DELAY_MASK', + 'PCIE_LC_L1_PM_SUBSTATE5__T_POWER_ON_FCH_L12_CLKREQ_DELAY__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_USE_PCS_SIDEBAND_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_USE_PCS_SIDEBAND__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_BLOCK_EXIT_PG_COMMIT_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_BLOCK_EXIT_PG_COMMIT__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_1_ABORT_IN_L1_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_2_ABORT_IN_L1_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__LC_WAKE_FROM_ASPM_L1_ON_PM_CONTROL_CLEAR_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__LC_WAKE_FROM_ASPM_L1_ON_PM_CONTROL_CLEAR__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_EN_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_EN__SHIFT', + 'PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_TRIGGER_MASK', + 'PCIE_LC_L1_PM_SUBSTATE__T_POWER_ON_FCH_COPY_TRIGGER__SHIFT', + 'PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK', + 'PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK', + 'PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_32GT_CNTL_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_32GT_CNTL__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT', + 'PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT', + 'PCIE_LC_PM_CNTL2__LC_PORT_8_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL2__LC_PORT_8_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT', + 'PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK', + 'PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT', + 'PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EQ_SETTINGS_RESTORED_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EQ_SETTINGS_RESTORED__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK', + 'PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT', + 'PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK', + 'PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_AFTER_FAILED_EQ_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_AFTER_FAILED_EQ__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_ON_FAIL_SPEED_CHANGE_LIMIT_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_ABORT_AUTO_EQ_ON_FAIL_SPEED_CHANGE_LIMIT__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_ALLOW_SET_INITIATE_SPEED_CHANGE_IN_RECOVERY_LOCK_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_ALLOW_SET_INITIATE_SPEED_CHANGE_IN_RECOVERY_LOCK__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_DEFER_PRIVATE_SPEED_CHANGE_UNTIL_EXIT_RECOVERY_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_DEFER_PRIVATE_SPEED_CHANGE_UNTIL_EXIT_RECOVERY__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_DEFER_RETRAIN_LINK_UNTIL_EXIT_RECOVERY_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_DEFER_RETRAIN_LINK_UNTIL_EXIT_RECOVERY__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_DONT_UPDATE_GEN_SUPPORT_MID_RECOVERY_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_DONT_UPDATE_GEN_SUPPORT_MID_RECOVERY__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_ENFORCE_CORRECT_SPEED_FOR_EQ_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_ENFORCE_CORRECT_SPEED_FOR_EQ__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SINGLE_EQ_PER_RECOVERY_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SINGLE_EQ_PER_RECOVERY__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SOFTWARE_PERFORM_EQ_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_ENFORCE_SOFTWARE_PERFORM_EQ__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_HW_SPEED_CHANGE_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_SW_SPEED_CHANGE_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_INITIATE_LINK_SPEED_CHANGE_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L1_EN_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_SEND_EQ_TS2_IF_OTHER_SIDE_EVER_ADVERTISED_SPEED_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_SEND_EQ_TS2_IF_OTHER_SIDE_EVER_ADVERTISED_SPEED__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_STATUS_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_SPEED_CHANGE_STATUS__SHIFT', + 'PCIE_LC_SPEED_CNTL2__LC_USE_LEGACY_CLEAR_DELAY_DLLPs_MASK', + 'PCIE_LC_SPEED_CNTL2__LC_USE_LEGACY_CLEAR_DELAY_DLLPs__SHIFT', + 'PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'PCIE_LC_STATE0__LC_CURRENT_STATE_MASK', + 'PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT', + 'PCIE_LC_STATE0__LC_PREV_STATE1_MASK', + 'PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT', + 'PCIE_LC_STATE0__LC_PREV_STATE2_MASK', + 'PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT', + 'PCIE_LC_STATE0__LC_PREV_STATE3_MASK', + 'PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT', + 'PCIE_LC_STATE10__LC_PREV_STATE40_MASK', + 'PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT', + 'PCIE_LC_STATE10__LC_PREV_STATE41_MASK', + 'PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT', + 'PCIE_LC_STATE10__LC_PREV_STATE42_MASK', + 'PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT', + 'PCIE_LC_STATE10__LC_PREV_STATE43_MASK', + 'PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT', + 'PCIE_LC_STATE11__LC_PREV_STATE44_MASK', + 'PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT', + 'PCIE_LC_STATE11__LC_PREV_STATE45_MASK', + 'PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT', + 'PCIE_LC_STATE11__LC_PREV_STATE46_MASK', + 'PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT', + 'PCIE_LC_STATE11__LC_PREV_STATE47_MASK', + 'PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT', + 'PCIE_LC_STATE1__LC_PREV_STATE4_MASK', + 'PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT', + 'PCIE_LC_STATE1__LC_PREV_STATE5_MASK', + 'PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT', + 'PCIE_LC_STATE1__LC_PREV_STATE6_MASK', + 'PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT', + 'PCIE_LC_STATE1__LC_PREV_STATE7_MASK', + 'PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT', + 'PCIE_LC_STATE2__LC_PREV_STATE10_MASK', + 'PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT', + 'PCIE_LC_STATE2__LC_PREV_STATE11_MASK', + 'PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT', + 'PCIE_LC_STATE2__LC_PREV_STATE8_MASK', + 'PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT', + 'PCIE_LC_STATE2__LC_PREV_STATE9_MASK', + 'PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT', + 'PCIE_LC_STATE3__LC_PREV_STATE12_MASK', + 'PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT', + 'PCIE_LC_STATE3__LC_PREV_STATE13_MASK', + 'PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT', + 'PCIE_LC_STATE3__LC_PREV_STATE14_MASK', + 'PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT', + 'PCIE_LC_STATE3__LC_PREV_STATE15_MASK', + 'PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT', + 'PCIE_LC_STATE4__LC_PREV_STATE16_MASK', + 'PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT', + 'PCIE_LC_STATE4__LC_PREV_STATE17_MASK', + 'PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT', + 'PCIE_LC_STATE4__LC_PREV_STATE18_MASK', + 'PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT', + 'PCIE_LC_STATE4__LC_PREV_STATE19_MASK', + 'PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT', + 'PCIE_LC_STATE5__LC_PREV_STATE20_MASK', + 'PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT', + 'PCIE_LC_STATE5__LC_PREV_STATE21_MASK', + 'PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT', + 'PCIE_LC_STATE5__LC_PREV_STATE22_MASK', + 'PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT', + 'PCIE_LC_STATE5__LC_PREV_STATE23_MASK', + 'PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT', + 'PCIE_LC_STATE6__LC_PREV_STATE24_MASK', + 'PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT', + 'PCIE_LC_STATE6__LC_PREV_STATE25_MASK', + 'PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT', + 'PCIE_LC_STATE6__LC_PREV_STATE26_MASK', + 'PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT', + 'PCIE_LC_STATE6__LC_PREV_STATE27_MASK', + 'PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT', + 'PCIE_LC_STATE7__LC_PREV_STATE28_MASK', + 'PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT', + 'PCIE_LC_STATE7__LC_PREV_STATE29_MASK', + 'PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT', + 'PCIE_LC_STATE7__LC_PREV_STATE30_MASK', + 'PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT', + 'PCIE_LC_STATE7__LC_PREV_STATE31_MASK', + 'PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT', + 'PCIE_LC_STATE8__LC_PREV_STATE32_MASK', + 'PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT', + 'PCIE_LC_STATE8__LC_PREV_STATE33_MASK', + 'PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT', + 'PCIE_LC_STATE8__LC_PREV_STATE34_MASK', + 'PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT', + 'PCIE_LC_STATE8__LC_PREV_STATE35_MASK', + 'PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT', + 'PCIE_LC_STATE9__LC_PREV_STATE36_MASK', + 'PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT', + 'PCIE_LC_STATE9__LC_PREV_STATE37_MASK', + 'PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT', + 'PCIE_LC_STATE9__LC_PREV_STATE38_MASK', + 'PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT', + 'PCIE_LC_STATE9__LC_PREV_STATE39_MASK', + 'PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT', + 'PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK', + 'PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT', + 'PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK', + 'PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT', + 'PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK', + 'PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT', + 'PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK', + 'PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT', + 'PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK', + 'PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT', + 'PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK', + 'PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT', + 'PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK', + 'PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT', + 'PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS_MASK', + 'PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS__SHIFT', + 'PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS_MASK', + 'PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS__SHIFT', + 'PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT_MASK', + 'PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT__SHIFT', + 'PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN_MASK', + 'PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN__SHIFT', + 'PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT_MASK', + 'PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT__SHIFT', + 'PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN_MASK', + 'PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN__SHIFT', + 'PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS_MASK', + 'PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS__SHIFT', + 'PCIE_MST_CTRL_1__MST_SDP_CREDITS_LIVE_OVERRIDE_DIS_MASK', + 'PCIE_MST_CTRL_1__MST_SDP_CREDITS_LIVE_OVERRIDE_DIS__SHIFT', + 'PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK', + 'PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT', + 'PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK', + 'PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK1_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK1__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK2_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_LCLK2__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK1_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK1__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK2_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_LCLK2__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK', + 'PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK', + 'PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT', + 'PCIE_PERF_CNTL_TXCLK10__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK10__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK10__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK10__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK10__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK10__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK10__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK10__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK1__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK1__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK1__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK1__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK2__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK2__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK2__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK2__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK3__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK3__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK3__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK3__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK4__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK4__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK4__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK4__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK5__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK5__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK5__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK5__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK5__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK5__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK5__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK5__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK6__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK6__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK6__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK6__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK6__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK6__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK6__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK6__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK7__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK7__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK7__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK7__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK7__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK7__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK8__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK8__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK8__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK8__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK8__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK8__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK8__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK8__EVENT1_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK9__COUNTER0_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK9__COUNTER0_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK9__COUNTER1_FULL_MASK', + 'PCIE_PERF_CNTL_TXCLK9__COUNTER1_FULL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK9__EVENT0_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK9__EVENT0_SEL__SHIFT', + 'PCIE_PERF_CNTL_TXCLK9__EVENT1_SEL_MASK', + 'PCIE_PERF_CNTL_TXCLK9__EVENT1_SEL__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK10__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK10__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK5__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK5__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK6__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK6__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK7__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK7__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK8__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK8__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT0_TXCLK9__COUNTER0_MASK', + 'PCIE_PERF_COUNT0_TXCLK9__COUNTER0__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK10__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK10__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK5__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK5__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK6__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK6__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK7__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK7__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK8__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK8__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT1_TXCLK9__COUNTER1_MASK', + 'PCIE_PERF_COUNT1_TXCLK9__COUNTER1__SHIFT', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_LCLK_STATUS_MASK', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_LCLK_STATUS__SHIFT', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK', + 'PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT', + 'PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK', + 'PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT', + 'PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK', + 'PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT', + 'PCIE_PGMST_CNTL__CFG_PG_EN_MASK', + 'PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT', + 'PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK', + 'PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT', + 'PCIE_PGMST_CNTL__PG_EXIT_TIMER_MASK', + 'PCIE_PGMST_CNTL__PG_EXIT_TIMER__SHIFT', + 'PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK', + 'PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT', + 'PCIE_PRBS_CLR__PRBS_CLR_MASK', 'PCIE_PRBS_CLR__PRBS_CLR__SHIFT', + 'PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK', + 'PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT', + 'PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK', + 'PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT', + 'PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK', + 'PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT', + 'PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK', + 'PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT', + 'PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK', + 'PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT', + 'PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK', + 'PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT', + 'PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK', + 'PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT', + 'PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK', + 'PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT', + 'PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK', + 'PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT', + 'PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK', + 'PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT', + 'PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK', + 'PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT', + 'PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK', + 'PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT', + 'PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK', + 'PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT', + 'PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK', + 'PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT', + 'PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK', + 'PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT', + 'PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK', + 'PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT', + 'PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK', + 'PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT', + 'PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK', + 'PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT', + 'PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK', + 'PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT', + 'PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK', + 'PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT', + 'PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK', + 'PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT', + 'PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK', + 'PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT', + 'PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK', + 'PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT', + 'PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK', + 'PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT', + 'PCIE_PRBS_MISC__PRBS_EN_MASK', 'PCIE_PRBS_MISC__PRBS_EN__SHIFT', + 'PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK', + 'PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT', + 'PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK', + 'PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT', + 'PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK', + 'PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT', + 'PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK', + 'PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT', + 'PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK', + 'PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT', + 'PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK', + 'PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT', + 'PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK', + 'PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT', + 'PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK', + 'PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT', + 'PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK', + 'PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT', + 'PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK', + 'PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT', + 'PCIE_P_CNTL__LC_FILTER_SKP_FROM_L_IDLE_MASK', + 'PCIE_P_CNTL__LC_FILTER_SKP_FROM_L_IDLE__SHIFT', + 'PCIE_P_CNTL__LC_MISSING_COM_RESET_SET_TRACK_MASK', + 'PCIE_P_CNTL__LC_MISSING_COM_RESET_SET_TRACK__SHIFT', + 'PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK', + 'PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT', + 'PCIE_P_CNTL__LC_RESET_TRACK_TSX_COUNTER_NO_DATA_VLD_MASK', + 'PCIE_P_CNTL__LC_RESET_TRACK_TSX_COUNTER_NO_DATA_VLD__SHIFT', + 'PCIE_P_CNTL__LC_TIEOFF_LANES_IGNORE_REFCLKACK_MASK', + 'PCIE_P_CNTL__LC_TIEOFF_LANES_IGNORE_REFCLKACK__SHIFT', + 'PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK', + 'PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT', + 'PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK', + 'PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT', + 'PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK', + 'PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT', + 'PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK', + 'PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT', + 'PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK', + 'PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT', + 'PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK', + 'PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT', + 'PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK', + 'PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT', + 'PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK', + 'PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT', + 'PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK', + 'PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT', + 'PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK', + 'PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT', + 'PCIE_P_CNTL__P_PWRDN_EN_MASK', 'PCIE_P_CNTL__P_PWRDN_EN__SHIFT', + 'PCIE_P_CNTL__P_SYMALIGN_MODE_MASK', + 'PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT', + 'PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK', + 'PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT', + 'PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK', + 'PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT', + 'PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK', + 'PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT', + 'PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK', + 'PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT', + 'PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK', + 'PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT', + 'PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK', + 'PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT', + 'PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK', + 'PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT', + 'PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK', + 'PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT', + 'PCIE_RESERVED__RESERVED_MASK', 'PCIE_RESERVED__RESERVED__SHIFT', + 'PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK', + 'PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT', + 'PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK', + 'PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT', + 'PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK', + 'PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT', + 'PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK', + 'PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT', + 'PCIE_RXMARGIN_2_SETTINGS__ENABLE_PRECODING_MASK', + 'PCIE_RXMARGIN_2_SETTINGS__ENABLE_PRECODING__SHIFT', + 'PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK', + 'PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT', + 'PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK', + 'PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT', + 'PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK', + 'PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT', + 'PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK', + 'PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT', + 'PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK', + 'PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK', + 'PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT', + 'PCIE_RX_AD__RC_IGNORE_ACS_ERR_ON_DRS_DIS_MASK', + 'PCIE_RX_AD__RC_IGNORE_ACS_ERR_ON_DRS_DIS__SHIFT', + 'PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK', + 'PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT', + 'PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK', + 'PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT', + 'PCIE_RX_AD__RX_RC_DROP_VDM0_MASK', + 'PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT', + 'PCIE_RX_AD__RX_RC_DROP_VDM1_MASK', + 'PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT', + 'PCIE_RX_AD__RX_RC_LARGE_VDM_BFRC_EN_MASK', + 'PCIE_RX_AD__RX_RC_LARGE_VDM_BFRC_EN__SHIFT', + 'PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK', + 'PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT', + 'PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK', + 'PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT', + 'PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK', + 'PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT', + 'PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK', + 'PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT', + 'PCIE_RX_AD__RX_RC_UR_VDM0_MASK', + 'PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT', + 'PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK', + 'PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT', + 'PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK', + 'PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT', + 'PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK', + 'PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT', + 'PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK', + 'PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT', + 'PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK', + 'PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT', + 'PCIE_RX_AD__RX_SWUS_IGNORE_ROUTING_ON_VDM_EN_MASK', + 'PCIE_RX_AD__RX_SWUS_IGNORE_ROUTING_ON_VDM_EN__SHIFT', + 'PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK', + 'PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT', + 'PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK', + 'PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT', + 'PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK', + 'PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT', + 'PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK', + 'PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT', + 'PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK', + 'PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT', + 'PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK', + 'PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT', + 'PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK', + 'PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT', + 'PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK', + 'PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT', + 'PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK', + 'PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT', + 'PCIE_RX_CNTL3__RX_ENH_ATOMIC_EN_MASK', + 'PCIE_RX_CNTL3__RX_ENH_ATOMIC_EN__SHIFT', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK', + 'PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT', + 'PCIE_RX_CNTL3__RX_INGRESS_POISONED_BLOCKING_EN_MASK', + 'PCIE_RX_CNTL3__RX_INGRESS_POISONED_BLOCKING_EN__SHIFT', + 'PCIE_RX_CNTL3__RX_PRIV_POISON_EGRESS_BLOCK_EN_MASK', + 'PCIE_RX_CNTL3__RX_PRIV_POISON_EGRESS_BLOCK_EN__SHIFT', + 'PCIE_RX_CNTL3__RX_SWAP_RTRC_TO_BFRC_HDR_ONLY_ENABLE_MASK', + 'PCIE_RX_CNTL3__RX_SWAP_RTRC_TO_BFRC_HDR_ONLY_ENABLE__SHIFT', + 'PCIE_RX_CNTL4__CI_ATS_RO_DIS_MASK', + 'PCIE_RX_CNTL4__CI_ATS_RO_DIS__SHIFT', + 'PCIE_RX_CNTL4__RX_CTO_CPL_REFCLK_SPEED_MASK', + 'PCIE_RX_CNTL4__RX_CTO_CPL_REFCLK_SPEED__SHIFT', + 'PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE1_E_F_DIS_MASK', + 'PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE1_E_F_DIS__SHIFT', + 'PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE4_DIS_MASK', + 'PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_OPTYPE4_DIS__SHIFT', + 'PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_TPH_DIS_MASK', + 'PCIE_RX_CNTL4__RX_ENH_ATOMIC_UR_TPH_DIS__SHIFT', + 'PCIE_RX_CNTL4__RX_NAK_COUNTER_MODE_MASK', + 'PCIE_RX_CNTL4__RX_NAK_COUNTER_MODE__SHIFT', + 'PCIE_RX_CNTL4__RX_OVERFLOW_PRIV_MASK_MASK', + 'PCIE_RX_CNTL4__RX_OVERFLOW_PRIV_MASK__SHIFT', + 'PCIE_RX_CNTL4__RX_PD_OVERFLOW_FIX_DISABLE_MASK', + 'PCIE_RX_CNTL4__RX_PD_OVERFLOW_FIX_DISABLE__SHIFT', + 'PCIE_RX_CNTL4__RX_SF_FILTERING_END_FROM_DLLP_DIS_MASK', + 'PCIE_RX_CNTL4__RX_SF_FILTERING_END_FROM_DLLP_DIS__SHIFT', + 'PCIE_RX_CNTL5__RX_SB_ARB_LOWER_LIMIT_MASK', + 'PCIE_RX_CNTL5__RX_SB_ARB_LOWER_LIMIT__SHIFT', + 'PCIE_RX_CNTL5__RX_SB_ARB_MODE_MASK', + 'PCIE_RX_CNTL5__RX_SB_ARB_MODE__SHIFT', + 'PCIE_RX_CNTL5__RX_SB_ARB_UPPER_LIMIT_MASK', + 'PCIE_RX_CNTL5__RX_SB_ARB_UPPER_LIMIT__SHIFT', + 'PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK', + 'PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT', + 'PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK', + 'PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT', + 'PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK', + 'PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT', + 'PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK', + 'PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT', + 'PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK', + 'PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT', + 'PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK', + 'PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT', + 'PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK', + 'PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT', + 'PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK', + 'PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT', + 'PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK', + 'PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT', + 'PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK', + 'PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT', + 'PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK', + 'PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT', + 'PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK', + 'PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT', + 'PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK', + 'PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT', + 'PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK', + 'PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT', + 'PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK', + 'PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT', + 'PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK', + 'PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT', + 'PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'PCIE_SDP_CTRL2__CI_VIRTUAL_WIRE_DIS_MASK', + 'PCIE_SDP_CTRL2__CI_VIRTUAL_WIRE_DIS__SHIFT', + 'PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK', + 'PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT', + 'PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK', + 'PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT', + 'PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN_MASK', + 'PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN__SHIFT', + 'PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK', + 'PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT', + 'PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK', + 'PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT', + 'PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK', + 'PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT', + 'PCIE_SDP_CTRL__CI_SLV_SDP_PARITY_CHECK_EN_MASK', + 'PCIE_SDP_CTRL__CI_SLV_SDP_PARITY_CHECK_EN__SHIFT', + 'PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK', + 'PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT', + 'PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_BIT46_EN_MASK', + 'PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_BIT46_EN__SHIFT', + 'PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK', + 'PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT', + 'PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK', + 'PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT', + 'PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK', + 'PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT', + 'PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK', + 'PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT', + 'PCIE_SDP_CTRL__SDP_UNIT_ID_MASK', + 'PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT', + 'PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK', + 'PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT', + 'PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK', + 'PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK', + 'PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK', + 'PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK', + 'PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK', + 'PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK', + 'PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT', + 'PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK', + 'PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT', + 'PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK', + 'PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT', + 'PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK', + 'PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_DRS_SUPPORTED_MASK', + 'PCIE_STRAP_MISC2__STRAP_DRS_SUPPORTED__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_EN_MASK', + 'PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_EN__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_MAX_DEPTH_MASK', + 'PCIE_STRAP_MISC2__STRAP_FRS_QUEUE_MAX_DEPTH__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_FRS_SUPPORTED_MASK', + 'PCIE_STRAP_MISC2__STRAP_FRS_SUPPORTED__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK', + 'PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK', + 'PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK', + 'PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_GEN5_COMPLIANCE_MASK', + 'PCIE_STRAP_MISC2__STRAP_GEN5_COMPLIANCE__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_IMMEDIATE_READINESS_EN_MASK', + 'PCIE_STRAP_MISC2__STRAP_IMMEDIATE_READINESS_EN__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK', + 'PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_RTR_EN_MASK', + 'PCIE_STRAP_MISC2__STRAP_RTR_EN__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_RTR_RESET_TIME_MASK', + 'PCIE_STRAP_MISC2__STRAP_RTR_RESET_TIME__SHIFT', + 'PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'PCIE_STRAP_MISC__STRAP_16GT_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_32GT_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_32GT_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK', + 'PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT', + 'PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_DLF_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK', + 'PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT', + 'PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_NPEM_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_NPEM_EN__SHIFT', + 'PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK', + 'PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT', + 'PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK', + 'PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT', + 'PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK', + 'PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT', + 'PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK', + 'PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT', + 'PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK', + 'PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_FC_ARB_ENABLE_MASK', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_FC_ARB_ENABLE__SHIFT', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_ADJUSTMENT_MASK', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_ADJUSTMENT__SHIFT', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_SCALE_MASK', + 'PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_SCALE__SHIFT', + 'PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK', + 'PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT', + 'PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK', + 'PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT', + 'PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK', + 'PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT', + 'PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK', + 'PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT', + 'PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK', + 'PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT', + 'PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK', + 'PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK', + 'PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT', + 'PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK', + 'PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT', + 'PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK', + 'PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT', + 'PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK', + 'PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT', + 'PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK', + 'PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT', + 'PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK', + 'PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT', + 'PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK', + 'PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK', + 'PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT', + 'PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW_MASK', + 'PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW__SHIFT', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK', + 'PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT', + 'PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK', + 'PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT', + 'PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK', + 'PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT', + 'PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK', + 'PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT', + 'PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK', + 'PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT', + 'PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK', + 'PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT', + 'PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK', + 'PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_ALL_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_ALL__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_DISABLE_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_DISABLE__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_FORCE_WRSCH_ACK_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_FORCE_WRSCH_ACK__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_ROLLOVER_EN_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_ROLLOVER_EN__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_STALL_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_STALL__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK', + 'PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT', + 'PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT', + 'PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_BUS_MASK', + 'PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_BUS__SHIFT', + 'PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_DEVICE_MASK', + 'PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_DEVICE__SHIFT', + 'PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_FUNCTION_MASK', + 'PCIE_TX_REQUESTER_ID__TX_SWUS_REQUESTER_ID_FUNCTION__SHIFT', + 'PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK', + 'PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT', + 'PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK', + 'PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK', + 'PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT', + 'PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT', + 'PCIE_TX_SEQ__TX_ACKD_SEQ_MASK', + 'PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT', + 'PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK', + 'PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT', + 'PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK', + 'PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT', + 'PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK', + 'PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT', + 'PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK', + 'PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT', + 'PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK', + 'PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT', + 'PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK', + 'PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT', + 'PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK', + 'PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT', + 'PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK', + 'PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT', + 'PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK', + 'PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT', + 'PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK', + 'PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT', + 'PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK', + 'PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT', + 'PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK', + 'PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT', + 'PCIE_TX_STATUS__TX_MST_MEM_READY_MASK', + 'PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT', + 'PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK', + 'PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT', + 'PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK', + 'PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT', + 'PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK', + 'PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT', + 'PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK', + 'PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK', + 'PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT', + 'PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK', + 'PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT', + 'PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK', + 'PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK', + 'PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT', + 'PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK', + 'PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT', + 'PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK', + 'PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT', + 'PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK', + 'PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT', + 'PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK', + 'PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT', + 'PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK', + 'PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT', + 'PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK', + 'PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT', + 'PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK', + 'PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT', + 'PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK', + 'PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT', + 'PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK', + 'PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT', + 'PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'PSWUSCFG0_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'PSWUSCFG0_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'PSWUSCFG0_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'PSWUSCFG0_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'PSWUSCFG0_0_BASE_CLASS__BASE_CLASS_MASK', + 'PSWUSCFG0_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'PSWUSCFG0_0_BIST__BIST_CAP_MASK', + 'PSWUSCFG0_0_BIST__BIST_CAP__SHIFT', + 'PSWUSCFG0_0_BIST__BIST_COMP_MASK', + 'PSWUSCFG0_0_BIST__BIST_COMP__SHIFT', + 'PSWUSCFG0_0_BIST__BIST_STRT_MASK', + 'PSWUSCFG0_0_BIST__BIST_STRT__SHIFT', + 'PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'PSWUSCFG0_0_CAP_PTR__CAP_PTR_MASK', + 'PSWUSCFG0_0_CAP_PTR__CAP_PTR__SHIFT', + 'PSWUSCFG0_0_COMMAND__AD_STEPPING_MASK', + 'PSWUSCFG0_0_COMMAND__AD_STEPPING__SHIFT', + 'PSWUSCFG0_0_COMMAND__BUS_MASTER_EN_MASK', + 'PSWUSCFG0_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'PSWUSCFG0_0_COMMAND__FAST_B2B_EN_MASK', + 'PSWUSCFG0_0_COMMAND__FAST_B2B_EN__SHIFT', + 'PSWUSCFG0_0_COMMAND__INT_DIS_MASK', + 'PSWUSCFG0_0_COMMAND__INT_DIS__SHIFT', + 'PSWUSCFG0_0_COMMAND__IO_ACCESS_EN_MASK', + 'PSWUSCFG0_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN_MASK', + 'PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN_MASK', + 'PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'PSWUSCFG0_0_COMMAND__SERR_EN_MASK', + 'PSWUSCFG0_0_COMMAND__SERR_EN__SHIFT', + 'PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'PSWUSCFG0_0_DEVICE_ID__DEVICE_ID_MASK', + 'PSWUSCFG0_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS2__RESERVED_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'PSWUSCFG0_0_HEADER__DEVICE_TYPE_MASK', + 'PSWUSCFG0_0_HEADER__DEVICE_TYPE__SHIFT', + 'PSWUSCFG0_0_HEADER__HEADER_TYPE_MASK', + 'PSWUSCFG0_0_HEADER__HEADER_TYPE__SHIFT', + 'PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_MASK', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_0_LATENCY__LATENCY_TIMER_MASK', + 'PSWUSCFG0_0_LATENCY__LATENCY_TIMER__SHIFT', + 'PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP_16GT__RESERVED_MASK', + 'PSWUSCFG0_0_LINK_CAP_16GT__RESERVED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'PSWUSCFG0_0_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED_MASK', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED_MASK', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED_MASK', + 'PSWUSCFG0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED_MASK', + 'PSWUSCFG0_0_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__LINK_SPEED_MASK', + 'PSWUSCFG0_0_LINK_CAP__LINK_SPEED__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__LINK_WIDTH_MASK', + 'PSWUSCFG0_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__PM_SUPPORT_MASK', + 'PSWUSCFG0_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__PORT_NUMBER_MASK', + 'PSWUSCFG0_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED_MASK', + 'PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE_MASK', + 'PSWUSCFG0_0_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED_MASK', + 'PSWUSCFG0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE_MASK', + 'PSWUSCFG0_0_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__LINK_DIS_MASK', + 'PSWUSCFG0_0_LINK_CNTL__LINK_DIS__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__PM_CONTROL_MASK', + 'PSWUSCFG0_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'PSWUSCFG0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'PSWUSCFG0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE_MASK', + 'PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING_MASK', + 'PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'PSWUSCFG0_0_MSI_MSG_DATA__MSI_EXT_DATA_MASK', + 'PSWUSCFG0_0_MSI_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'PSWUSCFG0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'PSWUSCFG0_0_PCIE_CAP__VERSION_MASK', + 'PSWUSCFG0_0_PCIE_CAP__VERSION__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__AUX_CURRENT_MASK', + 'PSWUSCFG0_0_PMI_CAP__AUX_CURRENT__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__D1_SUPPORT_MASK', + 'PSWUSCFG0_0_PMI_CAP__D1_SUPPORT__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__D2_SUPPORT_MASK', + 'PSWUSCFG0_0_PMI_CAP__D2_SUPPORT__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__PME_CLOCK_MASK', + 'PSWUSCFG0_0_PMI_CAP__PME_CLOCK__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__PME_SUPPORT_MASK', + 'PSWUSCFG0_0_PMI_CAP__PME_SUPPORT__SHIFT', + 'PSWUSCFG0_0_PMI_CAP__VERSION_MASK', + 'PSWUSCFG0_0_PMI_CAP__VERSION__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID_MASK', + 'PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'PSWUSCFG0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'PSWUSCFG0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'PSWUSCFG0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID_MASK', + 'PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'PSWUSCFG0_0_STATUS__CAP_LIST_MASK', + 'PSWUSCFG0_0_STATUS__CAP_LIST__SHIFT', + 'PSWUSCFG0_0_STATUS__DEVSEL_TIMING_MASK', + 'PSWUSCFG0_0_STATUS__DEVSEL_TIMING__SHIFT', + 'PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS_MASK', + 'PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'PSWUSCFG0_0_STATUS__INT_STATUS_MASK', + 'PSWUSCFG0_0_STATUS__INT_STATUS__SHIFT', + 'PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'PSWUSCFG0_0_STATUS__PCI_66_CAP_MASK', + 'PSWUSCFG0_0_STATUS__PCI_66_CAP__SHIFT', + 'PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'PSWUSCFG0_0_SUB_CLASS__SUB_CLASS_MASK', + 'PSWUSCFG0_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH_MASK', + 'PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_0_VENDOR_ID__VENDOR_ID_MASK', + 'PSWUSCFG0_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'PSWUSCFG0_1_BASE_ADDR_1__BASE_ADDR_MASK', + 'PSWUSCFG0_1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'PSWUSCFG0_1_BASE_ADDR_2__BASE_ADDR_MASK', + 'PSWUSCFG0_1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'PSWUSCFG0_1_BASE_CLASS__BASE_CLASS_MASK', + 'PSWUSCFG0_1_BASE_CLASS__BASE_CLASS__SHIFT', + 'PSWUSCFG0_1_BIST__BIST_CAP_MASK', + 'PSWUSCFG0_1_BIST__BIST_CAP__SHIFT', + 'PSWUSCFG0_1_BIST__BIST_COMP_MASK', + 'PSWUSCFG0_1_BIST__BIST_COMP__SHIFT', + 'PSWUSCFG0_1_BIST__BIST_STRT_MASK', + 'PSWUSCFG0_1_BIST__BIST_STRT__SHIFT', + 'PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'PSWUSCFG0_1_CAP_PTR__CAP_PTR_MASK', + 'PSWUSCFG0_1_CAP_PTR__CAP_PTR__SHIFT', + 'PSWUSCFG0_1_COMMAND__AD_STEPPING_MASK', + 'PSWUSCFG0_1_COMMAND__AD_STEPPING__SHIFT', + 'PSWUSCFG0_1_COMMAND__BUS_MASTER_EN_MASK', + 'PSWUSCFG0_1_COMMAND__BUS_MASTER_EN__SHIFT', + 'PSWUSCFG0_1_COMMAND__FAST_B2B_EN_MASK', + 'PSWUSCFG0_1_COMMAND__FAST_B2B_EN__SHIFT', + 'PSWUSCFG0_1_COMMAND__INT_DIS_MASK', + 'PSWUSCFG0_1_COMMAND__INT_DIS__SHIFT', + 'PSWUSCFG0_1_COMMAND__IO_ACCESS_EN_MASK', + 'PSWUSCFG0_1_COMMAND__IO_ACCESS_EN__SHIFT', + 'PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN_MASK', + 'PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN_MASK', + 'PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'PSWUSCFG0_1_COMMAND__SERR_EN_MASK', + 'PSWUSCFG0_1_COMMAND__SERR_EN__SHIFT', + 'PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'PSWUSCFG0_1_DEVICE_ID__DEVICE_ID_MASK', + 'PSWUSCFG0_1_DEVICE_ID__DEVICE_ID__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS2__RESERVED_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS2__RESERVED__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED_MASK', + 'PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'PSWUSCFG0_1_HEADER__DEVICE_TYPE_MASK', + 'PSWUSCFG0_1_HEADER__DEVICE_TYPE__SHIFT', + 'PSWUSCFG0_1_HEADER__HEADER_TYPE_MASK', + 'PSWUSCFG0_1_HEADER__HEADER_TYPE__SHIFT', + 'PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_MASK', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK', + 'PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'PSWUSCFG0_1_LATENCY__LATENCY_TIMER_MASK', + 'PSWUSCFG0_1_LATENCY__LATENCY_TIMER__SHIFT', + 'PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP_16GT__RESERVED_MASK', + 'PSWUSCFG0_1_LINK_CAP_16GT__RESERVED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'PSWUSCFG0_1_LINK_CAP_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED_MASK', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_0_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED_MASK', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_1_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED_MASK', + 'PSWUSCFG0_1_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE_2_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED_MASK', + 'PSWUSCFG0_1_LINK_CAP_32GT__NO_EQUALIZATION_NEEDED_SUPPORTED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__LINK_SPEED_MASK', + 'PSWUSCFG0_1_LINK_CAP__LINK_SPEED__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__LINK_WIDTH_MASK', + 'PSWUSCFG0_1_LINK_CAP__LINK_WIDTH__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__PM_SUPPORT_MASK', + 'PSWUSCFG0_1_LINK_CAP__PM_SUPPORT__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__PORT_NUMBER_MASK', + 'PSWUSCFG0_1_LINK_CAP__PORT_NUMBER__SHIFT', + 'PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED_MASK', + 'PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE_MASK', + 'PSWUSCFG0_1_LINK_CNTL_32GT__EQUALIZATION_BYPASS_TO_HIGHEST_RATE_DISABLE__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED_MASK', + 'PSWUSCFG0_1_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SELECTED__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE_MASK', + 'PSWUSCFG0_1_LINK_CNTL_32GT__NO_EQUALIZATION_NEEDED_DISABLE__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__LINK_DIS_MASK', + 'PSWUSCFG0_1_LINK_CNTL__LINK_DIS__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__PM_CONTROL_MASK', + 'PSWUSCFG0_1_LINK_CNTL__PM_CONTROL__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'PSWUSCFG0_1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK_MASK', + 'PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__NO_EQUALIZATION_NEEDED_RECEIVED__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOUR_CONTROL__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'PSWUSCFG0_1_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE_MASK', + 'PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING_MASK', + 'PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN_MASK', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA_MASK', + 'PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'PSWUSCFG0_1_MSI_MSG_DATA__MSI_EXT_DATA_MASK', + 'PSWUSCFG0_1_MSI_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'PSWUSCFG0_1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE_MASK', + 'PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'PSWUSCFG0_1_PCIE_CAP__VERSION_MASK', + 'PSWUSCFG0_1_PCIE_CAP__VERSION__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK', + 'PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT', + 'PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__AUX_CURRENT_MASK', + 'PSWUSCFG0_1_PMI_CAP__AUX_CURRENT__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__D1_SUPPORT_MASK', + 'PSWUSCFG0_1_PMI_CAP__D1_SUPPORT__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__D2_SUPPORT_MASK', + 'PSWUSCFG0_1_PMI_CAP__D2_SUPPORT__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__PME_CLOCK_MASK', + 'PSWUSCFG0_1_PMI_CAP__PME_CLOCK__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__PME_SUPPORT_MASK', + 'PSWUSCFG0_1_PMI_CAP__PME_SUPPORT__SHIFT', + 'PSWUSCFG0_1_PMI_CAP__VERSION_MASK', + 'PSWUSCFG0_1_PMI_CAP__VERSION__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID_MASK', + 'PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID_MASK', + 'PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'PSWUSCFG0_1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'PSWUSCFG0_1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'PSWUSCFG0_1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID_MASK', + 'PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'PSWUSCFG0_1_STATUS__CAP_LIST_MASK', + 'PSWUSCFG0_1_STATUS__CAP_LIST__SHIFT', + 'PSWUSCFG0_1_STATUS__DEVSEL_TIMING_MASK', + 'PSWUSCFG0_1_STATUS__DEVSEL_TIMING__SHIFT', + 'PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE_MASK', + 'PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS_MASK', + 'PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'PSWUSCFG0_1_STATUS__INT_STATUS_MASK', + 'PSWUSCFG0_1_STATUS__INT_STATUS__SHIFT', + 'PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'PSWUSCFG0_1_STATUS__PCI_66_CAP_MASK', + 'PSWUSCFG0_1_STATUS__PCI_66_CAP__SHIFT', + 'PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'PSWUSCFG0_1_SUB_CLASS__SUB_CLASS_MASK', + 'PSWUSCFG0_1_SUB_CLASS__SUB_CLASS__SHIFT', + 'PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH_MASK', + 'PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_1_VENDOR_ID__VENDOR_ID_MASK', + 'PSWUSCFG0_1_VENDOR_ID__VENDOR_ID__SHIFT', + 'PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_MASK', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'PSWUSCFG0_SSID_CAP_LIST__CAP_ID_MASK', + 'PSWUSCFG0_SSID_CAP_LIST__CAP_ID__SHIFT', + 'PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR_MASK', + 'PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID_MASK', + 'PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK', + 'PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_POIS_TLP_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_POIS_TLP__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT', + 'PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT', + 'PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK', + 'PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN5_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN5__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN5_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN5__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK', + 'PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK', + 'PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_3_EN_MASK', + 'PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_3_EN__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_ON_SURPDN_EN_MASK', + 'PSWUSP0_PCIE_RX_CNTL__DPC_PRIV_TRIGGER_ON_SURPDN_EN__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_L23_MODE_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_L23_MODE__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT', + 'PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK', + 'RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT', + 'RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK', + 'RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT', + 'RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK', + 'RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK', + 'RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT', + 'RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK', + 'RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT', + 'RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK', + 'RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT', + 'RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK', + 'RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK', + 'RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK', + 'RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT', + 'RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK', + 'RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT', + 'RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK', + 'RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT', + 'RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK', + 'RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT', + 'RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK', + 'RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK', + 'RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK', + 'RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK', + 'RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT', + 'RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK', + 'RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK', + 'RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK', + 'RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT', + 'RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK', + 'RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK', + 'RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT', + 'RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK', + 'RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT', + 'RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK', + 'RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT', + 'RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK', + 'RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_AP_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK', + 'RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT', + 'RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK', + 'RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT', + 'RCC_BIF_STRAP1__STRAP_DLF_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK', + 'RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT', + 'RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK', + 'RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT', + 'RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK', + 'RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT', + 'RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK', + 'RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT', + 'RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK', + 'RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT', + 'RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK', + 'RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT', + 'RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK', + 'RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT', + 'RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK', + 'RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT', + 'RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK', + 'RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT', + 'RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK', + 'RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT', + 'RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK', + 'RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT', + 'RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK', + 'RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT', + 'RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK', + 'RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT', + 'RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK', + 'RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK', + 'RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT', + 'RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK', + 'RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT', + 'RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK', + 'RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT', + 'RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK', + 'RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT', + 'RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK', + 'RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT', + 'RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK', + 'RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT', + 'RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK', + 'RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT', + 'RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK', + 'RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT', + 'RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK', + 'RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK', + 'RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT', + 'RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK', + 'RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT', + 'RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK', + 'RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT', + 'RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK', + 'RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT', + 'RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK', + 'RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT', + 'RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK', + 'RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT', + 'RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK', + 'RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT', + 'RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK', + 'RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT', + 'RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK', + 'RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT', + 'RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK', + 'RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT', + 'RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK', + 'RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT', + 'RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK', + 'RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT', + 'RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK', + 'RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT', + 'RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK', + 'RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT', + 'RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK', + 'RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT', + 'RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK', + 'RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT', + 'RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK', + 'RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT', + 'RCC_BUSNUM_CNTL1__ID_MASK_MASK', + 'RCC_BUSNUM_CNTL1__ID_MASK__SHIFT', + 'RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK', + 'RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT', + 'RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK', + 'RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT', + 'RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK', + 'RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT', + 'RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK', + 'RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT', + 'RCC_BUSNUM_LIST0__ID0_MASK', 'RCC_BUSNUM_LIST0__ID0__SHIFT', + 'RCC_BUSNUM_LIST0__ID1_MASK', 'RCC_BUSNUM_LIST0__ID1__SHIFT', + 'RCC_BUSNUM_LIST0__ID2_MASK', 'RCC_BUSNUM_LIST0__ID2__SHIFT', + 'RCC_BUSNUM_LIST0__ID3_MASK', 'RCC_BUSNUM_LIST0__ID3__SHIFT', + 'RCC_BUSNUM_LIST1__ID4_MASK', 'RCC_BUSNUM_LIST1__ID4__SHIFT', + 'RCC_BUSNUM_LIST1__ID5_MASK', 'RCC_BUSNUM_LIST1__ID5__SHIFT', + 'RCC_BUSNUM_LIST1__ID6_MASK', 'RCC_BUSNUM_LIST1__ID6__SHIFT', + 'RCC_BUSNUM_LIST1__ID7_MASK', 'RCC_BUSNUM_LIST1__ID7__SHIFT', + 'RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK', + 'RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT', + 'RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK', + 'RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT', + 'RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK', + 'RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT', + 'RCC_BUS_CNTL__PMI_BM_DIS_MASK', + 'RCC_BUS_CNTL__PMI_BM_DIS__SHIFT', + 'RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK', + 'RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT', + 'RCC_BUS_CNTL__PMI_IO_DIS_MASK', + 'RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK', + 'RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT', + 'RCC_BUS_CNTL__PMI_IO_DIS__SHIFT', + 'RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK', + 'RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT', + 'RCC_BUS_CNTL__PMI_MEM_DIS_MASK', + 'RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK', + 'RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT', + 'RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT', + 'RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK', + 'RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT', + 'RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK', + 'RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT', + 'RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK', + 'RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT', + 'RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK', + 'RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT', + 'RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK', + 'RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT', + 'RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK', + 'RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT', + 'RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK', + 'RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT', + 'RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK', + 'RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT', + 'RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK', + 'RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT', + 'RCC_CONFIG_APER_SIZE__APER_SIZE_MASK', + 'RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT', + 'RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK', + 'RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT', + 'RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK', + 'RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT', + 'RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK', + 'RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT', + 'RCC_CONFIG_F0_BASE__F0_BASE_MASK', + 'RCC_CONFIG_F0_BASE__F0_BASE__SHIFT', + 'RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK', + 'RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT', + 'RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK', + 'RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT', + 'RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK', + 'RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT', + 'RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK', + 'RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT', + 'RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK', + 'RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT', + 'RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK', + 'RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK', + 'RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK', + 'RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK', + 'RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT', + 'RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK', + 'RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT', + 'RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK', + 'RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT', + 'RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK', + 'RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT', + 'RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK', + 'RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK', + 'RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK', + 'RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT', + 'RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK', + 'RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK', + 'RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK', + 'RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK', + 'RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT', + 'RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK', + 'RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT', + 'RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK', + 'RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT', + 'RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK', + 'RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT', + 'RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK', + 'RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK', + 'RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK', + 'RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT', + 'RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK', + 'RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK', + 'RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK', + 'RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT', + 'RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK', + 'RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT', + 'RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT', + 'RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK', + 'RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT', + 'RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK', + 'RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT', + 'RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK', + 'RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT', + 'RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK', + 'RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK', + 'RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT', + 'RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK', + 'RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK', + 'RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK', + 'RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT', + 'RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK', + 'RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK', + 'RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK', + 'RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK', + 'RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK', + 'RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK', + 'RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK', + 'RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK', + 'RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK', + 'RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK', + 'RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT', + 'RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK', + 'RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT', + 'RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK', + 'RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK', + 'RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK', + 'RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK', + 'RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK', + 'RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK', + 'RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK', + 'RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK', + 'RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK', + 'RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT', + 'RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK', + 'RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT', + 'RCC_GPUIOV_REGION__LFB_REGION_MASK', + 'RCC_GPUIOV_REGION__LFB_REGION__SHIFT', + 'RCC_GPUIOV_REGION__MAX_REGION_MASK', + 'RCC_GPUIOV_REGION__MAX_REGION__SHIFT', + 'RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK', + 'RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT', + 'RCC_HOST_BUSNUM__HOST_ID_MASK', + 'RCC_HOST_BUSNUM__HOST_ID__SHIFT', + 'RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK', + 'RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK', + 'RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK', + 'RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT', + 'RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK', + 'RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT', + 'RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK', + 'RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT', + 'RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK', + 'RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT', + 'RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK', + 'RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT', + 'RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK', + 'RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT', + 'RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK', + 'RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT', + 'RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK', + 'RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT', + 'RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK', + 'RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT', + 'RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK', + 'RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT', + 'RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK', + 'RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT', + 'RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK', + 'RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT', + 'RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK', + 'RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT', + 'RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK', + 'RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT', + 'RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK', + 'RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT', + 'RCC_PEER_REG_RANGE0__END_ADDR_MASK', + 'RCC_PEER_REG_RANGE0__END_ADDR__SHIFT', + 'RCC_PEER_REG_RANGE0__START_ADDR_MASK', + 'RCC_PEER_REG_RANGE0__START_ADDR__SHIFT', + 'RCC_PEER_REG_RANGE1__END_ADDR_MASK', + 'RCC_PEER_REG_RANGE1__END_ADDR__SHIFT', + 'RCC_PEER_REG_RANGE1__START_ADDR_MASK', + 'RCC_PEER_REG_RANGE1__START_ADDR__SHIFT', + 'RCC_RESET_EN__DB_APER_RESET_EN_MASK', + 'RCC_RESET_EN__DB_APER_RESET_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT', + 'RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK', + 'RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT', + 'RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK', + 'RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT', + 'RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK', + 'RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT', + 'RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK', + 'RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT', + 'RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK', + 'RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT', + 'RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK', + 'RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT', + 'RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK', + 'RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT', + 'RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK', + 'RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT', + 'REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK', + 'REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT', + 'REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK', + 'REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT', + 'REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK', + 'REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT', + 'S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK', + 'S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT', + 'S2A_MISC_CNTL__ATM_ARB_MODE_MASK', + 'S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT', + 'S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK', + 'S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT', + 'S2A_MISC_CNTL__HSTR_ARB_MODE_MASK', + 'S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT', + 'S2A_MISC_CNTL__RB_ARB_MODE_MASK', + 'S2A_MISC_CNTL__RB_ARB_MODE__SHIFT', + 'S2A_MISC_CNTL__WRSP_ARB_MODE_MASK', + 'S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT', + 'SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK', + 'SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT', + 'SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK', + 'SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT', + 'SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK', + 'SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT', + 'SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK', + 'SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT', + 'SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK', + 'SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT', + 'SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK', + 'SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT', + 'SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK', + 'SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT', + 'SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK', + 'SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT', + 'SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK', + 'SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT', + 'SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK', + 'SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT', + 'SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK', + 'SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT', + 'SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK', + 'SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT', + 'SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK', + 'SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT', + 'SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK', + 'SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT', + 'SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK', + 'SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT', + 'SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK', + 'SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_CFG_RST_MASK', + 'SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_PRV_RST_MASK', + 'SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST_2__NBIF_S5_CDC_RST_MASK', + 'SELF_SOFT_RST_2__NBIF_S5_CDC_RST__SHIFT', + 'SELF_SOFT_RST_2__NBIF_S5_RST_MASK', + 'SELF_SOFT_RST_2__NBIF_S5_RST__SHIFT', + 'SELF_SOFT_RST_2__STRAP_RST_MASK', + 'SELF_SOFT_RST_2__STRAP_RST__SHIFT', + 'SELF_SOFT_RST__CORE_RST_MASK', 'SELF_SOFT_RST__CORE_RST__SHIFT', + 'SELF_SOFT_RST__CORE_STICKY_RST_MASK', + 'SELF_SOFT_RST__CORE_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_CFG_RST_MASK', + 'SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_PRV_RST_MASK', + 'SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__EP0_CFG_RST_MASK', + 'SELF_SOFT_RST__EP0_CFG_RST__SHIFT', + 'SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__EP0_PRV_RST_MASK', + 'SELF_SOFT_RST__EP0_PRV_RST__SHIFT', + 'SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__RELOAD_STRAP_MASK', + 'SELF_SOFT_RST__RELOAD_STRAP__SHIFT', + 'SELF_SOFT_RST__SWUS_SHADOW_RST_MASK', + 'SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT', + 'SHADOW_BASE_ADDR_1__BAR1_UP_MASK', + 'SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT', + 'SHADOW_BASE_ADDR_2__BAR2_UP_MASK', + 'SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT', + 'SHADOW_COMMAND__IOEN_UP_MASK', 'SHADOW_COMMAND__IOEN_UP__SHIFT', + 'SHADOW_COMMAND__MEMEN_UP_MASK', + 'SHADOW_COMMAND__MEMEN_UP__SHIFT', + 'SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK', + 'SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT', + 'SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK', + 'SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT', + 'SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK', + 'SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT', + 'SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK', + 'SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT', + 'SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK', + 'SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT', + 'SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK', + 'SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT', + 'SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK', + 'SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT', + 'SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK', + 'SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT', + 'SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK', + 'SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT', + 'SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK', + 'SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT', + 'SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK', + 'SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT', + 'SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT', + 'SHUB_LINK_RESET__LINK_P0_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P0_RESET__SHIFT', + 'SHUB_LINK_RESET__LINK_P1_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P1_RESET__SHIFT', + 'SHUB_LINK_RESET__LINK_P2_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P2_RESET__SHIFT', + 'SHUB_LINK_RESET__LINK_P3_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P3_RESET__SHIFT', + 'SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK', + 'SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT', + 'SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK', + 'SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT', + 'SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK', + 'SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT', + 'SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK', + 'SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT', + 'SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK', + 'SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT', + 'SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__SION_AON_RST_MASK', + 'SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT', + 'SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT', + 'SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK', + 'SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT', + 'SLOT_CAP__ATTN_BUTTON_PRESENT_MASK', + 'SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT', + 'SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK', + 'SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT', + 'SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK', + 'SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT', + 'SLOT_CAP__HOTPLUG_CAPABLE_MASK', + 'SLOT_CAP__HOTPLUG_CAPABLE__SHIFT', + 'SLOT_CAP__HOTPLUG_SURPRISE_MASK', + 'SLOT_CAP__HOTPLUG_SURPRISE__SHIFT', + 'SLOT_CAP__MRL_SENSOR_PRESENT_MASK', + 'SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT', + 'SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK', + 'SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT', + 'SLOT_CAP__PHYSICAL_SLOT_NUM_MASK', + 'SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT', + 'SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK', + 'SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT', + 'SLOT_CAP__PWR_INDICATOR_PRESENT_MASK', + 'SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT', + 'SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK', + 'SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT', + 'SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK', + 'SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT', + 'SLOT_CNTL2__RESERVED_MASK', 'SLOT_CNTL2__RESERVED__SHIFT', + 'SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK', + 'SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT', + 'SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK', + 'SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT', + 'SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK', + 'SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT', + 'SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK', + 'SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT', + 'SLOT_CNTL__DL_STATE_CHANGED_EN_MASK', + 'SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT', + 'SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK', + 'SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT', + 'SLOT_CNTL__HOTPLUG_INTR_EN_MASK', + 'SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT', + 'SLOT_CNTL__INBAND_PD_DISABLE_MASK', + 'SLOT_CNTL__INBAND_PD_DISABLE__SHIFT', + 'SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK', + 'SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT', + 'SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK', + 'SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT', + 'SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK', + 'SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT', + 'SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK', + 'SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT', + 'SLOT_CNTL__PWR_INDICATOR_CNTL_MASK', + 'SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT', + 'SLOT_STATUS2__RESERVED_MASK', 'SLOT_STATUS2__RESERVED__SHIFT', + 'SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK', + 'SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT', + 'SLOT_STATUS__COMMAND_COMPLETED_MASK', + 'SLOT_STATUS__COMMAND_COMPLETED__SHIFT', + 'SLOT_STATUS__DL_STATE_CHANGED_MASK', + 'SLOT_STATUS__DL_STATE_CHANGED__SHIFT', + 'SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK', + 'SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT', + 'SLOT_STATUS__MRL_SENSOR_CHANGED_MASK', + 'SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT', + 'SLOT_STATUS__MRL_SENSOR_STATE_MASK', + 'SLOT_STATUS__MRL_SENSOR_STATE__SHIFT', + 'SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK', + 'SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT', + 'SLOT_STATUS__PRESENCE_DETECT_STATE_MASK', + 'SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT', + 'SLOT_STATUS__PWR_FAULT_DETECTED_MASK', + 'SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT', + 'SMNCLK_SEL__S5_SMN_CLK_SEL_MASK', + 'SMNCLK_SEL__S5_SMN_CLK_SEL__SHIFT', + 'SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK', + 'SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT', + 'SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK', + 'SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT', + 'SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK', + 'SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT', + 'SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK', + 'SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT', + 'SMN_MST_CNTL0__SMN_ARB_MODE_MASK', + 'SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__DPC_INT_STATUS_MASK', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__DPC_INT_STATUS__SHIFT', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__PD_INT_STATUS_MASK', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO__PD_INT_STATUS__SHIFT', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK', + 'SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT', + 'SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK', + 'SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT', + 'SMU_PCIE_FENCED2_REG__MP0_PCIE_OVERCLOCKING_EN_MASK', + 'SMU_PCIE_FENCED2_REG__MP0_PCIE_OVERCLOCKING_EN__SHIFT', + 'SUC_DATA__SUC_DATA_MASK', 'SUC_DATA__SUC_DATA__SHIFT', + 'SUC_INDEX__SUC_INDEX_MASK', 'SUC_INDEX__SUC_INDEX__SHIFT', + 'SUM_DATA__SUM_DATA_MASK', 'SUM_DATA__SUM_DATA__SHIFT', + 'SUM_INDEX_HI__SUM_INDEX_HI_MASK', + 'SUM_INDEX_HI__SUM_INDEX_HI__SHIFT', 'SUM_INDEX__SUM_INDEX_MASK', + 'SUM_INDEX__SUM_INDEX__SHIFT', + 'SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT', + 'SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT', + 'SWRST_COMMAND_0__BIF0_CORE_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT', + 'SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT', + 'SWRST_COMMAND_0__BIF0_PHY_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT', + 'SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT', + 'SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET__SHIFT', + 'SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK', + 'SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT0_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT0_COR_RESET_MASK', + 'SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT1_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT2_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT3_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT4_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT5_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT6_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT7_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT', + 'SWRST_COMMAND_0__PORT8_CFG_RESET_MASK', + 'SWRST_COMMAND_0__PORT8_CFG_RESET__SHIFT', + 'SWRST_COMMAND_1__RESETCPM_MASK', + 'SWRST_COMMAND_1__RESETCPM__SHIFT', + 'SWRST_COMMAND_1__RESETHLTR_MASK', + 'SWRST_COMMAND_1__RESETHLTR__SHIFT', + 'SWRST_COMMAND_1__RESETLNCT_MASK', + 'SWRST_COMMAND_1__RESETLNCT__SHIFT', + 'SWRST_COMMAND_1__RESETMNTR_MASK', + 'SWRST_COMMAND_1__RESETMNTR__SHIFT', + 'SWRST_COMMAND_1__RESETPCFG_MASK', + 'SWRST_COMMAND_1__RESETPCFG__SHIFT', + 'SWRST_COMMAND_1__RESETPCS0_MASK', + 'SWRST_COMMAND_1__RESETPCS0__SHIFT', + 'SWRST_COMMAND_1__RESETPCS10_MASK', + 'SWRST_COMMAND_1__RESETPCS10__SHIFT', + 'SWRST_COMMAND_1__RESETPCS11_MASK', + 'SWRST_COMMAND_1__RESETPCS11__SHIFT', + 'SWRST_COMMAND_1__RESETPCS12_MASK', + 'SWRST_COMMAND_1__RESETPCS12__SHIFT', + 'SWRST_COMMAND_1__RESETPCS13_MASK', + 'SWRST_COMMAND_1__RESETPCS13__SHIFT', + 'SWRST_COMMAND_1__RESETPCS14_MASK', + 'SWRST_COMMAND_1__RESETPCS14__SHIFT', + 'SWRST_COMMAND_1__RESETPCS15_MASK', + 'SWRST_COMMAND_1__RESETPCS15__SHIFT', + 'SWRST_COMMAND_1__RESETPCS1_MASK', + 'SWRST_COMMAND_1__RESETPCS1__SHIFT', + 'SWRST_COMMAND_1__RESETPCS2_MASK', + 'SWRST_COMMAND_1__RESETPCS2__SHIFT', + 'SWRST_COMMAND_1__RESETPCS3_MASK', + 'SWRST_COMMAND_1__RESETPCS3__SHIFT', + 'SWRST_COMMAND_1__RESETPCS4_MASK', + 'SWRST_COMMAND_1__RESETPCS4__SHIFT', + 'SWRST_COMMAND_1__RESETPCS5_MASK', + 'SWRST_COMMAND_1__RESETPCS5__SHIFT', + 'SWRST_COMMAND_1__RESETPCS6_MASK', + 'SWRST_COMMAND_1__RESETPCS6__SHIFT', + 'SWRST_COMMAND_1__RESETPCS7_MASK', + 'SWRST_COMMAND_1__RESETPCS7__SHIFT', + 'SWRST_COMMAND_1__RESETPCS8_MASK', + 'SWRST_COMMAND_1__RESETPCS8__SHIFT', + 'SWRST_COMMAND_1__RESETPCS9_MASK', + 'SWRST_COMMAND_1__RESETPCS9__SHIFT', + 'SWRST_COMMAND_1__RESETPHY0_MASK', + 'SWRST_COMMAND_1__RESETPHY0__SHIFT', + 'SWRST_COMMAND_1__SWITCHCLK_MASK', + 'SWRST_COMMAND_1__SWITCHCLK__SHIFT', + 'SWRST_COMMAND_1__TOGGLESTRAP_MASK', + 'SWRST_COMMAND_1__TOGGLESTRAP__SHIFT', + 'SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK', + 'SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT', + 'SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK', + 'SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT', + 'SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK', + 'SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT', + 'SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK', + 'SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT', + 'SWRST_COMMAND_STATUS__PERST_ASRT_MASK', + 'SWRST_COMMAND_STATUS__PERST_ASRT__SHIFT', + 'SWRST_COMMAND_STATUS__RECONFIGURE_MASK', + 'SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT', + 'SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK', + 'SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT', + 'SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK', + 'SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT', + 'SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK', + 'SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT', + 'SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK', + 'SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT', + 'SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK', + 'SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK', + 'SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT', + 'SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT', + 'SWRST_COMMAND_STATUS__WAIT_STATE_MASK', + 'SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT', + 'SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK', + 'SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT', + 'SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT0_COR_RCEN_MASK', + 'SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_0__PORT8_CFG_RCEN_MASK', + 'SWRST_CONTROL_0__PORT8_CFG_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET0_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET10_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET11_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET12_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET13_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET14_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET15_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET1_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET2_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET3_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET4_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET5_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET6_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET7_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET8_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT', + 'SWRST_CONTROL_1__PCSRESET9_RCEN_MASK', + 'SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT', + 'SWRST_CONTROL_1__RESETCPM_RCEN_MASK', + 'SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT', + 'SWRST_CONTROL_1__RESETHLTR_RCEN_MASK', + 'SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT', + 'SWRST_CONTROL_1__RESETLNCT_RCEN_MASK', + 'SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT', + 'SWRST_CONTROL_1__RESETMNTR_RCEN_MASK', + 'SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT', + 'SWRST_CONTROL_1__RESETPCFG_RCEN_MASK', + 'SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT', + 'SWRST_CONTROL_1__RESETPHY0_RCEN_MASK', + 'SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT', + 'SWRST_CONTROL_1__STRAPVLD_RCEN_MASK', + 'SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT', + 'SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK', + 'SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK', + 'SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT', + 'SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT0_COR_ATEN_MASK', + 'SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_2__PORT8_CFG_ATEN_MASK', + 'SWRST_CONTROL_2__PORT8_CFG_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET0_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET10_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET11_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET12_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET13_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET14_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET15_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET1_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET2_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET3_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET4_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET5_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET6_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET7_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET8_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT', + 'SWRST_CONTROL_3__PCSRESET9_ATEN_MASK', + 'SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT', + 'SWRST_CONTROL_3__RESETCPM_ATEN_MASK', + 'SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT', + 'SWRST_CONTROL_3__RESETHLTR_ATEN_MASK', + 'SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT', + 'SWRST_CONTROL_3__RESETLNCT_ATEN_MASK', + 'SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT', + 'SWRST_CONTROL_3__RESETMNTR_ATEN_MASK', + 'SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT', + 'SWRST_CONTROL_3__RESETPCFG_ATEN_MASK', + 'SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT', + 'SWRST_CONTROL_3__RESETPHY0_ATEN_MASK', + 'SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT', + 'SWRST_CONTROL_3__STRAPVLD_ATEN_MASK', + 'SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT', + 'SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK', + 'SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK', + 'SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT', + 'SWRST_CONTROL_4__PORT0_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT0_COR_WREN_MASK', + 'SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT1_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT2_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT3_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT4_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT5_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT6_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT7_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT', + 'SWRST_CONTROL_4__PORT8_CFG_WREN_MASK', + 'SWRST_CONTROL_4__PORT8_CFG_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET0_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET10_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET11_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET12_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET13_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET14_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET15_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET1_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET2_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET3_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET4_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET5_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET6_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET7_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET8_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT', + 'SWRST_CONTROL_5__PCSRESET9_WREN_MASK', + 'SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT', + 'SWRST_CONTROL_5__WRRESETCPM_EN_MASK', + 'SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT', + 'SWRST_CONTROL_5__WRRESETHLTR_EN_MASK', + 'SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT', + 'SWRST_CONTROL_5__WRRESETLNCT_EN_MASK', + 'SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT', + 'SWRST_CONTROL_5__WRRESETMNTR_EN_MASK', + 'SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT', + 'SWRST_CONTROL_5__WRRESETPCFG_EN_MASK', + 'SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT', + 'SWRST_CONTROL_5__WRRESETPHY0_EN_MASK', + 'SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT', + 'SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK', + 'SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT', + 'SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK', + 'SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_A_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_B_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_C_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_D_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_E_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_F_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_G_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_H_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_I_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_J_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT', + 'SWRST_CONTROL_6__HOLD_TRAINING_K_MASK', + 'SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT', + 'SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK', + 'SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT', + 'SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK', + 'SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT', + 'SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK', + 'SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT', + 'SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK', + 'SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT', + 'SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK', + 'SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT', + 'SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK', + 'SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT', + 'SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK', + 'SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT', + 'SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK', + 'SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT', + 'SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK', + 'SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT', + 'SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK', + 'SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT', + 'SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK', + 'SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT', + 'SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK', + 'SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT', + 'SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK', + 'SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT', + 'SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK', + 'SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT', + 'SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK', + 'SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT', + 'SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK', + 'SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT', + 'SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK', + 'SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT', + 'SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS_MASK', + 'SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS__SHIFT', + 'SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK', + 'SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT', + 'VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK', + 'VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK', + 'VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF0_MASK', 'VF_FB_EN__VF_FB_EN_VF0__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF10_MASK', 'VF_FB_EN__VF_FB_EN_VF10__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF11_MASK', 'VF_FB_EN__VF_FB_EN_VF11__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF12_MASK', 'VF_FB_EN__VF_FB_EN_VF12__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF13_MASK', 'VF_FB_EN__VF_FB_EN_VF13__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF14_MASK', 'VF_FB_EN__VF_FB_EN_VF14__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF15_MASK', 'VF_FB_EN__VF_FB_EN_VF15__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF16_MASK', 'VF_FB_EN__VF_FB_EN_VF16__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF17_MASK', 'VF_FB_EN__VF_FB_EN_VF17__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF18_MASK', 'VF_FB_EN__VF_FB_EN_VF18__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF19_MASK', 'VF_FB_EN__VF_FB_EN_VF19__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF1_MASK', 'VF_FB_EN__VF_FB_EN_VF1__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF20_MASK', 'VF_FB_EN__VF_FB_EN_VF20__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF21_MASK', 'VF_FB_EN__VF_FB_EN_VF21__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF22_MASK', 'VF_FB_EN__VF_FB_EN_VF22__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF23_MASK', 'VF_FB_EN__VF_FB_EN_VF23__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF24_MASK', 'VF_FB_EN__VF_FB_EN_VF24__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF25_MASK', 'VF_FB_EN__VF_FB_EN_VF25__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF26_MASK', 'VF_FB_EN__VF_FB_EN_VF26__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF27_MASK', 'VF_FB_EN__VF_FB_EN_VF27__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF28_MASK', 'VF_FB_EN__VF_FB_EN_VF28__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF29_MASK', 'VF_FB_EN__VF_FB_EN_VF29__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF2_MASK', 'VF_FB_EN__VF_FB_EN_VF2__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF30_MASK', 'VF_FB_EN__VF_FB_EN_VF30__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF3_MASK', 'VF_FB_EN__VF_FB_EN_VF3__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF4_MASK', 'VF_FB_EN__VF_FB_EN_VF4__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF5_MASK', 'VF_FB_EN__VF_FB_EN_VF5__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF6_MASK', 'VF_FB_EN__VF_FB_EN_VF6__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF7_MASK', 'VF_FB_EN__VF_FB_EN_VF7__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF8_MASK', 'VF_FB_EN__VF_FB_EN_VF8__SHIFT', + 'VF_FB_EN__VF_FB_EN_VF9_MASK', 'VF_FB_EN__VF_FB_EN_VF9__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF0_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF10_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF11_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF12_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF13_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF14_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF15_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF16_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF17_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF18_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF19_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF1_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF20_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF21_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF22_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF23_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF24_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF25_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF26_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF27_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF28_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF29_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF2_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF30_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF3_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF4_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF5_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF6_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF7_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF8_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT', + 'VF_FB_STATUS__VF_FB_STATUS_VF9_MASK', + 'VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF0_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF10_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF11_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF12_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF13_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF14_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF15_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF16_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF17_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF18_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF19_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF1_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF20_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF21_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF22_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF23_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF24_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF25_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF26_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF27_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF28_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF29_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF2_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF30_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF3_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF4_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF5_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF6_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF7_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF8_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT', + 'VF_REGWR_EN__VF_REGWR_EN_VF9_MASK', + 'VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK', + 'VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT', + '_nbio_4_3_0_OFFSET_HEADER', '_nbio_4_3_0_SH_MASK_HEADER', + 'cfgATDMA_MISC_CNTL', 'cfgBACO_CNTL', 'cfgBIF_BACO_EXIT_TIME0', + 'cfgBIF_BACO_EXIT_TIMER1', 'cfgBIF_BACO_EXIT_TIMER2', + 'cfgBIF_BACO_EXIT_TIMER3', 'cfgBIF_BACO_EXIT_TIMER4', + 'cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG', + 'cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS', + 'cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING', + 'cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA', + 'cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX', + 'cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI', + 'cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_BX_PF0_MM_DATA', 'cfgBIF_BX_PF0_MM_INDEX', + 'cfgBIF_BX_PF0_MM_INDEX_HI', 'cfgBIF_BX_PF1_MM_DATA', + 'cfgBIF_BX_PF1_MM_INDEX', 'cfgBIF_BX_PF1_MM_INDEX_HI', + 'cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG', 'cfgBIF_BX_PF_BIF_BME_STATUS', + 'cfgBIF_BX_PF_BIF_TRANS_PENDING', 'cfgBIF_BX_PF_BIF_VMHV_MAILBOX', + 'cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL', + 'cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE', + 'cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ', + 'cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'cfgBIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL', + 'cfgBIF_BX_PF_MAILBOX_CONTROL', 'cfgBIF_BX_PF_MAILBOX_INT_CNTL', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2', + 'cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3', + 'cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS', + 'cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT', + 'cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT', + 'cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF1_0_BIST', + 'cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF1_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF1_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF1_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF1_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF1_1_BIST', + 'cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF1_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF1_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF1_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF1_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF2_0_BIST', + 'cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF2_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD', + 'cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF2_0_FLADJ', 'cfgBIF_CFG_DEV0_EPF2_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF2_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF2_0_SBRN', 'cfgBIF_CFG_DEV0_EPF2_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF2_1_BIST', + 'cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF2_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD', + 'cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF2_1_FLADJ', 'cfgBIF_CFG_DEV0_EPF2_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF2_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF2_1_SBRN', 'cfgBIF_CFG_DEV0_EPF2_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF3_0_BIST', + 'cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF3_0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD', + 'cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF3_0_FLADJ', 'cfgBIF_CFG_DEV0_EPF3_0_HEADER', + 'cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF3_0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF3_0_SBRN', 'cfgBIF_CFG_DEV0_EPF3_0_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF3_1_BIST', + 'cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF3_1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD', + 'cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF3_1_FLADJ', 'cfgBIF_CFG_DEV0_EPF3_1_HEADER', + 'cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF3_1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF3_1_SBRN', 'cfgBIF_CFG_DEV0_EPF3_1_STATUS', + 'cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_RC0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_RC0_BASE_CLASS', 'cfgBIF_CFG_DEV0_RC0_BIST', + 'cfgBIF_CFG_DEV0_RC0_CACHE_LINE', 'cfgBIF_CFG_DEV0_RC0_CAP_PTR', + 'cfgBIF_CFG_DEV0_RC0_COMMAND', + 'cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP', + 'cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_RC0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_RC0_HEADER', + 'cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI', + 'cfgBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LATENCY', 'cfgBIF_CFG_DEV0_RC0_LINK_CAP', + 'cfgBIF_CFG_DEV0_RC0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_RC0_LINK_CAP_16GT', + 'cfgBIF_CFG_DEV0_RC0_LINK_CAP_32GT', + 'cfgBIF_CFG_DEV0_RC0_LINK_CNTL', 'cfgBIF_CFG_DEV0_RC0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_RC0_LINK_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC0_LINK_CNTL_32GT', + 'cfgBIF_CFG_DEV0_RC0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_RC0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_RC0_LINK_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC0_LINK_STATUS_32GT', + 'cfgBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP', + 'cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS', + 'cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1', + 'cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2', + 'cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS', + 'cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_RC0_PMI_CAP', 'cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER', + 'cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER', + 'cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_RC0_REVISION_ID', + 'cfgBIF_CFG_DEV0_RC0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS', + 'cfgBIF_CFG_DEV0_RC0_SLOT_CAP', 'cfgBIF_CFG_DEV0_RC0_SLOT_CAP2', + 'cfgBIF_CFG_DEV0_RC0_SLOT_CNTL', 'cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2', + 'cfgBIF_CFG_DEV0_RC0_SLOT_STATUS', + 'cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2', + 'cfgBIF_CFG_DEV0_RC0_SSID_CAP', + 'cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST', 'cfgBIF_CFG_DEV0_RC0_STATUS', + 'cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY', + 'cfgBIF_CFG_DEV0_RC0_SUB_CLASS', 'cfgBIF_CFG_DEV0_RC0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_RC1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_RC1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_RC1_BASE_CLASS', 'cfgBIF_CFG_DEV0_RC1_BIST', + 'cfgBIF_CFG_DEV0_RC1_CACHE_LINE', 'cfgBIF_CFG_DEV0_RC1_CAP_PTR', + 'cfgBIF_CFG_DEV0_RC1_COMMAND', + 'cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP', + 'cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_RC1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_RC1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_RC1_HEADER', + 'cfgBIF_CFG_DEV0_RC1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_RC1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI', + 'cfgBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LATENCY', 'cfgBIF_CFG_DEV0_RC1_LINK_CAP', + 'cfgBIF_CFG_DEV0_RC1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_RC1_LINK_CAP_16GT', + 'cfgBIF_CFG_DEV0_RC1_LINK_CAP_32GT', + 'cfgBIF_CFG_DEV0_RC1_LINK_CNTL', 'cfgBIF_CFG_DEV0_RC1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_RC1_LINK_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC1_LINK_CNTL_32GT', + 'cfgBIF_CFG_DEV0_RC1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_RC1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_RC1_LINK_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC1_LINK_STATUS_32GT', + 'cfgBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP', + 'cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS', + 'cfgBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_RC1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_RC1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1', + 'cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2', + 'cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS', + 'cfgBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_RC1_PMI_CAP', 'cfgBIF_CFG_DEV0_RC1_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC1_PREF_BASE_UPPER', + 'cfgBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER', + 'cfgBIF_CFG_DEV0_RC1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_RC1_REVISION_ID', + 'cfgBIF_CFG_DEV0_RC1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC1_SECONDARY_STATUS', + 'cfgBIF_CFG_DEV0_RC1_SLOT_CAP', 'cfgBIF_CFG_DEV0_RC1_SLOT_CAP2', + 'cfgBIF_CFG_DEV0_RC1_SLOT_CNTL', 'cfgBIF_CFG_DEV0_RC1_SLOT_CNTL2', + 'cfgBIF_CFG_DEV0_RC1_SLOT_STATUS', + 'cfgBIF_CFG_DEV0_RC1_SLOT_STATUS2', + 'cfgBIF_CFG_DEV0_RC1_SSID_CAP', + 'cfgBIF_CFG_DEV0_RC1_SSID_CAP_LIST', 'cfgBIF_CFG_DEV0_RC1_STATUS', + 'cfgBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY', + 'cfgBIF_CFG_DEV0_RC1_SUB_CLASS', 'cfgBIF_CFG_DEV0_RC1_VENDOR_ID', + 'cfgBIF_CLKREQB_PAD_CNTL', 'cfgBIF_DOORBELL_CNTL', + 'cfgBIF_DOORBELL_INT_CNTL', 'cfgBIF_FB_EN', + 'cfgBIF_FEATURES_CONTROL_MISC', 'cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE', + 'cfgBIF_INTR_CNTL', 'cfgBIF_MM_INDACCESS_CNTL', + 'cfgBIF_MP1_INTR_CTRL', 'cfgBIF_MST_TRANS_PENDING_VF', + 'cfgBIF_PERSTB_PAD_CNTL', 'cfgBIF_PWRBRK_PAD_CNTL', + 'cfgBIF_PX_EN_PAD_CNTL', 'cfgBIF_RB_BASE', 'cfgBIF_RB_CNTL', + 'cfgBIF_RB_RPTR', 'cfgBIF_RB_WPTR', 'cfgBIF_RB_WPTR_ADDR_HI', + 'cfgBIF_RB_WPTR_ADDR_LO', 'cfgBIF_REFPADKIN_PAD_CNTL', + 'cfgBIF_RLC_INTR_CNTL', 'cfgBIF_SCRATCH0', 'cfgBIF_SCRATCH1', + 'cfgBIF_SLV_TRANS_PENDING_VF', 'cfgBIF_UVD_INTR_CNTL', + 'cfgBIF_VAUX_PRESENT_PAD_CNTL', 'cfgBIF_VCE_INTR_CNTL', + 'cfgBIF_WAKEB_PAD_CNTL', 'cfgBIOS_SCRATCH_0', 'cfgBIOS_SCRATCH_1', + 'cfgBIOS_SCRATCH_10', 'cfgBIOS_SCRATCH_11', 'cfgBIOS_SCRATCH_12', + 'cfgBIOS_SCRATCH_13', 'cfgBIOS_SCRATCH_14', 'cfgBIOS_SCRATCH_15', + 'cfgBIOS_SCRATCH_2', 'cfgBIOS_SCRATCH_3', 'cfgBIOS_SCRATCH_4', + 'cfgBIOS_SCRATCH_5', 'cfgBIOS_SCRATCH_6', 'cfgBIOS_SCRATCH_7', + 'cfgBIOS_SCRATCH_8', 'cfgBIOS_SCRATCH_9', 'cfgBUS_CNTL', + 'cfgBX_RESET_CNTL', 'cfgBX_RESET_EN', 'cfgCC_BIF_BX_PINSTRAP0', + 'cfgCC_BIF_BX_STRAP0', 'cfgCLKREQB_PAD_CNTL', + 'cfgDN_PCIE_BUS_CNTL', 'cfgDN_PCIE_CFG_CNTL', 'cfgDN_PCIE_CNTL', + 'cfgDN_PCIE_CONFIG_CNTL', 'cfgDN_PCIE_RESERVED', + 'cfgDN_PCIE_RX_CNTL2', 'cfgDN_PCIE_SCRATCH', + 'cfgDN_PCIE_STRAP_F0', 'cfgDN_PCIE_STRAP_MISC', + 'cfgDN_PCIE_STRAP_MISC2', 'cfgDRIVER_SCRATCH_0', + 'cfgDRIVER_SCRATCH_1', 'cfgDRIVER_SCRATCH_10', + 'cfgDRIVER_SCRATCH_11', 'cfgDRIVER_SCRATCH_12', + 'cfgDRIVER_SCRATCH_13', 'cfgDRIVER_SCRATCH_14', + 'cfgDRIVER_SCRATCH_15', 'cfgDRIVER_SCRATCH_2', + 'cfgDRIVER_SCRATCH_3', 'cfgDRIVER_SCRATCH_4', + 'cfgDRIVER_SCRATCH_5', 'cfgDRIVER_SCRATCH_6', + 'cfgDRIVER_SCRATCH_7', 'cfgDRIVER_SCRATCH_8', + 'cfgDRIVER_SCRATCH_9', 'cfgEP_PCIEP_RESERVED', + 'cfgEP_PCIE_BUS_CNTL', 'cfgEP_PCIE_CFG_CNTL', 'cfgEP_PCIE_CNTL', + 'cfgEP_PCIE_ERR_CNTL', 'cfgEP_PCIE_F0_DPA_CAP', + 'cfgEP_PCIE_F0_DPA_CNTL', 'cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR', + 'cfgEP_PCIE_INT_CNTL', 'cfgEP_PCIE_INT_STATUS', + 'cfgEP_PCIE_LC_SPEED_CNTL', 'cfgEP_PCIE_PME_CONTROL', + 'cfgEP_PCIE_RX_CNTL', 'cfgEP_PCIE_RX_CNTL2', 'cfgEP_PCIE_SCRATCH', + 'cfgEP_PCIE_STRAP_MISC', 'cfgEP_PCIE_STRAP_MISC2', + 'cfgEP_PCIE_TX_CNTL', 'cfgEP_PCIE_TX_LTR_CNTL', + 'cfgEP_PCIE_TX_REQUESTER_ID', 'cfgFW_SCRATCH_0', + 'cfgFW_SCRATCH_1', 'cfgFW_SCRATCH_10', 'cfgFW_SCRATCH_11', + 'cfgFW_SCRATCH_12', 'cfgFW_SCRATCH_13', 'cfgFW_SCRATCH_14', + 'cfgFW_SCRATCH_15', 'cfgFW_SCRATCH_2', 'cfgFW_SCRATCH_3', + 'cfgFW_SCRATCH_4', 'cfgFW_SCRATCH_5', 'cfgFW_SCRATCH_6', + 'cfgFW_SCRATCH_7', 'cfgFW_SCRATCH_8', 'cfgFW_SCRATCH_9', + 'cfgGFX_MMIOREG_CAM_ADDR0', 'cfgGFX_MMIOREG_CAM_ADDR1', + 'cfgGFX_MMIOREG_CAM_ADDR2', 'cfgGFX_MMIOREG_CAM_ADDR3', + 'cfgGFX_MMIOREG_CAM_ADDR4', 'cfgGFX_MMIOREG_CAM_ADDR5', + 'cfgGFX_MMIOREG_CAM_ADDR6', 'cfgGFX_MMIOREG_CAM_ADDR7', + 'cfgGFX_MMIOREG_CAM_CNTL', 'cfgGFX_MMIOREG_CAM_ONE_CPL', + 'cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR0', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR1', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR2', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR3', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR4', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR5', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR6', + 'cfgGFX_MMIOREG_CAM_REMAP_ADDR7', 'cfgGFX_MMIOREG_CAM_ZERO_CPL', + 'cfgHDP_ATOMIC_CONTROL_MISC', 'cfgINTERRUPT_CNTL', + 'cfgINTERRUPT_CNTL2', 'cfgLTR_MSG_INFO_FROM_EP', + 'cfgMAILBOX_INDEX', 'cfgMEM_TYPE_CNTL', 'cfgMM_CFGREGS_CNTL', + 'cfgNBIF_GFX_ADDR_LUT_0', 'cfgNBIF_GFX_ADDR_LUT_1', + 'cfgNBIF_GFX_ADDR_LUT_10', 'cfgNBIF_GFX_ADDR_LUT_11', + 'cfgNBIF_GFX_ADDR_LUT_12', 'cfgNBIF_GFX_ADDR_LUT_13', + 'cfgNBIF_GFX_ADDR_LUT_14', 'cfgNBIF_GFX_ADDR_LUT_15', + 'cfgNBIF_GFX_ADDR_LUT_2', 'cfgNBIF_GFX_ADDR_LUT_3', + 'cfgNBIF_GFX_ADDR_LUT_4', 'cfgNBIF_GFX_ADDR_LUT_5', + 'cfgNBIF_GFX_ADDR_LUT_6', 'cfgNBIF_GFX_ADDR_LUT_7', + 'cfgNBIF_GFX_ADDR_LUT_8', 'cfgNBIF_GFX_ADDR_LUT_9', + 'cfgNBIF_GFX_ADDR_LUT_CNTL', 'cfgNGDC_MGCG_CTRL', + 'cfgNGDC_PGMST_CTRL', 'cfgNGDC_PGSLV_CTRL', + 'cfgNGDC_PG_MISC_CTRL', 'cfgNGDC_RESERVED_0', + 'cfgNGDC_RESERVED_1', 'cfgPCIEP_STRAP_MISC', 'cfgPCIE_DATA', + 'cfgPCIE_DATA2', 'cfgPCIE_ERR_CNTL', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7', 'cfgPCIE_INDEX', + 'cfgPCIE_INDEX2', 'cfgPCIE_INDEX2_HI', 'cfgPCIE_INDEX_HI', + 'cfgPCIE_LC_CNTL2', 'cfgPCIE_LC_SPEED_CNTL', 'cfgPCIE_RX_CNTL', + 'cfgPSWUSCFG0_0_ADAPTER_ID_W', 'cfgPSWUSCFG0_0_BASE_CLASS', + 'cfgPSWUSCFG0_0_BIST', 'cfgPSWUSCFG0_0_CACHE_LINE', + 'cfgPSWUSCFG0_0_CAP_PTR', 'cfgPSWUSCFG0_0_COMMAND', + 'cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP', + 'cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS', + 'cfgPSWUSCFG0_0_DEVICE_CAP', 'cfgPSWUSCFG0_0_DEVICE_CAP2', + 'cfgPSWUSCFG0_0_DEVICE_CNTL', 'cfgPSWUSCFG0_0_DEVICE_CNTL2', + 'cfgPSWUSCFG0_0_DEVICE_ID', 'cfgPSWUSCFG0_0_DEVICE_STATUS', + 'cfgPSWUSCFG0_0_DEVICE_STATUS2', 'cfgPSWUSCFG0_0_HEADER', + 'cfgPSWUSCFG0_0_INTERRUPT_LINE', 'cfgPSWUSCFG0_0_INTERRUPT_PIN', + 'cfgPSWUSCFG0_0_IO_BASE_LIMIT', 'cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI', + 'cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_0_LATENCY', 'cfgPSWUSCFG0_0_LINK_CAP', + 'cfgPSWUSCFG0_0_LINK_CAP2', 'cfgPSWUSCFG0_0_LINK_CAP_16GT', + 'cfgPSWUSCFG0_0_LINK_CAP_32GT', 'cfgPSWUSCFG0_0_LINK_CNTL', + 'cfgPSWUSCFG0_0_LINK_CNTL2', 'cfgPSWUSCFG0_0_LINK_CNTL_16GT', + 'cfgPSWUSCFG0_0_LINK_CNTL_32GT', 'cfgPSWUSCFG0_0_LINK_STATUS', + 'cfgPSWUSCFG0_0_LINK_STATUS2', 'cfgPSWUSCFG0_0_LINK_STATUS_16GT', + 'cfgPSWUSCFG0_0_LINK_STATUS_32GT', + 'cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgPSWUSCFG0_0_MARGINING_PORT_CAP', + 'cfgPSWUSCFG0_0_MARGINING_PORT_STATUS', + 'cfgPSWUSCFG0_0_MEM_BASE_LIMIT', 'cfgPSWUSCFG0_0_MSI_CAP_LIST', + 'cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI', + 'cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO', 'cfgPSWUSCFG0_0_MSI_MSG_CNTL', + 'cfgPSWUSCFG0_0_MSI_MSG_DATA', 'cfgPSWUSCFG0_0_MSI_MSG_DATA_64', + 'cfgPSWUSCFG0_0_PCIE_ACS_CAP', 'cfgPSWUSCFG0_0_PCIE_ACS_CNTL', + 'cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_ARI_CAP', 'cfgPSWUSCFG0_0_PCIE_ARI_CNTL', + 'cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST', 'cfgPSWUSCFG0_0_PCIE_CAP', + 'cfgPSWUSCFG0_0_PCIE_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK', + 'cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS', + 'cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_HDR_LOG0', 'cfgPSWUSCFG0_0_PCIE_HDR_LOG1', + 'cfgPSWUSCFG0_0_PCIE_HDR_LOG2', 'cfgPSWUSCFG0_0_PCIE_HDR_LOG3', + 'cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS', + 'cfgPSWUSCFG0_0_PCIE_LINK_CNTL3', 'cfgPSWUSCFG0_0_PCIE_LTR_CAP', + 'cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_MC_ADDR0', 'cfgPSWUSCFG0_0_PCIE_MC_ADDR1', + 'cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0', + 'cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1', + 'cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'cfgPSWUSCFG0_0_PCIE_MC_CAP', 'cfgPSWUSCFG0_0_PCIE_MC_CNTL', + 'cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_MC_RCV0', 'cfgPSWUSCFG0_0_PCIE_MC_RCV1', + 'cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1', + 'cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2', + 'cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL', + 'cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS', + 'cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0', + 'cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1', + 'cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2', + 'cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3', + 'cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK', + 'cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS', + 'cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP', + 'cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL', + 'cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS', + 'cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP', + 'cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL', + 'cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS', + 'cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1', + 'cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2', + 'cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgPSWUSCFG0_0_PMI_CAP', 'cfgPSWUSCFG0_0_PMI_CAP_LIST', + 'cfgPSWUSCFG0_0_PMI_STATUS_CNTL', + 'cfgPSWUSCFG0_0_PREF_BASE_LIMIT', + 'cfgPSWUSCFG0_0_PREF_BASE_UPPER', + 'cfgPSWUSCFG0_0_PREF_LIMIT_UPPER', + 'cfgPSWUSCFG0_0_PROG_INTERFACE', 'cfgPSWUSCFG0_0_REVISION_ID', + 'cfgPSWUSCFG0_0_ROM_BASE_ADDR', + 'cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgPSWUSCFG0_0_SECONDARY_STATUS', 'cfgPSWUSCFG0_0_SSID_CAP', + 'cfgPSWUSCFG0_0_SSID_CAP_LIST', 'cfgPSWUSCFG0_0_STATUS', + 'cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY', + 'cfgPSWUSCFG0_0_SUB_CLASS', 'cfgPSWUSCFG0_0_VENDOR_CAP_LIST', + 'cfgPSWUSCFG0_0_VENDOR_ID', 'cfgPSWUSCFG0_1_ADAPTER_ID_W', + 'cfgPSWUSCFG0_1_BASE_CLASS', 'cfgPSWUSCFG0_1_BIST', + 'cfgPSWUSCFG0_1_CACHE_LINE', 'cfgPSWUSCFG0_1_CAP_PTR', + 'cfgPSWUSCFG0_1_COMMAND', 'cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP', + 'cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS', + 'cfgPSWUSCFG0_1_DEVICE_CAP', 'cfgPSWUSCFG0_1_DEVICE_CAP2', + 'cfgPSWUSCFG0_1_DEVICE_CNTL', 'cfgPSWUSCFG0_1_DEVICE_CNTL2', + 'cfgPSWUSCFG0_1_DEVICE_ID', 'cfgPSWUSCFG0_1_DEVICE_STATUS', + 'cfgPSWUSCFG0_1_DEVICE_STATUS2', 'cfgPSWUSCFG0_1_HEADER', + 'cfgPSWUSCFG0_1_INTERRUPT_LINE', 'cfgPSWUSCFG0_1_INTERRUPT_PIN', + 'cfgPSWUSCFG0_1_IO_BASE_LIMIT', 'cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI', + 'cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL', + 'cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS', + 'cfgPSWUSCFG0_1_LATENCY', 'cfgPSWUSCFG0_1_LINK_CAP', + 'cfgPSWUSCFG0_1_LINK_CAP2', 'cfgPSWUSCFG0_1_LINK_CAP_16GT', + 'cfgPSWUSCFG0_1_LINK_CAP_32GT', 'cfgPSWUSCFG0_1_LINK_CNTL', + 'cfgPSWUSCFG0_1_LINK_CNTL2', 'cfgPSWUSCFG0_1_LINK_CNTL_16GT', + 'cfgPSWUSCFG0_1_LINK_CNTL_32GT', 'cfgPSWUSCFG0_1_LINK_STATUS', + 'cfgPSWUSCFG0_1_LINK_STATUS2', 'cfgPSWUSCFG0_1_LINK_STATUS_16GT', + 'cfgPSWUSCFG0_1_LINK_STATUS_32GT', + 'cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgPSWUSCFG0_1_MARGINING_PORT_CAP', + 'cfgPSWUSCFG0_1_MARGINING_PORT_STATUS', + 'cfgPSWUSCFG0_1_MEM_BASE_LIMIT', 'cfgPSWUSCFG0_1_MSI_CAP_LIST', + 'cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI', + 'cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO', 'cfgPSWUSCFG0_1_MSI_MSG_CNTL', + 'cfgPSWUSCFG0_1_MSI_MSG_DATA', 'cfgPSWUSCFG0_1_MSI_MSG_DATA_64', + 'cfgPSWUSCFG0_1_PCIE_ACS_CAP', 'cfgPSWUSCFG0_1_PCIE_ACS_CNTL', + 'cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_ARI_CAP', 'cfgPSWUSCFG0_1_PCIE_ARI_CNTL', + 'cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST', 'cfgPSWUSCFG0_1_PCIE_CAP', + 'cfgPSWUSCFG0_1_PCIE_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK', + 'cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS', + 'cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_HDR_LOG0', 'cfgPSWUSCFG0_1_PCIE_HDR_LOG1', + 'cfgPSWUSCFG0_1_PCIE_HDR_LOG2', 'cfgPSWUSCFG0_1_PCIE_HDR_LOG3', + 'cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS', + 'cfgPSWUSCFG0_1_PCIE_LINK_CNTL3', 'cfgPSWUSCFG0_1_PCIE_LTR_CAP', + 'cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_MC_ADDR0', 'cfgPSWUSCFG0_1_PCIE_MC_ADDR1', + 'cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0', + 'cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1', + 'cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'cfgPSWUSCFG0_1_PCIE_MC_CAP', 'cfgPSWUSCFG0_1_PCIE_MC_CNTL', + 'cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_MC_RCV0', 'cfgPSWUSCFG0_1_PCIE_MC_RCV1', + 'cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1', + 'cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2', + 'cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL', + 'cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS', + 'cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0', + 'cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1', + 'cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2', + 'cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3', + 'cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK', + 'cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS', + 'cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP', + 'cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL', + 'cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS', + 'cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP', + 'cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL', + 'cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS', + 'cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1', + 'cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2', + 'cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgPSWUSCFG0_1_PMI_CAP', 'cfgPSWUSCFG0_1_PMI_CAP_LIST', + 'cfgPSWUSCFG0_1_PMI_STATUS_CNTL', + 'cfgPSWUSCFG0_1_PREF_BASE_LIMIT', + 'cfgPSWUSCFG0_1_PREF_BASE_UPPER', + 'cfgPSWUSCFG0_1_PREF_LIMIT_UPPER', + 'cfgPSWUSCFG0_1_PROG_INTERFACE', 'cfgPSWUSCFG0_1_REVISION_ID', + 'cfgPSWUSCFG0_1_ROM_BASE_ADDR', + 'cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgPSWUSCFG0_1_SECONDARY_STATUS', 'cfgPSWUSCFG0_1_SSID_CAP', + 'cfgPSWUSCFG0_1_SSID_CAP_LIST', 'cfgPSWUSCFG0_1_STATUS', + 'cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY', + 'cfgPSWUSCFG0_1_SUB_CLASS', 'cfgPSWUSCFG0_1_VENDOR_CAP_LIST', + 'cfgPSWUSCFG0_1_VENDOR_ID', 'cfgRCC_BACO_CNTL_MISC', + 'cfgRCC_BIF_STRAP0', 'cfgRCC_BIF_STRAP1', 'cfgRCC_BIF_STRAP2', + 'cfgRCC_BIF_STRAP3', 'cfgRCC_BIF_STRAP4', 'cfgRCC_BIF_STRAP5', + 'cfgRCC_BIF_STRAP6', 'cfgRCC_BUSNUM_CNTL1', 'cfgRCC_BUSNUM_CNTL2', + 'cfgRCC_BUSNUM_LIST0', 'cfgRCC_BUSNUM_LIST1', 'cfgRCC_BUS_CNTL', + 'cfgRCC_CAPTURE_HOST_BUSNUM', 'cfgRCC_CMN_LINK_CNTL', + 'cfgRCC_CONFIG_APER_SIZE', 'cfgRCC_CONFIG_CNTL', + 'cfgRCC_CONFIG_F0_BASE', 'cfgRCC_CONFIG_REG_APER_SIZE', + 'cfgRCC_DEV0_EPF0_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_STRAP0', 'cfgRCC_DEV0_EPF0_STRAP1', + 'cfgRCC_DEV0_EPF0_STRAP13', 'cfgRCC_DEV0_EPF0_STRAP14', + 'cfgRCC_DEV0_EPF0_STRAP15', 'cfgRCC_DEV0_EPF0_STRAP16', + 'cfgRCC_DEV0_EPF0_STRAP17', 'cfgRCC_DEV0_EPF0_STRAP18', + 'cfgRCC_DEV0_EPF0_STRAP2', 'cfgRCC_DEV0_EPF0_STRAP26', + 'cfgRCC_DEV0_EPF0_STRAP3', 'cfgRCC_DEV0_EPF0_STRAP4', + 'cfgRCC_DEV0_EPF0_STRAP5', 'cfgRCC_DEV0_EPF0_STRAP8', + 'cfgRCC_DEV0_EPF0_STRAP9', 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL', + 'cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA', + 'cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE', + 'cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED', + 'cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN', + 'cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG', + 'cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER', + 'cfgRCC_DEV0_EPF1_STRAP0', 'cfgRCC_DEV0_EPF1_STRAP2', + 'cfgRCC_DEV0_EPF1_STRAP20', 'cfgRCC_DEV0_EPF1_STRAP21', + 'cfgRCC_DEV0_EPF1_STRAP22', 'cfgRCC_DEV0_EPF1_STRAP23', + 'cfgRCC_DEV0_EPF1_STRAP24', 'cfgRCC_DEV0_EPF1_STRAP25', + 'cfgRCC_DEV0_EPF1_STRAP3', 'cfgRCC_DEV0_EPF1_STRAP4', + 'cfgRCC_DEV0_EPF1_STRAP5', 'cfgRCC_DEV0_EPF1_STRAP6', + 'cfgRCC_DEV0_EPF1_STRAP7', 'cfgRCC_DEV0_LINK_CNTL', + 'cfgRCC_DEV0_PORT_STRAP0', 'cfgRCC_DEV0_PORT_STRAP1', + 'cfgRCC_DEV0_PORT_STRAP10', 'cfgRCC_DEV0_PORT_STRAP11', + 'cfgRCC_DEV0_PORT_STRAP12', 'cfgRCC_DEV0_PORT_STRAP13', + 'cfgRCC_DEV0_PORT_STRAP14', 'cfgRCC_DEV0_PORT_STRAP2', + 'cfgRCC_DEV0_PORT_STRAP3', 'cfgRCC_DEV0_PORT_STRAP4', + 'cfgRCC_DEV0_PORT_STRAP5', 'cfgRCC_DEV0_PORT_STRAP6', + 'cfgRCC_DEV0_PORT_STRAP7', 'cfgRCC_DEV0_PORT_STRAP8', + 'cfgRCC_DEV0_PORT_STRAP9', 'cfgRCC_DEVFUNCNUM_LIST0', + 'cfgRCC_DEVFUNCNUM_LIST1', 'cfgRCC_EP_REQUESTERID_RESTORE', + 'cfgRCC_ERR_INT_CNTL', 'cfgRCC_FEATURES_CONTROL_MISC', + 'cfgRCC_GPUIOV_REGION', 'cfgRCC_HOST_BUSNUM', + 'cfgRCC_LTR_LSWITCH_CNTL', 'cfgRCC_MARGIN_PARAM_CNTL0', + 'cfgRCC_MARGIN_PARAM_CNTL1', 'cfgRCC_MH_ARB_CNTL', + 'cfgRCC_PEER0_FB_OFFSET_HI', 'cfgRCC_PEER0_FB_OFFSET_LO', + 'cfgRCC_PEER1_FB_OFFSET_HI', 'cfgRCC_PEER1_FB_OFFSET_LO', + 'cfgRCC_PEER2_FB_OFFSET_HI', 'cfgRCC_PEER2_FB_OFFSET_LO', + 'cfgRCC_PEER3_FB_OFFSET_HI', 'cfgRCC_PEER3_FB_OFFSET_LO', + 'cfgRCC_PEER_REG_RANGE0', 'cfgRCC_PEER_REG_RANGE1', + 'cfgRCC_RESET_EN', 'cfgRCC_VDM_SUPPORT', 'cfgRCC_XDMA_HI', + 'cfgRCC_XDMA_LO', 'cfgREMAP_HDP_MEM_FLUSH_CNTL', + 'cfgREMAP_HDP_REG_FLUSH_CNTL', 'cfgS2A_MISC_CNTL', + 'cfgSBIOS_SCRATCH_0', 'cfgSBIOS_SCRATCH_1', 'cfgSBIOS_SCRATCH_10', + 'cfgSBIOS_SCRATCH_11', 'cfgSBIOS_SCRATCH_12', + 'cfgSBIOS_SCRATCH_13', 'cfgSBIOS_SCRATCH_14', + 'cfgSBIOS_SCRATCH_15', 'cfgSBIOS_SCRATCH_2', 'cfgSBIOS_SCRATCH_3', + 'cfgSBIOS_SCRATCH_4', 'cfgSBIOS_SCRATCH_5', 'cfgSBIOS_SCRATCH_6', + 'cfgSBIOS_SCRATCH_7', 'cfgSBIOS_SCRATCH_8', 'cfgSBIOS_SCRATCH_9', + 'cfgSHADOW_BASE_ADDR_1', 'cfgSHADOW_BASE_ADDR_2', + 'cfgSHADOW_COMMAND', 'cfgSHADOW_IO_BASE_LIMIT', + 'cfgSHADOW_IO_BASE_LIMIT_HI', 'cfgSHADOW_MEM_BASE_LIMIT', + 'cfgSHADOW_PREF_BASE_LIMIT', 'cfgSHADOW_PREF_BASE_UPPER', + 'cfgSHADOW_PREF_LIMIT_UPPER', 'cfgSHADOW_SUB_BUS_NUMBER_LATENCY', + 'cfgSHUB_REGS_IF_CTL', 'cfgSUC_DATA', 'cfgSUC_INDEX', + 'cfgSUM_DATA', 'cfgSUM_INDEX', 'cfgSUM_INDEX_HI', + 'regBIFC_ATHUB_ACT_CNTL', 'regBIFC_ATHUB_ACT_CNTL_BASE_IDX', + 'regBIFC_BME_ERR_LOG_HB', 'regBIFC_BME_ERR_LOG_HB_BASE_IDX', + 'regBIFC_BME_ERR_LOG_LB', 'regBIFC_BME_ERR_LOG_LB_BASE_IDX', + 'regBIFC_DMA_ATTR_CNTL2_DEV0', + 'regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX', + 'regBIFC_EARLY_WAKEUP_CNTL', 'regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX', + 'regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC', + 'regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC', + 'regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC', + 'regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC', + 'regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_GSI_CNTL', 'regBIFC_GSI_CNTL_BASE_IDX', + 'regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC', + 'regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC', + 'regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_HSTARB_CNTL', 'regBIFC_HSTARB_CNTL_BASE_IDX', + 'regBIFC_LC_TIMER_CTRL', 'regBIFC_LC_TIMER_CTRL_BASE_IDX', + 'regBIFC_MISC_CTRL0', 'regBIFC_MISC_CTRL0_BASE_IDX', + 'regBIFC_MISC_CTRL1', 'regBIFC_MISC_CTRL1_BASE_IDX', + 'regBIFC_PASID_CHECK_DIS', 'regBIFC_PASID_CHECK_DIS_BASE_IDX', + 'regBIFC_PASID_STS', 'regBIFC_PASID_STS_BASE_IDX', + 'regBIFC_PCIEFUNC_CNTL', 'regBIFC_PCIEFUNC_CNTL_BASE_IDX', + 'regBIFC_PERF_CNTL_0', 'regBIFC_PERF_CNTL_0_BASE_IDX', + 'regBIFC_PERF_CNTL_1', 'regBIFC_PERF_CNTL_1_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_RD_H16BIT', + 'regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_RD_L32BIT', + 'regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_WR_H16BIT', + 'regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_WR_L32BIT', + 'regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_RD_H16BIT', + 'regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_RD_L32BIT', + 'regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_WR_H16BIT', + 'regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_WR_L32BIT', + 'regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX', + 'regBIFC_RCCBIH_BME_ERR_LOG0', + 'regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX', 'regBIFC_SDP_CNTL_0', + 'regBIFC_SDP_CNTL_0_BASE_IDX', 'regBIFC_SDP_CNTL_1', + 'regBIFC_SDP_CNTL_1_BASE_IDX', 'regBIFC_SDP_CNTL_2', + 'regBIFC_SDP_CNTL_2_BASE_IDX', 'regBIFL_IOHUB_RAS_IH_CNTL', + 'regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX', 'regBIFL_RAS_CENTRAL_CNTL', + 'regBIFL_RAS_CENTRAL_CNTL_BASE_IDX', 'regBIFL_RAS_CENTRAL_STATUS', + 'regBIFL_RAS_CENTRAL_STATUS_BASE_IDX', 'regBIFL_RAS_LEAF0_CTRL', + 'regBIFL_RAS_LEAF0_CTRL_BASE_IDX', 'regBIFL_RAS_LEAF0_STATUS', + 'regBIFL_RAS_LEAF0_STATUS_BASE_IDX', 'regBIFL_RAS_LEAF1_CTRL', + 'regBIFL_RAS_LEAF1_CTRL_BASE_IDX', 'regBIFL_RAS_LEAF1_STATUS', + 'regBIFL_RAS_LEAF1_STATUS_BASE_IDX', 'regBIFL_RAS_LEAF2_CTRL', + 'regBIFL_RAS_LEAF2_CTRL_BASE_IDX', 'regBIFL_RAS_LEAF2_STATUS', + 'regBIFL_RAS_LEAF2_STATUS_BASE_IDX', 'regBIFL_RAS_LEAF3_CTRL', + 'regBIFL_RAS_LEAF3_CTRL_BASE_IDX', 'regBIFL_RAS_LEAF3_STATUS', + 'regBIFL_RAS_LEAF3_STATUS_BASE_IDX', 'regBIFL_RAS_VWR_FROM_IOHUB', + 'regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F0', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F1', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F2', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F3', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX', + 'regBIF_BX0_BIF_DOORBELL_CNTL', + 'regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_DOORBELL_INT_CNTL', + 'regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_FB_EN', 'regBIF_BX0_BIF_FB_EN_BASE_IDX', + 'regBIF_BX0_BIF_FEATURES_CONTROL_MISC', + 'regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX', + 'regBIF_BX0_BIF_INTR_CNTL', 'regBIF_BX0_BIF_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_MM_INDACCESS_CNTL', + 'regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_MP1_INTR_CTRL', + 'regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX', + 'regBIF_BX0_BIF_MST_TRANS_PENDING_VF', + 'regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX0_BIF_RB_BASE', 'regBIF_BX0_BIF_RB_BASE_BASE_IDX', + 'regBIF_BX0_BIF_RB_CNTL', 'regBIF_BX0_BIF_RB_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_RB_RPTR', 'regBIF_BX0_BIF_RB_RPTR_BASE_IDX', + 'regBIF_BX0_BIF_RB_WPTR', 'regBIF_BX0_BIF_RB_WPTR_ADDR_HI', + 'regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX', + 'regBIF_BX0_BIF_RB_WPTR_ADDR_LO', + 'regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX', + 'regBIF_BX0_BIF_RB_WPTR_BASE_IDX', 'regBIF_BX0_BIF_RLC_INTR_CNTL', + 'regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_SCRATCH0', 'regBIF_BX0_BIF_SCRATCH0_BASE_IDX', + 'regBIF_BX0_BIF_SCRATCH1', 'regBIF_BX0_BIF_SCRATCH1_BASE_IDX', + 'regBIF_BX0_BIF_SLV_TRANS_PENDING_VF', + 'regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX0_BIF_UVD_INTR_CNTL', + 'regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_VCE_INTR_CNTL', + 'regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_0', 'regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_1', 'regBIF_BX0_BIOS_SCRATCH_10', + 'regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_11', + 'regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_12', + 'regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_13', + 'regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_14', + 'regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_15', + 'regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_2', + 'regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_3', + 'regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_4', + 'regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_5', + 'regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_6', + 'regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_7', + 'regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_8', + 'regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_9', + 'regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX', 'regBIF_BX0_BUS_CNTL', + 'regBIF_BX0_BUS_CNTL_BASE_IDX', 'regBIF_BX0_BX_RESET_CNTL', + 'regBIF_BX0_BX_RESET_CNTL_BASE_IDX', 'regBIF_BX0_BX_RESET_EN', + 'regBIF_BX0_BX_RESET_EN_BASE_IDX', + 'regBIF_BX0_CC_BIF_BX_PINSTRAP0', + 'regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX', + 'regBIF_BX0_CC_BIF_BX_STRAP0', + 'regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX', + 'regBIF_BX0_CLKREQB_PAD_CNTL', + 'regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_0', + 'regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_1', 'regBIF_BX0_DRIVER_SCRATCH_10', + 'regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_11', + 'regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_12', + 'regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_13', + 'regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_14', + 'regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_15', + 'regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_2', + 'regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_3', + 'regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_4', + 'regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_5', + 'regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_6', + 'regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_7', + 'regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_8', + 'regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_9', + 'regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_0', + 'regBIF_BX0_FW_SCRATCH_0_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_1', + 'regBIF_BX0_FW_SCRATCH_10', 'regBIF_BX0_FW_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_11', 'regBIF_BX0_FW_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_12', 'regBIF_BX0_FW_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_13', 'regBIF_BX0_FW_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_14', 'regBIF_BX0_FW_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_15', 'regBIF_BX0_FW_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_1_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_2', + 'regBIF_BX0_FW_SCRATCH_2_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_3', + 'regBIF_BX0_FW_SCRATCH_3_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_4', + 'regBIF_BX0_FW_SCRATCH_4_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_5', + 'regBIF_BX0_FW_SCRATCH_5_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_6', + 'regBIF_BX0_FW_SCRATCH_6_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_7', + 'regBIF_BX0_FW_SCRATCH_7_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_8', + 'regBIF_BX0_FW_SCRATCH_8_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_9', + 'regBIF_BX0_FW_SCRATCH_9_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR0', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR1', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR2', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR3', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR4', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR5', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR6', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR7', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_CNTL', + 'regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL', + 'regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL', + 'regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL', + 'regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX', + 'regBIF_BX0_HDP_ATOMIC_CONTROL_MISC', + 'regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX', + 'regBIF_BX0_INTERRUPT_CNTL', 'regBIF_BX0_INTERRUPT_CNTL2', + 'regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX', + 'regBIF_BX0_INTERRUPT_CNTL_BASE_IDX', 'regBIF_BX0_MEM_TYPE_CNTL', + 'regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX', 'regBIF_BX0_MM_CFGREGS_CNTL', + 'regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_0', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_1', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_10', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_11', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_12', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_13', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_14', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_15', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_2', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_3', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_4', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_5', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_6', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_7', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_8', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_9', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX', + 'regBIF_BX0_PCIE_DATA', 'regBIF_BX0_PCIE_DATA2', + 'regBIF_BX0_PCIE_DATA2_BASE_IDX', 'regBIF_BX0_PCIE_DATA_BASE_IDX', + 'regBIF_BX0_PCIE_INDEX', 'regBIF_BX0_PCIE_INDEX2', + 'regBIF_BX0_PCIE_INDEX2_BASE_IDX', 'regBIF_BX0_PCIE_INDEX2_HI', + 'regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX', + 'regBIF_BX0_PCIE_INDEX_BASE_IDX', 'regBIF_BX0_PCIE_INDEX_HI', + 'regBIF_BX0_PCIE_INDEX_HI_BASE_IDX', + 'regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL', + 'regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL', + 'regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_0', + 'regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_1', 'regBIF_BX0_SBIOS_SCRATCH_10', + 'regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_11', + 'regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_12', + 'regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_13', + 'regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_14', + 'regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_15', + 'regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_2', + 'regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_3', + 'regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_4', + 'regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_5', + 'regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_6', + 'regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_7', + 'regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_8', + 'regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_9', + 'regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX', + 'regBIF_BX1_BIF_CLKREQB_PAD_CNTL', + 'regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_DOORBELL_CNTL', + 'regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_DOORBELL_INT_CNTL', + 'regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_FB_EN', 'regBIF_BX1_BIF_FB_EN_BASE_IDX', + 'regBIF_BX1_BIF_FEATURES_CONTROL_MISC', + 'regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX', + 'regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE', + 'regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX', + 'regBIF_BX1_BIF_INTR_CNTL', 'regBIF_BX1_BIF_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_MM_INDACCESS_CNTL', + 'regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_MP1_INTR_CTRL', + 'regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX', + 'regBIF_BX1_BIF_MST_TRANS_PENDING_VF', + 'regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX1_BIF_PERSTB_PAD_CNTL', + 'regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_PWRBRK_PAD_CNTL', + 'regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_PX_EN_PAD_CNTL', + 'regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_RB_BASE', 'regBIF_BX1_BIF_RB_BASE_BASE_IDX', + 'regBIF_BX1_BIF_RB_CNTL', 'regBIF_BX1_BIF_RB_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_RB_RPTR', 'regBIF_BX1_BIF_RB_RPTR_BASE_IDX', + 'regBIF_BX1_BIF_RB_WPTR', 'regBIF_BX1_BIF_RB_WPTR_ADDR_HI', + 'regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX', + 'regBIF_BX1_BIF_RB_WPTR_ADDR_LO', + 'regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX', + 'regBIF_BX1_BIF_RB_WPTR_BASE_IDX', + 'regBIF_BX1_BIF_REFPADKIN_PAD_CNTL', + 'regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_RLC_INTR_CNTL', + 'regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_S5_DUMMY_REGS', + 'regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX', + 'regBIF_BX1_BIF_S5_MEM_POWER_CTRL0', + 'regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX', + 'regBIF_BX1_BIF_S5_MEM_POWER_CTRL1', + 'regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX', + 'regBIF_BX1_BIF_SCRATCH0', 'regBIF_BX1_BIF_SCRATCH0_BASE_IDX', + 'regBIF_BX1_BIF_SCRATCH1', 'regBIF_BX1_BIF_SCRATCH1_BASE_IDX', + 'regBIF_BX1_BIF_SLV_TRANS_PENDING_VF', + 'regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX1_BIF_UVD_INTR_CNTL', + 'regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL', + 'regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_VCE_INTR_CNTL', + 'regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE', + 'regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX', + 'regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE', + 'regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX', + 'regBIF_BX1_BIF_WAKEB_PAD_CNTL', + 'regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_0', 'regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_1', 'regBIF_BX1_BIOS_SCRATCH_10', + 'regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_11', + 'regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_12', + 'regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_13', + 'regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_14', + 'regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_15', + 'regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_2', + 'regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_3', + 'regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_4', + 'regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_5', + 'regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_6', + 'regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_7', + 'regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_8', + 'regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_9', + 'regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX', 'regBIF_BX1_BUS_CNTL', + 'regBIF_BX1_BUS_CNTL_BASE_IDX', 'regBIF_BX1_BX_RESET_CNTL', + 'regBIF_BX1_BX_RESET_CNTL_BASE_IDX', 'regBIF_BX1_BX_RESET_EN', + 'regBIF_BX1_BX_RESET_EN_BASE_IDX', + 'regBIF_BX1_CC_BIF_BX_PINSTRAP0', + 'regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX', + 'regBIF_BX1_CC_BIF_BX_STRAP0', + 'regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX', + 'regBIF_BX1_CLKREQB_PAD_CNTL', + 'regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_0', + 'regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_1', 'regBIF_BX1_DRIVER_SCRATCH_10', + 'regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_11', + 'regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_12', + 'regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_13', + 'regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_14', + 'regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_15', + 'regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_2', + 'regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_3', + 'regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_4', + 'regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_5', + 'regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_6', + 'regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_7', + 'regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_8', + 'regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_9', + 'regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_0', + 'regBIF_BX1_FW_SCRATCH_0_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_1', + 'regBIF_BX1_FW_SCRATCH_10', 'regBIF_BX1_FW_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_11', 'regBIF_BX1_FW_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_12', 'regBIF_BX1_FW_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_13', 'regBIF_BX1_FW_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_14', 'regBIF_BX1_FW_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_15', 'regBIF_BX1_FW_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_1_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_2', + 'regBIF_BX1_FW_SCRATCH_2_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_3', + 'regBIF_BX1_FW_SCRATCH_3_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_4', + 'regBIF_BX1_FW_SCRATCH_4_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_5', + 'regBIF_BX1_FW_SCRATCH_5_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_6', + 'regBIF_BX1_FW_SCRATCH_6_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_7', + 'regBIF_BX1_FW_SCRATCH_7_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_8', + 'regBIF_BX1_FW_SCRATCH_8_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_9', + 'regBIF_BX1_FW_SCRATCH_9_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR0', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR1', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR2', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR3', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR4', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR5', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR6', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR7', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_CNTL', + 'regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL', + 'regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL', + 'regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL', + 'regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX', + 'regBIF_BX1_HDP_ATOMIC_CONTROL_MISC', + 'regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX', + 'regBIF_BX1_INTERRUPT_CNTL', 'regBIF_BX1_INTERRUPT_CNTL2', + 'regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX', + 'regBIF_BX1_INTERRUPT_CNTL_BASE_IDX', 'regBIF_BX1_MAILBOX_INDEX', + 'regBIF_BX1_MAILBOX_INDEX_BASE_IDX', 'regBIF_BX1_MEM_TYPE_CNTL', + 'regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX', 'regBIF_BX1_MM_CFGREGS_CNTL', + 'regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_0', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_1', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_10', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_11', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_12', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_13', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_14', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_15', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_2', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_3', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_4', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_5', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_6', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_7', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_8', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_9', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX', + 'regBIF_BX1_PCIE_DATA', 'regBIF_BX1_PCIE_DATA2', + 'regBIF_BX1_PCIE_DATA2_BASE_IDX', 'regBIF_BX1_PCIE_DATA_BASE_IDX', + 'regBIF_BX1_PCIE_INDEX', 'regBIF_BX1_PCIE_INDEX2', + 'regBIF_BX1_PCIE_INDEX2_BASE_IDX', 'regBIF_BX1_PCIE_INDEX2_HI', + 'regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX', + 'regBIF_BX1_PCIE_INDEX_BASE_IDX', 'regBIF_BX1_PCIE_INDEX_HI', + 'regBIF_BX1_PCIE_INDEX_HI_BASE_IDX', + 'regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL', + 'regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX', + 'regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL', + 'regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL', + 'regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_0', + 'regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_1', 'regBIF_BX1_SBIOS_SCRATCH_10', + 'regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_11', + 'regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_12', + 'regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_13', + 'regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_14', + 'regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_15', + 'regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_2', + 'regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_3', + 'regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_4', + 'regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_5', + 'regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_6', + 'regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_7', + 'regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_8', + 'regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_9', + 'regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX', + 'regBIF_BX1_VF_DOORBELL_EN', 'regBIF_BX1_VF_DOORBELL_EN_BASE_IDX', + 'regBIF_BX1_VF_DOORBELL_STATUS', + 'regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX', 'regBIF_BX1_VF_FB_EN', + 'regBIF_BX1_VF_FB_EN_BASE_IDX', 'regBIF_BX1_VF_FB_STATUS', + 'regBIF_BX1_VF_FB_STATUS_BASE_IDX', 'regBIF_BX1_VF_REGWR_EN', + 'regBIF_BX1_VF_REGWR_EN_BASE_IDX', 'regBIF_BX1_VF_REGWR_STATUS', + 'regBIF_BX1_VF_REGWR_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_PF0_BIF_BME_STATUS', + 'regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_PF0_BIF_TRANS_PENDING', + 'regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF0_MM_DATA', 'regBIF_BX_PF0_MM_DATA_BASE_IDX', + 'regBIF_BX_PF0_MM_INDEX', 'regBIF_BX_PF0_MM_INDEX_BASE_IDX', + 'regBIF_BX_PF0_MM_INDEX_HI', 'regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_PF0_RSMU_DATA', 'regBIF_BX_PF0_RSMU_DATA_BASE_IDX', + 'regBIF_BX_PF0_RSMU_INDEX', 'regBIF_BX_PF0_RSMU_INDEX_BASE_IDX', + 'regBIF_BX_PF0_RSMU_INDEX_HI', + 'regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX', + 'regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_PF1_BIF_BME_STATUS', + 'regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_PF1_BIF_TRANS_PENDING', + 'regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_PF1_BIF_VMHV_MAILBOX', + 'regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_CONTROL', + 'regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_INT_CNTL', + 'regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_PF1_MM_DATA', 'regBIF_BX_PF1_MM_DATA_BASE_IDX', + 'regBIF_BX_PF1_MM_INDEX', 'regBIF_BX_PF1_MM_INDEX_BASE_IDX', + 'regBIF_BX_PF1_MM_INDEX_HI', 'regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W', + 'regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_BIST', 'regBIF_CFG_DEV0_EPF0_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_COMMAND', + 'regBIF_CFG_DEV0_EPF0_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP', + 'regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS', + 'regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_HEADER', + 'regBIF_CFG_DEV0_EPF0_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LATENCY', + 'regBIF_CFG_DEV0_EPF0_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CAP', 'regBIF_CFG_DEV0_EPF0_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT', + 'regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT', + 'regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP', + 'regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS', + 'regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1', + 'regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2', + 'regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3', + 'regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1', + 'regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE', + 'regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PMI_CAP', + 'regBIF_CFG_DEV0_EPF0_PMI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL', + 'regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_STATUS', + 'regBIF_CFG_DEV0_EPF0_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_BIST', + 'regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_BIST', + 'regBIF_CFG_DEV0_EPF0_VF10_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF10_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF10_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF10_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF10_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_BIST', + 'regBIF_CFG_DEV0_EPF0_VF11_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF11_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF11_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF11_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF11_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_BIST', + 'regBIF_CFG_DEV0_EPF0_VF12_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF12_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF12_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF12_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF12_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_BIST', + 'regBIF_CFG_DEV0_EPF0_VF13_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF13_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF13_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF13_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF13_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_BIST', + 'regBIF_CFG_DEV0_EPF0_VF14_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF14_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF14_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF14_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF14_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_BIST', + 'regBIF_CFG_DEV0_EPF0_VF15_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF15_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF15_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF15_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF15_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_BIST', + 'regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_BIST', + 'regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_BIST', + 'regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_BIST', + 'regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_BIST', + 'regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_BIST', + 'regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_BIST', + 'regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_BIST', + 'regBIF_CFG_DEV0_EPF0_VF8_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF8_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF8_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF8_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF8_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_BIST', + 'regBIF_CFG_DEV0_EPF0_VF9_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_COMMAND', + 'regBIF_CFG_DEV0_EPF0_VF9_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_HEADER', + 'regBIF_CFG_DEV0_EPF0_VF9_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF9_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_STATUS', + 'regBIF_CFG_DEV0_EPF0_VF9_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W', + 'regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_BIST', 'regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_CAP_PTR', + 'regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_COMMAND', + 'regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_HEADER', + 'regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_LATENCY', + 'regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_LINK_CAP', 'regBIF_CFG_DEV0_EPF1_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF1_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF1_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_MASK', + 'regBIF_CFG_DEV0_EPF1_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF1_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1', + 'regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2', + 'regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS', + 'regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3', + 'regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1', + 'regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE', + 'regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PMI_CAP', + 'regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL', + 'regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_REVISION_ID', + 'regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_STATUS', + 'regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF2_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W', + 'regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF2_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF2_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_BIST', 'regBIF_CFG_DEV0_EPF2_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF2_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_CAP_PTR', + 'regBIF_CFG_DEV0_EPF2_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_COMMAND', + 'regBIF_CFG_DEV0_EPF2_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DBESL_DBESLD', + 'regBIF_CFG_DEV0_EPF2_DBESL_DBESLD_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF2_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_FLADJ', + 'regBIF_CFG_DEV0_EPF2_FLADJ_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_HEADER', + 'regBIF_CFG_DEV0_EPF2_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_LATENCY', + 'regBIF_CFG_DEV0_EPF2_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_LINK_CAP', 'regBIF_CFG_DEV0_EPF2_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF2_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF2_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF2_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF2_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF2_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF2_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF2_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF2_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF2_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_MASK', + 'regBIF_CFG_DEV0_EPF2_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF2_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF2_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF2_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL', + 'regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PMI_CAP', + 'regBIF_CFG_DEV0_EPF2_PMI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL', + 'regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF2_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_REVISION_ID', + 'regBIF_CFG_DEV0_EPF2_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_SBRN', 'regBIF_CFG_DEV0_EPF2_SBRN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_STATUS', + 'regBIF_CFG_DEV0_EPF2_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF2_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST', + 'regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF2_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF2_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF3_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W', + 'regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF3_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF3_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_BIST', 'regBIF_CFG_DEV0_EPF3_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF3_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_CAP_PTR', + 'regBIF_CFG_DEV0_EPF3_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_COMMAND', + 'regBIF_CFG_DEV0_EPF3_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DBESL_DBESLD', + 'regBIF_CFG_DEV0_EPF3_DBESL_DBESLD_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF3_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_FLADJ', + 'regBIF_CFG_DEV0_EPF3_FLADJ_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_HEADER', + 'regBIF_CFG_DEV0_EPF3_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_LATENCY', + 'regBIF_CFG_DEV0_EPF3_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_LINK_CAP', 'regBIF_CFG_DEV0_EPF3_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF3_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF3_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF3_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF3_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF3_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF3_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF3_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF3_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF3_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_MASK', + 'regBIF_CFG_DEV0_EPF3_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF3_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF3_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF3_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL', + 'regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PMI_CAP', + 'regBIF_CFG_DEV0_EPF3_PMI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL', + 'regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF3_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_REVISION_ID', + 'regBIF_CFG_DEV0_EPF3_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_SBRN', 'regBIF_CFG_DEV0_EPF3_SBRN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_STATUS', + 'regBIF_CFG_DEV0_EPF3_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF3_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST', + 'regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF3_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF3_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_RC_IO_BASE_LIMIT', + 'regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_BASE_IDX', + 'regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI', + 'regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI_BASE_IDX', + 'regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT', + 'regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT_BASE_IDX', + 'regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT', + 'regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT_BASE_IDX', + 'regBIF_CFG_DEV0_RC_PREF_BASE_UPPER', + 'regBIF_CFG_DEV0_RC_PREF_BASE_UPPER_BASE_IDX', + 'regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER', + 'regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER_BASE_IDX', + 'regBIF_CFG_DEV0_RC_SECONDARY_STATUS', + 'regBIF_CFG_DEV0_RC_SECONDARY_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC_SSID_CAP', + 'regBIF_CFG_DEV0_RC_SSID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC_SSID_CAP_LIST', + 'regBIF_CFG_DEV0_RC_SSID_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY', + 'regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY_BASE_IDX', + 'regBIF_D3HOTD0_INTR_MASK', 'regBIF_D3HOTD0_INTR_MASK_BASE_IDX', + 'regBIF_D3HOTD0_INTR_STS', 'regBIF_D3HOTD0_INTR_STS_BASE_IDX', + 'regBIF_DEV0_PF0_DSTATE_VALUE', + 'regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX', + 'regBIF_DEV0_PF1_DSTATE_VALUE', + 'regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX', + 'regBIF_DEV0_PF2_DSTATE_VALUE', + 'regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX', + 'regBIF_DEV0_PF3_DSTATE_VALUE', + 'regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX', 'regBIF_DMA_MP4_ERR_LOG', + 'regBIF_DMA_MP4_ERR_LOG_BASE_IDX', 'regBIF_GFX_DRV_VPU_RST', + 'regBIF_GFX_DRV_VPU_RST_BASE_IDX', 'regBIF_GMI_WRR_WEIGHT', + 'regBIF_GMI_WRR_WEIGHT2', 'regBIF_GMI_WRR_WEIGHT2_BASE_IDX', + 'regBIF_GMI_WRR_WEIGHT3', 'regBIF_GMI_WRR_WEIGHT3_BASE_IDX', + 'regBIF_GMI_WRR_WEIGHT_BASE_IDX', 'regBIF_INST_RESET_INTR_MASK', + 'regBIF_INST_RESET_INTR_MASK_BASE_IDX', + 'regBIF_INST_RESET_INTR_STS', + 'regBIF_INST_RESET_INTR_STS_BASE_IDX', 'regBIF_PASID_ERR_CLR', + 'regBIF_PASID_ERR_CLR_BASE_IDX', 'regBIF_PASID_ERR_LOG', + 'regBIF_PASID_ERR_LOG_BASE_IDX', 'regBIF_PF_DSTATE_INTR_MASK', + 'regBIF_PF_DSTATE_INTR_MASK_BASE_IDX', + 'regBIF_PF_DSTATE_INTR_STS', 'regBIF_PF_DSTATE_INTR_STS_BASE_IDX', + 'regBIF_PF_FLR_INTR_MASK', 'regBIF_PF_FLR_INTR_MASK_BASE_IDX', + 'regBIF_PF_FLR_INTR_STS', 'regBIF_PF_FLR_INTR_STS_BASE_IDX', + 'regBIF_PF_FLR_RST', 'regBIF_PF_FLR_RST_BASE_IDX', + 'regBIF_PORT0_DSTATE_VALUE', 'regBIF_PORT0_DSTATE_VALUE_BASE_IDX', + 'regBIF_POWER_INTR_MASK', 'regBIF_POWER_INTR_MASK_BASE_IDX', + 'regBIF_POWER_INTR_STS', 'regBIF_POWER_INTR_STS_BASE_IDX', + 'regBIF_RST_MISC_CTRL', 'regBIF_RST_MISC_CTRL2', + 'regBIF_RST_MISC_CTRL2_BASE_IDX', 'regBIF_RST_MISC_CTRL3', + 'regBIF_RST_MISC_CTRL3_BASE_IDX', 'regBIF_RST_MISC_CTRL_BASE_IDX', + 'regBIF_SELFRING_BUFFER_VID', + 'regBIF_SELFRING_BUFFER_VID_BASE_IDX', + 'regBIF_SELFRING_VECTOR_CNTL', + 'regBIF_SELFRING_VECTOR_CNTL_BASE_IDX', 'regBME_DUMMY_CNTL_0', + 'regBME_DUMMY_CNTL_0_BASE_IDX', 'regCPM_CONTROL', + 'regCPM_CONTROL_BASE_IDX', 'regCPM_CONTROL_EXT', + 'regCPM_CONTROL_EXT_BASE_IDX', 'regCPM_SPLIT_CONTROL', + 'regCPM_SPLIT_CONTROL_BASE_IDX', 'regDEV0_PF0_D3HOTD0_RST_CTRL', + 'regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX', + 'regDEV0_PF0_FLR_RST_CTRL', 'regDEV0_PF0_FLR_RST_CTRL_BASE_IDX', + 'regDEV0_PF1_D3HOTD0_RST_CTRL', + 'regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX', + 'regDEV0_PF1_FLR_RST_CTRL', 'regDEV0_PF1_FLR_RST_CTRL_BASE_IDX', + 'regDEV0_PF2_D3HOTD0_RST_CTRL', + 'regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX', + 'regDEV0_PF2_FLR_RST_CTRL', 'regDEV0_PF2_FLR_RST_CTRL_BASE_IDX', + 'regDEV0_PF3_D3HOTD0_RST_CTRL', + 'regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX', + 'regDEV0_PF3_FLR_RST_CTRL', 'regDEV0_PF3_FLR_RST_CTRL_BASE_IDX', + 'regDISCON_HYSTERESIS_HEAD_CTRL', + 'regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX', + 'regGDC0_ATDMA_MISC_CNTL', 'regGDC0_ATDMA_MISC_CNTL_BASE_IDX', + 'regGDC0_NBIF_GFX_DOORBELL_STATUS', + 'regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX', + 'regGDC0_S2A_MISC_CNTL', 'regGDC0_S2A_MISC_CNTL_BASE_IDX', + 'regGDC0_SHUB_REGS_IF_CTL', 'regGDC0_SHUB_REGS_IF_CTL_BASE_IDX', + 'regGDC1_ATDMA_MISC_CNTL', 'regGDC1_ATDMA_MISC_CNTL_BASE_IDX', + 'regGDC1_NBIF_GFX_DOORBELL_STATUS', + 'regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX', + 'regGDC1_NGDC_EARLY_WAKEUP_CTRL', + 'regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX', + 'regGDC1_NGDC_MGCG_CTRL', 'regGDC1_NGDC_MGCG_CTRL_BASE_IDX', + 'regGDC1_NGDC_PGMST_CTRL', 'regGDC1_NGDC_PGMST_CTRL_BASE_IDX', + 'regGDC1_NGDC_PGSLV_CTRL', 'regGDC1_NGDC_PGSLV_CTRL_BASE_IDX', + 'regGDC1_NGDC_PG_MISC_CTRL', 'regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX', + 'regGDC1_NGDC_RESERVED_0', 'regGDC1_NGDC_RESERVED_0_BASE_IDX', + 'regGDC1_NGDC_RESERVED_1', 'regGDC1_NGDC_RESERVED_1_BASE_IDX', + 'regGDC1_S2A_MISC_CNTL', 'regGDC1_S2A_MISC_CNTL_BASE_IDX', + 'regGDC1_SHUB_REGS_IF_CTL', 'regGDC1_SHUB_REGS_IF_CTL_BASE_IDX', + 'regGDCSOC_ERR_RSP_CNTL', 'regGDCSOC_ERR_RSP_CNTL_BASE_IDX', + 'regGDCSOC_RAS_CENTRAL_STATUS', + 'regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX', + 'regGDCSOC_RAS_LEAF0_CTRL', 'regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX', + 'regGDCSOC_RAS_LEAF0_STATUS', + 'regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX', 'regGDCSOC_RAS_LEAF1_CTRL', + 'regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX', 'regGDCSOC_RAS_LEAF1_STATUS', + 'regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX', 'regGDCSOC_RAS_LEAF2_CTRL', + 'regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX', + 'regGDCSOC_RAS_LEAF2_MISC_CTRL', 'regGDCSOC_RAS_LEAF2_MISC_CTRL2', + 'regGDCSOC_RAS_LEAF2_MISC_CTRL2_BASE_IDX', + 'regGDCSOC_RAS_LEAF2_MISC_CTRL_BASE_IDX', + 'regGDCSOC_RAS_LEAF2_STATUS', + 'regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX', 'regGDCSOC_RAS_LEAF3_CTRL', + 'regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX', 'regGDCSOC_RAS_LEAF3_STATUS', + 'regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX', 'regGDCSOC_RAS_LEAF4_CTRL', + 'regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX', 'regGDCSOC_RAS_LEAF4_STATUS', + 'regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX', + 'regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_Req_BurstTarget_REG0', + 'regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_Req_BurstTarget_REG1', + 'regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_Req_TimeSlot_REG0', + 'regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_Req_TimeSlot_REG1', + 'regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_Req_BurstTarget_REG0', + 'regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_Req_BurstTarget_REG1', + 'regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_Req_TimeSlot_REG0', + 'regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_Req_TimeSlot_REG1', + 'regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_Req_BurstTarget_REG0', + 'regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_Req_BurstTarget_REG1', + 'regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_Req_TimeSlot_REG0', + 'regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_Req_TimeSlot_REG1', + 'regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_Req_BurstTarget_REG0', + 'regGDC_DMA_SION_CL3_Req_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_Req_BurstTarget_REG1', + 'regGDC_DMA_SION_CL3_Req_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_Req_TimeSlot_REG0', + 'regGDC_DMA_SION_CL3_Req_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_Req_TimeSlot_REG1', + 'regGDC_DMA_SION_CL3_Req_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0', + 'regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1', + 'regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0', + 'regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1', + 'regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0', + 'regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1', + 'regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_DMA_SION_CNTL_REG0', 'regGDC_DMA_SION_CNTL_REG0_BASE_IDX', + 'regGDC_DMA_SION_CNTL_REG1', 'regGDC_DMA_SION_CNTL_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0', + 'regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1', + 'regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0', + 'regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1', + 'regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_Req_BurstTarget_REG0', + 'regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_Req_BurstTarget_REG1', + 'regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_Req_TimeSlot_REG0', + 'regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_Req_TimeSlot_REG1', + 'regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0', + 'regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1', + 'regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0', + 'regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1', + 'regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0', + 'regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1', + 'regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0', + 'regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1', + 'regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_Req_BurstTarget_REG0', + 'regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_Req_BurstTarget_REG1', + 'regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_Req_TimeSlot_REG0', + 'regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_Req_TimeSlot_REG1', + 'regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0', + 'regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1', + 'regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0', + 'regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1', + 'regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0', + 'regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1', + 'regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0', + 'regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1', + 'regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_Req_BurstTarget_REG0', + 'regGDC_HST_SION_CL2_Req_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_Req_BurstTarget_REG1', + 'regGDC_HST_SION_CL2_Req_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_Req_TimeSlot_REG0', + 'regGDC_HST_SION_CL2_Req_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_Req_TimeSlot_REG1', + 'regGDC_HST_SION_CL2_Req_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0', + 'regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1', + 'regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0', + 'regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1', + 'regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX', + 'regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0', + 'regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX', + 'regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1', + 'regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX', + 'regGDC_HST_SION_CNTL_REG0', 'regGDC_HST_SION_CNTL_REG0_BASE_IDX', + 'regGDC_HST_SION_CNTL_REG1', 'regGDC_HST_SION_CNTL_REG1_BASE_IDX', + 'regHARD_RST_CTRL', 'regHARD_RST_CTRL_BASE_IDX', + 'regHST_CLK0_SW0_CL0_CNTL', 'regHST_CLK0_SW0_CL0_CNTL_BASE_IDX', + 'regHST_CLK0_SW1_CL0_CNTL', 'regHST_CLK0_SW1_CL0_CNTL_BASE_IDX', + 'regINTR_LINE_ENABLE', 'regINTR_LINE_ENABLE_BASE_IDX', + 'regINTR_LINE_POLARITY', 'regINTR_LINE_POLARITY_BASE_IDX', + 'regLC_CPM_CONTROL_0', 'regLC_CPM_CONTROL_0_BASE_IDX', + 'regLC_CPM_CONTROL_1', 'regLC_CPM_CONTROL_1_BASE_IDX', + 'regLNCNT_CONTROL', 'regLNCNT_CONTROL_BASE_IDX', + 'regMISC_SCRATCH', 'regMISC_SCRATCH_BASE_IDX', + 'regNBIF_DS_CTRL_LCLK', 'regNBIF_DS_CTRL_LCLK_BASE_IDX', + 'regNBIF_INTX_DSTATE_MISC_CNTL', + 'regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX', + 'regNBIF_MGCG_CTRL_LCLK', 'regNBIF_MGCG_CTRL_LCLK_BASE_IDX', + 'regNBIF_PENDING_MISC_CNTL', 'regNBIF_PENDING_MISC_CNTL_BASE_IDX', + 'regNBIF_PGMST_CTRL', 'regNBIF_PGMST_CTRL_BASE_IDX', + 'regNBIF_PGSLV_CTRL', 'regNBIF_PGSLV_CTRL_BASE_IDX', + 'regNBIF_PG_MISC_CTRL', 'regNBIF_PG_MISC_CTRL_BASE_IDX', + 'regNBIF_PWRBRK_REQUEST', 'regNBIF_PWRBRK_REQUEST_BASE_IDX', + 'regNBIF_REGIF_ERRSET_CTRL', 'regNBIF_REGIF_ERRSET_CTRL_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_DIS_CTRL', + 'regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL0', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL1', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_TRIG', 'regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_CTRL', + 'regNBIF_SHUB_TODET_CLIENT_CTRL2', + 'regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_STATUS', + 'regNBIF_SHUB_TODET_CLIENT_STATUS2', + 'regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX', + 'regNBIF_SHUB_TODET_CTRL', 'regNBIF_SHUB_TODET_CTRL_BASE_IDX', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL_1', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_RST_CTRL0', + 'regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_TRIG', 'regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX', + 'regNBIF_SMN_VWR_WTRIG_CNTL', + 'regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX', 'regNBIF_STRAP_BIOS_CNTL', + 'regNBIF_STRAP_BIOS_CNTL_BASE_IDX', 'regNBIF_STRAP_WRITE_CTRL', + 'regNBIF_STRAP_WRITE_CTRL_BASE_IDX', 'regNBIF_VWIRE_CTRL', + 'regNBIF_VWIRE_CTRL_BASE_IDX', 'regOUTSTANDING_VC_ALLOC', + 'regOUTSTANDING_VC_ALLOC_BASE_IDX', 'regPCIEMSIX_PBA_0', + 'regPCIEMSIX_PBA_0_BASE_IDX', 'regPCIEMSIX_PBA_1', + 'regPCIEMSIX_PBA_1_BASE_IDX', 'regPCIEMSIX_PBA_2', + 'regPCIEMSIX_PBA_2_BASE_IDX', 'regPCIEMSIX_PBA_3', + 'regPCIEMSIX_PBA_3_BASE_IDX', 'regPCIEMSIX_PBA_4', + 'regPCIEMSIX_PBA_4_BASE_IDX', 'regPCIEMSIX_PBA_5', + 'regPCIEMSIX_PBA_5_BASE_IDX', 'regPCIEMSIX_PBA_6', + 'regPCIEMSIX_PBA_6_BASE_IDX', 'regPCIEMSIX_PBA_7', + 'regPCIEMSIX_PBA_7_BASE_IDX', 'regPCIEMSIX_VECT0_ADDR_HI', + 'regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX', 'regPCIEMSIX_VECT0_ADDR_LO', + 'regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX', 'regPCIEMSIX_VECT0_CONTROL', + 'regPCIEMSIX_VECT0_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT0_MSG_DATA', + 'regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT100_ADDR_HI', + 'regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT100_ADDR_LO', + 'regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT100_CONTROL', + 'regPCIEMSIX_VECT100_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT100_MSG_DATA', + 'regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT101_ADDR_HI', + 'regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT101_ADDR_LO', + 'regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT101_CONTROL', + 'regPCIEMSIX_VECT101_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT101_MSG_DATA', + 'regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT102_ADDR_HI', + 'regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT102_ADDR_LO', + 'regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT102_CONTROL', + 'regPCIEMSIX_VECT102_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT102_MSG_DATA', + 'regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT103_ADDR_HI', + 'regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT103_ADDR_LO', + 'regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT103_CONTROL', + 'regPCIEMSIX_VECT103_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT103_MSG_DATA', + 'regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT104_ADDR_HI', + 'regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT104_ADDR_LO', + 'regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT104_CONTROL', + 'regPCIEMSIX_VECT104_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT104_MSG_DATA', + 'regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT105_ADDR_HI', + 'regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT105_ADDR_LO', + 'regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT105_CONTROL', + 'regPCIEMSIX_VECT105_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT105_MSG_DATA', + 'regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT106_ADDR_HI', + 'regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT106_ADDR_LO', + 'regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT106_CONTROL', + 'regPCIEMSIX_VECT106_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT106_MSG_DATA', + 'regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT107_ADDR_HI', + 'regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT107_ADDR_LO', + 'regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT107_CONTROL', + 'regPCIEMSIX_VECT107_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT107_MSG_DATA', + 'regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT108_ADDR_HI', + 'regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT108_ADDR_LO', + 'regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT108_CONTROL', + 'regPCIEMSIX_VECT108_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT108_MSG_DATA', + 'regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT109_ADDR_HI', + 'regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT109_ADDR_LO', + 'regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT109_CONTROL', + 'regPCIEMSIX_VECT109_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT109_MSG_DATA', + 'regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT10_ADDR_HI', + 'regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT10_ADDR_LO', + 'regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT10_CONTROL', + 'regPCIEMSIX_VECT10_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT10_MSG_DATA', + 'regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT110_ADDR_HI', + 'regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT110_ADDR_LO', + 'regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT110_CONTROL', + 'regPCIEMSIX_VECT110_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT110_MSG_DATA', + 'regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT111_ADDR_HI', + 'regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT111_ADDR_LO', + 'regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT111_CONTROL', + 'regPCIEMSIX_VECT111_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT111_MSG_DATA', + 'regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT112_ADDR_HI', + 'regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT112_ADDR_LO', + 'regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT112_CONTROL', + 'regPCIEMSIX_VECT112_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT112_MSG_DATA', + 'regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT113_ADDR_HI', + 'regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT113_ADDR_LO', + 'regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT113_CONTROL', + 'regPCIEMSIX_VECT113_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT113_MSG_DATA', + 'regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT114_ADDR_HI', + 'regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT114_ADDR_LO', + 'regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT114_CONTROL', + 'regPCIEMSIX_VECT114_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT114_MSG_DATA', + 'regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT115_ADDR_HI', + 'regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT115_ADDR_LO', + 'regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT115_CONTROL', + 'regPCIEMSIX_VECT115_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT115_MSG_DATA', + 'regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT116_ADDR_HI', + 'regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT116_ADDR_LO', + 'regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT116_CONTROL', + 'regPCIEMSIX_VECT116_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT116_MSG_DATA', + 'regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT117_ADDR_HI', + 'regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT117_ADDR_LO', + 'regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT117_CONTROL', + 'regPCIEMSIX_VECT117_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT117_MSG_DATA', + 'regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT118_ADDR_HI', + 'regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT118_ADDR_LO', + 'regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT118_CONTROL', + 'regPCIEMSIX_VECT118_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT118_MSG_DATA', + 'regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT119_ADDR_HI', + 'regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT119_ADDR_LO', + 'regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT119_CONTROL', + 'regPCIEMSIX_VECT119_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT119_MSG_DATA', + 'regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT11_ADDR_HI', + 'regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT11_ADDR_LO', + 'regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT11_CONTROL', + 'regPCIEMSIX_VECT11_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT11_MSG_DATA', + 'regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT120_ADDR_HI', + 'regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT120_ADDR_LO', + 'regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT120_CONTROL', + 'regPCIEMSIX_VECT120_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT120_MSG_DATA', + 'regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT121_ADDR_HI', + 'regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT121_ADDR_LO', + 'regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT121_CONTROL', + 'regPCIEMSIX_VECT121_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT121_MSG_DATA', + 'regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT122_ADDR_HI', + 'regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT122_ADDR_LO', + 'regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT122_CONTROL', + 'regPCIEMSIX_VECT122_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT122_MSG_DATA', + 'regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT123_ADDR_HI', + 'regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT123_ADDR_LO', + 'regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT123_CONTROL', + 'regPCIEMSIX_VECT123_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT123_MSG_DATA', + 'regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT124_ADDR_HI', + 'regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT124_ADDR_LO', + 'regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT124_CONTROL', + 'regPCIEMSIX_VECT124_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT124_MSG_DATA', + 'regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT125_ADDR_HI', + 'regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT125_ADDR_LO', + 'regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT125_CONTROL', + 'regPCIEMSIX_VECT125_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT125_MSG_DATA', + 'regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT126_ADDR_HI', + 'regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT126_ADDR_LO', + 'regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT126_CONTROL', + 'regPCIEMSIX_VECT126_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT126_MSG_DATA', + 'regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT127_ADDR_HI', + 'regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT127_ADDR_LO', + 'regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT127_CONTROL', + 'regPCIEMSIX_VECT127_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT127_MSG_DATA', + 'regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT128_ADDR_HI', + 'regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT128_ADDR_LO', + 'regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT128_CONTROL', + 'regPCIEMSIX_VECT128_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT128_MSG_DATA', + 'regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT129_ADDR_HI', + 'regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT129_ADDR_LO', + 'regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT129_CONTROL', + 'regPCIEMSIX_VECT129_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT129_MSG_DATA', + 'regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT12_ADDR_HI', + 'regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT12_ADDR_LO', + 'regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT12_CONTROL', + 'regPCIEMSIX_VECT12_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT12_MSG_DATA', + 'regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT130_ADDR_HI', + 'regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT130_ADDR_LO', + 'regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT130_CONTROL', + 'regPCIEMSIX_VECT130_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT130_MSG_DATA', + 'regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT131_ADDR_HI', + 'regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT131_ADDR_LO', + 'regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT131_CONTROL', + 'regPCIEMSIX_VECT131_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT131_MSG_DATA', + 'regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT132_ADDR_HI', + 'regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT132_ADDR_LO', + 'regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT132_CONTROL', + 'regPCIEMSIX_VECT132_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT132_MSG_DATA', + 'regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT133_ADDR_HI', + 'regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT133_ADDR_LO', + 'regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT133_CONTROL', + 'regPCIEMSIX_VECT133_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT133_MSG_DATA', + 'regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT134_ADDR_HI', + 'regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT134_ADDR_LO', + 'regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT134_CONTROL', + 'regPCIEMSIX_VECT134_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT134_MSG_DATA', + 'regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT135_ADDR_HI', + 'regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT135_ADDR_LO', + 'regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT135_CONTROL', + 'regPCIEMSIX_VECT135_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT135_MSG_DATA', + 'regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT136_ADDR_HI', + 'regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT136_ADDR_LO', + 'regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT136_CONTROL', + 'regPCIEMSIX_VECT136_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT136_MSG_DATA', + 'regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT137_ADDR_HI', + 'regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT137_ADDR_LO', + 'regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT137_CONTROL', + 'regPCIEMSIX_VECT137_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT137_MSG_DATA', + 'regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT138_ADDR_HI', + 'regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT138_ADDR_LO', + 'regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT138_CONTROL', + 'regPCIEMSIX_VECT138_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT138_MSG_DATA', + 'regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT139_ADDR_HI', + 'regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT139_ADDR_LO', + 'regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT139_CONTROL', + 'regPCIEMSIX_VECT139_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT139_MSG_DATA', + 'regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT13_ADDR_HI', + 'regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT13_ADDR_LO', + 'regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT13_CONTROL', + 'regPCIEMSIX_VECT13_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT13_MSG_DATA', + 'regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT140_ADDR_HI', + 'regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT140_ADDR_LO', + 'regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT140_CONTROL', + 'regPCIEMSIX_VECT140_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT140_MSG_DATA', + 'regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT141_ADDR_HI', + 'regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT141_ADDR_LO', + 'regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT141_CONTROL', + 'regPCIEMSIX_VECT141_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT141_MSG_DATA', + 'regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT142_ADDR_HI', + 'regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT142_ADDR_LO', + 'regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT142_CONTROL', + 'regPCIEMSIX_VECT142_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT142_MSG_DATA', + 'regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT143_ADDR_HI', + 'regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT143_ADDR_LO', + 'regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT143_CONTROL', + 'regPCIEMSIX_VECT143_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT143_MSG_DATA', + 'regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT144_ADDR_HI', + 'regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT144_ADDR_LO', + 'regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT144_CONTROL', + 'regPCIEMSIX_VECT144_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT144_MSG_DATA', + 'regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT145_ADDR_HI', + 'regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT145_ADDR_LO', + 'regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT145_CONTROL', + 'regPCIEMSIX_VECT145_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT145_MSG_DATA', + 'regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT146_ADDR_HI', + 'regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT146_ADDR_LO', + 'regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT146_CONTROL', + 'regPCIEMSIX_VECT146_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT146_MSG_DATA', + 'regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT147_ADDR_HI', + 'regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT147_ADDR_LO', + 'regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT147_CONTROL', + 'regPCIEMSIX_VECT147_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT147_MSG_DATA', + 'regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT148_ADDR_HI', + 'regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT148_ADDR_LO', + 'regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT148_CONTROL', + 'regPCIEMSIX_VECT148_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT148_MSG_DATA', + 'regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT149_ADDR_HI', + 'regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT149_ADDR_LO', + 'regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT149_CONTROL', + 'regPCIEMSIX_VECT149_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT149_MSG_DATA', + 'regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT14_ADDR_HI', + 'regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT14_ADDR_LO', + 'regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT14_CONTROL', + 'regPCIEMSIX_VECT14_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT14_MSG_DATA', + 'regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT150_ADDR_HI', + 'regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT150_ADDR_LO', + 'regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT150_CONTROL', + 'regPCIEMSIX_VECT150_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT150_MSG_DATA', + 'regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT151_ADDR_HI', + 'regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT151_ADDR_LO', + 'regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT151_CONTROL', + 'regPCIEMSIX_VECT151_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT151_MSG_DATA', + 'regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT152_ADDR_HI', + 'regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT152_ADDR_LO', + 'regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT152_CONTROL', + 'regPCIEMSIX_VECT152_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT152_MSG_DATA', + 'regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT153_ADDR_HI', + 'regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT153_ADDR_LO', + 'regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT153_CONTROL', + 'regPCIEMSIX_VECT153_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT153_MSG_DATA', + 'regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT154_ADDR_HI', + 'regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT154_ADDR_LO', + 'regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT154_CONTROL', + 'regPCIEMSIX_VECT154_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT154_MSG_DATA', + 'regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT155_ADDR_HI', + 'regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT155_ADDR_LO', + 'regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT155_CONTROL', + 'regPCIEMSIX_VECT155_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT155_MSG_DATA', + 'regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT156_ADDR_HI', + 'regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT156_ADDR_LO', + 'regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT156_CONTROL', + 'regPCIEMSIX_VECT156_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT156_MSG_DATA', + 'regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT157_ADDR_HI', + 'regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT157_ADDR_LO', + 'regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT157_CONTROL', + 'regPCIEMSIX_VECT157_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT157_MSG_DATA', + 'regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT158_ADDR_HI', + 'regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT158_ADDR_LO', + 'regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT158_CONTROL', + 'regPCIEMSIX_VECT158_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT158_MSG_DATA', + 'regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT159_ADDR_HI', + 'regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT159_ADDR_LO', + 'regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT159_CONTROL', + 'regPCIEMSIX_VECT159_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT159_MSG_DATA', + 'regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT15_ADDR_HI', + 'regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT15_ADDR_LO', + 'regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT15_CONTROL', + 'regPCIEMSIX_VECT15_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT15_MSG_DATA', + 'regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT160_ADDR_HI', + 'regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT160_ADDR_LO', + 'regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT160_CONTROL', + 'regPCIEMSIX_VECT160_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT160_MSG_DATA', + 'regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT161_ADDR_HI', + 'regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT161_ADDR_LO', + 'regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT161_CONTROL', + 'regPCIEMSIX_VECT161_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT161_MSG_DATA', + 'regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT162_ADDR_HI', + 'regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT162_ADDR_LO', + 'regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT162_CONTROL', + 'regPCIEMSIX_VECT162_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT162_MSG_DATA', + 'regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT163_ADDR_HI', + 'regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT163_ADDR_LO', + 'regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT163_CONTROL', + 'regPCIEMSIX_VECT163_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT163_MSG_DATA', + 'regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT164_ADDR_HI', + 'regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT164_ADDR_LO', + 'regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT164_CONTROL', + 'regPCIEMSIX_VECT164_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT164_MSG_DATA', + 'regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT165_ADDR_HI', + 'regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT165_ADDR_LO', + 'regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT165_CONTROL', + 'regPCIEMSIX_VECT165_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT165_MSG_DATA', + 'regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT166_ADDR_HI', + 'regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT166_ADDR_LO', + 'regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT166_CONTROL', + 'regPCIEMSIX_VECT166_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT166_MSG_DATA', + 'regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT167_ADDR_HI', + 'regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT167_ADDR_LO', + 'regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT167_CONTROL', + 'regPCIEMSIX_VECT167_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT167_MSG_DATA', + 'regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT168_ADDR_HI', + 'regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT168_ADDR_LO', + 'regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT168_CONTROL', + 'regPCIEMSIX_VECT168_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT168_MSG_DATA', + 'regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT169_ADDR_HI', + 'regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT169_ADDR_LO', + 'regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT169_CONTROL', + 'regPCIEMSIX_VECT169_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT169_MSG_DATA', + 'regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT16_ADDR_HI', + 'regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT16_ADDR_LO', + 'regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT16_CONTROL', + 'regPCIEMSIX_VECT16_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT16_MSG_DATA', + 'regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT170_ADDR_HI', + 'regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT170_ADDR_LO', + 'regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT170_CONTROL', + 'regPCIEMSIX_VECT170_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT170_MSG_DATA', + 'regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT171_ADDR_HI', + 'regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT171_ADDR_LO', + 'regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT171_CONTROL', + 'regPCIEMSIX_VECT171_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT171_MSG_DATA', + 'regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT172_ADDR_HI', + 'regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT172_ADDR_LO', + 'regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT172_CONTROL', + 'regPCIEMSIX_VECT172_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT172_MSG_DATA', + 'regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT173_ADDR_HI', + 'regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT173_ADDR_LO', + 'regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT173_CONTROL', + 'regPCIEMSIX_VECT173_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT173_MSG_DATA', + 'regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT174_ADDR_HI', + 'regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT174_ADDR_LO', + 'regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT174_CONTROL', + 'regPCIEMSIX_VECT174_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT174_MSG_DATA', + 'regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT175_ADDR_HI', + 'regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT175_ADDR_LO', + 'regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT175_CONTROL', + 'regPCIEMSIX_VECT175_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT175_MSG_DATA', + 'regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT176_ADDR_HI', + 'regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT176_ADDR_LO', + 'regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT176_CONTROL', + 'regPCIEMSIX_VECT176_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT176_MSG_DATA', + 'regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT177_ADDR_HI', + 'regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT177_ADDR_LO', + 'regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT177_CONTROL', + 'regPCIEMSIX_VECT177_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT177_MSG_DATA', + 'regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT178_ADDR_HI', + 'regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT178_ADDR_LO', + 'regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT178_CONTROL', + 'regPCIEMSIX_VECT178_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT178_MSG_DATA', + 'regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT179_ADDR_HI', + 'regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT179_ADDR_LO', + 'regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT179_CONTROL', + 'regPCIEMSIX_VECT179_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT179_MSG_DATA', + 'regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT17_ADDR_HI', + 'regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT17_ADDR_LO', + 'regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT17_CONTROL', + 'regPCIEMSIX_VECT17_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT17_MSG_DATA', + 'regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT180_ADDR_HI', + 'regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT180_ADDR_LO', + 'regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT180_CONTROL', + 'regPCIEMSIX_VECT180_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT180_MSG_DATA', + 'regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT181_ADDR_HI', + 'regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT181_ADDR_LO', + 'regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT181_CONTROL', + 'regPCIEMSIX_VECT181_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT181_MSG_DATA', + 'regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT182_ADDR_HI', + 'regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT182_ADDR_LO', + 'regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT182_CONTROL', + 'regPCIEMSIX_VECT182_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT182_MSG_DATA', + 'regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT183_ADDR_HI', + 'regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT183_ADDR_LO', + 'regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT183_CONTROL', + 'regPCIEMSIX_VECT183_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT183_MSG_DATA', + 'regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT184_ADDR_HI', + 'regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT184_ADDR_LO', + 'regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT184_CONTROL', + 'regPCIEMSIX_VECT184_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT184_MSG_DATA', + 'regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT185_ADDR_HI', + 'regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT185_ADDR_LO', + 'regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT185_CONTROL', + 'regPCIEMSIX_VECT185_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT185_MSG_DATA', + 'regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT186_ADDR_HI', + 'regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT186_ADDR_LO', + 'regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT186_CONTROL', + 'regPCIEMSIX_VECT186_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT186_MSG_DATA', + 'regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT187_ADDR_HI', + 'regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT187_ADDR_LO', + 'regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT187_CONTROL', + 'regPCIEMSIX_VECT187_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT187_MSG_DATA', + 'regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT188_ADDR_HI', + 'regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT188_ADDR_LO', + 'regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT188_CONTROL', + 'regPCIEMSIX_VECT188_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT188_MSG_DATA', + 'regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT189_ADDR_HI', + 'regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT189_ADDR_LO', + 'regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT189_CONTROL', + 'regPCIEMSIX_VECT189_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT189_MSG_DATA', + 'regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT18_ADDR_HI', + 'regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT18_ADDR_LO', + 'regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT18_CONTROL', + 'regPCIEMSIX_VECT18_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT18_MSG_DATA', + 'regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT190_ADDR_HI', + 'regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT190_ADDR_LO', + 'regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT190_CONTROL', + 'regPCIEMSIX_VECT190_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT190_MSG_DATA', + 'regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT191_ADDR_HI', + 'regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT191_ADDR_LO', + 'regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT191_CONTROL', + 'regPCIEMSIX_VECT191_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT191_MSG_DATA', + 'regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT192_ADDR_HI', + 'regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT192_ADDR_LO', + 'regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT192_CONTROL', + 'regPCIEMSIX_VECT192_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT192_MSG_DATA', + 'regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT193_ADDR_HI', + 'regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT193_ADDR_LO', + 'regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT193_CONTROL', + 'regPCIEMSIX_VECT193_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT193_MSG_DATA', + 'regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT194_ADDR_HI', + 'regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT194_ADDR_LO', + 'regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT194_CONTROL', + 'regPCIEMSIX_VECT194_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT194_MSG_DATA', + 'regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT195_ADDR_HI', + 'regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT195_ADDR_LO', + 'regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT195_CONTROL', + 'regPCIEMSIX_VECT195_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT195_MSG_DATA', + 'regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT196_ADDR_HI', + 'regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT196_ADDR_LO', + 'regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT196_CONTROL', + 'regPCIEMSIX_VECT196_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT196_MSG_DATA', + 'regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT197_ADDR_HI', + 'regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT197_ADDR_LO', + 'regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT197_CONTROL', + 'regPCIEMSIX_VECT197_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT197_MSG_DATA', + 'regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT198_ADDR_HI', + 'regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT198_ADDR_LO', + 'regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT198_CONTROL', + 'regPCIEMSIX_VECT198_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT198_MSG_DATA', + 'regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT199_ADDR_HI', + 'regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT199_ADDR_LO', + 'regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT199_CONTROL', + 'regPCIEMSIX_VECT199_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT199_MSG_DATA', + 'regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT19_ADDR_HI', + 'regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT19_ADDR_LO', + 'regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT19_CONTROL', + 'regPCIEMSIX_VECT19_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT19_MSG_DATA', + 'regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT1_ADDR_HI', 'regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT1_ADDR_LO', 'regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT1_CONTROL', 'regPCIEMSIX_VECT1_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT1_MSG_DATA', + 'regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT200_ADDR_HI', + 'regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT200_ADDR_LO', + 'regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT200_CONTROL', + 'regPCIEMSIX_VECT200_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT200_MSG_DATA', + 'regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT201_ADDR_HI', + 'regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT201_ADDR_LO', + 'regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT201_CONTROL', + 'regPCIEMSIX_VECT201_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT201_MSG_DATA', + 'regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT202_ADDR_HI', + 'regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT202_ADDR_LO', + 'regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT202_CONTROL', + 'regPCIEMSIX_VECT202_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT202_MSG_DATA', + 'regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT203_ADDR_HI', + 'regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT203_ADDR_LO', + 'regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT203_CONTROL', + 'regPCIEMSIX_VECT203_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT203_MSG_DATA', + 'regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT204_ADDR_HI', + 'regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT204_ADDR_LO', + 'regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT204_CONTROL', + 'regPCIEMSIX_VECT204_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT204_MSG_DATA', + 'regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT205_ADDR_HI', + 'regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT205_ADDR_LO', + 'regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT205_CONTROL', + 'regPCIEMSIX_VECT205_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT205_MSG_DATA', + 'regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT206_ADDR_HI', + 'regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT206_ADDR_LO', + 'regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT206_CONTROL', + 'regPCIEMSIX_VECT206_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT206_MSG_DATA', + 'regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT207_ADDR_HI', + 'regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT207_ADDR_LO', + 'regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT207_CONTROL', + 'regPCIEMSIX_VECT207_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT207_MSG_DATA', + 'regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT208_ADDR_HI', + 'regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT208_ADDR_LO', + 'regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT208_CONTROL', + 'regPCIEMSIX_VECT208_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT208_MSG_DATA', + 'regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT209_ADDR_HI', + 'regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT209_ADDR_LO', + 'regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT209_CONTROL', + 'regPCIEMSIX_VECT209_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT209_MSG_DATA', + 'regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT20_ADDR_HI', + 'regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT20_ADDR_LO', + 'regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT20_CONTROL', + 'regPCIEMSIX_VECT20_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT20_MSG_DATA', + 'regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT210_ADDR_HI', + 'regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT210_ADDR_LO', + 'regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT210_CONTROL', + 'regPCIEMSIX_VECT210_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT210_MSG_DATA', + 'regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT211_ADDR_HI', + 'regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT211_ADDR_LO', + 'regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT211_CONTROL', + 'regPCIEMSIX_VECT211_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT211_MSG_DATA', + 'regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT212_ADDR_HI', + 'regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT212_ADDR_LO', + 'regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT212_CONTROL', + 'regPCIEMSIX_VECT212_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT212_MSG_DATA', + 'regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT213_ADDR_HI', + 'regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT213_ADDR_LO', + 'regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT213_CONTROL', + 'regPCIEMSIX_VECT213_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT213_MSG_DATA', + 'regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT214_ADDR_HI', + 'regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT214_ADDR_LO', + 'regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT214_CONTROL', + 'regPCIEMSIX_VECT214_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT214_MSG_DATA', + 'regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT215_ADDR_HI', + 'regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT215_ADDR_LO', + 'regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT215_CONTROL', + 'regPCIEMSIX_VECT215_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT215_MSG_DATA', + 'regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT216_ADDR_HI', + 'regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT216_ADDR_LO', + 'regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT216_CONTROL', + 'regPCIEMSIX_VECT216_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT216_MSG_DATA', + 'regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT217_ADDR_HI', + 'regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT217_ADDR_LO', + 'regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT217_CONTROL', + 'regPCIEMSIX_VECT217_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT217_MSG_DATA', + 'regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT218_ADDR_HI', + 'regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT218_ADDR_LO', + 'regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT218_CONTROL', + 'regPCIEMSIX_VECT218_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT218_MSG_DATA', + 'regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT219_ADDR_HI', + 'regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT219_ADDR_LO', + 'regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT219_CONTROL', + 'regPCIEMSIX_VECT219_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT219_MSG_DATA', + 'regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT21_ADDR_HI', + 'regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT21_ADDR_LO', + 'regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT21_CONTROL', + 'regPCIEMSIX_VECT21_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT21_MSG_DATA', + 'regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT220_ADDR_HI', + 'regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT220_ADDR_LO', + 'regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT220_CONTROL', + 'regPCIEMSIX_VECT220_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT220_MSG_DATA', + 'regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT221_ADDR_HI', + 'regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT221_ADDR_LO', + 'regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT221_CONTROL', + 'regPCIEMSIX_VECT221_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT221_MSG_DATA', + 'regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT222_ADDR_HI', + 'regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT222_ADDR_LO', + 'regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT222_CONTROL', + 'regPCIEMSIX_VECT222_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT222_MSG_DATA', + 'regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT223_ADDR_HI', + 'regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT223_ADDR_LO', + 'regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT223_CONTROL', + 'regPCIEMSIX_VECT223_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT223_MSG_DATA', + 'regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT224_ADDR_HI', + 'regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT224_ADDR_LO', + 'regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT224_CONTROL', + 'regPCIEMSIX_VECT224_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT224_MSG_DATA', + 'regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT225_ADDR_HI', + 'regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT225_ADDR_LO', + 'regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT225_CONTROL', + 'regPCIEMSIX_VECT225_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT225_MSG_DATA', + 'regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT226_ADDR_HI', + 'regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT226_ADDR_LO', + 'regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT226_CONTROL', + 'regPCIEMSIX_VECT226_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT226_MSG_DATA', + 'regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT227_ADDR_HI', + 'regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT227_ADDR_LO', + 'regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT227_CONTROL', + 'regPCIEMSIX_VECT227_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT227_MSG_DATA', + 'regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT228_ADDR_HI', + 'regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT228_ADDR_LO', + 'regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT228_CONTROL', + 'regPCIEMSIX_VECT228_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT228_MSG_DATA', + 'regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT229_ADDR_HI', + 'regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT229_ADDR_LO', + 'regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT229_CONTROL', + 'regPCIEMSIX_VECT229_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT229_MSG_DATA', + 'regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT22_ADDR_HI', + 'regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT22_ADDR_LO', + 'regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT22_CONTROL', + 'regPCIEMSIX_VECT22_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT22_MSG_DATA', + 'regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT230_ADDR_HI', + 'regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT230_ADDR_LO', + 'regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT230_CONTROL', + 'regPCIEMSIX_VECT230_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT230_MSG_DATA', + 'regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT231_ADDR_HI', + 'regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT231_ADDR_LO', + 'regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT231_CONTROL', + 'regPCIEMSIX_VECT231_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT231_MSG_DATA', + 'regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT232_ADDR_HI', + 'regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT232_ADDR_LO', + 'regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT232_CONTROL', + 'regPCIEMSIX_VECT232_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT232_MSG_DATA', + 'regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT233_ADDR_HI', + 'regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT233_ADDR_LO', + 'regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT233_CONTROL', + 'regPCIEMSIX_VECT233_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT233_MSG_DATA', + 'regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT234_ADDR_HI', + 'regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT234_ADDR_LO', + 'regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT234_CONTROL', + 'regPCIEMSIX_VECT234_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT234_MSG_DATA', + 'regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT235_ADDR_HI', + 'regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT235_ADDR_LO', + 'regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT235_CONTROL', + 'regPCIEMSIX_VECT235_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT235_MSG_DATA', + 'regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT236_ADDR_HI', + 'regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT236_ADDR_LO', + 'regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT236_CONTROL', + 'regPCIEMSIX_VECT236_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT236_MSG_DATA', + 'regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT237_ADDR_HI', + 'regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT237_ADDR_LO', + 'regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT237_CONTROL', + 'regPCIEMSIX_VECT237_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT237_MSG_DATA', + 'regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT238_ADDR_HI', + 'regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT238_ADDR_LO', + 'regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT238_CONTROL', + 'regPCIEMSIX_VECT238_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT238_MSG_DATA', + 'regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT239_ADDR_HI', + 'regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT239_ADDR_LO', + 'regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT239_CONTROL', + 'regPCIEMSIX_VECT239_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT239_MSG_DATA', + 'regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT23_ADDR_HI', + 'regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT23_ADDR_LO', + 'regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT23_CONTROL', + 'regPCIEMSIX_VECT23_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT23_MSG_DATA', + 'regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT240_ADDR_HI', + 'regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT240_ADDR_LO', + 'regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT240_CONTROL', + 'regPCIEMSIX_VECT240_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT240_MSG_DATA', + 'regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT241_ADDR_HI', + 'regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT241_ADDR_LO', + 'regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT241_CONTROL', + 'regPCIEMSIX_VECT241_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT241_MSG_DATA', + 'regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT242_ADDR_HI', + 'regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT242_ADDR_LO', + 'regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT242_CONTROL', + 'regPCIEMSIX_VECT242_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT242_MSG_DATA', + 'regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT243_ADDR_HI', + 'regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT243_ADDR_LO', + 'regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT243_CONTROL', + 'regPCIEMSIX_VECT243_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT243_MSG_DATA', + 'regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT244_ADDR_HI', + 'regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT244_ADDR_LO', + 'regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT244_CONTROL', + 'regPCIEMSIX_VECT244_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT244_MSG_DATA', + 'regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT245_ADDR_HI', + 'regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT245_ADDR_LO', + 'regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT245_CONTROL', + 'regPCIEMSIX_VECT245_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT245_MSG_DATA', + 'regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT246_ADDR_HI', + 'regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT246_ADDR_LO', + 'regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT246_CONTROL', + 'regPCIEMSIX_VECT246_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT246_MSG_DATA', + 'regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT247_ADDR_HI', + 'regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT247_ADDR_LO', + 'regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT247_CONTROL', + 'regPCIEMSIX_VECT247_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT247_MSG_DATA', + 'regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT248_ADDR_HI', + 'regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT248_ADDR_LO', + 'regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT248_CONTROL', + 'regPCIEMSIX_VECT248_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT248_MSG_DATA', + 'regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT249_ADDR_HI', + 'regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT249_ADDR_LO', + 'regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT249_CONTROL', + 'regPCIEMSIX_VECT249_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT249_MSG_DATA', + 'regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT24_ADDR_HI', + 'regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT24_ADDR_LO', + 'regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT24_CONTROL', + 'regPCIEMSIX_VECT24_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT24_MSG_DATA', + 'regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT250_ADDR_HI', + 'regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT250_ADDR_LO', + 'regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT250_CONTROL', + 'regPCIEMSIX_VECT250_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT250_MSG_DATA', + 'regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT251_ADDR_HI', + 'regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT251_ADDR_LO', + 'regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT251_CONTROL', + 'regPCIEMSIX_VECT251_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT251_MSG_DATA', + 'regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT252_ADDR_HI', + 'regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT252_ADDR_LO', + 'regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT252_CONTROL', + 'regPCIEMSIX_VECT252_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT252_MSG_DATA', + 'regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT253_ADDR_HI', + 'regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT253_ADDR_LO', + 'regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT253_CONTROL', + 'regPCIEMSIX_VECT253_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT253_MSG_DATA', + 'regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT254_ADDR_HI', + 'regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT254_ADDR_LO', + 'regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT254_CONTROL', + 'regPCIEMSIX_VECT254_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT254_MSG_DATA', + 'regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT255_ADDR_HI', + 'regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT255_ADDR_LO', + 'regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT255_CONTROL', + 'regPCIEMSIX_VECT255_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT255_MSG_DATA', + 'regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT25_ADDR_HI', + 'regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT25_ADDR_LO', + 'regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT25_CONTROL', + 'regPCIEMSIX_VECT25_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT25_MSG_DATA', + 'regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT26_ADDR_HI', + 'regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT26_ADDR_LO', + 'regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT26_CONTROL', + 'regPCIEMSIX_VECT26_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT26_MSG_DATA', + 'regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT27_ADDR_HI', + 'regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT27_ADDR_LO', + 'regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT27_CONTROL', + 'regPCIEMSIX_VECT27_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT27_MSG_DATA', + 'regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT28_ADDR_HI', + 'regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT28_ADDR_LO', + 'regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT28_CONTROL', + 'regPCIEMSIX_VECT28_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT28_MSG_DATA', + 'regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT29_ADDR_HI', + 'regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT29_ADDR_LO', + 'regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT29_CONTROL', + 'regPCIEMSIX_VECT29_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT29_MSG_DATA', + 'regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT2_ADDR_HI', 'regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT2_ADDR_LO', 'regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT2_CONTROL', 'regPCIEMSIX_VECT2_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT2_MSG_DATA', + 'regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT30_ADDR_HI', + 'regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT30_ADDR_LO', + 'regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT30_CONTROL', + 'regPCIEMSIX_VECT30_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT30_MSG_DATA', + 'regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT31_ADDR_HI', + 'regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT31_ADDR_LO', + 'regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT31_CONTROL', + 'regPCIEMSIX_VECT31_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT31_MSG_DATA', + 'regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT32_ADDR_HI', + 'regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT32_ADDR_LO', + 'regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT32_CONTROL', + 'regPCIEMSIX_VECT32_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT32_MSG_DATA', + 'regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT33_ADDR_HI', + 'regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT33_ADDR_LO', + 'regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT33_CONTROL', + 'regPCIEMSIX_VECT33_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT33_MSG_DATA', + 'regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT34_ADDR_HI', + 'regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT34_ADDR_LO', + 'regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT34_CONTROL', + 'regPCIEMSIX_VECT34_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT34_MSG_DATA', + 'regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT35_ADDR_HI', + 'regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT35_ADDR_LO', + 'regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT35_CONTROL', + 'regPCIEMSIX_VECT35_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT35_MSG_DATA', + 'regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT36_ADDR_HI', + 'regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT36_ADDR_LO', + 'regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT36_CONTROL', + 'regPCIEMSIX_VECT36_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT36_MSG_DATA', + 'regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT37_ADDR_HI', + 'regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT37_ADDR_LO', + 'regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT37_CONTROL', + 'regPCIEMSIX_VECT37_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT37_MSG_DATA', + 'regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT38_ADDR_HI', + 'regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT38_ADDR_LO', + 'regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT38_CONTROL', + 'regPCIEMSIX_VECT38_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT38_MSG_DATA', + 'regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT39_ADDR_HI', + 'regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT39_ADDR_LO', + 'regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT39_CONTROL', + 'regPCIEMSIX_VECT39_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT39_MSG_DATA', + 'regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT3_ADDR_HI', 'regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT3_ADDR_LO', 'regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT3_CONTROL', 'regPCIEMSIX_VECT3_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT3_MSG_DATA', + 'regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT40_ADDR_HI', + 'regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT40_ADDR_LO', + 'regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT40_CONTROL', + 'regPCIEMSIX_VECT40_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT40_MSG_DATA', + 'regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT41_ADDR_HI', + 'regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT41_ADDR_LO', + 'regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT41_CONTROL', + 'regPCIEMSIX_VECT41_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT41_MSG_DATA', + 'regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT42_ADDR_HI', + 'regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT42_ADDR_LO', + 'regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT42_CONTROL', + 'regPCIEMSIX_VECT42_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT42_MSG_DATA', + 'regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT43_ADDR_HI', + 'regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT43_ADDR_LO', + 'regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT43_CONTROL', + 'regPCIEMSIX_VECT43_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT43_MSG_DATA', + 'regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT44_ADDR_HI', + 'regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT44_ADDR_LO', + 'regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT44_CONTROL', + 'regPCIEMSIX_VECT44_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT44_MSG_DATA', + 'regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT45_ADDR_HI', + 'regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT45_ADDR_LO', + 'regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT45_CONTROL', + 'regPCIEMSIX_VECT45_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT45_MSG_DATA', + 'regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT46_ADDR_HI', + 'regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT46_ADDR_LO', + 'regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT46_CONTROL', + 'regPCIEMSIX_VECT46_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT46_MSG_DATA', + 'regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT47_ADDR_HI', + 'regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT47_ADDR_LO', + 'regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT47_CONTROL', + 'regPCIEMSIX_VECT47_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT47_MSG_DATA', + 'regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT48_ADDR_HI', + 'regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT48_ADDR_LO', + 'regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT48_CONTROL', + 'regPCIEMSIX_VECT48_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT48_MSG_DATA', + 'regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT49_ADDR_HI', + 'regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT49_ADDR_LO', + 'regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT49_CONTROL', + 'regPCIEMSIX_VECT49_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT49_MSG_DATA', + 'regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT4_ADDR_HI', 'regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT4_ADDR_LO', 'regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT4_CONTROL', 'regPCIEMSIX_VECT4_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT4_MSG_DATA', + 'regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT50_ADDR_HI', + 'regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT50_ADDR_LO', + 'regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT50_CONTROL', + 'regPCIEMSIX_VECT50_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT50_MSG_DATA', + 'regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT51_ADDR_HI', + 'regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT51_ADDR_LO', + 'regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT51_CONTROL', + 'regPCIEMSIX_VECT51_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT51_MSG_DATA', + 'regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT52_ADDR_HI', + 'regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT52_ADDR_LO', + 'regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT52_CONTROL', + 'regPCIEMSIX_VECT52_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT52_MSG_DATA', + 'regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT53_ADDR_HI', + 'regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT53_ADDR_LO', + 'regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT53_CONTROL', + 'regPCIEMSIX_VECT53_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT53_MSG_DATA', + 'regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT54_ADDR_HI', + 'regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT54_ADDR_LO', + 'regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT54_CONTROL', + 'regPCIEMSIX_VECT54_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT54_MSG_DATA', + 'regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT55_ADDR_HI', + 'regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT55_ADDR_LO', + 'regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT55_CONTROL', + 'regPCIEMSIX_VECT55_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT55_MSG_DATA', + 'regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT56_ADDR_HI', + 'regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT56_ADDR_LO', + 'regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT56_CONTROL', + 'regPCIEMSIX_VECT56_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT56_MSG_DATA', + 'regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT57_ADDR_HI', + 'regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT57_ADDR_LO', + 'regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT57_CONTROL', + 'regPCIEMSIX_VECT57_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT57_MSG_DATA', + 'regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT58_ADDR_HI', + 'regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT58_ADDR_LO', + 'regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT58_CONTROL', + 'regPCIEMSIX_VECT58_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT58_MSG_DATA', + 'regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT59_ADDR_HI', + 'regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT59_ADDR_LO', + 'regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT59_CONTROL', + 'regPCIEMSIX_VECT59_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT59_MSG_DATA', + 'regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT5_ADDR_HI', 'regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT5_ADDR_LO', 'regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT5_CONTROL', 'regPCIEMSIX_VECT5_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT5_MSG_DATA', + 'regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT60_ADDR_HI', + 'regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT60_ADDR_LO', + 'regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT60_CONTROL', + 'regPCIEMSIX_VECT60_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT60_MSG_DATA', + 'regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT61_ADDR_HI', + 'regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT61_ADDR_LO', + 'regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT61_CONTROL', + 'regPCIEMSIX_VECT61_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT61_MSG_DATA', + 'regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT62_ADDR_HI', + 'regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT62_ADDR_LO', + 'regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT62_CONTROL', + 'regPCIEMSIX_VECT62_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT62_MSG_DATA', + 'regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT63_ADDR_HI', + 'regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT63_ADDR_LO', + 'regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT63_CONTROL', + 'regPCIEMSIX_VECT63_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT63_MSG_DATA', + 'regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT64_ADDR_HI', + 'regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT64_ADDR_LO', + 'regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT64_CONTROL', + 'regPCIEMSIX_VECT64_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT64_MSG_DATA', + 'regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT65_ADDR_HI', + 'regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT65_ADDR_LO', + 'regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT65_CONTROL', + 'regPCIEMSIX_VECT65_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT65_MSG_DATA', + 'regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT66_ADDR_HI', + 'regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT66_ADDR_LO', + 'regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT66_CONTROL', + 'regPCIEMSIX_VECT66_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT66_MSG_DATA', + 'regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT67_ADDR_HI', + 'regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT67_ADDR_LO', + 'regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT67_CONTROL', + 'regPCIEMSIX_VECT67_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT67_MSG_DATA', + 'regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT68_ADDR_HI', + 'regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT68_ADDR_LO', + 'regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT68_CONTROL', + 'regPCIEMSIX_VECT68_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT68_MSG_DATA', + 'regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT69_ADDR_HI', + 'regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT69_ADDR_LO', + 'regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT69_CONTROL', + 'regPCIEMSIX_VECT69_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT69_MSG_DATA', + 'regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT6_ADDR_HI', 'regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT6_ADDR_LO', 'regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT6_CONTROL', 'regPCIEMSIX_VECT6_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT6_MSG_DATA', + 'regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT70_ADDR_HI', + 'regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT70_ADDR_LO', + 'regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT70_CONTROL', + 'regPCIEMSIX_VECT70_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT70_MSG_DATA', + 'regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT71_ADDR_HI', + 'regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT71_ADDR_LO', + 'regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT71_CONTROL', + 'regPCIEMSIX_VECT71_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT71_MSG_DATA', + 'regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT72_ADDR_HI', + 'regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT72_ADDR_LO', + 'regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT72_CONTROL', + 'regPCIEMSIX_VECT72_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT72_MSG_DATA', + 'regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT73_ADDR_HI', + 'regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT73_ADDR_LO', + 'regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT73_CONTROL', + 'regPCIEMSIX_VECT73_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT73_MSG_DATA', + 'regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT74_ADDR_HI', + 'regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT74_ADDR_LO', + 'regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT74_CONTROL', + 'regPCIEMSIX_VECT74_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT74_MSG_DATA', + 'regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT75_ADDR_HI', + 'regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT75_ADDR_LO', + 'regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT75_CONTROL', + 'regPCIEMSIX_VECT75_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT75_MSG_DATA', + 'regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT76_ADDR_HI', + 'regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT76_ADDR_LO', + 'regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT76_CONTROL', + 'regPCIEMSIX_VECT76_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT76_MSG_DATA', + 'regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT77_ADDR_HI', + 'regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT77_ADDR_LO', + 'regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT77_CONTROL', + 'regPCIEMSIX_VECT77_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT77_MSG_DATA', + 'regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT78_ADDR_HI', + 'regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT78_ADDR_LO', + 'regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT78_CONTROL', + 'regPCIEMSIX_VECT78_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT78_MSG_DATA', + 'regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT79_ADDR_HI', + 'regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT79_ADDR_LO', + 'regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT79_CONTROL', + 'regPCIEMSIX_VECT79_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT79_MSG_DATA', + 'regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT7_ADDR_HI', 'regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT7_ADDR_LO', 'regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT7_CONTROL', 'regPCIEMSIX_VECT7_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT7_MSG_DATA', + 'regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT80_ADDR_HI', + 'regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT80_ADDR_LO', + 'regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT80_CONTROL', + 'regPCIEMSIX_VECT80_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT80_MSG_DATA', + 'regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT81_ADDR_HI', + 'regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT81_ADDR_LO', + 'regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT81_CONTROL', + 'regPCIEMSIX_VECT81_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT81_MSG_DATA', + 'regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT82_ADDR_HI', + 'regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT82_ADDR_LO', + 'regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT82_CONTROL', + 'regPCIEMSIX_VECT82_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT82_MSG_DATA', + 'regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT83_ADDR_HI', + 'regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT83_ADDR_LO', + 'regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT83_CONTROL', + 'regPCIEMSIX_VECT83_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT83_MSG_DATA', + 'regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT84_ADDR_HI', + 'regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT84_ADDR_LO', + 'regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT84_CONTROL', + 'regPCIEMSIX_VECT84_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT84_MSG_DATA', + 'regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT85_ADDR_HI', + 'regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT85_ADDR_LO', + 'regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT85_CONTROL', + 'regPCIEMSIX_VECT85_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT85_MSG_DATA', + 'regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT86_ADDR_HI', + 'regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT86_ADDR_LO', + 'regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT86_CONTROL', + 'regPCIEMSIX_VECT86_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT86_MSG_DATA', + 'regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT87_ADDR_HI', + 'regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT87_ADDR_LO', + 'regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT87_CONTROL', + 'regPCIEMSIX_VECT87_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT87_MSG_DATA', + 'regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT88_ADDR_HI', + 'regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT88_ADDR_LO', + 'regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT88_CONTROL', + 'regPCIEMSIX_VECT88_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT88_MSG_DATA', + 'regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT89_ADDR_HI', + 'regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT89_ADDR_LO', + 'regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT89_CONTROL', + 'regPCIEMSIX_VECT89_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT89_MSG_DATA', + 'regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT8_ADDR_HI', 'regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT8_ADDR_LO', 'regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT8_CONTROL', 'regPCIEMSIX_VECT8_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT8_MSG_DATA', + 'regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT90_ADDR_HI', + 'regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT90_ADDR_LO', + 'regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT90_CONTROL', + 'regPCIEMSIX_VECT90_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT90_MSG_DATA', + 'regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT91_ADDR_HI', + 'regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT91_ADDR_LO', + 'regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT91_CONTROL', + 'regPCIEMSIX_VECT91_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT91_MSG_DATA', + 'regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT92_ADDR_HI', + 'regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT92_ADDR_LO', + 'regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT92_CONTROL', + 'regPCIEMSIX_VECT92_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT92_MSG_DATA', + 'regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT93_ADDR_HI', + 'regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT93_ADDR_LO', + 'regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT93_CONTROL', + 'regPCIEMSIX_VECT93_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT93_MSG_DATA', + 'regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT94_ADDR_HI', + 'regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT94_ADDR_LO', + 'regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT94_CONTROL', + 'regPCIEMSIX_VECT94_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT94_MSG_DATA', + 'regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT95_ADDR_HI', + 'regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT95_ADDR_LO', + 'regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT95_CONTROL', + 'regPCIEMSIX_VECT95_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT95_MSG_DATA', + 'regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT96_ADDR_HI', + 'regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT96_ADDR_LO', + 'regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT96_CONTROL', + 'regPCIEMSIX_VECT96_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT96_MSG_DATA', + 'regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT97_ADDR_HI', + 'regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT97_ADDR_LO', + 'regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT97_CONTROL', + 'regPCIEMSIX_VECT97_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT97_MSG_DATA', + 'regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT98_ADDR_HI', + 'regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT98_ADDR_LO', + 'regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT98_CONTROL', + 'regPCIEMSIX_VECT98_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT98_MSG_DATA', + 'regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT99_ADDR_HI', + 'regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT99_ADDR_LO', + 'regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT99_CONTROL', + 'regPCIEMSIX_VECT99_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT99_MSG_DATA', + 'regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT9_ADDR_HI', 'regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT9_ADDR_LO', 'regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT9_CONTROL', 'regPCIEMSIX_VECT9_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT9_MSG_DATA', + 'regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX', 'regPCIEP_BCH_ECC_CNTL', + 'regPCIEP_BCH_ECC_CNTL_BASE_IDX', + 'regPCIEP_ERROR_INJECT_PHYSICAL', + 'regPCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX', + 'regPCIEP_ERROR_INJECT_TRANSACTION', + 'regPCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX', + 'regPCIEP_NAK_COUNTER', 'regPCIEP_NAK_COUNTER_BASE_IDX', + 'regPCIEP_PORT_CNTL', 'regPCIEP_PORT_CNTL_BASE_IDX', + 'regPCIEP_RESERVED', 'regPCIEP_RESERVED_BASE_IDX', + 'regPCIEP_SCRATCH', 'regPCIEP_SCRATCH_BASE_IDX', + 'regPCIEP_STRAP_LC', 'regPCIEP_STRAP_LC2', + 'regPCIEP_STRAP_LC2_BASE_IDX', 'regPCIEP_STRAP_LC_BASE_IDX', + 'regPCIE_BUS_CNTL', 'regPCIE_BUS_CNTL_BASE_IDX', + 'regPCIE_CFG_CNTL', 'regPCIE_CFG_CNTL_BASE_IDX', + 'regPCIE_CI_CNTL', 'regPCIE_CI_CNTL_BASE_IDX', 'regPCIE_CNTL', + 'regPCIE_CNTL2', 'regPCIE_CNTL2_BASE_IDX', + 'regPCIE_CNTL_BASE_IDX', 'regPCIE_COMMON_AER_MASK', + 'regPCIE_COMMON_AER_MASK_BASE_IDX', 'regPCIE_CONFIG_CNTL', + 'regPCIE_CONFIG_CNTL_BASE_IDX', 'regPCIE_FC_CPL', + 'regPCIE_FC_CPL_BASE_IDX', 'regPCIE_FC_CPL_VC1', + 'regPCIE_FC_CPL_VC1_BASE_IDX', 'regPCIE_FC_NP', + 'regPCIE_FC_NP_BASE_IDX', 'regPCIE_FC_NP_VC1', + 'regPCIE_FC_NP_VC1_BASE_IDX', 'regPCIE_FC_P', + 'regPCIE_FC_P_BASE_IDX', 'regPCIE_FC_P_VC1', + 'regPCIE_FC_P_VC1_BASE_IDX', 'regPCIE_HIP_REG0', + 'regPCIE_HIP_REG0_BASE_IDX', 'regPCIE_HIP_REG1', + 'regPCIE_HIP_REG1_BASE_IDX', 'regPCIE_HIP_REG2', + 'regPCIE_HIP_REG2_BASE_IDX', 'regPCIE_HIP_REG3', + 'regPCIE_HIP_REG3_BASE_IDX', 'regPCIE_HIP_REG4', + 'regPCIE_HIP_REG4_BASE_IDX', 'regPCIE_HIP_REG5', + 'regPCIE_HIP_REG5_BASE_IDX', 'regPCIE_HIP_REG6', + 'regPCIE_HIP_REG6_BASE_IDX', 'regPCIE_HIP_REG7', + 'regPCIE_HIP_REG7_BASE_IDX', 'regPCIE_HIP_REG8', + 'regPCIE_HIP_REG8_BASE_IDX', 'regPCIE_I2C_REG_ADDR_EXPAND', + 'regPCIE_I2C_REG_ADDR_EXPAND_BASE_IDX', 'regPCIE_I2C_REG_DATA', + 'regPCIE_I2C_REG_DATA_BASE_IDX', 'regPCIE_LC_BEST_EQ_SETTINGS', + 'regPCIE_LC_BEST_EQ_SETTINGS_BASE_IDX', + 'regPCIE_LC_BW_CHANGE_CNTL', 'regPCIE_LC_BW_CHANGE_CNTL_BASE_IDX', + 'regPCIE_LC_CDR_CNTL', 'regPCIE_LC_CDR_CNTL_BASE_IDX', + 'regPCIE_LC_CNTL', 'regPCIE_LC_CNTL10', + 'regPCIE_LC_CNTL10_BASE_IDX', 'regPCIE_LC_CNTL11', + 'regPCIE_LC_CNTL11_BASE_IDX', 'regPCIE_LC_CNTL12', + 'regPCIE_LC_CNTL12_BASE_IDX', 'regPCIE_LC_CNTL3', + 'regPCIE_LC_CNTL3_BASE_IDX', 'regPCIE_LC_CNTL4', + 'regPCIE_LC_CNTL4_BASE_IDX', 'regPCIE_LC_CNTL5', + 'regPCIE_LC_CNTL5_BASE_IDX', 'regPCIE_LC_CNTL6', + 'regPCIE_LC_CNTL6_BASE_IDX', 'regPCIE_LC_CNTL7', + 'regPCIE_LC_CNTL7_BASE_IDX', 'regPCIE_LC_CNTL8', + 'regPCIE_LC_CNTL8_BASE_IDX', 'regPCIE_LC_CNTL9', + 'regPCIE_LC_CNTL9_BASE_IDX', 'regPCIE_LC_CNTL_BASE_IDX', + 'regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES', + 'regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX', + 'regPCIE_LC_FORCE_COEFF', 'regPCIE_LC_FORCE_COEFF2', + 'regPCIE_LC_FORCE_COEFF2_BASE_IDX', 'regPCIE_LC_FORCE_COEFF3', + 'regPCIE_LC_FORCE_COEFF3_BASE_IDX', + 'regPCIE_LC_FORCE_COEFF_BASE_IDX', + 'regPCIE_LC_FORCE_EQ_REQ_COEFF', 'regPCIE_LC_FORCE_EQ_REQ_COEFF2', + 'regPCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX', + 'regPCIE_LC_FORCE_EQ_REQ_COEFF3', + 'regPCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX', + 'regPCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX', + 'regPCIE_LC_L1_PM_SUBSTATE', 'regPCIE_LC_L1_PM_SUBSTATE2', + 'regPCIE_LC_L1_PM_SUBSTATE2_BASE_IDX', + 'regPCIE_LC_L1_PM_SUBSTATE3', + 'regPCIE_LC_L1_PM_SUBSTATE3_BASE_IDX', + 'regPCIE_LC_L1_PM_SUBSTATE4', + 'regPCIE_LC_L1_PM_SUBSTATE4_BASE_IDX', + 'regPCIE_LC_L1_PM_SUBSTATE5', + 'regPCIE_LC_L1_PM_SUBSTATE5_BASE_IDX', + 'regPCIE_LC_L1_PM_SUBSTATE_BASE_IDX', 'regPCIE_LC_LANE_CNTL', + 'regPCIE_LC_LANE_CNTL_BASE_IDX', 'regPCIE_LC_LINK_WIDTH_CNTL', + 'regPCIE_LC_LINK_WIDTH_CNTL_BASE_IDX', 'regPCIE_LC_N_FTS_CNTL', + 'regPCIE_LC_N_FTS_CNTL_BASE_IDX', 'regPCIE_LC_PM_CNTL', + 'regPCIE_LC_PM_CNTL2', 'regPCIE_LC_PM_CNTL2_BASE_IDX', + 'regPCIE_LC_PM_CNTL_BASE_IDX', + 'regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL', + 'regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX', + 'regPCIE_LC_SAVE_RESTORE_1', 'regPCIE_LC_SAVE_RESTORE_1_BASE_IDX', + 'regPCIE_LC_SAVE_RESTORE_2', 'regPCIE_LC_SAVE_RESTORE_2_BASE_IDX', + 'regPCIE_LC_SPEED_CNTL2', 'regPCIE_LC_SPEED_CNTL2_BASE_IDX', + 'regPCIE_LC_STATE0', 'regPCIE_LC_STATE0_BASE_IDX', + 'regPCIE_LC_STATE1', 'regPCIE_LC_STATE10', + 'regPCIE_LC_STATE10_BASE_IDX', 'regPCIE_LC_STATE11', + 'regPCIE_LC_STATE11_BASE_IDX', 'regPCIE_LC_STATE1_BASE_IDX', + 'regPCIE_LC_STATE2', 'regPCIE_LC_STATE2_BASE_IDX', + 'regPCIE_LC_STATE3', 'regPCIE_LC_STATE3_BASE_IDX', + 'regPCIE_LC_STATE4', 'regPCIE_LC_STATE4_BASE_IDX', + 'regPCIE_LC_STATE5', 'regPCIE_LC_STATE5_BASE_IDX', + 'regPCIE_LC_STATE6', 'regPCIE_LC_STATE6_BASE_IDX', + 'regPCIE_LC_STATE7', 'regPCIE_LC_STATE7_BASE_IDX', + 'regPCIE_LC_STATE8', 'regPCIE_LC_STATE8_BASE_IDX', + 'regPCIE_LC_STATE9', 'regPCIE_LC_STATE9_BASE_IDX', + 'regPCIE_LC_STATUS1', 'regPCIE_LC_STATUS1_BASE_IDX', + 'regPCIE_LC_STATUS2', 'regPCIE_LC_STATUS2_BASE_IDX', + 'regPCIE_LC_TRAINING_CNTL', 'regPCIE_LC_TRAINING_CNTL_BASE_IDX', + 'regPCIE_MST_CTRL_1', 'regPCIE_MST_CTRL_1_BASE_IDX', + 'regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL', + 'regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX', + 'regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL', + 'regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX', + 'regPCIE_PERF_CNTL_TXCLK1', 'regPCIE_PERF_CNTL_TXCLK10', + 'regPCIE_PERF_CNTL_TXCLK10_BASE_IDX', + 'regPCIE_PERF_CNTL_TXCLK1_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK2', + 'regPCIE_PERF_CNTL_TXCLK2_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK3', + 'regPCIE_PERF_CNTL_TXCLK3_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK4', + 'regPCIE_PERF_CNTL_TXCLK4_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK5', + 'regPCIE_PERF_CNTL_TXCLK5_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK6', + 'regPCIE_PERF_CNTL_TXCLK6_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK7', + 'regPCIE_PERF_CNTL_TXCLK7_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK8', + 'regPCIE_PERF_CNTL_TXCLK8_BASE_IDX', 'regPCIE_PERF_CNTL_TXCLK9', + 'regPCIE_PERF_CNTL_TXCLK9_BASE_IDX', 'regPCIE_PERF_COUNT0_TXCLK1', + 'regPCIE_PERF_COUNT0_TXCLK10', + 'regPCIE_PERF_COUNT0_TXCLK10_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK1_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK2', + 'regPCIE_PERF_COUNT0_TXCLK2_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK3', + 'regPCIE_PERF_COUNT0_TXCLK3_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK4', + 'regPCIE_PERF_COUNT0_TXCLK4_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK5', + 'regPCIE_PERF_COUNT0_TXCLK5_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK6', + 'regPCIE_PERF_COUNT0_TXCLK6_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK7', + 'regPCIE_PERF_COUNT0_TXCLK7_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK8', + 'regPCIE_PERF_COUNT0_TXCLK8_BASE_IDX', + 'regPCIE_PERF_COUNT0_TXCLK9', + 'regPCIE_PERF_COUNT0_TXCLK9_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK1', 'regPCIE_PERF_COUNT1_TXCLK10', + 'regPCIE_PERF_COUNT1_TXCLK10_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK1_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK2', + 'regPCIE_PERF_COUNT1_TXCLK2_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK3', + 'regPCIE_PERF_COUNT1_TXCLK3_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK4', + 'regPCIE_PERF_COUNT1_TXCLK4_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK5', + 'regPCIE_PERF_COUNT1_TXCLK5_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK6', + 'regPCIE_PERF_COUNT1_TXCLK6_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK7', + 'regPCIE_PERF_COUNT1_TXCLK7_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK8', + 'regPCIE_PERF_COUNT1_TXCLK8_BASE_IDX', + 'regPCIE_PERF_COUNT1_TXCLK9', + 'regPCIE_PERF_COUNT1_TXCLK9_BASE_IDX', 'regPCIE_PERF_COUNT_CNTL', + 'regPCIE_PERF_COUNT_CNTL_BASE_IDX', 'regPCIE_PGMST_CNTL', + 'regPCIE_PGMST_CNTL_BASE_IDX', 'regPCIE_PGSLV_CNTL', + 'regPCIE_PGSLV_CNTL_BASE_IDX', 'regPCIE_PRBS_CLR', + 'regPCIE_PRBS_CLR_BASE_IDX', 'regPCIE_PRBS_ERRCNT_0', + 'regPCIE_PRBS_ERRCNT_0_BASE_IDX', 'regPCIE_PRBS_ERRCNT_1', + 'regPCIE_PRBS_ERRCNT_10', 'regPCIE_PRBS_ERRCNT_10_BASE_IDX', + 'regPCIE_PRBS_ERRCNT_11', 'regPCIE_PRBS_ERRCNT_11_BASE_IDX', + 'regPCIE_PRBS_ERRCNT_12', 'regPCIE_PRBS_ERRCNT_12_BASE_IDX', + 'regPCIE_PRBS_ERRCNT_13', 'regPCIE_PRBS_ERRCNT_13_BASE_IDX', + 'regPCIE_PRBS_ERRCNT_14', 'regPCIE_PRBS_ERRCNT_14_BASE_IDX', + 'regPCIE_PRBS_ERRCNT_15', 'regPCIE_PRBS_ERRCNT_15_BASE_IDX', + 'regPCIE_PRBS_ERRCNT_1_BASE_IDX', 'regPCIE_PRBS_ERRCNT_2', + 'regPCIE_PRBS_ERRCNT_2_BASE_IDX', 'regPCIE_PRBS_ERRCNT_3', + 'regPCIE_PRBS_ERRCNT_3_BASE_IDX', 'regPCIE_PRBS_ERRCNT_4', + 'regPCIE_PRBS_ERRCNT_4_BASE_IDX', 'regPCIE_PRBS_ERRCNT_5', + 'regPCIE_PRBS_ERRCNT_5_BASE_IDX', 'regPCIE_PRBS_ERRCNT_6', + 'regPCIE_PRBS_ERRCNT_6_BASE_IDX', 'regPCIE_PRBS_ERRCNT_7', + 'regPCIE_PRBS_ERRCNT_7_BASE_IDX', 'regPCIE_PRBS_ERRCNT_8', + 'regPCIE_PRBS_ERRCNT_8_BASE_IDX', 'regPCIE_PRBS_ERRCNT_9', + 'regPCIE_PRBS_ERRCNT_9_BASE_IDX', 'regPCIE_PRBS_FREERUN', + 'regPCIE_PRBS_FREERUN_BASE_IDX', 'regPCIE_PRBS_HI_BITCNT', + 'regPCIE_PRBS_HI_BITCNT_BASE_IDX', 'regPCIE_PRBS_LO_BITCNT', + 'regPCIE_PRBS_LO_BITCNT_BASE_IDX', 'regPCIE_PRBS_MISC', + 'regPCIE_PRBS_MISC_BASE_IDX', 'regPCIE_PRBS_STATUS1', + 'regPCIE_PRBS_STATUS1_BASE_IDX', 'regPCIE_PRBS_STATUS2', + 'regPCIE_PRBS_STATUS2_BASE_IDX', 'regPCIE_PRBS_USER_PATTERN', + 'regPCIE_PRBS_USER_PATTERN_BASE_IDX', 'regPCIE_P_BUF_STATUS', + 'regPCIE_P_BUF_STATUS_BASE_IDX', 'regPCIE_P_CNTL', + 'regPCIE_P_CNTL_BASE_IDX', 'regPCIE_P_DECODER_STATUS', + 'regPCIE_P_DECODER_STATUS_BASE_IDX', 'regPCIE_P_MISC_STATUS', + 'regPCIE_P_MISC_STATUS_BASE_IDX', 'regPCIE_P_PORT_LANE_STATUS', + 'regPCIE_P_PORT_LANE_STATUS_BASE_IDX', + 'regPCIE_P_RCV_L0S_FTS_DET', 'regPCIE_P_RCV_L0S_FTS_DET_BASE_IDX', + 'regPCIE_RESERVED', 'regPCIE_RESERVED_BASE_IDX', + 'regPCIE_RXMARGIN_1_SETTINGS', + 'regPCIE_RXMARGIN_1_SETTINGS_BASE_IDX', + 'regPCIE_RXMARGIN_2_SETTINGS', + 'regPCIE_RXMARGIN_2_SETTINGS_BASE_IDX', + 'regPCIE_RXMARGIN_CONTROL_CAPABILITIES', + 'regPCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX', 'regPCIE_RX_AD', + 'regPCIE_RX_AD_BASE_IDX', 'regPCIE_RX_CNTL2', + 'regPCIE_RX_CNTL2_BASE_IDX', 'regPCIE_RX_CNTL3', + 'regPCIE_RX_CNTL3_BASE_IDX', 'regPCIE_RX_CNTL4', + 'regPCIE_RX_CNTL4_BASE_IDX', 'regPCIE_RX_CNTL5', + 'regPCIE_RX_CNTL5_BASE_IDX', 'regPCIE_RX_CREDITS_ALLOCATED_CPL', + 'regPCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX', + 'regPCIE_RX_CREDITS_ALLOCATED_NP', + 'regPCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX', + 'regPCIE_RX_CREDITS_ALLOCATED_P', + 'regPCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX', + 'regPCIE_RX_EXPECTED_SEQNUM', + 'regPCIE_RX_EXPECTED_SEQNUM_BASE_IDX', 'regPCIE_RX_LAST_TLP0', + 'regPCIE_RX_LAST_TLP0_BASE_IDX', 'regPCIE_RX_LAST_TLP1', + 'regPCIE_RX_LAST_TLP1_BASE_IDX', 'regPCIE_RX_LAST_TLP2', + 'regPCIE_RX_LAST_TLP2_BASE_IDX', 'regPCIE_RX_LAST_TLP3', + 'regPCIE_RX_LAST_TLP3_BASE_IDX', 'regPCIE_RX_NUM_NAK', + 'regPCIE_RX_NUM_NAK_BASE_IDX', 'regPCIE_RX_NUM_NAK_GENERATED', + 'regPCIE_RX_NUM_NAK_GENERATED_BASE_IDX', + 'regPCIE_RX_VENDOR_SPECIFIC', + 'regPCIE_RX_VENDOR_SPECIFIC_BASE_IDX', 'regPCIE_SCRATCH', + 'regPCIE_SCRATCH_BASE_IDX', 'regPCIE_SDP_CTRL', + 'regPCIE_SDP_CTRL2', 'regPCIE_SDP_CTRL2_BASE_IDX', + 'regPCIE_SDP_CTRL_BASE_IDX', 'regPCIE_SDP_SWUS_SLV_ATTR_CTRL', + 'regPCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX', 'regPCIE_STRAP_F0', + 'regPCIE_STRAP_F0_BASE_IDX', 'regPCIE_STRAP_I2C_BD', + 'regPCIE_STRAP_I2C_BD_BASE_IDX', 'regPCIE_STRAP_MISC', + 'regPCIE_STRAP_MISC2', 'regPCIE_STRAP_MISC2_BASE_IDX', + 'regPCIE_STRAP_MISC_BASE_IDX', 'regPCIE_STRAP_PI', + 'regPCIE_STRAP_PI_BASE_IDX', 'regPCIE_TX_ACK_LATENCY_LIMIT', + 'regPCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX', + 'regPCIE_TX_CREDITS_ADVT_CPL', + 'regPCIE_TX_CREDITS_ADVT_CPL_BASE_IDX', + 'regPCIE_TX_CREDITS_ADVT_NP', + 'regPCIE_TX_CREDITS_ADVT_NP_BASE_IDX', + 'regPCIE_TX_CREDITS_ADVT_P', 'regPCIE_TX_CREDITS_ADVT_P_BASE_IDX', + 'regPCIE_TX_CREDITS_FCU_THRESHOLD', + 'regPCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX', + 'regPCIE_TX_CREDITS_INIT_CPL', + 'regPCIE_TX_CREDITS_INIT_CPL_BASE_IDX', + 'regPCIE_TX_CREDITS_INIT_NP', + 'regPCIE_TX_CREDITS_INIT_NP_BASE_IDX', + 'regPCIE_TX_CREDITS_INIT_P', 'regPCIE_TX_CREDITS_INIT_P_BASE_IDX', + 'regPCIE_TX_CREDITS_STATUS', 'regPCIE_TX_CREDITS_STATUS_BASE_IDX', + 'regPCIE_TX_CTRL_4', 'regPCIE_TX_CTRL_4_BASE_IDX', + 'regPCIE_TX_F0_ATTR_CNTL', 'regPCIE_TX_F0_ATTR_CNTL_BASE_IDX', + 'regPCIE_TX_LAST_TLP0', 'regPCIE_TX_LAST_TLP0_BASE_IDX', + 'regPCIE_TX_LAST_TLP1', 'regPCIE_TX_LAST_TLP1_BASE_IDX', + 'regPCIE_TX_LAST_TLP2', 'regPCIE_TX_LAST_TLP2_BASE_IDX', + 'regPCIE_TX_LAST_TLP3', 'regPCIE_TX_LAST_TLP3_BASE_IDX', + 'regPCIE_TX_NOP_DLLP', 'regPCIE_TX_NOP_DLLP_BASE_IDX', + 'regPCIE_TX_REPLAY', 'regPCIE_TX_REPLAY_BASE_IDX', + 'regPCIE_TX_REQUESTER_ID', 'regPCIE_TX_REQUESTER_ID_BASE_IDX', + 'regPCIE_TX_REQUEST_NUM_CNTL', + 'regPCIE_TX_REQUEST_NUM_CNTL_BASE_IDX', 'regPCIE_TX_SEQ', + 'regPCIE_TX_SEQ_BASE_IDX', 'regPCIE_TX_STATUS', + 'regPCIE_TX_STATUS_BASE_IDX', 'regPCIE_TX_SWUS_ATTR_CNTL', + 'regPCIE_TX_SWUS_ATTR_CNTL_BASE_IDX', + 'regPCIE_TX_TRACKING_ADDR_HI', + 'regPCIE_TX_TRACKING_ADDR_HI_BASE_IDX', + 'regPCIE_TX_TRACKING_ADDR_LO', + 'regPCIE_TX_TRACKING_ADDR_LO_BASE_IDX', + 'regPCIE_TX_TRACKING_CTRL_STATUS', + 'regPCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX', + 'regPCIE_TX_VENDOR_SPECIFIC', + 'regPCIE_TX_VENDOR_SPECIFIC_BASE_IDX', 'regPCIE_WPR_CNTL', + 'regPCIE_WPR_CNTL_BASE_IDX', 'regPSWUSCFG0_IO_BASE_LIMIT', + 'regPSWUSCFG0_IO_BASE_LIMIT_BASE_IDX', + 'regPSWUSCFG0_IO_BASE_LIMIT_HI', + 'regPSWUSCFG0_IO_BASE_LIMIT_HI_BASE_IDX', + 'regPSWUSCFG0_MEM_BASE_LIMIT', + 'regPSWUSCFG0_MEM_BASE_LIMIT_BASE_IDX', + 'regPSWUSCFG0_PREF_BASE_LIMIT', + 'regPSWUSCFG0_PREF_BASE_LIMIT_BASE_IDX', + 'regPSWUSCFG0_PREF_BASE_UPPER', + 'regPSWUSCFG0_PREF_BASE_UPPER_BASE_IDX', + 'regPSWUSCFG0_PREF_LIMIT_UPPER', + 'regPSWUSCFG0_PREF_LIMIT_UPPER_BASE_IDX', + 'regPSWUSCFG0_SECONDARY_STATUS', + 'regPSWUSCFG0_SECONDARY_STATUS_BASE_IDX', 'regPSWUSCFG0_SSID_CAP', + 'regPSWUSCFG0_SSID_CAP_BASE_IDX', 'regPSWUSCFG0_SSID_CAP_LIST', + 'regPSWUSCFG0_SSID_CAP_LIST_BASE_IDX', + 'regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY', + 'regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_BASE_IDX', + 'regPSWUSP0_PCIEP_STRAP_MISC', + 'regPSWUSP0_PCIEP_STRAP_MISC_BASE_IDX', + 'regPSWUSP0_PCIE_ERR_CNTL', 'regPSWUSP0_PCIE_ERR_CNTL_BASE_IDX', + 'regPSWUSP0_PCIE_LC_CNTL2', 'regPSWUSP0_PCIE_LC_CNTL2_BASE_IDX', + 'regPSWUSP0_PCIE_LC_SPEED_CNTL', + 'regPSWUSP0_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regPSWUSP0_PCIE_RX_CNTL', 'regPSWUSP0_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_BACO_CNTL_MISC', + 'regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL1', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL2', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST0', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST1', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUS_CNTL', + 'regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM', + 'regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_0_RCC_CMN_LINK_CNTL', + 'regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_APER_SIZE', + 'regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_CNTL', + 'regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_F0_BASE', + 'regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE', + 'regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX', + 'regRCC_DEV0_0_RCC_DEV0_LINK_CNTL', + 'regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE', + 'regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX', + 'regRCC_DEV0_0_RCC_ERR_INT_CNTL', + 'regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC', + 'regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX', + 'regRCC_DEV0_0_RCC_GPUIOV_REGION', + 'regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX', + 'regRCC_DEV0_0_RCC_GPU_HOSTVM_EN', + 'regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX', + 'regRCC_DEV0_0_RCC_HOST_BUSNUM', + 'regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL', + 'regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX', + 'regRCC_DEV0_0_RCC_MH_ARB_CNTL', + 'regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE0', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE1', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX', + 'regRCC_DEV0_0_RCC_RESET_EN', + 'regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX', + 'regRCC_DEV0_0_RCC_VDM_SUPPORT', + 'regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX', + 'regRCC_DEV0_0_RCC_XDMA_HI', 'regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_XDMA_LO', 'regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_BACO_CNTL_MISC', + 'regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL1', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL2', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST0', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST1', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUS_CNTL', + 'regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM', + 'regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_1_RCC_CMN_LINK_CNTL', + 'regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_APER_SIZE', + 'regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_CNTL', + 'regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_F0_BASE', + 'regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE', + 'regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX', + 'regRCC_DEV0_1_RCC_DEV0_LINK_CNTL', + 'regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE', + 'regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX', + 'regRCC_DEV0_1_RCC_ERR_INT_CNTL', + 'regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC', + 'regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX', + 'regRCC_DEV0_1_RCC_GPUIOV_REGION', + 'regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX', + 'regRCC_DEV0_1_RCC_GPU_HOSTVM_EN', + 'regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX', + 'regRCC_DEV0_1_RCC_HOST_BUSNUM', + 'regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL', + 'regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX', + 'regRCC_DEV0_1_RCC_MH_ARB_CNTL', + 'regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE0', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE1', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX', + 'regRCC_DEV0_1_RCC_RESET_EN', + 'regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX', + 'regRCC_DEV0_1_RCC_VDM_SUPPORT', + 'regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX', + 'regRCC_DEV0_1_RCC_XDMA_HI', 'regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_XDMA_LO', 'regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX', + 'regRCC_DEV0_2_RCC_BUS_CNTL', + 'regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_CMN_LINK_CNTL', + 'regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_DEV0_LINK_CNTL', + 'regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE', + 'regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX', + 'regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC', + 'regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX', + 'regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL', + 'regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX', + 'regRCC_DEV0_2_RCC_MH_ARB_CNTL', + 'regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_VDM_SUPPORT', + 'regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP0', 'regRCC_DEV0_EPF2_STRAP0_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP10', 'regRCC_DEV0_EPF2_STRAP10_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP11', 'regRCC_DEV0_EPF2_STRAP11_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP12', 'regRCC_DEV0_EPF2_STRAP12_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP13', 'regRCC_DEV0_EPF2_STRAP13_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP14', 'regRCC_DEV0_EPF2_STRAP14_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP2', 'regRCC_DEV0_EPF2_STRAP20', + 'regRCC_DEV0_EPF2_STRAP20_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP3', + 'regRCC_DEV0_EPF2_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP4', + 'regRCC_DEV0_EPF2_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP5', + 'regRCC_DEV0_EPF2_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP6', + 'regRCC_DEV0_EPF2_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP7', + 'regRCC_DEV0_EPF2_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP0', + 'regRCC_DEV0_EPF3_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP10', + 'regRCC_DEV0_EPF3_STRAP10_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP11', + 'regRCC_DEV0_EPF3_STRAP11_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP12', + 'regRCC_DEV0_EPF3_STRAP12_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP13', + 'regRCC_DEV0_EPF3_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP14', + 'regRCC_DEV0_EPF3_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP2', + 'regRCC_DEV0_EPF3_STRAP20', 'regRCC_DEV0_EPF3_STRAP20_BASE_IDX', + 'regRCC_DEV0_EPF3_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP3', + 'regRCC_DEV0_EPF3_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP4', + 'regRCC_DEV0_EPF3_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP5', + 'regRCC_DEV0_EPF3_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP6', + 'regRCC_DEV0_EPF3_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP7', + 'regRCC_DEV0_EPF3_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP0', + 'regRCC_DEV0_EPF4_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP13', + 'regRCC_DEV0_EPF4_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP14', + 'regRCC_DEV0_EPF4_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP2', + 'regRCC_DEV0_EPF4_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP3', + 'regRCC_DEV0_EPF4_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP4', + 'regRCC_DEV0_EPF4_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP5', + 'regRCC_DEV0_EPF4_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP6', + 'regRCC_DEV0_EPF4_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP7', + 'regRCC_DEV0_EPF4_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP0', + 'regRCC_DEV0_EPF5_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP13', + 'regRCC_DEV0_EPF5_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP14', + 'regRCC_DEV0_EPF5_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP2', + 'regRCC_DEV0_EPF5_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP3', + 'regRCC_DEV0_EPF5_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP4', + 'regRCC_DEV0_EPF5_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP5', + 'regRCC_DEV0_EPF5_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP6', + 'regRCC_DEV0_EPF5_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP7', + 'regRCC_DEV0_EPF5_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP0', + 'regRCC_DEV0_EPF6_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP13', + 'regRCC_DEV0_EPF6_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP14', + 'regRCC_DEV0_EPF6_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP2', + 'regRCC_DEV0_EPF6_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP3', + 'regRCC_DEV0_EPF6_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP4', + 'regRCC_DEV0_EPF6_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP5', + 'regRCC_DEV0_EPF6_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP6', + 'regRCC_DEV0_EPF6_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP0', + 'regRCC_DEV0_EPF7_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP13', + 'regRCC_DEV0_EPF7_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP14', + 'regRCC_DEV0_EPF7_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP2', + 'regRCC_DEV0_EPF7_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP3', + 'regRCC_DEV0_EPF7_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP4', + 'regRCC_DEV0_EPF7_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP5', + 'regRCC_DEV0_EPF7_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP6', + 'regRCC_DEV0_EPF7_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP7', + 'regRCC_DEV0_EPF7_STRAP7_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP0', + 'regRCC_DEV1_EPF0_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP13', + 'regRCC_DEV1_EPF0_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP14', + 'regRCC_DEV1_EPF0_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP2', + 'regRCC_DEV1_EPF0_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP3', + 'regRCC_DEV1_EPF0_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP4', + 'regRCC_DEV1_EPF0_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP5', + 'regRCC_DEV1_EPF0_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP6', + 'regRCC_DEV1_EPF0_STRAP6_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP7', + 'regRCC_DEV1_EPF0_STRAP7_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP0', + 'regRCC_DEV1_EPF1_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP13', + 'regRCC_DEV1_EPF1_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP14', + 'regRCC_DEV1_EPF1_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP2', + 'regRCC_DEV1_EPF1_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP3', + 'regRCC_DEV1_EPF1_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP4', + 'regRCC_DEV1_EPF1_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP5', + 'regRCC_DEV1_EPF1_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP6', + 'regRCC_DEV1_EPF1_STRAP6_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP7', + 'regRCC_DEV1_EPF1_STRAP7_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP0', + 'regRCC_DEV1_EPF2_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP13', + 'regRCC_DEV1_EPF2_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP14', + 'regRCC_DEV1_EPF2_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP2', + 'regRCC_DEV1_EPF2_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP3', + 'regRCC_DEV1_EPF2_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP4', + 'regRCC_DEV1_EPF2_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP5', + 'regRCC_DEV1_EPF2_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF2_STRAP6', + 'regRCC_DEV1_EPF2_STRAP6_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP0', + 'regRCC_DEV1_EPF3_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP13', + 'regRCC_DEV1_EPF3_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP14', + 'regRCC_DEV1_EPF3_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP2', + 'regRCC_DEV1_EPF3_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP3', + 'regRCC_DEV1_EPF3_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP4', + 'regRCC_DEV1_EPF3_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP5', + 'regRCC_DEV1_EPF3_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF3_STRAP6', + 'regRCC_DEV1_EPF3_STRAP6_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP0', + 'regRCC_DEV1_EPF4_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP13', + 'regRCC_DEV1_EPF4_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP14', + 'regRCC_DEV1_EPF4_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP2', + 'regRCC_DEV1_EPF4_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP3', + 'regRCC_DEV1_EPF4_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP4', + 'regRCC_DEV1_EPF4_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP5', + 'regRCC_DEV1_EPF4_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF4_STRAP6', + 'regRCC_DEV1_EPF4_STRAP6_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP0', + 'regRCC_DEV1_EPF5_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP13', + 'regRCC_DEV1_EPF5_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP14', + 'regRCC_DEV1_EPF5_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP2', + 'regRCC_DEV1_EPF5_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP3', + 'regRCC_DEV1_EPF5_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP4', + 'regRCC_DEV1_EPF5_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP5', + 'regRCC_DEV1_EPF5_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF5_STRAP6', + 'regRCC_DEV1_EPF5_STRAP6_BASE_IDX', 'regRCC_DEV1_PORT_STRAP0', + 'regRCC_DEV1_PORT_STRAP0_BASE_IDX', 'regRCC_DEV1_PORT_STRAP1', + 'regRCC_DEV1_PORT_STRAP10', 'regRCC_DEV1_PORT_STRAP10_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP11', 'regRCC_DEV1_PORT_STRAP11_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP12', 'regRCC_DEV1_PORT_STRAP12_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP13', 'regRCC_DEV1_PORT_STRAP13_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP14', 'regRCC_DEV1_PORT_STRAP14_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP1_BASE_IDX', 'regRCC_DEV1_PORT_STRAP2', + 'regRCC_DEV1_PORT_STRAP2_BASE_IDX', 'regRCC_DEV1_PORT_STRAP3', + 'regRCC_DEV1_PORT_STRAP3_BASE_IDX', 'regRCC_DEV1_PORT_STRAP4', + 'regRCC_DEV1_PORT_STRAP4_BASE_IDX', 'regRCC_DEV1_PORT_STRAP5', + 'regRCC_DEV1_PORT_STRAP5_BASE_IDX', 'regRCC_DEV1_PORT_STRAP6', + 'regRCC_DEV1_PORT_STRAP6_BASE_IDX', 'regRCC_DEV1_PORT_STRAP7', + 'regRCC_DEV1_PORT_STRAP7_BASE_IDX', 'regRCC_DEV1_PORT_STRAP8', + 'regRCC_DEV1_PORT_STRAP8_BASE_IDX', 'regRCC_DEV1_PORT_STRAP9', + 'regRCC_DEV1_PORT_STRAP9_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP0', + 'regRCC_DEV2_EPF0_STRAP0_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP13', + 'regRCC_DEV2_EPF0_STRAP13_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP14', + 'regRCC_DEV2_EPF0_STRAP14_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP2', + 'regRCC_DEV2_EPF0_STRAP2_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP3', + 'regRCC_DEV2_EPF0_STRAP3_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP4', + 'regRCC_DEV2_EPF0_STRAP4_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP5', + 'regRCC_DEV2_EPF0_STRAP5_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP6', + 'regRCC_DEV2_EPF0_STRAP6_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP7', + 'regRCC_DEV2_EPF0_STRAP7_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP0', + 'regRCC_DEV2_EPF1_STRAP0_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP13', + 'regRCC_DEV2_EPF1_STRAP13_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP14', + 'regRCC_DEV2_EPF1_STRAP14_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP2', + 'regRCC_DEV2_EPF1_STRAP2_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP3', + 'regRCC_DEV2_EPF1_STRAP3_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP4', + 'regRCC_DEV2_EPF1_STRAP4_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP5', + 'regRCC_DEV2_EPF1_STRAP5_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP6', + 'regRCC_DEV2_EPF1_STRAP6_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP0', + 'regRCC_DEV2_EPF2_STRAP0_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP13', + 'regRCC_DEV2_EPF2_STRAP13_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP14', + 'regRCC_DEV2_EPF2_STRAP14_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP2', + 'regRCC_DEV2_EPF2_STRAP2_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP3', + 'regRCC_DEV2_EPF2_STRAP3_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP4', + 'regRCC_DEV2_EPF2_STRAP4_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP5', + 'regRCC_DEV2_EPF2_STRAP5_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP6', + 'regRCC_DEV2_EPF2_STRAP6_BASE_IDX', 'regRCC_DEV2_PORT_STRAP0', + 'regRCC_DEV2_PORT_STRAP0_BASE_IDX', 'regRCC_DEV2_PORT_STRAP1', + 'regRCC_DEV2_PORT_STRAP10', 'regRCC_DEV2_PORT_STRAP10_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP11', 'regRCC_DEV2_PORT_STRAP11_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP12', 'regRCC_DEV2_PORT_STRAP12_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP13', 'regRCC_DEV2_PORT_STRAP13_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP14', 'regRCC_DEV2_PORT_STRAP14_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP1_BASE_IDX', 'regRCC_DEV2_PORT_STRAP2', + 'regRCC_DEV2_PORT_STRAP2_BASE_IDX', 'regRCC_DEV2_PORT_STRAP3', + 'regRCC_DEV2_PORT_STRAP3_BASE_IDX', 'regRCC_DEV2_PORT_STRAP4', + 'regRCC_DEV2_PORT_STRAP4_BASE_IDX', 'regRCC_DEV2_PORT_STRAP5', + 'regRCC_DEV2_PORT_STRAP5_BASE_IDX', 'regRCC_DEV2_PORT_STRAP6', + 'regRCC_DEV2_PORT_STRAP6_BASE_IDX', 'regRCC_DEV2_PORT_STRAP7', + 'regRCC_DEV2_PORT_STRAP7_BASE_IDX', 'regRCC_DEV2_PORT_STRAP8', + 'regRCC_DEV2_PORT_STRAP8_BASE_IDX', 'regRCC_DEV2_PORT_STRAP9', + 'regRCC_DEV2_PORT_STRAP9_BASE_IDX', + 'regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP', + 'regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC', + 'regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL', + 'regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2', + 'regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL', + 'regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_RX_CNTL', + 'regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP', + 'regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC', + 'regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL', + 'regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2', + 'regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL', + 'regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_RX_CNTL', + 'regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP', + 'regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC', + 'regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL', + 'regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2', + 'regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL', + 'regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_RX_CNTL', + 'regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_RESERVED', + 'regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2', + 'regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH', + 'regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_RESERVED', + 'regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2', + 'regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH', + 'regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_RESERVED', + 'regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2', + 'regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH', + 'regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIEP_RESERVED', + 'regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL', + 'regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_SCRATCH', + 'regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIEP_RESERVED', + 'regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL', + 'regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_SCRATCH', + 'regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIEP_RESERVED', + 'regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL', + 'regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_SCRATCH', + 'regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP0', + 'regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP1', + 'regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP2', + 'regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP3', + 'regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP4', + 'regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP5', + 'regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP6', + 'regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP0', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP1', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP10', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP11', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP12', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP13', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP14', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP2', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP3', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP4', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP5', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP6', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP7', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP8', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP9', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP0', + 'regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP1', + 'regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP2', + 'regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP3', + 'regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP4', + 'regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP5', + 'regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP6', + 'regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP0', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP1', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP10', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP11', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP12', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP13', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP14', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP2', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP3', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP4', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP5', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP6', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP7', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP8', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP9', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP0', + 'regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP1', + 'regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP2', + 'regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP3', + 'regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP4', + 'regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP5', + 'regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP6', + 'regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP0', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP1', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP10', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP11', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP12', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP13', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP14', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP2', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP3', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP4', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP5', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP6', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP7', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP8', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP9', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX', + 'regREGS_ROM_OFFSET_CTRL', 'regREGS_ROM_OFFSET_CTRL_BASE_IDX', + 'regS2A_DOORBELL_COMMON_CTRL_REG', + 'regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_0_CTRL', + 'regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_10_CTRL', + 'regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_11_CTRL', + 'regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_12_CTRL', + 'regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_13_CTRL', + 'regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_14_CTRL', + 'regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_15_CTRL', + 'regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_1_CTRL', + 'regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_2_CTRL', + 'regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_3_CTRL', + 'regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_4_CTRL', + 'regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_5_CTRL', + 'regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_6_CTRL', + 'regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_7_CTRL', + 'regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_8_CTRL', + 'regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_9_CTRL', + 'regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX', 'regSELF_SOFT_RST', + 'regSELF_SOFT_RST_2', 'regSELF_SOFT_RST_2_BASE_IDX', + 'regSELF_SOFT_RST_BASE_IDX', 'regSHADOW_BASE_ADDR_1', + 'regSHADOW_BASE_ADDR_1_BASE_IDX', 'regSHADOW_BASE_ADDR_2', + 'regSHADOW_BASE_ADDR_2_BASE_IDX', 'regSHADOW_COMMAND', + 'regSHADOW_COMMAND_BASE_IDX', 'regSHADOW_IO_BASE_LIMIT', + 'regSHADOW_IO_BASE_LIMIT_BASE_IDX', 'regSHADOW_IO_BASE_LIMIT_HI', + 'regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX', 'regSHADOW_MEM_BASE_LIMIT', + 'regSHADOW_MEM_BASE_LIMIT_BASE_IDX', 'regSHADOW_PREF_BASE_LIMIT', + 'regSHADOW_PREF_BASE_LIMIT_BASE_IDX', 'regSHADOW_PREF_BASE_UPPER', + 'regSHADOW_PREF_BASE_UPPER_BASE_IDX', + 'regSHADOW_PREF_LIMIT_UPPER', + 'regSHADOW_PREF_LIMIT_UPPER_BASE_IDX', + 'regSHADOW_SUB_BUS_NUMBER_LATENCY', + 'regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX', + 'regSHUB_GFX_DRV_VPU_RST', 'regSHUB_GFX_DRV_VPU_RST_BASE_IDX', + 'regSHUB_HARD_RST_CTRL', 'regSHUB_HARD_RST_CTRL_BASE_IDX', + 'regSHUB_LINK_RESET', 'regSHUB_LINK_RESET_BASE_IDX', + 'regSHUB_PF_FLR_RST', 'regSHUB_PF_FLR_RST_BASE_IDX', + 'regSHUB_RST_MISC_TRL', 'regSHUB_RST_MISC_TRL_BASE_IDX', + 'regSHUB_SDP_PORT_RST', 'regSHUB_SDP_PORT_RST_BASE_IDX', + 'regSHUB_SOFT_RST_CTRL', 'regSHUB_SOFT_RST_CTRL_BASE_IDX', + 'regSLOT_CAP', 'regSLOT_CAP2', 'regSLOT_CAP2_BASE_IDX', + 'regSLOT_CAP_BASE_IDX', 'regSLOT_CNTL', 'regSLOT_CNTL2', + 'regSLOT_CNTL2_BASE_IDX', 'regSLOT_CNTL_BASE_IDX', + 'regSLOT_STATUS', 'regSLOT_STATUS2', 'regSLOT_STATUS2_BASE_IDX', + 'regSLOT_STATUS_BASE_IDX', 'regSMN_APERTURE_ID_A', + 'regSMN_APERTURE_ID_A_BASE_IDX', 'regSMN_APERTURE_ID_B', + 'regSMN_APERTURE_ID_B_BASE_IDX', 'regSMN_MST_CNTL0', + 'regSMN_MST_CNTL0_BASE_IDX', 'regSMN_MST_CNTL1', + 'regSMN_MST_CNTL1_BASE_IDX', 'regSMN_MST_EP_CNTL1', + 'regSMN_MST_EP_CNTL1_BASE_IDX', 'regSMN_MST_EP_CNTL2', + 'regSMN_MST_EP_CNTL2_BASE_IDX', 'regSMN_MST_EP_CNTL3', + 'regSMN_MST_EP_CNTL3_BASE_IDX', 'regSMN_MST_EP_CNTL4', + 'regSMN_MST_EP_CNTL4_BASE_IDX', 'regSMN_MST_EP_CNTL5', + 'regSMN_MST_EP_CNTL5_BASE_IDX', + 'regSMU_INT_PIN_SHARING_PORT_INDICATOR', + 'regSMU_INT_PIN_SHARING_PORT_INDICATOR_BASE_IDX', + 'regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO', + 'regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO_BASE_IDX', + 'regSMU_PCIE_FENCED1_REG', 'regSMU_PCIE_FENCED1_REG_BASE_IDX', + 'regSMU_PCIE_FENCED2_REG', 'regSMU_PCIE_FENCED2_REG_BASE_IDX', + 'regSUC_DATA', 'regSUC_DATA_BASE_IDX', 'regSUC_INDEX', + 'regSUC_INDEX_BASE_IDX', 'regSUM_DATA', 'regSUM_DATA_BASE_IDX', + 'regSUM_INDEX', 'regSUM_INDEX_BASE_IDX', 'regSUM_INDEX_HI', + 'regSUM_INDEX_HI_BASE_IDX', 'regSWRST_COMMAND_0', + 'regSWRST_COMMAND_0_BASE_IDX', 'regSWRST_COMMAND_1', + 'regSWRST_COMMAND_1_BASE_IDX', 'regSWRST_COMMAND_STATUS', + 'regSWRST_COMMAND_STATUS_BASE_IDX', 'regSWRST_CONTROL_0', + 'regSWRST_CONTROL_0_BASE_IDX', 'regSWRST_CONTROL_1', + 'regSWRST_CONTROL_1_BASE_IDX', 'regSWRST_CONTROL_2', + 'regSWRST_CONTROL_2_BASE_IDX', 'regSWRST_CONTROL_3', + 'regSWRST_CONTROL_3_BASE_IDX', 'regSWRST_CONTROL_4', + 'regSWRST_CONTROL_4_BASE_IDX', 'regSWRST_CONTROL_5', + 'regSWRST_CONTROL_5_BASE_IDX', 'regSWRST_CONTROL_6', + 'regSWRST_CONTROL_6_BASE_IDX', 'regSWRST_EP_COMMAND_0', + 'regSWRST_EP_COMMAND_0_BASE_IDX', 'regSWRST_EP_CONTROL_0', + 'regSWRST_EP_CONTROL_0_BASE_IDX', 'regSWRST_GENERAL_CONTROL', + 'regSWRST_GENERAL_CONTROL_BASE_IDX'] diff --git a/tinygrad/runtime/autogen/am/osssys_6_0_0.py b/tinygrad/runtime/autogen/am/osssys_6_0_0.py new file mode 100644 index 0000000000..bbaa4e9c82 --- /dev/null +++ b/tinygrad/runtime/autogen/am/osssys_6_0_0.py @@ -0,0 +1,1961 @@ +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_osssys_6_0_0_OFFSET_HEADER = True # macro +regIH_VMID_0_LUT = 0x0000 # macro +regIH_VMID_0_LUT_BASE_IDX = 0 # macro +regIH_VMID_1_LUT = 0x0001 # macro +regIH_VMID_1_LUT_BASE_IDX = 0 # macro +regIH_VMID_2_LUT = 0x0002 # macro +regIH_VMID_2_LUT_BASE_IDX = 0 # macro +regIH_VMID_3_LUT = 0x0003 # macro +regIH_VMID_3_LUT_BASE_IDX = 0 # macro +regIH_VMID_4_LUT = 0x0004 # macro +regIH_VMID_4_LUT_BASE_IDX = 0 # macro +regIH_VMID_5_LUT = 0x0005 # macro +regIH_VMID_5_LUT_BASE_IDX = 0 # macro +regIH_VMID_6_LUT = 0x0006 # macro +regIH_VMID_6_LUT_BASE_IDX = 0 # macro +regIH_VMID_7_LUT = 0x0007 # macro +regIH_VMID_7_LUT_BASE_IDX = 0 # macro +regIH_VMID_8_LUT = 0x0008 # macro +regIH_VMID_8_LUT_BASE_IDX = 0 # macro +regIH_VMID_9_LUT = 0x0009 # macro +regIH_VMID_9_LUT_BASE_IDX = 0 # macro +regIH_VMID_10_LUT = 0x000a # macro +regIH_VMID_10_LUT_BASE_IDX = 0 # macro +regIH_VMID_11_LUT = 0x000b # macro +regIH_VMID_11_LUT_BASE_IDX = 0 # macro +regIH_VMID_12_LUT = 0x000c # macro +regIH_VMID_12_LUT_BASE_IDX = 0 # macro +regIH_VMID_13_LUT = 0x000d # macro +regIH_VMID_13_LUT_BASE_IDX = 0 # macro +regIH_VMID_14_LUT = 0x000e # macro +regIH_VMID_14_LUT_BASE_IDX = 0 # macro +regIH_VMID_15_LUT = 0x000f # macro +regIH_VMID_15_LUT_BASE_IDX = 0 # macro +regIH_VMID_0_LUT_MM = 0x0010 # macro +regIH_VMID_0_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_1_LUT_MM = 0x0011 # macro +regIH_VMID_1_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_2_LUT_MM = 0x0012 # macro +regIH_VMID_2_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_3_LUT_MM = 0x0013 # macro +regIH_VMID_3_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_4_LUT_MM = 0x0014 # macro +regIH_VMID_4_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_5_LUT_MM = 0x0015 # macro +regIH_VMID_5_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_6_LUT_MM = 0x0016 # macro +regIH_VMID_6_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_7_LUT_MM = 0x0017 # macro +regIH_VMID_7_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_8_LUT_MM = 0x0018 # macro +regIH_VMID_8_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_9_LUT_MM = 0x0019 # macro +regIH_VMID_9_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_10_LUT_MM = 0x001a # macro +regIH_VMID_10_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_11_LUT_MM = 0x001b # macro +regIH_VMID_11_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_12_LUT_MM = 0x001c # macro +regIH_VMID_12_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_13_LUT_MM = 0x001d # macro +regIH_VMID_13_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_14_LUT_MM = 0x001e # macro +regIH_VMID_14_LUT_MM_BASE_IDX = 0 # macro +regIH_VMID_15_LUT_MM = 0x001f # macro +regIH_VMID_15_LUT_MM_BASE_IDX = 0 # macro +regIH_COOKIE_0 = 0x0020 # macro +regIH_COOKIE_0_BASE_IDX = 0 # macro +regIH_COOKIE_1 = 0x0021 # macro +regIH_COOKIE_1_BASE_IDX = 0 # macro +regIH_COOKIE_2 = 0x0022 # macro +regIH_COOKIE_2_BASE_IDX = 0 # macro +regIH_COOKIE_3 = 0x0023 # macro +regIH_COOKIE_3_BASE_IDX = 0 # macro +regIH_COOKIE_4 = 0x0024 # macro +regIH_COOKIE_4_BASE_IDX = 0 # macro +regIH_COOKIE_5 = 0x0025 # macro +regIH_COOKIE_5_BASE_IDX = 0 # macro +regIH_COOKIE_6 = 0x0026 # macro +regIH_COOKIE_6_BASE_IDX = 0 # macro +regIH_COOKIE_7 = 0x0027 # macro +regIH_COOKIE_7_BASE_IDX = 0 # macro +regIH_REGISTER_LAST_PART0 = 0x003f # macro +regIH_REGISTER_LAST_PART0_BASE_IDX = 0 # macro +regIH_RB_CNTL = 0x0080 # macro +regIH_RB_CNTL_BASE_IDX = 0 # macro +regIH_RB_BASE = 0x0081 # macro +regIH_RB_BASE_BASE_IDX = 0 # macro +regIH_RB_BASE_HI = 0x0082 # macro +regIH_RB_BASE_HI_BASE_IDX = 0 # macro +regIH_RB_RPTR = 0x0083 # macro +regIH_RB_RPTR_BASE_IDX = 0 # macro +regIH_RB_WPTR = 0x0084 # macro +regIH_RB_WPTR_BASE_IDX = 0 # macro +regIH_RB_WPTR_ADDR_HI = 0x0085 # macro +regIH_RB_WPTR_ADDR_HI_BASE_IDX = 0 # macro +regIH_RB_WPTR_ADDR_LO = 0x0086 # macro +regIH_RB_WPTR_ADDR_LO_BASE_IDX = 0 # macro +regIH_DOORBELL_RPTR = 0x0087 # macro +regIH_DOORBELL_RPTR_BASE_IDX = 0 # macro +regIH_DOORBELL_RETRY_CAM = 0x0088 # macro +regIH_DOORBELL_RETRY_CAM_BASE_IDX = 0 # macro +regIH_RB_CNTL_RING1 = 0x008c # macro +regIH_RB_CNTL_RING1_BASE_IDX = 0 # macro +regIH_RB_BASE_RING1 = 0x008d # macro +regIH_RB_BASE_RING1_BASE_IDX = 0 # macro +regIH_RB_BASE_HI_RING1 = 0x008e # macro +regIH_RB_BASE_HI_RING1_BASE_IDX = 0 # macro +regIH_RB_RPTR_RING1 = 0x008f # macro +regIH_RB_RPTR_RING1_BASE_IDX = 0 # macro +regIH_RB_WPTR_RING1 = 0x0090 # macro +regIH_RB_WPTR_RING1_BASE_IDX = 0 # macro +regIH_DOORBELL_RPTR_RING1 = 0x0093 # macro +regIH_DOORBELL_RPTR_RING1_BASE_IDX = 0 # macro +regIH_RETRY_CAM_ACK = 0x00a4 # macro +regIH_RETRY_CAM_ACK_BASE_IDX = 0 # macro +regIH_VERSION = 0x00a5 # macro +regIH_VERSION_BASE_IDX = 0 # macro +regIH_CNTL = 0x00c0 # macro +regIH_CNTL_BASE_IDX = 0 # macro +regIH_CNTL2 = 0x00c1 # macro +regIH_CNTL2_BASE_IDX = 0 # macro +regIH_STATUS = 0x00c2 # macro +regIH_STATUS_BASE_IDX = 0 # macro +regIH_PERFMON_CNTL = 0x00c3 # macro +regIH_PERFMON_CNTL_BASE_IDX = 0 # macro +regIH_PERFCOUNTER0_RESULT = 0x00c4 # macro +regIH_PERFCOUNTER0_RESULT_BASE_IDX = 0 # macro +regIH_PERFCOUNTER1_RESULT = 0x00c5 # macro +regIH_PERFCOUNTER1_RESULT_BASE_IDX = 0 # macro +regIH_DSM_MATCH_VALUE_BIT_31_0 = 0x00c7 # macro +regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX = 0 # macro +regIH_DSM_MATCH_VALUE_BIT_63_32 = 0x00c8 # macro +regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX = 0 # macro +regIH_DSM_MATCH_VALUE_BIT_95_64 = 0x00c9 # macro +regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX = 0 # macro +regIH_DSM_MATCH_FIELD_CONTROL = 0x00ca # macro +regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX = 0 # macro +regIH_DSM_MATCH_DATA_CONTROL = 0x00cb # macro +regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX = 0 # macro +regIH_DSM_MATCH_FCN_ID = 0x00cc # macro +regIH_DSM_MATCH_FCN_ID_BASE_IDX = 0 # macro +regIH_LIMIT_INT_RATE_CNTL = 0x00cd # macro +regIH_LIMIT_INT_RATE_CNTL_BASE_IDX = 0 # macro +regIH_VF_RB_STATUS = 0x00ce # macro +regIH_VF_RB_STATUS_BASE_IDX = 0 # macro +regIH_VF_RB_STATUS2 = 0x00cf # macro +regIH_VF_RB_STATUS2_BASE_IDX = 0 # macro +regIH_VF_RB1_STATUS = 0x00d0 # macro +regIH_VF_RB1_STATUS_BASE_IDX = 0 # macro +regIH_VF_RB1_STATUS2 = 0x00d1 # macro +regIH_VF_RB1_STATUS2_BASE_IDX = 0 # macro +regIH_RB_STATUS = 0x00d4 # macro +regIH_RB_STATUS_BASE_IDX = 0 # macro +regIH_INT_FLOOD_CNTL = 0x00d5 # macro +regIH_INT_FLOOD_CNTL_BASE_IDX = 0 # macro +regIH_RB0_INT_FLOOD_STATUS = 0x00d6 # macro +regIH_RB0_INT_FLOOD_STATUS_BASE_IDX = 0 # macro +regIH_RB1_INT_FLOOD_STATUS = 0x00d7 # macro +regIH_RB1_INT_FLOOD_STATUS_BASE_IDX = 0 # macro +regIH_INT_FLOOD_STATUS = 0x00d9 # macro +regIH_INT_FLOOD_STATUS_BASE_IDX = 0 # macro +regIH_STORM_CLIENT_LIST_CNTL = 0x00da # macro +regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX = 0 # macro +regIH_CLK_CTRL = 0x00db # macro +regIH_CLK_CTRL_BASE_IDX = 0 # macro +regIH_INT_FLAGS = 0x00dc # macro +regIH_INT_FLAGS_BASE_IDX = 0 # macro +regIH_LAST_INT_INFO0 = 0x00dd # macro +regIH_LAST_INT_INFO0_BASE_IDX = 0 # macro +regIH_LAST_INT_INFO1 = 0x00de # macro +regIH_LAST_INT_INFO1_BASE_IDX = 0 # macro +regIH_LAST_INT_INFO2 = 0x00df # macro +regIH_LAST_INT_INFO2_BASE_IDX = 0 # macro +regIH_SCRATCH = 0x00e0 # macro +regIH_SCRATCH_BASE_IDX = 0 # macro +regIH_CLIENT_CREDIT_ERROR = 0x00e1 # macro +regIH_CLIENT_CREDIT_ERROR_BASE_IDX = 0 # macro +regIH_COOKIE_REC_VIOLATION_LOG = 0x00e4 # macro +regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX = 0 # macro +regIH_CREDIT_STATUS = 0x00e5 # macro +regIH_CREDIT_STATUS_BASE_IDX = 0 # macro +regIH_MMHUB_ERROR = 0x00e6 # macro +regIH_MMHUB_ERROR_BASE_IDX = 0 # macro +regIH_MEM_POWER_CTRL = 0x00e9 # macro +regIH_MEM_POWER_CTRL_BASE_IDX = 0 # macro +regIH_VF_RB_STATUS3 = 0x00ea # macro +regIH_VF_RB_STATUS3_BASE_IDX = 0 # macro +regIH_VF_RB_STATUS4 = 0x00eb # macro +regIH_VF_RB_STATUS4_BASE_IDX = 0 # macro +regIH_VF_RB1_STATUS3 = 0x00ec # macro +regIH_VF_RB1_STATUS3_BASE_IDX = 0 # macro +regIH_RETRY_INT_CAM_CNTL = 0x00ef # macro +regIH_RETRY_INT_CAM_CNTL_BASE_IDX = 0 # macro +regIH_MEM_POWER_CTRL2 = 0x00f0 # macro +regIH_MEM_POWER_CTRL2_BASE_IDX = 0 # macro +regIH_MSI_STORM_CTRL = 0x00f1 # macro +regIH_MSI_STORM_CTRL_BASE_IDX = 0 # macro +regIH_MSI_STORM_CLIENT_INDEX = 0x00f2 # macro +regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX = 0 # macro +regIH_MSI_STORM_CLIENT_DATA = 0x00f3 # macro +regIH_MSI_STORM_CLIENT_DATA_BASE_IDX = 0 # macro +regIH_REGISTER_LAST_PART2 = 0x00ff # macro +regIH_REGISTER_LAST_PART2_BASE_IDX = 0 # macro +regSEM_MAILBOX = 0x010a # macro +regSEM_MAILBOX_BASE_IDX = 0 # macro +regSEM_MAILBOX_CLEAR = 0x010b # macro +regSEM_MAILBOX_CLEAR_BASE_IDX = 0 # macro +regSEM_REGISTER_LAST_PART2 = 0x017f # macro +regSEM_REGISTER_LAST_PART2_BASE_IDX = 0 # macro +regIH_CLIENT_CFG = 0x0184 # macro +regIH_CLIENT_CFG_BASE_IDX = 0 # macro +regIH_RING1_CLIENT_CFG_INDEX = 0x0185 # macro +regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX = 0 # macro +regIH_RING1_CLIENT_CFG_DATA = 0x0186 # macro +regIH_RING1_CLIENT_CFG_DATA_BASE_IDX = 0 # macro +regIH_CLIENT_CFG_INDEX = 0x0188 # macro +regIH_CLIENT_CFG_INDEX_BASE_IDX = 0 # macro +regIH_CLIENT_CFG_DATA = 0x0189 # macro +regIH_CLIENT_CFG_DATA_BASE_IDX = 0 # macro +regIH_CID_REMAP_INDEX = 0x018b # macro +regIH_CID_REMAP_INDEX_BASE_IDX = 0 # macro +regIH_CID_REMAP_DATA = 0x018c # macro +regIH_CID_REMAP_DATA_BASE_IDX = 0 # macro +regIH_CHICKEN = 0x018d # macro +regIH_CHICKEN_BASE_IDX = 0 # macro +regIH_INT_DROP_CNTL = 0x018f # macro +regIH_INT_DROP_CNTL_BASE_IDX = 0 # macro +regIH_INT_DROP_MATCH_VALUE0 = 0x0190 # macro +regIH_INT_DROP_MATCH_VALUE0_BASE_IDX = 0 # macro +regIH_INT_DROP_MATCH_VALUE1 = 0x0191 # macro +regIH_INT_DROP_MATCH_VALUE1_BASE_IDX = 0 # macro +regIH_INT_DROP_MATCH_MASK0 = 0x0192 # macro +regIH_INT_DROP_MATCH_MASK0_BASE_IDX = 0 # macro +regIH_INT_DROP_MATCH_MASK1 = 0x0193 # macro +regIH_INT_DROP_MATCH_MASK1_BASE_IDX = 0 # macro +regIH_REGISTER_LAST_PART1 = 0x019f # macro +regIH_REGISTER_LAST_PART1_BASE_IDX = 0 # macro +_osssys_6_0_0_SH_MASK_HEADER = True # macro +IH_VMID_0_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_0_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_1_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_1_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_2_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_2_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_3_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_3_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_4_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_4_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_5_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_5_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_6_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_6_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_7_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_7_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_8_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_8_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_9_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_9_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_10_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_10_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_11_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_11_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_12_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_12_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_13_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_13_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_14_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_14_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_15_LUT__PASID__SHIFT = 0x0 # macro +IH_VMID_15_LUT__PASID_MASK = 0x0000FFFF # macro +IH_VMID_0_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_0_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_1_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_1_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_2_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_2_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_3_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_3_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_4_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_4_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_5_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_5_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_6_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_6_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_7_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_7_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_8_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_8_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_9_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_9_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_10_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_10_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_11_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_11_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_12_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_12_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_13_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_13_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_14_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_14_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_VMID_15_LUT_MM__PASID__SHIFT = 0x0 # macro +IH_VMID_15_LUT_MM__PASID_MASK = 0x0000FFFF # macro +IH_COOKIE_0__CLIENT_ID__SHIFT = 0x0 # macro +IH_COOKIE_0__SOURCE_ID__SHIFT = 0x8 # macro +IH_COOKIE_0__RING_ID__SHIFT = 0x10 # macro +IH_COOKIE_0__VM_ID__SHIFT = 0x18 # macro +IH_COOKIE_0__RESERVED__SHIFT = 0x1c # macro +IH_COOKIE_0__VMID_TYPE__SHIFT = 0x1f # macro +IH_COOKIE_0__CLIENT_ID_MASK = 0x000000FF # macro +IH_COOKIE_0__SOURCE_ID_MASK = 0x0000FF00 # macro +IH_COOKIE_0__RING_ID_MASK = 0x00FF0000 # macro +IH_COOKIE_0__VM_ID_MASK = 0x0F000000 # macro +IH_COOKIE_0__RESERVED_MASK = 0x70000000 # macro +IH_COOKIE_0__VMID_TYPE_MASK = 0x80000000 # macro +IH_COOKIE_1__TIMESTAMP_31_0__SHIFT = 0x0 # macro +IH_COOKIE_1__TIMESTAMP_31_0_MASK = 0xFFFFFFFF # macro +IH_COOKIE_2__TIMESTAMP_47_32__SHIFT = 0x0 # macro +IH_COOKIE_2__RESERVED__SHIFT = 0x10 # macro +IH_COOKIE_2__TIMESTAMP_SRC__SHIFT = 0x1f # macro +IH_COOKIE_2__TIMESTAMP_47_32_MASK = 0x0000FFFF # macro +IH_COOKIE_2__RESERVED_MASK = 0x7FFF0000 # macro +IH_COOKIE_2__TIMESTAMP_SRC_MASK = 0x80000000 # macro +IH_COOKIE_3__PAS_ID__SHIFT = 0x0 # macro +IH_COOKIE_3__RESERVED__SHIFT = 0x10 # macro +IH_COOKIE_3__PASID_SRC__SHIFT = 0x1f # macro +IH_COOKIE_3__PAS_ID_MASK = 0x0000FFFF # macro +IH_COOKIE_3__RESERVED_MASK = 0x7FFF0000 # macro +IH_COOKIE_3__PASID_SRC_MASK = 0x80000000 # macro +IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT = 0x0 # macro +IH_COOKIE_4__CONTEXT_ID_31_0_MASK = 0xFFFFFFFF # macro +IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT = 0x0 # macro +IH_COOKIE_5__CONTEXT_ID_63_32_MASK = 0xFFFFFFFF # macro +IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT = 0x0 # macro +IH_COOKIE_6__CONTEXT_ID_95_64_MASK = 0xFFFFFFFF # macro +IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT = 0x0 # macro +IH_COOKIE_7__CONTEXT_ID_128_96_MASK = 0xFFFFFFFF # macro +IH_REGISTER_LAST_PART0__RESERVED__SHIFT = 0x0 # macro +IH_REGISTER_LAST_PART0__RESERVED_MASK = 0xFFFFFFFF # macro +IH_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +IH_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT = 0x8 # macro +IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT = 0x9 # macro +IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT = 0xa # macro +IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT = 0xb # macro +IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT = 0xc # macro +IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT = 0x10 # macro +IH_RB_CNTL__ENABLE_INTR__SHIFT = 0x11 # macro +IH_RB_CNTL__MC_SWAP__SHIFT = 0x12 # macro +IH_RB_CNTL__MC_SNOOP__SHIFT = 0x14 # macro +IH_RB_CNTL__RPTR_REARM__SHIFT = 0x15 # macro +IH_RB_CNTL__MC_RO__SHIFT = 0x16 # macro +IH_RB_CNTL__MC_VMID__SHIFT = 0x18 # macro +IH_RB_CNTL__MC_SPACE__SHIFT = 0x1c # macro +IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT = 0x1f # macro +IH_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +IH_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK = 0x00000100 # macro +IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK = 0x00000200 # macro +IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK = 0x00000400 # macro +IH_RB_CNTL__PAGE_RB_CLEAR_MASK = 0x00000800 # macro +IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK = 0x0000F000 # macro +IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK = 0x00010000 # macro +IH_RB_CNTL__ENABLE_INTR_MASK = 0x00020000 # macro +IH_RB_CNTL__MC_SWAP_MASK = 0x000C0000 # macro +IH_RB_CNTL__MC_SNOOP_MASK = 0x00100000 # macro +IH_RB_CNTL__RPTR_REARM_MASK = 0x00200000 # macro +IH_RB_CNTL__MC_RO_MASK = 0x00400000 # macro +IH_RB_CNTL__MC_VMID_MASK = 0x0F000000 # macro +IH_RB_CNTL__MC_SPACE_MASK = 0x70000000 # macro +IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK = 0x80000000 # macro +IH_RB_BASE__ADDR__SHIFT = 0x0 # macro +IH_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +IH_RB_BASE_HI__ADDR__SHIFT = 0x0 # macro +IH_RB_BASE_HI__ADDR_MASK = 0x000000FF # macro +IH_RB_RPTR__OFFSET__SHIFT = 0x2 # macro +IH_RB_RPTR__OFFSET_MASK = 0x0003FFFC # macro +IH_RB_WPTR__RB_OVERFLOW__SHIFT = 0x0 # macro +IH_RB_WPTR__OFFSET__SHIFT = 0x2 # macro +IH_RB_WPTR__RB_LEFT_NONE__SHIFT = 0x12 # macro +IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT = 0x13 # macro +IH_RB_WPTR__RB_OVERFLOW_MASK = 0x00000001 # macro +IH_RB_WPTR__OFFSET_MASK = 0x0003FFFC # macro +IH_RB_WPTR__RB_LEFT_NONE_MASK = 0x00040000 # macro +IH_RB_WPTR__RB_MAY_OVERFLOW_MASK = 0x00080000 # macro +IH_RB_WPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +IH_RB_WPTR_ADDR_HI__ADDR_MASK = 0x0000FFFF # macro +IH_RB_WPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +IH_RB_WPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +IH_DOORBELL_RPTR__OFFSET__SHIFT = 0x0 # macro +IH_DOORBELL_RPTR__ENABLE__SHIFT = 0x1c # macro +IH_DOORBELL_RPTR__OFFSET_MASK = 0x03FFFFFF # macro +IH_DOORBELL_RPTR__ENABLE_MASK = 0x10000000 # macro +IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT = 0x0 # macro +IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT = 0x1c # macro +IH_DOORBELL_RETRY_CAM__OFFSET_MASK = 0x03FFFFFF # macro +IH_DOORBELL_RETRY_CAM__ENABLE_MASK = 0x10000000 # macro +IH_RB_CNTL_RING1__RB_ENABLE__SHIFT = 0x0 # macro +IH_RB_CNTL_RING1__RB_SIZE__SHIFT = 0x1 # macro +IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT = 0x9 # macro +IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT = 0xa # macro +IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT = 0xb # macro +IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT = 0xc # macro +IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT = 0x10 # macro +IH_RB_CNTL_RING1__MC_SWAP__SHIFT = 0x12 # macro +IH_RB_CNTL_RING1__MC_SNOOP__SHIFT = 0x14 # macro +IH_RB_CNTL_RING1__MC_RO__SHIFT = 0x16 # macro +IH_RB_CNTL_RING1__MC_VMID__SHIFT = 0x18 # macro +IH_RB_CNTL_RING1__MC_SPACE__SHIFT = 0x1c # macro +IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT = 0x1f # macro +IH_RB_CNTL_RING1__RB_ENABLE_MASK = 0x00000001 # macro +IH_RB_CNTL_RING1__RB_SIZE_MASK = 0x0000003E # macro +IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK = 0x00000200 # macro +IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK = 0x00000400 # macro +IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK = 0x00000800 # macro +IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK = 0x0000F000 # macro +IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK = 0x00010000 # macro +IH_RB_CNTL_RING1__MC_SWAP_MASK = 0x000C0000 # macro +IH_RB_CNTL_RING1__MC_SNOOP_MASK = 0x00100000 # macro +IH_RB_CNTL_RING1__MC_RO_MASK = 0x00400000 # macro +IH_RB_CNTL_RING1__MC_VMID_MASK = 0x0F000000 # macro +IH_RB_CNTL_RING1__MC_SPACE_MASK = 0x70000000 # macro +IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK = 0x80000000 # macro +IH_RB_BASE_RING1__ADDR__SHIFT = 0x0 # macro +IH_RB_BASE_RING1__ADDR_MASK = 0xFFFFFFFF # macro +IH_RB_BASE_HI_RING1__ADDR__SHIFT = 0x0 # macro +IH_RB_BASE_HI_RING1__ADDR_MASK = 0x000000FF # macro +IH_RB_RPTR_RING1__OFFSET__SHIFT = 0x2 # macro +IH_RB_RPTR_RING1__OFFSET_MASK = 0x0003FFFC # macro +IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT = 0x0 # macro +IH_RB_WPTR_RING1__OFFSET__SHIFT = 0x2 # macro +IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT = 0x12 # macro +IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT = 0x13 # macro +IH_RB_WPTR_RING1__RB_OVERFLOW_MASK = 0x00000001 # macro +IH_RB_WPTR_RING1__OFFSET_MASK = 0x0003FFFC # macro +IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK = 0x00040000 # macro +IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK = 0x00080000 # macro +IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT = 0x0 # macro +IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT = 0x1c # macro +IH_DOORBELL_RPTR_RING1__OFFSET_MASK = 0x03FFFFFF # macro +IH_DOORBELL_RPTR_RING1__ENABLE_MASK = 0x10000000 # macro +IH_RETRY_CAM_ACK__INDEX__SHIFT = 0x0 # macro +IH_RETRY_CAM_ACK__INDEX_MASK = 0x000003FF # macro +IH_VERSION__MINVER__SHIFT = 0x0 # macro +IH_VERSION__MAJVER__SHIFT = 0x8 # macro +IH_VERSION__REV__SHIFT = 0x10 # macro +IH_VERSION__MINVER_MASK = 0x0000007F # macro +IH_VERSION__MAJVER_MASK = 0x00007F00 # macro +IH_VERSION__REV_MASK = 0x003F0000 # macro +IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT = 0x0 # macro +IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT = 0x6 # macro +IH_CNTL__IH_FIFO_HIGHWATER__SHIFT = 0x8 # macro +IH_CNTL__MC_WR_CLEAN_CNT__SHIFT = 0x14 # macro +IH_CNTL__WPTR_WRITEBACK_TIMER_MASK = 0x0000001F # macro +IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK = 0x000000C0 # macro +IH_CNTL__IH_FIFO_HIGHWATER_MASK = 0x00007F00 # macro +IH_CNTL__MC_WR_CLEAN_CNT_MASK = 0x01F00000 # macro +IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT = 0x0 # macro +IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT = 0x8 # macro +IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK = 0x0000001F # macro +IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK = 0x00000100 # macro +IH_STATUS__IDLE__SHIFT = 0x0 # macro +IH_STATUS__INPUT_IDLE__SHIFT = 0x1 # macro +IH_STATUS__BUFFER_IDLE__SHIFT = 0x2 # macro +IH_STATUS__RB_FULL__SHIFT = 0x3 # macro +IH_STATUS__RB_FULL_DRAIN__SHIFT = 0x4 # macro +IH_STATUS__RB_OVERFLOW__SHIFT = 0x5 # macro +IH_STATUS__MC_WR_IDLE__SHIFT = 0x6 # macro +IH_STATUS__MC_WR_STALL__SHIFT = 0x7 # macro +IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT = 0x8 # macro +IH_STATUS__MC_WR_CLEAN_STALL__SHIFT = 0x9 # macro +IH_STATUS__BIF_INTERRUPT_LINE__SHIFT = 0xa # macro +IH_STATUS__SWITCH_READY__SHIFT = 0xb # macro +IH_STATUS__RB1_FULL__SHIFT = 0xc # macro +IH_STATUS__RB1_FULL_DRAIN__SHIFT = 0xd # macro +IH_STATUS__RB1_OVERFLOW__SHIFT = 0xe # macro +IH_STATUS__SELF_INT_GEN_IDLE__SHIFT = 0x12 # macro +IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT = 0x13 # macro +IH_STATUS__ZSTATES_FENCE__SHIFT = 0x14 # macro +IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT = 0x15 # macro +IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT = 0x16 # macro +IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT = 0x17 # macro +IH_STATUS__IDLE_MASK = 0x00000001 # macro +IH_STATUS__INPUT_IDLE_MASK = 0x00000002 # macro +IH_STATUS__BUFFER_IDLE_MASK = 0x00000004 # macro +IH_STATUS__RB_FULL_MASK = 0x00000008 # macro +IH_STATUS__RB_FULL_DRAIN_MASK = 0x00000010 # macro +IH_STATUS__RB_OVERFLOW_MASK = 0x00000020 # macro +IH_STATUS__MC_WR_IDLE_MASK = 0x00000040 # macro +IH_STATUS__MC_WR_STALL_MASK = 0x00000080 # macro +IH_STATUS__MC_WR_CLEAN_PENDING_MASK = 0x00000100 # macro +IH_STATUS__MC_WR_CLEAN_STALL_MASK = 0x00000200 # macro +IH_STATUS__BIF_INTERRUPT_LINE_MASK = 0x00000400 # macro +IH_STATUS__SWITCH_READY_MASK = 0x00000800 # macro +IH_STATUS__RB1_FULL_MASK = 0x00001000 # macro +IH_STATUS__RB1_FULL_DRAIN_MASK = 0x00002000 # macro +IH_STATUS__RB1_OVERFLOW_MASK = 0x00004000 # macro +IH_STATUS__SELF_INT_GEN_IDLE_MASK = 0x00040000 # macro +IH_STATUS__RETRY_INT_CAM_IDLE_MASK = 0x00080000 # macro +IH_STATUS__ZSTATES_FENCE_MASK = 0x00100000 # macro +IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK = 0x00200000 # macro +IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK = 0x00400000 # macro +IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK = 0x00800000 # macro +IH_PERFMON_CNTL__ENABLE0__SHIFT = 0x0 # macro +IH_PERFMON_CNTL__CLEAR0__SHIFT = 0x1 # macro +IH_PERFMON_CNTL__PERF_SEL0__SHIFT = 0x2 # macro +IH_PERFMON_CNTL__ENABLE1__SHIFT = 0x10 # macro +IH_PERFMON_CNTL__CLEAR1__SHIFT = 0x11 # macro +IH_PERFMON_CNTL__PERF_SEL1__SHIFT = 0x12 # macro +IH_PERFMON_CNTL__ENABLE0_MASK = 0x00000001 # macro +IH_PERFMON_CNTL__CLEAR0_MASK = 0x00000002 # macro +IH_PERFMON_CNTL__PERF_SEL0_MASK = 0x00000FFC # macro +IH_PERFMON_CNTL__ENABLE1_MASK = 0x00010000 # macro +IH_PERFMON_CNTL__CLEAR1_MASK = 0x00020000 # macro +IH_PERFMON_CNTL__PERF_SEL1_MASK = 0x0FFC0000 # macro +IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT = 0x0 # macro +IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK = 0xFFFFFFFF # macro +IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT = 0x0 # macro +IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK = 0xFFFFFFFF # macro +IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT = 0x0 # macro +IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK = 0xFFFFFFFF # macro +IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT = 0x0 # macro +IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK = 0xFFFFFFFF # macro +IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT = 0x0 # macro +IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK = 0xFFFFFFFF # macro +IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT = 0x0 # macro +IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT = 0x1 # macro +IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT = 0x2 # macro +IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT = 0x3 # macro +IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT = 0x4 # macro +IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT = 0x5 # macro +IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT = 0x6 # macro +IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK = 0x00000001 # macro +IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK = 0x00000002 # macro +IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK = 0x00000004 # macro +IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK = 0x00000008 # macro +IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK = 0x00000010 # macro +IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK = 0x00000020 # macro +IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK = 0x00000040 # macro +IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT = 0x0 # macro +IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK = 0x0FFFFFFF # macro +IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT = 0x0 # macro +IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT = 0x7 # macro +IH_DSM_MATCH_FCN_ID__VF_ID_MASK = 0x0000000F # macro +IH_DSM_MATCH_FCN_ID__PF_VF_MASK = 0x00000080 # macro +IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT = 0x0 # macro +IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT = 0x1 # macro +IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT = 0x5 # macro +IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT = 0x11 # macro +IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT = 0x15 # macro +IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK = 0x00000001 # macro +IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK = 0x0000001E # macro +IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK = 0x0000FFE0 # macro +IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK = 0x001E0000 # macro +IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK = 0xFFE00000 # macro +IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT = 0x0 # macro +IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK = 0x0000FFFF # macro +IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT = 0x0 # macro +IH_VF_RB_STATUS2__RB_FULL_VF_MASK = 0x0000FFFF # macro +IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT = 0x0 # macro +IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK = 0x0000FFFF # macro +IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT = 0x0 # macro +IH_VF_RB1_STATUS2__RB_FULL_VF_MASK = 0x0000FFFF # macro +IH_RB_STATUS__RB_FULL__SHIFT = 0x0 # macro +IH_RB_STATUS__RB_FULL_DRAIN__SHIFT = 0x1 # macro +IH_RB_STATUS__RB_OVERFLOW__SHIFT = 0x2 # macro +IH_RB_STATUS__RB1_FULL__SHIFT = 0x4 # macro +IH_RB_STATUS__RB1_FULL_DRAIN__SHIFT = 0x5 # macro +IH_RB_STATUS__RB1_OVERFLOW__SHIFT = 0x6 # macro +IH_RB_STATUS__RB_FULL_MASK = 0x00000001 # macro +IH_RB_STATUS__RB_FULL_DRAIN_MASK = 0x00000002 # macro +IH_RB_STATUS__RB_OVERFLOW_MASK = 0x00000004 # macro +IH_RB_STATUS__RB1_FULL_MASK = 0x00000010 # macro +IH_RB_STATUS__RB1_FULL_DRAIN_MASK = 0x00000020 # macro +IH_RB_STATUS__RB1_OVERFLOW_MASK = 0x00000040 # macro +IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT = 0x0 # macro +IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT = 0x3 # macro +IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT = 0x4 # macro +IH_INT_FLOOD_CNTL__HIGHWATER_MASK = 0x00000007 # macro +IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK = 0x00000008 # macro +IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK = 0x00000010 # macro +IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT = 0x0 # macro +IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT = 0x1f # macro +IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK = 0x0000FFFF # macro +IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK = 0x80000000 # macro +IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT = 0x0 # macro +IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT = 0x1f # macro +IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK = 0x0000FFFF # macro +IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK = 0x80000000 # macro +IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT = 0x0 # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT = 0x8 # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT = 0x10 # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT = 0x18 # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT = 0x1d # macro +IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT = 0x1e # macro +IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK = 0x000000FF # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK = 0x0000FF00 # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK = 0x00FF0000 # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK = 0x0F000000 # macro +IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK = 0x20000000 # macro +IH_INT_FLOOD_STATUS__INT_DROPPED_MASK = 0x40000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT = 0x1 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT = 0x2 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT = 0x3 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT = 0x4 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT = 0x5 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT = 0x6 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT = 0x7 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT = 0x8 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT = 0x9 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT = 0xa # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT = 0xb # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT = 0xc # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT = 0xd # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT = 0xe # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT = 0xf # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT = 0x10 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT = 0x11 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT = 0x12 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT = 0x13 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT = 0x14 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT = 0x15 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT = 0x16 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT = 0x17 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT = 0x18 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT = 0x19 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT = 0x1a # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT = 0x1b # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT = 0x1c # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT = 0x1d # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT = 0x1e # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT = 0x1f # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK = 0x00000002 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK = 0x00000004 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK = 0x00000008 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK = 0x00000010 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK = 0x00000020 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK = 0x00000040 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK = 0x00000080 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK = 0x00000100 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK = 0x00000200 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK = 0x00000400 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK = 0x00000800 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK = 0x00001000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK = 0x00002000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK = 0x00004000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK = 0x00008000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK = 0x00010000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK = 0x00020000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK = 0x00040000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK = 0x00080000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK = 0x00100000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK = 0x00200000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK = 0x00400000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK = 0x00800000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK = 0x01000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK = 0x02000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK = 0x04000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK = 0x08000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK = 0x10000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK = 0x20000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK = 0x40000000 # macro +IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK = 0x80000000 # macro +IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT = 0x17 # macro +IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE__SHIFT = 0x18 # macro +IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT = 0x19 # macro +IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT = 0x1a # macro +IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT = 0x1b # macro +IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT = 0x1c # macro +IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT = 0x1d # macro +IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT = 0x1e # macro +IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT = 0x1f # macro +IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK = 0x00800000 # macro +IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE_MASK = 0x01000000 # macro +IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK = 0x02000000 # macro +IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK = 0x04000000 # macro +IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK = 0x08000000 # macro +IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK = 0x10000000 # macro +IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK = 0x20000000 # macro +IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK = 0x40000000 # macro +IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK = 0x80000000 # macro +IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT = 0x0 # macro +IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT = 0x1 # macro +IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT = 0x2 # macro +IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT = 0x3 # macro +IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT = 0x4 # macro +IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT = 0x5 # macro +IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT = 0x6 # macro +IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT = 0x7 # macro +IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT = 0x8 # macro +IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT = 0x9 # macro +IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT = 0xa # macro +IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT = 0xb # macro +IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT = 0xc # macro +IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT = 0xd # macro +IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT = 0xe # macro +IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT = 0xf # macro +IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT = 0x10 # macro +IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT = 0x11 # macro +IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT = 0x12 # macro +IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT = 0x13 # macro +IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT = 0x14 # macro +IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT = 0x15 # macro +IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT = 0x16 # macro +IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT = 0x17 # macro +IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT = 0x18 # macro +IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT = 0x19 # macro +IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT = 0x1a # macro +IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT = 0x1b # macro +IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT = 0x1c # macro +IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT = 0x1d # macro +IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT = 0x1e # macro +IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT = 0x1f # macro +IH_INT_FLAGS__CLIENT_0_FLAG_MASK = 0x00000001 # macro +IH_INT_FLAGS__CLIENT_1_FLAG_MASK = 0x00000002 # macro +IH_INT_FLAGS__CLIENT_2_FLAG_MASK = 0x00000004 # macro +IH_INT_FLAGS__CLIENT_3_FLAG_MASK = 0x00000008 # macro +IH_INT_FLAGS__CLIENT_4_FLAG_MASK = 0x00000010 # macro +IH_INT_FLAGS__CLIENT_5_FLAG_MASK = 0x00000020 # macro +IH_INT_FLAGS__CLIENT_6_FLAG_MASK = 0x00000040 # macro +IH_INT_FLAGS__CLIENT_7_FLAG_MASK = 0x00000080 # macro +IH_INT_FLAGS__CLIENT_8_FLAG_MASK = 0x00000100 # macro +IH_INT_FLAGS__CLIENT_9_FLAG_MASK = 0x00000200 # macro +IH_INT_FLAGS__CLIENT_10_FLAG_MASK = 0x00000400 # macro +IH_INT_FLAGS__CLIENT_11_FLAG_MASK = 0x00000800 # macro +IH_INT_FLAGS__CLIENT_12_FLAG_MASK = 0x00001000 # macro +IH_INT_FLAGS__CLIENT_13_FLAG_MASK = 0x00002000 # macro +IH_INT_FLAGS__CLIENT_14_FLAG_MASK = 0x00004000 # macro +IH_INT_FLAGS__CLIENT_15_FLAG_MASK = 0x00008000 # macro +IH_INT_FLAGS__CLIENT_16_FLAG_MASK = 0x00010000 # macro +IH_INT_FLAGS__CLIENT_17_FLAG_MASK = 0x00020000 # macro +IH_INT_FLAGS__CLIENT_18_FLAG_MASK = 0x00040000 # macro +IH_INT_FLAGS__CLIENT_19_FLAG_MASK = 0x00080000 # macro +IH_INT_FLAGS__CLIENT_20_FLAG_MASK = 0x00100000 # macro +IH_INT_FLAGS__CLIENT_21_FLAG_MASK = 0x00200000 # macro +IH_INT_FLAGS__CLIENT_22_FLAG_MASK = 0x00400000 # macro +IH_INT_FLAGS__CLIENT_23_FLAG_MASK = 0x00800000 # macro +IH_INT_FLAGS__CLIENT_24_FLAG_MASK = 0x01000000 # macro +IH_INT_FLAGS__CLIENT_25_FLAG_MASK = 0x02000000 # macro +IH_INT_FLAGS__CLIENT_26_FLAG_MASK = 0x04000000 # macro +IH_INT_FLAGS__CLIENT_27_FLAG_MASK = 0x08000000 # macro +IH_INT_FLAGS__CLIENT_28_FLAG_MASK = 0x10000000 # macro +IH_INT_FLAGS__CLIENT_29_FLAG_MASK = 0x20000000 # macro +IH_INT_FLAGS__CLIENT_30_FLAG_MASK = 0x40000000 # macro +IH_INT_FLAGS__CLIENT_31_FLAG_MASK = 0x80000000 # macro +IH_LAST_INT_INFO0__CLIENT_ID__SHIFT = 0x0 # macro +IH_LAST_INT_INFO0__SOURCE_ID__SHIFT = 0x8 # macro +IH_LAST_INT_INFO0__RING_ID__SHIFT = 0x10 # macro +IH_LAST_INT_INFO0__VM_ID__SHIFT = 0x18 # macro +IH_LAST_INT_INFO0__VMID_TYPE__SHIFT = 0x1f # macro +IH_LAST_INT_INFO0__CLIENT_ID_MASK = 0x000000FF # macro +IH_LAST_INT_INFO0__SOURCE_ID_MASK = 0x0000FF00 # macro +IH_LAST_INT_INFO0__RING_ID_MASK = 0x00FF0000 # macro +IH_LAST_INT_INFO0__VM_ID_MASK = 0x0F000000 # macro +IH_LAST_INT_INFO0__VMID_TYPE_MASK = 0x80000000 # macro +IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT = 0x0 # macro +IH_LAST_INT_INFO1__CONTEXT_ID_MASK = 0xFFFFFFFF # macro +IH_LAST_INT_INFO2__PAS_ID__SHIFT = 0x0 # macro +IH_LAST_INT_INFO2__VF_ID__SHIFT = 0x10 # macro +IH_LAST_INT_INFO2__VF__SHIFT = 0x17 # macro +IH_LAST_INT_INFO2__PAS_ID_MASK = 0x0000FFFF # macro +IH_LAST_INT_INFO2__VF_ID_MASK = 0x000F0000 # macro +IH_LAST_INT_INFO2__VF_MASK = 0x00800000 # macro +IH_SCRATCH__DATA__SHIFT = 0x0 # macro +IH_SCRATCH__DATA_MASK = 0xFFFFFFFF # macro +IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT = 0x0 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT = 0x1 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT = 0x2 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT = 0x3 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT = 0x4 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT = 0x5 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT = 0x6 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT = 0x7 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT = 0x8 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT = 0x9 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT = 0xa # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT = 0xb # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT = 0xc # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT = 0xd # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT = 0xe # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT = 0xf # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT = 0x10 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT = 0x11 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT = 0x12 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT = 0x13 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT = 0x14 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT = 0x15 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT = 0x16 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT = 0x17 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT = 0x18 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT = 0x19 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT = 0x1a # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT = 0x1b # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT = 0x1c # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT = 0x1d # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT = 0x1e # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT = 0x1f # macro +IH_CLIENT_CREDIT_ERROR__CLEAR_MASK = 0x00000001 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK = 0x00000002 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK = 0x00000004 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK = 0x00000008 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK = 0x00000010 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK = 0x00000020 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK = 0x00000040 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK = 0x00000080 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK = 0x00000100 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK = 0x00000200 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK = 0x00000400 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK = 0x00000800 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK = 0x00001000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK = 0x00002000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK = 0x00004000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK = 0x00008000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK = 0x00010000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK = 0x00020000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK = 0x00040000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK = 0x00080000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK = 0x00100000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK = 0x00200000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK = 0x00400000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK = 0x00800000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK = 0x01000000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK = 0x02000000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK = 0x04000000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK = 0x08000000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK = 0x10000000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK = 0x20000000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK = 0x40000000 # macro +IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK = 0x80000000 # macro +IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT = 0x0 # macro +IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT = 0x8 # macro +IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT = 0x10 # macro +IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK = 0x00000001 # macro +IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK = 0x0000FF00 # macro +IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK = 0x03FF0000 # macro +IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT = 0x1 # macro +IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT = 0x2 # macro +IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT = 0x3 # macro +IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT = 0x4 # macro +IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT = 0x5 # macro +IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT = 0x6 # macro +IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT = 0x7 # macro +IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT = 0x8 # macro +IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT = 0x9 # macro +IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT = 0xa # macro +IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT = 0xb # macro +IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT = 0xc # macro +IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT = 0xd # macro +IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT = 0xe # macro +IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT = 0xf # macro +IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT = 0x10 # macro +IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT = 0x11 # macro +IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT = 0x12 # macro +IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT = 0x13 # macro +IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT = 0x14 # macro +IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT = 0x15 # macro +IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT = 0x16 # macro +IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT = 0x17 # macro +IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT = 0x18 # macro +IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT = 0x19 # macro +IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT = 0x1a # macro +IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT = 0x1b # macro +IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT = 0x1c # macro +IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT = 0x1d # macro +IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT = 0x1e # macro +IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT = 0x1f # macro +IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK = 0x00000002 # macro +IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK = 0x00000004 # macro +IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK = 0x00000008 # macro +IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK = 0x00000010 # macro +IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK = 0x00000020 # macro +IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK = 0x00000040 # macro +IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK = 0x00000080 # macro +IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK = 0x00000100 # macro +IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK = 0x00000200 # macro +IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK = 0x00000400 # macro +IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK = 0x00000800 # macro +IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK = 0x00001000 # macro +IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK = 0x00002000 # macro +IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK = 0x00004000 # macro +IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK = 0x00008000 # macro +IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK = 0x00010000 # macro +IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK = 0x00020000 # macro +IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK = 0x00040000 # macro +IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK = 0x00080000 # macro +IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK = 0x00100000 # macro +IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK = 0x00200000 # macro +IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK = 0x00400000 # macro +IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK = 0x00800000 # macro +IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK = 0x01000000 # macro +IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK = 0x02000000 # macro +IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK = 0x04000000 # macro +IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK = 0x08000000 # macro +IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK = 0x10000000 # macro +IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK = 0x20000000 # macro +IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK = 0x40000000 # macro +IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK = 0x80000000 # macro +IH_MMHUB_ERROR__IH_BRESP_01__SHIFT = 0x1 # macro +IH_MMHUB_ERROR__IH_BRESP_10__SHIFT = 0x2 # macro +IH_MMHUB_ERROR__IH_BRESP_11__SHIFT = 0x3 # macro +IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT = 0x5 # macro +IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT = 0x6 # macro +IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT = 0x7 # macro +IH_MMHUB_ERROR__IH_BRESP_01_MASK = 0x00000002 # macro +IH_MMHUB_ERROR__IH_BRESP_10_MASK = 0x00000004 # macro +IH_MMHUB_ERROR__IH_BRESP_11_MASK = 0x00000008 # macro +IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK = 0x00000020 # macro +IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK = 0x00000040 # macro +IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK = 0x00000080 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT = 0x0 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT = 0x1 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT = 0x2 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT = 0x3 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT = 0x4 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT = 0x8 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY__SHIFT = 0xe # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT = 0x10 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT = 0x11 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT = 0x12 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT = 0x13 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT = 0x14 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT = 0x18 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY__SHIFT = 0x1e # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK = 0x00000001 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK = 0x00000002 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK = 0x00000004 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK = 0x00000008 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK = 0x00000070 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK = 0x00003F00 # macro +IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY_MASK = 0x0000C000 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK = 0x00010000 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK = 0x00020000 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK = 0x00040000 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK = 0x00080000 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK = 0x00700000 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK = 0x3F000000 # macro +IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY_MASK = 0xC0000000 # macro +IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT = 0x0 # macro +IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK = 0x0000FFFF # macro +IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT = 0x0 # macro +IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK = 0x0000FFFF # macro +IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT = 0x0 # macro +IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK = 0x0000FFFF # macro +IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT = 0x0 # macro +IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT = 0x8 # macro +IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT = 0x10 # macro +IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE__SHIFT = 0x11 # macro +IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE__SHIFT = 0x12 # macro +IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT = 0x14 # macro +IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK = 0x0000001F # macro +IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK = 0x00003F00 # macro +IH_RETRY_INT_CAM_CNTL__ENABLE_MASK = 0x00010000 # macro +IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE_MASK = 0x00020000 # macro +IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE_MASK = 0x00040000 # macro +IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK = 0x00300000 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT = 0x0 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT = 0x1 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT = 0x2 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT = 0x3 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT = 0x4 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT = 0x8 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY__SHIFT = 0xe # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK = 0x00000001 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK = 0x00000002 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK = 0x00000004 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK = 0x00000008 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK = 0x00000070 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK = 0x00003F00 # macro +IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY_MASK = 0x0000C000 # macro +IH_MSI_STORM_CTRL__DELAY__SHIFT = 0x0 # macro +IH_MSI_STORM_CTRL__DELAY_MASK = 0x00000FFF # macro +IH_MSI_STORM_CLIENT_INDEX__INDEX__SHIFT = 0x0 # macro +IH_MSI_STORM_CLIENT_INDEX__INDEX_MASK = 0x00000007 # macro +IH_MSI_STORM_CLIENT_DATA__CLIENT_ID__SHIFT = 0x0 # macro +IH_MSI_STORM_CLIENT_DATA__SOURCE_ID__SHIFT = 0x8 # macro +IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT = 0x10 # macro +IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE__SHIFT = 0x11 # macro +IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID__SHIFT = 0x1f # macro +IH_MSI_STORM_CLIENT_DATA__CLIENT_ID_MASK = 0x000000FF # macro +IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MASK = 0x0000FF00 # macro +IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE_MASK = 0x00010000 # macro +IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE_MASK = 0x00020000 # macro +IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID_MASK = 0x80000000 # macro +IH_REGISTER_LAST_PART2__RESERVED__SHIFT = 0x0 # macro +IH_REGISTER_LAST_PART2__RESERVED_MASK = 0xFFFFFFFF # macro +SEM_MAILBOX__HOSTPORT__SHIFT = 0x0 # macro +SEM_MAILBOX__RESERVED__SHIFT = 0x10 # macro +SEM_MAILBOX__HOSTPORT_MASK = 0x0000FFFF # macro +SEM_MAILBOX__RESERVED_MASK = 0xFFFF0000 # macro +SEM_MAILBOX_CLEAR__CLEAR__SHIFT = 0x0 # macro +SEM_MAILBOX_CLEAR__RESERVED__SHIFT = 0x10 # macro +SEM_MAILBOX_CLEAR__CLEAR_MASK = 0x0000FFFF # macro +SEM_MAILBOX_CLEAR__RESERVED_MASK = 0xFFFF0000 # macro +SEM_REGISTER_LAST_PART2__RESERVED__SHIFT = 0x0 # macro +SEM_REGISTER_LAST_PART2__RESERVED_MASK = 0xFFFFFFFF # macro +IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT = 0x0 # macro +IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK = 0x0000003F # macro +IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT = 0x0 # macro +IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK = 0x00000007 # macro +IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT = 0x0 # macro +IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT = 0x8 # macro +IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT = 0x10 # macro +IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK = 0x000000FF # macro +IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK = 0x0000FF00 # macro +IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK = 0x00010000 # macro +IH_CLIENT_CFG_INDEX__INDEX__SHIFT = 0x0 # macro +IH_CLIENT_CFG_INDEX__INDEX_MASK = 0x0000001F # macro +IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT = 0x12 # macro +IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT = 0x16 # macro +IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT = 0x19 # macro +IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK = 0x000C0000 # macro +IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK = 0x00C00000 # macro +IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK = 0x02000000 # macro +IH_CID_REMAP_INDEX__INDEX__SHIFT = 0x0 # macro +IH_CID_REMAP_INDEX__INDEX_MASK = 0x00000003 # macro +IH_CID_REMAP_DATA__CLIENT_ID__SHIFT = 0x0 # macro +IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT = 0x8 # macro +IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT = 0x18 # macro +IH_CID_REMAP_DATA__CLIENT_ID_MASK = 0x000000FF # macro +IH_CID_REMAP_DATA__INITIATOR_ID_MASK = 0x0003FF00 # macro +IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK = 0xFF000000 # macro +IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT = 0x2 # macro +IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT = 0x3 # macro +IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT = 0x4 # macro +IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK = 0x00000004 # macro +IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK = 0x00000008 # macro +IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK = 0x00000010 # macro +IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT = 0x0 # macro +IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT = 0x1 # macro +IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT = 0x2 # macro +IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT = 0x3 # macro +IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT = 0x4 # macro +IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT = 0x5 # macro +IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT = 0x6 # macro +IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT = 0x8 # macro +IH_INT_DROP_CNTL__INT_DROPPED__SHIFT = 0x10 # macro +IH_INT_DROP_CNTL__INT_DROP_EN_MASK = 0x00000001 # macro +IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK = 0x00000002 # macro +IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK = 0x00000004 # macro +IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK = 0x00000008 # macro +IH_INT_DROP_CNTL__VF_MATCH_EN_MASK = 0x00000010 # macro +IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK = 0x00000020 # macro +IH_INT_DROP_CNTL__INT_DROP_MODE_MASK = 0x000000C0 # macro +IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK = 0x00000100 # macro +IH_INT_DROP_CNTL__INT_DROPPED_MASK = 0x00010000 # macro +IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT = 0x0 # macro +IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT = 0x8 # macro +IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT = 0x10 # macro +IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT = 0x17 # macro +IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT = 0x18 # macro +IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK = 0x000000FF # macro +IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK = 0x0000FF00 # macro +IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK = 0x001F0000 # macro +IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK = 0x00800000 # macro +IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK = 0xFF000000 # macro +IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT = 0x0 # macro +IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK = 0xFFFFFFFF # macro +IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT = 0x0 # macro +IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT = 0x8 # macro +IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT = 0x10 # macro +IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT = 0x17 # macro +IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT = 0x18 # macro +IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK = 0x000000FF # macro +IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK = 0x0000FF00 # macro +IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK = 0x001F0000 # macro +IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK = 0x00800000 # macro +IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK = 0xFF000000 # macro +IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT = 0x0 # macro +IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK = 0xFFFFFFFF # macro +IH_REGISTER_LAST_PART1__RESERVED__SHIFT = 0x0 # macro +IH_REGISTER_LAST_PART1__RESERVED_MASK = 0xFFFFFFFF # macro +__all__ = \ + ['IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK', + 'IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT', + 'IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK', + 'IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT', + 'IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK', + 'IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT', + 'IH_CID_REMAP_DATA__CLIENT_ID_MASK', + 'IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK', + 'IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT', + 'IH_CID_REMAP_DATA__CLIENT_ID__SHIFT', + 'IH_CID_REMAP_DATA__INITIATOR_ID_MASK', + 'IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT', + 'IH_CID_REMAP_INDEX__INDEX_MASK', + 'IH_CID_REMAP_INDEX__INDEX__SHIFT', + 'IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK', + 'IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT', + 'IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK', + 'IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT', + 'IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK', + 'IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT', + 'IH_CLIENT_CFG_INDEX__INDEX_MASK', + 'IH_CLIENT_CFG_INDEX__INDEX__SHIFT', + 'IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK', + 'IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLEAR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK', + 'IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT', + 'IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK', + 'IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT', + 'IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK', + 'IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT', + 'IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK', + 'IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT', + 'IH_CNTL__IH_FIFO_HIGHWATER_MASK', + 'IH_CNTL__IH_FIFO_HIGHWATER__SHIFT', + 'IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK', + 'IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT', + 'IH_CNTL__MC_WR_CLEAN_CNT_MASK', + 'IH_CNTL__MC_WR_CLEAN_CNT__SHIFT', + 'IH_CNTL__WPTR_WRITEBACK_TIMER_MASK', + 'IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT', + 'IH_COOKIE_0__CLIENT_ID_MASK', 'IH_COOKIE_0__CLIENT_ID__SHIFT', + 'IH_COOKIE_0__RESERVED_MASK', 'IH_COOKIE_0__RESERVED__SHIFT', + 'IH_COOKIE_0__RING_ID_MASK', 'IH_COOKIE_0__RING_ID__SHIFT', + 'IH_COOKIE_0__SOURCE_ID_MASK', 'IH_COOKIE_0__SOURCE_ID__SHIFT', + 'IH_COOKIE_0__VMID_TYPE_MASK', 'IH_COOKIE_0__VMID_TYPE__SHIFT', + 'IH_COOKIE_0__VM_ID_MASK', 'IH_COOKIE_0__VM_ID__SHIFT', + 'IH_COOKIE_1__TIMESTAMP_31_0_MASK', + 'IH_COOKIE_1__TIMESTAMP_31_0__SHIFT', + 'IH_COOKIE_2__RESERVED_MASK', 'IH_COOKIE_2__RESERVED__SHIFT', + 'IH_COOKIE_2__TIMESTAMP_47_32_MASK', + 'IH_COOKIE_2__TIMESTAMP_47_32__SHIFT', + 'IH_COOKIE_2__TIMESTAMP_SRC_MASK', + 'IH_COOKIE_2__TIMESTAMP_SRC__SHIFT', + 'IH_COOKIE_3__PASID_SRC_MASK', 'IH_COOKIE_3__PASID_SRC__SHIFT', + 'IH_COOKIE_3__PAS_ID_MASK', 'IH_COOKIE_3__PAS_ID__SHIFT', + 'IH_COOKIE_3__RESERVED_MASK', 'IH_COOKIE_3__RESERVED__SHIFT', + 'IH_COOKIE_4__CONTEXT_ID_31_0_MASK', + 'IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT', + 'IH_COOKIE_5__CONTEXT_ID_63_32_MASK', + 'IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT', + 'IH_COOKIE_6__CONTEXT_ID_95_64_MASK', + 'IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT', + 'IH_COOKIE_7__CONTEXT_ID_128_96_MASK', + 'IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT', + 'IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK', + 'IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT', + 'IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK', + 'IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT', + 'IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK', + 'IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT', + 'IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK', + 'IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT', + 'IH_DOORBELL_RETRY_CAM__ENABLE_MASK', + 'IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT', + 'IH_DOORBELL_RETRY_CAM__OFFSET_MASK', + 'IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT', + 'IH_DOORBELL_RPTR_RING1__ENABLE_MASK', + 'IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT', + 'IH_DOORBELL_RPTR_RING1__OFFSET_MASK', + 'IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT', + 'IH_DOORBELL_RPTR__ENABLE_MASK', + 'IH_DOORBELL_RPTR__ENABLE__SHIFT', + 'IH_DOORBELL_RPTR__OFFSET_MASK', + 'IH_DOORBELL_RPTR__OFFSET__SHIFT', + 'IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK', + 'IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT', + 'IH_DSM_MATCH_FCN_ID__PF_VF_MASK', + 'IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT', + 'IH_DSM_MATCH_FCN_ID__VF_ID_MASK', + 'IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT', + 'IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK', + 'IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT', + 'IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK', + 'IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT', + 'IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK', + 'IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT', + 'IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK', + 'IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT', + 'IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK', + 'IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT', + 'IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK', + 'IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT', + 'IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK', + 'IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT', + 'IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK', + 'IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT', + 'IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK', + 'IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT', + 'IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK', + 'IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT', + 'IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK', + 'IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT', + 'IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK', + 'IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT', + 'IH_INT_DROP_CNTL__INT_DROPPED_MASK', + 'IH_INT_DROP_CNTL__INT_DROPPED__SHIFT', + 'IH_INT_DROP_CNTL__INT_DROP_EN_MASK', + 'IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT', + 'IH_INT_DROP_CNTL__INT_DROP_MODE_MASK', + 'IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT', + 'IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK', + 'IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT', + 'IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK', + 'IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT', + 'IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK', + 'IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT', + 'IH_INT_DROP_CNTL__VF_MATCH_EN_MASK', + 'IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT', + 'IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK', + 'IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT', + 'IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK', + 'IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT', + 'IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK', + 'IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT', + 'IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK', + 'IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT', + 'IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK', + 'IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT', + 'IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK', + 'IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT', + 'IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK', + 'IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT', + 'IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK', + 'IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT', + 'IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK', + 'IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT', + 'IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK', + 'IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT', + 'IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK', + 'IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT', + 'IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK', + 'IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT', + 'IH_INT_FLAGS__CLIENT_0_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_10_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_11_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_12_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_13_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_14_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_15_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_16_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_17_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_18_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_19_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_1_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_20_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_21_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_22_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_23_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_24_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_25_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_26_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_27_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_28_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_29_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_2_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_30_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_31_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_3_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_4_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_5_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_6_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_7_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_8_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT', + 'IH_INT_FLAGS__CLIENT_9_FLAG_MASK', + 'IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT', + 'IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK', + 'IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT', + 'IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK', + 'IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT', + 'IH_INT_FLOOD_CNTL__HIGHWATER_MASK', + 'IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK', + 'IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT', + 'IH_INT_FLOOD_STATUS__INT_DROPPED_MASK', + 'IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT', + 'IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK', + 'IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT', + 'IH_LAST_INT_INFO0__CLIENT_ID_MASK', + 'IH_LAST_INT_INFO0__CLIENT_ID__SHIFT', + 'IH_LAST_INT_INFO0__RING_ID_MASK', + 'IH_LAST_INT_INFO0__RING_ID__SHIFT', + 'IH_LAST_INT_INFO0__SOURCE_ID_MASK', + 'IH_LAST_INT_INFO0__SOURCE_ID__SHIFT', + 'IH_LAST_INT_INFO0__VMID_TYPE_MASK', + 'IH_LAST_INT_INFO0__VMID_TYPE__SHIFT', + 'IH_LAST_INT_INFO0__VM_ID_MASK', + 'IH_LAST_INT_INFO0__VM_ID__SHIFT', + 'IH_LAST_INT_INFO1__CONTEXT_ID_MASK', + 'IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT', + 'IH_LAST_INT_INFO2__PAS_ID_MASK', + 'IH_LAST_INT_INFO2__PAS_ID__SHIFT', + 'IH_LAST_INT_INFO2__VF_ID_MASK', + 'IH_LAST_INT_INFO2__VF_ID__SHIFT', 'IH_LAST_INT_INFO2__VF_MASK', + 'IH_LAST_INT_INFO2__VF__SHIFT', + 'IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK', + 'IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT', + 'IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK', + 'IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT', + 'IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK', + 'IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT', + 'IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK', + 'IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT', + 'IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK', + 'IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY_MASK', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY__SHIFT', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK', + 'IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY_MASK', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY__SHIFT', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK', + 'IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY_MASK', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY__SHIFT', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK', + 'IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT', + 'IH_MMHUB_ERROR__IH_BRESP_01_MASK', + 'IH_MMHUB_ERROR__IH_BRESP_01__SHIFT', + 'IH_MMHUB_ERROR__IH_BRESP_10_MASK', + 'IH_MMHUB_ERROR__IH_BRESP_10__SHIFT', + 'IH_MMHUB_ERROR__IH_BRESP_11_MASK', + 'IH_MMHUB_ERROR__IH_BRESP_11__SHIFT', + 'IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK', + 'IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT', + 'IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK', + 'IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT', + 'IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK', + 'IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT', + 'IH_MSI_STORM_CLIENT_DATA__CLIENT_ID_MASK', + 'IH_MSI_STORM_CLIENT_DATA__CLIENT_ID__SHIFT', + 'IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID_MASK', + 'IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID__SHIFT', + 'IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MASK', + 'IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE_MASK', + 'IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT', + 'IH_MSI_STORM_CLIENT_DATA__SOURCE_ID__SHIFT', + 'IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE_MASK', + 'IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE__SHIFT', + 'IH_MSI_STORM_CLIENT_INDEX__INDEX_MASK', + 'IH_MSI_STORM_CLIENT_INDEX__INDEX__SHIFT', + 'IH_MSI_STORM_CTRL__DELAY_MASK', + 'IH_MSI_STORM_CTRL__DELAY__SHIFT', + 'IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK', + 'IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT', + 'IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK', + 'IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT', + 'IH_PERFMON_CNTL__CLEAR0_MASK', 'IH_PERFMON_CNTL__CLEAR0__SHIFT', + 'IH_PERFMON_CNTL__CLEAR1_MASK', 'IH_PERFMON_CNTL__CLEAR1__SHIFT', + 'IH_PERFMON_CNTL__ENABLE0_MASK', + 'IH_PERFMON_CNTL__ENABLE0__SHIFT', + 'IH_PERFMON_CNTL__ENABLE1_MASK', + 'IH_PERFMON_CNTL__ENABLE1__SHIFT', + 'IH_PERFMON_CNTL__PERF_SEL0_MASK', + 'IH_PERFMON_CNTL__PERF_SEL0__SHIFT', + 'IH_PERFMON_CNTL__PERF_SEL1_MASK', + 'IH_PERFMON_CNTL__PERF_SEL1__SHIFT', + 'IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK', + 'IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK', + 'IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT', + 'IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT', + 'IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK', + 'IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK', + 'IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT', + 'IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT', + 'IH_RB_BASE_HI_RING1__ADDR_MASK', + 'IH_RB_BASE_HI_RING1__ADDR__SHIFT', 'IH_RB_BASE_HI__ADDR_MASK', + 'IH_RB_BASE_HI__ADDR__SHIFT', 'IH_RB_BASE_RING1__ADDR_MASK', + 'IH_RB_BASE_RING1__ADDR__SHIFT', 'IH_RB_BASE__ADDR_MASK', + 'IH_RB_BASE__ADDR__SHIFT', + 'IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK', + 'IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT', + 'IH_RB_CNTL_RING1__MC_RO_MASK', 'IH_RB_CNTL_RING1__MC_RO__SHIFT', + 'IH_RB_CNTL_RING1__MC_SNOOP_MASK', + 'IH_RB_CNTL_RING1__MC_SNOOP__SHIFT', + 'IH_RB_CNTL_RING1__MC_SPACE_MASK', + 'IH_RB_CNTL_RING1__MC_SPACE__SHIFT', + 'IH_RB_CNTL_RING1__MC_SWAP_MASK', + 'IH_RB_CNTL_RING1__MC_SWAP__SHIFT', + 'IH_RB_CNTL_RING1__MC_VMID_MASK', + 'IH_RB_CNTL_RING1__MC_VMID__SHIFT', + 'IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK', + 'IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT', + 'IH_RB_CNTL_RING1__RB_ENABLE_MASK', + 'IH_RB_CNTL_RING1__RB_ENABLE__SHIFT', + 'IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK', + 'IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT', + 'IH_RB_CNTL_RING1__RB_SIZE_MASK', + 'IH_RB_CNTL_RING1__RB_SIZE__SHIFT', + 'IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK', + 'IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT', + 'IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK', + 'IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT', + 'IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK', + 'IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT', + 'IH_RB_CNTL__ENABLE_INTR_MASK', 'IH_RB_CNTL__ENABLE_INTR__SHIFT', + 'IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK', + 'IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT', 'IH_RB_CNTL__MC_RO_MASK', + 'IH_RB_CNTL__MC_RO__SHIFT', 'IH_RB_CNTL__MC_SNOOP_MASK', + 'IH_RB_CNTL__MC_SNOOP__SHIFT', 'IH_RB_CNTL__MC_SPACE_MASK', + 'IH_RB_CNTL__MC_SPACE__SHIFT', 'IH_RB_CNTL__MC_SWAP_MASK', + 'IH_RB_CNTL__MC_SWAP__SHIFT', 'IH_RB_CNTL__MC_VMID_MASK', + 'IH_RB_CNTL__MC_VMID__SHIFT', 'IH_RB_CNTL__PAGE_RB_CLEAR_MASK', + 'IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT', 'IH_RB_CNTL__RB_ENABLE_MASK', + 'IH_RB_CNTL__RB_ENABLE__SHIFT', + 'IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK', + 'IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT', + 'IH_RB_CNTL__RB_SIZE_MASK', 'IH_RB_CNTL__RB_SIZE__SHIFT', + 'IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK', + 'IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT', + 'IH_RB_CNTL__RPTR_REARM_MASK', 'IH_RB_CNTL__RPTR_REARM__SHIFT', + 'IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK', + 'IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT', + 'IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK', + 'IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT', + 'IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK', + 'IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT', + 'IH_RB_RPTR_RING1__OFFSET_MASK', + 'IH_RB_RPTR_RING1__OFFSET__SHIFT', 'IH_RB_RPTR__OFFSET_MASK', + 'IH_RB_RPTR__OFFSET__SHIFT', 'IH_RB_STATUS__RB1_FULL_DRAIN_MASK', + 'IH_RB_STATUS__RB1_FULL_DRAIN__SHIFT', + 'IH_RB_STATUS__RB1_FULL_MASK', 'IH_RB_STATUS__RB1_FULL__SHIFT', + 'IH_RB_STATUS__RB1_OVERFLOW_MASK', + 'IH_RB_STATUS__RB1_OVERFLOW__SHIFT', + 'IH_RB_STATUS__RB_FULL_DRAIN_MASK', + 'IH_RB_STATUS__RB_FULL_DRAIN__SHIFT', + 'IH_RB_STATUS__RB_FULL_MASK', 'IH_RB_STATUS__RB_FULL__SHIFT', + 'IH_RB_STATUS__RB_OVERFLOW_MASK', + 'IH_RB_STATUS__RB_OVERFLOW__SHIFT', + 'IH_RB_WPTR_ADDR_HI__ADDR_MASK', + 'IH_RB_WPTR_ADDR_HI__ADDR__SHIFT', + 'IH_RB_WPTR_ADDR_LO__ADDR_MASK', + 'IH_RB_WPTR_ADDR_LO__ADDR__SHIFT', + 'IH_RB_WPTR_RING1__OFFSET_MASK', + 'IH_RB_WPTR_RING1__OFFSET__SHIFT', + 'IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK', + 'IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT', + 'IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK', + 'IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT', + 'IH_RB_WPTR_RING1__RB_OVERFLOW_MASK', + 'IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT', 'IH_RB_WPTR__OFFSET_MASK', + 'IH_RB_WPTR__OFFSET__SHIFT', 'IH_RB_WPTR__RB_LEFT_NONE_MASK', + 'IH_RB_WPTR__RB_LEFT_NONE__SHIFT', + 'IH_RB_WPTR__RB_MAY_OVERFLOW_MASK', + 'IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT', + 'IH_RB_WPTR__RB_OVERFLOW_MASK', 'IH_RB_WPTR__RB_OVERFLOW__SHIFT', + 'IH_REGISTER_LAST_PART0__RESERVED_MASK', + 'IH_REGISTER_LAST_PART0__RESERVED__SHIFT', + 'IH_REGISTER_LAST_PART1__RESERVED_MASK', + 'IH_REGISTER_LAST_PART1__RESERVED__SHIFT', + 'IH_REGISTER_LAST_PART2__RESERVED_MASK', + 'IH_REGISTER_LAST_PART2__RESERVED__SHIFT', + 'IH_RETRY_CAM_ACK__INDEX_MASK', 'IH_RETRY_CAM_ACK__INDEX__SHIFT', + 'IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK', + 'IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT', + 'IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK', + 'IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT', + 'IH_RETRY_INT_CAM_CNTL__ENABLE_MASK', + 'IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT', + 'IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE_MASK', + 'IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE__SHIFT', + 'IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE_MASK', + 'IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE__SHIFT', + 'IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK', + 'IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT', + 'IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK', + 'IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT', + 'IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK', + 'IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK', + 'IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT', + 'IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT', + 'IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK', + 'IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT', + 'IH_SCRATCH__DATA_MASK', 'IH_SCRATCH__DATA__SHIFT', + 'IH_STATUS__BIF_INTERRUPT_LINE_MASK', + 'IH_STATUS__BIF_INTERRUPT_LINE__SHIFT', + 'IH_STATUS__BUFFER_IDLE_MASK', 'IH_STATUS__BUFFER_IDLE__SHIFT', + 'IH_STATUS__IDLE_MASK', 'IH_STATUS__IDLE__SHIFT', + 'IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK', + 'IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT', + 'IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK', + 'IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT', + 'IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK', + 'IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT', + 'IH_STATUS__INPUT_IDLE_MASK', 'IH_STATUS__INPUT_IDLE__SHIFT', + 'IH_STATUS__MC_WR_CLEAN_PENDING_MASK', + 'IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT', + 'IH_STATUS__MC_WR_CLEAN_STALL_MASK', + 'IH_STATUS__MC_WR_CLEAN_STALL__SHIFT', + 'IH_STATUS__MC_WR_IDLE_MASK', 'IH_STATUS__MC_WR_IDLE__SHIFT', + 'IH_STATUS__MC_WR_STALL_MASK', 'IH_STATUS__MC_WR_STALL__SHIFT', + 'IH_STATUS__RB1_FULL_DRAIN_MASK', + 'IH_STATUS__RB1_FULL_DRAIN__SHIFT', 'IH_STATUS__RB1_FULL_MASK', + 'IH_STATUS__RB1_FULL__SHIFT', 'IH_STATUS__RB1_OVERFLOW_MASK', + 'IH_STATUS__RB1_OVERFLOW__SHIFT', 'IH_STATUS__RB_FULL_DRAIN_MASK', + 'IH_STATUS__RB_FULL_DRAIN__SHIFT', 'IH_STATUS__RB_FULL_MASK', + 'IH_STATUS__RB_FULL__SHIFT', 'IH_STATUS__RB_OVERFLOW_MASK', + 'IH_STATUS__RB_OVERFLOW__SHIFT', + 'IH_STATUS__RETRY_INT_CAM_IDLE_MASK', + 'IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT', + 'IH_STATUS__SELF_INT_GEN_IDLE_MASK', + 'IH_STATUS__SELF_INT_GEN_IDLE__SHIFT', + 'IH_STATUS__SWITCH_READY_MASK', 'IH_STATUS__SWITCH_READY__SHIFT', + 'IH_STATUS__ZSTATES_FENCE_MASK', + 'IH_STATUS__ZSTATES_FENCE__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK', + 'IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT', + 'IH_VERSION__MAJVER_MASK', 'IH_VERSION__MAJVER__SHIFT', + 'IH_VERSION__MINVER_MASK', 'IH_VERSION__MINVER__SHIFT', + 'IH_VERSION__REV_MASK', 'IH_VERSION__REV__SHIFT', + 'IH_VF_RB1_STATUS2__RB_FULL_VF_MASK', + 'IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT', + 'IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK', + 'IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT', + 'IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK', + 'IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT', + 'IH_VF_RB_STATUS2__RB_FULL_VF_MASK', + 'IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT', + 'IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK', + 'IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT', + 'IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK', + 'IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT', + 'IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK', + 'IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT', + 'IH_VMID_0_LUT_MM__PASID_MASK', 'IH_VMID_0_LUT_MM__PASID__SHIFT', + 'IH_VMID_0_LUT__PASID_MASK', 'IH_VMID_0_LUT__PASID__SHIFT', + 'IH_VMID_10_LUT_MM__PASID_MASK', + 'IH_VMID_10_LUT_MM__PASID__SHIFT', 'IH_VMID_10_LUT__PASID_MASK', + 'IH_VMID_10_LUT__PASID__SHIFT', 'IH_VMID_11_LUT_MM__PASID_MASK', + 'IH_VMID_11_LUT_MM__PASID__SHIFT', 'IH_VMID_11_LUT__PASID_MASK', + 'IH_VMID_11_LUT__PASID__SHIFT', 'IH_VMID_12_LUT_MM__PASID_MASK', + 'IH_VMID_12_LUT_MM__PASID__SHIFT', 'IH_VMID_12_LUT__PASID_MASK', + 'IH_VMID_12_LUT__PASID__SHIFT', 'IH_VMID_13_LUT_MM__PASID_MASK', + 'IH_VMID_13_LUT_MM__PASID__SHIFT', 'IH_VMID_13_LUT__PASID_MASK', + 'IH_VMID_13_LUT__PASID__SHIFT', 'IH_VMID_14_LUT_MM__PASID_MASK', + 'IH_VMID_14_LUT_MM__PASID__SHIFT', 'IH_VMID_14_LUT__PASID_MASK', + 'IH_VMID_14_LUT__PASID__SHIFT', 'IH_VMID_15_LUT_MM__PASID_MASK', + 'IH_VMID_15_LUT_MM__PASID__SHIFT', 'IH_VMID_15_LUT__PASID_MASK', + 'IH_VMID_15_LUT__PASID__SHIFT', 'IH_VMID_1_LUT_MM__PASID_MASK', + 'IH_VMID_1_LUT_MM__PASID__SHIFT', 'IH_VMID_1_LUT__PASID_MASK', + 'IH_VMID_1_LUT__PASID__SHIFT', 'IH_VMID_2_LUT_MM__PASID_MASK', + 'IH_VMID_2_LUT_MM__PASID__SHIFT', 'IH_VMID_2_LUT__PASID_MASK', + 'IH_VMID_2_LUT__PASID__SHIFT', 'IH_VMID_3_LUT_MM__PASID_MASK', + 'IH_VMID_3_LUT_MM__PASID__SHIFT', 'IH_VMID_3_LUT__PASID_MASK', + 'IH_VMID_3_LUT__PASID__SHIFT', 'IH_VMID_4_LUT_MM__PASID_MASK', + 'IH_VMID_4_LUT_MM__PASID__SHIFT', 'IH_VMID_4_LUT__PASID_MASK', + 'IH_VMID_4_LUT__PASID__SHIFT', 'IH_VMID_5_LUT_MM__PASID_MASK', + 'IH_VMID_5_LUT_MM__PASID__SHIFT', 'IH_VMID_5_LUT__PASID_MASK', + 'IH_VMID_5_LUT__PASID__SHIFT', 'IH_VMID_6_LUT_MM__PASID_MASK', + 'IH_VMID_6_LUT_MM__PASID__SHIFT', 'IH_VMID_6_LUT__PASID_MASK', + 'IH_VMID_6_LUT__PASID__SHIFT', 'IH_VMID_7_LUT_MM__PASID_MASK', + 'IH_VMID_7_LUT_MM__PASID__SHIFT', 'IH_VMID_7_LUT__PASID_MASK', + 'IH_VMID_7_LUT__PASID__SHIFT', 'IH_VMID_8_LUT_MM__PASID_MASK', + 'IH_VMID_8_LUT_MM__PASID__SHIFT', 'IH_VMID_8_LUT__PASID_MASK', + 'IH_VMID_8_LUT__PASID__SHIFT', 'IH_VMID_9_LUT_MM__PASID_MASK', + 'IH_VMID_9_LUT_MM__PASID__SHIFT', 'IH_VMID_9_LUT__PASID_MASK', + 'IH_VMID_9_LUT__PASID__SHIFT', 'SEM_MAILBOX_CLEAR__CLEAR_MASK', + 'SEM_MAILBOX_CLEAR__CLEAR__SHIFT', + 'SEM_MAILBOX_CLEAR__RESERVED_MASK', + 'SEM_MAILBOX_CLEAR__RESERVED__SHIFT', + 'SEM_MAILBOX__HOSTPORT_MASK', 'SEM_MAILBOX__HOSTPORT__SHIFT', + 'SEM_MAILBOX__RESERVED_MASK', 'SEM_MAILBOX__RESERVED__SHIFT', + 'SEM_REGISTER_LAST_PART2__RESERVED_MASK', + 'SEM_REGISTER_LAST_PART2__RESERVED__SHIFT', + '_osssys_6_0_0_OFFSET_HEADER', '_osssys_6_0_0_SH_MASK_HEADER', + 'regIH_CHICKEN', 'regIH_CHICKEN_BASE_IDX', 'regIH_CID_REMAP_DATA', + 'regIH_CID_REMAP_DATA_BASE_IDX', 'regIH_CID_REMAP_INDEX', + 'regIH_CID_REMAP_INDEX_BASE_IDX', 'regIH_CLIENT_CFG', + 'regIH_CLIENT_CFG_BASE_IDX', 'regIH_CLIENT_CFG_DATA', + 'regIH_CLIENT_CFG_DATA_BASE_IDX', 'regIH_CLIENT_CFG_INDEX', + 'regIH_CLIENT_CFG_INDEX_BASE_IDX', 'regIH_CLIENT_CREDIT_ERROR', + 'regIH_CLIENT_CREDIT_ERROR_BASE_IDX', 'regIH_CLK_CTRL', + 'regIH_CLK_CTRL_BASE_IDX', 'regIH_CNTL', 'regIH_CNTL2', + 'regIH_CNTL2_BASE_IDX', 'regIH_CNTL_BASE_IDX', 'regIH_COOKIE_0', + 'regIH_COOKIE_0_BASE_IDX', 'regIH_COOKIE_1', + 'regIH_COOKIE_1_BASE_IDX', 'regIH_COOKIE_2', + 'regIH_COOKIE_2_BASE_IDX', 'regIH_COOKIE_3', + 'regIH_COOKIE_3_BASE_IDX', 'regIH_COOKIE_4', + 'regIH_COOKIE_4_BASE_IDX', 'regIH_COOKIE_5', + 'regIH_COOKIE_5_BASE_IDX', 'regIH_COOKIE_6', + 'regIH_COOKIE_6_BASE_IDX', 'regIH_COOKIE_7', + 'regIH_COOKIE_7_BASE_IDX', 'regIH_COOKIE_REC_VIOLATION_LOG', + 'regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX', 'regIH_CREDIT_STATUS', + 'regIH_CREDIT_STATUS_BASE_IDX', 'regIH_DOORBELL_RETRY_CAM', + 'regIH_DOORBELL_RETRY_CAM_BASE_IDX', 'regIH_DOORBELL_RPTR', + 'regIH_DOORBELL_RPTR_BASE_IDX', 'regIH_DOORBELL_RPTR_RING1', + 'regIH_DOORBELL_RPTR_RING1_BASE_IDX', + 'regIH_DSM_MATCH_DATA_CONTROL', + 'regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX', 'regIH_DSM_MATCH_FCN_ID', + 'regIH_DSM_MATCH_FCN_ID_BASE_IDX', + 'regIH_DSM_MATCH_FIELD_CONTROL', + 'regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX', + 'regIH_DSM_MATCH_VALUE_BIT_31_0', + 'regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX', + 'regIH_DSM_MATCH_VALUE_BIT_63_32', + 'regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX', + 'regIH_DSM_MATCH_VALUE_BIT_95_64', + 'regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX', 'regIH_INT_DROP_CNTL', + 'regIH_INT_DROP_CNTL_BASE_IDX', 'regIH_INT_DROP_MATCH_MASK0', + 'regIH_INT_DROP_MATCH_MASK0_BASE_IDX', + 'regIH_INT_DROP_MATCH_MASK1', + 'regIH_INT_DROP_MATCH_MASK1_BASE_IDX', + 'regIH_INT_DROP_MATCH_VALUE0', + 'regIH_INT_DROP_MATCH_VALUE0_BASE_IDX', + 'regIH_INT_DROP_MATCH_VALUE1', + 'regIH_INT_DROP_MATCH_VALUE1_BASE_IDX', 'regIH_INT_FLAGS', + 'regIH_INT_FLAGS_BASE_IDX', 'regIH_INT_FLOOD_CNTL', + 'regIH_INT_FLOOD_CNTL_BASE_IDX', 'regIH_INT_FLOOD_STATUS', + 'regIH_INT_FLOOD_STATUS_BASE_IDX', 'regIH_LAST_INT_INFO0', + 'regIH_LAST_INT_INFO0_BASE_IDX', 'regIH_LAST_INT_INFO1', + 'regIH_LAST_INT_INFO1_BASE_IDX', 'regIH_LAST_INT_INFO2', + 'regIH_LAST_INT_INFO2_BASE_IDX', 'regIH_LIMIT_INT_RATE_CNTL', + 'regIH_LIMIT_INT_RATE_CNTL_BASE_IDX', 'regIH_MEM_POWER_CTRL', + 'regIH_MEM_POWER_CTRL2', 'regIH_MEM_POWER_CTRL2_BASE_IDX', + 'regIH_MEM_POWER_CTRL_BASE_IDX', 'regIH_MMHUB_ERROR', + 'regIH_MMHUB_ERROR_BASE_IDX', 'regIH_MSI_STORM_CLIENT_DATA', + 'regIH_MSI_STORM_CLIENT_DATA_BASE_IDX', + 'regIH_MSI_STORM_CLIENT_INDEX', + 'regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX', 'regIH_MSI_STORM_CTRL', + 'regIH_MSI_STORM_CTRL_BASE_IDX', 'regIH_PERFCOUNTER0_RESULT', + 'regIH_PERFCOUNTER0_RESULT_BASE_IDX', 'regIH_PERFCOUNTER1_RESULT', + 'regIH_PERFCOUNTER1_RESULT_BASE_IDX', 'regIH_PERFMON_CNTL', + 'regIH_PERFMON_CNTL_BASE_IDX', 'regIH_RB0_INT_FLOOD_STATUS', + 'regIH_RB0_INT_FLOOD_STATUS_BASE_IDX', + 'regIH_RB1_INT_FLOOD_STATUS', + 'regIH_RB1_INT_FLOOD_STATUS_BASE_IDX', 'regIH_RB_BASE', + 'regIH_RB_BASE_BASE_IDX', 'regIH_RB_BASE_HI', + 'regIH_RB_BASE_HI_BASE_IDX', 'regIH_RB_BASE_HI_RING1', + 'regIH_RB_BASE_HI_RING1_BASE_IDX', 'regIH_RB_BASE_RING1', + 'regIH_RB_BASE_RING1_BASE_IDX', 'regIH_RB_CNTL', + 'regIH_RB_CNTL_BASE_IDX', 'regIH_RB_CNTL_RING1', + 'regIH_RB_CNTL_RING1_BASE_IDX', 'regIH_RB_RPTR', + 'regIH_RB_RPTR_BASE_IDX', 'regIH_RB_RPTR_RING1', + 'regIH_RB_RPTR_RING1_BASE_IDX', 'regIH_RB_STATUS', + 'regIH_RB_STATUS_BASE_IDX', 'regIH_RB_WPTR', + 'regIH_RB_WPTR_ADDR_HI', 'regIH_RB_WPTR_ADDR_HI_BASE_IDX', + 'regIH_RB_WPTR_ADDR_LO', 'regIH_RB_WPTR_ADDR_LO_BASE_IDX', + 'regIH_RB_WPTR_BASE_IDX', 'regIH_RB_WPTR_RING1', + 'regIH_RB_WPTR_RING1_BASE_IDX', 'regIH_REGISTER_LAST_PART0', + 'regIH_REGISTER_LAST_PART0_BASE_IDX', 'regIH_REGISTER_LAST_PART1', + 'regIH_REGISTER_LAST_PART1_BASE_IDX', 'regIH_REGISTER_LAST_PART2', + 'regIH_REGISTER_LAST_PART2_BASE_IDX', 'regIH_RETRY_CAM_ACK', + 'regIH_RETRY_CAM_ACK_BASE_IDX', 'regIH_RETRY_INT_CAM_CNTL', + 'regIH_RETRY_INT_CAM_CNTL_BASE_IDX', + 'regIH_RING1_CLIENT_CFG_DATA', + 'regIH_RING1_CLIENT_CFG_DATA_BASE_IDX', + 'regIH_RING1_CLIENT_CFG_INDEX', + 'regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX', 'regIH_SCRATCH', + 'regIH_SCRATCH_BASE_IDX', 'regIH_STATUS', 'regIH_STATUS_BASE_IDX', + 'regIH_STORM_CLIENT_LIST_CNTL', + 'regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX', 'regIH_VERSION', + 'regIH_VERSION_BASE_IDX', 'regIH_VF_RB1_STATUS', + 'regIH_VF_RB1_STATUS2', 'regIH_VF_RB1_STATUS2_BASE_IDX', + 'regIH_VF_RB1_STATUS3', 'regIH_VF_RB1_STATUS3_BASE_IDX', + 'regIH_VF_RB1_STATUS_BASE_IDX', 'regIH_VF_RB_STATUS', + 'regIH_VF_RB_STATUS2', 'regIH_VF_RB_STATUS2_BASE_IDX', + 'regIH_VF_RB_STATUS3', 'regIH_VF_RB_STATUS3_BASE_IDX', + 'regIH_VF_RB_STATUS4', 'regIH_VF_RB_STATUS4_BASE_IDX', + 'regIH_VF_RB_STATUS_BASE_IDX', 'regIH_VMID_0_LUT', + 'regIH_VMID_0_LUT_BASE_IDX', 'regIH_VMID_0_LUT_MM', + 'regIH_VMID_0_LUT_MM_BASE_IDX', 'regIH_VMID_10_LUT', + 'regIH_VMID_10_LUT_BASE_IDX', 'regIH_VMID_10_LUT_MM', + 'regIH_VMID_10_LUT_MM_BASE_IDX', 'regIH_VMID_11_LUT', + 'regIH_VMID_11_LUT_BASE_IDX', 'regIH_VMID_11_LUT_MM', + 'regIH_VMID_11_LUT_MM_BASE_IDX', 'regIH_VMID_12_LUT', + 'regIH_VMID_12_LUT_BASE_IDX', 'regIH_VMID_12_LUT_MM', + 'regIH_VMID_12_LUT_MM_BASE_IDX', 'regIH_VMID_13_LUT', + 'regIH_VMID_13_LUT_BASE_IDX', 'regIH_VMID_13_LUT_MM', + 'regIH_VMID_13_LUT_MM_BASE_IDX', 'regIH_VMID_14_LUT', + 'regIH_VMID_14_LUT_BASE_IDX', 'regIH_VMID_14_LUT_MM', + 'regIH_VMID_14_LUT_MM_BASE_IDX', 'regIH_VMID_15_LUT', + 'regIH_VMID_15_LUT_BASE_IDX', 'regIH_VMID_15_LUT_MM', + 'regIH_VMID_15_LUT_MM_BASE_IDX', 'regIH_VMID_1_LUT', + 'regIH_VMID_1_LUT_BASE_IDX', 'regIH_VMID_1_LUT_MM', + 'regIH_VMID_1_LUT_MM_BASE_IDX', 'regIH_VMID_2_LUT', + 'regIH_VMID_2_LUT_BASE_IDX', 'regIH_VMID_2_LUT_MM', + 'regIH_VMID_2_LUT_MM_BASE_IDX', 'regIH_VMID_3_LUT', + 'regIH_VMID_3_LUT_BASE_IDX', 'regIH_VMID_3_LUT_MM', + 'regIH_VMID_3_LUT_MM_BASE_IDX', 'regIH_VMID_4_LUT', + 'regIH_VMID_4_LUT_BASE_IDX', 'regIH_VMID_4_LUT_MM', + 'regIH_VMID_4_LUT_MM_BASE_IDX', 'regIH_VMID_5_LUT', + 'regIH_VMID_5_LUT_BASE_IDX', 'regIH_VMID_5_LUT_MM', + 'regIH_VMID_5_LUT_MM_BASE_IDX', 'regIH_VMID_6_LUT', + 'regIH_VMID_6_LUT_BASE_IDX', 'regIH_VMID_6_LUT_MM', + 'regIH_VMID_6_LUT_MM_BASE_IDX', 'regIH_VMID_7_LUT', + 'regIH_VMID_7_LUT_BASE_IDX', 'regIH_VMID_7_LUT_MM', + 'regIH_VMID_7_LUT_MM_BASE_IDX', 'regIH_VMID_8_LUT', + 'regIH_VMID_8_LUT_BASE_IDX', 'regIH_VMID_8_LUT_MM', + 'regIH_VMID_8_LUT_MM_BASE_IDX', 'regIH_VMID_9_LUT', + 'regIH_VMID_9_LUT_BASE_IDX', 'regIH_VMID_9_LUT_MM', + 'regIH_VMID_9_LUT_MM_BASE_IDX', 'regSEM_MAILBOX', + 'regSEM_MAILBOX_BASE_IDX', 'regSEM_MAILBOX_CLEAR', + 'regSEM_MAILBOX_CLEAR_BASE_IDX', 'regSEM_REGISTER_LAST_PART2', + 'regSEM_REGISTER_LAST_PART2_BASE_IDX'] diff --git a/tinygrad/runtime/autogen/am/smu_v13_0_0.py b/tinygrad/runtime/autogen/am/smu_v13_0_0.py new file mode 100644 index 0000000000..b67f1ce734 --- /dev/null +++ b/tinygrad/runtime/autogen/am/smu_v13_0_0.py @@ -0,0 +1,3068 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + +class AsDictMixin: + @classmethod + def as_dict(cls, self): + result = {} + if not isinstance(self, AsDictMixin): + # not a structure, assume it's already a python object + return self + if not hasattr(cls, "_fields_"): + return result + # sys.version_info >= (3, 5) + # for (field, *_) in cls._fields_: # noqa + for field_tuple in cls._fields_: # noqa + field = field_tuple[0] + if field.startswith('PADDING_'): + continue + value = getattr(self, field) + type_ = type(value) + if hasattr(value, "_length_") and hasattr(value, "_type_"): + # array + if not hasattr(type_, "as_dict"): + value = [v for v in value] + else: + type_ = type_._type_ + value = [type_.as_dict(v) for v in value] + elif hasattr(value, "contents") and hasattr(value, "_type_"): + # pointer + try: + if not hasattr(type_, "as_dict"): + value = value.contents + else: + type_ = type_._type_ + value = type_.as_dict(value.contents) + except ValueError: + # nullptr + value = None + elif isinstance(value, AsDictMixin): + # other structure + value = type_.as_dict(value) + result[field] = value + return result + + +class Structure(ctypes.Structure, AsDictMixin): + + def __init__(self, *args, **kwds): + # We don't want to use positional arguments fill PADDING_* fields + + args = dict(zip(self.__class__._field_names_(), args)) + args.update(kwds) + super(Structure, self).__init__(**args) + + @classmethod + def _field_names_(cls): + if hasattr(cls, '_fields_'): + return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) + else: + return () + + @classmethod + def get_type(cls, field): + for f in cls._fields_: + if f[0] == field: + return f[1] + return None + + @classmethod + def bind(cls, bound_fields): + fields = {} + for name, type_ in cls._fields_: + if hasattr(type_, "restype"): + if name in bound_fields: + if bound_fields[name] is None: + fields[name] = type_() + else: + # use a closure to capture the callback from the loop scope + fields[name] = ( + type_((lambda callback: lambda *args: callback(*args))( + bound_fields[name])) + ) + del bound_fields[name] + else: + # default callback implementation (does nothing) + try: + default_ = type_(0).restype().value + except TypeError: + default_ = None + fields[name] = type_(( + lambda default_: lambda *args: default_)(default_)) + else: + # not a callback function, use default initialization + if name in bound_fields: + fields[name] = bound_fields[name] + del bound_fields[name] + else: + fields[name] = type_() + if len(bound_fields) != 0: + raise ValueError( + "Cannot bind the following unknown callback(s) {}.{}".format( + cls.__name__, bound_fields.keys() + )) + return cls(**fields) + + +class Union(ctypes.Union, AsDictMixin): + pass + + + +c_int128 = ctypes.c_ubyte*16 +c_uint128 = c_int128 +void = None +if ctypes.sizeof(ctypes.c_longdouble) == 16: + c_long_double_t = ctypes.c_longdouble +else: + c_long_double_t = ctypes.c_ubyte*16 + + + +SMU_V13_0_0_PPSMC_H = True # macro +PPSMC_VERSION = 0x1 # macro +DEBUGSMC_VERSION = 0x1 # macro +PPSMC_Result_OK = 0x1 # macro +PPSMC_Result_Failed = 0xFF # macro +PPSMC_Result_UnknownCmd = 0xFE # macro +PPSMC_Result_CmdRejectedPrereq = 0xFD # macro +PPSMC_Result_CmdRejectedBusy = 0xFC # macro +PPSMC_MSG_TestMessage = 0x1 # macro +PPSMC_MSG_GetSmuVersion = 0x2 # macro +PPSMC_MSG_GetDriverIfVersion = 0x3 # macro +PPSMC_MSG_SetAllowedFeaturesMaskLow = 0x4 # macro +PPSMC_MSG_SetAllowedFeaturesMaskHigh = 0x5 # macro +PPSMC_MSG_EnableAllSmuFeatures = 0x6 # macro +PPSMC_MSG_DisableAllSmuFeatures = 0x7 # macro +PPSMC_MSG_EnableSmuFeaturesLow = 0x8 # macro +PPSMC_MSG_EnableSmuFeaturesHigh = 0x9 # macro +PPSMC_MSG_DisableSmuFeaturesLow = 0xA # macro +PPSMC_MSG_DisableSmuFeaturesHigh = 0xB # macro +PPSMC_MSG_GetRunningSmuFeaturesLow = 0xC # macro +PPSMC_MSG_GetRunningSmuFeaturesHigh = 0xD # macro +PPSMC_MSG_SetDriverDramAddrHigh = 0xE # macro +PPSMC_MSG_SetDriverDramAddrLow = 0xF # macro +PPSMC_MSG_SetToolsDramAddrHigh = 0x10 # macro +PPSMC_MSG_SetToolsDramAddrLow = 0x11 # macro +PPSMC_MSG_TransferTableSmu2Dram = 0x12 # macro +PPSMC_MSG_TransferTableDram2Smu = 0x13 # macro +PPSMC_MSG_UseDefaultPPTable = 0x14 # macro +PPSMC_MSG_EnterBaco = 0x15 # macro +PPSMC_MSG_ExitBaco = 0x16 # macro +PPSMC_MSG_ArmD3 = 0x17 # macro +PPSMC_MSG_BacoAudioD3PME = 0x18 # macro +PPSMC_MSG_SetSoftMinByFreq = 0x19 # macro +PPSMC_MSG_SetSoftMaxByFreq = 0x1A # macro +PPSMC_MSG_SetHardMinByFreq = 0x1B # macro +PPSMC_MSG_SetHardMaxByFreq = 0x1C # macro +PPSMC_MSG_GetMinDpmFreq = 0x1D # macro +PPSMC_MSG_GetMaxDpmFreq = 0x1E # macro +PPSMC_MSG_GetDpmFreqByIndex = 0x1F # macro +PPSMC_MSG_OverridePcieParameters = 0x20 # macro +PPSMC_MSG_DramLogSetDramAddrHigh = 0x21 # macro +PPSMC_MSG_DramLogSetDramAddrLow = 0x22 # macro +PPSMC_MSG_DramLogSetDramSize = 0x23 # macro +PPSMC_MSG_SetWorkloadMask = 0x24 # macro +PPSMC_MSG_GetVoltageByDpm = 0x25 # macro +PPSMC_MSG_SetVideoFps = 0x26 # macro +PPSMC_MSG_GetDcModeMaxDpmFreq = 0x27 # macro +PPSMC_MSG_AllowGfxOff = 0x28 # macro +PPSMC_MSG_DisallowGfxOff = 0x29 # macro +PPSMC_MSG_PowerUpVcn = 0x2A # macro +PPSMC_MSG_PowerDownVcn = 0x2B # macro +PPSMC_MSG_PowerUpJpeg = 0x2C # macro +PPSMC_MSG_PowerDownJpeg = 0x2D # macro +PPSMC_MSG_PrepareMp1ForUnload = 0x2E # macro +PPSMC_MSG_Mode1Reset = 0x2F # macro +PPSMC_MSG_Mode2Reset = 0x4F # macro +PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x30 # macro +PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x31 # macro +PPSMC_MSG_SetPptLimit = 0x32 # macro +PPSMC_MSG_GetPptLimit = 0x33 # macro +PPSMC_MSG_ReenableAcDcInterrupt = 0x34 # macro +PPSMC_MSG_NotifyPowerSource = 0x35 # macro +PPSMC_MSG_RunDcBtc = 0x36 # macro +PPSMC_MSG_GetDebugData = 0x37 # macro +PPSMC_MSG_SetTemperatureInputSelect = 0x38 # macro +PPSMC_MSG_SetFwDstatesMask = 0x39 # macro +PPSMC_MSG_SetThrottlerMask = 0x3A # macro +PPSMC_MSG_SetExternalClientDfCstateAllow = 0x3B # macro +PPSMC_MSG_SetMGpuFanBoostLimitRpm = 0x3C # macro +PPSMC_MSG_DumpSTBtoDram = 0x3D # macro +PPSMC_MSG_STBtoDramLogSetDramAddrHigh = 0x3E # macro +PPSMC_MSG_STBtoDramLogSetDramAddrLow = 0x3F # macro +PPSMC_MSG_STBtoDramLogSetDramSize = 0x40 # macro +PPSMC_MSG_SetGpoAllow = 0x41 # macro +PPSMC_MSG_AllowGfxDcs = 0x42 # macro +PPSMC_MSG_DisallowGfxDcs = 0x43 # macro +PPSMC_MSG_EnableAudioStutterWA = 0x44 # macro +PPSMC_MSG_PowerUpUmsch = 0x45 # macro +PPSMC_MSG_PowerDownUmsch = 0x46 # macro +PPSMC_MSG_SetDcsArch = 0x47 # macro +PPSMC_MSG_TriggerVFFLR = 0x48 # macro +PPSMC_MSG_SetNumBadMemoryPagesRetired = 0x49 # macro +PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel = 0x4A # macro +PPSMC_MSG_SetPriorityDeltaGain = 0x4B # macro +PPSMC_MSG_AllowIHHostInterrupt = 0x4C # macro +PPSMC_MSG_DALNotPresent = 0x4E # macro +PPSMC_MSG_EnableUCLKShadow = 0x51 # macro +PPSMC_Message_Count = 0x52 # macro +DEBUGSMC_MSG_TestMessage = 0x1 # macro +DEBUGSMC_MSG_GetDebugData = 0x2 # macro +DEBUGSMC_MSG_DebugDumpExit = 0x3 # macro +DEBUGSMC_Message_Count = 0x4 # macro +SMU13_DRIVER_IF_V13_0_0_H = True # macro +int32_t = True # macro +uint32_t = True # macro +int8_t = True # macro +uint8_t = True # macro +uint16_t = True # macro +int16_t = True # macro +uint64_t = True # macro +bool = True # macro +SMU13_0_0_DRIVER_IF_VERSION = 0x3D # macro +PPTABLE_VERSION = 0x2B # macro +NUM_GFXCLK_DPM_LEVELS = 16 # macro +NUM_SOCCLK_DPM_LEVELS = 8 # macro +NUM_MP0CLK_DPM_LEVELS = 2 # macro +NUM_DCLK_DPM_LEVELS = 8 # macro +NUM_VCLK_DPM_LEVELS = 8 # macro +NUM_DISPCLK_DPM_LEVELS = 8 # macro +NUM_DPPCLK_DPM_LEVELS = 8 # macro +NUM_DPREFCLK_DPM_LEVELS = 8 # macro +NUM_DCFCLK_DPM_LEVELS = 8 # macro +NUM_DTBCLK_DPM_LEVELS = 8 # macro +NUM_UCLK_DPM_LEVELS = 4 # macro +NUM_LINK_LEVELS = 3 # macro +NUM_FCLK_DPM_LEVELS = 8 # macro +NUM_OD_FAN_MAX_POINTS = 6 # macro +FEATURE_FW_DATA_READ_BIT = 0 # macro +FEATURE_DPM_GFXCLK_BIT = 1 # macro +FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT = 2 # macro +FEATURE_DPM_UCLK_BIT = 3 # macro +FEATURE_DPM_FCLK_BIT = 4 # macro +FEATURE_DPM_SOCCLK_BIT = 5 # macro +FEATURE_DPM_MP0CLK_BIT = 6 # macro +FEATURE_DPM_LINK_BIT = 7 # macro +FEATURE_DPM_DCN_BIT = 8 # macro +FEATURE_VMEMP_SCALING_BIT = 9 # macro +FEATURE_VDDIO_MEM_SCALING_BIT = 10 # macro +FEATURE_DS_GFXCLK_BIT = 11 # macro +FEATURE_DS_SOCCLK_BIT = 12 # macro +FEATURE_DS_FCLK_BIT = 13 # macro +FEATURE_DS_LCLK_BIT = 14 # macro +FEATURE_DS_DCFCLK_BIT = 15 # macro +FEATURE_DS_UCLK_BIT = 16 # macro +FEATURE_GFX_ULV_BIT = 17 # macro +FEATURE_FW_DSTATE_BIT = 18 # macro +FEATURE_GFXOFF_BIT = 19 # macro +FEATURE_BACO_BIT = 20 # macro +FEATURE_MM_DPM_BIT = 21 # macro +FEATURE_SOC_MPCLK_DS_BIT = 22 # macro +FEATURE_BACO_MPCLK_DS_BIT = 23 # macro +FEATURE_THROTTLERS_BIT = 24 # macro +FEATURE_SMARTSHIFT_BIT = 25 # macro +FEATURE_GTHR_BIT = 26 # macro +FEATURE_ACDC_BIT = 27 # macro +FEATURE_VR0HOT_BIT = 28 # macro +FEATURE_FW_CTF_BIT = 29 # macro +FEATURE_FAN_CONTROL_BIT = 30 # macro +FEATURE_GFX_DCS_BIT = 31 # macro +FEATURE_GFX_READ_MARGIN_BIT = 32 # macro +FEATURE_LED_DISPLAY_BIT = 33 # macro +FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT = 34 # macro +FEATURE_OUT_OF_BAND_MONITOR_BIT = 35 # macro +FEATURE_OPTIMIZED_VMIN_BIT = 36 # macro +FEATURE_GFX_IMU_BIT = 37 # macro +FEATURE_BOOT_TIME_CAL_BIT = 38 # macro +FEATURE_GFX_PCC_DFLL_BIT = 39 # macro +FEATURE_SOC_CG_BIT = 40 # macro +FEATURE_DF_CSTATE_BIT = 41 # macro +FEATURE_GFX_EDC_BIT = 42 # macro +FEATURE_BOOT_POWER_OPT_BIT = 43 # macro +FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT = 44 # macro +FEATURE_DS_VCN_BIT = 45 # macro +FEATURE_BACO_CG_BIT = 46 # macro +FEATURE_MEM_TEMP_READ_BIT = 47 # macro +FEATURE_ATHUB_MMHUB_PG_BIT = 48 # macro +FEATURE_SOC_PCC_BIT = 49 # macro +FEATURE_EDC_PWRBRK_BIT = 50 # macro +FEATURE_BOMXCO_SVI3_PROG_BIT = 51 # macro +FEATURE_SPARE_52_BIT = 52 # macro +FEATURE_SPARE_53_BIT = 53 # macro +FEATURE_SPARE_54_BIT = 54 # macro +FEATURE_SPARE_55_BIT = 55 # macro +FEATURE_SPARE_56_BIT = 56 # macro +FEATURE_SPARE_57_BIT = 57 # macro +FEATURE_SPARE_58_BIT = 58 # macro +FEATURE_SPARE_59_BIT = 59 # macro +FEATURE_SPARE_60_BIT = 60 # macro +FEATURE_SPARE_61_BIT = 61 # macro +FEATURE_SPARE_62_BIT = 62 # macro +FEATURE_SPARE_63_BIT = 63 # macro +NUM_FEATURES = 64 # macro +ALLOWED_FEATURE_CTRL_DEFAULT = 0xFFFFFFFFFFFFFFFF # macro +ALLOWED_FEATURE_CTRL_SCPM = ((1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<45)) # macro +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK = 0x00000001 # macro +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK = 0x00000002 # macro +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK = 0x00000004 # macro +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK = 0x00000008 # macro +DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER = 0x00000010 # macro +DEBUG_OVERRIDE_DISABLE_VCN_PG = 0x00000020 # macro +DEBUG_OVERRIDE_DISABLE_FMAX_VMAX = 0x00000040 # macro +DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS = 0x00000080 # macro +DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK = 0x00000100 # macro +DEBUG_OVERRIDE_DISABLE_DFLL = 0x00000200 # macro +DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE = 0x00000400 # macro +DEBUG_OVERRIDE_DFLL_MASTER_MODE = 0x00000800 # macro +DEBUG_OVERRIDE_ENABLE_PROFILING_MODE = 0x00001000 # macro +VR_MAPPING_VR_SELECT_MASK = 0x01 # macro +VR_MAPPING_VR_SELECT_SHIFT = 0x00 # macro +VR_MAPPING_PLANE_SELECT_MASK = 0x02 # macro +VR_MAPPING_PLANE_SELECT_SHIFT = 0x01 # macro +PSI_SEL_VR0_PLANE0_PSI0 = 0x01 # macro +PSI_SEL_VR0_PLANE0_PSI1 = 0x02 # macro +PSI_SEL_VR0_PLANE1_PSI0 = 0x04 # macro +PSI_SEL_VR0_PLANE1_PSI1 = 0x08 # macro +PSI_SEL_VR1_PLANE0_PSI0 = 0x10 # macro +PSI_SEL_VR1_PLANE0_PSI1 = 0x20 # macro +PSI_SEL_VR1_PLANE1_PSI0 = 0x40 # macro +PSI_SEL_VR1_PLANE1_PSI1 = 0x80 # macro +THROTTLER_TEMP_EDGE_BIT = 0 # macro +THROTTLER_TEMP_HOTSPOT_BIT = 1 # macro +THROTTLER_TEMP_HOTSPOT_G_BIT = 2 # macro +THROTTLER_TEMP_HOTSPOT_M_BIT = 3 # macro +THROTTLER_TEMP_MEM_BIT = 4 # macro +THROTTLER_TEMP_VR_GFX_BIT = 5 # macro +THROTTLER_TEMP_VR_MEM0_BIT = 6 # macro +THROTTLER_TEMP_VR_MEM1_BIT = 7 # macro +THROTTLER_TEMP_VR_SOC_BIT = 8 # macro +THROTTLER_TEMP_VR_U_BIT = 9 # macro +THROTTLER_TEMP_LIQUID0_BIT = 10 # macro +THROTTLER_TEMP_LIQUID1_BIT = 11 # macro +THROTTLER_TEMP_PLX_BIT = 12 # macro +THROTTLER_TDC_GFX_BIT = 13 # macro +THROTTLER_TDC_SOC_BIT = 14 # macro +THROTTLER_TDC_U_BIT = 15 # macro +THROTTLER_PPT0_BIT = 16 # macro +THROTTLER_PPT1_BIT = 17 # macro +THROTTLER_PPT2_BIT = 18 # macro +THROTTLER_PPT3_BIT = 19 # macro +THROTTLER_FIT_BIT = 20 # macro +THROTTLER_GFX_APCC_PLUS_BIT = 21 # macro +THROTTLER_COUNT = 22 # macro +FW_DSTATE_SOC_ULV_BIT = 0 # macro +FW_DSTATE_G6_HSR_BIT = 1 # macro +FW_DSTATE_G6_PHY_VMEMP_OFF_BIT = 2 # macro +FW_DSTATE_SMN_DS_BIT = 3 # macro +FW_DSTATE_MP1_WHISPER_MODE_BIT = 4 # macro +FW_DSTATE_SOC_LIV_MIN_BIT = 5 # macro +FW_DSTATE_SOC_PLL_PWRDN_BIT = 6 # macro +FW_DSTATE_MEM_PLL_PWRDN_BIT = 7 # macro +FW_DSTATE_MALL_ALLOC_BIT = 8 # macro +FW_DSTATE_MEM_PSI_BIT = 9 # macro +FW_DSTATE_HSR_NON_STROBE_BIT = 10 # macro +FW_DSTATE_MP0_ENTER_WFI_BIT = 11 # macro +FW_DSTATE_U_ULV_BIT = 12 # macro +FW_DSTATE_MALL_FLUSH_BIT = 13 # macro +FW_DSTATE_SOC_PSI_BIT = 14 # macro +FW_DSTATE_U_PSI_BIT = 15 # macro +FW_DSTATE_UCP_DS_BIT = 16 # macro +FW_DSTATE_CSRCLK_DS_BIT = 17 # macro +FW_DSTATE_MMHUB_INTERLOCK_BIT = 18 # macro +FW_DSTATE_D0i3_2_QUIET_FW_BIT = 19 # macro +FW_DSTATE_CLDO_PRG_BIT = 20 # macro +FW_DSTATE_DF_PLL_PWRDN_BIT = 21 # macro +FW_DSTATE_U_LOW_PWR_MODE_EN_BIT = 22 # macro +FW_DSTATE_GFX_PSI6_BIT = 23 # macro +FW_DSTATE_GFX_VR_PWR_STAGE_BIT = 24 # macro +LED_DISPLAY_GFX_DPM_BIT = 0 # macro +LED_DISPLAY_PCIE_BIT = 1 # macro +LED_DISPLAY_ERROR_BIT = 2 # macro +MEM_TEMP_READ_OUT_OF_BAND_BIT = 0 # macro +MEM_TEMP_READ_IN_BAND_REFRESH_BIT = 1 # macro +MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT = 2 # macro +NUM_I2C_CONTROLLERS = 8 # macro +I2C_CONTROLLER_ENABLED = 1 # macro +I2C_CONTROLLER_DISABLED = 0 # macro +MAX_SW_I2C_COMMANDS = 24 # macro +CMDCONFIG_STOP_BIT = 0 # macro +CMDCONFIG_RESTART_BIT = 1 # macro +CMDCONFIG_READWRITE_BIT = 2 # macro +CMDCONFIG_STOP_MASK = (1<<0) # macro +CMDCONFIG_RESTART_MASK = (1<<1) # macro +CMDCONFIG_READWRITE_MASK = (1<<2) # macro +PP_NUM_RTAVFS_PWL_ZONES = 5 # macro +PP_OD_FEATURE_GFX_VF_CURVE_BIT = 0 # macro +PP_OD_FEATURE_PPT_BIT = 2 # macro +PP_OD_FEATURE_FAN_CURVE_BIT = 3 # macro +PP_OD_FEATURE_GFXCLK_BIT = 7 # macro +PP_OD_FEATURE_UCLK_BIT = 8 # macro +PP_OD_FEATURE_ZERO_FAN_BIT = 9 # macro +PP_OD_FEATURE_TEMPERATURE_BIT = 10 # macro +PP_OD_FEATURE_COUNT = 13 # macro +PP_NUM_OD_VF_CURVE_POINTS = 5 + 1 # macro +INVALID_BOARD_GPIO = 0xFF # macro +MARKETING_BASE_CLOCKS = 0 # macro +MARKETING_GAME_CLOCKS = 1 # macro +MARKETING_BOOST_CLOCKS = 2 # macro +NUM_WM_RANGES = 4 # macro +WORKLOAD_PPLIB_DEFAULT_BIT = 0 # macro +WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT = 1 # macro +WORKLOAD_PPLIB_POWER_SAVING_BIT = 2 # macro +WORKLOAD_PPLIB_VIDEO_BIT = 3 # macro +WORKLOAD_PPLIB_VR_BIT = 4 # macro +WORKLOAD_PPLIB_COMPUTE_BIT = 5 # macro +WORKLOAD_PPLIB_CUSTOM_BIT = 6 # macro +WORKLOAD_PPLIB_WINDOW_3D_BIT = 7 # macro +WORKLOAD_PPLIB_COUNT = 8 # macro +TABLE_TRANSFER_OK = 0x0 # macro +TABLE_TRANSFER_FAILED = 0xFF # macro +TABLE_TRANSFER_PENDING = 0xAB # macro +TABLE_PPTABLE = 0 # macro +TABLE_COMBO_PPTABLE = 1 # macro +TABLE_WATERMARKS = 2 # macro +TABLE_AVFS_PSM_DEBUG = 3 # macro +TABLE_PMSTATUSLOG = 4 # macro +TABLE_SMU_METRICS = 5 # macro +TABLE_DRIVER_SMU_CONFIG = 6 # macro +TABLE_ACTIVITY_MONITOR_COEFF = 7 # macro +TABLE_OVERDRIVE = 8 # macro +TABLE_I2C_COMMANDS = 9 # macro +TABLE_DRIVER_INFO = 10 # macro +TABLE_ECCINFO = 11 # macro +TABLE_WIFIBAND = 12 # macro +TABLE_COUNT = 13 # macro +IH_INTERRUPT_ID_TO_DRIVER = 0xFE # macro +IH_INTERRUPT_CONTEXT_ID_BACO = 0x2 # macro +IH_INTERRUPT_CONTEXT_ID_AC = 0x3 # macro +IH_INTERRUPT_CONTEXT_ID_DC = 0x4 # macro +IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 = 0x5 # macro +IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 = 0x6 # macro +IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7 # macro +IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL = 0x8 # macro +IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY = 0x9 # macro + +# values for enumeration 'c__EA_FEATURE_PWR_DOMAIN_e' +c__EA_FEATURE_PWR_DOMAIN_e__enumvalues = { + 0: 'FEATURE_PWR_ALL', + 1: 'FEATURE_PWR_S5', + 2: 'FEATURE_PWR_BACO', + 3: 'FEATURE_PWR_SOC', + 4: 'FEATURE_PWR_GFX', + 5: 'FEATURE_PWR_DOMAIN_COUNT', +} +FEATURE_PWR_ALL = 0 +FEATURE_PWR_S5 = 1 +FEATURE_PWR_BACO = 2 +FEATURE_PWR_SOC = 3 +FEATURE_PWR_GFX = 4 +FEATURE_PWR_DOMAIN_COUNT = 5 +c__EA_FEATURE_PWR_DOMAIN_e = ctypes.c_uint32 # enum +FEATURE_PWR_DOMAIN_e = c__EA_FEATURE_PWR_DOMAIN_e +FEATURE_PWR_DOMAIN_e__enumvalues = c__EA_FEATURE_PWR_DOMAIN_e__enumvalues + +# values for enumeration 'c__EA_SVI_PSI_e' +c__EA_SVI_PSI_e__enumvalues = { + 0: 'SVI_PSI_0', + 1: 'SVI_PSI_1', + 2: 'SVI_PSI_2', + 3: 'SVI_PSI_3', + 4: 'SVI_PSI_4', + 5: 'SVI_PSI_5', + 6: 'SVI_PSI_6', + 7: 'SVI_PSI_7', +} +SVI_PSI_0 = 0 +SVI_PSI_1 = 1 +SVI_PSI_2 = 2 +SVI_PSI_3 = 3 +SVI_PSI_4 = 4 +SVI_PSI_5 = 5 +SVI_PSI_6 = 6 +SVI_PSI_7 = 7 +c__EA_SVI_PSI_e = ctypes.c_uint32 # enum +SVI_PSI_e = c__EA_SVI_PSI_e +SVI_PSI_e__enumvalues = c__EA_SVI_PSI_e__enumvalues + +# values for enumeration 'c__EA_SMARTSHIFT_VERSION_e' +c__EA_SMARTSHIFT_VERSION_e__enumvalues = { + 0: 'SMARTSHIFT_VERSION_1', + 1: 'SMARTSHIFT_VERSION_2', + 2: 'SMARTSHIFT_VERSION_3', +} +SMARTSHIFT_VERSION_1 = 0 +SMARTSHIFT_VERSION_2 = 1 +SMARTSHIFT_VERSION_3 = 2 +c__EA_SMARTSHIFT_VERSION_e = ctypes.c_uint32 # enum +SMARTSHIFT_VERSION_e = c__EA_SMARTSHIFT_VERSION_e +SMARTSHIFT_VERSION_e__enumvalues = c__EA_SMARTSHIFT_VERSION_e__enumvalues + +# values for enumeration 'c__EA_FOPT_CALC_e' +c__EA_FOPT_CALC_e__enumvalues = { + 0: 'FOPT_CALC_AC_CALC_DC', + 1: 'FOPT_PPTABLE_AC_CALC_DC', + 2: 'FOPT_CALC_AC_PPTABLE_DC', + 3: 'FOPT_PPTABLE_AC_PPTABLE_DC', +} +FOPT_CALC_AC_CALC_DC = 0 +FOPT_PPTABLE_AC_CALC_DC = 1 +FOPT_CALC_AC_PPTABLE_DC = 2 +FOPT_PPTABLE_AC_PPTABLE_DC = 3 +c__EA_FOPT_CALC_e = ctypes.c_uint32 # enum +FOPT_CALC_e = c__EA_FOPT_CALC_e +FOPT_CALC_e__enumvalues = c__EA_FOPT_CALC_e__enumvalues + +# values for enumeration 'c__EA_DRAM_BIT_WIDTH_TYPE_e' +c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues = { + 0: 'DRAM_BIT_WIDTH_DISABLED', + 8: 'DRAM_BIT_WIDTH_X_8', + 16: 'DRAM_BIT_WIDTH_X_16', + 32: 'DRAM_BIT_WIDTH_X_32', + 64: 'DRAM_BIT_WIDTH_X_64', + 128: 'DRAM_BIT_WIDTH_X_128', + 129: 'DRAM_BIT_WIDTH_COUNT', +} +DRAM_BIT_WIDTH_DISABLED = 0 +DRAM_BIT_WIDTH_X_8 = 8 +DRAM_BIT_WIDTH_X_16 = 16 +DRAM_BIT_WIDTH_X_32 = 32 +DRAM_BIT_WIDTH_X_64 = 64 +DRAM_BIT_WIDTH_X_128 = 128 +DRAM_BIT_WIDTH_COUNT = 129 +c__EA_DRAM_BIT_WIDTH_TYPE_e = ctypes.c_uint32 # enum +DRAM_BIT_WIDTH_TYPE_e = c__EA_DRAM_BIT_WIDTH_TYPE_e +DRAM_BIT_WIDTH_TYPE_e__enumvalues = c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues + +# values for enumeration 'c__EA_I2cControllerPort_e' +c__EA_I2cControllerPort_e__enumvalues = { + 0: 'I2C_CONTROLLER_PORT_0', + 1: 'I2C_CONTROLLER_PORT_1', + 2: 'I2C_CONTROLLER_PORT_COUNT', +} +I2C_CONTROLLER_PORT_0 = 0 +I2C_CONTROLLER_PORT_1 = 1 +I2C_CONTROLLER_PORT_COUNT = 2 +c__EA_I2cControllerPort_e = ctypes.c_uint32 # enum +I2cControllerPort_e = c__EA_I2cControllerPort_e +I2cControllerPort_e__enumvalues = c__EA_I2cControllerPort_e__enumvalues + +# values for enumeration 'c__EA_I2cControllerName_e' +c__EA_I2cControllerName_e__enumvalues = { + 0: 'I2C_CONTROLLER_NAME_VR_GFX', + 1: 'I2C_CONTROLLER_NAME_VR_SOC', + 2: 'I2C_CONTROLLER_NAME_VR_VMEMP', + 3: 'I2C_CONTROLLER_NAME_VR_VDDIO', + 4: 'I2C_CONTROLLER_NAME_LIQUID0', + 5: 'I2C_CONTROLLER_NAME_LIQUID1', + 6: 'I2C_CONTROLLER_NAME_PLX', + 7: 'I2C_CONTROLLER_NAME_FAN_INTAKE', + 8: 'I2C_CONTROLLER_NAME_COUNT', +} +I2C_CONTROLLER_NAME_VR_GFX = 0 +I2C_CONTROLLER_NAME_VR_SOC = 1 +I2C_CONTROLLER_NAME_VR_VMEMP = 2 +I2C_CONTROLLER_NAME_VR_VDDIO = 3 +I2C_CONTROLLER_NAME_LIQUID0 = 4 +I2C_CONTROLLER_NAME_LIQUID1 = 5 +I2C_CONTROLLER_NAME_PLX = 6 +I2C_CONTROLLER_NAME_FAN_INTAKE = 7 +I2C_CONTROLLER_NAME_COUNT = 8 +c__EA_I2cControllerName_e = ctypes.c_uint32 # enum +I2cControllerName_e = c__EA_I2cControllerName_e +I2cControllerName_e__enumvalues = c__EA_I2cControllerName_e__enumvalues + +# values for enumeration 'c__EA_I2cControllerThrottler_e' +c__EA_I2cControllerThrottler_e__enumvalues = { + 0: 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', + 1: 'I2C_CONTROLLER_THROTTLER_VR_GFX', + 2: 'I2C_CONTROLLER_THROTTLER_VR_SOC', + 3: 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', + 4: 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', + 5: 'I2C_CONTROLLER_THROTTLER_LIQUID0', + 6: 'I2C_CONTROLLER_THROTTLER_LIQUID1', + 7: 'I2C_CONTROLLER_THROTTLER_PLX', + 8: 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', + 9: 'I2C_CONTROLLER_THROTTLER_INA3221', + 10: 'I2C_CONTROLLER_THROTTLER_COUNT', +} +I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0 +I2C_CONTROLLER_THROTTLER_VR_GFX = 1 +I2C_CONTROLLER_THROTTLER_VR_SOC = 2 +I2C_CONTROLLER_THROTTLER_VR_VMEMP = 3 +I2C_CONTROLLER_THROTTLER_VR_VDDIO = 4 +I2C_CONTROLLER_THROTTLER_LIQUID0 = 5 +I2C_CONTROLLER_THROTTLER_LIQUID1 = 6 +I2C_CONTROLLER_THROTTLER_PLX = 7 +I2C_CONTROLLER_THROTTLER_FAN_INTAKE = 8 +I2C_CONTROLLER_THROTTLER_INA3221 = 9 +I2C_CONTROLLER_THROTTLER_COUNT = 10 +c__EA_I2cControllerThrottler_e = ctypes.c_uint32 # enum +I2cControllerThrottler_e = c__EA_I2cControllerThrottler_e +I2cControllerThrottler_e__enumvalues = c__EA_I2cControllerThrottler_e__enumvalues + +# values for enumeration 'c__EA_I2cControllerProtocol_e' +c__EA_I2cControllerProtocol_e__enumvalues = { + 0: 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', + 1: 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', + 2: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', + 3: 'I2C_CONTROLLER_PROTOCOL_INA3221', + 4: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', + 5: 'I2C_CONTROLLER_PROTOCOL_COUNT', +} +I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5 = 0 +I2C_CONTROLLER_PROTOCOL_VR_IR35217 = 1 +I2C_CONTROLLER_PROTOCOL_TMP_MAX31875 = 2 +I2C_CONTROLLER_PROTOCOL_INA3221 = 3 +I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = 4 +I2C_CONTROLLER_PROTOCOL_COUNT = 5 +c__EA_I2cControllerProtocol_e = ctypes.c_uint32 # enum +I2cControllerProtocol_e = c__EA_I2cControllerProtocol_e +I2cControllerProtocol_e__enumvalues = c__EA_I2cControllerProtocol_e__enumvalues +class struct_c__SA_I2cControllerConfig_t(Structure): + pass + +struct_c__SA_I2cControllerConfig_t._pack_ = 1 # source:False +struct_c__SA_I2cControllerConfig_t._fields_ = [ + ('Enabled', ctypes.c_ubyte), + ('Speed', ctypes.c_ubyte), + ('SlaveAddress', ctypes.c_ubyte), + ('ControllerPort', ctypes.c_ubyte), + ('ControllerName', ctypes.c_ubyte), + ('ThermalThrotter', ctypes.c_ubyte), + ('I2cProtocol', ctypes.c_ubyte), + ('PaddingConfig', ctypes.c_ubyte), +] + +I2cControllerConfig_t = struct_c__SA_I2cControllerConfig_t + +# values for enumeration 'c__EA_I2cPort_e' +c__EA_I2cPort_e__enumvalues = { + 0: 'I2C_PORT_SVD_SCL', + 1: 'I2C_PORT_GPIO', +} +I2C_PORT_SVD_SCL = 0 +I2C_PORT_GPIO = 1 +c__EA_I2cPort_e = ctypes.c_uint32 # enum +I2cPort_e = c__EA_I2cPort_e +I2cPort_e__enumvalues = c__EA_I2cPort_e__enumvalues + +# values for enumeration 'c__EA_I2cSpeed_e' +c__EA_I2cSpeed_e__enumvalues = { + 0: 'I2C_SPEED_FAST_50K', + 1: 'I2C_SPEED_FAST_100K', + 2: 'I2C_SPEED_FAST_400K', + 3: 'I2C_SPEED_FAST_PLUS_1M', + 4: 'I2C_SPEED_HIGH_1M', + 5: 'I2C_SPEED_HIGH_2M', + 6: 'I2C_SPEED_COUNT', +} +I2C_SPEED_FAST_50K = 0 +I2C_SPEED_FAST_100K = 1 +I2C_SPEED_FAST_400K = 2 +I2C_SPEED_FAST_PLUS_1M = 3 +I2C_SPEED_HIGH_1M = 4 +I2C_SPEED_HIGH_2M = 5 +I2C_SPEED_COUNT = 6 +c__EA_I2cSpeed_e = ctypes.c_uint32 # enum +I2cSpeed_e = c__EA_I2cSpeed_e +I2cSpeed_e__enumvalues = c__EA_I2cSpeed_e__enumvalues + +# values for enumeration 'c__EA_I2cCmdType_e' +c__EA_I2cCmdType_e__enumvalues = { + 0: 'I2C_CMD_READ', + 1: 'I2C_CMD_WRITE', + 2: 'I2C_CMD_COUNT', +} +I2C_CMD_READ = 0 +I2C_CMD_WRITE = 1 +I2C_CMD_COUNT = 2 +c__EA_I2cCmdType_e = ctypes.c_uint32 # enum +I2cCmdType_e = c__EA_I2cCmdType_e +I2cCmdType_e__enumvalues = c__EA_I2cCmdType_e__enumvalues +class struct_c__SA_SwI2cCmd_t(Structure): + pass + +struct_c__SA_SwI2cCmd_t._pack_ = 1 # source:False +struct_c__SA_SwI2cCmd_t._fields_ = [ + ('ReadWriteData', ctypes.c_ubyte), + ('CmdConfig', ctypes.c_ubyte), +] + +SwI2cCmd_t = struct_c__SA_SwI2cCmd_t +class struct_c__SA_SwI2cRequest_t(Structure): + pass + +struct_c__SA_SwI2cRequest_t._pack_ = 1 # source:False +struct_c__SA_SwI2cRequest_t._fields_ = [ + ('I2CcontrollerPort', ctypes.c_ubyte), + ('I2CSpeed', ctypes.c_ubyte), + ('SlaveAddress', ctypes.c_ubyte), + ('NumCmds', ctypes.c_ubyte), + ('SwI2cCmds', struct_c__SA_SwI2cCmd_t * 24), +] + +SwI2cRequest_t = struct_c__SA_SwI2cRequest_t +class struct_c__SA_SwI2cRequestExternal_t(Structure): + pass + +struct_c__SA_SwI2cRequestExternal_t._pack_ = 1 # source:False +struct_c__SA_SwI2cRequestExternal_t._fields_ = [ + ('SwI2cRequest', SwI2cRequest_t), + ('Spare', ctypes.c_uint32 * 8), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +SwI2cRequestExternal_t = struct_c__SA_SwI2cRequestExternal_t +class struct_c__SA_EccInfo_t(Structure): + pass + +struct_c__SA_EccInfo_t._pack_ = 1 # source:False +struct_c__SA_EccInfo_t._fields_ = [ + ('mca_umc_status', ctypes.c_uint64), + ('mca_umc_addr', ctypes.c_uint64), + ('ce_count_lo_chip', ctypes.c_uint16), + ('ce_count_hi_chip', ctypes.c_uint16), + ('eccPadding', ctypes.c_uint32), +] + +EccInfo_t = struct_c__SA_EccInfo_t +class struct_c__SA_EccInfoTable_t(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('EccInfo', struct_c__SA_EccInfo_t * 24), + ] + +EccInfoTable_t = struct_c__SA_EccInfoTable_t + +# values for enumeration 'c__EA_D3HOTSequence_e' +c__EA_D3HOTSequence_e__enumvalues = { + 0: 'BACO_SEQUENCE', + 1: 'MSR_SEQUENCE', + 2: 'BAMACO_SEQUENCE', + 3: 'ULPS_SEQUENCE', + 4: 'D3HOT_SEQUENCE_COUNT', +} +BACO_SEQUENCE = 0 +MSR_SEQUENCE = 1 +BAMACO_SEQUENCE = 2 +ULPS_SEQUENCE = 3 +D3HOT_SEQUENCE_COUNT = 4 +c__EA_D3HOTSequence_e = ctypes.c_uint32 # enum +D3HOTSequence_e = c__EA_D3HOTSequence_e +D3HOTSequence_e__enumvalues = c__EA_D3HOTSequence_e__enumvalues + +# values for enumeration 'c__EA_PowerGatingMode_e' +c__EA_PowerGatingMode_e__enumvalues = { + 0: 'PG_DYNAMIC_MODE', + 1: 'PG_STATIC_MODE', +} +PG_DYNAMIC_MODE = 0 +PG_STATIC_MODE = 1 +c__EA_PowerGatingMode_e = ctypes.c_uint32 # enum +PowerGatingMode_e = c__EA_PowerGatingMode_e +PowerGatingMode_e__enumvalues = c__EA_PowerGatingMode_e__enumvalues + +# values for enumeration 'c__EA_PowerGatingSettings_e' +c__EA_PowerGatingSettings_e__enumvalues = { + 0: 'PG_POWER_DOWN', + 1: 'PG_POWER_UP', +} +PG_POWER_DOWN = 0 +PG_POWER_UP = 1 +c__EA_PowerGatingSettings_e = ctypes.c_uint32 # enum +PowerGatingSettings_e = c__EA_PowerGatingSettings_e +PowerGatingSettings_e__enumvalues = c__EA_PowerGatingSettings_e__enumvalues +class struct_c__SA_QuadraticInt_t(Structure): + pass + +struct_c__SA_QuadraticInt_t._pack_ = 1 # source:False +struct_c__SA_QuadraticInt_t._fields_ = [ + ('a', ctypes.c_uint32), + ('b', ctypes.c_uint32), + ('c', ctypes.c_uint32), +] + +QuadraticInt_t = struct_c__SA_QuadraticInt_t +class struct_c__SA_LinearInt_t(Structure): + pass + +struct_c__SA_LinearInt_t._pack_ = 1 # source:False +struct_c__SA_LinearInt_t._fields_ = [ + ('m', ctypes.c_uint32), + ('b', ctypes.c_uint32), +] + +LinearInt_t = struct_c__SA_LinearInt_t +class struct_c__SA_DroopInt_t(Structure): + pass + +struct_c__SA_DroopInt_t._pack_ = 1 # source:False +struct_c__SA_DroopInt_t._fields_ = [ + ('a', ctypes.c_uint32), + ('b', ctypes.c_uint32), + ('c', ctypes.c_uint32), +] + +DroopInt_t = struct_c__SA_DroopInt_t + +# values for enumeration 'c__EA_DCS_ARCH_e' +c__EA_DCS_ARCH_e__enumvalues = { + 0: 'DCS_ARCH_DISABLED', + 1: 'DCS_ARCH_FADCS', + 2: 'DCS_ARCH_ASYNC', +} +DCS_ARCH_DISABLED = 0 +DCS_ARCH_FADCS = 1 +DCS_ARCH_ASYNC = 2 +c__EA_DCS_ARCH_e = ctypes.c_uint32 # enum +DCS_ARCH_e = c__EA_DCS_ARCH_e +DCS_ARCH_e__enumvalues = c__EA_DCS_ARCH_e__enumvalues + +# values for enumeration 'c__EA_PPCLK_e' +c__EA_PPCLK_e__enumvalues = { + 0: 'PPCLK_GFXCLK', + 1: 'PPCLK_SOCCLK', + 2: 'PPCLK_UCLK', + 3: 'PPCLK_FCLK', + 4: 'PPCLK_DCLK_0', + 5: 'PPCLK_VCLK_0', + 6: 'PPCLK_DCLK_1', + 7: 'PPCLK_VCLK_1', + 8: 'PPCLK_DISPCLK', + 9: 'PPCLK_DPPCLK', + 10: 'PPCLK_DPREFCLK', + 11: 'PPCLK_DCFCLK', + 12: 'PPCLK_DTBCLK', + 13: 'PPCLK_COUNT', +} +PPCLK_GFXCLK = 0 +PPCLK_SOCCLK = 1 +PPCLK_UCLK = 2 +PPCLK_FCLK = 3 +PPCLK_DCLK_0 = 4 +PPCLK_VCLK_0 = 5 +PPCLK_DCLK_1 = 6 +PPCLK_VCLK_1 = 7 +PPCLK_DISPCLK = 8 +PPCLK_DPPCLK = 9 +PPCLK_DPREFCLK = 10 +PPCLK_DCFCLK = 11 +PPCLK_DTBCLK = 12 +PPCLK_COUNT = 13 +c__EA_PPCLK_e = ctypes.c_uint32 # enum +PPCLK_e = c__EA_PPCLK_e +PPCLK_e__enumvalues = c__EA_PPCLK_e__enumvalues + +# values for enumeration 'c__EA_VOLTAGE_MODE_e' +c__EA_VOLTAGE_MODE_e__enumvalues = { + 0: 'VOLTAGE_MODE_PPTABLE', + 1: 'VOLTAGE_MODE_FUSES', + 2: 'VOLTAGE_MODE_COUNT', +} +VOLTAGE_MODE_PPTABLE = 0 +VOLTAGE_MODE_FUSES = 1 +VOLTAGE_MODE_COUNT = 2 +c__EA_VOLTAGE_MODE_e = ctypes.c_uint32 # enum +VOLTAGE_MODE_e = c__EA_VOLTAGE_MODE_e +VOLTAGE_MODE_e__enumvalues = c__EA_VOLTAGE_MODE_e__enumvalues + +# values for enumeration 'c__EA_AVFS_VOLTAGE_TYPE_e' +c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues = { + 0: 'AVFS_VOLTAGE_GFX', + 1: 'AVFS_VOLTAGE_SOC', + 2: 'AVFS_VOLTAGE_COUNT', +} +AVFS_VOLTAGE_GFX = 0 +AVFS_VOLTAGE_SOC = 1 +AVFS_VOLTAGE_COUNT = 2 +c__EA_AVFS_VOLTAGE_TYPE_e = ctypes.c_uint32 # enum +AVFS_VOLTAGE_TYPE_e = c__EA_AVFS_VOLTAGE_TYPE_e +AVFS_VOLTAGE_TYPE_e__enumvalues = c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues + +# values for enumeration 'c__EA_AVFS_TEMP_e' +c__EA_AVFS_TEMP_e__enumvalues = { + 0: 'AVFS_TEMP_COLD', + 1: 'AVFS_TEMP_HOT', + 2: 'AVFS_TEMP_COUNT', +} +AVFS_TEMP_COLD = 0 +AVFS_TEMP_HOT = 1 +AVFS_TEMP_COUNT = 2 +c__EA_AVFS_TEMP_e = ctypes.c_uint32 # enum +AVFS_TEMP_e = c__EA_AVFS_TEMP_e +AVFS_TEMP_e__enumvalues = c__EA_AVFS_TEMP_e__enumvalues + +# values for enumeration 'c__EA_AVFS_D_e' +c__EA_AVFS_D_e__enumvalues = { + 0: 'AVFS_D_G', + 1: 'AVFS_D_M_B', + 2: 'AVFS_D_M_S', + 3: 'AVFS_D_COUNT', +} +AVFS_D_G = 0 +AVFS_D_M_B = 1 +AVFS_D_M_S = 2 +AVFS_D_COUNT = 3 +c__EA_AVFS_D_e = ctypes.c_uint32 # enum +AVFS_D_e = c__EA_AVFS_D_e +AVFS_D_e__enumvalues = c__EA_AVFS_D_e__enumvalues + +# values for enumeration 'c__EA_UCLK_DIV_e' +c__EA_UCLK_DIV_e__enumvalues = { + 0: 'UCLK_DIV_BY_1', + 1: 'UCLK_DIV_BY_2', + 2: 'UCLK_DIV_BY_4', + 3: 'UCLK_DIV_BY_8', +} +UCLK_DIV_BY_1 = 0 +UCLK_DIV_BY_2 = 1 +UCLK_DIV_BY_4 = 2 +UCLK_DIV_BY_8 = 3 +c__EA_UCLK_DIV_e = ctypes.c_uint32 # enum +UCLK_DIV_e = c__EA_UCLK_DIV_e +UCLK_DIV_e__enumvalues = c__EA_UCLK_DIV_e__enumvalues + +# values for enumeration 'c__EA_GpioIntPolarity_e' +c__EA_GpioIntPolarity_e__enumvalues = { + 0: 'GPIO_INT_POLARITY_ACTIVE_LOW', + 1: 'GPIO_INT_POLARITY_ACTIVE_HIGH', +} +GPIO_INT_POLARITY_ACTIVE_LOW = 0 +GPIO_INT_POLARITY_ACTIVE_HIGH = 1 +c__EA_GpioIntPolarity_e = ctypes.c_uint32 # enum +GpioIntPolarity_e = c__EA_GpioIntPolarity_e +GpioIntPolarity_e__enumvalues = c__EA_GpioIntPolarity_e__enumvalues + +# values for enumeration 'c__EA_PwrConfig_e' +c__EA_PwrConfig_e__enumvalues = { + 0: 'PWR_CONFIG_TDP', + 1: 'PWR_CONFIG_TGP', + 2: 'PWR_CONFIG_TCP_ESTIMATED', + 3: 'PWR_CONFIG_TCP_MEASURED', +} +PWR_CONFIG_TDP = 0 +PWR_CONFIG_TGP = 1 +PWR_CONFIG_TCP_ESTIMATED = 2 +PWR_CONFIG_TCP_MEASURED = 3 +c__EA_PwrConfig_e = ctypes.c_uint32 # enum +PwrConfig_e = c__EA_PwrConfig_e +PwrConfig_e__enumvalues = c__EA_PwrConfig_e__enumvalues +class struct_c__SA_DpmDescriptor_t(Structure): + pass + +struct_c__SA_DpmDescriptor_t._pack_ = 1 # source:False +struct_c__SA_DpmDescriptor_t._fields_ = [ + ('Padding', ctypes.c_ubyte), + ('SnapToDiscrete', ctypes.c_ubyte), + ('NumDiscreteLevels', ctypes.c_ubyte), + ('CalculateFopt', ctypes.c_ubyte), + ('ConversionToAvfsClk', LinearInt_t), + ('Padding3', ctypes.c_uint32 * 3), + ('Padding4', ctypes.c_uint16), + ('FoptimalDc', ctypes.c_uint16), + ('FoptimalAc', ctypes.c_uint16), + ('Padding2', ctypes.c_uint16), +] + +DpmDescriptor_t = struct_c__SA_DpmDescriptor_t + +# values for enumeration 'c__EA_PPT_THROTTLER_e' +c__EA_PPT_THROTTLER_e__enumvalues = { + 0: 'PPT_THROTTLER_PPT0', + 1: 'PPT_THROTTLER_PPT1', + 2: 'PPT_THROTTLER_PPT2', + 3: 'PPT_THROTTLER_PPT3', + 4: 'PPT_THROTTLER_COUNT', +} +PPT_THROTTLER_PPT0 = 0 +PPT_THROTTLER_PPT1 = 1 +PPT_THROTTLER_PPT2 = 2 +PPT_THROTTLER_PPT3 = 3 +PPT_THROTTLER_COUNT = 4 +c__EA_PPT_THROTTLER_e = ctypes.c_uint32 # enum +PPT_THROTTLER_e = c__EA_PPT_THROTTLER_e +PPT_THROTTLER_e__enumvalues = c__EA_PPT_THROTTLER_e__enumvalues + +# values for enumeration 'c__EA_TEMP_e' +c__EA_TEMP_e__enumvalues = { + 0: 'TEMP_EDGE', + 1: 'TEMP_HOTSPOT', + 2: 'TEMP_HOTSPOT_G', + 3: 'TEMP_HOTSPOT_M', + 4: 'TEMP_MEM', + 5: 'TEMP_VR_GFX', + 6: 'TEMP_VR_MEM0', + 7: 'TEMP_VR_MEM1', + 8: 'TEMP_VR_SOC', + 9: 'TEMP_VR_U', + 10: 'TEMP_LIQUID0', + 11: 'TEMP_LIQUID1', + 12: 'TEMP_PLX', + 13: 'TEMP_COUNT', +} +TEMP_EDGE = 0 +TEMP_HOTSPOT = 1 +TEMP_HOTSPOT_G = 2 +TEMP_HOTSPOT_M = 3 +TEMP_MEM = 4 +TEMP_VR_GFX = 5 +TEMP_VR_MEM0 = 6 +TEMP_VR_MEM1 = 7 +TEMP_VR_SOC = 8 +TEMP_VR_U = 9 +TEMP_LIQUID0 = 10 +TEMP_LIQUID1 = 11 +TEMP_PLX = 12 +TEMP_COUNT = 13 +c__EA_TEMP_e = ctypes.c_uint32 # enum +TEMP_e = c__EA_TEMP_e +TEMP_e__enumvalues = c__EA_TEMP_e__enumvalues + +# values for enumeration 'c__EA_TDC_THROTTLER_e' +c__EA_TDC_THROTTLER_e__enumvalues = { + 0: 'TDC_THROTTLER_GFX', + 1: 'TDC_THROTTLER_SOC', + 2: 'TDC_THROTTLER_U', + 3: 'TDC_THROTTLER_COUNT', +} +TDC_THROTTLER_GFX = 0 +TDC_THROTTLER_SOC = 1 +TDC_THROTTLER_U = 2 +TDC_THROTTLER_COUNT = 3 +c__EA_TDC_THROTTLER_e = ctypes.c_uint32 # enum +TDC_THROTTLER_e = c__EA_TDC_THROTTLER_e +TDC_THROTTLER_e__enumvalues = c__EA_TDC_THROTTLER_e__enumvalues + +# values for enumeration 'c__EA_SVI_PLANE_e' +c__EA_SVI_PLANE_e__enumvalues = { + 0: 'SVI_PLANE_GFX', + 1: 'SVI_PLANE_SOC', + 2: 'SVI_PLANE_VMEMP', + 3: 'SVI_PLANE_VDDIO_MEM', + 4: 'SVI_PLANE_U', + 5: 'SVI_PLANE_COUNT', +} +SVI_PLANE_GFX = 0 +SVI_PLANE_SOC = 1 +SVI_PLANE_VMEMP = 2 +SVI_PLANE_VDDIO_MEM = 3 +SVI_PLANE_U = 4 +SVI_PLANE_COUNT = 5 +c__EA_SVI_PLANE_e = ctypes.c_uint32 # enum +SVI_PLANE_e = c__EA_SVI_PLANE_e +SVI_PLANE_e__enumvalues = c__EA_SVI_PLANE_e__enumvalues + +# values for enumeration 'c__EA_PMFW_VOLT_PLANE_e' +c__EA_PMFW_VOLT_PLANE_e__enumvalues = { + 0: 'PMFW_VOLT_PLANE_GFX', + 1: 'PMFW_VOLT_PLANE_SOC', + 2: 'PMFW_VOLT_PLANE_COUNT', +} +PMFW_VOLT_PLANE_GFX = 0 +PMFW_VOLT_PLANE_SOC = 1 +PMFW_VOLT_PLANE_COUNT = 2 +c__EA_PMFW_VOLT_PLANE_e = ctypes.c_uint32 # enum +PMFW_VOLT_PLANE_e = c__EA_PMFW_VOLT_PLANE_e +PMFW_VOLT_PLANE_e__enumvalues = c__EA_PMFW_VOLT_PLANE_e__enumvalues + +# values for enumeration 'c__EA_CUSTOMER_VARIANT_e' +c__EA_CUSTOMER_VARIANT_e__enumvalues = { + 0: 'CUSTOMER_VARIANT_ROW', + 1: 'CUSTOMER_VARIANT_FALCON', + 2: 'CUSTOMER_VARIANT_COUNT', +} +CUSTOMER_VARIANT_ROW = 0 +CUSTOMER_VARIANT_FALCON = 1 +CUSTOMER_VARIANT_COUNT = 2 +c__EA_CUSTOMER_VARIANT_e = ctypes.c_uint32 # enum +CUSTOMER_VARIANT_e = c__EA_CUSTOMER_VARIANT_e +CUSTOMER_VARIANT_e__enumvalues = c__EA_CUSTOMER_VARIANT_e__enumvalues + +# values for enumeration 'c__EA_POWER_SOURCE_e' +c__EA_POWER_SOURCE_e__enumvalues = { + 0: 'POWER_SOURCE_AC', + 1: 'POWER_SOURCE_DC', + 2: 'POWER_SOURCE_COUNT', +} +POWER_SOURCE_AC = 0 +POWER_SOURCE_DC = 1 +POWER_SOURCE_COUNT = 2 +c__EA_POWER_SOURCE_e = ctypes.c_uint32 # enum +POWER_SOURCE_e = c__EA_POWER_SOURCE_e +POWER_SOURCE_e__enumvalues = c__EA_POWER_SOURCE_e__enumvalues + +# values for enumeration 'c__EA_MEM_VENDOR_e' +c__EA_MEM_VENDOR_e__enumvalues = { + 0: 'MEM_VENDOR_PLACEHOLDER0', + 1: 'MEM_VENDOR_SAMSUNG', + 2: 'MEM_VENDOR_INFINEON', + 3: 'MEM_VENDOR_ELPIDA', + 4: 'MEM_VENDOR_ETRON', + 5: 'MEM_VENDOR_NANYA', + 6: 'MEM_VENDOR_HYNIX', + 7: 'MEM_VENDOR_MOSEL', + 8: 'MEM_VENDOR_WINBOND', + 9: 'MEM_VENDOR_ESMT', + 10: 'MEM_VENDOR_PLACEHOLDER1', + 11: 'MEM_VENDOR_PLACEHOLDER2', + 12: 'MEM_VENDOR_PLACEHOLDER3', + 13: 'MEM_VENDOR_PLACEHOLDER4', + 14: 'MEM_VENDOR_PLACEHOLDER5', + 15: 'MEM_VENDOR_MICRON', + 16: 'MEM_VENDOR_COUNT', +} +MEM_VENDOR_PLACEHOLDER0 = 0 +MEM_VENDOR_SAMSUNG = 1 +MEM_VENDOR_INFINEON = 2 +MEM_VENDOR_ELPIDA = 3 +MEM_VENDOR_ETRON = 4 +MEM_VENDOR_NANYA = 5 +MEM_VENDOR_HYNIX = 6 +MEM_VENDOR_MOSEL = 7 +MEM_VENDOR_WINBOND = 8 +MEM_VENDOR_ESMT = 9 +MEM_VENDOR_PLACEHOLDER1 = 10 +MEM_VENDOR_PLACEHOLDER2 = 11 +MEM_VENDOR_PLACEHOLDER3 = 12 +MEM_VENDOR_PLACEHOLDER4 = 13 +MEM_VENDOR_PLACEHOLDER5 = 14 +MEM_VENDOR_MICRON = 15 +MEM_VENDOR_COUNT = 16 +c__EA_MEM_VENDOR_e = ctypes.c_uint32 # enum +MEM_VENDOR_e = c__EA_MEM_VENDOR_e +MEM_VENDOR_e__enumvalues = c__EA_MEM_VENDOR_e__enumvalues + +# values for enumeration 'c__EA_PP_GRTAVFS_HW_FUSE_e' +c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues = { + 0: 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', + 1: 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', + 2: 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', + 3: 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', + 4: 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', + 5: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', + 6: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', + 7: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', + 8: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', + 9: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', + 10: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', + 11: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', + 12: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', + 13: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', + 14: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', + 15: 'PP_GRTAVFS_HW_ZONE0_VF', + 16: 'PP_GRTAVFS_HW_ZONE1_VF1', + 17: 'PP_GRTAVFS_HW_ZONE2_VF2', + 18: 'PP_GRTAVFS_HW_ZONE3_VF3', + 19: 'PP_GRTAVFS_HW_VOLTAGE_GB', + 20: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', + 21: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', + 22: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', + 23: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', + 24: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', + 25: 'PP_GRTAVFS_HW_RESERVED_0', + 26: 'PP_GRTAVFS_HW_RESERVED_1', + 27: 'PP_GRTAVFS_HW_RESERVED_2', + 28: 'PP_GRTAVFS_HW_RESERVED_3', + 29: 'PP_GRTAVFS_HW_RESERVED_4', + 30: 'PP_GRTAVFS_HW_RESERVED_5', + 31: 'PP_GRTAVFS_HW_RESERVED_6', + 32: 'PP_GRTAVFS_HW_FUSE_COUNT', +} +PP_GRTAVFS_HW_CPO_CTL_ZONE0 = 0 +PP_GRTAVFS_HW_CPO_CTL_ZONE1 = 1 +PP_GRTAVFS_HW_CPO_CTL_ZONE2 = 2 +PP_GRTAVFS_HW_CPO_CTL_ZONE3 = 3 +PP_GRTAVFS_HW_CPO_CTL_ZONE4 = 4 +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 = 5 +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 = 6 +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 = 7 +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 = 8 +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 = 9 +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 = 10 +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 = 11 +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 = 12 +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 = 13 +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 = 14 +PP_GRTAVFS_HW_ZONE0_VF = 15 +PP_GRTAVFS_HW_ZONE1_VF1 = 16 +PP_GRTAVFS_HW_ZONE2_VF2 = 17 +PP_GRTAVFS_HW_ZONE3_VF3 = 18 +PP_GRTAVFS_HW_VOLTAGE_GB = 19 +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 = 20 +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 = 21 +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 = 22 +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 = 23 +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 = 24 +PP_GRTAVFS_HW_RESERVED_0 = 25 +PP_GRTAVFS_HW_RESERVED_1 = 26 +PP_GRTAVFS_HW_RESERVED_2 = 27 +PP_GRTAVFS_HW_RESERVED_3 = 28 +PP_GRTAVFS_HW_RESERVED_4 = 29 +PP_GRTAVFS_HW_RESERVED_5 = 30 +PP_GRTAVFS_HW_RESERVED_6 = 31 +PP_GRTAVFS_HW_FUSE_COUNT = 32 +c__EA_PP_GRTAVFS_HW_FUSE_e = ctypes.c_uint32 # enum +PP_GRTAVFS_HW_FUSE_e = c__EA_PP_GRTAVFS_HW_FUSE_e +PP_GRTAVFS_HW_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues + +# values for enumeration 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e' +c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = { + 0: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', + 1: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', + 2: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', + 3: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', + 4: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', + 5: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', + 6: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', + 7: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', + 8: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', + 9: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', + 10: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', + 11: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', + 12: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', + 13: 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', +} +PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 = 0 +PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 = 1 +PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 = 2 +PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 = 3 +PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 = 4 +PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 = 5 +PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 = 6 +PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 = 7 +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 = 8 +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 = 9 +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 = 10 +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 = 11 +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 = 12 +PP_GRTAVFS_FW_COMMON_FUSE_COUNT = 13 +c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e = ctypes.c_uint32 # enum +PP_GRTAVFS_FW_COMMON_FUSE_e = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e +PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues + +# values for enumeration 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e' +c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = { + 0: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', + 1: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', + 2: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', + 3: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', + 4: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', + 5: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', + 6: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', + 7: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', + 8: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', + 9: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', + 10: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', + 11: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', + 12: 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', + 13: 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', + 14: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', + 15: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', + 16: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', + 17: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', + 18: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', + 19: 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', +} +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 = 0 +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 = 1 +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 = 2 +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 = 3 +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 = 4 +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 = 5 +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 = 6 +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 = 7 +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 = 8 +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 = 9 +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 = 10 +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 = 11 +PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY = 12 +PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY = 13 +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 = 14 +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 = 15 +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 = 16 +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = 17 +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = 18 +PP_GRTAVFS_FW_SEP_FUSE_COUNT = 19 +c__EA_PP_GRTAVFS_FW_SEP_FUSE_e = ctypes.c_uint32 # enum +PP_GRTAVFS_FW_SEP_FUSE_e = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e +PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues +class struct_c__SA_SviTelemetryScale_t(Structure): + pass + +struct_c__SA_SviTelemetryScale_t._pack_ = 1 # source:False +struct_c__SA_SviTelemetryScale_t._fields_ = [ + ('Offset', ctypes.c_byte), + ('Padding', ctypes.c_ubyte), + ('MaxCurrent', ctypes.c_uint16), +] + +SviTelemetryScale_t = struct_c__SA_SviTelemetryScale_t + +# values for enumeration 'c__EA_FanMode_e' +c__EA_FanMode_e__enumvalues = { + 0: 'FAN_MODE_AUTO', + 1: 'FAN_MODE_MANUAL_LINEAR', +} +FAN_MODE_AUTO = 0 +FAN_MODE_MANUAL_LINEAR = 1 +c__EA_FanMode_e = ctypes.c_uint32 # enum +FanMode_e = c__EA_FanMode_e +FanMode_e__enumvalues = c__EA_FanMode_e__enumvalues +class struct_c__SA_OverDriveTable_t(Structure): + pass + +struct_c__SA_OverDriveTable_t._pack_ = 1 # source:False +struct_c__SA_OverDriveTable_t._fields_ = [ + ('FeatureCtrlMask', ctypes.c_uint32), + ('VoltageOffsetPerZoneBoundary', ctypes.c_int16 * 6), + ('Reserved', ctypes.c_uint32), + ('GfxclkFmin', ctypes.c_int16), + ('GfxclkFmax', ctypes.c_int16), + ('UclkFmin', ctypes.c_uint16), + ('UclkFmax', ctypes.c_uint16), + ('Ppt', ctypes.c_int16), + ('Tdc', ctypes.c_int16), + ('FanLinearPwmPoints', ctypes.c_ubyte * 6), + ('FanLinearTempPoints', ctypes.c_ubyte * 6), + ('FanMinimumPwm', ctypes.c_uint16), + ('AcousticTargetRpmThreshold', ctypes.c_uint16), + ('AcousticLimitRpmThreshold', ctypes.c_uint16), + ('FanTargetTemperature', ctypes.c_uint16), + ('FanZeroRpmEnable', ctypes.c_ubyte), + ('FanZeroRpmStopTemp', ctypes.c_ubyte), + ('FanMode', ctypes.c_ubyte), + ('MaxOpTemp', ctypes.c_ubyte), + ('Spare', ctypes.c_uint32 * 13), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +OverDriveTable_t = struct_c__SA_OverDriveTable_t +class struct_c__SA_OverDriveTableExternal_t(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('OverDriveTable', OverDriveTable_t), + ] + +OverDriveTableExternal_t = struct_c__SA_OverDriveTableExternal_t +class struct_c__SA_OverDriveLimits_t(Structure): + pass + +struct_c__SA_OverDriveLimits_t._pack_ = 1 # source:False +struct_c__SA_OverDriveLimits_t._fields_ = [ + ('FeatureCtrlMask', ctypes.c_uint32), + ('VoltageOffsetPerZoneBoundary', ctypes.c_int16), + ('Reserved1', ctypes.c_uint16), + ('Reserved2', ctypes.c_uint16), + ('GfxclkFmin', ctypes.c_int16), + ('GfxclkFmax', ctypes.c_int16), + ('UclkFmin', ctypes.c_uint16), + ('UclkFmax', ctypes.c_uint16), + ('Ppt', ctypes.c_int16), + ('Tdc', ctypes.c_int16), + ('FanLinearPwmPoints', ctypes.c_ubyte), + ('FanLinearTempPoints', ctypes.c_ubyte), + ('FanMinimumPwm', ctypes.c_uint16), + ('AcousticTargetRpmThreshold', ctypes.c_uint16), + ('AcousticLimitRpmThreshold', ctypes.c_uint16), + ('FanTargetTemperature', ctypes.c_uint16), + ('FanZeroRpmEnable', ctypes.c_ubyte), + ('FanZeroRpmStopTemp', ctypes.c_ubyte), + ('FanMode', ctypes.c_ubyte), + ('MaxOpTemp', ctypes.c_ubyte), + ('Spare', ctypes.c_uint32 * 13), +] + +OverDriveLimits_t = struct_c__SA_OverDriveLimits_t + +# values for enumeration 'c__EA_BOARD_GPIO_TYPE_e' +c__EA_BOARD_GPIO_TYPE_e__enumvalues = { + 0: 'BOARD_GPIO_SMUIO_0', + 1: 'BOARD_GPIO_SMUIO_1', + 2: 'BOARD_GPIO_SMUIO_2', + 3: 'BOARD_GPIO_SMUIO_3', + 4: 'BOARD_GPIO_SMUIO_4', + 5: 'BOARD_GPIO_SMUIO_5', + 6: 'BOARD_GPIO_SMUIO_6', + 7: 'BOARD_GPIO_SMUIO_7', + 8: 'BOARD_GPIO_SMUIO_8', + 9: 'BOARD_GPIO_SMUIO_9', + 10: 'BOARD_GPIO_SMUIO_10', + 11: 'BOARD_GPIO_SMUIO_11', + 12: 'BOARD_GPIO_SMUIO_12', + 13: 'BOARD_GPIO_SMUIO_13', + 14: 'BOARD_GPIO_SMUIO_14', + 15: 'BOARD_GPIO_SMUIO_15', + 16: 'BOARD_GPIO_SMUIO_16', + 17: 'BOARD_GPIO_SMUIO_17', + 18: 'BOARD_GPIO_SMUIO_18', + 19: 'BOARD_GPIO_SMUIO_19', + 20: 'BOARD_GPIO_SMUIO_20', + 21: 'BOARD_GPIO_SMUIO_21', + 22: 'BOARD_GPIO_SMUIO_22', + 23: 'BOARD_GPIO_SMUIO_23', + 24: 'BOARD_GPIO_SMUIO_24', + 25: 'BOARD_GPIO_SMUIO_25', + 26: 'BOARD_GPIO_SMUIO_26', + 27: 'BOARD_GPIO_SMUIO_27', + 28: 'BOARD_GPIO_SMUIO_28', + 29: 'BOARD_GPIO_SMUIO_29', + 30: 'BOARD_GPIO_SMUIO_30', + 31: 'BOARD_GPIO_SMUIO_31', + 32: 'MAX_BOARD_GPIO_SMUIO_NUM', + 33: 'BOARD_GPIO_DC_GEN_A', + 34: 'BOARD_GPIO_DC_GEN_B', + 35: 'BOARD_GPIO_DC_GEN_C', + 36: 'BOARD_GPIO_DC_GEN_D', + 37: 'BOARD_GPIO_DC_GEN_E', + 38: 'BOARD_GPIO_DC_GEN_F', + 39: 'BOARD_GPIO_DC_GEN_G', + 40: 'BOARD_GPIO_DC_GENLK_CLK', + 41: 'BOARD_GPIO_DC_GENLK_VSYNC', + 42: 'BOARD_GPIO_DC_SWAPLOCK_A', + 43: 'BOARD_GPIO_DC_SWAPLOCK_B', +} +BOARD_GPIO_SMUIO_0 = 0 +BOARD_GPIO_SMUIO_1 = 1 +BOARD_GPIO_SMUIO_2 = 2 +BOARD_GPIO_SMUIO_3 = 3 +BOARD_GPIO_SMUIO_4 = 4 +BOARD_GPIO_SMUIO_5 = 5 +BOARD_GPIO_SMUIO_6 = 6 +BOARD_GPIO_SMUIO_7 = 7 +BOARD_GPIO_SMUIO_8 = 8 +BOARD_GPIO_SMUIO_9 = 9 +BOARD_GPIO_SMUIO_10 = 10 +BOARD_GPIO_SMUIO_11 = 11 +BOARD_GPIO_SMUIO_12 = 12 +BOARD_GPIO_SMUIO_13 = 13 +BOARD_GPIO_SMUIO_14 = 14 +BOARD_GPIO_SMUIO_15 = 15 +BOARD_GPIO_SMUIO_16 = 16 +BOARD_GPIO_SMUIO_17 = 17 +BOARD_GPIO_SMUIO_18 = 18 +BOARD_GPIO_SMUIO_19 = 19 +BOARD_GPIO_SMUIO_20 = 20 +BOARD_GPIO_SMUIO_21 = 21 +BOARD_GPIO_SMUIO_22 = 22 +BOARD_GPIO_SMUIO_23 = 23 +BOARD_GPIO_SMUIO_24 = 24 +BOARD_GPIO_SMUIO_25 = 25 +BOARD_GPIO_SMUIO_26 = 26 +BOARD_GPIO_SMUIO_27 = 27 +BOARD_GPIO_SMUIO_28 = 28 +BOARD_GPIO_SMUIO_29 = 29 +BOARD_GPIO_SMUIO_30 = 30 +BOARD_GPIO_SMUIO_31 = 31 +MAX_BOARD_GPIO_SMUIO_NUM = 32 +BOARD_GPIO_DC_GEN_A = 33 +BOARD_GPIO_DC_GEN_B = 34 +BOARD_GPIO_DC_GEN_C = 35 +BOARD_GPIO_DC_GEN_D = 36 +BOARD_GPIO_DC_GEN_E = 37 +BOARD_GPIO_DC_GEN_F = 38 +BOARD_GPIO_DC_GEN_G = 39 +BOARD_GPIO_DC_GENLK_CLK = 40 +BOARD_GPIO_DC_GENLK_VSYNC = 41 +BOARD_GPIO_DC_SWAPLOCK_A = 42 +BOARD_GPIO_DC_SWAPLOCK_B = 43 +c__EA_BOARD_GPIO_TYPE_e = ctypes.c_uint32 # enum +BOARD_GPIO_TYPE_e = c__EA_BOARD_GPIO_TYPE_e +BOARD_GPIO_TYPE_e__enumvalues = c__EA_BOARD_GPIO_TYPE_e__enumvalues +class struct_c__SA_BootValues_t(Structure): + pass + +struct_c__SA_BootValues_t._pack_ = 1 # source:False +struct_c__SA_BootValues_t._fields_ = [ + ('InitGfxclk_bypass', ctypes.c_uint16), + ('InitSocclk', ctypes.c_uint16), + ('InitMp0clk', ctypes.c_uint16), + ('InitMpioclk', ctypes.c_uint16), + ('InitSmnclk', ctypes.c_uint16), + ('InitUcpclk', ctypes.c_uint16), + ('InitCsrclk', ctypes.c_uint16), + ('InitDprefclk', ctypes.c_uint16), + ('InitDcfclk', ctypes.c_uint16), + ('InitDtbclk', ctypes.c_uint16), + ('InitDclk', ctypes.c_uint16), + ('InitVclk', ctypes.c_uint16), + ('InitUsbdfsclk', ctypes.c_uint16), + ('InitMp1clk', ctypes.c_uint16), + ('InitLclk', ctypes.c_uint16), + ('InitBaco400clk_bypass', ctypes.c_uint16), + ('InitBaco1200clk_bypass', ctypes.c_uint16), + ('InitBaco700clk_bypass', ctypes.c_uint16), + ('InitFclk', ctypes.c_uint16), + ('InitGfxclk_clkb', ctypes.c_uint16), + ('InitUclkDPMState', ctypes.c_ubyte), + ('Padding', ctypes.c_ubyte * 3), + ('InitVcoFreqPll0', ctypes.c_uint32), + ('InitVcoFreqPll1', ctypes.c_uint32), + ('InitVcoFreqPll2', ctypes.c_uint32), + ('InitVcoFreqPll3', ctypes.c_uint32), + ('InitVcoFreqPll4', ctypes.c_uint32), + ('InitVcoFreqPll5', ctypes.c_uint32), + ('InitVcoFreqPll6', ctypes.c_uint32), + ('InitGfx', ctypes.c_uint16), + ('InitSoc', ctypes.c_uint16), + ('InitU', ctypes.c_uint16), + ('Padding2', ctypes.c_uint16), + ('Spare', ctypes.c_uint32 * 8), +] + +BootValues_t = struct_c__SA_BootValues_t +class struct_c__SA_MsgLimits_t(Structure): + pass + +struct_c__SA_MsgLimits_t._pack_ = 1 # source:False +struct_c__SA_MsgLimits_t._fields_ = [ + ('Power', ctypes.c_uint16 * 2 * 4), + ('Tdc', ctypes.c_uint16 * 3), + ('Temperature', ctypes.c_uint16 * 13), + ('PwmLimitMin', ctypes.c_ubyte), + ('PwmLimitMax', ctypes.c_ubyte), + ('FanTargetTemperature', ctypes.c_ubyte), + ('Spare1', ctypes.c_ubyte * 1), + ('AcousticTargetRpmThresholdMin', ctypes.c_uint16), + ('AcousticTargetRpmThresholdMax', ctypes.c_uint16), + ('AcousticLimitRpmThresholdMin', ctypes.c_uint16), + ('AcousticLimitRpmThresholdMax', ctypes.c_uint16), + ('PccLimitMin', ctypes.c_uint16), + ('PccLimitMax', ctypes.c_uint16), + ('FanStopTempMin', ctypes.c_uint16), + ('FanStopTempMax', ctypes.c_uint16), + ('FanStartTempMin', ctypes.c_uint16), + ('FanStartTempMax', ctypes.c_uint16), + ('PowerMinPpt0', ctypes.c_uint16 * 2), + ('Spare', ctypes.c_uint32 * 11), +] + +MsgLimits_t = struct_c__SA_MsgLimits_t +class struct_c__SA_DriverReportedClocks_t(Structure): + pass + +struct_c__SA_DriverReportedClocks_t._pack_ = 1 # source:False +struct_c__SA_DriverReportedClocks_t._fields_ = [ + ('BaseClockAc', ctypes.c_uint16), + ('GameClockAc', ctypes.c_uint16), + ('BoostClockAc', ctypes.c_uint16), + ('BaseClockDc', ctypes.c_uint16), + ('GameClockDc', ctypes.c_uint16), + ('BoostClockDc', ctypes.c_uint16), + ('Reserved', ctypes.c_uint32 * 4), +] + +DriverReportedClocks_t = struct_c__SA_DriverReportedClocks_t +class struct_c__SA_AvfsDcBtcParams_t(Structure): + pass + +struct_c__SA_AvfsDcBtcParams_t._pack_ = 1 # source:False +struct_c__SA_AvfsDcBtcParams_t._fields_ = [ + ('DcBtcEnabled', ctypes.c_ubyte), + ('Padding', ctypes.c_ubyte * 3), + ('DcTol', ctypes.c_uint16), + ('DcBtcGb', ctypes.c_uint16), + ('DcBtcMin', ctypes.c_uint16), + ('DcBtcMax', ctypes.c_uint16), + ('DcBtcGbScalar', LinearInt_t), +] + +AvfsDcBtcParams_t = struct_c__SA_AvfsDcBtcParams_t +class struct_c__SA_AvfsFuseOverride_t(Structure): + pass + +struct_c__SA_AvfsFuseOverride_t._pack_ = 1 # source:False +struct_c__SA_AvfsFuseOverride_t._fields_ = [ + ('AvfsTemp', ctypes.c_uint16 * 2), + ('VftFMin', ctypes.c_uint16), + ('VInversion', ctypes.c_uint16), + ('qVft', struct_c__SA_QuadraticInt_t * 2), + ('qAvfsGb', QuadraticInt_t), + ('qAvfsGb2', QuadraticInt_t), +] + +AvfsFuseOverride_t = struct_c__SA_AvfsFuseOverride_t +class struct_c__SA_SkuTable_t(Structure): + pass + +struct_c__SA_SkuTable_t._pack_ = 1 # source:False +struct_c__SA_SkuTable_t._fields_ = [ + ('Version', ctypes.c_uint32), + ('FeaturesToRun', ctypes.c_uint32 * 2), + ('TotalPowerConfig', ctypes.c_ubyte), + ('CustomerVariant', ctypes.c_ubyte), + ('MemoryTemperatureTypeMask', ctypes.c_ubyte), + ('SmartShiftVersion', ctypes.c_ubyte), + ('SocketPowerLimitAc', ctypes.c_uint16 * 4), + ('SocketPowerLimitDc', ctypes.c_uint16 * 4), + ('SocketPowerLimitSmartShift2', ctypes.c_uint16), + ('EnableLegacyPptLimit', ctypes.c_ubyte), + ('UseInputTelemetry', ctypes.c_ubyte), + ('SmartShiftMinReportedPptinDcs', ctypes.c_ubyte), + ('PaddingPpt', ctypes.c_ubyte * 1), + ('VrTdcLimit', ctypes.c_uint16 * 3), + ('PlatformTdcLimit', ctypes.c_uint16 * 3), + ('TemperatureLimit', ctypes.c_uint16 * 13), + ('HwCtfTempLimit', ctypes.c_uint16), + ('PaddingInfra', ctypes.c_uint16), + ('FitControllerFailureRateLimit', ctypes.c_uint32), + ('FitControllerGfxDutyCycle', ctypes.c_uint32), + ('FitControllerSocDutyCycle', ctypes.c_uint32), + ('FitControllerSocOffset', ctypes.c_uint32), + ('GfxApccPlusResidencyLimit', ctypes.c_uint32), + ('ThrottlerControlMask', ctypes.c_uint32), + ('FwDStateMask', ctypes.c_uint32), + ('UlvVoltageOffset', ctypes.c_uint16 * 2), + ('UlvVoltageOffsetU', ctypes.c_uint16), + ('DeepUlvVoltageOffsetSoc', ctypes.c_uint16), + ('DefaultMaxVoltage', ctypes.c_uint16 * 2), + ('BoostMaxVoltage', ctypes.c_uint16 * 2), + ('VminTempHystersis', ctypes.c_int16 * 2), + ('VminTempThreshold', ctypes.c_int16 * 2), + ('Vmin_Hot_T0', ctypes.c_uint16 * 2), + ('Vmin_Cold_T0', ctypes.c_uint16 * 2), + ('Vmin_Hot_Eol', ctypes.c_uint16 * 2), + ('Vmin_Cold_Eol', ctypes.c_uint16 * 2), + ('Vmin_Aging_Offset', ctypes.c_uint16 * 2), + ('Spare_Vmin_Plat_Offset_Hot', ctypes.c_uint16 * 2), + ('Spare_Vmin_Plat_Offset_Cold', ctypes.c_uint16 * 2), + ('VcBtcFixedVminAgingOffset', ctypes.c_uint16 * 2), + ('VcBtcVmin2PsmDegrationGb', ctypes.c_uint16 * 2), + ('VcBtcPsmA', ctypes.c_uint32 * 2), + ('VcBtcPsmB', ctypes.c_uint32 * 2), + ('VcBtcVminA', ctypes.c_uint32 * 2), + ('VcBtcVminB', ctypes.c_uint32 * 2), + ('PerPartVminEnabled', ctypes.c_ubyte * 2), + ('VcBtcEnabled', ctypes.c_ubyte * 2), + ('SocketPowerLimitAcTau', ctypes.c_uint16 * 4), + ('SocketPowerLimitDcTau', ctypes.c_uint16 * 4), + ('Vmin_droop', QuadraticInt_t), + ('SpareVmin', ctypes.c_uint32 * 9), + ('DpmDescriptor', struct_c__SA_DpmDescriptor_t * 13), + ('FreqTableGfx', ctypes.c_uint16 * 16), + ('FreqTableVclk', ctypes.c_uint16 * 8), + ('FreqTableDclk', ctypes.c_uint16 * 8), + ('FreqTableSocclk', ctypes.c_uint16 * 8), + ('FreqTableUclk', ctypes.c_uint16 * 4), + ('FreqTableDispclk', ctypes.c_uint16 * 8), + ('FreqTableDppClk', ctypes.c_uint16 * 8), + ('FreqTableDprefclk', ctypes.c_uint16 * 8), + ('FreqTableDcfclk', ctypes.c_uint16 * 8), + ('FreqTableDtbclk', ctypes.c_uint16 * 8), + ('FreqTableFclk', ctypes.c_uint16 * 8), + ('DcModeMaxFreq', ctypes.c_uint32 * 13), + ('Mp0clkFreq', ctypes.c_uint16 * 2), + ('Mp0DpmVoltage', ctypes.c_uint16 * 2), + ('GfxclkSpare', ctypes.c_ubyte * 2), + ('GfxclkFreqCap', ctypes.c_uint16), + ('GfxclkFgfxoffEntry', ctypes.c_uint16), + ('GfxclkFgfxoffExitImu', ctypes.c_uint16), + ('GfxclkFgfxoffExitRlc', ctypes.c_uint16), + ('GfxclkThrottleClock', ctypes.c_uint16), + ('EnableGfxPowerStagesGpio', ctypes.c_ubyte), + ('GfxIdlePadding', ctypes.c_ubyte), + ('SmsRepairWRCKClkDivEn', ctypes.c_ubyte), + ('SmsRepairWRCKClkDivVal', ctypes.c_ubyte), + ('GfxOffEntryEarlyMGCGEn', ctypes.c_ubyte), + ('GfxOffEntryForceCGCGEn', ctypes.c_ubyte), + ('GfxOffEntryForceCGCGDelayEn', ctypes.c_ubyte), + ('GfxOffEntryForceCGCGDelayVal', ctypes.c_ubyte), + ('GfxclkFreqGfxUlv', ctypes.c_uint16), + ('GfxIdlePadding2', ctypes.c_ubyte * 2), + ('GfxOffEntryHysteresis', ctypes.c_uint32), + ('GfxoffSpare', ctypes.c_uint32 * 15), + ('DfllBtcMasterScalerM', ctypes.c_uint32), + ('DfllBtcMasterScalerB', ctypes.c_int32), + ('DfllBtcSlaveScalerM', ctypes.c_uint32), + ('DfllBtcSlaveScalerB', ctypes.c_int32), + ('DfllPccAsWaitCtrl', ctypes.c_uint32), + ('DfllPccAsStepCtrl', ctypes.c_uint32), + ('DfllL2FrequencyBoostM', ctypes.c_uint32), + ('DfllL2FrequencyBoostB', ctypes.c_uint32), + ('GfxGpoSpare', ctypes.c_uint32 * 8), + ('DcsGfxOffVoltage', ctypes.c_uint16), + ('PaddingDcs', ctypes.c_uint16), + ('DcsMinGfxOffTime', ctypes.c_uint16), + ('DcsMaxGfxOffTime', ctypes.c_uint16), + ('DcsMinCreditAccum', ctypes.c_uint32), + ('DcsExitHysteresis', ctypes.c_uint16), + ('DcsTimeout', ctypes.c_uint16), + ('FoptEnabled', ctypes.c_ubyte), + ('DcsSpare2', ctypes.c_ubyte * 3), + ('DcsFoptM', ctypes.c_uint32), + ('DcsFoptB', ctypes.c_uint32), + ('DcsSpare', ctypes.c_uint32 * 11), + ('ShadowFreqTableUclk', ctypes.c_uint16 * 4), + ('UseStrobeModeOptimizations', ctypes.c_ubyte), + ('PaddingMem', ctypes.c_ubyte * 3), + ('UclkDpmPstates', ctypes.c_ubyte * 4), + ('FreqTableUclkDiv', ctypes.c_ubyte * 4), + ('MemVmempVoltage', ctypes.c_uint16 * 4), + ('MemVddioVoltage', ctypes.c_uint16 * 4), + ('FclkDpmUPstates', ctypes.c_ubyte * 8), + ('FclkDpmVddU', ctypes.c_uint16 * 8), + ('FclkDpmUSpeed', ctypes.c_uint16 * 8), + ('FclkDpmDisallowPstateFreq', ctypes.c_uint16), + ('PaddingFclk', ctypes.c_uint16), + ('PcieGenSpeed', ctypes.c_ubyte * 3), + ('PcieLaneCount', ctypes.c_ubyte * 3), + ('LclkFreq', ctypes.c_uint16 * 3), + ('FanStopTemp', ctypes.c_uint16 * 13), + ('FanStartTemp', ctypes.c_uint16 * 13), + ('FanGain', ctypes.c_uint16 * 13), + ('FanGainPadding', ctypes.c_uint16), + ('FanPwmMin', ctypes.c_uint16), + ('AcousticTargetRpmThreshold', ctypes.c_uint16), + ('AcousticLimitRpmThreshold', ctypes.c_uint16), + ('FanMaximumRpm', ctypes.c_uint16), + ('MGpuAcousticLimitRpmThreshold', ctypes.c_uint16), + ('FanTargetGfxclk', ctypes.c_uint16), + ('TempInputSelectMask', ctypes.c_uint32), + ('FanZeroRpmEnable', ctypes.c_ubyte), + ('FanTachEdgePerRev', ctypes.c_ubyte), + ('FanTargetTemperature', ctypes.c_uint16 * 13), + ('FuzzyFan_ErrorSetDelta', ctypes.c_int16), + ('FuzzyFan_ErrorRateSetDelta', ctypes.c_int16), + ('FuzzyFan_PwmSetDelta', ctypes.c_int16), + ('FuzzyFan_Reserved', ctypes.c_uint16), + ('FwCtfLimit', ctypes.c_uint16 * 13), + ('IntakeTempEnableRPM', ctypes.c_uint16), + ('IntakeTempOffsetTemp', ctypes.c_int16), + ('IntakeTempReleaseTemp', ctypes.c_uint16), + ('IntakeTempHighIntakeAcousticLimit', ctypes.c_uint16), + ('IntakeTempAcouticLimitReleaseRate', ctypes.c_uint16), + ('FanAbnormalTempLimitOffset', ctypes.c_int16), + ('FanStalledTriggerRpm', ctypes.c_uint16), + ('FanAbnormalTriggerRpmCoeff', ctypes.c_uint16), + ('FanAbnormalDetectionEnable', ctypes.c_uint16), + ('FanIntakeSensorSupport', ctypes.c_ubyte), + ('FanIntakePadding', ctypes.c_ubyte * 3), + ('FanSpare', ctypes.c_uint32 * 13), + ('OverrideGfxAvfsFuses', ctypes.c_ubyte), + ('GfxAvfsPadding', ctypes.c_ubyte * 3), + ('L2HwRtAvfsFuses', ctypes.c_uint32 * 32), + ('SeHwRtAvfsFuses', ctypes.c_uint32 * 32), + ('CommonRtAvfs', ctypes.c_uint32 * 13), + ('L2FwRtAvfsFuses', ctypes.c_uint32 * 19), + ('SeFwRtAvfsFuses', ctypes.c_uint32 * 19), + ('Droop_PWL_F', ctypes.c_uint32 * 5), + ('Droop_PWL_a', ctypes.c_uint32 * 5), + ('Droop_PWL_b', ctypes.c_uint32 * 5), + ('Droop_PWL_c', ctypes.c_uint32 * 5), + ('Static_PWL_Offset', ctypes.c_uint32 * 5), + ('dGbV_dT_vmin', ctypes.c_uint32), + ('dGbV_dT_vmax', ctypes.c_uint32), + ('V2F_vmin_range_low', ctypes.c_uint32), + ('V2F_vmin_range_high', ctypes.c_uint32), + ('V2F_vmax_range_low', ctypes.c_uint32), + ('V2F_vmax_range_high', ctypes.c_uint32), + ('DcBtcGfxParams', AvfsDcBtcParams_t), + ('GfxAvfsSpare', ctypes.c_uint32 * 32), + ('OverrideSocAvfsFuses', ctypes.c_ubyte), + ('MinSocAvfsRevision', ctypes.c_ubyte), + ('SocAvfsPadding', ctypes.c_ubyte * 2), + ('SocAvfsFuseOverride', struct_c__SA_AvfsFuseOverride_t * 3), + ('dBtcGbSoc', struct_c__SA_DroopInt_t * 3), + ('qAgingGb', struct_c__SA_LinearInt_t * 3), + ('qStaticVoltageOffset', struct_c__SA_QuadraticInt_t * 3), + ('DcBtcSocParams', struct_c__SA_AvfsDcBtcParams_t * 3), + ('SocAvfsSpare', ctypes.c_uint32 * 32), + ('BootValues', BootValues_t), + ('DriverReportedClocks', DriverReportedClocks_t), + ('MsgLimits', MsgLimits_t), + ('OverDriveLimitsMin', OverDriveLimits_t), + ('OverDriveLimitsBasicMax', OverDriveLimits_t), + ('reserved', ctypes.c_uint32 * 22), + ('DebugOverrides', ctypes.c_uint32), + ('TotalBoardPowerSupport', ctypes.c_ubyte), + ('TotalBoardPowerPadding', ctypes.c_ubyte * 3), + ('TotalIdleBoardPowerM', ctypes.c_int16), + ('TotalIdleBoardPowerB', ctypes.c_int16), + ('TotalBoardPowerM', ctypes.c_int16), + ('TotalBoardPowerB', ctypes.c_int16), + ('qFeffCoeffGameClock', struct_c__SA_QuadraticInt_t * 2), + ('qFeffCoeffBaseClock', struct_c__SA_QuadraticInt_t * 2), + ('qFeffCoeffBoostClock', struct_c__SA_QuadraticInt_t * 2), + ('TemperatureLimit_Hynix', ctypes.c_uint16), + ('TemperatureLimit_Micron', ctypes.c_uint16), + ('TemperatureFwCtfLimit_Hynix', ctypes.c_uint16), + ('TemperatureFwCtfLimit_Micron', ctypes.c_uint16), + ('Spare', ctypes.c_uint32 * 41), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +SkuTable_t = struct_c__SA_SkuTable_t +class struct_c__SA_BoardTable_t(Structure): + pass + +struct_c__SA_BoardTable_t._pack_ = 1 # source:False +struct_c__SA_BoardTable_t._fields_ = [ + ('Version', ctypes.c_uint32), + ('I2cControllers', struct_c__SA_I2cControllerConfig_t * 8), + ('VddGfxVrMapping', ctypes.c_ubyte), + ('VddSocVrMapping', ctypes.c_ubyte), + ('VddMem0VrMapping', ctypes.c_ubyte), + ('VddMem1VrMapping', ctypes.c_ubyte), + ('GfxUlvPhaseSheddingMask', ctypes.c_ubyte), + ('SocUlvPhaseSheddingMask', ctypes.c_ubyte), + ('VmempUlvPhaseSheddingMask', ctypes.c_ubyte), + ('VddioUlvPhaseSheddingMask', ctypes.c_ubyte), + ('SlaveAddrMapping', ctypes.c_ubyte * 5), + ('VrPsiSupport', ctypes.c_ubyte * 5), + ('PaddingPsi', ctypes.c_ubyte * 5), + ('EnablePsi6', ctypes.c_ubyte * 5), + ('SviTelemetryScale', struct_c__SA_SviTelemetryScale_t * 5), + ('VoltageTelemetryRatio', ctypes.c_uint32 * 5), + ('DownSlewRateVr', ctypes.c_ubyte * 5), + ('LedOffGpio', ctypes.c_ubyte), + ('FanOffGpio', ctypes.c_ubyte), + ('GfxVrPowerStageOffGpio', ctypes.c_ubyte), + ('AcDcGpio', ctypes.c_ubyte), + ('AcDcPolarity', ctypes.c_ubyte), + ('VR0HotGpio', ctypes.c_ubyte), + ('VR0HotPolarity', ctypes.c_ubyte), + ('GthrGpio', ctypes.c_ubyte), + ('GthrPolarity', ctypes.c_ubyte), + ('LedPin0', ctypes.c_ubyte), + ('LedPin1', ctypes.c_ubyte), + ('LedPin2', ctypes.c_ubyte), + ('LedEnableMask', ctypes.c_ubyte), + ('LedPcie', ctypes.c_ubyte), + ('LedError', ctypes.c_ubyte), + ('UclkTrainingModeSpreadPercent', ctypes.c_ubyte), + ('UclkSpreadPadding', ctypes.c_ubyte), + ('UclkSpreadFreq', ctypes.c_uint16), + ('UclkSpreadPercent', ctypes.c_ubyte * 16), + ('GfxclkSpreadEnable', ctypes.c_ubyte), + ('FclkSpreadPercent', ctypes.c_ubyte), + ('FclkSpreadFreq', ctypes.c_uint16), + ('DramWidth', ctypes.c_ubyte), + ('PaddingMem1', ctypes.c_ubyte * 7), + ('HsrEnabled', ctypes.c_ubyte), + ('VddqOffEnabled', ctypes.c_ubyte), + ('PaddingUmcFlags', ctypes.c_ubyte * 2), + ('PostVoltageSetBacoDelay', ctypes.c_uint32), + ('BacoEntryDelay', ctypes.c_uint32), + ('FuseWritePowerMuxPresent', ctypes.c_ubyte), + ('FuseWritePadding', ctypes.c_ubyte * 3), + ('BoardSpare', ctypes.c_uint32 * 63), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +BoardTable_t = struct_c__SA_BoardTable_t +class struct_c__SA_PPTable_t(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('SkuTable', SkuTable_t), + ('BoardTable', BoardTable_t), + ] + +PPTable_t = struct_c__SA_PPTable_t +class struct_c__SA_DriverSmuConfig_t(Structure): + pass + +struct_c__SA_DriverSmuConfig_t._pack_ = 1 # source:False +struct_c__SA_DriverSmuConfig_t._fields_ = [ + ('GfxclkAverageLpfTau', ctypes.c_uint16), + ('FclkAverageLpfTau', ctypes.c_uint16), + ('UclkAverageLpfTau', ctypes.c_uint16), + ('GfxActivityLpfTau', ctypes.c_uint16), + ('UclkActivityLpfTau', ctypes.c_uint16), + ('SocketPowerLpfTau', ctypes.c_uint16), + ('VcnClkAverageLpfTau', ctypes.c_uint16), + ('VcnUsageAverageLpfTau', ctypes.c_uint16), +] + +DriverSmuConfig_t = struct_c__SA_DriverSmuConfig_t +class struct_c__SA_DriverSmuConfigExternal_t(Structure): + pass + +struct_c__SA_DriverSmuConfigExternal_t._pack_ = 1 # source:False +struct_c__SA_DriverSmuConfigExternal_t._fields_ = [ + ('DriverSmuConfig', DriverSmuConfig_t), + ('Spare', ctypes.c_uint32 * 8), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +DriverSmuConfigExternal_t = struct_c__SA_DriverSmuConfigExternal_t +class struct_c__SA_DriverInfoTable_t(Structure): + pass + +struct_c__SA_DriverInfoTable_t._pack_ = 1 # source:False +struct_c__SA_DriverInfoTable_t._fields_ = [ + ('FreqTableGfx', ctypes.c_uint16 * 16), + ('FreqTableVclk', ctypes.c_uint16 * 8), + ('FreqTableDclk', ctypes.c_uint16 * 8), + ('FreqTableSocclk', ctypes.c_uint16 * 8), + ('FreqTableUclk', ctypes.c_uint16 * 4), + ('FreqTableDispclk', ctypes.c_uint16 * 8), + ('FreqTableDppClk', ctypes.c_uint16 * 8), + ('FreqTableDprefclk', ctypes.c_uint16 * 8), + ('FreqTableDcfclk', ctypes.c_uint16 * 8), + ('FreqTableDtbclk', ctypes.c_uint16 * 8), + ('FreqTableFclk', ctypes.c_uint16 * 8), + ('DcModeMaxFreq', ctypes.c_uint16 * 13), + ('Padding', ctypes.c_uint16), + ('Spare', ctypes.c_uint32 * 32), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +DriverInfoTable_t = struct_c__SA_DriverInfoTable_t +class struct_c__SA_SmuMetrics_t(Structure): + pass + +struct_c__SA_SmuMetrics_t._pack_ = 1 # source:False +struct_c__SA_SmuMetrics_t._fields_ = [ + ('CurrClock', ctypes.c_uint32 * 13), + ('AverageGfxclkFrequencyTarget', ctypes.c_uint16), + ('AverageGfxclkFrequencyPreDs', ctypes.c_uint16), + ('AverageGfxclkFrequencyPostDs', ctypes.c_uint16), + ('AverageFclkFrequencyPreDs', ctypes.c_uint16), + ('AverageFclkFrequencyPostDs', ctypes.c_uint16), + ('AverageMemclkFrequencyPreDs', ctypes.c_uint16), + ('AverageMemclkFrequencyPostDs', ctypes.c_uint16), + ('AverageVclk0Frequency', ctypes.c_uint16), + ('AverageDclk0Frequency', ctypes.c_uint16), + ('AverageVclk1Frequency', ctypes.c_uint16), + ('AverageDclk1Frequency', ctypes.c_uint16), + ('PCIeBusy', ctypes.c_uint16), + ('dGPU_W_MAX', ctypes.c_uint16), + ('padding', ctypes.c_uint16), + ('MetricsCounter', ctypes.c_uint32), + ('AvgVoltage', ctypes.c_uint16 * 5), + ('AvgCurrent', ctypes.c_uint16 * 5), + ('AverageGfxActivity', ctypes.c_uint16), + ('AverageUclkActivity', ctypes.c_uint16), + ('Vcn0ActivityPercentage', ctypes.c_uint16), + ('Vcn1ActivityPercentage', ctypes.c_uint16), + ('EnergyAccumulator', ctypes.c_uint32), + ('AverageSocketPower', ctypes.c_uint16), + ('AverageTotalBoardPower', ctypes.c_uint16), + ('AvgTemperature', ctypes.c_uint16 * 13), + ('AvgTemperatureFanIntake', ctypes.c_uint16), + ('PcieRate', ctypes.c_ubyte), + ('PcieWidth', ctypes.c_ubyte), + ('AvgFanPwm', ctypes.c_ubyte), + ('Padding', ctypes.c_ubyte * 1), + ('AvgFanRpm', ctypes.c_uint16), + ('ThrottlingPercentage', ctypes.c_ubyte * 22), + ('VmaxThrottlingPercentage', ctypes.c_ubyte), + ('Padding1', ctypes.c_ubyte * 3), + ('D3HotEntryCountPerMode', ctypes.c_uint32 * 4), + ('D3HotExitCountPerMode', ctypes.c_uint32 * 4), + ('ArmMsgReceivedCountPerMode', ctypes.c_uint32 * 4), + ('ApuSTAPMSmartShiftLimit', ctypes.c_uint16), + ('ApuSTAPMLimit', ctypes.c_uint16), + ('AvgApuSocketPower', ctypes.c_uint16), + ('AverageUclkActivity_MAX', ctypes.c_uint16), + ('PublicSerialNumberLower', ctypes.c_uint32), + ('PublicSerialNumberUpper', ctypes.c_uint32), +] + +SmuMetrics_t = struct_c__SA_SmuMetrics_t +class struct_c__SA_SmuMetricsExternal_t(Structure): + pass + +struct_c__SA_SmuMetricsExternal_t._pack_ = 1 # source:False +struct_c__SA_SmuMetricsExternal_t._fields_ = [ + ('SmuMetrics', SmuMetrics_t), + ('Spare', ctypes.c_uint32 * 29), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +SmuMetricsExternal_t = struct_c__SA_SmuMetricsExternal_t +class struct_c__SA_WatermarkRowGeneric_t(Structure): + pass + +struct_c__SA_WatermarkRowGeneric_t._pack_ = 1 # source:False +struct_c__SA_WatermarkRowGeneric_t._fields_ = [ + ('WmSetting', ctypes.c_ubyte), + ('Flags', ctypes.c_ubyte), + ('Padding', ctypes.c_ubyte * 2), +] + +WatermarkRowGeneric_t = struct_c__SA_WatermarkRowGeneric_t + +# values for enumeration 'c__EA_WATERMARKS_FLAGS_e' +c__EA_WATERMARKS_FLAGS_e__enumvalues = { + 0: 'WATERMARKS_CLOCK_RANGE', + 1: 'WATERMARKS_DUMMY_PSTATE', + 2: 'WATERMARKS_MALL', + 3: 'WATERMARKS_COUNT', +} +WATERMARKS_CLOCK_RANGE = 0 +WATERMARKS_DUMMY_PSTATE = 1 +WATERMARKS_MALL = 2 +WATERMARKS_COUNT = 3 +c__EA_WATERMARKS_FLAGS_e = ctypes.c_uint32 # enum +WATERMARKS_FLAGS_e = c__EA_WATERMARKS_FLAGS_e +WATERMARKS_FLAGS_e__enumvalues = c__EA_WATERMARKS_FLAGS_e__enumvalues +class struct_c__SA_Watermarks_t(Structure): + _pack_ = 1 # source:False + _fields_ = [ + ('WatermarkRow', struct_c__SA_WatermarkRowGeneric_t * 4), + ] + +Watermarks_t = struct_c__SA_Watermarks_t +class struct_c__SA_WatermarksExternal_t(Structure): + pass + +struct_c__SA_WatermarksExternal_t._pack_ = 1 # source:False +struct_c__SA_WatermarksExternal_t._fields_ = [ + ('Watermarks', Watermarks_t), + ('Spare', ctypes.c_uint32 * 16), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +WatermarksExternal_t = struct_c__SA_WatermarksExternal_t +class struct_c__SA_AvfsDebugTable_t(Structure): + pass + +struct_c__SA_AvfsDebugTable_t._pack_ = 1 # source:False +struct_c__SA_AvfsDebugTable_t._fields_ = [ + ('avgPsmCount', ctypes.c_uint16 * 214), + ('minPsmCount', ctypes.c_uint16 * 214), + ('avgPsmVoltage', ctypes.c_float * 214), + ('minPsmVoltage', ctypes.c_float * 214), +] + +AvfsDebugTable_t = struct_c__SA_AvfsDebugTable_t +class struct_c__SA_AvfsDebugTableExternal_t(Structure): + pass + +struct_c__SA_AvfsDebugTableExternal_t._pack_ = 1 # source:False +struct_c__SA_AvfsDebugTableExternal_t._fields_ = [ + ('AvfsDebugTable', AvfsDebugTable_t), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +AvfsDebugTableExternal_t = struct_c__SA_AvfsDebugTableExternal_t +class struct_c__SA_DpmActivityMonitorCoeffInt_t(Structure): + pass + +struct_c__SA_DpmActivityMonitorCoeffInt_t._pack_ = 1 # source:False +struct_c__SA_DpmActivityMonitorCoeffInt_t._fields_ = [ + ('Gfx_ActiveHystLimit', ctypes.c_ubyte), + ('Gfx_IdleHystLimit', ctypes.c_ubyte), + ('Gfx_FPS', ctypes.c_ubyte), + ('Gfx_MinActiveFreqType', ctypes.c_ubyte), + ('Gfx_BoosterFreqType', ctypes.c_ubyte), + ('PaddingGfx', ctypes.c_ubyte), + ('Gfx_MinActiveFreq', ctypes.c_uint16), + ('Gfx_BoosterFreq', ctypes.c_uint16), + ('Gfx_PD_Data_time_constant', ctypes.c_uint16), + ('Gfx_PD_Data_limit_a', ctypes.c_uint32), + ('Gfx_PD_Data_limit_b', ctypes.c_uint32), + ('Gfx_PD_Data_limit_c', ctypes.c_uint32), + ('Gfx_PD_Data_error_coeff', ctypes.c_uint32), + ('Gfx_PD_Data_error_rate_coeff', ctypes.c_uint32), + ('Fclk_ActiveHystLimit', ctypes.c_ubyte), + ('Fclk_IdleHystLimit', ctypes.c_ubyte), + ('Fclk_FPS', ctypes.c_ubyte), + ('Fclk_MinActiveFreqType', ctypes.c_ubyte), + ('Fclk_BoosterFreqType', ctypes.c_ubyte), + ('PaddingFclk', ctypes.c_ubyte), + ('Fclk_MinActiveFreq', ctypes.c_uint16), + ('Fclk_BoosterFreq', ctypes.c_uint16), + ('Fclk_PD_Data_time_constant', ctypes.c_uint16), + ('Fclk_PD_Data_limit_a', ctypes.c_uint32), + ('Fclk_PD_Data_limit_b', ctypes.c_uint32), + ('Fclk_PD_Data_limit_c', ctypes.c_uint32), + ('Fclk_PD_Data_error_coeff', ctypes.c_uint32), + ('Fclk_PD_Data_error_rate_coeff', ctypes.c_uint32), + ('Mem_UpThreshold_Limit', ctypes.c_uint32 * 4), + ('Mem_UpHystLimit', ctypes.c_ubyte * 4), + ('Mem_DownHystLimit', ctypes.c_ubyte * 4), + ('Mem_Fps', ctypes.c_uint16), + ('padding', ctypes.c_ubyte * 2), +] + +DpmActivityMonitorCoeffInt_t = struct_c__SA_DpmActivityMonitorCoeffInt_t +class struct_c__SA_DpmActivityMonitorCoeffIntExternal_t(Structure): + pass + +struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._pack_ = 1 # source:False +struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._fields_ = [ + ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), + ('MmHubPadding', ctypes.c_uint32 * 8), +] + +DpmActivityMonitorCoeffIntExternal_t = struct_c__SA_DpmActivityMonitorCoeffIntExternal_t +__AMDGPU_SMU_H__ = True # macro +u32 = True # macro +SMU_THERMAL_MINIMUM_ALERT_TEMP = 0 # macro +SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255 # macro +SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000 # macro +SMU_FW_NAME_LEN = 0x24 # macro +SMU_DPM_USER_PROFILE_RESTORE = (1<<0) # macro +SMU_CUSTOM_FAN_SPEED_RPM = (1<<1) # macro +SMU_CUSTOM_FAN_SPEED_PWM = (1<<2) # macro +SMU_THROTTLER_PPT0_BIT = 0 # macro +SMU_THROTTLER_PPT1_BIT = 1 # macro +SMU_THROTTLER_PPT2_BIT = 2 # macro +SMU_THROTTLER_PPT3_BIT = 3 # macro +SMU_THROTTLER_SPL_BIT = 4 # macro +SMU_THROTTLER_FPPT_BIT = 5 # macro +SMU_THROTTLER_SPPT_BIT = 6 # macro +SMU_THROTTLER_SPPT_APU_BIT = 7 # macro +SMU_THROTTLER_TDC_GFX_BIT = 16 # macro +SMU_THROTTLER_TDC_SOC_BIT = 17 # macro +SMU_THROTTLER_TDC_MEM_BIT = 18 # macro +SMU_THROTTLER_TDC_VDD_BIT = 19 # macro +SMU_THROTTLER_TDC_CVIP_BIT = 20 # macro +SMU_THROTTLER_EDC_CPU_BIT = 21 # macro +SMU_THROTTLER_EDC_GFX_BIT = 22 # macro +SMU_THROTTLER_APCC_BIT = 23 # macro +SMU_THROTTLER_TEMP_GPU_BIT = 32 # macro +SMU_THROTTLER_TEMP_CORE_BIT = 33 # macro +SMU_THROTTLER_TEMP_MEM_BIT = 34 # macro +SMU_THROTTLER_TEMP_EDGE_BIT = 35 # macro +SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36 # macro +SMU_THROTTLER_TEMP_SOC_BIT = 37 # macro +SMU_THROTTLER_TEMP_VR_GFX_BIT = 38 # macro +SMU_THROTTLER_TEMP_VR_SOC_BIT = 39 # macro +SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40 # macro +SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41 # macro +SMU_THROTTLER_TEMP_LIQUID0_BIT = 42 # macro +SMU_THROTTLER_TEMP_LIQUID1_BIT = 43 # macro +SMU_THROTTLER_VRHOT0_BIT = 44 # macro +SMU_THROTTLER_VRHOT1_BIT = 45 # macro +SMU_THROTTLER_PROCHOT_CPU_BIT = 46 # macro +SMU_THROTTLER_PROCHOT_GFX_BIT = 47 # macro +SMU_THROTTLER_PPM_BIT = 56 # macro +SMU_THROTTLER_FIT_BIT = 57 # macro +# def SMU_TABLE_INIT(tables, table_id, s, a, d): # macro +# return {tables[table_id].size=s;tables[table_id].align=a;tables[table_id].domain=d;}(0) +class struct_smu_hw_power_state(Structure): + pass + +struct_smu_hw_power_state._pack_ = 1 # source:False +struct_smu_hw_power_state._fields_ = [ + ('magic', ctypes.c_uint32), +] + +class struct_smu_power_state(Structure): + pass + + +# values for enumeration 'smu_state_ui_label' +smu_state_ui_label__enumvalues = { + 0: 'SMU_STATE_UI_LABEL_NONE', + 1: 'SMU_STATE_UI_LABEL_BATTERY', + 2: 'SMU_STATE_UI_TABEL_MIDDLE_LOW', + 3: 'SMU_STATE_UI_LABEL_BALLANCED', + 4: 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', + 5: 'SMU_STATE_UI_LABEL_PERFORMANCE', + 6: 'SMU_STATE_UI_LABEL_BACO', +} +SMU_STATE_UI_LABEL_NONE = 0 +SMU_STATE_UI_LABEL_BATTERY = 1 +SMU_STATE_UI_TABEL_MIDDLE_LOW = 2 +SMU_STATE_UI_LABEL_BALLANCED = 3 +SMU_STATE_UI_LABEL_MIDDLE_HIGHT = 4 +SMU_STATE_UI_LABEL_PERFORMANCE = 5 +SMU_STATE_UI_LABEL_BACO = 6 +smu_state_ui_label = ctypes.c_uint32 # enum + +# values for enumeration 'smu_state_classification_flag' +smu_state_classification_flag__enumvalues = { + 1: 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', + 2: 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', + 4: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', + 8: 'SMU_STATE_CLASSIFICATION_FLAG_RESET', + 16: 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', + 32: 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', + 64: 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', + 128: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', + 256: 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', + 512: 'SMU_STATE_CLASSIFICATION_FLAG_UVD', + 1024: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', + 2048: 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', + 4096: 'SMU_STATE_CLASSIFICATION_FLAG_HD2', + 8192: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', + 16384: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', + 32768: 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', + 65536: 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', + 131072: 'SMU_STATE_CLASSIFICATION_FLAG_BACO', + 262144: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', + 524288: 'SMU_STATE_CLASSIFICATION_FLAG_ULV', + 1048576: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', +} +SMU_STATE_CLASSIFICATION_FLAG_BOOT = 1 +SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 2 +SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 4 +SMU_STATE_CLASSIFICATION_FLAG_RESET = 8 +SMU_STATE_CLASSIFICATION_FLAG_FORCED = 16 +SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 32 +SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 64 +SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 128 +SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 256 +SMU_STATE_CLASSIFICATION_FLAG_UVD = 512 +SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 1024 +SMU_STATE_CLASSIFICATION_FLAG_ACPI = 2048 +SMU_STATE_CLASSIFICATION_FLAG_HD2 = 4096 +SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 8192 +SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 16384 +SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 32768 +SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 65536 +SMU_STATE_CLASSIFICATION_FLAG_BACO = 131072 +SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 262144 +SMU_STATE_CLASSIFICATION_FLAG_ULV = 524288 +SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 1048576 +smu_state_classification_flag = ctypes.c_uint32 # enum +class struct_smu_state_classification_block(Structure): + pass + +struct_smu_state_classification_block._pack_ = 1 # source:False +struct_smu_state_classification_block._fields_ = [ + ('ui_label', smu_state_ui_label), + ('flags', smu_state_classification_flag), + ('bios_index', ctypes.c_int32), + ('temporary_state', ctypes.c_bool), + ('to_be_deleted', ctypes.c_bool), + ('PADDING_0', ctypes.c_ubyte * 2), +] + +class struct_smu_state_pcie_block(Structure): + pass + +struct_smu_state_pcie_block._pack_ = 1 # source:False +struct_smu_state_pcie_block._fields_ = [ + ('lanes', ctypes.c_uint32), +] + + +# values for enumeration 'smu_refreshrate_source' +smu_refreshrate_source__enumvalues = { + 0: 'SMU_REFRESHRATE_SOURCE_EDID', + 1: 'SMU_REFRESHRATE_SOURCE_EXPLICIT', +} +SMU_REFRESHRATE_SOURCE_EDID = 0 +SMU_REFRESHRATE_SOURCE_EXPLICIT = 1 +smu_refreshrate_source = ctypes.c_uint32 # enum +class struct_smu_state_display_block(Structure): + pass + +struct_smu_state_display_block._pack_ = 1 # source:False +struct_smu_state_display_block._fields_ = [ + ('disable_frame_modulation', ctypes.c_bool), + ('limit_refreshrate', ctypes.c_bool), + ('PADDING_0', ctypes.c_ubyte * 2), + ('refreshrate_source', smu_refreshrate_source), + ('explicit_refreshrate', ctypes.c_int32), + ('edid_refreshrate_index', ctypes.c_int32), + ('enable_vari_bright', ctypes.c_bool), + ('PADDING_1', ctypes.c_ubyte * 3), +] + +class struct_smu_state_memory_block(Structure): + pass + +struct_smu_state_memory_block._pack_ = 1 # source:False +struct_smu_state_memory_block._fields_ = [ + ('dll_off', ctypes.c_bool), + ('m3arb', ctypes.c_ubyte), + ('unused', ctypes.c_ubyte * 3), +] + +class struct_smu_state_software_algorithm_block(Structure): + pass + +struct_smu_state_software_algorithm_block._pack_ = 1 # source:False +struct_smu_state_software_algorithm_block._fields_ = [ + ('disable_load_balancing', ctypes.c_bool), + ('enable_sleep_for_timestamps', ctypes.c_bool), +] + +class struct_smu_temperature_range(Structure): + pass + +struct_smu_temperature_range._pack_ = 1 # source:False +struct_smu_temperature_range._fields_ = [ + ('min', ctypes.c_int32), + ('max', ctypes.c_int32), + ('edge_emergency_max', ctypes.c_int32), + ('hotspot_min', ctypes.c_int32), + ('hotspot_crit_max', ctypes.c_int32), + ('hotspot_emergency_max', ctypes.c_int32), + ('mem_min', ctypes.c_int32), + ('mem_crit_max', ctypes.c_int32), + ('mem_emergency_max', ctypes.c_int32), + ('software_shutdown_temp', ctypes.c_int32), + ('software_shutdown_temp_offset', ctypes.c_int32), +] + +class struct_smu_state_validation_block(Structure): + pass + +struct_smu_state_validation_block._pack_ = 1 # source:False +struct_smu_state_validation_block._fields_ = [ + ('single_display_only', ctypes.c_bool), + ('disallow_on_dc', ctypes.c_bool), + ('supported_power_levels', ctypes.c_ubyte), +] + +class struct_smu_uvd_clocks(Structure): + pass + +struct_smu_uvd_clocks._pack_ = 1 # source:False +struct_smu_uvd_clocks._fields_ = [ + ('vclk', ctypes.c_uint32), + ('dclk', ctypes.c_uint32), +] + + +# values for enumeration 'smu_power_src_type' +smu_power_src_type__enumvalues = { + 0: 'SMU_POWER_SOURCE_AC', + 1: 'SMU_POWER_SOURCE_DC', + 2: 'SMU_POWER_SOURCE_COUNT', +} +SMU_POWER_SOURCE_AC = 0 +SMU_POWER_SOURCE_DC = 1 +SMU_POWER_SOURCE_COUNT = 2 +smu_power_src_type = ctypes.c_uint32 # enum + +# values for enumeration 'smu_ppt_limit_type' +smu_ppt_limit_type__enumvalues = { + 0: 'SMU_DEFAULT_PPT_LIMIT', + 1: 'SMU_FAST_PPT_LIMIT', +} +SMU_DEFAULT_PPT_LIMIT = 0 +SMU_FAST_PPT_LIMIT = 1 +smu_ppt_limit_type = ctypes.c_uint32 # enum + +# values for enumeration 'smu_ppt_limit_level' +smu_ppt_limit_level__enumvalues = { + -1: 'SMU_PPT_LIMIT_MIN', + 0: 'SMU_PPT_LIMIT_CURRENT', + 1: 'SMU_PPT_LIMIT_DEFAULT', + 2: 'SMU_PPT_LIMIT_MAX', +} +SMU_PPT_LIMIT_MIN = -1 +SMU_PPT_LIMIT_CURRENT = 0 +SMU_PPT_LIMIT_DEFAULT = 1 +SMU_PPT_LIMIT_MAX = 2 +smu_ppt_limit_level = ctypes.c_int32 # enum + +# values for enumeration 'smu_memory_pool_size' +smu_memory_pool_size__enumvalues = { + 0: 'SMU_MEMORY_POOL_SIZE_ZERO', + 268435456: 'SMU_MEMORY_POOL_SIZE_256_MB', + 536870912: 'SMU_MEMORY_POOL_SIZE_512_MB', + 1073741824: 'SMU_MEMORY_POOL_SIZE_1_GB', + 2147483648: 'SMU_MEMORY_POOL_SIZE_2_GB', +} +SMU_MEMORY_POOL_SIZE_ZERO = 0 +SMU_MEMORY_POOL_SIZE_256_MB = 268435456 +SMU_MEMORY_POOL_SIZE_512_MB = 536870912 +SMU_MEMORY_POOL_SIZE_1_GB = 1073741824 +SMU_MEMORY_POOL_SIZE_2_GB = 2147483648 +smu_memory_pool_size = ctypes.c_uint32 # enum + +# values for enumeration 'smu_clk_type' +smu_clk_type__enumvalues = { + 0: 'SMU_GFXCLK', + 1: 'SMU_VCLK', + 2: 'SMU_DCLK', + 3: 'SMU_VCLK1', + 4: 'SMU_DCLK1', + 5: 'SMU_ECLK', + 6: 'SMU_SOCCLK', + 7: 'SMU_UCLK', + 8: 'SMU_DCEFCLK', + 9: 'SMU_DISPCLK', + 10: 'SMU_PIXCLK', + 11: 'SMU_PHYCLK', + 12: 'SMU_FCLK', + 13: 'SMU_SCLK', + 14: 'SMU_MCLK', + 15: 'SMU_PCIE', + 16: 'SMU_LCLK', + 17: 'SMU_OD_CCLK', + 18: 'SMU_OD_SCLK', + 19: 'SMU_OD_MCLK', + 20: 'SMU_OD_VDDC_CURVE', + 21: 'SMU_OD_RANGE', + 22: 'SMU_OD_VDDGFX_OFFSET', + 23: 'SMU_OD_FAN_CURVE', + 24: 'SMU_OD_ACOUSTIC_LIMIT', + 25: 'SMU_OD_ACOUSTIC_TARGET', + 26: 'SMU_OD_FAN_TARGET_TEMPERATURE', + 27: 'SMU_OD_FAN_MINIMUM_PWM', + 28: 'SMU_CLK_COUNT', +} +SMU_GFXCLK = 0 +SMU_VCLK = 1 +SMU_DCLK = 2 +SMU_VCLK1 = 3 +SMU_DCLK1 = 4 +SMU_ECLK = 5 +SMU_SOCCLK = 6 +SMU_UCLK = 7 +SMU_DCEFCLK = 8 +SMU_DISPCLK = 9 +SMU_PIXCLK = 10 +SMU_PHYCLK = 11 +SMU_FCLK = 12 +SMU_SCLK = 13 +SMU_MCLK = 14 +SMU_PCIE = 15 +SMU_LCLK = 16 +SMU_OD_CCLK = 17 +SMU_OD_SCLK = 18 +SMU_OD_MCLK = 19 +SMU_OD_VDDC_CURVE = 20 +SMU_OD_RANGE = 21 +SMU_OD_VDDGFX_OFFSET = 22 +SMU_OD_FAN_CURVE = 23 +SMU_OD_ACOUSTIC_LIMIT = 24 +SMU_OD_ACOUSTIC_TARGET = 25 +SMU_OD_FAN_TARGET_TEMPERATURE = 26 +SMU_OD_FAN_MINIMUM_PWM = 27 +SMU_CLK_COUNT = 28 +smu_clk_type = ctypes.c_uint32 # enum +class struct_smu_user_dpm_profile(Structure): + pass + +struct_smu_user_dpm_profile._pack_ = 1 # source:False +struct_smu_user_dpm_profile._fields_ = [ + ('fan_mode', ctypes.c_uint32), + ('power_limit', ctypes.c_uint32), + ('fan_speed_pwm', ctypes.c_uint32), + ('fan_speed_rpm', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('user_od', ctypes.c_uint32), + ('clk_mask', ctypes.c_uint32 * 28), + ('clk_dependency', ctypes.c_uint32), +] + +class struct_smu_table(Structure): + pass + +class struct_amdgpu_bo(Structure): + pass + +struct_smu_table._pack_ = 1 # source:False +struct_smu_table._fields_ = [ + ('size', ctypes.c_uint64), + ('align', ctypes.c_uint32), + ('domain', ctypes.c_ubyte), + ('PADDING_0', ctypes.c_ubyte * 3), + ('mc_address', ctypes.c_uint64), + ('cpu_addr', ctypes.POINTER(None)), + ('bo', ctypes.POINTER(struct_amdgpu_bo)), + ('version', ctypes.c_uint32), + ('PADDING_1', ctypes.c_ubyte * 4), +] + + +# values for enumeration 'smu_perf_level_designation' +smu_perf_level_designation__enumvalues = { + 0: 'PERF_LEVEL_ACTIVITY', + 1: 'PERF_LEVEL_POWER_CONTAINMENT', +} +PERF_LEVEL_ACTIVITY = 0 +PERF_LEVEL_POWER_CONTAINMENT = 1 +smu_perf_level_designation = ctypes.c_uint32 # enum +class struct_smu_performance_level(Structure): + pass + +struct_smu_performance_level._pack_ = 1 # source:False +struct_smu_performance_level._fields_ = [ + ('core_clock', ctypes.c_uint32), + ('memory_clock', ctypes.c_uint32), + ('vddc', ctypes.c_uint32), + ('vddci', ctypes.c_uint32), + ('non_local_mem_freq', ctypes.c_uint32), + ('non_local_mem_width', ctypes.c_uint32), +] + +class struct_smu_clock_info(Structure): + pass + +struct_smu_clock_info._pack_ = 1 # source:False +struct_smu_clock_info._fields_ = [ + ('min_mem_clk', ctypes.c_uint32), + ('max_mem_clk', ctypes.c_uint32), + ('min_eng_clk', ctypes.c_uint32), + ('max_eng_clk', ctypes.c_uint32), + ('min_bus_bandwidth', ctypes.c_uint32), + ('max_bus_bandwidth', ctypes.c_uint32), +] + +class struct_smu_bios_boot_up_values(Structure): + pass + +struct_smu_bios_boot_up_values._pack_ = 1 # source:False +struct_smu_bios_boot_up_values._fields_ = [ + ('revision', ctypes.c_uint32), + ('gfxclk', ctypes.c_uint32), + ('uclk', ctypes.c_uint32), + ('socclk', ctypes.c_uint32), + ('dcefclk', ctypes.c_uint32), + ('eclk', ctypes.c_uint32), + ('vclk', ctypes.c_uint32), + ('dclk', ctypes.c_uint32), + ('vddc', ctypes.c_uint16), + ('vddci', ctypes.c_uint16), + ('mvddc', ctypes.c_uint16), + ('vdd_gfx', ctypes.c_uint16), + ('cooling_id', ctypes.c_ubyte), + ('PADDING_0', ctypes.c_ubyte * 3), + ('pp_table_id', ctypes.c_uint32), + ('format_revision', ctypes.c_uint32), + ('content_revision', ctypes.c_uint32), + ('fclk', ctypes.c_uint32), + ('lclk', ctypes.c_uint32), + ('firmware_caps', ctypes.c_uint32), +] + + +# values for enumeration 'smu_table_id' +smu_table_id__enumvalues = { + 0: 'SMU_TABLE_PPTABLE', + 1: 'SMU_TABLE_WATERMARKS', + 2: 'SMU_TABLE_CUSTOM_DPM', + 3: 'SMU_TABLE_DPMCLOCKS', + 4: 'SMU_TABLE_AVFS', + 5: 'SMU_TABLE_AVFS_PSM_DEBUG', + 6: 'SMU_TABLE_AVFS_FUSE_OVERRIDE', + 7: 'SMU_TABLE_PMSTATUSLOG', + 8: 'SMU_TABLE_SMU_METRICS', + 9: 'SMU_TABLE_DRIVER_SMU_CONFIG', + 10: 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', + 11: 'SMU_TABLE_OVERDRIVE', + 12: 'SMU_TABLE_I2C_COMMANDS', + 13: 'SMU_TABLE_PACE', + 14: 'SMU_TABLE_ECCINFO', + 15: 'SMU_TABLE_COMBO_PPTABLE', + 16: 'SMU_TABLE_WIFIBAND', + 17: 'SMU_TABLE_COUNT', +} +SMU_TABLE_PPTABLE = 0 +SMU_TABLE_WATERMARKS = 1 +SMU_TABLE_CUSTOM_DPM = 2 +SMU_TABLE_DPMCLOCKS = 3 +SMU_TABLE_AVFS = 4 +SMU_TABLE_AVFS_PSM_DEBUG = 5 +SMU_TABLE_AVFS_FUSE_OVERRIDE = 6 +SMU_TABLE_PMSTATUSLOG = 7 +SMU_TABLE_SMU_METRICS = 8 +SMU_TABLE_DRIVER_SMU_CONFIG = 9 +SMU_TABLE_ACTIVITY_MONITOR_COEFF = 10 +SMU_TABLE_OVERDRIVE = 11 +SMU_TABLE_I2C_COMMANDS = 12 +SMU_TABLE_PACE = 13 +SMU_TABLE_ECCINFO = 14 +SMU_TABLE_COMBO_PPTABLE = 15 +SMU_TABLE_WIFIBAND = 16 +SMU_TABLE_COUNT = 17 +smu_table_id = ctypes.c_uint32 # enum +__all__ = \ + ['ALLOWED_FEATURE_CTRL_DEFAULT', 'ALLOWED_FEATURE_CTRL_SCPM', + 'AVFS_D_COUNT', 'AVFS_D_G', 'AVFS_D_M_B', 'AVFS_D_M_S', + 'AVFS_D_e', 'AVFS_D_e__enumvalues', 'AVFS_TEMP_COLD', + 'AVFS_TEMP_COUNT', 'AVFS_TEMP_HOT', 'AVFS_TEMP_e', + 'AVFS_TEMP_e__enumvalues', 'AVFS_VOLTAGE_COUNT', + 'AVFS_VOLTAGE_GFX', 'AVFS_VOLTAGE_SOC', 'AVFS_VOLTAGE_TYPE_e', + 'AVFS_VOLTAGE_TYPE_e__enumvalues', 'AvfsDcBtcParams_t', + 'AvfsDebugTableExternal_t', 'AvfsDebugTable_t', + 'AvfsFuseOverride_t', 'BACO_SEQUENCE', 'BAMACO_SEQUENCE', + 'BOARD_GPIO_DC_GENLK_CLK', 'BOARD_GPIO_DC_GENLK_VSYNC', + 'BOARD_GPIO_DC_GEN_A', 'BOARD_GPIO_DC_GEN_B', + 'BOARD_GPIO_DC_GEN_C', 'BOARD_GPIO_DC_GEN_D', + 'BOARD_GPIO_DC_GEN_E', 'BOARD_GPIO_DC_GEN_F', + 'BOARD_GPIO_DC_GEN_G', 'BOARD_GPIO_DC_SWAPLOCK_A', + 'BOARD_GPIO_DC_SWAPLOCK_B', 'BOARD_GPIO_SMUIO_0', + 'BOARD_GPIO_SMUIO_1', 'BOARD_GPIO_SMUIO_10', + 'BOARD_GPIO_SMUIO_11', 'BOARD_GPIO_SMUIO_12', + 'BOARD_GPIO_SMUIO_13', 'BOARD_GPIO_SMUIO_14', + 'BOARD_GPIO_SMUIO_15', 'BOARD_GPIO_SMUIO_16', + 'BOARD_GPIO_SMUIO_17', 'BOARD_GPIO_SMUIO_18', + 'BOARD_GPIO_SMUIO_19', 'BOARD_GPIO_SMUIO_2', + 'BOARD_GPIO_SMUIO_20', 'BOARD_GPIO_SMUIO_21', + 'BOARD_GPIO_SMUIO_22', 'BOARD_GPIO_SMUIO_23', + 'BOARD_GPIO_SMUIO_24', 'BOARD_GPIO_SMUIO_25', + 'BOARD_GPIO_SMUIO_26', 'BOARD_GPIO_SMUIO_27', + 'BOARD_GPIO_SMUIO_28', 'BOARD_GPIO_SMUIO_29', + 'BOARD_GPIO_SMUIO_3', 'BOARD_GPIO_SMUIO_30', + 'BOARD_GPIO_SMUIO_31', 'BOARD_GPIO_SMUIO_4', 'BOARD_GPIO_SMUIO_5', + 'BOARD_GPIO_SMUIO_6', 'BOARD_GPIO_SMUIO_7', 'BOARD_GPIO_SMUIO_8', + 'BOARD_GPIO_SMUIO_9', 'BOARD_GPIO_TYPE_e', + 'BOARD_GPIO_TYPE_e__enumvalues', 'BoardTable_t', 'BootValues_t', + 'CMDCONFIG_READWRITE_BIT', 'CMDCONFIG_READWRITE_MASK', + 'CMDCONFIG_RESTART_BIT', 'CMDCONFIG_RESTART_MASK', + 'CMDCONFIG_STOP_BIT', 'CMDCONFIG_STOP_MASK', + 'CUSTOMER_VARIANT_COUNT', 'CUSTOMER_VARIANT_FALCON', + 'CUSTOMER_VARIANT_ROW', 'CUSTOMER_VARIANT_e', + 'CUSTOMER_VARIANT_e__enumvalues', 'D3HOTSequence_e', + 'D3HOTSequence_e__enumvalues', 'D3HOT_SEQUENCE_COUNT', + 'DCS_ARCH_ASYNC', 'DCS_ARCH_DISABLED', 'DCS_ARCH_FADCS', + 'DCS_ARCH_e', 'DCS_ARCH_e__enumvalues', + 'DEBUGSMC_MSG_DebugDumpExit', 'DEBUGSMC_MSG_GetDebugData', + 'DEBUGSMC_MSG_TestMessage', 'DEBUGSMC_Message_Count', + 'DEBUGSMC_VERSION', 'DEBUG_OVERRIDE_DFLL_MASTER_MODE', + 'DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK', + 'DEBUG_OVERRIDE_DISABLE_DFLL', + 'DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER', + 'DEBUG_OVERRIDE_DISABLE_FMAX_VMAX', + 'DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS', + 'DEBUG_OVERRIDE_DISABLE_VCN_PG', + 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK', + 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK', + 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK', + 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK', + 'DEBUG_OVERRIDE_ENABLE_PROFILING_MODE', + 'DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE', + 'DRAM_BIT_WIDTH_COUNT', 'DRAM_BIT_WIDTH_DISABLED', + 'DRAM_BIT_WIDTH_TYPE_e', 'DRAM_BIT_WIDTH_TYPE_e__enumvalues', + 'DRAM_BIT_WIDTH_X_128', 'DRAM_BIT_WIDTH_X_16', + 'DRAM_BIT_WIDTH_X_32', 'DRAM_BIT_WIDTH_X_64', + 'DRAM_BIT_WIDTH_X_8', 'DpmActivityMonitorCoeffIntExternal_t', + 'DpmActivityMonitorCoeffInt_t', 'DpmDescriptor_t', + 'DriverInfoTable_t', 'DriverReportedClocks_t', + 'DriverSmuConfigExternal_t', 'DriverSmuConfig_t', 'DroopInt_t', + 'EccInfoTable_t', 'EccInfo_t', 'FAN_MODE_AUTO', + 'FAN_MODE_MANUAL_LINEAR', 'FEATURE_ACDC_BIT', + 'FEATURE_ATHUB_MMHUB_PG_BIT', 'FEATURE_BACO_BIT', + 'FEATURE_BACO_CG_BIT', 'FEATURE_BACO_MPCLK_DS_BIT', + 'FEATURE_BOMXCO_SVI3_PROG_BIT', 'FEATURE_BOOT_POWER_OPT_BIT', + 'FEATURE_BOOT_TIME_CAL_BIT', + 'FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT', 'FEATURE_DF_CSTATE_BIT', + 'FEATURE_DPM_DCN_BIT', 'FEATURE_DPM_FCLK_BIT', + 'FEATURE_DPM_GFXCLK_BIT', 'FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT', + 'FEATURE_DPM_LINK_BIT', 'FEATURE_DPM_MP0CLK_BIT', + 'FEATURE_DPM_SOCCLK_BIT', 'FEATURE_DPM_UCLK_BIT', + 'FEATURE_DS_DCFCLK_BIT', 'FEATURE_DS_FCLK_BIT', + 'FEATURE_DS_GFXCLK_BIT', 'FEATURE_DS_LCLK_BIT', + 'FEATURE_DS_SOCCLK_BIT', 'FEATURE_DS_UCLK_BIT', + 'FEATURE_DS_VCN_BIT', 'FEATURE_EDC_PWRBRK_BIT', + 'FEATURE_FAN_CONTROL_BIT', 'FEATURE_FW_CTF_BIT', + 'FEATURE_FW_DATA_READ_BIT', 'FEATURE_FW_DSTATE_BIT', + 'FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT', 'FEATURE_GFXOFF_BIT', + 'FEATURE_GFX_DCS_BIT', 'FEATURE_GFX_EDC_BIT', + 'FEATURE_GFX_IMU_BIT', 'FEATURE_GFX_PCC_DFLL_BIT', + 'FEATURE_GFX_READ_MARGIN_BIT', 'FEATURE_GFX_ULV_BIT', + 'FEATURE_GTHR_BIT', 'FEATURE_LED_DISPLAY_BIT', + 'FEATURE_MEM_TEMP_READ_BIT', 'FEATURE_MM_DPM_BIT', + 'FEATURE_OPTIMIZED_VMIN_BIT', 'FEATURE_OUT_OF_BAND_MONITOR_BIT', + 'FEATURE_PWR_ALL', 'FEATURE_PWR_BACO', 'FEATURE_PWR_DOMAIN_COUNT', + 'FEATURE_PWR_DOMAIN_e', 'FEATURE_PWR_DOMAIN_e__enumvalues', + 'FEATURE_PWR_GFX', 'FEATURE_PWR_S5', 'FEATURE_PWR_SOC', + 'FEATURE_SMARTSHIFT_BIT', 'FEATURE_SOC_CG_BIT', + 'FEATURE_SOC_MPCLK_DS_BIT', 'FEATURE_SOC_PCC_BIT', + 'FEATURE_SPARE_52_BIT', 'FEATURE_SPARE_53_BIT', + 'FEATURE_SPARE_54_BIT', 'FEATURE_SPARE_55_BIT', + 'FEATURE_SPARE_56_BIT', 'FEATURE_SPARE_57_BIT', + 'FEATURE_SPARE_58_BIT', 'FEATURE_SPARE_59_BIT', + 'FEATURE_SPARE_60_BIT', 'FEATURE_SPARE_61_BIT', + 'FEATURE_SPARE_62_BIT', 'FEATURE_SPARE_63_BIT', + 'FEATURE_THROTTLERS_BIT', 'FEATURE_VDDIO_MEM_SCALING_BIT', + 'FEATURE_VMEMP_SCALING_BIT', 'FEATURE_VR0HOT_BIT', + 'FOPT_CALC_AC_CALC_DC', 'FOPT_CALC_AC_PPTABLE_DC', 'FOPT_CALC_e', + 'FOPT_CALC_e__enumvalues', 'FOPT_PPTABLE_AC_CALC_DC', + 'FOPT_PPTABLE_AC_PPTABLE_DC', 'FW_DSTATE_CLDO_PRG_BIT', + 'FW_DSTATE_CSRCLK_DS_BIT', 'FW_DSTATE_D0i3_2_QUIET_FW_BIT', + 'FW_DSTATE_DF_PLL_PWRDN_BIT', 'FW_DSTATE_G6_HSR_BIT', + 'FW_DSTATE_G6_PHY_VMEMP_OFF_BIT', 'FW_DSTATE_GFX_PSI6_BIT', + 'FW_DSTATE_GFX_VR_PWR_STAGE_BIT', 'FW_DSTATE_HSR_NON_STROBE_BIT', + 'FW_DSTATE_MALL_ALLOC_BIT', 'FW_DSTATE_MALL_FLUSH_BIT', + 'FW_DSTATE_MEM_PLL_PWRDN_BIT', 'FW_DSTATE_MEM_PSI_BIT', + 'FW_DSTATE_MMHUB_INTERLOCK_BIT', 'FW_DSTATE_MP0_ENTER_WFI_BIT', + 'FW_DSTATE_MP1_WHISPER_MODE_BIT', 'FW_DSTATE_SMN_DS_BIT', + 'FW_DSTATE_SOC_LIV_MIN_BIT', 'FW_DSTATE_SOC_PLL_PWRDN_BIT', + 'FW_DSTATE_SOC_PSI_BIT', 'FW_DSTATE_SOC_ULV_BIT', + 'FW_DSTATE_UCP_DS_BIT', 'FW_DSTATE_U_LOW_PWR_MODE_EN_BIT', + 'FW_DSTATE_U_PSI_BIT', 'FW_DSTATE_U_ULV_BIT', 'FanMode_e', + 'FanMode_e__enumvalues', 'GPIO_INT_POLARITY_ACTIVE_HIGH', + 'GPIO_INT_POLARITY_ACTIVE_LOW', 'GpioIntPolarity_e', + 'GpioIntPolarity_e__enumvalues', 'I2C_CMD_COUNT', 'I2C_CMD_READ', + 'I2C_CMD_WRITE', 'I2C_CONTROLLER_DISABLED', + 'I2C_CONTROLLER_ENABLED', 'I2C_CONTROLLER_NAME_COUNT', + 'I2C_CONTROLLER_NAME_FAN_INTAKE', 'I2C_CONTROLLER_NAME_LIQUID0', + 'I2C_CONTROLLER_NAME_LIQUID1', 'I2C_CONTROLLER_NAME_PLX', + 'I2C_CONTROLLER_NAME_VR_GFX', 'I2C_CONTROLLER_NAME_VR_SOC', + 'I2C_CONTROLLER_NAME_VR_VDDIO', 'I2C_CONTROLLER_NAME_VR_VMEMP', + 'I2C_CONTROLLER_PORT_0', 'I2C_CONTROLLER_PORT_1', + 'I2C_CONTROLLER_PORT_COUNT', 'I2C_CONTROLLER_PROTOCOL_COUNT', + 'I2C_CONTROLLER_PROTOCOL_INA3221', + 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', + 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', + 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', + 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', + 'I2C_CONTROLLER_THROTTLER_COUNT', + 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', + 'I2C_CONTROLLER_THROTTLER_INA3221', + 'I2C_CONTROLLER_THROTTLER_LIQUID0', + 'I2C_CONTROLLER_THROTTLER_LIQUID1', + 'I2C_CONTROLLER_THROTTLER_PLX', + 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', + 'I2C_CONTROLLER_THROTTLER_VR_GFX', + 'I2C_CONTROLLER_THROTTLER_VR_SOC', + 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', + 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', 'I2C_PORT_GPIO', + 'I2C_PORT_SVD_SCL', 'I2C_SPEED_COUNT', 'I2C_SPEED_FAST_100K', + 'I2C_SPEED_FAST_400K', 'I2C_SPEED_FAST_50K', + 'I2C_SPEED_FAST_PLUS_1M', 'I2C_SPEED_HIGH_1M', + 'I2C_SPEED_HIGH_2M', 'I2cCmdType_e', 'I2cCmdType_e__enumvalues', + 'I2cControllerConfig_t', 'I2cControllerName_e', + 'I2cControllerName_e__enumvalues', 'I2cControllerPort_e', + 'I2cControllerPort_e__enumvalues', 'I2cControllerProtocol_e', + 'I2cControllerProtocol_e__enumvalues', 'I2cControllerThrottler_e', + 'I2cControllerThrottler_e__enumvalues', 'I2cPort_e', + 'I2cPort_e__enumvalues', 'I2cSpeed_e', 'I2cSpeed_e__enumvalues', + 'IH_INTERRUPT_CONTEXT_ID_AC', 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D0', + 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D3', + 'IH_INTERRUPT_CONTEXT_ID_BACO', 'IH_INTERRUPT_CONTEXT_ID_DC', + 'IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL', + 'IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY', + 'IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING', + 'IH_INTERRUPT_ID_TO_DRIVER', 'INVALID_BOARD_GPIO', + 'LED_DISPLAY_ERROR_BIT', 'LED_DISPLAY_GFX_DPM_BIT', + 'LED_DISPLAY_PCIE_BIT', 'LinearInt_t', 'MARKETING_BASE_CLOCKS', + 'MARKETING_BOOST_CLOCKS', 'MARKETING_GAME_CLOCKS', + 'MAX_BOARD_GPIO_SMUIO_NUM', 'MAX_SW_I2C_COMMANDS', + 'MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT', + 'MEM_TEMP_READ_IN_BAND_REFRESH_BIT', + 'MEM_TEMP_READ_OUT_OF_BAND_BIT', 'MEM_VENDOR_COUNT', + 'MEM_VENDOR_ELPIDA', 'MEM_VENDOR_ESMT', 'MEM_VENDOR_ETRON', + 'MEM_VENDOR_HYNIX', 'MEM_VENDOR_INFINEON', 'MEM_VENDOR_MICRON', + 'MEM_VENDOR_MOSEL', 'MEM_VENDOR_NANYA', 'MEM_VENDOR_PLACEHOLDER0', + 'MEM_VENDOR_PLACEHOLDER1', 'MEM_VENDOR_PLACEHOLDER2', + 'MEM_VENDOR_PLACEHOLDER3', 'MEM_VENDOR_PLACEHOLDER4', + 'MEM_VENDOR_PLACEHOLDER5', 'MEM_VENDOR_SAMSUNG', + 'MEM_VENDOR_WINBOND', 'MEM_VENDOR_e', 'MEM_VENDOR_e__enumvalues', + 'MSR_SEQUENCE', 'MsgLimits_t', 'NUM_DCFCLK_DPM_LEVELS', + 'NUM_DCLK_DPM_LEVELS', 'NUM_DISPCLK_DPM_LEVELS', + 'NUM_DPPCLK_DPM_LEVELS', 'NUM_DPREFCLK_DPM_LEVELS', + 'NUM_DTBCLK_DPM_LEVELS', 'NUM_FCLK_DPM_LEVELS', 'NUM_FEATURES', + 'NUM_GFXCLK_DPM_LEVELS', 'NUM_I2C_CONTROLLERS', 'NUM_LINK_LEVELS', + 'NUM_MP0CLK_DPM_LEVELS', 'NUM_OD_FAN_MAX_POINTS', + 'NUM_SOCCLK_DPM_LEVELS', 'NUM_UCLK_DPM_LEVELS', + 'NUM_VCLK_DPM_LEVELS', 'NUM_WM_RANGES', 'OverDriveLimits_t', + 'OverDriveTableExternal_t', 'OverDriveTable_t', + 'PERF_LEVEL_ACTIVITY', 'PERF_LEVEL_POWER_CONTAINMENT', + 'PG_DYNAMIC_MODE', 'PG_POWER_DOWN', 'PG_POWER_UP', + 'PG_STATIC_MODE', 'PMFW_VOLT_PLANE_COUNT', 'PMFW_VOLT_PLANE_GFX', + 'PMFW_VOLT_PLANE_SOC', 'PMFW_VOLT_PLANE_e', + 'PMFW_VOLT_PLANE_e__enumvalues', 'POWER_SOURCE_AC', + 'POWER_SOURCE_COUNT', 'POWER_SOURCE_DC', 'POWER_SOURCE_e', + 'POWER_SOURCE_e__enumvalues', 'PPCLK_COUNT', 'PPCLK_DCFCLK', + 'PPCLK_DCLK_0', 'PPCLK_DCLK_1', 'PPCLK_DISPCLK', 'PPCLK_DPPCLK', + 'PPCLK_DPREFCLK', 'PPCLK_DTBCLK', 'PPCLK_FCLK', 'PPCLK_GFXCLK', + 'PPCLK_SOCCLK', 'PPCLK_UCLK', 'PPCLK_VCLK_0', 'PPCLK_VCLK_1', + 'PPCLK_e', 'PPCLK_e__enumvalues', 'PPSMC_MSG_AllowGfxDcs', + 'PPSMC_MSG_AllowGfxOff', 'PPSMC_MSG_AllowIHHostInterrupt', + 'PPSMC_MSG_ArmD3', 'PPSMC_MSG_BacoAudioD3PME', + 'PPSMC_MSG_DALNotPresent', 'PPSMC_MSG_DisableAllSmuFeatures', + 'PPSMC_MSG_DisableSmuFeaturesHigh', + 'PPSMC_MSG_DisableSmuFeaturesLow', 'PPSMC_MSG_DisallowGfxDcs', + 'PPSMC_MSG_DisallowGfxOff', 'PPSMC_MSG_DramLogSetDramAddrHigh', + 'PPSMC_MSG_DramLogSetDramAddrLow', 'PPSMC_MSG_DramLogSetDramSize', + 'PPSMC_MSG_DumpSTBtoDram', 'PPSMC_MSG_EnableAllSmuFeatures', + 'PPSMC_MSG_EnableAudioStutterWA', + 'PPSMC_MSG_EnableSmuFeaturesHigh', + 'PPSMC_MSG_EnableSmuFeaturesLow', 'PPSMC_MSG_EnableUCLKShadow', + 'PPSMC_MSG_EnterBaco', 'PPSMC_MSG_ExitBaco', + 'PPSMC_MSG_GetDcModeMaxDpmFreq', 'PPSMC_MSG_GetDebugData', + 'PPSMC_MSG_GetDpmFreqByIndex', 'PPSMC_MSG_GetDriverIfVersion', + 'PPSMC_MSG_GetMaxDpmFreq', 'PPSMC_MSG_GetMinDpmFreq', + 'PPSMC_MSG_GetPptLimit', 'PPSMC_MSG_GetRunningSmuFeaturesHigh', + 'PPSMC_MSG_GetRunningSmuFeaturesLow', 'PPSMC_MSG_GetSmuVersion', + 'PPSMC_MSG_GetVoltageByDpm', 'PPSMC_MSG_Mode1Reset', + 'PPSMC_MSG_Mode2Reset', 'PPSMC_MSG_NotifyPowerSource', + 'PPSMC_MSG_OverridePcieParameters', 'PPSMC_MSG_PowerDownJpeg', + 'PPSMC_MSG_PowerDownUmsch', 'PPSMC_MSG_PowerDownVcn', + 'PPSMC_MSG_PowerUpJpeg', 'PPSMC_MSG_PowerUpUmsch', + 'PPSMC_MSG_PowerUpVcn', 'PPSMC_MSG_PrepareMp1ForUnload', + 'PPSMC_MSG_ReenableAcDcInterrupt', 'PPSMC_MSG_RunDcBtc', + 'PPSMC_MSG_STBtoDramLogSetDramAddrHigh', + 'PPSMC_MSG_STBtoDramLogSetDramAddrLow', + 'PPSMC_MSG_STBtoDramLogSetDramSize', + 'PPSMC_MSG_SetAllowedFeaturesMaskHigh', + 'PPSMC_MSG_SetAllowedFeaturesMaskLow', + 'PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel', + 'PPSMC_MSG_SetDcsArch', 'PPSMC_MSG_SetDriverDramAddrHigh', + 'PPSMC_MSG_SetDriverDramAddrLow', + 'PPSMC_MSG_SetExternalClientDfCstateAllow', + 'PPSMC_MSG_SetFwDstatesMask', 'PPSMC_MSG_SetGpoAllow', + 'PPSMC_MSG_SetHardMaxByFreq', 'PPSMC_MSG_SetHardMinByFreq', + 'PPSMC_MSG_SetMGpuFanBoostLimitRpm', + 'PPSMC_MSG_SetNumBadMemoryPagesRetired', 'PPSMC_MSG_SetPptLimit', + 'PPSMC_MSG_SetPriorityDeltaGain', 'PPSMC_MSG_SetSoftMaxByFreq', + 'PPSMC_MSG_SetSoftMinByFreq', + 'PPSMC_MSG_SetSystemVirtualDramAddrHigh', + 'PPSMC_MSG_SetSystemVirtualDramAddrLow', + 'PPSMC_MSG_SetTemperatureInputSelect', + 'PPSMC_MSG_SetThrottlerMask', 'PPSMC_MSG_SetToolsDramAddrHigh', + 'PPSMC_MSG_SetToolsDramAddrLow', 'PPSMC_MSG_SetVideoFps', + 'PPSMC_MSG_SetWorkloadMask', 'PPSMC_MSG_TestMessage', + 'PPSMC_MSG_TransferTableDram2Smu', + 'PPSMC_MSG_TransferTableSmu2Dram', 'PPSMC_MSG_TriggerVFFLR', + 'PPSMC_MSG_UseDefaultPPTable', 'PPSMC_Message_Count', + 'PPSMC_Result_CmdRejectedBusy', 'PPSMC_Result_CmdRejectedPrereq', + 'PPSMC_Result_Failed', 'PPSMC_Result_OK', + 'PPSMC_Result_UnknownCmd', 'PPSMC_VERSION', 'PPTABLE_VERSION', + 'PPT_THROTTLER_COUNT', 'PPT_THROTTLER_PPT0', 'PPT_THROTTLER_PPT1', + 'PPT_THROTTLER_PPT2', 'PPT_THROTTLER_PPT3', 'PPT_THROTTLER_e', + 'PPT_THROTTLER_e__enumvalues', 'PPTable_t', + 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', 'PP_GRTAVFS_FW_COMMON_FUSE_e', + 'PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', + 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', + 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', + 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', + 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', + 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', + 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', + 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', + 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', + 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', + 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', + 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', + 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', + 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', + 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', + 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', + 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', + 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', + 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', + 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', + 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', + 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', + 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', + 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', + 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', + 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', + 'PP_GRTAVFS_FW_SEP_FUSE_e', + 'PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues', + 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', + 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', + 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', + 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', + 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', + 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', + 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', + 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', + 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', + 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', + 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', + 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', + 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', + 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', + 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', + 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', + 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', 'PP_GRTAVFS_HW_FUSE_COUNT', + 'PP_GRTAVFS_HW_FUSE_e', 'PP_GRTAVFS_HW_FUSE_e__enumvalues', + 'PP_GRTAVFS_HW_RESERVED_0', 'PP_GRTAVFS_HW_RESERVED_1', + 'PP_GRTAVFS_HW_RESERVED_2', 'PP_GRTAVFS_HW_RESERVED_3', + 'PP_GRTAVFS_HW_RESERVED_4', 'PP_GRTAVFS_HW_RESERVED_5', + 'PP_GRTAVFS_HW_RESERVED_6', 'PP_GRTAVFS_HW_VOLTAGE_GB', + 'PP_GRTAVFS_HW_ZONE0_VF', 'PP_GRTAVFS_HW_ZONE1_VF1', + 'PP_GRTAVFS_HW_ZONE2_VF2', 'PP_GRTAVFS_HW_ZONE3_VF3', + 'PP_NUM_OD_VF_CURVE_POINTS', 'PP_NUM_RTAVFS_PWL_ZONES', + 'PP_OD_FEATURE_COUNT', 'PP_OD_FEATURE_FAN_CURVE_BIT', + 'PP_OD_FEATURE_GFXCLK_BIT', 'PP_OD_FEATURE_GFX_VF_CURVE_BIT', + 'PP_OD_FEATURE_PPT_BIT', 'PP_OD_FEATURE_TEMPERATURE_BIT', + 'PP_OD_FEATURE_UCLK_BIT', 'PP_OD_FEATURE_ZERO_FAN_BIT', + 'PSI_SEL_VR0_PLANE0_PSI0', 'PSI_SEL_VR0_PLANE0_PSI1', + 'PSI_SEL_VR0_PLANE1_PSI0', 'PSI_SEL_VR0_PLANE1_PSI1', + 'PSI_SEL_VR1_PLANE0_PSI0', 'PSI_SEL_VR1_PLANE0_PSI1', + 'PSI_SEL_VR1_PLANE1_PSI0', 'PSI_SEL_VR1_PLANE1_PSI1', + 'PWR_CONFIG_TCP_ESTIMATED', 'PWR_CONFIG_TCP_MEASURED', + 'PWR_CONFIG_TDP', 'PWR_CONFIG_TGP', 'PowerGatingMode_e', + 'PowerGatingMode_e__enumvalues', 'PowerGatingSettings_e', + 'PowerGatingSettings_e__enumvalues', 'PwrConfig_e', + 'PwrConfig_e__enumvalues', 'QuadraticInt_t', + 'SMARTSHIFT_VERSION_1', 'SMARTSHIFT_VERSION_2', + 'SMARTSHIFT_VERSION_3', 'SMARTSHIFT_VERSION_e', + 'SMARTSHIFT_VERSION_e__enumvalues', 'SMU13_0_0_DRIVER_IF_VERSION', + 'SMU13_DRIVER_IF_V13_0_0_H', 'SMU_CLK_COUNT', + 'SMU_CUSTOM_FAN_SPEED_PWM', 'SMU_CUSTOM_FAN_SPEED_RPM', + 'SMU_DCEFCLK', 'SMU_DCLK', 'SMU_DCLK1', 'SMU_DEFAULT_PPT_LIMIT', + 'SMU_DISPCLK', 'SMU_DPM_USER_PROFILE_RESTORE', 'SMU_ECLK', + 'SMU_FAST_PPT_LIMIT', 'SMU_FCLK', 'SMU_FW_NAME_LEN', 'SMU_GFXCLK', + 'SMU_LCLK', 'SMU_MCLK', 'SMU_MEMORY_POOL_SIZE_1_GB', + 'SMU_MEMORY_POOL_SIZE_256_MB', 'SMU_MEMORY_POOL_SIZE_2_GB', + 'SMU_MEMORY_POOL_SIZE_512_MB', 'SMU_MEMORY_POOL_SIZE_ZERO', + 'SMU_OD_ACOUSTIC_LIMIT', 'SMU_OD_ACOUSTIC_TARGET', 'SMU_OD_CCLK', + 'SMU_OD_FAN_CURVE', 'SMU_OD_FAN_MINIMUM_PWM', + 'SMU_OD_FAN_TARGET_TEMPERATURE', 'SMU_OD_MCLK', 'SMU_OD_RANGE', + 'SMU_OD_SCLK', 'SMU_OD_VDDC_CURVE', 'SMU_OD_VDDGFX_OFFSET', + 'SMU_PCIE', 'SMU_PHYCLK', 'SMU_PIXCLK', 'SMU_POWER_SOURCE_AC', + 'SMU_POWER_SOURCE_COUNT', 'SMU_POWER_SOURCE_DC', + 'SMU_PPT_LIMIT_CURRENT', 'SMU_PPT_LIMIT_DEFAULT', + 'SMU_PPT_LIMIT_MAX', 'SMU_PPT_LIMIT_MIN', + 'SMU_REFRESHRATE_SOURCE_EDID', 'SMU_REFRESHRATE_SOURCE_EXPLICIT', + 'SMU_SCLK', 'SMU_SOCCLK', + 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', + 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', + 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', + 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', + 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', + 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', + 'SMU_STATE_CLASSIFICATION_FLAG_BACO', + 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', + 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', + 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', + 'SMU_STATE_CLASSIFICATION_FLAG_HD2', + 'SMU_STATE_CLASSIFICATION_FLAG_RESET', + 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', + 'SMU_STATE_CLASSIFICATION_FLAG_ULV', + 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', + 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', + 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', + 'SMU_STATE_CLASSIFICATION_FLAG_UVD', + 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', + 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', + 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', 'SMU_STATE_UI_LABEL_BACO', + 'SMU_STATE_UI_LABEL_BALLANCED', 'SMU_STATE_UI_LABEL_BATTERY', + 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', 'SMU_STATE_UI_LABEL_NONE', + 'SMU_STATE_UI_LABEL_PERFORMANCE', 'SMU_STATE_UI_TABEL_MIDDLE_LOW', + 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', 'SMU_TABLE_AVFS', + 'SMU_TABLE_AVFS_FUSE_OVERRIDE', 'SMU_TABLE_AVFS_PSM_DEBUG', + 'SMU_TABLE_COMBO_PPTABLE', 'SMU_TABLE_COUNT', + 'SMU_TABLE_CUSTOM_DPM', 'SMU_TABLE_DPMCLOCKS', + 'SMU_TABLE_DRIVER_SMU_CONFIG', 'SMU_TABLE_ECCINFO', + 'SMU_TABLE_I2C_COMMANDS', 'SMU_TABLE_OVERDRIVE', 'SMU_TABLE_PACE', + 'SMU_TABLE_PMSTATUSLOG', 'SMU_TABLE_PPTABLE', + 'SMU_TABLE_SMU_METRICS', 'SMU_TABLE_WATERMARKS', + 'SMU_TABLE_WIFIBAND', 'SMU_TEMPERATURE_UNITS_PER_CENTIGRADES', + 'SMU_THERMAL_MAXIMUM_ALERT_TEMP', + 'SMU_THERMAL_MINIMUM_ALERT_TEMP', 'SMU_THROTTLER_APCC_BIT', + 'SMU_THROTTLER_EDC_CPU_BIT', 'SMU_THROTTLER_EDC_GFX_BIT', + 'SMU_THROTTLER_FIT_BIT', 'SMU_THROTTLER_FPPT_BIT', + 'SMU_THROTTLER_PPM_BIT', 'SMU_THROTTLER_PPT0_BIT', + 'SMU_THROTTLER_PPT1_BIT', 'SMU_THROTTLER_PPT2_BIT', + 'SMU_THROTTLER_PPT3_BIT', 'SMU_THROTTLER_PROCHOT_CPU_BIT', + 'SMU_THROTTLER_PROCHOT_GFX_BIT', 'SMU_THROTTLER_SPL_BIT', + 'SMU_THROTTLER_SPPT_APU_BIT', 'SMU_THROTTLER_SPPT_BIT', + 'SMU_THROTTLER_TDC_CVIP_BIT', 'SMU_THROTTLER_TDC_GFX_BIT', + 'SMU_THROTTLER_TDC_MEM_BIT', 'SMU_THROTTLER_TDC_SOC_BIT', + 'SMU_THROTTLER_TDC_VDD_BIT', 'SMU_THROTTLER_TEMP_CORE_BIT', + 'SMU_THROTTLER_TEMP_EDGE_BIT', 'SMU_THROTTLER_TEMP_GPU_BIT', + 'SMU_THROTTLER_TEMP_HOTSPOT_BIT', + 'SMU_THROTTLER_TEMP_LIQUID0_BIT', + 'SMU_THROTTLER_TEMP_LIQUID1_BIT', 'SMU_THROTTLER_TEMP_MEM_BIT', + 'SMU_THROTTLER_TEMP_SOC_BIT', 'SMU_THROTTLER_TEMP_VR_GFX_BIT', + 'SMU_THROTTLER_TEMP_VR_MEM0_BIT', + 'SMU_THROTTLER_TEMP_VR_MEM1_BIT', 'SMU_THROTTLER_TEMP_VR_SOC_BIT', + 'SMU_THROTTLER_VRHOT0_BIT', 'SMU_THROTTLER_VRHOT1_BIT', + 'SMU_UCLK', 'SMU_V13_0_0_PPSMC_H', 'SMU_VCLK', 'SMU_VCLK1', + 'SVI_PLANE_COUNT', 'SVI_PLANE_GFX', 'SVI_PLANE_SOC', + 'SVI_PLANE_U', 'SVI_PLANE_VDDIO_MEM', 'SVI_PLANE_VMEMP', + 'SVI_PLANE_e', 'SVI_PLANE_e__enumvalues', 'SVI_PSI_0', + 'SVI_PSI_1', 'SVI_PSI_2', 'SVI_PSI_3', 'SVI_PSI_4', 'SVI_PSI_5', + 'SVI_PSI_6', 'SVI_PSI_7', 'SVI_PSI_e', 'SVI_PSI_e__enumvalues', + 'SkuTable_t', 'SmuMetricsExternal_t', 'SmuMetrics_t', + 'SviTelemetryScale_t', 'SwI2cCmd_t', 'SwI2cRequestExternal_t', + 'SwI2cRequest_t', 'TABLE_ACTIVITY_MONITOR_COEFF', + 'TABLE_AVFS_PSM_DEBUG', 'TABLE_COMBO_PPTABLE', 'TABLE_COUNT', + 'TABLE_DRIVER_INFO', 'TABLE_DRIVER_SMU_CONFIG', 'TABLE_ECCINFO', + 'TABLE_I2C_COMMANDS', 'TABLE_OVERDRIVE', 'TABLE_PMSTATUSLOG', + 'TABLE_PPTABLE', 'TABLE_SMU_METRICS', 'TABLE_TRANSFER_FAILED', + 'TABLE_TRANSFER_OK', 'TABLE_TRANSFER_PENDING', 'TABLE_WATERMARKS', + 'TABLE_WIFIBAND', 'TDC_THROTTLER_COUNT', 'TDC_THROTTLER_GFX', + 'TDC_THROTTLER_SOC', 'TDC_THROTTLER_U', 'TDC_THROTTLER_e', + 'TDC_THROTTLER_e__enumvalues', 'TEMP_COUNT', 'TEMP_EDGE', + 'TEMP_HOTSPOT', 'TEMP_HOTSPOT_G', 'TEMP_HOTSPOT_M', + 'TEMP_LIQUID0', 'TEMP_LIQUID1', 'TEMP_MEM', 'TEMP_PLX', + 'TEMP_VR_GFX', 'TEMP_VR_MEM0', 'TEMP_VR_MEM1', 'TEMP_VR_SOC', + 'TEMP_VR_U', 'TEMP_e', 'TEMP_e__enumvalues', 'THROTTLER_COUNT', + 'THROTTLER_FIT_BIT', 'THROTTLER_GFX_APCC_PLUS_BIT', + 'THROTTLER_PPT0_BIT', 'THROTTLER_PPT1_BIT', 'THROTTLER_PPT2_BIT', + 'THROTTLER_PPT3_BIT', 'THROTTLER_TDC_GFX_BIT', + 'THROTTLER_TDC_SOC_BIT', 'THROTTLER_TDC_U_BIT', + 'THROTTLER_TEMP_EDGE_BIT', 'THROTTLER_TEMP_HOTSPOT_BIT', + 'THROTTLER_TEMP_HOTSPOT_G_BIT', 'THROTTLER_TEMP_HOTSPOT_M_BIT', + 'THROTTLER_TEMP_LIQUID0_BIT', 'THROTTLER_TEMP_LIQUID1_BIT', + 'THROTTLER_TEMP_MEM_BIT', 'THROTTLER_TEMP_PLX_BIT', + 'THROTTLER_TEMP_VR_GFX_BIT', 'THROTTLER_TEMP_VR_MEM0_BIT', + 'THROTTLER_TEMP_VR_MEM1_BIT', 'THROTTLER_TEMP_VR_SOC_BIT', + 'THROTTLER_TEMP_VR_U_BIT', 'UCLK_DIV_BY_1', 'UCLK_DIV_BY_2', + 'UCLK_DIV_BY_4', 'UCLK_DIV_BY_8', 'UCLK_DIV_e', + 'UCLK_DIV_e__enumvalues', 'ULPS_SEQUENCE', 'VOLTAGE_MODE_COUNT', + 'VOLTAGE_MODE_FUSES', 'VOLTAGE_MODE_PPTABLE', 'VOLTAGE_MODE_e', + 'VOLTAGE_MODE_e__enumvalues', 'VR_MAPPING_PLANE_SELECT_MASK', + 'VR_MAPPING_PLANE_SELECT_SHIFT', 'VR_MAPPING_VR_SELECT_MASK', + 'VR_MAPPING_VR_SELECT_SHIFT', 'WATERMARKS_CLOCK_RANGE', + 'WATERMARKS_COUNT', 'WATERMARKS_DUMMY_PSTATE', + 'WATERMARKS_FLAGS_e', 'WATERMARKS_FLAGS_e__enumvalues', + 'WATERMARKS_MALL', 'WORKLOAD_PPLIB_COMPUTE_BIT', + 'WORKLOAD_PPLIB_COUNT', 'WORKLOAD_PPLIB_CUSTOM_BIT', + 'WORKLOAD_PPLIB_DEFAULT_BIT', 'WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT', + 'WORKLOAD_PPLIB_POWER_SAVING_BIT', 'WORKLOAD_PPLIB_VIDEO_BIT', + 'WORKLOAD_PPLIB_VR_BIT', 'WORKLOAD_PPLIB_WINDOW_3D_BIT', + 'WatermarkRowGeneric_t', 'WatermarksExternal_t', 'Watermarks_t', + '__AMDGPU_SMU_H__', 'bool', 'c__EA_AVFS_D_e', 'c__EA_AVFS_TEMP_e', + 'c__EA_AVFS_VOLTAGE_TYPE_e', 'c__EA_BOARD_GPIO_TYPE_e', + 'c__EA_CUSTOMER_VARIANT_e', 'c__EA_D3HOTSequence_e', + 'c__EA_DCS_ARCH_e', 'c__EA_DRAM_BIT_WIDTH_TYPE_e', + 'c__EA_FEATURE_PWR_DOMAIN_e', 'c__EA_FOPT_CALC_e', + 'c__EA_FanMode_e', 'c__EA_GpioIntPolarity_e', + 'c__EA_I2cCmdType_e', 'c__EA_I2cControllerName_e', + 'c__EA_I2cControllerPort_e', 'c__EA_I2cControllerProtocol_e', + 'c__EA_I2cControllerThrottler_e', 'c__EA_I2cPort_e', + 'c__EA_I2cSpeed_e', 'c__EA_MEM_VENDOR_e', + 'c__EA_PMFW_VOLT_PLANE_e', 'c__EA_POWER_SOURCE_e', + 'c__EA_PPCLK_e', 'c__EA_PPT_THROTTLER_e', + 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e', + 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e', 'c__EA_PP_GRTAVFS_HW_FUSE_e', + 'c__EA_PowerGatingMode_e', 'c__EA_PowerGatingSettings_e', + 'c__EA_PwrConfig_e', 'c__EA_SMARTSHIFT_VERSION_e', + 'c__EA_SVI_PLANE_e', 'c__EA_SVI_PSI_e', 'c__EA_TDC_THROTTLER_e', + 'c__EA_TEMP_e', 'c__EA_UCLK_DIV_e', 'c__EA_VOLTAGE_MODE_e', + 'c__EA_WATERMARKS_FLAGS_e', 'int16_t', 'int32_t', 'int8_t', + 'smu_clk_type', 'smu_memory_pool_size', + 'smu_perf_level_designation', 'smu_power_src_type', + 'smu_ppt_limit_level', 'smu_ppt_limit_type', + 'smu_refreshrate_source', 'smu_state_classification_flag', + 'smu_state_ui_label', 'smu_table_id', 'struct_amdgpu_bo', + 'struct_c__SA_AvfsDcBtcParams_t', + 'struct_c__SA_AvfsDebugTableExternal_t', + 'struct_c__SA_AvfsDebugTable_t', + 'struct_c__SA_AvfsFuseOverride_t', 'struct_c__SA_BoardTable_t', + 'struct_c__SA_BootValues_t', + 'struct_c__SA_DpmActivityMonitorCoeffIntExternal_t', + 'struct_c__SA_DpmActivityMonitorCoeffInt_t', + 'struct_c__SA_DpmDescriptor_t', 'struct_c__SA_DriverInfoTable_t', + 'struct_c__SA_DriverReportedClocks_t', + 'struct_c__SA_DriverSmuConfigExternal_t', + 'struct_c__SA_DriverSmuConfig_t', 'struct_c__SA_DroopInt_t', + 'struct_c__SA_EccInfoTable_t', 'struct_c__SA_EccInfo_t', + 'struct_c__SA_I2cControllerConfig_t', 'struct_c__SA_LinearInt_t', + 'struct_c__SA_MsgLimits_t', 'struct_c__SA_OverDriveLimits_t', + 'struct_c__SA_OverDriveTableExternal_t', + 'struct_c__SA_OverDriveTable_t', 'struct_c__SA_PPTable_t', + 'struct_c__SA_QuadraticInt_t', 'struct_c__SA_SkuTable_t', + 'struct_c__SA_SmuMetricsExternal_t', 'struct_c__SA_SmuMetrics_t', + 'struct_c__SA_SviTelemetryScale_t', 'struct_c__SA_SwI2cCmd_t', + 'struct_c__SA_SwI2cRequestExternal_t', + 'struct_c__SA_SwI2cRequest_t', + 'struct_c__SA_WatermarkRowGeneric_t', + 'struct_c__SA_WatermarksExternal_t', 'struct_c__SA_Watermarks_t', + 'struct_smu_bios_boot_up_values', 'struct_smu_clock_info', + 'struct_smu_hw_power_state', 'struct_smu_performance_level', + 'struct_smu_power_state', 'struct_smu_state_classification_block', + 'struct_smu_state_display_block', 'struct_smu_state_memory_block', + 'struct_smu_state_pcie_block', + 'struct_smu_state_software_algorithm_block', + 'struct_smu_state_validation_block', 'struct_smu_table', + 'struct_smu_temperature_range', 'struct_smu_user_dpm_profile', + 'struct_smu_uvd_clocks', 'u32', 'uint16_t', 'uint32_t', + 'uint64_t', 'uint8_t'] diff --git a/tinygrad/runtime/autogen/libpciaccess.py b/tinygrad/runtime/autogen/libpciaccess.py new file mode 100644 index 0000000000..7d3248f980 --- /dev/null +++ b/tinygrad/runtime/autogen/libpciaccess.py @@ -0,0 +1,2023 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes, os + + +class AsDictMixin: + @classmethod + def as_dict(cls, self): + result = {} + if not isinstance(self, AsDictMixin): + # not a structure, assume it's already a python object + return self + if not hasattr(cls, "_fields_"): + return result + # sys.version_info >= (3, 5) + # for (field, *_) in cls._fields_: # noqa + for field_tuple in cls._fields_: # noqa + field = field_tuple[0] + if field.startswith('PADDING_'): + continue + value = getattr(self, field) + type_ = type(value) + if hasattr(value, "_length_") and hasattr(value, "_type_"): + # array + if not hasattr(type_, "as_dict"): + value = [v for v in value] + else: + type_ = type_._type_ + value = [type_.as_dict(v) for v in value] + elif hasattr(value, "contents") and hasattr(value, "_type_"): + # pointer + try: + if not hasattr(type_, "as_dict"): + value = value.contents + else: + type_ = type_._type_ + value = type_.as_dict(value.contents) + except ValueError: + # nullptr + value = None + elif isinstance(value, AsDictMixin): + # other structure + value = type_.as_dict(value) + result[field] = value + return result + + +class Structure(ctypes.Structure, AsDictMixin): + + def __init__(self, *args, **kwds): + # We don't want to use positional arguments fill PADDING_* fields + + args = dict(zip(self.__class__._field_names_(), args)) + args.update(kwds) + super(Structure, self).__init__(**args) + + @classmethod + def _field_names_(cls): + if hasattr(cls, '_fields_'): + return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) + else: + return () + + @classmethod + def get_type(cls, field): + for f in cls._fields_: + if f[0] == field: + return f[1] + return None + + @classmethod + def bind(cls, bound_fields): + fields = {} + for name, type_ in cls._fields_: + if hasattr(type_, "restype"): + if name in bound_fields: + if bound_fields[name] is None: + fields[name] = type_() + else: + # use a closure to capture the callback from the loop scope + fields[name] = ( + type_((lambda callback: lambda *args: callback(*args))( + bound_fields[name])) + ) + del bound_fields[name] + else: + # default callback implementation (does nothing) + try: + default_ = type_(0).restype().value + except TypeError: + default_ = None + fields[name] = type_(( + lambda default_: lambda *args: default_)(default_)) + else: + # not a callback function, use default initialization + if name in bound_fields: + fields[name] = bound_fields[name] + del bound_fields[name] + else: + fields[name] = type_() + if len(bound_fields) != 0: + raise ValueError( + "Cannot bind the following unknown callback(s) {}.{}".format( + cls.__name__, bound_fields.keys() + )) + return cls(**fields) + + +class Union(ctypes.Union, AsDictMixin): + pass + + + +_libraries = {} +_libraries['libpciaccess.so'] = ctypes.CDLL('/usr/lib/x86_64-linux-gnu/libpciaccess.so') if os.path.exists('/usr/lib/x86_64-linux-gnu/libpciaccess.so') else None +c_int128 = ctypes.c_ubyte*16 +c_uint128 = c_int128 +void = None +if ctypes.sizeof(ctypes.c_longdouble) == 16: + c_long_double_t = ctypes.c_longdouble +else: + c_long_double_t = ctypes.c_ubyte*16 + +def string_cast(char_pointer, encoding='utf-8', errors='strict'): + value = ctypes.cast(char_pointer, ctypes.c_char_p).value + if value is not None and encoding is not None: + value = value.decode(encoding, errors=errors) + return value + + +def char_pointer_cast(string, encoding='utf-8'): + if encoding is not None: + try: + string = string.encode(encoding) + except AttributeError: + # In Python3, bytes has no encode attribute + pass + string = ctypes.c_char_p(string) + return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) + + + + + +PCIACCESS_H = True # macro +# __deprecated = ((deprecated)) # macro +PCI_DEV_MAP_FLAG_WRITABLE = (1<<0) # macro +PCI_DEV_MAP_FLAG_WRITE_COMBINE = (1<<1) # macro +PCI_DEV_MAP_FLAG_CACHABLE = (1<<2) # macro +PCI_MATCH_ANY = (~0) # macro +def PCI_ID_COMPARE(a, b): # macro + return (((a)==(~0)) or ((a)==(b))) +VGA_ARB_RSRC_NONE = 0x00 # macro +VGA_ARB_RSRC_LEGACY_IO = 0x01 # macro +VGA_ARB_RSRC_LEGACY_MEM = 0x02 # macro +VGA_ARB_RSRC_NORMAL_IO = 0x04 # macro +VGA_ARB_RSRC_NORMAL_MEM = 0x08 # macro +pciaddr_t = ctypes.c_uint64 +class struct_pci_device_iterator(Structure): + pass + +class struct_pci_device(Structure): + pass + +try: + pci_device_has_kernel_driver = _libraries['libpciaccess.so'].pci_device_has_kernel_driver + pci_device_has_kernel_driver.restype = ctypes.c_int32 + pci_device_has_kernel_driver.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_is_boot_vga = _libraries['libpciaccess.so'].pci_device_is_boot_vga + pci_device_is_boot_vga.restype = ctypes.c_int32 + pci_device_is_boot_vga.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_read_rom = _libraries['libpciaccess.so'].pci_device_read_rom + pci_device_read_rom.restype = ctypes.c_int32 + pci_device_read_rom.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(None)] +except AttributeError: + pass +try: + pci_device_map_region = _libraries['libpciaccess.so'].pci_device_map_region + pci_device_map_region.restype = ctypes.c_int32 + pci_device_map_region.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.c_uint32, ctypes.c_int32] +except AttributeError: + pass +try: + pci_device_unmap_region = _libraries['libpciaccess.so'].pci_device_unmap_region + pci_device_unmap_region.restype = ctypes.c_int32 + pci_device_unmap_region.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.c_uint32] +except AttributeError: + pass +try: + pci_device_map_range = _libraries['libpciaccess.so'].pci_device_map_range + pci_device_map_range.restype = ctypes.c_int32 + pci_device_map_range.argtypes = [ctypes.POINTER(struct_pci_device), pciaddr_t, pciaddr_t, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(None))] +except AttributeError: + pass +try: + pci_device_unmap_range = _libraries['libpciaccess.so'].pci_device_unmap_range + pci_device_unmap_range.restype = ctypes.c_int32 + pci_device_unmap_range.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(None), pciaddr_t] +except AttributeError: + pass +try: + pci_device_map_memory_range = _libraries['libpciaccess.so'].pci_device_map_memory_range + pci_device_map_memory_range.restype = ctypes.c_int32 + pci_device_map_memory_range.argtypes = [ctypes.POINTER(struct_pci_device), pciaddr_t, pciaddr_t, ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(None))] +except AttributeError: + pass +try: + pci_device_unmap_memory_range = _libraries['libpciaccess.so'].pci_device_unmap_memory_range + pci_device_unmap_memory_range.restype = ctypes.c_int32 + pci_device_unmap_memory_range.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(None), pciaddr_t] +except AttributeError: + pass +try: + pci_device_probe = _libraries['libpciaccess.so'].pci_device_probe + pci_device_probe.restype = ctypes.c_int32 + pci_device_probe.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +class struct_pci_agp_info(Structure): + pass + +try: + pci_device_get_agp_info = _libraries['libpciaccess.so'].pci_device_get_agp_info + pci_device_get_agp_info.restype = ctypes.POINTER(struct_pci_agp_info) + pci_device_get_agp_info.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +class struct_pci_bridge_info(Structure): + pass + +try: + pci_device_get_bridge_info = _libraries['libpciaccess.so'].pci_device_get_bridge_info + pci_device_get_bridge_info.restype = ctypes.POINTER(struct_pci_bridge_info) + pci_device_get_bridge_info.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +class struct_pci_pcmcia_bridge_info(Structure): + pass + +try: + pci_device_get_pcmcia_bridge_info = _libraries['libpciaccess.so'].pci_device_get_pcmcia_bridge_info + pci_device_get_pcmcia_bridge_info.restype = ctypes.POINTER(struct_pci_pcmcia_bridge_info) + pci_device_get_pcmcia_bridge_info.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_get_bridge_buses = _libraries['libpciaccess.so'].pci_device_get_bridge_buses + pci_device_get_bridge_buses.restype = ctypes.c_int32 + pci_device_get_bridge_buses.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: + pass +try: + pci_system_init = _libraries['libpciaccess.so'].pci_system_init + pci_system_init.restype = ctypes.c_int32 + pci_system_init.argtypes = [] +except AttributeError: + pass +try: + pci_system_init_dev_mem = _libraries['libpciaccess.so'].pci_system_init_dev_mem + pci_system_init_dev_mem.restype = None + pci_system_init_dev_mem.argtypes = [ctypes.c_int32] +except AttributeError: + pass +try: + pci_system_cleanup = _libraries['libpciaccess.so'].pci_system_cleanup + pci_system_cleanup.restype = None + pci_system_cleanup.argtypes = [] +except AttributeError: + pass +class struct_pci_slot_match(Structure): + pass + +try: + pci_slot_match_iterator_create = _libraries['libpciaccess.so'].pci_slot_match_iterator_create + pci_slot_match_iterator_create.restype = ctypes.POINTER(struct_pci_device_iterator) + pci_slot_match_iterator_create.argtypes = [ctypes.POINTER(struct_pci_slot_match)] +except AttributeError: + pass +class struct_pci_id_match(Structure): + pass + +try: + pci_id_match_iterator_create = _libraries['libpciaccess.so'].pci_id_match_iterator_create + pci_id_match_iterator_create.restype = ctypes.POINTER(struct_pci_device_iterator) + pci_id_match_iterator_create.argtypes = [ctypes.POINTER(struct_pci_id_match)] +except AttributeError: + pass +try: + pci_iterator_destroy = _libraries['libpciaccess.so'].pci_iterator_destroy + pci_iterator_destroy.restype = None + pci_iterator_destroy.argtypes = [ctypes.POINTER(struct_pci_device_iterator)] +except AttributeError: + pass +try: + pci_device_next = _libraries['libpciaccess.so'].pci_device_next + pci_device_next.restype = ctypes.POINTER(struct_pci_device) + pci_device_next.argtypes = [ctypes.POINTER(struct_pci_device_iterator)] +except AttributeError: + pass +uint32_t = ctypes.c_uint32 +try: + pci_device_find_by_slot = _libraries['libpciaccess.so'].pci_device_find_by_slot + pci_device_find_by_slot.restype = ctypes.POINTER(struct_pci_device) + pci_device_find_by_slot.argtypes = [uint32_t, uint32_t, uint32_t, uint32_t] +except AttributeError: + pass +try: + pci_device_get_parent_bridge = _libraries['libpciaccess.so'].pci_device_get_parent_bridge + pci_device_get_parent_bridge.restype = ctypes.POINTER(struct_pci_device) + pci_device_get_parent_bridge.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_get_strings = _libraries['libpciaccess.so'].pci_get_strings + pci_get_strings.restype = None + pci_get_strings.argtypes = [ctypes.POINTER(struct_pci_id_match), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: + pass +try: + pci_device_get_device_name = _libraries['libpciaccess.so'].pci_device_get_device_name + pci_device_get_device_name.restype = ctypes.POINTER(ctypes.c_char) + pci_device_get_device_name.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_get_subdevice_name = _libraries['libpciaccess.so'].pci_device_get_subdevice_name + pci_device_get_subdevice_name.restype = ctypes.POINTER(ctypes.c_char) + pci_device_get_subdevice_name.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_get_vendor_name = _libraries['libpciaccess.so'].pci_device_get_vendor_name + pci_device_get_vendor_name.restype = ctypes.POINTER(ctypes.c_char) + pci_device_get_vendor_name.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_get_subvendor_name = _libraries['libpciaccess.so'].pci_device_get_subvendor_name + pci_device_get_subvendor_name.restype = ctypes.POINTER(ctypes.c_char) + pci_device_get_subvendor_name.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_enable = _libraries['libpciaccess.so'].pci_device_enable + pci_device_enable.restype = None + pci_device_enable.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_cfg_read = _libraries['libpciaccess.so'].pci_device_cfg_read + pci_device_cfg_read.restype = ctypes.c_int32 + pci_device_cfg_read.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(None), pciaddr_t, pciaddr_t, ctypes.POINTER(ctypes.c_uint64)] +except AttributeError: + pass +try: + pci_device_cfg_read_u8 = _libraries['libpciaccess.so'].pci_device_cfg_read_u8 + pci_device_cfg_read_u8.restype = ctypes.c_int32 + pci_device_cfg_read_u8.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(ctypes.c_ubyte), pciaddr_t] +except AttributeError: + pass +try: + pci_device_cfg_read_u16 = _libraries['libpciaccess.so'].pci_device_cfg_read_u16 + pci_device_cfg_read_u16.restype = ctypes.c_int32 + pci_device_cfg_read_u16.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(ctypes.c_uint16), pciaddr_t] +except AttributeError: + pass +try: + pci_device_cfg_read_u32 = _libraries['libpciaccess.so'].pci_device_cfg_read_u32 + pci_device_cfg_read_u32.restype = ctypes.c_int32 + pci_device_cfg_read_u32.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(ctypes.c_uint32), pciaddr_t] +except AttributeError: + pass +try: + pci_device_cfg_write = _libraries['libpciaccess.so'].pci_device_cfg_write + pci_device_cfg_write.restype = ctypes.c_int32 + pci_device_cfg_write.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(None), pciaddr_t, pciaddr_t, ctypes.POINTER(ctypes.c_uint64)] +except AttributeError: + pass +uint8_t = ctypes.c_uint8 +try: + pci_device_cfg_write_u8 = _libraries['libpciaccess.so'].pci_device_cfg_write_u8 + pci_device_cfg_write_u8.restype = ctypes.c_int32 + pci_device_cfg_write_u8.argtypes = [ctypes.POINTER(struct_pci_device), uint8_t, pciaddr_t] +except AttributeError: + pass +uint16_t = ctypes.c_uint16 +try: + pci_device_cfg_write_u16 = _libraries['libpciaccess.so'].pci_device_cfg_write_u16 + pci_device_cfg_write_u16.restype = ctypes.c_int32 + pci_device_cfg_write_u16.argtypes = [ctypes.POINTER(struct_pci_device), uint16_t, pciaddr_t] +except AttributeError: + pass +try: + pci_device_cfg_write_u32 = _libraries['libpciaccess.so'].pci_device_cfg_write_u32 + pci_device_cfg_write_u32.restype = ctypes.c_int32 + pci_device_cfg_write_u32.argtypes = [ctypes.POINTER(struct_pci_device), uint32_t, pciaddr_t] +except AttributeError: + pass +try: + pci_device_cfg_write_bits = _libraries['libpciaccess.so'].pci_device_cfg_write_bits + pci_device_cfg_write_bits.restype = ctypes.c_int32 + pci_device_cfg_write_bits.argtypes = [ctypes.POINTER(struct_pci_device), uint32_t, uint32_t, pciaddr_t] +except AttributeError: + pass +class struct_pci_mem_region(Structure): + pass + +struct_pci_mem_region._pack_ = 1 # source:False +struct_pci_mem_region._fields_ = [ + ('memory', ctypes.POINTER(None)), + ('bus_addr', ctypes.c_uint64), + ('base_addr', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('is_IO', ctypes.c_uint32, 1), + ('is_prefetchable', ctypes.c_uint32, 1), + ('is_64', ctypes.c_uint32, 1), + ('PADDING_0', ctypes.c_uint64, 61), +] + +class struct_pci_pcmcia_bridge_info_0(Structure): + pass + +struct_pci_pcmcia_bridge_info_0._pack_ = 1 # source:False +struct_pci_pcmcia_bridge_info_0._fields_ = [ + ('base', ctypes.c_uint32), + ('limit', ctypes.c_uint32), +] + +class struct_pci_pcmcia_bridge_info_1(Structure): + pass + +struct_pci_pcmcia_bridge_info_1._pack_ = 1 # source:False +struct_pci_pcmcia_bridge_info_1._fields_ = [ + ('base', ctypes.c_uint32), + ('limit', ctypes.c_uint32), +] + +try: + pci_device_vgaarb_init = _libraries['libpciaccess.so'].pci_device_vgaarb_init + pci_device_vgaarb_init.restype = ctypes.c_int32 + pci_device_vgaarb_init.argtypes = [] +except AttributeError: + pass +try: + pci_device_vgaarb_fini = _libraries['libpciaccess.so'].pci_device_vgaarb_fini + pci_device_vgaarb_fini.restype = None + pci_device_vgaarb_fini.argtypes = [] +except AttributeError: + pass +try: + pci_device_vgaarb_set_target = _libraries['libpciaccess.so'].pci_device_vgaarb_set_target + pci_device_vgaarb_set_target.restype = ctypes.c_int32 + pci_device_vgaarb_set_target.argtypes = [ctypes.POINTER(struct_pci_device)] +except AttributeError: + pass +try: + pci_device_vgaarb_decodes = _libraries['libpciaccess.so'].pci_device_vgaarb_decodes + pci_device_vgaarb_decodes.restype = ctypes.c_int32 + pci_device_vgaarb_decodes.argtypes = [ctypes.c_int32] +except AttributeError: + pass +try: + pci_device_vgaarb_lock = _libraries['libpciaccess.so'].pci_device_vgaarb_lock + pci_device_vgaarb_lock.restype = ctypes.c_int32 + pci_device_vgaarb_lock.argtypes = [] +except AttributeError: + pass +try: + pci_device_vgaarb_trylock = _libraries['libpciaccess.so'].pci_device_vgaarb_trylock + pci_device_vgaarb_trylock.restype = ctypes.c_int32 + pci_device_vgaarb_trylock.argtypes = [] +except AttributeError: + pass +try: + pci_device_vgaarb_unlock = _libraries['libpciaccess.so'].pci_device_vgaarb_unlock + pci_device_vgaarb_unlock.restype = ctypes.c_int32 + pci_device_vgaarb_unlock.argtypes = [] +except AttributeError: + pass +try: + pci_device_vgaarb_get_info = _libraries['libpciaccess.so'].pci_device_vgaarb_get_info + pci_device_vgaarb_get_info.restype = ctypes.c_int32 + pci_device_vgaarb_get_info.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: + pass +class struct_pci_io_handle(Structure): + pass + +try: + pci_device_open_io = _libraries['libpciaccess.so'].pci_device_open_io + pci_device_open_io.restype = ctypes.POINTER(struct_pci_io_handle) + pci_device_open_io.argtypes = [ctypes.POINTER(struct_pci_device), pciaddr_t, pciaddr_t] +except AttributeError: + pass +try: + pci_legacy_open_io = _libraries['libpciaccess.so'].pci_legacy_open_io + pci_legacy_open_io.restype = ctypes.POINTER(struct_pci_io_handle) + pci_legacy_open_io.argtypes = [ctypes.POINTER(struct_pci_device), pciaddr_t, pciaddr_t] +except AttributeError: + pass +try: + pci_device_close_io = _libraries['libpciaccess.so'].pci_device_close_io + pci_device_close_io.restype = None + pci_device_close_io.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(struct_pci_io_handle)] +except AttributeError: + pass +try: + pci_io_read32 = _libraries['libpciaccess.so'].pci_io_read32 + pci_io_read32.restype = uint32_t + pci_io_read32.argtypes = [ctypes.POINTER(struct_pci_io_handle), uint32_t] +except AttributeError: + pass +try: + pci_io_read16 = _libraries['libpciaccess.so'].pci_io_read16 + pci_io_read16.restype = uint16_t + pci_io_read16.argtypes = [ctypes.POINTER(struct_pci_io_handle), uint32_t] +except AttributeError: + pass +try: + pci_io_read8 = _libraries['libpciaccess.so'].pci_io_read8 + pci_io_read8.restype = uint8_t + pci_io_read8.argtypes = [ctypes.POINTER(struct_pci_io_handle), uint32_t] +except AttributeError: + pass +try: + pci_io_write32 = _libraries['libpciaccess.so'].pci_io_write32 + pci_io_write32.restype = None + pci_io_write32.argtypes = [ctypes.POINTER(struct_pci_io_handle), uint32_t, uint32_t] +except AttributeError: + pass +try: + pci_io_write16 = _libraries['libpciaccess.so'].pci_io_write16 + pci_io_write16.restype = None + pci_io_write16.argtypes = [ctypes.POINTER(struct_pci_io_handle), uint32_t, uint16_t] +except AttributeError: + pass +try: + pci_io_write8 = _libraries['libpciaccess.so'].pci_io_write8 + pci_io_write8.restype = None + pci_io_write8.argtypes = [ctypes.POINTER(struct_pci_io_handle), uint32_t, uint8_t] +except AttributeError: + pass +try: + pci_device_map_legacy = _libraries['libpciaccess.so'].pci_device_map_legacy + pci_device_map_legacy.restype = ctypes.c_int32 + pci_device_map_legacy.argtypes = [ctypes.POINTER(struct_pci_device), pciaddr_t, pciaddr_t, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(None))] +except AttributeError: + pass +try: + pci_device_unmap_legacy = _libraries['libpciaccess.so'].pci_device_unmap_legacy + pci_device_unmap_legacy.restype = ctypes.c_int32 + pci_device_unmap_legacy.argtypes = [ctypes.POINTER(struct_pci_device), ctypes.POINTER(None), pciaddr_t] +except AttributeError: + pass +LINUX_PCI_REGS_H = True # macro +PCI_CFG_SPACE_SIZE = 256 # macro +PCI_CFG_SPACE_EXP_SIZE = 4096 # macro +PCI_STD_HEADER_SIZEOF = 64 # macro +PCI_STD_NUM_BARS = 6 # macro +PCI_VENDOR_ID = 0x00 # macro +PCI_DEVICE_ID = 0x02 # macro +PCI_COMMAND = 0x04 # macro +PCI_COMMAND_IO = 0x1 # macro +PCI_COMMAND_MEMORY = 0x2 # macro +PCI_COMMAND_MASTER = 0x4 # macro +PCI_COMMAND_SPECIAL = 0x8 # macro +PCI_COMMAND_INVALIDATE = 0x10 # macro +PCI_COMMAND_VGA_PALETTE = 0x20 # macro +PCI_COMMAND_PARITY = 0x40 # macro +PCI_COMMAND_WAIT = 0x80 # macro +PCI_COMMAND_SERR = 0x100 # macro +PCI_COMMAND_FAST_BACK = 0x200 # macro +PCI_COMMAND_INTX_DISABLE = 0x400 # macro +PCI_STATUS = 0x06 # macro +PCI_STATUS_IMM_READY = 0x01 # macro +PCI_STATUS_INTERRUPT = 0x08 # macro +PCI_STATUS_CAP_LIST = 0x10 # macro +PCI_STATUS_66MHZ = 0x20 # macro +PCI_STATUS_UDF = 0x40 # macro +PCI_STATUS_FAST_BACK = 0x80 # macro +PCI_STATUS_PARITY = 0x100 # macro +PCI_STATUS_DEVSEL_MASK = 0x600 # macro +PCI_STATUS_DEVSEL_FAST = 0x000 # macro +PCI_STATUS_DEVSEL_MEDIUM = 0x200 # macro +PCI_STATUS_DEVSEL_SLOW = 0x400 # macro +PCI_STATUS_SIG_TARGET_ABORT = 0x800 # macro +PCI_STATUS_REC_TARGET_ABORT = 0x1000 # macro +PCI_STATUS_REC_MASTER_ABORT = 0x2000 # macro +PCI_STATUS_SIG_SYSTEM_ERROR = 0x4000 # macro +PCI_STATUS_DETECTED_PARITY = 0x8000 # macro +PCI_CLASS_REVISION = 0x08 # macro +PCI_REVISION_ID = 0x08 # macro +PCI_CLASS_PROG = 0x09 # macro +PCI_CLASS_DEVICE = 0x0a # macro +PCI_CACHE_LINE_SIZE = 0x0c # macro +PCI_LATENCY_TIMER = 0x0d # macro +PCI_HEADER_TYPE = 0x0e # macro +PCI_HEADER_TYPE_MASK = 0x7f # macro +PCI_HEADER_TYPE_NORMAL = 0 # macro +PCI_HEADER_TYPE_BRIDGE = 1 # macro +PCI_HEADER_TYPE_CARDBUS = 2 # macro +PCI_BIST = 0x0f # macro +PCI_BIST_CODE_MASK = 0x0f # macro +PCI_BIST_START = 0x40 # macro +PCI_BIST_CAPABLE = 0x80 # macro +PCI_BASE_ADDRESS_0 = 0x10 # macro +PCI_BASE_ADDRESS_1 = 0x14 # macro +PCI_BASE_ADDRESS_2 = 0x18 # macro +PCI_BASE_ADDRESS_3 = 0x1c # macro +PCI_BASE_ADDRESS_4 = 0x20 # macro +PCI_BASE_ADDRESS_5 = 0x24 # macro +PCI_BASE_ADDRESS_SPACE = 0x01 # macro +PCI_BASE_ADDRESS_SPACE_IO = 0x01 # macro +PCI_BASE_ADDRESS_SPACE_MEMORY = 0x00 # macro +PCI_BASE_ADDRESS_MEM_TYPE_MASK = 0x06 # macro +PCI_BASE_ADDRESS_MEM_TYPE_32 = 0x00 # macro +PCI_BASE_ADDRESS_MEM_TYPE_1M = 0x02 # macro +PCI_BASE_ADDRESS_MEM_TYPE_64 = 0x04 # macro +PCI_BASE_ADDRESS_MEM_PREFETCH = 0x08 # macro +PCI_BASE_ADDRESS_MEM_MASK = (~0x0f) # macro +PCI_BASE_ADDRESS_IO_MASK = (~0x03) # macro +PCI_CARDBUS_CIS = 0x28 # macro +PCI_SUBSYSTEM_VENDOR_ID = 0x2c # macro +PCI_SUBSYSTEM_ID = 0x2e # macro +PCI_ROM_ADDRESS = 0x30 # macro +PCI_ROM_ADDRESS_ENABLE = 0x01 # macro +PCI_ROM_ADDRESS_MASK = (~0x7ff) # macro +PCI_CAPABILITY_LIST = 0x34 # macro +PCI_INTERRUPT_LINE = 0x3c # macro +PCI_INTERRUPT_PIN = 0x3d # macro +PCI_MIN_GNT = 0x3e # macro +PCI_MAX_LAT = 0x3f # macro +PCI_PRIMARY_BUS = 0x18 # macro +PCI_SECONDARY_BUS = 0x19 # macro +PCI_SUBORDINATE_BUS = 0x1a # macro +PCI_SEC_LATENCY_TIMER = 0x1b # macro +PCI_IO_BASE = 0x1c # macro +PCI_IO_LIMIT = 0x1d # macro +PCI_IO_RANGE_TYPE_MASK = 0x0f # macro +PCI_IO_RANGE_TYPE_16 = 0x00 # macro +PCI_IO_RANGE_TYPE_32 = 0x01 # macro +PCI_IO_RANGE_MASK = (~0x0f) # macro +PCI_IO_1K_RANGE_MASK = (~0x03) # macro +PCI_SEC_STATUS = 0x1e # macro +PCI_MEMORY_BASE = 0x20 # macro +PCI_MEMORY_LIMIT = 0x22 # macro +PCI_MEMORY_RANGE_TYPE_MASK = 0x0f # macro +PCI_MEMORY_RANGE_MASK = (~0x0f) # macro +PCI_PREF_MEMORY_BASE = 0x24 # macro +PCI_PREF_MEMORY_LIMIT = 0x26 # macro +PCI_PREF_RANGE_TYPE_MASK = 0x0f # macro +PCI_PREF_RANGE_TYPE_32 = 0x00 # macro +PCI_PREF_RANGE_TYPE_64 = 0x01 # macro +PCI_PREF_RANGE_MASK = (~0x0f) # macro +PCI_PREF_BASE_UPPER32 = 0x28 # macro +PCI_PREF_LIMIT_UPPER32 = 0x2c # macro +PCI_IO_BASE_UPPER16 = 0x30 # macro +PCI_IO_LIMIT_UPPER16 = 0x32 # macro +PCI_ROM_ADDRESS1 = 0x38 # macro +PCI_BRIDGE_CONTROL = 0x3e # macro +PCI_BRIDGE_CTL_PARITY = 0x01 # macro +PCI_BRIDGE_CTL_SERR = 0x02 # macro +PCI_BRIDGE_CTL_ISA = 0x04 # macro +PCI_BRIDGE_CTL_VGA = 0x08 # macro +PCI_BRIDGE_CTL_MASTER_ABORT = 0x20 # macro +PCI_BRIDGE_CTL_BUS_RESET = 0x40 # macro +PCI_BRIDGE_CTL_FAST_BACK = 0x80 # macro +PCI_CB_CAPABILITY_LIST = 0x14 # macro +PCI_CB_SEC_STATUS = 0x16 # macro +PCI_CB_PRIMARY_BUS = 0x18 # macro +PCI_CB_CARD_BUS = 0x19 # macro +PCI_CB_SUBORDINATE_BUS = 0x1a # macro +PCI_CB_LATENCY_TIMER = 0x1b # macro +PCI_CB_MEMORY_BASE_0 = 0x1c # macro +PCI_CB_MEMORY_LIMIT_0 = 0x20 # macro +PCI_CB_MEMORY_BASE_1 = 0x24 # macro +PCI_CB_MEMORY_LIMIT_1 = 0x28 # macro +PCI_CB_IO_BASE_0 = 0x2c # macro +PCI_CB_IO_BASE_0_HI = 0x2e # macro +PCI_CB_IO_LIMIT_0 = 0x30 # macro +PCI_CB_IO_LIMIT_0_HI = 0x32 # macro +PCI_CB_IO_BASE_1 = 0x34 # macro +PCI_CB_IO_BASE_1_HI = 0x36 # macro +PCI_CB_IO_LIMIT_1 = 0x38 # macro +PCI_CB_IO_LIMIT_1_HI = 0x3a # macro +PCI_CB_IO_RANGE_MASK = (~0x03) # macro +PCI_CB_BRIDGE_CONTROL = 0x3e # macro +PCI_CB_BRIDGE_CTL_PARITY = 0x01 # macro +PCI_CB_BRIDGE_CTL_SERR = 0x02 # macro +PCI_CB_BRIDGE_CTL_ISA = 0x04 # macro +PCI_CB_BRIDGE_CTL_VGA = 0x08 # macro +PCI_CB_BRIDGE_CTL_MASTER_ABORT = 0x20 # macro +PCI_CB_BRIDGE_CTL_CB_RESET = 0x40 # macro +PCI_CB_BRIDGE_CTL_16BIT_INT = 0x80 # macro +PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 = 0x100 # macro +PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 = 0x200 # macro +PCI_CB_BRIDGE_CTL_POST_WRITES = 0x400 # macro +PCI_CB_SUBSYSTEM_VENDOR_ID = 0x40 # macro +PCI_CB_SUBSYSTEM_ID = 0x42 # macro +PCI_CB_LEGACY_MODE_BASE = 0x44 # macro +PCI_CAP_LIST_ID = 0 # macro +PCI_CAP_ID_PM = 0x01 # macro +PCI_CAP_ID_AGP = 0x02 # macro +PCI_CAP_ID_VPD = 0x03 # macro +PCI_CAP_ID_SLOTID = 0x04 # macro +PCI_CAP_ID_MSI = 0x05 # macro +PCI_CAP_ID_CHSWP = 0x06 # macro +PCI_CAP_ID_PCIX = 0x07 # macro +PCI_CAP_ID_HT = 0x08 # macro +PCI_CAP_ID_VNDR = 0x09 # macro +PCI_CAP_ID_DBG = 0x0A # macro +PCI_CAP_ID_CCRC = 0x0B # macro +PCI_CAP_ID_SHPC = 0x0C # macro +PCI_CAP_ID_SSVID = 0x0D # macro +PCI_CAP_ID_AGP3 = 0x0E # macro +PCI_CAP_ID_SECDEV = 0x0F # macro +PCI_CAP_ID_EXP = 0x10 # macro +PCI_CAP_ID_MSIX = 0x11 # macro +PCI_CAP_ID_SATA = 0x12 # macro +PCI_CAP_ID_AF = 0x13 # macro +PCI_CAP_ID_EA = 0x14 # macro +PCI_CAP_ID_MAX = 0x14 # macro +PCI_CAP_LIST_NEXT = 1 # macro +PCI_CAP_FLAGS = 2 # macro +PCI_CAP_SIZEOF = 4 # macro +PCI_PM_PMC = 2 # macro +PCI_PM_CAP_VER_MASK = 0x0007 # macro +PCI_PM_CAP_PME_CLOCK = 0x0008 # macro +PCI_PM_CAP_RESERVED = 0x0010 # macro +PCI_PM_CAP_DSI = 0x0020 # macro +PCI_PM_CAP_AUX_POWER = 0x01C0 # macro +PCI_PM_CAP_D1 = 0x0200 # macro +PCI_PM_CAP_D2 = 0x0400 # macro +PCI_PM_CAP_PME = 0x0800 # macro +PCI_PM_CAP_PME_MASK = 0xF800 # macro +PCI_PM_CAP_PME_D0 = 0x0800 # macro +PCI_PM_CAP_PME_D1 = 0x1000 # macro +PCI_PM_CAP_PME_D2 = 0x2000 # macro +PCI_PM_CAP_PME_D3hot = 0x4000 # macro +PCI_PM_CAP_PME_D3cold = 0x8000 # macro +PCI_PM_CAP_PME_SHIFT = 11 # macro +PCI_PM_CTRL = 4 # macro +PCI_PM_CTRL_STATE_MASK = 0x0003 # macro +PCI_PM_CTRL_NO_SOFT_RESET = 0x0008 # macro +PCI_PM_CTRL_PME_ENABLE = 0x0100 # macro +PCI_PM_CTRL_DATA_SEL_MASK = 0x1e00 # macro +PCI_PM_CTRL_DATA_SCALE_MASK = 0x6000 # macro +PCI_PM_CTRL_PME_STATUS = 0x8000 # macro +PCI_PM_PPB_EXTENSIONS = 6 # macro +PCI_PM_PPB_B2_B3 = 0x40 # macro +PCI_PM_BPCC_ENABLE = 0x80 # macro +PCI_PM_DATA_REGISTER = 7 # macro +PCI_PM_SIZEOF = 8 # macro +PCI_AGP_VERSION = 2 # macro +PCI_AGP_RFU = 3 # macro +PCI_AGP_STATUS = 4 # macro +PCI_AGP_STATUS_RQ_MASK = 0xff000000 # macro +PCI_AGP_STATUS_SBA = 0x0200 # macro +PCI_AGP_STATUS_64BIT = 0x0020 # macro +PCI_AGP_STATUS_FW = 0x0010 # macro +PCI_AGP_STATUS_RATE4 = 0x0004 # macro +PCI_AGP_STATUS_RATE2 = 0x0002 # macro +PCI_AGP_STATUS_RATE1 = 0x0001 # macro +PCI_AGP_COMMAND = 8 # macro +PCI_AGP_COMMAND_RQ_MASK = 0xff000000 # macro +PCI_AGP_COMMAND_SBA = 0x0200 # macro +PCI_AGP_COMMAND_AGP = 0x0100 # macro +PCI_AGP_COMMAND_64BIT = 0x0020 # macro +PCI_AGP_COMMAND_FW = 0x0010 # macro +PCI_AGP_COMMAND_RATE4 = 0x0004 # macro +PCI_AGP_COMMAND_RATE2 = 0x0002 # macro +PCI_AGP_COMMAND_RATE1 = 0x0001 # macro +PCI_AGP_SIZEOF = 12 # macro +PCI_VPD_ADDR = 2 # macro +PCI_VPD_ADDR_MASK = 0x7fff # macro +PCI_VPD_ADDR_F = 0x8000 # macro +PCI_VPD_DATA = 4 # macro +PCI_CAP_VPD_SIZEOF = 8 # macro +PCI_SID_ESR = 2 # macro +PCI_SID_ESR_NSLOTS = 0x1f # macro +PCI_SID_ESR_FIC = 0x20 # macro +PCI_SID_CHASSIS_NR = 3 # macro +PCI_MSI_FLAGS = 2 # macro +PCI_MSI_FLAGS_ENABLE = 0x0001 # macro +PCI_MSI_FLAGS_QMASK = 0x000e # macro +PCI_MSI_FLAGS_QSIZE = 0x0070 # macro +PCI_MSI_FLAGS_64BIT = 0x0080 # macro +PCI_MSI_FLAGS_MASKBIT = 0x0100 # macro +PCI_MSI_RFU = 3 # macro +PCI_MSI_ADDRESS_LO = 4 # macro +PCI_MSI_ADDRESS_HI = 8 # macro +PCI_MSI_DATA_32 = 8 # macro +PCI_MSI_MASK_32 = 12 # macro +PCI_MSI_PENDING_32 = 16 # macro +PCI_MSI_DATA_64 = 12 # macro +PCI_MSI_MASK_64 = 16 # macro +PCI_MSI_PENDING_64 = 20 # macro +PCI_MSIX_FLAGS = 2 # macro +PCI_MSIX_FLAGS_QSIZE = 0x07FF # macro +PCI_MSIX_FLAGS_MASKALL = 0x4000 # macro +PCI_MSIX_FLAGS_ENABLE = 0x8000 # macro +PCI_MSIX_TABLE = 4 # macro +PCI_MSIX_TABLE_BIR = 0x00000007 # macro +PCI_MSIX_TABLE_OFFSET = 0xfffffff8 # macro +PCI_MSIX_PBA = 8 # macro +PCI_MSIX_PBA_BIR = 0x00000007 # macro +PCI_MSIX_PBA_OFFSET = 0xfffffff8 # macro +PCI_MSIX_FLAGS_BIRMASK = 0x00000007 # macro +PCI_CAP_MSIX_SIZEOF = 12 # macro +PCI_MSIX_ENTRY_SIZE = 16 # macro +PCI_MSIX_ENTRY_LOWER_ADDR = 0 # macro +PCI_MSIX_ENTRY_UPPER_ADDR = 4 # macro +PCI_MSIX_ENTRY_DATA = 8 # macro +PCI_MSIX_ENTRY_VECTOR_CTRL = 12 # macro +PCI_MSIX_ENTRY_CTRL_MASKBIT = 0x00000001 # macro +PCI_CHSWP_CSR = 2 # macro +PCI_CHSWP_DHA = 0x01 # macro +PCI_CHSWP_EIM = 0x02 # macro +PCI_CHSWP_PIE = 0x04 # macro +PCI_CHSWP_LOO = 0x08 # macro +PCI_CHSWP_PI = 0x30 # macro +PCI_CHSWP_EXT = 0x40 # macro +PCI_CHSWP_INS = 0x80 # macro +PCI_AF_LENGTH = 2 # macro +PCI_AF_CAP = 3 # macro +PCI_AF_CAP_TP = 0x01 # macro +PCI_AF_CAP_FLR = 0x02 # macro +PCI_AF_CTRL = 4 # macro +PCI_AF_CTRL_FLR = 0x01 # macro +PCI_AF_STATUS = 5 # macro +PCI_AF_STATUS_TP = 0x01 # macro +PCI_CAP_AF_SIZEOF = 6 # macro +PCI_EA_NUM_ENT = 2 # macro +PCI_EA_NUM_ENT_MASK = 0x3f # macro +PCI_EA_FIRST_ENT = 4 # macro +PCI_EA_FIRST_ENT_BRIDGE = 8 # macro +PCI_EA_ES = 0x00000007 # macro +PCI_EA_BEI = 0x000000f0 # macro +PCI_EA_SEC_BUS_MASK = 0xff # macro +PCI_EA_SUB_BUS_MASK = 0xff00 # macro +PCI_EA_SUB_BUS_SHIFT = 8 # macro +PCI_EA_BEI_BAR0 = 0 # macro +PCI_EA_BEI_BAR5 = 5 # macro +PCI_EA_BEI_BRIDGE = 6 # macro +PCI_EA_BEI_ENI = 7 # macro +PCI_EA_BEI_ROM = 8 # macro +PCI_EA_BEI_VF_BAR0 = 9 # macro +PCI_EA_BEI_VF_BAR5 = 14 # macro +PCI_EA_BEI_RESERVED = 15 # macro +PCI_EA_PP = 0x0000ff00 # macro +PCI_EA_SP = 0x00ff0000 # macro +PCI_EA_P_MEM = 0x00 # macro +PCI_EA_P_MEM_PREFETCH = 0x01 # macro +PCI_EA_P_IO = 0x02 # macro +PCI_EA_P_VF_MEM_PREFETCH = 0x03 # macro +PCI_EA_P_VF_MEM = 0x04 # macro +PCI_EA_P_BRIDGE_MEM = 0x05 # macro +PCI_EA_P_BRIDGE_MEM_PREFETCH = 0x06 # macro +PCI_EA_P_BRIDGE_IO = 0x07 # macro +PCI_EA_P_MEM_RESERVED = 0xfd # macro +PCI_EA_P_IO_RESERVED = 0xfe # macro +PCI_EA_P_UNAVAILABLE = 0xff # macro +PCI_EA_WRITABLE = 0x40000000 # macro +PCI_EA_ENABLE = 0x80000000 # macro +PCI_EA_BASE = 4 # macro +PCI_EA_MAX_OFFSET = 8 # macro +PCI_EA_IS_64 = 0x00000002 # macro +PCI_EA_FIELD_MASK = 0xfffffffc # macro +PCI_X_CMD = 2 # macro +PCI_X_CMD_DPERR_E = 0x0001 # macro +PCI_X_CMD_ERO = 0x0002 # macro +PCI_X_CMD_READ_512 = 0x0000 # macro +PCI_X_CMD_READ_1K = 0x0004 # macro +PCI_X_CMD_READ_2K = 0x0008 # macro +PCI_X_CMD_READ_4K = 0x000c # macro +PCI_X_CMD_MAX_READ = 0x000c # macro +PCI_X_CMD_SPLIT_1 = 0x0000 # macro +PCI_X_CMD_SPLIT_2 = 0x0010 # macro +PCI_X_CMD_SPLIT_3 = 0x0020 # macro +PCI_X_CMD_SPLIT_4 = 0x0030 # macro +PCI_X_CMD_SPLIT_8 = 0x0040 # macro +PCI_X_CMD_SPLIT_12 = 0x0050 # macro +PCI_X_CMD_SPLIT_16 = 0x0060 # macro +PCI_X_CMD_SPLIT_32 = 0x0070 # macro +PCI_X_CMD_MAX_SPLIT = 0x0070 # macro +def PCI_X_CMD_VERSION(x): # macro + return (((x)>>12)&3) +PCI_X_STATUS = 4 # macro +PCI_X_STATUS_DEVFN = 0x000000ff # macro +PCI_X_STATUS_BUS = 0x0000ff00 # macro +PCI_X_STATUS_64BIT = 0x00010000 # macro +PCI_X_STATUS_133MHZ = 0x00020000 # macro +PCI_X_STATUS_SPL_DISC = 0x00040000 # macro +PCI_X_STATUS_UNX_SPL = 0x00080000 # macro +PCI_X_STATUS_COMPLEX = 0x00100000 # macro +PCI_X_STATUS_MAX_READ = 0x00600000 # macro +PCI_X_STATUS_MAX_SPLIT = 0x03800000 # macro +PCI_X_STATUS_MAX_CUM = 0x1c000000 # macro +PCI_X_STATUS_SPL_ERR = 0x20000000 # macro +PCI_X_STATUS_266MHZ = 0x40000000 # macro +PCI_X_STATUS_533MHZ = 0x80000000 # macro +PCI_X_ECC_CSR = 8 # macro +PCI_CAP_PCIX_SIZEOF_V0 = 8 # macro +PCI_CAP_PCIX_SIZEOF_V1 = 24 # macro +PCI_CAP_PCIX_SIZEOF_V2 = 24 # macro +PCI_X_BRIDGE_SSTATUS = 2 # macro +PCI_X_SSTATUS_64BIT = 0x0001 # macro +PCI_X_SSTATUS_133MHZ = 0x0002 # macro +PCI_X_SSTATUS_FREQ = 0x03c0 # macro +PCI_X_SSTATUS_VERS = 0x3000 # macro +PCI_X_SSTATUS_V1 = 0x1000 # macro +PCI_X_SSTATUS_V2 = 0x2000 # macro +PCI_X_SSTATUS_266MHZ = 0x4000 # macro +PCI_X_SSTATUS_533MHZ = 0x8000 # macro +PCI_X_BRIDGE_STATUS = 4 # macro +PCI_SSVID_VENDOR_ID = 4 # macro +PCI_SSVID_DEVICE_ID = 6 # macro +PCI_EXP_FLAGS = 2 # macro +PCI_EXP_FLAGS_VERS = 0x000f # macro +PCI_EXP_FLAGS_TYPE = 0x00f0 # macro +PCI_EXP_TYPE_ENDPOINT = 0x0 # macro +PCI_EXP_TYPE_LEG_END = 0x1 # macro +PCI_EXP_TYPE_ROOT_PORT = 0x4 # macro +PCI_EXP_TYPE_UPSTREAM = 0x5 # macro +PCI_EXP_TYPE_DOWNSTREAM = 0x6 # macro +PCI_EXP_TYPE_PCI_BRIDGE = 0x7 # macro +PCI_EXP_TYPE_PCIE_BRIDGE = 0x8 # macro +PCI_EXP_TYPE_RC_END = 0x9 # macro +PCI_EXP_TYPE_RC_EC = 0xa # macro +PCI_EXP_FLAGS_SLOT = 0x0100 # macro +PCI_EXP_FLAGS_IRQ = 0x3e00 # macro +PCI_EXP_DEVCAP = 4 # macro +PCI_EXP_DEVCAP_PAYLOAD = 0x00000007 # macro +PCI_EXP_DEVCAP_PHANTOM = 0x00000018 # macro +PCI_EXP_DEVCAP_EXT_TAG = 0x00000020 # macro +PCI_EXP_DEVCAP_L0S = 0x000001c0 # macro +PCI_EXP_DEVCAP_L1 = 0x00000e00 # macro +PCI_EXP_DEVCAP_ATN_BUT = 0x00001000 # macro +PCI_EXP_DEVCAP_ATN_IND = 0x00002000 # macro +PCI_EXP_DEVCAP_PWR_IND = 0x00004000 # macro +PCI_EXP_DEVCAP_RBER = 0x00008000 # macro +PCI_EXP_DEVCAP_PWR_VAL = 0x03fc0000 # macro +PCI_EXP_DEVCAP_PWR_SCL = 0x0c000000 # macro +PCI_EXP_DEVCAP_FLR = 0x10000000 # macro +PCI_EXP_DEVCTL = 8 # macro +PCI_EXP_DEVCTL_CERE = 0x0001 # macro +PCI_EXP_DEVCTL_NFERE = 0x0002 # macro +PCI_EXP_DEVCTL_FERE = 0x0004 # macro +PCI_EXP_DEVCTL_URRE = 0x0008 # macro +PCI_EXP_DEVCTL_RELAX_EN = 0x0010 # macro +PCI_EXP_DEVCTL_PAYLOAD = 0x00e0 # macro +PCI_EXP_DEVCTL_PAYLOAD_128B = 0x0000 # macro +PCI_EXP_DEVCTL_PAYLOAD_256B = 0x0020 # macro +PCI_EXP_DEVCTL_PAYLOAD_512B = 0x0040 # macro +PCI_EXP_DEVCTL_PAYLOAD_1024B = 0x0060 # macro +PCI_EXP_DEVCTL_PAYLOAD_2048B = 0x0080 # macro +PCI_EXP_DEVCTL_PAYLOAD_4096B = 0x00a0 # macro +PCI_EXP_DEVCTL_EXT_TAG = 0x0100 # macro +PCI_EXP_DEVCTL_PHANTOM = 0x0200 # macro +PCI_EXP_DEVCTL_AUX_PME = 0x0400 # macro +PCI_EXP_DEVCTL_NOSNOOP_EN = 0x0800 # macro +PCI_EXP_DEVCTL_READRQ = 0x7000 # macro +PCI_EXP_DEVCTL_READRQ_128B = 0x0000 # macro +PCI_EXP_DEVCTL_READRQ_256B = 0x1000 # macro +PCI_EXP_DEVCTL_READRQ_512B = 0x2000 # macro +PCI_EXP_DEVCTL_READRQ_1024B = 0x3000 # macro +PCI_EXP_DEVCTL_READRQ_2048B = 0x4000 # macro +PCI_EXP_DEVCTL_READRQ_4096B = 0x5000 # macro +PCI_EXP_DEVCTL_BCR_FLR = 0x8000 # macro +PCI_EXP_DEVSTA = 10 # macro +PCI_EXP_DEVSTA_CED = 0x0001 # macro +PCI_EXP_DEVSTA_NFED = 0x0002 # macro +PCI_EXP_DEVSTA_FED = 0x0004 # macro +PCI_EXP_DEVSTA_URD = 0x0008 # macro +PCI_EXP_DEVSTA_AUXPD = 0x0010 # macro +PCI_EXP_DEVSTA_TRPND = 0x0020 # macro +PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 = 12 # macro +PCI_EXP_LNKCAP = 12 # macro +PCI_EXP_LNKCAP_SLS = 0x0000000f # macro +PCI_EXP_LNKCAP_SLS_2_5GB = 0x00000001 # macro +PCI_EXP_LNKCAP_SLS_5_0GB = 0x00000002 # macro +PCI_EXP_LNKCAP_SLS_8_0GB = 0x00000003 # macro +PCI_EXP_LNKCAP_SLS_16_0GB = 0x00000004 # macro +PCI_EXP_LNKCAP_SLS_32_0GB = 0x00000005 # macro +PCI_EXP_LNKCAP_SLS_64_0GB = 0x00000006 # macro +PCI_EXP_LNKCAP_MLW = 0x000003f0 # macro +PCI_EXP_LNKCAP_ASPMS = 0x00000c00 # macro +PCI_EXP_LNKCAP_ASPM_L0S = 0x00000400 # macro +PCI_EXP_LNKCAP_ASPM_L1 = 0x00000800 # macro +PCI_EXP_LNKCAP_L0SEL = 0x00007000 # macro +PCI_EXP_LNKCAP_L1EL = 0x00038000 # macro +PCI_EXP_LNKCAP_CLKPM = 0x00040000 # macro +PCI_EXP_LNKCAP_SDERC = 0x00080000 # macro +PCI_EXP_LNKCAP_DLLLARC = 0x00100000 # macro +PCI_EXP_LNKCAP_LBNC = 0x00200000 # macro +PCI_EXP_LNKCAP_PN = 0xff000000 # macro +PCI_EXP_LNKCTL = 16 # macro +PCI_EXP_LNKCTL_ASPMC = 0x0003 # macro +PCI_EXP_LNKCTL_ASPM_L0S = 0x0001 # macro +PCI_EXP_LNKCTL_ASPM_L1 = 0x0002 # macro +PCI_EXP_LNKCTL_RCB = 0x0008 # macro +PCI_EXP_LNKCTL_LD = 0x0010 # macro +PCI_EXP_LNKCTL_RL = 0x0020 # macro +PCI_EXP_LNKCTL_CCC = 0x0040 # macro +PCI_EXP_LNKCTL_ES = 0x0080 # macro +PCI_EXP_LNKCTL_CLKREQ_EN = 0x0100 # macro +PCI_EXP_LNKCTL_HAWD = 0x0200 # macro +PCI_EXP_LNKCTL_LBMIE = 0x0400 # macro +PCI_EXP_LNKCTL_LABIE = 0x0800 # macro +PCI_EXP_LNKSTA = 18 # macro +PCI_EXP_LNKSTA_CLS = 0x000f # macro +PCI_EXP_LNKSTA_CLS_2_5GB = 0x0001 # macro +PCI_EXP_LNKSTA_CLS_5_0GB = 0x0002 # macro +PCI_EXP_LNKSTA_CLS_8_0GB = 0x0003 # macro +PCI_EXP_LNKSTA_CLS_16_0GB = 0x0004 # macro +PCI_EXP_LNKSTA_CLS_32_0GB = 0x0005 # macro +PCI_EXP_LNKSTA_CLS_64_0GB = 0x0006 # macro +PCI_EXP_LNKSTA_NLW = 0x03f0 # macro +PCI_EXP_LNKSTA_NLW_X1 = 0x0010 # macro +PCI_EXP_LNKSTA_NLW_X2 = 0x0020 # macro +PCI_EXP_LNKSTA_NLW_X4 = 0x0040 # macro +PCI_EXP_LNKSTA_NLW_X8 = 0x0080 # macro +PCI_EXP_LNKSTA_NLW_SHIFT = 4 # macro +PCI_EXP_LNKSTA_LT = 0x0800 # macro +PCI_EXP_LNKSTA_SLC = 0x1000 # macro +PCI_EXP_LNKSTA_DLLLA = 0x2000 # macro +PCI_EXP_LNKSTA_LBMS = 0x4000 # macro +PCI_EXP_LNKSTA_LABS = 0x8000 # macro +PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 = 20 # macro +PCI_EXP_SLTCAP = 20 # macro +PCI_EXP_SLTCAP_ABP = 0x00000001 # macro +PCI_EXP_SLTCAP_PCP = 0x00000002 # macro +PCI_EXP_SLTCAP_MRLSP = 0x00000004 # macro +PCI_EXP_SLTCAP_AIP = 0x00000008 # macro +PCI_EXP_SLTCAP_PIP = 0x00000010 # macro +PCI_EXP_SLTCAP_HPS = 0x00000020 # macro +PCI_EXP_SLTCAP_HPC = 0x00000040 # macro +PCI_EXP_SLTCAP_SPLV = 0x00007f80 # macro +PCI_EXP_SLTCAP_SPLS = 0x00018000 # macro +PCI_EXP_SLTCAP_EIP = 0x00020000 # macro +PCI_EXP_SLTCAP_NCCS = 0x00040000 # macro +PCI_EXP_SLTCAP_PSN = 0xfff80000 # macro +PCI_EXP_SLTCTL = 24 # macro +PCI_EXP_SLTCTL_ABPE = 0x0001 # macro +PCI_EXP_SLTCTL_PFDE = 0x0002 # macro +PCI_EXP_SLTCTL_MRLSCE = 0x0004 # macro +PCI_EXP_SLTCTL_PDCE = 0x0008 # macro +PCI_EXP_SLTCTL_CCIE = 0x0010 # macro +PCI_EXP_SLTCTL_HPIE = 0x0020 # macro +PCI_EXP_SLTCTL_AIC = 0x00c0 # macro +PCI_EXP_SLTCTL_ATTN_IND_SHIFT = 6 # macro +PCI_EXP_SLTCTL_ATTN_IND_ON = 0x0040 # macro +PCI_EXP_SLTCTL_ATTN_IND_BLINK = 0x0080 # macro +PCI_EXP_SLTCTL_ATTN_IND_OFF = 0x00c0 # macro +PCI_EXP_SLTCTL_PIC = 0x0300 # macro +PCI_EXP_SLTCTL_PWR_IND_ON = 0x0100 # macro +PCI_EXP_SLTCTL_PWR_IND_BLINK = 0x0200 # macro +PCI_EXP_SLTCTL_PWR_IND_OFF = 0x0300 # macro +PCI_EXP_SLTCTL_PCC = 0x0400 # macro +PCI_EXP_SLTCTL_PWR_ON = 0x0000 # macro +PCI_EXP_SLTCTL_PWR_OFF = 0x0400 # macro +PCI_EXP_SLTCTL_EIC = 0x0800 # macro +PCI_EXP_SLTCTL_DLLSCE = 0x1000 # macro +PCI_EXP_SLTCTL_IBPD_DISABLE = 0x4000 # macro +PCI_EXP_SLTSTA = 26 # macro +PCI_EXP_SLTSTA_ABP = 0x0001 # macro +PCI_EXP_SLTSTA_PFD = 0x0002 # macro +PCI_EXP_SLTSTA_MRLSC = 0x0004 # macro +PCI_EXP_SLTSTA_PDC = 0x0008 # macro +PCI_EXP_SLTSTA_CC = 0x0010 # macro +PCI_EXP_SLTSTA_MRLSS = 0x0020 # macro +PCI_EXP_SLTSTA_PDS = 0x0040 # macro +PCI_EXP_SLTSTA_EIS = 0x0080 # macro +PCI_EXP_SLTSTA_DLLSC = 0x0100 # macro +PCI_EXP_RTCTL = 28 # macro +PCI_EXP_RTCTL_SECEE = 0x0001 # macro +PCI_EXP_RTCTL_SENFEE = 0x0002 # macro +PCI_EXP_RTCTL_SEFEE = 0x0004 # macro +PCI_EXP_RTCTL_PMEIE = 0x0008 # macro +PCI_EXP_RTCTL_CRSSVE = 0x0010 # macro +PCI_EXP_RTCAP = 30 # macro +PCI_EXP_RTCAP_CRSVIS = 0x0001 # macro +PCI_EXP_RTSTA = 32 # macro +PCI_EXP_RTSTA_PME = 0x00010000 # macro +PCI_EXP_RTSTA_PENDING = 0x00020000 # macro +PCI_EXP_DEVCAP2 = 36 # macro +PCI_EXP_DEVCAP2_COMP_TMOUT_DIS = 0x00000010 # macro +PCI_EXP_DEVCAP2_ARI = 0x00000020 # macro +PCI_EXP_DEVCAP2_ATOMIC_ROUTE = 0x00000040 # macro +PCI_EXP_DEVCAP2_ATOMIC_COMP32 = 0x00000080 # macro +PCI_EXP_DEVCAP2_ATOMIC_COMP64 = 0x00000100 # macro +PCI_EXP_DEVCAP2_ATOMIC_COMP128 = 0x00000200 # macro +PCI_EXP_DEVCAP2_LTR = 0x00000800 # macro +PCI_EXP_DEVCAP2_OBFF_MASK = 0x000c0000 # macro +PCI_EXP_DEVCAP2_OBFF_MSG = 0x00040000 # macro +PCI_EXP_DEVCAP2_OBFF_WAKE = 0x00080000 # macro +PCI_EXP_DEVCAP2_EE_PREFIX = 0x00200000 # macro +PCI_EXP_DEVCTL2 = 40 # macro +PCI_EXP_DEVCTL2_COMP_TIMEOUT = 0x000f # macro +PCI_EXP_DEVCTL2_COMP_TMOUT_DIS = 0x0010 # macro +PCI_EXP_DEVCTL2_ARI = 0x0020 # macro +PCI_EXP_DEVCTL2_ATOMIC_REQ = 0x0040 # macro +PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK = 0x0080 # macro +PCI_EXP_DEVCTL2_IDO_REQ_EN = 0x0100 # macro +PCI_EXP_DEVCTL2_IDO_CMP_EN = 0x0200 # macro +PCI_EXP_DEVCTL2_LTR_EN = 0x0400 # macro +PCI_EXP_DEVCTL2_OBFF_MSGA_EN = 0x2000 # macro +PCI_EXP_DEVCTL2_OBFF_MSGB_EN = 0x4000 # macro +PCI_EXP_DEVCTL2_OBFF_WAKE_EN = 0x6000 # macro +PCI_EXP_DEVSTA2 = 42 # macro +PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 = 44 # macro +PCI_EXP_LNKCAP2 = 44 # macro +PCI_EXP_LNKCAP2_SLS_2_5GB = 0x00000002 # macro +PCI_EXP_LNKCAP2_SLS_5_0GB = 0x00000004 # macro +PCI_EXP_LNKCAP2_SLS_8_0GB = 0x00000008 # macro +PCI_EXP_LNKCAP2_SLS_16_0GB = 0x00000010 # macro +PCI_EXP_LNKCAP2_SLS_32_0GB = 0x00000020 # macro +PCI_EXP_LNKCAP2_SLS_64_0GB = 0x00000040 # macro +PCI_EXP_LNKCAP2_CROSSLINK = 0x00000100 # macro +PCI_EXP_LNKCTL2 = 48 # macro +PCI_EXP_LNKCTL2_TLS = 0x000f # macro +PCI_EXP_LNKCTL2_TLS_2_5GT = 0x0001 # macro +PCI_EXP_LNKCTL2_TLS_5_0GT = 0x0002 # macro +PCI_EXP_LNKCTL2_TLS_8_0GT = 0x0003 # macro +PCI_EXP_LNKCTL2_TLS_16_0GT = 0x0004 # macro +PCI_EXP_LNKCTL2_TLS_32_0GT = 0x0005 # macro +PCI_EXP_LNKCTL2_TLS_64_0GT = 0x0006 # macro +PCI_EXP_LNKCTL2_ENTER_COMP = 0x0010 # macro +PCI_EXP_LNKCTL2_TX_MARGIN = 0x0380 # macro +PCI_EXP_LNKCTL2_HASD = 0x0020 # macro +PCI_EXP_LNKSTA2 = 50 # macro +PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 = 52 # macro +PCI_EXP_SLTCAP2 = 52 # macro +PCI_EXP_SLTCAP2_IBPD = 0x00000001 # macro +PCI_EXP_SLTCTL2 = 56 # macro +PCI_EXP_SLTSTA2 = 58 # macro +def PCI_EXT_CAP_ID(header): # macro + return (header&0x0000ffff) +def PCI_EXT_CAP_VER(header): # macro + return ((header>>16)&0xf) +def PCI_EXT_CAP_NEXT(header): # macro + return ((header>>20)&0xffc) +PCI_EXT_CAP_ID_ERR = 0x01 # macro +PCI_EXT_CAP_ID_VC = 0x02 # macro +PCI_EXT_CAP_ID_DSN = 0x03 # macro +PCI_EXT_CAP_ID_PWR = 0x04 # macro +PCI_EXT_CAP_ID_RCLD = 0x05 # macro +PCI_EXT_CAP_ID_RCILC = 0x06 # macro +PCI_EXT_CAP_ID_RCEC = 0x07 # macro +PCI_EXT_CAP_ID_MFVC = 0x08 # macro +PCI_EXT_CAP_ID_VC9 = 0x09 # macro +PCI_EXT_CAP_ID_RCRB = 0x0A # macro +PCI_EXT_CAP_ID_VNDR = 0x0B # macro +PCI_EXT_CAP_ID_CAC = 0x0C # macro +PCI_EXT_CAP_ID_ACS = 0x0D # macro +PCI_EXT_CAP_ID_ARI = 0x0E # macro +PCI_EXT_CAP_ID_ATS = 0x0F # macro +PCI_EXT_CAP_ID_SRIOV = 0x10 # macro +PCI_EXT_CAP_ID_MRIOV = 0x11 # macro +PCI_EXT_CAP_ID_MCAST = 0x12 # macro +PCI_EXT_CAP_ID_PRI = 0x13 # macro +PCI_EXT_CAP_ID_AMD_XXX = 0x14 # macro +PCI_EXT_CAP_ID_REBAR = 0x15 # macro +PCI_EXT_CAP_ID_DPA = 0x16 # macro +PCI_EXT_CAP_ID_TPH = 0x17 # macro +PCI_EXT_CAP_ID_LTR = 0x18 # macro +PCI_EXT_CAP_ID_SECPCI = 0x19 # macro +PCI_EXT_CAP_ID_PMUX = 0x1A # macro +PCI_EXT_CAP_ID_PASID = 0x1B # macro +PCI_EXT_CAP_ID_DPC = 0x1D # macro +PCI_EXT_CAP_ID_L1SS = 0x1E # macro +PCI_EXT_CAP_ID_PTM = 0x1F # macro +PCI_EXT_CAP_ID_DVSEC = 0x23 # macro +PCI_EXT_CAP_ID_DLF = 0x25 # macro +PCI_EXT_CAP_ID_PL_16GT = 0x26 # macro +PCI_EXT_CAP_ID_MAX = 0x26 # macro +PCI_EXT_CAP_DSN_SIZEOF = 12 # macro +PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF = 40 # macro +PCI_ERR_UNCOR_STATUS = 4 # macro +PCI_ERR_UNC_UND = 0x00000001 # macro +PCI_ERR_UNC_DLP = 0x00000010 # macro +PCI_ERR_UNC_SURPDN = 0x00000020 # macro +PCI_ERR_UNC_POISON_TLP = 0x00001000 # macro +PCI_ERR_UNC_FCP = 0x00002000 # macro +PCI_ERR_UNC_COMP_TIME = 0x00004000 # macro +PCI_ERR_UNC_COMP_ABORT = 0x00008000 # macro +PCI_ERR_UNC_UNX_COMP = 0x00010000 # macro +PCI_ERR_UNC_RX_OVER = 0x00020000 # macro +PCI_ERR_UNC_MALF_TLP = 0x00040000 # macro +PCI_ERR_UNC_ECRC = 0x00080000 # macro +PCI_ERR_UNC_UNSUP = 0x00100000 # macro +PCI_ERR_UNC_ACSV = 0x00200000 # macro +PCI_ERR_UNC_INTN = 0x00400000 # macro +PCI_ERR_UNC_MCBTLP = 0x00800000 # macro +PCI_ERR_UNC_ATOMEG = 0x01000000 # macro +PCI_ERR_UNC_TLPPRE = 0x02000000 # macro +PCI_ERR_UNCOR_MASK = 8 # macro +PCI_ERR_UNCOR_SEVER = 12 # macro +PCI_ERR_COR_STATUS = 16 # macro +PCI_ERR_COR_RCVR = 0x00000001 # macro +PCI_ERR_COR_BAD_TLP = 0x00000040 # macro +PCI_ERR_COR_BAD_DLLP = 0x00000080 # macro +PCI_ERR_COR_REP_ROLL = 0x00000100 # macro +PCI_ERR_COR_REP_TIMER = 0x00001000 # macro +PCI_ERR_COR_ADV_NFAT = 0x00002000 # macro +PCI_ERR_COR_INTERNAL = 0x00004000 # macro +PCI_ERR_COR_LOG_OVER = 0x00008000 # macro +PCI_ERR_COR_MASK = 20 # macro +PCI_ERR_CAP = 24 # macro +def PCI_ERR_CAP_FEP(x): # macro + return ((x)&31) +PCI_ERR_CAP_ECRC_GENC = 0x00000020 # macro +PCI_ERR_CAP_ECRC_GENE = 0x00000040 # macro +PCI_ERR_CAP_ECRC_CHKC = 0x00000080 # macro +PCI_ERR_CAP_ECRC_CHKE = 0x00000100 # macro +PCI_ERR_HEADER_LOG = 28 # macro +PCI_ERR_ROOT_COMMAND = 44 # macro +PCI_ERR_ROOT_CMD_COR_EN = 0x00000001 # macro +PCI_ERR_ROOT_CMD_NONFATAL_EN = 0x00000002 # macro +PCI_ERR_ROOT_CMD_FATAL_EN = 0x00000004 # macro +PCI_ERR_ROOT_STATUS = 48 # macro +PCI_ERR_ROOT_COR_RCV = 0x00000001 # macro +PCI_ERR_ROOT_MULTI_COR_RCV = 0x00000002 # macro +PCI_ERR_ROOT_UNCOR_RCV = 0x00000004 # macro +PCI_ERR_ROOT_MULTI_UNCOR_RCV = 0x00000008 # macro +PCI_ERR_ROOT_FIRST_FATAL = 0x00000010 # macro +PCI_ERR_ROOT_NONFATAL_RCV = 0x00000020 # macro +PCI_ERR_ROOT_FATAL_RCV = 0x00000040 # macro +PCI_ERR_ROOT_AER_IRQ = 0xf8000000 # macro +PCI_ERR_ROOT_ERR_SRC = 52 # macro +PCI_VC_PORT_CAP1 = 4 # macro +PCI_VC_CAP1_EVCC = 0x00000007 # macro +PCI_VC_CAP1_LPEVCC = 0x00000070 # macro +PCI_VC_CAP1_ARB_SIZE = 0x00000c00 # macro +PCI_VC_PORT_CAP2 = 8 # macro +PCI_VC_CAP2_32_PHASE = 0x00000002 # macro +PCI_VC_CAP2_64_PHASE = 0x00000004 # macro +PCI_VC_CAP2_128_PHASE = 0x00000008 # macro +PCI_VC_CAP2_ARB_OFF = 0xff000000 # macro +PCI_VC_PORT_CTRL = 12 # macro +PCI_VC_PORT_CTRL_LOAD_TABLE = 0x00000001 # macro +PCI_VC_PORT_STATUS = 14 # macro +PCI_VC_PORT_STATUS_TABLE = 0x00000001 # macro +PCI_VC_RES_CAP = 16 # macro +PCI_VC_RES_CAP_32_PHASE = 0x00000002 # macro +PCI_VC_RES_CAP_64_PHASE = 0x00000004 # macro +PCI_VC_RES_CAP_128_PHASE = 0x00000008 # macro +PCI_VC_RES_CAP_128_PHASE_TB = 0x00000010 # macro +PCI_VC_RES_CAP_256_PHASE = 0x00000020 # macro +PCI_VC_RES_CAP_ARB_OFF = 0xff000000 # macro +PCI_VC_RES_CTRL = 20 # macro +PCI_VC_RES_CTRL_LOAD_TABLE = 0x00010000 # macro +PCI_VC_RES_CTRL_ARB_SELECT = 0x000e0000 # macro +PCI_VC_RES_CTRL_ID = 0x07000000 # macro +PCI_VC_RES_CTRL_ENABLE = 0x80000000 # macro +PCI_VC_RES_STATUS = 26 # macro +PCI_VC_RES_STATUS_TABLE = 0x00000001 # macro +PCI_VC_RES_STATUS_NEGO = 0x00000002 # macro +PCI_CAP_VC_BASE_SIZEOF = 0x10 # macro +PCI_CAP_VC_PER_VC_SIZEOF = 0x0C # macro +PCI_PWR_DSR = 4 # macro +PCI_PWR_DATA = 8 # macro +def PCI_PWR_DATA_BASE(x): # macro + return ((x)&0xff) +def PCI_PWR_DATA_SCALE(x): # macro + return (((x)>>8)&3) +def PCI_PWR_DATA_PM_SUB(x): # macro + return (((x)>>10)&7) +def PCI_PWR_DATA_PM_STATE(x): # macro + return (((x)>>13)&3) +def PCI_PWR_DATA_TYPE(x): # macro + return (((x)>>15)&7) +def PCI_PWR_DATA_RAIL(x): # macro + return (((x)>>18)&7) +PCI_PWR_CAP = 12 # macro +def PCI_PWR_CAP_BUDGET(x): # macro + return ((x)&1) +PCI_EXT_CAP_PWR_SIZEOF = 16 # macro +PCI_RCEC_RCIEP_BITMAP = 4 # macro +PCI_RCEC_BUSN = 8 # macro +PCI_RCEC_BUSN_REG_VER = 0x02 # macro +def PCI_RCEC_BUSN_NEXT(x): # macro + return (((x)>>8)&0xff) +def PCI_RCEC_BUSN_LAST(x): # macro + return (((x)>>16)&0xff) +PCI_VNDR_HEADER = 4 # macro +def PCI_VNDR_HEADER_ID(x): # macro + return ((x)&0xffff) +def PCI_VNDR_HEADER_REV(x): # macro + return (((x)>>16)&0xf) +def PCI_VNDR_HEADER_LEN(x): # macro + return (((x)>>20)&0xfff) +HT_3BIT_CAP_MASK = 0xE0 # macro +HT_CAPTYPE_SLAVE = 0x00 # macro +HT_CAPTYPE_HOST = 0x20 # macro +HT_5BIT_CAP_MASK = 0xF8 # macro +HT_CAPTYPE_IRQ = 0x80 # macro +HT_CAPTYPE_REMAPPING_40 = 0xA0 # macro +HT_CAPTYPE_REMAPPING_64 = 0xA2 # macro +HT_CAPTYPE_UNITID_CLUMP = 0x90 # macro +HT_CAPTYPE_EXTCONF = 0x98 # macro +HT_CAPTYPE_MSI_MAPPING = 0xA8 # macro +HT_MSI_FLAGS = 0x02 # macro +HT_MSI_FLAGS_ENABLE = 0x1 # macro +HT_MSI_FLAGS_FIXED = 0x2 # macro +HT_MSI_FIXED_ADDR = 0x00000000FEE00000 # macro +HT_MSI_ADDR_LO = 0x04 # macro +HT_MSI_ADDR_LO_MASK = 0xFFF00000 # macro +HT_MSI_ADDR_HI = 0x08 # macro +HT_CAPTYPE_DIRECT_ROUTE = 0xB0 # macro +HT_CAPTYPE_VCSET = 0xB8 # macro +HT_CAPTYPE_ERROR_RETRY = 0xC0 # macro +HT_CAPTYPE_GEN3 = 0xD0 # macro +HT_CAPTYPE_PM = 0xE0 # macro +HT_CAP_SIZEOF_LONG = 28 # macro +HT_CAP_SIZEOF_SHORT = 24 # macro +PCI_ARI_CAP = 0x04 # macro +PCI_ARI_CAP_MFVC = 0x0001 # macro +PCI_ARI_CAP_ACS = 0x0002 # macro +def PCI_ARI_CAP_NFN(x): # macro + return (((x)>>8)&0xff) +PCI_ARI_CTRL = 0x06 # macro +PCI_ARI_CTRL_MFVC = 0x0001 # macro +PCI_ARI_CTRL_ACS = 0x0002 # macro +def PCI_ARI_CTRL_FG(x): # macro + return (((x)>>4)&7) +PCI_EXT_CAP_ARI_SIZEOF = 8 # macro +PCI_ATS_CAP = 0x04 # macro +def PCI_ATS_CAP_QDEP(x): # macro + return ((x)&0x1f) +PCI_ATS_MAX_QDEP = 32 # macro +PCI_ATS_CAP_PAGE_ALIGNED = 0x0020 # macro +PCI_ATS_CTRL = 0x06 # macro +PCI_ATS_CTRL_ENABLE = 0x8000 # macro +def PCI_ATS_CTRL_STU(x): # macro + return ((x)&0x1f) +PCI_ATS_MIN_STU = 12 # macro +PCI_EXT_CAP_ATS_SIZEOF = 8 # macro +PCI_PRI_CTRL = 0x04 # macro +PCI_PRI_CTRL_ENABLE = 0x0001 # macro +PCI_PRI_CTRL_RESET = 0x0002 # macro +PCI_PRI_STATUS = 0x06 # macro +PCI_PRI_STATUS_RF = 0x0001 # macro +PCI_PRI_STATUS_UPRGI = 0x0002 # macro +PCI_PRI_STATUS_STOPPED = 0x0100 # macro +PCI_PRI_STATUS_PASID = 0x8000 # macro +PCI_PRI_MAX_REQ = 0x08 # macro +PCI_PRI_ALLOC_REQ = 0x0c # macro +PCI_EXT_CAP_PRI_SIZEOF = 16 # macro +PCI_PASID_CAP = 0x04 # macro +PCI_PASID_CAP_EXEC = 0x02 # macro +PCI_PASID_CAP_PRIV = 0x04 # macro +PCI_PASID_CTRL = 0x06 # macro +PCI_PASID_CTRL_ENABLE = 0x01 # macro +PCI_PASID_CTRL_EXEC = 0x02 # macro +PCI_PASID_CTRL_PRIV = 0x04 # macro +PCI_EXT_CAP_PASID_SIZEOF = 8 # macro +PCI_SRIOV_CAP = 0x04 # macro +PCI_SRIOV_CAP_VFM = 0x00000001 # macro +def PCI_SRIOV_CAP_INTR(x): # macro + return ((x)>>21) +PCI_SRIOV_CTRL = 0x08 # macro +PCI_SRIOV_CTRL_VFE = 0x0001 # macro +PCI_SRIOV_CTRL_VFM = 0x0002 # macro +PCI_SRIOV_CTRL_INTR = 0x0004 # macro +PCI_SRIOV_CTRL_MSE = 0x0008 # macro +PCI_SRIOV_CTRL_ARI = 0x0010 # macro +PCI_SRIOV_STATUS = 0x0a # macro +PCI_SRIOV_STATUS_VFM = 0x0001 # macro +PCI_SRIOV_INITIAL_VF = 0x0c # macro +PCI_SRIOV_TOTAL_VF = 0x0e # macro +PCI_SRIOV_NUM_VF = 0x10 # macro +PCI_SRIOV_FUNC_LINK = 0x12 # macro +PCI_SRIOV_VF_OFFSET = 0x14 # macro +PCI_SRIOV_VF_STRIDE = 0x16 # macro +PCI_SRIOV_VF_DID = 0x1a # macro +PCI_SRIOV_SUP_PGSIZE = 0x1c # macro +PCI_SRIOV_SYS_PGSIZE = 0x20 # macro +PCI_SRIOV_BAR = 0x24 # macro +PCI_SRIOV_NUM_BARS = 6 # macro +PCI_SRIOV_VFM = 0x3c # macro +def PCI_SRIOV_VFM_BIR(x): # macro + return ((x)&7) +def PCI_SRIOV_VFM_OFFSET(x): # macro + return ((x)&~7) +PCI_SRIOV_VFM_UA = 0x0 # macro +PCI_SRIOV_VFM_MI = 0x1 # macro +PCI_SRIOV_VFM_MO = 0x2 # macro +PCI_SRIOV_VFM_AV = 0x3 # macro +PCI_EXT_CAP_SRIOV_SIZEOF = 64 # macro +PCI_LTR_MAX_SNOOP_LAT = 0x4 # macro +PCI_LTR_MAX_NOSNOOP_LAT = 0x6 # macro +PCI_LTR_VALUE_MASK = 0x000003ff # macro +PCI_LTR_SCALE_MASK = 0x00001c00 # macro +PCI_LTR_SCALE_SHIFT = 10 # macro +PCI_EXT_CAP_LTR_SIZEOF = 8 # macro +PCI_ACS_CAP = 0x04 # macro +PCI_ACS_SV = 0x0001 # macro +PCI_ACS_TB = 0x0002 # macro +PCI_ACS_RR = 0x0004 # macro +PCI_ACS_CR = 0x0008 # macro +PCI_ACS_UF = 0x0010 # macro +PCI_ACS_EC = 0x0020 # macro +PCI_ACS_DT = 0x0040 # macro +PCI_ACS_EGRESS_BITS = 0x05 # macro +PCI_ACS_CTRL = 0x06 # macro +PCI_ACS_EGRESS_CTL_V = 0x08 # macro +PCI_VSEC_HDR = 4 # macro +PCI_VSEC_HDR_LEN_SHIFT = 20 # macro +PCI_SATA_REGS = 4 # macro +PCI_SATA_REGS_MASK = 0xF # macro +PCI_SATA_REGS_INLINE = 0xF # macro +PCI_SATA_SIZEOF_SHORT = 8 # macro +PCI_SATA_SIZEOF_LONG = 16 # macro +PCI_REBAR_CAP = 4 # macro +PCI_REBAR_CAP_SIZES = 0x00FFFFF0 # macro +PCI_REBAR_CTRL = 8 # macro +PCI_REBAR_CTRL_BAR_IDX = 0x00000007 # macro +PCI_REBAR_CTRL_NBAR_MASK = 0x000000E0 # macro +PCI_REBAR_CTRL_NBAR_SHIFT = 5 # macro +PCI_REBAR_CTRL_BAR_SIZE = 0x00001F00 # macro +PCI_REBAR_CTRL_BAR_SHIFT = 8 # macro +PCI_DPA_CAP = 4 # macro +PCI_DPA_CAP_SUBSTATE_MASK = 0x1F # macro +PCI_DPA_BASE_SIZEOF = 16 # macro +PCI_TPH_CAP = 4 # macro +PCI_TPH_CAP_LOC_MASK = 0x600 # macro +PCI_TPH_LOC_NONE = 0x000 # macro +PCI_TPH_LOC_CAP = 0x200 # macro +PCI_TPH_LOC_MSIX = 0x400 # macro +PCI_TPH_CAP_ST_MASK = 0x07FF0000 # macro +PCI_TPH_CAP_ST_SHIFT = 16 # macro +PCI_TPH_BASE_SIZEOF = 12 # macro +PCI_EXP_DPC_CAP = 4 # macro +PCI_EXP_DPC_IRQ = 0x001F # macro +PCI_EXP_DPC_CAP_RP_EXT = 0x0020 # macro +PCI_EXP_DPC_CAP_POISONED_TLP = 0x0040 # macro +PCI_EXP_DPC_CAP_SW_TRIGGER = 0x0080 # macro +PCI_EXP_DPC_RP_PIO_LOG_SIZE = 0x0F00 # macro +PCI_EXP_DPC_CAP_DL_ACTIVE = 0x1000 # macro +PCI_EXP_DPC_CTL = 6 # macro +PCI_EXP_DPC_CTL_EN_FATAL = 0x0001 # macro +PCI_EXP_DPC_CTL_EN_NONFATAL = 0x0002 # macro +PCI_EXP_DPC_CTL_INT_EN = 0x0008 # macro +PCI_EXP_DPC_STATUS = 8 # macro +PCI_EXP_DPC_STATUS_TRIGGER = 0x0001 # macro +PCI_EXP_DPC_STATUS_TRIGGER_RSN = 0x0006 # macro +PCI_EXP_DPC_STATUS_INTERRUPT = 0x0008 # macro +PCI_EXP_DPC_RP_BUSY = 0x0010 # macro +PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT = 0x0060 # macro +PCI_EXP_DPC_SOURCE_ID = 10 # macro +PCI_EXP_DPC_RP_PIO_STATUS = 0x0C # macro +PCI_EXP_DPC_RP_PIO_MASK = 0x10 # macro +PCI_EXP_DPC_RP_PIO_SEVERITY = 0x14 # macro +PCI_EXP_DPC_RP_PIO_SYSERROR = 0x18 # macro +PCI_EXP_DPC_RP_PIO_EXCEPTION = 0x1C # macro +PCI_EXP_DPC_RP_PIO_HEADER_LOG = 0x20 # macro +PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG = 0x30 # macro +PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG = 0x34 # macro +PCI_PTM_CAP = 0x04 # macro +PCI_PTM_CAP_REQ = 0x00000001 # macro +PCI_PTM_CAP_ROOT = 0x00000004 # macro +PCI_PTM_GRANULARITY_MASK = 0x0000FF00 # macro +PCI_PTM_CTRL = 0x08 # macro +PCI_PTM_CTRL_ENABLE = 0x00000001 # macro +PCI_PTM_CTRL_ROOT = 0x00000002 # macro +PCI_L1SS_CAP = 0x04 # macro +PCI_L1SS_CAP_PCIPM_L1_2 = 0x00000001 # macro +PCI_L1SS_CAP_PCIPM_L1_1 = 0x00000002 # macro +PCI_L1SS_CAP_ASPM_L1_2 = 0x00000004 # macro +PCI_L1SS_CAP_ASPM_L1_1 = 0x00000008 # macro +PCI_L1SS_CAP_L1_PM_SS = 0x00000010 # macro +PCI_L1SS_CAP_CM_RESTORE_TIME = 0x0000ff00 # macro +PCI_L1SS_CAP_P_PWR_ON_SCALE = 0x00030000 # macro +PCI_L1SS_CAP_P_PWR_ON_VALUE = 0x00f80000 # macro +PCI_L1SS_CTL1 = 0x08 # macro +PCI_L1SS_CTL1_PCIPM_L1_2 = 0x00000001 # macro +PCI_L1SS_CTL1_PCIPM_L1_1 = 0x00000002 # macro +PCI_L1SS_CTL1_ASPM_L1_2 = 0x00000004 # macro +PCI_L1SS_CTL1_ASPM_L1_1 = 0x00000008 # macro +PCI_L1SS_CTL1_L1_2_MASK = 0x00000005 # macro +PCI_L1SS_CTL1_L1SS_MASK = 0x0000000f # macro +PCI_L1SS_CTL1_CM_RESTORE_TIME = 0x0000ff00 # macro +PCI_L1SS_CTL1_LTR_L12_TH_VALUE = 0x03ff0000 # macro +PCI_L1SS_CTL1_LTR_L12_TH_SCALE = 0xe0000000 # macro +PCI_L1SS_CTL2 = 0x0c # macro +PCI_DVSEC_HEADER1 = 0x4 # macro +PCI_DVSEC_HEADER2 = 0x8 # macro +PCI_DLF_CAP = 0x04 # macro +PCI_DLF_EXCHANGE_ENABLE = 0x80000000 # macro +PCI_PL_16GT_LE_CTRL = 0x20 # macro +PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK = 0x0000000F # macro +PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK = 0x000000F0 # macro +PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT = 4 # macro +struct_pci_device._pack_ = 1 # source:False +struct_pci_device._fields_ = [ + ('domain_16', ctypes.c_uint16), + ('bus', ctypes.c_ubyte), + ('dev', ctypes.c_ubyte), + ('func', ctypes.c_ubyte), + ('PADDING_0', ctypes.c_ubyte), + ('vendor_id', ctypes.c_uint16), + ('device_id', ctypes.c_uint16), + ('subvendor_id', ctypes.c_uint16), + ('subdevice_id', ctypes.c_uint16), + ('PADDING_1', ctypes.c_ubyte * 2), + ('device_class', ctypes.c_uint32), + ('revision', ctypes.c_ubyte), + ('PADDING_2', ctypes.c_ubyte * 3), + ('regions', struct_pci_mem_region * 6), + ('rom_size', ctypes.c_uint64), + ('irq', ctypes.c_int32), + ('PADDING_3', ctypes.c_ubyte * 4), + ('user_data', ctypes.c_int64), + ('vgaarb_rsrc', ctypes.c_int32), + ('domain', ctypes.c_uint32), +] + +struct_pci_agp_info._pack_ = 1 # source:False +struct_pci_agp_info._fields_ = [ + ('config_offset', ctypes.c_uint32), + ('major_version', ctypes.c_ubyte), + ('minor_version', ctypes.c_ubyte), + ('rates', ctypes.c_ubyte), + ('fast_writes', ctypes.c_uint32, 1), + ('addr64', ctypes.c_uint32, 1), + ('htrans', ctypes.c_uint32, 1), + ('gart64', ctypes.c_uint32, 1), + ('coherent', ctypes.c_uint32, 1), + ('sideband', ctypes.c_uint32, 1), + ('isochronus', ctypes.c_uint32, 1), + ('PADDING_0', ctypes.c_uint8, 1), + ('async_req_size', ctypes.c_uint32, 8), + ('calibration_cycle_timing', ctypes.c_ubyte), + ('max_requests', ctypes.c_ubyte), + ('PADDING_1', ctypes.c_ubyte), +] + +struct_pci_bridge_info._pack_ = 1 # source:False +struct_pci_bridge_info._fields_ = [ + ('primary_bus', ctypes.c_ubyte), + ('secondary_bus', ctypes.c_ubyte), + ('subordinate_bus', ctypes.c_ubyte), + ('secondary_latency_timer', ctypes.c_ubyte), + ('io_type', ctypes.c_ubyte), + ('mem_type', ctypes.c_ubyte), + ('prefetch_mem_type', ctypes.c_ubyte), + ('PADDING_0', ctypes.c_ubyte), + ('secondary_status', ctypes.c_uint16), + ('bridge_control', ctypes.c_uint16), + ('io_base', ctypes.c_uint32), + ('io_limit', ctypes.c_uint32), + ('mem_base', ctypes.c_uint32), + ('mem_limit', ctypes.c_uint32), + ('PADDING_1', ctypes.c_ubyte * 4), + ('prefetch_mem_base', ctypes.c_uint64), + ('prefetch_mem_limit', ctypes.c_uint64), +] + +struct_pci_pcmcia_bridge_info._pack_ = 1 # source:False +struct_pci_pcmcia_bridge_info._fields_ = [ + ('primary_bus', ctypes.c_ubyte), + ('card_bus', ctypes.c_ubyte), + ('subordinate_bus', ctypes.c_ubyte), + ('cardbus_latency_timer', ctypes.c_ubyte), + ('secondary_status', ctypes.c_uint16), + ('bridge_control', ctypes.c_uint16), + ('io', struct_pci_pcmcia_bridge_info_0 * 2), + ('mem', struct_pci_pcmcia_bridge_info_1 * 2), +] + +struct_pci_slot_match._pack_ = 1 # source:False +struct_pci_slot_match._fields_ = [ + ('domain', ctypes.c_uint32), + ('bus', ctypes.c_uint32), + ('dev', ctypes.c_uint32), + ('func', ctypes.c_uint32), + ('match_data', ctypes.c_int64), +] + +struct_pci_id_match._pack_ = 1 # source:False +struct_pci_id_match._fields_ = [ + ('vendor_id', ctypes.c_uint32), + ('device_id', ctypes.c_uint32), + ('subvendor_id', ctypes.c_uint32), + ('subdevice_id', ctypes.c_uint32), + ('device_class', ctypes.c_uint32), + ('device_class_mask', ctypes.c_uint32), + ('match_data', ctypes.c_int64), +] + +__all__ = \ + ['HT_3BIT_CAP_MASK', 'HT_5BIT_CAP_MASK', + 'HT_CAPTYPE_DIRECT_ROUTE', 'HT_CAPTYPE_ERROR_RETRY', + 'HT_CAPTYPE_EXTCONF', 'HT_CAPTYPE_GEN3', 'HT_CAPTYPE_HOST', + 'HT_CAPTYPE_IRQ', 'HT_CAPTYPE_MSI_MAPPING', 'HT_CAPTYPE_PM', + 'HT_CAPTYPE_REMAPPING_40', 'HT_CAPTYPE_REMAPPING_64', + 'HT_CAPTYPE_SLAVE', 'HT_CAPTYPE_UNITID_CLUMP', 'HT_CAPTYPE_VCSET', + 'HT_CAP_SIZEOF_LONG', 'HT_CAP_SIZEOF_SHORT', 'HT_MSI_ADDR_HI', + 'HT_MSI_ADDR_LO', 'HT_MSI_ADDR_LO_MASK', 'HT_MSI_FIXED_ADDR', + 'HT_MSI_FLAGS', 'HT_MSI_FLAGS_ENABLE', 'HT_MSI_FLAGS_FIXED', + 'LINUX_PCI_REGS_H', 'PCIACCESS_H', 'PCI_ACS_CAP', 'PCI_ACS_CR', + 'PCI_ACS_CTRL', 'PCI_ACS_DT', 'PCI_ACS_EC', 'PCI_ACS_EGRESS_BITS', + 'PCI_ACS_EGRESS_CTL_V', 'PCI_ACS_RR', 'PCI_ACS_SV', 'PCI_ACS_TB', + 'PCI_ACS_UF', 'PCI_AF_CAP', 'PCI_AF_CAP_FLR', 'PCI_AF_CAP_TP', + 'PCI_AF_CTRL', 'PCI_AF_CTRL_FLR', 'PCI_AF_LENGTH', + 'PCI_AF_STATUS', 'PCI_AF_STATUS_TP', 'PCI_AGP_COMMAND', + 'PCI_AGP_COMMAND_64BIT', 'PCI_AGP_COMMAND_AGP', + 'PCI_AGP_COMMAND_FW', 'PCI_AGP_COMMAND_RATE1', + 'PCI_AGP_COMMAND_RATE2', 'PCI_AGP_COMMAND_RATE4', + 'PCI_AGP_COMMAND_RQ_MASK', 'PCI_AGP_COMMAND_SBA', 'PCI_AGP_RFU', + 'PCI_AGP_SIZEOF', 'PCI_AGP_STATUS', 'PCI_AGP_STATUS_64BIT', + 'PCI_AGP_STATUS_FW', 'PCI_AGP_STATUS_RATE1', + 'PCI_AGP_STATUS_RATE2', 'PCI_AGP_STATUS_RATE4', + 'PCI_AGP_STATUS_RQ_MASK', 'PCI_AGP_STATUS_SBA', 'PCI_AGP_VERSION', + 'PCI_ARI_CAP', 'PCI_ARI_CAP_ACS', 'PCI_ARI_CAP_MFVC', + 'PCI_ARI_CTRL', 'PCI_ARI_CTRL_ACS', 'PCI_ARI_CTRL_MFVC', + 'PCI_ATS_CAP', 'PCI_ATS_CAP_PAGE_ALIGNED', 'PCI_ATS_CTRL', + 'PCI_ATS_CTRL_ENABLE', 'PCI_ATS_MAX_QDEP', 'PCI_ATS_MIN_STU', + 'PCI_BASE_ADDRESS_0', 'PCI_BASE_ADDRESS_1', 'PCI_BASE_ADDRESS_2', + 'PCI_BASE_ADDRESS_3', 'PCI_BASE_ADDRESS_4', 'PCI_BASE_ADDRESS_5', + 'PCI_BASE_ADDRESS_IO_MASK', 'PCI_BASE_ADDRESS_MEM_MASK', + 'PCI_BASE_ADDRESS_MEM_PREFETCH', 'PCI_BASE_ADDRESS_MEM_TYPE_1M', + 'PCI_BASE_ADDRESS_MEM_TYPE_32', 'PCI_BASE_ADDRESS_MEM_TYPE_64', + 'PCI_BASE_ADDRESS_MEM_TYPE_MASK', 'PCI_BASE_ADDRESS_SPACE', + 'PCI_BASE_ADDRESS_SPACE_IO', 'PCI_BASE_ADDRESS_SPACE_MEMORY', + 'PCI_BIST', 'PCI_BIST_CAPABLE', 'PCI_BIST_CODE_MASK', + 'PCI_BIST_START', 'PCI_BRIDGE_CONTROL', + 'PCI_BRIDGE_CTL_BUS_RESET', 'PCI_BRIDGE_CTL_FAST_BACK', + 'PCI_BRIDGE_CTL_ISA', 'PCI_BRIDGE_CTL_MASTER_ABORT', + 'PCI_BRIDGE_CTL_PARITY', 'PCI_BRIDGE_CTL_SERR', + 'PCI_BRIDGE_CTL_VGA', 'PCI_CACHE_LINE_SIZE', + 'PCI_CAPABILITY_LIST', 'PCI_CAP_AF_SIZEOF', + 'PCI_CAP_EXP_ENDPOINT_SIZEOF_V1', + 'PCI_CAP_EXP_ENDPOINT_SIZEOF_V2', + 'PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1', + 'PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2', 'PCI_CAP_FLAGS', + 'PCI_CAP_ID_AF', 'PCI_CAP_ID_AGP', 'PCI_CAP_ID_AGP3', + 'PCI_CAP_ID_CCRC', 'PCI_CAP_ID_CHSWP', 'PCI_CAP_ID_DBG', + 'PCI_CAP_ID_EA', 'PCI_CAP_ID_EXP', 'PCI_CAP_ID_HT', + 'PCI_CAP_ID_MAX', 'PCI_CAP_ID_MSI', 'PCI_CAP_ID_MSIX', + 'PCI_CAP_ID_PCIX', 'PCI_CAP_ID_PM', 'PCI_CAP_ID_SATA', + 'PCI_CAP_ID_SECDEV', 'PCI_CAP_ID_SHPC', 'PCI_CAP_ID_SLOTID', + 'PCI_CAP_ID_SSVID', 'PCI_CAP_ID_VNDR', 'PCI_CAP_ID_VPD', + 'PCI_CAP_LIST_ID', 'PCI_CAP_LIST_NEXT', 'PCI_CAP_MSIX_SIZEOF', + 'PCI_CAP_PCIX_SIZEOF_V0', 'PCI_CAP_PCIX_SIZEOF_V1', + 'PCI_CAP_PCIX_SIZEOF_V2', 'PCI_CAP_SIZEOF', + 'PCI_CAP_VC_BASE_SIZEOF', 'PCI_CAP_VC_PER_VC_SIZEOF', + 'PCI_CAP_VPD_SIZEOF', 'PCI_CARDBUS_CIS', 'PCI_CB_BRIDGE_CONTROL', + 'PCI_CB_BRIDGE_CTL_16BIT_INT', 'PCI_CB_BRIDGE_CTL_CB_RESET', + 'PCI_CB_BRIDGE_CTL_ISA', 'PCI_CB_BRIDGE_CTL_MASTER_ABORT', + 'PCI_CB_BRIDGE_CTL_PARITY', 'PCI_CB_BRIDGE_CTL_POST_WRITES', + 'PCI_CB_BRIDGE_CTL_PREFETCH_MEM0', + 'PCI_CB_BRIDGE_CTL_PREFETCH_MEM1', 'PCI_CB_BRIDGE_CTL_SERR', + 'PCI_CB_BRIDGE_CTL_VGA', 'PCI_CB_CAPABILITY_LIST', + 'PCI_CB_CARD_BUS', 'PCI_CB_IO_BASE_0', 'PCI_CB_IO_BASE_0_HI', + 'PCI_CB_IO_BASE_1', 'PCI_CB_IO_BASE_1_HI', 'PCI_CB_IO_LIMIT_0', + 'PCI_CB_IO_LIMIT_0_HI', 'PCI_CB_IO_LIMIT_1', + 'PCI_CB_IO_LIMIT_1_HI', 'PCI_CB_IO_RANGE_MASK', + 'PCI_CB_LATENCY_TIMER', 'PCI_CB_LEGACY_MODE_BASE', + 'PCI_CB_MEMORY_BASE_0', 'PCI_CB_MEMORY_BASE_1', + 'PCI_CB_MEMORY_LIMIT_0', 'PCI_CB_MEMORY_LIMIT_1', + 'PCI_CB_PRIMARY_BUS', 'PCI_CB_SEC_STATUS', + 'PCI_CB_SUBORDINATE_BUS', 'PCI_CB_SUBSYSTEM_ID', + 'PCI_CB_SUBSYSTEM_VENDOR_ID', 'PCI_CFG_SPACE_EXP_SIZE', + 'PCI_CFG_SPACE_SIZE', 'PCI_CHSWP_CSR', 'PCI_CHSWP_DHA', + 'PCI_CHSWP_EIM', 'PCI_CHSWP_EXT', 'PCI_CHSWP_INS', + 'PCI_CHSWP_LOO', 'PCI_CHSWP_PI', 'PCI_CHSWP_PIE', + 'PCI_CLASS_DEVICE', 'PCI_CLASS_PROG', 'PCI_CLASS_REVISION', + 'PCI_COMMAND', 'PCI_COMMAND_FAST_BACK', + 'PCI_COMMAND_INTX_DISABLE', 'PCI_COMMAND_INVALIDATE', + 'PCI_COMMAND_IO', 'PCI_COMMAND_MASTER', 'PCI_COMMAND_MEMORY', + 'PCI_COMMAND_PARITY', 'PCI_COMMAND_SERR', 'PCI_COMMAND_SPECIAL', + 'PCI_COMMAND_VGA_PALETTE', 'PCI_COMMAND_WAIT', 'PCI_DEVICE_ID', + 'PCI_DEV_MAP_FLAG_CACHABLE', 'PCI_DEV_MAP_FLAG_WRITABLE', + 'PCI_DEV_MAP_FLAG_WRITE_COMBINE', 'PCI_DLF_CAP', + 'PCI_DLF_EXCHANGE_ENABLE', 'PCI_DPA_BASE_SIZEOF', 'PCI_DPA_CAP', + 'PCI_DPA_CAP_SUBSTATE_MASK', 'PCI_DVSEC_HEADER1', + 'PCI_DVSEC_HEADER2', 'PCI_EA_BASE', 'PCI_EA_BEI', + 'PCI_EA_BEI_BAR0', 'PCI_EA_BEI_BAR5', 'PCI_EA_BEI_BRIDGE', + 'PCI_EA_BEI_ENI', 'PCI_EA_BEI_RESERVED', 'PCI_EA_BEI_ROM', + 'PCI_EA_BEI_VF_BAR0', 'PCI_EA_BEI_VF_BAR5', 'PCI_EA_ENABLE', + 'PCI_EA_ES', 'PCI_EA_FIELD_MASK', 'PCI_EA_FIRST_ENT', + 'PCI_EA_FIRST_ENT_BRIDGE', 'PCI_EA_IS_64', 'PCI_EA_MAX_OFFSET', + 'PCI_EA_NUM_ENT', 'PCI_EA_NUM_ENT_MASK', 'PCI_EA_PP', + 'PCI_EA_P_BRIDGE_IO', 'PCI_EA_P_BRIDGE_MEM', + 'PCI_EA_P_BRIDGE_MEM_PREFETCH', 'PCI_EA_P_IO', + 'PCI_EA_P_IO_RESERVED', 'PCI_EA_P_MEM', 'PCI_EA_P_MEM_PREFETCH', + 'PCI_EA_P_MEM_RESERVED', 'PCI_EA_P_UNAVAILABLE', + 'PCI_EA_P_VF_MEM', 'PCI_EA_P_VF_MEM_PREFETCH', + 'PCI_EA_SEC_BUS_MASK', 'PCI_EA_SP', 'PCI_EA_SUB_BUS_MASK', + 'PCI_EA_SUB_BUS_SHIFT', 'PCI_EA_WRITABLE', 'PCI_ERR_CAP', + 'PCI_ERR_CAP_ECRC_CHKC', 'PCI_ERR_CAP_ECRC_CHKE', + 'PCI_ERR_CAP_ECRC_GENC', 'PCI_ERR_CAP_ECRC_GENE', + 'PCI_ERR_COR_ADV_NFAT', 'PCI_ERR_COR_BAD_DLLP', + 'PCI_ERR_COR_BAD_TLP', 'PCI_ERR_COR_INTERNAL', + 'PCI_ERR_COR_LOG_OVER', 'PCI_ERR_COR_MASK', 'PCI_ERR_COR_RCVR', + 'PCI_ERR_COR_REP_ROLL', 'PCI_ERR_COR_REP_TIMER', + 'PCI_ERR_COR_STATUS', 'PCI_ERR_HEADER_LOG', + 'PCI_ERR_ROOT_AER_IRQ', 'PCI_ERR_ROOT_CMD_COR_EN', + 'PCI_ERR_ROOT_CMD_FATAL_EN', 'PCI_ERR_ROOT_CMD_NONFATAL_EN', + 'PCI_ERR_ROOT_COMMAND', 'PCI_ERR_ROOT_COR_RCV', + 'PCI_ERR_ROOT_ERR_SRC', 'PCI_ERR_ROOT_FATAL_RCV', + 'PCI_ERR_ROOT_FIRST_FATAL', 'PCI_ERR_ROOT_MULTI_COR_RCV', + 'PCI_ERR_ROOT_MULTI_UNCOR_RCV', 'PCI_ERR_ROOT_NONFATAL_RCV', + 'PCI_ERR_ROOT_STATUS', 'PCI_ERR_ROOT_UNCOR_RCV', + 'PCI_ERR_UNCOR_MASK', 'PCI_ERR_UNCOR_SEVER', + 'PCI_ERR_UNCOR_STATUS', 'PCI_ERR_UNC_ACSV', 'PCI_ERR_UNC_ATOMEG', + 'PCI_ERR_UNC_COMP_ABORT', 'PCI_ERR_UNC_COMP_TIME', + 'PCI_ERR_UNC_DLP', 'PCI_ERR_UNC_ECRC', 'PCI_ERR_UNC_FCP', + 'PCI_ERR_UNC_INTN', 'PCI_ERR_UNC_MALF_TLP', 'PCI_ERR_UNC_MCBTLP', + 'PCI_ERR_UNC_POISON_TLP', 'PCI_ERR_UNC_RX_OVER', + 'PCI_ERR_UNC_SURPDN', 'PCI_ERR_UNC_TLPPRE', 'PCI_ERR_UNC_UND', + 'PCI_ERR_UNC_UNSUP', 'PCI_ERR_UNC_UNX_COMP', 'PCI_EXP_DEVCAP', + 'PCI_EXP_DEVCAP2', 'PCI_EXP_DEVCAP2_ARI', + 'PCI_EXP_DEVCAP2_ATOMIC_COMP128', 'PCI_EXP_DEVCAP2_ATOMIC_COMP32', + 'PCI_EXP_DEVCAP2_ATOMIC_COMP64', 'PCI_EXP_DEVCAP2_ATOMIC_ROUTE', + 'PCI_EXP_DEVCAP2_COMP_TMOUT_DIS', 'PCI_EXP_DEVCAP2_EE_PREFIX', + 'PCI_EXP_DEVCAP2_LTR', 'PCI_EXP_DEVCAP2_OBFF_MASK', + 'PCI_EXP_DEVCAP2_OBFF_MSG', 'PCI_EXP_DEVCAP2_OBFF_WAKE', + 'PCI_EXP_DEVCAP_ATN_BUT', 'PCI_EXP_DEVCAP_ATN_IND', + 'PCI_EXP_DEVCAP_EXT_TAG', 'PCI_EXP_DEVCAP_FLR', + 'PCI_EXP_DEVCAP_L0S', 'PCI_EXP_DEVCAP_L1', + 'PCI_EXP_DEVCAP_PAYLOAD', 'PCI_EXP_DEVCAP_PHANTOM', + 'PCI_EXP_DEVCAP_PWR_IND', 'PCI_EXP_DEVCAP_PWR_SCL', + 'PCI_EXP_DEVCAP_PWR_VAL', 'PCI_EXP_DEVCAP_RBER', 'PCI_EXP_DEVCTL', + 'PCI_EXP_DEVCTL2', 'PCI_EXP_DEVCTL2_ARI', + 'PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK', + 'PCI_EXP_DEVCTL2_ATOMIC_REQ', 'PCI_EXP_DEVCTL2_COMP_TIMEOUT', + 'PCI_EXP_DEVCTL2_COMP_TMOUT_DIS', 'PCI_EXP_DEVCTL2_IDO_CMP_EN', + 'PCI_EXP_DEVCTL2_IDO_REQ_EN', 'PCI_EXP_DEVCTL2_LTR_EN', + 'PCI_EXP_DEVCTL2_OBFF_MSGA_EN', 'PCI_EXP_DEVCTL2_OBFF_MSGB_EN', + 'PCI_EXP_DEVCTL2_OBFF_WAKE_EN', 'PCI_EXP_DEVCTL_AUX_PME', + 'PCI_EXP_DEVCTL_BCR_FLR', 'PCI_EXP_DEVCTL_CERE', + 'PCI_EXP_DEVCTL_EXT_TAG', 'PCI_EXP_DEVCTL_FERE', + 'PCI_EXP_DEVCTL_NFERE', 'PCI_EXP_DEVCTL_NOSNOOP_EN', + 'PCI_EXP_DEVCTL_PAYLOAD', 'PCI_EXP_DEVCTL_PAYLOAD_1024B', + 'PCI_EXP_DEVCTL_PAYLOAD_128B', 'PCI_EXP_DEVCTL_PAYLOAD_2048B', + 'PCI_EXP_DEVCTL_PAYLOAD_256B', 'PCI_EXP_DEVCTL_PAYLOAD_4096B', + 'PCI_EXP_DEVCTL_PAYLOAD_512B', 'PCI_EXP_DEVCTL_PHANTOM', + 'PCI_EXP_DEVCTL_READRQ', 'PCI_EXP_DEVCTL_READRQ_1024B', + 'PCI_EXP_DEVCTL_READRQ_128B', 'PCI_EXP_DEVCTL_READRQ_2048B', + 'PCI_EXP_DEVCTL_READRQ_256B', 'PCI_EXP_DEVCTL_READRQ_4096B', + 'PCI_EXP_DEVCTL_READRQ_512B', 'PCI_EXP_DEVCTL_RELAX_EN', + 'PCI_EXP_DEVCTL_URRE', 'PCI_EXP_DEVSTA', 'PCI_EXP_DEVSTA2', + 'PCI_EXP_DEVSTA_AUXPD', 'PCI_EXP_DEVSTA_CED', + 'PCI_EXP_DEVSTA_FED', 'PCI_EXP_DEVSTA_NFED', + 'PCI_EXP_DEVSTA_TRPND', 'PCI_EXP_DEVSTA_URD', 'PCI_EXP_DPC_CAP', + 'PCI_EXP_DPC_CAP_DL_ACTIVE', 'PCI_EXP_DPC_CAP_POISONED_TLP', + 'PCI_EXP_DPC_CAP_RP_EXT', 'PCI_EXP_DPC_CAP_SW_TRIGGER', + 'PCI_EXP_DPC_CTL', 'PCI_EXP_DPC_CTL_EN_FATAL', + 'PCI_EXP_DPC_CTL_EN_NONFATAL', 'PCI_EXP_DPC_CTL_INT_EN', + 'PCI_EXP_DPC_IRQ', 'PCI_EXP_DPC_RP_BUSY', + 'PCI_EXP_DPC_RP_PIO_EXCEPTION', 'PCI_EXP_DPC_RP_PIO_HEADER_LOG', + 'PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG', 'PCI_EXP_DPC_RP_PIO_LOG_SIZE', + 'PCI_EXP_DPC_RP_PIO_MASK', 'PCI_EXP_DPC_RP_PIO_SEVERITY', + 'PCI_EXP_DPC_RP_PIO_STATUS', 'PCI_EXP_DPC_RP_PIO_SYSERROR', + 'PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG', 'PCI_EXP_DPC_SOURCE_ID', + 'PCI_EXP_DPC_STATUS', 'PCI_EXP_DPC_STATUS_INTERRUPT', + 'PCI_EXP_DPC_STATUS_TRIGGER', 'PCI_EXP_DPC_STATUS_TRIGGER_RSN', + 'PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT', 'PCI_EXP_FLAGS', + 'PCI_EXP_FLAGS_IRQ', 'PCI_EXP_FLAGS_SLOT', 'PCI_EXP_FLAGS_TYPE', + 'PCI_EXP_FLAGS_VERS', 'PCI_EXP_LNKCAP', 'PCI_EXP_LNKCAP2', + 'PCI_EXP_LNKCAP2_CROSSLINK', 'PCI_EXP_LNKCAP2_SLS_16_0GB', + 'PCI_EXP_LNKCAP2_SLS_2_5GB', 'PCI_EXP_LNKCAP2_SLS_32_0GB', + 'PCI_EXP_LNKCAP2_SLS_5_0GB', 'PCI_EXP_LNKCAP2_SLS_64_0GB', + 'PCI_EXP_LNKCAP2_SLS_8_0GB', 'PCI_EXP_LNKCAP_ASPMS', + 'PCI_EXP_LNKCAP_ASPM_L0S', 'PCI_EXP_LNKCAP_ASPM_L1', + 'PCI_EXP_LNKCAP_CLKPM', 'PCI_EXP_LNKCAP_DLLLARC', + 'PCI_EXP_LNKCAP_L0SEL', 'PCI_EXP_LNKCAP_L1EL', + 'PCI_EXP_LNKCAP_LBNC', 'PCI_EXP_LNKCAP_MLW', 'PCI_EXP_LNKCAP_PN', + 'PCI_EXP_LNKCAP_SDERC', 'PCI_EXP_LNKCAP_SLS', + 'PCI_EXP_LNKCAP_SLS_16_0GB', 'PCI_EXP_LNKCAP_SLS_2_5GB', + 'PCI_EXP_LNKCAP_SLS_32_0GB', 'PCI_EXP_LNKCAP_SLS_5_0GB', + 'PCI_EXP_LNKCAP_SLS_64_0GB', 'PCI_EXP_LNKCAP_SLS_8_0GB', + 'PCI_EXP_LNKCTL', 'PCI_EXP_LNKCTL2', 'PCI_EXP_LNKCTL2_ENTER_COMP', + 'PCI_EXP_LNKCTL2_HASD', 'PCI_EXP_LNKCTL2_TLS', + 'PCI_EXP_LNKCTL2_TLS_16_0GT', 'PCI_EXP_LNKCTL2_TLS_2_5GT', + 'PCI_EXP_LNKCTL2_TLS_32_0GT', 'PCI_EXP_LNKCTL2_TLS_5_0GT', + 'PCI_EXP_LNKCTL2_TLS_64_0GT', 'PCI_EXP_LNKCTL2_TLS_8_0GT', + 'PCI_EXP_LNKCTL2_TX_MARGIN', 'PCI_EXP_LNKCTL_ASPMC', + 'PCI_EXP_LNKCTL_ASPM_L0S', 'PCI_EXP_LNKCTL_ASPM_L1', + 'PCI_EXP_LNKCTL_CCC', 'PCI_EXP_LNKCTL_CLKREQ_EN', + 'PCI_EXP_LNKCTL_ES', 'PCI_EXP_LNKCTL_HAWD', + 'PCI_EXP_LNKCTL_LABIE', 'PCI_EXP_LNKCTL_LBMIE', + 'PCI_EXP_LNKCTL_LD', 'PCI_EXP_LNKCTL_RCB', 'PCI_EXP_LNKCTL_RL', + 'PCI_EXP_LNKSTA', 'PCI_EXP_LNKSTA2', 'PCI_EXP_LNKSTA_CLS', + 'PCI_EXP_LNKSTA_CLS_16_0GB', 'PCI_EXP_LNKSTA_CLS_2_5GB', + 'PCI_EXP_LNKSTA_CLS_32_0GB', 'PCI_EXP_LNKSTA_CLS_5_0GB', + 'PCI_EXP_LNKSTA_CLS_64_0GB', 'PCI_EXP_LNKSTA_CLS_8_0GB', + 'PCI_EXP_LNKSTA_DLLLA', 'PCI_EXP_LNKSTA_LABS', + 'PCI_EXP_LNKSTA_LBMS', 'PCI_EXP_LNKSTA_LT', 'PCI_EXP_LNKSTA_NLW', + 'PCI_EXP_LNKSTA_NLW_SHIFT', 'PCI_EXP_LNKSTA_NLW_X1', + 'PCI_EXP_LNKSTA_NLW_X2', 'PCI_EXP_LNKSTA_NLW_X4', + 'PCI_EXP_LNKSTA_NLW_X8', 'PCI_EXP_LNKSTA_SLC', 'PCI_EXP_RTCAP', + 'PCI_EXP_RTCAP_CRSVIS', 'PCI_EXP_RTCTL', 'PCI_EXP_RTCTL_CRSSVE', + 'PCI_EXP_RTCTL_PMEIE', 'PCI_EXP_RTCTL_SECEE', + 'PCI_EXP_RTCTL_SEFEE', 'PCI_EXP_RTCTL_SENFEE', 'PCI_EXP_RTSTA', + 'PCI_EXP_RTSTA_PENDING', 'PCI_EXP_RTSTA_PME', 'PCI_EXP_SLTCAP', + 'PCI_EXP_SLTCAP2', 'PCI_EXP_SLTCAP2_IBPD', 'PCI_EXP_SLTCAP_ABP', + 'PCI_EXP_SLTCAP_AIP', 'PCI_EXP_SLTCAP_EIP', 'PCI_EXP_SLTCAP_HPC', + 'PCI_EXP_SLTCAP_HPS', 'PCI_EXP_SLTCAP_MRLSP', + 'PCI_EXP_SLTCAP_NCCS', 'PCI_EXP_SLTCAP_PCP', 'PCI_EXP_SLTCAP_PIP', + 'PCI_EXP_SLTCAP_PSN', 'PCI_EXP_SLTCAP_SPLS', + 'PCI_EXP_SLTCAP_SPLV', 'PCI_EXP_SLTCTL', 'PCI_EXP_SLTCTL2', + 'PCI_EXP_SLTCTL_ABPE', 'PCI_EXP_SLTCTL_AIC', + 'PCI_EXP_SLTCTL_ATTN_IND_BLINK', 'PCI_EXP_SLTCTL_ATTN_IND_OFF', + 'PCI_EXP_SLTCTL_ATTN_IND_ON', 'PCI_EXP_SLTCTL_ATTN_IND_SHIFT', + 'PCI_EXP_SLTCTL_CCIE', 'PCI_EXP_SLTCTL_DLLSCE', + 'PCI_EXP_SLTCTL_EIC', 'PCI_EXP_SLTCTL_HPIE', + 'PCI_EXP_SLTCTL_IBPD_DISABLE', 'PCI_EXP_SLTCTL_MRLSCE', + 'PCI_EXP_SLTCTL_PCC', 'PCI_EXP_SLTCTL_PDCE', + 'PCI_EXP_SLTCTL_PFDE', 'PCI_EXP_SLTCTL_PIC', + 'PCI_EXP_SLTCTL_PWR_IND_BLINK', 'PCI_EXP_SLTCTL_PWR_IND_OFF', + 'PCI_EXP_SLTCTL_PWR_IND_ON', 'PCI_EXP_SLTCTL_PWR_OFF', + 'PCI_EXP_SLTCTL_PWR_ON', 'PCI_EXP_SLTSTA', 'PCI_EXP_SLTSTA2', + 'PCI_EXP_SLTSTA_ABP', 'PCI_EXP_SLTSTA_CC', 'PCI_EXP_SLTSTA_DLLSC', + 'PCI_EXP_SLTSTA_EIS', 'PCI_EXP_SLTSTA_MRLSC', + 'PCI_EXP_SLTSTA_MRLSS', 'PCI_EXP_SLTSTA_PDC', + 'PCI_EXP_SLTSTA_PDS', 'PCI_EXP_SLTSTA_PFD', + 'PCI_EXP_TYPE_DOWNSTREAM', 'PCI_EXP_TYPE_ENDPOINT', + 'PCI_EXP_TYPE_LEG_END', 'PCI_EXP_TYPE_PCIE_BRIDGE', + 'PCI_EXP_TYPE_PCI_BRIDGE', 'PCI_EXP_TYPE_RC_EC', + 'PCI_EXP_TYPE_RC_END', 'PCI_EXP_TYPE_ROOT_PORT', + 'PCI_EXP_TYPE_UPSTREAM', 'PCI_EXT_CAP_ARI_SIZEOF', + 'PCI_EXT_CAP_ATS_SIZEOF', 'PCI_EXT_CAP_DSN_SIZEOF', + 'PCI_EXT_CAP_ID_ACS', 'PCI_EXT_CAP_ID_AMD_XXX', + 'PCI_EXT_CAP_ID_ARI', 'PCI_EXT_CAP_ID_ATS', 'PCI_EXT_CAP_ID_CAC', + 'PCI_EXT_CAP_ID_DLF', 'PCI_EXT_CAP_ID_DPA', 'PCI_EXT_CAP_ID_DPC', + 'PCI_EXT_CAP_ID_DSN', 'PCI_EXT_CAP_ID_DVSEC', + 'PCI_EXT_CAP_ID_ERR', 'PCI_EXT_CAP_ID_L1SS', 'PCI_EXT_CAP_ID_LTR', + 'PCI_EXT_CAP_ID_MAX', 'PCI_EXT_CAP_ID_MCAST', + 'PCI_EXT_CAP_ID_MFVC', 'PCI_EXT_CAP_ID_MRIOV', + 'PCI_EXT_CAP_ID_PASID', 'PCI_EXT_CAP_ID_PL_16GT', + 'PCI_EXT_CAP_ID_PMUX', 'PCI_EXT_CAP_ID_PRI', 'PCI_EXT_CAP_ID_PTM', + 'PCI_EXT_CAP_ID_PWR', 'PCI_EXT_CAP_ID_RCEC', + 'PCI_EXT_CAP_ID_RCILC', 'PCI_EXT_CAP_ID_RCLD', + 'PCI_EXT_CAP_ID_RCRB', 'PCI_EXT_CAP_ID_REBAR', + 'PCI_EXT_CAP_ID_SECPCI', 'PCI_EXT_CAP_ID_SRIOV', + 'PCI_EXT_CAP_ID_TPH', 'PCI_EXT_CAP_ID_VC', 'PCI_EXT_CAP_ID_VC9', + 'PCI_EXT_CAP_ID_VNDR', 'PCI_EXT_CAP_LTR_SIZEOF', + 'PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF', 'PCI_EXT_CAP_PASID_SIZEOF', + 'PCI_EXT_CAP_PRI_SIZEOF', 'PCI_EXT_CAP_PWR_SIZEOF', + 'PCI_EXT_CAP_SRIOV_SIZEOF', 'PCI_HEADER_TYPE', + 'PCI_HEADER_TYPE_BRIDGE', 'PCI_HEADER_TYPE_CARDBUS', + 'PCI_HEADER_TYPE_MASK', 'PCI_HEADER_TYPE_NORMAL', + 'PCI_INTERRUPT_LINE', 'PCI_INTERRUPT_PIN', 'PCI_IO_1K_RANGE_MASK', + 'PCI_IO_BASE', 'PCI_IO_BASE_UPPER16', 'PCI_IO_LIMIT', + 'PCI_IO_LIMIT_UPPER16', 'PCI_IO_RANGE_MASK', + 'PCI_IO_RANGE_TYPE_16', 'PCI_IO_RANGE_TYPE_32', + 'PCI_IO_RANGE_TYPE_MASK', 'PCI_L1SS_CAP', + 'PCI_L1SS_CAP_ASPM_L1_1', 'PCI_L1SS_CAP_ASPM_L1_2', + 'PCI_L1SS_CAP_CM_RESTORE_TIME', 'PCI_L1SS_CAP_L1_PM_SS', + 'PCI_L1SS_CAP_PCIPM_L1_1', 'PCI_L1SS_CAP_PCIPM_L1_2', + 'PCI_L1SS_CAP_P_PWR_ON_SCALE', 'PCI_L1SS_CAP_P_PWR_ON_VALUE', + 'PCI_L1SS_CTL1', 'PCI_L1SS_CTL1_ASPM_L1_1', + 'PCI_L1SS_CTL1_ASPM_L1_2', 'PCI_L1SS_CTL1_CM_RESTORE_TIME', + 'PCI_L1SS_CTL1_L1SS_MASK', 'PCI_L1SS_CTL1_L1_2_MASK', + 'PCI_L1SS_CTL1_LTR_L12_TH_SCALE', + 'PCI_L1SS_CTL1_LTR_L12_TH_VALUE', 'PCI_L1SS_CTL1_PCIPM_L1_1', + 'PCI_L1SS_CTL1_PCIPM_L1_2', 'PCI_L1SS_CTL2', 'PCI_LATENCY_TIMER', + 'PCI_LTR_MAX_NOSNOOP_LAT', 'PCI_LTR_MAX_SNOOP_LAT', + 'PCI_LTR_SCALE_MASK', 'PCI_LTR_SCALE_SHIFT', 'PCI_LTR_VALUE_MASK', + 'PCI_MATCH_ANY', 'PCI_MAX_LAT', 'PCI_MEMORY_BASE', + 'PCI_MEMORY_LIMIT', 'PCI_MEMORY_RANGE_MASK', + 'PCI_MEMORY_RANGE_TYPE_MASK', 'PCI_MIN_GNT', + 'PCI_MSIX_ENTRY_CTRL_MASKBIT', 'PCI_MSIX_ENTRY_DATA', + 'PCI_MSIX_ENTRY_LOWER_ADDR', 'PCI_MSIX_ENTRY_SIZE', + 'PCI_MSIX_ENTRY_UPPER_ADDR', 'PCI_MSIX_ENTRY_VECTOR_CTRL', + 'PCI_MSIX_FLAGS', 'PCI_MSIX_FLAGS_BIRMASK', + 'PCI_MSIX_FLAGS_ENABLE', 'PCI_MSIX_FLAGS_MASKALL', + 'PCI_MSIX_FLAGS_QSIZE', 'PCI_MSIX_PBA', 'PCI_MSIX_PBA_BIR', + 'PCI_MSIX_PBA_OFFSET', 'PCI_MSIX_TABLE', 'PCI_MSIX_TABLE_BIR', + 'PCI_MSIX_TABLE_OFFSET', 'PCI_MSI_ADDRESS_HI', + 'PCI_MSI_ADDRESS_LO', 'PCI_MSI_DATA_32', 'PCI_MSI_DATA_64', + 'PCI_MSI_FLAGS', 'PCI_MSI_FLAGS_64BIT', 'PCI_MSI_FLAGS_ENABLE', + 'PCI_MSI_FLAGS_MASKBIT', 'PCI_MSI_FLAGS_QMASK', + 'PCI_MSI_FLAGS_QSIZE', 'PCI_MSI_MASK_32', 'PCI_MSI_MASK_64', + 'PCI_MSI_PENDING_32', 'PCI_MSI_PENDING_64', 'PCI_MSI_RFU', + 'PCI_PASID_CAP', 'PCI_PASID_CAP_EXEC', 'PCI_PASID_CAP_PRIV', + 'PCI_PASID_CTRL', 'PCI_PASID_CTRL_ENABLE', 'PCI_PASID_CTRL_EXEC', + 'PCI_PASID_CTRL_PRIV', 'PCI_PL_16GT_LE_CTRL', + 'PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK', + 'PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK', + 'PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT', 'PCI_PM_BPCC_ENABLE', + 'PCI_PM_CAP_AUX_POWER', 'PCI_PM_CAP_D1', 'PCI_PM_CAP_D2', + 'PCI_PM_CAP_DSI', 'PCI_PM_CAP_PME', 'PCI_PM_CAP_PME_CLOCK', + 'PCI_PM_CAP_PME_D0', 'PCI_PM_CAP_PME_D1', 'PCI_PM_CAP_PME_D2', + 'PCI_PM_CAP_PME_D3cold', 'PCI_PM_CAP_PME_D3hot', + 'PCI_PM_CAP_PME_MASK', 'PCI_PM_CAP_PME_SHIFT', + 'PCI_PM_CAP_RESERVED', 'PCI_PM_CAP_VER_MASK', 'PCI_PM_CTRL', + 'PCI_PM_CTRL_DATA_SCALE_MASK', 'PCI_PM_CTRL_DATA_SEL_MASK', + 'PCI_PM_CTRL_NO_SOFT_RESET', 'PCI_PM_CTRL_PME_ENABLE', + 'PCI_PM_CTRL_PME_STATUS', 'PCI_PM_CTRL_STATE_MASK', + 'PCI_PM_DATA_REGISTER', 'PCI_PM_PMC', 'PCI_PM_PPB_B2_B3', + 'PCI_PM_PPB_EXTENSIONS', 'PCI_PM_SIZEOF', 'PCI_PREF_BASE_UPPER32', + 'PCI_PREF_LIMIT_UPPER32', 'PCI_PREF_MEMORY_BASE', + 'PCI_PREF_MEMORY_LIMIT', 'PCI_PREF_RANGE_MASK', + 'PCI_PREF_RANGE_TYPE_32', 'PCI_PREF_RANGE_TYPE_64', + 'PCI_PREF_RANGE_TYPE_MASK', 'PCI_PRIMARY_BUS', + 'PCI_PRI_ALLOC_REQ', 'PCI_PRI_CTRL', 'PCI_PRI_CTRL_ENABLE', + 'PCI_PRI_CTRL_RESET', 'PCI_PRI_MAX_REQ', 'PCI_PRI_STATUS', + 'PCI_PRI_STATUS_PASID', 'PCI_PRI_STATUS_RF', + 'PCI_PRI_STATUS_STOPPED', 'PCI_PRI_STATUS_UPRGI', 'PCI_PTM_CAP', + 'PCI_PTM_CAP_REQ', 'PCI_PTM_CAP_ROOT', 'PCI_PTM_CTRL', + 'PCI_PTM_CTRL_ENABLE', 'PCI_PTM_CTRL_ROOT', + 'PCI_PTM_GRANULARITY_MASK', 'PCI_PWR_CAP', 'PCI_PWR_DATA', + 'PCI_PWR_DSR', 'PCI_RCEC_BUSN', 'PCI_RCEC_BUSN_REG_VER', + 'PCI_RCEC_RCIEP_BITMAP', 'PCI_REBAR_CAP', 'PCI_REBAR_CAP_SIZES', + 'PCI_REBAR_CTRL', 'PCI_REBAR_CTRL_BAR_IDX', + 'PCI_REBAR_CTRL_BAR_SHIFT', 'PCI_REBAR_CTRL_BAR_SIZE', + 'PCI_REBAR_CTRL_NBAR_MASK', 'PCI_REBAR_CTRL_NBAR_SHIFT', + 'PCI_REVISION_ID', 'PCI_ROM_ADDRESS', 'PCI_ROM_ADDRESS1', + 'PCI_ROM_ADDRESS_ENABLE', 'PCI_ROM_ADDRESS_MASK', 'PCI_SATA_REGS', + 'PCI_SATA_REGS_INLINE', 'PCI_SATA_REGS_MASK', + 'PCI_SATA_SIZEOF_LONG', 'PCI_SATA_SIZEOF_SHORT', + 'PCI_SECONDARY_BUS', 'PCI_SEC_LATENCY_TIMER', 'PCI_SEC_STATUS', + 'PCI_SID_CHASSIS_NR', 'PCI_SID_ESR', 'PCI_SID_ESR_FIC', + 'PCI_SID_ESR_NSLOTS', 'PCI_SRIOV_BAR', 'PCI_SRIOV_CAP', + 'PCI_SRIOV_CAP_VFM', 'PCI_SRIOV_CTRL', 'PCI_SRIOV_CTRL_ARI', + 'PCI_SRIOV_CTRL_INTR', 'PCI_SRIOV_CTRL_MSE', 'PCI_SRIOV_CTRL_VFE', + 'PCI_SRIOV_CTRL_VFM', 'PCI_SRIOV_FUNC_LINK', + 'PCI_SRIOV_INITIAL_VF', 'PCI_SRIOV_NUM_BARS', 'PCI_SRIOV_NUM_VF', + 'PCI_SRIOV_STATUS', 'PCI_SRIOV_STATUS_VFM', + 'PCI_SRIOV_SUP_PGSIZE', 'PCI_SRIOV_SYS_PGSIZE', + 'PCI_SRIOV_TOTAL_VF', 'PCI_SRIOV_VFM', 'PCI_SRIOV_VFM_AV', + 'PCI_SRIOV_VFM_MI', 'PCI_SRIOV_VFM_MO', 'PCI_SRIOV_VFM_UA', + 'PCI_SRIOV_VF_DID', 'PCI_SRIOV_VF_OFFSET', 'PCI_SRIOV_VF_STRIDE', + 'PCI_SSVID_DEVICE_ID', 'PCI_SSVID_VENDOR_ID', 'PCI_STATUS', + 'PCI_STATUS_66MHZ', 'PCI_STATUS_CAP_LIST', + 'PCI_STATUS_DETECTED_PARITY', 'PCI_STATUS_DEVSEL_FAST', + 'PCI_STATUS_DEVSEL_MASK', 'PCI_STATUS_DEVSEL_MEDIUM', + 'PCI_STATUS_DEVSEL_SLOW', 'PCI_STATUS_FAST_BACK', + 'PCI_STATUS_IMM_READY', 'PCI_STATUS_INTERRUPT', + 'PCI_STATUS_PARITY', 'PCI_STATUS_REC_MASTER_ABORT', + 'PCI_STATUS_REC_TARGET_ABORT', 'PCI_STATUS_SIG_SYSTEM_ERROR', + 'PCI_STATUS_SIG_TARGET_ABORT', 'PCI_STATUS_UDF', + 'PCI_STD_HEADER_SIZEOF', 'PCI_STD_NUM_BARS', + 'PCI_SUBORDINATE_BUS', 'PCI_SUBSYSTEM_ID', + 'PCI_SUBSYSTEM_VENDOR_ID', 'PCI_TPH_BASE_SIZEOF', 'PCI_TPH_CAP', + 'PCI_TPH_CAP_LOC_MASK', 'PCI_TPH_CAP_ST_MASK', + 'PCI_TPH_CAP_ST_SHIFT', 'PCI_TPH_LOC_CAP', 'PCI_TPH_LOC_MSIX', + 'PCI_TPH_LOC_NONE', 'PCI_VC_CAP1_ARB_SIZE', 'PCI_VC_CAP1_EVCC', + 'PCI_VC_CAP1_LPEVCC', 'PCI_VC_CAP2_128_PHASE', + 'PCI_VC_CAP2_32_PHASE', 'PCI_VC_CAP2_64_PHASE', + 'PCI_VC_CAP2_ARB_OFF', 'PCI_VC_PORT_CAP1', 'PCI_VC_PORT_CAP2', + 'PCI_VC_PORT_CTRL', 'PCI_VC_PORT_CTRL_LOAD_TABLE', + 'PCI_VC_PORT_STATUS', 'PCI_VC_PORT_STATUS_TABLE', + 'PCI_VC_RES_CAP', 'PCI_VC_RES_CAP_128_PHASE', + 'PCI_VC_RES_CAP_128_PHASE_TB', 'PCI_VC_RES_CAP_256_PHASE', + 'PCI_VC_RES_CAP_32_PHASE', 'PCI_VC_RES_CAP_64_PHASE', + 'PCI_VC_RES_CAP_ARB_OFF', 'PCI_VC_RES_CTRL', + 'PCI_VC_RES_CTRL_ARB_SELECT', 'PCI_VC_RES_CTRL_ENABLE', + 'PCI_VC_RES_CTRL_ID', 'PCI_VC_RES_CTRL_LOAD_TABLE', + 'PCI_VC_RES_STATUS', 'PCI_VC_RES_STATUS_NEGO', + 'PCI_VC_RES_STATUS_TABLE', 'PCI_VENDOR_ID', 'PCI_VNDR_HEADER', + 'PCI_VPD_ADDR', 'PCI_VPD_ADDR_F', 'PCI_VPD_ADDR_MASK', + 'PCI_VPD_DATA', 'PCI_VSEC_HDR', 'PCI_VSEC_HDR_LEN_SHIFT', + 'PCI_X_BRIDGE_SSTATUS', 'PCI_X_BRIDGE_STATUS', 'PCI_X_CMD', + 'PCI_X_CMD_DPERR_E', 'PCI_X_CMD_ERO', 'PCI_X_CMD_MAX_READ', + 'PCI_X_CMD_MAX_SPLIT', 'PCI_X_CMD_READ_1K', 'PCI_X_CMD_READ_2K', + 'PCI_X_CMD_READ_4K', 'PCI_X_CMD_READ_512', 'PCI_X_CMD_SPLIT_1', + 'PCI_X_CMD_SPLIT_12', 'PCI_X_CMD_SPLIT_16', 'PCI_X_CMD_SPLIT_2', + 'PCI_X_CMD_SPLIT_3', 'PCI_X_CMD_SPLIT_32', 'PCI_X_CMD_SPLIT_4', + 'PCI_X_CMD_SPLIT_8', 'PCI_X_ECC_CSR', 'PCI_X_SSTATUS_133MHZ', + 'PCI_X_SSTATUS_266MHZ', 'PCI_X_SSTATUS_533MHZ', + 'PCI_X_SSTATUS_64BIT', 'PCI_X_SSTATUS_FREQ', 'PCI_X_SSTATUS_V1', + 'PCI_X_SSTATUS_V2', 'PCI_X_SSTATUS_VERS', 'PCI_X_STATUS', + 'PCI_X_STATUS_133MHZ', 'PCI_X_STATUS_266MHZ', + 'PCI_X_STATUS_533MHZ', 'PCI_X_STATUS_64BIT', 'PCI_X_STATUS_BUS', + 'PCI_X_STATUS_COMPLEX', 'PCI_X_STATUS_DEVFN', + 'PCI_X_STATUS_MAX_CUM', 'PCI_X_STATUS_MAX_READ', + 'PCI_X_STATUS_MAX_SPLIT', 'PCI_X_STATUS_SPL_DISC', + 'PCI_X_STATUS_SPL_ERR', 'PCI_X_STATUS_UNX_SPL', + 'VGA_ARB_RSRC_LEGACY_IO', 'VGA_ARB_RSRC_LEGACY_MEM', + 'VGA_ARB_RSRC_NONE', 'VGA_ARB_RSRC_NORMAL_IO', + 'VGA_ARB_RSRC_NORMAL_MEM', 'pci_device_cfg_read', + 'pci_device_cfg_read_u16', 'pci_device_cfg_read_u32', + 'pci_device_cfg_read_u8', 'pci_device_cfg_write', + 'pci_device_cfg_write_bits', 'pci_device_cfg_write_u16', + 'pci_device_cfg_write_u32', 'pci_device_cfg_write_u8', + 'pci_device_close_io', 'pci_device_enable', + 'pci_device_find_by_slot', 'pci_device_get_agp_info', + 'pci_device_get_bridge_buses', 'pci_device_get_bridge_info', + 'pci_device_get_device_name', 'pci_device_get_parent_bridge', + 'pci_device_get_pcmcia_bridge_info', + 'pci_device_get_subdevice_name', 'pci_device_get_subvendor_name', + 'pci_device_get_vendor_name', 'pci_device_has_kernel_driver', + 'pci_device_is_boot_vga', 'pci_device_map_legacy', + 'pci_device_map_memory_range', 'pci_device_map_range', + 'pci_device_map_region', 'pci_device_next', 'pci_device_open_io', + 'pci_device_probe', 'pci_device_read_rom', + 'pci_device_unmap_legacy', 'pci_device_unmap_memory_range', + 'pci_device_unmap_range', 'pci_device_unmap_region', + 'pci_device_vgaarb_decodes', 'pci_device_vgaarb_fini', + 'pci_device_vgaarb_get_info', 'pci_device_vgaarb_init', + 'pci_device_vgaarb_lock', 'pci_device_vgaarb_set_target', + 'pci_device_vgaarb_trylock', 'pci_device_vgaarb_unlock', + 'pci_get_strings', 'pci_id_match_iterator_create', + 'pci_io_read16', 'pci_io_read32', 'pci_io_read8', + 'pci_io_write16', 'pci_io_write32', 'pci_io_write8', + 'pci_iterator_destroy', 'pci_legacy_open_io', + 'pci_slot_match_iterator_create', 'pci_system_cleanup', + 'pci_system_init', 'pci_system_init_dev_mem', 'pciaddr_t', + 'struct_pci_agp_info', 'struct_pci_bridge_info', + 'struct_pci_device', 'struct_pci_device_iterator', + 'struct_pci_id_match', 'struct_pci_io_handle', + 'struct_pci_mem_region', 'struct_pci_pcmcia_bridge_info', + 'struct_pci_pcmcia_bridge_info_0', + 'struct_pci_pcmcia_bridge_info_1', 'struct_pci_slot_match', + 'uint16_t', 'uint32_t', 'uint8_t'] diff --git a/tinygrad/runtime/autogen/vfio.py b/tinygrad/runtime/autogen/vfio.py new file mode 100644 index 0000000000..ff0cda416a --- /dev/null +++ b/tinygrad/runtime/autogen/vfio.py @@ -0,0 +1,891 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + +import fcntl, functools + +def _do_ioctl_io(__idir, __base, __nr, __fd, val=0, __len=0): + return fcntl.ioctl(__fd, (__idir<<30) | (__len<<16) | (__base<<8) | __nr, val) + +def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, __val=None, **kwargs): + ret = fcntl.ioctl(__fd, (__idir<<30) | (ctypes.sizeof(made := (__made or __user_struct(**kwargs)))<<16) | (__base<<8) | __nr, made) + if ret != 0: raise RuntimeError(f"ioctl returned {ret}") + return made + +def _IO(base, nr): return functools.partial(_do_ioctl_io, 0, ord(base) if isinstance(base, str) else base, nr) +def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) +def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) +def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) + +class AsDictMixin: + @classmethod + def as_dict(cls, self): + result = {} + if not isinstance(self, AsDictMixin): + # not a structure, assume it's already a python object + return self + if not hasattr(cls, "_fields_"): + return result + # sys.version_info >= (3, 5) + # for (field, *_) in cls._fields_: # noqa + for field_tuple in cls._fields_: # noqa + field = field_tuple[0] + if field.startswith('PADDING_'): + continue + value = getattr(self, field) + type_ = type(value) + if hasattr(value, "_length_") and hasattr(value, "_type_"): + # array + if not hasattr(type_, "as_dict"): + value = [v for v in value] + else: + type_ = type_._type_ + value = [type_.as_dict(v) for v in value] + elif hasattr(value, "contents") and hasattr(value, "_type_"): + # pointer + try: + if not hasattr(type_, "as_dict"): + value = value.contents + else: + type_ = type_._type_ + value = type_.as_dict(value.contents) + except ValueError: + # nullptr + value = None + elif isinstance(value, AsDictMixin): + # other structure + value = type_.as_dict(value) + result[field] = value + return result + + +class Structure(ctypes.Structure, AsDictMixin): + + def __init__(self, *args, **kwds): + # We don't want to use positional arguments fill PADDING_* fields + + args = dict(zip(self.__class__._field_names_(), args)) + args.update(kwds) + super(Structure, self).__init__(**args) + + @classmethod + def _field_names_(cls): + if hasattr(cls, '_fields_'): + return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) + else: + return () + + @classmethod + def get_type(cls, field): + for f in cls._fields_: + if f[0] == field: + return f[1] + return None + + @classmethod + def bind(cls, bound_fields): + fields = {} + for name, type_ in cls._fields_: + if hasattr(type_, "restype"): + if name in bound_fields: + if bound_fields[name] is None: + fields[name] = type_() + else: + # use a closure to capture the callback from the loop scope + fields[name] = ( + type_((lambda callback: lambda *args: callback(*args))( + bound_fields[name])) + ) + del bound_fields[name] + else: + # default callback implementation (does nothing) + try: + default_ = type_(0).restype().value + except TypeError: + default_ = None + fields[name] = type_(( + lambda default_: lambda *args: default_)(default_)) + else: + # not a callback function, use default initialization + if name in bound_fields: + fields[name] = bound_fields[name] + del bound_fields[name] + else: + fields[name] = type_() + if len(bound_fields) != 0: + raise ValueError( + "Cannot bind the following unknown callback(s) {}.{}".format( + cls.__name__, bound_fields.keys() + )) + return cls(**fields) + + +class Union(ctypes.Union, AsDictMixin): + pass + + + + + +VFIO_H = True # macro +VFIO_API_VERSION = 0 # macro +VFIO_TYPE1_IOMMU = 1 # macro +VFIO_SPAPR_TCE_IOMMU = 2 # macro +VFIO_TYPE1v2_IOMMU = 3 # macro +VFIO_DMA_CC_IOMMU = 4 # macro +VFIO_EEH = 5 # macro +VFIO_TYPE1_NESTING_IOMMU = 6 # macro +VFIO_SPAPR_TCE_v2_IOMMU = 7 # macro +VFIO_NOIOMMU_IOMMU = 8 # macro +VFIO_UNMAP_ALL = 9 # macro +VFIO_UPDATE_VADDR = 10 # macro +VFIO_TYPE = (';') # macro +VFIO_BASE = 100 # macro +VFIO_GET_API_VERSION = _IO ( ( ';' ) , 100 + 0 ) # macro (from list) +VFIO_CHECK_EXTENSION = _IO ( ( ';' ) , 100 + 1 ) # macro (from list) +VFIO_SET_IOMMU = _IO ( ( ';' ) , 100 + 2 ) # macro (from list) +VFIO_GROUP_FLAGS_VIABLE = (1<<0) # macro +VFIO_GROUP_FLAGS_CONTAINER_SET = (1<<1) # macro +VFIO_GROUP_GET_STATUS = _IO ( ( ';' ) , 100 + 3 ) # macro (from list) +VFIO_GROUP_SET_CONTAINER = _IO ( ( ';' ) , 100 + 4 ) # macro (from list) +VFIO_GROUP_UNSET_CONTAINER = _IO ( ( ';' ) , 100 + 5 ) # macro (from list) +VFIO_GROUP_GET_DEVICE_FD = _IO ( ( ';' ) , 100 + 6 ) # macro (from list) +VFIO_DEVICE_FLAGS_RESET = (1<<0) # macro +VFIO_DEVICE_FLAGS_PCI = (1<<1) # macro +VFIO_DEVICE_FLAGS_PLATFORM = (1<<2) # macro +VFIO_DEVICE_FLAGS_AMBA = (1<<3) # macro +VFIO_DEVICE_FLAGS_CCW = (1<<4) # macro +VFIO_DEVICE_FLAGS_AP = (1<<5) # macro +VFIO_DEVICE_FLAGS_FSL_MC = (1<<6) # macro +VFIO_DEVICE_FLAGS_CAPS = (1<<7) # macro +VFIO_DEVICE_GET_INFO = _IO ( ( ';' ) , 100 + 7 ) # macro (from list) +VFIO_DEVICE_API_PCI_STRING = "vfio-pci" # macro +VFIO_DEVICE_API_PLATFORM_STRING = "vfio-platform" # macro +VFIO_DEVICE_API_AMBA_STRING = "vfio-amba" # macro +VFIO_DEVICE_API_CCW_STRING = "vfio-ccw" # macro +VFIO_DEVICE_API_AP_STRING = "vfio-ap" # macro +VFIO_DEVICE_INFO_CAP_ZPCI_BASE = 1 # macro +VFIO_DEVICE_INFO_CAP_ZPCI_GROUP = 2 # macro +VFIO_DEVICE_INFO_CAP_ZPCI_UTIL = 3 # macro +VFIO_DEVICE_INFO_CAP_ZPCI_PFIP = 4 # macro +VFIO_REGION_INFO_FLAG_READ = (1<<0) # macro +VFIO_REGION_INFO_FLAG_WRITE = (1<<1) # macro +VFIO_REGION_INFO_FLAG_MMAP = (1<<2) # macro +VFIO_REGION_INFO_FLAG_CAPS = (1<<3) # macro +VFIO_DEVICE_GET_REGION_INFO = _IO ( ( ';' ) , 100 + 8 ) # macro (from list) +VFIO_REGION_INFO_CAP_SPARSE_MMAP = 1 # macro +VFIO_REGION_INFO_CAP_TYPE = 2 # macro +VFIO_REGION_TYPE_PCI_VENDOR_TYPE = (1<<31) # macro +VFIO_REGION_TYPE_PCI_VENDOR_MASK = (0xffff) # macro +VFIO_REGION_TYPE_GFX = (1) # macro +VFIO_REGION_TYPE_CCW = (2) # macro +VFIO_REGION_TYPE_MIGRATION = (3) # macro +VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION = (1) # macro +VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG = (2) # macro +VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG = (3) # macro +VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM = (1) # macro +VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD = (1) # macro +VFIO_REGION_SUBTYPE_GFX_EDID = (1) # macro +VFIO_DEVICE_GFX_LINK_STATE_UP = 1 # macro +VFIO_DEVICE_GFX_LINK_STATE_DOWN = 2 # macro +VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD = (1) # macro +VFIO_REGION_SUBTYPE_CCW_SCHIB = (2) # macro +VFIO_REGION_SUBTYPE_CCW_CRW = (3) # macro +VFIO_REGION_SUBTYPE_MIGRATION = (1) # macro +VFIO_DEVICE_STATE_STOP = (0) # macro +VFIO_DEVICE_STATE_RUNNING = (1<<0) # macro +VFIO_DEVICE_STATE_SAVING = (1<<1) # macro +VFIO_DEVICE_STATE_RESUMING = (1<<2) # macro +VFIO_DEVICE_STATE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro +# def VFIO_DEVICE_STATE_VALID(state): # macro +# return (state&(1<<2)?(state&((1<<0)|(1<<1)|(1<<2)))==(1<<2):1) +def VFIO_DEVICE_STATE_IS_ERROR(state): # macro + return ((state&((1<<0)|(1<<1)|(1<<2)))==((1<<1)|(1<<2))) +# def VFIO_DEVICE_STATE_SET_ERROR(state): # macro +# return ((state&~((1<<0)|(1<<1)|(1<<2)))|VFIO_DEVICE_SATE_SAVING|(1<<2)) +VFIO_REGION_INFO_CAP_MSIX_MAPPABLE = 3 # macro +VFIO_REGION_INFO_CAP_NVLINK2_SSATGT = 4 # macro +VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD = 5 # macro +VFIO_IRQ_INFO_EVENTFD = (1<<0) # macro +VFIO_IRQ_INFO_MASKABLE = (1<<1) # macro +VFIO_IRQ_INFO_AUTOMASKED = (1<<2) # macro +VFIO_IRQ_INFO_NORESIZE = (1<<3) # macro +VFIO_DEVICE_GET_IRQ_INFO = _IO ( ( ';' ) , 100 + 9 ) # macro (from list) +VFIO_IRQ_SET_DATA_NONE = (1<<0) # macro +VFIO_IRQ_SET_DATA_BOOL = (1<<1) # macro +VFIO_IRQ_SET_DATA_EVENTFD = (1<<2) # macro +VFIO_IRQ_SET_ACTION_MASK = (1<<3) # macro +VFIO_IRQ_SET_ACTION_UNMASK = (1<<4) # macro +VFIO_IRQ_SET_ACTION_TRIGGER = (1<<5) # macro +VFIO_DEVICE_SET_IRQS = _IO ( ( ';' ) , 100 + 10 ) # macro (from list) +VFIO_IRQ_SET_DATA_TYPE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro +VFIO_IRQ_SET_ACTION_TYPE_MASK = ((1<<3)|(1<<4)|(1<<5)) # macro +VFIO_DEVICE_RESET = _IO ( ( ';' ) , 100 + 11 ) # macro (from list) +VFIO_DEVICE_GET_PCI_HOT_RESET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) +VFIO_DEVICE_PCI_HOT_RESET = _IO ( ( ';' ) , 100 + 13 ) # macro (from list) +VFIO_GFX_PLANE_TYPE_PROBE = (1<<0) # macro +VFIO_GFX_PLANE_TYPE_DMABUF = (1<<1) # macro +VFIO_GFX_PLANE_TYPE_REGION = (1<<2) # macro +VFIO_DEVICE_QUERY_GFX_PLANE = _IO ( ( ';' ) , 100 + 14 ) # macro (from list) +VFIO_DEVICE_GET_GFX_DMABUF = _IO ( ( ';' ) , 100 + 15 ) # macro (from list) +VFIO_DEVICE_IOEVENTFD_8 = (1<<0) # macro +VFIO_DEVICE_IOEVENTFD_16 = (1<<1) # macro +VFIO_DEVICE_IOEVENTFD_32 = (1<<2) # macro +VFIO_DEVICE_IOEVENTFD_64 = (1<<3) # macro +VFIO_DEVICE_IOEVENTFD_SIZE_MASK = (0xf) # macro +VFIO_DEVICE_IOEVENTFD = _IO ( ( ';' ) , 100 + 16 ) # macro (from list) +VFIO_DEVICE_FEATURE_MASK = (0xffff) # macro +VFIO_DEVICE_FEATURE_GET = (1<<16) # macro +VFIO_DEVICE_FEATURE_SET = (1<<17) # macro +VFIO_DEVICE_FEATURE_PROBE = (1<<18) # macro +VFIO_DEVICE_FEATURE = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) +VFIO_DEVICE_FEATURE_PCI_VF_TOKEN = (0) # macro +VFIO_IOMMU_INFO_PGSIZES = (1<<0) # macro +VFIO_IOMMU_INFO_CAPS = (1<<1) # macro +VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE = 1 # macro +VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION = 2 # macro +VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL = 3 # macro +VFIO_IOMMU_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) +VFIO_DMA_MAP_FLAG_READ = (1<<0) # macro +VFIO_DMA_MAP_FLAG_WRITE = (1<<1) # macro +VFIO_DMA_MAP_FLAG_VADDR = (1<<2) # macro +VFIO_IOMMU_MAP_DMA = _IO ( ( ';' ) , 100 + 13 ) # macro (from list) +VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP = (1<<0) # macro +VFIO_DMA_UNMAP_FLAG_ALL = (1<<1) # macro +VFIO_DMA_UNMAP_FLAG_VADDR = (1<<2) # macro +VFIO_IOMMU_UNMAP_DMA = _IO ( ( ';' ) , 100 + 14 ) # macro (from list) +VFIO_IOMMU_ENABLE = _IO ( ( ';' ) , 100 + 15 ) # macro (from list) +VFIO_IOMMU_DISABLE = _IO ( ( ';' ) , 100 + 16 ) # macro (from list) +VFIO_IOMMU_DIRTY_PAGES_FLAG_START = (1<<0) # macro +VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP = (1<<1) # macro +VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP = (1<<2) # macro +VFIO_IOMMU_DIRTY_PAGES = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) +VFIO_IOMMU_SPAPR_INFO_DDW = (1<<0) # macro +VFIO_IOMMU_SPAPR_TCE_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) +VFIO_EEH_PE_DISABLE = 0 # macro +VFIO_EEH_PE_ENABLE = 1 # macro +VFIO_EEH_PE_UNFREEZE_IO = 2 # macro +VFIO_EEH_PE_UNFREEZE_DMA = 3 # macro +VFIO_EEH_PE_GET_STATE = 4 # macro +VFIO_EEH_PE_STATE_NORMAL = 0 # macro +VFIO_EEH_PE_STATE_RESET = 1 # macro +VFIO_EEH_PE_STATE_STOPPED = 2 # macro +VFIO_EEH_PE_STATE_STOPPED_DMA = 4 # macro +VFIO_EEH_PE_STATE_UNAVAIL = 5 # macro +VFIO_EEH_PE_RESET_DEACTIVATE = 5 # macro +VFIO_EEH_PE_RESET_HOT = 6 # macro +VFIO_EEH_PE_RESET_FUNDAMENTAL = 7 # macro +VFIO_EEH_PE_CONFIGURE = 8 # macro +VFIO_EEH_PE_INJECT_ERR = 9 # macro +VFIO_EEH_PE_OP = _IO ( ( ';' ) , 100 + 21 ) # macro (from list) +VFIO_IOMMU_SPAPR_REGISTER_MEMORY = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) +VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY = _IO ( ( ';' ) , 100 + 18 ) # macro (from list) +VFIO_IOMMU_SPAPR_TCE_CREATE = _IO ( ( ';' ) , 100 + 19 ) # macro (from list) +VFIO_IOMMU_SPAPR_TCE_REMOVE = _IO ( ( ';' ) , 100 + 20 ) # macro (from list) +class struct_vfio_info_cap_header(Structure): + pass + +struct_vfio_info_cap_header._pack_ = 1 # source:False +struct_vfio_info_cap_header._fields_ = [ + ('id', ctypes.c_uint16), + ('version', ctypes.c_uint16), + ('next', ctypes.c_uint32), +] + +class struct_vfio_group_status(Structure): + pass + +struct_vfio_group_status._pack_ = 1 # source:False +struct_vfio_group_status._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), +] + +class struct_vfio_device_info(Structure): + pass + +struct_vfio_device_info._pack_ = 1 # source:False +struct_vfio_device_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('num_regions', ctypes.c_uint32), + ('num_irqs', ctypes.c_uint32), + ('cap_offset', ctypes.c_uint32), +] + +class struct_vfio_region_info(Structure): + pass + +struct_vfio_region_info._pack_ = 1 # source:False +struct_vfio_region_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('index', ctypes.c_uint32), + ('cap_offset', ctypes.c_uint32), + ('size', ctypes.c_uint64), + ('offset', ctypes.c_uint64), +] + +class struct_vfio_region_sparse_mmap_area(Structure): + pass + +struct_vfio_region_sparse_mmap_area._pack_ = 1 # source:False +struct_vfio_region_sparse_mmap_area._fields_ = [ + ('offset', ctypes.c_uint64), + ('size', ctypes.c_uint64), +] + +class struct_vfio_region_info_cap_sparse_mmap(Structure): + pass + +struct_vfio_region_info_cap_sparse_mmap._pack_ = 1 # source:False +struct_vfio_region_info_cap_sparse_mmap._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('nr_areas', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('areas', struct_vfio_region_sparse_mmap_area * 0), +] + +class struct_vfio_region_info_cap_type(Structure): + pass + +struct_vfio_region_info_cap_type._pack_ = 1 # source:False +struct_vfio_region_info_cap_type._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('type', ctypes.c_uint32), + ('subtype', ctypes.c_uint32), +] + +class struct_vfio_region_gfx_edid(Structure): + pass + +struct_vfio_region_gfx_edid._pack_ = 1 # source:False +struct_vfio_region_gfx_edid._fields_ = [ + ('edid_offset', ctypes.c_uint32), + ('edid_max_size', ctypes.c_uint32), + ('edid_size', ctypes.c_uint32), + ('max_xres', ctypes.c_uint32), + ('max_yres', ctypes.c_uint32), + ('link_state', ctypes.c_uint32), +] + +class struct_vfio_device_migration_info(Structure): + pass + +struct_vfio_device_migration_info._pack_ = 1 # source:False +struct_vfio_device_migration_info._fields_ = [ + ('device_state', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('pending_bytes', ctypes.c_uint64), + ('data_offset', ctypes.c_uint64), + ('data_size', ctypes.c_uint64), +] + +class struct_vfio_region_info_cap_nvlink2_ssatgt(Structure): + pass + +struct_vfio_region_info_cap_nvlink2_ssatgt._pack_ = 1 # source:False +struct_vfio_region_info_cap_nvlink2_ssatgt._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('tgt', ctypes.c_uint64), +] + +class struct_vfio_region_info_cap_nvlink2_lnkspd(Structure): + pass + +struct_vfio_region_info_cap_nvlink2_lnkspd._pack_ = 1 # source:False +struct_vfio_region_info_cap_nvlink2_lnkspd._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('link_speed', ctypes.c_uint32), + ('__pad', ctypes.c_uint32), +] + +class struct_vfio_irq_info(Structure): + pass + +struct_vfio_irq_info._pack_ = 1 # source:False +struct_vfio_irq_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('index', ctypes.c_uint32), + ('count', ctypes.c_uint32), +] + +class struct_vfio_irq_set(Structure): + pass + +struct_vfio_irq_set._pack_ = 1 # source:False +struct_vfio_irq_set._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('index', ctypes.c_uint32), + ('start', ctypes.c_uint32), + ('count', ctypes.c_uint32), + ('data', ctypes.c_int * 1), +] + + +# values for enumeration 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX' +c__Ea_VFIO_PCI_BAR0_REGION_INDEX__enumvalues = { + 0: 'VFIO_PCI_BAR0_REGION_INDEX', + 1: 'VFIO_PCI_BAR1_REGION_INDEX', + 2: 'VFIO_PCI_BAR2_REGION_INDEX', + 3: 'VFIO_PCI_BAR3_REGION_INDEX', + 4: 'VFIO_PCI_BAR4_REGION_INDEX', + 5: 'VFIO_PCI_BAR5_REGION_INDEX', + 6: 'VFIO_PCI_ROM_REGION_INDEX', + 7: 'VFIO_PCI_CONFIG_REGION_INDEX', + 8: 'VFIO_PCI_VGA_REGION_INDEX', + 9: 'VFIO_PCI_NUM_REGIONS', +} +VFIO_PCI_BAR0_REGION_INDEX = 0 +VFIO_PCI_BAR1_REGION_INDEX = 1 +VFIO_PCI_BAR2_REGION_INDEX = 2 +VFIO_PCI_BAR3_REGION_INDEX = 3 +VFIO_PCI_BAR4_REGION_INDEX = 4 +VFIO_PCI_BAR5_REGION_INDEX = 5 +VFIO_PCI_ROM_REGION_INDEX = 6 +VFIO_PCI_CONFIG_REGION_INDEX = 7 +VFIO_PCI_VGA_REGION_INDEX = 8 +VFIO_PCI_NUM_REGIONS = 9 +c__Ea_VFIO_PCI_BAR0_REGION_INDEX = ctypes.c_uint32 # enum + +# values for enumeration 'c__Ea_VFIO_PCI_INTX_IRQ_INDEX' +c__Ea_VFIO_PCI_INTX_IRQ_INDEX__enumvalues = { + 0: 'VFIO_PCI_INTX_IRQ_INDEX', + 1: 'VFIO_PCI_MSI_IRQ_INDEX', + 2: 'VFIO_PCI_MSIX_IRQ_INDEX', + 3: 'VFIO_PCI_ERR_IRQ_INDEX', + 4: 'VFIO_PCI_REQ_IRQ_INDEX', + 5: 'VFIO_PCI_NUM_IRQS', +} +VFIO_PCI_INTX_IRQ_INDEX = 0 +VFIO_PCI_MSI_IRQ_INDEX = 1 +VFIO_PCI_MSIX_IRQ_INDEX = 2 +VFIO_PCI_ERR_IRQ_INDEX = 3 +VFIO_PCI_REQ_IRQ_INDEX = 4 +VFIO_PCI_NUM_IRQS = 5 +c__Ea_VFIO_PCI_INTX_IRQ_INDEX = ctypes.c_uint32 # enum + +# values for enumeration 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX' +c__Ea_VFIO_CCW_CONFIG_REGION_INDEX__enumvalues = { + 0: 'VFIO_CCW_CONFIG_REGION_INDEX', + 1: 'VFIO_CCW_NUM_REGIONS', +} +VFIO_CCW_CONFIG_REGION_INDEX = 0 +VFIO_CCW_NUM_REGIONS = 1 +c__Ea_VFIO_CCW_CONFIG_REGION_INDEX = ctypes.c_uint32 # enum + +# values for enumeration 'c__Ea_VFIO_CCW_IO_IRQ_INDEX' +c__Ea_VFIO_CCW_IO_IRQ_INDEX__enumvalues = { + 0: 'VFIO_CCW_IO_IRQ_INDEX', + 1: 'VFIO_CCW_CRW_IRQ_INDEX', + 2: 'VFIO_CCW_REQ_IRQ_INDEX', + 3: 'VFIO_CCW_NUM_IRQS', +} +VFIO_CCW_IO_IRQ_INDEX = 0 +VFIO_CCW_CRW_IRQ_INDEX = 1 +VFIO_CCW_REQ_IRQ_INDEX = 2 +VFIO_CCW_NUM_IRQS = 3 +c__Ea_VFIO_CCW_IO_IRQ_INDEX = ctypes.c_uint32 # enum +class struct_vfio_pci_dependent_device(Structure): + pass + +struct_vfio_pci_dependent_device._pack_ = 1 # source:False +struct_vfio_pci_dependent_device._fields_ = [ + ('group_id', ctypes.c_uint32), + ('segment', ctypes.c_uint16), + ('bus', ctypes.c_ubyte), + ('devfn', ctypes.c_ubyte), +] + +class struct_vfio_pci_hot_reset_info(Structure): + pass + +struct_vfio_pci_hot_reset_info._pack_ = 1 # source:False +struct_vfio_pci_hot_reset_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('count', ctypes.c_uint32), + ('devices', struct_vfio_pci_dependent_device * 0), +] + +class struct_vfio_pci_hot_reset(Structure): + pass + +struct_vfio_pci_hot_reset._pack_ = 1 # source:False +struct_vfio_pci_hot_reset._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('count', ctypes.c_uint32), + ('group_fds', ctypes.c_int32 * 0), +] + +class struct_vfio_device_gfx_plane_info(Structure): + pass + +class union_vfio_device_gfx_plane_info_0(Union): + pass + +union_vfio_device_gfx_plane_info_0._pack_ = 1 # source:False +union_vfio_device_gfx_plane_info_0._fields_ = [ + ('region_index', ctypes.c_uint32), + ('dmabuf_id', ctypes.c_uint32), +] + +struct_vfio_device_gfx_plane_info._pack_ = 1 # source:False +struct_vfio_device_gfx_plane_info._anonymous_ = ('_0',) +struct_vfio_device_gfx_plane_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('drm_plane_type', ctypes.c_uint32), + ('drm_format', ctypes.c_uint32), + ('drm_format_mod', ctypes.c_uint64), + ('width', ctypes.c_uint32), + ('height', ctypes.c_uint32), + ('stride', ctypes.c_uint32), + ('size', ctypes.c_uint32), + ('x_pos', ctypes.c_uint32), + ('y_pos', ctypes.c_uint32), + ('x_hot', ctypes.c_uint32), + ('y_hot', ctypes.c_uint32), + ('_0', union_vfio_device_gfx_plane_info_0), + ('PADDING_0', ctypes.c_ubyte * 4), +] + +class struct_vfio_device_ioeventfd(Structure): + pass + +struct_vfio_device_ioeventfd._pack_ = 1 # source:False +struct_vfio_device_ioeventfd._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('offset', ctypes.c_uint64), + ('data', ctypes.c_uint64), + ('fd', ctypes.c_int32), + ('PADDING_0', ctypes.c_ubyte * 4), +] + +class struct_vfio_device_feature(Structure): + pass + +struct_vfio_device_feature._pack_ = 1 # source:False +struct_vfio_device_feature._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('data', ctypes.c_ubyte * 0), +] + +class struct_vfio_iommu_type1_info(Structure): + pass + +struct_vfio_iommu_type1_info._pack_ = 1 # source:False +struct_vfio_iommu_type1_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('iova_pgsizes', ctypes.c_uint64), + ('cap_offset', ctypes.c_uint32), + ('PADDING_0', ctypes.c_ubyte * 4), +] + +class struct_vfio_iova_range(Structure): + pass + +struct_vfio_iova_range._pack_ = 1 # source:False +struct_vfio_iova_range._fields_ = [ + ('start', ctypes.c_uint64), + ('end', ctypes.c_uint64), +] + +class struct_vfio_iommu_type1_info_cap_iova_range(Structure): + pass + +struct_vfio_iommu_type1_info_cap_iova_range._pack_ = 1 # source:False +struct_vfio_iommu_type1_info_cap_iova_range._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('nr_iovas', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('iova_ranges', struct_vfio_iova_range * 0), +] + +class struct_vfio_iommu_type1_info_cap_migration(Structure): + pass + +struct_vfio_iommu_type1_info_cap_migration._pack_ = 1 # source:False +struct_vfio_iommu_type1_info_cap_migration._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('flags', ctypes.c_uint32), + ('PADDING_0', ctypes.c_ubyte * 4), + ('pgsize_bitmap', ctypes.c_uint64), + ('max_dirty_bitmap_size', ctypes.c_uint64), +] + +class struct_vfio_iommu_type1_info_dma_avail(Structure): + pass + +struct_vfio_iommu_type1_info_dma_avail._pack_ = 1 # source:False +struct_vfio_iommu_type1_info_dma_avail._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('avail', ctypes.c_uint32), +] + +class struct_vfio_iommu_type1_dma_map(Structure): + pass + +struct_vfio_iommu_type1_dma_map._pack_ = 1 # source:False +struct_vfio_iommu_type1_dma_map._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('vaddr', ctypes.c_uint64), + ('iova', ctypes.c_uint64), + ('size', ctypes.c_uint64), +] + +class struct_vfio_bitmap(Structure): + pass + +struct_vfio_bitmap._pack_ = 1 # source:False +struct_vfio_bitmap._fields_ = [ + ('pgsize', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('data', ctypes.POINTER(ctypes.c_uint64)), +] + +class struct_vfio_iommu_type1_dma_unmap(Structure): + pass + +struct_vfio_iommu_type1_dma_unmap._pack_ = 1 # source:False +struct_vfio_iommu_type1_dma_unmap._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('iova', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('data', ctypes.c_ubyte * 0), +] + +class struct_vfio_iommu_type1_dirty_bitmap(Structure): + pass + +struct_vfio_iommu_type1_dirty_bitmap._pack_ = 1 # source:False +struct_vfio_iommu_type1_dirty_bitmap._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('data', ctypes.c_ubyte * 0), +] + +class struct_vfio_iommu_type1_dirty_bitmap_get(Structure): + pass + +struct_vfio_iommu_type1_dirty_bitmap_get._pack_ = 1 # source:False +struct_vfio_iommu_type1_dirty_bitmap_get._fields_ = [ + ('iova', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('bitmap', struct_vfio_bitmap), +] + +class struct_vfio_iommu_spapr_tce_ddw_info(Structure): + pass + +struct_vfio_iommu_spapr_tce_ddw_info._pack_ = 1 # source:False +struct_vfio_iommu_spapr_tce_ddw_info._fields_ = [ + ('pgsizes', ctypes.c_uint64), + ('max_dynamic_windows_supported', ctypes.c_uint32), + ('levels', ctypes.c_uint32), +] + +class struct_vfio_iommu_spapr_tce_info(Structure): + pass + +struct_vfio_iommu_spapr_tce_info._pack_ = 1 # source:False +struct_vfio_iommu_spapr_tce_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('dma32_window_start', ctypes.c_uint32), + ('dma32_window_size', ctypes.c_uint32), + ('ddw', struct_vfio_iommu_spapr_tce_ddw_info), +] + +class struct_vfio_eeh_pe_err(Structure): + pass + +struct_vfio_eeh_pe_err._pack_ = 1 # source:False +struct_vfio_eeh_pe_err._fields_ = [ + ('type', ctypes.c_uint32), + ('func', ctypes.c_uint32), + ('addr', ctypes.c_uint64), + ('mask', ctypes.c_uint64), +] + +class struct_vfio_eeh_pe_op(Structure): + pass + +class union_vfio_eeh_pe_op_0(Union): + _pack_ = 1 # source:False + _fields_ = [ + ('err', struct_vfio_eeh_pe_err), + ] + +struct_vfio_eeh_pe_op._pack_ = 1 # source:False +struct_vfio_eeh_pe_op._anonymous_ = ('_0',) +struct_vfio_eeh_pe_op._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('op', ctypes.c_uint32), + ('PADDING_0', ctypes.c_ubyte * 4), + ('_0', union_vfio_eeh_pe_op_0), +] + +class struct_vfio_iommu_spapr_register_memory(Structure): + pass + +struct_vfio_iommu_spapr_register_memory._pack_ = 1 # source:False +struct_vfio_iommu_spapr_register_memory._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('vaddr', ctypes.c_uint64), + ('size', ctypes.c_uint64), +] + +class struct_vfio_iommu_spapr_tce_create(Structure): + pass + +struct_vfio_iommu_spapr_tce_create._pack_ = 1 # source:False +struct_vfio_iommu_spapr_tce_create._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('page_shift', ctypes.c_uint32), + ('__resv1', ctypes.c_uint32), + ('window_size', ctypes.c_uint64), + ('levels', ctypes.c_uint32), + ('__resv2', ctypes.c_uint32), + ('start_addr', ctypes.c_uint64), +] + +class struct_vfio_iommu_spapr_tce_remove(Structure): + pass + +struct_vfio_iommu_spapr_tce_remove._pack_ = 1 # source:False +struct_vfio_iommu_spapr_tce_remove._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('start_addr', ctypes.c_uint64), +] + +__all__ = \ + ['VFIO_API_VERSION', 'VFIO_BASE', 'VFIO_CCW_CONFIG_REGION_INDEX', + 'VFIO_CCW_CRW_IRQ_INDEX', 'VFIO_CCW_IO_IRQ_INDEX', + 'VFIO_CCW_NUM_IRQS', 'VFIO_CCW_NUM_REGIONS', + 'VFIO_CCW_REQ_IRQ_INDEX', 'VFIO_DEVICE_API_AMBA_STRING', + 'VFIO_DEVICE_API_AP_STRING', 'VFIO_DEVICE_API_CCW_STRING', + 'VFIO_DEVICE_API_PCI_STRING', 'VFIO_DEVICE_API_PLATFORM_STRING', + 'VFIO_DEVICE_FEATURE_GET', 'VFIO_DEVICE_FEATURE_MASK', + 'VFIO_DEVICE_FEATURE_PCI_VF_TOKEN', 'VFIO_DEVICE_FEATURE_PROBE', + 'VFIO_DEVICE_FEATURE_SET', 'VFIO_DEVICE_FLAGS_AMBA', + 'VFIO_DEVICE_FLAGS_AP', 'VFIO_DEVICE_FLAGS_CAPS', + 'VFIO_DEVICE_FLAGS_CCW', 'VFIO_DEVICE_FLAGS_FSL_MC', + 'VFIO_DEVICE_FLAGS_PCI', 'VFIO_DEVICE_FLAGS_PLATFORM', + 'VFIO_DEVICE_FLAGS_RESET', 'VFIO_DEVICE_GFX_LINK_STATE_DOWN', + 'VFIO_DEVICE_GFX_LINK_STATE_UP', 'VFIO_DEVICE_INFO_CAP_ZPCI_BASE', + 'VFIO_DEVICE_INFO_CAP_ZPCI_GROUP', + 'VFIO_DEVICE_INFO_CAP_ZPCI_PFIP', + 'VFIO_DEVICE_INFO_CAP_ZPCI_UTIL', 'VFIO_DEVICE_IOEVENTFD_16', + 'VFIO_DEVICE_IOEVENTFD_32', 'VFIO_DEVICE_IOEVENTFD_64', + 'VFIO_DEVICE_IOEVENTFD_8', 'VFIO_DEVICE_IOEVENTFD_SIZE_MASK', + 'VFIO_DEVICE_STATE_MASK', 'VFIO_DEVICE_STATE_RESUMING', + 'VFIO_DEVICE_STATE_RUNNING', 'VFIO_DEVICE_STATE_SAVING', + 'VFIO_DEVICE_STATE_STOP', 'VFIO_DMA_CC_IOMMU', + 'VFIO_DMA_MAP_FLAG_READ', 'VFIO_DMA_MAP_FLAG_VADDR', + 'VFIO_DMA_MAP_FLAG_WRITE', 'VFIO_DMA_UNMAP_FLAG_ALL', + 'VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP', + 'VFIO_DMA_UNMAP_FLAG_VADDR', 'VFIO_EEH', 'VFIO_EEH_PE_CONFIGURE', + 'VFIO_EEH_PE_DISABLE', 'VFIO_EEH_PE_ENABLE', + 'VFIO_EEH_PE_GET_STATE', 'VFIO_EEH_PE_INJECT_ERR', + 'VFIO_EEH_PE_RESET_DEACTIVATE', 'VFIO_EEH_PE_RESET_FUNDAMENTAL', + 'VFIO_EEH_PE_RESET_HOT', 'VFIO_EEH_PE_STATE_NORMAL', + 'VFIO_EEH_PE_STATE_RESET', 'VFIO_EEH_PE_STATE_STOPPED', + 'VFIO_EEH_PE_STATE_STOPPED_DMA', 'VFIO_EEH_PE_STATE_UNAVAIL', + 'VFIO_EEH_PE_UNFREEZE_DMA', 'VFIO_EEH_PE_UNFREEZE_IO', + 'VFIO_GFX_PLANE_TYPE_DMABUF', 'VFIO_GFX_PLANE_TYPE_PROBE', + 'VFIO_GFX_PLANE_TYPE_REGION', 'VFIO_GROUP_FLAGS_CONTAINER_SET', + 'VFIO_GROUP_FLAGS_VIABLE', 'VFIO_H', + 'VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP', + 'VFIO_IOMMU_DIRTY_PAGES_FLAG_START', + 'VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP', 'VFIO_IOMMU_INFO_CAPS', + 'VFIO_IOMMU_INFO_PGSIZES', 'VFIO_IOMMU_SPAPR_INFO_DDW', + 'VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE', + 'VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION', + 'VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL', 'VFIO_IRQ_INFO_AUTOMASKED', + 'VFIO_IRQ_INFO_EVENTFD', 'VFIO_IRQ_INFO_MASKABLE', + 'VFIO_IRQ_INFO_NORESIZE', 'VFIO_IRQ_SET_ACTION_MASK', + 'VFIO_IRQ_SET_ACTION_TRIGGER', 'VFIO_IRQ_SET_ACTION_TYPE_MASK', + 'VFIO_IRQ_SET_ACTION_UNMASK', 'VFIO_IRQ_SET_DATA_BOOL', + 'VFIO_IRQ_SET_DATA_EVENTFD', 'VFIO_IRQ_SET_DATA_NONE', + 'VFIO_IRQ_SET_DATA_TYPE_MASK', 'VFIO_NOIOMMU_IOMMU', + 'VFIO_PCI_BAR0_REGION_INDEX', 'VFIO_PCI_BAR1_REGION_INDEX', + 'VFIO_PCI_BAR2_REGION_INDEX', 'VFIO_PCI_BAR3_REGION_INDEX', + 'VFIO_PCI_BAR4_REGION_INDEX', 'VFIO_PCI_BAR5_REGION_INDEX', + 'VFIO_PCI_CONFIG_REGION_INDEX', 'VFIO_PCI_ERR_IRQ_INDEX', + 'VFIO_PCI_INTX_IRQ_INDEX', 'VFIO_PCI_MSIX_IRQ_INDEX', + 'VFIO_PCI_MSI_IRQ_INDEX', 'VFIO_PCI_NUM_IRQS', + 'VFIO_PCI_NUM_REGIONS', 'VFIO_PCI_REQ_IRQ_INDEX', + 'VFIO_PCI_ROM_REGION_INDEX', 'VFIO_PCI_VGA_REGION_INDEX', + 'VFIO_REGION_INFO_CAP_MSIX_MAPPABLE', + 'VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD', + 'VFIO_REGION_INFO_CAP_NVLINK2_SSATGT', + 'VFIO_REGION_INFO_CAP_SPARSE_MMAP', 'VFIO_REGION_INFO_CAP_TYPE', + 'VFIO_REGION_INFO_FLAG_CAPS', 'VFIO_REGION_INFO_FLAG_MMAP', + 'VFIO_REGION_INFO_FLAG_READ', 'VFIO_REGION_INFO_FLAG_WRITE', + 'VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD', + 'VFIO_REGION_SUBTYPE_CCW_CRW', 'VFIO_REGION_SUBTYPE_CCW_SCHIB', + 'VFIO_REGION_SUBTYPE_GFX_EDID', + 'VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD', + 'VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG', + 'VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG', + 'VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION', + 'VFIO_REGION_SUBTYPE_MIGRATION', + 'VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM', 'VFIO_REGION_TYPE_CCW', + 'VFIO_REGION_TYPE_GFX', 'VFIO_REGION_TYPE_MIGRATION', + 'VFIO_REGION_TYPE_PCI_VENDOR_MASK', + 'VFIO_REGION_TYPE_PCI_VENDOR_TYPE', 'VFIO_SPAPR_TCE_IOMMU', + 'VFIO_SPAPR_TCE_v2_IOMMU', 'VFIO_TYPE', 'VFIO_TYPE1_IOMMU', + 'VFIO_TYPE1_NESTING_IOMMU', 'VFIO_TYPE1v2_IOMMU', + 'VFIO_UNMAP_ALL', 'VFIO_UPDATE_VADDR', '_IO', '_IOR', '_IOW', + '_IOWR', 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX', + 'c__Ea_VFIO_CCW_IO_IRQ_INDEX', 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX', + 'c__Ea_VFIO_PCI_INTX_IRQ_INDEX', 'struct_vfio_bitmap', + 'struct_vfio_device_feature', 'struct_vfio_device_gfx_plane_info', + 'struct_vfio_device_info', 'struct_vfio_device_ioeventfd', + 'struct_vfio_device_migration_info', 'struct_vfio_eeh_pe_err', + 'struct_vfio_eeh_pe_op', 'struct_vfio_group_status', + 'struct_vfio_info_cap_header', + 'struct_vfio_iommu_spapr_register_memory', + 'struct_vfio_iommu_spapr_tce_create', + 'struct_vfio_iommu_spapr_tce_ddw_info', + 'struct_vfio_iommu_spapr_tce_info', + 'struct_vfio_iommu_spapr_tce_remove', + 'struct_vfio_iommu_type1_dirty_bitmap', + 'struct_vfio_iommu_type1_dirty_bitmap_get', + 'struct_vfio_iommu_type1_dma_map', + 'struct_vfio_iommu_type1_dma_unmap', + 'struct_vfio_iommu_type1_info', + 'struct_vfio_iommu_type1_info_cap_iova_range', + 'struct_vfio_iommu_type1_info_cap_migration', + 'struct_vfio_iommu_type1_info_dma_avail', + 'struct_vfio_iova_range', 'struct_vfio_irq_info', + 'struct_vfio_irq_set', 'struct_vfio_pci_dependent_device', + 'struct_vfio_pci_hot_reset', 'struct_vfio_pci_hot_reset_info', + 'struct_vfio_region_gfx_edid', 'struct_vfio_region_info', + 'struct_vfio_region_info_cap_nvlink2_lnkspd', + 'struct_vfio_region_info_cap_nvlink2_ssatgt', + 'struct_vfio_region_info_cap_sparse_mmap', + 'struct_vfio_region_info_cap_type', + 'struct_vfio_region_sparse_mmap_area', + 'union_vfio_device_gfx_plane_info_0', 'union_vfio_eeh_pe_op_0'] diff --git a/tinygrad/runtime/ops_amd.py b/tinygrad/runtime/ops_amd.py index 399d434959..fcaea5485a 100644 --- a/tinygrad/runtime/ops_amd.py +++ b/tinygrad/runtime/ops_amd.py @@ -1,6 +1,6 @@ from __future__ import annotations from typing import Any, Optional -import os, ctypes, ctypes.util, functools, pathlib, mmap, errno, array, contextlib, sys +import os, ctypes, ctypes.util, functools, pathlib, mmap, errno, array, contextlib, sys, select, struct assert sys.platform != 'win32' from dataclasses import dataclass from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQBuffer, HWQueue, CLikeArgsState, HCQSignal, HCQProgram @@ -8,9 +8,11 @@ from tinygrad.ops import sint from tinygrad.device import BufferSpec from tinygrad.helpers import getenv, to_mv, round_up, data64_le, mv_address from tinygrad.renderer.cstyle import AMDRenderer -from tinygrad.runtime.autogen import kfd, hsa, amd_gpu, libc +from tinygrad.runtime.autogen import kfd, hsa, amd_gpu, libc, libpciaccess, vfio +from tinygrad.runtime.autogen.am import am from tinygrad.runtime.support.compiler_hip import AMDCompiler from tinygrad.runtime.support.elf import elf_loader +from tinygrad.runtime.support.am.amdev import AMDev if getenv("IOCTL"): import extra.hip_gpu_driver.hip_ioctl # noqa: F401 # pylint: disable=unused-import if getenv("MOCKGPU"): import test.mockgpu.mockgpu # noqa: F401 # pylint: disable=unused-import @@ -128,7 +130,7 @@ class AMDComputeQueue(HWQueue): self.release_mem(signal.value_addr, value, amd_gpu.data_sel__mec_release_mem__send_32_bit_low, amd_gpu.int_sel__mec_release_mem__send_interrupt_after_write_confirm, cache_flush=True) - if (dev:=signal.timeline_for_device) is not None: + if not AMDDevice.driverless and (dev:=signal.timeline_for_device) is not None: self.release_mem(dev.queue_event_mailbox_ptr, dev.queue_event.event_id, amd_gpu.data_sel__mec_release_mem__send_32_bit_low, amd_gpu.int_sel__mec_release_mem__send_interrupt_after_write_confirm, ctxid=dev.queue_event.event_id) return self @@ -178,7 +180,7 @@ class AMDCopyQueue(HWQueue): def signal(self, signal:AMDSignal, value:sint=0): self.q(amd_gpu.SDMA_OP_FENCE | amd_gpu.SDMA_PKT_FENCE_HEADER_MTYPE(3), *data64_le(signal.value_addr), value) - if (dev:=signal.timeline_for_device) is not None: + if not AMDDevice.driverless and (dev:=signal.timeline_for_device) is not None: self.q(amd_gpu.SDMA_OP_FENCE | amd_gpu.SDMA_PKT_FENCE_HEADER_MTYPE(3), *data64_le(dev.queue_event_mailbox_ptr), dev.queue_event.event_id) self.q(amd_gpu.SDMA_OP_TRAP, amd_gpu.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(dev.queue_event.event_id)) @@ -267,7 +269,7 @@ class AMDAllocator(HCQAllocator['AMDDevice']): def map(self, buf:HCQBuffer): self.dev.dev_iface.map(buf._base if buf._base is not None else buf) -MAP_FIXED, MAP_NORESERVE = 0x10, 0x400 +MAP_FIXED, MAP_NORESERVE, MAP_LOCKED = 0x10, 0x400, 0x2000 @dataclass class AMDQueueDesc: @@ -394,20 +396,142 @@ class KFDIface: raise RuntimeError("\n".join(report)) +class PCIIface: + vfio:bool = getenv("VFIO", 1) and os.path.exists("/dev/vfio/vfio") + vfio_fd:int = -1 + gpus:list[Any] = [] + + def __init__(self, dev, dev_id): + self.dev = dev + + if first_dev:=len(PCIIface.gpus) == 0: + libpciaccess.pci_system_init() + pci_iter = libpciaccess.pci_id_match_iterator_create(None) + while pcidev:=libpciaccess.pci_device_next(pci_iter): + if pcidev.contents.vendor_id == 0x1002 and pcidev.contents.device_id == 0x744c: PCIIface.gpus.append(pcidev.contents) + + # TODO: visible_devices should be handled layer above this? + visible_devices = [int(x) for x in (getenv('VISIBLE_DEVICES', getenv('HIP_VISIBLE_DEVICES', ''))).split(',') if x.strip()] + PCIIface.gpus = [PCIIface.gpus[x] for x in visible_devices] if visible_devices else PCIIface.gpus + + self.pcidev = PCIIface.gpus[dev_id] + self.pcibus = f"{self.pcidev.domain_16:04x}:{self.pcidev.bus:02x}:{self.pcidev.dev:02x}.{self.pcidev.func:d}" + + # Unbind the device from the kernel driver + if os.path.exists(f"/sys/bus/pci/devices/{self.pcibus}/driver"): + pathlib.Path(f"/sys/bus/pci/devices/{self.pcibus}/driver/unbind").write_text(self.pcibus) + pathlib.Path(f"/sys/bus/pci/devices/{self.pcibus}/resource0_resize").write_text("15") + + # Probe device + libpciaccess.pci_device_probe(ctypes.byref(self.pcidev)) + + # Try to init vfio. Use it if success. + if PCIIface.vfio and PCIIface.vfio_fd == -1: + try: + pathlib.Path("/sys/module/vfio/parameters/enable_unsafe_noiommu_mode").write_text("1") + PCIIface.vfio_fd = os.open("/dev/vfio/vfio", os.O_RDWR) + vfio.VFIO_CHECK_EXTENSION(PCIIface.vfio_fd, vfio.VFIO_NOIOMMU_IOMMU) + except OSError: PCIIface.vfio = False + + # Init vfio for the device + if PCIIface.vfio: + pathlib.Path(f"/sys/bus/pci/devices/{self.pcibus}/driver_override").write_text("vfio-pci") + pathlib.Path("/sys/bus/pci/drivers_probe").write_text(self.pcibus) + + iommu_group = os.readlink(f"/sys/bus/pci/devices/{self.pcibus}/iommu_group").split('/')[-1] + self.vfio_group = os.open(f"/dev/vfio/noiommu-{iommu_group}", os.O_RDWR) + vfio.VFIO_GROUP_SET_CONTAINER(self.vfio_group, ctypes.c_int(PCIIface.vfio_fd)) + + if first_dev: vfio.VFIO_SET_IOMMU(PCIIface.vfio_fd, vfio.VFIO_NOIOMMU_IOMMU) + self.vfio_dev = vfio.VFIO_GROUP_GET_DEVICE_FD(self.vfio_group, ctypes.create_string_buffer(self.pcibus.encode())) + + self.irq_fd = os.eventfd(0, 0) + self.irq_poller = select.poll() + self.irq_poller.register(self.irq_fd, select.POLLIN) + + irqs = vfio.struct_vfio_irq_set(index=vfio.VFIO_PCI_MSI_IRQ_INDEX, flags=vfio.VFIO_IRQ_SET_DATA_EVENTFD|vfio.VFIO_IRQ_SET_ACTION_TRIGGER, + argsz=ctypes.sizeof(vfio.struct_vfio_irq_set), count=1, data=(ctypes.c_int * 1)(self.irq_fd)) + vfio.VFIO_DEVICE_SET_IRQS(self.vfio_dev, irqs) + else: libpciaccess.pci_device_enable(ctypes.byref(self.pcidev)) + + self.bar_fds = {bar: os.open(f"/sys/bus/pci/devices/{self.pcibus}/resource{bar}", os.O_RDWR | os.O_SYNC) for bar in [0, 2, 5]} + + self.adev = AMDev(self.pcidev, self._map_pci_range(0), dbell:=self._map_pci_range(2).cast('Q'), self._map_pci_range(5).cast('I')) + self.doorbell_cpu_addr = mv_address(dbell) + + # TODO: this is for 7900xtx, the only tested card. + self.props = {'simd_count': 192, 'simd_per_cu': 2, 'max_waves_per_simd': 16, 'gfx_target_version': 110000, 'max_slots_scratch_cu': 32, + 'array_count': 12, 'simd_arrays_per_engine': 2, 'lds_size_in_kb': 64} + + def _map_pci_range(self, bar, off=0, addr=0, size=None): + if PCIIface.vfio: + vfio.VFIO_DEVICE_GET_REGION_INFO(self.vfio_dev, reg:=vfio.struct_vfio_region_info(argsz=ctypes.sizeof(vfio.struct_vfio_region_info), index=bar)) + fd, sz, off = self.vfio_dev, size or reg.size, reg.offset + off + else: fd, sz = self.bar_fds[bar], size or self.pcidev.regions[bar].size + return to_mv(libc.mmap(addr, sz, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | (MAP_FIXED if addr else 0), fd, off), sz) + + def alloc(self, size:int, host=False, uncached=False, cpu_access=False): + if host: + vaddr = self.adev.mm.alloc_vaddr(size, align=mmap.PAGESIZE) + va = libc.mmap(vaddr, size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | mmap.MAP_ANONYMOUS | MAP_LOCKED | MAP_FIXED, -1, 0) + + # Read pagemap to get the physical address of each page. The pages are locked. + with open("/proc/self/pagemap", "rb") as f: + for off in range(0, size, mmap.PAGESIZE): + f.seek(((va + off) // mmap.PAGESIZE) * 8) + pt_entry = struct.unpack("Q", f.read(8))[0] & ((1 << 55) - 1) + self.adev.mm.map_range(vaddr=vaddr + off, size=mmap.PAGESIZE, paddr=pt_entry * mmap.PAGESIZE, system=True, snooped=True, uncached=True) + return HCQBuffer(vaddr, size, meta=(self.dev, [self.dev], None)) + + vm = self.adev.mm.valloc(size:=round_up(size, 4 << 10), uncached=uncached, contigous=cpu_access) + if cpu_access: self._map_pci_range(bar=0, off=vm.paddr, addr=vm.va_addr, size=vm.size) + return HCQBuffer(vm.va_addr, size, meta=(self.dev, [self.dev], vm)) + + def free(self, mem): + if mem.meta[2] is not None: + for dev in mem.meta[1][1:]: dev.dev_iface.adev.mm.unmap_range(mem.va_addr, mem.size, free_paddrs=False) + self.adev.mm.vfree(mem.meta[2]) + + def map(self, mem): + if mem.meta[0] == self.dev or self.dev in mem.meta[1]: return + mem.meta[1].append(self.dev) + self.adev.mm.map_from(mem.va_addr, mem.size, mem.meta[0].dev_iface.adev) + + def create_queue(self, queue_type, ring, gart, eop_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, debug_memory_size=0): + if queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: + self.adev.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, + doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0), pipe=0, queue=0) + else: + self.adev.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, + eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0) + + return AMDQueueDesc(ring=to_mv(ring.va_addr, ring.size).cast("I"), doorbell=to_mv(self.doorbell_cpu_addr + doorbell_index * 8, 8).cast("Q"), + read_ptr=to_mv(gart.va_addr, 8).cast("Q"), write_ptr=to_mv(gart.va_addr+0x10, 8).cast("Q")) + + def sleep(self, timeout): + if PCIIface.vfio and len(self.irq_poller.poll(timeout)): + os.read(self.irq_fd, 1024) + self.adev.ih.interrupt_handler() + + def on_device_hang(self): + for d in self.dev.devices: d.dev_iface.adev.gmc.on_interrupt() + raise RuntimeError("Device hang detected") + class AMDDevice(HCQCompiled): + driverless:bool = not os.path.exists('/sys/module/amdgpu') or bool(getenv("AMD_DRIVERLESS", 0)) signals_page:Any = None signals_pool:list[int] = [] def __init__(self, device:str=""): self.device_id = int(device.split(":")[1]) if ":" in device else 0 - self.dev_iface = KFDIface(self, self.device_id) + self.dev_iface = PCIIface(self, self.device_id) if AMDDevice.driverless else KFDIface(self, self.device_id) self.target = int(self.dev_iface.props['gfx_target_version']) self.arch = "gfx%d%x%x" % (self.target // 10000, (self.target // 100) % 100, self.target % 100) if self.target < 100300 or self.target >= 120000: raise RuntimeError(f"Unsupported arch: {self.arch}") if AMDDevice.signals_page is None: - AMDDevice.signals_page = self.dev_iface.alloc(16 * 65536, uncached=True, cpu_access=True) + AMDDevice.signals_page = self.dev_iface.alloc(16 * 65536, host=AMDDevice.driverless, uncached=True, cpu_access=True) AMDDevice.signals_pool = [AMDDevice.signals_page.va_addr + off for off in range(0, AMDDevice.signals_page.size, 16)] else: self.dev_iface.map(AMDDevice.signals_page) diff --git a/tinygrad/runtime/support/allocator.py b/tinygrad/runtime/support/allocator.py new file mode 100644 index 0000000000..5e2effddce --- /dev/null +++ b/tinygrad/runtime/support/allocator.py @@ -0,0 +1,91 @@ +import collections +from typing import Optional +from tinygrad.helpers import round_up + +class TLSFAllocator: + """ + The allocator is based on the Two-Level Segregated Fit (TLSF) algorithm. The allocator maintains 2 level of buckets: + * 1st level is determined by the most significant bit of the size. + * 2nd level splits the covered memory of 1st level into @lv2_cnt entries. + + For each allocation request, the allocator searches for the smallest block that can fit the requested size. + For each deallocation request, the allocator merges the block with its neighbors if they are free. + """ + + def __init__(self, size:int, base:int=0, block_size:int=16, lv2_cnt:int=16): + self.size, self.base, self.block_size, self.l2_cnt = size, base, block_size, lv2_cnt.bit_length() + self.storage:list = [collections.defaultdict(list) for _ in range(size.bit_length() + 1)] + + # self.blocks is more like a linked list, where each entry is a contigous block. + self.blocks:dict[int, tuple[int, Optional[int], Optional[int], bool]] = {0: (size, None, None, True)} # size, next, prev, is_free + self._insert_block(0, size) + + def lv1(self, size): return size.bit_length() + def lv2(self, size): return (size - (1 << (size.bit_length() - 1))) // (1 << max(0, size.bit_length() - self.l2_cnt)) + + def _insert_block(self, start:int, size:int, prev:Optional[int]=None): + if prev is None: prev = self.blocks[start][2] + self.storage[self.lv1(size)][self.lv2(size)].append(start) + self.blocks[start] = (size, start + size, prev, True) + return self + + def _remove_block(self, start:int, size:int, prev:Optional[int]=None): + if prev is None: prev = self.blocks[start][2] + self.storage[self.lv1(size)][self.lv2(size)].remove(start) + self.blocks[start] = (size, start + size, prev, False) + return self + + def _split_block(self, start:int, size:int, new_size:int): + nxt = self.blocks[start][1] + assert self.blocks[start][3], "block must be free" + self._remove_block(start, size)._insert_block(start, new_size)._insert_block(start + new_size, size - new_size, prev=start) + if nxt in self.blocks: self.blocks[nxt] = (self.blocks[nxt][0], self.blocks[nxt][1], start + new_size, self.blocks[nxt][3]) + return self + + def _merge_right(self, start:int): + size, nxt, _, is_free = self.blocks[start] + assert is_free, "block must be free" + + while is_free and nxt in self.blocks: + if (blk:=self.blocks[nxt])[3] is False: break + self._remove_block(start, size)._remove_block(nxt, blk[0])._insert_block(start, size:=size + blk[0]) + assert self.blocks[start][1] == blk[1] + _, nxt, _, _ = self.blocks.pop(nxt) + + if nxt in self.blocks: self.blocks[nxt] = (self.blocks[nxt][0], self.blocks[nxt][1], start, self.blocks[nxt][3]) + + def _merge_block(self, start:int): + # Go left while blocks are free. Then merge all them right. + while (x:=self.blocks[start][2]) is not None and self.blocks[x][3] is True: start = x + self._merge_right(start) + + def alloc(self, req_size:int, align:int=1) -> int: + req_size = max(self.block_size, req_size) # at least block size. + size = max(self.block_size, req_size + align - 1) + + # Round up the allocation size to the next bucket, so any entry there can fit the requested size. + size = round_up(size, (1 << size.bit_length() - self.l2_cnt)) + + # Search for the smallest block that can fit the requested size. Start with the it's bucket and go up until any block is found. + for l1 in range(self.lv1(size), len(self.storage)): + for l2 in range(self.lv2(size) if l1 == size.bit_length() else 0, (1 << self.l2_cnt)): + if len(self.storage[l1][l2]) > 0: + nsize = self.blocks[self.storage[l1][l2][0]][0] + assert nsize >= size, "block must be larger" + + # Block start address. + start = self.storage[l1][l2][0] + + # If request contains alignment, split the block into two parts. + if (new_start:=round_up(start, align)) != start: + self._split_block(start, nsize, new_start - start) + start, nsize = new_start, self.blocks[new_start][0] + + # If the block is larger than the requested size, split it into two parts. + if nsize > req_size: self._split_block(start, nsize, req_size) + self._remove_block(start, req_size) # Mark the block as allocated. + return start + self.base + raise MemoryError(f"Can't allocate {req_size} bytes") + + def free(self, start:int): + self._insert_block(start - self.base, self.blocks[start - self.base][0])._merge_block(start - self.base) diff --git a/tinygrad/runtime/support/am/__init__.py b/tinygrad/runtime/support/am/__init__.py new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tinygrad/runtime/support/am/amdev.py b/tinygrad/runtime/support/am/amdev.py new file mode 100644 index 0000000000..434510df9c --- /dev/null +++ b/tinygrad/runtime/support/am/amdev.py @@ -0,0 +1,363 @@ +from __future__ import annotations +import ctypes, collections, time, dataclasses, pathlib +from typing import Optional +from tinygrad.helpers import to_mv, mv_address, getenv, round_up +from tinygrad.runtime.autogen.am import am, mp_11_0, mp_13_0_0, nbio_4_3_0, mmhub_3_0_0, gc_11_0_0, osssys_6_0_0 +from tinygrad.runtime.support.allocator import TLSFAllocator +from tinygrad.runtime.support.am.ip import AM_SOC21, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA + +AM_DEBUG = getenv("AM_DEBUG", 0) + +@dataclasses.dataclass(frozen=True) +class AMRegister: + adev:AMDev; reg_off:int; reg_fields:dict[str, tuple[int, int]] # noqa: E702 + + def _parse_kwargs(self, **kwargs): + mask, values = 0xffffffff, 0 + for k, v in kwargs.items(): + if k not in self.reg_fields: raise ValueError(f"Unknown register field: {k}. {self.reg_fields.keys()}") + m, s = self.reg_fields[k] + if v & (m>>s) != v: raise ValueError(f"Value {v} for {k} is out of range {m=} {s=}") + mask &= ~m + values |= v << s + return mask, values + + def build(self, **kwargs) -> int: return self._parse_kwargs(**kwargs)[1] + + def update(self, **kwargs): self.write(value=self.read(), **kwargs) + + def write(self, value=0, **kwargs): + mask, values = self._parse_kwargs(**kwargs) + self.adev.wreg(self.reg_off, (value & mask) | values) + + def read(self, **kwargs): return self.adev.rreg(self.reg_off) & self._parse_kwargs(**kwargs)[0] + +class AMFirmware: + def __init__(self): + # Load SOS firmware + self.sos_fw = {} + + blob, sos_hdr = self.load_fw("psp_13_0_0_sos.bin", am.struct_psp_firmware_header_v2_0) + fw_bin = sos_hdr.psp_fw_bin + + for fw_i in range(sos_hdr.psp_fw_bin_count): + fw_bin_desc = am.struct_psp_fw_bin_desc.from_address(ctypes.addressof(fw_bin) + fw_i * ctypes.sizeof(am.struct_psp_fw_bin_desc)) + ucode_start_offset = fw_bin_desc.offset_bytes + sos_hdr.header.ucode_array_offset_bytes + self.sos_fw[fw_bin_desc.fw_type] = blob[ucode_start_offset:ucode_start_offset+fw_bin_desc.size_bytes] + + # Load other fw + self.ucode_start: dict[str, int] = {} + self.descs: list[tuple[int, memoryview]] = [] + + blob, hdr = self.load_fw("smu_13_0_0.bin", am.struct_smc_firmware_header_v1_0) + self.smu_psp_desc = self.desc(am.GFX_FW_TYPE_SMU, blob, hdr.header.ucode_array_offset_bytes, hdr.header.ucode_size_bytes) + + # SDMA firmware + blob, hdr = self.load_fw("sdma_6_0_0.bin", am.struct_sdma_firmware_header_v2_0) + self.descs += [self.desc(am.GFX_FW_TYPE_SDMA_UCODE_TH0, blob, hdr.header.ucode_array_offset_bytes, hdr.ctx_ucode_size_bytes)] + self.descs += [self.desc(am.GFX_FW_TYPE_SDMA_UCODE_TH1, blob, hdr.ctl_ucode_offset, hdr.ctl_ucode_size_bytes)] + + # PFP, ME, MEC firmware + for (fw_name, fw_cnt) in [('PFP', 2), ('ME', 2), ('MEC', 4)]: + blob, hdr = self.load_fw(f"gc_11_0_0_{fw_name.lower()}.bin", am.struct_gfx_firmware_header_v2_0) + + # Code part + self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}'), blob, hdr.header.ucode_array_offset_bytes, hdr.ucode_size_bytes)] + + # Stack + fw_types = [getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}_P{fwnun}_STACK') for fwnun in range(fw_cnt)] + self.descs += [self.desc(typ, blob, hdr.data_offset_bytes, hdr.data_size_bytes) for typ in fw_types] + self.ucode_start[fw_name] = hdr.ucode_start_addr_lo | (hdr.ucode_start_addr_hi << 32) + + # IMU firmware + blob, hdr = self.load_fw("gc_11_0_0_imu.bin", am.struct_imu_firmware_header_v1_0) + imu_i_off, imu_i_sz, imu_d_sz = hdr.header.ucode_array_offset_bytes, hdr.imu_iram_ucode_size_bytes, hdr.imu_dram_ucode_size_bytes + self.descs += [self.desc(am.GFX_FW_TYPE_IMU_I, blob, imu_i_off, imu_i_sz), self.desc(am.GFX_FW_TYPE_IMU_D, blob, imu_i_off + imu_i_sz, imu_d_sz)] + + # RLC firmware + blob, hdr0, hdr1, hdr2, hdr3 = self.load_fw("gc_11_0_0_rlc.bin", am.struct_rlc_firmware_header_v2_0, + am.struct_rlc_firmware_header_v2_1, am.struct_rlc_firmware_header_v2_2, am.struct_rlc_firmware_header_v2_3) + + for mem in ['GPM', 'SRM']: + off, sz = getattr(hdr1, f'save_restore_list_{mem.lower()}_offset_bytes'), getattr(hdr1, f'save_restore_list_{mem.lower()}_size_bytes') + self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RLC_RESTORE_LIST_{mem}_MEM'), blob, off, sz)] + + for mem,fmem in [('IRAM', 'iram'), ('DRAM_BOOT', 'dram')]: + off, sz = getattr(hdr2, f'rlc_{fmem}_ucode_offset_bytes'), getattr(hdr2, f'rlc_{fmem}_ucode_size_bytes') + self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RLC_{mem}'), blob, off, sz)] + + for mem in ['P', 'V']: + off, sz = getattr(hdr3, f'rlc{mem.lower()}_ucode_offset_bytes'), getattr(hdr3, f'rlc{mem.lower()}_ucode_size_bytes') + self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RLC_{mem}'), blob, off, sz)] + + self.descs += [self.desc(am.GFX_FW_TYPE_RLC_G, blob, hdr0.header.ucode_array_offset_bytes, hdr0.header.ucode_size_bytes)] + + def load_fw(self, fname:str, *headers): + fpath = next(f for loc in ["/lib/firmware/updates/amdgpu/", "/lib/firmware/amdgpu/"] if (f:=pathlib.Path(loc + fname)).exists()) + blob = memoryview(bytearray(fpath.read_bytes())) + return tuple([blob] + [hdr.from_address(mv_address(blob)) for hdr in headers]) + + def desc(self, typ:int, blob:memoryview, offset:int, size:int) -> tuple[int, memoryview]: return (typ, blob[offset:offset+size]) + +class AMPhysicalMemoryBlock: + def __init__(self, adev:AMDev, paddr:int, size:int): self.adev, self.paddr, self.size = adev, paddr, size + def mc_addr(self): return self.adev.gmc.mc_base + self.paddr + def cpu_addr(self): return mv_address(self.adev.vram) + self.paddr + def cpu_view(self): return to_mv(self.cpu_addr(), self.size) + +@dataclasses.dataclass(frozen=True) +class AMVirtualMapping: va_addr:int; size:int; cpu_addr:Optional[int]=None; paddr:Optional[int]=None # noqa: E702 + +class AMPageTableEntry: + def __init__(self, pm, lv): self.pm, self.view, self.lv = pm, pm.cpu_view().cast('Q'), lv + + def set_table(self, entry_id, pte:AMPageTableEntry, valid=True): + self.view[entry_id] = (pte.pm.paddr & 0x0000FFFFFFFFF000) | (am.AMDGPU_PTE_VALID if valid else 0) + + def set_page(self, entry_id, paddr, uncached=False, system=False, snooped=False, frag=0, valid=True): + f = (am.AMDGPU_PTE_VALID if valid else 0) | am.AMDGPU_PTE_WRITEABLE | am.AMDGPU_PTE_READABLE | am.AMDGPU_PTE_EXECUTABLE \ + | am.AMDGPU_PTE_FRAG(frag) | (am.AMDGPU_PDE_PTE if self.lv != am.AMDGPU_VM_PTB else 0) \ + | ((am.AMDGPU_PTE_SYSTEM) if system else 0) | ((am.AMDGPU_PTE_SNOOPED) if snooped else 0) \ + | (am.AMDGPU_PTE_MTYPE_NV10(0, am.MTYPE_UC) if uncached else 0) + self.view[entry_id] = (paddr & 0x0000FFFFFFFFF000) | f + + def get_entry(self, entry_id): return self.view[entry_id] + +class AMMemoryManager: + va_allocator = TLSFAllocator(512 * (1 << 30), base=0x7F0000000000) # global for all devices. + + def __init__(self, adev, vram_size:int): + self.adev, self.vram_size = adev, vram_size + self.pa_allocator = TLSFAllocator(vram_size - (64 << 20)) # per device + self.root_page_table = AMPageTableEntry(self.palloc(0x1000, zero=True), lv=am.AMDGPU_VM_PDB1) + + def page_table_walker(self, page_table, vaddr, size, offset=0, free_pt=False, creat_pt=True): + """ + The function traverses the page table structure, yielding the largest entries that cover the requested virtual address range. + """ + + pte_covers = 1 << ((9 * (3-page_table.lv)) + 12) + assert size // pte_covers < 512, "Size must be less than 512 ptes" + + def _move_cursor(sz): + nonlocal vaddr, offset, size + vaddr, offset, size = vaddr + sz, offset + sz, size - sz + + def _level_down(va, sz): + entry = page_table.get_entry(pte_idx:=(va // pte_covers) % 512) + if entry & am.AMDGPU_PTE_VALID: + assert entry & am.AMDGPU_PDE_PTE == 0, f"Must be table pt={page_table.pm.paddr:#x}, {pte_idx=} {entry=:#x}" + child_page_table = AMPageTableEntry(AMPhysicalMemoryBlock(page_table.pm.adev, entry & 0x0000FFFFFFFFF000, 0x1000), lv=page_table.lv+1) + else: + assert creat_pt, "Not allowed to create new page table" + child_page_table = AMPageTableEntry(self.palloc(0x1000, zero=True), lv=page_table.lv+1) + page_table.set_table(pte_idx, child_page_table) + yield from self.page_table_walker(child_page_table, va, sz, offset=offset, free_pt=free_pt, creat_pt=creat_pt) + + if free_pt and all(child_page_table.get_entry(i) & am.AMDGPU_PTE_VALID == 0 for i in range(512)): + self.pfree(child_page_table.pm) + page_table.set_page(pte_idx, paddr=0x0, valid=False) + + # First pte is not full covered + if vaddr % pte_covers != 0: + yield from _level_down(vaddr, min(pte_covers - (vaddr % pte_covers), size)) + _move_cursor(min(pte_covers - (vaddr % pte_covers), size)) + + n_ptes = size // pte_covers + if n_ptes > 0: yield (vaddr, offset, (vaddr // pte_covers) % 512, n_ptes, pte_covers, page_table) + _move_cursor(n_ptes * pte_covers) + + # Last pte is not full covered + if size > 0: yield from _level_down(vaddr, size) + + def frags_walker(self, page_table, vaddr, size, from_entry=False, free_pt=False, creat_pt=True): + """ + The TLB hardware has a feature to optimize the number of entries when mapping contiguous regions. + The function yields the largest possible fragments to cover the requested area. + """ + + for va, off, pte_st_idx, n_ptes, pte_covers, pt in self.page_table_walker(page_table, vaddr, size, free_pt=free_pt, creat_pt=creat_pt): + inner_off = 0 + while n_ptes > 0: + if from_entry: frags_cnt = (pt.get_entry(pte_st_idx) >> 7) & 0x1f + else: frags_cnt = pte_covers.bit_length() - 13 # TODO: optimize for other frag sizes + + update_ptes = (1 << (frags_cnt + 12)) // pte_covers + assert update_ptes > 0, f"Invalid update_ptes {update_ptes} {frags_cnt} {pte_covers}" + + yield va + inner_off, off + inner_off, pte_st_idx, update_ptes, pte_covers, pt, frags_cnt + + pte_st_idx, n_ptes, inner_off = pte_st_idx + update_ptes, n_ptes - update_ptes, inner_off + pte_covers * update_ptes + + def _try_alloc(self, pte_cnt, pte_cvrs, frags_cnt): + # Try to allocate contiguous physical memory. + try: return self.pa_allocator.alloc(pte_cnt * pte_cvrs), pte_cnt, frags_cnt + except MemoryError: + if pte_cnt > 1: return self._try_alloc(pte_cnt // 2, pte_cvrs, frags_cnt - 1) + raise + + def map_range(self, vaddr, size, paddr=None, uncached=False, system=False, snooped=False): + if AM_DEBUG >= 2: print(f"Mapping {vaddr=:#x} -> {paddr} ({size=:#x})") + + vaddr = vaddr - AMMemoryManager.va_allocator.base + for _, off, pte_st_idx, n_ptes, pte_covers, pt, frags_cnt in self.frags_walker(self.root_page_table, vaddr, size): + while n_ptes > 0: + # Trying to alloc the contigous frags when possible. + (lpaddr, upd_pte, f_cnt), off = (self._try_alloc(n_ptes, pte_covers, frags_cnt), 0) if paddr is None else ((paddr, n_ptes, frags_cnt), off) + + for pte_idx in range(upd_pte): + assert (pe:=pt.get_entry(pte_st_idx + pte_idx)) & am.AMDGPU_PTE_VALID == 0, f"Entry already set {pe:#x}" + pt.set_page(pte_st_idx + pte_idx, paddr=lpaddr + off, uncached=uncached, system=system, snooped=snooped, frag=f_cnt, valid=True) + off += pte_covers + + if AM_DEBUG >= 3: print(f"\tnptes={upd_pte:#x} incr={pte_covers:#x} upd_flags={pt.get_entry(pte_st_idx):#x} frags={f_cnt:#x}") + n_ptes, pte_st_idx = n_ptes - upd_pte, pte_st_idx + upd_pte + + # Invalidate TLB after mappings. + self.adev.gmc.flush_tlb(ip="GC", vmid=0, flush_type=2) + self.adev.gmc.flush_tlb(ip="GC", vmid=0) + self.adev.gmc.flush_tlb(ip="MM", vmid=0, flush_type=2) + self.adev.gmc.flush_tlb(ip="MM", vmid=0) + + def unmap_range(self, vaddr:int, size:int, free_paddrs=True): + if AM_DEBUG >= 2: print(f"Unmapping {vaddr=:#x} ({size=:#x})") + + vaddr = vaddr - AMMemoryManager.va_allocator.base + for _, _, pte_st_idx, n_ptes, _, pt, _ in self.frags_walker(self.root_page_table, vaddr, size, from_entry=True, free_pt=True): + entry = pt.get_entry(pte_st_idx) + if not (entry & am.AMDGPU_PTE_SYSTEM) and free_paddrs: self.pa_allocator.free(entry & 0x0000FFFFFFFFF000) + + for pte_idx in range(n_ptes): + assert pt.get_entry(pte_st_idx + pte_idx) & am.AMDGPU_PTE_VALID == am.AMDGPU_PTE_VALID, "Entry must be set" + pt.set_page(pte_st_idx + pte_idx, paddr=0x0, valid=False) + + def map_from(self, vaddr:int, size:int, from_adev): + if AM_DEBUG >= 2: print(f"Mapping from {vaddr=:#x} {size=:#x} from {from_adev.pcidev}") + + vaddr = vaddr - AMMemoryManager.va_allocator.base + for va, _, pte_st_idx, n_ptes, pte_covers, pt, _ in self.frags_walker(from_adev.mm.root_page_table, vaddr, size, from_entry=True, creat_pt=False): + entry = pt.get_entry(pte_st_idx) + paddr = (entry & 0x0000FFFFFFFFF000) if entry & am.AMDGPU_PTE_SYSTEM else (entry & 0x0000FFFFFFFFF000) + from_adev.pcidev.regions[0].base_addr + self.map_range(va + AMMemoryManager.va_allocator.base, n_ptes * pte_covers, paddr=paddr, system=True, + uncached=bool(entry & am.AMDGPU_PTE_MTYPE_NV10(0, am.MTYPE_UC)), snooped=bool(entry & am.AMDGPU_PTE_SNOOPED)) + + @staticmethod + def alloc_vaddr(size:int, align=0x1000) -> int: return AMMemoryManager.va_allocator.alloc(size, max((1 << (size.bit_length() - 1)), align)) + + def valloc(self, size:int, align=0x1000, uncached=False, contigous=False) -> AMVirtualMapping: + pm = self.palloc(round_up(size, 0x1000), zero=True) if contigous else None + self.map_range(va:=self.alloc_vaddr(size, align), size, paddr=pm.paddr if pm else None, uncached=uncached) + return AMVirtualMapping(va, size, pm.cpu_addr() if pm is not None else None, pm.paddr if pm is not None else None) + + def vfree(self, vm:AMVirtualMapping): + self.unmap_range(vm.va_addr, vm.size, free_paddrs=(vm.paddr is None)) + self.va_allocator.free(vm.va_addr) + if vm.paddr is not None: self.pa_allocator.free(vm.paddr) + + def palloc(self, size, align=0x1000, zero=True) -> AMPhysicalMemoryBlock: + pm = AMPhysicalMemoryBlock(self.adev, self.pa_allocator.alloc(round_up(size, 0x1000), align), size) + if zero: ctypes.memset(pm.cpu_addr(), 0, pm.size) + return pm + + def pfree(self, pm:AMPhysicalMemoryBlock): self.pa_allocator.free(pm.paddr) + +class AMDev: + def __init__(self, pcidev, vram_bar:memoryview, doorbell_bar:memoryview, mmio_bar:memoryview): + self.pcidev = pcidev + self.vram, self.doorbell64, self.mmio = vram_bar, doorbell_bar, mmio_bar + + self._run_discovery() + self._build_regs() + + # Memory manager & firmware + self.mm = AMMemoryManager(self, self.vram_size) + self.fw = AMFirmware() + + # Initialize IP blocks + self.soc21:AM_SOC21 = AM_SOC21(self) + self.gmc:AM_GMC = AM_GMC(self) + self.ih:AM_IH = AM_IH(self) + self.psp:AM_PSP = AM_PSP(self) + self.smu:AM_SMU = AM_SMU(self) + self.gfx:AM_GFX = AM_GFX(self) + self.sdma:AM_SDMA = AM_SDMA(self) + + if self.psp.is_sos_alive(): self.smu.mode1_reset() + + # Initialize all blocks + for ip in [self.soc21, self.gmc, self.ih, self.psp, self.smu, self.gfx, self.sdma]: ip.init() + self.gfx.set_clockgating_state() + + def ip_base(self, ip:str, inst:int, seg:int) -> int: return self.regs_offset[am.__dict__[f"{ip}_HWIP"]][inst][seg] + + def reg(self, reg:str) -> AMRegister: return self.__dict__[reg] + + def rreg(self, reg:int) -> int: + val = self.indirect_rreg(reg * 4) if reg > len(self.mmio) else self.mmio[reg] + if AM_DEBUG >= 4 and getattr(self, '_prev_rreg', None) != (reg, val): print(f"Reading register {reg:#x} with value {val:#x}") + self._prev_rreg = (reg, val) + return val + + def wreg(self, reg:int, val:int): + if AM_DEBUG >= 4: print(f"Writing register {reg:#x} with value {val:#x}") + if reg > len(self.mmio): self.indirect_wreg(reg * 4, val) + else: self.mmio[reg] = val + + def wreg_pair(self, reg_base:str, lo_suffix:str, hi_suffix:str, val:int): + self.reg(f"{reg_base}{lo_suffix}").write(val & 0xffffffff) + self.reg(f"{reg_base}{hi_suffix}").write(val >> 32) + + def indirect_rreg(self, reg:int) -> int: + self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg) + return self.reg("regBIF_BX_PF0_RSMU_DATA").read() + + def indirect_wreg(self, reg:int, val:int): + self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg) + self.reg("regBIF_BX_PF0_RSMU_DATA").write(val) + + def wait_reg(self, reg:AMRegister, value:int, mask=0xffffffff) -> int: + for _ in range(10000): + if ((rval:=reg.read()) & mask) == value: return rval + time.sleep(0.001) + raise RuntimeError(f'wait_reg timeout reg=0x{reg.reg_off:X} mask=0x{mask:X} value=0x{value:X} last_val=0x{rval}') + + def _run_discovery(self): + # NOTE: Fixed register to query memory size without known ip bases to find the discovery table. + # The table is located at the end of VRAM - 64KB and is 10KB in size. + mmRCC_CONFIG_MEMSIZE = 0xde3 + self.vram_size = self.rreg(mmRCC_CONFIG_MEMSIZE) << 20 + self.discovery_pm = AMPhysicalMemoryBlock(self, self.vram_size - (64 << 10), 10 << 10) + + bhdr = am.struct_binary_header.from_address(self.discovery_pm.cpu_addr()) + ihdr = am.struct_ip_discovery_header.from_address(ctypes.addressof(bhdr) + bhdr.table_list[am.IP_DISCOVERY].offset) + assert ihdr.signature == am.DISCOVERY_TABLE_SIGNATURE and not ihdr.base_addr_64_bit + + # Mapping of HW IP to Discovery HW IP + hw_id_map = {am.__dict__[x]: int(y) for x,y in am.hw_id_map} + self.regs_offset:dict[int, dict[int, list]] = collections.defaultdict(dict) + + for num_die in range(ihdr.num_dies): + dhdr = am.struct_die_header.from_address(ctypes.addressof(bhdr) + ihdr.die_info[num_die].die_offset) + + ip_offset = ctypes.addressof(bhdr) + ctypes.sizeof(dhdr) + ihdr.die_info[num_die].die_offset + for _ in range(dhdr.num_ips): + ip = am.struct_ip_v4.from_address(ip_offset) + ba = (ctypes.c_uint32 * ip.num_base_address).from_address(ip_offset + 8) + for hw_ip in range(1, am.MAX_HWIP): + if hw_ip in hw_id_map and hw_id_map[hw_ip] == ip.hw_id: self.regs_offset[hw_ip][ip.instance_number] = list(ba) + + ip_offset += 8 + (8 if ihdr.base_addr_64_bit else 4) * ip.num_base_address + + def _build_regs(self): + mods = [("MP0", mp_13_0_0), ("MP1", mp_11_0), ("NBIO", nbio_4_3_0), ("MMHUB", mmhub_3_0_0), ("GC", gc_11_0_0), ("OSSSYS", osssys_6_0_0)] + for base, module in mods: + rpref = "mm" if base == "MP1" else "reg" # MP1 regs starts with mm + reg_names: set[str] = set(k[len(rpref):] for k in module.__dict__.keys() if k.startswith(rpref) and not k.endswith("_BASE_IDX")) + reg_fields: dict[str, dict[str, tuple]] = collections.defaultdict(dict) + for k, val in module.__dict__.items(): + if k.endswith("_MASK") and ((rname:=k.split("__")[0]) in reg_names): + reg_fields[rname][k[2+len(rname):-5].lower()] = (val, module.__dict__.get(f"{k[:-5]}__SHIFT", val.bit_length() - 1)) + + for k, regval in module.__dict__.items(): + if k.startswith(rpref) and not k.endswith("_BASE_IDX") and (base_idx:=getattr(module, f"{k}_BASE_IDX", None)) is not None: + setattr(self, k, AMRegister(self, self.ip_base(base, 0, base_idx) + regval, reg_fields.get(k[len(rpref):], {}))) diff --git a/tinygrad/runtime/support/am/ip.py b/tinygrad/runtime/support/am/ip.py new file mode 100644 index 0000000000..d9fba3b125 --- /dev/null +++ b/tinygrad/runtime/support/am/ip.py @@ -0,0 +1,412 @@ +from __future__ import annotations +import ctypes, time +from typing import Literal +from tinygrad.runtime.autogen import libpciaccess +from tinygrad.runtime.autogen.am import am, gc_11_0_0, smu_v13_0_0 +from tinygrad.helpers import to_mv, data64, lo32, hi32 + +class AM_IP: + def __init__(self, adev): self.adev = adev + def init(self): raise NotImplementedError("IP block init must be implemeted") + +class AM_SOC21(AM_IP): + def init(self): + self.adev.regRCC_DEV0_EPF2_STRAP2.update(strap_no_soft_reset_dev0_f2=0x0) + self.adev.regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN.write(0x1) + +class AM_GMC(AM_IP): + def __init__(self, adev): + super().__init__(adev) + + # Memory controller aperture + self.mc_base = self.adev.regMMMC_VM_FB_LOCATION_BASE.read() << 24 + self.mc_end = self.mc_base + self.adev.mm.vram_size - 1 + + # VM aperture + self.vm_base = self.adev.mm.va_allocator.base + self.vm_end = self.vm_base + self.adev.mm.va_allocator.size - 1 + + self.memscratch_pm = self.adev.mm.palloc(0x1000) + self.dummy_page_pm = self.adev.mm.palloc(0x1000) + self.hub_initted = {"MM": False, "GC": False} + + def init(self): self.init_hub("MM") + + def flush_hdp(self): self.adev.regBIF_BX_PF0_GPU_HDP_FLUSH_REQ.write(0xffffffff) + def flush_tlb(self, ip:Literal["MM", "GC"], vmid, flush_type=0): + self.flush_hdp() + + # Can't issue TLB invalidation if the hub isn't initialized. + if not self.hub_initted[ip]: return + + if ip == "MM": self.adev.wait_reg(self.adev.regMMVM_INVALIDATE_ENG17_SEM, mask=0x1, value=0x1) + + self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_REQ").write(flush_type=flush_type, per_vmid_invalidate_req=(1 << vmid), invalidate_l2_ptes=1, + invalidate_l2_pde0=1, invalidate_l2_pde1=1, invalidate_l2_pde2=1, invalidate_l1_ptes=1, clear_protection_fault_status_addr=0) + + self.adev.wait_reg(self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_ACK"), mask=(1 << vmid), value=(1 << vmid)) + + if ip == "MM": + self.adev.regMMVM_INVALIDATE_ENG17_SEM.write(0x0) + self.adev.regMMVM_L2_BANK_SELECT_RESERVED_CID2.update(reserved_cache_private_invalidation=1) + + # Read back the register to ensure the invalidation is complete + self.adev.regMMVM_L2_BANK_SELECT_RESERVED_CID2.read() + + def enable_vm_addressing(self, page_table, ip:Literal["MM", "GC"], vmid): + self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_START_ADDR", "_LO32", "_HI32", self.vm_base >> 12) + self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_END_ADDR", "_LO32", "_HI32", self.vm_end >> 12) + self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_BASE_ADDR", "_LO32", "_HI32", page_table.pm.paddr | 1) + self.adev.reg(f"reg{ip}VM_CONTEXT{vmid}_CNTL").write(0x1fffe00, enable_context=1, page_table_depth=(3 - page_table.lv)) + + def init_hub(self, ip:Literal["MM", "GC"]): + # Init system apertures + self.adev.reg(f"reg{ip}MC_VM_AGP_BASE").write(0) + self.adev.reg(f"reg{ip}MC_VM_AGP_BOT").write(0xffffffffffff >> 24) # disable AGP + self.adev.reg(f"reg{ip}MC_VM_AGP_TOP").write(0) + + self.adev.reg(f"reg{ip}MC_VM_SYSTEM_APERTURE_LOW_ADDR").write(self.mc_base >> 18) + self.adev.reg(f"reg{ip}MC_VM_SYSTEM_APERTURE_HIGH_ADDR").write(self.mc_end >> 18) + self.adev.wreg_pair(f"reg{ip}MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", "_LSB", "_MSB", self.memscratch_pm.paddr >> 12) + self.adev.wreg_pair(f"reg{ip}VM_L2_PROTECTION_FAULT_DEFAULT_ADDR", "_LO32", "_HI32", self.dummy_page_pm.paddr >> 12) + + self.adev.reg(f"reg{ip}VM_L2_PROTECTION_FAULT_CNTL2").update(active_page_migration_pte_read_retry=1) + + # Init TLB and cache + self.adev.reg(f"reg{ip}MC_VM_MX_L1_TLB_CNTL").update(enable_l1_tlb=1, system_access_mode=3, enable_advanced_driver_model=1, + system_aperture_unmapped_access=0, eco_bits=0, mtype=am.MTYPE_UC) + + self.adev.reg(f"reg{ip}VM_L2_CNTL").update(enable_l2_cache=1, enable_l2_fragment_processing=0, enable_default_page_out_to_system_memory=1, + l2_pde0_cache_tag_generation_mode=0, pde_fault_classification=0, context1_identity_access_mode=1, identity_mode_fragment_size=0) + self.adev.reg(f"reg{ip}VM_L2_CNTL2").update(invalidate_all_l1_tlbs=1, invalidate_l2_cache=1) + self.adev.reg(f"reg{ip}VM_L2_CNTL3").write(bank_select=9, l2_cache_bigk_fragment_size=6,l2_cache_4k_associativity=1,l2_cache_bigk_associativity=1) + self.adev.reg(f"reg{ip}VM_L2_CNTL4").write(l2_cache_4k_partition_count=1) + self.adev.reg(f"reg{ip}VM_L2_CNTL5").write(walker_priority_client_id=0x1ff) + + self.enable_vm_addressing(self.adev.mm.root_page_table, ip, vmid=0) + + # Disable identity aperture + self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", "_LO32", "_HI32", 0xfffffffff) + self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", "_LO32", "_HI32", 0x0) + self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", "_LO32", "_HI32", 0x0) + + for eng_i in range(18): self.adev.wreg_pair(f"reg{ip}VM_INVALIDATE_ENG{eng_i}_ADDR_RANGE", "_LO32", "_HI32", 0x1fffffffff) + self.hub_initted[ip] = True + + def on_interrupt(self): + for ip in ["MM", "GC"]: + st, va = self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_STATUS').read(), self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_LO32').read() + va = (va | (self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_HI32').read()) << 32) << 12 + if self.adev.reg(f"reg{ip}VM_L2_PROTECTION_FAULT_STATUS").read(): raise RuntimeError(f"{ip}VM_L2_PROTECTION_FAULT_STATUS: {st:#x} {va:#x}") + +class AM_SMU(AM_IP): + def init(self): + self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_EnableAllSmuFeatures, 0, poll=True) + + for clck in [0x00000C94, 0x000204E1, 0x000105DC, 0x00050B76, 0x00070B76, 0x00040898, 0x00060898, 0x000308FD]: + self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_SetSoftMinByFreq, clck, poll=True) + self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_SetSoftMaxByFreq, clck, poll=True) + + def mode1_reset(self): + self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_Mode1Reset, 0, poll=True) + time.sleep(0.5) + + def _smu_cmn_poll_stat(self): self.adev.wait_reg(self.adev.mmMP1_SMN_C2PMSG_90, mask=0xFFFFFFFF, value=1) + def _smu_cmn_send_msg(self, msg, param=0): + self.adev.mmMP1_SMN_C2PMSG_90.write(0) # resp reg + self.adev.mmMP1_SMN_C2PMSG_82.write(param) + self.adev.mmMP1_SMN_C2PMSG_66.write(msg) + + def _smu_cmn_send_smc_msg_with_param(self, msg, param, poll=True, read_back_arg=False): + if poll: self._smu_cmn_poll_stat() + + self._smu_cmn_send_msg(msg, param) + self._smu_cmn_poll_stat() + return self.adev.rreg(self.adev.mmMP1_SMN_C2PMSG_82) if read_back_arg else None + +class AM_GFX(AM_IP): + def init(self): + self._wait_for_rlc_autoload() + self._config_gfx_rs64() + self.adev.gmc.init_hub("GC") + + # NOTE: Golden reg for gfx11. No values for this reg provided. The kernel just ors 0x20000000 to this reg. + self.adev.regTCP_CNTL.write(self.adev.regTCP_CNTL.read() | 0x20000000) + self.adev.regRLC_SRM_CNTL.update(srm_enable=1, auto_incr_addr=1) + + self.adev.regGRBM_CNTL.update(read_timeout=0xff) + for i in range(0, 16): + self._grbm_select(vmid=i) + self.adev.regSH_MEM_CONFIG.write(address_mode=am.SH_MEM_ADDRESS_MODE_64, alignment_mode=am.SH_MEM_ALIGNMENT_MODE_UNALIGNED, + initial_inst_prefetch=3) + + # Configure apertures: + # LDS: 0x10000000'00000000 - 0x10000001'00000000 (4GB) + # Scratch: 0x20000000'00000000 - 0x20000001'00000000 (4GB) + self.adev.regSH_MEM_BASES.write(shared_base=0x1, private_base=0x2) + self._grbm_select() + + # Configure MEC doorbell range + self.adev.regCP_MEC_DOORBELL_RANGE_LOWER.write(0x0) + self.adev.regCP_MEC_DOORBELL_RANGE_UPPER.write(0x450) + + # Enable MEC + self.adev.regCP_MEC_RS64_CNTL.update(mec_invalidate_icache=0, mec_pipe0_reset=0, mec_pipe1_reset=0, mec_pipe2_reset=0, mec_pipe3_reset=0, + mec_pipe0_active=1, mec_pipe1_active=1, mec_pipe2_active=1, mec_pipe3_active=1, mec_halt=0) + + # NOTE: Wait for MEC to be ready. The kernel does udelay here as well. + time.sleep(0.5) + + def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, eop_addr:int, eop_size:int, doorbell:int, pipe:int, queue:int): + mqd = self.adev.mm.valloc(0x1000, uncached=True, contigous=True) + + mqd_struct = am.struct_v11_compute_mqd(header=0xC0310800, cp_mqd_base_addr_lo=lo32(mqd.va_addr), cp_mqd_base_addr_hi=hi32(mqd.va_addr), + cp_hqd_persistent_state=self.adev.regCP_HQD_PERSISTENT_STATE.build(preload_size=0x55, preload_req=1), + cp_hqd_pipe_priority=0x2, cp_hqd_queue_priority=0xf, cp_hqd_quantum=0x111, + cp_hqd_pq_base_lo=lo32(ring_addr>>8), cp_hqd_pq_base_hi=hi32(ring_addr>>8), + cp_hqd_pq_rptr_report_addr_lo=lo32(rptr_addr), cp_hqd_pq_rptr_report_addr_hi=hi32(rptr_addr), + cp_hqd_pq_wptr_poll_addr_lo=lo32(wptr_addr), cp_hqd_pq_wptr_poll_addr_hi=hi32(wptr_addr), + cp_hqd_pq_doorbell_control=self.adev.regCP_HQD_PQ_DOORBELL_CONTROL.build(doorbell_offset=doorbell*2, doorbell_en=1), + cp_hqd_pq_control=self.adev.regCP_HQD_PQ_CONTROL.build(rptr_block_size=5, unord_dispatch=1, queue_size=(ring_size//4).bit_length()-2), + cp_hqd_ib_control=self.adev.regCP_HQD_IB_CONTROL.build(min_ib_avail_size=0x3), cp_hqd_hq_status0=0x20004000, + cp_mqd_control=self.adev.regCP_MQD_CONTROL.build(priv_state=1), cp_hqd_vmid=0, + cp_hqd_eop_base_addr_lo=lo32(eop_addr>>8), cp_hqd_eop_base_addr_hi=hi32(eop_addr>>8), + cp_hqd_eop_control=self.adev.regCP_HQD_EOP_CONTROL.build(eop_size=(eop_size//4).bit_length()-2)) + + # Copy mqd into memory + ctypes.memmove(mqd.cpu_addr, ctypes.addressof(mqd_struct), ctypes.sizeof(mqd_struct)) + self.adev.gmc.flush_hdp() + + self._grbm_select(me=1, pipe=pipe, queue=queue) + + mqd_st_mv = to_mv(ctypes.addressof(mqd_struct), ctypes.sizeof(mqd_struct)).cast('I') + for i, reg in enumerate(range(self.adev.regCP_MQD_BASE_ADDR.reg_off, self.adev.regCP_HQD_PQ_WPTR_HI.reg_off + 1)): + self.adev.wreg(reg, mqd_st_mv[0x80 + i]) + self.adev.regCP_HQD_ACTIVE.write(0x1) + + self._grbm_select() + + self.adev.reg(f"regCP_ME1_PIPE{pipe}_INT_CNTL").update(time_stamp_int_enable=1, generic0_int_enable=1) + + def set_clockgating_state(self): + self.adev.regRLC_SAFE_MODE.write(message=1, cmd=1) + self.adev.wait_reg(self.adev.regRLC_SAFE_MODE, mask=0x1, value=0x0) + + self.adev.regRLC_CGCG_CGLS_CTRL.update(cgcg_gfx_idle_threshold=0x36, cgcg_en=1, cgls_rep_compansat_delay=0xf, cgls_en=1) + + self.adev.regCP_RB_WPTR_POLL_CNTL.update(poll_frequency=0x100, idle_poll_count=0x90) + self.adev.regCP_INT_CNTL.update(cntx_busy_int_enable=1, cntx_empty_int_enable=1, cmp_busy_int_enable=1, gfx_idle_int_enable=1) + self.adev.regSDMA0_RLC_CGCG_CTRL.update(cgcg_int_enable=1) + + self.adev.regRLC_CGTT_MGCG_OVERRIDE.update(perfmon_clock_state=0, gfxip_fgcg_override=0, gfxip_repeater_fgcg_override=0, + grbm_cgtt_sclk_override=0, rlc_cgtt_sclk_override=0, gfxip_mgcg_override=0, gfxip_cgls_override=0) + + self.adev.regRLC_SAFE_MODE.write(message=0, cmd=1) + + def _grbm_select(self, me=0, pipe=0, queue=0, vmid=0): self.adev.regGRBM_GFX_CNTL.write(meid=me, pipeid=pipe, vmid=vmid, queueid=queue) + + def _wait_for_rlc_autoload(self): + while True: + bootload_ready = (self.adev.regRLC_RLCS_BOOTLOAD_STATUS.read() & gc_11_0_0.RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK) != 0 + if self.adev.regCP_STAT.read() == 0 and bootload_ready: break + + def _config_gfx_rs64(self): + def _config_helper(eng_name, cntl_reg, eng_reg, pipe_cnt, me=0): + for pipe in range(pipe_cnt): + self._grbm_select(me=me, pipe=pipe) + self.adev.wreg_pair(f"regCP_{eng_reg}_PRGRM_CNTR_START", "", "_HI", self.adev.fw.ucode_start[eng_name] >> 2) + self._grbm_select() + self.adev.reg(f"regCP_{cntl_reg}_CNTL").update(**{f"{eng_name.lower()}_pipe{pipe}_reset": 1 for pipe in range(pipe_cnt)}) + self.adev.reg(f"regCP_{cntl_reg}_CNTL").update(**{f"{eng_name.lower()}_pipe{pipe}_reset": 0 for pipe in range(pipe_cnt)}) + + _config_helper(eng_name="PFP", cntl_reg="ME", eng_reg="PFP", pipe_cnt=2) + _config_helper(eng_name="ME", cntl_reg="ME", eng_reg="ME", pipe_cnt=2) + _config_helper(eng_name="MEC", cntl_reg="MEC_RS64", eng_reg="MEC_RS64", pipe_cnt=4, me=1) + +class AM_IH(AM_IP): + def interrupt_handler(self): + ring_vm, rwptr_vm, suf, _ = self.rings[0] + wptr = to_mv(rwptr_vm.cpu_addr, 8).cast('Q')[0] + + if self.adev.reg(f"regIH_RB_WPTR{suf}").read(rb_overflow=1): + self.adev.reg(f"regIH_RB_WPTR{suf}").update(rb_overflow=0) + self.adev.reg(f"regIH_RB_CNTL{suf}").update(wptr_overflow_clear=1) + self.adev.reg(f"regIH_RB_CNTL{suf}").update(wptr_overflow_clear=0) + self.adev.regIH_RB_RPTR.write(wptr % ring_vm.size) + + def init(self): + self.rings = [(self.adev.mm.valloc(1 << 20, uncached=True, contigous=True), self.adev.mm.valloc(0x1000, uncached=True, contigous=True), "", 0), + (self.adev.mm.valloc(1 << 20, uncached=True, contigous=True), self.adev.mm.valloc(0x1000, uncached=True, contigous=True), "_RING1", 1)] + + for ring_vm, rwptr_vm, suf, ring_id in self.rings: + self.adev.wreg_pair("regIH_RB_BASE", suf, f"_HI{suf}", ring_vm.va_addr >> 8) + + self.adev.reg(f"regIH_RB_CNTL{suf}").write(mc_space=4, wptr_overflow_clear=1, rb_size=(ring_vm.size//4).bit_length(), + mc_snoop=1, mc_ro=0, mc_vmid=0, **({'wptr_overflow_enable': 1, 'rptr_rearm': 1} if ring_id == 0 else {'rb_full_drain_enable': 1})) + + if ring_id == 0: self.adev.wreg_pair("regIH_RB_WPTR_ADDR", "_LO", "_HI", rwptr_vm.va_addr) + + self.adev.reg(f"regIH_RB_WPTR{suf}").write(0) + self.adev.reg(f"regIH_RB_RPTR{suf}").write(0) + + self.adev.reg(f"regIH_DOORBELL_RPTR{suf}").write(((am.AMDGPU_NAVI10_DOORBELL_IH + ring_id) * 2), enable=1) + + self.adev.regIH_STORM_CLIENT_LIST_CNTL.update(client18_is_storm_client=1) + self.adev.regIH_INT_FLOOD_CNTL.update(flood_cntl_enable=1) + self.adev.regIH_MSI_STORM_CTRL.update(delay=3) + + libpciaccess.pci_device_cfg_read_u16(self.adev.pcidev, ctypes.byref(val:=ctypes.c_uint16()), libpciaccess.PCI_COMMAND) + libpciaccess.pci_device_cfg_write_u16(self.adev.pcidev, val.value | libpciaccess.PCI_COMMAND_MASTER, libpciaccess.PCI_COMMAND) + + # toggle interrupts + for _, rwptr_vm, suf, ring_id in self.rings: + self.adev.reg(f"regIH_RB_CNTL{suf}").update(rb_enable=1, **({'enable_intr': 1} if ring_id == 0 else {})) + +class AM_SDMA(AM_IP): + def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, doorbell:int, pipe:int, queue:int): + # Stop if something is running... + self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_RB_CNTL").update(rb_enable=0) + while not self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_CONTEXT_STATUS").read(idle=1): pass + + # Setup the ring + self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_RPTR", "", "_HI", 0) + self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_WPTR", "", "_HI", 0) + self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_BASE", "", "_HI", ring_addr >> 8) + self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_RPTR_ADDR", "_LO", "_HI", rptr_addr) + self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_WPTR_POLL_ADDR", "_LO", "_HI", wptr_addr) + self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_DOORBELL_OFFSET").update(offset=doorbell * 2) + self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_DOORBELL").update(enable=1) + self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_RB_CNTL").write(rb_vmid=0, rptr_writeback_enable=1, rptr_writeback_timer=4, + f32_wptr_poll_enable=1, rb_size=(ring_size//4).bit_length()-1, rb_enable=1, rb_priv=1) + self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_IB_CNTL").update(ib_enable=1) + + def init(self): + self.adev.regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL.write(0x0) + self.adev.regSDMA0_WATCHDOG_CNTL.update(queue_hang_count=100) # 10s, 100ms per unit + self.adev.regSDMA0_UTCL1_CNTL.update(resp_mode=3, redo_delay=9) + self.adev.regSDMA0_UTCL1_PAGE.update(rd_l2_policy=0x2, wr_l2_policy=0x3, llc_noalloc=1) # rd=noa, wr=bypass + self.adev.regSDMA0_F32_CNTL.update(halt=0, th1_reset=0) + self.adev.regSDMA0_CNTL.update(ctxempty_int_enable=1, trap_enable=1) + +class AM_PSP(AM_IP): + def __init__(self, adev): + super().__init__(adev) + + self.msg1_pm = self.adev.mm.palloc(am.PSP_1_MEG, align=am.PSP_1_MEG) + self.cmd_pm = self.adev.mm.palloc(am.PSP_CMD_BUFFER_SIZE) + self.fence_pm = self.adev.mm.palloc(am.PSP_FENCE_BUFFER_SIZE) + self.ring_pm = self.adev.mm.palloc(0x10000) + + def is_sos_alive(self): return self.adev.regMP0_SMN_C2PMSG_81.read() != 0x0 + def init(self): + sos_components_load_order = [ + (am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_KEY_DATABASE), (am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_TOS_SPL_TABLE), + (am.PSP_FW_TYPE_PSP_SYS_DRV, am.PSP_BL__LOAD_SYSDRV), (am.PSP_FW_TYPE_PSP_SOC_DRV, am.PSP_BL__LOAD_SOCDRV), + (am.PSP_FW_TYPE_PSP_INTF_DRV, am.PSP_BL__LOAD_INTFDRV), (am.PSP_FW_TYPE_PSP_DBG_DRV, am.PSP_BL__LOAD_DBGDRV), + (am.PSP_FW_TYPE_PSP_RAS_DRV, am.PSP_BL__LOAD_RASDRV), (am.PSP_FW_TYPE_PSP_SOS, am.PSP_BL__LOAD_SOSDRV)] + + for fw, compid in sos_components_load_order: self._bootloader_load_component(fw, compid) + while not self.is_sos_alive(): time.sleep(0.01) + + self._ring_create() + self._tmr_init() + + # SMU fw should be loaded before TMR. + self._load_ip_fw_cmd(self.adev.fw.smu_psp_desc) + self._tmr_load_cmd() + + for psp_desc in self.adev.fw.descs: self._load_ip_fw_cmd(psp_desc) + self._rlc_autoload_cmd() + + def _wait_for_bootloader(self): self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_35, mask=0xFFFFFFFF, value=0x80000000) + + def _prep_msg1(self, data): + ctypes.memset(self.msg1_pm.cpu_addr(), 0, self.msg1_pm.size) + self.msg1_pm.cpu_view()[:len(data)] = data + self.adev.gmc.flush_hdp() + + def _bootloader_load_component(self, fw, compid): + if fw not in self.adev.fw.sos_fw: return 0 + + self._wait_for_bootloader() + + self._prep_msg1(self.adev.fw.sos_fw[fw]) + self.adev.regMP0_SMN_C2PMSG_36.write(self.msg1_pm.mc_addr() >> 20) + self.adev.regMP0_SMN_C2PMSG_35.write(compid) + + return self._wait_for_bootloader() + + def _tmr_init(self): + # Load TOC and calculate TMR size + self._prep_msg1(fwm:=self.adev.fw.sos_fw[am.PSP_FW_TYPE_PSP_TOC]) + resp = self._load_toc_cmd(len(fwm)) + + self.tmr_pm = self.adev.mm.palloc(resp.resp.tmr_size, align=am.PSP_TMR_ALIGNMENT) + + def _ring_create(self): + # Wait until the sOS is ready + self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_64, mask=0x80000000, value=0x80000000) + + self.adev.wreg_pair("regMP0_SMN_C2PMSG", "_69", "_70", self.ring_pm.mc_addr()) + self.adev.regMP0_SMN_C2PMSG_71.write(self.ring_pm.size) + self.adev.regMP0_SMN_C2PMSG_64.write(am.PSP_RING_TYPE__KM << 16) + + # There might be handshake issue with hardware which needs delay + time.sleep(0.1) + + self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_64, mask=0x8000FFFF, value=0x80000000) + + def _ring_submit(self): + prev_wptr = self.adev.regMP0_SMN_C2PMSG_67.read() + ring_entry_addr = self.ring_pm.cpu_addr() + prev_wptr * 4 + + ctypes.memset(ring_entry_addr, 0, ctypes.sizeof(am.struct_psp_gfx_rb_frame)) + write_loc = am.struct_psp_gfx_rb_frame.from_address(ring_entry_addr) + write_loc.cmd_buf_addr_hi, write_loc.cmd_buf_addr_lo = data64(self.cmd_pm.mc_addr()) + write_loc.fence_addr_hi, write_loc.fence_addr_lo = data64(self.fence_pm.mc_addr()) + write_loc.fence_value = prev_wptr + + # Move the wptr + self.adev.regMP0_SMN_C2PMSG_67.write(prev_wptr + ctypes.sizeof(am.struct_psp_gfx_rb_frame) // 4) + + while self.fence_pm.cpu_view().cast('I')[0] != prev_wptr: pass + time.sleep(0.05) + + resp = am.struct_psp_gfx_cmd_resp.from_address(self.cmd_pm.cpu_addr()) + if resp.resp.status != 0: raise RuntimeError(f"PSP command failed {resp.cmd_id} {resp.resp.status}") + + return resp + + def _prep_ring_cmd(self, hdr): + ctypes.memset(self.cmd_pm.cpu_addr(), 0, 0x1000) + cmd = am.struct_psp_gfx_cmd_resp.from_address(self.cmd_pm.cpu_addr()) + cmd.cmd_id = hdr + return cmd + + def _load_ip_fw_cmd(self, psp_desc): + fw_type, fw_bytes = psp_desc + + self._prep_msg1(fw_bytes) + cmd = self._prep_ring_cmd(am.GFX_CMD_ID_LOAD_IP_FW) + cmd.cmd.cmd_load_ip_fw.fw_phy_addr_hi, cmd.cmd.cmd_load_ip_fw.fw_phy_addr_lo = data64(self.msg1_pm.mc_addr()) + cmd.cmd.cmd_load_ip_fw.fw_size = len(fw_bytes) + cmd.cmd.cmd_load_ip_fw.fw_type = fw_type + return self._ring_submit() + + def _tmr_load_cmd(self): + cmd = self._prep_ring_cmd(am.GFX_CMD_ID_SETUP_TMR) + cmd.cmd.cmd_setup_tmr.buf_phy_addr_hi, cmd.cmd.cmd_setup_tmr.buf_phy_addr_lo = data64(self.tmr_pm.mc_addr()) + cmd.cmd.cmd_setup_tmr.system_phy_addr_hi, cmd.cmd.cmd_setup_tmr.system_phy_addr_lo = data64(self.tmr_pm.paddr) + cmd.cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1 + cmd.cmd.cmd_setup_tmr.buf_size = self.tmr_pm.size + return self._ring_submit() + + def _load_toc_cmd(self, toc_size): + cmd = self._prep_ring_cmd(am.GFX_CMD_ID_LOAD_TOC) + cmd.cmd.cmd_load_toc.toc_phy_addr_hi, cmd.cmd.cmd_load_toc.toc_phy_addr_lo = data64(self.msg1_pm.mc_addr()) + cmd.cmd.cmd_load_toc.toc_size = toc_size + return self._ring_submit() + + def _rlc_autoload_cmd(self): + self._prep_ring_cmd(am.GFX_CMD_ID_AUTOLOAD_RLC) + return self._ring_submit()